diff --git a/ChangeLog b/ChangeLog index f68317c1f8d..0faa7426054 100644 --- a/ChangeLog +++ b/ChangeLog @@ -3609,7 +3609,7 @@ NuttX OS test, but configured to build natively on Windows. Its only real purpose is to very the native Windows build logic. * tools/mkdeps.bat and tools/mkdeps.c: mkdeps.bat is a failed attempt - to leverage mkdeps.sh to CMD.exe. It fails because the are certain + to leverage mkdeps.sh to CMD.exe. It fails because there are certain critical CFLAG values that cannot be passed on the CMD.exe command line (like '='). mkdeps.c is a work in progress that will, hopefully, replace both mkdeps.sh and mkdeps.bat. @@ -23764,4 +23764,501 @@ break compilation in certain configurations. From Mateusz Szafoni (2019-03-24). -7.30 2019-xx-xx Gregory Nutt +7.30 2019-05-19 Gregory Nutt + + * arch/ and config/ files: All board interfaces (those starting with + board_) must be defined in board-specific logic. Otherwise, they cannot + be customized for specialized usage by different boards. The + board_reset() interface was defined in architecture-specific logic that + only called up_systemreset(). That is useless! This change removes the + board_reset() implementation from the architecture-specific code and + re-implements it in the src/ directory of each board that has + CONFIG_BOARDCTL_RESET enabled. That is the correct functional + partitioning. From Gregory Nutt (2019-03-25). + * configs/omnibusf4/src/stm32_reset: Add boardctl() reset logic. From + Bill Gatliff (2019-03-25). + * arch/arm/src/stm32f7/stm32_qspi.c: Fix QuadSPI interrupts. This commit + essentially replaces wrongly named configuration variables + STM32F7_QSPI_INTERRUPTS into CONFIG_STM32F7_QSPI_INTERRUPTS. Also fixes + some getreg/putreg where register addresses were used instead of + register offsets From Pierre-Olivier Vauboin (2019-03-25). + * graphics/nxmu, include/nuttx/nx/nxmu.h, libs/libnx: Add new + server->client callback to notify the window client of server events. + Remove the old 'blocked' callback and just make it one case of an 'event' + callback. From Gregory Nutt (2019-03-25). + * graphics/ and libs/libnx: Implement new interfaces nx_synch() and + nxtk_synch(). This are used to synchronize the NX server with the window + client. Currently most of the logic is equivalent to nx_block() and + nxtk_block(), but with slightly different semantics. They are separate + now because they are likely to diverge in the future. From Gregory Nutt + (2019-03-25). + * configs/stm32f103-minimum/src/: USB reset was not working appropriately + since the pin connected to D+ was incorrectly defined and the pullup/down + logic was reversed. From Matias N (2019-03-25). + * configs/omnibusf4: Add board_ioctl() which is needed only if + CONFIG_BOARDCTL_IOCTL=y is selected; Update NSH configuration to enable + board IOCTLs and DFU mode reset. From Bill Gatliff (2019-03-26). + * include/limits.h: Remove the duplicate TMP_MAX definitions. The + standard requires that TMP_MAX defines be in stdio.h. From Xiang Xiao + (2019-03-26). + * include/sys/select.h: Fix compiler error when CONFIG_NSOCKET_DESCRIPTORS + is undefined. From Xiang Xiao (2019-03-26). + * arch/arm/src/armv7-a/Toolchain.defs: Fix 'cc1: warning: switch + -mcpu=cortex-a7 conflicts with -march=armv7-a switch' From Xiang Xiao + (2019-03-26). + * drivers/usbdev/cdcacm.c: This fixes a problem where the host sent a "get + descriptor" message of type "standard" with a recipient of type + "interface". Since the composite driver would only pass messages to the + child interfaces when a message was not "standard", this message was not + handled. I changed the condition so that the composite driver checks not + only if this is a "standard" message but if it is also directed to the + device. Otherwise, the handling is delegated to the children of the + composite device. From Matias N (2019-03-26). + * drivers/video/max7456.c: Adds a read-only (for now) /dev/osd0/CM + interface for obtaining the chip's onboard NVM character map data. Use + seek() to position the cursor over a desired subset of bytes, or request + a large read to obtain the entire EEPROM memory contents. Values are + returned in binary form. Use hexdump, etc. to format them for viewing. + From Bill Gatliff (2019-03-26). + * configs/nucleo-l476rg/src/stm32_gpio.c, + configs/stm32f103-minimum/src/stm32_gpio.c, and + drivers/sensors/zerocross.c: Fix some errors when debug assertions are + enabled. From Matous Pokorny (2019-03-29). + * configs/boardctl.c, include/sys/boardctl.h: Add a command to start the + VNC server. From Gregory Nutt (2019-04-02). + * drivers/syslog/syslog_stream.c: In syslog buffered mode, avoid IOB alloc + lock-up with heavy network activity. This change alters the buffered + syslog logic to use 'iob_tryalloc' instead of blocking 'iob_alloc' to + avoid syslog printing from getting stuck when all IOBs are depleted by + network activity. An issue was seen when large incoming TCP transfer + uses free IOB buffers and processing threads try to use syslog which then + block at iob_alloc. From Jussi Kivilinna (2019-04-03). + * arch/stm32f7: Support bypassing the input clock divider on the SDMMC + interface. This enables using the full clock speed provided to the SDMMC + interface with no dividing. From Anthony Merlino (2019-04-03). + * arch/arc/stm32f7: Add support for using the HSE in bypass mode, + configured by board.h From Anthony Merlino (2019-04-03). + * arch/arm/stm32f7: Fixes some macros related to OTGFS/OTGHS preventing + OTGHS from working. From Anthony Merlino (2019-04-03). + * arch/arm/src/nrf52/nrf52832_errdata.c: Fix compiler error when following + C89. From Erik Englund (2019-04-03). + * PIC32MZ: The commit corrects the gpioirq when mismatch mode is selected + and add support for edge detect mode. Slew Rate was also added for + completeness. From Abdelatif Guettouche (2019-04-03). + * libs/libc/stdio/lib_libvsprintf.c: Restore support for printing NULL + string as "(null)". Legacy printf supported printing "(null)" in place + for NULL string: printf("null: %s\n", NULL); => null: (null). This + commit restores this functionality for new printf library. From Jussi + Kivilinna (2019-04-04). + * fs/littlefs/lfs.c: Fix lfs_format bug. In superblock disk root-block + assignment, the second must be root[1]. From YanLin Zhu (2019-04-04). + * sched/pthread: Added non-standard pthread_get_stackaddr_np() and + pthread_get_stacksize_np(). From Joao Matos (2019-04-04). + * include/pthread.h and libs/libcpthread: Fixed + pthread_attr_get/setstacksize param type to size_t. From Joao Matos + (2019-04-04). + * Fixed R_OK/X_OK definitions to match POSIX. From Joao Matos (2019-04-04). + * libs/libc/locale/lib_setlocale.c: Improved error handling in + setlocale(). From Joao Matos (2019-04-04). + * libs/libc/misc/lib_utsname.c: Fixed return code in uname(). From Joao + Matos (2019-04-04). + * include/sys/syscall.h and syscall/: Added support for munmap() syscall. + From Joao Matos (2019-04-04). + * include/alloca.h: Add alloca.h. Included limited implementation of + alloc() that is only available for GCC versions 3 and above. From Joao + Matos (2019-04-04). + * configs/nucleo-144/include/board.h: Added STM32_RCC_DCKCFGR2_DSISRC + definition. From Joao Matos (2019-04-04). + * include/signal.h: Add commented out definition of the si_addr field. + From oao Matos (2019-04-04). + * arch/arm/src/stm32f7/stm32_fmc.h: Updated stm32_fmc.h with more FMC + definitions. From oao Matos (2019-04-04). + * Added support for KSZ8081RNA PHY to LPC17xx Ethernet driver. From + jjlange (2019-04-04). + * Refresh configurations. Remove CONFIG_NXWM_UNITTEST=y, not longer in + Kconfigs. From Gregory Nutt (2019-04-04). + * syscall/syscall.csv: Fix a warning due to inconsistencies in return + type. From Gregory Nutt (2019-04-04). + * syscall/syscall.csv: Correct an error in creating the munmap() proxy if + CONFIG_FS_RAMMAP is not defined. From Gregory Nutt (2019-04-04). + * graphics/, lib/libnx, include/nutt/nx: Add support for modal windows. + From Gregory Nutt (2019-04-05). + * drivers/contactless/mfrc522.c: Fixes for MFRC522. In mfrc522_read + uid.sak must be different from 0x04 not as before from 0x00. SAK == 0x00 + is a valid PICC type. Add interface to read MIFARE Ultralight data From + Mateusz Szafoni (2019-04-05). + * configs/nucleo-l073rz: add mfrc522 support From Mateusz Szafoni + (2019-04-05). + * graphics/nxbe: Implement hooks that will eventually support software + 'sprites', i.e., things like OSD functionality, a software cursor, + selection rectangles, window resize preview, etc. From Gregory Nutt + (2019-04-05). + * Added support for Ethernet PHY ioctl() on LPC17xx. From jjlange + (2019-04-05). + * include/nuttx/nx/nxcursor.h: Add a header file describing the + implementation of an NX cursor interface. From Gregory Nutt (2019-04-06). + * libs/libnx/nxmu: Add front-end, client, message handling needed for + cursor support. Still actual cursor logic yet, just message handling. + graphics/nxmu and graphics/nxbe: Add back-end message handling needed + for cursor support. No actual cursor logic yet, just message handling. + From Gregory Nutt (2019-04-06). + * graphics: Extend the definition of the cursor image structure. From + Gregory Nutt (2019-04-07). + * arch/arm/src/stm32f7: USB High speed for STM32F7 series From Ramtin + Amin (2019-04-07). + * I2C1 config on stm32f746g-disco. Typo in stm32f7/stm32_i2c.c From + Matthew Koch (2019-04-08). + * Kconfig warnings: defaults for choice values not supported From Matthew + Koch (2019-04-08). + * arch/arm/src/stm32f7: Ported the PWM from F4 to F7. From Eduard Niesner + (2019-04-08). + * graphics/nxbe: Correct some experimental cursor drawing algorithms. + From Gregory Nutt (2019-04-08). + * grahics/nxglib/nxglib.h: Move internal function prototypes from + include/nuttx/nx/nxglib.h to graphics/nxglib/nxglib.h. From Gregory Nutt + (2019-04-08). + * Support for STM32L071X and a few improvements for STM32F0L0: + arch/arm/src/stm32f0l0: add peripherals configuration for STM32L0 + arch/arm/src/stm32f0l0: a few fixes for USART + arch/arm/include/stm32f0l0/stm32f0_irq.h: use names as in other STM32 + arch/arm/include/stm32f0l0/chip.h: use names as in other STM32 + From Mateusz Szafoni (2019-04-09). + * Adds support for software cursors with differing pixel depths on multiple + displays. This bring the software cursor to code complete. Still + untested. From Gregory Nutt (2019-04-09). + * graphics/nxbe: Add some missing checks: Don't permit the software + cursor to be enabled until it has been assigned an image; don't perform + any cursor operations while the cursor is disabled. From Gregory Nutt + (2019-04-10). + * include/nuttx/usb/hid.h: The usbhid_descriptor_s struct defined in hid.h + included some optional fields that should not be hard-defined as part of + that structure. An arbitrary number of optional entries could be + included in the descriptor, but that is not properly represented. No + code on NuttX currently depends on the structure definition with an + optional descriptor so it is safe to remove. From Matias N (2019-03-30). + * arch/arm/src/stm32f7/stm32_otgdev.c: Correct hard-coded FIFO size that is + wrong for OTG FS. From Ramtin Amin (2019-04-11). + * /graphics/nxglib/cursor: Correct two locations where y was used but + where x was intended. From Gregory Nutt (2019-04-11). + * Documentation/NXGraphicsSubsystem.html: Update documentation to describe + blocking, synchronization, and cursor interfaces. From Gregory Nutt + (2019-04-11). + * arch/arm/src/stm32f: Added support for TICKLESS mode. From Valmantas + Paliksa (2019-04-12). + * arch/arm/src/stm32f7/stm32_spi.c: Add SPI DMA threshold configuration. + From Valmantas Paliksa (2019-04-12). + * arch/arm/src/stm32f7/stm32_ethernet.c: Auto-generate Ethernet MAC + address from device unique ID. From Valmantas Paliksa (2019-04-12). + * arch/arm/src/stm32f7/stm32_flash.c: Add flash block mapping support for + progmem. From Valmantas Paliksa (2019-04-12). + * arch/arm/src/stm32f7/stm32_uid.c: Add UID access. From Valmantas + Paliksa (2019-04-12). + * drivers/can/can.c: Support multiple readers of the same port From + Valmantas Paliksa (2019-04-12). + * drivers/can/mcp2515.c: mcp2515 driver optimizations. From Valmantas + Paliksa (2019-04-12). + * arch/arm/src/stm32f7/stm32_can.c: CAN fixes. From Valmantas Paliksa + (2019-04-12). + * graphics/nxbe: More work cursor coordinates. Still at least one big bug + in the logic. From Gregory Nutt (2019-04-13). + * arch/arm/src/stm32: As noted by Matias N, the FLASH base address used + was incorrect. It was using the address of the FLASH data, not the + address of the FLASH registers. From Gregory Nutt (2019-04-13). + * arch/arm/src/stm32/stm32f10xxf30xx_flash.c: RCC register access should + not be offset by FLASH register base. From Matias N (2019-04-13). + * graphics/nxbe: This seems to fix the last of software cursor bugs. On + the LPC54, it looks pretty clean. Not flickery as I feared. Probably + not so good on low end displays. Possible transient artifacts? Not + sure, maybe. Or maybe my eyes are playing tricks from staring at this + too long. From Gregory Nutt (2019-04-13). + * configs/stm32f103-minimum/src: Add PROCFS automount support From Alan + Carvalho de Assis (2019-04-14). + * net/utils: net_lock() and net_restorelock() now return a value. That + values is the standard zero on success; negated errno value on failure. + This return value is only needed for -ECANCELED. That cancellation + indication needs to ripple all the way back to the highest levels where + the cancellation can be acted on. This commit only adds the return + value; it does not add checking for the return values of net_lock() and + net_restorelock() at higher levels. That is required too. From Gregory + Nutt (2019-04-14). + * configs/stm32ldiscovery/src: Add support for board_late_initialize(), + Move common initialization logic out of board_app_initialize() into new + file stm32_bringup.c From Gregory Nutt (2019-04-15). + * drivers/leds/userled: Fix ledset validity check in ULEDIOC_SETALL + ioctl. From Jussi Kivilinna (2019-04-15). + * arch/arm/src/stm32/Kconfig: It seems one option in the timer + configuration was lost at some point. From Matias N (2019-04-15). + * stm32f7: I2C Interrupt storm fix From David Sidrane (2019-04-16). + * arch/arm/src/stm32l4/stm32l4_pwm.c Fix register addr, en_bit and resetbit + for pwm timers From Fabian Justi (2019-04-17). + * configs/nucleo-l476rg/src/nucleo-l476rg.h Fixed naming stm32l4_pwm_setup + configs/nucleo-l476rg/src/stm32_appinit.c Fixed naming stm32l4_pwm_setup + From Fabian Justi (2019-04-17). + * stm32f7: I2C track bad state. The previous commit was true draconian. + Now we track bad state and so the SW reset only when it occurs. From + David Sidrane (2019-04-17). + * arch/arm/src/stm32f7: stm32f76xx77xx_pinmap.h: Adds additional pin + alternate function for SPI2 From Anthony Merlino (2019-04-17). + * include/cxx/cstdlib: Add std::random() From Gregory Nutt (2019-04-21). + * arch/arm/src/cxd56xx and arch/arm/include/cxd56xx: Add initial CXD56xx + chip sources. From Nobuto Kobayashi (2019-04-22). + * configs/spresense: Add Spresense board support. From Nobuto Kobayashi + (2019-04-22). + * drivers/usbhost/usbhost_storage.c: Correct typo "const const" to "const". + arch/arm/src/stm32/stm32_i2s.c: In debug assertions, it on a sample rate + of 0, but based on other code comments this value implies disabling the + i2s master clock. + arch/arm/src/stm32/stm32_usbhost.h and arch/arm/src/stm32/Kconfig: Allow + vbus monitoring for the OTG_HS host driver. + From Jason Harris (2019-04-23). + * drivers/serial: The upper half serial driver configuration + CONFIG_SERIAL_DMA used to enable DMA on both RX and TX streams. This was + replaced with CONFIG_SERIAL_RXDMA and CONFIG_SERIAKL_TXDMA which will + permit supporting DMA on only one or both streams. From Gregory Nutt + (2019-04-24). + * configs/stm32f103-minimum/src/stm32_mcp2515.c: Patch up more breakage + found in build testing. Looks like fields were added and removed by + commit eb7373cedfa, but the implementation that uses the structure were + not updated. From Gregory Nutt (2019-04-24). + * arch/arm/src/stm32h7/stm32_start.c: Inclusion of nvic.h should not be + conditioned on CONFIG_ARCH_FPU. From Mateusz Szafoni (2019-04-25). + * arch/arm/src: Remove dependency on CONFIG_ARCH_FPU for inclusion of + nvic.h in all other *_start.c files. From Gregory Nutt (2019-04-25). + * nucleo-144: Regenerate f767-netnsh/defconfig. It appear that + CONFIG_NET_SOCKOPTS, is no more explicitly needed. From Phil Coval + (2019-04-25). + * configs/nucleo-h743zi/nsh/defconfig: Enable the FPU. From Jason Harris + (2019-04-25). + * Revert "sched/clock/clock_initialize.c: clock_inittime() needs to be + done with CONFIG_SCHED_TICKLESS and clock_initialize should skip + clock_inittime() for external RTC case since the RTC isn't ready yet." + This reverts commit 2bc709d4b99447f8decdc7580fdabab6dd8939b1. Commit + 2bc709d4b99447f8decdc7580fdabab6dd8939b1 was intended to handle the case + where up_timer_gettime may not start from zero case. However, this + change has the side-effect of breaking every implementation of tickless + mode: After this change the tickless timer structures are used before + they are initialized in clock_inittime(). Initialization happens later + when up_initialize is called() when arm_timer_initialize(). + + Since the tickless mode timer is very special, one solution might be to: + (1) Rename xxx_timer_initialize to up_timer_initialize, (2) Move + up_timer_initialize to include/nuttx/arch.h, and (3) Call it from clock + subsystem instead up_initialize. Basically, this change make timer + initialization almost same as rtc initialization(up_rtc_initialize). For + now, however, we just need to revert the change. From Gregory Nutt + (2019-04-26). + * nucleo-144: Mount sysfs for ifconfig for f767-netnsh/defconfig. Even if + ifconfig is working to set IP, it will not work to display NICs (without + args) From Phil Coval (2019-04-26). + * nucleo-144: Update mbed URL and fix mistakes From Phil Coval (2019-04-26). + * stm32f7: Add basic PWM support to nucleo-144 board. More PWMs and multi + channels support may be investigated and added later. Tested on + nucleo-f767zi. From Phil Coval (2019-04-27). + * configs/nucleo-h743zi: Add support for I2C devices: ssd1306, pca9635, + i2ctools From Mateusz Szafoni (2019-04-28). + * Documentation/NuttxPortingGuide.html & drivers/syslog/README.txt: vsyslog + returns nothing. From Mateusz Szafoni (2019-04-28). + * configs/same70-xplained/twm4nx: Add a configuration for test Twm4Nx + using VNC. From Gregory Nutt (2019-04-28). + * configs/nucleo-l476rg/src: Make naming of functions consistent: + stm32l4_ no stm32_. Inconsistency noted by Phil Coval in Bitbucket PR + 864. This commit takes a different approach to resolving the naming + inconsistency, however. From Gregory Nutt (2019-04-29). + * arch/arm/src/stm32l4: Add USB FS device support. From Juha Niskanen + (2019-04-29). + * configs: Update all configurations to account for the configuration + changes resulting from the separation of network initialization logic + from NSH. From Gregory Nutt (2019-04-29). + * configs/same70-xplained/twm4nx/defconfig: Updated to correctly + initialize network. I am getting a VNC display. It is incomplete and + crashes thereafter. But that is a start. From Gregory Nutt (2019-04-29). + * In many files: Remove references to CONFIG_DISABLE_SIGNALS. Signals can + no longer be disabled. From Gregory Nutt (2019-04-29). + * net/socket/getsockname.c: Fix addrlen check in socket debug features. + Getsockname checked erroneously a pointer agains 0, where the intention + was to dereference the pointer and to check the length. This causes also + a compilation failure if the code is compiled with CONFIG_DEBUG_FEATURES + and with -Werror flag set. From Jukka Laitinen (2019-04-30). + * drivers/net/phy_notify.c: Change sprintf to strncpy in phy_notify. On + some platforms, the sprintf doesn't accept a const char* as a format + argument. From Jukka Laitinen (2019-04-30). + * arch/arm/src/stm32h7: Add STM32H7 SDMMC driver. This is the initial + SDMMC driver for STM32H7. It is mostly copied from STM32F7, with + modified register addresses and bits, and IDMA added. This is still WIP; + it only works with IDMA. From Jukka Laitinen (2019-04-30). + * configs/nucleo-h743zi/include/board.h: Add default clock configuration + for SDMMC for nucleo-h743zi. From Jukka Laitinen (2019-04-30). + * arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h: Fixes for STM32H7 RCC + definitions: (1) Fix compilation for UART7, UART8 and I2C4, (2) Add + backup domain control registers. From Jukka Laitinen (2019-04-30). + * arch/arm/src/stm32h7/stm32h7x3xx_rcc.c: Set the STM32H7 default HSI + pre-divider to 4. The I2C driver currently assumes HSI clock to be + 16MHz. From Jukka Laitinen (2019-04-30). + * arch/arm/src/stm32h7/chip/stm32h7x3xx_memorymap.h: Add the STM32H7 + SYSTEM_UID and DEBUGMCU_BASE register definitions. From Jukka Laitinen + (2019-04-30). + * arch/arm/src/stm32h7/chip/stm32h7x3xx_pinmap.h: Add the + GPIO_ETH_RMII_RXD1 pinmap definition for STM32H7. From Jukka Laitinen + (2019-04-30). + * arch/arm/src/stm32h7/stm32_i2c.c: Fix I2C4 compilation for STM32H7. From + Jukka Laitinen (2019-04-30). + * arch/arm/src/stm32h7/: Add stm32h7 Ethernet driver. This is the initial + push for the Ethernet driver. The driver has been tested to be working + on a nucleo board. This is still WIP, it doesn't for example do MAC + filtering on HW level, but just receives all ethernet packets. From + Jukka Laitinen (2019-04-30). + * arch/arm/src/stm32h7/: Add timer devices driver for STM32H7. This is + mostly a forklift from stm32f7 with some h7 specific modifications. From + Jukka Laitinen (2019-04-30). + * - Mostly arch/arm/src/imxrt and include/imxrt: This commit gets imx1020 + family support started. It is pretty similar, but subtly different, to + 1050/60 (less PLLs, less GPIO banks, differently numbered ports etc. + etc.). I think it's time to at least look at what needs to be done + before we can get these into the mainline kernel even though they're not + properly mature yet. Core memory functions, PLLs, serial and networking + are all working, but there's no stress-testing or similar been done...I'm + not aware of anything broken, but there again I haven't looked too hard. + + I want to go through and start moving each of the imxrt family-specific + files into its own subdirectory to tidy things up a bit, and remove the + vast majority of ifdefs from the mainline code...but I think it's + appropriate to separate the cleanup steps from the new-chip-support + steps to keep things a bit more compartmentalized. Next week is a travel + week so it's possible I'll get time on the cleanup side of the house. + + I can't be 100% certain I didn't inflict casualties on the imxrt1050/60 + code in the process of doing this, but nsh for 1050 and netnsh and nsh + for the 1060 both compile correctly, so if I did break anything it's + going to be properly evil and difficult to find. + + - Directory re-arrangement and splitting of each imxrt family variant + - Prevent intermittent SDCard timeouts by increasing timer in line with + spec. + - Support data dump on Hardfault + - Fix missing ccm definitions and wrong iomux offset + - Prevent hardfault when can't read from ENET PHY + - More consistent Ethernet pinmux. + From Dave Marples (2019-04-30). + * include/nuttx/usb/hid.h: The usbhid_descriptor_s struct defined in + hid.h included some optional fields that should not be hard-defined as + part of that structure. An arbitrary number of optional entries could be + included in the descriptor, but that is not properly represented. No + code on NuttX currently depends on the structure definition with an + optional descriptor so it is safe to remove. + * Documentation/NuttShell.html: Command date is misspelled as data in + chapter 2.12 Show or set the date and time (date). From Michał Łyszczek + (2019-05-01). + * configs/same70-xplained/twm4nx/defconfig: Increase packet MTU to 1500. + From Gregory Nutt (2019-05-03). + * Fix build for battery gauge From Tom Kopriva (2019-05-03). + * configs/same70-xplained/twm4nx/defconfig: Switch to 8BPP. That is the + negotiated size requested by the VNC client anyway. From Gregory Nutt + (2019-05-03). + * graphics/vnc/server/vnc_color.c: Fix an error in color conversion. From + Gregory Nutt (2019-05-03). + * configs/lpcxpresso-lpc54628: Add a Twm4Nx configuration. From Gregory + Nutt (2019-05-04). + * arch/arm/src/common/up_initialize.c: up_initialize.c needs to know about + ramlog_consoleinit() From Jason Harris (2019-05-04). + * NX graphics: This commit adds support for hiding windows. This features + is needed by Twm4Nx: When a window is iconified, the icon should appear + on the background and the window should disappear (i.e., be hidden). The + windows needs to remain healthy and to be updated in all ways, but it + cannot affect the display content. + + Conversely, when the icon is clicked, the icon needs to be hidden on + the background and the window needs to be restored in its current state + (which may be different than the state of the window at the time it + was iconified. + From Gregory Nutt (2019-05-05). + * arch/arm/src/stm32h7: Add missing parts for timer driver: Add the + missing header files, add the driver Kconfig, and add it to make + system. From Jukka Laitinen (2019-05-05). + * configs/nucleo-h743zi/include/board.h: Add the input clock frequency + definitions for all the drivers. Assumes internal clock source for all + the timers. From Jukka Laitinen (2019-05-05). + * arch/arm/src/stm32h7/stm32_tim.c: don't use hardcoded UIF interrupt + From Mateusz Szafoni (2019-05-06). + * Add missing files of BMP180 example for nucleo-l476rg From Fabian Justi + (2019-05-06). + * drivers/sensors/apds9960.c: Initial state of allocated structure was not + being set. Noted by Leif Jacob. From Gregory Nutt (2019-05-06). + * graphics/nxbe/nxbe_setvisibility.c: Fix a missed redraw command in last + NX visibility changes. From Gregory Nutt (2019-05-06). + * graphics/: Windows can now be created in the hidden state. This can be + used to clean up initial window presentation which may involve several + steps. This makes those steps all invisible until nx[tk]_setvisibility() + is called to make the windows visible. From Gregory Nutt (2019-05-07). + * libs/libnx/nxtk/nxtk_events: Fix an error in handling mouse events for + framed windows. When drawing, NX may report mouse positions outside of + the Window. The is only for NX windows, but the outside-the-side + positions were being discarded by nxtk_events(). From Gregory Nutt + (2019-05-07). + * net/sixlowpan/sixlowpan_hc06.c: Correct an endian-ness problem in HC06 + decompression. From Ivan Ucherdzhiev (2019-05-08). + * arm/src/lpc54xx/: Bring in the USB FS OHCI driver from LPC17. This is a + quick'n'dirty port that I will finish sometime later (I hope). + Currently, it is missing hardware clocking setup and is not even hooked + into the build system yet. Needless to say it does not yet even + compile. From Gregory Nutt (2019-05-08). + * Documentation/NXGraphicsSubsystem.html: Add documentation for new + nx[tk]_modal() and nx[tk]_setvisibility() interfaces. From Gregory Nutt + (2019-05-08). + * arch/arm/src/stm32f0l0: Initial ADC support and some improvements for + the STM32 M0 From Mateusz Szafoni (2019-05-09). + * configs/b-l072z-lrwan1: add ADC example From Mateusz Szafoni (2019-05-09). + * graphics/: Add new NX interfaces to query if a window is hidden or not. + From Gregory Nutt (2019-05-09). + * libs/libnx/nxtk/nxtk_opentoolbar.c: Refuse to open a toolbar of height + zero or less. From Gregory Nutt (2019-05-10). + * graphics/nxbe/nxbe_getrectangle.c: Fix an error in coordinate system + usage. Expected rectangle in device coordinate frame, but was passing + the rectangle in window-relative coordinate frame. From Gregory Nutt + (2019-05-10). + * nrf24l01: don't block in read if file descriptor is O_NONBLOCK. Add + support for "multicast" TX mode - no waiting for ACK (needs to be enabled + with fcntl SETTXPAYLOADNOACK) From Leif Jakob (2019-05-11). + * libs/libnx/nxmu/: Add a few bad input parameter checks. + configs/lpcxpresso-lpc54628/twm4nx/defconfig: Need to enable the NX + library. From Gregory Nutt (2019-05-12). + * libs/libnx/nxglib/nxglib_intersecting.c: Correct bogus logic in + nxgl_interesting. Good to know I was stupid then too and that is it not + just a recent thing. From Gregory Nutt (2019-05-13). + * arch/arm/src/stm32l4/stm32l4_usbdev.c: Add missing PWR USBV enable, + correct two USB register bits From Juha Niskanen (2019-05-14). + * arch/arm/src/stm32l4: Port HSI48 and CRS from STM32F0L0 From Juha + Niskanen (2019-05-14). + * arch/arm/src/stm32 and arch/arm/src/stm32f0l0: Port STM32F7 I2C to + STM32F3 and STM32F0L0 From Mateusz Szafoni (2019-05-15). + * configs/b-l072z-lrwan1: Add nxlines_oled example (ssd1306). Add support + for the I2C tool From Mateusz Szafoni (2019-05-15). + * configs/nucleo-f303ze: nxlines_oled example (ssd1306) From Mateusz + Szafoni (2019-05-15). + * graphics/: Fix an oversight in the implementation of per-window + framebuffers. It is true that redraw callbacks can be suppressed for all + cases ... EXCEPT ONE: When the window is resized to a larger size, then + the newly exposed territory must be drawn for the first time. From + Gregory Nutt (2019-05-16). + * graphics/nxterm and configs/boardctl.c: Replace specific interfaces + between boardctl and nxterm with a generalized IOCTL interface. From + Gregory Nutt (2019-05-16). + * graphics/nxterm: Add a new IOCTL that can be used to inform NxTerm that + the size of a window has changed. From Gregory Nutt (2019-05-16). + * configs/stm32f4discovery: Keep c++ global constructor symbols From + Masayuki Ishikawa (2019-05-17). + * arch/arm/src/stm32/Kconfig: simplify ARCH_HAVE_FPU selection and remove + redundant options for F207 From Mateusz Szafoni (2019-05-17). + * drivers/usbmisc: Add FUSB303 driver From Juha Niskanen (2019-05-17). + * sched/signal/sig_default.c: The abnormal termination handler was just + calling exit() conditionally when, for example, Ctrl-C is sent to a + task. The abnormal termination handler must obey the rules of + cancellation points: If cancelation is disabled, then the abnormal + termination logic must wait for cancelation to be re-enabled; If + cancellation is deffered then the abnormal termination logic may have to + wait for the victim task to enter or exit a cancellation point. From + Gregory Nutt (2019-05-17). + * arch/arm/src/stm32f0l0: Add support for AES, RND, and HS148 for L0. + Move HSI48 enable from stm32_usbdev.c to stm32xx_rcc.c From Mateusz + Szafoni (2019-05-17). + +8.1 2019-xx-xx Gregory Nutt diff --git a/Documentation/NXGraphicsSubsystem.html b/Documentation/NXGraphicsSubsystem.html index 1cfa3a63c94..ed89ef9cc49 100644 --- a/Documentation/NXGraphicsSubsystem.html +++ b/Documentation/NXGraphicsSubsystem.html @@ -2,6 +2,7 @@ NX Graphics Subsystem + @@ -12,7 +13,7 @@

NX Graphics Subsystem

-

Last Updated: March 13, 2019

+

Last Updated: May 16, 2019

@@ -103,7 +104,8 @@ 2.3.4.1 redraw()
2.3.4.2 position()
2.3.4.3 mousein()
- 2.3.4.4 kbdin() + 2.3.4.4 kbdin()
+ 2.3.4.5 event()

2.3.5 nx_runinstance() (and nx_run() macro)
@@ -111,26 +113,31 @@ 2.3.7 nx_disconnect()
2.3.8 nx_eventhandler()
2.3.9 nx_eventnotify()
- 2.3.10 nx_openwindow()
- 2.3.11 nx_closewindow()
- 2.3.12 nx_requestbkgd()
- 2.3.13 nx_releasebkgd()
- 2.3.14 nx_getposition()
- 2.3.15 nx_setposition()
- 2.3.16 nx_setsize()
- 2.3.17 nx_raise()
- 2.3.18 nx_lower()
- 2.3.19 nx_fill()
- 2.3.20 nx_getrectangle()
- 2.3.21 nx_filltrapezoid()
- 2.3.22 nx_drawline()
- 2.3.23 nx_drawcircle()
- 2.3.24 nx_fillcircle()
- 2.3.25 nx_setbgcolor()
- 2.3.26 nx_move()
- 2.3.27 nx_bitmap()
- 2.3.28 nx_kbdin()
- 2.3.29 nx_mousein()
+ 2.3.10 nx_block()
+ 2.3.11 nx_synch()
+ 2.3.12 nx_openwindow()
+ 2.3.13 nx_closewindow()
+ 2.3.14 nx_requestbkgd()
+ 2.3.15 nx_releasebkgd()
+ 2.3.16 nx_getposition()
+ 2.3.17 nx_setposition()
+ 2.3.18 nx_setsize()
+ 2.3.19 nx_raise()
+ 2.3.20 nx_lower()
+ 2.3.21 nx_modal()
+ 2.3.22 nx_setvisibility()
+ 2.3.23 nx_ishidden()
+ 2.3.24 nx_fill()
+ 2.3.25 nx_getrectangle()
+ 2.3.26 nx_filltrapezoid()
+ 2.3.27 nx_drawline()
+ 2.3.28 nx_drawcircle()
+ 2.3.29 nx_fillcircle()
+ 2.3.30 nx_setbgcolor()
+ 2.3.31 nx_move()
+ 2.3.32 nx_bitmap()
+ 2.3.33 nx_kbdin()
+ 2.3.34 nx_mousein()

@@ -141,31 +148,36 @@

@@ -181,7 +193,17 @@

- 2.6 Sample Code + 2.6 NX Cursor Support (NXCURSOR) +

+

+

+

+

+ 2.7 Sample Code

@@ -1142,6 +1164,44 @@ void (*kbdin)(NXWINDOW hwnd, uint8_t nch, FAR const uint8_t *ch, FAR void *arg); Returned Value: None

+ 2.3.4.5 event() +

2.3.4.5 event()

+

Callback Function Prototype:

+
    +void (*event)(NXWINDOW hwnd, enum nx_event_e event, FAR void *arg1, FAR void *arg2);
+
+

+ Description: + This callback is used to communicate server events to the window listener. +

+
+
NXEVENT_BLOCKED - Window messages are blocked. +
This callback is the response from nx_block(), nxtk_block(). Those blocking interfaces are used to assure that no further messages are directed to the window. Receipt of the blocked callback signifies that (1) there are no further pending callbacks and (2) that the window is now defunct and will receive no further callbacks. + + This callback supports coordinated destruction of a window. In the multi-user mode, the client window logic must stay intact until all of the queued callbacks are processed. Then the window may be safely closed. Closing the window prior with pending callbacks can lead to bad behavior when the callback is executed. +
NXEVENT_SYNCHED - Synchronization handshake +
This completes the handshake started by nx_synch(), or nxtk_synch(). Those interfaces send a synchronization messages to the NX server which responds with this event. The sleeping client is awakened and continues graphics processing, completing the handshake. + + Due to the highly asynchronous nature of client-server communications, synchronization is sometimes necessary to assure that the client and server are working together properly. +
+

+ Input Parameters: +

+

+

+ Returned Value: None +

+ +

2.3.5 nx_runinstance() (and nx_run() macro)

Function Prototype:

    @@ -1302,11 +1362,7 @@ int nx_eventhandler(NXHANDLE handle);
 #include <nuttx/nx/nxglib.h>
 #include <nuttx/nx/nx.h>
 
-#ifndef CONFIG_DISABLE_SIGNALS
 int nx_eventnotify(NXHANDLE handle, int signo);
-#else
-#  define nx_eventnotify(handle, signo) (OK)
-#endif

Description: @@ -1342,7 +1398,93 @@ int nx_eventnotify(NXHANDLE handle, int signo); ERROR on failure with errno set appropriately

-

2.3.10 nx_openwindow()

+

2.3.10 nx_block()

+

Function Prototype:

+
    +#include <nuttx/nx/nx.h>
+
+int nx_block(NXWINDOW hwnd, FAR void *arg);
+
+

+ Description: + The response to this function call is two things: (1) any queued callback messages to the window are 'blocked' and then (2) also subsequent window messaging is blocked. +

+

+ The event callback with the NXEVENT_BLOCKED event is the response from nx_block(). This blocking interface is used to assure that no further messages are are directed to the window. Receipt of the NXEVENT_BLOCKED event signifies that (1) there are no further pending callbacks and (2) that the window is now defunct and will receive no further callbacks. +

+

+ This callback supports coordinated destruction of a window. The client window logic must stay intact until all of the queued callbacks are processed. Then the window may be safely closed. Closing the window prior with pending callbacks can lead to bad behavior when the callback is executed. +

+

+ Input Parameters: +

    +
    +
    wnd +
    The window to be blocked +
    arg +
    An argument that will accompany the block messages (This is arg2 in the event callback). +
+

+

+ Returned Value: + OK on success; ERROR on failure with errno set appropriately. +

+ +

2.3.11 nx_synch()

+

Function Prototype:

+
    +#include <nuttx/nx/nx.h>
+
+int nx_synch(NXWINDOW hwnd, FAR void *arg);
+
+

+ Description: + This interface can be used to synchronize the window client with the NX server. It really just implements an echo: A synch message is sent from the window client to the server which then responds immediately by sending the NXEVENT_SYNCHED back to the windows client. +

+

+ Due to the highly asynchronous nature of client-server communications, nx_synch() is sometimes necessary to assure that the client and server are fully synchronized in time. +

+

+ Usage by the window client might be something like this: +

+
    +  extern bool g_synched;
+  extern sem_t g_synch_sem;
+
+  g_synched = false;
+  ret = nx_synch(hwnd, handle);
+  if (ret < 0)
+    {
+       -- Handle the error --
+    }
+
+  while (!g_synched)
+    {
+      ret = sem_wait(&g_sync_sem);
+      if (ret < 0)
+        {
+           -- Handle the error --
+        }
+    }
+
+

+ When the window listener thread receives the NXEVENT_SYNCHED event, it would set g_synched to true and post g_synch_sem, waking up the above loop. +

+

+ Input Parameters: +

    +
    wnd +
    The window to be synched +
    arg +
    An argument that will accompany the synch messages (This is arg2 in the event callback). +
+

+

+ Returned Value: + OK on success; ERROR on failure with errno set appropriately +

+ +

2.3.12 nx_openwindow()

Function Prototype:

     #include <nuttx/nx/nxglib.h>
@@ -1362,8 +1504,14 @@ NXWINDOW nx_openwindow(NXHANDLE handle, uint8_t flags,
     
    The handle returned by nx_connect().
     
    flags
     
    Optional flags.
-    Must be zero unless CONFIG_NX_RAMBACKED is enabled.
-    In that case, it may be zero or NXBE_WINDOW_RAMBACKED.
+      These include:
+      
      
+        
    • NXBE_WINDOW_RAMBACKED:  Creates a RAM backed window.
+          This option is only valid if CONFIG_NX_RAMBACKED is enabled.
+        
      • 
+        
    • NXBE_WINDOW_HIDDEN:  The window is create in the HIDDEN state and can be made visible later with nx_setvisibility().
+        
      • 
+      
    
     
    cb
     
    Callbacks used to process window events
     
    arg
@@ -1378,7 +1526,7 @@ NXWINDOW nx_openwindow(NXHANDLE handle, uint8_t flags,
     Failure:  NULL is returned and errno is set appropriately.
-

2.3.11 nx_closewindow()

+

2.3.13 nx_closewindow()

Function Prototype:

     #include <nuttx/nx/nxglib.h>
@@ -1406,7 +1554,7 @@ int nx_closewindow(NXWINDOW hwnd);
   ERROR on failure with errno set appropriately
 
    
 
-
    2.3.12 nx_requestbkgd()
    
+
    2.3.14 nx_requestbkgd()
    
 
    Function Prototype:
    
 
       #include <nuttx/nx/nxglib.h>
@@ -1451,6 +1599,8 @@ int nx_requestbkgd(NXHANDLE handle,
     nx_setsize(),
     nx_raise(), or
     nx_lower().
+    nx_modal().
+    nx_setvisibility().
   
   
    • 
     Neither nx_requestbkgd() nor
@@ -1476,7 +1626,7 @@ int nx_requestbkgd(NXHANDLE handle,
   ERROR on failure with errno set appropriately
 
      
 
-
      2.3.13 nx_releasebkgd()
      
+
      2.3.15 nx_releasebkgd()
      
 
      Function Prototype:
      
 
         #include <nuttx/nx/nxglib.h>
@@ -1506,7 +1656,7 @@ int nx_releasebkgd(NXWINDOW hwnd);
   ERROR on failure with errno set appropriately
 
        
 
-
        2.3.14 nx_getposition()
        
+
        2.3.16 nx_getposition()
        
 
        Function Prototype:
        
 
           #include <nuttx/nx/nxglib.h>
@@ -1534,7 +1684,7 @@ int nx_getposition(NXWINDOW hwnd);
   ERROR on failure with errno set appropriately
 
          
 
-
          2.3.15 nx_setposition()
          
+
          2.3.17 nx_setposition()
          
 
          Function Prototype:
          
 
             #include <nuttx/nx/nxglib.h>
@@ -1563,7 +1713,7 @@ int nx_setposition(NXWINDOW hwnd, FAR struct nxgl_point_s *pos);
   ERROR on failure with errno set appropriately
 
            
 
-
            2.3.16 nx_setsize()
            
+
            2.3.18 nx_setsize()
            
 
            Function Prototype:
            
 
               #include <nuttx/nx/nxglib.h>
@@ -1591,7 +1741,7 @@ int nx_setsize(NXWINDOW hwnd, FAR struct nxgl_size_s *size);
   ERROR on failure with errno set appropriately
 
              
 
-
              2.3.17 nx_raise()
              
+
              2.3.19 nx_raise()
              
 
              Function Prototype:
              
 
                 #include <nuttx/nx/nxglib.h>
@@ -1619,7 +1769,7 @@ int nx_raise(NXWINDOW hwnd);
   ERROR on failure with errno set appropriately
 
                
 
-
                2.3.18 nx_lower()
                
+
                2.3.20 nx_lower()
                
 
                Function Prototype:
                
 
                   #include <nuttx/nx/nxglib.h>
@@ -1647,7 +1797,90 @@ int nx_lower(NXWINDOW hwnd);
   ERROR on failure with errno set appropriately
 
                  
 
-
                  2.3.19 nx_fill()
                  
+
                  2.3.21 nx_modal()
                  
+
                  Function Prototype:
                  
+
                    +#include <nuttx/nx/nxglib.h>
+#include <nuttx/nx/nx.h>
+
+int nx_modal(NXWINDOW hwnd, bool modal);
+
                  
+
                  
+  Description: May be used to either (1) raise a window to the top of the display and select modal behavior, or (2) disable modal behavior.
+
                  
+
                  
+  Input Parameters:
+  
                    
+    
                    hwnd
+    
                    The handle returned by nx_openwindow().
+      This handle must not have been created by
+      nx_requestbkgd().
+    
                    modal
+    
                    True: enter modal state; False: leave modal state
+  
                  
+
                  
+
                  
+  Returned Value:
+  OK on success;
+  ERROR on failure with errno set appropriately
+
                  
+
+
                  2.3.22 nx_setvisibility()
                  
+
                  Function Prototype:
                  
+
                    +#include <nuttx/nx/nxglib.h>
+#include <nuttx/nx/nx.h>
+
+int nx_setvisibility(NXWINDOW hwnd, bool hide);
+
                  
+
                  
+  Description:  Select if the window is visible or hidden.
+  A hidden window is still present and will update normally, but will not be visible on the display until it is unhidden.
+
                  
+
                  
+  Input Parameters:
+  
                    
+    
                    hwnd
+    
                    The handle returned by nx_openwindow().
+      This handle must not have been created by
+      nx_requestbkgd().
+    
                    hide
+    
                    True: Window will be hidden; false: Window will be visible
+  
                  
+
                  
+
                  
+  Returned Value:
+  OK on success;
+  ERROR on failure with errno set appropriately
+
                  
+
+
                  2.3.23 nx_ishidden()
                  
+
                  Function Prototype:
                  
+
                    +#include <nuttx/nx/nx.h>
+
+bool nx_ishidden(NXWINDOW hwnd);
+
                  
+
                  
+  Description: Return true if the window is hidden.
+
                  
+
                  
+  NOTE:  There will be a delay between the time that the visibility of the window is changed via nx_setvisibily() before that new setting is reported by nx_ishidden().
+  nx_synch() may be used if temporal synchronization is required.
+
                  
+
                  
+  Input Parameters:
+  
                    
+    
                    hwnd
+    
                    The handle returned by nx_openwindow() that indentifies the window to be queried.
+  
                  
+
                  
+
                  
+  Returned Value:
+  True: the window is hidden, false: the window is visible
+
                  
+
+
                  2.3.24 nx_fill()
                  
 
                  Function Prototype:
                  
 
                     #include <nuttx/nx/nxglib.h>
@@ -1678,7 +1911,7 @@ int nx_fill(NXWINDOW hwnd, FAR const struct nxgl_rect_s *rect,
   ERROR on failure with errno set appropriately
 
                    
 
-
                    2.3.20 nx_getrectangle()
                    
+
                    2.3.25 nx_getrectangle()
                    
 
                    Function Prototype:
                    
 
                       #include <nuttx/nx/nxglib.h>
@@ -1718,7 +1951,7 @@ void nx_getrectangle(NXWINDOW hwnd, FAR const struct nxgl_rect_s *rect,
   ERROR on failure with errno set appropriately
 
                      
 
-
                      2.3.21 nx_filltrapezoid()
                      
+
                      2.3.26 nx_filltrapezoid()
                      
 
                      Function Prototype:
                      
 
                         #include <nuttx/nx/nxglib.h>
@@ -1752,7 +1985,7 @@ int nx_filltrapezoid(NXWINDOW hwnd, FAR const struct nxgl_rect_s *clip,
   ERROR on failure with errno set appropriately
 
                        
 
-
                        2.3.22 nx_drawline()
                        
+
                        2.3.27 nx_drawline()
                        
 
                        Function Prototype:
                        
 
                           #include <nuttx/nx/nxglib.h>
@@ -1800,7 +2033,7 @@ int nx_drawline(NXWINDOW hwnd, FAR struct nxgl_vector_s *vector,
   ERROR on failure with errno set appropriately
 
                          
 
-
                          2.3.23 nx_drawcircle()
                          
+
                          2.3.28 nx_drawcircle()
                          
 
                          Function Prototype:
                          
 
                             #include <nuttx/nx/nxglib.h>
@@ -1836,7 +2069,7 @@ int nx_drawcircle(NXWINDOW hwnd, FAR const struct nxgl_point_s *center,
   ERROR on failure with errno set appropriately
 
                            
 
-
                            2.3.24 nx_fillcircle()
                            
+
                            2.3.29 nx_fillcircle()
                            
 
                            Function Prototype:
                            
 
                               #include <nuttx/nx/nxglib.h>
@@ -1869,7 +2102,7 @@ int nx_fillcircle(NXWINDOW hwnd, FAR const struct nxgl_point_s *center,
   ERROR on failure with errno set appropriately
 
                              
 
-
                              2.3.25 nx_setbgcolor()
                              
+
                              2.3.30 nx_setbgcolor()
                              
 
                              Function Prototype:
                              
 
                                 #include <nuttx/nx/nxglib.h>
@@ -1897,7 +2130,7 @@ int nx_setbgcolor(NXHANDLE handle,
   ERROR on failure with errno set appropriately
 
                                
 
-
                                2.3.26 nx_move()
                                
+
                                2.3.31 nx_move()
                                
 
                                Function Prototype:
                                
 
                                   #include <nuttx/nx/nxglib.h>
@@ -1928,7 +2161,7 @@ int nx_move(NXWINDOW hwnd, FAR const struct nxgl_rect_s *rect,
   ERROR on failure with errno set appropriately
 
                                  
 
-
                                  2.3.27 nx_bitmap()
                                  
+
                                  2.3.32 nx_bitmap()
                                  
 
                                  Function Prototype:
                                  
 
                                     #include <nuttx/nx/nxglib.h>
@@ -1970,7 +2203,7 @@ int nx_bitmap(NXWINDOW hwnd, FAR const struct nxgl_rect_s *dest,
   ERROR on failure with errno set appropriately
 
                                    
 
-
                                    2.3.28 nx_kbdin()
                                    
+
                                    2.3.33 nx_kbdin()
                                    
 
                                    Function Prototype:
                                    
 
                                       #include <nuttx/nx/nxglib.h>
@@ -1993,7 +2226,7 @@ int nx_kbdin(NXHANDLE handle, uint8_t nch, FAR const uint8_t *ch);
   ERROR on failure with errno set appropriately
 
                                      
 
-
                                      2.3.29 nx_mousein()
                                      
+
                                      2.3.34 nx_mousein()
                                      
 
                                      Function Prototype:
                                      
 
                                         #include <nuttx/nx/nxglib.h>
@@ -2070,7 +2303,93 @@ int nx_mousein(NXHANDLE handle, nxgl_coord_t x, nxgl_coord_t y, uint8_t buttons)
 typedef FAR void *NXTKWINDOW;
 
                                      
 
-
                                      2.4.2 nxtk_openwindow()
                                      
+
                                      2.4.2 nxtk_block()
                                      
+
                                      Function Prototype:
                                      
+
                                        +#include <nuttx/nx/nxtk.h>
+
+int nxtk_block(NXWINDOW hwnd, FAR void *arg);
+
                                      
+
                                      
+  Description:
+   The response to this function call is two things:  (1) any queued callback messages to the window are 'blocked' and then (2) also subsequent window messaging is blocked.
+
                                      
+
                                      
+   The event callback with the NXEVENT_BLOCKED event is the response from nxtk_block().  This blocking interface is used to assure that no further messages are are directed to the window. Receipt of the NXEVENT_BLOCKED event signifies that (1) there are no further pending callbacks and (2) that the window is now defunct and will receive no further callbacks.
+
                                      
+
                                      
+   This callback supports coordinated destruction of a window.  The client window logic must stay intact until all of the queued callbacks are processed.  Then the window may be safely closed.  Closing the window prior with pending callbacks can lead to bad behavior when the callback is executed.
+
                                      
+
                                      
+  Input Parameters:
+  
                                        
+  
                                        
+    
                                        wnd
+    
                                        The window to be blocked
+    
                                        arg
+    
                                        An argument that will accompany the block messages (This is arg2 in the event callback).
+  
                                      
+
                                      
+
                                      
+  Returned Value:
+  OK on success; ERROR on failure with errno set appropriately.
+
                                      
+
+
                                      2.4.3 nxtk_synch()
                                      
+
                                      Function Prototype:
                                      
+
                                        +#include <nuttx/nx/nxtk.h>
+
+int nxtk_synch(NXWINDOW hwnd, FAR void *arg);
+
                                      
+
                                      
+  Description:
+  This interface can be used to synchronize the window client with the NX server.  It really just implements an echo:  A synch message is sent from the window client to the server which then responds immediately by sending the NXEVENT_SYNCHED back to the windows client.
+
                                      
+
                                      
+  Due to the highly asynchronous nature of client-server communications, nx_synch() is sometimes necessary to assure that the client and server are fully synchronized in time.
+
                                      
+
                                      
+  Usage by the window client might be something like this:
+
                                      
+
                                        +  extern bool g_synched;
+  extern sem_t g_synch_sem;
+
+  g_synched = false;
+  ret = nxtk_synch(hfwnd, handle);
+  if (ret < 0)
+    {
+       -- Handle the error --
+    }
+
+  while (!g_synched)
+    {
+      ret = sem_wait(&g_sync_sem);
+      if (ret < 0)
+        {
+           -- Handle the error --
+        }
+    }
+
                                      
+
                                      
+   When the window listener thread receives the NXEVENT_SYNCHED event, it would set g_synched to true and post g_synch_sem, waking up the above loop.
+
                                      
+
                                      
+  Input Parameters:
+  
                                        
+    
                                        wnd
+    
                                        The window to be synched
+    
                                        arg
+    
                                        An argument that will accompany the synch messages (This is arg2 in the event callback).
+  
                                      
+
                                      
+
                                      
+  Returned Value:
+  OK on success; ERROR on failure with errno set appropriately
+
                                      
+
+
                                      2.4.4 nxtk_openwindow()
                                      
 
                                      Function Prototype:
                                      
 
                                         #include <nuttx/nx/nxglib.h>
@@ -2091,8 +2410,14 @@ NXTKWINDOW nxtk_openwindow(NXHANDLE handle, uint8_t flags,
     
                                        The handle returned by nx_connect().
     
                                        flags
     
                                        Optional flags.
-    Must be zero unless CONFIG_NX_RAMBACKED is enabled.
-    In that case, it may be zero or NXBE_WINDOW_RAMBACKED.
+      These include:
+      
                                          
+        
                                        • NXBE_WINDOW_RAMBACKED:  Creates a RAM backed window.
+          This option is only valid if CONFIG_NX_RAMBACKED is enabled.
+        
                                          • 
+        
                                        • NXBE_WINDOW_HIDDEN:  The window is create in the HIDDEN state and can be made visible later with nxtk_setvisibility().
+        
                                          • 
+      
                                        
     
                                        cb
     
                                        Callbacks used to process window events
     
                                        arg
@@ -2107,7 +2432,7 @@ NXTKWINDOW nxtk_openwindow(NXHANDLE handle, uint8_t flags,
     Failure:  NULL is returned and errno is set appropriately.
 
                                      
 
-
                                      2.4.3 nxtk_closewindow()
                                      
+
                                      2.4.5 nxtk_closewindow()
                                      
 
                                      Function Prototype:
                                      
 
                                         #include <nuttx/nx/nxglib.h>
@@ -2134,7 +2459,7 @@ int nxtk_closewindow(NXTKWINDOW hfwnd);
   ERROR on failure with errno set appropriately
 
                                        
 
-
                                        2.4.4 nxtk_getposition()
                                        
+
                                        2.4.6 nxtk_getposition()
                                        
 
                                        Function Prototype:
                                        
 
                                           #include <nuttx/nx/nxglib.h>
@@ -2163,7 +2488,7 @@ int nxtk_getposition(NXTKWINDOW hfwnd);
   ERROR on failure with errno set appropriately
 
                                          
 
-
                                          2.4.5 nxtk_setposition()
                                          
+
                                          2.4.7 nxtk_setposition()
                                          
 
                                          Function Prototype:
                                          
 
                                             #include <nuttx/nx/nxglib.h>
@@ -2194,7 +2519,7 @@ int nxtk_setposition(NXTKWINDOW hfwnd, FAR struct nxgl_point_s *pos);
   ERROR on failure with errno set appropriately
 
                                            
 
-
                                            2.4.6 nxtk_setsize()
                                            
+
                                            2.4.8 nxtk_setsize()
                                            
 
                                            Function Prototype:
                                            
 
                                               #include <nuttx/nx/nxglib.h>
@@ -2225,7 +2550,7 @@ int nxtk_setsize(NXTKWINDOW hfwnd, FAR struct nxgl_size_s *size);
   ERROR on failure with errno set appropriately
 
                                              
 
-
                                              2.4.7 nxtk_raise()
                                              
+
                                              2.4.9 nxtk_raise()
                                              
 
                                              Function Prototype:
                                              
 
                                                 #include <nuttx/nx/nxglib.h>
@@ -2256,7 +2581,7 @@ int nxtk_raise(NXTKWINDOW hfwnd);
   ERROR on failure with errno set appropriately
 
                                                
 
-
                                                2.4.8 nxtk_lower()
                                                
+
                                                2.4.10 nxtk_lower()
                                                
 
                                                Function Prototype:
                                                
 
                                                   #include <nuttx/nx/nxglib.h>
@@ -2287,7 +2612,88 @@ int nxtk_lower(NXTKWINDOW hfwnd);
   ERROR on failure with errno set appropriately
 
                                                  
 
-
                                                  2.4.9 nxtk_fillwindow()
                                                  
+
                                                  2.4.11 nxtk_modal()
                                                  
+
                                                  Function Prototype:
                                                  
+
                                                    +#include <nuttx/nx/nxglib.h>
+#include <nuttx/nx/nx.h>
+#include <nuttx/nx/nxtk.h>
+
+int nxtk_modal(NXWINDOW hwnd, bool modal);
+
                                                  
+
                                                  
+  Description: May be used to either (1) raise a window to the top of the display and select modal behavior, or (2) disable modal behavior.
+
                                                  
+
                                                  
+  Input Parameters:
+  
                                                    
+    
                                                    hwnd
+    
                                                    The handle returned by nxtk_openwindow() specifying the window to be modified.
+    
                                                    modal
+    
                                                    True: enter modal state; False: leave modal state
+  
                                                  
+
                                                  
+
                                                  
+  Returned Value:
+  OK on success;
+  ERROR on failure with errno set appropriately
+
                                                  
+
+
                                                  2.4.12 nxtk_setvisibility()
                                                  
+
                                                  Function Prototype:
                                                  
+
                                                    +#include <nuttx/nx/nxglib.h>
+#include <nuttx/nx/nx.h>
+#include <nuttx/nx/nxtk.h>
+
+int nxtk_setvisibility(NXWINDOW hwnd, bool hide);
+
                                                  
+
                                                  
+  Description:  Select if the window is visible or hidden.
+  A hidden window is still present and will update normally, but will not be visible on the display until it is unhidden.
+
                                                  
+
                                                  
+  Input Parameters:
+  
                                                    
+    
                                                    hwnd
+    
                                                    The handle returned by nxtk_openwindow() specifying the window to be modified.
+    
                                                    hide
+    
                                                    True: Window will be hidden; false: Window will be visible
+  
                                                  
+
                                                  
+
                                                  
+  Returned Value:
+  OK on success;
+  ERROR on failure with errno set appropriately
+
                                                  
+
+
                                                  2.4.13 nxtk_ishidden()
                                                  
+
                                                  Function Prototype:
                                                  
+
                                                    +#include <nuttx/nx/nxtk.h>
+
+bool nxtk_ishidden(NXTKWINDOW hfwnd);
+
                                                  
+
                                                  
+  Description: Return true if the window is hidden.
+
                                                  
+
                                                  
+  NOTE:  There will be a delay between the time that the visibility of the window is changed via nxtk_setvisibily() before that new setting is reported by nxtk_ishidden().
+  nxtk_synch() may be used if temporal synchronization is required.
+
                                                  
+
                                                  
+  Input Parameters:
+  
                                                    
+    
                                                    hfwnd
+    
                                                    The handle returned by nxtk_openwindow() that indentifies the window to be queried.
+  
                                                  
+
                                                  
+
                                                  
+  Returned Value:
+  True: the window is hidden, false: the window is visible
+
                                                  
+
+
                                                  2.4.14 nxtk_fillwindow()
                                                  
 
                                                  Function Prototype:
                                                  
 
                                                     #include <nuttx/nx/nxglib.h>
@@ -2319,7 +2725,7 @@ int nxtk_fillwindow(NXTKWINDOW hfwnd, FAR const struct nxgl_rect_s *rect,
   ERROR on failure with errno set appropriately
 
                                                    
 
-
                                                    2.4.10 nxtk_getwindow()
                                                    
+
                                                    2.4.15 nxtk_getwindow()
                                                    
 
                                                    Function Prototype:
                                                    
 
                                                       #include <nuttx/nx/nxglib.h>
@@ -2359,7 +2765,7 @@ void nxtk_getwindow(NXTKWINDOW hfwnd, FAR const struct nxgl_rect_s *rect,
   ERROR on failure with errno set appropriately
 
                                                      
 
-
                                                      2.4.11 nxtk_filltrapwindow()
                                                      
+
                                                      2.4.16 nxtk_filltrapwindow()
                                                      
 
                                                      Function Prototype:
                                                      
 
                                                         #include <nuttx/nx/nxglib.h>
@@ -2392,7 +2798,7 @@ int nxtk_filltrapwindow(NXTKWINDOW hfwnd,
   ERROR on failure with errno set appropriately
 
                                                        
 
-
                                                        2.4.12 nxtk_drawlinewindow()
                                                        
+
                                                        2.4.17 nxtk_drawlinewindow()
                                                        
 
                                                        Function Prototype:
                                                        
 
                                                           #include <nuttx/nx/nxglib.h>
@@ -2441,7 +2847,7 @@ int nxtk_drawlinewindow(NXTKWINDOW hfwnd, FAR struct nxgl_vector_s *vector,
   ERROR on failure with errno set appropriately
 
                                                          
 
-
                                                          2.4.13 nxtk_drawcirclewindow()
                                                          
+
                                                          2.4.18 nxtk_drawcirclewindow()
                                                          
 
                                                          Function Prototype:
                                                          
 
                                                             #include <nuttx/nx/nxglib.h>
@@ -2477,7 +2883,7 @@ int nxtk_drawcirclewindow(NXTKWINDOW hfwnd, FAR const struct nxgl_point_s *cente
   ERROR on failure with errno set appropriately
 
                                                            
 
-
                                                            2.4.14 nxtk_fillcirclewindow()
                                                            
+
                                                            2.4.19 nxtk_fillcirclewindow()
                                                            
 
                                                            Function Prototype:
                                                            
 
                                                               #include <nuttx/nx/nxglib.h>
@@ -2510,7 +2916,7 @@ int nxtk_fillcirclewindow(NXWINDOW hfwnd, FAR const struct nxgl_point_s *center,
   ERROR on failure with errno set appropriately
 
                                                              
 
-
                                                              2.4.15 nxtk_movewindow()
                                                              
+
                                                              2.4.20 nxtk_movewindow()
                                                              
 
                                                              Function Prototype:
                                                              
 
                                                                 #include <nuttx/nx/nxglib.h>
@@ -2543,7 +2949,7 @@ int nxtk_movewindow(NXTKWINDOW hfwnd, FAR const struct nxgl_rect_s *rect,
   ERROR on failure with errno set appropriately
 
                                                                
 
-
                                                                2.4.16 nxtk_bitmapwindow()
                                                                
+
                                                                2.4.21 nxtk_bitmapwindow()
                                                                
 
                                                                Function Prototype:
                                                                
 
                                                                   #include <nuttx/nx/nxglib.h>
@@ -2588,7 +2994,7 @@ int nxtk_bitmapwindow(NXTKWINDOW hfwnd,
   ERROR on failure with errno set appropriately
 
                                                                  
 
-
                                                                  2.4.17 nxtk_opentoolbar()
                                                                  
+
                                                                  2.4.22 nxtk_opentoolbar()
                                                                  
 
                                                                  Function Prototype:
                                                                  
 
                                                                     #include <nuttx/nx/nxglib.h>
@@ -2623,7 +3029,7 @@ int nxtk_opentoolbar(NXTKWINDOW hfwnd, nxgl_coord_t height,
   ERROR on failure with errno set appropriately
 
                                                                    
 
-
                                                                    2.4.18 nxtk_closetoolbar()
                                                                    
+
                                                                    2.4.23 nxtk_closetoolbar()
                                                                    
 
                                                                    Function Prototype:
                                                                    
 
                                                                       #include <nuttx/nx/nxglib.h>
@@ -2652,7 +3058,7 @@ int nxtk_closetoolbar(NXTKWINDOW hfwnd);
   ERROR on failure with errno set appropriately
 
                                                                      
 
-
                                                                      2.4.19 nxtk_filltoolbar()
                                                                      
+
                                                                      2.4.24 nxtk_filltoolbar()
                                                                      
 
                                                                      Function Prototype:
                                                                      
 
                                                                         #include <nuttx/nx/nxglib.h>
@@ -2684,7 +3090,7 @@ int nxtk_filltoolbar(NXTKWINDOW hfwnd, FAR const struct nxgl_rect_s *rect,
   ERROR on failure with errno set appropriately
 
                                                                        
 
-
                                                                        2.4.19 nxtk_gettoolbar()
                                                                        
+
                                                                        2.4.25 nxtk_gettoolbar()
                                                                        
 
                                                                        Function Prototype:
                                                                        
 
                                                                           #include <nuttx/nx/nxglib.h>
@@ -2725,7 +3131,7 @@ int nxtk_gettoolbar(NXTKWINDOW hfwnd, FAR const struct nxgl_rect_s *rect,
   ERROR on failure with errno set appropriately
 
                                                                          
 
-
                                                                          2.4.21 nxtk_filltraptoolbar()
                                                                          
+
                                                                          2.4.26 nxtk_filltraptoolbar()
                                                                          
 
                                                                          Function Prototype:
                                                                          
 
                                                                             #include <nuttx/nx/nxglib.h>
@@ -2757,7 +3163,7 @@ int nxtk_filltraptoolbar(NXTKWINDOW hfwnd, FAR const struct nxgl_trapezoid_s *tr
   ERROR on failure with errno set appropriately
 
                                                                            
 
-
                                                                            2.4.22 nxtk_drawlinetoolbar()
                                                                            
+
                                                                            2.4.27 nxtk_drawlinetoolbar()
                                                                            
 
                                                                            Function Prototype:
                                                                            
 
                                                                               #include <nuttx/nx/nxglib.h>
@@ -2806,7 +3212,7 @@ int nxtk_drawlinetoolbar(NXTKWINDOW hfwnd, FAR struct nxgl_vector_s *vector,
   ERROR on failure with errno set appropriately
 
                                                                              
 
-
                                                                              2.4.23 nxtk_drawcircletoolbar()
                                                                              
+
                                                                              2.4.28 nxtk_drawcircletoolbar()
                                                                              
 
                                                                              Function Prototype:
                                                                              
 
                                                                                 #include <nuttx/nx/nxglib.h>
@@ -2842,7 +3248,7 @@ int nxtk_drawcircletoolbar(NXTKWINDOW hfwnd, FAR const struct nxgl_point_s *cent
   ERROR on failure with errno set appropriately
 
                                                                                
 
-
                                                                                2.4.24 nxtk_fillcircletoolbar()
                                                                                
+
                                                                                2.4.29 nxtk_fillcircletoolbar()
                                                                                
 
                                                                                Function Prototype:
                                                                                
 
                                                                                   #include <nuttx/nx/nxglib.h>
@@ -2875,7 +3281,7 @@ int nxtk_fillcircletoolbar(NXWINDOW hfwnd, FAR const struct nxgl_point_s *center
   ERROR on failure with errno set appropriately
 
                                                                                  
 
-
                                                                                  2.4.25 nxtk_movetoolbar()
                                                                                  
+
                                                                                  2.4.30 nxtk_movetoolbar()
                                                                                  
 
                                                                                  Function Prototype:
                                                                                  
 
                                                                                     #include <nuttx/nx/nxglib.h>
@@ -2909,7 +3315,7 @@ int nxtk_movetoolbar(NXTKWINDOW hfwnd, FAR const struct nxgl_rect_s *rect,
   ERROR on failure with errno set appropriately
 
                                                                                    
 
-
                                                                                    2.4.26 nxtk_bitmaptoolbar()
                                                                                    
+
                                                                                    2.4.31 nxtk_bitmaptoolbar()
                                                                                    
 
                                                                                    Function Prototype:
                                                                                    
 
                                                                                       #include <nuttx/nx/nxglib.h>
@@ -3138,7 +3544,115 @@ int nxf_convert_32bpp(FAR uint32_t *dest, uint16_t height,
   ERROR on failure with errno set appropriately.
 
                                                                                      
 
-
                                                                                      2.6 Sample Code
                                                                                      
+
+
+   
                                                                                      
+     2.6 
+   
                                                                                      
+   
                                                                                      
+     
                                                                                      
+   
                                                                                      
+
+
                                                                                      2.6 NX Cursor Support (NXCURSOR)
                                                                                      
+
+
                                                                                      2.6.1 nxcursor_enable()
                                                                                      
+
                                                                                      Function Prototype:
                                                                                      
+
                                                                                        +#include <nuttx/nx/nxcursor.h>
+
+#ifdef CONFIG_NX_SWCURSOR
+int nxcursor_enable(NXHANDLE hnd, bool enable);
+#endif
+
                                                                                      
+
                                                                                      
+  Description:
+  Enable/disable presentation of the cursor.  The disabled cursor still exits and still may be controlled, but is not visible on the display.
+
                                                                                      
+
                                                                                      
+  Input Parameters:
+  
                                                                                        
+    
                                                                                        hnd
+    
                                                                                        The server handle returned by nx_connect().
+    
                                                                                        enable
+    
                                                                                        The new cursor position
+  
                                                                                      
+
                                                                                      
+
                                                                                      
+  Returned Value:
+  OK on success; ERROR on failure with errno set appropriately.
+
                                                                                      
+
+
                                                                                      2.6.2 nxcursor_setimage()
                                                                                      
+
                                                                                      Function Prototype:
                                                                                      
+
                                                                                        +#include <nuttx/nx/nxcursor.h>
+
+#ifdef CONFIG_NX_SWCURSOR
+int nxcursor_setimage(NXHANDLE hnd, FAR const struct nx_cursorimage_s *image);
+#endif
+
                                                                                      
+
                                                                                      
+  Description:
+  Set the cursor image.
+
                                                                                      
+
                                                                                      
+  The image is provided a a 2-bits-per-pixel image.  The two bit incoding is as followings:
+
                                                                                      
+
                                                                                        
+  00 - The transparent background.
                                                                                        
+  01 - Color1:  The main color of the cursor.
                                                                                        
+  10 - Color2:  The color of any border.
                                                                                        
+  11 - Color3:  A blend color for better imaging (fake anti-aliasing).
                                                                                        
+
                                                                                      
+
                                                                                      
+  NOTE: The NX logic will reference the user image buffer repeatedly.  That image buffer must persist for as long as the NX server connection persists.
+
                                                                                      
+
                                                                                      
+  Input Parameters:
+  
                                                                                        
+    
                                                                                        hnd
+    
                                                                                        The server handle returned by nx_connect().
+    
                                                                                        image
+    
                                                                                        An instance of struct struct nx_cursorimage_s that describes the cursor image.  See  <nuttx/nx/nxcursor.h> for the full description of this structure.
+  
                                                                                      
+
                                                                                      
+
                                                                                      
+  Returned Value:
+  OK on success; ERROR on failure with errno set appropriately.
+
                                                                                      
+
+
                                                                                      2.6.3 nxcursor_setposition()
                                                                                      
+
                                                                                      Function Prototype:
                                                                                      
+
                                                                                        +#include <nuttx/nx/nxcursor.h>
+
+#ifdef CONFIG_NX_SWCURSOR
+int nxcursor_setposition(NXHANDLE hnd, FAR const struct nxgl_point_s *pos);
+#endif
+
                                                                                      
+
                                                                                      
+  Description:
+  Move the cursor to the specified position.
+
                                                                                      
+
                                                                                      
+  Input Parameters:
+  
                                                                                        
+    
                                                                                        hnd
+    
                                                                                        The server handle returned by nx_connect().
+    
                                                                                        pos
+    
                                                                                        The new cursor position
+  
                                                                                      
+
                                                                                      
+
                                                                                      
+  Returned Value:
+  OK on success; ERROR on failure with errno set appropriately.
+
                                                                                      
+
+
                                                                                      2.7 Sample Code
                                                                                      
 
 
                                                                                      apps/examples/nx*.
   No sample code is provided in this document.
@@ -3262,6 +3776,11 @@ int nxf_convert_32bpp(FAR uint32_t *dest, uint16_t height,
       If this option is selected, then the system will redraw the exposed portion of the window from the backup framebuffer without intervention of the window applications.
       This greatly reduces the complexity of the application and performance of the window at the expense of increased memory usage.
     
                                                                                      
+    
                                                                                      
+       An exception is the case when the window is resized to a wider and/or taller size.
+       In that case, the redraw callback will till occur.
+       It is necessary in that case to provide new graphic content for the extended window area.
+    
                                                                                      
     
                                                                                      
       Redraw requests in other cases are also suppressed:  Changes to window position, size, etc.
     
                                                                                      
@@ -4012,6 +4531,22 @@ sudo ln -s libXext.so.6.4.0 libXext.so
      <NuttX-Directory>/.config file
   YES
 
+
+
+  nx_modal()
+   
+  NO
+
+
+  nx_setvisibility()
+  Exercized using Twm4Nx
+  YES, Informally
+
+
+  nx_ishidden()
+  Exercized using Twm4Nx
+  YES, Informally
+
 
   nx_fill()
   Change to CONFIG_EXAMPLES_NX_RAWWINDOWS=y in the
@@ -4123,6 +4658,21 @@ sudo ln -s libXext.so.6.4.0 libXext.so
   
                                                                                      
   YES
 
+
+  nxtk_modal()
+  
                                                                                      
+  NO
+
+
+  nxtk_setvisibility()
+  Exercized using Twm4Nx
+  YES, informally
+
+
+  nxtk_ishidden()
+  Exercized using Twm4Nx
+  YES, informally
+
 
   nxtk_fillwindow()
   
                                                                                      
diff --git a/Documentation/NuttShell.html b/Documentation/NuttShell.html
index 0351d9fcd28..9d9ca632745 100644
--- a/Documentation/NuttShell.html
+++ b/Documentation/NuttShell.html
@@ -1,18 +1,11 @@
 
 
 NuttShell
+
 
 
-
                                                                                      
-
-  
-    
-  
-
                                                                                      
-      
                                                                                      NuttShell (NSH)
                                                                                      
-      
                                                                                      Last Updated:  February 11, 2019
                                                                                      
-    
                                                                                      
-
                                                                                      
+
                                                                                      
+
                                                                                      
 
                                                                                      
   
                                                                                      
     
@@ -21,7 +14,7 @@
   
                                                                                      
 
                                                                                      
 
-
                                                                                      
+
                                                                                      
 
                                                                                      
 
 
@@ -626,7 +619,21 @@
     Index
-
                                                                                      
   
 
                                                                                      
+
                                                                                      
+
                                                                                      
+
+
                                                                                      
+
                                                                                      
+
+  
+    
+  
+
                                                                                      
+      
                                                                                      NuttShell (NSH)
                                                                                      
+      
                                                                                      Last Updated:  February 11, 2019
                                                                                      
+    
                                                                                      
+
                                                                                      
+
 
 
@@ -1494,7 +1501,7 @@ date [-s "MMM DD HH:MM:SS YYYY"]
   Only one format is used both on display and when setting the date/time:
   MMM DD HH:MM:SS YYYY.  For example,
 
                                                                                        -data -s "Sep 1 11:30:00 2011"
+date -s "Sep 1 11:30:00 2011"
 
                                                                                      
@@ -3731,7 +3738,7 @@ nsh>
   
                                                                                      
-    
+    
@@ -3881,7 +3888,7 @@ nsh>
   
-    
+    
@@ -3941,7 +3948,7 @@ nsh>
   
-    
+    
@@ -3996,12 +4003,12 @@ nsh>
   
+        CONFIG_NET_ICMP_SOCKET && CONFIG_SYSTEM_PING
+        CONFIG_NET_ICMPv6_SOCKET && CONFIG_SYSTEM_PING6
                                                                                      
   
                                                                                      
 
 
                                                                                      
   
                                                                                      
     kill!CONFIG_DISABLE_SIGNALS 
     CONFIG_NSH_DISABLE_KILL
   
                                                                                      
   
                                                                                      
   
                                                                                      
     sleep!CONFIG_DISABLE_SIGNALS 
     CONFIG_NSH_DISABLE_SLEEP
   
                                                                                      
   
                                                                                      
   
                                                                                      
     usleep!CONFIG_DISABLE_SIGNALS 
     CONFIG_NSH_DISABLE_USLEEP
   
                                                                                      
   
                                                                                      
     ping
     CONFIG_NET && CONFIG_NET_ICMP &&
-        CONFIG_NET_ICMP_SOCKET && CONFIG_SYSTEM_PING && !CONFIG_DISABLE_SIGNALS && !CONFIG_DISABLE_POLL
   
                                                                                      
   
                                                                                      
     ping6
     CONFIG_NET && CONFIG_NET_ICMPv6 &&
-        CONFIG_NET_ICMPv6_SOCKET && CONFIG_SYSTEM_PING6 && !CONFIG_DISABLE_SIGNALS && !CONFIG_DISABLE_POLL
   
                                                                                      
 
                                                                                      
 
@@ -5912,5 +5919,7 @@ xxd -i romfs_img >nsh_romfsimg.h
 
                                                                                    
 
 
+
+
 
 
diff --git a/Documentation/NuttX.html b/Documentation/NuttX.html
index cc4f2ea654a..7c6111b6d4e 100644
--- a/Documentation/NuttX.html
+++ b/Documentation/NuttX.html
@@ -1,18 +1,11 @@
 
 
 NuttX
+
 
 
-
                                                                                    
-
-  
-    
-  
-
                                                                                    
-      
                                                                                    NuttX RTOS
                                                                                    
-      
                                                                                    Last Updated: March 25, 2019
                                                                                    
-    
                                                                                    
-
                                                                                    
+
                                                                                    
+
                                                                                    
 
                                                                                    
   
                                                                                    
     
@@ -21,7 +14,7 @@
   
                                                                                    
 
                                                                                    
 
-
                                                                                    
+
                                                                                    
-
                                                                                    
 
                                                                                    
 
 
@@ -102,7 +95,20 @@
 
                                                                                    
                                                                                     		
 
                                                                                    
+
+
                                                                                    
+
+
                                                                                    
+
                                                                                    
+
+  
+    
+  
+
                                                                                    
+      
                                                                                    NuttX RTOS
                                                                                    
+      
                                                                                    Last Updated: May 19, 2019
                                                                                    
+    
                                                                                    
+
                                                                                    
 
 
@@ -1461,11 +1467,11 @@
 
                                                                                    Released Versions
                                                                                    
   In addition to the ever-changing GIT repository, there are frozen released versions of NuttX available.
-  The current release is NuttX 7.29.
-  NuttX 7.29 is the 129th release of NuttX.
-  It was released on March 25, 2019, and is available for download from the
+  The current release is NuttX 7.30.
+  NuttX 7.30 is the 130th release of NuttX.
+  It was released on May 19, 2019, and is available for download from the
   Bitbucket.org website.
-  Note that the release consists of two tarballs:  nuttx-7.29.tar.gz and apps-7.29.tar.gz.
+  Note that the release consists of two tarballs:  nuttx-7.30.tar.gz and apps-7.30.tar.gz.
   Both may be needed (see the top-level nuttx/README.txt file for build information).
 
                                                                                    
 
@@ -1474,7 +1480,7 @@
 
                                                                                      
   
                                                                                    • nuttx.
     
                                                                                        
-      Release notes for NuttX 7.29 are available here.
+      Release notes for NuttX 7.30 are available here.
       Release notes for all released versions on NuttX are available in the Bitbucket GIT.
       The ChangeLog for all releases of NuttX is available in the ChangeLog file that can viewed in the Bitbucket GIT.
       The ChangeLog for the current release is at the bottom of that file.
@@ -1482,7 +1488,7 @@
   
                                                                                      
   
                                                                                    • apps.
     
   
                                                                                    • Atmel AVR
     
   
                                                                                      • 
+  
                                                                                    • Sony.
+    
+  
                                                                                      • 
   
                                                                                    • STMicroelectronics
     
                                                                                        
       
                                                                                      • STMicro STR71x (ARM7TDMI)
                                                                                        • 
@@ -3197,33 +3208,8 @@ nsh>
         Contributed by Juha Niskanen in NuttX-7.21.
       
     
                                                                                      
-    
                                                                                      
-      STATUS:
-    
                                                                                      
-    
                                                                                        
-      
                                                                                      • 
-        NuttX-7.21.
-        In this initial release, the level of support for the STM32 F0 family is minimal.
-        Certainly enough is in place to support a robust NSH configuration.
-        There are also unverified I2C and USB device drivers available in
-        NuttX-7.21.
-      
                                                                                        • 
-      
                                                                                      • 
-        NuttX-7.28
-        Added support for GPIO EXTI.  From Mateusz Sfafoni.
-      
                                                                                        • 
-      
                                                                                      • 
-        NuttX-7.29
-        Added an SPI driver.  From Mateusz Sfafoni.
-      
                                                                                        • 
-    
                                                                                        
   
 
                                                                                    
-
-
-  
-  
-
+
+  
+  
-
 
@@ -3906,7 +3922,7 @@ nsh>
   
@@ -4208,6 +4224,7 @@ nsh>
   
+
 
@@ -4216,8 +4233,32 @@ nsh>
   
+
+
+  
+  
+
+
+  
+  
@@ -5537,6 +5582,9 @@ Mem:         29232       5920      23312      23312
         See the board README.txt file for further information.
       
                                                                                    
+    
                                                                                    STATUS:
+      See below for STM32 F7 driver availability.
+    
                                                                                    
 
@@ -5556,6 +5604,7 @@ Mem:         29232       5920      23312      23312
         
                                                                                    
           STM32F746G Discovery.
            One port uses the STMicro STM32F746G-DISCO development board featuring the STM32F746NGH6 MCU. The STM32F746NGH6  is a 216MHz Cortex-M7 operation with 1024Kb Flash.
+           The first release of the STM32F746G_DISCO port was available in NuttX-7.11.
            Refer to the STMicro web site for further information about this board.
         
                                                                                    
@@ -5569,17 +5618,8 @@ Mem:         29232       5920      23312      23312
     
                                                                                      
       
                                                                                      
         STATUS:
-      
                                                                                      
-      
                                                                                        
-        
                                                                                        
-          The basic STM32F746G-DISCO port is complete and there are two, verified configurations available.
-          Both configurations use the NuttShell (NSH) and a serial console; one includes Ethernet support.
-          The first release of the STM32F746G_DISCO port was available in NuttX-7.11.
-        
                                                                                        
-        
                                                                                        
           Refer to the NuttX board README file for further information.
-        
                                                                                        
-      
                                                                                      
+      
                                                                                      
     
                                                                                    
       STM32 F7 Driver Status:
@@ -5596,9 +5636,22 @@ Mem:         29232       5920      23312      23312
         David Sidrane contributed PWR, RTC, BBSRAM, and DBGMCU support.
         Lok Tep contribed SPI, I2c, ADC, SDMMC, and USB device driver support.
       
+      
                                                                                  • 
+        
                                                                                    NuttX-7.22.
+          Titus von Boxberg also contributed LTDC support for the onboard LCD in NuttX-7.22.
+        
                                                                                    
+      
                                                                                  • 
         
                                                                                    NuttX-7.29.
-        In NuttX-7.29, Valmantas Paliksa added a timer lowerhalf driver for STM32F7, ITM syslog support, a CAN driver with support for three bxCAN interfaces, and STM32F7 Quad SPI support.
+          In NuttX-7.29, Valmantas Paliksa added a timer lowerhalf driver for STM32F7, ITM syslog support, a CAN driver with support for three bxCAN interfaces, and STM32F7 Quad SPI support.
+          Support for DMA and USB OTG was added by Mateusz Szafoni in NuttX-7.29.
+        
                                                                                    
+      
                                                                                    • 
+      
                                                                                  • 
+        
                                                                                    NuttX-7.30.
+          From Eduard Niesner contributed a PWM driver.
+          Added UID access from Valmantas Paliksa.
+          USB High speed driver was added for STM32F7 series by Ramtin Amin.
       
                                                                                    • 
@@ -5663,15 +5716,12 @@ Mem:         29232       5920      23312      23312
           
                                                                                  • Ethernet connector compliant with IEEE-802.3-2002 and PoE
                                                                                    • 
-          Refer to the http://www.st.com website for further information about this board (search keyword: stm32f769i-disco)
-        
                                                                                    
-        
                                                                                    
-          Titus von Boxberg also contributed LTDC support for the onboard LCD in NuttX-7.22.
-          See the board README.txt file for further information.
+          Refer to the http://www.st.com website for further information about this board (search keyword: stm32f769i-disco).
+          See also the board README.txt file for further information.
         
                                                                                    
-    
                                                                                    
+    
                                                                                    STATUS:
       See above for STM32 F7 driver availability.
     
                                                                                    
@@ -5696,15 +5746,29 @@ Mem:         29232       5920      23312      23312
           This is a member of the Nucleo-144 board family.
           Support for this board was also added NuttX-7.26.
           See the board README.txt file for further information.
+        
                                                                                    
           The basic NSH configuration is fully, thanks to the bring-up efforts of Mateusz Szafoni.
           This port is port is still a work in progress and additional drivers are being ported from the F7 family.
         
                                                                                    
-    
                                                                                    
-      NuttX-7.29
-      Support for DMA and USB OTG was added by Mateusz Szafoni in NuttX-7.29.
+
+
                                                                                    
+  
+  
@@ -5733,9 +5797,13 @@ Mem:         29232       5920      23312      23312
         Refer to the NuttX board README file for further information.
       
                                                                                  • 
-        The basic IMXRT1060-EVK port is complete but un-verified as of NuttX-7.27.
+        The basic IMXRT1060-EVK port was complete but un-verified as of NuttX-7.27 but has been fully verified since NuttX-7.27
         Refer to the NuttX board README file for more current status information.
       
                                                                                    • 
+      
                                                                                  • 
+        Architecture-only support for the IMXRT1020 family was contributed in NuttX-7.30 by Dave Marples.
+        Board support is anticipated in the next release.
+      
                                                                                    • 
       i.MX RT Driver Status:
@@ -7046,5 +7114,7 @@ if [ -x "$WINELOADER" ]; then exec "$WINELOADER" "$appname" "$@"; fi
 
                                                                                    
 
+
+
diff --git a/Documentation/NuttXBinfmt.html b/Documentation/NuttXBinfmt.html
index d229492464e..e1898e897f6 100644
--- a/Documentation/NuttXBinfmt.html
+++ b/Documentation/NuttXBinfmt.html
@@ -1,6 +1,7 @@
 NuttX Binary Loader
+
                                                                                    
diff --git a/Documentation/NuttXCCodingStandard.html b/Documentation/NuttXCCodingStandard.html
index f3bf450eac0..cd6eead0d59 100644
--- a/Documentation/NuttXCCodingStandard.html
+++ b/Documentation/NuttXCCodingStandard.html
@@ -2,22 +2,12 @@
 NuttX C Coding Standard
+
 
-
-
                                                                                    
-
                                                                                    
   
                                                                                    
 

                                                                                    
 
                                                                                    
   
                                                                                    		
   
@@ -3242,9 +3228,39 @@ nsh>
         Contributed byMateusz Sfafoni in NuttX-7.28.
       
     
+

                                                                                    		
+    
                                                                                    
+      STATUS:
+      Status for both the STM32F0xx and STM32L0xx is show together since the two parts share many drivers in common.
+    
                                                                                    
+    
                                                                                      
+      
                                                                                    • 
+        NuttX-7.21.
+        In this initial release, the level of support for the STM32 F0 family is minimal.
+        Certainly enough is in place to support a robust NSH configuration.
+        There are also unverified I2C and USB device drivers available in
+        NuttX-7.21.
+      
                                                                                      • 
+      
                                                                                    • 
+        NuttX-7.28
+        Added support for GPIO EXTI.  From Mateusz Sfafoni.
+      
                                                                                      • 
+      
                                                                                    • 
+        NuttX-7.29
+        Added an SPI driver.  From Mateusz Sfafoni.
+      
                                                                                      • 
+      
                                                                                    • 
+        NuttX-7.30
+        Added ADC and I2C drivers.  From Mateusz Szafoni.
+        Add AES and RND drivers for the L0.  From Mateusz Szafoni.
+        Add support for HS148 for L0.  From Mateusz Szafoni.
+      
                                                                                      • 
+    
                                                                                      
   
                                                                                    		
 
                                                                                    
   
                                                                                    		
   
                                                                                    		
     
                                                                                    
       ON Semiconductor LC823450 (Dual core ARM Cortex-M3).
-      In NuttX-7.22, Masayuki Ishakawa contributed support for both the LC823450 architecture and for ON Semiconductor's LC823450XGEVK board:
+      In NuttX-7.22, Masayuki Ishikawa contributed support for both the LC823450 architecture and for ON Semiconductor's LC823450XGEVK board:
     
                                                                                    
     
                                                                                    
       The LC823450XGEVK is an audio processing system Evaluation Board Kit used to demonstrate the LC823450.  This part can record and playback, and offers High-Resolution 32-bit & 192 kHz audio processing capability.  It is possible to cover most of the functions necessary for a portable audio with only this LSI as follows.  It has Dual CPU and DSP with High processing capability, and internal 1656K-Byte SRAM, which make it possible to implement large scale program.  And it has integrated analog functions (low-power Class D HP amplifier, PLL, ADC etc.) so that PCB space and cost is reduced, and it has various interface (USB, SD, SPI, UART, etc.) to make extensibility high.  Also it is provided with various function including SBC/AAC codec by DSP and UART and ASRC (Asynchronous Sample Rate Converter) for Bluetooth® audio. It is very small chip size in spite of the multi-funciton as described above and it realizes the low power consumption. Therefore, it is applicable to portable audio markets such as Wireless headsets and will show high performance.
@@ -3917,8 +3933,8 @@ nsh>
     
                                                                                    
     
                                                                                    
       This port is intended to test LC823450 features including SMP. Supported peripherals include UART, TIMER, RTC, GPIO, DMA, I2C, SPI, LCD, eMMC, and USB device.
-      ADC, Watchdog, IPC2, and I2S support was added by Masayuki Ishakawa in NuttX-7.23.
-      Bluetooth, SPI, and PROTECTED build support were added by Masayuki Ishakawa in NuttX-7.26.
+      ADC, Watchdog, IPC2, and I2S support was added by Masayuki Ishikawa in NuttX-7.23.
+      Bluetooth, SPI, and PROTECTED build support were added by Masayuki Ishikawa in NuttX-7.26.
       Support for for SPI flash boot was added in NuttX-7.28.
     
                                                                                    
   
                                                                                    		
 
                                                                                    
 
                                                                                    
   
                                                                                    		
   

                                                                                    		
   
     
                                                                                    
-      STMicro STM32 F302 (STM32 F3 family).
-      Architecture (only) support for the STM32 F302 was contributed in NuttX-7.10 by Ben Dyer (vi the PX4 team and David Sidrane).
+      Sony CXD56xx (6 x ARM Cortex-M4).
+      Support for the CXD56xx was introduced by Nobuto Kobayashi in NuttX-7.30.
+    
                                                                                    
+    
                                                                                    
+      Sony Spresence.
+      Basic support for the Sony Spresense board was include in the contribution of Nobuto Kobayashi in NuttX-7.30.  NOTE:  This is a bare bone basic Spresense port sufficient for running a NuttShell (NSH) and should not be confused with the full Spresence SDK offered from Sony.
+    
                                                                                    
+      Spresense is a compact development board based on Sony’s power-efficient multicore microcontroller CXD5602.  Features:
+    
                                                                                    
+    
                                                                                      
+      
                                                                                    • Integrated GPS:  Embedded GNSS with support for GPS, QZSS.
                                                                                      • 
+      
                                                                                    • Hi-res audio output and multi mic inputs"  Advanced 192kHz/24 bit audio codec and amplifier for audio output, and support for up to 8 mic input channels.
                                                                                      • 
+      
                                                                                    • Multicore microcontroller:  Spresense is powered by Sony's CXD5602 microcontroller (ARM® Cortex®-M4F × 6 cores), with a clock speed of 156 MHz.
                                                                                      • 
+    
                                                                                    
+  


                                                                                    		
+    
                                                                                    
+      STMicro STM32 F302 (STM32 F3 family).
+      Architecture (only) support for the STM32 F302 was contributed in NuttX-7.10 by Ben Dyer (via the PX4 team and David Sidrane).
     
                                                                                    
     
                                                                                    
       Support for the Nucleo-F302R8 board was added by raiden00pl in NuttX-7.27.
@@ -4233,7 +4274,7 @@ nsh>
   

                                                                                    		
   
     
                                                                                    
-      STMicro STM32 F303 (STM32 F3 family).
+      STMicro STM32 F303 (STM32 F3 family).
     
                                                                                    
     
                                                                                      
     
                                                                                    • 
@@ -4273,7 +4314,7 @@ nsh>
   

                                                                                    		
   
     
                                                                                    
-      STMicro STM32 F334 (STM32 F3 family, ARM Cortex-M4).
+      STMicro STM32 F334 (STM32 F3 family, ARM Cortex-M4).
     
                                                                                    
     
                                                                                    
       Support for the STMicro STM32F334-Disco board was contributed by Mateusz Szafoni in NuttX-7.22 and for the Nucleo-STM32F334R8 was contributed in an earlier release.
@@ -4289,7 +4330,7 @@ nsh>
   

                                                                                    		
   
     
                                                                                    
-      STMicro STM32 F372/F373 (Cortex-M4).
+      STMicro STM32 F372/F373 (ARM Cortex-M4).
     
                                                                                    
     
                                                                                    
       Basic architecture support for the STM32F372/F373 was contributed by Marten Svanfeldt in NuttX 7.9.
@@ -4306,7 +4347,7 @@ nsh>
   

                                                                                    		
   
     
                                                                                    
-      STMicro STM324x1 (STM32 F4 family).
+      STMicro STM324x1 (STM32 F4 family).
     
                                                                                    
     
                                                                                      
     
                                                                                      
@@ -4347,7 +4388,7 @@ nsh>
   

                                                                                    		
   
     
                                                                                    
-      STMicro STM32410 (STM32 F4 family).
+      STMicro STM32410 (STM32 F4 family).
     
                                                                                    
     
                                                                                      
     
                                                                                      
@@ -4364,7 +4405,7 @@ nsh>
   

                                                                                    		
   
     
                                                                                    
-      STMicro STM32405x/407x (STM32 F4 family).
+      STMicro STM32405x/407x (STM32 F4 family).
     
                                                                                    
     
                                                                                      
     
                                                                                      
@@ -4761,6 +4802,10 @@ nsh>
     
                                                                                        
       
                                                                                      • DAC and ADC drivers were contributed by Juha Niskanen.
                                                                                        • 
     
                                                                                      
+    
                                                                                      
+      NuttX-7.30.
+    
                                                                                        
+      
                                                                                      • Added USB FS device driver, CRS and HSI38 support from Juha Niskanen.
                                                                                        • 
     
                                                                                        
   
                                                                                    		
 
                                                                                    
     
   
 
       
     
       
     
   
         
         
       
     
   
         
       
     

                                                                                    		
+    
                                                                                    Driver Availability:
                                                                                    
+    
                                                                                      
+      
                                                                                    • 
+         
                                                                                      NuttX-7.27.
+         Add I2C and SPI support for the STM32H7.  From Mateusz Szafoni.
+         
                                                                                      
+      
                                                                                      • 
+      
                                                                                    • 
+        
                                                                                      NuttX-7.30.
+         Added support for Ethernet, SDMMC, and Timer drivers.  All from Jukka Laitinen.
+        
                                                                                      
+      
                                                                                      • 
     
                                                                                      
   
                                                                                    		
 
                                                                                    
       
     
     
 
 
 
 
 
 
 
 
 
 
 
                                                                                    
-  
-    
-  
-
                                                                                    
-      
                                                                                    
-        NuttX C Coding Standard
-      
                                                                                    
-      
                                                                                    Last Updated: February 5, 2019
                                                                                    
-    
                                                                                    
-
                                                                                    
-
+
+
                                                                                    
+
                                                                                    
 
                                                                                    
   
                                                                                    
     
@@ -74,6 +64,21 @@
     A.2 C Header File Structure
   
 
+
+
+
                                                                                    
+
                                                                                    
+
+  
+    
+  
+
                                                                                    
+      
                                                                                    
+        NuttX C Coding Standard
+      
                                                                                    
+      
                                                                                    Last Updated: February 5, 2019
                                                                                    
+    
                                                                                    
+
                                                                                    
 
 
@@ -2984,5 +2989,8 @@ Each is preceded by a function header similar to the above.
                                                                                    Ending with the header file idempotence #endif.
                                                                                    
 
+
+
+
 
diff --git a/Documentation/NuttXDemandPaging.html b/Documentation/NuttXDemandPaging.html
index e3a682c8b2d..b18e97480ac 100644
--- a/Documentation/NuttXDemandPaging.html
+++ b/Documentation/NuttXDemandPaging.html
@@ -1,6 +1,7 @@
 On-Demand Paging
+
                                                                                    
diff --git a/Documentation/NuttXNxFlat.html b/Documentation/NuttXNxFlat.html
index 5fe5c24455c..4e44e45fce3 100644
--- a/Documentation/NuttXNxFlat.html
+++ b/Documentation/NuttXNxFlat.html
@@ -1,6 +1,7 @@
 NXFLAT
+
 
diff --git a/Documentation/NuttxPortingGuide.html b/Documentation/NuttxPortingGuide.html
index dedb90c32ce..7746ee3c5ce 100644
--- a/Documentation/NuttxPortingGuide.html
+++ b/Documentation/NuttxPortingGuide.html
@@ -2,22 +2,13 @@
 NuttX Porting Guide
+
 
-
-
                                                                                    
-
                                                                                    
   
                                                                                    
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
                                                                                    
-  
-    
-  
-
                                                                                    
-      
                                                                                    
-        NuttX RTOS Porting Guide
-      
                                                                                    
-      
                                                                                    Last Updated: February 18, 2019
                                                                                    
-    
                                                                                    
-
                                                                                    
+
 
+
                                                                                    
+
                                                                                    
 
                                                                                    
   
                                                                                    
     
@@ -238,6 +229,22 @@
   Appendix A: NuttX Configuration Settings
                                                                                    
   Appendix B:  Trademarks
 
+
+
+
                                                                                    
+
+
                                                                                    
+
+  
+    
+  
+
                                                                                    
+      
                                                                                    
+        NuttX RTOS Porting Guide
+      
                                                                                    
+      
                                                                                    Last Updated: May 25, 2019
                                                                                    
+    
                                                                                    
+
                                                                                    
 
 
@@ -481,7 +488,7 @@
 
 
                                                                                    
   Configuration Files.
-  The NuttX configuration consists of logic in processor architecture directories, chip/SoC directories, and board configuration directories.
+  The NuttX configuration consists of logic in processor architecture directories, chip/SoC directories, and board configuration directories.
   The complete configuration is specified by several settings in the NuttX configuration file.
 
                                                                                      
@@ -1773,7 +1780,7 @@ The specific environmental definitions are unique for each board but should incl
       This strict layering is enforced in the NuttX build system by controlling the compiler include paths:  Higher level code can never include header files from either; of the platform-specific source directories;  microcontroller-specific code can never include header files from the board-specific source directories.  The board-specific directories are, then, at the bottom of the layered hierarchy.
     
                                                                                      
     
                                                                                      
-      An exception to these inclusion restrictions is the platform-specific include/.  These are made available to higher level OS logic.  The microcontroller-specific include directory will be linked at include/arch/chip and, hence, can be included like #include <arch/chip/chip.h.
+      An exception to these inclusion restrictions is the platform-specific include/.  These are made available to higher level OS logic.  The microcontroller-specific include directory will be linked at include/arch/chip and, hence, can be included like #include <arch/hardware/chip.h.
       Similarly, the board-specific include directory will be linked at include/arch/board and, hence, can be included like #include <arch/board/board.h.
     
                                                                                      
     
                                                                                      
@@ -2176,10 +2183,6 @@ The specific environmental definitions are unique for each board but should incl
     handler now.
   
 
-
                                                                                      
-  This API is NOT required if CONFIG_DISABLE_SIGNALS
-  is defined.
-
                                                                                      
 
 
                                                                                      4.2.15 up_allocate_heap()
                                                                                      
 
                                                                                      Function Prototype: void up_allocate_heap(FAR void **heap_start, size_t *heap_size);
                                                                                      
@@ -5168,7 +5171,7 @@ void iob_dump(FAR const char *msg, FAR struct iob_s *iob, unsigned int len,
   
                                                                                    • 
     
                                                                                      
     Examples:
-    arch/arm/src/chip/lm_serial.c, arch/arm/src/lpc214x/lpc214x_serial.c, arch/z16/src/z16f/z16f_serial.c, etc.
+    arch/arm/src/stm32/stm32_serial.c, arch/arm/src/lpc214x/lpc214x_serial.c, arch/z16/src/z16f/z16f_serial.c, etc.
     
                                                                                      
   
                                                                                      • 
 
                                                                                    
@@ -5201,7 +5204,7 @@ void iob_dump(FAR const char *msg, FAR struct iob_s *iob, unsigned int len,
     The controller-specific, "upper half" touchscreen drivers reside in the directory drivers/input.
   
                                                                                  • "Lower Half" Drivers.
-    Platform-specific touchscreen drivers reside in either: (1) The arch/<architecture>/src/<chip> directory for the processor architectures that have build in touchscreen controllers or (2) the configs/<board>/src/ directory for boards that use an external touchscreen controller chip.
+    Platform-specific touchscreen drivers reside in either: (1) The arch/<architecture>/src/<hardware> directory for the processor architectures that have build in touchscreen controllers or (2) the configs/<board>/src/ directory for boards that use an external touchscreen controller chip.
   
                                                                                    • 
 
@@ -5226,7 +5229,7 @@ void iob_dump(FAR const char *msg, FAR struct iob_s *iob, unsigned int len,
     Common analog logic and share-able analog drivers reside in the drivers/analog/.
   
                                                                                  • 
-    Platform-specific drivers reside in arch/<architecture>/src/<chip> directory for the specific processor <architecture> and for the specific <chip> analog peripheral devices.
+    Platform-specific drivers reside in arch/<architecture>/src/<hardware> directory for the specific processor <architecture> and for the specific <chip> analog peripheral devices.
   
                                                                                    • 
 
@@ -5312,7 +5315,7 @@ void iob_dump(FAR const char *msg, FAR struct iob_s *iob, unsigned int len,
     The generic, "upper half" PWM driver resides at drivers/pwm.c.
   
                                                                                  • "Lower Half" Drivers.
-    Platform-specific PWM drivers reside in arch/<architecture>/src/<chip> directory for the specific processor <architecture> and for the specific <chip> PWM peripheral devices.
+    Platform-specific PWM drivers reside in arch/<architecture>/src/<hardware> directory for the specific processor <architecture> and for the specific <chip> PWM peripheral devices.
   
                                                                                    • 
 
@@ -5343,7 +5346,7 @@ void iob_dump(FAR const char *msg, FAR struct iob_s *iob, unsigned int len,
     The generic, "upper half" CAN driver resides at drivers/can.c.
   
                                                                                  • "Lower Half" Drivers.
-    Platform-specific CAN drivers reside in arch/<architecture>/src/<chip> directory for the specific processor <architecture> and for the specific <chip> CAN peripheral devices.
+    Platform-specific CAN drivers reside in arch/<architecture>/src/<hardware> directory for the specific processor <architecture> and for the specific <chip> CAN peripheral devices.
   
                                                                                    • 
@@ -5411,7 +5414,7 @@ for (i = 0; i <= nread - CAN_MSGLEN(0); i += msglen)
     The generic, "upper half" Quadrature Encoder driver resides at drivers/sensors/qencoder.c.
   
   
                                                                                  • "Lower Half" Drivers.
-    Platform-specific Quadrature Encoder drivers reside in arch/<architecture>/src/<chip> directory for the specific processor <architecture> and for the specific <chip> Quadrature Encoder peripheral devices.
+    Platform-specific Quadrature Encoder drivers reside in arch/<architecture>/src/<hardware> directory for the specific processor <architecture> and for the specific <chip> Quadrature Encoder peripheral devices.
   
                                                                                    • 
 
@@ -5440,7 +5443,7 @@ for (i = 0; i <= nread - CAN_MSGLEN(0); i += msglen)
     The generic, "upper half" timer driver resides at drivers/timers/timer.c.
   
                                                                                  • "Lower Half" Drivers.
-    Platform-specific timer drivers reside in arch/<architecture>/src/<chip> directory for the specific processor <architecture> and for the specific <chip> timer peripheral devices.
+    Platform-specific timer drivers reside in arch/<architecture>/src/<hardware> directory for the specific processor <architecture> and for the specific <chip> timer peripheral devices.
   
                                                                                    • 
 
@@ -5469,7 +5472,7 @@ for (i = 0; i <= nread - CAN_MSGLEN(0); i += msglen)
     The generic, "upper half" RTC driver resides at drivers/timers/rtc.c.
   
                                                                                  • "Lower Half" Drivers.
-    Platform-specific RTC drivers reside in arch/<architecture>/src/<chip> directory for the specific processor <architecture> and for the specific <chip> RTC peripheral devices.
+    Platform-specific RTC drivers reside in arch/<architecture>/src/<hardware> directory for the specific processor <architecture> and for the specific <chip> RTC peripheral devices.
   
                                                                                    • 
 
@@ -5498,7 +5501,7 @@ for (i = 0; i <= nread - CAN_MSGLEN(0); i += msglen)
     The generic, "upper half" watchdog timer driver resides at drivers/timers/watchdog.c.
   
                                                                                  • "Lower Half" Drivers.
-    Platform-specific watchdog timer drivers reside in arch/<architecture>/src/<chip> directory for the specific processor <architecture> and for the specific <chip> watchdog timer peripheral devices.
+    Platform-specific watchdog timer drivers reside in arch/<architecture>/src/<hardware> directory for the specific processor <architecture> and for the specific <chip> watchdog timer peripheral devices.
   
                                                                                    • 
 
@@ -6470,7 +6473,7 @@ int kbd_decode(FAR struct lib_instream_s *stream, FAR struct kbd_getstate_s *sta
 
                                                                                       #include <syslog.h>
 int syslog(int priority, FAR const IPTR char *format, ...);
-int vsyslog(int priority, FAR const IPTR char *src, va_list ap);
+void vsyslog(int priority, FAR const IPTR char *src, va_list ap);
 
                                                                                    Description:
   syslog() generates a log message. The priority argument is formed by  ORing the facility and the level values (see include/syslog.h). The remaining arguments are a format, as in printf() and any arguments to the format.
@@ -7301,6 +7304,9 @@ void (*notify)(FAR struct pm_callback_s *cb, int domain, enum pm_state_e pmstate
   standard as a development guideline only.
 
                                                                                    
 
+
+
+
 
 
diff --git a/Documentation/NuttxUserGuide.html b/Documentation/NuttxUserGuide.html
index e6bab2cf571..2b0167d0e75 100644
--- a/Documentation/NuttxUserGuide.html
+++ b/Documentation/NuttxUserGuide.html
@@ -3,6 +3,7 @@
 NuttX Users Manual
+
@@ -1476,9 +1477,8 @@ int posix_spawnattr_getschedpolicy(FAR const posix_spawnattr_t *attr, FAR int *p
 
                                                                                       #include <spawn.h>
-#ifndef CONFIG_DISABLE_SIGNALS
+
 int posix_spawnattr_getsigmask(FAR const posix_spawnattr_t *attr, FAR sigset_t *sigmask);
-#endif
 
                                                                                    
   Description:
@@ -1598,9 +1598,8 @@ int posix_spawnattr_setschedpolicy(FAR posix_spawnattr_t *attr, int policy);
 
                                                                                       #include <spawn.h>
-#ifndef CONFIG_DISABLE_SIGNALS
+
 int posix_spawnattr_setsigmask(FAR posix_spawnattr_t *attr, FAR const sigset_t *sigmask);
-#endif
 
                                                                                    
   Description:
@@ -8618,14 +8617,7 @@ interface of the same name.
 
                                                                                    
   Configuration Settings.
-  In order to use the poll() API, the following must be defined
-  in your NuttX configuration file:
-
                                                                                    
-
                                                                                      
-  
                                                                                    • CONFIG_DISABLE_POLL NOT defined
                                                                                      • 
-
                                                                                    
-
                                                                                    
-  In order to use the select with TCP/IP sockets test, you must also have the following additional things
+  In order to use the select with TCP/IP sockets test, you must have the following things
   selected in your NuttX configuration file:
 
                                                                                      
diff --git a/Documentation/NxWidgets.html b/Documentation/NxWidgets.html
index 24f4a4a4b88..63765a328bc 100644
--- a/Documentation/NxWidgets.html
+++ b/Documentation/NxWidgets.html
@@ -1,6 +1,7 @@
 
 
 NxWidgets
+
 
 
 
                                                                                      
diff --git a/Documentation/README.html b/Documentation/README.html
index c27aaab74a7..094a883ce9e 100644
--- a/Documentation/README.html
+++ b/Documentation/README.html
@@ -8,7 +8,7 @@
   
                                                                                    
   
                                                                                    
 
   
 
   
 
   
 
   
 
 
 
   
 
   
 
   
 
 
 
 
 
 
 
 
   
 
   
 
 
 
                                                                                    
     
       
                                                                                    NuttX README Files
                                                                                    
-      
                                                                                    Last Updated: March 13, 2019
                                                                                    
+      
                                                                                    Last Updated: June 4, 2019
                                                                                    
                                                                                         		
   
                                                                                    
 
                                                                                    
@@ -29,9 +29,13 @@ nuttx/
  |- arch/
  |   |
  |   |- arm/
- |   |   |- src
- |   |      |- lpc214x/README.txt
- |   |      `- stm32l4/README.txt
+ |   |   `- src
+ |   |       |- common
+ |   |       |   `- README_lwl_console.txt
+ |   |       |- lpc214x
+ |   |       |   `- README.txt
+ |   |       `- stm32l4
+ |   |           `- stm32l4/README.txt
  |   |- renesas/
  |   |   |- include/
  |   |   |   `-README.txt
@@ -63,6 +67,8 @@ nuttx/
  |   |   `- README.txt
  |   |- avr32dev1/
  |   |   `- README.txt
+ |   |- axoloti/
+ |   |   `- README.txt
  |   |- b-l475e-iot01a/
  |   |   `- README.txt
  |   |- bambino-200e/
@@ -153,6 +159,8 @@ nuttx/
  |   |   `- README.txt
  |   |- lpcxpresso-lpc54628/
  |   |   `- README.txt
+ |   |- makerlisp/
+ |   |   `- README.txt\
  |   |- maple/
  |   |   `- README.txt\
  |   |- max32660-evsys/
@@ -286,6 +294,8 @@ nuttx/
  |   |   `- README.txt
  |   |- skp16c26/
  |   |   `- README.txt
+ |   |- spresense/
+ |   |   `- README.txt
  |   |- stm3210e-eval/
  |   |   |- RIDE/README.txt
  |   |   `- README.txt
diff --git a/Documentation/UsbTrace.html b/Documentation/UsbTrace.html
index 4794d524dff..2b26986e7f9 100644
--- a/Documentation/UsbTrace.html
+++ b/Documentation/UsbTrace.html
@@ -1,6 +1,7 @@
 
 
 NuttX USB Trace Capability
+
 
 
 
diff --git a/Documentation/style.css b/Documentation/style.css
new file mode 100644
index 00000000000..70ee0ed10f5
--- /dev/null
+++ b/Documentation/style.css
@@ -0,0 +1,84 @@
+body
+{
+    background: none;
+    font-family: sans-serif;
+    height: 100%;
+}
+
+a
+{
+    color: #dd2f2f;
+    text-decoration: none;
+}
+
+a:hover
+{
+    text-decoration: underline;
+}
+
+code
+{
+    font-family: "Bitstream Vera Sans Mono";
+    color: #2b4893;
+    background: #f4f4f4;
+    padding-left: 0.25em;
+    padding-right: 0.25em;
+}
+
+pre
+{
+    font-family: "Bitstream Vera Sans Mono";
+    background: #f4f4f4;
+    padding: 1em;
+}
+
+.container
+{
+  overflow-x: hidden;
+}
+
+.toc
+{
+    top: 0;
+    left: 0;
+    float: left;
+    width: 22%;
+    font-size: 80%;
+    overflow-y: scroll;
+    height: 100%;
+    position: fixed;
+}
+
+.toc tbody
+{
+    font-size: 80%;
+}
+
+.toc .toc_table
+{
+    margin-left: 1em;
+}
+
+.toc  ul
+{
+    padding-left: 1.5em;
+}
+
+.toc > ul
+{
+    padding-left: 1.0em;
+}
+
+.toc h1
+{
+    padding-left: 0.5em;
+    padding-top: 0.5em;
+}
+
+.main
+{
+    padding-left: 1em;
+    padding-right: 1em;
+    width: 75%;
+    float: right;
+}
diff --git a/README.txt b/README.txt
index 57263368aac..d4e4acb15e8 100644
--- a/README.txt
+++ b/README.txt
@@ -1707,8 +1707,12 @@ nuttx/
  |   |
  |   |- arm/
  |   |   `- src
- |   |       |- lpc214x/README.txt
- |   |       `- stm32l4/README.txt
+ |   |       |- common
+ |   |       |   `- README_lwl_console.txt
+ |   |       |- lpc214x
+ |   |       |    `-README.txt
+ |   |       `- stm32l4
+ |   |           `- README.txt
  |   |- renesas/
  |   |   |- include/
  |   |   |   `-README.txt
@@ -1738,6 +1742,8 @@ nuttx/
  |   |   `- README.txt
  |   |- avr32dev1/
  |   |   `- README.txt
+ |   |- axoloti/
+ |   |   `- README.txt
  |   |- b-l475e-iot01a/
  |   |   `- README.txt
  |   |- bambino-200e/
@@ -1827,6 +1833,8 @@ nuttx/
  |   |   `- README.txt
  |   |- lpcxpresso-lpc54628/
  |   |   `- README.txt
+ |   |- makerlisp/
+ |   |   `- README.txt
  |   |- maple/
  |   |   `- README.txt
  |   |- max32660-evsys/
@@ -1959,6 +1967,8 @@ nuttx/
  |   |   `- README.txt
  |   |- skp16c26/
  |   |   `- README.txt
+ |   |- spresense/
+ |   |   `- README.txt
  |   |- stm3210e-eval/
  |   |   |- RIDE/README.txt
  |   |   `- README.txt
diff --git a/ReleaseNotes b/ReleaseNotes
index 15f94603192..119f1dfd2b2 100644
--- a/ReleaseNotes
+++ b/ReleaseNotes
@@ -11321,7 +11321,7 @@ Additional new features and extended functionality:
         Mateusz Szafoni.
       - Nucleo-144: Added USB OTG device to Nucleo-144.  From David Sidrane.
       - Nucleo-144: Added bbsram test to Nucleo-144.  From David Sidrane.
-      - STM32F4 Disovery: add CAN support for STM32F4 Discovery.  From
+      - STM32F4 Disovery:  Add CAN support for STM32F4 Discovery.  From
         Matthias Renner.
       - STM32F4 Disovery:  added a canard configuration files.  From
         Matthias Renner.
@@ -12253,7 +12253,7 @@ detailed bugfix information):
         dirlinks target only sets up the directory links but does not try
         to run all of the context setup; the compiler is never invoked; no
         code is autogenerated and things work.
-      - CXXFLAGS: add -fcheck-new whenever -fno-exceptions is used. From
+      - CXXFLAGS:  Add -fcheck-new whenever -fno-exceptions is used. From
         Beat Kng.
 
     * Tools
@@ -12798,7 +12798,7 @@ detailed bugfix information):
       - ARMv7-R:  Remove the redundant update on SCTLR. mpu_control() is
         invoking cp15_wrsctlr() around SCTLR update redundantly.  From Heesub
         Shin.
-      - ARMv7-R: add new Kconfig entries for d/i-cache. Unlike in ARMv7-A/M,
+      - ARMv7-R:  Add new Kconfig entries for D/I-cache. Unlike in ARMv7-A/M,
         Kconfig entries for data and instruction caches are currently missing
         in ARMv7-R. This change adds those missing Kconfig entries. Actual
         implmenetation for those functions will be added in the subsequent
@@ -13247,7 +13247,7 @@ Additional new features and extended functionality:
       - Olimex STM32 P407: Add a NSH protected build configuration; Enable
         procfs/ in all configurations.
       - Olimex STM32 P407: Add support for on-board microSD slot.
-      - STM32F429i Discovery: add support for the L3GD20 driver.  From
+      - STM32F429i Discovery:  Add support for the L3GD20 driver.  From
         raiden00.
       - STM32F103 Minimum: Add support to QEncoder on STM32F103 Minimum
         board.   From Alan Carvalho de Assis.
@@ -14679,7 +14679,7 @@ Additional new features and extended functionality:
         dynamic configuration.  From Frank Benkert.
       - Franks' change remained on a branch until all issues were resolved.
         the current version in Master is complete and ready for use.
-      - power:  battery_charger: add ioctl for charging input current.  From
+      - power:  battery_charger:  Add ioctl for charging input current.  From
         Juha Niskanen.
       - SMPS driver:  Add generic upper-half driver for SMPS.  From Mateusz
         Szafoni.
@@ -14695,7 +14695,7 @@ Additional new features and extended functionality:
       - HC-SR04 Driver:  Add support to HC-SR04 distance sensor.  From Alan
         Carvalho de Assis.
       - COMP Driver:  Add poll support.  From Pekka Ervasti.
-      - BQ2429X Driver: add driver for TI BQ2429X battery charger.  From Juha
+      - BQ2429X Driver:  Add driver for TI BQ2429X battery charger.  From Juha
         Niskanen.
       - ADC Driver:  Add poll support.  From Juha Niskanen.
       - BCH Driver:  Add poll support.  From Jussi Kivilinna.
@@ -14901,7 +14901,7 @@ Additional new features and extended functionality:
       - B-L475E-IOT01A: Add support for the SPSRGF/Spirit1 radio module.  Add
         a configuration for testing sprit radio.
       - B-L475E-IOT01A:  Add configurations to support a star topology.
-      - B-L475E-IOT01A: add basic support for external Macronix QuadSPI flash
+      - B-L475E-IOT01A:  Add basic support for external Macronix QuadSPI flash
         memory.  From Simon Piriou.
       - B-L475E-IOT01A:  Enable UDP broadcast test in the spirit-starhub
         configuration.
@@ -15024,7 +15024,7 @@ Additional new features and extended functionality:
       - examples/pf_ieee802154:  Add for testing PF_IEEE802154 sockets.  Add
         PANID to command line options; Cannot bind to address zero... There is
         no counterpart to INADDR_ANY for these radios (not now at least).
-      - examples/dac: add DAC example.  From Juha Niskanen.
+      - examples/dac:  Add DAC example.  From Juha Niskanen.
 
     * Network Utilities: apps/netutils:
 
@@ -16134,7 +16134,7 @@ Additional new features and extended functionality:
       - apps/examples/obd2:  Add OBD2 example application.  From Alan
         Carvalho de Assis.
       - apps/examples/userfs:  Add a test case for verifying UserFS.
-      - apps/examples/smps: add SMPS driver example.  From Mateusz Szafoni.
+      - apps/examples/smps:  Add SMPS driver example.  From Mateusz Szafoni.
       - apps/examples/pdcurses:  Bring in pdcurses demos and make them
         conform to the NuttX coding style.
       - apps/examples/pdcurses:  Add a very simple example that just shows
@@ -19122,7 +19122,7 @@ Additional new features and extended functionality:
 
     * Test Utilities:  apps/testing:
 
-    - testing/unity: add Unity - unit testing library from
+    - testing/unity:  Add Unity - unit testing library from
         ThrowTheSwitch.org. From Mateusz Szafoni.
 
 Bugfixes.  Only the most critical bugfixes are listed here (see the
@@ -22881,3 +22881,613 @@ detailed bugfix information):
 
       - apps/tools/mksymtab.sh:  'export LC_ALL=C' to get the traditional
         sort order  From anchao.
+
+NuttX-7.30 Release Notes
+------------------------
+
+The 130th release of NuttX, Version 7.30, was made on May 19, 2019,
+and is available for download from the Bitbucket.org website.  Note
+that release consists of two tarballs:  nuttx-7.30.tar.gz and
+apps-7.30.tar.gz.  These are available from:
+
+    https://bitbucket.org/nuttx/nuttx/downloads
+    https://bitbucket.org/nuttx/apps/downloads
+
+Both may be needed (see the top-level nuttx/README.txt file for build
+information).
+
+Additional new features and extended functionality:
+
+    * Core OS:
+
+      - pthreads:  Added non-standard pthread_get_stackaddr_np() and
+        pthread_get_stacksize_np().  From Joao Matos.
+      - boardctl():  Add a command to start the VNC server.  From Gregory
+        Nutt.
+      - Signals:  Remove references to CONFIG_DISABLE_SIGNALS in many
+        files.  Signals can no longer be disabled.  From Gregory Nutt.
+
+    * Wireless/Wireless Drivers:
+
+      - NRF24L01:  Add support for "multicast" TX mode - no waiting for ACK
+        (needs to be enabled with fcntl SETTXPAYLOADNOACK)  From Leif Jakob.
+
+    * Graphics/Display Drivers:
+
+      - NX Graphics:  Add new server->client callback to notify the window
+        client of server events. Remove the old 'blocked' callback and just
+        make it one case of an 'event' callback.  From Gregory Nutt.
+      - NX Graphics:  Implement new interfaces nx_synch() and nxtk_synch().
+        This are used to synchronize the NX server with the window client.
+        Currently most of the logic is equivalent to nx_block() and
+        nxtk_block(), but with slightly different semantics.  They are
+        separate now because they are likely to diverge in the future.
+        From Gregory Nutt.
+      - NX Graphics:  Add support for modal windows.  From Gregory Nutt.
+      - NX Graphics:  Implement a software cursor.  The cursor behaves
+        like a "sprite", always at the top of the display with a
+        transparent background.  Includes new NX interfaces to show/hide
+        the cursor, set the cursor image, and to move the cursor position.
+        From Gregory Nutt.
+      - NX Graphics:  Added support for hiding windows. This features is
+        needed by Twm4Nx:  When a window is iconified, the icon should
+        appear on the background and the window should disappear (i.e., be
+        hidden).  The windows needs to remain healthy and to be updated in
+        all ways, but it cannot affect the display content.  Conversely,
+        when the icon is clicked, the icon needs to be hidden on the
+        background and the window needs to be restored in its current
+        state (which may be different than the state of the window at the
+        time it was iconified.  From Gregory Nutt.
+      - NX Graphics:  Windows can now be created in the hidden state.
+        This can be used to clean up initial window presentation which may
+        involve several steps.  This makes those steps all invisible until
+        nx[tk]_setvisibility() is called to make the windows visible.
+        From Gregory Nutt.
+      - NX Graphics:  Add new NX interfaces to query if a window is hidden
+        or not.  From Gregory Nutt.
+      - NxTerm IOCTLs:  Replace specific interfaces between boardctl and
+        nxterm with a generalized IOCTL interface.  From Gregory Nutt.
+      - NxTerm:  Add a new IOCTL that can be used to inform NxTerm that
+        the size of a window has changed.  From Gregory Nutt.
+
+    * Other Common Device Drivers:
+
+      - CAN Upper Half:  Support multiple readers of the same port  From
+        Valmantas Paliksa.
+      - MAX7456:  Adds a read-only (for now) /dev/osd0/CM interface for
+        obtaining the chip's onboard NVM character map data.  Use seek()
+        to position the cursor over a desired subset of bytes, or request
+        a large read to obtain the entire EEPROM memory contents.  Values
+        are returned in binary form. Use hexdump, etc. to format them for
+        viewing.  From Bill Gatliff.
+      - Serial Upper Half:  The upper half serial driver configuration
+        CONFIG_SERIAL_DMA used to enable DMA on both RX and TX streams.
+        This was replaced with CONFIG_SERIAL_RXDMA and CONFIG_SERIAKL_TXDMA
+        which will permit supporting DMA on only one or both streams.
+        From Gregory Nutt.
+      - FUSB303:  Add FUSB303 driver  From Juha Niskanen.
+
+    * Microchip PIC32MZ Drivers:
+
+      - PIC32MZ GPIO:  Adds support for edge detect mode.  Slew Rate was
+        also added for completeness.  From Abdelatif Guettouche.
+
+    * Microchip/Atmel SAMv7 Boards
+
+      - SAME70-xplained:  Add a configuration for test Twm4Nx using VNC.
+        From Gregory Nutt.
+
+    * Microchip LPCxx Drivers:
+
+      - LPC17xx Ethernet:  Added support for KSZ8081RNA PHY to LPC17xx
+        Ethernet driver.  From jjlange.
+      - LPC17xx Ethernet:  Added support for Ethernet PHY ioctl() on
+        LPC17xx.  From jjlange.
+
+    * NXP i.MX RT:
+
+      - .i.MXRT1020:  Gets imx1020 family support started. It is pretty
+        similar, but subtly different, to 1050/60 (less PLLs, less GPIO
+        banks, differently numbered ports etc. etc.).
+
+        Moved each of the imxrt family-specific files into its own
+        subdirectory to tidy things up a bit, and remove the vast majority
+        of ifdefs from the mainline code.
+
+        From Dave Marples.
+
+    * NXP LPC54xx Drivers
+
+      - LPC54xx USB FS Host:  Bring in the USB FS OHCI driver from LPC17.
+        This is a quick'n'dirty port from LPC17 that I hope finish
+        sometime later.  Currently, it is missing hardware clocking setup
+        and is not even hooked into the build system yet.  From Gregory
+        Nutt.
+
+    * NXP LPC54xx Boards
+
+      - LPCXpresso-LPC54628:  Add a Twm4Nx configuration.  From Gregory Nutt.
+
+    * Sony CXD56xx
+
+      - CXD56xx:  Add initial CXD56xx chip driver sources.  From Nobuto
+        Kobayashi.
+
+    * Sony CXD56xx Spresense Board
+
+      - Spresense:  Add Spresense board support.  This is not the full
+        Spresense BSP from Sony, only the barebones logic to present an
+        NSH console.  From Nobuto Kobayashi.
+
+    * STMicro STM32:
+
+      - STM32F7 Clocking: Add support for using the HSE in bypass mode,
+        configured by board.h  From Anthony Merlino.
+      - STM32F7 Clocking:  Added support for TICKLESS mode.  From Valmantas
+        Paliksa.
+      - STM32H7 Backup Domain:  Add backup domain control registers.  From
+        Jukka Laitinen.
+      - STM32H7 Clocking:  Set the STM32H7 default HSI pre-divider to 4.
+        The I2C driver currently assumes HSI clock to be 16MHz.  From Jukka
+        Laitinen.
+      - STM32H7 Memorymap.:  Add the STM32H7 SYSTEM_UID and DEBUGMCU_BASE
+        register definitions.  From Jukka Laitinen.
+      - STM32L071x:  Add support for STM32L071x.  From Mateusz Szafoni.
+
+    * STMicro STM32 Drivers:
+
+      - STM32 OTGHS Host:  Allow VBUS monitoring for the OTG_HS host
+        driver.  From Jason Harris.
+      - STM32F0/L0 ADC:  Initial ADC support for the STM32 M0  From Mateusz
+        Szafoni.
+      - STM32F0/LO I2C: Port STM32F7 I2C to STM32F0/L0,  From Mateusz Szafoni.
+      - STM32F1 FLASH:  As noted by Matias N, the FLASH base address used
+        was incorrect.  It was using the address of the FLASH data, not
+        the address of the FLASH registers.  From Gregory Nutt.
+      - STM32F3 I2C: Port STM32F7 I2C to STM32F3.  From Mateusz Szafoni.
+      - STM32F7 Ethernet.c:  Auto-generate Ethernet MAC address from
+        device unique ID.  From Valmantas Paliksa.
+      - STM32F7 FLASH:  Add flash block mapping support for progmem.  From
+        Valmantas Paliksa.
+      - STM32F7 FMC:  Updated stm32_fmc.h with more FMC definitions.  From
+        Joao Matos.
+      - STM32F7 GPIO:  Adds additional pin alternate function for SPI2.
+        From Anthony Merlino.
+      - STM32F7 PWM:  Ported the PWM from F4 to F7.  From Eduard Niesner.
+      - STM32F7 SDMMC: Support bypassing the input clock divider on the
+        SDMMC interface. This enables using the full clock speed provided
+        to the SDMMC interface with no dividing.  From Anthony Merlino.
+      - STM32F7 SPI:  Add SPI DMA threshold configuration.  From Valmantas
+        Paliksa.
+      - STM32F7 UID:  Add UID access.  From Valmantas Paliksa.
+      - STM32F7 USB:  USB High speed for STM32F7 series  From Ramtin Amin.
+      - STM32H7 Ethernet:  Add stm32h7 Ethernet driver.  This is the
+        initial push for the Ethernet driver.  The driver has been tested
+        to be working on a nucleo board.  This is still WIP, it doesn't
+        for example do MAC filtering on HW level, but just receives all
+        Ethernet packets.  From Jukka Laitinen.
+      - STM32H7 GPIO:  Add the GPIO_ETH_RMII_RXD1 pinmap definition for
+        STM32H7.  From Jukka Laitinen.
+      - STM32H7 SDMMC:  Add STM32H7 SDMMC driver.  It is mostly copied
+        from STM32F7, with modified register addresses and bits, and IDMA
+        dded.  This is still WIP; it only works with IDMA.  From Jukka
+        Laitinen.
+      - STM32H7 Timers:  Add timer devices driver for STM32H7.  This i
+        mostly a forklift from stm32f7 with some h7 specific
+        modifications.  From Jukka Laitinen.
+      - STM32L0 AES:  Add support for AES for L0.  From Mateusz Szafoni.
+      - STM32L0 RND:  Add support for RND.  From Mateusz Szafoni.
+      - STM32L0 HSI48:  Add support for HS148 for L0. Move HSI48 enable
+        from stm32_usbdev.c to stm32xx_rcc.c  From Mateusz Szafoni.
+      - STM32L4 USB FS Device:  Add USB FS device support.  From Juha
+        Niskanen.
+      - STM32L4 HSI48:  Port HSI48 from STM32F0/L0  From Juha Niskanen.
+      - STM32L4 CRS:  Port CRS from STM32F0/L0  From Juha Niskanen.
+
+    * STMicro STM32 Boards:
+
+      - B-L072Z-LRWAN1:  Add ADC example.  From Mateusz Szafoni.
+      - B-L072Z-LRWAN1:  Add nxlines_oled example (ssd1306).  Add support
+        for the I2C tool  From Mateusz Szafoni.
+      - Nucleo-144:  Added STM32_RCC_DCKCFGR2_DSISRC definition to board.h.
+        From Joao Matos.
+      - Nucleo-144:  Mount sysfs for ifconfig for f767-netnsh/defconfig.
+        Even if ifconfig is working to set IP, it will not work to display
+        NICs (without args)  From Phil Coval.
+      - Nucleo-144:  Add basic PWM support to nucleo-144 board.  More PWMs
+        and multi channels support may be investigated and added later.
+        Tested on Nucleo-F767ZI.  From Phil Coval.
+      - Nucleo-F303ZE:  Add nxlines_oled example (ssd1306)  From Mateusz
+        Szafoni.
+      - Nucleo-H743ZI:  Enable the FPU.  From Jason Harris.
+      - Nucleo-H743ZI:  Add support for I2C devices: ssd1306, pca9635,
+        i2ctools  From Mateusz Szafoni.
+      - Nucleo-H743ZI:  Add default clock configuration for SDMMC for
+        Nucleo-H743ZI's board.h.  From Jukka Laitinen.
+      - Nucleo-H743ZI:  Add the input clock frequency definitions in
+        board.h for all the drivers. Assumes internal clock source for
+        all the timers.  From Jukka Laitinen.
+      - STM32F4 Discovery:  Keep c++ global constructor symbols  From
+        Masayuki Ishikawa.
+      - Nucleo-L073RZ:  Add MFRC522 support  From Mateusz Szafoni.
+      - OmnibusF4:  Add boardctl() reset logic.  From Bill Gatliff.
+      - OmnibusF4:  Add board_ioctl() which is needed only if
+        CONFIG_BOARDCTL_IOCTL=y is selected;  Update NSH configuration
+        to enable board IOCTLs and DFU mode reset.  From Bill Gatliff.
+      - STM32L Discovery:  Add support for board_late_initialize(), Move
+        common initialization logic out of board_app_initialize() into new
+        file stm32_bringup.c  From Gregory Nutt.
+      - STM32F103-Minimum:  Add PROCFS automount support  From Alan
+        Carvalho de Assis.
+
+    * Libraries/Header Files:
+
+      - include/alloca.h:  Add alloca.h.  Included limited implementation
+        of alloc() that is only available for GCC versions 3 and above.
+        From Joao Matos.
+      - include/cxx/cstdlib:  Add std::random()  From Gregory Nutt.
+
+    * apps/ General:
+
+      - Many locations:  Remove references to CONFIG_DISABLE_SIGNALS.
+        Signals can no longer be disabled.  From Gregory Nutt.
+
+    * Examples/Tests: apps/examples:
+
+      - apps/examples/fb:  Add some awareness of overlays to
+        apps/examples/fb  From Matthew Koch.
+      - apps/examples/lvgldemo.  Update to Littlevgl 5.3.  From Matthew
+        Koch.
+      - apps/examples/pwfb:  Extend example to verify software cursors.
+        From Gregory Nutt.
+      - apps/examples/pwfb:  Add options to reduce the number of windows.
+        This is helpful during debug to reduce the complexity.  From
+        Gregory Nutt.
+
+    * Network Utilities: apps/netutils:
+
+      - apps/netutils/cjson:  Support for the current version of cJSON.
+        From Mateusz Szafoni.
+      - apps/netutils/libcurl4nx:  This is an initial commit libcurl4nx.
+        It is not complete yet, but I still wish to commit the unfinished
+        bits to describe the roadmap, and because it is already usable.  It
+        will be updated and fixed in the future weeks and months, certainly
+        including POST support and later, SSL.  From Sebastien Lorquet.
+      - apps/netutils/netinit.  This commit removes the private network
+        initialization logic from NSH and puts in a common location at
+        apps/netutils/netinit.  Now that netork initialization logic can be
+        used by applications that do not include NSH.  From Gregory Nutt.
+      - apps/netutils/netlib:  Add a  more flexible version of
+        netlib_parsehttpurl().  This one can parse any URL, and is
+        extensible so future improvements keep the same API.  From Sebastien
+        Lorquet.
+
+    * System Utilities: apps/system
+
+     - apps/system/spi:  I needed a small test tool for spi in the style of
+       the I2C tool, but I didn't see one so I've hacked one out of the I2C
+       tool source.  From Dave Marples.
+
+    * Graphics:  apps/graphics:
+
+      - apps/graphics/twm4nx.  This release introduces Twm4Nx.  Twm4Nx is a
+        "port" of TWM, Tab Window Manager (or Tom's Window Manager) version
+        1.0.10 to NuttX NX windows server.  No, a port is not the right
+        word.  It is are-design of TWM from the inside out to work with the
+        NuttX NX server and NXWidgets.  The name Twm4Nx reflects this
+        legacy.  But Twm4Nx is more a homage to TWM than a port of TWM.
+
+        The original TWM was based on X11 which provides a rich set of
+        features.  TWM provided titlebars, shaped windows, several forms of
+        icon management, user-defined macro functions, click-to-type and
+        pointer-driven keyboard focus, graphic contexts, and user-specified
+        key and pointer button bindings, etc.
+
+        Twm4Nx, on the other hand is based on the NuttX NX server which
+        provides comparatively minimal support.  Additional drawing support
+        comes from the NuttX NxWidgets library (which necessitated a
+        conversion to C++).
+
+        Twm4Nx is greatly stripped down and targeted on small embedded systems
+        with minimal resources.  For example, no assumption is made about the
+        availability of a file system; no .twmrc file is used.
+
+        The state of the "port" is available in
+        apps/graphics/twm4mx/README.txt.  To summarize:  The port is fully
+        functional but probably only at an alpha release level.  The only
+        missing critical feature is built-in touchscreen calibration.
+
+      - apps/graphics/littlevgl.  Update to Littlevgl 5.3.  From Matthew
+        Koch.
+      - apps/graphics/nxglyphs:  Put all NxWidgets and NxWM glyphs into a
+        common directory where they can eventually be shared. Decouple
+        from nxwidgets and nxwm so that they can be used elsewhere.
+        Creates include/graphics/nxglyphs.h  From Gregory Nutt.
+      - apps/graphics/nxglyphs:  Add some new cursor bitmap images.  From
+        Gregory Nutt.
+      - apps/graphics/nxglyphs:  Add mkcursor.c.  Will auto-generate
+        cursor image header file from Gimp C output.  From Gregory Nutt.
+      - apps/graphics/nxglyphs:  Add 16x16 cursor images.  30x30 are kind
+        of large on small displays.  From Gregory Nutt.
+      - apps/graphics/nxglyphs:  Add a new resize cursor image. From
+        Gregory Nutt.
+      - apps/graphics/nxwm:  Separate NxWidgets and NxWM into separate
+        directories.  Remove old, common NxWidgets directory.  From
+        Gregory Nutt.
+      - apps/graphics/nxwm:  Move the NxWM unit test main() to apps/nxwm.
+        It is no longer a unit test, but the main startup entry point for
+        NxWM.  From Gregory Nutt.
+      - apps/graphics/nxwidgets:  Update NX window clients so that they
+        use the new 'event' callback (vs. the obsoleted 'blocked' callback).
+        From Gregory Nutt.
+      - apps/graphics/nxwidgets:  Add a synchronize method to every window.
+        This is a wrapper arounc nx[tk]_sync and permits C++ applications
+        to synchronize with the NX server.  From Gregory Nutt.
+      - apps/graphics/nxwidgets:  Add support for modal windows.  From
+        Gregory Nutt.
+      - apps/graphics/nxwidgets:  Add cursor control methods to the
+        CNxServer class.  From Gregory Nutt.
+      - apps/graphics/nxwidgets:  Add a method to CButtonArray that will
+        allow us to dynamically resize the array (at the cost of losing all
+        button labels).  From Gregory Nutt.
+      - apps/graphics/nxwidgets:  Fix a possible deadlock condition when
+        waiting for window geometry data that will never come.  Fixed by
+        re-requesting geometry data if we don't already have it.  From
+        Gregory Nutt.
+      - apps/graphics/nxwidgets:  Add handshake to
+        CWidgetControl::getWindowHandle() to avoid returning a NULL
+        handle.  From Gregory Nutt.
+      - apps/graphics/nxwidgets:  CNxTkWindow, CNxWindow, CNxServer:  Add
+        support to create RAM backed windows.  From Gregory Nutt.
+      - apps/graphics/nxwidgets:  Add methods to all windows to query if a
+        window is visible or hidden.  From Gregory Nutt.
+
+Bugfixes.  Only the most critical bugfixes are listed here (see the
+ChangeLog for the complete list of bugfixes and for additional, more
+detailed bugfix information):
+
+    * Core OS:
+
+      - Clock Initialization:  A recent change broke Tickless mode for all
+        architectures.    The original change was intended to handle the
+        case where up_timer_gettime may not start from zero case.  The
+        side effect is that this changed to order of initialization of
+        clocking, breaking Tickless mode::  After this change the tickless
+        timer structures are used before they are initialized in
+        clock_inittime().  The commit has been reverted.
+      - pthread Stack Attribute:  Fixed pthread_attr_get/setstacksize
+        param type to size_t.  From Joao Matos.
+      - Signals:  The abnormal termination signal handler was just calling
+        exit() conditionally when, for example, Ctrl-C is sent to a task.
+        The abnormal termination handler must obey the rules of cancellation
+        points:  If cancelation is disabled, then the abnormal termination
+        logic must wait for cancelation to be re-enabled; If cancellation
+        is deferred then the abnormal termination logic may have to wait
+        for the victim task to enter or exit a cancellation point.  From
+        Gregory Nutt.
+      - Syscall: Added support for munmap() syscall.  From Joao Matos.
+      - Syscall: Fix a warning due to inconsistencies in return type in
+        syscall.csv.  From Gregory Nutt.
+      - Syscall:  Correct an error syscall.csv. Error occurred when
+        creating the munmap() proxy if CONFIG_FS_RAMMAP is not defined.
+        From Gregory Nutt.
+
+    * File System/Block and MTD Drivers:
+
+      - fs/littlefs/lfs.c:  Fix lfs_format bug.  In superblock disk root-
+        block assignment, the second must be root[1].  From YanLin Zhu.
+
+    * Networking/Network Drivers:
+
+      - getsockname():  Fix addrlen check in socket debug features.
+        Getsockname() checked erroneously a pointer agains 0, where the
+        intention was to dereference the pointer and to check the length.
+        This causes also a compilation failure if the code is compiled
+        with CONFIG_DEBUG_FEATURES and with -Werror flag set.  From Jukka
+        Laitinen.
+      - Network Locking:  net_lock() and net_restorelock() now return a
+        value.  That values is the standard zero on success; negated errn
+        value on failure.  This return value is only needed for
+        -ECANCELED.  That cancellation indication needs to ripple all the
+        way back to the highest levels where the cancellation can be acted
+        on.  This commit only adds the return value; it does not add
+        checking for the return values of net_lock() and net_restorelock()
+        at higher levels.  That is required too.  From Gregory Nutt.
+      - PHY Notification Driver:  Change sprintf to strncpy in phy_notify.
+        On some platforms, the sprintf doesn't accept a const char* as a
+        format argument.  From Jukka Laitinen.
+      - 6LoWPAN HC06:  Correct an endian-ness problem in HC06 decompression.
+        From Ivan Ucherdzhiev.
+
+    * Wireless/Wireless Drivers:
+
+      - NRF24L01:  Don't block in read if file descriptor is O_NONBLOCK.
+        From Leif Jakob.
+
+    * Graphics/Display Drivers:
+
+      - NX Graphics:  Fix an error in coordinate system usage.  Expected
+        rectangle in device coordinate frame, but was passing the
+        rectangle in window-relative coordinate frame.  From Gregory Nutt.
+      - NX Graphics:  Fix an oversight in the implementation of per-window
+        framebuffers.  It is true that redraw callbacks can be suppressed
+        for all cases ... EXCEPT ONE:  When the window is resized to a
+        larger size, then the newly exposed territory must be drawn for
+        the first time.  From Gregory Nutt.
+      - NxTK:  Fix an error in handling mouse events for framed windows.
+        When drawing, NX may report mouse positions outside of the Window.
+        The is only for NX windows, but the outside-the-side positions were
+        being discarded by nxtk_events().  From Gregory Nutt.
+      - NxTK:  Refuse to open a toolbar of height zero or less.  From
+        Gregory Nutt.
+      - Nxglib:  Correct bogus logic in nxgl_interesting().  From Gregory
+        Nutt.
+      - VNC Server:  Fix an error in color conversion.  From Gregory Nutt.
+
+    * Common Drivers:
+
+      - APDS9960:  Initial state of allocated structure was not being set.
+        Noted by Leif Jacob.  From Gregory Nutt.
+      - MFRC522:  In mfrc522_read uid.sak must be different from 0x04 not
+        as before from 0x00. SAK == 0x00 is a valid PICC type.  Add
+        interface to read MIFARE Ultralight data  From Mateusz Szafoni.
+      - Power:  Fix build for battery gauge  From Tom Kopriva.
+      - Syslog:  In syslog buffered mode, avoid IOB alloc lock-up with
+        heavy network activity.  This change alters the buffered syslog
+        logic to use 'iob_tryalloc' instead of blocking 'iob_alloc' to
+        avoid syslog printing from getting stuck when all IOBs are
+        depleted by network activity.  An issue was seen when large
+        incoming TCP transfer uses free IOB buffers and processing
+        threads try to use syslog which then block at iob_alloc.  From
+        Jussi Kivilinna.
+      - USB CDC/ACM Device:  This fixes a problem where the host sent a
+        "get descriptor" message of type "standard" with a recipient of
+        type "interface". Since the composite driver would only pass
+        messages to the child interfaces when a message was not
+        "standard", this message was not handled. I changed the condition
+        so that the composite driver checks not only if this is a
+        "standard" message but if it is also directed to the device.
+        Otherwise, the handling is delegated to the children of the
+        composite device.  From Matias N.
+      - USB HID:  The usbhid_descriptor_s struct defined in hid.h included
+        some optional fields that should not be hard-defined as part of
+        that structure.  An arbitrary number of optional entries could be
+        included in the descriptor, but that is not properly represented.
+        No code on NuttX currently depends on the structure definition
+        with an optional descriptor so it is safe to remove.  From Matias N.
+      - USB MSC Device:  Correct typo "const const" to "const".
+        arch/arm/src/stm32/stm32_i2s.c:  In debug assertions, it on a
+        sample rate of 0, but based on other code comments this value
+        implies disabling the i2s master clock.  From Jason Harris.
+      - Zerocross Driver:  Fix some errors when debug assertions are
+        enabled.  From Matous Pokorny.
+      - User Leds:  Fix ledset validity check in ULEDIOC_SETALL ioctl.
+        From Jussi Kivilinna.
+
+    * Architecture Common:
+
+      - All board interfaces (those starting with board_) must be defined
+        in board-specific logic.  Otherwise, they cannot be customized for
+        specialized usage by different boards.  The board_reset()
+        interface was defined in architecture-specific logic that only
+        called up_systemreset().  That is useless!  This change removes
+        the board_reset() implementation from the architecture-specific
+        code and re-implements it in the src/ directory of each board that
+        has CONFIG_BOARDCTL_RESET enabled.  That is the correct functional
+        partitioning.  From Gregory Nutt.
+      - Start-up:  Remove dependency on CONFIG_ARCH_FPU for inclusion of
+        nvic.h in all other *_start.c files.  From Gregory Nutt.
+      - Architecture initialization:  up_initialize() needs to know about
+        ramlog_consoleinit()  From Jason Harris.
+
+    * Microchip PIC32MZ Drivers:
+
+      - PIC32MZ GPIO:  Corrects the gpioirq when mismatch mode is
+        selected.  From Abdelatif Guettouche.
+
+    * ARMv7-A:
+
+      - ARMv7-A Build:  Fix 'cc1: warning: switch -mcpu=cortex-a7 conflicts
+        with -march=armv7-a switch'  From Xiang Xiao.
+
+    * Nordic NRFxx
+
+      - NRF52:  Fix compiler error in nrf52832_errdata.c when following
+        C89.  From Erik Englund.
+
+    * STMicro STM32:
+
+      - STM32 Configuration:  It seems one option in the timer configuration
+        was lost at some point.  From Matias N.
+      - STM32 start-up:  Inclusion of nvic.h should not be conditioned on
+        CONFIG_ARCH_FPU.  From Mateusz Szafoni.
+      - STM32H7 Clocking:  Fixes for STM32H7 RCC definitions.  From Jukka
+        Laitinen.
+
+    * STMicro STM32 Drivers:
+
+      - STM32F0/L USART:  A few fixes for USART.  From Mateusz Szafoni.
+      - STM32F1/F30 FLASH:  RCC register access should not be offset by
+        FLASH register base.  From Matias N.
+      - STM32F7 CAN:  CAN fixes.  From Valmantas Paliksa.
+      - STM32F7 I2C:  I2C Interrupt storm fix.  I2C track bad state.  Now
+        we track bad state and so the SW reset only when it occurs.  From
+        David Sidrane.
+      - STM32F7 OTG: Fixes some macros related to OTGFS/OTGHS preventing
+        OTGHS from working.  From Anthony Merlino.
+      - STM32F7 OTG Device:  Correct hard-coded FIFO size that is wrong
+        for OTG FS.  From Ramtin Amin.
+      - STM32F7 QSPI:  Fix QuadSPI interrupts.  This commit essentially
+        replaces wrongly named configuration variable STM32F7_QSPI_INTERRUPTS
+        into CONFIG_STM32F7_QSPI_INTERRUPTS.  Also fixes some getreg/
+        putreg where register addresses were used instead of register
+        offsets  From Pierre-Olivier Vauboin.
+      - STM32H7 I2C: Fix I2C4 compilation for STM32H7.  From Jukka
+        Laitinen.
+      - STM32H7 UART: Fix compilation for UART7, UART8 and I2C4s.  From
+        Jukka Laitinen.
+      - STM32L4 USB Device:  Add missing PWR USBV enable, correct two USB
+        register bits  From Juha Niskanen.
+
+    * STMicro STM32 Boards:
+
+      - STM32F103-Minimum:  USB reset was not working appropriately since
+        the pin connected to D+ was incorrectly defined and the pullup/down
+        logic was reversed.  From Matias N.
+      - Nucleo-l476RG:  Fix some errors in GPIO logic when debug assertions
+        are enabled.  From Matous Pokorny.
+      - Nucleo-L476RG:  Add missing files of BMP180 example for Nucleo-L476RG.
+        From Fabian Justi.
+      - STM32F103-Minimum GPIO:  Fix some errors when debug assertions are
+        enabled.  From Matous Pokorny.
+      - STM32L4 PWM:  Fix register addr, en_bit and resetbit for pwm timers.
+        From Fabian Justi.
+      - STM32F746G-DISCO: I2C1 config on stm32f746g-disco. Typo in
+        stm32f7/stm32_i2c.c  From Matthew Koch.
+
+    * C Library/Header Files:
+
+      - include/limits.h:  Remove the duplicate TMP_MAX definitions.  The
+        standard requires that TMP_MAX defines be in stdio.h.  From
+        Xiang Xiao.
+      - include/sys/select.h:  Fix compiler error when
+        CONFIG_NSOCKET_DESCRIPTORS is undefined.  From Xiang Xiao.
+      - include/signal.h:  Add commented out definition of the si_addr
+        field.  From Joao Matos.
+      - include/unistd.h:  Fixed R_OK/X_OK definitions to match POSIX.
+        From Joao Matos.
+
+      - libs/libc/locale: Improved error handling in setlocale().  From Joao
+        Matos.
+      - libs/libc: Fixed return code in uname().  From Joao Matos.
+      - libs/libc/stdio:  Restore support for printing NULL string as
+        "(null)".  Legacy printf supported printing "(null)" in place for
+        NULL string:  printf("null: %s\n", NULL); => null: (null).  This
+        commit restores this functionality for new printf library.  From
+        Jussi Kivilinna.
+
+    * Examples: apps/examples:
+
+      - apps/examples/pca9635/pca9635_main.c: fix compilation error. From
+        Mateusz Szafoni.
+
+    * Graphics Utilities: apps/graphics:
+
+      - Various graphics apps (and apps/examples):  If CONFIG_VNCSERVER=y,
+        don't call vnc_default_fbinitialize() directly.  That is a violation
+        of the portable POSIX interface.  Instead, call
+        boardctl(BOARDIOC_VNC_START);.  From Gregory Nutt.
+      - apps/graphics/nxwidgets:  CWidgetControl::handleLeftClick now
+        returns a value to indicate if the click was actually processed or
+        not. CWidgetControl::pollMouseEvents:  Correct return value.  From
+        Gregory Nutt.
+      - apps/graphics/nxwidgets/:  NXWidgets::CNxWidgets:  Fix some issues
+        with returned values.  On setting the widget size or position, it was
+        returning false if there was no change in size or position.  Many
+        places in the code were treating the false return value as an error.
+        From Gregory Nutt.
+
+    * System Utilities: apps/system:
+
+      - apps/system/nxplayer:  Fix some logical errors from recent commits.
+        They broke the build of the nxplayer as a library vs. a task.
diff --git a/TODO b/TODO
index b9a845141b2..67587d1ab78 100644
--- a/TODO
+++ b/TODO
@@ -1,4 +1,4 @@
-NuttX TODO List (Last updated March 18, 2019)
+NuttX TODO List (Last updated April 29, 2019)
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -31,7 +31,7 @@ nuttx/:
 
 apps/ and other Add-Ons:
 
-  (2)  Network Utilities (apps/netutils/)
+  (1)  Network Utilities (apps/netutils/)
   (1)  NuttShell (NSH) (apps/nshlib)
   (1)  System libraries apps/system (apps/system)
   (1)  Modbus (apps/modbus)
@@ -560,7 +560,7 @@ o SMP
                This would also be an essential part of a high priority,
                nested interrupt implementation (unrelated).
   Status:      Open
-  Priority:    Low.  There are no know issues with the current non-maskable
+  Priority:    Low.  There are no known issues with the current non-maskable
                SGI implementation.  This change would, however, lead to
                simplification in the design and permit commonality with
                other, non-GIC implementations.
@@ -2720,14 +2720,6 @@ o Network Utilities (apps/netutils/)
   Status:      Open
   Priority:    Medium
 
-  Title:       NETWORK MONITOR NOT GENERALLY AVAILABLE
-  Description: The NSH network management logic has general applicability
-               but is currently useful only because it is embedded in the NSH
-               module.  It should be moved to apps/system or, better,
-               apps/netutils.
-  Status:      Open
-  Priority:    Low
-
 o NuttShell (NSH) (apps/nshlib)
   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4342c2946c3..1a0e67c6881 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -317,6 +317,12 @@ config ARCH_CHIP_STM32L0
 	---help---
 		STMicro STM32L0 architectures (ARM Cortex-M0).
 
+config ARCH_CHIP_STM32G0
+	bool "STMicro STM32 G0"
+	select ARCH_CORTEXM0
+	---help---
+		STMicro STM32G0 architectures (ARM Cortex-M0).
+
 config ARCH_CHIP_STM32F7
 	bool "STMicro STM32 F7"
 	select ARCH_CORTEXM7
@@ -328,6 +334,8 @@ config ARCH_CHIP_STM32F7
 	select ARCH_HAVE_SPI_BITORDER
 	select ARM_HAVE_MPU_UNIFIED
 	select ARMV7M_HAVE_STACKCHECK
+	select ARCH_HAVE_TICKLESS
+	select ARCH_HAVE_TIMEKEEPING
 	---help---
 		STMicro STM32 architectures (ARM Cortex-M7).
 
@@ -400,6 +408,18 @@ config ARCH_CHIP_XMC4
 	---help---
 		Infineon XMC4xxx(ARM Cortex-M4) architectures
 
+config ARCH_CHIP_CXD56XX
+	bool "Sony CXD56xx"
+	select ARCH_CORTEXM4
+	select ARCH_HAVE_MPU
+	select ARM_HAVE_MPU_UNIFIED
+	select ARCH_HAVE_FPU
+	select ARCH_HAVE_HEAPCHECK
+	select ARCH_HAVE_MULTICPU
+	select ARCH_HAVE_SDIO if MMCSD
+	---help---
+		Sony CXD56XX (ARM Cortex-M4) architectures
+
 endchoice
 
 config ARCH_ARM7TDMI
@@ -663,13 +683,14 @@ config ARCH_CHIP
 	default "sam34"		if ARCH_CHIP_SAM34
 	default "samv7"		if ARCH_CHIP_SAMV7
 	default "stm32"		if ARCH_CHIP_STM32
-	default "stm32f0l0"	if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0
+	default "stm32f0l0g0"	if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0
 	default "stm32f7"	if ARCH_CHIP_STM32F7
 	default "stm32h7"	if ARCH_CHIP_STM32H7
 	default "stm32l4"	if ARCH_CHIP_STM32L4
 	default "str71x"	if ARCH_CHIP_STR71X
 	default "tms570"	if ARCH_CHIP_TMS570
 	default "xmc4"		if ARCH_CHIP_XMC4
+	default "cxd56xx"	if ARCH_CHIP_CXD56XX
 
 config ARCH_HAVE_TRUSTZONE
 	bool
@@ -792,6 +813,19 @@ config ARM_SEMIHOSTING_HOSTFS
 	---help---
 		Mount HostFS through semihosting.
 
+config ARM_LWL_CONSOLE
+	bool "Lightweight Link Console Support"
+	default n
+	depends on DEV_CONSOLE && ARCH_CHIP_STM32
+	---help---
+		Use the lightweight link console which provides console over a
+		debug channel by means of shared memory.  A terminal application
+		for openocd as the debugger is available in tools/ocdconsole.py.
+
+		Currently only available for STM32 architectures, but easily
+		added to other ARM architectures be addd up_low_console.c to the
+		architecture Make.defs file.
+
 if ARCH_CORTEXM0
 source arch/arm/src/armv6-m/Kconfig
 endif
@@ -894,8 +928,8 @@ endif
 if ARCH_CHIP_STM32
 source arch/arm/src/stm32/Kconfig
 endif
-if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0
-source arch/arm/src/stm32f0l0/Kconfig
+if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0
+source arch/arm/src/stm32f0l0g0/Kconfig
 endif
 if ARCH_CHIP_STM32F7
 source arch/arm/src/stm32f7/Kconfig
@@ -915,5 +949,8 @@ endif
 if ARCH_CHIP_XMC4
 source arch/arm/src/xmc4/Kconfig
 endif
+if ARCH_CHIP_CXD56XX
+source arch/arm/src/cxd56xx/Kconfig
+endif
 
 endif # ARCH_ARM
diff --git a/arch/arm/include/arm/irq.h b/arch/arm/include/arm/irq.h
index a369ad58882..a124c74e733 100644
--- a/arch/arm/include/arm/irq.h
+++ b/arch/arm/include/arm/irq.h
@@ -138,7 +138,6 @@
 #ifndef __ASSEMBLY__
 struct xcptcontext
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there
    * are pending signals to be processed.
    */
@@ -156,7 +155,6 @@ struct xcptcontext
 
   uint32_t saved_pc;
   uint32_t saved_cpsr;
-#endif
 
   /* Register save area */
 
diff --git a/arch/arm/include/armv6-m/irq.h b/arch/arm/include/armv6-m/irq.h
index 1ac545d1ded..338f24ada97 100644
--- a/arch/arm/include/armv6-m/irq.h
+++ b/arch/arm/include/armv6-m/irq.h
@@ -164,7 +164,6 @@ struct xcpt_syscall_s
 
 struct xcptcontext
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there
    * are pending signals to be processed.
    */
@@ -191,8 +190,6 @@ struct xcptcontext
    */
 
   uint32_t sigreturn;
-
-# endif
 #endif
 
 #ifdef CONFIG_LIB_SYSCALL
diff --git a/arch/arm/include/armv7-a/irq.h b/arch/arm/include/armv7-a/irq.h
index 837a1acb074..f0dc452006b 100644
--- a/arch/arm/include/armv7-a/irq.h
+++ b/arch/arm/include/armv7-a/irq.h
@@ -229,7 +229,6 @@ struct xcpt_syscall_s
 #ifndef __ASSEMBLY__
 struct xcptcontext
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there are pending signals
    * to be processed.
    */
@@ -247,14 +246,13 @@ struct xcptcontext
   uint32_t saved_pc;
   uint32_t saved_cpsr;
 
-# ifdef CONFIG_BUILD_KERNEL
+#ifdef CONFIG_BUILD_KERNEL
   /* This is the saved address to use when returning from a user-space
    * signal handler.
    */
 
   uint32_t sigreturn;
 
-# endif
 #endif
 
   /* Register save area */
@@ -302,11 +300,9 @@ struct xcptcontext
 
   FAR uint32_t *ustkptr;  /* Saved user stack pointer */
   FAR uint32_t *kstack;   /* Allocate base of the (aligned) kernel stack */
-#ifndef CONFIG_DISABLE_SIGNALS
   FAR uint32_t *kstkptr;  /* Saved kernel stack pointer */
 #endif
 #endif
-#endif
 };
 #endif
 
diff --git a/arch/arm/include/armv7-m/irq.h b/arch/arm/include/armv7-m/irq.h
index 6b07c94622c..53698d6e98f 100644
--- a/arch/arm/include/armv7-m/irq.h
+++ b/arch/arm/include/armv7-m/irq.h
@@ -119,7 +119,6 @@ struct xcpt_syscall_s
 
 struct xcptcontext
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there
    * are pending signals to be processed.
    */
@@ -151,7 +150,6 @@ struct xcptcontext
 
   uint32_t sigreturn;
 
-# endif
 #endif
 
 #ifdef CONFIG_LIB_SYSCALL
diff --git a/arch/arm/include/armv7-r/irq.h b/arch/arm/include/armv7-r/irq.h
index 3d9e739b1b6..0d80c0b7794 100644
--- a/arch/arm/include/armv7-r/irq.h
+++ b/arch/arm/include/armv7-r/irq.h
@@ -229,7 +229,6 @@ struct xcpt_syscall_s
 #ifndef __ASSEMBLY__
 struct xcptcontext
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there are pending signals
    * to be processed.
    */
@@ -247,14 +246,12 @@ struct xcptcontext
   uint32_t saved_pc;
   uint32_t saved_cpsr;
 
-# ifdef CONFIG_BUILD_KERNEL
+#ifdef CONFIG_BUILD_KERNEL
   /* This is the saved address to use when returning from a user-space
    * signal handler.
    */
 
   uint32_t sigreturn;
-
-# endif
 #endif
 
   /* Register save area */
@@ -302,11 +299,9 @@ struct xcptcontext
 
   FAR uint32_t *ustkptr;  /* Saved user stack pointer */
   FAR uint32_t *kstack;   /* Allocate base of the (aligned) kernel stack */
-#ifndef CONFIG_DISABLE_SIGNALS
   FAR uint32_t *kstkptr;  /* Saved kernel stack pointer */
 #endif
 #endif
-#endif
 };
 #endif
 
diff --git a/arch/arm/include/cxd56xx/chip.h b/arch/arm/include/cxd56xx/chip.h
new file mode 100644
index 00000000000..9a790817d2f
--- /dev/null
+++ b/arch/arm/include/cxd56xx/chip.h
@@ -0,0 +1,104 @@
+/*****************************************************************************
+ * arch/arm/include/cxd56xx/chip.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ *   Copyright (C) 2012-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_CXD56XX_CHIP_H
+#define __ARCH_ARM_INCLUDE_CXD56XX_CHIP_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CXD56M4_SYSH_PRIORITY_MIN     0xe0 /* All bits[7:5] set is minimum priority */
+#define CXD56M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define CXD56M4_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
+#define CXD56M4_SYSH_PRIORITY_STEP    0x20 /* Steps between priorities */
+
+#define NVIC_SYSH_PRIORITY_MIN        CXD56M4_SYSH_PRIORITY_MIN
+#define NVIC_SYSH_PRIORITY_DEFAULT    CXD56M4_SYSH_PRIORITY_DEFAULT
+#define NVIC_SYSH_PRIORITY_MAX        CXD56M4_SYSH_PRIORITY_MAX
+#define NVIC_SYSH_PRIORITY_STEP       CXD56M4_SYSH_PRIORITY_STEP
+
+/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
+ * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
+ * interrupts will not have execution priority.  SVCall must have execution
+ * priority in all cases.
+ *
+ * In the normal cases, interrupts are not nest-able and all interrupts run
+ * at an execution priority between NVIC_SYSH_PRIORITY_MIN and
+ * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
+ *
+ * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
+ * high priority interrupts are supported.  These are not "nested" in the
+ * normal sense of the word.  These high priority interrupts can interrupt
+ * normal processing but execute outside of OS (although they can "get back
+ * into the game" via a PendSV interrupt).
+ *
+ * In the normal course of things, interrupts must occasionally be disabled
+ * using the up_irq_save() inline function to prevent contention in use of
+ * resources that may be shared between interrupt level and non-interrupt
+ * level logic.  Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
+ * do we disable all interrupts (except SVCall), or do we only disable the
+ * "normal" interrupts.  Since the high priority interrupts cannot interact
+ * with the OS, you may want to permit the high priority interrupts even if
+ * interrupts are disabled.  The setting CONFIG_ARCH_INT_DISABLEALL can be
+ * used to select either behavior:
+ *
+ *   ----------------------------+--------------+----------------------------
+ *   CONFIG_ARCH_HIPRI_INTERRUPT |      NO      |             YES
+ *   ----------------------------+--------------+--------------+-------------
+ *   CONFIG_ARCH_INT_DISABLEALL  |     N/A      |     YES      |      NO
+ *   ----------------------------+--------------+--------------+-------------
+ *                               |              |              |    SVCall
+ *                               |    SVCall    |    SVCall    |    HIGH
+ *   Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
+ *                               |              |    MAXNORMAL |
+ *   ----------------------------+--------------+--------------+-------------
+ */
+
+#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
+#  define NVIC_SYSH_MAXNORMAL_PRIORITY  (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
+#  define NVIC_SYSH_HIGH_PRIORITY       (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
+#  define NVIC_SYSH_DISABLE_PRIORITY    NVIC_SYSH_HIGH_PRIORITY
+#  define NVIC_SYSH_SVCALL_PRIORITY     NVIC_SYSH_PRIORITY_MAX
+#else
+#  define NVIC_SYSH_MAXNORMAL_PRIORITY  (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
+#  define NVIC_SYSH_HIGH_PRIORITY       NVIC_SYSH_PRIORITY_MAX
+#  define NVIC_SYSH_DISABLE_PRIORITY    NVIC_SYSH_MAXNORMAL_PRIORITY
+#  define NVIC_SYSH_SVCALL_PRIORITY     NVIC_SYSH_PRIORITY_MAX
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_CXD56XX_CHIP_H */
diff --git a/arch/arm/include/cxd56xx/irq.h b/arch/arm/include/cxd56xx/irq.h
new file mode 100644
index 00000000000..7b20667d800
--- /dev/null
+++ b/arch/arm/include/cxd56xx/irq.h
@@ -0,0 +1,272 @@
+/****************************************************************************
+ * arch/arm/include/cxd56xx/irq.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_CXD56XX_IRQ_H
+#define __ARCH_ARM_INCLUDE_CXD56XX_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#  include 
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC. This does, however, waste several words of
+ * memory in the IRQ to handle mapping tables.
+ */
+
+/* Processor Exceptions (vectors 0-15) */
+
+#define CXD56_IRQ_RESERVED       (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+                                     /* Vector  0: Reset stack pointer value */
+                                     /* Vector  1: Reset (not handler as an IRQ) */
+#define CXD56_IRQ_NMI            (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
+#define CXD56_IRQ_HARDFAULT      (3) /* Vector  3: Hard fault */
+#define CXD56_IRQ_MEMFAULT       (4) /* Vector  4: Memory management (MPU) */
+#define CXD56_IRQ_BUSFAULT       (5) /* Vector  5: Bus fault */
+#define CXD56_IRQ_USAGEFAULT     (6) /* Vector  6: Usage fault */
+#define CXD56_IRQ_SIGNVALUE      (7) /* Vector  7: Sign value */
+#define CXD56_IRQ_SVCALL        (11) /* Vector 11: SVC call */
+#define CXD56_IRQ_DBGMONITOR    (12) /* Vector 12: Debug Monitor */
+                                     /* Vector 13: Reserved */
+#define CXD56_IRQ_PENDSV        (14) /* Vector 14: Pendable system service request */
+#define CXD56_IRQ_SYSTICK       (15) /* Vector 15: System tick */
+#define CXD56_IRQ_EXTINT        (16) /* Vector 16: Vector number of the first external interrupt */
+
+/* Cortex-M4 External interrupts (vectors >= 16) */
+
+#define CXD56_IRQ_PMU           (CXD56_IRQ_EXTINT+0)  /**< PMU IRQ number */
+#define CXD56_IRQ_CRG           (CXD56_IRQ_EXTINT+1)  /**< CRG IRQ number */
+#define CXD56_IRQ_HVDD          (CXD56_IRQ_EXTINT+2)  /**< HVDD IRQ number */
+#define CXD56_IRQ_LP            (CXD56_IRQ_EXTINT+3)  /**< LP IRQ number */
+#define CXD56_IRQ_RTC0_A0       (CXD56_IRQ_EXTINT+4)  /**< RTC0_A0 IRQ number */
+#define CXD56_IRQ_RTC0_A1       (CXD56_IRQ_EXTINT+5)  /**< RTC0_A1 IRQ number */
+#define CXD56_IRQ_RTC0_A2       (CXD56_IRQ_EXTINT+6)  /**< RTC0_A2 IRQ number */
+#define CXD56_IRQ_RTC1_A0       (CXD56_IRQ_EXTINT+7)  /**< RTC1_A0 IRQ number */
+#define CXD56_IRQ_RTC1_A1       (CXD56_IRQ_EXTINT+8)  /**< RTC1_A1 IRQ number */
+#define CXD56_IRQ_RTC1_A2       (CXD56_IRQ_EXTINT+9)  /**< RTC1_A2 IRQ number */
+#define CXD56_IRQ_RTC_INT       (CXD56_IRQ_EXTINT+10) /**< RTC_INT IRQ number */
+#define CXD56_IRQ_UART1         (CXD56_IRQ_EXTINT+11) /**< UART1 IRQ number */
+#define CXD56_IRQ_UART0         (CXD56_IRQ_EXTINT+12) /**< UART0 IRQ number */
+#define CXD56_IRQ_HOSTIF_0      (CXD56_IRQ_EXTINT+13) /**< HOSTIF_0 IRQ number */
+#define CXD56_IRQ_HOSTIF_1      (CXD56_IRQ_EXTINT+14) /**< HOSTIF_1 IRQ number */
+#define CXD56_IRQ_HOSTIF_2      (CXD56_IRQ_EXTINT+15) /**< HOSTIF_2 IRQ number */
+#define CXD56_IRQ_SCU_SPI       (CXD56_IRQ_EXTINT+16) /**< SCU_0 SPI IRQ number */
+#define CXD56_IRQ_SCU_I2C0      (CXD56_IRQ_EXTINT+17) /**< SCU_1 I2C1 IRQ number */
+#define CXD56_IRQ_SCU_I2C1      (CXD56_IRQ_EXTINT+18) /**< SCU_2 I2C2 IRQ number */
+#define CXD56_IRQ_SCU_3         (CXD56_IRQ_EXTINT+19) /**< SCU_3 SCU IRQ number */
+#define CXD56_IRQ_EXDEVICE_0    (CXD56_IRQ_EXTINT+20) /**< EXDEVICE_0 IRQ number */
+#define CXD56_IRQ_EXDEVICE_1    (CXD56_IRQ_EXTINT+21) /**< EXDEVICE_1 IRQ number */
+#define CXD56_IRQ_EXDEVICE_2    (CXD56_IRQ_EXTINT+22) /**< EXDEVICE_2 IRQ number */
+#define CXD56_IRQ_EXDEVICE_3    (CXD56_IRQ_EXTINT+23) /**< EXDEVICE_3 IRQ number */
+#define CXD56_IRQ_EXDEVICE_4    (CXD56_IRQ_EXTINT+24) /**< EXDEVICE_4 IRQ number */
+#define CXD56_IRQ_EXDEVICE_5    (CXD56_IRQ_EXTINT+25) /**< EXDEVICE_5 IRQ number */
+#define CXD56_IRQ_EXDEVICE_6    (CXD56_IRQ_EXTINT+26) /**< EXDEVICE_6 IRQ number */
+#define CXD56_IRQ_EXDEVICE_7    (CXD56_IRQ_EXTINT+27) /**< EXDEVICE_7 IRQ number */
+#define CXD56_IRQ_EXDEVICE_8    (CXD56_IRQ_EXTINT+28) /**< EXDEVICE_8 IRQ number */
+#define CXD56_IRQ_EXDEVICE_9    (CXD56_IRQ_EXTINT+29) /**< EXDEVICE_9 IRQ number */
+#define CXD56_IRQ_EXDEVICE_10   (CXD56_IRQ_EXTINT+30) /**< EXDEVICE_10 IRQ number */
+#define CXD56_IRQ_EXDEVICE_11   (CXD56_IRQ_EXTINT+31) /**< EXDEVICE_11 IRQ number */
+#define CXD56_IRQ_DMA_A_0       (CXD56_IRQ_EXTINT+32) /**< DMA_A_0 IRQ number */
+#define CXD56_IRQ_DMA_A_1       (CXD56_IRQ_EXTINT+33) /**< DMA_A_1 IRQ number */
+#define CXD56_IRQ_DMA_A_2       (CXD56_IRQ_EXTINT+34) /**< DMA_A_2 IRQ number */
+#define CXD56_IRQ_DMA_A_3       (CXD56_IRQ_EXTINT+35) /**< DMA_A_3 IRQ number */
+#define CXD56_IRQ_DMA_A_4       (CXD56_IRQ_EXTINT+36) /**< DMA_A_4 IRQ number */
+#define CXD56_IRQ_DMA_A_5       (CXD56_IRQ_EXTINT+37) /**< DMA_A_5 IRQ number */
+#define CXD56_IRQ_DMA_A_6       (CXD56_IRQ_EXTINT+38) /**< DMA_A_6 IRQ number */
+#define CXD56_IRQ_DMA_A_7       (CXD56_IRQ_EXTINT+39) /**< DMA_A_7 IRQ number */
+#define CXD56_IRQ_DMA_A_8       (CXD56_IRQ_EXTINT+40) /**< DMA_A_8 IRQ number */
+#define CXD56_IRQ_DMA_A_9       (CXD56_IRQ_EXTINT+41) /**< DMA_A_9 IRQ number */
+#define CXD56_IRQ_DMA_A_10      (CXD56_IRQ_EXTINT+42) /**< DMA_A_10 IRQ number */
+#define CXD56_IRQ_DMA_A_11      (CXD56_IRQ_EXTINT+43) /**< DMA_A_11 IRQ number */
+#define CXD56_IRQ_DMA_A_12      (CXD56_IRQ_EXTINT+44) /**< DMA_A_12 IRQ number */
+#define CXD56_IRQ_DMA_A_13      (CXD56_IRQ_EXTINT+45) /**< DMA_A_13 IRQ number */
+#define CXD56_IRQ_DMA_A_14      (CXD56_IRQ_EXTINT+46) /**< DMA_A_14 IRQ number */
+#define CXD56_IRQ_DMA_A_15      (CXD56_IRQ_EXTINT+47) /**< DMA_A_15 IRQ number */
+#define CXD56_IRQ_DMA_A_16      (CXD56_IRQ_EXTINT+48) /**< DMA_A_16 IRQ number */
+#define CXD56_IRQ_DMA_A_17      (CXD56_IRQ_EXTINT+49) /**< DMA_A_17 IRQ number */
+#define CXD56_IRQ_DMA_A_18      (CXD56_IRQ_EXTINT+50) /**< DMA_A_18 IRQ number */
+#define CXD56_IRQ_DMA_A_19      (CXD56_IRQ_EXTINT+51) /**< DMA_A_19 IRQ number */
+#define CXD56_IRQ_DMA_A_20      (CXD56_IRQ_EXTINT+52) /**< DMA_A_20 IRQ number */
+#define CXD56_IRQ_DMA_A_21      (CXD56_IRQ_EXTINT+53) /**< DMA_A_21 IRQ number */
+#define CXD56_IRQ_DMA_A_22      (CXD56_IRQ_EXTINT+54) /**< DMA_A_22 IRQ number */
+#define CXD56_IRQ_DMA_A_23      (CXD56_IRQ_EXTINT+55) /**< DMA_A_23 IRQ number */
+#define CXD56_IRQ_DMA_A_24      (CXD56_IRQ_EXTINT+56) /**< DMA_A_24 IRQ number */
+#define CXD56_IRQ_DMA_A_25      (CXD56_IRQ_EXTINT+57) /**< DMA_A_25 IRQ number */
+#define CXD56_IRQ_DMA_A_26      (CXD56_IRQ_EXTINT+58) /**< DMA_A_26 IRQ number */
+#define CXD56_IRQ_DMA_A_27      (CXD56_IRQ_EXTINT+59) /**< DMA_A_27 IRQ number */
+#define CXD56_IRQ_DMA_A_28      (CXD56_IRQ_EXTINT+60) /**< DMA_A_28 IRQ number */
+#define CXD56_IRQ_DMA_A_29      (CXD56_IRQ_EXTINT+61) /**< DMA_A_29 IRQ number */
+#define CXD56_IRQ_DMA_A_30      (CXD56_IRQ_EXTINT+62) /**< DMA_A_30 IRQ number */
+#define CXD56_IRQ_DMA_A_31      (CXD56_IRQ_EXTINT+63) /**< DMA_A_31 IRQ number */
+#define CXD56_IRQ_DMA_B_0       (CXD56_IRQ_EXTINT+64) /**< DMA_B_0 IRQ number */
+#define CXD56_IRQ_DMA_B_1       (CXD56_IRQ_EXTINT+65) /**< DMA_B_1 IRQ number */
+#define CXD56_IRQ_DMA_C_0       (CXD56_IRQ_EXTINT+66) /**< DMA_C_0 IRQ number */
+#define CXD56_IRQ_DMA_C_1       (CXD56_IRQ_EXTINT+67) /**< DMA_C_1 IRQ number */
+#define CXD56_IRQ_DMA_D_0       (CXD56_IRQ_EXTINT+68) /**< DMA_D_0 IRQ number */
+#define CXD56_IRQ_DMA_D_1       (CXD56_IRQ_EXTINT+69) /**< DMA_D_1 IRQ number */
+#define CXD56_IRQ_SAKE_NSEC     (CXD56_IRQ_EXTINT+70) /**< SAKE_NSEC IRQ number */
+#define CXD56_IRQ_SAKE_SEC      (CXD56_IRQ_EXTINT+71) /**< SAKE_SEC IRQ number */
+#define CXD56_IRQ_USB_VBUS      (CXD56_IRQ_EXTINT+72) /**< USB_VBUS IRQ number */
+#define CXD56_IRQ_USB_VBUSN     (CXD56_IRQ_EXTINT+73) /**< USB_VBUSN IRQ number */
+#define CXD56_IRQ_SPIM          (CXD56_IRQ_EXTINT+74) /**< SPI0 IRQ number */
+#define CXD56_IRQ_I2CM          (CXD56_IRQ_EXTINT+75) /**< I2C0 IRQ number */
+#define CXD56_IRQ_DEBUG0        (CXD56_IRQ_EXTINT+76) /**< DEBUG0 IRQ number */
+#define CXD56_IRQ_DEBUG1        (CXD56_IRQ_EXTINT+77) /**< DEBUG1 IRQ number */
+#define CXD56_IRQ_FIFO_TO       (CXD56_IRQ_EXTINT+78) /**< FIFO_TO IRQ number */
+#define CXD56_IRQ_FIFO_FROM     (CXD56_IRQ_EXTINT+79) /**< FIFO_FROM IRQ number */
+#define CXD56_IRQ_SPH0          (CXD56_IRQ_EXTINT+80) /**< SPH0 IRQ number */
+#define CXD56_IRQ_SPH1          (CXD56_IRQ_EXTINT+81) /**< SPH1 IRQ number */
+#define CXD56_IRQ_SPH2          (CXD56_IRQ_EXTINT+82) /**< SPH2 IRQ number */
+#define CXD56_IRQ_SPH3          (CXD56_IRQ_EXTINT+83) /**< SPH3 IRQ number */
+#define CXD56_IRQ_SPH4          (CXD56_IRQ_EXTINT+84) /**< SPH4 IRQ number */
+#define CXD56_IRQ_SPH5          (CXD56_IRQ_EXTINT+85) /**< SPH5 IRQ number */
+#define CXD56_IRQ_SPH6          (CXD56_IRQ_EXTINT+86) /**< SPH6 IRQ number */
+#define CXD56_IRQ_SPH7          (CXD56_IRQ_EXTINT+87) /**< SPH7 IRQ number */
+#define CXD56_IRQ_SPH8          (CXD56_IRQ_EXTINT+88) /**< SPH8 IRQ number */
+#define CXD56_IRQ_SPH9          (CXD56_IRQ_EXTINT+89) /**< SPH9 IRQ number */
+#define CXD56_IRQ_SPH10         (CXD56_IRQ_EXTINT+90) /**< SPH10 IRQ number */
+#define CXD56_IRQ_SPH11         (CXD56_IRQ_EXTINT+91) /**< SPH11 IRQ number */
+#define CXD56_IRQ_SPH12         (CXD56_IRQ_EXTINT+92) /**< SPH12 IRQ number */
+#define CXD56_IRQ_SPH13         (CXD56_IRQ_EXTINT+93) /**< SPH13 IRQ number */
+#define CXD56_IRQ_SPH14         (CXD56_IRQ_EXTINT+94) /**< SPH14 IRQ number */
+#define CXD56_IRQ_SPH15         (CXD56_IRQ_EXTINT+95) /**< SPH15 IRQ number */
+#define CXD56_IRQ_SW_INT        (CXD56_IRQ_EXTINT+96) /**< SW_INT IRQ number */
+#define CXD56_IRQ_TIMER0        (CXD56_IRQ_EXTINT+97) /**< TIMER0 IRQ number */
+#define CXD56_IRQ_TIMER1        (CXD56_IRQ_EXTINT+98) /**< TIMER1 IRQ number */
+#define CXD56_IRQ_TIMER2        (CXD56_IRQ_EXTINT+99) /**< TIMER2 IRQ number */
+#define CXD56_IRQ_WDT_INT       (CXD56_IRQ_EXTINT+100) /**< WDT_INT IRQ number */
+#define CXD56_IRQ_WDT_RES       (CXD56_IRQ_EXTINT+101) /**< WDT_RES IRQ number */
+#define CXD56_IRQ_AUDIO_0       (CXD56_IRQ_EXTINT+102) /**< AUDIO_0(MIC) IRQ number */
+#define CXD56_IRQ_AUDIO_1       (CXD56_IRQ_EXTINT+103) /**< AUDIO_1(I2S1) IRQ number */
+#define CXD56_IRQ_AUDIO_2       (CXD56_IRQ_EXTINT+104) /**< AUDIO_2(I2S2) IRQ number */
+#define CXD56_IRQ_AUDIO_3       (CXD56_IRQ_EXTINT+105) /**< AUDIO_3(CODEC) IRQ number */
+#define CXD56_IRQ_GE2D          (CXD56_IRQ_EXTINT+106) /**< APP_IMG 2D Graphics Engine IRQ number */
+#define CXD56_IRQ_ROT           (CXD56_IRQ_EXTINT+107) /**< APP_IMG_ROTation IRQ number */
+#define CXD56_IRQ_CISIF         (CXD56_IRQ_EXTINT+108) /**< APP_IMG CISIF IRQ number */
+#define CXD56_IRQ_IMG_WSPI      (CXD56_IRQ_EXTINT+109) /**< APP_IMG WSSP IRQ number */
+#define CXD56_IRQ_IDMAC         (CXD56_IRQ_EXTINT+110) /**< APP_IMG DMAC IRQ number */
+#define CXD56_IRQ_APP_UART      (CXD56_IRQ_EXTINT+111) /**< APP_IMG UART IRQ number */
+#define CXD56_IRQ_VSYNC         (CXD56_IRQ_EXTINT+112) /**< APP_IMG VSYNC IRQ number */
+#define CXD56_IRQ_IMG_SPI       (CXD56_IRQ_EXTINT+113) /**< APP_IMG SSP IRQ number */
+#define CXD56_IRQ_EMMC          (CXD56_IRQ_EXTINT+114) /**< APP_PER EMMC IRQ number */
+#define CXD56_IRQ_SDIO          (CXD56_IRQ_EXTINT+115) /**< APP_PER SDIO IRQ number */
+#define CXD56_IRQ_USB_INT       (CXD56_IRQ_EXTINT+116) /**< APP_PER USB_INT IRQ number */
+#define CXD56_IRQ_USB_SYS       (CXD56_IRQ_EXTINT+117) /**< APP_PER USB_SYS IRQ number */
+#define CXD56_IRQ_APP_DMAC0     (CXD56_IRQ_EXTINT+118) /**< APP_DMAC0 IRQ number */
+#define CXD56_IRQ_APP_DMAC1     (CXD56_IRQ_EXTINT+119) /**< APP_DMAC1 IRQ number */
+#define CXD56_IRQ_APP_SAKE_NSEC (CXD56_IRQ_EXTINT+120) /**< APP_SAKE_NSEC IRQ number */
+#define CXD56_IRQ_APP_SAKE_SEC  (CXD56_IRQ_EXTINT+121) /**< APP_SAKE_SEC IRQ number */
+#define CXD56_IRQ_SKDMAC_0      (CXD56_IRQ_EXTINT+122) /**< APP_SAKE_DMAC_0 IRQ number */
+#define CXD56_IRQ_SKDMAC_1      (CXD56_IRQ_EXTINT+123) /**< APP_SAKE_DMAC_1 IRQ number */
+#define CXD56_IRQ_APP_PPB       (CXD56_IRQ_EXTINT+124) /**< reserved */
+#define CXD56_IRQ_GPS_OR        (CXD56_IRQ_EXTINT+125) /**< GNSS_OR IRQ number */
+#define CXD56_IRQ_SFC           (CXD56_IRQ_EXTINT+126) /**< SFC IRQ number */
+#define CXD56_IRQ_PMIC          (CXD56_IRQ_EXTINT+127) /**< PMIC IRQ number */
+
+#define CXD56_IRQ_NEXTINT       (128)
+#define CXD56_IRQ_NIRQS         (CXD56_IRQ_EXTINT+CXD56_IRQ_NEXTINT)
+
+/* Total number of IRQ numbers (This will need to be revisited if/when the
+ * Cortex-M0 is supported)
+ */
+
+#define NR_VECTORS              CXD56_IRQ_NIRQS
+#define NR_IRQS                 CXD56_IRQ_NIRQS
+
+/* Cortex-M0 External interrupts (vectors >= 16) */
+
+#if 0
+#  define CXD56M0_IRQ_NIRQS     (CXD56_IRQ_EXTINT + CXD56M0_IRQ_NEXTINT)
+#endif
+
+/* Total number of IRQ numbers (This will need to be revisited if/when the
+ * Cortex-M0 is supported)
+ */
+
+#if 0
+#  define NR_VECTORS            CXD56M0_IRQ_NIRQS
+#  define NR_IRQS               CXD56M0_IRQ_NIRQS
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*vic_vector_t)(uint32_t *regs);
+#endif
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_CXD56XX_IRQ_H */
+
diff --git a/arch/arm/include/cxd56xx/pin.h b/arch/arm/include/cxd56xx/pin.h
new file mode 100644
index 00000000000..f309745507d
--- /dev/null
+++ b/arch/arm/include/cxd56xx/pin.h
@@ -0,0 +1,151 @@
+/****************************************************************************
+ * arch/arm/include/cxd56xx/pin.h
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_CXD56XX_PIN_H
+#define __ARCH_ARM_INCLUDE_CXD56XX_PIN_H
+
+/****************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include 
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Pin number Definitions */
+
+#define PIN_RTC_CLK_IN          (0)
+
+/* SYS GPIO: system power domain GPIOs */
+
+#define PIN_I2C4_BCK            (1)
+#define PIN_I2C4_BDT            (2)
+#define PIN_PMIC_INT            (3)
+#define PIN_RTC_IRQ_OUT         (4)
+#define PIN_AP_CLK              (5)
+#define PIN_GNSS_1PPS_OUT       (6)
+#define PIN_SPI0_CS_X           (17)
+#define PIN_SPI0_SCK            (18)
+#define PIN_SPI0_MOSI           (19)
+#define PIN_SPI0_MISO           (20)
+#define PIN_SPI1_CS_X           (21)
+#define PIN_SPI1_SCK            (22)
+#define PIN_SPI1_IO0            (23)
+#define PIN_SPI1_IO1            (24)
+#define PIN_SPI1_IO2            (25)
+#define PIN_SPI1_IO3            (26)
+#define PIN_SPI2_CS_X           (27)
+#define PIN_SPI2_SCK            (28)
+#define PIN_SPI2_MOSI           (29)
+#define PIN_SPI2_MISO           (30)
+#define PIN_HIF_IRQ_OUT         (31)
+#define PIN_HIF_GPIO0           (32)
+#define PIN_SEN_IRQ_IN          (37)
+#define PIN_SPI3_CS0_X          (38)
+#define PIN_SPI3_CS1_X          (39)
+#define PIN_SPI3_CS2_X          (40)
+#define PIN_SPI3_SCK            (41)
+#define PIN_SPI3_MOSI           (42)
+#define PIN_SPI3_MISO           (43)
+#define PIN_I2C0_BCK            (44)
+#define PIN_I2C0_BDT            (45)
+#define PIN_PWM0                (46)
+#define PIN_PWM1                (47)
+#define PIN_PWM2                (48)
+#define PIN_PWM3                (49)
+
+/* APP GPIO: application power domain GPIOs */
+
+#define PIN_IS_CLK              (56)
+#define PIN_IS_VSYNC            (57)
+#define PIN_IS_HSYNC            (58)
+#define PIN_IS_DATA0            (59)
+#define PIN_IS_DATA1            (60)
+#define PIN_IS_DATA2            (61)
+#define PIN_IS_DATA3            (62)
+#define PIN_IS_DATA4            (63)
+#define PIN_IS_DATA5            (64)
+#define PIN_IS_DATA6            (65)
+#define PIN_IS_DATA7            (66)
+#define PIN_UART2_TXD           (67)
+#define PIN_UART2_RXD           (68)
+#define PIN_UART2_CTS           (69)
+#define PIN_UART2_RTS           (70)
+#define PIN_SPI4_CS_X           (71)
+#define PIN_SPI4_SCK            (72)
+#define PIN_SPI4_MOSI           (73)
+#define PIN_SPI4_MISO           (74)
+#define PIN_EMMC_CLK            (75)
+#define PIN_SPI5_SCK            (PIN_EMMC_CLK)
+#define PIN_EMMC_CMD            (76)
+#define PIN_SPI5_CS_X           (PIN_EMMC_CMD)
+#define PIN_EMMC_DATA0          (77)
+#define PIN_SPI5_MOSI           (PIN_EMMC_DATA0)
+#define PIN_EMMC_DATA1          (78)
+#define PIN_SPI5_MISO           (PIN_EMMC_DATA1)
+#define PIN_EMMC_DATA2          (79)
+#define PIN_EMMC_DATA3          (80)
+#define PIN_SDIO_CLK            (81)
+#define PIN_SDIO_CMD            (82)
+#define PIN_SDIO_DATA0          (83)
+#define PIN_SDIO_DATA1          (84)
+#define PIN_SDIO_DATA2          (85)
+#define PIN_SDIO_DATA3          (86)
+#define PIN_SDIO_CD             (87)
+#define PIN_SDIO_WP             (88)
+#define PIN_SDIO_CMDDIR         (89)
+#define PIN_SDIO_DIR0           (90)
+#define PIN_SDIO_DIR1_3         (91)
+#define PIN_SDIO_CLKI           (92)
+#define PIN_I2S0_BCK            (93)
+#define PIN_I2S0_LRCK           (94)
+#define PIN_I2S0_DATA_IN        (95)
+#define PIN_I2S0_DATA_OUT       (96)
+#define PIN_I2S1_BCK            (97)
+#define PIN_I2S1_LRCK           (98)
+#define PIN_I2S1_DATA_IN        (99)
+#define PIN_I2S1_DATA_OUT       (100)
+#define PIN_MCLK                (101)
+#define PIN_PDM_CLK             (102)
+#define PIN_PDM_IN              (103)
+#define PIN_PDM_OUT             (104)
+#define PIN_USB_VBUSINT         (105)
+
+#endif /* __ARCH_ARM_INCLUDE_CXD56XX_PIN_H */
diff --git a/arch/arm/include/cxd56xx/pm.h b/arch/arm/include/cxd56xx/pm.h
new file mode 100644
index 00000000000..50b05271023
--- /dev/null
+++ b/arch/arm/include/cxd56xx/pm.h
@@ -0,0 +1,391 @@
+/****************************************************************************
+ * arch/arm/include/cxd56xx/pm.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+/**
+ * @file       pm.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_CXD56XX_PM_H
+#define __ARCH_ARM_INCLUDE_CXD56XX_PM_H
+
+/*-----------------------------------------------------------------------------
+ * include files
+ *---------------------------------------------------------------------------*/
+
+#include 
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Boot Cause definitions */
+
+#define PM_BOOT_POR_NORMAL      (0x00000000ul) /** Power On Reset like as battery attached */
+#define PM_BOOT_POR_DEADBATT    (0x00000001ul) /** Battery charged from DeadBattery state */
+#define PM_BOOT_WDT_REBOOT      (0x00000002ul) /** System WDT expired or Explicitly Self Reboot */
+#define PM_BOOT_WDT_RESET       (0x00000004ul) /** Chip WDT expired (might be used in HV-only system) */
+#define PM_BOOT_DEEP_WKUPL      (0x00000008ul) /** In DeepSleep state, Detected WKUPL signal */
+#define PM_BOOT_DEEP_WKUPS      (0x00000010ul) /** In DeepSleep state, Detected WKUPS signal */
+#define PM_BOOT_DEEP_RTC        (0x00000020ul) /** In DeepSleep state, RTC Alarm expired */
+#define PM_BOOT_DEEP_USB_ATTACH (0x00000040ul) /** In DeepSleep state, USB Connected */
+#define PM_BOOT_DEEP_OTHERS     (0x00000080ul) /** In DeepSleep state, Reserved others cause occurred */
+#define PM_BOOT_COLD_SCU_INT    (0x00000100ul) /** In ColdSleep state, Detected SCU Interrupt */
+#define PM_BOOT_COLD_RTC        (0x00001e00ul) /** In ColdSleep state, RTC Alarm Interrupt */
+#define PM_BOOT_COLD_RTC_ALM0   (0x00000200ul) /** In ColdSleep state, RTC Alarm0 expired */
+#define PM_BOOT_COLD_RTC_ALM1   (0x00000400ul) /** In ColdSleep state, RTC Alarm1 expired */
+#define PM_BOOT_COLD_RTC_ALM2   (0x00000800ul) /** In ColdSleep state, RTC Alarm2 expired */
+#define PM_BOOT_COLD_RTC_ALMERR (0x00001000ul) /** In ColdSleep state, RTC Alarm Error occurred */
+#define PM_BOOT_COLD_GPIO       (0x0fff0000ul) /** In ColdSleep state, Detected GPIO interrupt */
+#define PM_BOOT_COLD_SEN_INT    (0x10000000ul) /** In ColdSleep state, Detected SEN_INT Interrupt */
+#define PM_BOOT_COLD_PMIC_INT   (0x20000000ul) /** In ColdSleep state, Detected PMIC Interrupt */
+#define PM_BOOT_COLD_USB_DETACH (0x40000000ul) /** In ColdSleep state, USB Disconnected */
+#define PM_BOOT_COLD_USB_ATTACH (0x80000000ul) /** In ColdSleep state, USB Connected */
+
+/* SRAM power status definitions */
+
+#define PMCMD_RAM_OFF 0  /* Power off */
+#define PMCMD_RAM_RET 1  /* Retention */
+#define PMCMD_RAM_ON  3  /* Power on */
+
+/* FrequencyLock request flag definitions */
+
+#define PM_CPUFREQLOCK_FLAG_HV (0x0001) /* request HV */
+#define PM_CPUFREQLOCK_FLAG_LV (0x4000) /* request LV */
+
+/* FrequencyLock identifier tag helper macro function */
+
+#define PM_CPUFREQLOCK_TAG(prefix1, prefix2, num) \
+          (((prefix1) << 24) + ((prefix2) << 16) + (num))
+
+/* FrequencyLock initializer macro function */
+
+#  define PM_CPUFREQLOCK_INIT(_tag, _flag) \
+{ \
+  .count = 0, \
+  .info = _tag, \
+  .flag = _flag, \
+}
+
+/* WakeLock identifier tag helper macro function */
+
+#define PM_CPUWAKELOCK_TAG(prefix1, prefix2, num) \
+          (((prefix1) << 24) + ((prefix2) << 16) + (num))
+
+/* WakeLock initializer macro function */
+
+#define PM_CPUWAKELOCK_INIT(_tag) \
+{ \
+  .count = 0, \
+  .info = _tag, \
+}
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* slee mode definitions */
+
+enum pm_sleepmode_e
+{
+  PM_SLEEP_DEEP,
+  PM_SLEEP_COLD,
+};
+
+/* FreqLock structure */
+
+struct pm_cpu_freqlock_s
+{
+  struct sq_entry_s sq_entry;
+  int      count;
+  uint32_t info;
+  int      flag;
+};
+
+/* WakeLock structure */
+
+struct pm_cpu_wakelock_s
+{
+  struct sq_entry_s sq_entry;
+  int      count;
+  uint32_t info;
+};
+
+/* Definitions for pmic notify */
+
+enum pmic_notify_e
+{
+  PMIC_NOTIFY_ALARM = 0,
+  PMIC_NOTIFY_WKUPS,
+  PMIC_NOTIFY_WKUPL,
+  PMIC_NOTIFY_LOWBATT,
+  PMIC_NOTIFY_MAX
+};
+
+/* callback function for pmic notify */
+
+typedef void (*pmic_notify_t)(void *arg);
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: up_pmstatdump
+ *
+ * Description:
+ *   Print architecture specific power status
+ *
+ ****************************************************************************/
+
+int up_pmramctrl(int cmd, uintptr_t addr, size_t size);
+
+#ifdef CONFIG_DEBUG_PM
+/****************************************************************************
+ * Name: up_pmstatdump
+ *
+ * Description:
+ *   Print architecture specific power status
+ *
+ ****************************************************************************/
+
+void up_pmstatdump(void);
+#else
+#  define up_pmstatdump()
+#endif
+
+/****************************************************************************
+ * Name: up_pm_acquire_freqlock
+ *
+ * Description:
+ *   Acquire the specified freqlock. If the higher freqlock is acquired, the
+ *   system can clockup until it is released.
+ *
+ * Parameter:
+ *   lock - the pointer of a wakelock variable
+ *
+ ****************************************************************************/
+
+void up_pm_acquire_freqlock(struct pm_cpu_freqlock_s *lock);
+
+/****************************************************************************
+ * Name: up_pm_release_freqlock
+ *
+ * Description:
+ *   Release the specified freqlock. If the freqlock are released, the system
+ *   can drop to the lower clock mode for power saving.
+ *
+ * Parameter:
+ *   lock - the pointer of a freqlock variable
+ *
+ ****************************************************************************/
+
+void up_pm_release_freqlock(struct pm_cpu_freqlock_s *lock);
+
+/****************************************************************************
+ * Name: up_pm_get_freqlock_count
+ *
+ * Description:
+ *   Get the locked count of the specified freqlock
+ *
+ * Parameter:
+ *   lock - the pointer of a freqlock variable
+ *
+ * Return:
+ *   the locked count of the specified freqlock
+ *
+ ****************************************************************************/
+
+int up_pm_get_freqlock_count(struct pm_cpu_freqlock_s *lock);
+
+/****************************************************************************
+ * Name: up_pm_acquire_wakelock
+ *
+ * Description:
+ *   Acquire the specified wakelock. If any wakelock is acquired, CPU can't
+ *   enter to the hot sleep state.
+ *
+ * Parameter:
+ *   lock - the pointer of a wakelock variable
+ *
+ ****************************************************************************/
+
+void up_pm_acquire_wakelock(struct pm_cpu_wakelock_s *lock);
+
+/****************************************************************************
+ * Name: up_pm_release_wakelock
+ *
+ * Description:
+ *   Release the specified wakelock. If all of the wakelock are released,
+ *   CPU can enter to the hot sleep state.
+ *
+ * Parameter:
+ *   lock - the pointer of a wakelock variable
+ *
+ ****************************************************************************/
+
+void up_pm_release_wakelock(struct pm_cpu_wakelock_s *lock);
+
+/****************************************************************************
+ * Name: up_pm_count_acquire_wakelock
+ *
+ * Description:
+ *   Count the total number of wakelock
+ *
+ * Return:
+ *   the total number of wakelock
+ *
+ ****************************************************************************/
+
+int up_pm_count_acquire_wakelock(void);
+
+/****************************************************************************
+ * Name: up_pm_get_bootcause
+ *
+ * Description:
+ *   Get the system boot cause. This boot cause indicates the cause why the
+ *   system is launched from the state of power-off, deep sleep or cold sleep.
+ *   Each boot cause is defined as PM_BOOT_XXX.
+ *
+ * Return:
+ *   Boot cause
+ *
+ ****************************************************************************/
+
+uint32_t up_pm_get_bootcause(void);
+
+/****************************************************************************
+ * Name: up_pm_get_bootmask
+ *
+ * Description:
+ *   Get the system boot mask. This boot mask indicates whether the specified
+ *   bit is enabled or not as the boot cause. If a bit of boot mask is set,
+ *   the boot cause is enabled. Each boot mask is defined as PM_BOOT_XXX.
+ *
+ * Return:
+ *   Boot mask
+ *
+ ****************************************************************************/
+
+uint32_t up_pm_get_bootmask(void);
+
+/****************************************************************************
+ * Name: up_pm_set_bootmask
+ *
+ * Description:
+ *   Enable the boot cause of the specified bit.
+ *
+ * Parameter:
+ *   mask - OR of Boot mask definied as PM_BOOT_XXX
+ *
+ * Return:
+ *   Updated boot mask
+ *
+ ****************************************************************************/
+
+uint32_t up_pm_set_bootmask(uint32_t mask);
+
+/****************************************************************************
+ * Name: up_pm_clr_bootmask
+ *
+ * Description:
+ *   Disable the boot cause of the specified bit.
+ *
+ * Parameter:
+ *   mask - OR of Boot mask definied as PM_BOOT_XXX
+ *
+ * Return:
+ *   Updated boot mask
+ *
+ ****************************************************************************/
+
+uint32_t up_pm_clr_bootmask(uint32_t mask);
+
+/****************************************************************************
+ * Name: up_pm_sleep
+ *
+ * Description:
+ *   Enter sleep mode. This function never returns.
+ *
+ * Parameter:
+ *   mode - PM_SLEEP_DEEP or PM_SLEEP_COLD
+ *
+ ****************************************************************************/
+
+int up_pm_sleep(enum pm_sleepmode_e mode);
+
+/****************************************************************************
+ * Name: up_pm_reboot
+ *
+ * Description:
+ *   System reboot. This function never returns.
+ *
+ ****************************************************************************/
+
+int up_pm_reboot(void);
+
+/****************************************************************************
+ * Name: up_pmic_set_notify
+ *
+ * Description:
+ *   Register a callback for pmic interrupt
+ *
+ * Input Parameter:
+ *   kind - A kind of pmic interrupt defined as pmic_notify_e
+ *   cb - A callback function for a kind of pmic interrupt
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_CXD56_PMIC_INT
+int up_pmic_set_notify(int kind, pmic_notify_t cb);
+#else
+#  define up_pmic_set_notify(kind, cb)
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_CXD56XX_PM_H */
diff --git a/arch/arm/include/cxd56xx/usbdev.h b/arch/arm/include/cxd56xx/usbdev.h
new file mode 100644
index 00000000000..f44e75487bf
--- /dev/null
+++ b/arch/arm/include/cxd56xx/usbdev.h
@@ -0,0 +1,65 @@
+/****************************************************************************
+ * arch/arm/include/cxd56xx/usbdev.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_CXD56XX_USBDEV_H
+#define __ARCH_ARM_INCLUDE_CXD56XX_USBDEV_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+/* BOARDIOC_USBDEV_SETNOTIFYSIG signal value ************************************************/
+
+#define USBDEV_STATE_DETACH       0
+#define USBDEV_STATE_ATTACH       1
+
+/*
+ * The BOARDIOC_USBDEV_SETNOTIFYSIG signal output the VBUS connection state
+ * and supply current value to the signal handler argument (sival_int).
+ *
+ * Please use the following macros.
+ *
+ * - USBDEV_CONNECTED : Get VBUS connection state.
+ * - USBDEV_POWER_CURRENT : Get VBUS supply current.
+ */
+
+#define USBDEV_CONNECTED(x)       (0xffff & ((x)>>16))
+#define USBDEV_POWER_CURRENT(x)   (0xffff & (x))
+
+#endif /* __ARCH_ARM_INCLUDE_CXD56XX_USBDEV_H */
diff --git a/arch/arm/include/imxrt/chip.h b/arch/arm/include/imxrt/chip.h
index b2942107806..34faf216dc4 100644
--- a/arch/arm/include/imxrt/chip.h
+++ b/arch/arm/include/imxrt/chip.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/*****************************************************************************
  * arch/arm/include/imxrt/chip.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
@@ -32,27 +32,42 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- ************************************************************************************/
+ *****************************************************************************/
 
 #ifndef __ARCH_ARM_INCLUDE_IMXRT_CHIP_H
 #define __ARCH_ARM_INCLUDE_IMXRT_CHIP_H
 
-/************************************************************************************
+/*****************************************************************************
  * Included Files
- ************************************************************************************/
+ *****************************************************************************/
 
 #include 
 
-/************************************************************************************
+/*****************************************************************************
  * Pre-processor Definitions
- ************************************************************************************/
+ *****************************************************************************/
 
 /* Get customizations for each supported chip */
 
-#if defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \
-    defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \
-    defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \
-    defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A)
+#if defined(CONFIG_ARCH_CHIP_MIMXRT1021CAG4A) || \
+    defined(CONFIG_ARCH_CHIP_MIMXRT1021CAF4A) || \
+    defined(CONFIG_ARCH_CHIP_MIMXRT1021DAF5A) || \
+    defined(CONFIG_ARCH_CHIP_MIMXRT1021DAG5A)
+
+/*  MIMXRT1021CAG4A - 144 pin, 400MHz Industrial
+ *  MIMXRT1021CAF4A - 100 pin, 400MHz Industrial
+ *  MIMXRT1021DAF5A - 100 pin, 500MHz Consumer
+ *  MIMXRT1021DAG5A - 144 pin, 500MHz Consumer
+ */
+
+#  define IMXRT_OCRAM_SIZE      (256 * 1024) /* 256Kb OCRAM */
+#  define IMXRT_GPIO_NPORTS     5            /* Five total ports */
+                                             /* but 4 doesn't exist */
+
+#elif defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \
+      defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \
+      defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \
+      defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A)
 /* MIMXRT1051CVL5A - Industrial, Reduced Features, 528MHz
  * MIMXRT1051DVL6A - Consumer, Reduced Features, 600MHz
  * MIMXRT1052CVL5A - Industrial, Full Feature, 528MHz
@@ -63,9 +78,9 @@
 #  define IMXRT_GPIO_NPORTS            5           /* Five total ports */
 
 #elif defined(CONFIG_ARCH_CHIP_MIMXRT1061DVL6A) || \
-    defined(CONFIG_ARCH_CHIP_MIMXRT1061CVL5A) || \
-    defined(CONFIG_ARCH_CHIP_MIMXRT1062DVL6A) || \
-    defined(CONFIG_ARCH_CHIP_MIMXRT1062CVL5A)
+      defined(CONFIG_ARCH_CHIP_MIMXRT1061CVL5A) || \
+      defined(CONFIG_ARCH_CHIP_MIMXRT1062DVL6A) || \
+      defined(CONFIG_ARCH_CHIP_MIMXRT1062CVL5A)
 /* MIMXRT1061CVL5A - Industrial, Reduced Features, 528MHz
  * MIMXRT1061DVL6A - Consumer, Reduced Features, 600MHz
  * MIMXRT1062CVL5A - Industrial, Full Feature, 528MHz
@@ -78,27 +93,28 @@
 #  error "Unknown i.MX RT chip type"
 #endif
 
-/* NVIC priority levels *************************************************************/
-/* Each priority field holds an 8-bit priority value, 0-15. The lower the value, the
- * greater the priority of the corresponding interrupt.  The i.MX RT processor
- * implements only  bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
+/* NVIC priority levels ******************************************************
+/* Each priority field holds an 8-bit priority value, 0-15. The lower the
+ * value, the greater the priority of the corresponding interrupt.  The i.MX
+ * RT processor implements only bits[7:4] of each field, bits[3:0] read as
+ * zero and ignore writes.
  */
 
-#define NVIC_SYSH_PRIORITY_MIN        0xf0 /* All bits[7:4] set is minimum priority */
+#define NVIC_SYSH_PRIORITY_MIN        0xf0 /* All bits[7:4] set is min pri */
 #define NVIC_SYSH_PRIORITY_DEFAULT    0x80 /* Midpoint is the default */
 #define NVIC_SYSH_PRIORITY_MAX        0x00 /* Zero is maximum priority */
-#define NVIC_SYSH_PRIORITY_STEP       0x40 /* Two bits of interrupt priority used */
+#define NVIC_SYSH_PRIORITY_STEP       0x40 /* Two bits of interrupt pri used */
 
-/************************************************************************************
+/*****************************************************************************
  * Public Types
- ************************************************************************************/
+ *****************************************************************************/
 
-/************************************************************************************
+/*****************************************************************************
  * Public Data
- ************************************************************************************/
+ *****************************************************************************/
 
-/************************************************************************************
+/*****************************************************************************
  * Public Functions
- ************************************************************************************/
+ *****************************************************************************/
 
 #endif /* __ARCH_ARM_INCLUDE_IMXRT_CHIP_H */
diff --git a/arch/arm/include/imxrt/imxrt102x_irq.h b/arch/arm/include/imxrt/imxrt102x_irq.h
new file mode 100644
index 00000000000..98cf25460b6
--- /dev/null
+++ b/arch/arm/include/imxrt/imxrt102x_irq.h
@@ -0,0 +1,469 @@
+/****************************************************************************************
+ * arch/arm/include/imxrt/imxrt105x_irq.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *           Dave Marples 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly through
+ * nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_IMXRT_IMXRT102X_IRQ_H
+#define __ARCH_ARM_INCLUDE_IMXRT_IMXRT102X_IRQ_H
+
+/****************************************************************************************
+ * Included Files
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************/
+
+/* External interrupts (priority levels >= 256) *****************************************/
+
+#define IMXRT_IRQ_EDMA0_16     (IMXRT_IRQ_EXTINT + 0)   /* eDMA Channel 0/16 Transfer Complete */
+#define IMXRT_IRQ_EDMA1_17     (IMXRT_IRQ_EXTINT + 1)   /* eDMA Channel 1/17 Transfer Complete */
+#define IMXRT_IRQ_EDMA2_18     (IMXRT_IRQ_EXTINT + 2)   /* eDMA Channel 2/18 Transfer Complete */
+#define IMXRT_IRQ_EDMA3_19     (IMXRT_IRQ_EXTINT + 3)   /* eDMA Channel 3/19 Transfer Complete */
+#define IMXRT_IRQ_EDMA4_20     (IMXRT_IRQ_EXTINT + 4)   /* eDMA Channel 4/20 Transfer Complete */
+#define IMXRT_IRQ_EDMA5_21     (IMXRT_IRQ_EXTINT + 5)   /* eDMA Channel 5/21 Transfer Complete */
+#define IMXRT_IRQ_EDMA6_22     (IMXRT_IRQ_EXTINT + 6)   /* eDMA Channel 6/22 Transfer Complete */
+#define IMXRT_IRQ_EDMA7_23     (IMXRT_IRQ_EXTINT + 7)   /* eDMA Channel 7/23 Transfer Complete */
+#define IMXRT_IRQ_EDMA8_24     (IMXRT_IRQ_EXTINT + 8)   /* eDMA Channel 8/24 Transfer Complete */
+#define IMXRT_IRQ_EDMA9_25     (IMXRT_IRQ_EXTINT + 9)   /* eDMA Channel 9/25 Transfer Complete */
+#define IMXRT_IRQ_EDMA10_26    (IMXRT_IRQ_EXTINT + 10)  /* eDMA Channel 10/26 Transfer Complete */
+#define IMXRT_IRQ_EDMA11_27    (IMXRT_IRQ_EXTINT + 11)  /* eDMA Channel 11/27 Transfer Complete */
+#define IMXRT_IRQ_EDMA12_28    (IMXRT_IRQ_EXTINT + 12)  /* eDMA Channel 12/28 Transfer Complete */
+#define IMXRT_IRQ_EDMA13_29    (IMXRT_IRQ_EXTINT + 13)  /* eDMA Channel 13/29 Transfer Complete */
+#define IMXRT_IRQ_EDMA14_30    (IMXRT_IRQ_EXTINT + 14)  /* eDMA Channel 14/30 Transfer Complete */
+#define IMXRT_IRQ_EDMA15_31    (IMXRT_IRQ_EXTINT + 15)  /* eDMA Channel 15/31 Transfer Complete */
+#define IMXRT_IRQ_EDMA_ERROR   (IMXRT_IRQ_EXTINT + 16)  /* Error Interrupt, Channels 0-15 / 16-31 */
+#define IMXRT_IRQ_CM70         (IMXRT_IRQ_EXTINT + 17)  /* CTI trigger outputs (internal: CTIIRQ[0]) */
+#define IMXRT_IRQ_CM71         (IMXRT_IRQ_EXTINT + 18)  /* CTI trigger outputs (internal: CTIIRQ[1]) */
+#define IMXRT_IRQ_CM7CP        (IMXRT_IRQ_EXTINT + 19)  /* CorePlatform exception IRQ */
+#define IMXRT_IRQ_LPUART1      (IMXRT_IRQ_EXTINT + 20)  /* UART1 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART2      (IMXRT_IRQ_EXTINT + 21)  /* UART2 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART3      (IMXRT_IRQ_EXTINT + 22)  /* UART3 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART4      (IMXRT_IRQ_EXTINT + 23)  /* UART4 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART5      (IMXRT_IRQ_EXTINT + 24)  /* UART5 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART6      (IMXRT_IRQ_EXTINT + 25)  /* UART6 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART7      (IMXRT_IRQ_EXTINT + 26)  /* UART7 TX/RX interrupt */
+#define IMXRT_IRQ_LPUART8      (IMXRT_IRQ_EXTINT + 27)  /* UART8 TX/RX interrupt */
+#define IMXRT_IRQ_LPI2C1       (IMXRT_IRQ_EXTINT + 28)  /* I2C1 Interrupt */
+#define IMXRT_IRQ_LPI2C2       (IMXRT_IRQ_EXTINT + 29)  /* I2C2 Interrupt */
+#define IMXRT_IRQ_LPI2C3       (IMXRT_IRQ_EXTINT + 30)  /* I2C3 Interrupt */
+#define IMXRT_IRQ_LPI2C4       (IMXRT_IRQ_EXTINT + 31)  /* I2C4 Interrupt */
+#define IMXRT_IRQ_LPSPI1       (IMXRT_IRQ_EXTINT + 32)  /* LPSPI1 interrupt */
+#define IMXRT_IRQ_LPSPI2       (IMXRT_IRQ_EXTINT + 33)  /* LPSPI2 interrupt */
+#define IMXRT_IRQ_LPSPI3       (IMXRT_IRQ_EXTINT + 34)  /* LPSPI3 interrupt */
+#define IMXRT_IRQ_LPSPI4       (IMXRT_IRQ_EXTINT + 35)  /* LPSPI4 interrupt */
+#define IMXRT_IRQ_CAN1         (IMXRT_IRQ_EXTINT + 36)  /* CAN1 interrupt */
+#define IMXRT_IRQ_CAN2         (IMXRT_IRQ_EXTINT + 37)  /* CAN2 interrupt */
+#define IMXRT_IRQ_CM7FR        (IMXRT_IRQ_EXTINT + 38)  /* FlexRAM address fault */
+#define IMXRT_IRQ_KPP          (IMXRT_IRQ_EXTINT + 39)  /* Keypad Interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 40)  RESERVED */
+#define IMXRT_IRQ_GPRIRQ       (IMXRT_IRQ_EXTINT + 41)  /* Notify cores on exception while boot */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 42)  RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 43)  RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 44)  RESERVED */
+#define IMXRT_IRQ_WDOG2        (IMXRT_IRQ_EXTINT + 45)  /* Watchdog Timer reset */
+#define IMXRT_IRQ_SNVS         (IMXRT_IRQ_EXTINT + 46)  /* SNVS Functional Interrupt */
+#define IMXRT_IRQ_SNVSSEC      (IMXRT_IRQ_EXTINT + 47)  /* SNVS Security Interrupt */
+#define IMXRT_IRQ_SNVSSB       (IMXRT_IRQ_EXTINT + 48)  /* ON-OFF short button press */
+#define IMXRT_IRQ_CSU          (IMXRT_IRQ_EXTINT + 49)  /* CSU Interrupt Request 1 */
+#define IMXRT_IRQ_DCP          (IMXRT_IRQ_EXTINT + 50)  /* DCP channel/CRC interrupts (channel != 0) */
+#define IMXRT_IRQ_DCP0         (IMXRT_IRQ_EXTINT + 51)  /* DCP channel 0 interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 52)  RESERVED */
+#define IMXRT_IRQ_TRNG         (IMXRT_IRQ_EXTINT + 53)  /* TRNG Interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 54)  RESERVED */
+#define IMXRT_IRQ_BEE          (IMXRT_IRQ_EXTINT + 55)  /* BEE IRQ */
+#define IMXRT_IRQ_SAI1         (IMXRT_IRQ_EXTINT + 56)  /* SAI1 interrupt (RX/TX) */
+#define IMXRT_IRQ_SAI2         (IMXRT_IRQ_EXTINT + 57)  /* SAI2 interrupt (RX/TX) */
+#define IMXRT_IRQ_SAI3RX       (IMXRT_IRQ_EXTINT + 58)  /* SAI3 RX interrupt (RX/TX) */
+#define IMXRT_IRQ_SAI3TX       (IMXRT_IRQ_EXTINT + 59)  /* SAI3 TX interrupt (RX/TX) */
+#define IMXRT_IRQ_SPDIF        (IMXRT_IRQ_EXTINT + 60)  /* SPDIF interrupt */
+#define IMXRT_IRQ_PMU          (IMXRT_IRQ_EXTINT + 61)  /* Brown-out event 1.1, 2.5 or 3.0 regulators */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 62)  RESERVED */
+#define IMXRT_IRQ_TEMP         (IMXRT_IRQ_EXTINT + 63)  /* Temperature Monitor */
+#define IMXRT_IRQ_TEMPPANIC    (IMXRT_IRQ_EXTINT + 64)  /* TempSensor panic */
+#define IMXRT_IRQ_USBPHY0      (IMXRT_IRQ_EXTINT + 65)  /* USBPHY (UTMI0) interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 66)  RESERVED */
+#define IMXRT_IRQ_ADC1         (IMXRT_IRQ_EXTINT + 67)  /* ADC1 interrupt */
+#define IMXRT_IRQ_ADC2         (IMXRT_IRQ_EXTINT + 68)  /* ADC2 interrupt */
+#define IMXRT_IRQ_DCDC         (IMXRT_IRQ_EXTINT + 69)  /* DCDC interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 70)  RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 71)  RESERVED */
+#define IMXRT_IRQ_GPIO1_0      (IMXRT_IRQ_EXTINT + 72)  /* GPIO1 INT0 interrupt */
+#define IMXRT_IRQ_GPIO1_1      (IMXRT_IRQ_EXTINT + 73)  /* GPIO1 INT1 interrupt */
+#define IMXRT_IRQ_GPIO1_2      (IMXRT_IRQ_EXTINT + 74)  /* GPIO1 INT2 interrupt */
+#define IMXRT_IRQ_GPIO1_3      (IMXRT_IRQ_EXTINT + 75)  /* GPIO1 INT3 interrupt */
+#define IMXRT_IRQ_GPIO1_4      (IMXRT_IRQ_EXTINT + 76)  /* GPIO1 INT4 interrupt */
+#define IMXRT_IRQ_GPIO1_5      (IMXRT_IRQ_EXTINT + 77)  /* GPIO1 INT5 interrupt */
+#define IMXRT_IRQ_GPIO1_6      (IMXRT_IRQ_EXTINT + 78)  /* GPIO1 INT6 interrupt */
+#define IMXRT_IRQ_GPIO1_7      (IMXRT_IRQ_EXTINT + 79)  /* GPIO1 INT7 interrupt */
+#define IMXRT_IRQ_GPIO1_0_15   (IMXRT_IRQ_EXTINT + 80)  /* GPIO1 INT0-15 interrupt */
+#define IMXRT_IRQ_GPIO1_16_31  (IMXRT_IRQ_EXTINT + 81)  /* GPIO1 INT16-31 interrupt */
+#define IMXRT_IRQ_GPIO2_0_15   (IMXRT_IRQ_EXTINT + 82)  /* GPIO2 INT0-15 interrupt */
+#define IMXRT_IRQ_GPIO2_16_31  (IMXRT_IRQ_EXTINT + 83)  /* GPIO2 INT16-31 interrupt */
+#define IMXRT_IRQ_GPIO3_0_15   (IMXRT_IRQ_EXTINT + 84)  /* GPIO3 INT0-15 interrupt */
+#define IMXRT_IRQ_GPIO3_16_31  (IMXRT_IRQ_EXTINT + 85)  /* GPIO3 INT16-31 interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 86)  RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 87)  RESERVED */
+#define IMXRT_IRQ_GPIO5_0_15   (IMXRT_IRQ_EXTINT + 88)  /* GPIO5 INT0-15 interrupt */
+#define IMXRT_IRQ_GPIO5_16_31  (IMXRT_IRQ_EXTINT + 89)  /* GPIO5 INT16-31 interrupt */
+#define IMXRT_IRQ_FLEXIO1      (IMXRT_IRQ_EXTINT + 90)  /* FlexIO Interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 91)  RESERVED */
+#define IMXRT_IRQ_WDOG1        (IMXRT_IRQ_EXTINT + 92)  /* Watchdog Timer reset */
+#define IMXRT_IRQ_RTWDOG       (IMXRT_IRQ_EXTINT + 93)  /* Watchdog Timer reset */
+#define IMXRT_IRQ_EWM          (IMXRT_IRQ_EXTINT + 94)  /* EWM interrupt */
+#define IMXRT_IRQ_CCM_1        (IMXRT_IRQ_EXTINT + 95)  /* CCM interrupt 1 */
+#define IMXRT_IRQ_CCM_2        (IMXRT_IRQ_EXTINT + 96)  /* CCM interrupt 2 */
+#define IMXRT_IRQ_GPC          (IMXRT_IRQ_EXTINT + 97)  /* GPC interrupt 1 */
+#define IMXRT_IRQ_SRC          (IMXRT_IRQ_EXTINT + 98)  /* SRC interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 99)  RESERVED */
+#define IMXRT_IRQ_GPT1         (IMXRT_IRQ_EXTINT + 100) /* GPT1 interrupt */
+#define IMXRT_IRQ_GPT2         (IMXRT_IRQ_EXTINT + 101) /* GPT2 interrupt */
+#define IMXRT_IRQ_FLEXPWM1_0   (IMXRT_IRQ_EXTINT + 102) /* FLEXPWM1 capture/compare/reload 0 interrupt */
+#define IMXRT_IRQ_FLEXPWM1_1   (IMXRT_IRQ_EXTINT + 103) /* FLEXPWM1 capture/compare/reload 1 interrupt */
+#define IMXRT_IRQ_FLEXPWM1_2   (IMXRT_IRQ_EXTINT + 104) /* FLEXPWM1 capture/compare/reload 2 interrupt */
+#define IMXRT_IRQ_FLEXPWM1_3   (IMXRT_IRQ_EXTINT + 105) /* FLEXPWM1 capture/compare/reload 3 interrupt */
+#define IMXRT_IRQ_FLEXPWM1_F   (IMXRT_IRQ_EXTINT + 106) /* FLEXPWM1 fault interrupt OR reload error */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 107) RESERVED */
+#define IMXRT_IRQ_FLEXSPI      (IMXRT_IRQ_EXTINT + 108) /* FlexSPI interrupt */
+#define IMXRT_IRQ_SEMC         (IMXRT_IRQ_EXTINT + 109) /* SEMC interrupt */
+#define IMXRT_IRQ_USDHC1       (IMXRT_IRQ_EXTINT + 110) /* USDHC1 interrupt */
+#define IMXRT_IRQ_USDHC2       (IMXRT_IRQ_EXTINT + 111) /* USDHC2 interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 112) RESERVED */
+#define IMXRT_IRQ_USBOTG1      (IMXRT_IRQ_EXTINT + 113) /* USBO2 USB OTG1 interrupt */
+#define IMXRT_IRQ_ENET         (IMXRT_IRQ_EXTINT + 114) /* ENET MAC 0 interrupt */
+#define IMXRT_IRQ_ENET1588     (IMXRT_IRQ_EXTINT + 115) /* ENET MAC 0 1588 Timer Interrupt */
+#define IMXRT_IRQ_XBAR1_0_1    (IMXRT_IRQ_EXTINT + 116) /* XBAR1 interrupt 0/1 */
+#define IMXRT_IRQ_XBAR1_2_3    (IMXRT_IRQ_EXTINT + 117) /* XBAR1 interrupt 2/3 */
+#define IMXRT_IRQ_ADCETC_0     (IMXRT_IRQ_EXTINT + 118) /* ADC_ETC interrupt 0 */
+#define IMXRT_IRQ_ADCETC_1     (IMXRT_IRQ_EXTINT + 119) /* ADC_ETC interrupt 1 */
+#define IMXRT_IRQ_ADCETC_2     (IMXRT_IRQ_EXTINT + 120) /* ADC_ETC interrupt 2 */
+#define IMXRT_IRQ_ADCETC_ERR   (IMXRT_IRQ_EXTINT + 121) /* ADC_ETC error interrupt */
+#define IMXRT_IRQ_PIT          (IMXRT_IRQ_EXTINT + 122) /* PIT interrupt */
+#define IMXRT_IRQ_ACMP1        (IMXRT_IRQ_EXTINT + 123) /* ACMP1 interrupt */
+#define IMXRT_IRQ_ACMP2        (IMXRT_IRQ_EXTINT + 124) /* ACMP2 interrupt */
+#define IMXRT_IRQ_ACMP3        (IMXRT_IRQ_EXTINT + 125) /* ACMP3 interrupt */
+#define IMXRT_IRQ_ACMP4        (IMXRT_IRQ_EXTINT + 126) /* ACMP4 interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 127) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 128) RESERVED */
+#define IMXRT_IRQ_ENC1         (IMXRT_IRQ_EXTINT + 129) /* ENC1 interrupt */
+#define IMXRT_IRQ_ENC2         (IMXRT_IRQ_EXTINT + 130) /* ENC2 interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 131) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 132) RESERVED */
+#define IMXRT_IRQ_QTIMER1      (IMXRT_IRQ_EXTINT + 133) /* QTIMER1 timer 0-3 interrupt */
+#define IMXRT_IRQ_QTIMER2      (IMXRT_IRQ_EXTINT + 134) /* QTIMER2 timer 0-3 interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 135) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 136) RESERVED */
+#define IMXRT_IRQ_FLEXPWM2_0   (IMXRT_IRQ_EXTINT + 137) /* FLEXPWM2 capture/compare/reload 0 interrupt */
+#define IMXRT_IRQ_FLEXPWM2_1   (IMXRT_IRQ_EXTINT + 138) /* FLEXPWM2 capture/compare/reload 1 interrupt */
+#define IMXRT_IRQ_FLEXPWM2_2   (IMXRT_IRQ_EXTINT + 139) /* FLEXPWM2 capture/compare/reload 1 interrupt */
+#define IMXRT_IRQ_FLEXPWM2_3   (IMXRT_IRQ_EXTINT + 140) /* FLEXPWM2 capture/compare/reload 3 interrupt */
+#define IMXRT_IRQ_FLEXPWM2_F   (IMXRT_IRQ_EXTINT + 141) /* FLEXPWM2 fault interrupt */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 142) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 143) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 144) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 146) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 147) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 148) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 149) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 150) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 151) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 152) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 153) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 154) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 155) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 156) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 157) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 158) RESERVED */
+/* RESERVED                    (IMXRT_IRQ_EXTINT + 159) RESERVED */
+
+#define IMXRT_IRQ_NEXTINT      160
+
+/* GPIO second level interrupt **********************************************************/
+
+#define IMXRT_GPIO_IRQ_FIRST   (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT)
+#define _IMXRT_GPIO1_0_15_BASE IMXRT_GPIO_IRQ_FIRST
+
+#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ
+  /* GPIO1 has dedicated interrupts for pins 0-7
+   * REVISIT:  I am assuming that you really cannot use the dedicated and the multiplex
+   * interrupts concurrently.
+   */
+
+#  define IMXRT_IRQ_GPIO1_0    (_IMXRT_GPIO1_0_15_BASE + 0)   /* GPIO1 pin 0 interrupt */
+#  define IMXRT_IRQ_GPIO1_1    (_IMXRT_GPIO1_0_15_BASE + 1)   /* GPIO1 pin 1 interrupt */
+#  define IMXRT_IRQ_GPIO1_2    (_IMXRT_GPIO1_0_15_BASE + 2)   /* GPIO1 pin 2 interrupt */
+#  define IMXRT_IRQ_GPIO1_3    (_IMXRT_GPIO1_0_15_BASE + 3)   /* GPIO1 pin 3 interrupt */
+#  define IMXRT_IRQ_GPIO1_4    (_IMXRT_GPIO1_0_15_BASE + 4)   /* GPIO1 pin 4 interrupt */
+#  define IMXRT_IRQ_GPIO1_5    (_IMXRT_GPIO1_0_15_BASE + 5)   /* GPIO1 pin 5 interrupt */
+#  define IMXRT_IRQ_GPIO1_6    (_IMXRT_GPIO1_0_15_BASE + 6)   /* GPIO1 pin 6 interrupt */
+#  define IMXRT_IRQ_GPIO1_7    (_IMXRT_GPIO1_0_15_BASE + 7)   /* GPIO1 pin 7 interrupt */
+#  define IMXRT_IRQ_GPIO1_8    (_IMXRT_GPIO1_0_15_BASE + 8)   /* GPIO1 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO1_9    (_IMXRT_GPIO1_0_15_BASE + 9)   /* GPIO1 pin 9 interrupt */
+#  define IMXRT_IRQ_GPIO1_10   (_IMXRT_GPIO1_0_15_BASE + 10)  /* GPIO1 pin 10 interrupt */
+#  define IMXRT_IRQ_GPIO1_11   (_IMXRT_GPIO1_0_15_BASE + 11)  /* GPIO1 pin 11 interrupt */
+#  define IMXRT_IRQ_GPIO1_12   (_IMXRT_GPIO1_0_15_BASE + 12)  /* GPIO1 pin 12 interrupt */
+#  define IMXRT_IRQ_GPIO1_13   (_IMXRT_GPIO1_0_15_BASE + 13)  /* GPIO1 pin 13 interrupt */
+#  define IMXRT_IRQ_GPIO1_14   (_IMXRT_GPIO1_0_15_BASE + 14)  /* GPIO1 pin 14 interrupt */
+#  define IMXRT_IRQ_GPIO1_15   (_IMXRT_GPIO1_0_15_BASE + 15)  /* GPIO1 pin 15 interrupt */
+
+#  define _IMXRT_GPIO1_8_15_NIRQS 16
+#  define _IMXRT_GPIO1_16_31_BASE (_IMXRT_GPIO1_0_15_BASE + _IMXRT_GPIO1_8_15_NIRQS)
+#else
+#  define _IMXRT_GPIO1_8_15_NIRQS 0
+#  define _IMXRT_GPIO1_16_31_BASE _IMXRT_GPIO1_0_15_BASE
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO1_16_31_IRQ
+#  define IMXRT_IRQ_GPIO1_16   (_IMXRT_GPIO1_16_31_BASE + 0)  /* GPIO1 pin 16 interrupt */
+#  define IMXRT_IRQ_GPIO1_17   (_IMXRT_GPIO1_16_31_BASE + 1)  /* GPIO1 pin 17 interrupt */
+#  define IMXRT_IRQ_GPIO1_18   (_IMXRT_GPIO1_16_31_BASE + 2)  /* GPIO1 pin 18 interrupt */
+#  define IMXRT_IRQ_GPIO1_19   (_IMXRT_GPIO1_16_31_BASE + 3)  /* GPIO1 pin 19 interrupt */
+#  define IMXRT_IRQ_GPIO1_20   (_IMXRT_GPIO1_16_31_BASE + 4)  /* GPIO1 pin 10 interrupt */
+#  define IMXRT_IRQ_GPIO1_21   (_IMXRT_GPIO1_16_31_BASE + 5)  /* GPIO1 pin 21 interrupt */
+#  define IMXRT_IRQ_GPIO1_22   (_IMXRT_GPIO1_16_31_BASE + 6)  /* GPIO1 pin 22 interrupt */
+#  define IMXRT_IRQ_GPIO1_23   (_IMXRT_GPIO1_16_31_BASE + 7)  /* GPIO1 pin 23 interrupt */
+#  define IMXRT_IRQ_GPIO1_24   (_IMXRT_GPIO1_16_31_BASE + 8)  /* GPIO1 pin 24 interrupt */
+#  define IMXRT_IRQ_GPIO1_25   (_IMXRT_GPIO1_16_31_BASE + 9)  /* GPIO1 pin 25 interrupt */
+#  define IMXRT_IRQ_GPIO1_26   (_IMXRT_GPIO1_16_31_BASE + 10) /* GPIO1 pin 26 interrupt */
+#  define IMXRT_IRQ_GPIO1_27   (_IMXRT_GPIO1_16_31_BASE + 11) /* GPIO1 pin 27 interrupt */
+#  define IMXRT_IRQ_GPIO1_28   (_IMXRT_GPIO1_16_31_BASE + 12) /* GPIO1 pin 28 interrupt */
+#  define IMXRT_IRQ_GPIO1_29   (_IMXRT_GPIO1_16_31_BASE + 13) /* GPIO1 pin 29 interrupt */
+#  define IMXRT_IRQ_GPIO1_30   (_IMXRT_GPIO1_16_31_BASE + 14) /* GPIO1 pin 30 interrupt */
+#  define IMXRT_IRQ_GPIO1_31   (_IMXRT_GPIO1_16_31_BASE + 15) /* GPIO1 pin 31 interrupt */
+
+#  define _IMXRT_GPIO1_16_31_NIRQS 16
+#  define _IMXRT_GPIO2_0_15_BASE (_IMXRT_GPIO1_16_31_BASE + _IMXRT_GPIO1_16_31_NIRQS)
+#  define IMXRT_GPIO1_NIRQS    (_IMXRT_GPIO1_8_15_NIRQS + _IMXRT_GPIO1_16_31_NIRQS)
+#else
+#  define _IMXRT_GPIO2_0_15_BASE _IMXRT_GPIO1_16_31_BASE
+#  define IMXRT_GPIO1_NIRQS    _IMXRT_GPIO1_8_15_NIRQS
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO2_0_15_IRQ
+#  define IMXRT_IRQ_GPIO2_0    (_IMXRT_GPIO2_0_15_BASE + 0)   /* GPIO2 pin 0 interrupt */
+#  define IMXRT_IRQ_GPIO2_1    (_IMXRT_GPIO2_0_15_BASE + 1)   /* GPIO2 pin 1 interrupt */
+#  define IMXRT_IRQ_GPIO2_2    (_IMXRT_GPIO2_0_15_BASE + 2)   /* GPIO2 pin 2 interrupt */
+#  define IMXRT_IRQ_GPIO2_3    (_IMXRT_GPIO2_0_15_BASE + 3)   /* GPIO2 pin 3 interrupt */
+#  define IMXRT_IRQ_GPIO2_4    (_IMXRT_GPIO2_0_15_BASE + 4)   /* GPIO2 pin 4 interrupt */
+#  define IMXRT_IRQ_GPIO2_5    (_IMXRT_GPIO2_0_15_BASE + 5)   /* GPIO2 pin 5 interrupt */
+#  define IMXRT_IRQ_GPIO2_6    (_IMXRT_GPIO2_0_15_BASE + 6)   /* GPIO2 pin 6 interrupt */
+#  define IMXRT_IRQ_GPIO2_7    (_IMXRT_GPIO2_0_15_BASE + 7)   /* GPIO2 pin 7 interrupt */
+#  define IMXRT_IRQ_GPIO2_8    (_IMXRT_GPIO2_0_15_BASE + 8)   /* GPIO2 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO2_9    (_IMXRT_GPIO2_0_15_BASE + 9)   /* GPIO2 pin 9 interrupt */
+#  define IMXRT_IRQ_GPIO2_10   (_IMXRT_GPIO2_0_15_BASE + 10)  /* GPIO2 pin 10 interrupt */
+#  define IMXRT_IRQ_GPIO2_11   (_IMXRT_GPIO2_0_15_BASE + 11)  /* GPIO2 pin 11 interrupt */
+#  define IMXRT_IRQ_GPIO2_12   (_IMXRT_GPIO2_0_15_BASE + 12)  /* GPIO2 pin 12 interrupt */
+#  define IMXRT_IRQ_GPIO2_13   (_IMXRT_GPIO2_0_15_BASE + 13)  /* GPIO2 pin 13 interrupt */
+#  define IMXRT_IRQ_GPIO2_14   (_IMXRT_GPIO2_0_15_BASE + 14)  /* GPIO2 pin 14 interrupt */
+#  define IMXRT_IRQ_GPIO2_15   (_IMXRT_GPIO2_0_15_BASE + 15)  /* GPIO2 pin 15 interrupt */
+
+#  define _IMXRT_GPIO2_0_15_NIRQS 16
+#  define _IMXRT_GPIO2_16_31_BASE (_IMXRT_GPIO2_0_15_BASE + _IMXRT_GPIO2_0_15_NIRQS)
+#else
+#  define _IMXRT_GPIO2_0_15_NIRQS 0
+#  define _IMXRT_GPIO2_16_31_BASE _IMXRT_GPIO2_0_15_BASE
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO2_16_31_IRQ
+#  define IMXRT_IRQ_GPIO2_16   (_IMXRT_GPIO2_16_31_BASE + 0)  /* GPIO2 pin 16 interrupt */
+#  define IMXRT_IRQ_GPIO2_17   (_IMXRT_GPIO2_16_31_BASE + 1)  /* GPIO2 pin 17 interrupt */
+#  define IMXRT_IRQ_GPIO2_18   (_IMXRT_GPIO2_16_31_BASE + 2)  /* GPIO2 pin 18 interrupt */
+#  define IMXRT_IRQ_GPIO2_19   (_IMXRT_GPIO2_16_31_BASE + 3)  /* GPIO2 pin 19 interrupt */
+#  define IMXRT_IRQ_GPIO2_20   (_IMXRT_GPIO2_16_31_BASE + 4)  /* GPIO2 pin 20 interrupt */
+#  define IMXRT_IRQ_GPIO2_21   (_IMXRT_GPIO2_16_31_BASE + 5)  /* GPIO2 pin 21 interrupt */
+#  define IMXRT_IRQ_GPIO2_22   (_IMXRT_GPIO2_16_31_BASE + 6)  /* GPIO2 pin 22 interrupt */
+#  define IMXRT_IRQ_GPIO2_23   (_IMXRT_GPIO2_16_31_BASE + 7)  /* GPIO2 pin 23 interrupt */
+#  define IMXRT_IRQ_GPIO2_24   (_IMXRT_GPIO2_16_31_BASE + 8)  /* GPIO2 pin 24 interrupt */
+#  define IMXRT_IRQ_GPIO2_25   (_IMXRT_GPIO2_16_31_BASE + 9)  /* GPIO2 pin 25 interrupt */
+#  define IMXRT_IRQ_GPIO2_26   (_IMXRT_GPIO2_16_31_BASE + 10) /* GPIO2 pin 26 interrupt */
+#  define IMXRT_IRQ_GPIO2_27   (_IMXRT_GPIO2_16_31_BASE + 11) /* GPIO2 pin 27 interrupt */
+#  define IMXRT_IRQ_GPIO2_28   (_IMXRT_GPIO2_16_31_BASE + 12) /* GPIO2 pin 28 interrupt */
+#  define IMXRT_IRQ_GPIO2_29   (_IMXRT_GPIO2_16_31_BASE + 13) /* GPIO2 pin 29 interrupt */
+#  define IMXRT_IRQ_GPIO2_30   (_IMXRT_GPIO2_16_31_BASE + 14) /* GPIO2 pin 30 interrupt */
+#  define IMXRT_IRQ_GPIO2_31   (_IMXRT_GPIO2_16_31_BASE + 15) /* GPIO2 pin 31 interrupt */
+
+#  define _IMXRT_GPIO2_16_31_NIRQS 16
+#  define _IMXRT_GPIO3_0_15_BASE (_IMXRT_GPIO2_16_31_BASE + _IMXRT_GPIO2_16_31_NIRQS)
+#  define IMXRT_GPIO2_NIRQS    (_IMXRT_GPIO2_0_15_NIRQS + _IMXRT_GPIO2_16_31_NIRQS)
+#else
+#  define _IMXRT_GPIO3_0_15_BASE _IMXRT_GPIO2_16_31_BASE
+#  define IMXRT_GPIO2_NIRQS    _IMXRT_GPIO2_0_15_NIRQS
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO3_0_15_IRQ
+#  define IMXRT_IRQ_GPIO3_0    (_IMXRT_GPIO3_0_15_BASE + 0)   /* GPIO3 pin 0 interrupt */
+#  define IMXRT_IRQ_GPIO3_1    (_IMXRT_GPIO3_0_15_BASE + 1)   /* GPIO3 pin 1 interrupt */
+#  define IMXRT_IRQ_GPIO3_2    (_IMXRT_GPIO3_0_15_BASE + 2)   /* GPIO3 pin 2 interrupt */
+#  define IMXRT_IRQ_GPIO3_3    (_IMXRT_GPIO3_0_15_BASE + 3)   /* GPIO3 pin 3 interrupt */
+#  define IMXRT_IRQ_GPIO3_4    (_IMXRT_GPIO3_0_15_BASE + 4)   /* GPIO3 pin 4 interrupt */
+#  define IMXRT_IRQ_GPIO3_5    (_IMXRT_GPIO3_0_15_BASE + 5)   /* GPIO3 pin 5 interrupt */
+#  define IMXRT_IRQ_GPIO3_6    (_IMXRT_GPIO3_0_15_BASE + 6)   /* GPIO3 pin 6 interrupt */
+#  define IMXRT_IRQ_GPIO3_7    (_IMXRT_GPIO3_0_15_BASE + 7)   /* GPIO3 pin 7 interrupt */
+#  define IMXRT_IRQ_GPIO3_8    (_IMXRT_GPIO3_0_15_BASE + 8)   /* GPIO3 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO3_9    (_IMXRT_GPIO3_0_15_BASE + 9)   /* GPIO3 pin 9 interrupt */
+#  define IMXRT_IRQ_GPIO3_10   (_IMXRT_GPIO3_0_15_BASE + 10)  /* GPIO3 pin 10 interrupt */
+#  define IMXRT_IRQ_GPIO3_11   (_IMXRT_GPIO3_0_15_BASE + 11)  /* GPIO3 pin 11 interrupt */
+#  define IMXRT_IRQ_GPIO3_12   (_IMXRT_GPIO3_0_15_BASE + 12)  /* GPIO3 pin 12 interrupt */
+#  define IMXRT_IRQ_GPIO3_13   (_IMXRT_GPIO3_0_15_BASE + 13)  /* GPIO3 pin 13 interrupt */
+#  define IMXRT_IRQ_GPIO3_14   (_IMXRT_GPIO3_0_15_BASE + 14)  /* GPIO3 pin 14 interrupt */
+#  define IMXRT_IRQ_GPIO3_15   (_IMXRT_GPIO3_0_15_BASE + 15)  /* GPIO3 pin 15 interrupt */
+
+#  define _IMXRT_GPIO3_0_15_NIRQS 16
+#  define _IMXRT_GPIO3_16_31_BASE (_IMXRT_GPIO3_0_15_BASE + _IMXRT_GPIO3_0_15_NIRQS)
+#else
+#  define _IMXRT_GPIO3_0_15_NIRQS 0
+#  define _IMXRT_GPIO3_16_31_BASE _IMXRT_GPIO3_0_15_BASE
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO3_16_31_IRQ
+#  define IMXRT_IRQ_GPIO3_16   (_IMXRT_GPIO3_16_31_BASE + 0)  /* GPIO3 pin 16 interrupt */
+#  define IMXRT_IRQ_GPIO3_17   (_IMXRT_GPIO3_16_31_BASE + 1)  /* GPIO3 pin 17 interrupt */
+#  define IMXRT_IRQ_GPIO3_18   (_IMXRT_GPIO3_16_31_BASE + 2)  /* GPIO3 pin 18 interrupt */
+#  define IMXRT_IRQ_GPIO3_19   (_IMXRT_GPIO3_16_31_BASE + 3)  /* GPIO3 pin 19 interrupt */
+#  define IMXRT_IRQ_GPIO3_20   (_IMXRT_GPIO3_16_31_BASE + 4)  /* GPIO3 pin 20 interrupt */
+#  define IMXRT_IRQ_GPIO3_21   (_IMXRT_GPIO3_16_31_BASE + 5)  /* GPIO3 pin 21 interrupt */
+#  define IMXRT_IRQ_GPIO3_22   (_IMXRT_GPIO3_16_31_BASE + 6)  /* GPIO3 pin 22 interrupt */
+#  define IMXRT_IRQ_GPIO3_23   (_IMXRT_GPIO3_16_31_BASE + 7)  /* GPIO3 pin 23 interrupt */
+#  define IMXRT_IRQ_GPIO3_24   (_IMXRT_GPIO3_16_31_BASE + 8)  /* GPIO3 pin 24 interrupt */
+#  define IMXRT_IRQ_GPIO3_25   (_IMXRT_GPIO3_16_31_BASE + 9)  /* GPIO3 pin 25 interrupt */
+#  define IMXRT_IRQ_GPIO3_26   (_IMXRT_GPIO3_16_31_BASE + 10) /* GPIO3 pin 26 interrupt */
+#  define IMXRT_IRQ_GPIO3_27   (_IMXRT_GPIO3_16_31_BASE + 11) /* GPIO3 pin 27 interrupt */
+#  define IMXRT_IRQ_GPIO3_28   (_IMXRT_GPIO3_16_31_BASE + 12) /* GPIO3 pin 28 interrupt */
+#  define IMXRT_IRQ_GPIO3_29   (_IMXRT_GPIO3_16_31_BASE + 13) /* GPIO3 pin 29 interrupt */
+#  define IMXRT_IRQ_GPIO3_30   (_IMXRT_GPIO3_16_31_BASE + 14) /* GPIO3 pin 30 interrupt */
+#  define IMXRT_IRQ_GPIO3_31   (_IMXRT_GPIO3_16_31_BASE + 15) /* GPIO3 pin 31 interrupt */
+
+#  define _IMXRT_GPIO3_16_31_NIRQS 16
+#  define _IMXRT_GPIO5_0_15_BASE (_IMXRT_GPIO3_16_31_BASE + _IMXRT_GPIO3_16_31_NIRQS)
+#  define IMXRT_GPIO3_NIRQS    (_IMXRT_GPIO3_0_15_NIRQS + _IMXRT_GPIO3_16_31_NIRQS)
+#else
+#  define _IMXRT_GPIO5_0_15_BASE _IMXRT_GPIO3_16_31_BASE
+#  define IMXRT_GPIO3_NIRQS    _IMXRT_GPIO3_0_15_NIRQS
+#endif
+
+/* There is no GPIO4 on this chip */
+
+#ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
+#  define IMXRT_IRQ_GPIO5_0    (_IMXRT_GPIO5_0_15_BASE + 0)   /* GPIO5 pin 0 interrupt */
+#  define IMXRT_IRQ_GPIO5_1    (_IMXRT_GPIO5_0_15_BASE + 1)   /* GPIO5 pin 1 interrupt */
+#  define IMXRT_IRQ_GPIO5_2    (_IMXRT_GPIO5_0_15_BASE + 2)   /* GPIO5 pin 2 interrupt */
+#  define IMXRT_IRQ_GPIO5_3    (_IMXRT_GPIO5_0_15_BASE + 3)   /* GPIO5 pin 3 interrupt */
+#  define IMXRT_IRQ_GPIO5_4    (_IMXRT_GPIO5_0_15_BASE + 4)   /* GPIO5 pin 4 interrupt */
+#  define IMXRT_IRQ_GPIO5_5    (_IMXRT_GPIO5_0_15_BASE + 5)   /* GPIO5 pin 5 interrupt */
+#  define IMXRT_IRQ_GPIO5_6    (_IMXRT_GPIO5_0_15_BASE + 6)   /* GPIO5 pin 6 interrupt */
+#  define IMXRT_IRQ_GPIO5_7    (_IMXRT_GPIO5_0_15_BASE + 7)   /* GPIO5 pin 7 interrupt */
+#  define IMXRT_IRQ_GPIO5_8    (_IMXRT_GPIO5_0_15_BASE + 8)   /* GPIO5 pin 8 interrupt */
+#  define IMXRT_IRQ_GPIO5_9    (_IMXRT_GPIO5_0_15_BASE + 9)   /* GPIO5 pin 9 interrupt */
+#  define IMXRT_IRQ_GPIO5_10   (_IMXRT_GPIO5_0_15_BASE + 10)  /* GPIO5 pin 10 interrupt */
+#  define IMXRT_IRQ_GPIO5_11   (_IMXRT_GPIO5_0_15_BASE + 11)  /* GPIO5 pin 11 interrupt */
+#  define IMXRT_IRQ_GPIO5_12   (_IMXRT_GPIO5_0_15_BASE + 12)  /* GPIO5 pin 12 interrupt */
+#  define IMXRT_IRQ_GPIO5_13   (_IMXRT_GPIO5_0_15_BASE + 13)  /* GPIO5 pin 13 interrupt */
+#  define IMXRT_IRQ_GPIO5_14   (_IMXRT_GPIO5_0_15_BASE + 14)  /* GPIO5 pin 14 interrupt */
+#  define IMXRT_IRQ_GPIO5_15   (_IMXRT_GPIO5_0_15_BASE + 15)  /* GPIO5 pin 15 interrupt */
+
+#  define _IMXRT_GPIO5_0_15_NIRQS 16
+#  define _IMXRT_GPIO5_16_31_BASE (_IMXRT_GPIO5_0_15_BASE + _IMXRT_GPIO5_0_15_NIRQS)
+#else
+#  define _IMXRT_GPIO5_0_15_NIRQS 0
+#  define _IMXRT_GPIO5_16_31_BASE _IMXRT_GPIO5_0_15_BASE
+#endif
+
+#ifdef CONFIG_IMXRT_GPIO5_16_31_IRQ
+#  define IMXRT_IRQ_GPIO5_16   (_IMXRT_GPIO5_16_31_BASE + 0)  /* GPIO5 pin 16 interrupt */
+#  define IMXRT_IRQ_GPIO5_17   (_IMXRT_GPIO5_16_31_BASE + 1)  /* GPIO5 pin 17 interrupt */
+#  define IMXRT_IRQ_GPIO5_18   (_IMXRT_GPIO5_16_31_BASE + 2)  /* GPIO5 pin 18 interrupt */
+#  define IMXRT_IRQ_GPIO5_19   (_IMXRT_GPIO5_16_31_BASE + 3)  /* GPIO5 pin 19 interrupt */
+#  define IMXRT_IRQ_GPIO5_20   (_IMXRT_GPIO5_16_31_BASE + 4)  /* GPIO5 pin 20 interrupt */
+#  define IMXRT_IRQ_GPIO5_21   (_IMXRT_GPIO5_16_31_BASE + 5)  /* GPIO5 pin 21 interrupt */
+#  define IMXRT_IRQ_GPIO5_22   (_IMXRT_GPIO5_16_31_BASE + 6)  /* GPIO5 pin 22 interrupt */
+#  define IMXRT_IRQ_GPIO5_23   (_IMXRT_GPIO5_16_31_BASE + 7)  /* GPIO5 pin 23 interrupt */
+#  define IMXRT_IRQ_GPIO5_24   (_IMXRT_GPIO5_16_31_BASE + 8)  /* GPIO5 pin 24 interrupt */
+#  define IMXRT_IRQ_GPIO5_25   (_IMXRT_GPIO5_16_31_BASE + 9)  /* GPIO5 pin 25 interrupt */
+#  define IMXRT_IRQ_GPIO5_26   (_IMXRT_GPIO5_16_31_BASE + 10) /* GPIO5 pin 26 interrupt */
+#  define IMXRT_IRQ_GPIO5_27   (_IMXRT_GPIO5_16_31_BASE + 11) /* GPIO5 pin 27 interrupt */
+#  define IMXRT_IRQ_GPIO5_28   (_IMXRT_GPIO5_16_31_BASE + 12) /* GPIO5 pin 28 interrupt */
+#  define IMXRT_IRQ_GPIO5_29   (_IMXRT_GPIO5_16_31_BASE + 13) /* GPIO5 pin 29 interrupt */
+#  define IMXRT_IRQ_GPIO5_30   (_IMXRT_GPIO5_16_31_BASE + 14) /* GPIO5 pin 30 interrupt */
+#  define IMXRT_IRQ_GPIO5_31   (_IMXRT_GPIO5_16_31_BASE + 15) /* GPIO5 pin 31 interrupt */
+
+#  define _IMXRT_GPIO5_16_31_NIRQS 16
+#  define IMXRT_GPIO5_NIRQS    (_IMXRT_GPIO5_0_15_NIRQS + _IMXRT_GPIO5_16_31_NIRQS)
+#else
+#  define IMXRT_GPIO5_NIRQS    _IMXRT_GPIO5_0_15_NIRQS
+#endif
+
+#define IMXRT_GPIO_NIRQS       (IMXRT_GPIO1_NIRQS + IMXRT_GPIO2_NIRQS + \
+                                IMXRT_GPIO3_NIRQS + IMXRT_GPIO5_NIRQS)
+#define IMXRT_GPIO_IRQ_LAST    (_IMXRT_GPIO1_0_15_BASE + IMXRT_GPIO_NIRQS)
+
+/* Total number of IRQ numbers **********************************************************/
+
+#define NR_IRQS                (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT + IMXRT_GPIO_NIRQS)
+
+/****************************************************************************************
+ * Public Types
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Inline functions
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Data
+ ****************************************************************************************/
+
+/****************************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_IMXRT_IMXRT102X_IRQ_H */
diff --git a/arch/arm/include/imxrt/irq.h b/arch/arm/include/imxrt/irq.h
index 72bca14fabe..0773511b2f5 100644
--- a/arch/arm/include/imxrt/irq.h
+++ b/arch/arm/include/imxrt/irq.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
  * arch/arm/include/imxrt/irq.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
@@ -32,53 +32,61 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- ****************************************************************************************/
+ ****************************************************************************/
 
-/* This file should never be included directed but, rather, only indirectly through
- * nuttx/irq.h
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
  */
 
 #ifndef __ARCH_ARM_INCLUDE_IMXRT_IRQ_H
 #define __ARCH_ARM_INCLUDE_IMXRT_IRQ_H
 
-/****************************************************************************************
+/*****************************************************************************
  * Included Files
- ****************************************************************************************/
+ *****************************************************************************/
 
 #include 
 #include 
 
-/****************************************************************************************
+/*****************************************************************************
  * Pre-processor Definitions
- ****************************************************************************************/
+ *****************************************************************************/
 
-/* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to
- * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
- * to handle mapping tables.
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC.  This does, however, waste several words
+ * of memory in the IRQ to handle mapping tables.
  */
 
 /* Common Processor Exceptions (vectors 0-15) */
 
-#define IMXRT_IRQ_RESERVED       (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
+#define IMXRT_IRQ_RESERVED       (0) /* Reserved vector .. only used with
+                                        CONFIG_DEBUG_FEATURES */
+
                                      /* Vector  0: Reset stack pointer value */
-                                     /* Vector  1: Reset (not handler as an IRQ) */
-#define IMXRT_IRQ_NMI            (2) /* Vector  2: Non-Maskable Interrupt (NMI) */
+
+                                     /* Vector  1: Reset (not handled by IRQ) */
+
+#define IMXRT_IRQ_NMI            (2) /* Vector  2: Non-Maskable Int (NMI) */
 #define IMXRT_IRQ_HARDFAULT      (3) /* Vector  3: Hard fault */
 #define IMXRT_IRQ_MEMFAULT       (4) /* Vector  4: Memory management (MPU) */
 #define IMXRT_IRQ_BUSFAULT       (5) /* Vector  5: Bus fault */
 #define IMXRT_IRQ_USAGEFAULT     (6) /* Vector  6: Usage fault */
                                      /* Vectors 7-10: Reserved */
+
 #define IMXRT_IRQ_SVCALL        (11) /* Vector 11: SVC call */
 #define IMXRT_IRQ_DBGMONITOR    (12) /* Vector 12: Debug Monitor */
                                      /* Vector 13: Reserved */
-#define IMXRT_IRQ_PENDSV        (14) /* Vector 14: Pendable system service request */
+
+#define IMXRT_IRQ_PENDSV        (14) /* Vector 14: Pendable SSR */
 #define IMXRT_IRQ_SYSTICK       (15) /* Vector 15: System tick */
 
 /* Chip-Specific External interrupts */
 
-#define IMXRT_IRQ_EXTINT        (16) /* Vector number of the first external interrupt */
+#define IMXRT_IRQ_EXTINT        (16) /* Vector number of the first ext int */
 
-#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include 
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
 #  include 
 #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
 #  include 
@@ -86,15 +94,15 @@
 #  error Unrecognized i.MX RT architecture
 #endif
 
-/****************************************************************************************
+/****************************************************************************
  * Public Types
- ****************************************************************************************/
+ ****************************************************************************/
 
 #ifndef __ASSEMBLY__
 
-/****************************************************************************************
+/****************************************************************************
  * Public Data
- ****************************************************************************************/
+ ****************************************************************************/
 
 #ifdef __cplusplus
 #define EXTERN extern "C"
@@ -104,9 +112,9 @@ extern "C"
 #define EXTERN extern
 #endif
 
-/****************************************************************************************
+/****************************************************************************
  * Public Function Prototypes
- ****************************************************************************************/
+ ****************************************************************************/
 
 #undef EXTERN
 #ifdef __cplusplus
diff --git a/arch/arm/include/stm32f0l0/chip.h b/arch/arm/include/stm32f0l0g0/chip.h
similarity index 71%
rename from arch/arm/include/stm32f0l0/chip.h
rename to arch/arm/include/stm32f0l0g0/chip.h
index f5d6c3b6c38..b05fc7eb281 100644
--- a/arch/arm/include/stm32f0l0/chip.h
+++ b/arch/arm/include/stm32f0l0g0/chip.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/include/stm32f0l0/chip.h
+ * arch/arm/include/stm32f0l0g0/chip.h
  *
  *   Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H
-#define __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H
+#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H
+#define __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H
 
 /************************************************************************************
  * Included Files
@@ -57,12 +57,13 @@
 #  define STM32_NSPI            2  /* Two SPI modules (SPI or I2S) */
 #  define STM32_NI2S            2  /* Two I2S modules (SPI or I2S) */
 #  define STM32_NI2C            2  /* Two I2C modules */
+#  define STM32_NDMA            1  /* 1 DMA1, 7-channels */
 #  define STM32_NUSART          2  /* Two USARTs modules */
 #  define STM32_NCAN            0  /* No CAN controllers */
 #  define STM32_NUSBDEV         1  /* One USB full-speed device controller */
 #  define STM32_NUSBOTG         0  /* No USB OTG FS/HS (only USB 2.0 device) */
-#  define STM32_NDAC            1  /* One DAC module */
-#  define STM32_NDACCHAN        1  /* One DAC channels */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            1  /* One DAC channel */
 #  define STM32_NCOMP           2  /* Two Analog Comparators */
 #  define STM32_NCAP            13 /* Capacitive sensing channels (14 on UFQFPN32)) */
 #  define STM32_NPORTS          6  /* Six GPIO ports, GPIOA-F */
@@ -83,16 +84,14 @@
 #  define STM32_NSPI            2  /* Two SPI modules (SPI or I2S) */
 #  define STM32_NI2S            2  /* Two I2S modules (SPI or I2S) */
 #  define STM32_NI2C            2  /* Two I2C modules */
+#  define STM32_NDMA            1  /* 1 DMA1, 7-channels */
 #  define STM32_NUSART          4  /* Four USARTs module */
 #  define STM32_NCAN            1  /* One CAN controller */
 #  define STM32_NUSBDEV         1  /* One USB full-speed device controller */
 #  define STM32_NUSBOTG         0  /* No USB OTG FS/HS (only USB 2.0 device) */
 #  define STM32_NCEC            1  /* One HDMI-CEC controller */
-#  define STM32_NADC12          1  /* One 12-bit module */
-#  define STM32_NADCCHAN        10 /* Ten external channels */
-#  define STM32_NADCINT         3  /* Three internal channels */
-#  define STM32_NDAC            1  /* One DAC module */
-#  define STM32_NDACCHAN        2  /* Two DAC channels */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            2  /* Two DAC channel */
 #  define STM32_NCOMP           2  /* Two Analog Comparators */
 #  define STM32_NCAP            17 /* Capacitive sensing channels */
 #  define STM32_NPORTS          6  /* Six GPIO ports, GPIOA-F */
@@ -113,16 +112,14 @@
 #  define STM32_NSPI            2  /* Two SPI modules (SPI or I2S) */
 #  define STM32_NI2S            2  /* Two I2S modules (SPI or I2S) */
 #  define STM32_NI2C            2  /* Two I2C modules */
+#  define STM32_NDMA            1  /* 1 DMA1, 7-channels */
 #  define STM32_NUSART          4  /* Four USARTs module */
 #  define STM32_NCAN            1  /* One CAN controller */
 #  define STM32_NUSBDEV         1  /* One USB full-speed device controller */
 #  define STM32_NUSBOTG         0  /* No USB OTG FS/HS (only USB 2.0 device) */
 #  define STM32_NCEC            1  /* One HDMI-CEC controller */
-#  define STM32_NADC12          1  /* One 12-bit module */
-#  define STM32_NADCCHAN        16 /* 16 external channels */
-#  define STM32_NADCINT         3  /* Three internal channels */
-#  define STM32_NDAC            1  /* One DAC module */
-#  define STM32_NDACCHAN        2  /* Two DAC channels */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            2  /* Two DAC channel */
 #  define STM32_NCOMP           2  /* Two Analog Comparators */
 #  define STM32_NCAP            18 /* Capacitive sensing channels */
 #  define STM32_NPORTS          6  /* Six GPIO ports, GPIOA-F */
@@ -143,16 +140,14 @@
 #  define STM32_NSPI            2  /* Two SPI modules (SPI or I2S) */
 #  define STM32_NI2S            2  /* Two I2S modules (SPI or I2S) */
 #  define STM32_NI2C            2  /* Two I2C modules */
+#  define STM32_NDMA            1  /* 1 DMA1, 7-channels */
 #  define STM32_NUSART          4  /* Four USARTs module */
 #  define STM32_NCAN            1  /* One CAN controller */
 #  define STM32_NUSBDEV         1  /* One USB full-speed device controller */
 #  define STM32_NUSBOTG         0  /* No USB OTG FS/HS (only USB 2.0 device) */
 #  define STM32_NCEC            1  /* One HDMI-CEC controller */
-#  define STM32_NADC12          1  /* One 12-bit module */
-#  define STM32_NADCCHAN        16 /* 16 external channels */
-#  define STM32_NADCINT         3  /* Three internal channels */
-#  define STM32_NDAC            1  /* One DAC module */
-#  define STM32_NDACCHAN        2  /* Two DAC channels */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            2  /* Two DAC channel */
 #  define STM32_NCOMP           2  /* Two Analog Comparators */
 #  define STM32_NCAP            24 /* Capacitive sensing channels */
 #  define STM32_NPORTS          6  /* Six GPIO ports, GPIOA-F */
@@ -173,16 +168,14 @@
 #  define STM32_NSPI            2  /* Two SPI modules (SPI or I2S) */
 #  define STM32_NI2S            2  /* Two I2S modules (SPI or I2S) */
 #  define STM32_NI2C            2  /* Two I2C modules */
+#  define STM32_NDMA            2  /* DMA1, DMA2 */
 #  define STM32_NUSART          6  /* Six USARTs modules */
 #  define STM32_NCAN            1  /* One CAN controller */
 #  define STM32_NUSBDEV         0  /* No USB full-speed device controller */
 #  define STM32_NUSBOTG         0  /* No USB OTG FS/HS (only USB 2.0 device) */
 #  define STM32_NCEC            1  /* One HDMI-CEC controller */
-#  define STM32_NADC12          1  /* One 12-bit module */
-#  define STM32_NADCCHAN        10 /* 10 external channels */
-#  define STM32_NADCINT         3  /* Three internal channels */
-#  define STM32_NDAC            1  /* One DAC module */
-#  define STM32_NDACCHAN        2  /* Two DAC channels */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            2  /* Two DAC channel */
 #  define STM32_NCOMP           2  /* Two Analog Comparators */
 #  define STM32_NCAP            17 /* Capacitive sensing channels */
 #  define STM32_NPORTS          6  /* Six GPIO ports, GPIOA-F */
@@ -204,16 +197,14 @@
 #  define STM32_NSPI            2  /* Two SPI modules (SPI or I2S) */
 #  define STM32_NI2S            2  /* Two I2S modules (SPI or I2S) */
 #  define STM32_NI2C            2  /* Two I2C modules */
+#  define STM32_NDMA            2  /* DMA1, DMA2 */
 #  define STM32_NUSART          8  /* Eight USARTs modules */
 #  define STM32_NCAN            1  /* One CAN controller */
 #  define STM32_NUSBDEV         0  /* No USB full-speed device controller */
 #  define STM32_NUSBOTG         0  /* No USB OTG FS/HS (only USB 2.0 device) */
 #  define STM32_NCEC            1  /* One HDMI-CEC controller */
-#  define STM32_NADC12          1  /* One 12-bit module */
-#  define STM32_NADCCHAN        16 /* 16 external channels */
-#  define STM32_NADCINT         3  /* Three internal channels */
-#  define STM32_NDAC            1  /* One DAC module */
-#  define STM32_NDACCHAN        2  /* Two DAC channels */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            2  /* Two DAC channel */
 #  define STM32_NCOMP           2  /* Two Analog Comparators */
 #  if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
 #    define STM32_NCAP          24 /* Capacitive sensing channels */
@@ -222,10 +213,44 @@
 #  endif
 #  define STM32_NPORTS          6  /* Six GPIO ports, GPIOA-F */
 
+#elif defined(CONFIG_ARCH_CHIP_STM32G071EB)   || defined(CONFIG_ARCH_CHIP_STM32G071G8)   || \
+      defined(CONFIG_ARCH_CHIP_STM32G071GB)   || defined(CONFIG_ARCH_CHIP_STM32G071G8XN) || \
+      defined(CONFIG_ARCH_CHIP_STM32G071GBXN) || defined(CONFIG_ARCH_CHIP_STM32G071K8)   || \
+      defined(CONFIG_ARCH_CHIP_STM32G071KB)   || defined(CONFIG_ARCH_CHIP_STM32G071K8XN) || \
+      defined(CONFIG_ARCH_CHIP_STM32G071KBXN) || defined(CONFIG_ARCH_CHIP_STM32G071C8)   || \
+      defined(CONFIG_ARCH_CHIP_STM32G071CB)   || defined(CONFIG_ARCH_CHIP_STM32G071R8)   || \
+      defined(CONFIG_ARCH_CHIP_STM32G071RB)
+
+#  define STM32_NATIM           1  /* One advanced timer TIM1 */
+#  define STM32_NGTIM16         4  /* 16-bit general up/down timers TIM2-3
+                                    * (with DMA) and TIM21-22 without DMA */
+#  define STM32_NGTIM32         0  /* No 32-bit general up/down timers */
+#  define STM32_NBTIM           2  /* Two basic timers: TIM6, TIM7 with DMA */
+                                   /* Two LPTIMER */
+#  define STM32_NSPI            2  /* Two SPI modules SPI1-2 */
+#  define STM32_NI2C            2  /* Two I2C (2 with SMBus/PMBus) */
+#  define STM32_NDMA            1  /* One DMA1, 7-channels */
+#  define STM32_NUSART          4  /* Four USART modules, USART1-4 */
+                                   /* One LPUART */
+#  define STM32_NCAN            0  /* No CAN controllers */
+#  define STM32_NLCD            0  /* No LCD */
+#  define STM32_NUSBDEV         0  /* No USB full-speed device controller */
+#  define STM32_NUSBOTG         0  /* No USB OTG */
+#  define STM32_NCEC            1  /* One HDMI-CEC controller */
+#  define STM32_NADC            1   /* (1) ADC1, 12-channels */
+
+#  define STM32_NDAC            2  /* Two DAC channels */
+#  define STM32_NCOMP           2  /* Two Analog Comparators */
+#  define STM32_NCRC            0  /* No CRC module */
+#  define STM32_NRNG            0  /* No Random number generator (RNG) */
+#  define STM32_NCAP            0  /* No Capacitive sensing channels */
+#  define STM32_NPORTS          6  /* Six GPIO ports, GPIOA-E, H */
+
 /* STM32L EnergyLite Line ***********************************************************/
- 
-/* STM32L03XX  - With LCD
- * STM32L02XX  - No LCD
+
+/* STM32L073XX  - With LCD
+ * STM32L072XX  - No LCD
+ * STM32L071XX  - Access line, no LCD
  *
  * STM32L0XXX8 - 64KB FLASH, 20KB SRAM, 3KB EEPROM
  * STM32L0XXXB - 128KB FLASH, 20KB SRAM, 6KB EEPROM
@@ -236,6 +261,87 @@
  * STM32L0XXVX - 100-pins
  */
 
+#elif defined(CONFIG_ARCH_CHIP_STM32L071K8)
+#  define STM32_NATIM           0  /* No advanced timers */
+#  define STM32_NGTIM16         4  /* 16-bit general up/down timers TIM2-3
+                                    * (with DMA) and TIM21-22 without DMA */
+#  define STM32_NGTIM32         0  /* No 32-bit general up/down timers */
+#  define STM32_NBTIM           2  /* 2 basic timers: TIM6, TIM7 with DMA */
+                                   /* 1 LPTIMER */
+#  define STM32_NSPI            1  /* 1 SPI modules SPI1 */
+#  define STM32_NI2S            0  /* 0 I2S module */
+#  define STM32_NI2C            2  /* 2 I2C */
+#  define STM32_NDMA            1  /* 1 DMA1, 7-channels */
+#  define STM32_NUSART          3  /* 3 USART modules, USART1-3 */
+                                   /* 1 LPUART */
+#  define STM32_NCAN            0  /* 0 CAN controllers */
+#  define STM32_NLCD            0  /* 0 LCD */
+#  define STM32_NUSBDEV         0  /* 0 USB full-speed device controller */
+#  define STM32_NUSBOTG         0  /* 0 USB OTG FS/HS (only USB 2.0 device) */
+#  define STM32_NCEC            0  /* 0 HDMI-CEC controller */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            0  /* 0 DAC channel */
+#  define STM32_NCOMP           2  /* 2 Analog Comparators */
+#  define STM32_NCRC            0  /* 0 CRC module */
+#  define STM32_NRNG            0  /* 0 Random number generator (RNG) */
+#  define STM32_NCAP            0  /* 0 Capacitive sensing channels */
+#  define STM32_NPORTS          6  /* Six GPIO ports, GPIOA-E, H */
+
+#elif defined(CONFIG_ARCH_CHIP_STM32L071C8) || defined(CONFIG_ARCH_CHIP_STM32L071V8) || \
+      defined(CONFIG_ARCH_CHIP_STM32L071CB) || defined(CONFIG_ARCH_CHIP_STM32L071VB) || \
+      defined(CONFIG_ARCH_CHIP_STM32L071RB) || defined(CONFIG_ARCH_CHIP_STM32L071CZ) || \
+      defined(CONFIG_ARCH_CHIP_STM32L071VZ) || defined(CONFIG_ARCH_CHIP_STM32L071RZ)
+#  define STM32_NATIM           0  /* 0 advanced timers */
+#  define STM32_NGTIM16         4  /* 16-bit general up/down timers TIM2-3
+                                    * (with DMA) and TIM21-22 without DMA */
+#  define STM32_NGTIM32         0  /* 0 32-bit general up/down timers */
+#  define STM32_NBTIM           2  /* 2 basic timers: TIM6, TIM7 with DMA */
+                                   /* 1 LPTIMER */
+#  define STM32_NSPI            2  /* 2 SPI modules SPI1-2 */
+#  define STM32_NI2S            1  /* 1 I2S module */
+#  define STM32_NI2C            3  /* 3 I2C */
+#  define STM32_NDMA            1  /* 1 DMA1, 7-channels */
+#  define STM32_NUSART          4  /* 4 USART modules, USART1-4 */
+                                   /* 1 LPUART */
+#  define STM32_NCAN            0  /* 0 CAN controllers */
+#  define STM32_NLCD            0  /* 0 LCD */
+#  define STM32_NUSBDEV         0  /* 0 USB full-speed device controller */
+#  define STM32_NUSBOTG         0  /* 0 USB OTG FS/HS (only USB 2.0 device) */
+#  define STM32_NCEC            0  /* 0 HDMI-CEC controller */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            0  /* 0 DAC channel */
+#  define STM32_NCOMP           2  /* 2 Analog Comparators */
+#  define STM32_NCRC            0  /* 0 CRC module */
+#  define STM32_NRNG            0  /* 0 Random number generator (RNG) */
+#  define STM32_NCAP            0  /* 0 Capacitive sensing channels */
+#  define STM32_NPORTS          6  /* Six GPIO ports, GPIOA-E, H */
+
+#elif defined(CONFIG_ARCH_CHIP_STM32L071KB) || defined(CONFIG_ARCH_CHIP_STM32L071KZ)
+#  define STM32_NATIM           0  /* 0 advanced timers */
+#  define STM32_NGTIM16         4  /* 16-bit general up/down timers TIM2-3
+                                    * (with DMA) and TIM21-22 without DMA */
+#  define STM32_NGTIM32         0  /* 0 32-bit general up/down timers */
+#  define STM32_NBTIM           2  /* 2 basic timers: TIM6, TIM7 with DMA */
+                                   /* 1 LPTIMER */
+#  define STM32_NSPI            1  /* 1 SPI modules SPI1 */
+#  define STM32_NI2S            0  /* 0 I2S module */
+#  define STM32_NI2C            3  /* 3 I2C */
+#  define STM32_NDMA            1  /* 1 DMA1, 7-channels */
+#  define STM32_NUSART          4  /* 4 USART modules, USART1-4 */
+                                   /* 1 LPUART */
+#  define STM32_NCAN            0  /* 0 CAN controllers */
+#  define STM32_NLCD            0  /* 0 LCD */
+#  define STM32_NUSBDEV         0  /* 0 USB full-speed device controller */
+#  define STM32_NUSBOTG         0  /* 0 USB OTG FS/HS (only USB 2.0 device) */
+#  define STM32_NCEC            0  /* 0 HDMI-CEC controller */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            0  /* 0 DAC channel */
+#  define STM32_NCOMP           2  /* 2 Analog Comparators */
+#  define STM32_NCRC            0  /* 0 CRC module */
+#  define STM32_NRNG            0  /* 0 Random number generator (RNG) */
+#  define STM32_NCAP            0  /* 0 Capacitive sensing channels */
+#  define STM32_NPORTS          6  /* Six GPIO ports, GPIOA-E, H */
+
 #elif defined(CONFIG_ARCH_CHIP_STM32L072V8) || defined(CONFIG_ARCH_CHIP_STM32L072VB) || \
       defined(CONFIG_ARCH_CHIP_STM32L072VZ)
 #  define STM32_NATIM           0  /* No advanced timers */
@@ -255,11 +361,8 @@
 #  define STM32_NUSBDEV         0  /* No USB full-speed device controller */
 #  define STM32_NUSBOTG         1  /* One USB OTG FS/HS (only USB 2.0 device) */
 #  define STM32_NCEC            0  /* No HDMI-CEC controller */
-#  define STM32_NADC12          1  /* One 12-bit ADC module */
-#  define STM32_NADCCHAN        14 /* 14 channels */
-#  define STM32_NADCINT         0  /* ? internal channels vs external? */
-#  define STM32_NDAC            2  /* Two DAC module */
-#  define STM32_NDACCHAN        2  /* Two DAC channels */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            2  /* Two DAC channels */
 #  define STM32_NCOMP           2  /* Two Analog Comparators */
 #  define STM32_NCRC            1  /* One CRC module */
 #  define STM32_NRNG            1  /* One Random number generator (RNG) */
@@ -283,9 +386,8 @@
 #  define STM32_NUSBDEV         0  /* No USB full-speed device controller */
 #  define STM32_NUSBOTG         1  /* One USB OTG FS/HS (only USB 2.0 device) */
 #  define STM32_NCEC            0  /* No HDMI-CEC controller */
-#  define STM32_NADC                     1   /* (1) ADC1, 14-channels */
-#  define STM32_NDAC            2  /* Two DAC module */
-#  define STM32_NDACCHAN        2  /* Two DAC channels */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            2  /* Two DAC channels */
 #  define STM32_NCOMP           2  /* Two Analog Comparators */
 #  define STM32_NCRC            1  /* One CRC module */
 #  define STM32_NRNG            1  /* One Random number generator (RNG) */
@@ -310,11 +412,8 @@
 #  define STM32_NUSBDEV         0  /* No USB full-speed device controller */
 #  define STM32_NUSBOTG         1  /* One USB OTG FS/HS (only USB 2.0 device) */
 #  define STM32_NCEC            0  /* No HDMI-CEC controller */
-#  define STM32_NADC12          1  /* One 12-bit ADC module */
-#  define STM32_NADCCHAN        14 /* 14 channels */
-#  define STM32_NADCINT         0  /* ? internal channels vs external? */
-#  define STM32_NDAC            2  /* Two DAC module */
-#  define STM32_NDACCHAN        2  /* Two DAC channels */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            2  /* Two DAC channels */
 #  define STM32_NCOMP           2  /* Two Analog Comparators */
 #  define STM32_NCRC            1  /* One CRC module */
 #  define STM32_NRNG            1  /* One Random number generator (RNG) */
@@ -339,11 +438,8 @@
 #  define STM32_NUSBDEV         0  /* No USB full-speed device controller */
 #  define STM32_NUSBOTG         1  /* One USB OTG FS/HS (only USB 2.0 device) */
 #  define STM32_NCEC            0  /* No HDMI-CEC controller */
-#  define STM32_NADC12          1  /* One 12-bit ADC module */
-#  define STM32_NADCCHAN        14 /* 14 channels */
-#  define STM32_NADCINT         0  /* ? internal channels vs external? */
-#  define STM32_NDAC            2  /* Two DAC module */
-#  define STM32_NDACCHAN        2  /* Two DAC channels */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            2  /* Two DAC channels */
 #  define STM32_NCOMP           2  /* Two Analog Comparators */
 #  define STM32_NCRC            1   /* One CRC module */
 #  define STM32_NRNG            1  /* One Random number generator (RNG) */
@@ -369,11 +465,8 @@
 #  define STM32_NUSBDEV         0  /* No USB full-speed device controller */
 #  define STM32_NUSBOTG         1  /* One USB OTG FS/HS (only USB 2.0 device) */
 #  define STM32_NCEC            0  /* No HDMI-CEC controller */
-#  define STM32_NADC12          1  /* One 12-bit ADC module */
-#  define STM32_NADCCHAN        14 /* 14 channels */
-#  define STM32_NADCINT         0  /* ? internal channels vs external? */
-#  define STM32_NDAC            2  /* Two DAC module */
-#  define STM32_NDACCHAN        2  /* Two DAC channels */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            2  /* Two DAC channels */
 #  define STM32_NCOMP           2  /* Two Analog Comparators */
 #  define STM32_NCRC            1  /* One CRC module */
 #  define STM32_NRNG            1  /* One Random number generator (RNG) */
@@ -398,11 +491,8 @@
 #  define STM32_NUSBDEV         0  /* No USB full-speed device controller */
 #  define STM32_NUSBOTG         1  /* One USB OTG FS/HS (only USB 2.0 device) */
 #  define STM32_NCEC            0  /* No HDMI-CEC controller */
-#  define STM32_NADC12          1  /* One 12-bit ADC module */
-#  define STM32_NADCCHAN        14 /* 14 channels */
-#  define STM32_NADCINT         0  /* ? internal channels vs external? */
-#  define STM32_NDAC            2  /* Two DAC module */
-#  define STM32_NDACCHAN        2  /* Two DAC channels */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            2  /* Two DAC channels */
 #  define STM32_NCOMP           2  /* Two Analog Comparators */
 #  define STM32_NCRC            1   /* One CRC module */
 #  define STM32_NRNG            1  /* One Random number generator (RNG) */
@@ -427,11 +517,8 @@
 #  define STM32_NUSBDEV         0  /* No USB full-speed device controller */
 #  define STM32_NUSBOTG         1  /* One USB OTG FS/HS (only USB 2.0 device) */
 #  define STM32_NCEC            0  /* No HDMI-CEC controller */
-#  define STM32_NADC12          1  /* One 12-bit ADC module */
-#  define STM32_NADCCHAN        14 /* 14 channels */
-#  define STM32_NADCINT         0  /* ? internal channels vs external? */
-#  define STM32_NDAC            2  /* Two DAC module */
-#  define STM32_NDACCHAN        2  /* Two DAC channels */
+#  define STM32_NADC            1  /* One 12-bit module */
+#  define STM32_NDAC            2  /* Two DAC channels */
 #  define STM32_NCOMP           2  /* Two Analog Comparators */
 #  define STM32_NCRC            1  /* One CRC module */
 #  define STM32_NRNG            1  /* One Random number generator (RNG) */
@@ -465,4 +552,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_CHIP_H */
+#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H */
diff --git a/arch/arm/include/stm32f0l0/irq.h b/arch/arm/include/stm32f0l0g0/irq.h
similarity index 93%
rename from arch/arm/include/stm32f0l0/irq.h
rename to arch/arm/include/stm32f0l0g0/irq.h
index f168747afde..61c63c4f805 100644
--- a/arch/arm/include/stm32f0l0/irq.h
+++ b/arch/arm/include/stm32f0l0g0/irq.h
@@ -38,8 +38,8 @@
  * through nuttx/irq.h
  */
 
-#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H
-#define __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H
+#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H
 
 /****************************************************************************
  * Included Files
@@ -48,7 +48,7 @@
 #ifndef __ASSEMBLY__
 #  include 
 #endif
-#include 
+#include 
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -79,9 +79,11 @@
 /* Include MCU-specific external interrupt definitions */
 
 #if defined(CONFIG_ARCH_CHIP_STM32F0)
-#  include 
+#  include 
 #elif defined(CONFIG_ARCH_CHIP_STM32L0)
-#  include 
+#  include 
+#elif defined(CONFIG_ARCH_CHIP_STM32G0)
+#  include 
 #else
 #  error Unrecognized STM32 Cortex M0 family
 #endif
@@ -117,4 +119,4 @@ extern "C"
 #endif
 #endif /* __ASSEMBLY__ */
 
-#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_IRQ_H */
+#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H */
diff --git a/arch/arm/include/stm32f0l0/stm32f0_irq.h b/arch/arm/include/stm32f0l0g0/stm32f0_irq.h
similarity index 56%
rename from arch/arm/include/stm32f0l0/stm32f0_irq.h
rename to arch/arm/include/stm32f0l0g0/stm32f0_irq.h
index 52ad609a938..3ba8a1eef0a 100644
--- a/arch/arm/include/stm32f0l0/stm32f0_irq.h
+++ b/arch/arm/include/stm32f0l0g0/stm32f0_irq.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/include/stm32f0l0/stm32f0_irq.h
+ * arch/arm/include/stm32f0l0g0/stm32f0_irq.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -38,8 +38,8 @@
  * through nuttx/irq.h
  */
 
-#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H
-#define __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H
+#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H
 
 /****************************************************************************
  * Included Files
@@ -47,7 +47,7 @@
 
 #include 
 #include 
-#include 
+#include 
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -58,7 +58,7 @@
  * to handle mapping tables.
  *
  * Processor Exceptions (vectors 0-15).  These common definitions can be found
- * in nuttx/arch/arm/include/stm32f0l0/irq.h
+ * in nuttx/arch/arm/include/stm32f0l0g0/irq.h
  */
 
 #define STM32_IRQ_WWDG          (STM32_IRQ_EXTINT + 0)  /* 0: WWDG */
@@ -70,29 +70,46 @@
 #define STM32_IRQ_EXTI2_3       (STM32_IRQ_EXTINT + 6)  /* 6: EXTI2_3 */
 #define STM32_IRQ_EXTI4_15      (STM32_IRQ_EXTINT + 7)  /* 7: EXTI4_15 */
 #define STM32_IRQ_TSC           (STM32_IRQ_EXTINT + 8)  /* 8: TSC */
-#define STM32_IRQ_DMA_CH1       (STM32_IRQ_EXTINT + 9)  /* 9: DMA_CH1 */
-#define STM32_IRQ_DMA_CH23      (STM32_IRQ_EXTINT + 10) /* 0: DMA_CH2_3 and DMA2_CH1_2 */
-#define STM32_IRQ_DMA_CH4567    (STM32_IRQ_EXTINT + 11) /* 1: DMA_CH4_5_6_7 and DMA2_CH3_4_5 */
-#define STM32_IRQ_ADC_COMP      (STM32_IRQ_EXTINT + 12) /* 2: ADC_COMP */
-#define STM32_IRQ_TIM1_BRK      (STM32_IRQ_EXTINT + 13) /* 3: TIM1_BRK_UP_TRG_COM */
-#define STM32_IRQ_TIM1_CC       (STM32_IRQ_EXTINT + 14) /* 4: TIM1_CC */
-#define STM32_IRQ_TIM2          (STM32_IRQ_EXTINT + 15) /* 5: TIM2 */
-#define STM32_IRQ_TIM3          (STM32_IRQ_EXTINT + 16) /* 6: TIM3 */
-#define STM32_IRQ_TIM6_DAC      (STM32_IRQ_EXTINT + 17) /* 7: TIM6 and DAC */
-#define STM32_IRQ_TIM7          (STM32_IRQ_EXTINT + 18) /* 8: TIM7 */
-#define STM32_IRQ_TIM14         (STM32_IRQ_EXTINT + 19) /* 9: TIM14 */
-#define STM32_IRQ_TIM15         (STM32_IRQ_EXTINT + 20) /* 0: TIM15 */
-#define STM32_IRQ_TIM16         (STM32_IRQ_EXTINT + 21) /* 1: TIM16 */
-#define STM32_IRQ_TIM17         (STM32_IRQ_EXTINT + 22) /* 2: TIM17 */
-#define STM32_IRQ_I2C1          (STM32_IRQ_EXTINT + 23) /* 3: I2C1 */
-#define STM32_IRQ_I2C2          (STM32_IRQ_EXTINT + 24) /* 4: I2C2 */
-#define STM32_IRQ_SPI1          (STM32_IRQ_EXTINT + 25) /* 5: SPI1 */
-#define STM32_IRQ_SPI2          (STM32_IRQ_EXTINT + 26) /* 6: SPI2 */
-#define STM32_IRQ_USART1        (STM32_IRQ_EXTINT + 27) /* 7: USART1 */
-#define STM32_IRQ_USART2        (STM32_IRQ_EXTINT + 28) /* 8: USART2 */
-#define STM32_IRQ_USART345678   (STM32_IRQ_EXTINT + 29) /* 9: USART3_4_5_6_7_8 */
-#define STM32_IRQ_CEC_CAN       (STM32_IRQ_EXTINT + 30) /* 0: HDMI CEC and CAN */
-#define STM32_IRQ_USB           (STM32_IRQ_EXTINT + 31) /* 1: USB */
+#define STM32_IRQ_DMA1CH1       (STM32_IRQ_EXTINT + 9)  /* 9: DMA1_CH1 */
+#define STM32_IRQ_DMA1CH2       (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH2 */
+#define STM32_IRQ_DMA1CH3       (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH3 */
+#define STM32_IRQ_DMA2CH1       (STM32_IRQ_EXTINT + 10) /* 10: DMA2_CH1 */
+#define STM32_IRQ_DMA2CH2       (STM32_IRQ_EXTINT + 10) /* 10: DMA2_CH2 */
+#define STM32_IRQ_DMA1CH4       (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH4 */
+#define STM32_IRQ_DMA1CH5       (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH5 */
+#define STM32_IRQ_DMA1CH6       (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */
+#define STM32_IRQ_DMA1CH7       (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */
+#define STM32_IRQ_DMA2CH3       (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH3 */
+#define STM32_IRQ_DMA2CH4       (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH4 */
+#define STM32_IRQ_DMA2CH5       (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH5 */
+#define STM32_IRQ_ADC           (STM32_IRQ_EXTINT + 12) /* 12: ADC */
+#define STM32_IRQ_COMP          (STM32_IRQ_EXTINT + 12) /* 12: COMP */
+#define STM32_IRQ_TIM1_BRK      (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */
+#define STM32_IRQ_TIM1_CC       (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */
+#define STM32_IRQ_TIM2          (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */
+#define STM32_IRQ_TIM3          (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */
+#define STM32_IRQ_TIM6          (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */
+#define STM32_IRQ_DAC           (STM32_IRQ_EXTINT + 17) /* 17: DAC */
+#define STM32_IRQ_TIM7          (STM32_IRQ_EXTINT + 18) /* 18: TIM7 */
+#define STM32_IRQ_TIM14         (STM32_IRQ_EXTINT + 19) /* 19: TIM14 */
+#define STM32_IRQ_TIM15         (STM32_IRQ_EXTINT + 20) /* 20: TIM15 */
+#define STM32_IRQ_TIM16         (STM32_IRQ_EXTINT + 21) /* 21: TIM16 */
+#define STM32_IRQ_TIM17         (STM32_IRQ_EXTINT + 22) /* 22: TIM17 */
+#define STM32_IRQ_I2C1          (STM32_IRQ_EXTINT + 23) /* 23: I2C1 */
+#define STM32_IRQ_I2C2          (STM32_IRQ_EXTINT + 24) /* 24: I2C2 */
+#define STM32_IRQ_SPI1          (STM32_IRQ_EXTINT + 25) /* 25: SPI1 */
+#define STM32_IRQ_SPI2          (STM32_IRQ_EXTINT + 26) /* 26: SPI2 */
+#define STM32_IRQ_USART1        (STM32_IRQ_EXTINT + 27) /* 27: USART1 */
+#define STM32_IRQ_USART2        (STM32_IRQ_EXTINT + 28) /* 28: USART2 */
+#define STM32_IRQ_USART3        (STM32_IRQ_EXTINT + 29) /* 29: USART3 */
+#define STM32_IRQ_USART4        (STM32_IRQ_EXTINT + 29) /* 29: USART4 */
+#define STM32_IRQ_USART5        (STM32_IRQ_EXTINT + 29) /* 29: USART5 */
+#define STM32_IRQ_USART6        (STM32_IRQ_EXTINT + 29) /* 29: USART6 */
+#define STM32_IRQ_USART7        (STM32_IRQ_EXTINT + 29) /* 29: USART7 */
+#define STM32_IRQ_USART8        (STM32_IRQ_EXTINT + 29) /* 29: USART8 */
+#define STM32_IRQ_CEC           (STM32_IRQ_EXTINT + 30) /* 30: HDMI CEC */
+#define STM32_IRQ_CAN           (STM32_IRQ_EXTINT + 30) /* 30: HDMI CAN */
+#define STM32_IRQ_USB           (STM32_IRQ_EXTINT + 31) /* 31: USB */
 
 #define STM32_IRQ_NEXTINT       (32) /* 32 external interrupts */
 
@@ -125,4 +142,4 @@ extern "C"
 #endif
 #endif /* __ASSEMBLY__ */
 
-#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H */
+#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H */
diff --git a/arch/arm/include/stm32f0l0g0/stm32g0_irq.h b/arch/arm/include/stm32f0l0g0/stm32g0_irq.h
new file mode 100644
index 00000000000..0b646f33d66
--- /dev/null
+++ b/arch/arm/include/stm32f0l0g0/stm32g0_irq.h
@@ -0,0 +1,142 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32f0l0g0/stm32g0_irq.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include 
+#include 
+#include 
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to
+ * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
+ * to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15).  These common definitions can be found
+ * in nuttx/arch/arm/include/stm32f0l0g0/irq.h
+ */
+
+#define STM32_IRQ_WWDG        (STM32_IRQ_EXTINT + 0)  /* 0: Window Watchdog interrupt */
+#define STM32_IRQ_PVD         (STM32_IRQ_EXTINT + 1)  /* 1: PVD through EXTI Line detection interrupt */
+#define STM32_IRQ_RTC         (STM32_IRQ_EXTINT + 2)  /* 2: RTC */
+#define STM32_IRQ_FLASH       (STM32_IRQ_EXTINT + 3)  /* 3: Flash */
+#define STM32_IRQ_RCC         (STM32_IRQ_EXTINT + 4)  /* 4: RCC */
+#define STM32_IRQ_EXTI0_1     (STM32_IRQ_EXTINT + 5)  /* 5: EXTI0_1 */
+#define STM32_IRQ_EXTI2_3     (STM32_IRQ_EXTINT + 6)  /* 6: EXTI2_3 */
+#define STM32_IRQ_EXTI4_15    (STM32_IRQ_EXTINT + 7)  /* 7: EXTI4_15 */
+#define STM32_IRQ_UCPD12      (STM32_IRQ_EXTINT + 8)  /* 8: UCPD1_2 */
+#define STM32_IRQ_EXTI32_33   (STM32_IRQ_EXTINT + 8)  /* 8: EXTI_32_33 */
+#define STM32_IRQ_DMA1CH1     (STM32_IRQ_EXTINT + 9)  /* 9: DMA1_CH1 */
+#define STM32_IRQ_DMA1CH2     (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH2 */
+#define STM32_IRQ_DMA1CH3     (STM32_IRQ_EXTINT + 10) /* 10: DMA1_CH3 */
+#define STM32_IRQ_DMA1CH4     (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH4 */
+#define STM32_IRQ_DMA1CH5     (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH5 */
+#define STM32_IRQ_DMA1CH6     (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */
+#define STM32_IRQ_DMA1CH7     (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */
+#define STM32_IRQ_DMAMUX      (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */
+#define STM32_IRQ_ADC         (STM32_IRQ_EXTINT + 12) /* 12: ADC */
+#define STM32_IRQ_EXTI17_18   (STM32_IRQ_EXTINT + 12) /* 12: EXTI_17_18 */
+#define STM32_IRQ_COMP        (STM32_IRQ_EXTINT + 12) /* 12: COMP */
+#define STM32_IRQ_TIM1_BRK    (STM32_IRQ_EXTINT + 13) /* 13: TIM1_BRK_UP_TRG_COM */
+#define STM32_IRQ_TIM1_CC     (STM32_IRQ_EXTINT + 14) /* 14: TIM1_CC */
+#define STM32_IRQ_TIM2        (STM32_IRQ_EXTINT + 15) /* 15: TIM2 */
+#define STM32_IRQ_TIM3        (STM32_IRQ_EXTINT + 16) /* 16: TIM3 */
+#define STM32_IRQ_TIM6        (STM32_IRQ_EXTINT + 17) /* 17: TIM6 */
+#define STM32_IRQ_DAC         (STM32_IRQ_EXTINT + 17) /* 17: DAC */
+#define STM32_IRQ_LPTIM1      (STM32_IRQ_EXTINT + 17) /* 17: LPTIM1 */
+#define STM32_IRQ_TIM7        (STM32_IRQ_EXTINT + 18) /* 18: TIM7 */
+#define STM32_IRQ_LPTIM2      (STM32_IRQ_EXTINT + 18) /* 18: LPTIM2 */
+#define STM32_IRQ_TIM14       (STM32_IRQ_EXTINT + 19) /* 19: TIM14 */
+#define STM32_IRQ_TIM15       (STM32_IRQ_EXTINT + 20) /* 20: TIM15 */
+#define STM32_IRQ_TIM16       (STM32_IRQ_EXTINT + 21) /* 21: TIM16 */
+#define STM32_IRQ_TIM17       (STM32_IRQ_EXTINT + 22) /* 22: TIM17 */
+#define STM32_IRQ_I2C1        (STM32_IRQ_EXTINT + 23) /* 23: I2C1 */
+#define STM32_IRQ_EXTI23      (STM32_IRQ_EXTINT + 23) /* 23: EXTI_23 */
+#define STM32_IRQ_I2C2        (STM32_IRQ_EXTINT + 24) /* 24: I2C2 */
+#define STM32_IRQ_SPI1        (STM32_IRQ_EXTINT + 25) /* 25: SPI1 */
+#define STM32_IRQ_SPI2        (STM32_IRQ_EXTINT + 26) /* 26: SPI2 */
+#define STM32_IRQ_USART1      (STM32_IRQ_EXTINT + 27) /* 27: USART1 */
+#define STM32_IRQ_EXTI25      (STM32_IRQ_EXTINT + 27) /* 27: EXTI_25 */
+#define STM32_IRQ_USART2      (STM32_IRQ_EXTINT + 28) /* 28: USART2  */
+#define STM32_IRQ_EXTI26      (STM32_IRQ_EXTINT + 28) /* 28: EXTI_26 */
+#define STM32_IRQ_USART3      (STM32_IRQ_EXTINT + 29) /* 29: USART3 */
+#define STM32_IRQ_USART4      (STM32_IRQ_EXTINT + 29) /* 29: USART4 */
+#define STM32_IRQ_LPUART1     (STM32_IRQ_EXTINT + 29) /* 29: LPUART1 */
+#define STM32_IRQ_EXTI28      (STM32_IRQ_EXTINT + 29) /* 29: EXTI_28 */
+#define STM32_IRQ_CEC         (STM32_IRQ_EXTINT + 30) /* 30: HDMI CEC */
+#define STM32_IRQ_EXTI27      (STM32_IRQ_EXTINT + 30) /* 30: EXTI_27 */
+#define STM32_IRQ_AES         (STM32_IRQ_EXTINT + 31) /* 31: AES */
+#define STM32_IRQ_RNG         (STM32_IRQ_EXTINT + 31) /* 31: RNG */
+
+#define STM32_IRQ_NEXTINT     (32)
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+****************************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H */
diff --git a/arch/arm/include/stm32f0l0/stm32l0_irq.h b/arch/arm/include/stm32f0l0g0/stm32l0_irq.h
similarity index 96%
rename from arch/arm/include/stm32f0l0/stm32l0_irq.h
rename to arch/arm/include/stm32f0l0g0/stm32l0_irq.h
index 704309bcc4c..236d10d3342 100644
--- a/arch/arm/include/stm32f0l0/stm32l0_irq.h
+++ b/arch/arm/include/stm32f0l0g0/stm32l0_irq.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/include/stm32f0l0/stm32_irq.h
+ * arch/arm/include/stm32f0l0g0/stm32l0_irq.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -35,8 +35,8 @@
 
 /* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
 
-#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_STM32L0_IRQ_H
-#define __ARCH_ARM_INCLUDE_STM32F0L0_STM32L0_IRQ_H
+#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H
 
 /****************************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 
 #include 
 #include 
-#include 
+#include 
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -55,7 +55,7 @@
  * to handle mapping tables.
  *
  * Processor Exceptions (vectors 0-15).  These common definitions can be found
- * in nuttx/arch/arm/include/stm32f0l0/irq.h
+ * in nuttx/arch/arm/include/stm32f0l0g0/irq.h
  */
 
 #define STM32_IRQ_WWDG        (STM32_IRQ_EXTINT + 0)  /* 0:  Window Watchdog interrupt */
@@ -129,4 +129,4 @@ extern "C"
 #endif
 #endif
 
-#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_STM32L0_IRQ_H */
+#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H */
diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h
index ab3e999dfcf..a1b7ffe5269 100644
--- a/arch/arm/include/stm32h7/chip.h
+++ b/arch/arm/include/stm32h7/chip.h
@@ -122,17 +122,21 @@
 
 /* Diversification based on Family and package */
 
-// TODO:
-// #if defined(CONFIG_STM32F7_HAVE_FMC)
-// #  define STM32F7_NFMC                 1           /* Have FMC memory controller */
-// #else
-// #  define STM32F7_NFMC                 0           /* No FMC memory controller */
-// #endif
+#if defined(CONFIG_STM32H7_HAVE_ETHERNET)
+#  define STM32H7_NETHERNET                1   /* 100/100 Ethernet MAC */
+#else
+#  define STM32H7_NETHERNET                0   /* No 100/100 Ethernet MAC */
+#endif
 
-/* NVIC priority levels *************************************************************/
+#if defined(CONFIG_STM32F7_HAVE_FMC)
+#  define STM32F7_NFMC                     1   /* Have FMC memory controller */
+#else
+#  define STM32F7_NFMC                     0   /* No FMC memory controller */
+#endif
+
+/* NVIC priority levels **********************************************************o***/
 /* 16 Programmable interrupt levels */
 
-// TODO: check this
 #define NVIC_SYSH_PRIORITY_MIN     0xf0 /* All bits set in minimum priority */
 #define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
 #define NVIC_SYSH_PRIORITY_MAX     0x00 /* Zero is maximum priority */
diff --git a/arch/arm/src/a1x/a1x_irq.h b/arch/arm/src/a1x/a1x_irq.h
index ad0925707c5..d3633839f14 100644
--- a/arch/arm/src/a1x/a1x_irq.h
+++ b/arch/arm/src/a1x/a1x_irq.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/a1x_intc.h"
+#include "hardware/a1x_intc.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/a1x/a1x_lowputc.c b/arch/arm/src/a1x/a1x_lowputc.c
index e3f682da880..9085aa122a9 100644
--- a/arch/arm/src/a1x/a1x_lowputc.c
+++ b/arch/arm/src/a1x/a1x_lowputc.c
@@ -48,7 +48,7 @@
 #include "up_arch.h"
 
 #include "a1x_config.h"
-#include "chip/a1x_uart.h"
+#include "hardware/a1x_uart.h"
 #include "a1x_pio.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/a1x/a1x_pio.c b/arch/arm/src/a1x/a1x_pio.c
index 8016b007594..5c5ba699d25 100644
--- a/arch/arm/src/a1x/a1x_pio.c
+++ b/arch/arm/src/a1x/a1x_pio.c
@@ -53,7 +53,7 @@
 
 #include "chip.h"
 #include "a1x_pio.h"
-#include "chip/a1x_pio.h"
+#include "hardware/a1x_pio.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/a1x/a1x_pio.h b/arch/arm/src/a1x/a1x_pio.h
index de69d4c3e1b..46622824374 100644
--- a/arch/arm/src/a1x/a1x_pio.h
+++ b/arch/arm/src/a1x/a1x_pio.h
@@ -45,7 +45,7 @@
 #include 
 #include 
 
-#include "chip/a1x_pio.h"
+#include "hardware/a1x_pio.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/a1x/a1x_serial.c b/arch/arm/src/a1x/a1x_serial.c
index 0107b4e248f..a77786604ee 100644
--- a/arch/arm/src/a1x/a1x_serial.c
+++ b/arch/arm/src/a1x/a1x_serial.c
@@ -62,7 +62,7 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/a1x_uart.h"
+#include "hardware/a1x_uart.h"
 #include "a1x_pio.h"
 #include "a1x_serial.h"
 
diff --git a/arch/arm/src/a1x/a1x_serial.h b/arch/arm/src/a1x/a1x_serial.h
index 47957ac12d4..ffef0794858 100644
--- a/arch/arm/src/a1x/a1x_serial.h
+++ b/arch/arm/src/a1x/a1x_serial.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/a1x_uart.h"
+#include "hardware/a1x_uart.h"
 
 #include "a1x_config.h"
 #include "a1x_pio.h"
diff --git a/arch/arm/src/a1x/a1x_timerisr.c b/arch/arm/src/a1x/a1x_timerisr.c
index 978cfcdd58e..071389eedea 100644
--- a/arch/arm/src/a1x/a1x_timerisr.c
+++ b/arch/arm/src/a1x/a1x_timerisr.c
@@ -49,7 +49,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/a1x_timer.h"
+#include "hardware/a1x_timer.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/a1x/chip.h b/arch/arm/src/a1x/chip.h
index 31521e2d0a4..516536ba6d2 100644
--- a/arch/arm/src/a1x/chip.h
+++ b/arch/arm/src/a1x/chip.h
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/a1x_memorymap.h"
+#include "hardware/a1x_memorymap.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/a1x/chip/a10_memorymap.h b/arch/arm/src/a1x/hardware/a10_memorymap.h
similarity index 99%
rename from arch/arm/src/a1x/chip/a10_memorymap.h
rename to arch/arm/src/a1x/hardware/a10_memorymap.h
index a4e5d669c94..eee9cbca165 100644
--- a/arch/arm/src/a1x/chip/a10_memorymap.h
+++ b/arch/arm/src/a1x/hardware/a10_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/a1x/a10_memorymap.h
+ * arch/arm/src/a1x/hardware/a10_memorymap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_A1X_CHIP_A10_MEMORYMAP_H
-#define __ARCH_ARM_SRC_A1X_CHIP_A10_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A10_MEMORYMAP_H
+#define __ARCH_ARM_SRC_A1X_HARDWARE_A10_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -615,4 +615,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_A1X_CHIP_A10_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_A1X_HARDWARE_A10_MEMORYMAP_H */
diff --git a/arch/arm/src/a1x/chip/a10_piocfg.h b/arch/arm/src/a1x/hardware/a10_piocfg.h
similarity index 99%
rename from arch/arm/src/a1x/chip/a10_piocfg.h
rename to arch/arm/src/a1x/hardware/a10_piocfg.h
index 3ed6a652dbc..12fd23c7927 100644
--- a/arch/arm/src/a1x/chip/a10_piocfg.h
+++ b/arch/arm/src/a1x/hardware/a10_piocfg.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/a1x/chip/a10_piocfg.h
+ * arch/arm/src/a1x/hardware/a10_piocfg.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_A1X_CHIP_A10_PIOCFG_H
-#define __ARCH_ARM_SRC_A1X_CHIP_A10_PIOCFG_H
+#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A10_PIOCFG_H
+#define __ARCH_ARM_SRC_A1X_HARDWARE_A10_PIOCFG_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/a1x_memorymap.h"
+#include "hardware/a1x_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -609,4 +609,4 @@
 #define PIO_UART7_TX_1    (PIO_PERIPH3 | PIO_PORT_PIOI | PIO_PIN20)
 #define PIO_UART7_TX_2    (PIO_PERIPH3 | PIO_PORT_PIOA | PIO_PIN14)
 
-#endif /* __ARCH_ARM_SRC_A1X_CHIP_A10_PIOCFG_H */
+#endif /* __ARCH_ARM_SRC_A1X_HARDWARE_A10_PIOCFG_H */
diff --git a/arch/arm/src/a1x/chip/a1x_intc.h b/arch/arm/src/a1x/hardware/a1x_intc.h
similarity index 97%
rename from arch/arm/src/a1x/chip/a1x_intc.h
rename to arch/arm/src/a1x/hardware/a1x_intc.h
index 86bdc911c88..0c3cd0eb3d7 100644
--- a/arch/arm/src/a1x/chip/a1x_intc.h
+++ b/arch/arm/src/a1x/hardware/a1x_intc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/a1x/chip/a1x_intc.h
+ * arch/arm/src/a1x/hardware/a1x_intc.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_A1X_CHIP_A1X_INTC_H
-#define __ARCH_ARM_SRC_A1X_CHIP_A1X_INTC_H
+#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A1X_INTC_H
+#define __ARCH_ARM_SRC_A1X_HARDWARE_A1X_INTC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/a1x_memorymap.h"
+#include "hardware/a1x_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -203,4 +203,4 @@
 #define INTC_PRIO_MASK(n)            (3 << INTC_PRIO_SHIFT(n))
 #  define INTC_PRIO(n,p)             ((uint32_t)(p) << INTC_PRIO_SHIFT(n))
 
-#endif /* __ARCH_ARM_SRC_A1X_CHIP_A1X_INTC_H */
+#endif /* __ARCH_ARM_SRC_A1X_HARDWARE_A1X_INTC_H */
diff --git a/arch/arm/src/a1x/chip/a1x_memorymap.h b/arch/arm/src/a1x/hardware/a1x_memorymap.h
similarity index 89%
rename from arch/arm/src/a1x/chip/a1x_memorymap.h
rename to arch/arm/src/a1x/hardware/a1x_memorymap.h
index 154a1641ba4..b791115ac68 100644
--- a/arch/arm/src/a1x/chip/a1x_memorymap.h
+++ b/arch/arm/src/a1x/hardware/a1x_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/a1x/chip/a1x_memorymap.h
+ * arch/arm/src/a1x/hardware/a1x_memorymap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_A1X_CHIP_A1X_MEMORYMAP_H
-#define __ARCH_ARM_SRC_A1X_CHIP_A1X_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A1X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_A1X_HARDWARE_A1X_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -44,9 +44,9 @@
 #include 
 
 #if defined(CONFIG_ARCH_CHIP_A10)
-#  include "chip/a10_memorymap.h"
+#  include "hardware/a10_memorymap.h"
 #else
 #  error Unrecognized A1X architecture
 #endif
 
-#endif /* __ARCH_ARM_SRC_A1X_CHIP_A1X_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_A1X_HARDWARE_A1X_MEMORYMAP_H */
diff --git a/arch/arm/src/a1x/chip/a1x_pio.h b/arch/arm/src/a1x/hardware/a1x_pio.h
similarity index 97%
rename from arch/arm/src/a1x/chip/a1x_pio.h
rename to arch/arm/src/a1x/hardware/a1x_pio.h
index 48cc2bd9d78..ccb619e93f2 100644
--- a/arch/arm/src/a1x/chip/a1x_pio.h
+++ b/arch/arm/src/a1x/hardware/a1x_pio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/a1x/chip/a1x_pio.h
+ * arch/arm/src/a1x/hardware/a1x_pio.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_A1X_CHIP_A1X_PIO_H
-#define __ARCH_ARM_SRC_A1X_CHIP_A1X_PIO_H
+#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A1X_PIO_H
+#define __ARCH_ARM_SRC_A1X_HARDWARE_A1X_PIO_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/a1x_memorymap.h"
+#include "hardware/a1x_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -217,4 +217,4 @@
 /* SDRAM Pad Pull Register */
 /* REVISIT: Missing register bit definitions */
 
-#endif /* __ARCH_ARM_SRC_A1X_CHIP_A1X_PIO_H */
+#endif /* __ARCH_ARM_SRC_A1X_HARDWARE_A1X_PIO_H */
diff --git a/arch/arm/src/a1x/chip/a1x_piocfg.h b/arch/arm/src/a1x/hardware/a1x_piocfg.h
similarity index 90%
rename from arch/arm/src/a1x/chip/a1x_piocfg.h
rename to arch/arm/src/a1x/hardware/a1x_piocfg.h
index 019eebf778d..d1fe6afe97f 100644
--- a/arch/arm/src/a1x/chip/a1x_piocfg.h
+++ b/arch/arm/src/a1x/hardware/a1x_piocfg.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/a1x/chip/a1x_piocfg.h
+ * arch/arm/src/a1x/hardware/a1x_piocfg.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_A1X_CHIP_A1X_PIOCFG_H
-#define __ARCH_ARM_SRC_A1X_CHIP_A1X_PIOCFG_H
+#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A1X_PIOCFG_H
+#define __ARCH_ARM_SRC_A1X_HARDWARE_A1X_PIOCFG_H
 
 /************************************************************************************
  * Included Files
@@ -44,9 +44,9 @@
 #include 
 
 #if defined(CONFIG_ARCH_CHIP_A10)
-#  include "chip/a10_piocfg.h"
+#  include "hardware/a10_piocfg.h"
 #else
 #  error Unrecognized A1X architecture
 #endif
 
-#endif /* __ARCH_ARM_SRC_A1X_CHIP_A1X_PIOCFG_H */
+#endif /* __ARCH_ARM_SRC_A1X_HARDWARE_A1X_PIOCFG_H */
diff --git a/arch/arm/src/a1x/chip/a1x_timer.h b/arch/arm/src/a1x/hardware/a1x_timer.h
similarity index 98%
rename from arch/arm/src/a1x/chip/a1x_timer.h
rename to arch/arm/src/a1x/hardware/a1x_timer.h
index afe3603057d..19f3745895d 100644
--- a/arch/arm/src/a1x/chip/a1x_timer.h
+++ b/arch/arm/src/a1x/hardware/a1x_timer.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/a1x/chip/a1x_timer.h
+ * arch/arm/src/a1x/hardware/a1x_timer.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_A1X_CHIP_A1X_TIMER_H
-#define __ARCH_ARM_SRC_A1X_CHIP_A1X_TIMER_H
+#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A1X_TIMER_H
+#define __ARCH_ARM_SRC_A1X_HARDWARE_A1X_TIMER_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/a1x_memorymap.h"
+#include "hardware/a1x_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -376,4 +376,4 @@
 #define CPU_CFG_L2DCACHE_INVEN     (1 << 0)  /* Bit 0:  Enable L2 data cache invalidation at reset */
 #define CPU_CFG_L1DCACHE_INVAEN    (1 << 1)  /* Bit 1:  Enable L1 data cache invalidation at reset */
 
-#endif /* __ARCH_ARM_SRC_A1X_CHIP_A1X_TIMER_H */
+#endif /* __ARCH_ARM_SRC_A1X_HARDWARE_A1X_TIMER_H */
diff --git a/arch/arm/src/a1x/chip/a1x_uart.h b/arch/arm/src/a1x/hardware/a1x_uart.h
similarity index 98%
rename from arch/arm/src/a1x/chip/a1x_uart.h
rename to arch/arm/src/a1x/hardware/a1x_uart.h
index 96f53a25056..199ad7ff1be 100644
--- a/arch/arm/src/a1x/chip/a1x_uart.h
+++ b/arch/arm/src/a1x/hardware/a1x_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/a1x/chip/a1x_uart.h
+ * arch/arm/src/a1x/hardware/a1x_uart.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_A1X_CHIP_A1X_UART_H
-#define __ARCH_ARM_SRC_A1X_CHIP_A1X_UART_H
+#ifndef __ARCH_ARM_SRC_A1X_HARDWARE_A1X_UART_H
+#define __ARCH_ARM_SRC_A1X_HARDWARE_A1X_UART_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/a1x_memorymap.h"
+#include "hardware/a1x_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -357,4 +357,4 @@
 #define UART_HALT_SIR_TX_INVERT   (1 << 4)  /* Bit 4:  SIR Transmit Pulse Polarity Invert */
 #define UART_HALT_SIR_RX_INVERT   (1 << 5)  /* Bit 5:  SIR Receiver Pulse Polarity Invert */
 
-#endif /* __ARCH_ARM_SRC_A1X_CHIP_A1X_UART_H */
+#endif /* __ARCH_ARM_SRC_A1X_HARDWARE_A1X_UART_H */
diff --git a/arch/arm/src/am335x/am335x_clockconfig.c b/arch/arm/src/am335x/am335x_clockconfig.c
index fbe5fe5b571..e719561c153 100644
--- a/arch/arm/src/am335x/am335x_clockconfig.c
+++ b/arch/arm/src/am335x/am335x_clockconfig.c
@@ -42,7 +42,7 @@
 #include "up_arch.h"
 #if 0
 /* TODO: add clock register module */
-#include "chip/am335x_ccm.h"
+#include "hardware/am335x_ccm.h"
 #endif
 #include "am335x_config.h"
 #include "am335x_clockconfig.h"
diff --git a/arch/arm/src/am335x/am335x_gpio.h b/arch/arm/src/am335x/am335x_gpio.h
index 033fde75098..b2f74107024 100644
--- a/arch/arm/src/am335x/am335x_gpio.h
+++ b/arch/arm/src/am335x/am335x_gpio.h
@@ -45,8 +45,8 @@
 #include 
 #include 
 
-#include "chip/am335x_control.h"
-#include "chip/am335x_gpio.h"
+#include "hardware/am335x_control.h"
+#include "hardware/am335x_gpio.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/am335x/am335x_irq.h b/arch/arm/src/am335x/am335x_irq.h
index bad04939a84..091ade0b693 100644
--- a/arch/arm/src/am335x/am335x_irq.h
+++ b/arch/arm/src/am335x/am335x_irq.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/am335x_intc.h"
+#include "hardware/am335x_intc.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/am335x/am335x_lowputc.c b/arch/arm/src/am335x/am335x_lowputc.c
index c1d3b9e51cb..7fe6d1757c0 100644
--- a/arch/arm/src/am335x/am335x_lowputc.c
+++ b/arch/arm/src/am335x/am335x_lowputc.c
@@ -50,7 +50,7 @@
 #include "am335x_config.h"
 #include "am335x_gpio.h"
 #include "am335x_pinmux.h"
-#include "chip/am335x_uart.h"
+#include "hardware/am335x_uart.h"
 
 /**************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/am335x/am335x_pinmux.h b/arch/arm/src/am335x/am335x_pinmux.h
index 0bb4766c9e8..70c5fa00671 100644
--- a/arch/arm/src/am335x/am335x_pinmux.h
+++ b/arch/arm/src/am335x/am335x_pinmux.h
@@ -42,8 +42,8 @@
 
 #include 
 
-#include "chip/am335x_control.h"
-#include "chip/am335x_pinmux.h"
+#include "hardware/am335x_control.h"
+#include "hardware/am335x_pinmux.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/am335x/am335x_serial.c b/arch/arm/src/am335x/am335x_serial.c
index a16c296deef..ba1e3eddcf9 100644
--- a/arch/arm/src/am335x/am335x_serial.c
+++ b/arch/arm/src/am335x/am335x_serial.c
@@ -62,8 +62,9 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/am335x_uart.h"
+#include "hardware/am335x_uart.h"
 #include "am335x_gpio.h"
+#include "am335x_pinmux.h"
 #include "am335x_serial.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/am335x/am335x_serial.h b/arch/arm/src/am335x/am335x_serial.h
index 304fd5794e9..7097582bb77 100644
--- a/arch/arm/src/am335x/am335x_serial.h
+++ b/arch/arm/src/am335x/am335x_serial.h
@@ -43,10 +43,10 @@
 #include 
 #include 
 
-#include "chip/am335x_uart.h"
+#include "hardware/am335x_uart.h"
 
 #include "am335x_config.h"
-#include "chip/am335x_gpio.h"
+#include "hardware/am335x_gpio.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/am335x/am335x_timerisr.c b/arch/arm/src/am335x/am335x_timerisr.c
index 9537252c2f8..f54d5709553 100644
--- a/arch/arm/src/am335x/am335x_timerisr.c
+++ b/arch/arm/src/am335x/am335x_timerisr.c
@@ -49,7 +49,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/am335x_timer.h"
+#include "hardware/am335x_timer.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/am335x/am335x_wdog.c b/arch/arm/src/am335x/am335x_wdog.c
index 05a783bbc67..7b0aec8ec2c 100644
--- a/arch/arm/src/am335x/am335x_wdog.c
+++ b/arch/arm/src/am335x/am335x_wdog.c
@@ -42,7 +42,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/am335x_wdog.h"
+#include "hardware/am335x_wdog.h"
 
 /****************************************************************************
  * Public Functions
diff --git a/arch/arm/src/am335x/am335x_wdog.h b/arch/arm/src/am335x/am335x_wdog.h
index 40a763f1425..4ad85784d57 100644
--- a/arch/arm/src/am335x/am335x_wdog.h
+++ b/arch/arm/src/am335x/am335x_wdog.h
@@ -49,7 +49,7 @@
 
 #include "up_internal.h"
 #include "chip.h"
-#include "chip/am335x_wdog.h"
+#include "hardware/am335x_wdog.h"
 
 /****************************************************************************
  * Public Types
diff --git a/arch/arm/src/am335x/chip.h b/arch/arm/src/am335x/chip.h
index 54465118ca3..f5f8a71fbf7 100644
--- a/arch/arm/src/am335x/chip.h
+++ b/arch/arm/src/am335x/chip.h
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/am335x_memorymap.h"
+#include "hardware/am335x_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/am335x/chip/am3358_memorymap.h b/arch/arm/src/am335x/hardware/am3358_memorymap.h
similarity index 99%
rename from arch/arm/src/am335x/chip/am3358_memorymap.h
rename to arch/arm/src/am335x/hardware/am3358_memorymap.h
index b103f57fbb8..50dda4f80d1 100644
--- a/arch/arm/src/am335x/chip/am3358_memorymap.h
+++ b/arch/arm/src/am335x/hardware/am3358_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/am335x/chip/am3358_memorymap.h
+ * arch/arm/src/am335x/hardware/am3358_memorymap.h
  *
  *   Copyright (C) 2018 Petro Karashchenko. All rights reserved.
  *   Author: Petro Karashchenko 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM3358_MEMORYMAP_H
-#define __ARCH_ARM_SRC_AM335X_CHIP_AM3358_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM3358_MEMORYMAP_H
+#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM3358_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -614,4 +614,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM3358_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM3358_MEMORYMAP_H */
diff --git a/arch/arm/src/am335x/chip/am3358_pinmux.h b/arch/arm/src/am335x/hardware/am3358_pinmux.h
similarity index 99%
rename from arch/arm/src/am335x/chip/am3358_pinmux.h
rename to arch/arm/src/am335x/hardware/am3358_pinmux.h
index 0ba6f464d60..ce398b56a7f 100644
--- a/arch/arm/src/am335x/chip/am3358_pinmux.h
+++ b/arch/arm/src/am335x/hardware/am3358_pinmux.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/am335x/chip/am3358_pinmux.h
+ * arch/arm/src/am335x/hardware/am3358_pinmux.h
  *
  *   Copyright (C) 2018 Petro Karashchenko. All rights reserved.
  *   Author: Petro Karashchenko 
@@ -33,15 +33,15 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM3358_PINMUX_H
-#define __ARCH_ARM_SRC_AM335X_CHIP_AM3358_PINMUX_H
+#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM3358_PINMUX_H
+#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM3358_PINMUX_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/am335x_memorymap.h"
+#include "hardware/am335x_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -859,4 +859,4 @@
 
 #define GPIO_USB1_DRVVBUS             (GPIO_PERIPH | GPIO_PADCTL(AM335X_PADCTL_USB1_DRVVBUS_INDEX) | PINMUX_MODE0)
 
-#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM3358_PINMUX_H */
+#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM3358_PINMUX_H */
diff --git a/arch/arm/src/am335x/chip/am335x_control.h b/arch/arm/src/am335x/hardware/am335x_control.h
similarity index 99%
rename from arch/arm/src/am335x/chip/am335x_control.h
rename to arch/arm/src/am335x/hardware/am335x_control.h
index 2ae2615fc7f..44ae78be6f6 100644
--- a/arch/arm/src/am335x/chip/am335x_control.h
+++ b/arch/arm/src/am335x/hardware/am335x_control.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/am335x/chip/am335x_control.h
+ * arch/arm/src/am335x/hardware/am335x_control.h
  *
  *   Copyright (C) 2018 Petro Karashchenko. All rights reserved.
  *   Author: Petro Karashchenko 
@@ -33,15 +33,15 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM335X_CONTROL_H
-#define __ARCH_ARM_SRC_AM335X_CHIP_AM335X_CONTROL_H
+#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_CONTROL_H
+#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_CONTROL_H
 
 /********************************************************************************************
  * Included Files
  ********************************************************************************************/
 
 #include 
-#include 
+#include "hardware/am335x_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -643,4 +643,4 @@
 #define PADCTL_RXACTIVE         (1 << 5) /* Bit 5: Receiver enabled */
 #define PADCTL_SLEWCTRL         (1 << 6) /* Bit 6: Select between faster or slower slew rate */
 
-#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM335X_CONTROL_H */
+#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_CONTROL_H */
diff --git a/arch/arm/src/am335x/chip/am335x_gpio.h b/arch/arm/src/am335x/hardware/am335x_gpio.h
similarity index 98%
rename from arch/arm/src/am335x/chip/am335x_gpio.h
rename to arch/arm/src/am335x/hardware/am335x_gpio.h
index bcb38ca50a6..51944e5ffb2 100644
--- a/arch/arm/src/am335x/chip/am335x_gpio.h
+++ b/arch/arm/src/am335x/hardware/am335x_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/am335x/am335x_gpio.h
+ * arch/arm/src/am335x/hardware/am335x_gpio.h
  *
  *   Copyright (C) 2018 Petro Karashchenko. All rights reserved.
  *   Author: Petro Karashchenko 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM335X_GPIO_H
-#define __ARCH_ARM_SRC_AM335X_CHIP_AM335X_GPIO_H
+#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_GPIO_H
+#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_GPIO_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include 
+#include "hardware/am335x_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -241,4 +241,4 @@
 #define GPIO_ICR_MASK(n)         (3 << GPIO_ICR_SHIFT(n))
 #define GPIO_ICR(i,n)            ((uint32_t)(n) << GPIO_ICR_SHIFT(n))
 
-#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM335X_GPIO_H */
+#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_GPIO_H */
diff --git a/arch/arm/src/am335x/chip/am335x_intc.h b/arch/arm/src/am335x/hardware/am335x_intc.h
similarity index 98%
rename from arch/arm/src/am335x/chip/am335x_intc.h
rename to arch/arm/src/am335x/hardware/am335x_intc.h
index 2d6c36a8850..2521053d8ce 100644
--- a/arch/arm/src/am335x/chip/am335x_intc.h
+++ b/arch/arm/src/am335x/hardware/am335x_intc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/am335x/chip/am335x_intc.h
+ * arch/arm/src/am335x/hardware/am335x_intc.h
  *
  *   Copyright (C) 2018 Petro Karashchenko. All rights reserved.
  *   Author: Petro Karashchenko 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM335X_INTC_H
-#define __ARCH_ARM_SRC_AM335X_CHIP_AM335X_INTC_H
+#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_INTC_H
+#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_INTC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/am335x_memorymap.h"
+#include "hardware/am335x_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -268,4 +268,4 @@
 #define INTC_ILR_PRIO_MASK              (127)  /* Bits 2..7:  Interrupt Priority */
 #  define INTC_ILR_PRIO(p)              (((p) & INTC_ILR_PRIO_MASK) << INTC_ILR_PRIO_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM335X_INTC_H */
+#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_INTC_H */
diff --git a/arch/arm/src/am335x/chip/am335x_memorymap.h b/arch/arm/src/am335x/hardware/am335x_memorymap.h
similarity index 88%
rename from arch/arm/src/am335x/chip/am335x_memorymap.h
rename to arch/arm/src/am335x/hardware/am335x_memorymap.h
index 3460ada57b4..a46997c97dd 100644
--- a/arch/arm/src/am335x/chip/am335x_memorymap.h
+++ b/arch/arm/src/am335x/hardware/am335x_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/am335x/chip/am335x_memorymap.h
+ * arch/arm/src/am335x/hardware/am335x_memorymap.h
  *
  *   Copyright (C) 2018 Petro Karashchenko. All rights reserved.
  *   Author: Petro Karashchenko 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM335X_MEMORYMAP_H
-#define __ARCH_ARM_SRC_AM335X_CHIP_AM335X_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -44,9 +44,9 @@
 #include 
 
 #if defined(CONFIG_ARCH_CHIP_AM3358)
-#  include "chip/am3358_memorymap.h"
+#  include "hardware/am3358_memorymap.h"
 #else
 #  error Unrecognized AM335X architecture
 #endif
 
-#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM335X_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_MEMORYMAP_H */
diff --git a/arch/arm/src/am335x/chip/am335x_pinmux.h b/arch/arm/src/am335x/hardware/am335x_pinmux.h
similarity index 89%
rename from arch/arm/src/am335x/chip/am335x_pinmux.h
rename to arch/arm/src/am335x/hardware/am335x_pinmux.h
index 42d789dcc72..2b15ccebca0 100644
--- a/arch/arm/src/am335x/chip/am335x_pinmux.h
+++ b/arch/arm/src/am335x/hardware/am335x_pinmux.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/am335x/chip/am335x_pinmux.h
+ * arch/arm/src/am335x/hardware/am335x_pinmux.h
  *
  *   Copyright (C) 2018 Petro Karashchenko. All rights reserved.
  *   Author: Petro Karashchenko 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM335X_PINMUX_H
-#define __ARCH_ARM_SRC_AM335X_CHIP_AM335X_PINMUX_H
+#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_PINMUX_H
+#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_PINMUX_H
 
 /************************************************************************************
  * Included Files
@@ -44,9 +44,9 @@
 #include 
 
 #if defined(CONFIG_ARCH_CHIP_AM3358)
-#  include "chip/am3358_pinmux.h"
+#  include "hardware/am3358_pinmux.h"
 #else
 #  error Unrecognized AM335X architecture
 #endif
 
-#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM335X_PINMUX_H */
+#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_PINMUX_H */
diff --git a/arch/arm/src/am335x/chip/am335x_timer.h b/arch/arm/src/am335x/hardware/am335x_timer.h
similarity index 98%
rename from arch/arm/src/am335x/chip/am335x_timer.h
rename to arch/arm/src/am335x/hardware/am335x_timer.h
index cfec609516a..ff72b73aa5f 100644
--- a/arch/arm/src/am335x/chip/am335x_timer.h
+++ b/arch/arm/src/am335x/hardware/am335x_timer.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/am335x/chip/am335x_timer.h
+ * arch/arm/src/am335x/hardware/am335x_timer.h
  *
  *   Copyright (C) 2018 Petro Karashchenko. All rights reserved.
  *   Author: Petro Karashchenko 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM335X_TIMER_H
-#define __ARCH_ARM_SRC_AM335X_CHIP_AM335X_TIMER_H
+#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_TIMER_H
+#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_TIMER_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/am335x_memorymap.h"
+#include "hardware/am335x_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -213,4 +213,4 @@
 
 #define TMR1MS_TOWR_MASK                (0xffffff)
 
-#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM335X_TIMER_H */
+#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_TIMER_H */
diff --git a/arch/arm/src/am335x/chip/am335x_uart.h b/arch/arm/src/am335x/hardware/am335x_uart.h
similarity index 99%
rename from arch/arm/src/am335x/chip/am335x_uart.h
rename to arch/arm/src/am335x/hardware/am335x_uart.h
index 4a6255d266d..122b478b98e 100644
--- a/arch/arm/src/am335x/chip/am335x_uart.h
+++ b/arch/arm/src/am335x/hardware/am335x_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/am335x/chip/am335x_uart.h
+ * arch/arm/src/am335x/hardware/am335x_uart.h
  *
  *   Copyright (C) 2018 Petro Karashchenko. All rights reserved.
  *   Author: Petro Karashchenko 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM335X_UART_H
-#define __ARCH_ARM_SRC_AM335X_CHIP_AM335X_UART_H
+#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_UART_H
+#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_UART_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/am335x_memorymap.h"
+#include "hardware/am335x_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -401,5 +401,5 @@
 #define UART_EFR_AUTORTSEN           (1 << 6)  /* Bit 6: Enable Auto-RTS */
 #define UART_EFR_AUTOCTSEN           (1 << 7)  /* Bit 7: Enable Auto-CTS */
 
-#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM335X_UART_H */
+#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_UART_H */
 
diff --git a/arch/arm/src/am335x/chip/am335x_wdog.h b/arch/arm/src/am335x/hardware/am335x_wdog.h
similarity index 96%
rename from arch/arm/src/am335x/chip/am335x_wdog.h
rename to arch/arm/src/am335x/hardware/am335x_wdog.h
index 2bedef07538..cd52b23395c 100644
--- a/arch/arm/src/am335x/chip/am335x_wdog.h
+++ b/arch/arm/src/am335x/hardware/am335x_wdog.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/am335x/chip/am335x_wdog.h
+ * arch/arm/src/am335x/hardware/am335x_wdog.h
  *
  *   Copyright (C) 2019 Petro Karashchenko. All rights reserved.
  *   Author: Petro Karashchenko 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_AM335X_CHIP_AM335X_WDOG_H
-#define __ARCH_ARM_SRC_AM335X_CHIP_AM335X_WDOG_H
+#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_WDOG_H
+#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_WDOG_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/am335x_memorymap.h"
+#include "hardware/am335x_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -129,5 +129,5 @@
 #define WDT_WSPR_STOP_FEED_A            (0x0000aaaa)
 #define WDT_WSPR_STOP_FEED_B            (0x00005555)
 
-#endif /* __ARCH_ARM_SRC_AM335X_CHIP_AM335X_WDOG_H */
+#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_WDOG_H */
 
diff --git a/arch/arm/src/arm/up_schedulesigaction.c b/arch/arm/src/arm/up_schedulesigaction.c
index f6f0c655e8f..5b731692eaf 100644
--- a/arch/arm/src/arm/up_schedulesigaction.c
+++ b/arch/arm/src/arm/up_schedulesigaction.c
@@ -51,8 +51,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -189,5 +187,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/arm/src/arm/up_sigdeliver.c b/arch/arm/src/arm/up_sigdeliver.c
index afc843b1e1a..19419e12240 100644
--- a/arch/arm/src/arm/up_sigdeliver.c
+++ b/arch/arm/src/arm/up_sigdeliver.c
@@ -53,8 +53,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -131,6 +129,3 @@ void up_sigdeliver(void)
   board_autoled_off(LED_SIGNAL);
   up_fullcontextrestore(regs);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
-
diff --git a/arch/arm/src/armv6-m/up_schedulesigaction.c b/arch/arm/src/armv6-m/up_schedulesigaction.c
index 5040582bacf..1636db6de68 100644
--- a/arch/arm/src/armv6-m/up_schedulesigaction.c
+++ b/arch/arm/src/armv6-m/up_schedulesigaction.c
@@ -52,20 +52,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -211,5 +197,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/arm/src/armv6-m/up_sigdeliver.c b/arch/arm/src/armv6-m/up_sigdeliver.c
index 1688019729a..834c16348c7 100644
--- a/arch/arm/src/armv6-m/up_sigdeliver.c
+++ b/arch/arm/src/armv6-m/up_sigdeliver.c
@@ -52,8 +52,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -141,5 +139,3 @@ void up_sigdeliver(void)
   board_autoled_off(LED_SIGNAL);
   up_fullcontextrestore(regs);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/arm/src/armv6-m/up_signal_dispatch.c b/arch/arm/src/armv6-m/up_signal_dispatch.c
index 45446a2b5e4..f69702f953c 100644
--- a/arch/arm/src/armv6-m/up_signal_dispatch.c
+++ b/arch/arm/src/armv6-m/up_signal_dispatch.c
@@ -43,20 +43,8 @@
 #include "svcall.h"
 #include "up_internal.h"
 
-#if ((defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
-      defined(CONFIG_BUILD_KERNEL)) && !defined(CONFIG_DISABLE_SIGNALS)
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
+#if (defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
+     defined(CONFIG_BUILD_KERNEL)
 
 /****************************************************************************
  * Public Functions
diff --git a/arch/arm/src/armv6-m/up_svcall.c b/arch/arm/src/armv6-m/up_svcall.c
index 98377230346..d2b5b9cf12e 100644
--- a/arch/arm/src/armv6-m/up_svcall.c
+++ b/arch/arm/src/armv6-m/up_svcall.c
@@ -351,7 +351,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
        *   R4 = ucontext
        */
 
-#if defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_DISABLE_SIGNALS)
+#ifdef CONFIG_BUILD_PROTECTED
       case SYS_signal_handler:
         {
           struct tcb_s *rtcb   = sched_self();
@@ -389,7 +389,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
        *   R0 = SYS_signal_handler_return
        */
 
-#if defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_DISABLE_SIGNALS)
+#ifdef CONFIG_BUILD_PROTECTED
       case SYS_signal_handler_return:
         {
           struct tcb_s *rtcb   = sched_self();
diff --git a/arch/arm/src/armv7-a/arm_schedulesigaction.c b/arch/arm/src/armv7-a/arm_schedulesigaction.c
index 1fc7f48c237..7a565365bfb 100644
--- a/arch/arm/src/armv7-a/arm_schedulesigaction.c
+++ b/arch/arm/src/armv7-a/arm_schedulesigaction.c
@@ -53,8 +53,6 @@
 
 #include "irq/irq.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -384,5 +382,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
   leave_critical_section(flags);
 }
 #endif /* CONFIG_SMP */
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/arm/src/armv7-a/arm_sigdeliver.c b/arch/arm/src/armv7-a/arm_sigdeliver.c
index e1f500b1e98..25bd57358fb 100644
--- a/arch/arm/src/armv7-a/arm_sigdeliver.c
+++ b/arch/arm/src/armv7-a/arm_sigdeliver.c
@@ -53,8 +53,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -184,5 +182,3 @@ void up_sigdeliver(void)
   board_autoled_off(LED_SIGNAL);
   up_fullcontextrestore(regs);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/arm/src/armv7-a/arm_signal_dispatch.c b/arch/arm/src/armv7-a/arm_signal_dispatch.c
index 1b461f5cb92..ec1eb56485f 100644
--- a/arch/arm/src/armv7-a/arm_signal_dispatch.c
+++ b/arch/arm/src/armv7-a/arm_signal_dispatch.c
@@ -44,8 +44,8 @@
 #include "pgalloc.h"
 #include "up_internal.h"
 
-#if ((defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
-      defined(CONFIG_BUILD_KERNEL)) && !defined(CONFIG_DISABLE_SIGNALS)
+#if (defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
+     defined(CONFIG_BUILD_KERNEL)
 
 /****************************************************************************
  * Public Functions
@@ -104,4 +104,4 @@ void up_signal_dispatch(_sa_sigaction_t sighand, int signo,
     }
 }
 
-#endif /* (CONFIG_BUILD_PROTECTED || CONFIG_BUILD_KERNEL) && !CONFIG_DISABLE_SIGNALS */
+#endif /* CONFIG_BUILD_PROTECTED || CONFIG_BUILD_KERNEL */
diff --git a/arch/arm/src/armv7-a/arm_syscall.c b/arch/arm/src/armv7-a/arm_syscall.c
index 7b95e4935b3..00e4f43c6b9 100644
--- a/arch/arm/src/armv7-a/arm_syscall.c
+++ b/arch/arm/src/armv7-a/arm_syscall.c
@@ -312,7 +312,7 @@ uint32_t *arm_syscall(uint32_t *regs)
         break;
 #endif
 
-#if defined(CONFIG_BUILD_KERNEL) && !defined(CONFIG_DISABLE_SIGNALS)
+#ifdef CONFIG_BUILD_KERNEL
       /* R0=SYS_signal_handler:  This a user signal handler callback
        *
        * void signal_handler(_sa_sigaction_t sighand, int signo,
@@ -372,7 +372,7 @@ uint32_t *arm_syscall(uint32_t *regs)
         break;
 #endif
 
-#if defined(CONFIG_BUILD_KERNEL) && !defined(CONFIG_DISABLE_SIGNALS)
+#ifdef CONFIG_BUILD_KERNEL
       /* R0=SYS_signal_handler_return:  This a user signal handler callback
        *
        *   void signal_handler_return(void);
diff --git a/arch/arm/src/armv7-a/crt0.c b/arch/arm/src/armv7-a/crt0.c
index f13148aa9b8..399ff8e2948 100644
--- a/arch/arm/src/armv7-a/crt0.c
+++ b/arch/arm/src/armv7-a/crt0.c
@@ -79,7 +79,6 @@ int main(int argc, char *argv[]);
  *
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_SIGNALS
 static void sig_trampoline(void) naked_function;
 static void sig_trampoline(void)
 {
@@ -97,7 +96,6 @@ static void sig_trampoline(void)
     " svc #0x900001\n"   /* Return from the signal handler */
   );
 }
-#endif
 
 /****************************************************************************
  * Public Functions
@@ -127,13 +125,11 @@ void _start(int argc, FAR char *argv[])
 {
   int ret;
 
-#ifndef CONFIG_DISABLE_SIGNALS
   /* Initialize the reserved area at the beginning of the .bss/.data region
    * that is visible to the RTOS.
    */
 
   ARCH_DATA_RESERVE->ar_sigtramp = (addrenv_sigtramp_t)sig_trampoline;
-#endif
 
   /* Call C++ constructors */
   /* Setup so that C++ destructors called on task exit */
diff --git a/arch/arm/src/armv7-m/up_schedulesigaction.c b/arch/arm/src/armv7-m/up_schedulesigaction.c
index df994c41fad..760f3b6c594 100644
--- a/arch/arm/src/armv7-m/up_schedulesigaction.c
+++ b/arch/arm/src/armv7-m/up_schedulesigaction.c
@@ -55,8 +55,6 @@
 
 #include "irq/irq.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -448,5 +446,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
   leave_critical_section(flags);
 }
 #endif /* CONFIG_SMP */
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/arm/src/armv7-m/up_sigdeliver.c b/arch/arm/src/armv7-m/up_sigdeliver.c
index e79f569d3d0..66fa9b3530a 100644
--- a/arch/arm/src/armv7-m/up_sigdeliver.c
+++ b/arch/arm/src/armv7-m/up_sigdeliver.c
@@ -53,8 +53,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -198,5 +196,3 @@ void up_sigdeliver(void)
   board_autoled_off(LED_SIGNAL);
   up_fullcontextrestore(regs);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/arm/src/armv7-m/up_signal_dispatch.c b/arch/arm/src/armv7-m/up_signal_dispatch.c
index 332d61252e0..54bc8e5cd51 100644
--- a/arch/arm/src/armv7-m/up_signal_dispatch.c
+++ b/arch/arm/src/armv7-m/up_signal_dispatch.c
@@ -43,8 +43,8 @@
 #include "svcall.h"
 #include "up_internal.h"
 
-#if ((defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
-      defined(CONFIG_BUILD_KERNEL)) && !defined(CONFIG_DISABLE_SIGNALS)
+#if (defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
+     defined(CONFIG_BUILD_KERNEL)
 
 /****************************************************************************
  * Public Functions
diff --git a/arch/arm/src/armv7-m/up_svcall.c b/arch/arm/src/armv7-m/up_svcall.c
index d549edc9590..c0e782cd2e0 100644
--- a/arch/arm/src/armv7-m/up_svcall.c
+++ b/arch/arm/src/armv7-m/up_svcall.c
@@ -351,7 +351,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
        *   R4 = ucontext
        */
 
-#if defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_DISABLE_SIGNALS)
+#ifdef CONFIG_BUILD_PROTECTED
       case SYS_signal_handler:
         {
           struct tcb_s *rtcb   = sched_self();
@@ -389,7 +389,7 @@ int up_svcall(int irq, FAR void *context, FAR void *arg)
        *   R0 = SYS_signal_handler_return
        */
 
-#if defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_DISABLE_SIGNALS)
+#ifdef CONFIG_BUILD_PROTECTED
       case SYS_signal_handler_return:
         {
           struct tcb_s *rtcb   = sched_self();
diff --git a/arch/arm/src/armv7-r/arm_schedulesigaction.c b/arch/arm/src/armv7-r/arm_schedulesigaction.c
index 3752cc0e7d1..f14901adcda 100644
--- a/arch/arm/src/armv7-r/arm_schedulesigaction.c
+++ b/arch/arm/src/armv7-r/arm_schedulesigaction.c
@@ -51,8 +51,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -196,5 +194,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/arm/src/armv7-r/arm_sigdeliver.c b/arch/arm/src/armv7-r/arm_sigdeliver.c
index 6f560d14ff4..e6002fe1166 100644
--- a/arch/arm/src/armv7-r/arm_sigdeliver.c
+++ b/arch/arm/src/armv7-r/arm_sigdeliver.c
@@ -52,8 +52,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -130,5 +128,3 @@ void up_sigdeliver(void)
   board_autoled_off(LED_SIGNAL);
   up_fullcontextrestore(regs);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/arm/src/armv7-r/arm_signal_dispatch.c b/arch/arm/src/armv7-r/arm_signal_dispatch.c
index c09c1481b6c..2b4ed038691 100644
--- a/arch/arm/src/armv7-r/arm_signal_dispatch.c
+++ b/arch/arm/src/armv7-r/arm_signal_dispatch.c
@@ -44,20 +44,8 @@
 #include "pgalloc.h"
 #include "up_internal.h"
 
-#if ((defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
-      defined(CONFIG_BUILD_PROTECTED)) && !defined(CONFIG_DISABLE_SIGNALS)
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
+#if (defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
+     defined(CONFIG_BUILD_PROTECTED)
 
 /****************************************************************************
  * Public Functions
@@ -116,4 +104,4 @@ void up_signal_dispatch(_sa_sigaction_t sighand, int signo,
     }
 }
 
-#endif /* (CONFIG_BUILD_PROTECTED || CONFIG_BUILD_PROTECTED) && !CONFIG_DISABLE_SIGNALS */
+#endif /* CONFIG_BUILD_PROTECTED || CONFIG_BUILD_PROTECTED */
diff --git a/arch/arm/src/armv7-r/arm_syscall.c b/arch/arm/src/armv7-r/arm_syscall.c
index 26168ce4b5c..3abc36df903 100644
--- a/arch/arm/src/armv7-r/arm_syscall.c
+++ b/arch/arm/src/armv7-r/arm_syscall.c
@@ -310,7 +310,7 @@ uint32_t *arm_syscall(uint32_t *regs)
         break;
 #endif
 
-#if defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_DISABLE_SIGNALS)
+#ifdef CONFIG_BUILD_PROTECTED
       /* R0=SYS_signal_handler:  This a user signal handler callback
        *
        * void signal_handler(_sa_sigaction_t sighand, int signo,
@@ -370,7 +370,7 @@ uint32_t *arm_syscall(uint32_t *regs)
         break;
 #endif
 
-#if defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_DISABLE_SIGNALS)
+#ifdef CONFIG_BUILD_PROTECTED
       /* R0=SYS_signal_handler_return:  This a user signal handler callback
        *
        *   void signal_handler_return(void);
diff --git a/arch/arm/src/common/README_lwl_console.txt b/arch/arm/src/common/README_lwl_console.txt
new file mode 100644
index 00000000000..3e2cd3dfa43
--- /dev/null
+++ b/arch/arm/src/common/README_lwl_console.txt
@@ -0,0 +1,59 @@
+The file up_lwl_console.c implements a 'Lightweight Link' protocol between
+a target and debugger for use when you need a console but the target doesn't
+have a spare serial port or other available resource. This implements a
+new console type which uses two words of memory for data exchange.
+
+It is not particularly efficient because of the various compromises that are
+made (polling in busy loops, mostly) but it works well enough to give you
+something where you previously had nothing...typically the case when you're
+bring up a new CPU, or when the hardware designer thought the softies could
+cope without a logging port. It has an advantage over semi-hosting in that
+it doesn't put the target into debug mode while it's running, so you've got
+some hope of maintaining real time semantics.  To be clear, for output only
+use you'd be better off with SWO if you've got it available!
+
+There is a terminal program in python(*) for the host side in
+tools/ocdconsole.py for use with openocd...the NuttX side functionality is
+not dependent on a specific debugger, the only requirement on it being that
+the debugger can watch and modify a memory location on the target while it is executing.
+
+Typical use is;
+
+$ tools/ocdconsole.py
+==Link Activated
+
+NuttShell (NSH)
+nsh> help
+help usage:  help [-v] []
+
+  ?        echo     exit     hexdump  ls       mh sleep    xd
+  cat      exec     help     kill     mb       mw usleep
+nsh>
+
+On the target side it's transparent, and is just a console;
+
+nsh> ls /dev
+/dev:
+ console
+ null
+ ttyS0
+nsh> echo "Hello World" > /dev/console
+Hello World
+nsh>
+
+CPU load on the host is surprisingly low given that the polling loop is
+continuous (probably due to the fact that openocd is spending most of it's
+time waiting for messages to/from the debug port on the target). When not
+actively doing anything there's no load on the target, but waiting for input
+is done in a busy polled loop (so the thread is effectively busy-locked)
+and output busy-waits for the previous message to be collected before it
+sends the next one.
+
+For now I've only made it available on stm32, but it should only be a case
+of changing the Kconfig and Make.defs for other arm CPUs to make it
+available for them too. Moving beyond arm needs knowledge of the targets
+that I don't have.
+
+If anyone fancies extending this proof-of-concept to full Segger-RTT-style
+functionality then drop me a note, there are plenty of ways to improve
+performance.
diff --git a/arch/arm/src/common/up_initialize.c b/arch/arm/src/common/up_initialize.c
index 82669eace87..7c0d1dcc0ea 100644
--- a/arch/arm/src/common/up_initialize.c
+++ b/arch/arm/src/common/up_initialize.c
@@ -51,6 +51,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -203,7 +204,9 @@ void up_initialize(void)
    * serial driver).
    */
 
-#if defined(CONFIG_DEV_LOWCONSOLE)
+#if defined (CONFIG_ARM_LWL_CONSOLE)
+  lwlconsole_init();
+#elif defined(CONFIG_DEV_LOWCONSOLE)
   lowconsole_init();
 #elif defined(CONFIG_CONSOLE_SYSLOG)
   syslog_console_init();
@@ -258,9 +261,11 @@ void up_initialize(void)
   (void)telnet_initialize();
 #endif
 
+#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)
   /* Initialize USB -- device and/or host */
 
   up_usbinitialize();
+#endif
 
   /* Initialize the L2 cache if present and selected */
 
diff --git a/arch/arm/src/common/up_internal.h b/arch/arm/src/common/up_internal.h
index 51ea73f4a4e..64290551729 100644
--- a/arch/arm/src/common/up_internal.h
+++ b/arch/arm/src/common/up_internal.h
@@ -63,7 +63,11 @@
 #  undef  CONFIG_DEV_LOWCONSOLE
 #  undef  CONFIG_RAMLOG_CONSOLE
 #else
-#  if defined(CONFIG_RAMLOG_CONSOLE)
+#  if defined(CONFIG_ARM_LWL_CONSOLE)
+#    undef  USE_SERIALDRIVER
+#    undef  USE_EARLYSERIALINIT
+#    undef  CONFIG_DEV_LOWCONSOLE
+#  elif defined(CONFIG_RAMLOG_CONSOLE)
 #    undef  USE_SERIALDRIVER
 #    undef  USE_EARLYSERIALINIT
 #    undef  CONFIG_DEV_LOWCONSOLE
@@ -299,7 +303,7 @@ EXTERN uint32_t _eramfuncs;       /* Copy destination end address in RAM */
  ****************************************************************************/
 
 /****************************************************************************
- * Public Functions
+ * Public Function Prototypes
  ****************************************************************************/
 
 #ifndef __ASSEMBLY__
@@ -449,10 +453,18 @@ void up_earlyserialinit(void);
 #  define up_earlyserialinit()
 #endif
 
+#ifdef CONFIG_ARM_LWL_CONSOLE
+
+/* Defined in src/common/up_lwl_console.c */
+
+void lwlconsole_init(void);
+
+#elif defined(CONFIG_DEV_LOWCONSOLE)
+
 /* Defined in drivers/lowconsole.c */
 
-#ifdef CONFIG_DEV_LOWCONSOLE
 void lowconsole_init(void);
+
 #else
 # define lowconsole_init()
 #endif
diff --git a/arch/arm/src/common/up_lwl_console.c b/arch/arm/src/common/up_lwl_console.c
new file mode 100644
index 00000000000..a915a3879f5
--- /dev/null
+++ b/arch/arm/src/common/up_lwl_console.c
@@ -0,0 +1,327 @@
+/****************************************************************************
+ * drivers/serial/lwlconsole.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Dave Marples 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Lightweight Link (lwl)
+ * ======================
+ *
+ * Lightweight bidirectional communication between target and debug host
+ * without any need for additional hardware.
+ *
+ * Works with openOCD and other debuggers that are capable of reading and
+ * writing memory while the target is running.
+ *
+ * Principle of operation is simple; An 'upword' of 32 bits communicates
+ * from the target to the host, a 'downword' of the same size runs in the
+ * opposite direction. These two words can be in any memory that is
+ * read/write access for both the target and the debug host. A simple ping
+ * pong handshake protocol over these words allows up/down link
+ * communication.  On the upside no additional integration is needed. On
+ * the downside it may be necessary to feed lwl with cycles to poll for
+ * changes in the downword, depending on the use case.
+ *
+ * Bit configuration
+ * -----------------
+ *
+ * Downword (Host to target);
+ *
+ * A D U VV XXX
+ *
+ * A   31    1 - Service Active (Set by host)
+ * D   30    1 - Downsense (Toggled when there is data)
+ * U   29    1 - Upsense ack (Toggled to acknowledge receipt of uplink data)
+ * VV  28-27 2 - Valid Octets (Number of octets valid in the message)
+ * XXX 26-24 3 - Port in use (Type of the message)
+ * O2  23-16 8 - Octet 2
+ * O1  15-08 8 - Octet 1
+ * O0  07-00 8 - Octet 0
+ *
+ * Upword (Target to Host);
+ *
+ * A   31    1 - Service Active (Set by device)
+ * D   30    1 - Downsense ack (Toggled to acknowledge receipt of downlink
+ *               data)
+ * U   29    1 - Upsense (Toggled when there is data)
+ * VV  28-27 2 - Valid upword octets
+ * XXX 26-24 3 - Port in use (Type of the message)
+ * O2  23-16 8 - Octet 2
+ * O1  15-08 8 - Octet 1
+ * O0  07-00 8 - Octet 0
+ *
+ */
+
+/* Protocol bits */
+
+#define LWL_GETACTIVE(x) (((x) & (1 << 31)) != 0)
+#define LWL_ACTIVE(x) (((x)&1) << 31)
+
+#define LWL_DNSENSEBIT (1 << 30)
+#define LWL_DNSENSE(x) ((x)&LWL_DNSENSEBIT)
+#define LWL_UPSENSEBIT (1 << 29)
+#define LWL_UPSENSE(x) ((x)&LWL_UPSENSEBIT)
+#define LWL_SENSEMASK (3 << 29)
+
+#define LWL_GETOCTVAL(x) (((x) >> 27) & 3)
+#define LWL_OCTVAL(x) (((x)&3) << 27)
+#define LWL_GETPORT(x) (((x) >> 24) & 7)
+#define LWL_PORT(x) (((x)&7) << 24)
+
+#define LWL_PORT_CONSOLE 1
+#define ID_SIG 0x7216A318
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static ssize_t lwlconsole_read(struct file *filep, char *buffer,
+                               size_t buflen);
+static ssize_t lwlconsole_write(struct file *filep, const char *buffer,
+                                size_t buflen);
+static int lwlconsole_ioctl(struct file *filep, int cmd, unsigned long arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static struct
+{
+  uint32_t sig;               /* Location signature */
+  volatile uint32_t downword; /* Host to Target word */
+  uint32_t upword;            /* Target to Host word */
+} g_d =
+{
+  .sig = ID_SIG
+};
+
+static const struct file_operations g_consoleops =
+{
+  NULL,                       /* open */
+  NULL,                       /* close */
+  lwlconsole_read,            /* read */
+  lwlconsole_write,           /* write */
+  NULL,                       /* seek */
+  lwlconsole_ioctl,           /* ioctl */
+  NULL                        /* poll */
+#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
+    ,
+  NULL                        /* unlink */
+#endif
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static bool linkactive(void)
+{
+  return (LWL_GETACTIVE(g_d.downword) != 0);
+}
+
+static bool writeword(uint32_t newupword)
+{
+  /* Check link is active */
+
+  if (!linkactive())
+    {
+      return false;
+    }
+
+  /* Spin waiting for previous data to be collected */
+
+  while (LWL_UPSENSE(g_d.downword) != LWL_UPSENSE(g_d.upword))
+    {
+    }
+
+  /* Load new data, toggling UPSENSE bit to show it is new */
+
+  g_d.upword = LWL_DNSENSE(g_d.upword) | newupword |
+               (LWL_UPSENSE(g_d.upword) ? 0 : LWL_UPSENSEBIT);
+
+  return true;
+}
+
+static bool write8bits(uint8_t port, uint8_t val)
+{
+  /* Prepare new word */
+
+  uint32_t newupword = LWL_ACTIVE(true) | LWL_OCTVAL(1) |
+                       LWL_PORT(port) | (val & 0xff);
+
+  return writeword(newupword);
+}
+
+static bool write16bits(uint8_t port, uint32_t val)
+{
+  /* Prepare new word */
+
+  uint32_t newupword = LWL_ACTIVE(true) | LWL_OCTVAL(2) |
+                       LWL_PORT(port) | (val & 0xffff);
+
+  return writeword(newupword);
+}
+
+static bool write24bits(uint8_t port, uint32_t val)
+{
+  /* Prepare new word */
+
+  uint32_t newupword = LWL_ACTIVE(true) | LWL_OCTVAL(3) |
+                       LWL_PORT(port) | (val & 0xffffff);
+
+  return writeword(newupword);
+}
+
+static bool read8bits(uint8_t port, uint8_t * store)
+{
+  if (LWL_DNSENSE(g_d.downword) == LWL_DNSENSE(g_d.upword))
+    {
+      return false;
+    }
+
+  *store = g_d.downword & 255;
+
+  /* Flip the bit to indicate the datum is read */
+
+  g_d.upword = (g_d.upword & ~LWL_DNSENSEBIT) | LWL_DNSENSE(g_d.downword);
+
+  return true;
+}
+
+/****************************************************************************
+ * Name: lwlconsole_ioctl
+ ****************************************************************************/
+
+static int lwlconsole_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+  return -ENOTTY;
+}
+
+/****************************************************************************
+ * Name: lwlconsole_read
+ ****************************************************************************/
+
+static ssize_t lwlconsole_read(struct file *filep, char *buffer,
+                               size_t buflen)
+{
+  if (buflen == 0 || !linkactive())
+    {
+      return 0;
+    }
+
+  while (!read8bits(LWL_PORT_CONSOLE, (uint8_t *) buffer))
+    {
+    }
+
+  return 1;
+}
+
+/****************************************************************************
+ * Name: lwlconsole_write
+ ****************************************************************************/
+
+static ssize_t lwlconsole_write(struct file *filep, const char *buffer,
+                                size_t buflen)
+{
+  uint32_t oc = 0;
+
+  while (buflen)
+    {
+      switch (buflen)
+        {
+          case 0:
+            return oc;
+
+          case 1:
+            if (write8bits(LWL_PORT_CONSOLE, buffer[0]))
+              {
+                oc++;
+                buffer++;
+                buflen--;
+              }
+            break;
+
+          case 2:
+            if (write16bits(LWL_PORT_CONSOLE, buffer[0] | (buffer[1] << 8)))
+              {
+                oc += 2;
+                buffer += 2;
+                buflen -= 2;
+              }
+            break;
+
+          default:
+            if (write24bits(LWL_PORT_CONSOLE, buffer[0] |
+                            (buffer[1] << 8) | (buffer[2] << 16)))
+              {
+                oc += 3;
+                buffer += 3;
+                buflen -= 3;
+              }
+            break;
+        }
+    }
+
+  return oc;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lwlconsole_init
+ ****************************************************************************/
+
+void lwlconsole_init(void)
+{
+  g_d.upword = 0;
+  (void)register_driver("/dev/console", &g_consoleops, 0666, NULL);
+}
diff --git a/arch/arm/src/cxd56xx/Kconfig b/arch/arm/src/cxd56xx/Kconfig
new file mode 100644
index 00000000000..30740742731
--- /dev/null
+++ b/arch/arm/src/cxd56xx/Kconfig
@@ -0,0 +1,118 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+comment "CXD56xx Configuration Options"
+
+config CXD56_ARCH_OPTS
+	bool
+	default y
+	select ARCH_DMA
+	select SDIO_DMA if MMCSD
+
+menu "CXD56xx Package Configuration"
+
+choice
+	prompt "CXD56xx package selection"
+	default CXD56_FCBGA if !CXD56_100PIN
+	default CXD56_WLCSP if CXD56_100PIN
+
+config CXD56_FCBGA
+	bool "FCBGA 185 pin package"
+
+config CXD56_WLCSP
+	bool "WLCSP 100 pin package"
+
+endchoice
+endmenu
+
+comment "Basic Options"
+
+config CXD56_XOSC_CLOCK
+	int
+	default 26000000
+
+config CXD56_PMIC
+	bool
+	default y
+
+config CXD56_CPUFIFO
+	bool
+
+config CXD56_ICC
+	bool
+	default y
+
+menu "CXD56xx Peripheral Support"
+
+config CXD56_GPIO_IRQ
+	bool "GPIO interrupt"
+	default y
+	---help---
+		Enable support for GPIO interrupts
+
+config CXD56_UART1
+	bool "UART1"
+	default y
+	select UART1_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+	---help---
+		UART interface in the communication subsystem. This doesn't have any
+		hardware flow control, and is mainly used for debug console.
+
+config CXD56_UART2
+	bool "UART2"
+	default n
+	select UART2_SERIALDRIVER
+	---help---
+		UART interface with hardware flow control in the application subsystem.
+
+config CXD56_USBDEV
+	bool "USB"
+	default n
+	---help---
+		Enables USB
+
+menuconfig CXD56_SDIO
+	bool "SDIO SD Card"
+	default n
+	select ARCH_HAVE_SDIO
+	select SDIO_BLOCKSETUP
+	select SCHED_WORKQUEUE
+	select SCHED_HPWORK
+
+if CXD56_SDIO
+
+config CXD56_SDIO_DMA
+	bool "Support DMA data transfers"
+	default y
+	select SDIO_DMA
+	---help---
+		Support DMA data transfers.
+		Enable SD card DMA data transfers.  This is marginally optional.
+		For most usages, SD accesses will cause data overruns if used without
+		DMA.
+
+config CXD56_SDIO_WIDTH_D1_ONLY
+	bool "Use D1 only"
+	default n
+	---help---
+		Select 1-bit transfer mode.  Default: 4-bit transfer mode.
+
+config CXD56_SDIO_DISABLE_CD_WP
+	bool "Disable the CD and WP pin for SDIO"
+	default y
+	---help---
+		Disable the CD and WP pin for Embedded SDIO.If the CD pin is not disable,
+		the SDIO initialization will be failed.
+
+config CXD56_SDIO_ENABLE_MULTIFUNCTION
+	bool "Enable SDIO multi-function"
+	default n
+	---help---
+		Support multi-function with SDIO interfaced peripheral other than SD Card.
+
+endif # SDIO Configuration
+
+endmenu
diff --git a/arch/arm/src/cxd56xx/Make.defs b/arch/arm/src/cxd56xx/Make.defs
new file mode 100644
index 00000000000..cbc488ef2bc
--- /dev/null
+++ b/arch/arm/src/cxd56xx/Make.defs
@@ -0,0 +1,103 @@
+############################################################################
+# arch/arm/src/cxd56xx/Make.defs
+#
+#   Copyright 2018 Sony Semiconductor Solutions Corporation
+#
+#   Copyright (C) 2012-2015 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt 
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+HEAD_ASRC  =
+
+CMN_ASRCS  = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
+CMN_ASRCS += up_testset.S vfork.S
+
+CMN_CSRCS  = up_assert.c up_blocktask.c up_copyfullstate.c
+CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
+CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
+CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
+CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
+CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_stackframe.c
+CMN_CSRCS += up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c
+CMN_CSRCS += up_svcall.c up_vfork.c
+
+ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
+CMN_ASRCS += up_lazyexception.S
+else
+CMN_ASRCS += up_exception.S
+endif
+CMN_CSRCS += up_vectors.c
+
+ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
+CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
+endif
+
+ifeq ($(CONFIG_ARCH_MEMCPY),y)
+CMN_ASRCS += up_memcpy.S
+endif
+
+ifeq ($(CONFIG_BUILD_PROTECTED),y)
+CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
+CMN_CSRCS += up_signal_dispatch.c
+CMN_UASRCS += up_signal_handler.S
+endif
+
+ifeq ($(CONFIG_STACK_COLORATION),y)
+CMN_CSRCS += up_checkstack.c
+endif
+
+ifeq ($(CONFIG_ARCH_FPU),y)
+CMN_ASRCS += up_fpu.S
+ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
+CMN_CSRCS += up_copyarmstate.c
+else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
+CMN_CSRCS += up_copyarmstate.c
+endif
+endif
+
+CHIP_CSRCS  = cxd56_allocateheap.c cxd56_idle.c
+CHIP_CSRCS += cxd56_serial.c cxd56_uart.c cxd56_irq.c
+CHIP_CSRCS += cxd56_start.c
+CHIP_CSRCS += cxd56_timerisr.c
+CHIP_CSRCS += cxd56_pinconfig.c
+CHIP_CSRCS += cxd56_clock.c
+CHIP_CSRCS += cxd56_gpio.c
+CHIP_CSRCS += cxd56_pmic.c
+CHIP_CSRCS += cxd56_cpufifo.c
+CHIP_CSRCS += cxd56_icc.c
+
+ifeq ($(CONFIG_CXD56_GPIO_IRQ),y)
+CHIP_CSRCS += cxd56_gpioint.c
+endif
+
+ifeq ($(CONFIG_USBDEV),y)
+CHIP_CSRCS += cxd56_usbdev.c
+endif
diff --git a/arch/arm/src/cxd56xx/chip.h b/arch/arm/src/cxd56xx/chip.h
new file mode 100644
index 00000000000..0ccfe5ffda2
--- /dev/null
+++ b/arch/arm/src/cxd56xx/chip.h
@@ -0,0 +1,69 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/chip.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_H
+#define __ARCH_ARM_SRC_CXD56XX_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+/* Include the chip capabilities file */
+
+#include 
+
+#define  ARMV7M_PERIPHERAL_INTERRUPTS 128
+
+#include "hardware/cxd5602_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_H */
diff --git a/arch/arm/src/cxd56xx/cxd56_allocateheap.c b/arch/arm/src/cxd56xx/cxd56_allocateheap.c
new file mode 100644
index 00000000000..606e2139bc7
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_allocateheap.c
@@ -0,0 +1,139 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_allocateheap.c
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ *   Copyright (C) 2012-2013, 2015-2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* _sbss is the start of the BSS region (see the linker script) _ebss is the
+ * end of the BSS regsion (see the linker script). The idle task stack starts
+ * at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.  The IDLE
+ * thread is the thread that the system boots on and, eventually, becomes the
+ * idle, do nothing task that runs only when there is nothing else to run.
+ * The heap continues from there until the configured end of memory.
+ * g_idle_topstack is the beginning of this heap region (not necessarily
+ * aligned).
+ */
+
+const uint32_t g_idle_topstack = (uint32_t)&_ebss +
+  CONFIG_IDLETHREAD_STACKSIZE;
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/* Sanity check */
+
+#if (CONFIG_RAM_START < CXD56_RAM_BASE) || \
+  (CONFIG_RAM_START + CONFIG_RAM_SIZE > CXD56_RAM_BASE + CXD56_RAM_SIZE)
+#  error Invalid memory configuration
+#endif
+
+#define MM_RAM_END CONFIG_RAM_END
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_heap_color
+ *
+ * Description:
+ *   Set heap memory to a known, non-zero state to checking heap usage.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_HEAP_COLORATION
+static inline void up_heap_color(FAR void *start, size_t size)
+{
+  memset(start, HEAP_COLOR, size);
+}
+#else
+#  define up_heap_color(start,size)
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ *   This function will be called to dynamically set aside the heap region.
+ *
+ *   For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
+ *   user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
+ *   size of the unprotected, user-space heap.
+ *
+ *   If a protected kernel-space heap is provided, the kernel heap must be
+ *   allocated (and protected) by an analogous up_allocate_kheap().
+ *
+ ****************************************************************************/
+
+void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
+{
+  /* Start with the first SRAM region */
+
+  board_autoled_on(LED_HEAPALLOCATE);
+  *heap_start = (FAR void *)g_idle_topstack;
+  *heap_size = MM_RAM_END - g_idle_topstack;
+
+  /* Colorize the heap for debug */
+
+  up_heap_color(*heap_start, *heap_size);
+}
diff --git a/arch/arm/src/cxd56xx/cxd56_clock.c b/arch/arm/src/cxd56xx/cxd56_clock.c
new file mode 100644
index 00000000000..ecdc5c3b9b9
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_clock.c
@@ -0,0 +1,2357 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_clock.c
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+
+#include "up_arch.h"
+
+#include "chip.h"
+#include "hardware/cxd56_crg.h"
+#include "hardware/cxd5602_backupmem.h"
+#include "hardware/cxd5602_topreg.h"
+
+#include "cxd56_clock.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_PM
+#  define pmerr(fmt, ...)  logerr(fmt, ## __VA_ARGS__)
+#  define pminfo(fmt, ...) loginfo(fmt, ## __VA_ARGS__)
+#  define pmdbg(fmt, ...)  logdebug(fmt, ## __VA_ARGS__)
+#else
+#  define pmerr(fmt, ...)
+#  define pminfo(fmt, ...)
+#  define pmdbg(fmt, ...)
+#endif
+
+/* For enable_pwd, disable_pwd (digital domain) */
+
+#define PDID_SCU         0
+#define PDID_APP_DSP     9
+#define PDID_APP_SUB    10
+#define PDID_APP_AUD    14
+
+/* For enable_apwd, disable_apwd (analog domain) */
+
+#define APDID_RCOSC      0
+#define APDID_XOSC       1
+#define APDID_HPADC     12
+#define APDID_LPADC     13
+
+/* Compiler hint shortcut */
+
+#define __unused __attribute__((unused))
+
+#define ALIGNUP(v, a) (((v) + ((a) - 1)) & ~((a) - 1))
+#define TILESIZESHIT 17
+#define TILESIZE     (1 << TILESIZESHIT)
+#define TILEALIGN(v)  ALIGNUP(v, TILESIZE)
+#define TILEALIGNIDX(v) (((v) >> TILESIZESHIT) & 0xf)
+
+#ifndef CONFIG_CXD56_UART2_BASE_CLOCK_DIVIDER
+#define CONFIG_CXD56_UART2_BASE_CLOCK_DIVIDER 4
+#endif /* CONFIG_CXD56_UART2_BASE_CLOCK_DIVIDER */
+
+/*
+ * Flags for IMG device active
+ *
+ * This flags for fixed clock devices.
+ */
+
+#define FLAG_IMG_CISIF   (1 << 0)
+#define FLAG_IMG_GE2D    (1 << 1)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+enum clock_source {
+  RCOSC = 1,
+  RTC,
+  RCRTC,
+  XOSC,
+  SYSPLL,
+};
+
+struct scu_peripheral
+{
+  int8_t cken;
+  int8_t swreset;
+  int8_t crgintmask;
+  int8_t reserved;
+};
+
+struct power_domain
+{
+  uint8_t refs[16];
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static void cxd56_img_clock_enable(void);
+static void cxd56_img_clock_disable(void);
+static void cxd56_scu_clock_ctrl(uint32_t block, uint32_t intr, int on);
+static void cxd56_scu_peri_clock_enable(FAR const struct scu_peripheral *p) __unused;
+static void cxd56_scu_peri_clock_disable(FAR const struct scu_peripheral *p) __unused;
+static void cxd56_scu_peri_clock_gating(FAR const struct scu_peripheral *p, int enable) __unused;
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static struct power_domain g_digital;
+static struct power_domain g_analog;
+
+/* Store calibrated RCOSC */
+
+static uint32_t rcosc_clock = 0;
+
+/* Save used IMG block devices */
+
+static uint32_t g_active_imgdevs = 0;
+
+/* Exclusive control */
+
+static sem_t g_clockexc = SEM_INITIALIZER(1);
+
+/* For peripherals inside SCU block
+ *
+ * Related registers are:
+ *  cken       : SCU_CKEN
+ *  swreset    : SWRESET_SCU
+ *  crgintmask : CRG_INT_CLR0, CRG_INT_STAT_RAW0
+ *
+ * Each member values are indicated the number of bit in apropriate registers.
+ */
+
+#if defined(CONFIG_CXD56_SPI3)
+const struct scu_peripheral g_scuspi =
+{
+  .cken = 3,
+  .swreset = 8,
+  .crgintmask = 10,
+};
+#endif
+#if defined(CONFIG_CXD56_I2C0)
+const struct scu_peripheral g_scui2c0 =
+{
+  .cken = 1,
+  .swreset = 5,
+  .crgintmask = 11,
+};
+#endif
+#if defined(CONFIG_CXD56_I2C1)
+const struct scu_peripheral g_scui2c1 =
+{
+  .cken = 2,
+  .swreset = 6,
+  .crgintmask = 12,
+};
+#endif
+#if defined(CONFIG_CXD56_SCUSEQ)
+const struct scu_peripheral g_scuseq =
+{
+  .cken = 4,
+  .swreset = 7,
+  .crgintmask = 13,
+};
+#endif
+#if defined(CONFIG_CXD56_ADC)
+const struct scu_peripheral g_sculpadc =
+{
+  .cken = 6,
+  .swreset = 4,
+  .crgintmask = 17,
+};
+const struct scu_peripheral g_scuhpadc =
+{
+  .cken = 7,
+  .swreset = 2,
+  .crgintmask = 16,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static void clock_semtake(sem_t *id)
+{
+  if (!up_interrupt_context())
+    {
+      sem_wait(id);
+    }
+}
+
+static void clock_semgive(sem_t *id)
+{
+  if (!up_interrupt_context())
+    {
+      sem_post(id);
+    }
+}
+
+static void busy_wait(int cnt)
+{
+  for (; cnt; cnt--)
+    {
+      getreg32(CXD56_TOPREG_CHIP_ID);
+    }
+}
+
+static void do_power_control(void)
+{
+  uint32_t stat;
+
+  putreg32(0xf1f, CXD56_TOPREG_PMU_INT_CLR);
+  putreg32(0xf1f, CXD56_TOPREG_PMU_INT_MASK);
+  putreg32(1, CXD56_TOPREG_PMU_PW_CTL);
+
+  do
+    {
+      stat = getreg32(CXD56_TOPREG_PMU_RAW_INT_STAT);
+      stat &= 0x1f;
+    }
+  while (stat == 0);
+
+  DEBUGASSERT(stat == 1);
+
+  putreg32(0xf1f, CXD56_TOPREG_PMU_INT_CLR);
+}
+
+static inline void release_pwd_reset(uint32_t domain)
+{
+  /* Reset acts only belows
+   *   [ 0] SCU
+   *   [ 6] SYSIOP_SUB
+   *   [ 8] APP
+   *   [12] GNSS_ITP
+   *   [13] GNSS
+   */
+
+  if (domain & 0x3141)
+    {
+      /* Release power domain reset */
+
+      putreg32(domain | domain <<16, CXD56_TOPREG_PWD_RESET0);
+    }
+}
+
+static void enable_pwd(int pdid)
+{
+  uint32_t stat;
+  int domain = 1u << pdid;
+
+  stat = getreg32(CXD56_TOPREG_PWD_STAT);
+  if ((stat & domain) != domain)
+    {
+      putreg32((domain|(domain<<16)), CXD56_TOPREG_PWD_CTL);
+      do_power_control();
+      release_pwd_reset(domain);
+    }
+  g_digital.refs[pdid]++;
+}
+
+static void disable_pwd(int pdid)
+{
+  uint32_t stat;
+  int domain = 1u << pdid;
+
+  stat = getreg32(CXD56_TOPREG_PWD_STAT);
+  if (stat & domain)
+    {
+      g_digital.refs[pdid]--;
+      if (g_digital.refs[pdid] == 0)
+        {
+          putreg32(domain<<16, CXD56_TOPREG_PWD_CTL);
+          do_power_control();
+        }
+    }
+}
+
+static void enable_apwd(int apdid)
+{
+  uint32_t stat;
+  int domain = 1u << apdid;
+
+  stat = getreg32(CXD56_TOPREG_ANA_PW_STAT);
+  if ((stat & domain) != domain)
+    {
+      putreg32(domain|(domain<<16), CXD56_TOPREG_ANA_PW_CTL);
+      do_power_control();
+    }
+  g_analog.refs[apdid]++;
+}
+
+static void disable_apwd(int apdid)
+{
+  uint32_t stat;
+  int domain = 1u << apdid;
+
+  stat = getreg32(CXD56_TOPREG_ANA_PW_STAT);
+  if (stat & domain)
+    {
+      g_analog.refs[apdid]--;
+      if (g_analog.refs[apdid] == 0)
+        {
+          putreg32(domain<<16, CXD56_TOPREG_ANA_PW_CTL);
+          do_power_control();
+        }
+    }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+/****************************************************************************
+ * Name: cxd56_rcosc_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_rcosc_enable(void)
+{
+  enable_apwd(APDID_RCOSC);
+}
+
+/****************************************************************************
+ * Name: cxd56_rcosc_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_rcosc_disable(void)
+{
+  disable_apwd(APDID_RCOSC);
+}
+
+/****************************************************************************
+ * Name: cxd56_xosc_enable
+ *
+ * Description:
+ *   Enable XOSC (if needed)
+ *
+ ****************************************************************************/
+
+void cxd56_xosc_enable(void)
+{
+  enable_apwd(APDID_XOSC);
+}
+
+/****************************************************************************
+ * Name: cxd56_xosc_disable
+ *
+ * Description:
+ *   Disable XOSC.
+ *
+ * CAUTION:
+ *   This function is tentative. We need to consider that clock source control
+ *   with other devices which XOSC is used.
+ *
+ ****************************************************************************/
+
+void cxd56_xosc_disable(void)
+{
+  disable_apwd(APDID_XOSC);
+}
+
+/****************************************************************************
+ * Name: cxd56_spif_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_spif_clock_enable(void)
+{
+  uint32_t val, rst;
+
+  val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
+  if (val & CK_SFC)
+    {
+      return;
+    }
+
+  putreg32(val | CK_SFC, CXD56_TOPREG_SYSIOP_SUB_CKEN);
+
+  busy_wait(10);
+
+  putreg32(val, CXD56_TOPREG_SYSIOP_SUB_CKEN);
+  rst = getreg32(CXD56_TOPREG_SWRESET_BUS);
+  putreg32(rst | XRST_SFC, CXD56_TOPREG_SWRESET_BUS);
+  putreg32(val | CK_SFC, CXD56_TOPREG_SYSIOP_SUB_CKEN);
+}
+
+/****************************************************************************
+ * Name: cxd56_spif_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_spif_clock_disable(void)
+{
+  uint32_t val, rst;
+
+  val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
+  if (!(val & CK_SFC))
+    {
+      return;
+    }
+
+  putreg32(val & ~CK_SFC, CXD56_TOPREG_SYSIOP_SUB_CKEN);
+  rst = getreg32(CXD56_TOPREG_SWRESET_BUS);
+  putreg32(rst & ~XRST_SFC, CXD56_TOPREG_SWRESET_BUS);
+}
+
+/****************************************************************************
+ * Name: cxd56_get_cpu_baseclk
+ *
+ * Description:
+ *   Get CPU clock.
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_cpu_baseclk(void)
+{
+  uint32_t val;
+  int n, m;
+
+  val = getreg32(CXD56_CRG_GEAR_AHB);
+  n = (val >> 16) & 0x7f;
+  m = val & 0x7f;
+
+  if (n && m)
+    {
+      return cxd56_get_appsmp_baseclock() * n / m;
+    }
+  else
+    {
+      return 0;
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_cpu_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_cpu_clock_enable(int cpu)
+{
+  cxd56_cpulist_clock_enable(1 << cpu);
+}
+
+/****************************************************************************
+ * Name: cxd56_cpulist_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_cpulist_clock_enable(uint32_t cpus)
+{
+  uint32_t c, bits = (cpus & 0x3f) << 16;
+
+  c = getreg32(CXD56_CRG_CK_GATE_AHB);
+  putreg32(c | bits, CXD56_CRG_CK_GATE_AHB);
+}
+
+/****************************************************************************
+ * Name: cxd56_cpu_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_cpu_clock_disable(int cpu)
+{
+  cxd56_cpulist_clock_disable(1 << cpu);
+}
+
+/****************************************************************************
+ * Name: cxd56_cpulist_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_cpulist_clock_disable(uint32_t cpus)
+{
+  uint32_t c, bits = (cpus & 0x3f) << 16;
+
+  c = getreg32(CXD56_CRG_CK_GATE_AHB);
+  putreg32(c & ~bits, CXD56_CRG_CK_GATE_AHB);
+}
+
+/****************************************************************************
+ * Name: cxd56_cpu_reset
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_cpu_reset(int cpu)
+{
+  cxd56_cpulist_reset(1 << cpu);
+}
+
+/****************************************************************************
+ * Name: cxd56_cpulist_reset
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_cpulist_reset(uint32_t cpus)
+{
+  uint32_t c, r, bits = (cpus & 0x3f) << 16;
+
+  /* Reset assert */
+
+  r = getreg32(CXD56_CRG_RESET);
+  putreg32(r & ~bits, CXD56_CRG_RESET);
+
+  /* Temporary provide clock for perform reset */
+
+  c = getreg32(CXD56_CRG_CK_GATE_AHB);
+  putreg32(c | bits, CXD56_CRG_CK_GATE_AHB);
+  busy_wait(10);
+  putreg32(c, CXD56_CRG_CK_GATE_AHB);
+
+  /* Reset deassert */
+
+  putreg32(r | bits, CXD56_CRG_RESET);
+}
+
+/****************************************************************************
+ * Name: cxd56_usb_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_usb_clock_enable(void)
+{
+  uint32_t c, r;
+
+  enable_pwd(PDID_APP_SUB);
+
+  c = getreg32(CXD56_CRG_CK_GATE_AHB);
+  if (!(c & CK_GATE_USB))
+    {
+      r = getreg32(CXD56_CRG_RESET);
+      putreg32(r & ~XRS_USB, CXD56_CRG_RESET);
+      putreg32(c | CK_GATE_USB, CXD56_CRG_CK_GATE_AHB);
+      busy_wait(10);
+      putreg32(r | XRS_USB, CXD56_CRG_RESET);
+      putreg32(1, CXD56_TOPREG_USBPHY_CKEN);
+      putreg32(0x00010002, CXD56_CRG_GEAR_PER_USB);
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_usb_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_usb_clock_disable(void)
+{
+  uint32_t c, r;
+
+  c = getreg32(CXD56_CRG_CK_GATE_AHB);
+  if (c & CK_GATE_USB)
+    {
+      putreg32(0, CXD56_CRG_GEAR_PER_USB);
+      putreg32(0, CXD56_TOPREG_USBPHY_CKEN);
+      putreg32(c & ~CK_GATE_USB, CXD56_CRG_CK_GATE_AHB);
+      r = getreg32(CXD56_CRG_RESET);
+      putreg32(r & ~XRS_USB, CXD56_CRG_RESET);
+    }
+
+  disable_pwd(PDID_APP_SUB);
+}
+
+/****************************************************************************
+ * Name: cxd56_emmc_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_emmc_clock_enable(uint32_t div, uint32_t driver, uint32_t sample)
+{
+  uint32_t c, r, g;
+
+  enable_pwd(PDID_APP_SUB);
+
+  c = getreg32(CXD56_CRG_CKEN_EMMC);
+  if (c == 7)
+    {
+      /* already enabled */
+
+      return;
+    }
+
+  r = getreg32(CXD56_CRG_RESET);
+  r = (r & ~XRS_MMC) | XRS_MMC_CRG;
+  putreg32(r, CXD56_CRG_RESET);
+
+  g = getreg32(CXD56_CRG_CK_GATE_AHB);
+  putreg32(g | CK_GATE_MMC, CXD56_CRG_CK_GATE_AHB);
+  putreg32(7, CXD56_CRG_CKEN_EMMC);
+
+  busy_wait(10);
+
+  putreg32(g & ~CK_GATE_MMC, CXD56_CRG_CK_GATE_AHB);
+  putreg32(0, CXD56_CRG_CKEN_EMMC);
+
+  r |= XRS_MMC;
+  putreg32(r, CXD56_CRG_RESET);
+
+  putreg32(g | CK_GATE_MMC, CXD56_CRG_CK_GATE_AHB);
+
+  /* T.B.D: This register located at eMMC controller */
+
+  *((volatile uint32_t *)0x4e201108) = (div << 30) |
+    ((driver & 0x7f) << 23) | ((sample & 0x7f) << 16);
+
+  putreg32(7, CXD56_CRG_CKEN_EMMC);
+}
+
+/****************************************************************************
+ * Name: cxd56_emmc_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_emmc_clock_disable(void)
+{
+  uint32_t c, r, g;
+
+  c = getreg32(CXD56_CRG_CKEN_EMMC);
+  if (c != 7)
+    {
+      return;
+    }
+
+  g = getreg32(CXD56_CRG_CK_GATE_AHB);
+  putreg32(g & ~CK_GATE_MMC, CXD56_CRG_CK_GATE_AHB);
+  putreg32(0, CXD56_CRG_CKEN_EMMC);
+
+  r = getreg32(CXD56_CRG_RESET);
+  putreg32(r & ~(XRS_MMC|XRS_MMC_CRG), CXD56_CRG_RESET);
+
+  disable_pwd(PDID_APP_SUB);
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_sdio_clock_enable(void)
+{
+  uint32_t c, r;
+
+  enable_pwd(PDID_APP_SUB);
+
+  c = getreg32(CXD56_CRG_CK_GATE_AHB);
+  if (!(c & CK_GATE_SDIO))
+    {
+      r = getreg32(CXD56_CRG_RESET);
+      putreg32(r & ~XRS_SDIO, CXD56_CRG_RESET);
+      putreg32(c | CK_GATE_SDIO, CXD56_CRG_CK_GATE_AHB);
+      putreg32(0x00010002, CXD56_CRG_GEAR_PER_SDIO);
+      busy_wait(10);
+      putreg32(r | XRS_SDIO, CXD56_CRG_RESET);
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_sdio_clock_disable(void)
+{
+  uint32_t c, r;
+
+  c = getreg32(CXD56_CRG_CK_GATE_AHB);
+  if (c & CK_GATE_SDIO)
+    {
+      putreg32(0, CXD56_CRG_GEAR_PER_SDIO);
+      putreg32(c & ~CK_GATE_SDIO, CXD56_CRG_CK_GATE_AHB);
+      r = getreg32(CXD56_CRG_RESET);
+      putreg32(r & ~XRS_SDIO, CXD56_CRG_RESET);
+    }
+
+  disable_pwd(PDID_APP_SUB);
+}
+
+/****************************************************************************
+ * Name: cxd56_audio_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_audio_clock_enable(uint32_t clk, uint32_t div)
+{
+  enable_pwd(PDID_APP_AUD);
+
+  modifyreg32(CXD56_TOPREG_APP_CKSEL, AUD_MCLK_MASK, clk);
+  if (AUD_MCLK_XOSC == clk)
+    {
+      putreg32(div, CXD56_TOPREG_APP_DIV);
+    }
+
+  modifyreg32(CXD56_TOPREG_APP_CKEN, 0, APP_CKEN_MCLK);
+  modifyreg32(CXD56_CRG_RESET, 0, XRS_AUD);
+  modifyreg32(CXD56_CRG_CK_GATE_AHB, 0, CK_GATE_AUD);
+}
+
+/****************************************************************************
+ * Name: cxd56_audio_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_audio_clock_disable(void)
+{
+  modifyreg32(CXD56_CRG_RESET, XRS_AUD, 0);
+  modifyreg32(CXD56_CRG_CK_GATE_AHB, CK_GATE_AUD, 0);
+  modifyreg32(CXD56_TOPREG_APP_CKEN, APP_CKEN_MCLK, 0);
+
+  disable_pwd(PDID_APP_AUD);
+}
+
+/****************************************************************************
+ * Name: cxd56_audio_clock_is_enabled
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+bool cxd56_audio_clock_is_enabled(void)
+{
+  return (getreg32(CXD56_CRG_CK_GATE_AHB) & CK_GATE_AUD) == CK_GATE_AUD;
+}
+
+#if defined(CONFIG_CXD56_SPI0)
+/****************************************************************************
+ * Name: cxd56_spim_clock_enable
+ *
+ * Description:
+ *   Enable SPI channel 0 device clock. This is a SYS domain peripheral.
+ *   I expect SYSIOP_SUB power domain already enabled.
+ *
+ ****************************************************************************/
+
+static void cxd56_spim_clock_enable(void)
+{
+  uint32_t val, rst;
+
+  val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
+  if (val & CK_SPIM)
+    {
+      return;
+    }
+
+  putreg32(val | CK_SPIM | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
+
+  busy_wait(10);
+
+  putreg32(val | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
+  rst = getreg32(CXD56_TOPREG_SWRESET_BUS);
+  putreg32(rst | XRST_SPIM, CXD56_TOPREG_SWRESET_BUS);
+  putreg32(val | CK_SPIM | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
+}
+
+/****************************************************************************
+ * Name: cxd56_spim_clock_disable
+ *
+ * Description:
+ *   Disable SPI channel 0 device clock.
+ *
+ ****************************************************************************/
+
+static void cxd56_spim_clock_disable(void)
+{
+  uint32_t val, rst, mask;
+
+  val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
+  if (!(val & CK_SPIM))
+    {
+      return;
+    }
+
+  mask = CK_SPIM;
+  if (!(val & (CK_UART1 | CK_I2CM)))
+    {
+      mask |= CK_COM_BRG | CK_AHB_BRG_COMIF;
+    }
+
+  putreg32(val & ~mask, CXD56_TOPREG_SYSIOP_SUB_CKEN);
+  rst = getreg32(CXD56_TOPREG_SWRESET_BUS);
+  putreg32(rst & ~XRST_SPIM, CXD56_TOPREG_SWRESET_BUS);
+}
+#endif
+
+#if defined(CONFIG_CXD56_SPI4)
+/****************************************************************************
+ * Name: cxd56_img_spi_clock_enable
+ *
+ * Description:
+ *   Enable SPI channel 4 device clock.
+ *   This is called IMG_SPI, located at APP domain and inside of IMG block.
+ *
+ ****************************************************************************/
+
+static void cxd56_img_spi_clock_enable(void)
+{
+  clock_semtake(&g_clockexc);
+  enable_pwd(PDID_APP_SUB);
+  cxd56_img_clock_enable();
+  putreg32(0x00010002, CXD56_CRG_GEAR_IMG_SPI);
+  clock_semgive(&g_clockexc);
+}
+
+/****************************************************************************
+ * Name: cxd56_img_spi_clock_disable
+ *
+ * Description:
+ *   Disable SPI channel 4 device clock.
+ *
+ ****************************************************************************/
+
+static void cxd56_img_spi_clock_disable(void)
+{
+  clock_semtake(&g_clockexc);
+  putreg32(0, CXD56_CRG_GEAR_IMG_SPI);
+  cxd56_img_clock_disable();
+  disable_pwd(PDID_APP_SUB);
+  clock_semgive(&g_clockexc);
+}
+#endif
+
+#if defined(CONFIG_CXD56_SPI5)
+/****************************************************************************
+ * Name: cxd56_img_wspi_clock_enable
+ *
+ * Description:
+ *   Enable SPI channel 5 device clock.
+ *   This is called IMG_WSPI, located at APP domain and inside of IMG block.
+ *
+ ****************************************************************************/
+
+static void cxd56_img_wspi_clock_enable(void)
+{
+  clock_semtake(&g_clockexc);
+  enable_pwd(PDID_APP_SUB);
+  cxd56_img_clock_enable();
+  putreg32(0x00010004, CXD56_CRG_GEAR_IMG_WSPI);
+  clock_semgive(&g_clockexc);
+}
+
+/****************************************************************************
+ * Name: cxd56_img_wspi_clock_disable
+ *
+ * Description:
+ *   Disable SPI channel 5 device clock.
+ *
+ ****************************************************************************/
+
+static void cxd56_img_wspi_clock_disable(void)
+{
+  clock_semtake(&g_clockexc);
+  putreg32(0, CXD56_CRG_GEAR_IMG_WSPI);
+  cxd56_img_clock_disable();
+  disable_pwd(PDID_APP_SUB);
+  clock_semgive(&g_clockexc);
+}
+#endif
+
+void cxd56_spi_clock_enable(int port)
+{
+#if defined(CONFIG_CXD56_SPI4)
+  if (port == 4)
+    {
+      cxd56_img_spi_clock_enable();
+    }
+#endif
+#if defined(CONFIG_CXD56_SPI5)
+  if (port == 5)
+    {
+      cxd56_img_wspi_clock_enable();
+    }
+#endif
+#if defined(CONFIG_CXD56_SPI0)
+  if (port == 0)
+    {
+      cxd56_spim_clock_enable();
+    }
+#endif
+#if defined(CONFIG_CXD56_SPI3)
+  if (port == 3)
+    {
+      cxd56_scu_peri_clock_enable(&g_scuspi);
+    }
+#endif
+}
+
+void cxd56_spi_clock_disable(int port)
+{
+#if defined(CONFIG_CXD56_SPI4)
+  if (port == 4)
+    {
+      cxd56_img_spi_clock_disable();
+    }
+#endif
+#if defined(CONFIG_CXD56_SPI5)
+  if (port == 5)
+    {
+      cxd56_img_wspi_clock_disable();
+    }
+#endif
+#if defined(CONFIG_CXD56_SPI0)
+  if (port == 0)
+    {
+      cxd56_spim_clock_disable();
+    }
+#endif
+#if defined(CONFIG_CXD56_SPI3)
+  if (port == 3)
+    {
+      cxd56_scu_peri_clock_disable(&g_scuspi);
+    }
+#endif
+}
+
+/****************************************************************************
+ * Name: cxd56_spi_clock_gate_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_spi_clock_gate_enable(int port)
+{
+#if defined(CONFIG_CXD56_SPI3)
+  if (port == 3)
+    {
+      cxd56_scu_peri_clock_gating(&g_scuspi, 1);
+    }
+#endif
+}
+
+/****************************************************************************
+ * Name: cxd56_spi_clock_gate_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_spi_clock_gate_disable(int port)
+{
+#if defined(CONFIG_CXD56_SPI3)
+  if (port == 3)
+    {
+      cxd56_scu_peri_clock_gating(&g_scuspi, 0);
+    }
+#endif
+}
+
+/****************************************************************************
+ * Name: cxd56_spi_clock_gear_adjust
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_spi_clock_gear_adjust(int port, uint32_t maxfreq)
+{
+  uint32_t baseclock;
+  uint32_t gear;
+  uint32_t divisor;
+  uint32_t maxdivisor;
+  uint32_t addr;
+
+  if (maxfreq == 0)
+    {
+      return;
+    }
+
+#if defined(CONFIG_CXD56_SPI4)
+  if (port == 4)
+    {
+      maxdivisor = 0x7f;
+      addr       = CXD56_CRG_GEAR_IMG_SPI;
+    }
+  else
+#endif
+#if defined(CONFIG_CXD56_SPI5)
+  if (port == 5)
+    {
+      maxdivisor = 0xf;
+      addr       = CXD56_CRG_GEAR_IMG_WSPI;
+    }
+  else
+#endif
+    {
+      return;
+    }
+
+  clock_semtake(&g_clockexc);
+  baseclock = cxd56_get_appsmp_baseclock();
+  if (baseclock != 0)
+    {
+      divisor = baseclock / (maxfreq * 2);
+      if (baseclock % (maxfreq * 2))
+        {
+          divisor += 1;
+        }
+      if (divisor > maxdivisor)
+        {
+          divisor = maxdivisor;
+        }
+      gear = 0x00010000 | divisor;
+      putreg32(gear, addr);
+    }
+  clock_semgive(&g_clockexc);
+}
+
+#if defined(CONFIG_CXD56_I2C2)
+/****************************************************************************
+ * Name: cxd56_i2cm_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+static void cxd56_i2cm_clock_enable(void)
+{
+  uint32_t val, rst;
+
+  val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
+  if (val & CK_I2CM)
+    {
+      return;
+    }
+
+  putreg32(val | CK_I2CM | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
+
+  busy_wait(10);
+
+  putreg32(val | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
+  rst = getreg32(CXD56_TOPREG_SWRESET_BUS);
+  putreg32(rst | XRST_I2CM, CXD56_TOPREG_SWRESET_BUS);
+  putreg32(val | CK_I2CM | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN);
+}
+
+/****************************************************************************
+ * Name: cxd56_i2c0_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+static void cxd56_i2cm_clock_disable(void)
+{
+  uint32_t val, rst, mask;
+
+  val = getreg32(CXD56_TOPREG_SYSIOP_SUB_CKEN);
+  if (!(val & CK_I2CM))
+    {
+      return;
+    }
+
+  mask = CK_I2CM;
+  if (!(val & (CK_UART1 | CK_SPIM)))
+    {
+      mask |= CK_COM_BRG | CK_AHB_BRG_COMIF;
+    }
+
+  putreg32(val & ~mask, CXD56_TOPREG_SYSIOP_SUB_CKEN);
+  rst = getreg32(CXD56_TOPREG_SWRESET_BUS);
+  putreg32(rst & ~XRST_I2CM, CXD56_TOPREG_SWRESET_BUS);
+}
+#endif
+
+/****************************************************************************
+ * Name: cxd56_i2c_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_i2c_clock_enable(int port)
+{
+#if defined(CONFIG_CXD56_I2C0)
+  if (port == 0)
+    {
+      cxd56_scu_peri_clock_enable(&g_scui2c0);
+    }
+#endif
+#if defined(CONFIG_CXD56_I2C1)
+  if (port == 1)
+    {
+      cxd56_scu_peri_clock_enable(&g_scui2c1);
+    }
+#endif
+#if defined(CONFIG_CXD56_I2C2)
+  if (port == 2)
+    {
+      cxd56_i2cm_clock_enable();
+    }
+#endif
+}
+
+/****************************************************************************
+ * Name: cxd56_i2c1_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_i2c_clock_disable(int port)
+{
+#if defined(CONFIG_CXD56_I2C0)
+  if (port == 0)
+    {
+      cxd56_scu_peri_clock_disable(&g_scui2c0);
+    }
+#endif
+#if defined(CONFIG_CXD56_I2C1)
+  if (port == 1)
+    {
+      cxd56_scu_peri_clock_disable(&g_scui2c1);
+    }
+#endif
+#if defined(CONFIG_CXD56_I2C2)
+  if (port == 2)
+    {
+      cxd56_i2cm_clock_disable();
+    }
+#endif
+}
+
+/****************************************************************************
+ * Name: cxd56_i2c_clock_gate_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_i2c_clock_gate_enable(int port)
+{
+#if defined(CONFIG_CXD56_I2C0)
+  if (port == 0)
+    {
+      cxd56_scu_peri_clock_gating(&g_scui2c0, 1);
+    }
+#endif
+#if defined(CONFIG_CXD56_I2C1)
+  if (port == 1)
+    {
+      cxd56_scu_peri_clock_gating(&g_scui2c1, 1);
+    }
+#endif
+}
+
+/****************************************************************************
+ * Name: cxd56_i2c_clock_gate_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_i2c_clock_gate_disable(int port)
+{
+#if defined(CONFIG_CXD56_I2C0)
+  if (port == 0)
+    {
+      cxd56_scu_peri_clock_gating(&g_scui2c0, 0);
+    }
+#endif
+#if defined(CONFIG_CXD56_I2C1)
+  if (port == 1)
+    {
+      cxd56_scu_peri_clock_gating(&g_scui2c1, 0);
+    }
+#endif
+}
+
+uint32_t cxd56_get_img_uart_baseclock(void)
+{
+    uint32_t val;
+    int n, m;
+
+    val = getreg32(CXD56_CRG_GEAR_IMG_UART);
+    n = (val >> 16) & 1;
+    m = val & 0x7f;
+
+    if (n && m)
+    {
+        return cxd56_get_appsmp_baseclock() * n / m;
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_img_uart_clock_enable
+ *
+ * Description:
+ *   Enable img uart clock.
+ *
+ ****************************************************************************/
+
+void cxd56_img_uart_clock_enable()
+{
+  uint32_t val = 0;
+
+  clock_semtake(&g_clockexc);
+
+  enable_pwd(PDID_APP_SUB);
+  cxd56_img_clock_enable();
+
+  val = getreg32(CXD56_CRG_GEAR_IMG_UART);
+  val |= (1UL << 16);
+#ifdef CONFIG_CXD56_UART2
+  val &= ~0x7f;
+  val |= CONFIG_CXD56_UART2_BASE_CLOCK_DIVIDER;
+#endif /* CONFIG_CXD56_UART2 */
+  putreg32(val, CXD56_CRG_GEAR_IMG_UART);
+
+  clock_semgive(&g_clockexc);
+}
+
+/****************************************************************************
+ * Name: cxd56_img_uart_clock_dsiable
+ *
+ * Description:
+ *   Disable img uart clock.
+ *
+ ****************************************************************************/
+
+void cxd56_img_uart_clock_disable()
+{
+  uint32_t val = 0;
+
+  clock_semtake(&g_clockexc);
+
+  val = getreg32(CXD56_CRG_GEAR_IMG_UART);
+  val &= ~(1UL << 16);
+  putreg32(val, CXD56_CRG_GEAR_IMG_UART);
+
+  cxd56_img_clock_disable();
+  disable_pwd(PDID_APP_SUB);
+
+  clock_semgive(&g_clockexc);
+}
+
+/****************************************************************************
+ * Name: cxd56_img_cisif_clock_enable
+ *
+ * Description:
+ *   Enable img cisif clock.
+ *
+ ****************************************************************************/
+
+void cxd56_img_cisif_clock_enable(void)
+{
+  clock_semtake(&g_clockexc);
+
+  enable_pwd(PDID_APP_SUB);
+  cxd56_img_clock_enable();
+  g_active_imgdevs |= FLAG_IMG_CISIF;
+
+  clock_semgive(&g_clockexc);
+}
+
+/****************************************************************************
+ * Name: cxd56_img_cisif_clock_disable
+ *
+ * Description:
+ *   Disable img cisif clock.
+ *
+ ****************************************************************************/
+
+void cxd56_img_cisif_clock_disable(void)
+{
+  clock_semtake(&g_clockexc);
+
+  g_active_imgdevs &= ~FLAG_IMG_CISIF;
+  cxd56_img_clock_disable();
+  disable_pwd(PDID_APP_SUB);
+
+  clock_semgive(&g_clockexc);
+}
+
+/****************************************************************************
+ * Name: cxd56_img_ge2d_clock_enable
+ *
+ * Description:
+ *   Enable img cisif clock.
+ *
+ ****************************************************************************/
+
+void cxd56_img_ge2d_clock_enable(void)
+{
+  clock_semtake(&g_clockexc);
+
+  enable_pwd(PDID_APP_SUB);
+  cxd56_img_clock_enable();
+  g_active_imgdevs |= FLAG_IMG_GE2D;
+
+  clock_semgive(&g_clockexc);
+}
+
+/****************************************************************************
+ * Name: cxd56_img_ge2d_clock_disable
+ *
+ * Description:
+ *   Disable img cisif clock.
+ *
+ ****************************************************************************/
+
+void cxd56_img_ge2d_clock_disable(void)
+{
+  clock_semtake(&g_clockexc);
+
+  g_active_imgdevs &= ~FLAG_IMG_GE2D;
+  cxd56_img_clock_disable();
+  disable_pwd(PDID_APP_SUB);
+
+  clock_semgive(&g_clockexc);
+}
+
+static uint32_t cxd56_get_clock(enum clock_source cs)
+{
+  if (!rcosc_clock)
+    {
+      rcosc_clock = BKUP->rcosc_clock;
+    }
+
+  switch (cs)
+    {
+    case RCOSC:
+      return rcosc_clock;
+    case RTC:
+      return 32768;
+    case RCRTC:
+      return rcosc_clock / 250;
+    case XOSC:
+      return CONFIG_CXD56_XOSC_CLOCK;
+    case SYSPLL:
+      {
+        uint32_t ctrl, rc, fb;
+
+        ctrl = getreg32(CXD56_TOPREG_SYS_PLL_CTRL2);
+        rc = ctrl >> 30;
+        fb = (ctrl >> 27) & 0x7;
+
+        switch (rc)
+          {
+          case 0:
+            rc = 1;
+            break;
+          case 1:
+            rc = 2;
+            break;
+          case 3:
+            rc = 4;
+            break;
+          }
+
+        switch (fb)
+          {
+          case 0:
+            fb = 10;
+            break;
+          case 1:
+            fb = 12;
+            break;
+          case 2:
+            fb = 15;
+            break;
+          }
+
+        return CONFIG_CXD56_XOSC_CLOCK * fb / rc;
+      }
+    }
+
+  return 0;
+}
+
+uint32_t cxd56_get_sys_baseclock(void)
+{
+  uint32_t val;
+
+  val = getreg32(CXD56_TOPREG_CKSEL_ROOT);
+
+  switch ((val >> 22) & 0x3)
+    {
+    case 0:
+      return cxd56_get_clock(RCOSC);
+
+    case 1:
+      {
+        uint32_t div = ((val >> 10) & 0x3) + 1;
+
+        if (div == 4 && (val & (1<<2)))
+          {
+            div = 5;
+          }
+
+        return cxd56_get_clock(SYSPLL) / div;
+      }
+
+    case 2:
+      return cxd56_get_clock(XOSC);
+
+    case 3:
+      return cxd56_get_clock(RTC);
+    }
+
+  return 0;
+}
+
+uint32_t cxd56_get_scu_baseclock(void)
+{
+  uint32_t val;
+
+  val = getreg32(CXD56_TOPREG_CKSEL_SCU);
+
+  switch (val & 0x3)
+    {
+    case 0:
+      return cxd56_get_clock(RCOSC);
+
+    case 1:
+      return cxd56_get_clock(XOSC) / (((val >> 8) & 0x3) + 1);
+
+    case 2:
+      if (val & (1 << 4))
+        {
+          return cxd56_get_clock(RTC);
+        }
+      else
+        {
+          return cxd56_get_clock(RCRTC);
+        }
+    }
+
+  return 0;
+}
+
+uint32_t cxd56_get_appsmp_baseclock(void)
+{
+  uint32_t val = getreg32(CXD56_TOPREG_APP_CKSEL);
+
+  switch ((val >> 8) & 0x3)
+    {
+    case 0:
+      return cxd56_get_clock(RCOSC);
+
+    case 1:
+      {
+        uint32_t div = ((val >> 10) & 0x3) + 1;
+
+        if (div == 4 && (val & (1<<7)))
+          {
+            div = 5;
+          }
+
+        return cxd56_get_clock(SYSPLL) / div;
+      }
+
+    case 2:
+      return cxd56_get_clock(XOSC);
+
+    case 3:
+      return cxd56_get_clock(RTC);
+    }
+
+  return 0;
+}
+
+uint32_t cxd56_get_com_baseclock(void)
+{
+  uint32_t clock = cxd56_get_sys_baseclock();
+  uint32_t val = getreg32(CXD56_TOPREG_CKDIV_COM);
+
+  return clock / ((val & 0x1f) + 1);
+}
+
+uint32_t cxd56_get_sdio_baseclock(void)
+{
+  uint32_t val;
+  int n, m;
+
+  val = getreg32(CXD56_CRG_GEAR_PER_SDIO);
+  n = (val >> 16) & 1;
+  m = val & 0x3;
+
+  if (m != 0)
+    {
+      return cxd56_get_appsmp_baseclock() * n / m;
+    }
+  else
+    {
+      return 0;
+    }
+}
+
+uint32_t cxd56_get_img_spi_baseclock(void)
+{
+  uint32_t val;
+  int n, m;
+
+  val = getreg32(CXD56_CRG_GEAR_IMG_SPI);
+  n = (val >> 16) & 1;
+  m = val & 0x7f;
+
+  if (n && m)
+    {
+      return cxd56_get_appsmp_baseclock() * n / m;
+    }
+  else
+    {
+      return 0;
+    }
+}
+
+uint32_t cxd56_get_img_wspi_baseclock(void)
+{
+  uint32_t val;
+  int n, m;
+
+  val = getreg32(CXD56_CRG_GEAR_IMG_WSPI);
+  n = (val >> 16) & 1;
+  m = val & 0xf;
+
+  if (n && m)
+    {
+      return cxd56_get_appsmp_baseclock() * n / m;
+    }
+  else
+    {
+      return 0;
+    }
+}
+
+uint32_t cxd56_get_spi_baseclock(int port)
+{
+#if defined(CONFIG_CXD56_SPI4)
+  if (port == 4)
+    {
+      return cxd56_get_img_spi_baseclock();
+    }
+#endif
+#if defined(CONFIG_CXD56_SPI5)
+  if (port == 5)
+    {
+      return cxd56_get_img_wspi_baseclock();
+    }
+#endif
+#if defined(CONFIG_CXD56_SPI0)
+  if (port == 0)
+    {
+      return cxd56_get_com_baseclock();
+    }
+#endif
+#if defined(CONFIG_CXD56_SPI3)
+  if (port == 3)
+    {
+      return cxd56_get_scu_baseclock();
+    }
+#endif
+  return 0;
+}
+
+uint32_t cxd56_get_i2c_baseclock(int port)
+{
+#if defined(CONFIG_CXD56_I2C0)
+  if (port == 0)
+    {
+      return cxd56_get_scu_baseclock();
+    }
+#endif
+#if defined(CONFIG_CXD56_I2C1)
+  if (port == 1)
+    {
+      return cxd56_get_scu_baseclock();
+    }
+#endif
+#if defined(CONFIG_CXD56_I2C2)
+  if (port == 2)
+    {
+      return cxd56_get_com_baseclock();
+    }
+#endif
+  return 0;
+}
+
+uint32_t cxd56_get_pwm_baseclock(void)
+{
+  return cxd56_get_scu_baseclock();
+}
+
+static void cxd56_img_clock_enable(void)
+{
+  uint32_t val;
+
+  val = getreg32(CXD56_CRG_CK_GATE_AHB);
+  if (val & CK_GATE_IMG)
+    {
+      return;
+    }
+
+  putreg32(val | CK_GATE_IMG, CXD56_CRG_CK_GATE_AHB);
+  val = getreg32(CXD56_CRG_RESET);
+  putreg32(val | XRS_IMG, CXD56_CRG_RESET);
+}
+
+static void cxd56_img_clock_disable(void)
+{
+  uint32_t val;
+
+  /* Check IMG block peripherals in use */
+
+  val =  getreg32(CXD56_CRG_GEAR_IMG_UART) >> 16;
+  val |= getreg32(CXD56_CRG_GEAR_IMG_SPI) >> 16;
+  val |= getreg32(CXD56_CRG_GEAR_IMG_WSPI) >> 16;
+  val |= getreg32(CXD56_CRG_GEAR_N_IMG_VENB);
+
+  if (val || g_active_imgdevs)
+    {
+      return;
+    }
+
+  val = getreg32(CXD56_CRG_RESET);
+  putreg32(val & ~XRS_IMG, CXD56_CRG_RESET);
+  val = getreg32(CXD56_CRG_CK_GATE_AHB);
+  putreg32(val & ~CK_GATE_IMG, CXD56_CRG_CK_GATE_AHB);
+}
+
+static void cxd56_scu_clock_ctrl(uint32_t block, uint32_t intr, int on)
+{
+  uint32_t val, stat;
+  int retry = 10000;
+
+  putreg32(0xffffffff, CXD56_TOPREG_CRG_INT_CLR0);
+
+  val = getreg32(CXD56_TOPREG_SCU_CKEN);
+  if (on)
+    {
+      if ((val & block) == block)
+        {
+          /* Already clock on */
+
+          return;
+        }
+      putreg32(val | block, CXD56_TOPREG_SCU_CKEN);
+    }
+  else
+    {
+      if ((val & block) == 0)
+        {
+          /* Already clock off */
+
+          return;
+        }
+      putreg32(val & ~block, CXD56_TOPREG_SCU_CKEN);
+    }
+
+  do
+    {
+      stat = getreg32(CXD56_TOPREG_CRG_INT_STAT_RAW0);
+      busy_wait(1000);
+    }
+  while (retry-- && !(stat & intr));
+
+  putreg32(0xffffffff, CXD56_TOPREG_CRG_INT_CLR0);
+}
+
+static void cxd56_scu_clock_enable(void)
+{
+  uint32_t val, stat;
+  int retry = 1000;
+
+  val = getreg32(CXD56_TOPREG_SYSIOP_CKEN);
+  if (val & CKEN_BRG_SCU)
+    {
+      return;
+    }
+
+  /* SCU clock select default 0 (RCOSC) */
+
+#ifdef CONFIG_CXD56_SCU_32K
+  val = 2;
+#elif defined CONFIG_CXD56_SCU_XOSC
+  cxd56_xosc_enable();
+  val = 1 | ((CONFIG_CXD56_SCU_XOSC_DIV - 1) << 8);
+#else
+  cxd56_rcosc_enable();
+  val = 0;
+#endif
+#ifdef CONFIG_CXD56_SCU32K_RTC
+  val |= 1 << 4;
+#endif
+  putreg32(val, CXD56_TOPREG_CKSEL_SCU);
+
+  putreg32(0xffffffff, CXD56_TOPREG_CRG_INT_CLR0);
+
+  /* Enable SYSIOP and SCU bridge */
+
+  val = getreg32(CXD56_TOPREG_SYSIOP_CKEN);
+  putreg32(val | CKEN_BRG_SCU, CXD56_TOPREG_SYSIOP_CKEN);
+
+  /* Enable each blocks in SCU */
+
+  val = getreg32(CXD56_TOPREG_SCU_CKEN);
+  putreg32(val | SCU_SCU | SCU_SC | SCU_32K | SCU_SEQ, CXD56_TOPREG_SCU_CKEN);
+
+  do
+    {
+      stat = getreg32(CXD56_TOPREG_CRG_INT_STAT_RAW0);
+      busy_wait(1000);
+    }
+  while (retry-- &&
+         !(stat & (CRG_CK_SCU |
+                   CRG_CK_SCU_SC |
+                   CRG_CK_BRG_SCU |
+                   CRG_CK_32K |
+                   CRG_CK_SCU_SEQ)));
+
+  putreg32(0xffffffff, CXD56_TOPREG_CRG_INT_CLR0);
+}
+
+void cxd56_scu_clock_disable(void)
+{
+  uint32_t val, stat;
+  int retry = 1000;
+
+  val = getreg32(CXD56_TOPREG_SYSIOP_CKEN);
+  if (!(val & CKEN_BRG_SCU))
+    {
+      /* Already disabled */
+
+      return;
+    }
+
+  val = getreg32(CXD56_TOPREG_SWRESET_SCU);
+  putreg32(val & ~XRST_SCU_ISOP, CXD56_TOPREG_SWRESET_SCU);
+
+  up_udelay(1);
+
+  putreg32(0xffffffff, CXD56_TOPREG_CRG_INT_CLR0);
+
+  /* Enable SYSIOP and SCU bridge */
+
+  val = getreg32(CXD56_TOPREG_SYSIOP_CKEN);
+  putreg32(val & ~CKEN_BRG_SCU, CXD56_TOPREG_SYSIOP_CKEN);
+
+  /* Enable each blocks in SCU */
+
+  val = getreg32(CXD56_TOPREG_SCU_CKEN);
+  putreg32(val & ~(SCU_SCU | SCU_SC | SCU_32K | SCU_SEQ), CXD56_TOPREG_SCU_CKEN);
+
+  do
+    {
+      stat = getreg32(CXD56_TOPREG_CRG_INT_STAT_RAW0);
+      busy_wait(1000);
+    }
+  while (retry-- &&
+         !(stat & (CRG_CK_SCU |
+                   CRG_CK_SCU_SC |
+                   CRG_CK_BRG_SCU |
+                   CRG_CK_32K |
+                   CRG_CK_SCU_SEQ)));
+
+  putreg32(0xffffffff, CXD56_TOPREG_CRG_INT_CLR0);
+}
+
+bool cxd56_scuseq_clock_is_enabled(void)
+{
+  uint32_t rst;
+
+  /* If SCU reset is already released, it assumes that the SCU sequencer is
+   * already in running.
+   */
+
+  rst = getreg32(CXD56_TOPREG_SWRESET_SCU);
+  if (rst & XRST_SCU_ISOP)
+    {
+      return true;
+    }
+  else
+    {
+      return false;
+    }
+}
+
+int cxd56_scuseq_clock_enable(void)
+{
+  /* Enable SCU IRAM/DRAM & FIFO memory power.
+   * Actual power control will running at SCU power control.
+   */
+
+  putreg32(0x133f, CXD56_TOPREG_TOP_SCU_RAMMODE_SEL);
+
+  /* Up SCU power if needed */
+
+  enable_pwd(PDID_SCU);
+
+  cxd56_scu_clock_enable();
+
+  return OK;
+}
+
+void cxd56_scuseq_release_reset(void)
+{
+  uint32_t rst;
+
+  cxd56_scu_clock_ctrl(SCU_SEQ, CRG_CK_SCU_SEQ, 0);
+
+  rst = getreg32(CXD56_TOPREG_SWRESET_SCU);
+  putreg32(rst | XRST_SCU_ISOP, CXD56_TOPREG_SWRESET_SCU);
+
+  cxd56_scu_clock_ctrl(SCU_SEQ, CRG_CK_SCU_SEQ, 1);
+}
+
+void cxd56_scuseq_clock_disable(void)
+{
+  uint32_t rst;
+
+  cxd56_scu_clock_ctrl(SCU_SEQ, CRG_CK_SCU_SEQ, 0);
+
+  rst = getreg32(CXD56_TOPREG_SWRESET_SCU);
+  putreg32(rst & ~XRST_SCU_ISOP, CXD56_TOPREG_SWRESET_SCU);
+
+  /* Down SCU power if needed */
+
+  disable_pwd(PDID_SCU);
+}
+
+static void cxd56_scu_peri_clock_enable(FAR const struct scu_peripheral *p)
+{
+  uint32_t val, rst;
+  uint32_t cken = 1u << p->cken;
+  uint32_t crgintmask = 1u << p->crgintmask;
+  uint32_t swreset = 1u << p->swreset;
+
+  /* Up SCU power if needed */
+
+  enable_pwd(PDID_SCU);
+
+  cxd56_scu_clock_enable();
+
+  val = getreg32(CXD56_TOPREG_SCU_CKEN);
+  if (val & cken)
+    {
+      return;
+    }
+
+  cxd56_scu_clock_ctrl(cken, crgintmask, 1);
+  cxd56_scu_clock_ctrl(cken, crgintmask, 0);
+
+  rst = getreg32(CXD56_TOPREG_SWRESET_SCU);
+  putreg32(rst | swreset, CXD56_TOPREG_SWRESET_SCU);
+
+  cxd56_scu_clock_ctrl(cken, crgintmask, 1);
+}
+
+static void cxd56_scu_peri_clock_disable(FAR const struct scu_peripheral *p)
+{
+  uint32_t val, rst;
+  uint32_t cken = 1u << p->cken;
+  uint32_t crgintmask = 1u << p->crgintmask;
+  uint32_t swreset = 1u << p->swreset;
+
+  val = getreg32(CXD56_TOPREG_SCU_CKEN);
+  if (!(val & cken))
+    {
+      return;
+    }
+
+  cxd56_scu_clock_ctrl(cken, crgintmask, 0);
+
+  rst = getreg32(CXD56_TOPREG_SWRESET_SCU);
+  putreg32(rst & ~swreset, CXD56_TOPREG_SWRESET_SCU);
+
+  /* Down SCU power if needed */
+
+  disable_pwd(PDID_SCU);
+}
+
+static void cxd56_scu_peri_clock_gating(FAR const struct scu_peripheral *p, int enable)
+{
+  uint32_t cken = 1u << p->cken;
+
+  if (enable)
+    {
+      modifyreg32(CXD56_TOPREG_SCU_CKEN, cken, 0);  /* clock stop */
+    }
+  else
+    {
+      modifyreg32(CXD56_TOPREG_SCU_CKEN, 0, cken);  /* clock start */
+    }
+}
+
+void cxd56_udmac_clock_enable(void)
+{
+  uint32_t val;
+  val = getreg32(CXD56_TOPREG_SYSIOP_CKEN);
+  putreg32(val | CKEN_AHB_DMAC0, CXD56_TOPREG_SYSIOP_CKEN);
+}
+
+void cxd56_udmac_clock_disable(void)
+{
+  uint32_t val;
+  val = getreg32(CXD56_TOPREG_SYSIOP_CKEN);
+  putreg32(val & ~CKEN_AHB_DMAC0, CXD56_TOPREG_SYSIOP_CKEN);
+}
+
+void cxd56_lpadc_clock_enable(uint32_t div)
+{
+#if defined(CONFIG_CXD56_ADC)
+  uint32_t val;
+  uint32_t mask;
+
+  if (div > 4)
+    {
+      return;
+    }
+
+  enable_apwd(APDID_LPADC);
+
+  mask = 0x0000000f;
+  val = getreg32(CXD56_TOPREG_CKDIV_SCU) & ~mask;
+  val |= div;
+  putreg32(val, CXD56_TOPREG_CKDIV_SCU);
+
+  cxd56_scu_peri_clock_enable(&g_sculpadc);
+#endif
+}
+
+void cxd56_lpadc_clock_disable(void)
+{
+#if defined(CONFIG_CXD56_ADC)
+  cxd56_scu_peri_clock_disable(&g_sculpadc);
+
+  disable_apwd(APDID_LPADC);
+#endif
+}
+
+void cxd56_hpadc_clock_enable(uint32_t div)
+{
+#if defined(CONFIG_CXD56_ADC)
+  uint32_t val;
+  uint32_t mask;
+
+  if (div > 4)
+    {
+      return;
+    }
+
+  enable_apwd(APDID_HPADC);
+
+  mask = 0x000000f0;
+  val = getreg32(CXD56_TOPREG_CKDIV_SCU) & ~mask;
+  val |= (div << 4);
+  putreg32(val, CXD56_TOPREG_CKDIV_SCU);
+
+  mask = 0x00004000;
+  val = getreg32(CXD56_TOPREG_RCOSC_CTRL1) & ~mask;
+  putreg32(val, CXD56_TOPREG_RCOSC_CTRL1);
+
+  mask = 0x00020000;
+  val = getreg32(CXD56_TOPREG_XOSC_CTRL) & ~mask;
+  val |= mask;
+  putreg32(val, CXD56_TOPREG_XOSC_CTRL);
+
+  cxd56_scu_peri_clock_enable(&g_scuhpadc);
+#endif
+}
+
+void cxd56_hpadc_clock_disable(void)
+{
+#if defined(CONFIG_CXD56_ADC)
+  uint32_t val;
+  uint32_t mask;
+
+  mask = 0x00004000;
+  val = getreg32(CXD56_TOPREG_RCOSC_CTRL1) & ~mask;
+  val |= mask;
+  putreg32(val, CXD56_TOPREG_RCOSC_CTRL1);
+
+  mask = 0x00020000;
+  val = getreg32(CXD56_TOPREG_XOSC_CTRL) & ~mask;
+  putreg32(val, CXD56_TOPREG_XOSC_CTRL);
+
+  cxd56_scu_peri_clock_disable(&g_scuhpadc);
+
+  disable_apwd(APDID_HPADC);
+#endif
+}
+
+uint32_t cxd56_get_xosc_clock(void)
+{
+  return cxd56_get_clock(XOSC);
+}
+
+uint32_t cxd56_get_rcosc_clock(void)
+{
+  return cxd56_get_clock(RCOSC);
+}
+
+uint32_t cxd56_get_rtc_clock(void)
+{
+  return cxd56_get_clock(RTC);
+}
+
+uint32_t cxd56_get_syspll_clock(void)
+{
+  return cxd56_get_clock(SYSPLL);
+}
+
+uint32_t cxd56_get_sys_ahb_baseclock(void)
+{
+  uint32_t bus, ahb;
+
+  bus = getreg32(CXD56_TOPREG_CKDIV_CPU_DSP_BUS);
+  ahb = 1 << ((bus >> 16) & 0x7);
+  return cxd56_get_sys_baseclock() / ahb;
+}
+
+uint32_t cxd56_get_sys_apb_baseclock(void)
+{
+  uint32_t bus, apb;
+
+  bus = getreg32(CXD56_TOPREG_CKDIV_CPU_DSP_BUS);
+  apb = 1 << ((bus >> 24) & 0x3);
+  return cxd56_get_sys_ahb_baseclock() / apb;
+}
+
+uint32_t cxd56_get_sys_sfc_baseclock(void)
+{
+  uint32_t bus, sfchclk;
+
+  bus = getreg32(CXD56_TOPREG_CKDIV_CPU_DSP_BUS);
+  sfchclk = ((bus >> 28) & 0xf);
+  if (sfchclk <= 9)
+    {
+      return (cxd56_get_sys_baseclock() / ((sfchclk * 2) + 2));
+    }
+  else
+    {
+      return (cxd56_get_sys_baseclock() / ((1 << (sfchclk - 10)) * 32));
+    }
+}
+
+static uint32_t cxd56_get_suc32k_baseclock(void)
+{
+  uint32_t ckscu;
+
+  ckscu = getreg32(CXD56_TOPREG_CKSEL_SCU);
+
+  if (((ckscu >> 4) & 0x1) == 0)
+    {
+      return cxd56_get_clock(RCOSC) / 250;
+    }
+  else
+    {
+      return cxd56_get_clock(RTC);
+    }
+}
+
+uint32_t cxd56_get_hpadc_baseclock(void)
+{
+  uint32_t divscu;
+
+  divscu = getreg32(CXD56_TOPREG_CKDIV_SCU);
+  return cxd56_get_suc32k_baseclock() / (1 << ((divscu >> 4) & 0xf));
+}
+
+uint32_t cxd56_get_lpadc_baseclock(void)
+{
+  uint32_t divscu;
+
+  divscu = getreg32(CXD56_TOPREG_CKDIV_SCU);
+  return cxd56_get_suc32k_baseclock() / (1 << (divscu & 0xf));
+}
+
+uint32_t cxd56_get_pmui2c_baseclock(void)
+{
+  uint32_t ckpmu;
+
+  ckpmu = getreg32(CXD56_TOPREG_CKSEL_PMU);
+  switch (ckpmu & 0x3)
+    {
+      case 0:
+        return cxd56_get_sys_apb_baseclock();
+        break;
+      case 1:
+        return cxd56_get_clock(RTC);
+        break;
+      case 2:
+        return cxd56_get_clock(RCOSC);
+        break;
+      default:
+        return 0;
+        break;
+    }
+}
+
+uint32_t cxd56_get_gps_cpu_baseclock(void)
+{
+  uint32_t gnssdiv;
+
+  gnssdiv = getreg32(CXD56_TOPREG_GNSS_DIV);
+  return cxd56_get_sys_baseclock() / ((gnssdiv & 0x1f) + 1);
+}
+
+uint32_t cxd56_get_gps_ahb_baseclock(void)
+{
+  uint32_t gnssdiv;
+
+  gnssdiv = getreg32(CXD56_TOPREG_GNSS_DIV);
+  return cxd56_get_sys_baseclock() / (((gnssdiv >> 16) & 0x1f) + 1);
+}
+
+uint32_t cxd56_get_usb_baseclock(void)
+{
+  uint32_t val;
+  int n, m;
+
+  val = getreg32(CXD56_CRG_GEAR_PER_USB);
+  n = (val >> 16) & 1;
+  m = val & 0x3;
+
+  if (m != 0)
+    {
+      return cxd56_get_appsmp_baseclock() * n / m;
+    }
+  else
+    {
+      return 0;
+    }
+}
+
+uint32_t cxd56_get_img_vsync_baseclock(void)
+{
+  int n, m;
+
+  n = getreg32(CXD56_CRG_GEAR_N_IMG_VENB);
+  m = getreg32(CXD56_CRG_GEAR_M_IMG_VENB);
+
+  if (n != 0)
+    {
+      return cxd56_get_appsmp_baseclock() * n / m;
+    }
+  else
+    {
+      return 0;
+    }
+}
+
+int up_pmramctrl(int cmd, uintptr_t addr, size_t size)
+{
+  int startidx, endidx;
+  int i;
+  uint32_t mode, mask, ctrl, stat;
+  uint32_t val;
+  int changed = 0;
+
+  DEBUGASSERT(cmd == PMCMD_RAM_ON || cmd == PMCMD_RAM_OFF ||
+              cmd == PMCMD_RAM_RET);
+
+  /* Get tile index from address and size. */
+
+  startidx = TILEALIGNIDX(addr);
+  endidx = TILEALIGNIDX(TILEALIGN(addr + size));
+
+  DEBUGASSERT(startidx < 12 && endidx <= 12);
+  pmdbg("%x (size: %x) [%d:%d] -> %d\n", addr, size,
+        startidx, endidx, cmd);
+
+  /* Make controls bits for RAM power control */
+
+  mode = 0;
+  mask = 0;
+  ctrl = 0;
+  for (i = startidx; i < endidx; i++)
+    {
+      mode |= cmd << (i * 2);
+      mask |= 3 << (i * 2);
+      ctrl |= 1 << i;
+    }
+
+  /* Determine mode changes on lower half tiles. */
+
+  stat = getreg32(CXD56_TOPREG_APPDSP_RAMMODE_STAT0);
+  if ((stat & (mask & 0xfff)) != (mode & 0xfff))
+    {
+      val = (ctrl & 0x3f) << 24 | (mode & 0xfff);
+      putreg32(val, CXD56_TOPREG_APPDSP_RAMMODE_SEL0);
+      changed = 1;
+    }
+
+  /* Shift all bits for upper tiles. */
+
+  ctrl >>= 6;
+  mode >>= 12;
+  mask >>= 12;
+
+  /* Determine mode changes on upper half tiles. */
+
+  stat = getreg32(CXD56_TOPREG_APPDSP_RAMMODE_STAT1);
+  if ((stat & (mask & 0xfff)) != (mode & 0xfff))
+    {
+      val = (ctrl & 0x3f) << 24 | (mode & 0xfff);
+      putreg32(val, CXD56_TOPREG_APPDSP_RAMMODE_SEL1);
+      changed = 1;
+    }
+
+  /* Apply RAM tile power status changes */
+
+  if (changed)
+    {
+      do_power_control();
+
+      /* Clock gating for inactive tiles. */
+
+      stat  = getreg32(CXD56_TOPREG_APPDSP_RAMMODE_STAT1) << 12;
+      stat |= getreg32(CXD56_TOPREG_APPDSP_RAMMODE_STAT0);
+      val = 0;
+      for (i = 0, mask = 3; i < 12; i++, mask <<= 2)
+        {
+          if ((stat & mask) == 0)
+            {
+              val |= 1 << i;
+            }
+        }
+      putreg32(val, CXD56_CRG_APP_TILE_CLK_GATING_ENB);
+    }
+
+  return OK;
+}
+
+#ifdef CONFIG_DEBUG_PM
+/****************************************************************************
+ * Name: up_pmstatdump
+ *
+ * Description:
+ *   Print architecture specific power status
+ *
+ ****************************************************************************/
+
+void up_pmstatdump(void)
+{
+  uint32_t stat0, stat1;
+  const char statch[] = " -?+"; /* OFF, retention, invalid, ON */
+  const char gatech[] = "| ";   /* clock on, clock off */
+
+  stat0 = getreg32(CXD56_TOPREG_APPDSP_RAMMODE_STAT0);
+  stat1 = getreg32(CXD56_TOPREG_APPDSP_RAMMODE_STAT1);
+
+  pmdbg("              0 1 2 3 4 5 6 7 8 9 A B\n");
+  pmdbg("DSP RAM stat: %c %c %c %c %c %c %c %c %c %c %c %c\n",
+        statch[(stat0 >>  0) & 3],
+        statch[(stat0 >>  2) & 3],
+        statch[(stat0 >>  4) & 3],
+        statch[(stat0 >>  6) & 3],
+        statch[(stat0 >>  8) & 3],
+        statch[(stat0 >> 10) & 3],
+        statch[(stat1 >>  0) & 3],
+        statch[(stat1 >>  2) & 3],
+        statch[(stat1 >>  4) & 3],
+        statch[(stat1 >>  6) & 3],
+        statch[(stat1 >>  8) & 3],
+        statch[(stat1 >> 10) & 3]);
+
+  stat0 = getreg32(CXD56_CRG_APP_TILE_CLK_GATING_ENB);
+  pmdbg("Clock gating: %c %c %c %c %c %c %c %c %c %c %c %c\n",
+        gatech[(stat0 >>  0) & 1],
+        gatech[(stat0 >>  1) & 1],
+        gatech[(stat0 >>  2) & 1],
+        gatech[(stat0 >>  3) & 1],
+        gatech[(stat0 >>  4) & 1],
+        gatech[(stat0 >>  5) & 1],
+        gatech[(stat0 >>  6) & 1],
+        gatech[(stat0 >>  7) & 1],
+        gatech[(stat0 >>  8) & 1],
+        gatech[(stat0 >>  9) & 1],
+        gatech[(stat0 >> 10) & 1],
+        gatech[(stat0 >> 11) & 1]);
+}
+#endif
diff --git a/arch/arm/src/cxd56xx/cxd56_clock.h b/arch/arm/src/cxd56xx/cxd56_clock.h
new file mode 100644
index 00000000000..406e7c4a339
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_clock.h
@@ -0,0 +1,711 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_clock.h
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_CLOCK_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56_CLOCK_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include "hardware/cxd5602_topreg.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_spif_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_spif_clock_enable(void);
+
+/****************************************************************************
+ * Name: cxd56_spif_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_spif_clock_disable(void);
+
+/****************************************************************************
+ * Name: cxd56_get_cpu_baseclk
+ *
+ * Description:
+ *   Get CPU clock.
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_cpu_baseclk(void);
+
+/****************************************************************************
+ * Name: cxd56_cpu_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_cpu_clock_enable(int cpu);
+
+/****************************************************************************
+ * Name: cxd56_cpulist_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_cpulist_clock_enable(uint32_t cpus);
+
+/****************************************************************************
+ * Name: cxd56_cpu_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_cpu_clock_disable(int cpu);
+
+/****************************************************************************
+ * Name: cxd56_cpulist_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_cpulist_clock_disable(uint32_t cpus);
+
+/****************************************************************************
+ * Name: cxd56_cpu_reset
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_cpu_reset(int cpu);
+
+/****************************************************************************
+ * Name: cxd56_cpulist_reset
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_cpulist_reset(uint32_t cpus);
+
+/****************************************************************************
+ * Name: cxd56_usb_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_usb_clock_enable(void);
+
+/****************************************************************************
+ * Name: cxd56_usb_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_usb_clock_disable(void);
+
+/****************************************************************************
+ * Name: cxd56_emmc_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_emmc_clock_enable(uint32_t div, uint32_t driver, uint32_t sample);
+
+/****************************************************************************
+ * Name: cxd56_emmc_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_emmc_clock_disable(void);
+
+/****************************************************************************
+ * Name: cxd56_sdio_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_sdio_clock_enable(void);
+
+/****************************************************************************
+ * Name: cxd56_sdio_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_sdio_clock_disable(void);
+
+/****************************************************************************
+ * Name: cxd56_audio_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_audio_clock_enable(uint32_t clk, uint32_t div);
+
+/****************************************************************************
+ * Name: cxd56_audio_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_audio_clock_disable(void);
+
+/****************************************************************************
+ * Name: cxd56_audio_clock_is_enabled
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+bool cxd56_audio_clock_is_enabled(void);
+
+/****************************************************************************
+ * Name: cxd56_spi_clock_enable
+ *
+ * Description:
+ *   Enable SPI device clock.
+ *
+ ****************************************************************************/
+
+void cxd56_spi_clock_enable(int port);
+
+/****************************************************************************
+ * Name: cxd56_spi_clock_disable
+ *
+ * Description:
+ *   Disable SPI device clock.
+ *
+ ****************************************************************************/
+
+void cxd56_spi_clock_disable(int port);
+
+/****************************************************************************
+ * Name: cxd56_spi_clock_gate_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_spi_clock_gate_enable(int port);
+
+/****************************************************************************
+ * Name: cxd56_spi_clock_gate_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_spi_clock_gate_disable(int port);
+
+/****************************************************************************
+ * Name: cxd56_spi_clock_gear_adjust
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_spi_clock_gear_adjust(int port, uint32_t maxfreq);
+
+/****************************************************************************
+ * Name: cxd56_i2c0_clock_enable
+ *
+ * Description:
+ *   Enable I2C device clock.
+ *
+ ****************************************************************************/
+
+void cxd56_i2c_clock_enable(int port);
+
+/****************************************************************************
+ * Name: cxd56_i2c_clock_dsiable
+ *
+ * Description:
+ *   Disable I2C device clock.
+ *
+ ****************************************************************************/
+
+void cxd56_i2c_clock_disable(int port);
+
+/****************************************************************************
+ * Name: cxd56_i2c_clock_gate_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_i2c_clock_gate_enable(int port);
+
+/****************************************************************************
+ * Name: cxd56_i2c_clock_gate_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_i2c_clock_gate_disable(int port);
+
+/****************************************************************************
+ * Name: cxd56_scuseq_is_clock_enabled
+ *
+ * Description:
+ *   Get whether Sensor Control Unit Sequencer clock is enabled or not
+ *
+ ****************************************************************************/
+
+bool cxd56_scuseq_clock_is_enabled(void);
+
+/****************************************************************************
+ * Name: cxd56_scuseq_clock_enable
+ *
+ * Description:
+ *   Enable Sensor Control Unit Sequencer clock.
+ *
+ ****************************************************************************/
+
+int cxd56_scuseq_clock_enable(void);
+
+/****************************************************************************
+ * Name: cxd56_scuseq_release_reset
+ *
+ * Description:
+ *   Release sequencer reset. This function must be call after
+ *   cxd56_scuseq_clock_enable() and copy sequencer firmware.
+ *
+ ****************************************************************************/
+
+void cxd56_scuseq_release_reset(void);
+
+/****************************************************************************
+ * Name: cxd56_scuseq_clock_dsiable
+ *
+ * Description:
+ *   Disable Sensor Control Unit Sequencer clock.
+ *
+ ****************************************************************************/
+
+void cxd56_scuseq_clock_disable(void);
+
+/****************************************************************************
+ * Name: cxd56_img_uart_clock_enable
+ *
+ * Description:
+ *   Enable img uart clock.
+ *
+ ****************************************************************************/
+
+void cxd56_img_uart_clock_enable(void);
+
+/****************************************************************************
+ * Name: cxd56_img_uart_clock_dsiable
+ *
+ * Description:
+ *   Disable img uart clock.
+ *
+ ****************************************************************************/
+
+void cxd56_img_uart_clock_disable(void);
+
+/****************************************************************************
+ * Name: cxd56_get_img_uart_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_img_uart_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_img_cisif_clock_enable
+ *
+ * Description:
+ *   Enable cisif clock.
+ *
+ ****************************************************************************/
+
+void cxd56_img_cisif_clock_enable(void);
+
+/****************************************************************************
+ * Name: cxd56_img_cisif_clock_dsiable
+ *
+ * Description:
+ *   Disable cisif clock.
+ *
+ ****************************************************************************/
+
+void cxd56_img_cisif_clock_disable(void);
+
+/****************************************************************************
+ * Name: cxd56_img_ge2d_clock_enable
+ *
+ * Description:
+ *   Enable ge2d clock.
+ *
+ ****************************************************************************/
+
+void cxd56_img_ge2d_clock_enable(void);
+
+/****************************************************************************
+ * Name: cxd56_img_ge2d_clock_dsiable
+ *
+ * Description:
+ *   Disable ge2d clock.
+ *
+ ****************************************************************************/
+
+void cxd56_img_ge2d_clock_disable(void);
+
+/****************************************************************************
+ * Name: cxd56_get_com_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_com_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_sdio_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_sdio_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_spi_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_spi_baseclock(int port);
+
+/****************************************************************************
+ * Name: cxd56_get_i2c_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_i2c_baseclock(int port);
+
+/****************************************************************************
+ * Name: cxd56_get_pwm_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_pwm_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_udmac_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_udmac_clock_enable(void);
+
+/****************************************************************************
+ * Name: cxd56_udmac_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_udmac_clock_disable(void);
+
+/****************************************************************************
+ * Name: cxd56_lpadc_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_lpadc_clock_enable(uint32_t div);
+
+/****************************************************************************
+ * Name: cxd56_lpadc_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_lpadc_clock_disable(void);
+
+/****************************************************************************
+ * Name: cxd56_hpadc_clock_enable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_hpadc_clock_enable(uint32_t div);
+
+/****************************************************************************
+ * Name: cxd56_hpadc_clock_disable
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_hpadc_clock_disable(void);
+
+/****************************************************************************
+ * Name: cxd56_get_xosc_clock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_xosc_clock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_rcosc_clock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_rcosc_clock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_rtc_clock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_rtc_clock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_syspll_clock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_syspll_clock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_sys_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_sys_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_sys_ahb_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_sys_ahb_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_sys_apb_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_sys_apb_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_sys_sfc_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_sys_sfc_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_scu_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_scu_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_hpadc_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_hpadc_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_lpadc_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_lpadc_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_pmui2c_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_pmui2c_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_gps_cpu_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_gps_cpu_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_gps_ahb_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_gps_ahb_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_img_spi_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_img_spi_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_img_wspi_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_img_wspi_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_usb_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_usb_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_img_vsync_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_img_vsync_baseclock(void);
+
+/****************************************************************************
+ * Name: cxd56_get_appsmp_baseclock
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+uint32_t cxd56_get_appsmp_baseclock(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_CLOCK_H */
diff --git a/arch/arm/src/cxd56xx/cxd56_config.h b/arch/arm/src/cxd56xx/cxd56_config.h
new file mode 100644
index 00000000000..1a47f401cbb
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_config.h
@@ -0,0 +1,138 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_config.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56XX_CONFIG_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56XX_CONFIG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Required configuration settings */
+
+/* Are any UARTs enabled? */
+
+#undef HAVE_UART
+#if defined(CONFIG_CXD56_UART0) || defined(CONFIG_CXD56_UART1) || \
+    defined(CONFIG_CXD56_UART2)
+#  define HAVE_UART 1
+#endif
+
+/* Make sure all features are disabled for diabled U[S]ARTs.  This simplifies
+ * checking later.
+ */
+
+#ifndef CONFIG_CXD56_UART0
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART0_RS485MODE
+#  undef CONFIG_UART0_RS485_DTRDIR
+#endif
+
+#ifndef CONFIG_CXD56_UART1
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART1_RS485MODE
+#  undef CONFIG_UART1_RS485_DTRDIR
+#endif
+
+#ifndef CONFIG_CXD56_UART2
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  undef CONFIG_UART2_RS485MODE
+#  undef CONFIG_UART2_RS485_DTRDIR
+#endif
+
+/* Is there a serial console? There should be at most one defined.  It could
+ * be on any UARTn, n=0,1,2,3 - OR - there might not be any serial console at
+ * all.
+ */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  undef CONFIG_UART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  undef CONFIG_UART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART3_SERIAL_CONSOLE
+#  define HAVE_CONSOLE 1
+#else
+#  undef CONFIG_UART0_SERIAL_CONSOLE
+#  undef CONFIG_UART1_SERIAL_CONSOLE
+#  undef CONFIG_UART2_SERIAL_CONSOLE
+#  undef CONFIG_UART3_SERIAL_CONSOLE
+#  undef HAVE_CONSOLE
+#endif
+
+/* Check UART flow control (Only supported by UART1) */
+
+# undef CONFIG_UART0_FLOWCONTROL
+# undef CONFIG_UART2_FLOWCONTROL
+# undef CONFIG_UART3_FLOWCONTROL
+#ifndef CONFIG_CXD56_UART1
+# undef CONFIG_UART1_FLOWCONTROL
+#endif
+
+/* Get Firmware version */
+
+#define GET_SBL_VERSION()           (BKUP->sbl_version)
+#define GET_SYSFW_VERSION()         (BKUP->sysfw_version)
+#define GET_SYSFW_VERSION_MAJOR()   ((GET_SYSFW_VERSION() >> 28) & 0xf)
+#define GET_SYSFW_VERSION_MINOR()   ((GET_SYSFW_VERSION() >> 20) & 0xff)
+#define GET_SYSFW_VERSION_BUILD()   (GET_SYSFW_VERSION() & 0xfffff)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56XX_CONFIG_H */
diff --git a/arch/arm/src/cxd56xx/cxd56_cpufifo.c b/arch/arm/src/cxd56xx/cxd56_cpufifo.c
new file mode 100644
index 00000000000..b5ec0957e34
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_cpufifo.c
@@ -0,0 +1,262 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_cpufifo.c
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "up_arch.h"
+
+#include "chip.h"
+#include "hardware/cxd56_cpufifo.h"
+#include "cxd56_cpufifo.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+#ifdef CONFIG_CXD56_CPUFIFO_ENTRIES
+#define NR_PUSHBUFENTRIES   CONFIG_CXD56_CPUFIFO_ENTRIES
+#else
+#define NR_PUSHBUFENTRIES   8
+#endif
+
+#define MSGFROM(x)       (((x)[0] >> 28) & 0xf)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct cfpushdata_s
+{
+  FAR sq_entry_t entry;
+  uint32_t data[2];
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int  cpufifo_txhandler(int irq, FAR void *context, FAR void *arg);
+static int  cpufifo_rxhandler(int irq, FAR void *context, FAR void *arg);
+static int  cpufifo_trypush(uint32_t data[2]);
+static void cpufifo_reserve(uint32_t data[2]);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+/* Only for SYS, GNSS CPUs */
+
+static sq_queue_t          g_pushqueue;
+static sq_queue_t          g_emptyqueue;
+static struct cfpushdata_s g_pushbuffer[NR_PUSHBUFENTRIES];
+static cpufifo_handler_t   g_cfrxhandler;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static int cpufifo_txhandler(int irq, FAR void *context, FAR void *arg)
+{
+  FAR struct cfpushdata_s *pd;
+
+  pd = (FAR struct cfpushdata_s *)sq_remfirst(&g_pushqueue);
+  if (pd)
+    {
+      /* Ignore error because always FIFO is not full at here */
+
+      cpufifo_trypush(pd->data);
+      sq_addlast(&pd->entry, &g_emptyqueue);
+    }
+  if (sq_empty(&g_pushqueue))
+    {
+      up_disable_irq(CXD56_IRQ_FIFO_TO);
+    }
+
+  return OK;
+}
+
+static int cpufifo_rxhandler(int irq, FAR void *context, FAR void *arg)
+{
+  uint32_t word[2] = {0};
+  int cpuid;
+
+  /* Drain from PULL FIFO. But not all data because this handler
+   * will be re-entered when data remaining in PULL FIFO.
+   */
+
+  cxd56_cfpull(word);
+  cpuid = MSGFROM(word);
+
+  DEBUGASSERT(cpuid >= 0 && cpuid < 8);
+
+  if (g_cfrxhandler)
+    {
+      g_cfrxhandler(cpuid, word);
+    }
+
+  return OK;
+}
+
+static int cpufifo_trypush(uint32_t data[2])
+{
+  if (getreg32(CXD56_FIF_PUSH_FULL))
+    {
+      return -1;
+    }
+
+  putreg32(data[0], CXD56_FIF_PUSH_WRD0);
+  putreg32(data[1], CXD56_FIF_PUSH_WRD1);
+  putreg32(1, CXD56_FIF_PUSH_CMP);
+
+  return OK;
+}
+
+static void cpufifo_reserve(uint32_t data[2])
+{
+  FAR struct cfpushdata_s *pd;
+
+  pd = (FAR struct cfpushdata_s *)sq_remfirst(&g_emptyqueue);
+
+  /* This assertion indicate that need more sending buffer, it can be
+   * configured by CONFIG_CXD56_CPUFIFO_ENTRIES.
+   */
+
+  ASSERT(pd);
+
+  pd->data[0] = data[0];
+  pd->data[1] = data[1];
+  sq_addlast(&pd->entry, &g_pushqueue);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+int cxd56_cfpush(uint32_t data[2])
+{
+  irqstate_t flags;
+  int        ret;
+
+  flags = enter_critical_section();
+  if (!sq_empty(&g_pushqueue))
+    {
+      cpufifo_reserve(data);
+      return OK;
+    }
+
+  ret = cpufifo_trypush(data);
+  if (ret < 0)
+    {
+      cpufifo_reserve(data);
+      up_enable_irq(CXD56_IRQ_FIFO_TO);
+    }
+
+  leave_critical_section(flags);
+
+  return OK;
+}
+
+int cxd56_cfpull(uint32_t data[2])
+{
+  if (getreg32(CXD56_FIF_PULL_EMP))
+    {
+      return -1;
+    }
+
+  data[0] = getreg32(CXD56_FIF_PULL_WRD0);
+  data[1] = getreg32(CXD56_FIF_PULL_WRD1);
+  putreg32(1, CXD56_FIF_PULL_CMP);
+
+  return 0;
+}
+
+int cxd56_cfregrxhandler(cpufifo_handler_t handler)
+{
+  irqstate_t flags;
+  int ret = OK;
+
+  flags = enter_critical_section();
+  if (g_cfrxhandler)
+    {
+      ret = -1;
+    }
+  else
+    {
+      g_cfrxhandler = handler;
+    }
+  leave_critical_section(flags);
+  return ret;
+}
+
+void cxd56_cfunregrxhandler(void)
+{
+  irqstate_t flags;
+  flags = enter_critical_section();
+  g_cfrxhandler = NULL;
+  leave_critical_section(flags);
+}
+
+int cxd56_cfinitialize(void)
+{
+  int i;
+
+  /* Setup IRQ handlers. Enable only FROM (RX) interrupt because TO (TX)
+   * interrupt for retry sending when FIFO is full.
+   */
+
+  irq_attach(CXD56_IRQ_FIFO_FROM, cpufifo_rxhandler, NULL);
+  irq_attach(CXD56_IRQ_FIFO_TO, cpufifo_txhandler, NULL);
+  up_enable_irq(CXD56_IRQ_FIFO_FROM);
+
+  /* Initialize push buffer. */
+
+  sq_init(&g_pushqueue);
+  sq_init(&g_emptyqueue);
+
+  for (i = 0; i < NR_PUSHBUFENTRIES; i++)
+    {
+      sq_addlast((FAR sq_entry_t *)&g_pushbuffer[i], &g_emptyqueue);
+    }
+
+  /* Clear user defined receive handler. */
+
+  g_cfrxhandler = NULL;
+
+  return OK;
+}
diff --git a/arch/arm/src/cxd56xx/cxd56_cpufifo.h b/arch/arm/src/cxd56xx/cxd56_cpufifo.h
new file mode 100644
index 00000000000..af96fd28ecf
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_cpufifo.h
@@ -0,0 +1,62 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_cpufifo.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_CPUFIFO_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56_CPUFIFO_H
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+typedef int (*cpufifo_handler_t)(int cpuid, uint32_t data[2]);
+
+int  cxd56_cfinitialize(void);
+int  cxd56_cfpush(uint32_t data[2]);
+int  cxd56_cfpull(uint32_t data[2]);
+int  cxd56_cfregrxhandler(cpufifo_handler_t handler);
+void cxd56_cfunregrxhandler(void);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_CPUFIFO_H */
diff --git a/arch/arm/src/cxd56xx/cxd56_gpio.c b/arch/arm/src/cxd56xx/cxd56_gpio.c
new file mode 100644
index 00000000000..e4357774ab5
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_gpio.c
@@ -0,0 +1,299 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_gpio.c
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "chip.h"
+#include "up_arch.h"
+
+#include "cxd56_pinconfig.h"
+#include "cxd56_gpio.h"
+#include "hardware/cxd5602_topreg.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* GPIO register Definitions */
+
+#define GPIO_OUTPUT_EN_SHIFT    (16)
+#define GPIO_OUTPUT_EN_MASK     (1u << GPIO_OUTPUT_EN_SHIFT)
+#define GPIO_OUTPUT_ENABLE      (0u << GPIO_OUTPUT_EN_SHIFT)
+#define GPIO_OUTPUT_DISABLE     (1u << GPIO_OUTPUT_EN_SHIFT)
+#define GPIO_OUTPUT_ENABLED(v)  (((v) & GPIO_OUTPUT_EN_MASK) == GPIO_OUTPUT_ENABLE)
+#define GPIO_OUTPUT_SHIFT       (8)
+#define GPIO_OUTPUT_MASK        (1u << GPIO_OUTPUT_SHIFT)
+#define GPIO_OUTPUT_HIGH        (1u << GPIO_OUTPUT_SHIFT)
+#define GPIO_OUTPUT_LOW         (0u << GPIO_OUTPUT_SHIFT)
+#define GPIO_INPUT_SHIFT        (0)
+#define GPIO_INPUT_MASK         (1u << GPIO_INPUT_SHIFT)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static uint32_t get_gpio_regaddr(uint32_t pin)
+{
+  uint32_t base;
+
+  base = (pin < PIN_IS_CLK) ? 1 : 7;
+
+  return CXD56_TOPREG_GP_I2C4_BCK + ((pin - base) * 4);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_gpio_config
+ *
+ * Description:
+ *   Configure a GPIO which input is enabled or not.
+ *   Output is enabled when cxd56_gpio_write() is called.
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int cxd56_gpio_config(uint32_t pin, bool input_enable)
+{
+  int ret = 0;
+  uint32_t pinconf;
+  uint32_t regaddr;
+  uint32_t ioreg;
+  uint32_t ioval;
+
+  DEBUGASSERT((PIN_I2C4_BCK <= pin) && (pin <= PIN_USB_VBUSINT));
+  DEBUGASSERT((pin <= PIN_GNSS_1PPS_OUT) || (PIN_SPI0_CS_X <= pin));
+  DEBUGASSERT((pin <= PIN_HIF_GPIO0) || (PIN_SEN_IRQ_IN <= pin));
+  DEBUGASSERT((pin <= PIN_PWM3) || (PIN_IS_CLK <= pin));
+
+  ioreg = CXD56_TOPREG_IO_RTC_CLK_IN + (pin * 4);
+  ioval = getreg32(ioreg);
+
+  if (input_enable)
+    {
+      pinconf = PINCONF_SET(pin, PINCONF_MODE0, PINCONF_INPUT_ENABLE,
+                            ioval & PINCONF_DRIVE_MASK,
+                            ioval & PINCONF_PULL_MASK);
+    }
+  else
+    {
+      pinconf = PINCONF_SET(pin, PINCONF_MODE0, PINCONF_INPUT_DISABLE,
+                            ioval & PINCONF_DRIVE_MASK,
+                            ioval & PINCONF_PULL_MASK);
+    }
+
+  ret = cxd56_pin_config(pinconf);
+
+  /* output disabled */
+
+  regaddr = get_gpio_regaddr(pin);
+  putreg32(GPIO_OUTPUT_DISABLE, regaddr);
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_gpio_write
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void cxd56_gpio_write(uint32_t pin, bool value)
+{
+  uint32_t regaddr;
+  uint32_t regval;
+
+  DEBUGASSERT((PIN_I2C4_BCK <= pin) && (pin <= PIN_USB_VBUSINT));
+  DEBUGASSERT((pin <= PIN_GNSS_1PPS_OUT) || (PIN_SPI0_CS_X <= pin));
+  DEBUGASSERT((pin <= PIN_HIF_GPIO0) || (PIN_SEN_IRQ_IN <= pin));
+  DEBUGASSERT((pin <= PIN_PWM3) || (PIN_IS_CLK <= pin));
+
+  regaddr = get_gpio_regaddr(pin);
+
+  if (value)
+    {
+      regval = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_HIGH;
+    }
+  else
+    {
+      regval = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_LOW;
+    }
+
+  putreg32(regval, regaddr);
+}
+
+/****************************************************************************
+ * Name: cxd56_gpio_write_hiz
+ *
+ * Description:
+ *   Write HiZ to the selected opendrain GPIO pin
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void cxd56_gpio_write_hiz(uint32_t pin)
+{
+  uint32_t regaddr;
+  uint32_t regval;
+
+  DEBUGASSERT((PIN_I2C4_BCK <= pin) && (pin <= PIN_USB_VBUSINT));
+  DEBUGASSERT((pin <= PIN_GNSS_1PPS_OUT) || (PIN_SPI0_CS_X <= pin));
+  DEBUGASSERT((pin <= PIN_HIF_GPIO0) || (PIN_SEN_IRQ_IN <= pin));
+  DEBUGASSERT((pin <= PIN_PWM3) || (PIN_IS_CLK <= pin));
+
+  regaddr = get_gpio_regaddr(pin);
+
+  regval = GPIO_OUTPUT_DISABLE;
+
+  putreg32(regval, regaddr);
+}
+
+/****************************************************************************
+ * Name: cxd56_gpio_read
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ * Returned Value:
+ *   The boolean state of the input pin
+ *
+ ****************************************************************************/
+
+bool cxd56_gpio_read(uint32_t pin)
+{
+  uint32_t regaddr;
+  uint32_t regval;
+  uint32_t shift;
+  uint32_t ioreg;
+  uint32_t ioval;
+
+  DEBUGASSERT((PIN_I2C4_BCK <= pin) && (pin <= PIN_USB_VBUSINT));
+  DEBUGASSERT((pin <= PIN_GNSS_1PPS_OUT) || (PIN_SPI0_CS_X <= pin));
+  DEBUGASSERT((pin <= PIN_HIF_GPIO0) || (PIN_SEN_IRQ_IN <= pin));
+  DEBUGASSERT((pin <= PIN_PWM3) || (PIN_IS_CLK <= pin));
+
+  regaddr = get_gpio_regaddr(pin);
+  regval = getreg32(regaddr);
+
+  ioreg = CXD56_TOPREG_IO_RTC_CLK_IN + (pin * 4);
+  ioval = getreg32(ioreg);
+
+  if (PINCONF_INPUT_ENABLED(ioval))
+    {
+      shift = GPIO_INPUT_SHIFT;
+    }
+  else if (GPIO_OUTPUT_ENABLED(regval))
+    {
+      shift = GPIO_OUTPUT_SHIFT;
+    }
+  else
+    {
+      shift = GPIO_INPUT_SHIFT;
+    }
+
+  return ((regval & (1 << shift)) != 0);
+}
+
+/********************************************************************************************
+ * Name: cxd56_gpio_status
+ *
+ * Description:
+ *   Get a gpio status which input/output is enabled or not.
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ********************************************************************************************/
+
+int cxd56_gpio_status(uint32_t pin, cxd56_gpio_status_t *stat)
+{
+  uint32_t regaddr;
+  uint32_t regval;
+  uint32_t ioreg;
+  uint32_t ioval;
+
+  if ((pin < PIN_I2C4_BCK) ||
+      ((PIN_GNSS_1PPS_OUT < pin) && (pin < PIN_SPI0_CS_X)) ||
+      ((PIN_HIF_GPIO0 < pin) && (pin < PIN_SEN_IRQ_IN)) ||
+      ((PIN_PWM3 < pin) && (pin < PIN_IS_CLK)) ||
+      (PIN_USB_VBUSINT < pin))
+    {
+      return -EINVAL;
+    }
+
+  ioreg = CXD56_TOPREG_IO_RTC_CLK_IN + (pin * 4);
+  ioval = getreg32(ioreg);
+
+  regaddr = get_gpio_regaddr(pin);
+  regval = getreg32(regaddr);
+
+  stat->input_en  = PINCONF_INPUT_ENABLED(ioval);
+  stat->output_en = GPIO_OUTPUT_ENABLED(regval);
+
+  return 0;
+}
diff --git a/arch/arm/src/cxd56xx/cxd56_gpio.h b/arch/arm/src/cxd56xx/cxd56_gpio.h
new file mode 100644
index 00000000000..a94df810e18
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_gpio.h
@@ -0,0 +1,158 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_gpio.h
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_GPIO_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56_GPIO_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include 
+
+#include 
+#include 
+
+#include "cxd56_pinconfig.h"
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+struct cxd56_gpio_status_s
+{
+  bool input_en;
+  bool output_en;
+};
+
+typedef struct cxd56_gpio_status_s cxd56_gpio_status_t;
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Name: cxd56_gpio_config
+ *
+ * Description:
+ *   Configure a GPIO which input is enabled or not.
+ *   Output is enabled when cxd56_gpio_write() is called.
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ********************************************************************************************/
+
+int cxd56_gpio_config(uint32_t pin, bool input_enable);
+
+/********************************************************************************************
+ * Name: cxd56_gpio_write
+ *
+ * Description:
+ *   Write one or zero to the selected GPIO pin
+ *
+ * Returned Value:
+ *   None
+ *
+ ********************************************************************************************/
+
+void cxd56_gpio_write(uint32_t pin, bool value);
+
+/********************************************************************************************
+ * Name: cxd56_gpio_write_hiz
+ *
+ * Description:
+ *   Output HiZ to the selected opendrain GPIO pin
+ *
+ * Returned Value:
+ *   None
+ *
+ ********************************************************************************************/
+
+void cxd56_gpio_write_hiz(uint32_t pin);
+
+/********************************************************************************************
+ * Name: cxd56_gpio_read
+ *
+ * Description:
+ *   Read one or zero from the selected GPIO pin
+ *
+ * Returned Value:
+ *   The boolean state of the input pin
+ *
+ ********************************************************************************************/
+
+bool cxd56_gpio_read(uint32_t pin);
+
+/********************************************************************************************
+ * Name: cxd56_gpio_status
+ *
+ * Description:
+ *   Get a gpio status which input/output is enabled or not.
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ********************************************************************************************/
+
+int cxd56_gpio_status(uint32_t pin, cxd56_gpio_status_t *stat);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_GPIO_H */
diff --git a/arch/arm/src/cxd56xx/cxd56_gpioint.c b/arch/arm/src/cxd56xx/cxd56_gpioint.c
new file mode 100644
index 00000000000..fed9d517868
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_gpioint.c
@@ -0,0 +1,657 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_gpioint.c
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include 
+
+#include 
+
+#include 
+#include 
+
+#include "up_arch.h"
+#include "chip.h"
+
+#include "cxd56_pinconfig.h"
+#include "cxd56_gpio.h"
+#include "cxd56_gpioint.h"
+#include "hardware/cxd5602_topreg.h"
+
+#ifdef CONFIG_CXD56_GPIO_IRQ
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* GPIO Interrupt Polarity Definitions */
+
+#define GPIOINT_POLARITY_SHIFT      (0)
+#define GPIOINT_POLARITY_MASK       (7)
+#define GPIOINT_GET_POLARITY(v)     (((v) & GPIOINT_POLARITY_MASK) >> GPIOINT_POLARITY_SHIFT)
+#define GPIOINT_SET_POLARITY(v)     (((v) << GPIOINT_POLARITY_SHIFT) & GPIOINT_POLARITY_MASK)
+#define GPIOINT_IS_LEVEL(v)         (GPIOINT_GET_POLARITY(v) <= GPIOINT_LEVEL_LOW)
+#define GPIOINT_IS_EDGE(v)          (GPIOINT_EDGE_RISE <= GPIOINT_GET_POLARITY(v))
+#define GPIOINT_IS_HIGH(v)          ((GPIOINT_LEVEL_HIGH == GPIOINT_GET_POLARITY(v)) || \
+                                     (GPIOINT_EDGE_RISE == GPIOINT_GET_POLARITY(v)))
+#define GPIOINT_IS_LOW(v)           ((GPIOINT_LEVEL_LOW == GPIOINT_GET_POLARITY(v)) || \
+                                     (GPIOINT_EDGE_FALL == GPIOINT_GET_POLARITY(v)))
+
+/* GPIO Interrupt Noise Filter Definitions */
+
+#define GPIOINT_NOISE_FILTER_SHIFT      (3)
+#define GPIOINT_NOISE_FILTER_MASK       (1u << GPIOINT_NOISE_FILTER_SHIFT)
+#define GPIOINT_NOISE_FILTER_ENABLED(v) (((v) & GPIOINT_NOISE_FILTER_MASK) \
+                                         == GPIOINT_NOISE_FILTER_ENABLE)
+
+/* Use Pseudo Edge Interrupt */
+
+#define GPIOINT_TOGGLE_MODE_SHIFT       (16)
+
+/* GPIO Interrupt Index Number Definitions */
+
+#define MAX_SLOT                (12)
+#define MAX_SYS_SLOT            (6)
+#define INTSEL_DEFAULT_VAL      (63)
+
+#define GET_SLOT2IRQ(slot)      (CXD56_IRQ_EXDEVICE_0 + (slot))
+#define GET_IRQ2SLOT(irq)       ((irq) - CXD56_IRQ_EXDEVICE_0)
+
+/* PMU_WAKE_TRIG_CPUINTSELx */
+
+#define INT_ROUTE_THROUGH       (0)
+#define INT_ROUTE_INVERTER      (1)
+#define INT_ROUTE_PMU           (2)
+#define INT_ROUTE_PMU_LATCH     (3)
+
+#define CXD56_INTC_ENABLE       (CXD56_INTC_BASE + 0x10)
+#define CXD56_INTC_INVERT       (CXD56_INTC_BASE + 0x20)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static xcpt_t g_isr[MAX_SLOT];
+static uint32_t g_bothedge = 0;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/* allocate/deallocate/get slot number (SYS: 0~5, APP: 6~11) */
+
+static int alloc_slot(int pin, bool isalloc)
+{
+  irqstate_t flags;
+  int alloc = -1;
+  int slot;
+  uint8_t val;
+  uint32_t base = (pin < PIN_IS_CLK) ? CXD56_TOPREG_IOCSYS_INTSEL0
+                                     : CXD56_TOPREG_IOCAPP_INTSEL0;
+  int offset = (pin < PIN_IS_CLK) ? 1 : 56;
+
+  flags = enter_critical_section();
+
+  for (slot = 0; slot < MAX_SYS_SLOT; slot++)
+    {
+      val = getreg8(base + slot);
+      if ((pin - offset) == val)
+        {
+          if (isalloc == false)
+            {
+              putreg8(INTSEL_DEFAULT_VAL, base + slot);
+            }
+          break; /* already used */
+        }
+      if ((-1 == alloc) && (INTSEL_DEFAULT_VAL == val))
+        {
+          alloc = slot;
+        }
+    }
+
+  if (slot == MAX_SYS_SLOT)
+    {
+      if (isalloc && (-1 != alloc))
+        {
+          slot = alloc;
+          putreg8(pin - offset, base + slot);
+        }
+      else
+        {
+          leave_critical_section(flags);
+          return -ENXIO; /* no space */
+        }
+    }
+
+  leave_critical_section(flags);
+
+  if (PIN_IS_CLK <= pin)
+    {
+      slot += MAX_SYS_SLOT;
+    }
+
+  return slot;
+}
+
+/* convert from slot to pin */
+
+static int get_slot2pin(int slot)
+{
+  uint32_t base = (slot < MAX_SYS_SLOT) ? CXD56_TOPREG_IOCSYS_INTSEL0
+                                        : CXD56_TOPREG_IOCAPP_INTSEL0;
+  int offset = 1;
+
+  if (MAX_SYS_SLOT <= slot)
+    {
+      slot -= MAX_SYS_SLOT;
+      offset = 56;
+    }
+
+  return (int)getreg8(base + slot) + offset;
+}
+
+/* convert from pin to slot number (SYS: 0~5, APP: 6~11) */
+
+static int get_pin2slot(int pin)
+{
+  int slot;
+  uint32_t base = (pin < PIN_IS_CLK) ? CXD56_TOPREG_IOCSYS_INTSEL0
+                                     : CXD56_TOPREG_IOCAPP_INTSEL0;
+  int offset = (pin < PIN_IS_CLK) ? 1 : 56;
+
+  for (slot = 0; slot < MAX_SYS_SLOT; slot++)
+    {
+      if ((pin - offset) == getreg8(base + slot)) /* byte access */
+        {
+          break;
+        }
+    }
+
+  if (slot == MAX_SYS_SLOT)
+    {
+      return -1;
+    }
+
+  if (PIN_IS_CLK <= pin)
+    {
+      slot += MAX_SYS_SLOT;
+    }
+
+  return slot;
+}
+
+/* convert from pin to irq number */
+
+static int get_pin2irq(int pin)
+{
+  int slot = get_pin2slot(pin);
+
+  if ((0 <= slot) && (slot < MAX_SLOT))
+    {
+      return GET_SLOT2IRQ(slot);
+    }
+  else
+    {
+      return -1;
+    }
+}
+
+/* set GPIO interrupt configuration registers */
+
+static int set_gpioint_config(int slot, uint32_t gpiocfg)
+{
+  uint32_t val;
+  uint32_t shift;
+  uint32_t polreg = CXD56_TOPREG_PMU_WAKE_TRIG_INTDET0;
+  uint32_t selreg = CXD56_TOPREG_PMU_WAKE_TRIG_CPUINTSEL0;
+
+  /* Configure the noise filter */
+
+  val = getreg32(CXD56_TOPREG_PMU_WAKE_TRIG_NOISECUTEN0);
+  if (GPIOINT_NOISE_FILTER_ENABLED(gpiocfg))
+    {
+      val |= (1 << (slot + 16));
+    }
+  else
+    {
+      val &= ~(1 << (slot + 16));
+    }
+  putreg32(val, CXD56_TOPREG_PMU_WAKE_TRIG_NOISECUTEN0);
+
+  /* Configure the polarity */
+
+  shift = 16 + (slot * 4);
+  if (32 <= shift)
+    {
+      polreg = CXD56_TOPREG_PMU_WAKE_TRIG_INTDET1;
+      selreg = CXD56_TOPREG_PMU_WAKE_TRIG_CPUINTSEL1;
+      shift -= 32;
+    }
+
+  val = getreg32(polreg);
+  val &= ~(0x7 << shift);
+  val |= (GPIOINT_GET_POLARITY(gpiocfg) << shift);
+  putreg32(val, polreg);
+
+  /* Configure the interrupt route */
+
+  val = getreg32(selreg);
+  val &= ~(0x7 << shift);
+
+  switch (GPIOINT_GET_POLARITY(gpiocfg))
+    {
+    case GPIOINT_LEVEL_HIGH:
+      if (GPIOINT_NOISE_FILTER_ENABLED(gpiocfg))
+        {
+          val |= (INT_ROUTE_PMU << shift);
+        }
+      else
+        {
+          val |= (INT_ROUTE_THROUGH << shift);
+        }
+      break;
+    case GPIOINT_LEVEL_LOW:
+      if (GPIOINT_NOISE_FILTER_ENABLED(gpiocfg))
+        {
+          val |= (INT_ROUTE_PMU << shift);
+        }
+      else
+        {
+          val |= (INT_ROUTE_INVERTER << shift);
+        }
+      break;
+    case GPIOINT_EDGE_RISE:
+    case GPIOINT_EDGE_FALL:
+    case GPIOINT_EDGE_BOTH:
+      val |= (INT_ROUTE_PMU_LATCH << shift);
+      break;
+    default:
+      DEBUGASSERT(0);
+      break;
+    }
+  putreg32(val, selreg);
+
+  return 0;
+}
+
+/* Invert interrupt polarity in INTC */
+
+static void invert_irq(int irq)
+{
+  irqstate_t flags;
+  uint32_t val;
+
+  flags = enter_critical_section();
+
+  val = getreg32(CXD56_INTC_INVERT);
+  val ^= (1 << (irq - CXD56_IRQ_EXTINT));
+  putreg32(val, CXD56_INTC_INVERT);
+
+  leave_critical_section(flags);
+}
+
+static bool inverted_irq(int irq)
+{
+  uint32_t val;
+
+  val = getreg32(CXD56_INTC_INVERT);
+  return ((val & (1 << (irq - CXD56_IRQ_EXTINT))) != 0);
+}
+
+static bool enabled_irq(int irq)
+{
+  uint32_t val;
+
+  val = getreg32(CXD56_INTC_ENABLE);
+  return ((val & (1 << (irq - CXD56_IRQ_EXTINT))) != 0);
+}
+
+static int gpioint_handler(int irq, FAR void *context, FAR void *arg)
+{
+  uint32_t val;
+  uint32_t shift;
+  uint32_t polreg = CXD56_TOPREG_PMU_WAKE_TRIG_INTDET0;
+  int slot = GET_IRQ2SLOT(irq);
+
+  /* Invert mask of interrupt to be disable temporarily */
+
+  invert_irq(irq);
+
+  if (g_bothedge & (1 << slot))
+    {
+      g_isr[slot](irq, context, arg);
+      return 0;
+    }
+
+  /* Get the polarity */
+
+  shift = 16 + (slot * 4);
+  if (32 <= shift)
+    {
+      polreg = CXD56_TOPREG_PMU_WAKE_TRIG_INTDET1;
+      shift -= 32;
+    }
+
+  val = getreg32(polreg);
+  val = (val >> shift) & 0x7;
+
+  if (inverted_irq(irq))
+    {
+      /* Clear edge interrupt */
+
+      if (GPIOINT_IS_EDGE(val))
+        {
+          /* TBD: ignore access protection */
+
+          putreg32(1 << (slot + 16), CXD56_TOPREG_PMU_WAKE_TRIG0_CLR);
+        }
+
+      g_isr[slot](irq, context, arg);
+    }
+
+  return 0;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_gpioint_config
+ *
+ * Description:
+ *   Configure a GPIO pin as an GPIO pin interrupt source
+ *
+ * Input Parameters:
+ *   pin - Pin number defined in cxd56_pinconfig.h
+ *   gpiocfg - GPIO Interrupt Polarity and Noise Filter Configuration Value
+ *   isr - Interrupt handler. If isr is NULL, then free an allocated handler.
+ *
+ * Returned Value:
+ *   IRQ number on success; a negated errno value on failure.
+ *
+ * Assumptions:
+ *   The interrupt are disabled so that read-modify-write operations are safe.
+ *
+ ****************************************************************************/
+
+int cxd56_gpioint_config(uint32_t pin, uint32_t gpiocfg, xcpt_t isr)
+{
+  int slot;
+  int irq;
+  irqstate_t flags;
+
+  slot = alloc_slot(pin, (isr != NULL));
+  if (slot < 0)
+    {
+      return -ENXIO;
+    }
+
+  irq = GET_SLOT2IRQ(slot);
+
+  if (isr == NULL)
+    {
+      /* disable GPIO input */
+
+      cxd56_gpio_config(pin, false);
+
+      /* disable interrupt */
+
+      irq_attach(irq, NULL, NULL);
+      g_isr[slot] = NULL;
+
+      flags = enter_critical_section();
+      g_bothedge &= ~(1 << slot);
+      leave_critical_section(flags);
+      return irq;
+    }
+
+  /* enable GPIO input */
+
+  cxd56_gpio_config(pin, true);
+
+  /* set GPIO interrupt configuration */
+
+  if (gpiocfg & GPIOINT_TOGGLE_BOTH_MASK) {
+
+    /* set GPIO pseudo both edge interrupt */
+
+    flags = enter_critical_section();
+    g_bothedge |= (1 << slot);
+    leave_critical_section(flags);
+
+    /* detect the change from the current signal */
+
+    if (true == cxd56_gpio_read(pin)) {
+      gpiocfg |= GPIOINT_SET_POLARITY(GPIOINT_LEVEL_LOW);
+    } else {
+      gpiocfg |= GPIOINT_SET_POLARITY(GPIOINT_LEVEL_HIGH);
+    }
+  }
+
+  set_gpioint_config(slot, gpiocfg);
+
+  if ((gpiocfg & GPIOINT_TOGGLE_MODE_MASK) || GPIOINT_IS_EDGE(gpiocfg))
+    {
+      irq_attach(irq, gpioint_handler, (void *)pin); /* call intermediate handler */
+      g_isr[slot] = isr;
+    }
+  else
+    {
+      irq_attach(irq, isr, (void *)pin); /* call user handler directly */
+      g_isr[slot] = NULL;
+    }
+
+  return irq;
+}
+
+/****************************************************************************
+ * Name: cxd56_gpioint_irq
+ *
+ * Description:
+ *   Get a GPIO interrupt number for specified pin number
+ *
+ * Returned Value:
+ *   IRQ number on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int cxd56_gpioint_irq(uint32_t pin)
+{
+  return get_pin2irq(pin);
+}
+
+/****************************************************************************
+ * Name: cxd56_gpioint_pin
+ *
+ * Description:
+ *   Get a pin number for specified IRQ number
+ *
+ * Returned Value:
+ *   Pin number on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int cxd56_gpioint_pin(int irq)
+{
+  int slot;
+
+  if ((irq < CXD56_IRQ_EXDEVICE_0) || (CXD56_IRQ_EXDEVICE_11 < irq))
+    {
+      return -1;
+    }
+  slot = GET_IRQ2SLOT(irq);
+  return get_slot2pin(slot);
+}
+
+/****************************************************************************
+ * Name: cxd56_gpioint_enable
+ *
+ * Description:
+ *   Enable a GPIO interrupt for specified pin number
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void cxd56_gpioint_enable(uint32_t pin)
+{
+  int irq = get_pin2irq(pin);
+
+  if (irq > 0)
+    {
+      up_enable_irq(irq);
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_gpioint_disable
+ *
+ * Description:
+ *   Disable a GPIO interrupt for specified pin number
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void cxd56_gpioint_disable(uint32_t pin)
+{
+  int irq = get_pin2irq(pin);
+
+  if (irq > 0)
+    {
+      up_disable_irq(irq);
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_gpioint_invert
+ *
+ * Description:
+ *   Invert polarity of a GPIO interrupt for specified pin number
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void cxd56_gpioint_invert(uint32_t pin)
+{
+  int irq = get_pin2irq(pin);
+
+  if (irq > 0)
+    {
+      invert_irq(irq);
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_gpioint_status
+ *
+ * Description:
+ *   Get a gpio interrupt status
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int cxd56_gpioint_status(uint32_t pin, cxd56_gpioint_status_t *stat)
+{
+  uint32_t val;
+  uint32_t shift;
+  uint32_t polreg = CXD56_TOPREG_PMU_WAKE_TRIG_INTDET0;
+  int slot;
+
+  DEBUGASSERT(stat);
+
+  /* Get IRQ number */
+
+  stat->irq = cxd56_gpioint_irq(pin);
+
+  if (stat->irq < 0)
+    {
+      return -EINVAL;
+    }
+
+  /* Get polarity */
+
+  slot = GET_IRQ2SLOT(stat->irq);
+  shift = 16 + (slot * 4);
+  if (32 <= shift)
+    {
+      polreg = CXD56_TOPREG_PMU_WAKE_TRIG_INTDET1;
+      shift -= 32;
+    }
+
+  val = getreg32(polreg);
+  stat->polarity = GPIOINT_GET_POLARITY(val >> shift);
+
+  /* Replace for pseudo edge */
+
+  if ((g_isr[slot]) && (stat->polarity == GPIOINT_LEVEL_HIGH))
+    {
+      stat->polarity = GPIOINT_EDGE_RISE;
+    }
+  if ((g_isr[slot]) && (stat->polarity == GPIOINT_LEVEL_LOW))
+    {
+      stat->polarity = GPIOINT_EDGE_FALL;
+    }
+  if ((g_isr[slot]) && (g_bothedge & (1 << slot)))
+    {
+      stat->polarity = GPIOINT_EDGE_BOTH;
+    }
+
+  /* Get noise filter enabled or not */
+
+  val = getreg32(CXD56_TOPREG_PMU_WAKE_TRIG_NOISECUTEN0);
+  stat->filter = ((val >> (slot + 16)) & 1) ? true : false;
+
+  /* Get interrupt enabled or not */
+
+  stat->enable = enabled_irq(stat->irq);
+
+  return OK;
+}
+
+#endif /* CONFIG_CXD56_GPIO_IRQ */
diff --git a/arch/arm/src/cxd56xx/cxd56_gpioint.h b/arch/arm/src/cxd56xx/cxd56_gpioint.h
new file mode 100644
index 00000000000..8f198b1fe36
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_gpioint.h
@@ -0,0 +1,233 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_gpioint.h
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_GPIOINT_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56_GPIOINT_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include "chip.h"
+
+#ifdef CONFIG_CXD56_GPIO_IRQ
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* 32-bit encoded gpioconf value
+ *
+ * 3322 2222 2222 1111 1111 1100 0000 0000
+ * 1098 7654 3210 9876 5432 1098 7654 3210
+ * ---- ---- ---- ---- ---- ---- ---- ----
+ * .... .... .... ..B. .... .... .... .... Both detect mode
+ * .... .... .... ...T .... .... .... .... Toggle detect mode
+ * .... .... .... .... .... .... .... N... Noise Filter
+ * .... .... .... .... .... .... .... .YYY Polarity
+ */
+
+/* GPIO Interrupt Polarity Definitions */
+
+//#define GPIOINT_INSTANT_HIGH      (0) /* Not supported */
+//#define GPIOINT_INSTANT_LOW       (1) /* Not supported */
+#define GPIOINT_LEVEL_HIGH          (2) /* High Level */
+#define GPIOINT_LEVEL_LOW           (3) /* Low Level */
+#define GPIOINT_EDGE_RISE           (4) /* Rising Edge */
+#define GPIOINT_EDGE_FALL           (5) /* Falling Edge */
+#define GPIOINT_EDGE_BOTH           (7) /* Both Edge */
+#define GPIOINT_PSEUDO_EDGE_RISE    (GPIOINT_LEVEL_HIGH | \
+                                     GPIOINT_TOGGLE_MODE_MASK)
+                                        /* Rising Edge without clear */
+#define GPIOINT_PSEUDO_EDGE_FALL    (GPIOINT_LEVEL_LOW | \
+                                     GPIOINT_TOGGLE_MODE_MASK)
+                                        /* Falling Edge without clear */
+#define GPIOINT_PSEUDO_EDGE_BOTH    (GPIOINT_TOGGLE_MODE_MASK | \
+                                     GPIOINT_TOGGLE_BOTH_MASK)
+                                        /* Both Edge without clear */
+
+/* GPIO Interrupt Noise Filter Definitions */
+
+#define GPIOINT_NOISE_FILTER_ENABLE     (1u << 3)
+#define GPIOINT_NOISE_FILTER_DISABLE    (0u << 3)
+
+/* Use Pseudo Edge Interrupt */
+
+#define GPIOINT_TOGGLE_MODE_MASK        (1u << 16)
+#define GPIOINT_TOGGLE_BOTH_MASK        (1u << 17)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+struct cxd56_gpioint_status_s
+{
+  int       irq;
+  uint32_t  polarity;
+  bool      filter;
+  bool      enable;
+};
+
+typedef struct cxd56_gpioint_status_s cxd56_gpioint_status_t;
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_gpioint_config
+ *
+ * Description:
+ *   Configure a GPIO pin as an GPIO pin interrupt source
+ *
+ * Input Parameters:
+ *   pin - Pin number defined in cxd56_pinconfig.h
+ *   gpiocfg - GPIO Interrupt Polarity and Noise Filter Configuration Value
+ *   isr - Interrupt handler
+ *
+ * Returned Value:
+ *   IRQ number on success; a negated errno value on failure.
+ *
+ * Assumptions:
+ *   The interrupt are disabled so that read-modify-write operations are safe.
+ *
+ ****************************************************************************/
+
+int cxd56_gpioint_config(uint32_t pin, uint32_t gpiocfg, xcpt_t isr);
+
+/****************************************************************************
+ * Name: cxd56_gpioint_irq
+ *
+ * Description:
+ *   Get a GPIO interrupt number for specified pin number
+ *
+ * Returned Value:
+ *   IRQ number on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int cxd56_gpioint_irq(uint32_t pin);
+
+/****************************************************************************
+ * Name: cxd56_gpioint_pin
+ *
+ * Description:
+ *   Get a pin number for specified IRQ number
+ *
+ * Returned Value:
+ *   Pin number on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int cxd56_gpioint_pin(int irq);
+
+/****************************************************************************
+ * Name: cxd56_gpioint_enable
+ *
+ * Description:
+ *   Enable a GPIO interrupt for specified pin number
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void cxd56_gpioint_enable(uint32_t pin);
+
+/****************************************************************************
+ * Name: cxd56_gpioint_disable
+ *
+ * Description:
+ *   Disable a GPIO interrupt for specified pin number
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void cxd56_gpioint_disable(uint32_t pin);
+
+/****************************************************************************
+ * Name: cxd56_gpioint_invert
+ *
+ * Description:
+ *   Invert polarity of a GPIO interrupt for specified pin number
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void cxd56_gpioint_invert(uint32_t pin);
+
+/********************************************************************************************
+ * Name: cxd56_gpioint_status
+ *
+ * Description:
+ *   Get a gpio interrupt status
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ********************************************************************************************/
+
+int cxd56_gpioint_status(uint32_t pin, cxd56_gpioint_status_t *stat);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_CXD56_GPIO_IRQ */
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_GPIOINT_H */
diff --git a/arch/arm/src/cxd56xx/cxd56_icc.c b/arch/arm/src/cxd56xx/cxd56_icc.c
new file mode 100644
index 00000000000..a7dc5b17df4
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_icc.c
@@ -0,0 +1,653 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_icc.c
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "up_arch.h"
+#include "chip.h"
+#include "cxd56_cpufifo.h"
+#include "cxd56_icc.h"
+
+#ifdef CONFIG_CXD56_ICC
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_CXD56_CPUFIFO_NBUFFERS
+#  define NBUFFERS 4
+#else
+#  define NBUFFERS CONFIG_CXD56_CPUFIFO_NBUFFERS
+#endif
+
+#define NPROTOCOLS 16
+#define GET_PROTOCOLID(w) (((w)[0] >> 24) & 0xf)
+
+#define NCPUS      8
+
+#define FLAG_TIMEOUT (1 << 0)
+
+#define IS_SIGNAL(w) (((((w)[0]) >> 24) & 0xf) == CXD56_PROTO_SIG)
+
+#ifdef CONFIG_CXD56_ICC_DEBUG
+#  define iccerr(fmt, ...)  _err(fmt, ##__VA_ARGS__)
+#  define iccinfo(fmt, ...) _info(fmt, ##__VA_ARGS__)
+#else
+#  define iccerr(fmt, ...)
+#  define iccinfo(fmt, ...)
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct iccmsg_msg_s
+{
+  /* Little endian */
+
+  uint16_t pdata;
+  uint8_t msgid;
+  uint8_t proto: 4;
+  uint8_t cpuid: 4;
+
+  uint32_t data;
+};
+
+struct iccreq_s
+{
+  sq_entry_t entry;
+
+  union
+  {
+    uint32_t word[2];
+    struct iccmsg_msg_s msg;
+  };
+};
+
+struct iccdev_s
+{
+  union
+  {
+    cxd56_icchandler_t handler;
+    cxd56_iccsighandler_t sighandler;
+  } u;
+
+  FAR void *userdata;
+  sem_t rxwait;
+  WDOG_ID rxtimeout;
+
+  int flags;
+
+  /* for POSIX signal */
+
+  int signo;
+  int pid;
+  FAR void *sigdata;
+
+  struct sq_queue_s recvq;
+  struct sq_queue_s freelist;
+  struct iccreq_s pool[NBUFFERS];
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int icc_sighandler(int cpuid, int protoid, uint32_t pdata,
+                          uint32_t data, FAR void *userdata);
+static int icc_msghandler(int cpuid, int protoid, uint32_t pdata,
+                          uint32_t data, FAR void *userdata);
+static int icc_irqhandler(int cpuid, uint32_t word[2]);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static struct iccdev_s *g_protocol[NPROTOCOLS];
+static struct iccdev_s *g_cpumsg[NCPUS];
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static void icc_semtake(sem_t *semid)
+{
+  while (sem_wait(semid) != 0)
+    {
+      ASSERT(errno == EINTR);
+    }
+}
+
+static void icc_semgive(sem_t *semid)
+{
+  sem_post(semid);
+}
+
+static FAR struct iccdev_s *icc_getprotocol(int protoid)
+{
+  if (protoid < 0 || protoid >= NPROTOCOLS)
+    {
+      return NULL;
+    }
+  return g_protocol[protoid];
+}
+
+static FAR struct iccdev_s *icc_getcpu(int cpuid)
+{
+  if (cpuid < 0 || cpuid >= NCPUS)
+    {
+      return NULL;
+    }
+  return g_cpumsg[cpuid];
+}
+
+static int icc_irqhandler(int cpuid, uint32_t word[2])
+{
+  FAR struct iccdev_s *priv;
+  FAR struct iccreq_s *req;
+  int protoid;
+
+  protoid = GET_PROTOCOLID(word);
+  priv = icc_getprotocol(protoid);
+  if (!priv)
+    {
+      /* Nobody waits this message... */
+
+      iccerr("nobody waits %08x %08x\n", word[0], word[1]);
+      return OK;
+    }
+
+  /* If handler has been registered, then call it. */
+
+  if (priv->u.handler)
+    {
+      int ret;
+
+      ret = priv->u.handler(cpuid, protoid, word[0] & 0xffffff, word[1],
+                            priv->userdata);
+      if (ret == OK)
+        {
+          return OK;
+        }
+    }
+
+  /* If MSG protocol, then replace priv to cpu ones. */
+
+  if (protoid == CXD56_PROTO_MSG)
+    {
+      priv = icc_getcpu(cpuid);
+      if (!priv)
+        {
+          iccerr("nobody waits from CPU %d\n", cpuid);
+          return OK;
+        }
+    }
+
+  req = (FAR struct iccreq_s *)sq_remfirst(&priv->freelist);
+  if (!req)
+    {
+      iccerr("Receive buffer is full.\n");
+      return -ENOMEM;
+    }
+
+  req->word[0] = word[0];
+  req->word[1] = word[1];
+
+  sq_addlast((FAR sq_entry_t *)req, &priv->recvq);
+
+  icc_semgive(&priv->rxwait);
+
+  /* If signal registered by cxd56_iccnotify(), then send POSIX signal to
+   * process.
+   */
+
+#ifndef CONFIG_DISABLE_SIGNAL
+  if (priv->pid != INVALID_PROCESS_ID)
+    {
+#  ifdef CONFIG_CAN_PASS_STRUCTS
+      union sigval value;
+      value.sival_ptr = priv->sigdata;
+      (void)sigqueue(priv->pid, priv->signo, value);
+#  else
+      (void)sigqueue(priv->pid, priv->signo, priv->sigdata);
+#  endif
+    }
+#endif
+
+  return OK;
+}
+
+static int icc_sighandler(int cpuid, int protoid, uint32_t pdata,
+                          uint32_t data, FAR void *userdata)
+{
+  FAR struct iccdev_s *priv = icc_getcpu(cpuid);
+
+  if (!priv)
+    {
+      /* Nobody waits this message... */
+
+      iccerr("nobody waits %08x %08x\n", word[0], word[1]);
+      return OK;
+    }
+
+  iccinfo("Caught signal\n");
+
+  if (priv->u.sighandler)
+    {
+      int8_t signo;
+      uint16_t sigdata;
+
+      signo   = (int8_t)((pdata >> 16) & 0xff);
+      sigdata = pdata & 0xffff;
+
+      iccinfo("Call signal handler with No %d.\n", signo);
+      priv->u.sighandler(signo, sigdata, data, priv->userdata);
+    }
+  return OK;
+}
+
+static int icc_msghandler(int cpuid, int protoid, uint32_t pdata,
+                               uint32_t data, FAR void *userdata)
+{
+  /* Do nothing. This handler used for reserve MSG protocol handler.
+   * This handler returns -1 to indicate not consumed the passed
+   * message.
+   */
+
+  return -1;
+}
+
+static void icc_rxtimeout(int argc, uint32_t arg, ...)
+{
+  FAR struct iccdev_s *priv = (FAR struct iccdev_s *)arg;
+  icc_semgive(&priv->rxwait);
+}
+
+static int icc_recv(FAR struct iccdev_s *priv, FAR iccmsg_t *msg, int32_t ms)
+{
+  FAR struct iccreq_s *req;
+  irqstate_t flags;
+  int ret = OK;
+
+  if (ms)
+    {
+      int32_t timo;
+      timo = ms * 1000 / CONFIG_USEC_PER_TICK;
+      wd_start(priv->rxtimeout, timo, icc_rxtimeout, 1, (uint32_t)priv);
+    }
+
+  icc_semtake(&priv->rxwait);
+
+  wd_cancel(priv->rxtimeout);
+
+  flags = enter_critical_section();
+  req   = (FAR struct iccreq_s *)sq_remfirst(&priv->recvq);
+
+  if (req)
+    {
+      msg->msgid = req->msg.msgid;
+      msg->data  = req->msg.data;
+      msg->cpuid = req->msg.cpuid;
+      msg->protodata = req->msg.pdata;
+      sq_addlast((FAR sq_entry_t *)req, &priv->freelist);
+    }
+  else
+    {
+      ret = -ETIMEDOUT;
+    }
+
+  leave_critical_section(flags);
+
+  return ret;
+}
+
+static FAR struct iccdev_s *icc_devnew(void)
+{
+  FAR struct iccdev_s *priv;
+  int i;
+
+  priv = (struct iccdev_s *)kmm_malloc(sizeof(struct iccdev_s));
+  if (!priv)
+    {
+      return NULL;
+    }
+  memset(priv, 0, sizeof(struct iccdev_s));
+
+  priv->rxtimeout = wd_create();
+
+  sem_init(&priv->rxwait, 0, 0);
+
+  /* Initialize receive queue and free list */
+
+  sq_init(&priv->recvq);
+  sq_init(&priv->freelist);
+
+  for (i = 0; i < NBUFFERS; i++)
+    {
+      sq_addlast((FAR sq_entry_t *)&priv->pool[i], &priv->freelist);
+    }
+
+  priv->pid = INVALID_PROCESS_ID;
+
+  return priv;
+}
+
+static void icc_devfree(FAR struct iccdev_s *priv)
+{
+  wd_delete(priv->rxtimeout);
+  kmm_free(priv);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+int cxd56_iccregisterhandler(int protoid, cxd56_icchandler_t handler,
+                             FAR void *data)
+{
+  FAR struct iccdev_s *priv;
+  irqstate_t flags;
+  int ret = OK;
+
+  flags = enter_critical_section();
+  priv = icc_getprotocol(protoid);
+  if (priv)
+    {
+      priv->u.handler  = handler;
+      priv->userdata = data;
+    }
+  else
+    {
+      ret = -EINVAL;
+    }
+  leave_critical_section(flags);
+
+  return ret;
+}
+
+int cxd56_iccregistersighandler(int cpuid, cxd56_iccsighandler_t handler,
+                                FAR void *data)
+{
+  FAR struct iccdev_s *priv;
+  irqstate_t flags;
+  int ret = OK;
+
+  flags = enter_critical_section();
+  priv = icc_getcpu(cpuid);
+  if (priv)
+    {
+      priv->u.sighandler  = handler;
+      priv->userdata = data;
+    }
+  else
+    {
+      ret = -EINVAL;
+    }
+  leave_critical_section(flags);
+
+  return ret;
+}
+
+int cxd56_iccsend(int protoid, FAR iccmsg_t *msg, int32_t ms)
+{
+  FAR struct iccdev_s *priv;
+  struct iccreq_s req;
+
+  if (!msg)
+    {
+      return -EINVAL;
+    }
+
+  priv = icc_getprotocol(protoid);
+  if (!priv)
+    {
+      return -EINVAL;
+    }
+
+  req.msg.cpuid = msg->cpuid;
+  req.msg.msgid = msg->msgid;
+  req.msg.data  = msg->data;
+  req.msg.pdata = msg->protodata;
+  req.msg.proto = protoid;
+
+  priv->flags = 0;
+
+  return cxd56_cfpush(req.word);
+}
+
+int cxd56_iccsendmsg(FAR iccmsg_t *msg, int32_t ms)
+{
+  return cxd56_iccsend(CXD56_PROTO_MSG, msg, ms);
+}
+
+int cxd56_iccrecv(int protoid, FAR iccmsg_t *msg, int32_t ms)
+{
+  FAR struct iccdev_s *priv;
+
+  if (!msg)
+    {
+      return -EINVAL;
+    }
+
+  priv = icc_getprotocol(protoid);
+  if (!priv)
+    {
+      return -EINVAL;
+    }
+
+  return icc_recv(priv, msg, ms);
+}
+
+int cxd56_iccrecvmsg(FAR iccmsg_t *msg, int32_t ms)
+{
+  FAR struct iccdev_s *priv;
+
+  if (!msg)
+    {
+      return -EINVAL;
+    }
+
+  priv = icc_getcpu(msg->cpuid);
+  if (!priv)
+    {
+      return -EINVAL;
+    }
+
+  return icc_recv(priv, msg, ms);
+}
+
+int cxd56_iccsignal(int8_t cpuid, int8_t signo, int16_t sigdata, uint32_t data)
+{
+  struct iccreq_s req;
+
+  if (cpuid <= 2 && cpuid >= 7)
+    {
+      return -EINVAL;
+    }
+
+  req.msg.cpuid = cpuid;
+  req.msg.proto = CXD56_PROTO_SIG;
+  req.msg.msgid = signo;
+  req.msg.pdata = sigdata;
+  req.msg.data  = data;
+
+  return cxd56_cfpush(req.word);
+}
+
+int cxd56_iccnotify(int cpuid, int signo, FAR void *sigdata)
+{
+  FAR struct iccdev_s *priv;
+
+  priv = icc_getcpu(cpuid);
+  if (!priv)
+    {
+      return -ESRCH;
+    }
+
+  priv->pid     = getpid();
+  priv->signo   = signo;
+  priv->sigdata = sigdata;
+
+  return OK;
+}
+
+int cxd56_iccinit(int protoid)
+{
+  FAR struct iccdev_s *priv;
+
+  if (protoid < 0 || protoid >= NPROTOCOLS)
+    {
+      return -EINVAL;
+    }
+
+  if (g_protocol[protoid])
+    {
+      return OK;
+    }
+
+  priv = icc_devnew();
+  if (!priv)
+    {
+      return -ENOMEM;
+    }
+  g_protocol[protoid] = priv;
+
+  return OK;
+}
+
+int cxd56_iccinitmsg(int cpuid)
+{
+  FAR struct iccdev_s *priv;
+
+  if (cpuid < 0 || cpuid >= NCPUS)
+    {
+      return -EINVAL;
+    }
+
+  if (g_cpumsg[cpuid])
+    {
+      return OK;
+    }
+
+  priv = icc_devnew();
+  if (!priv)
+    {
+      return -ENOMEM;
+    }
+  g_cpumsg[cpuid] = priv;
+
+  return OK;
+}
+
+void cxd56_iccuninit(int protoid)
+{
+  FAR struct iccdev_s *priv;
+  irqstate_t flags;
+
+  if (protoid < 0 || protoid >= NPROTOCOLS)
+    {
+      return;
+    }
+
+  flags = enter_critical_section();
+  priv  = g_protocol[protoid];
+  if (priv)
+    {
+      icc_devfree(priv);
+      g_protocol[protoid] = NULL;
+    }
+  leave_critical_section(flags);
+}
+
+void cxd56_iccuninitmsg(int cpuid)
+{
+  FAR struct iccdev_s *priv;
+  irqstate_t flags;
+
+  if (cpuid < 0 || cpuid >= NCPUS)
+    {
+      return;
+    }
+
+  flags = enter_critical_section();
+  priv  = g_cpumsg[cpuid];
+  if (priv)
+    {
+      icc_devfree(priv);
+      g_cpumsg[cpuid] = NULL;
+    }
+  leave_critical_section(flags);
+}
+
+void cxd56_iccinitialize(void)
+{
+  int i;
+
+  for (i = 0; i < NPROTOCOLS; i++)
+    {
+      g_protocol[i] = NULL;
+    }
+
+  for (i = 0; i < NCPUS; i++)
+    {
+      g_cpumsg[i] = NULL;
+    }
+
+  /* Protocol MSG and SIG is special, reserved by ICC driver. */
+
+  cxd56_iccinit(CXD56_PROTO_MSG);
+  cxd56_iccregisterhandler(CXD56_PROTO_MSG, icc_msghandler, NULL);
+  cxd56_iccinit(CXD56_PROTO_SIG);
+  cxd56_iccregisterhandler(CXD56_PROTO_SIG, icc_sighandler, NULL);
+
+  cxd56_cfregrxhandler(icc_irqhandler);
+}
+
+#endif
diff --git a/arch/arm/src/cxd56xx/cxd56_icc.h b/arch/arm/src/cxd56xx/cxd56_icc.h
new file mode 100644
index 00000000000..a5d9f667f9d
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_icc.h
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_icc.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_ICC_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56_ICC_H
+
+#define CXD56_PROTO_MSG       0 /* Generic message */
+#define CXD56_PROTO_MBX       1
+#define CXD56_PROTO_SEM       2
+#define CXD56_PROTO_FLG       3
+#define CXD56_PROTO_MPF       4
+#define CXD56_PROTO_DBG       5
+#define CXD56_PROTO_AUDIO     6
+#define CXD56_PROTO_CALLBACK  7
+#define CXD56_PROTO_HOTSLEEP  8
+#define CXD56_PROTO_IMAGE     9
+#define CXD56_PROTO_PM       10 /* Power manager */
+#define CXD56_PROTO_SYSCTL   12
+#define CXD56_PROTO_GNSS     13
+#define CXD56_PROTO_SIG      15 /* Inter-CPU Comm signal */
+
+typedef int (*cxd56_icchandler_t)(int cpuid, int protoid, uint32_t pdata,
+                                  uint32_t data, FAR void *userdata);
+typedef int (*cxd56_iccsighandler_t)(int8_t signo, uint16_t sigdata,
+                                     uint32_t data, FAR void *userdata);
+
+struct cxd56_iccmsg_s
+{
+  int8_t cpuid;
+  int8_t msgid;
+  uint16_t protodata;
+  uint32_t data;
+};
+typedef struct cxd56_iccmsg_s iccmsg_t;
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+int cxd56_iccinit(int protoid);
+int cxd56_iccinitmsg(int cpuid);
+void cxd56_iccuninit(int protoid);
+void cxd56_iccuninitmsg(int cpuid);
+int cxd56_iccregisterhandler(int protoid, cxd56_icchandler_t handler,
+                             FAR void *data);
+int cxd56_iccregistersighandler(int cpuid, cxd56_iccsighandler_t handler,
+                                FAR void *data);
+int cxd56_iccsend(int protoid, FAR iccmsg_t *msg, int32_t ms);
+int cxd56_iccrecv(int protoid, FAR iccmsg_t *msg, int32_t ms);
+int cxd56_iccsendmsg(FAR iccmsg_t *msg, int32_t ms);
+int cxd56_iccrecvmsg(FAR iccmsg_t *msg, int32_t ms);
+int cxd56_iccsignal(int8_t cpuid, int8_t signo, int16_t sigdata,
+                    uint32_t data);
+int cxd56_iccnotify(int cpuid, int signo, FAR void *sigdata);
+
+void cxd56_iccinitialize(void);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_ICC_H */
diff --git a/arch/arm/src/cxd56xx/cxd56_idle.c b/arch/arm/src/cxd56xx/cxd56_idle.c
new file mode 100644
index 00000000000..b0655d025a2
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_idle.c
@@ -0,0 +1,189 @@
+/****************************************************************************
+ * arch/arm/src/cxd56/cxd56_idle.c
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ *   Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+#include "up_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Does the board support an IDLE LED to indicate that the board is in the
+ * IDLE state?
+ */
+
+#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
+#  define BEGIN_IDLE() board_autoled_on(LED_IDLE)
+#  define END_IDLE()   board_autoled_off(LED_IDLE)
+#else
+#  define BEGIN_IDLE()
+#  define END_IDLE()
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_idlepm
+ *
+ * Description:
+ *   Perform IDLE state power management.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+static void up_idlepm(void)
+{
+  static enum pm_state_e oldstate = PM_NORMAL;
+  enum pm_state_e newstate;
+  irqstate_t flags;
+  int ret;
+
+  /* Decide, which power saving level can be obtained */
+
+  newstate = pm_checkstate(PM_IDLE_DOMAIN);
+
+  /* Check for state changes */
+
+  if (newstate != oldstate)
+    {
+      flags = enter_critical_section();
+
+      /* Perform board-specific, state-dependent logic here */
+
+      _info("newstate= %d oldstate=%d\n", newstate, oldstate);
+
+      /* Then force the global state change */
+
+      ret = pm_changestate(PM_IDLE_DOMAIN, newstate);
+      if (ret < 0)
+        {
+          /* The new state change failed, revert to the preceding state */
+
+          (void)pm_changestate(PM_IDLE_DOMAIN, oldstate);
+        }
+      else
+        {
+          /* Save the new state */
+
+          oldstate = newstate;
+        }
+
+      /* MCU-specific power management logic */
+
+      switch (newstate)
+        {
+          case PM_NORMAL:
+            break;
+
+          case PM_IDLE:
+            break;
+
+          case PM_STANDBY:
+            cxd56_pmstandby(true);
+            break;
+
+          case PM_SLEEP:
+            (void)cxd56_pmsleep();
+            break;
+
+          default:
+            break;
+        }
+
+      leave_critical_section(flags);
+    }
+}
+#else
+#  define up_idlepm()
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_idle
+ *
+ * Description:
+ *   up_idle() is the logic that will be executed when their is no other
+ *   ready-to-run task.  This is processor idle time and will continue until
+ *   some interrupt occurs to cause a context switch from the idle task.
+ *
+ *   Processing in this state may be processor-specific. e.g., this is where
+ *   power management operations might be performed.
+ *
+ ****************************************************************************/
+
+void up_idle(void)
+{
+#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
+  /* If the system is idle and there are no timer interrupts, then process
+   * "fake" timer interrupts. Hopefully, something will wake up.
+   */
+
+  nxsched_process_timer();
+#else
+
+  /* Perform IDLE mode power management */
+
+  up_idlepm();
+
+  /* Sleep until an interrupt occurs to save power */
+
+  BEGIN_IDLE();
+  asm("WFI");
+  END_IDLE();
+#endif
+}
diff --git a/arch/arm/src/cxd56xx/cxd56_irq.c b/arch/arm/src/cxd56xx/cxd56_irq.c
new file mode 100644
index 00000000000..1734e25493c
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_irq.c
@@ -0,0 +1,558 @@
+/****************************************************************************
+ * arch/arm/src/cxd56/cxd56_irq.c
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ *   Copyright (C) 2012-2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "chip.h"
+#include "nvic.h"
+#include "ram_vectors.h"
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "cxd56_irq.h"
+
+#ifdef CONFIG_SMP
+#  include "init/init.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Get a 32-bit version of the default priority */
+
+#define DEFPRIORITY32 \
+  (CXD56M4_SYSH_PRIORITY_DEFAULT << 24 | CXD56M4_SYSH_PRIORITY_DEFAULT << 16 | \
+   CXD56M4_SYSH_PRIORITY_DEFAULT << 8 | CXD56M4_SYSH_PRIORITY_DEFAULT)
+
+#define INTC_EN(n) (CXD56_INTC_BASE + 0x10 + (((n) >> 5) << 2))
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a references to the current interrupt level
+ * register storage structure.  If is non-NULL only during interrupt
+ * processing.  Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+#ifdef CONFIG_SMP
+/* For the case of configurations with multiple CPUs, then there must be one
+ * such value for each processor that can receive an interrupt.
+ */
+
+volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
+#else
+volatile uint32_t *g_current_regs[1];
+#endif
+
+/* This is the address of the  exception vector table (determined by the
+ * linker script).
+ */
+
+extern uint32_t _vectors[];
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_dumpnvic
+ *
+ * Description:
+ *   Dump some interesting NVIC registers
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_DEBUG_IRQ_INFO)
+static void cxd56_dumpnvic(const char *msg, int irq)
+{
+  irqstate_t flags;
+
+  flags = enter_critical_section();
+  irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
+  irqinfo("  INTCTRL:    %08x VECTAB: %08x\n", getreg32(NVIC_INTCTRL),
+          getreg32(NVIC_VECTAB));
+#  if 0
+  irqinfo("  SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n",
+          getreg32(NVIC_SYSHCON_MEMFAULTENA),
+          getreg32(NVIC_SYSHCON_BUSFAULTENA),
+          getreg32(NVIC_SYSHCON_USGFAULTENA),
+          getreg32(NVIC_SYSTICK_CTRL_ENABLE));
+#  endif
+  irqinfo("  IRQ ENABLE: %08x %08x\n", getreg32(NVIC_IRQ0_31_ENABLE),
+          getreg32(NVIC_IRQ32_63_ENABLE));
+  irqinfo("  SYSH_PRIO:  %08x %08x %08x\n",
+          getreg32(NVIC_SYSH4_7_PRIORITY),
+          getreg32(NVIC_SYSH8_11_PRIORITY),
+          getreg32(NVIC_SYSH12_15_PRIORITY));
+  irqinfo("  IRQ PRIO:   %08x %08x %08x %08x\n",
+          getreg32(NVIC_IRQ0_3_PRIORITY),
+          getreg32(NVIC_IRQ4_7_PRIORITY),
+          getreg32(NVIC_IRQ8_11_PRIORITY),
+          getreg32(NVIC_IRQ12_15_PRIORITY));
+  irqinfo("              %08x %08x %08x %08x\n",
+          getreg32(NVIC_IRQ16_19_PRIORITY),
+          getreg32(NVIC_IRQ20_23_PRIORITY),
+          getreg32(NVIC_IRQ24_27_PRIORITY),
+          getreg32(NVIC_IRQ28_31_PRIORITY));
+  irqinfo("              %08x %08x %08x %08x\n",
+          getreg32(NVIC_IRQ32_35_PRIORITY),
+          getreg32(NVIC_IRQ36_39_PRIORITY),
+          getreg32(NVIC_IRQ40_43_PRIORITY),
+          getreg32(NVIC_IRQ44_47_PRIORITY));
+  irqinfo("              %08x %08x %08x\n",
+          getreg32(NVIC_IRQ48_51_PRIORITY),
+          getreg32(NVIC_IRQ52_55_PRIORITY),
+          getreg32(NVIC_IRQ56_59_PRIORITY));
+  leave_critical_section(flags);
+}
+#else
+#  define cxd56_dumpnvic(msg, irq)
+#endif
+
+/****************************************************************************
+ * Name: cxd56_nmi, cxd56_busfault, cxd56_usagefault, cxd56_pendsv,
+ *       cxd56_dbgmonitor, cxd56_pendsv, cxd56_reserved
+ *
+ * Description:
+ *   Handlers for various exceptions.  None are handled and all are fatal
+ *   error conditions.  The only advantage these provided over the default
+ *   unexpected interrupt handler is that they provide a diagnostic output.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_FEATURES
+static int cxd56_nmi(int irq, FAR void *context, FAR void *arg)
+{
+  (void)up_irq_save();
+  _err("PANIC!!! NMI received\n");
+  PANIC();
+  return 0;
+}
+
+static int cxd56_busfault(int irq, FAR void *context, FAR void *arg)
+{
+  (void)up_irq_save();
+  _err("PANIC!!! Bus fault recived\n");
+  PANIC();
+  return 0;
+}
+
+static int cxd56_usagefault(int irq, FAR void *context, FAR void *arg)
+{
+  (void)up_irq_save();
+  _err("PANIC!!! Usage fault received\n");
+  PANIC();
+  return 0;
+}
+
+static int cxd56_pendsv(int irq, FAR void *context, FAR void *arg)
+{
+  (void)up_irq_save();
+  _err("PANIC!!! PendSV received\n");
+  PANIC();
+  return 0;
+}
+
+static int cxd56_dbgmonitor(int irq, FAR void *context, FAR void *arg)
+{
+  (void)up_irq_save();
+  _err("PANIC!!! Debug Monitor received\n");
+  PANIC();
+  return 0;
+}
+
+static int cxd56_reserved(int irq, FAR void *context, FAR void *arg)
+{
+  (void)up_irq_save();
+  _err("PANIC!!! Reserved interrupt\n");
+  PANIC();
+  return 0;
+}
+#endif
+
+/****************************************************************************
+ * Name: cxd56_prioritize_syscall
+ *
+ * Description:
+ *   Set the priority of an exception.  This function may be needed
+ *   internally even if support for prioritized interrupts is not enabled.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+static inline void cxd56_prioritize_syscall(int priority)
+{
+  uint32_t regval;
+
+  /* SVCALL is system handler 11 */
+
+  regval = getreg32(NVIC_SYSH8_11_PRIORITY);
+  regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
+  regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
+  putreg32(regval, NVIC_SYSH8_11_PRIORITY);
+}
+#endif
+
+static int excinfo(int irq, uint32_t *regaddr, uint32_t *bit)
+{
+  *regaddr = NVIC_SYSHCON;
+  switch (irq)
+    {
+      case CXD56_IRQ_MEMFAULT:
+        *bit = NVIC_SYSHCON_MEMFAULTENA;
+        break;
+
+      case CXD56_IRQ_BUSFAULT:
+        *bit = NVIC_SYSHCON_BUSFAULTENA;
+        break;
+
+      case CXD56_IRQ_USAGEFAULT:
+        *bit = NVIC_SYSHCON_USGFAULTENA;
+        break;
+
+      case CXD56_IRQ_SYSTICK:
+        *regaddr = NVIC_SYSTICK_CTRL;
+        *bit     = NVIC_SYSTICK_CTRL_ENABLE;
+        break;
+
+      default:
+        return ERROR; /* Invalid or unsupported exception */
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ *
+ * Description:
+ *   Complete initialization of the interrupt system and enable normal,
+ *   interrupt processing.
+ *
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+  uint32_t regaddr;
+  int num_priority_registers;
+
+  /* Disable all interrupts */
+
+  putreg32(0, NVIC_IRQ0_31_ENABLE);
+  putreg32(0, NVIC_IRQ32_63_ENABLE);
+  putreg32(0, NVIC_IRQ64_95_ENABLE);
+  putreg32(0, NVIC_IRQ96_127_ENABLE);
+
+  /* Make sure that we are using the correct vector table.  The default
+   * vector address is 0x0000:0000 but if we are executing code that is
+   * positioned in SRAM or in external FLASH, then we may need to reset
+   * the interrupt vector so that it refers to the table in SRAM or in
+   * external FLASH.
+   */
+
+  putreg32((uint32_t)_vectors, NVIC_VECTAB);
+
+#ifdef CONFIG_ARCH_RAMVECTORS
+  /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
+   * vector table that requires special initialization.
+   */
+
+  up_ramvec_initialize();
+#endif
+
+  /* Set all interrupts (and exceptions) to the default priority */
+
+  putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
+  putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
+
+  /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt
+   * lines that the NVIC supports:
+   *
+   *  0 -> 32 interrupt lines,  8 priority registers
+   *  1 -> 64 "       " "   ", 16 priority registers
+   *  2 -> 96 "       " "   ", 32 priority registers
+   *  ...
+   */
+
+  num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8;
+
+  /* Now set all of the interrupt lines to the default priority */
+
+  regaddr = NVIC_IRQ0_3_PRIORITY;
+  while (num_priority_registers--)
+    {
+      putreg32(DEFPRIORITY32, regaddr);
+      regaddr += 4;
+    }
+
+  /* currents_regs is non-NULL only while processing an interrupt */
+
+  CURRENT_REGS = NULL;
+
+  /* Attach the SVCall and Hard Fault exception handlers.  The SVCall
+   * exception is used for performing context switches; The Hard Fault
+   * must also be caught because a SVCall may show up as a Hard Fault
+   * under certain conditions.
+   */
+
+  irq_attach(CXD56_IRQ_SVCALL, up_svcall, NULL);
+  irq_attach(CXD56_IRQ_HARDFAULT, up_hardfault, NULL);
+
+  /* Set the priority of the SVCall interrupt */
+
+#ifdef CONFIG_ARCH_IRQPRIO
+  /* up_prioritize_irq(CXD56_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
+#endif
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+  cxd56_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
+#endif
+
+  /* If the MPU is enabled, then attach and enable the Memory Management
+   * Fault handler.
+   */
+
+#ifdef CONFIG_ARM_MPU
+  irq_attach(CXD56_IRQ_MEMFAULT, up_memfault, NULL);
+  up_enable_irq(CXD56_IRQ_MEMFAULT);
+#endif
+
+  /* Attach all other processor exceptions (except reset and sys tick) */
+
+#ifdef CONFIG_DEBUG_FEATURES
+  irq_attach(CXD56_IRQ_NMI, cxd56_nmi, NULL);
+#  ifndef CONFIG_ARM_MPU
+  irq_attach(CXD56_IRQ_MEMFAULT, up_memfault, NULL);
+#  endif
+  irq_attach(CXD56_IRQ_BUSFAULT, cxd56_busfault, NULL);
+  irq_attach(CXD56_IRQ_USAGEFAULT, cxd56_usagefault, NULL);
+  irq_attach(CXD56_IRQ_PENDSV, cxd56_pendsv, NULL);
+  irq_attach(CXD56_IRQ_DBGMONITOR, cxd56_dbgmonitor, NULL);
+  irq_attach(CXD56_IRQ_RESERVED, cxd56_reserved, NULL);
+#endif
+
+  cxd56_dumpnvic("initial", CXD56_IRQ_NIRQS);
+
+  /* If a debugger is connected, try to prevent it from catching hardfaults.
+   * If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal
+   * operation.
+   */
+
+#if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV7M_USEBASEPRI)
+  {
+    uint32_t regval;
+
+    regval  = getreg32(NVIC_DEMCR);
+    regval &= ~NVIC_DEMCR_VCHARDERR;
+    putreg32(regval, NVIC_DEMCR);
+  }
+#endif
+
+  /* And finally, enable interrupts */
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+  up_irq_enable();
+#endif
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ *   Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+  uintptr_t regaddr;
+  uint32_t regval;
+  uint32_t bit;
+
+  if (irq >= CXD56_IRQ_EXTINT)
+    {
+      irqstate_t flags = enter_critical_section();
+      irq -= CXD56_IRQ_EXTINT;
+      bit  = 1 << (irq & 0x1f);
+
+      regval  = getreg32(INTC_EN(irq));
+      regval &= ~bit;
+      putreg32(regval, INTC_EN(irq));
+      leave_critical_section(flags);
+      putreg32(bit, NVIC_IRQ_CLEAR(irq));
+    }
+  else
+    {
+      if (excinfo(irq, ®addr, &bit) == OK)
+        {
+          regval  = getreg32(regaddr);
+          regval &= ~bit;
+          putreg32(regval, regaddr);
+        }
+    }
+
+  cxd56_dumpnvic("disable", irq);
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ *   Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+  uintptr_t regaddr;
+  uint32_t regval;
+  uint32_t bit;
+
+  if (irq >= CXD56_IRQ_EXTINT)
+    {
+      irqstate_t flags = enter_critical_section();
+      irq -= CXD56_IRQ_EXTINT;
+      bit  = 1 << (irq & 0x1f);
+
+      regval  = getreg32(INTC_EN(irq));
+      regval |= bit;
+      putreg32(regval, INTC_EN(irq));
+      leave_critical_section(flags);
+      putreg32(bit, NVIC_IRQ_ENABLE(irq));
+    }
+  else
+    {
+      if (excinfo(irq, ®addr, &bit) == OK)
+        {
+          regval  = getreg32(regaddr);
+          regval |= bit;
+          putreg32(regval, regaddr);
+        }
+    }
+
+  cxd56_dumpnvic("enable", irq);
+}
+
+/****************************************************************************
+ * Name: up_ack_irq
+ *
+ * Description:
+ *   Acknowledge the IRQ
+ *
+ ****************************************************************************/
+
+void up_ack_irq(int irq)
+{
+  /* Check for external interrupt */
+
+  if (irq >= CXD56_IRQ_EXTINT)
+    {
+      irq -= CXD56_IRQ_EXTINT;
+      putreg32(1 << (irq & 0x1f), NVIC_IRQ_CLRPEND(irq));
+    }
+}
+
+/****************************************************************************
+ * Name: up_prioritize_irq
+ *
+ * Description:
+ *   Set the priority of an IRQ.
+ *
+ *   Since this API is not supported on all architectures, it should be
+ *   avoided in common implementations where possible.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_IRQPRIO
+int up_prioritize_irq(int irq, int priority)
+{
+  uint32_t regaddr;
+  uint32_t regval;
+  int shift;
+
+  DEBUGASSERT(irq >= CXD56_IRQ_MEMFAULT && irq < NR_IRQS &&
+              (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
+
+  if (irq < CXD56_IRQ_EXTINT)
+    {
+      /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
+       * registers (0-3 are invalid)
+       */
+
+      regaddr = NVIC_SYSH_PRIORITY(irq);
+      irq -= 4;
+    }
+  else
+    {
+      /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
+
+      irq -= CXD56_IRQ_EXTINT;
+      regaddr = NVIC_IRQ_PRIORITY(irq);
+    }
+
+  regval  = getreg32(regaddr);
+  shift   = ((irq & 3) << 3);
+  regval &= ~(0xff << shift);
+  regval |= (priority << shift);
+  putreg32(regval, regaddr);
+
+  cxd56_dumpnvic("prioritize", irq);
+  return OK;
+}
+#endif
diff --git a/arch/arm/src/cxd56xx/cxd56_irq.h b/arch/arm/src/cxd56xx/cxd56_irq.h
new file mode 100644
index 00000000000..568e5d1963e
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_irq.h
@@ -0,0 +1,84 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_irq.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ *   Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_IRQ_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_IRQ_H */
diff --git a/arch/arm/src/cxd56xx/cxd56_pinconfig.c b/arch/arm/src/cxd56xx/cxd56_pinconfig.c
new file mode 100644
index 00000000000..5b9d4de9c68
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_pinconfig.c
@@ -0,0 +1,462 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_pinconfig.c
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "chip.h"
+#include "up_arch.h"
+
+#include "cxd56_pinconfig.h"
+#include "hardware/cxd5602_topreg.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define GET_IOVAL_MASK(p) \
+  ((p) & (PINCONF_DRIVE_MASK | PINCONF_PULL_MASK | PINCONF_IN_EN_MASK))
+
+/* IOCSYS_IOMD0 */
+
+#define GROUP_I2C4          (0)
+#define GROUP_PMIC_INT      (2)
+#define GROUP_RTC_IRQ_OUT   (4)
+#define GROUP_AP_CLK        (6)
+#define GROUP_GNSS_1PPS_OUT (8)
+#define GROUP_SPI0A         (12)
+#define GROUP_SPI0B         (14)
+#define GROUP_SPI1A         (16)
+#define GROUP_SPI1B         (18)
+#define GROUP_SPI2A         (20)
+#define GROUP_SPI2B         (22)
+#define GROUP_HIFIRQ        (24)
+#define GROUP_HIFEXT        (26)
+
+/* IOCSYS_IOMD1 */
+
+#define GROUP_SEN_IRQ_IN    (8)
+#define GROUP_SPI3_CS0_X    (10)
+#define GROUP_SPI3_CS1_X    (12)
+#define GROUP_SPI3_CS2_X    (14)
+#define GROUP_SPI3          (16)
+#define GROUP_I2C0          (18)
+#define GROUP_PWMA          (20)
+#define GROUP_PWMB          (22)
+
+/* IOCAPP_IOMD */
+
+#define GROUP_IS            (0)
+#define GROUP_UART2         (2)
+#define GROUP_SPI4          (4)
+#define GROUP_EMMCA         (6)
+#define GROUP_EMMCB         (8)
+#define GROUP_SDIOA         (10)
+#define GROUP_SDIOB         (12)
+#define GROUP_SDIOC         (14)
+#define GROUP_SDIOD         (16)
+#define GROUP_I2S0          (18)
+#define GROUP_I2S1          (20)
+#define GROUP_MCLK          (22)
+#define GROUP_PDM           (24)
+#define GROUP_USBVBUS       (26)
+
+/* DBG_HOSTIF_SEL */
+
+#define LATCH_OFF           (1ul << 0)
+#define LATCH_OFF_MASK      (1ul << 0)
+
+/* SYSTEM_CONFIG */
+
+#define SYSTEM_CONFIG_I2C   (0)
+#define SYSTEM_CONFIG_UART  (1)
+#define SYSTEM_CONFIG_SPI   (2)
+#define SYSTEM_CONFIG_MON   (3)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static int get_mode_regaddr(uint32_t pin, uint32_t *addr, uint32_t *shift)
+{
+  DEBUGASSERT(addr && shift);
+
+  if ((pin < PIN_I2C4_BCK) || (PIN_USB_VBUSINT < pin))
+    return -EINVAL;
+
+  if (pin <= PIN_HIF_GPIO0)
+    {
+      if (pin <= PIN_I2C4_BDT)
+        {
+          *shift = GROUP_I2C4;
+        }
+      else if (pin <= PIN_PMIC_INT)
+        {
+          *shift = GROUP_PMIC_INT;
+        }
+      else if (pin <= PIN_RTC_IRQ_OUT)
+        {
+          *shift = GROUP_RTC_IRQ_OUT;
+        }
+      else if (pin <= PIN_AP_CLK)
+        {
+          *shift = GROUP_AP_CLK;
+        }
+      else if (pin <= PIN_GNSS_1PPS_OUT)
+        {
+          *shift = GROUP_GNSS_1PPS_OUT;
+        }
+      else if (pin <= PIN_SPI0_SCK)
+        {
+          *shift = GROUP_SPI0A;
+        }
+      else if (pin <= PIN_SPI0_MISO)
+        {
+          *shift = GROUP_SPI0B;
+        }
+      else if (pin <= PIN_SPI1_IO1)
+        {
+          *shift = GROUP_SPI1A;
+        }
+      else if (pin <= PIN_SPI1_IO3)
+        {
+          *shift = GROUP_SPI1B;
+        }
+      else if (pin <= PIN_SPI2_SCK)
+        {
+          *shift = GROUP_SPI2A;
+        }
+      else if (pin <= PIN_SPI2_MISO)
+        {
+          *shift = GROUP_SPI2B;
+        }
+      else if (pin <= PIN_HIF_IRQ_OUT)
+        {
+          *shift = GROUP_HIFIRQ;
+        }
+      else
+        {
+          *shift = GROUP_HIFEXT;
+        }
+      *addr = CXD56_TOPREG_IOCSYS_IOMD0;
+    }
+  else if (pin <= PIN_PWM3)
+    {
+      if (pin <= PIN_SEN_IRQ_IN)
+        {
+          *shift = GROUP_SEN_IRQ_IN;
+        }
+      else if (pin <= PIN_SPI3_CS0_X)
+        {
+          *shift = GROUP_SPI3_CS0_X;
+        }
+      else if (pin <= PIN_SPI3_CS1_X)
+        {
+          *shift = GROUP_SPI3_CS1_X;
+        }
+      else if (pin <= PIN_SPI3_CS2_X)
+        {
+          *shift = GROUP_SPI3_CS2_X;
+        }
+      else if (pin <= PIN_SPI3_MISO)
+        {
+          *shift = GROUP_SPI3;
+        }
+      else if (pin <= PIN_I2C0_BDT)
+        {
+          *shift = GROUP_I2C0;
+        }
+      else if (pin <= PIN_PWM1)
+        {
+          *shift = GROUP_PWMA;
+        }
+      else
+        {
+          *shift = GROUP_PWMB;
+        }
+      *addr = CXD56_TOPREG_IOCSYS_IOMD1;
+    }
+  else
+    {
+      if (pin <= PIN_IS_DATA7)
+        {
+          *shift = GROUP_IS;
+        }
+      else if (pin <= PIN_UART2_RTS)
+        {
+          *shift = GROUP_UART2;
+        }
+      else if (pin <= PIN_SPI4_MISO)
+        {
+          *shift = GROUP_SPI4;
+        }
+      else if (pin <= PIN_EMMC_DATA1)
+        {
+          *shift = GROUP_EMMCA;
+        }
+      else if (pin <= PIN_EMMC_DATA3)
+        {
+          *shift = GROUP_EMMCB;
+        }
+      else if (pin <= PIN_SDIO_DATA3)
+        {
+          *shift = GROUP_SDIOA;
+        }
+      else if (pin <= PIN_SDIO_WP)
+        {
+          *shift = GROUP_SDIOB;
+        }
+      else if (pin <= PIN_SDIO_DIR1_3)
+        {
+          *shift = GROUP_SDIOC;
+        }
+      else if (pin <= PIN_SDIO_CLKI)
+        {
+          *shift = GROUP_SDIOD;
+        }
+      else if (pin <= PIN_I2S0_DATA_OUT)
+        {
+          *shift = GROUP_I2S0;
+        }
+      else if (pin <= PIN_I2S1_DATA_OUT)
+        {
+          *shift = GROUP_I2S1;
+        }
+      else if (pin <= PIN_MCLK)
+        {
+          *shift = GROUP_MCLK;
+        }
+      else if (pin <= PIN_PDM_OUT)
+        {
+          *shift = GROUP_PDM;
+        }
+      else
+        {
+          *shift = GROUP_USBVBUS;
+        }
+      *addr = CXD56_TOPREG_IOCAPP_IOMD;
+    }
+
+  return 0;
+}
+
+static void set_i2s_output_config(uint32_t pin, uint32_t mode, bool is_slave)
+{
+  uint32_t mask =
+    (PIN_I2S0_BCK == pin) ? (I2S0_BCK | I2S0_LRCK) : (I2S1_BCK | I2S1_LRCK);
+
+  if (is_slave)
+    {
+      modifyreg32(CXD56_TOPREG_IOOEN_APP, 0, mask);
+    }
+  else
+    {
+      modifyreg32(CXD56_TOPREG_IOOEN_APP, mask, 0);
+    }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_pin_config
+ *
+ * Description:
+ *   Configure a pin based on bit-encoded description of the pin.
+ *
+ * Input Value:
+ *   32-bit encoded value describing the pin.
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int cxd56_pin_config(uint32_t pinconf)
+{
+  return cxd56_pin_configs(&pinconf, 1);
+}
+
+/****************************************************************************
+ * Name: cxd56_pin_configs
+ *
+ * Description:
+ *   Configure multiple pins based on bit-encoded description of the pin.
+ *
+ * Input Value:
+ *   pinconfs[] - Array of 32-bit encoded value describing the pin.
+ *   n - The number of elements in the array.
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int cxd56_pin_configs(uint32_t pinconfs[], size_t n)
+{
+  int ret = 0;
+  int i;
+  uint32_t pin;
+  uint32_t mode;
+  uint32_t ioreg;
+  uint32_t ioval;
+  uint32_t modereg;
+  uint32_t shift;
+  uint32_t oldreg = 0;
+  uint32_t oldshift = 0;
+  uint32_t latch_endpin = PIN_SPI2_SCK;
+
+  if (SYSTEM_CONFIG_SPI == getreg8(CXD56_TOPREG_SYSTEM_CONFIG))
+    {
+      latch_endpin = PIN_SPI2_MISO;
+    }
+
+  for (i = 0; i < n; i++)
+    {
+      pin = PINCONF_GET_PIN(pinconfs[i]);
+      mode = PINCONF_GET_MODE(pinconfs[i]);
+      ioval = GET_IOVAL_MASK(pinconfs[i]);
+
+      DEBUGASSERT((PIN_RTC_CLK_IN <= pin) && (pin <= PIN_USB_VBUSINT));
+      DEBUGASSERT((pin <= PIN_GNSS_1PPS_OUT) || (PIN_SPI0_CS_X <= pin));
+      DEBUGASSERT((pin <= PIN_HIF_GPIO0) || (PIN_SEN_IRQ_IN <= pin));
+      DEBUGASSERT((pin <= PIN_PWM3) || (PIN_IS_CLK <= pin));
+
+      /* Set HostIF latch off */
+
+      if (((PIN_SPI2_CS_X <= pin) && (pin <= latch_endpin)) &&
+          (PINCONF_MODE0 == mode))
+        {
+          modifyreg32(CXD56_TOPREG_DBG_HOSTIF_SEL, LATCH_OFF_MASK, LATCH_OFF);
+        }
+
+      /* Set IO cell register */
+
+      ioreg = CXD56_TOPREG_IO_RTC_CLK_IN + (pin * 4);
+      putreg32(ioval, ioreg);
+
+      /* Set i2s output register */
+
+      if (((PIN_I2S0_BCK == pin) || (PIN_I2S1_BCK == pin)) &&
+          (PINCONF_MODE1 == mode))
+        {
+          set_i2s_output_config(pin, mode, PINCONF_INPUT_ENABLED(pinconfs[i]));
+        }
+
+      ret = get_mode_regaddr(pin, &modereg, &shift);
+
+      if ((!ret) && ((oldreg != modereg) || (oldshift != shift)))
+        {
+          oldreg = modereg;
+          oldshift = shift;
+
+          /* Set alternative mode register */
+
+          modifyreg32(modereg, (0x3 << shift), (mode << shift));
+        }
+    }
+  return 0;
+}
+
+/********************************************************************************************
+ * Name: cxd56_pin_status
+ *
+ * Description:
+ *   Get a pin status.
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ********************************************************************************************/
+
+int cxd56_pin_status(uint32_t pin, cxd56_pin_status_t *stat)
+{
+  int ret = 0;
+  uint32_t ioreg;
+  uint32_t ioval;
+  uint32_t modereg;
+  uint32_t modeval;
+  uint32_t shift;
+
+  DEBUGASSERT(stat);
+
+  stat->mode     = -1;
+  stat->input_en = -1;
+  stat->drive    = -1;
+  stat->pull     = -1;
+
+  if (((PIN_GNSS_1PPS_OUT < pin) && (pin < PIN_SPI0_CS_X)) ||
+      ((PIN_HIF_GPIO0 < pin) && (pin < PIN_SEN_IRQ_IN)) ||
+      ((PIN_PWM3 < pin) && (pin < PIN_IS_CLK)) || (PIN_USB_VBUSINT < pin))
+    {
+      return -EINVAL;
+    }
+
+  ioreg = CXD56_TOPREG_IO_RTC_CLK_IN + (pin * 4);
+  ioval = getreg32(ioreg);
+
+  ret = get_mode_regaddr(pin, &modereg, &shift);
+
+  if (!ret)
+    {
+      modeval = getreg32(modereg);
+      modeval = (modeval >> shift) & 0x3;
+
+      stat->mode = modeval;
+      stat->input_en = (ioval & PINCONF_IN_EN_MASK);
+      stat->drive = (ioval & PINCONF_DRIVE_MASK);
+      stat->pull = (ioval & PINCONF_PULL_MASK);
+    }
+
+  return ret;
+}
diff --git a/arch/arm/src/cxd56xx/cxd56_pinconfig.h b/arch/arm/src/cxd56xx/cxd56_pinconfig.h
new file mode 100644
index 00000000000..27c6c972408
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_pinconfig.h
@@ -0,0 +1,226 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_pinconfig.h
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_PINCONFIG_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56_PINCONFIG_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include "hardware/cxd5602_pinconfig.h"
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+/* 32-bit encoded pinconf value
+ *
+ * 3322 2222 2222 1111 1111 1100 0000 0000
+ * 1098 7654 3210 9876 5432 1098 7654 3210
+ * ---- ---- ---- ---- ---- ---- ---- ----
+ * PPPP PPP. .... .... .... .... .... .... Pin number
+ * .... ...D .... .... .... .... .... .... Drive strength
+ * .... .... .... ...U .... ...U .... .... Pull-up/down/off
+ * .... .... .... .... .... .... .... ...I Input enable
+ * .... .... .... .... .... .... .... .MM. Alternate mode number
+ */
+
+/* Pin number Definitions */
+
+#define PINCONF_PIN_SHIFT       (25)
+#define PINCONF_PIN_MASK        (0x7Fu << PINCONF_PIN_SHIFT)
+#define PINCONF_GET_PIN(p)      (((p) & PINCONF_PIN_MASK) >> PINCONF_PIN_SHIFT)
+#define PINCONF_SET_PIN(p)      (((p) << PINCONF_PIN_SHIFT) & PINCONF_PIN_MASK)
+
+/* Drive strength Definitions */
+
+#define PINCONF_DRIVE_SHIFT     (24)
+#define PINCONF_DRIVE_MASK      (1u << PINCONF_DRIVE_SHIFT)
+
+#define PINCONF_DRIVE_NORMAL    (1u << PINCONF_DRIVE_SHIFT) /* 2mA */
+#define PINCONF_DRIVE_HIGH      (0u << PINCONF_DRIVE_SHIFT) /* 4mA */
+
+#define PINCONF_IS_DRIVE_NORM(p) (((p) & PINCONF_DRIVE_MASK) == PINCONF_DRIVE_NORMAL)
+#define PINCONF_IS_DRIVE_HIGH(p) (((p) & PINCONF_DRIVE_MASK) == PINCONF_DRIVE_HIGH)
+
+/* Pull-up/down/off Definitions */
+
+#define PINCONF_PULL_MASK       ((1u << 16) | (1u << 8))
+
+#define PINCONF_FLOAT           ((1u << 16) | (1u << 8))
+#define PINCONF_PULLUP          ((1u << 16) | (0u << 8))
+#define PINCONF_PULLDOWN        ((0u << 16) | (1u << 8))
+#define PINCONF_BUSKEEPER       ((0u << 16) | (0u << 8))
+
+#define PINCONF_IS_FLOAT(p)     (((p) & PINCONF_PULL_MASK) == PINCONF_FLOAT)
+#define PINCONF_IS_PULLUP(p)    (((p) & PINCONF_PULL_MASK) == PINCONF_PULLUP)
+#define PINCONF_IS_PULLDOWN(p)  (((p) & PINCONF_PULL_MASK) == PINCONF_PULLDOWN)
+#define PINCONF_IS_BUSKEEPER(p) (((p) & PINCONF_PULL_MASK) == PINCONF_BUSKEEPER)
+
+/* Input enable Definitions */
+
+#define PINCONF_IN_EN_SHIFT     (0)
+#define PINCONF_IN_EN_MASK      (1u << PINCONF_IN_EN_SHIFT)
+
+#define PINCONF_INPUT_ENABLE    (1u << PINCONF_IN_EN_SHIFT)
+#define PINCONF_INPUT_DISABLE   (0u << PINCONF_IN_EN_SHIFT)
+
+#define PINCONF_INPUT_ENABLED(p) (((p) & PINCONF_IN_EN_MASK) == PINCONF_INPUT_ENABLE)
+
+/* Alternate mode number Definitions */
+
+#define PINCONF_MODE_SHIFT      (1)
+#define PINCONF_MODE_MASK       (3u << PINCONF_MODE_SHIFT)
+
+#define PINCONF_GET_MODE(p)     (((p) & PINCONF_MODE_MASK) >> PINCONF_MODE_SHIFT)
+#define PINCONF_SET_MODE(p)     (((p) << PINCONF_MODE_SHIFT) & PINCONF_MODE_MASK)
+
+#define PINCONF_MODE0           (0) /* GPIO */
+#define PINCONF_MODE1           (1) /* Function */
+#define PINCONF_MODE2           (2) /* Function */
+#define PINCONF_MODE3           (3) /* Function */
+
+/* Set pinconf macro Definitions */
+
+#define PINCONF_SET(pin, mode, input, drive, pull) \
+  ( \
+    (PINCONF_SET_PIN(pin)) | \
+    (PINCONF_SET_MODE(mode)) | \
+    (input) | (drive) | (pull) \
+    )
+
+#define PINCONF_SET_GPIO(pin, input) \
+  PINCONF_SET((pin), PINCONF_MODE0, (input), PINCONF_DRIVE_NORMAL, PINCONF_FLOAT)
+
+#define CXD56_PIN_CONFIGS(pin) do { \
+  uint32_t p[] = pin; \
+  cxd56_pin_configs((p), sizeof(p) / sizeof((p)[0])); \
+} while (0)
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+struct cxd56_pin_status_s
+{
+  uint32_t mode;     /* alternate pin function mode */
+  uint32_t input_en; /* input enable or disable */
+  uint32_t drive;    /* strength of drive current */
+  uint32_t pull;     /* internal pull-up, pull-down, floating or buskeeper */
+};
+
+typedef struct cxd56_pin_status_s cxd56_pin_status_t;
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Name: cxd56_pin_config
+ *
+ * Description:
+ *   Configure a pin based on bit-encoded description of the pin.
+ *
+ * Input Value:
+ *   32-bit encoded value describing the pin.
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ********************************************************************************************/
+
+int cxd56_pin_config(uint32_t pinconf);
+
+/********************************************************************************************
+ * Name: cxd56_pin_configs
+ *
+ * Description:
+ *   Configure multiple pins based on bit-encoded description of the pin.
+ *
+ * Input Value:
+ *   Array of 32-bit encoded value describing the pin.
+ *   Number of elements in the array.
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ********************************************************************************************/
+
+int cxd56_pin_configs(uint32_t pinconfs[], size_t n);
+
+/********************************************************************************************
+ * Name: cxd56_pin_status
+ *
+ * Description:
+ *   Get a pin status.
+ *
+ * Returned Value:
+ *   OK on success; A negated errno value on failure.
+ *
+ ********************************************************************************************/
+
+int cxd56_pin_status(uint32_t pin, cxd56_pin_status_t *stat);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_PINCONFIG_H */
diff --git a/arch/arm/src/cxd56xx/cxd56_pmic.c b/arch/arm/src/cxd56xx/cxd56_pmic.c
new file mode 100644
index 00000000000..67690811596
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_pmic.c
@@ -0,0 +1,1467 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_pmic.c
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include "cxd56_pmic.h"
+
+#ifdef CONFIG_CXD56_PMIC
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+enum pmic_cmd_type_e
+{
+  /* basic */
+  PMIC_CMD_READ = 0x00,
+  PMIC_CMD_WRITE,
+  PMIC_CMD_GPO,
+  PMIC_CMD_LOADSW,
+  PMIC_CMD_DDCLDO,
+  PMIC_CMD_INTSTATUS,
+  PMIC_CMD_SETPREVSYS,
+  PMIC_CMD_GETPREVSYS,
+  PMIC_CMD_SETVSYS,
+  PMIC_CMD_GETVSYS,
+  /* charger */
+  PMIC_CMD_GAUGE = 0x10,
+  PMIC_CMD_GET_USB_PORT_TYPE,
+  PMIC_CMD_GET_CHG_STATE,
+  PMIC_CMD_SET_CHG_VOLTAGE,
+  PMIC_CMD_GET_CHG_VOLTAGE,
+  PMIC_CMD_SET_CHG_CURRENT,
+  PMIC_CMD_GET_CHG_CURRENT,
+  PMIC_CMD_SET_CHG_TEMPERATURE_MODE,
+  PMIC_CMD_GET_CHG_TEMPERATURE_MODE,
+  PMIC_CMD_SET_RECHG_VOLTAGE,
+  PMIC_CMD_GET_RECHG_VOLTAGE,
+  PMIC_CMD_PRESET_CHG_CURRENT,
+  PMIC_CMD_CHG_START,
+  PMIC_CMD_CHG_STOP,
+  PMIC_CMD_CHG_PAUSE,
+  PMIC_CMD_CHG_ENABLE,
+  PMIC_CMD_CHG_DISABLE,
+  /* power monitor */
+  PMIC_CMD_POWER_MONITOR_ENABLE = 0x30,
+  PMIC_CMD_POWER_MONITOR_STATUS,
+  PMIC_CMD_POWER_MONITOR_SET,
+  PMIC_CMD_POWER_MONITOR_GET,
+  PMIC_CMD_AFE,
+  PMIC_CMD_SET_CHG_IFIN,
+  PMIC_CMD_GET_CHG_IFIN,
+  PMIC_CMD_SET_CHG_TEMPERATURE_TABLE,
+  PMIC_CMD_GET_CHG_TEMPERATURE_TABLE,
+};
+
+/* Register CNT_USB2 [1:0] USB_CUR_LIM constants */
+
+#define PMIC_CUR_LIM_2_5mA  0
+#define PMIC_CUR_LIM_100mA  1
+#define PMIC_CUR_LIM_500mA  2
+
+/* Register CNT_CHG1 [6:5] VO_CHG_DET4 constants */
+
+#define PMIC_CHG_DET_MINUS400  0
+#define PMIC_CHG_DET_MINUS350  1
+#define PMIC_CHG_DET_MINUS300  2
+#define PMIC_CHG_DET_MINUS250  3
+
+/* Register CNT_CHG2 [7:5] SET_CHG_IFIN constants */
+
+#define PMIC_CHG_IFIN_50   0
+#define PMIC_CHG_IFIN_40   1
+#define PMIC_CHG_IFIN_30   2
+#define PMIC_CHG_IFIN_20   3
+#define PMIC_CHG_IFIN_10   4
+
+/* RTC Register */
+
+#define PMIC_REG_RTC                   (0x40)
+#define PMIC_REG_RRQ_TIME              (0x46)
+#define PMIC_REG_RTC_ALM               (0x58)
+#define PMIC_REG_LRQ_ALM               (0x5E)
+#define PMIC_REG_RRQ_LRQ_STATUS        (0x60)
+
+/* Register RRQ_LRQ_STATUS */
+
+#define RRQ_TIME_STATE  (1 << 4)
+#define LRQ_TIME_STATE  (1 << 3)
+#define LRQ_OFST_STATE  (1 << 2)
+#define LRQ_WU_STATE    (1 << 1)
+#define LRQ_ALM_STATE   (1 << 0)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+/* FarAPI interface structures */
+
+struct pmic_afe_s
+{
+  int voltage;
+  int current;
+  int temperature;
+};
+
+struct pmic_temp_mode_s
+{
+  int low;
+  int high;
+};
+
+extern int PM_PmicControl(int cmd, void *arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_CXD56_PMIC_INT
+static pmic_notify_t g_pmic_notify[PMIC_NOTIFY_MAX];
+static struct work_s g_irqwork;
+#endif /* CONFIG_CXD56_PMIC_INT */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_CXD56_PMIC_INT
+/************************************************************************************
+ * Name: is_notify_registerd
+ *
+ * Description:
+ *   Return whether any notification is registered or not
+ *
+ ************************************************************************************/
+
+static bool is_notify_registerd(void)
+{
+  int i;
+
+  for (i = PMIC_NOTIFY_ALARM; i < PMIC_NOTIFY_MAX; i++)
+    {
+      if (g_pmic_notify[i])
+        {
+          return true;
+        }
+    }
+  return false;
+}
+
+/************************************************************************************
+ * Name: pmic_int_worker
+ *
+ * Description:
+ *   Work queue for pmic interrupt
+ *
+ ************************************************************************************/
+
+static void pmic_int_worker(void *arg)
+{
+  int        i;
+  uint8_t    stat;
+  irqstate_t flags;
+  int        irq = CXD56_IRQ_PMIC;
+
+  /* Get interrupt cause with clear and call the registered callback */
+
+  cxd56_pmic_get_interrupt_status(&stat);
+
+  for (i = PMIC_NOTIFY_ALARM; i < PMIC_NOTIFY_MAX; i++)
+    {
+      if ((stat & (1 << i)) && g_pmic_notify[i])
+        {
+          g_pmic_notify[i](arg);
+        }
+    }
+
+  /* Prevent from the race condition with up_pmic_set_notify() */
+
+  flags = enter_critical_section();
+
+  /* After processing of each notification, enable the pmic interrupt again */
+
+  if (is_notify_registerd())
+    {
+      up_enable_irq(irq);
+    }
+
+  leave_critical_section(flags);
+}
+
+/************************************************************************************
+ * Name: pmic_int_handler
+ *
+ * Description:
+ *   Interrupt handler for pmic interrupt
+ *
+ ************************************************************************************/
+
+static int pmic_int_handler(int irq, void *context, void *arg)
+{
+  int ret;
+
+  /* Schedule the callback to occur on the low-priority worker thread */
+
+  DEBUGASSERT(work_available(&g_irqwork));
+  ret = work_queue(LPWORK, &g_irqwork, pmic_int_worker, NULL, 0);
+  if (ret < 0)
+    {
+      logerr("ERROR: work_queue failed: %d\n", ret);
+    }
+
+  /* Disable any further pmic interrupts */
+
+  up_disable_irq(irq);
+
+  return OK;
+}
+#endif /* CONFIG_CXD56_PMIC_INT */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_pmic_get_interrupt_status
+ *
+ * Description:
+ *   Get Raw Interrupt Status register. And furthermore, if status is set,
+ *   then clear the interrupt. Register's decription is below:
+ *
+ *     7   6   5   4    3     2     1     0
+ *   +---------------+-----+-----+-----+-----+
+ *   | x   x   x   x |VSYS |WKUPL|WKUPS|ALARM| target of status
+ *   +---------------+-----+-----+-----+-----+
+ *
+ * Input Parameter:
+ *   status - a pointer to the polled value of interrupt status
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *   status - return the value of interrupt status register
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_get_interrupt_status(uint8_t *status)
+{
+  return PM_PmicControl(PMIC_CMD_INTSTATUS, status);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_set_gpo_reg
+ *
+ * Description:
+ *   Set GPO register. Register's decription is below:
+ *
+ *     7   6   5   4   3   2   1   0
+ *   +---+---+---+---+---+---+---+---+
+ *   |CH3|CH2|CH1|CH0|CH3|CH2|CH1|CH0| target of setbit0/clrbit0
+ *   +---+---+---+---+---+---+---+---+
+ *   +---+---+---+---+---+---+---+---+
+ *   |CH7|CH6|CH5|CH4|CH7|CH6|CH5|CH4| target of setbit1/clrbit1
+ *   +---+---+---+---+---+---+---+---+
+ *   |<- 0: Hi-Z   ->|<- 0: Low    ->|
+ *   |<- 1: Output ->|<- 1: High   ->|
+ *
+ * Input Parameter:
+ *   setbitX - set bit that 1 is set
+ *   clrbitX - clear bit that 1 is set
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *   setbitX - return the current value of register
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_set_gpo_reg(uint8_t *setbit0, uint8_t *clrbit0,
+                           uint8_t *setbit1, uint8_t *clrbit1)
+{
+  struct pmic_gpo_arg_s
+    {
+      uint8_t *setbit0;
+      uint8_t *clrbit0;
+      uint8_t *setbit1;
+      uint8_t *clrbit1;
+    }
+  arg =
+    {
+      .setbit0 = setbit0,
+      .clrbit0 = clrbit0,
+      .setbit1 = setbit1,
+      .clrbit1 = clrbit1,
+    };
+
+  return PM_PmicControl(PMIC_CMD_GPO, &arg);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_set_gpo
+ *
+ * Description:
+ *   Set High/Low to the specified GPO channel(s)
+ *
+ * Input Parameter:
+ *   chset - GPO Channel number(s)
+ *   value - true if output high, false if output low.
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_set_gpo(uint8_t chset, bool value)
+{
+  uint8_t setbit0 = 0;
+  uint8_t clrbit0 = 0;
+  uint8_t setbit1 = 0;
+  uint8_t clrbit1 = 0;
+  uint8_t set;
+
+  /* Set GPO0~3 */
+
+  set = chset & 0xf;
+  if (set)
+    {
+      if (value)
+        {
+          setbit0 = (set << 4) | set;
+        }
+      else
+        {
+          setbit0 = (set << 4);
+          clrbit0 = set;
+        }
+    }
+
+  /* Set GPO4~7 */
+
+  set = (chset >> 4) & 0xf;
+  if (set)
+    {
+      if (value)
+        {
+          setbit1 = (set << 4) | set;
+        }
+      else
+        {
+          setbit1 = (set << 4);
+          clrbit1 = set;
+        }
+    }
+
+  return cxd56_pmic_set_gpo_reg(&setbit0, &clrbit0, &setbit1, &clrbit1);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_set_gpo_hiz
+ *
+ * Description:
+ *   Set Hi-Z to the specified GPO channel(s)
+ *
+ * Input Parameter:
+ *   chset - GPO Channel number(s)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_set_gpo_hiz(uint8_t chset)
+{
+  uint8_t setbit0 = 0;
+  uint8_t clrbit0 = 0;
+  uint8_t setbit1 = 0;
+  uint8_t clrbit1 = 0;
+  uint8_t set;
+
+  /* Set GPO0~3 */
+
+  set = chset & 0xf;
+  if (set)
+    {
+      clrbit0 = (set << 4) | set;
+    }
+
+  /* Set GPO4~7 */
+
+  set = (chset >> 4) & 0xf;
+  if (set)
+    {
+      clrbit1 = (set << 4) | set;
+    }
+
+  return cxd56_pmic_set_gpo_reg(&setbit0, &clrbit0, &setbit1, &clrbit1);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_get_gpo
+ *
+ * Description:
+ *   Get the value from the specified GPO channel(s)
+ *
+ * Input Parameter:
+ *   chset : GPO Channel number(s)
+ *
+ * Returned Value:
+ *   Return true if all of the specified chset are high. Otherwise, return false
+ *
+ ****************************************************************************/
+
+bool cxd56_pmic_get_gpo(uint8_t chset)
+{
+  uint8_t setbit0 = 0;
+  uint8_t clrbit0 = 0;
+  uint8_t setbit1 = 0;
+  uint8_t clrbit1 = 0;
+  uint8_t set;
+
+  cxd56_pmic_set_gpo_reg(&setbit0, &clrbit0, &setbit1, &clrbit1);
+
+  set = ((setbit1 & 0xf) << 4) | (setbit0 & 0xf);
+
+  /* If all of the specified chset is high, return true */
+
+  if ((set & chset) == chset)
+    {
+      return true;
+    }
+  return false;
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_set_loadswitch_reg
+ *
+ * Description:
+ *   Set LoadSwitch register. Register's decription is below:
+ *
+ *     7   6   5   4   3   2   1   0
+ *   +---+---+---+---+---+---+---+---+
+ *   | - | - | - |CH4|CH3|CH2| 1 | 1 | target of setbit/clrbit
+ *   +---+---+---+---+---+---+---+---+
+ *               |<- 0: Off->|
+ *               |<- 1: On ->|
+ *
+ * Input Parameter:
+ *   setbit - set bit that 1 is set
+ *   clrbit - clear bit that 1 is set
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *   setbit - return the current value of register
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_set_loadswitch_reg(uint8_t *setbit, uint8_t *clrbit)
+{
+  struct pmic_loadswitch_arg_s
+    {
+      uint8_t *setbit;
+      uint8_t *clrbit;
+    }
+  arg =
+    {
+      .setbit = setbit,
+      .clrbit = clrbit,
+    };
+
+  return PM_PmicControl(PMIC_CMD_LOADSW, &arg);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_set_loadswitch
+ *
+ * Description:
+ *   Set On/Off to the specified LoadSwitch channel(s)
+ *
+ * Input Parameter:
+ *   chset - LoadSwitch Channel number(s)
+ *   value - true if set on, false if set off.
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_set_loadswitch(uint8_t chset, bool value)
+{
+  uint8_t setbit = 0;
+  uint8_t clrbit = 0;
+
+  if (value)
+    {
+      setbit = chset;
+    }
+  else
+    {
+      clrbit = chset;
+    }
+  return cxd56_pmic_set_loadswitch_reg(&setbit, &clrbit);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_get_loadswitch
+ *
+ * Description:
+ *   Get the value from the specified LoadSwitch channel(s)
+ *
+ * Input Parameter:
+ *   chset - LoadSwitch Channel number(s)
+ *
+ * Returned Value:
+ *   Return true if all of the specified chset are on. Otherwise, return false
+ *
+ ****************************************************************************/
+
+bool cxd56_pmic_get_loadswitch(uint8_t chset)
+{
+  uint8_t setbit = 0;
+  uint8_t clrbit = 0;
+
+  cxd56_pmic_set_loadswitch_reg(&setbit, &clrbit);
+
+  return ((setbit & chset) == chset);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_set_ddc_ldo_reg
+ *
+ * Description:
+ *   Set DDC/LDO register. Register's decription is below:
+ *
+ *      7    6    5    4    3    2    1    0
+ *   +----+----+----+----+----+----+----+----+
+ *   |    |    |LDO |DDC |LDO |DDC |LDO |DDC | target of setbit/clrbit
+ *   | -  | -  |PERI|CORE|ANA |ANA |EMMC|IO  |
+ *   +----+----+----+----+----+----+----+----+
+ *             |<-  0: Off                 ->|
+ *             |<-  1: On                  ->|
+ *
+ * Input Parameter:
+ *   setbit - set bit that 1 is set
+ *   clrbit - clear bit that 1 is set
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *   setbit - return the current value of register
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_set_ddc_ldo_reg(uint8_t *setbit, uint8_t *clrbit)
+{
+  struct pmic_ddc_ldo_arg_s
+    {
+      uint8_t *setbit;
+      uint8_t *clrbit;
+    }
+  arg =
+    {
+      .setbit = setbit,
+      .clrbit = clrbit,
+    };
+
+  return PM_PmicControl(PMIC_CMD_DDCLDO, &arg);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_set_ddc_ldo
+ *
+ * Description:
+ *   Set On/Off to the specified DDC/LDO channel(s)
+ *
+ * Input Parameter:
+ *   chset - DDC/LO Channel number(s)
+ *   value - true if set on, false if set off.
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_set_ddc_ldo(uint8_t chset, bool value)
+{
+  uint8_t setbit = 0;
+  uint8_t clrbit = 0;
+
+  if (value)
+    {
+      setbit = chset;
+    }
+  else
+    {
+      clrbit = chset;
+    }
+  return cxd56_pmic_set_ddc_ldo_reg(&setbit, &clrbit);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_get_ddc_ldo
+ *
+ * Description:
+ *   Get the value from the specified DDC/LDO channel(s)
+ *
+ * Input Parameter:
+ *   chset - DDC/LDO Channel number(s)
+ *
+ * Returned Value:
+ *   Return true if all of the specified chset are on. Otherwise, return false
+ *
+ ****************************************************************************/
+
+bool cxd56_pmic_get_ddc_ldo(uint8_t chset)
+{
+  uint8_t setbit = 0;
+  uint8_t clrbit = 0;
+
+  cxd56_pmic_set_ddc_ldo_reg(&setbit, &clrbit);
+
+  return ((setbit & chset) == chset);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_get_rtc
+ *
+ * Description:
+ *   Get the RTC value from PMIC
+ *
+ * Input Parameter:
+ *   count - the pointer to the returned RTC counter value
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_get_rtc(uint64_t *count)
+{
+  int ret = 0;
+  uint8_t data;
+  uint8_t rtc[6];
+
+  if (!count) return -EINVAL;
+
+  data = 0x1;
+  ret = cxd56_pmic_write(PMIC_REG_RRQ_TIME, &data, sizeof(data));
+  if (ret) goto error;
+
+  do {
+    ret = cxd56_pmic_read(PMIC_REG_RRQ_LRQ_STATUS, &data, sizeof(data));
+    if (ret) goto error;
+  } while (!(RRQ_TIME_STATE & data));
+
+  ret = cxd56_pmic_read(PMIC_REG_RTC, rtc, sizeof(rtc));
+  if (ret) goto error;
+
+  *count =
+    (((uint64_t)((rtc[5] << 24) | (rtc[4] << 16) | (rtc[3] << 8) | rtc[2]) << 15) |
+     ((rtc[1] << 8) | rtc[0]));
+
+error:
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_get_gauge
+ *
+ * Description:
+ *   Get the set of values (voltage, current and temperature) from PMIC.
+ *
+ * Input Parameter:
+ *   gauge - Set of gauge related values
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_get_gauge(FAR struct pmic_gauge_s *gauge)
+{
+  return PM_PmicControl(PMIC_CMD_AFE, gauge);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_getlowervol
+ *
+ * Description:
+ *   Get lower limit of voltage for system to be running.
+ *
+ * Input Parameter:
+ *   voltage - Lower limit voltage (mV)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getlowervol(FAR int *vol)
+{
+  return PM_PmicControl(PMIC_CMD_GETVSYS, vol);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_getchargevol
+ *
+ * Description:
+ *   Get charge voltage
+ *
+ * Input Parameter:
+ *   voltage - Possible values are every 50 between 4000 to 4400 (mV)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getchargevol(FAR int *voltage)
+{
+  int val;
+  int ret;
+
+  ret = PM_PmicControl(PMIC_CMD_GET_CHG_VOLTAGE, &val);
+  if (ret)
+    {
+      return -EIO;
+    }
+
+  val &= 0xf;
+
+  /* Convert register value to actual voltage (mV) */
+
+  if (val <= 8)
+    {
+      *voltage = 4000 + (val * 50);
+    }
+  else
+    {
+      *voltage = 4200;
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_setchargevol
+ *
+ * Description:
+ *   Set charge voltage
+ *
+ * Input Parameter:
+ *   voltage - Avalable values are every 50 between 4000 to 4400 (mV)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_setchargevol(int voltage)
+{
+  int val;
+
+  /* Sanity check */
+
+  if (voltage < 4000 || voltage > 4400)
+    {
+      return -EINVAL;
+    }
+  if (voltage % 50)
+    {
+      return -EINVAL;
+    }
+
+  /* Register setting values are every 50mV between 4.0V to 4.4V */
+
+  val = (voltage - 4000) / 50;
+
+  return PM_PmicControl(PMIC_CMD_SET_CHG_VOLTAGE, (void *)val);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_getchargecurrent
+ *
+ * Description:
+ *   Get charge current value
+ *
+ * Input Parameter:
+ *   current - Possible values are 2, 100 and 500 (mA). However,
+ *             2 means 2.5 mA actually.
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getchargecurrent(FAR int *current)
+{
+  int val;
+  int ret;
+
+  ret = PM_PmicControl(PMIC_CMD_GET_CHG_CURRENT, &val);
+  if (ret)
+    {
+      return ret;
+    }
+
+  /* Convert register value to current */
+
+  switch (val & 0x3)
+    {
+      case PMIC_CUR_LIM_2_5mA:
+        *current = 2;
+        break;
+
+      case PMIC_CUR_LIM_100mA:
+        *current = 100;
+        break;
+
+      case PMIC_CUR_LIM_500mA:
+        *current = 500;
+        break;
+
+      default:
+        return -EFAULT;
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_setchargecurrent
+ *
+ * Description:
+ *   Set charge current value
+ *
+ * Input Parameter:
+ *   current - Available values are 2, 100 and 500 (mA). However, 2 means
+ *             2.5 mA actually.
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_setchargecurrent(int current)
+{
+  int val;
+
+  /* Replace current values for CNT_USB2 [1:0] USB_CUR_LIM */
+
+  switch (current)
+    {
+      case 2:
+        val = PMIC_CUR_LIM_2_5mA;
+        break;
+
+      case 100:
+        val = PMIC_CUR_LIM_100mA;
+        break;
+
+      case 500:
+        val = PMIC_CUR_LIM_500mA;
+        break;
+
+      default:
+        return -EFAULT;
+    }
+
+  return PM_PmicControl(PMIC_CMD_SET_CHG_CURRENT, (void *)val);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_getporttype
+ *
+ * Description:
+ *   Get USB port type
+ *
+ * Input Parameter:
+ *   porttype - PMIC_PORTTYPE_SDP or PMIC_PORTTYPE_DCPCDP
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getporttype(FAR int *porttype)
+{
+  return PM_PmicControl(PMIC_CMD_GET_USB_PORT_TYPE, porttype);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_getchargestate
+ *
+ * Description:
+ *   Read charging status
+ *
+ * Input Parameter:
+ *   state - Charging status (see PMIC_STAT_* definitions)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getchargestate(uint8_t *state)
+{
+  struct pmic_afe_s arg;
+  int val;
+  int ret;
+
+  /* Update charge state */
+
+  ret = PM_PmicControl(PMIC_CMD_AFE, &arg);
+  if (ret)
+    {
+      return ret;
+    }
+
+  /* Get actual charging state (CNT_USB1) */
+
+  ret = PM_PmicControl(PMIC_CMD_GET_CHG_STATE, &val);
+  *state = val & 0xff;
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_setrechargevol
+ *
+ * Description:
+ *   Set threshold voltage against full charge for automatic restart charging.
+ *
+ * Input Parameter:
+ *   mV - Available values are -400, -350, -300 and -250 (mV)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_setrechargevol(int mV)
+{
+  int val;
+
+  /* Convert voltage to register value */
+
+  switch (mV)
+    {
+      case -400:
+        val = PMIC_CHG_DET_MINUS400;
+        break;
+
+      case -350:
+        val = PMIC_CHG_DET_MINUS350;
+        break;
+
+      case -300:
+        val = PMIC_CHG_DET_MINUS300;
+        break;
+
+      case -250:
+        val = PMIC_CHG_DET_MINUS250;
+        break;
+
+      default:
+        return -EINVAL;
+    }
+
+  return PM_PmicControl(PMIC_CMD_SET_RECHG_VOLTAGE, (void *)val);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_getrechargevol
+ *
+ * Description:
+ *   Get threshold voltage against full charge for automatic restart charging.
+ *
+ * Input Parameter:
+ *   mV - Possible values are -400, -350, -300 and -250 (mV)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getrechargevol(FAR int *mV)
+{
+  int val;
+  int ret;
+
+  ret = PM_PmicControl(PMIC_CMD_GET_RECHG_VOLTAGE, &val);
+  if (ret)
+    {
+      return ret;
+    }
+
+  /* Convert regsiter value to voltage */
+
+  switch (val)
+    {
+      case PMIC_CHG_DET_MINUS400:
+        *mV = -400;
+        break;
+
+      case PMIC_CHG_DET_MINUS350:
+        *mV = -350;
+        break;
+
+      case PMIC_CHG_DET_MINUS300:
+        *mV = -300;
+        break;
+
+      case PMIC_CHG_DET_MINUS250:
+        *mV = -250;
+        break;
+
+      default:
+        return -EINVAL;
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_setchargecompcurrent
+ *
+ * Description:
+ *   Set current value setting for determine fully charged.
+ *
+ * Input Parameter:
+ *   current - Possible values are 50, 40, 30, 20 and 10 (mA)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_setchargecompcurrent(int current)
+{
+  int val;
+
+  /* Convert current (mA) to register value */
+
+  switch (current)
+    {
+      case 50:
+        val = PMIC_CHG_IFIN_50;
+        break;
+
+      case 40:
+        val = PMIC_CHG_IFIN_40;
+        break;
+
+      case 30:
+        val = PMIC_CHG_IFIN_30;
+        break;
+
+      case 20:
+        val = PMIC_CHG_IFIN_20;
+        break;
+
+      case 10:
+        val = PMIC_CHG_IFIN_10;
+        break;
+
+      default:
+        return -EINVAL;
+        break;
+    }
+
+  return PM_PmicControl(PMIC_CMD_SET_CHG_IFIN, (void*)val);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_getchargecompcurrent
+ *
+ * Description:
+ *   Get current value setting for determine fully charged.
+ *
+ * Input Parameter:
+ *   current - Available values are 50, 40, 30, 20 and 10 (mA)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getchargecompcurrent(FAR int *current)
+{
+  int val;
+  int ret;
+
+  ret = PM_PmicControl(PMIC_CMD_GET_CHG_IFIN, &val);
+  if (ret)
+    {
+      return ret;
+    }
+
+  /* Convert register value to current (mA) */
+
+  switch (val)
+    {
+      case PMIC_CHG_IFIN_50:
+        *current = 50;
+        break;
+
+      case PMIC_CHG_IFIN_40:
+        *current = 40;
+        break;
+
+      case PMIC_CHG_IFIN_30:
+        *current = 30;
+        break;
+
+      case PMIC_CHG_IFIN_20:
+        *current = 20;
+        break;
+
+      case PMIC_CHG_IFIN_10:
+        *current = 10;
+        break;
+
+      default:
+        *current = 0;
+        ret = -EFAULT;
+        break;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_gettemptable
+ *
+ * Description:
+ *   Get temperature detect resistance table
+ *
+ * Input Parameter:
+ *   table - Settings values for temperature detecting (see CXD5247GF
+ *           specification for more detail)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_gettemptable(FAR struct pmic_temp_table_s *table)
+{
+  /* SET_T60 (70h) - SET_T0_2 (78h) */
+
+  return PM_PmicControl(PMIC_CMD_GET_CHG_TEMPERATURE_TABLE, table);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_settemptable
+ *
+ * Description:
+ *   Set temperature detect resistance table
+ *
+ * Input Parameter:
+ *   table - Settings values for temperature detecting (see CXD5247GF
+ *           specification for more detail)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_settemptable(FAR struct pmic_temp_table_s *table)
+{
+  return PM_PmicControl(PMIC_CMD_SET_CHG_TEMPERATURE_TABLE, table);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_setchargemode
+ *
+ * Description:
+ *   Set charging mode in each low/high temperatures.
+ *   In lower than 10 degrees Celsius, charging mode will be changed on/off
+ *   and weak (half of charge current) according to setting.
+ *   In higher than 45 degrees Celsius, charging mode will be charged on/off
+ *   and weak (-0.15V from charge voltage) according to setting.
+ *
+ * Input Parameter:
+ *   low  - Charging mode in low temperature (see PMIC_CHGMODE_*)
+ *   high - Charging mode in high temperature (see PMIC_CHGMODE_*)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_setchargemode(int low, int high)
+{
+  struct pmic_temp_mode_s arg;
+
+  /* CNT_CHG3
+   * [3:2] SEL_CHG_THL:    <-> low
+   * [1:0] SEL_CHG_THH:    <-> high
+   */
+
+  /* Sanity check */
+
+  if (low == PMIC_CHGMODE_ON || low == PMIC_CHGMODE_OFF ||
+      low == PMIC_CHGMODE_WEAK)
+    {
+      arg.low = low;
+    }
+  else
+    {
+      return -EINVAL;
+    }
+
+  if (high == PMIC_CHGMODE_ON || high == PMIC_CHGMODE_OFF ||
+      high == PMIC_CHGMODE_WEAK)
+    {
+      arg.high = high;
+    }
+  else
+    {
+      return -EINVAL;
+    }
+
+  return PM_PmicControl(PMIC_CMD_SET_CHG_TEMPERATURE_MODE, &arg);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_getchargemode
+ *
+ * Description:
+ *   Get charging mode in each low/high temperatures.
+ *   In lower than 10 degrees Celsius, charging mode will be changed on/off
+ *   and weak (half of charge current) according to setting.
+ *   In higher than 45 degrees Celsius, charging mode will be charged on/off
+ *   and weak (-0.15V from charge voltage) according to setting.
+ *
+ * Input Parameter:
+ *   low  - Charging mode in low temperature (see PMIC_CHG_*)
+ *   high - Charging mode in high temperature (see PMIC_CHG_*)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getchargemode(FAR int *low, FAR int *high)
+{
+  struct pmic_temp_mode_s arg;
+  int ret;
+
+  ret = PM_PmicControl(PMIC_CMD_GET_CHG_TEMPERATURE_MODE, &arg);
+  if (ret)
+    {
+      return ret;
+    }
+
+  *low = arg.low;
+  *high = arg.high;
+
+  return OK;
+}
+
+#ifdef CONFIG_CXD56_PMIC_BATMONITOR
+/****************************************************************************
+ * Battery monitor for debug
+ ****************************************************************************/
+
+int cxd56_pmic_monitor_enable(FAR struct pmic_mon_s *ptr)
+{
+  return PM_PmicControl(PMIC_CMD_POWER_MONITOR_ENABLE, ptr);
+}
+
+int cxd56_pmic_monitor_status(FAR struct pmic_mon_status_s *ptr)
+{
+  return PM_PmicControl(PMIC_CMD_POWER_MONITOR_STATUS, ptr);
+}
+
+int cxd56_pmic_monitor_set(FAR struct pmic_mon_set_s *ptr)
+{
+  return PM_PmicControl(PMIC_CMD_POWER_MONITOR_SET, ptr);
+}
+
+int cxd56_pmic_monitor_get(FAR struct pmic_mon_log_s *ptr)
+{
+  return PM_PmicControl(PMIC_CMD_POWER_MONITOR_GET, ptr);
+}
+#endif
+
+#ifdef CONFIG_CXD56_PMIC_INT
+/****************************************************************************
+ * Name: up_pmic_set_notify
+ *
+ * Description:
+ *   Register a callback for pmic interrupt
+ *
+ * Input Parameter:
+ *   kind - A kind of pmic interrupt defined as pmic_notify_e
+ *   cb - A callback function for a kind of pmic interrupt
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int up_pmic_set_notify(int kind, pmic_notify_t cb)
+{
+  static int is_first = 1;
+  irqstate_t flags;
+  int        irq = CXD56_IRQ_PMIC;
+  int        delayed_work = 0;
+
+  if ((kind < PMIC_NOTIFY_ALARM) || (PMIC_NOTIFY_MAX <= kind))
+    {
+      return -EINVAL;
+    }
+
+  /* attach interrupt handler only for the first time */
+
+  if (is_first)
+    {
+      irq_attach(irq, pmic_int_handler, NULL);
+      is_first = 0;
+    }
+
+  flags = enter_critical_section();
+
+  g_pmic_notify[kind] = cb;
+
+  if (is_notify_registerd())
+    {
+      /* If up_enable_irq() is called when interrupt is pending,
+       * an assertion may occur because workqueue is not prepared yet.
+       * As the workaround, call worker directly and in the worker
+       * both interrupt clear and enable processing are performed.
+       */
+
+      delayed_work = 1;
+    }
+  else
+    {
+      up_disable_irq(irq);
+    }
+
+  leave_critical_section(flags);
+
+  if (delayed_work)
+    {
+      pmic_int_worker(NULL);
+    }
+
+  return 0;
+}
+#endif /* CONFIG_CXD56_PMIC_INT */
+
+/****************************************************************************
+ * Name: cxd56_pmic_read
+ *
+ * Description:
+ *   Read the value from the specified sub address
+ *
+ * Input Parameter:
+ *   addr - sub address
+ *   buf - pointer to read buffer
+ *   size - byte count of read
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_read(uint8_t addr, void *buf, uint32_t size)
+{
+  struct pmic_trans_arg_s
+    {
+      uint8_t  addr;
+      void     *buf;
+      uint32_t size;
+    }
+  arg =
+    {
+      .addr = addr,
+      .buf = buf,
+      .size = size,
+    };
+
+  return PM_PmicControl(PMIC_CMD_READ, &arg);
+}
+
+/****************************************************************************
+ * Name: cxd56_pmic_write
+ *
+ * Description:
+ *   Write the value to the specified sub address
+ *
+ * Input Parameter:
+ *   addr - sub address
+ *   buf - pointer to write buffer
+ *   size - byte count of write
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_write(uint8_t addr, void *buf, uint32_t size)
+{
+  struct pmic_trans_arg_s
+    {
+      uint8_t  addr;
+      void     *buf;
+      uint32_t size;
+    }
+  arg =
+    {
+      .addr = addr,
+      .buf = buf,
+      .size = size,
+    };
+
+  return PM_PmicControl(PMIC_CMD_WRITE, &arg);
+}
+
+#endif /* CONFIG_CXD56_PMIC */
diff --git a/arch/arm/src/cxd56xx/cxd56_pmic.h b/arch/arm/src/cxd56xx/cxd56_pmic.h
new file mode 100644
index 00000000000..7712c0a9a35
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_pmic.h
@@ -0,0 +1,761 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_pmic.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_PMIC_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56_PMIC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_CXD56_PMIC
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* PMIC Register Definitions */
+
+#define PMIC_REG_DDC_ANA1   (0x26)
+#define PMIC_REG_CNT_USB2   (0x81)
+
+/* PMIC DDC_ANA1 Definitions */
+
+#define PMIC_PM_HIZ     (2u << 4)
+#define PMIC_PM_DEF     (0u << 4)
+#define PMIC_IOST_DEF   (2u << 2)
+#define PMIC_IOMAX_DEF  (2u << 0)
+
+/* PMIC CNT_USB2 Definitions */
+
+#define PMIC_SET_CHGOFF (1u << 2)
+
+/* PMIC Interrupt Status Definitions */
+
+#define PMIC_INT_ALARM  (1u << 0)
+#define PMIC_INT_WKUPS  (1u << 1)
+#define PMIC_INT_WKUPL  (1u << 2)
+#define PMIC_INT_VSYS   (1u << 3)
+
+/* PMIC GPO Channel Definitions */
+
+#define PMIC_GPO0       (1u << 0)
+#define PMIC_GPO1       (1u << 1)
+#define PMIC_GPO2       (1u << 2)
+#define PMIC_GPO3       (1u << 3)
+#define PMIC_GPO4       (1u << 4)
+#define PMIC_GPO5       (1u << 5)
+#define PMIC_GPO6       (1u << 6)
+#define PMIC_GPO7       (1u << 7)
+
+/* PMIC LoadSwitch Channel Definitions */
+
+#define PMIC_LOADSW2    (1u << 2)
+#define PMIC_LOADSW3    (1u << 3)
+#define PMIC_LOADSW4    (1u << 4)
+
+/* PMIC DDC/LDO Channel Definitions */
+
+#define PMIC_DDC_IO     (1u << 0)
+#define PMIC_LDO_EMMC   (1u << 1)
+#define PMIC_DDC_ANA    (1u << 2)
+#define PMIC_LDO_ANA    (1u << 3)
+#define PMIC_DDC_CORE   (1u << 4)
+#define PMIC_LDO_PERI   (1u << 5)
+
+/* Charge mode for both of low/high temperature */
+
+#define PMIC_CHGMODE_ON   0x00
+#define PMIC_CHGMODE_OFF  0x01
+#define PMIC_CHGMODE_WEAK 0x02
+
+/* Charge status */
+
+#define PMIC_STAT_INIT_RST       0
+#define PMIC_STAT_INIT_WAIT      1
+#define PMIC_STAT_INIT_CHK       2
+#define PMIC_STAT_DBP_START      3
+#define PMIC_STAT_DB_INICHARGE   4
+#define PMIC_STAT_DB_PRECHARGE   5
+#define PMIC_STAT_DCON_WAIT      6
+#define PMIC_STAT_PD_START       7
+#define PMIC_STAT_DM_COMPARE     8
+#define PMIC_STAT_PD_END         9
+#define PMIC_STAT_BAT_WAIT       10
+#define PMIC_STAT_CHG_STOP       11
+#define PMIC_STAT_GB_PRECHARGE   12
+#define PMIC_STAT_GB_QCKCHARGE   13
+#define PMIC_STAT_GB_LOWCHARGE   14
+#define PMIC_STAT_GB_HIGHCHARGE  15
+#define PMIC_STAT_CHG_JUDGE      16
+#define PMIC_STAT_CHG_COMPLETE   17
+#define PMIC_STAT_GB_CONWAIT     18
+#define PMIC_STAT_GB_CPTEMPWAIT1 19
+#define PMIC_STAT_GB_CPTEMPWAIT2 20
+#define PMIC_STAT_GB_TEMPWAIT    21
+#define PMIC_STAT_DB_TEMPWAIT    22
+#define PMIC_STAT_DB_CONWAIT     23
+#define PMIC_STAT_BAT_UNUSUAL    24
+#define PMIC_STAT_BAT_DISCON     25
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+struct pmic_gauge_s
+{
+  int voltage;
+  int current;
+  int temp;
+};
+
+struct pmic_temp_table_s
+{
+  int T60;
+  int T45;
+  int T10;
+  int T00;
+};
+
+struct pmic_mon_s
+{
+  int on;
+  int interval;
+  int threshold_volt;
+  int threshold_current;
+};
+
+struct pmic_mon_status_s
+{
+  int bRun;
+  int index;
+  int latest;
+  int total_watt;
+  int total_time;
+};
+
+struct pmic_mon_set_s
+{
+  int clearBuf;
+  int clearSum;
+};
+
+struct pmic_mon_rec_s
+{
+  uint16_t index;
+  uint16_t timestamp;
+  uint16_t voltage;
+  int16_t  current;
+};
+
+struct pmic_mon_log_s
+{
+  FAR struct pmic_monitor_rec_s *rec;
+  int index;
+  int size;
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_pmic_get_interrupt_status
+ *
+ * Description:
+ *   Get Raw Interrupt Status register. And furthermore, if status is set,
+ *   then clear the interrupt. Register's decription is below:
+ *
+ *     7   6   5   4    3     2     1     0
+ *   +---------------+-----+-----+-----+-----+
+ *   | x   x   x   x |VSYS |WKUPL|WKUPS|ALARM| target of status
+ *   +---------------+-----+-----+-----+-----+
+ *
+ * Input Parameter:
+ *   status - a pointer to the polled value of interrupt status
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *   status - return the value of interrupt status register
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_get_interrupt_status(FAR uint8_t *status);
+
+/****************************************************************************
+ * Name: cxd56_pmic_set_gpo_reg
+ *
+ * Description:
+ *   Set GPO register. Register's decription is below:
+ *
+ *     7   6   5   4   3   2   1   0
+ *   +---+---+---+---+---+---+---+---+
+ *   |CH3|CH2|CH1|CH0|CH3|CH2|CH1|CH0| target of setbit0/clrbit0
+ *   +---+---+---+---+---+---+---+---+
+ *   +---+---+---+---+---+---+---+---+
+ *   |CH7|CH6|CH5|CH4|CH7|CH6|CH5|CH4| target of setbit1/clrbit1
+ *   +---+---+---+---+---+---+---+---+
+ *   |<- 0: Hi-Z   ->|<- 0: Low    ->|
+ *   |<- 1: Output ->|<- 1: High   ->|
+ *
+ * Input Parameter:
+ *   setbitX - set bit that 1 is set
+ *   clrbitX - clear bit that 1 is set
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *   setbitX - return the current value of register
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_set_gpo_reg(FAR uint8_t *setbit0, FAR uint8_t *clrbit0,
+                           FAR uint8_t *setbit1, FAR uint8_t *clrbit1);
+
+/****************************************************************************
+ * Name: cxd56_pmic_set_gpo
+ *
+ * Description:
+ *   Set High/Low to the specified GPO channel(s)
+ *
+ * Input Parameter:
+ *   chset - GPO Channel number(s)
+ *   value - true if output high, false if output low.
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_set_gpo(uint8_t chset, bool value);
+
+/****************************************************************************
+ * Name: cxd56_pmic_set_gpo_hiz
+ *
+ * Description:
+ *   Set Hi-Z to the specified GPO channel(s)
+ *
+ * Input Parameter:
+ *   chset - GPO Channel number(s)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_set_gpo_hiz(uint8_t chset);
+
+/****************************************************************************
+ * Name: cxd56_pmic_get_gpo
+ *
+ * Description:
+ *   Get the value from the specified GPO channel(s)
+ *
+ * Input Parameter:
+ *   chset : GPO Channel number(s)
+ *
+ * Returned Value:
+ *   Return true if all of the specified chset are high. Otherwise, return false
+ *
+ ****************************************************************************/
+
+bool cxd56_pmic_get_gpo(uint8_t chset);
+
+/****************************************************************************
+ * Name: cxd56_pmic_set_loadswitch_reg
+ *
+ * Description:
+ *   Set LoadSwitch register. Register's decription is below:
+ *
+ *     7   6   5   4   3   2   1   0
+ *   +---+---+---+---+---+---+---+---+
+ *   | - | - | - |CH4|CH3|CH2| 1 | 1 | target of setbit/clrbit
+ *   +---+---+---+---+---+---+---+---+
+ *               |<- 0: Off->|
+ *               |<- 1: On ->|
+ *
+ * Input Parameter:
+ *   setbit - set bit that 1 is set
+ *   clrbit - clear bit that 1 is set
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *   setbit - return the current value of register
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_set_loadswitch_reg(FAR uint8_t *setbit, FAR uint8_t *clrbit);
+
+/****************************************************************************
+ * Name: cxd56_pmic_set_loadswitch
+ *
+ * Description:
+ *   Set On/Off to the specified LoadSwitch channel(s)
+ *
+ * Input Parameter:
+ *   chset - LoadSwitch Channel number(s)
+ *   value - true if set on, false if set off.
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_set_loadswitch(uint8_t chset, bool value);
+
+/****************************************************************************
+ * Name: cxd56_pmic_get_loadswitch
+ *
+ * Description:
+ *   Get the value from the specified LoadSwitch channel(s)
+ *
+ * Input Parameter:
+ *   chset - LoadSwitch Channel number(s)
+ *
+ * Returned Value:
+ *   Return true if all of the specified chset are on. Otherwise, return false
+ *
+ ****************************************************************************/
+
+bool cxd56_pmic_get_loadswitch(uint8_t chset);
+
+/****************************************************************************
+ * Name: cxd56_pmic_set_ddc_ldo_reg
+ *
+ * Description:
+ *   Set DDC/LDO register. Register's decription is below:
+ *
+ *      7    6    5    4    3    2    1    0
+ *   +----+----+----+----+----+----+----+----+
+ *   |    |    |LDO |DDC |LDO |DDC |LDO |DDC | target of setbit/clrbit
+ *   | -  | -  |PERI|CORE|ANA |ANA |EMMC|IO  |
+ *   +----+----+----+----+----+----+----+----+
+ *             |<-  0: Off                 ->|
+ *             |<-  1: On                  ->|
+ *
+ * Input Parameter:
+ *   setbit - set bit that 1 is set
+ *   clrbit - clear bit that 1 is set
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *   setbit - return the current value of register
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_set_ddc_ldo_reg(FAR uint8_t *setbit, FAR uint8_t *clrbit);
+
+/****************************************************************************
+ * Name: cxd56_pmic_set_ddc_ldo
+ *
+ * Description:
+ *   Set On/Off to the specified DDC/LDO channel(s)
+ *
+ * Input Parameter:
+ *   chset - DDC/LO Channel number(s)
+ *   value - true if set on, false if set off.
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_set_ddc_ldo(uint8_t chset, bool value);
+
+/****************************************************************************
+ * Name: cxd56_pmic_get_ddc_ldo
+ *
+ * Description:
+ *   Get the value from the specified DDC/LDO channel(s)
+ *
+ * Input Parameter:
+ *   chset - DDC/LDO Channel number(s)
+ *
+ * Returned Value:
+ *   Return true if all of the specified chset are on. Otherwise, return false
+ *
+ ****************************************************************************/
+
+bool cxd56_pmic_get_ddc_ldo(uint8_t chset);
+
+/****************************************************************************
+ * Name: cxd56_pmic_get_gauge
+ *
+ * Description:
+ *   Get the set of values (gauge, voltage, current and temperature) from
+ *   PMIC.
+ *
+ * Input Parameter:
+ *   gauge - Set of gauge values
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_get_gauge(FAR struct pmic_gauge_s *gauge);
+
+/****************************************************************************
+ * Name: cxd56_pmic_getlowervol
+ *
+ * Description:
+ *   Get lower limit of voltage for system to be running.
+ *
+ * Input Parameter:
+ *   voltage - Lower limit voltage (mV)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getlowervol(FAR int *vol);
+
+/****************************************************************************
+ * Name: cxd56_pmic_getchargevol
+ *
+ * Description:
+ *   Get charge voltage
+ *
+ * Input Parameter:
+ *   voltage - Possible values are every 50 between 4000 to 4400 (mV)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getchargevol(FAR int *voltage);
+
+/****************************************************************************
+ * Name: cxd56_pmic_setchargevol
+ *
+ * Description:
+ *   Set charge voltage
+ *
+ * Input Parameter:
+ *   voltage - Avalable values are every 50 between 4000 to 4400 (mV)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_setchargevol(int voltage);
+
+/****************************************************************************
+ * Name: cxd56_pmic_getchargecurrent
+ *
+ * Description:
+ *   Get charge current value
+ *
+ * Input Parameter:
+ *   current - Possible values are 2, 100 and 500 (mA). However,
+ *             2 means 2.5 mA actually.
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getchargecurrent(FAR int *current);
+
+/****************************************************************************
+ * Name: cxd56_pmic_setchargecurrent
+ *
+ * Description:
+ *   Set charge current value
+ *
+ * Input Parameter:
+ *   current - Available values are 2, 100 and 500 (mA). However, 2 means
+ *             2.5 mA actually.
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_setchargecurrent(int current);
+
+/****************************************************************************
+ * Name: cxd56_pmic_getporttype
+ *
+ * Description:
+ *   Get USB port type
+ *
+ * Input Parameter:
+ *   porttype - PMIC_PORTTYPE_SDP or PMIC_PORTTYPE_DCPCDP
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getporttype(FAR int *porttype);
+
+/****************************************************************************
+ * Name: cxd56_pmic_getchargestate
+ *
+ * Description:
+ *   Read charging status
+ *
+ * Input Parameter:
+ *   state - Charging status (see PMIC_STAT_* definitions)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getchargestate(FAR uint8_t *state);
+
+/****************************************************************************
+ * Name: cxd56_pmic_setrechargevol
+ *
+ * Description:
+ *   Set threshold voltage against full charge for automatic restart charging.
+ *
+ * Input Parameter:
+ *   mV - Available values are -400, -350, -300 and -250 (mV)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_setrechargevol(int mV);
+
+/****************************************************************************
+ * Name: cxd56_pmic_getrechargevol
+ *
+ * Description:
+ *   Get threshold voltage against full charge for automatic restart charging.
+ *
+ * Input Parameter:
+ *   mV - Possible values are -400, -350, -300 and -250 (mV)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getrechargevol(FAR int *mV);
+
+/****************************************************************************
+ * Name: cxd56_pmic_setchargecompcurrent
+ *
+ * Description:
+ *   Set current value setting for determine fully charged.
+ *
+ * Input Parameter:
+ *   current - Possible values are 50, 40, 30, 20 and 10 (mA)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_setchargecompcurrent(int current);
+
+/****************************************************************************
+ * Name: cxd56_pmic_getchargecompcurrent
+ *
+ * Description:
+ *   Get current value setting for determine fully charged.
+ *
+ * Input Parameter:
+ *   current - Available values are 50, 40, 30, 20 and 10 (mA)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getchargecompcurrent(FAR int *current);
+
+/****************************************************************************
+ * Name: cxd56_pmic_gettemptable
+ *
+ * Description:
+ *   Get temperature detect resistance table
+ *
+ * Input Parameter:
+ *   table - Settings values for temperature detecting (see CXD5247GF
+ *           specification for more detail)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_gettemptable(FAR struct pmic_temp_table_s *table);
+
+/****************************************************************************
+ * Name: cxd56_pmic_settemptable
+ *
+ * Description:
+ *   Set temperature detect resistance table
+ *
+ * Input Parameter:
+ *   table - Settings values for temperature detecting (see CXD5247GF
+ *           specification for more detail)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_settemptable(FAR struct pmic_temp_table_s *table);
+
+/****************************************************************************
+ * Name: cxd56_pmic_setchargemode
+ *
+ * Description:
+ *   Set charging mode in each low/high temperatures.
+ *   In lower than 10 degrees Celsius, charging mode will be changed on/off
+ *   and weak (half of charge current) according to setting.
+ *   In higher than 45 degrees Celsius, charging mode will be charged on/off
+ *   and weak (-0.15V from charge voltage) according to setting.
+ *
+ * Input Parameter:
+ *   low  - Charging mode in low temperature (see PMIC_CHGMODE_*)
+ *   high - Charging mode in high temperature (see PMIC_CHGMODE_*)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_setchargemode(int low, int high);
+
+/****************************************************************************
+ * Name: cxd56_pmic_getchargemode
+ *
+ * Description:
+ *   Get charging mode in each low/high temperatures.
+ *   In lower than 10 degrees Celsius, charging mode will be changed on/off
+ *   and weak (half of charge current) according to setting.
+ *   In higher than 45 degrees Celsius, charging mode will be charged on/off
+ *   and weak (-0.15V from charge voltage) according to setting.
+ *
+ * Input Parameter:
+ *   low  - Charging mode in low temperature (see PMIC_CHG_*)
+ *   high - Charging mode in high temperature (see PMIC_CHG_*)
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_getchargemode(FAR int *low, FAR int *high);
+
+/****************************************************************************
+ * Name: cxd56_pmic_read
+ *
+ * Description:
+ *   Read the value from the specified sub address
+ *
+ * Input Parameter:
+ *   addr - sub address
+ *   buf - pointer to read buffer
+ *   size - byte count of read
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_read(uint8_t addr, FAR void *buf, uint32_t size);
+
+/****************************************************************************
+ * Name: cxd56_pmic_write
+ *
+ * Description:
+ *   Write the value to the specified sub address
+ *
+ * Input Parameter:
+ *   addr - sub address
+ *   buf - pointer to write buffer
+ *   size - byte count of write
+ *
+ * Returned Value:
+ *   Return 0 on success. Otherwise, return a negated errno.
+ *
+ ****************************************************************************/
+
+int cxd56_pmic_write(uint8_t addr, FAR void *buf, uint32_t size);
+
+/****************************************************************************
+ * Battery monitor for debug
+ ****************************************************************************/
+
+#ifdef CONFIG_CXD56_PMIC_BATMONITOR
+int cxd56_pmic_monitor_enable(FAR struct pmic_mon_s *ptr);
+int cxd56_pmic_monitor_status(FAR struct pmic_mon_status_s *ptr);
+int cxd56_pmic_monitor_set(FAR struct pmic_mon_set_s *ptr);
+int cxd56_pmic_monitor_get(FAR struct pmic_mon_log_s *ptr);
+#else
+#define cxd56_pmic_monitor_enable(ptr)
+#define cxd56_pmic_monitor_status(ptr)
+#define cxd56_pmic_monitor_set(ptr)
+#define cxd56_pmic_monitor_get(ptr)
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_CXD56_PMIC */
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_PMIC_H */
diff --git a/arch/arm/src/cxd56xx/cxd56_sdhci.c b/arch/arm/src/cxd56xx/cxd56_sdhci.c
new file mode 100644
index 00000000000..a8129144be2
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_sdhci.c
@@ -0,0 +1,4583 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_sdhci.c
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "chip.h"
+#include "up_arch.h"
+#include "cxd56_sdhci.h"
+#include "cxd56_clock.h"
+#include "cxd56_pinconfig.h"
+
+#ifdef CONFIG_CXD56_SDIO
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#ifndef CONFIG_CXD56_SDIO_DMA
+#  warning "Large Non-DMA transfer may result in RX overrun failures"
+#endif
+
+#if !defined(CONFIG_SCHED_WORKQUEUE) || !defined(CONFIG_SCHED_HPWORK)
+#  error "Callback support requires CONFIG_SCHED_WORKQUEUE and CONFIG_SCHED_HPWORK"
+#endif
+
+#if !defined(CONFIG_MMCSD_MULTIBLOCK_DISABLE) && !defined(CONFIG_SDIO_BLOCKSETUP)
+#  error "This driver requires CONFIG_SDIO_BLOCKSETUP"
+#endif
+
+#ifndef CONFIG_CXD56_SDHCI_PRIO
+#  define CONFIG_CXD56_SDHCI_PRIO NVIC_SYSH_PRIORITY_DEFAULT
+#endif
+
+#ifndef CONFIG_CXD56_SDHCI_DMAPRIO
+#  define CONFIG_CXD56_SDHCI_DMAPRIO DMA_CCR_PRIMED
+#endif
+
+#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_VERBOSE)
+#  undef CONFIG_SDIO_XFRDEBUG
+#endif
+
+/* SDCLK frequencies corresponding to various modes of operation.  These
+ * values may be provided in either the NuttX configuration file or in
+ * the board.h file
+ *
+ * NOTE:  These settings are not currently used.  Since there are only four
+ * frequencies, it makes more sense to just "can" the fixed frequency prescaler
+ * and divider values.
+ */
+
+#ifndef CONFIG_CXD56_IDMODE_FREQ
+#  define CONFIG_CXD56_IDMODE_FREQ 400000    /* 400 KHz, ID mode */
+#endif
+#ifndef CONFIG_CXD56_MMCXFR_FREQ
+#  define CONFIG_CXD56_MMCXFR_FREQ 20000000  /* 20MHz MMC, normal clocking */
+#endif
+#ifndef CONFIG_CXD56_SD1BIT_FREQ
+#  define CONFIG_CXD56_SD1BIT_FREQ 20000000  /* 20MHz SD 1-bit, normal clocking */
+#endif
+#ifndef CONFIG_CXD56_SD4BIT_FREQ
+#  define CONFIG_CXD56_SD4BIT_FREQ 25000000  /* 25MHz SD 4-bit, normal clocking */
+#endif
+#ifndef CONFIG_CXD56_HSSD4BIT_FREQ
+#  define CONFIG_CXD56_HSSD4BIT_FREQ 50000000  /* 50MHz SD 4-bit, highspeed clocking */
+#endif
+
+#define CXD56_SDIO_BASECLK_FREQ (cxd56_get_sdio_baseclock()*2)
+
+/* Timing */
+
+#define SDHCI_CARDSTATETIMEOUT   (2000000)
+#define SDHCI_CMDTIMEOUT         (100000)
+#define SDHCI_LONGTIMEOUT        (1000000)
+
+#define SDHCI_WAIT_POWERON      MSEC2TICK(252)
+#define SDHCI_WAIT_POWEROFF     MSEC2TICK(300)
+
+/* Big DVS setting.  Range is 0=SDCLK*213 through 14=SDCLK*227 */
+
+#define SDHCI_DTOCV_MAXTIMEOUT     (0xF-0x1)
+#define SDHCI_DTOCV_DATATIMEOUT    (0XF-0x1)
+
+/* Data transfer / Event waiting interrupt mask bits */
+
+#define SDHCI_RESPERR_INTS  (SDHCI_INT_CCE|SDHCI_INT_CTOE|SDHCI_INT_CEBE|SDHCI_INT_CIE)
+#define SDHCI_RESPDONE_INTS (SDHCI_RESPERR_INTS|SDHCI_INT_CC)
+
+#define SDHCI_XFRERR_INTS   (SDHCI_INT_DCE|SDHCI_INT_DTOE|SDHCI_INT_DEBE)
+#define SDHCI_RCVDONE_INTS  (SDHCI_XFRERR_INTS|SDHCI_INT_BRR|SDHCI_INT_TC)
+#define SDHCI_SNDDONE_INTS  (SDHCI_XFRERR_INTS|SDHCI_INT_BWR|SDHCI_INT_TC)
+#define SDHCI_XFRDONE_INTS  (SDHCI_XFRERR_INTS|SDHCI_INT_BRR|SDHCI_INT_BWR|SDHCI_INT_TC)
+
+#define SDHCI_DMAERR_INTS   (SDHCI_INT_DCE|SDHCI_INT_DTOE|SDHCI_INT_DEBE|SDHCI_INT_DMAE)
+#define SDHCI_DMADONE_INTS  (SDHCI_DMAERR_INTS|SDHCI_INT_DINT|SDHCI_INT_TC)
+
+#define SDHCI_WAITALL_INTS  (SDHCI_RESPDONE_INTS|SDHCI_XFRDONE_INTS|SDHCI_DMADONE_INTS)
+
+/* Register logging support */
+
+#ifdef CONFIG_SDIO_XFRDEBUG
+#  define SAMPLENDX_BEFORE_SETUP  0
+#  define SAMPLENDX_AFTER_SETUP   1
+#  define SAMPLENDX_END_TRANSFER  2
+#  define DEBUG_NSAMPLES          3
+#endif
+
+/* DMA */
+
+#define CXD56_SDHCI_BUF_SIZE      (2048)
+#define SDHCI_MAX_BLOCK_COUNT     (0xffffffff)
+#define SDHCI_MAX_ADMA_TRANS_SIZE (0xffff+1)
+#ifndef CONFIG_CXD56_SDIO_MAX_LEN_ADMA_DSCR
+#  define CXD56_SDIO_MAX_LEN_ADMA_DSCR (16)
+#else
+#  define CXD56_SDIO_MAX_LEN_ADMA_DSCR (CONFIG_CXD56_SDIO_MAX_LEN_ADMA_DSCR)
+#endif
+
+#define SDHCI_ADMA_DSCR_L_LEN_MASK  (0xffff0000)
+#define SDHCI_ADMA_DSCR_L_LEN_SHIFT (16)
+#define SDHCI_ADMA_DSCR_L_ACT_SHIFT (4)
+#define SDHCI_ADMA_DSCR_L_ACT_NOP   (0<<4)
+#define SDHCI_ADMA_DSCR_L_ACT_RSV   (1<<4)
+#define SDHCI_ADMA_DSCR_L_ACT_TRAN  (2<<4)
+#define SDHCI_ADMA_DSCR_L_ACT_LNK   (3<<4)
+#define SDHCI_ADMA_DSCR_L_INT       (0x00000004)
+#define SDHCI_ADMA_DSCR_L_END       (0x00000002)
+#define SDHCI_ADMA_DSCR_L_VALID     (0x00000001)
+#define SDHCI_ADMA_DSCR_H_ADDR_MASK (0xffffffff)
+
+#define CXD56_SDHCI_ADSADDR_H (CXD56_SDHCI_ADSADDR+0x4)
+
+/* Card Common Control Registers (CCCR) */
+
+#define SDIO_CCCR_SIZE          0x100
+
+#define SDIO_CMD5253_READ       (0<<31)
+#define SDIO_CMD5253_WRITE      (1<<31)
+#define SDIO_CMD5253_FUNC_SHIFT (28)
+
+#define SDIO_CMD52_EXCHANGE     (1<<27)
+#define SDIO_CMD52_REG_SHIFT    (9)
+#define SDIO_CMD52_DATA_MASK    0xff
+
+#define CMD52_RESP_OK(resp)     (0 == (resp&0xCB00))
+
+/* For Function Basic Registers */
+
+#define SDIO_FBR_START          0x100
+
+/* Card Information Structure (CIS) */
+
+#define SDIO_CIS_START          0x1000
+#define SDIO_CIS_END            (SDIO_CIS_START+0x17000-0x10)
+
+/* CIS tuple codes (based on PC Card 16) */
+
+#define SDIO_CISTPL_NULL        0x00
+#define SDIO_CISTPL_VERS_1      0x15
+#define SDIO_CISTPL_MANFID      0x20
+#define SDIO_CISTPL_FUNCID      0x21
+#define SDIO_CISTPL_FUNCE       0x22
+#define SDIO_CISTPL_END         0xff
+
+/* CISTPL_FUNCID codes */
+
+#define TPLFID_FUNC_SDIO        0x0c
+
+#define SDIO_THREAD_DEFPRIO     50
+#define SDIO_THREAD_STACKSIZE   1024
+
+#define SDIO_OCR_NUM_FUNCTIONS(ocr) (((ocr) >> 28) & 0x7)
+#define SDIO_FUNC_NUM_MAX       (7)
+
+#ifndef MIN
+#  define MIN(a, b) ((a) < (b) ? (a) : (b))
+#endif
+
+#define SDIO_BLOCK_TIMEOUT      200
+#define SDIO_BLOCK_SIZE         512
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+#ifdef CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION
+/* Structure describing a single SDIO card slot. */
+
+struct sdio_softc_s
+{
+  int func_num;               /* number of I/O functions (SDIO) */
+  FAR struct sdio_function_s *fn[SDIO_FUNC_NUM_MAX + 1];     /* selected card */
+  bool full_speed;            /* high speed mode */
+  uint8_t dma;                /* true: hardware supports DMA */
+  sem_t  sem;                 /* Assures mutually exclusive access to the sdio */
+};
+
+/* Structure describing either an SDIO device I/O function. */
+
+struct sdio_function_s
+{
+  /* common members */
+  FAR struct sdio_softc_s *sc;  /* card slot softc */
+  sdio_irqhandler_t *irq_callback;    /* function callback */
+  int number;                 /* I/O function number or -1, 0 for func0,1 for func1... */
+  struct sdio_cis_s cis;        /* decoded CIS */
+};
+#endif /* CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION */
+
+/* This structure defines the state of the CXD56xx SDIO interface */
+
+struct cxd56_sdiodev_s
+{
+  struct sdio_dev_s  dev;        /* Standard, base SDIO interface */
+
+  /* CXD56xx-specific extensions */
+  /* Event support */
+
+  sem_t              waitsem;    /* Implements event waiting */
+  sdio_eventset_t    waitevents; /* Set of events to be waited for */
+  uint32_t           waitints;   /* Interrupt enables for event waiting */
+  volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
+  WDOG_ID            waitwdog;   /* Watchdog that handles event timeouts */
+
+  /* Callback support */
+
+  sdio_statset_t     cdstatus;   /* Card status */
+  sdio_eventset_t    cbevents;   /* Set of events to be cause callbacks */
+  worker_t           callback;   /* Registered callback function */
+  void              *cbarg;      /* Registered callback argument */
+  struct work_s      cbwork;     /* Callback work queue structure */
+
+  /* Interrupt mode data transfer support */
+
+  uint32_t          *buffer;     /* Address of current R/W buffer */
+  size_t             remaining;  /* Number of bytes remaining in the transfer */
+  uint32_t           xfrints;    /* Interrupt enables for data transfer */
+
+  /* DMA data transfer support */
+
+#ifdef CONFIG_SDIO_DMA
+  volatile uint8_t   xfrflags;   /* Used to synchronize SDIO and DMA completion events */
+  bool usedma;
+  bool dmasend_prepare;
+  size_t   receive_size;
+  uint8_t  *aligned_buffer; /* Used to buffer alignment */
+  uint8_t  *receive_buffer; /* Used to keep receive buffer address */
+  uint32_t dma_cmd;
+  uint32_t dmasend_cmd;
+  uint32_t dmasend_regcmd;
+#endif
+
+  /* Parameters */
+
+  uint16_t blocksize;
+#ifdef CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION
+  struct sdio_softc_s sc;           /* Structure describing a single SDIO card slot. */
+#endif /* CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION */
+};
+
+/* Register logging support */
+
+#ifdef CONFIG_SDIO_XFRDEBUG
+struct cxd56_sdhcregs_s
+{
+  /* All read-able SDHC registers */
+
+  uint32_t dsaddr;    /* DMA System Address Register */
+  uint32_t blkattr;   /* Block Attributes Register */
+  uint32_t cmdarg;    /* Command Argument Register */
+  uint32_t xferty;    /* Transfer Type Register */
+  uint32_t cmdrsp0;   /* Command Response 0 */
+  uint32_t cmdrsp1;   /* Command Response 1 */
+  uint32_t cmdrsp2;   /* Command Response 2 */
+  uint32_t cmdrsp3;   /* Command Response 3 */
+  uint32_t prsstat;   /* Present State Register */
+  uint32_t proctl;    /* Protocol Control Register */
+  uint32_t sysctl;    /* System Control Register */
+  uint32_t irqstat;   /* Interrupt Status Register */
+  uint32_t irqstaten; /* Interrupt Status Enable Register */
+  uint32_t irqsigen;  /* Interrupt Signal Enable Register */
+  uint32_t ac12err;   /* Auto CMD12 Error Status Register */
+  uint32_t htcapblt;  /* Host Controller Capabilities */
+  uint32_t admaes;    /* ADMA Error Status Register */
+  uint32_t adsaddr;   /* ADMA System Address Register */
+  uint32_t vendor;    /* Vendor Specific Register */
+  uint32_t hostver;   /* Host Controller Version */
+};
+#endif
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Low-level helpers ********************************************************/
+
+static void cxd56_takesem(struct cxd56_sdiodev_s *priv);
+#define     cxd56_givesem(priv) (sem_post(&(priv)->waitsem))
+static void cxd56_configwaitints(struct cxd56_sdiodev_s *priv, uint32_t waitints,
+              sdio_eventset_t waitevents, sdio_eventset_t wkupevents);
+static void cxd56_configxfrints(struct cxd56_sdiodev_s *priv, uint32_t xfrints);
+
+/* DMA Helpers **************************************************************/
+
+#ifdef CONFIG_SDIO_XFRDEBUG
+static void cxd56_sampleinit(void);
+static void cxd56_sdhcsample(struct cxd56_sdhcregs_s *regs);
+static void cxd56_sample(struct cxd56_sdiodev_s *priv, int index);
+static void cxd56_dumpsample(struct cxd56_sdiodev_s *priv,
+              struct cxd56_sdhcregs_s *regs, const char *msg);
+static void cxd56_dumpsamples(struct cxd56_sdiodev_s *priv);
+static void cxd56_showregs(struct cxd56_sdiodev_s *priv, const char *msg);
+#else
+#  define   cxd56_sampleinit()
+#  define   cxd56_sample(priv,index)
+#  define   cxd56_dumpsamples(priv)
+#  define   cxd56_showregs(priv,msg)
+#endif
+
+/* Data Transfer Helpers ****************************************************/
+
+static void cxd56_dataconfig(struct cxd56_sdiodev_s *priv, bool bwrite,
+                               unsigned int blocksize, unsigned int nblocks,
+                               unsigned int timeout);
+static void cxd56_datadisable(void);
+static void cxd56_transmit(struct cxd56_sdiodev_s *priv);
+static void cxd56_receive(struct cxd56_sdiodev_s *priv);
+static void cxd56_eventtimeout(int argc, uint32_t arg);
+static void cxd56_endwait(struct cxd56_sdiodev_s *priv, sdio_eventset_t wkupevent);
+static void cxd56_endtransfer(struct cxd56_sdiodev_s *priv, sdio_eventset_t wkupevent);
+
+/* Interrupt Handling *******************************************************/
+
+static int cxd56_interrupt(int irq, FAR void *context, FAR void *arg);
+
+/* SDIO interface methods ***************************************************/
+
+/* Mutual exclusion */
+
+#ifdef CONFIG_SDIO_MUXBUS
+static int cxd56_sdio_lock(FAR struct sdio_dev_s *dev, bool lock);
+#endif
+
+/* Initialization/setup */
+
+static void cxd56_sdio_sdhci_reset(FAR struct sdio_dev_s *dev);
+static sdio_capset_t cxd56_sdio_capabilities(FAR struct sdio_dev_s *dev);
+static sdio_statset_t cxd56_sdio_status(FAR struct sdio_dev_s *dev);
+static void cxd56_sdio_widebus(FAR struct sdio_dev_s *dev, bool enable);
+static void cxd56_sdio_frequency(uint32_t frequency);
+static void cxd56_sdio_clock(FAR struct sdio_dev_s *dev,
+              enum sdio_clock_e rate);
+static int  cxd56_sdio_attach(FAR struct sdio_dev_s *dev);
+
+/* Command/Status/Data Transfer */
+
+static int  cxd56_sdio_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
+              uint32_t arg);
+static void cxd56_blocksetup(FAR struct sdio_dev_s *dev, unsigned int blocklen,
+              unsigned int nblocks);
+static int  cxd56_sdio_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
+              size_t nbytes);
+static int  cxd56_sdio_sendsetup(FAR struct sdio_dev_s *dev,
+              FAR const uint8_t *buffer, uint32_t nbytes);
+static int  cxd56_sdio_cancel(FAR struct sdio_dev_s *dev);
+
+static int  cxd56_sdio_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd);
+static int  cxd56_sdio_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
+              uint32_t *rshort);
+static int  cxd56_sdio_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd,
+              uint32_t rlong[4]);
+static int  cxd56_sdio_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd,
+              uint32_t *rshort);
+
+/* EVENT handler */
+
+static void cxd56_sdio_waitenable(FAR struct sdio_dev_s *dev,
+              sdio_eventset_t eventset);
+static sdio_eventset_t
+            cxd56_sdio_eventwait(FAR struct sdio_dev_s *dev, uint32_t timeout);
+static void cxd56_sdio_callbackenable(FAR struct sdio_dev_s *dev,
+              sdio_eventset_t eventset);
+static int  cxd56_sdio_registercallback(FAR struct sdio_dev_s *dev,
+              worker_t callback, void *arg);
+
+/* DMA */
+
+#ifdef CONFIG_SDIO_DMA
+static int  cxd56_sdio_admasetup(FAR const uint8_t *buffer, size_t buflen);
+static int  cxd56_sdio_dmarecvsetup(FAR struct sdio_dev_s *dev,
+              FAR uint8_t *buffer, size_t buflen);
+static int  cxd56_sdio_dmasendsetup(FAR struct sdio_dev_s *dev,
+              FAR const uint8_t *buffer, size_t buflen);
+#endif
+
+#ifdef CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION
+static int cxd56_sdio_enable_cardint(void);
+static int cxd56_sdio_register_irq(FAR struct sdio_dev_s *dev, int func_num,
+                                   FAR sdio_irqhandler_t * handler);
+static int cxd56_sdio_function_disable(FAR struct sdio_dev_s *dev, int func_num);
+static int cxd56_sdio_function_enable(FAR struct sdio_dev_s *dev, int func_num);
+static int cxd56_sdio_readb(FAR struct sdio_dev_s *dev, int func_num,
+                            uint32_t addr, FAR uint8_t * rdata);
+static int cxd56_sdio_writeb(FAR struct sdio_dev_s *dev, int func_num,
+                             uint32_t addr, uint8_t data, FAR uint8_t * rdata);
+static int cxd56_sdio_read(FAR struct sdio_dev_s *dev, int func_num, uint32_t addr,
+                           FAR uint8_t * data, uint32_t size);
+static int cxd56_sdio_write(FAR struct sdio_dev_s *dev, int func_num, uint32_t addr,
+                            FAR uint8_t * data, uint32_t size);
+static int cxd56_sdhci_irq_handler(FAR struct sdio_dev_s *dev);
+static int cxd56_sdio_get_cis(FAR struct sdio_dev_s *dev, int func_num,
+                              FAR struct sdio_cis_s * cis);
+#endif /* CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION */
+
+/* Initialization/uninitialization/reset ************************************/
+
+static void cxd56_sdio_callback(void *arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+struct cxd56_sdiodev_s g_sdhcdev =
+{
+  .dev =
+    {
+#ifdef CONFIG_SDIO_MUXBUS
+      .lock             = cxd56_sdio_lock,
+#endif
+      .reset            = cxd56_sdio_sdhci_reset,
+      .capabilities     = cxd56_sdio_capabilities,
+      .status           = cxd56_sdio_status,
+      .widebus          = cxd56_sdio_widebus,
+      .clock            = cxd56_sdio_clock,
+      .attach           = cxd56_sdio_attach,
+      .sendcmd          = cxd56_sdio_sendcmd,
+      .blocksetup       = cxd56_blocksetup,
+      .recvsetup        = cxd56_sdio_recvsetup,
+      .sendsetup        = cxd56_sdio_sendsetup,
+      .cancel           = cxd56_sdio_cancel,
+      .waitresponse     = cxd56_sdio_waitresponse,
+      .recvR1           = cxd56_sdio_recvshortcrc,
+      .recvR2           = cxd56_sdio_recvlong,
+      .recvR3           = cxd56_sdio_recvshort,
+      .recvR4           = cxd56_sdio_recvshort,
+      .recvR5           = cxd56_sdio_recvshort,
+      .recvR6           = cxd56_sdio_recvshortcrc,
+      .recvR7           = cxd56_sdio_recvshort,
+      .waitenable       = cxd56_sdio_waitenable,
+      .eventwait        = cxd56_sdio_eventwait,
+      .callbackenable   = cxd56_sdio_callbackenable,
+      .registercallback = cxd56_sdio_registercallback,
+#ifdef CONFIG_SDIO_DMA
+      .dmarecvsetup     = cxd56_sdio_dmarecvsetup,
+      .dmasendsetup     = cxd56_sdio_dmasendsetup,
+#endif
+#ifdef CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION
+      .register_irq     = cxd56_sdio_register_irq,
+      .function_disable = cxd56_sdio_function_disable,
+      .function_enable  = cxd56_sdio_function_enable,
+      .readb            = cxd56_sdio_readb,
+      .writeb           = cxd56_sdio_writeb,
+      .read             = cxd56_sdio_read,
+      .write            = cxd56_sdio_write,
+      .get_cis          = cxd56_sdio_get_cis,
+#endif /* CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION */
+    },
+};
+
+/* Register logging support */
+
+#ifdef CONFIG_SDIO_XFRDEBUG
+static struct cxd56_sdhcregs_s g_sampleregs[DEBUG_NSAMPLES];
+#endif
+
+/* DMA */
+
+#ifdef CONFIG_SDIO_DMA
+static FAR uint32_t cxd56_sdhci_adma_dscr[CXD56_SDIO_MAX_LEN_ADMA_DSCR*2];
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Low-level Helpers
+ ****************************************************************************/
+/****************************************************************************
+ * Name: cxd56_takesem
+ *
+ * Description:
+ *   Take the wait semaphore (handling false alarm wakeups due to the receipt
+ *   of signals).
+ *
+ * Input Parameters:
+ *   dev - Instance of the SDIO device driver state structure.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void cxd56_takesem(struct cxd56_sdiodev_s *priv)
+{
+  /* Take the semaphore (perhaps waiting) */
+
+  while (sem_wait(&priv->waitsem) != 0)
+    {
+      /* The only case that an error should occr here is if the wait was
+       * awakened by a signal.
+       */
+
+      ASSERT(errno == EINTR);
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_configwaitints
+ *
+ * Description:
+ *   Enable/disable SDIO interrupts needed to suport the wait function
+ *
+ * Input Parameters:
+ *   priv       - A reference to the SDIO device state structure
+ *   waitints   - The set of bits in the SDIO MASK register to set
+ *   waitevents - Waited for events
+ *   wkupevent  - Wake-up events
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void cxd56_configwaitints(struct cxd56_sdiodev_s *priv, uint32_t waitints,
+                                 sdio_eventset_t waitevents,
+                                 sdio_eventset_t wkupevent)
+{
+  irqstate_t flags;
+
+  /* Save all of the data and set the new interrupt mask in one, atomic
+   * operation.
+   */
+
+  flags = enter_critical_section();
+  priv->waitevents = waitevents;
+  priv->wkupevent  = wkupevent;
+  priv->waitints   = waitints;
+#ifdef CONFIG_SDIO_DMA
+  priv->xfrflags   = 0;
+#endif
+  putreg32(priv->xfrints | priv->waitints | SDHCI_INT_CINT,
+           CXD56_SDHCI_IRQSIGEN);
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: cxd56_configxfrints
+ *
+ * Description:
+ *   Enable SDIO interrupts needed to support the data transfer event
+ *
+ * Input Parameters:
+ *   priv    - A reference to the SDIO device state structure
+ *   xfrints - The set of bits in the SDIO MASK register to set
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void cxd56_configxfrints(struct cxd56_sdiodev_s *priv, uint32_t xfrints)
+{
+  irqstate_t flags;
+  flags = enter_critical_section();
+  priv->xfrints = xfrints;
+  putreg32(priv->xfrints | priv->waitints | SDHCI_INT_CINT,CXD56_SDHCI_IRQSIGEN);
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * DMA Helpers
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_sampleinit
+ *
+ * Description:
+ *   Setup prior to collecting DMA samples
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SDIO_XFRDEBUG
+static void cxd56_sampleinit(void)
+{
+  memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * sizeof(struct cxd56_sdhcregs_s));
+}
+#endif
+
+/****************************************************************************
+ * Name: cxd56_sdhcsample
+ *
+ * Description:
+ *   Sample SDIO registers
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SDIO_XFRDEBUG
+static void cxd56_sdhcsample(struct cxd56_sdhcregs_s *regs)
+{
+  regs->dsaddr    = getreg32(CXD56_SDHCI_DSADDR);    /* DMA System Address Register */
+  regs->blkattr   = getreg32(CXD56_SDHCI_BLKATTR);   /* Block Attributes Register */
+  regs->cmdarg    = getreg32(CXD56_SDHCI_CMDARG);    /* Command Argument Register */
+  regs->xferty    = getreg32(CXD56_SDHCI_XFERTYP);   /* Transfer Type Register */
+  regs->cmdrsp0   = getreg32(CXD56_SDHCI_CMDRSP0);   /* Command Response 0 */
+  regs->cmdrsp1   = getreg32(CXD56_SDHCI_CMDRSP1);   /* Command Response 1 */
+  regs->cmdrsp2   = getreg32(CXD56_SDHCI_CMDRSP2);   /* Command Response 2 */
+  regs->cmdrsp3   = getreg32(CXD56_SDHCI_CMDRSP3);   /* Command Response 3 */
+  regs->prsstat   = getreg32(CXD56_SDHCI_PRSSTAT);   /* Present State Register */
+  regs->proctl    = getreg32(CXD56_SDHCI_PROCTL);    /* Protocol Control Register */
+  regs->sysctl    = getreg32(CXD56_SDHCI_SYSCTL);    /* System Control Register */
+  regs->irqstat   = getreg32(CXD56_SDHCI_IRQSTAT);   /* Interrupt Status Register */
+  regs->irqstaten = getreg32(CXD56_SDHCI_IRQSTATEN); /* Interrupt Status Enable Register */
+  regs->irqsigen  = getreg32(CXD56_SDHCI_IRQSIGEN);  /* Interrupt Signal Enable Register */
+  regs->ac12err   = getreg32(CXD56_SDHCI_AC12ERR);   /* Auto CMD12 Error Status Register */
+  regs->htcapblt  = getreg32(CXD56_SDHCI_HTCAPBLT);  /* Host Controller Capabilities */
+  regs->admaes    = getreg32(CXD56_SDHCI_ADMAES);    /* ADMA Error Status Register */
+  regs->adsaddr   = getreg32(CXD56_SDHCI_ADSADDR);   /* ADMA System Address Register */
+  regs->vendor    = getreg32(CXD56_SDHCI_VENDOR);    /* Vendor Specific Register */
+  regs->hostver   = getreg32(CXD56_SDHCI_HOSTVER);   /* Host Controller Version */
+}
+#endif
+
+/****************************************************************************
+ * Name: cxd56_sample
+ *
+ * Description:
+ *   Sample SDIO/DMA registers
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SDIO_XFRDEBUG
+static void cxd56_sample(struct cxd56_sdiodev_s *priv, int index)
+{
+  cxd56_sdhcsample(&g_sampleregs[index]);
+}
+#endif
+
+/****************************************************************************
+ * Name: cxd56_dumpsample
+ *
+ * Description:
+ *   Dump one register sample
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SDIO_XFRDEBUG
+static void cxd56_dumpsample(struct cxd56_sdiodev_s *priv,
+                               struct cxd56_sdhcregs_s *regs, const char *msg)
+{
+  mcinfo("SDHC Registers: %s\n", msg);
+  mcinfo("   DSADDR[%08x]: %08x\n", CXD56_SDHCI_DSADDR,    regs->dsaddr);
+  mcinfo("  BLKATTR[%08x]: %08x\n", CXD56_SDHCI_BLKATTR,   regs->blkattr);
+  mcinfo("   CMDARG[%08x]: %08x\n", CXD56_SDHCI_CMDARG,    regs->cmdarg);
+  mcinfo("  COMMAND[%08x]: %08x\n", CXD56_SDHCI_XFERTYP,   regs->xferty);
+  mcinfo("  CMDRSP0[%08x]: %08x\n", CXD56_SDHCI_CMDRSP0,   regs->cmdrsp0);
+  mcinfo("  CMDRSP1[%08x]: %08x\n", CXD56_SDHCI_CMDRSP1,   regs->cmdrsp1);
+  mcinfo("  CMDRSP2[%08x]: %08x\n", CXD56_SDHCI_CMDRSP2,   regs->cmdrsp2);
+  mcinfo("  CMDRSP3[%08x]: %08x\n", CXD56_SDHCI_CMDRSP3,   regs->cmdrsp3);
+  mcinfo("  PRSSTAT[%08x]: %08x\n", CXD56_SDHCI_PRSSTAT,   regs->prsstat);
+  mcinfo("   PROCTL[%08x]: %08x\n", CXD56_SDHCI_PROCTL,    regs->proctl);
+  mcinfo("  HOSTCTL[%08x]: %08x\n", CXD56_SDHCI_SYSCTL,    regs->sysctl);
+  mcinfo("  IRQSTAT[%08x]: %08x\n", CXD56_SDHCI_IRQSTAT,   regs->irqstat);
+  mcinfo("IRQSTATEN[%08x]: %08x\n", CXD56_SDHCI_IRQSTATEN, regs->irqstaten);
+  mcinfo(" IRQSIGEN[%08x]: %08x\n", CXD56_SDHCI_IRQSIGEN,  regs->irqsigen);
+  mcinfo("  AC12ERR[%08x]: %08x\n", CXD56_SDHCI_AC12ERR,   regs->ac12err);
+  mcinfo(" HTCAPBLT[%08x]: %08x\n", CXD56_SDHCI_HTCAPBLT,  regs->htcapblt);
+  mcinfo("   ADMAES[%08x]: %08x\n", CXD56_SDHCI_ADMAES,    regs->admaes);
+  mcinfo("  ADSADDR[%08x]: %08x\n", CXD56_SDHCI_ADSADDR,   regs->adsaddr);
+  mcinfo("  HOSTVER[%08x]: %08x\n", CXD56_SDHCI_HOSTVER,   regs->hostver);
+}
+#endif
+
+/****************************************************************************
+ * Name: cxd56_dumpsamples
+ *
+ * Description:
+ *   Dump all sampled register data
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SDIO_XFRDEBUG
+static void  cxd56_dumpsamples(struct cxd56_sdiodev_s *priv)
+{
+  cxd56_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup");
+  cxd56_dumpsample(priv, &g_sampleregs[SAMPLENDX_AFTER_SETUP], "After setup");
+  cxd56_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer");
+}
+#endif
+
+/****************************************************************************
+ * Name: cxd56_showregs
+ *
+ * Description:
+ *   Dump the current state of all registers
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SDIO_XFRDEBUG
+static void cxd56_showregs(struct cxd56_sdiodev_s *priv, const char *msg)
+{
+  struct cxd56_sdhcregs_s regs;
+
+  cxd56_sdhcsample(®s);
+  cxd56_dumpsample(priv, ®s, msg);
+}
+#endif
+
+/****************************************************************************
+ * Data Transfer Helpers
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_dataconfig
+ *
+ * Description:
+ *   Configure the SDIO data path for the next data transfer
+ *
+ ****************************************************************************/
+
+static void cxd56_dataconfig(struct cxd56_sdiodev_s *priv, bool bwrite,
+                               unsigned int blocksize, unsigned int nblocks,
+                               unsigned int timeout)
+{
+  //unsigned int watermark;
+  uint32_t regval = 0;
+
+  /* Set the data timeout value in the SDHCI_SYSCTL field to the selected value */
+
+  regval  = getreg32(CXD56_SDHCI_SYSCTL);
+  regval &= ~SDHCI_SYSCTL_DTOCV_MASK;
+  regval |= timeout << SDHCI_SYSCTL_DTOCV_SHIFT;
+  putreg32(regval, CXD56_SDHCI_SYSCTL);
+
+  /* Set the block size and count in the SDHCI_BLKATTR register.  The block
+   * size is only valid for multiple block transfers.
+   */
+
+  priv->blocksize = blocksize;
+
+  regval = blocksize << SDHCI_BLKATTR_SIZE_SHIFT |
+           nblocks   << SDHCI_BLKATTR_CNT_SHIFT;
+  putreg32(regval, CXD56_SDHCI_BLKATTR);
+}
+
+/****************************************************************************
+ * Name: cxd56_datadisable
+ *
+ * Description:
+ *   Disable the SDIO data path setup by cxd56_dataconfig() and
+ *   disable DMA.
+ *
+ ****************************************************************************/
+
+static void cxd56_datadisable(void)
+{
+  uint32_t regval;
+
+  /* Set the data timeout value in the SDHCI_SYSCTL field to the maximum value */
+
+  regval  = getreg32(CXD56_SDHCI_SYSCTL);
+  regval &= ~SDHCI_SYSCTL_DTOCV_MASK;
+  regval |= SDHCI_DTOCV_MAXTIMEOUT << SDHCI_SYSCTL_DTOCV_SHIFT;
+  putreg32(regval, CXD56_SDHCI_SYSCTL);
+
+  /* Set the block size to zero (no transfer) */
+
+  putreg32(0, CXD56_SDHCI_BLKATTR);
+}
+
+/****************************************************************************
+ * Name: cxd56_transmit
+ *
+ * Description:
+ *   Send SDIO data in interrupt mode
+ *
+ * Input Parameters:
+ *   priv - An instance of the SDIO device interface
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void cxd56_transmit(struct cxd56_sdiodev_s *priv)
+{
+  union
+    {
+      uint32_t w;
+      uint8_t  b[4];
+    } data;
+
+  /* Loop while there is more data to be sent, waiting for buffer write
+   * ready (BWR)
+   */
+
+  if (priv->buffer == 0)
+    {
+      return;
+    }
+
+  mcinfo("Entry: remaining: %d IRQSTAT: %08x\n",
+          priv->remaining, getreg32(CXD56_SDHCI_IRQSTAT));
+
+  while (priv->remaining > 0 &&
+         (getreg32(CXD56_SDHCI_IRQSTAT) & SDHCI_INT_BWR) != 0)
+    {
+      /* Clear BWR.  If there is more data in the buffer, writing to the
+       * buffer should reset BRR.
+       */
+
+      putreg32(SDHCI_INT_BWR, CXD56_SDHCI_IRQSTAT);
+
+      while (priv->remaining > 0 && (getreg32(CXD56_SDHCI_PRSSTAT) & SDHCI_PRSSTAT_BWEN) != 0)
+        {
+          /* Is there a full word remaining in the user buffer? */
+
+          if (priv->remaining >= sizeof(uint32_t))
+            {
+              /* Yes, transfer the word to the TX FIFO */
+
+              data.w           = *priv->buffer++;
+              priv->remaining -= sizeof(uint32_t);
+            }
+          else
+            {
+              /* No.. transfer just the bytes remaining in the user buffer,
+               * padding with zero as necessary to extend to a full word.
+               */
+
+              uint8_t *ptr = (uint8_t *)priv->buffer;
+              int i;
+
+              data.w = 0;
+              for (i = 0; i < priv->remaining; i++)
+                {
+                  data.b[i] = *ptr++;
+                }
+
+              /* Now the transfer is finished */
+
+              priv->remaining = 0;
+            }
+
+          /* Put the word in the FIFO */
+
+          putreg32(data.w, CXD56_SDHCI_DATPORT);
+        }
+    }
+
+  mcinfo("Exit: remaining: %d IRQSTAT: %08x\n",
+          priv->remaining, getreg32(CXD56_SDHCI_IRQSTAT));
+}
+
+/****************************************************************************
+ * Name: cxd56_receive
+ *
+ * Description:
+ *   Receive SDIO data in interrupt mode
+ *
+ * Input Parameters:
+ *   priv - An instance of the SDIO device interface
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void cxd56_receive(struct cxd56_sdiodev_s *priv)
+{
+  union
+    {
+      uint32_t w;
+      uint8_t  b[4];
+    } data;
+
+  /* Loop while there is space to store the data, waiting for buffer read
+   * ready (BRR)
+   */
+
+  if (priv->buffer == 0)
+    {
+      return;
+    }
+
+  mcinfo("Entry: remaining: %d IRQSTAT: %08x\n",
+          priv->remaining, getreg32(CXD56_SDHCI_IRQSTAT));
+
+  while (priv->remaining > 0 &&
+         (getreg32(CXD56_SDHCI_IRQSTAT) & SDHCI_INT_BRR) != 0)
+    {
+      /* Clear BRR.  If there is more data in the buffer, reading from the
+       * buffer should reset BRR.
+       */
+
+      putreg32(SDHCI_INT_BRR, CXD56_SDHCI_IRQSTAT);
+
+      while (priv->remaining > 0 && (getreg32(CXD56_SDHCI_PRSSTAT) & SDHCI_PRSSTAT_BREN) != 0)
+        {
+          /* Read the next word from the RX buffer */
+
+          data.w = getreg32(CXD56_SDHCI_DATPORT);
+          if (priv->remaining >= sizeof(uint32_t))
+            {
+              /* Transfer the whole word to the user buffer */
+
+              *priv->buffer++  = data.w;
+              priv->remaining -= sizeof(uint32_t);
+            }
+          else
+            {
+              /* Transfer any trailing fractional word */
+
+              uint8_t *ptr = (uint8_t *)priv->buffer;
+              int i;
+
+              for (i = 0; i < priv->remaining; i++)
+                {
+                  *ptr++ = data.b[i];
+                }
+
+              /* Now the transfer is finished */
+
+              priv->remaining = 0;
+            }
+        }
+    }
+
+}
+
+/****************************************************************************
+ * Name: cxd56_eventtimeout
+ *
+ * Description:
+ *   The watchdog timeout setup when the event wait start has expired without
+ *   any other waited-for event occurring.
+ *
+ * Input Parameters:
+ *   argc   - The number of arguments (should be 1)
+ *   arg    - The argument (state structure reference cast to uint32_t)
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Always called from the interrupt level with interrupts disabled.
+ *
+ ****************************************************************************/
+
+static void cxd56_eventtimeout(int argc, uint32_t arg)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)arg;
+
+  DEBUGASSERT(argc == 1 && priv != NULL);
+  DEBUGASSERT((priv->waitevents & SDIOWAIT_TIMEOUT) != 0);
+
+  /* Is a data transfer complete event expected? */
+
+  if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0)
+    {
+      /* Yes.. Sample registers at the time of the timeout */
+
+      cxd56_sample(priv, SAMPLENDX_END_TRANSFER);
+
+      /* Wake up any waiting threads */
+
+      cxd56_endwait(priv, SDIOWAIT_TIMEOUT);
+      mcwarn("Timeout: remaining: %d\n", priv->remaining);
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_endwait
+ *
+ * Description:
+ *   Wake up a waiting thread if the waited-for event has occurred.
+ *
+ * Input Parameters:
+ *   priv      - An instance of the SDIO device interface
+ *   wkupevent - The event that caused the wait to end
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Always called from the interrupt level with interrupts disabled.
+ *
+ ****************************************************************************/
+
+static void cxd56_endwait(struct cxd56_sdiodev_s *priv, sdio_eventset_t wkupevent)
+{
+  /* Cancel the watchdog timeout */
+
+  (void)wd_cancel(priv->waitwdog);
+
+  /* Disable event-related interrupts */
+
+  cxd56_configwaitints(priv, 0, 0, wkupevent);
+
+  /* Wake up the waiting thread */
+
+  cxd56_givesem(priv);
+}
+
+/****************************************************************************
+ * Name: cxd56_endtransfer
+ *
+ * Description:
+ *   Terminate a transfer with the provided status.  This function is called
+ *   only from the SDIO interrupt handler when end-of-transfer conditions
+ *   are detected.
+ *
+ * Input Parameters:
+ *   priv   - An instance of the SDIO device interface
+ *   wkupevent - The event that caused the transfer to end
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Always called from the interrupt level with interrupts disabled.
+ *
+ ****************************************************************************/
+
+static void cxd56_endtransfer(struct cxd56_sdiodev_s *priv, sdio_eventset_t wkupevent)
+{
+#ifdef CONFIG_SDIO_DMA
+  uint32_t regval;
+#endif
+
+  if (priv->buffer == 0)
+    {
+      return;
+    }
+
+  /* Disable all transfer related interrupts */
+
+  cxd56_configxfrints(priv, 0);
+
+  /* Clearing pending interrupt status on all transfer related interrupts */
+
+  putreg32(SDHCI_XFRDONE_INTS, CXD56_SDHCI_IRQSTAT);
+
+  /* If this was a DMA transfer, make sure that DMA is stopped */
+
+#ifdef CONFIG_SDIO_DMA
+  /* Stop the DMA by resetting the data path */
+
+  regval = getreg32(CXD56_SDHCI_SYSCTL);
+  regval |= SDHCI_SYSCTL_RSTD;
+  putreg32(regval, CXD56_SDHCI_SYSCTL);
+  cxd56_sdhci_adma_dscr[0] = 0;
+  cxd56_sdhci_adma_dscr[1] = 0;
+  putreg32((uint32_t)cxd56_sdhci_adma_dscr, CXD56_SDHCI_ADSADDR);
+  putreg32(0, CXD56_SDHCI_ADSADDR_H);
+  priv->usedma = false;
+  priv->dmasend_prepare = false;
+  priv->dmasend_cmd = 0;
+  priv->dmasend_regcmd = 0;
+#endif
+
+  /* Mark the transfer finished */
+
+  if ((priv->waitevents & wkupevent & (SDIOWAIT_TRANSFERDONE | SDIOWAIT_RESPONSEDONE)) == 0)
+    {
+      priv->remaining = 0;
+    }
+  priv->buffer = 0;
+
+  /* Debug instrumentation */
+
+  cxd56_sample(priv, SAMPLENDX_END_TRANSFER);
+
+  /* Is a thread wait for these data transfer complete events? */
+
+  if ((priv->waitevents & wkupevent) != 0)
+    {
+      /* Yes.. wake up any waiting threads */
+
+      cxd56_endwait(priv, wkupevent);
+    }
+}
+
+/****************************************************************************
+ * Interrupt Handling
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_interrupt
+ *
+ * Description:
+ *   SDIO interrupt handler
+ *
+ * Input Parameters:
+ *   dev - An instance of the SDIO device interface
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static int cxd56_interrupt(int irq, FAR void *context, FAR void *arg)
+{
+  struct cxd56_sdiodev_s *priv = &g_sdhcdev;
+  uint32_t enabled;
+  uint32_t pending;
+  uint32_t regval;
+
+  /* Check the SDHC IRQSTAT register.  Mask out all bits that don't
+   * correspond to enabled interrupts.  (This depends on the fact that bits
+   * are ordered the same in both the IRQSTAT and IRQSIGEN registers).  If
+   * there are non-zero bits remaining, then we have work to do here.
+   */
+
+  regval  = getreg32(CXD56_SDHCI_IRQSIGEN);
+  enabled = getreg32(CXD56_SDHCI_IRQSTAT) & regval;
+  mcinfo("IRQSTAT: %08x IRQSIGEN %08x enabled: %08x\n",
+          getreg32(CXD56_SDHCI_IRQSTAT), regval, enabled);
+
+  /* Disable card interrupts to clear the card interrupt to the host system. */
+
+  regval &= ~(SDHCI_INT_CINT | enabled);
+  putreg32(regval, CXD56_SDHCI_IRQSIGEN);
+
+  /* Clear all pending interrupts */
+
+  //putreg32(enabled, CXD56_SDHCI_IRQSTAT);
+
+  /* Handle in progress, interrupt driven data transfers ********************/
+
+  pending  = enabled & priv->xfrints;
+  if (pending != 0)
+    {
+      /* Is the RX buffer read ready?  Is so then we must be processing a
+       * non-DMA receive transaction.
+       */
+
+      if ((pending & SDHCI_INT_BRR) != 0)
+        {
+          /* Receive data from the RX buffer */
+
+          cxd56_receive(priv);
+        }
+
+      /* Otherwise, Is the TX buffer write ready? If so we must
+       * be processing a non-DMA send transaction.  NOTE:  We can't be
+       * processing both!
+       */
+
+      else if ((pending & SDHCI_INT_BWR) != 0)
+        {
+          /* Send data via the TX FIFO */
+
+          cxd56_transmit(priv);
+        }
+
+      /* Handle transfer complete events */
+
+      if ((pending & SDHCI_INT_TC) != 0)
+        {
+          /* Terminate the transfer */
+
+          cxd56_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
+        }
+
+      /* Handle data block send/receive CRC failure */
+
+      else if ((pending & SDHCI_INT_DCE) != 0)
+        {
+          /* Terminate the transfer with an error */
+
+          mcerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
+          cxd56_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
+        }
+
+      /* Handle data timeout error */
+
+      else if ((pending & SDHCI_INT_DTOE) != 0)
+        {
+          /* Terminate the transfer with an error */
+
+          mcerr("ERROR: Data timeout, remaining: %d\n", priv->remaining);
+          cxd56_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT);
+        }
+    }
+
+#ifdef CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION
+  if (enabled & SDHCI_INT_CINT)
+    {
+      /* Handle card interrupt events */
+
+      putreg32(getreg32(CXD56_SDHCI_IRQSIGEN) & (~SDHCI_INT_CINT), CXD56_SDHCI_IRQSIGEN);
+      putreg32(getreg32(CXD56_SDHCI_IRQSTATEN) & (~SDHCI_INT_CINT), CXD56_SDHCI_IRQSTATEN);
+      work_cancel(HPWORK, &priv->cbwork);
+      (void)work_queue(HPWORK, &priv->cbwork, (worker_t)cxd56_sdhci_irq_handler, &priv->dev, 0);
+    }
+#endif /* CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION */
+
+  /* Handle wait events *****************************************************/
+
+  pending  = enabled & priv->waitints;
+  if (pending != 0)
+    {
+      /* Is this a response completion event? */
+
+      if ((pending & SDHCI_RESPDONE_INTS) != 0)
+        {
+          /* Yes.. Is their a thread waiting for response done? */
+
+          if ((priv->waitevents & (SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE)) != 0)
+            {
+              /* Yes.. mask further interrupts and wake the thread up */
+
+              regval = getreg32(CXD56_SDHCI_IRQSIGEN);
+              regval &= ~SDHCI_RESPDONE_INTS;
+              putreg32(regval, CXD56_SDHCI_IRQSIGEN);
+
+              cxd56_endwait(priv, SDIOWAIT_RESPONSEDONE);
+            }
+        }
+    }
+
+  /* Re-enable card interrupts */
+
+  regval  = getreg32(CXD56_SDHCI_IRQSIGEN);
+  regval |= SDHCI_INT_CINT | enabled;
+  putreg32(regval, CXD56_SDHCI_IRQSIGEN);
+
+  return OK;
+}
+
+/****************************************************************************
+ * SDIO Interface Methods
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_sdio_lock
+ *
+ * Description:
+ *   Locks the bus. Function calls low-level multiplexed bus routines to
+ *   resolve bus requests and acknowledgement issues.
+ *
+ * Input Parameters:
+ *   dev    - An instance of the SDIO device interface
+ *   lock   - TRUE to lock, FALSE to unlock.
+ *
+ * Returned Value:
+ *   OK on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SDIO_MUXBUS
+static int cxd56_sdio_lock(FAR struct sdio_dev_s *dev, bool lock)
+{
+  /* Single SDIO instance so there is only one possibility.  The multiplex
+   * bus is part of board support package.
+   */
+
+  cxd56_muxbus_sdio_lock(lock);
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: cxd56_sdio_sdhci_reset
+ *
+ * Description:
+ *   Reset the SDIO controller.  Undo all setup and initialization.
+ *
+ * Input Parameters:
+ *   dev - An instance of the SDIO device interface
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void cxd56_sdio_sdhci_reset(FAR struct sdio_dev_s *dev)
+{
+  FAR struct cxd56_sdiodev_s *priv = (FAR struct cxd56_sdiodev_s *)dev;
+  uint32_t regval;
+  int32_t timeout = 100;
+
+  /* Disable all interrupts so that nothing interferes with the following. */
+
+  putreg32(0, CXD56_SDHCI_IRQSIGEN);
+
+  /* Reset the SDHC block, putting registers in their default, reset state.
+   * Initiate the reset by setting the RSTA bit in the SYSCTL register.
+   */
+
+  regval  = getreg32(CXD56_SDHCI_SYSCTL);
+  regval |= SDHCI_SYSCTL_RSTA;
+  putreg32(regval, CXD56_SDHCI_SYSCTL);
+
+  /* The SDHC will reset the RSTA bit to 0 when the capabilities
+   * registers are valid and the host driver can read them.
+   */
+
+  while ((getreg32(CXD56_SDHCI_SYSCTL) & SDHCI_SYSCTL_RSTA) != 0)
+    {
+      timeout--;
+      if (timeout < 1)
+        {
+          break;
+        }
+      up_mdelay(30);
+    }
+
+  /* Make sure that all clocking is disabled */
+
+  cxd56_sdio_clock(dev, CLOCK_SDIO_DISABLED);
+
+  /* Enable all status bits (these could not all be potential sources of
+   * interrupts.
+   */
+
+  putreg32(SDHCI_INT_ALL & (~SDHCI_INT_CINT), CXD56_SDHCI_IRQSTATEN);
+
+  mcinfo("SYSCTL: %08x PRSSTAT: %08x IRQSTATEN: %08x\n",
+        getreg32(CXD56_SDHCI_SYSCTL), getreg32(CXD56_SDHCI_PRSSTAT),
+        getreg32(CXD56_SDHCI_IRQSTATEN));
+
+  /* The next phase of the hardware reset would be to set the SYSCTRL INITA
+   * bit to send 80 clock ticks for card to power up and then reset the card
+   * with CMD0.  This is done elsewhere.
+   */
+
+  /* Reset state data */
+  sem_init(&priv->waitsem, 0, 1);
+  priv->waitwdog = wd_create();
+  DEBUGASSERT(priv->waitwdog);
+  sem_init(&priv->waitsem, 0, 1);
+  priv->waitevents = 0;      /* Set of events to be waited for */
+  priv->waitints   = 0;      /* Interrupt enables for event waiting */
+  priv->wkupevent  = 0;      /* The event that caused the wakeup */
+#ifdef CONFIG_SDIO_DMA
+  priv->xfrflags   = 0;      /* Used to synchronize SDIO and DMA completion events */
+#endif
+
+  wd_cancel(priv->waitwdog); /* Cancel any timeouts */
+
+  /* Interrupt mode data transfer support */
+
+  priv->buffer     = 0;      /* Address of current R/W buffer */
+  priv->remaining  = 0;      /* Number of bytes remaining in the transfer */
+  priv->xfrints    = 0;      /* Interrupt enables for data transfer */
+
+  priv->blocksize = CXD56_SDHCI_BUF_SIZE;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_capabilities
+ *
+ * Description:
+ *   Get capabilities (and limitations) of the SDIO driver (optional)
+ *
+ * Input Parameters:
+ *   dev   - Device-specific state data
+ *
+ * Returned Value:
+ *   Returns a bitset of status values (see SDIO_CAPS_* defines)
+ *
+ ****************************************************************************/
+
+static sdio_capset_t cxd56_sdio_capabilities(FAR struct sdio_dev_s *dev)
+{
+  sdio_capset_t caps = 0;
+
+#ifdef CONFIG_CXD56_SDIO_WIDTH_D1_ONLY
+  caps |= SDIO_CAPS_1BIT_ONLY;
+#endif
+#ifdef CONFIG_CXD56_SDIO_DMA
+  caps |= SDIO_CAPS_DMASUPPORTED;
+#endif
+#ifndef CONFIG_CXD56_SDIO_DMA
+  /* In case of non-DMA, add below capability to change the write single
+   * sequence with sending CMD24. If not, write is not completed.
+   */
+
+  caps |= SDIO_CAPS_DMABEFOREWRITE;
+#endif
+
+  return caps;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_status
+ *
+ * Description:
+ *   Get SDIO status.
+ *
+ * Input Parameters:
+ *   dev   - Device-specific state data
+ *
+ * Returned Value:
+ *   Returns a bitset of status values (see cxd56_status_* defines)
+ *
+ ****************************************************************************/
+
+static sdio_statset_t cxd56_sdio_status(FAR struct sdio_dev_s *dev)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+  return priv->cdstatus;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_widebus
+ *
+ * Description:
+ *   Called after change in Bus width has been selected (via ACMD6).  Most
+ *   controllers will need to perform some special operations to work
+ *   correctly in the new bus mode.
+ *
+ * Input Parameters:
+ *   dev  - An instance of the SDIO device interface
+ *   wide - true: wide bus (4-bit) bus mode enabled
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void cxd56_sdio_widebus(FAR struct sdio_dev_s *dev, bool wide)
+{
+  uint32_t regval;
+
+  /* Set the Data Transfer Width (DTW) field in the PROCTL register */
+
+  regval = getreg32(CXD56_SDHCI_PROCTL);
+  regval &= ~SDHCI_PROCTL_DTW_MASK;
+  if (wide)
+    {
+      regval |= SDHCI_PROCTL_DTW_4BIT;
+    }
+  else
+    {
+      regval |= SDHCI_PROCTL_DTW_1BIT;
+    }
+  putreg32(regval, CXD56_SDHCI_PROCTL);
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_frequency
+ *
+ * Description:
+ *   Set the SD clock frequency
+ *
+ * Input Parameters:
+ *   dev       - An instance of the SDIO device interface
+ *   frequency - The frequency to use
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void cxd56_sdio_frequency(uint32_t frequency)
+{
+  uint32_t baseclk;
+  uint16_t i;
+  uint32_t regval;
+  uint16_t divisor;
+
+  baseclk = cxd56_get_sdio_baseclock();
+  if (frequency >= baseclk)
+    {
+      divisor = 0;
+    }
+  else
+    {
+      for (i=1; i<0x3ff; i++)
+        {
+          if (baseclk / (2 * i) < frequency)
+            {
+              break;
+            }
+        }
+      divisor = i;
+    }
+
+  regval  = getreg32(CXD56_SDHCI_SYSCTL);
+  regval &= ~SDHCI_SYSCTL_GENSEL;
+  regval &= ~(SDHCI_SYSCTL_SDCLKFS_MASK | SDHCI_SYSCTL_SDCLKFSUP_MASK);
+  regval |= (divisor << SDHCI_SYSCTL_SDCLKFS_SHIFT) & SDHCI_SYSCTL_SDCLKFS_MASK;
+  regval |= ((divisor >> 8) << SDHCI_SYSCTL_SDCLKFSUP_SHIFT) & SDHCI_SYSCTL_SDCLKFSUP_MASK;
+  putreg32(regval, CXD56_SDHCI_SYSCTL);
+}
+
+static void cxd56_sdio_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
+{
+  uint32_t regval;
+  uint32_t frequency = 0;
+  uint32_t i;
+
+  /* The SDCLK must be disabled before its frequency can be changed: "SDCLK
+   * frequency can be changed when this bit is 0. Then, the host controller
+   * shall maintain the same clock frequency until SDCLK is stopped (stop at
+   * SDCLK = 0).
+   */
+
+  regval  = getreg32(CXD56_SDHCI_SYSCTL);
+  regval &= ~SDHCI_SYSCTL_SDCLKEN;
+  putreg32(regval, CXD56_SDHCI_SYSCTL);
+  mcinfo("SYSCTRL: %08x\n", getreg32(CXD56_SDHCI_SYSCTL));
+
+  /* sel_ttclk bit[16] */
+  if (cxd56_get_sdio_baseclock() < 48*1000*1000)
+    {
+      putreg32(getreg32(CXD56_SDHCI_USERDEF2CTL) | (0x1 << 16),
+               CXD56_SDHCI_USERDEF2CTL);
+    }
+  else
+    {
+      putreg32(getreg32(CXD56_SDHCI_USERDEF2CTL) & ~(0x1 << 16),
+               CXD56_SDHCI_USERDEF2CTL);
+    }
+
+  /* HS_SYNC_RISE bit[16] */
+  putreg32(0x01010100, CXD56_SDHCI_OTHERIOLL);
+
+  /* sdclk_dly_sel */
+  if (rate <= CLOCK_SD_TRANSFER_4BIT)
+    putreg32((getreg32(CXD56_SDHCI_USERDEF2CTL) & ~(0x7))| 0x1, CXD56_SDHCI_USERDEF2CTL);
+  else
+    putreg32((getreg32(CXD56_SDHCI_USERDEF2CTL) & ~(0x7))| 0x0, CXD56_SDHCI_USERDEF2CTL);
+
+  /* Select the new prescaler and divisor values based on the requested mode
+   * and the settings from the board.h file.
+   *
+   * TODO:  Investigate using the automatically gated clocks to reduce power
+   *        consumption.
+   */
+
+  switch (rate)
+    {
+    default:
+    case CLOCK_SDIO_DISABLED :     /* Clock is disabled */
+      {
+        /* Clear the prescaler and divisor settings and other clock
+         * enables as well.
+         */
+        regval &= ~(SDHCI_SYSCTL_SDCLKFS_MASK | SDHCI_SYSCTL_SDCLKFSUP_MASK);
+        putreg32(regval, CXD56_SDHCI_SYSCTL);
+        cxd56_sdio_frequency(CONFIG_CXD56_IDMODE_FREQ);
+        mcinfo("SYSCTRL: %08x\n", getreg32(CXD56_SDHCI_SYSCTL));
+        return;
+      }
+
+    case CLOCK_IDMODE :            /* Initial ID mode clocking (<400KHz) */
+      frequency = CONFIG_CXD56_IDMODE_FREQ;
+      break;
+
+    case CLOCK_MMC_TRANSFER :      /* MMC normal operation clocking */
+      frequency = CONFIG_CXD56_MMCXFR_FREQ;
+      break;
+
+    case CLOCK_SD_TRANSFER_1BIT :  /* SD normal operation clocking (narrow 1-bit mode) */
+#ifndef CONFIG_CXD56_SDIO_WIDTH_D1_ONLY
+      frequency = CONFIG_CXD56_SD1BIT_FREQ;
+      break;
+#endif
+
+    case CLOCK_SD_TRANSFER_4BIT :  /* SD normal operation clocking (wide 4-bit mode) */
+      frequency = CONFIG_CXD56_SD4BIT_FREQ;
+      break;
+    }
+
+  cxd56_sdio_frequency(frequency);
+
+  putreg32(getreg32(CXD56_SDHCI_SYSCTL) | SDHCI_SYSCTL_ICLKEN, CXD56_SDHCI_SYSCTL);
+  for (i=0;i<20;i++)
+    {
+      up_mdelay(50);
+      regval  = getreg32(CXD56_SDHCI_SYSCTL);
+      if (regval & SDHCI_SYSCTL_ICLKSTA)
+        {
+          break;
+        }
+    }
+  do
+    {
+      putreg32(regval | SDHCI_SYSCTL_SDCLKEN, CXD56_SDHCI_SYSCTL);
+    }
+  while((getreg32(CXD56_SDHCI_SYSCTL) & SDHCI_SYSCTL_SDCLKEN) == 0);
+  mcinfo("SYSCTRL: %08x\n", getreg32(CXD56_SDHCI_SYSCTL));
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_attach
+ *
+ * Description:
+ *   Attach and prepare interrupts
+ *
+ * Input Parameters:
+ *   dev - An instance of the SDIO device interface
+ *
+ * Returned Value:
+ *   OK on success; A negated errno on failure.
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_attach(FAR struct sdio_dev_s *dev)
+{
+  int ret;
+
+  /* Attach the SDIO interrupt handler */
+  ret = irq_attach(CXD56_IRQ_SDIO, cxd56_interrupt, NULL);
+  if (ret == OK)
+    {
+      /* Disable all interrupts at the SDIO controller and clear all pending
+       * interrupts.
+       */
+
+      putreg32(0,            CXD56_SDHCI_IRQSIGEN);
+      putreg32(SDHCI_INT_ALL, CXD56_SDHCI_IRQSTAT);
+
+#ifdef CONFIG_ARCH_IRQPRIO
+      /* Set the interrupt priority */
+
+      up_prioritize_irq(CXD56_IRQ_SDIO, CONFIG_CXD56_SDHCI_PRIO);
+#endif
+
+      /* Enable SDIO interrupts at the NVIC.  They can now be enabled at
+       * the SDIO controller as needed.
+       */
+
+      up_enable_irq(CXD56_IRQ_SDIO);
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_sendcmd
+ *
+ * Description:
+ *   Send the SDIO command
+ *
+ * Input Parameters:
+ *   dev  - An instance of the SDIO device interface
+ *   cmd  - The command to send (32-bits, encoded)
+ *   arg  - 32-bit argument required with some commands
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
+{
+#ifdef CONFIG_SDIO_DMA
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+#endif
+  uint32_t regval;
+  uint32_t cmdidx;
+  int32_t  timeout;
+
+  /* Initialize the command index */
+
+  cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT;
+  regval = cmdidx << SDHCI_XFERTYP_CMDINX_SHIFT;
+
+  /* Does a data transfer accompany the command? */
+
+  if ((cmd & MMCSD_DATAXFR) != 0)
+    {
+      /* Yes.. Configure the data transfer */
+
+      switch (cmd & MMCSD_DATAXFR_MASK)
+        {
+        default:
+        case MMCSD_NODATAXFR : /* No.. no data transfer */
+          break;
+
+          /* The following two cases are probably missing some setup logic */
+
+        case MMCSD_RDSTREAM :  /* Yes.. streaming read data transfer */
+          regval |= (SDHCI_XFERTYP_DPSEL | SDHCI_XFERTYP_DTDSEL);
+          break;
+
+        case MMCSD_WRSTREAM :  /* Yes.. streaming write data transfer */
+          regval |= SDHCI_XFERTYP_DPSEL;
+          break;
+
+        case MMCSD_RDDATAXFR : /* Yes.. normal read data transfer */
+          regval |= (SDHCI_XFERTYP_DPSEL | SDHCI_XFERTYP_DTDSEL);
+          break;
+
+        case MMCSD_WRDATAXFR : /* Yes.. normal write data transfer */
+          regval |= SDHCI_XFERTYP_DPSEL;
+          break;
+        }
+
+      /* Is it a multi-block transfer? */
+
+      if ((cmd & MMCSD_MULTIBLOCK) != 0)
+        {
+          /* Yes.. should the transfer be stopped with ACMD12? */
+
+          if ((cmd & MMCSD_STOPXFR) != 0)
+            {
+              /* Yes.. Indefinite block transfer */
+
+              regval |= (SDHCI_XFERTYP_MSBSEL | SDHCI_XFERTYP_AC12EN);
+            }
+          else
+            {
+              /* No.. Fixed block transfer */
+
+              regval |= (SDHCI_XFERTYP_MSBSEL | SDHCI_XFERTYP_BCEN);
+            }
+        }
+    }
+
+  /* Configure response type bits */
+
+  switch (cmd & MMCSD_RESPONSE_MASK)
+    {
+    case MMCSD_NO_RESPONSE:                /* No response */
+      regval |= SDHCI_XFERTYP_RSPTYP_NONE;
+      break;
+
+    case MMCSD_R1B_RESPONSE:              /* Response length 48, check busy & cmdindex */
+      regval |= (SDHCI_XFERTYP_RSPTYP_LEN48BSY | SDHCI_XFERTYP_CICEN |
+                 SDHCI_XFERTYP_CCCEN);
+      break;
+
+    case MMCSD_R1_RESPONSE:              /* Response length 48, check cmdindex */
+    case MMCSD_R5_RESPONSE:
+    case MMCSD_R6_RESPONSE:
+      regval |= (SDHCI_XFERTYP_RSPTYP_LEN48 | SDHCI_XFERTYP_CICEN |
+                 SDHCI_XFERTYP_CCCEN);
+      break;
+
+    case MMCSD_R2_RESPONSE:              /* Response length 136, check CRC */
+      regval |= (SDHCI_XFERTYP_RSPTYP_LEN136 | SDHCI_XFERTYP_CCCEN);
+      break;
+
+    case MMCSD_R3_RESPONSE:              /* Response length 48 */
+    case MMCSD_R4_RESPONSE:
+    case MMCSD_R7_RESPONSE:
+      regval |= SDHCI_XFERTYP_RSPTYP_LEN48;
+      break;
+    }
+
+  /* Enable DMA */
+
+#ifdef CONFIG_SDIO_DMA
+  /* Internal DMA is used */
+  priv->dmasend_prepare = false;
+  priv->dmasend_cmd = 0;
+  priv->dmasend_regcmd = 0;
+  if (((cmd & MMCSD_DATAXFR_MASK) != MMCSD_NODATAXFR) && priv->usedma)
+    {
+      regval |= SDHCI_XFERTYP_DMAEN;
+    }
+  else if (cmdidx == MMCSD_CMDIDX24 || cmdidx == MMCSD_CMDIDX25)
+    {
+      regval |= SDHCI_XFERTYP_DMAEN;
+      priv->usedma = true;
+      priv->dmasend_prepare = true;
+    }
+#endif
+
+  /* Other bits? What about CMDTYP? */
+
+  mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
+
+  /* The Command Inhibit (CIHB) bit is set in the PRSSTAT bit immediately
+   * after the transfer type register is written.  This bit is cleared when
+   * the command response is received.  If this status bit is 0, it
+   * indicates that the CMD line is not in use and the SDHC can issue a
+   * SD/MMC Command using the CMD line.
+   *
+   * CIHB should always be set when this function is called.
+   */
+
+  timeout = SDHCI_CMDTIMEOUT;
+  while ((getreg32(CXD56_SDHCI_PRSSTAT) & SDHCI_PRSSTAT_CIHB) != 0)
+    {
+      if (--timeout <= 0)
+        {
+          mcerr("ERROR: Timeout cmd: %08x PRSSTAT: %08x\n",
+               cmd, getreg32(CXD56_SDHCI_PRSSTAT));
+
+          return -EBUSY;
+        }
+    }
+
+  if ((cmd & MMCSD_DATAXFR_MASK) != MMCSD_NODATAXFR)
+    {
+      timeout = SDHCI_CMDTIMEOUT;
+      while ((getreg32(CXD56_SDHCI_PRSSTAT) & SDHCI_PRSSTAT_CDIHB) != 0)
+        {
+          if (--timeout <= 0)
+            {
+              mcerr("ERROR: Timeout cmd data: %08x PRSSTAT: %08x\n",
+                   cmd, getreg32(CXD56_SDHCI_PRSSTAT));
+
+              return -EBUSY;
+            }
+        }
+    }
+
+  /* Set the SDHC Argument value */
+  putreg32(arg, CXD56_SDHCI_CMDARG);
+
+  /* Clear interrupt status and write the SDHC CMD */
+  putreg32(SDHCI_RESPDONE_INTS, CXD56_SDHCI_IRQSTAT);
+#ifdef CONFIG_SDIO_DMA
+  priv->dma_cmd = cmd;
+  if (priv->dmasend_prepare)
+    {
+      priv->dmasend_regcmd = regval;
+      priv->dmasend_cmd = cmd;
+    }
+  else
+#endif
+    {
+      putreg32(regval, CXD56_SDHCI_XFERTYP);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_blocksetup
+ *
+ * Description:
+ *   Some hardward needs to be informed of the selected blocksize.
+ *
+ * Input Parameters:
+ *   dev      - An instance of the SDIO device interface
+ *   blocklen - The selected block size.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void cxd56_blocksetup(FAR struct sdio_dev_s *dev, unsigned int blocklen,
+                           unsigned int nblocks)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+  uint32_t regval;
+
+  DEBUGASSERT(dev != NULL && nblocks > 0 && nblocks < 65535);
+  DEBUGASSERT(blocklen < 65535);
+
+  priv->blocksize = blocklen;
+
+  /* Set the block size and count */
+
+  regval = (blocklen << SDHCI_BLKATTR_SIZE_SHIFT) |
+           (nblocks  << SDHCI_BLKATTR_CNT_SHIFT);
+  putreg32(regval, CXD56_SDHCI_BLKATTR);
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_recvsetup
+ *
+ * Description:
+ *   Setup hardware in preparation for data transfer from the card in non-DMA
+ *   (interrupt driven mode).  This method will do whatever controller setup
+ *   is necessary.  This would be called for SD memory just BEFORE sending
+ *   CMD13 (SEND_STATUS), CMD17 (READ_SINGLE_BLOCK), CMD18
+ *   (READ_MULTIPLE_BLOCKS), ACMD51 (SEND_SCR), etc.  Normally, SDIO_WAITEVENT
+ *   will be called to receive the indication that the transfer is complete.
+ *
+ * Input Parameters:
+ *   dev    - An instance of the SDIO device interface
+ *   buffer - Address of the buffer in which to receive the data
+ *   nbytes - The number of bytes in the transfer
+ *
+ * Returned Value:
+ *   Number of bytes sent on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
+                             size_t nbytes)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+
+  DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0);
+  DEBUGASSERT(((uint32_t)buffer & 3) == 0);
+
+#ifdef CONFIG_SDIO_DMA
+  priv->usedma = false;
+#endif
+
+  /* Reset the DPSM configuration */
+
+  cxd56_datadisable();
+  cxd56_sampleinit();
+  cxd56_sample(priv, SAMPLENDX_BEFORE_SETUP);
+
+  /* Save the destination buffer information for use by the interrupt handler */
+
+  priv->buffer    = (uint32_t *)buffer;
+  priv->remaining = nbytes;
+
+  /* Then set up the SDIO data path */
+
+  cxd56_dataconfig(priv, false, nbytes, 1, SDHCI_DTOCV_DATATIMEOUT);
+
+  /* And enable interrupts */
+
+  cxd56_configxfrints(priv, SDHCI_RCVDONE_INTS);
+  cxd56_sample(priv, SAMPLENDX_AFTER_SETUP);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_sendsetup
+ *
+ * Description:
+ *   Setup hardware in preparation for data transfer from the card.  This method
+ *   will do whatever controller setup is necessary.  This would be called
+ *   for SD memory just AFTER sending CMD24 (WRITE_BLOCK), CMD25
+ *   (WRITE_MULTIPLE_BLOCK), ... and before SDIO_SENDDATA is called.
+ *
+ * Input Parameters:
+ *   dev    - An instance of the SDIO device interface
+ *   buffer - Address of the buffer containing the data to send
+ *   nbytes - The number of bytes in the transfer
+ *
+ * Returned Value:
+ *   Number of bytes sent on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer,
+                           size_t nbytes)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+
+  DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0);
+  DEBUGASSERT(((uint32_t)buffer & 3) == 0);
+
+#ifdef CONFIG_SDIO_DMA
+  priv->usedma = false;
+#endif
+
+  /* Reset the DPSM configuration */
+
+  cxd56_datadisable();
+  cxd56_sampleinit();
+  cxd56_sample(priv, SAMPLENDX_BEFORE_SETUP);
+
+  /* Save the source buffer information for use by the interrupt handler */
+
+  priv->buffer    = (uint32_t *)buffer;
+  priv->remaining = nbytes;
+
+  /* Then set up the SDIO data path */
+
+  cxd56_dataconfig(priv, true, nbytes, 1, SDHCI_DTOCV_DATATIMEOUT);
+
+  /* Enable TX interrupts */
+
+  cxd56_configxfrints(priv, SDHCI_SNDDONE_INTS);
+  cxd56_sample(priv, SAMPLENDX_AFTER_SETUP);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_cancel
+ *
+ * Description:
+ *   Cancel the data transfer setup of SDIO_RECVSETUP, SDIO_SENDSETUP,
+ *   SDIO_DMARECVSETUP or SDIO_DMASENDSETUP.  This must be called to cancel
+ *   the data transfer setup if, for some reason, you cannot perform the
+ *   transfer.
+ *
+ * Input Parameters:
+ *   dev  - An instance of the SDIO device interface
+ *
+ * Returned Value:
+ *   OK is success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_cancel(FAR struct sdio_dev_s *dev)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+  uint32_t regval;
+
+#ifdef CONFIG_SDIO_DMA
+  /* Release allocated buffer */
+  if (priv->aligned_buffer)
+    {
+      /* Free aligned buffer */
+
+      kmm_free(priv->aligned_buffer);
+
+      priv->aligned_buffer = NULL;
+    }
+#endif
+
+  /* Disable all transfer- and event- related interrupts */
+
+  cxd56_configxfrints(priv, 0);
+  cxd56_configwaitints(priv, 0, 0, 0);
+
+  /* Clearing pending interrupt status on all transfer- and event- related
+   * interrupts
+   */
+
+  putreg32(SDHCI_WAITALL_INTS, CXD56_SDHCI_IRQSTAT);
+
+  /* Cancel any watchdog timeout */
+
+  (void)wd_cancel(priv->waitwdog);
+
+  /* If this was a DMA transfer, make sure that DMA is stopped */
+
+#ifdef CONFIG_SDIO_DMA
+  /* Stop the DMA by resetting the data path */
+
+  regval = getreg32(CXD56_SDHCI_SYSCTL);
+  regval |= SDHCI_SYSCTL_RSTD;
+  putreg32(regval, CXD56_SDHCI_SYSCTL);
+  priv->usedma = false;
+  priv->dmasend_prepare = false;
+  priv->dmasend_cmd = 0;
+  priv->dmasend_regcmd = 0;
+  cxd56_sdhci_adma_dscr[0] = 0;
+  cxd56_sdhci_adma_dscr[1] = 0;
+  putreg32((uint32_t)cxd56_sdhci_adma_dscr, CXD56_SDHCI_ADSADDR);
+  putreg32(0, CXD56_SDHCI_ADSADDR_H);
+#endif
+  regval  = getreg32(CXD56_SDHCI_SYSCTL);
+  regval |= SDHCI_SYSCTL_RSTC;
+  putreg32(regval, CXD56_SDHCI_SYSCTL);
+  regval = getreg32(CXD56_SDHCI_SYSCTL);
+  regval |= SDHCI_SYSCTL_RSTD;
+  putreg32(regval, CXD56_SDHCI_SYSCTL);
+
+  while ((getreg32(CXD56_SDHCI_SYSCTL) & SDHCI_SYSCTL_RSTC) != 0);
+  while ((getreg32(CXD56_SDHCI_SYSCTL) & SDHCI_SYSCTL_RSTD) != 0);
+
+  /* Mark no transfer in progress */
+  priv->remaining = 0;
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_waitresponse
+ *
+ * Description:
+ *   Poll-wait for the response to the last command to be ready.  This
+ *   function should be called even after sending commands that have no
+ *   response (such as CMD0) to make sure that the hardware is ready to
+ *   receive the next command.
+ *
+ * Input Parameters:
+ *   dev  - An instance of the SDIO device interface
+ *   cmd  - The command that was sent.  See 32-bit command definitions above.
+ *
+ * Returned Value:
+ *   OK is success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
+{
+  uint32_t errors;
+  int32_t  timeout = SDHCI_CMDTIMEOUT;
+  int      ret = OK;
+
+#ifdef CONFIG_SDIO_DMA
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+
+  if (priv->dmasend_prepare)
+    {
+      return OK;
+    }
+#endif
+
+  switch (cmd & MMCSD_RESPONSE_MASK)
+    {
+    case MMCSD_NO_RESPONSE:
+      timeout = SDHCI_CMDTIMEOUT;
+      errors  = 0;
+      return OK;
+
+    case MMCSD_R1_RESPONSE:
+    case MMCSD_R1B_RESPONSE:
+    case MMCSD_R2_RESPONSE:
+    case MMCSD_R6_RESPONSE:
+      timeout = SDHCI_LONGTIMEOUT;
+      errors  = SDHCI_RESPERR_INTS;
+      break;
+
+    case MMCSD_R4_RESPONSE:
+    case MMCSD_R5_RESPONSE:
+    case MMCSD_R3_RESPONSE:
+    case MMCSD_R7_RESPONSE:
+      timeout = SDHCI_CMDTIMEOUT;
+      errors  = SDHCI_RESPERR_INTS;
+      break;
+
+    default:
+      return -EINVAL;
+    }
+
+  /* Then wait for the Command Complete (CC) indication (or timeout).  The
+   * CC bit is set when the end bit of the command response is received
+   * (except Auto CMD12).
+   */
+
+  while ((getreg32(CXD56_SDHCI_IRQSTAT) & SDHCI_INT_CC) == 0)
+    {
+      timeout -= 1;
+      if (timeout <= 0)
+        {
+          mcerr("ERROR: Timeout cmd: %08x IRQSTAT: %08x\n",
+               cmd, getreg32(CXD56_SDHCI_IRQSTAT));
+          putreg32(0,CXD56_SDHCI_IRQSIGEN);
+
+          return -ETIMEDOUT;
+        }
+    }
+
+  /* Check for hardware detected errors */
+
+  if ((getreg32(CXD56_SDHCI_IRQSTAT) & errors) != 0)
+    {
+      mcerr("ERROR: cmd: %08x errors: %08x IRQSTAT: %08x\n",
+           cmd, errors, getreg32(CXD56_SDHCI_IRQSTAT));
+      ret = -EIO;
+    }
+
+  /* Clear the response wait status bits */
+  if ((cmd & MMCSD_DATAXFR_MASK) == MMCSD_NODATAXFR)
+    {
+      putreg32((SDHCI_INT_TC & getreg32(CXD56_SDHCI_IRQSTAT))| SDHCI_RESPDONE_INTS,
+               CXD56_SDHCI_IRQSTAT);
+    }
+  else
+    {
+      putreg32(SDHCI_RESPDONE_INTS, CXD56_SDHCI_IRQSTAT);
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_recvRx
+ *
+ * Description:
+ *   Receive response to SDIO command.  Only the critical payload is
+ *   returned -- that is 32 bits for 48 bit status and 128 bits for 136 bit
+ *   status.  The driver implementation should verify the correctness of
+ *   the remaining, non-returned bits (CRCs, CMD index, etc.).
+ *
+ * Input Parameters:
+ *   dev    - An instance of the SDIO device interface
+ *   Rx - Buffer in which to receive the response
+ *
+ * Returned Value:
+ *   Number of bytes sent on success; a negated errno on failure.  Here a
+ *   failure means only a faiure to obtain the requested reponse (due to
+ *   transport problem -- timeout, CRC, etc.).  The implementation only
+ *   assures that the response is returned intacta and does not check errors
+ *   within the response itself.
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
+                                uint32_t *rshort)
+{
+  uint32_t regval;
+  int ret = OK;
+#ifdef CONFIG_SDIO_DMA
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+#endif
+
+  /* R1  Command response (48-bit)
+   *     47        0               Start bit
+   *     46        0               Transmission bit (0=from card)
+   *     45:40     bit5   - bit0   Command index (0-63)
+   *     39:8      bit31  - bit0   32-bit card status
+   *     7:1       bit6   - bit0   CRC7
+   *     0         1               End bit
+   *
+   * R1b Identical to R1 with the additional busy signalling via the data
+   *     line.
+   *
+   * R6  Published RCA Response (48-bit, SD card only)
+   *     47        0               Start bit
+   *     46        0               Transmission bit (0=from card)
+   *     45:40     bit5   - bit0   Command index (0-63)
+   *     39:8      bit31  - bit0   32-bit Argument Field, consisting of:
+   *                               [31:16] New published RCA of card
+   *                               [15:0]  Card status bits {23,22,19,12:0}
+   *     7:1       bit6   - bit0   CRC7
+   *     0         1               End bit
+   */
+
+  if (rshort)
+    {
+      *rshort = 0;
+    }
+
+#ifdef CONFIG_SDIO_DMA
+  if (priv->dmasend_prepare)
+    {
+      return OK;
+    }
+#endif
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!rshort)
+    {
+      mcerr("ERROR: rshort=NULL\n");
+      ret = -EINVAL;
+    }
+
+  /* Check that this is the correct response to this command */
+
+  else if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1_RESPONSE &&
+           (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE &&
+           (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE)
+    {
+      mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
+      ret = -EINVAL;
+    }
+  else
+#endif
+    {
+      /* Check if a timeout or CRC error occurred */
+
+      regval = getreg32(CXD56_SDHCI_IRQSTAT);
+      if ((regval & SDHCI_INT_CTOE) != 0)
+        {
+          mcerr("ERROR: Command timeout: %08x\n", regval);
+          ret = -ETIMEDOUT;
+        }
+      else if ((regval & SDHCI_INT_CCE) != 0)
+        {
+          mcerr("ERROR: CRC failure: %08x\n", regval);
+          ret = -EIO;
+        }
+    }
+
+  /* Return the R1/R1b/R6 response.  These responses are returned in
+   * CDMRSP0.  NOTE: This is not true for R1b (Auto CMD12 response) which
+   * is returned in CMDRSP3.
+   */
+
+  *rshort = getreg32(CXD56_SDHCI_CMDRSP0);
+
+  return ret;
+}
+
+static int cxd56_sdio_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong[4])
+{
+  uint32_t regval;
+  int ret = OK;
+
+  /* R2  CID, CSD register (136-bit)
+   *     135       0               Start bit
+   *     134       0               Transmission bit (0=from card)
+   *     133:128   bit5   - bit0   Reserved
+   *     127:1     bit127 - bit1   127-bit CID or CSD register
+   *                               (including internal CRC)
+   *     0         1               End bit
+   */
+
+  if (rlong)
+    {
+      rlong[0] = 0;
+      rlong[1] = 0;
+      rlong[2] = 0;
+      rlong[3] = 0;
+    }
+#ifdef CONFIG_DEBUG_FEATURES
+  /* Check that R1 is the correct response to this command */
+
+  if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE)
+    {
+      mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
+      ret = -EINVAL;
+    }
+  else
+#endif
+    {
+      /* Check if a timeout or CRC error occurred */
+
+      regval = getreg32(CXD56_SDHCI_IRQSTAT);
+      if (regval & SDHCI_INT_CTOE)
+        {
+          mcerr("ERROR: Timeout IRQSTAT: %08x\n", regval);
+          ret = -ETIMEDOUT;
+        }
+      else if (regval & SDHCI_INT_CCE)
+        {
+          mcerr("ERROR: CRC fail IRQSTAT: %08x\n", regval);
+          ret = -EIO;
+        }
+    }
+
+  /* Return the long response in CMDRSP3..0 */
+
+  if (rlong)
+    {
+      rlong[0] = getreg32(CXD56_SDHCI_CMDRSP3);
+      rlong[1] = getreg32(CXD56_SDHCI_CMDRSP2);
+      rlong[2] = getreg32(CXD56_SDHCI_CMDRSP1);
+      rlong[3] = getreg32(CXD56_SDHCI_CMDRSP0);
+    }
+  if (1)
+    {
+      rlong[0] = ((rlong[0] << 8) & 0xffffff00) | ((rlong[1] >> 24) & 0x000000FF);
+      rlong[1] = ((rlong[1] << 8) & 0xffffff00) | ((rlong[2] >> 24) & 0x000000FF);
+      rlong[2] = ((rlong[2] << 8) & 0xffffff00) | ((rlong[3] >> 24) & 0x000000FF);
+      rlong[3] = (rlong[3] << 8)  & 0xffffff00;
+    }
+  return ret;
+}
+
+static int cxd56_sdio_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort)
+{
+  uint32_t regval;
+  int ret = OK;
+
+  /* R3  OCR (48-bit)
+   *     47        0               Start bit
+   *     46        0               Transmission bit (0=from card)
+   *     45:40     bit5   - bit0   Reserved
+   *     39:8      bit31  - bit0   32-bit OCR register
+   *     7:1       bit6   - bit0   Reserved
+   *     0         1               End bit
+   */
+
+  /* R4  Response (48-bit)
+   *     47        0               Start bit
+   *     46        0               Direction bit(0=card to host)
+   *     45:40     bit5   - bit0   Reserved
+   *     39        1               Set to 1 if Card is ready to operate after initialization
+   *     38:36     bit2   - bit0   Number of I/O functions
+   *     35        1               Memory Present
+   *     34:32     bit2   - bit0   Stuff Bits
+   *     31:8      bit23  - bit0   I/O OCR
+   *     7:1       bit6   - bit0   Reserved
+   *     0         1               End bit
+   */
+
+  /* R5  Response (48-bit)
+   *     47        0               Start bit
+   *     46        0               Direction bit(0=card to host)
+   *     45:40     bit5   - bit0   Command Index
+   *     39:24     bit15  - bit0   16-bit Stuff Bits
+   *     23:16     bit7   - bit0   Response Flags
+   *     15:8      bit7   - bit0   Read or Write Data
+   *     7:1       bit6   - bit0   CRC
+   *     0         1               End bit
+   */
+
+  if (!rshort)
+    {
+      *rshort = 0;
+    }
+  /* Check that this is the correct response to this command */
+#ifdef CONFIG_DEBUG_FEATURES
+  if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE &&
+      (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R4_RESPONSE &&
+      (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R5_RESPONSE &&
+      (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
+    {
+      mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
+      ret = -EINVAL;
+    }
+  else
+#endif
+    {
+      /* Check if a timeout occurred (Apparently a CRC error can terminate
+       * a good response)
+       */
+
+      regval = getreg32(CXD56_SDHCI_IRQSTAT);
+      if (regval & SDHCI_INT_CTOE)
+        {
+          mcerr("ERROR: Timeout IRQSTAT: %08x\n", regval);
+          ret = -ETIMEDOUT;
+        }
+    }
+
+  /* Return the short response in CMDRSP0 */
+
+  if (rshort)
+    {
+      *rshort = getreg32(CXD56_SDHCI_CMDRSP0);
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_waitenable
+ *
+ * Description:
+ *   Enable/disable of a set of SDIO wait events.  This is part of the
+ *   the SDIO_WAITEVENT sequence.  The set of to-be-waited-for events is
+ *   configured before calling cxd56_eventwait.  This is done in this way
+ *   to help the driver to eliminate race conditions between the command
+ *   setup and the subsequent events.
+ *
+ *   The enabled events persist until either (1) SDIO_WAITENABLE is called
+ *   again specifying a different set of wait events, or (2) SDIO_EVENTWAIT
+ *   returns.
+ *
+ * Input Parameters:
+ *   dev      - An instance of the SDIO device interface
+ *   eventset - A bitset of events to enable or disable (see SDIOWAIT_*
+ *              definitions). 0=disable; 1=enable.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void cxd56_sdio_waitenable(FAR struct sdio_dev_s *dev,
+                             sdio_eventset_t eventset)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+  uint32_t waitints;
+
+  DEBUGASSERT(priv != NULL);
+
+  /* Disable event-related interrupts */
+
+  cxd56_configwaitints(priv, 0, 0, 0);
+
+  /* Select the interrupt mask that will give us the appropriate wakeup
+   * interrupts.
+   */
+
+  waitints = 0;
+  if ((eventset & (SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE)) != 0)
+    {
+      waitints |= SDHCI_RESPDONE_INTS;
+    }
+
+  if ((eventset & SDIOWAIT_TRANSFERDONE) != 0)
+    {
+      waitints |= SDHCI_XFRDONE_INTS;
+    }
+
+  /* Enable event-related interrupts */
+
+  cxd56_configwaitints(priv, waitints, eventset, 0);
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_eventwait
+ *
+ * Description:
+ *   Wait for one of the enabled events to occur (or a timeout).  Note that
+ *   all events enabled by SDIO_WAITEVENTS are disabled when cxd56_eventwait
+ *   returns.  SDIO_WAITEVENTS must be called again before cxd56_eventwait
+ *   can be used again.
+ *
+ * Input Parameters:
+ *   dev     - An instance of the SDIO device interface
+ *   timeout - Maximum time in milliseconds to wait.  Zero means immediate
+ *             timeout with no wait.  The timeout value is ignored if
+ *             SDIOWAIT_TIMEOUT is not included in the waited-for eventset.
+ *
+ * Returned Value:
+ *   Event set containing the event(s) that ended the wait.  Should always
+ *   be non-zero.  All events are disabled after the wait concludes.
+ *
+ ****************************************************************************/
+
+static sdio_eventset_t cxd56_sdio_eventwait(FAR struct sdio_dev_s *dev,
+                                       uint32_t timeout)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+  sdio_eventset_t wkupevent = 0;
+  int ret;
+
+  /* There is a race condition here... the event may have completed before
+   * we get here.  In this case waitevents will be zero, but wkupevents will
+   * be non-zero (and, hopefully, the semaphore count will also be non-zero.
+   */
+
+  DEBUGASSERT((priv->waitevents != 0 && priv->wkupevent == 0) ||
+              (priv->waitevents == 0 && priv->wkupevent != 0));
+
+  /* Check if the timeout event is specified in the event set */
+
+  if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0)
+    {
+      int delay;
+
+      /* Yes.. Handle a corner case */
+
+      if (!timeout)
+        {
+          return SDIOWAIT_TIMEOUT;
+        }
+
+      /* Start the watchdog timer */
+
+      delay = MSEC2TICK(timeout);
+      ret   = wd_start(priv->waitwdog, delay, (wdentry_t)cxd56_eventtimeout,
+                       1, (uint32_t)priv);
+      if (ret != OK)
+        {
+          mcerr("ERROR: wd_start failed: %d\n", ret);
+        }
+    }
+
+  /* Loop until the event (or the timeout occurs). Race conditions are avoided
+   * by calling cxd56_waitenable prior to triggering the logic that will cause
+   * the wait to terminate.  Under certain race conditions, the waited-for
+   * may have already occurred before this function was called!
+   */
+
+  for (; ; )
+    {
+      /* Wait for an event in event set to occur.  If this the event has already
+       * occurred, then the semaphore will already have been incremented and
+       * there will be no wait.
+       */
+
+      cxd56_takesem(priv);
+      wkupevent = priv->wkupevent;
+
+      /* Check if the event has occurred.  When the event has occurred, then
+       * evenset will be set to 0 and wkupevent will be set to a non-zero value.
+       */
+
+      if (wkupevent != 0)
+        {
+          /* Yes... break out of the loop with wkupevent non-zero */
+          if (wkupevent & ( SDIOWAIT_RESPONSEDONE | SDIOWAIT_TRANSFERDONE))
+            {
+              if (priv->remaining > 0)
+                {
+                  priv->remaining = 0;
+                }
+            }
+          if (wkupevent & (SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR))
+            {
+              cxd56_sdio_cancel(&(priv->dev));
+            }
+          break;
+        }
+    }
+
+
+  /* Disable event-related interrupts */
+
+  cxd56_configwaitints(priv, 0, 0, 0);
+#ifdef CONFIG_SDIO_DMA
+  priv->xfrflags   = 0;
+  if (priv->aligned_buffer)
+    {
+      if (priv->dma_cmd == MMCSD_CMD17 || priv->dma_cmd == MMCSD_CMD18)
+        {
+          /* Copy receive buffer from aligned address */
+
+          memcpy(priv->receive_buffer, priv->aligned_buffer, priv->receive_size);
+        }
+
+      /* Free aligned buffer */
+
+      kmm_free(priv->aligned_buffer);
+
+      priv->aligned_buffer = NULL;
+    }
+#endif
+
+  cxd56_dumpsamples(priv);
+  return wkupevent;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_callbackenable
+ *
+ * Description:
+ *   Enable/disable of a set of SDIO callback events.  This is part of the
+ *   the SDIO callback sequence.  The set of events is configured to enabled
+ *   callbacks to the function provided in cxd56_registercallback.
+ *
+ *   Events are automatically disabled once the callback is performed and no
+ *   further callback events will occur until they are again enabled by
+ *   calling this method.
+ *
+ * Input Parameters:
+ *   dev      - An instance of the SDIO device interface
+ *   eventset - A bitset of events to enable or disable (see SDIOMEDIA_*
+ *              definitions). 0=disable; 1=enable.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void cxd56_sdio_callbackenable(FAR struct sdio_dev_s *dev,
+                                 sdio_eventset_t eventset)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+
+  mcinfo("eventset: %02x\n", eventset);
+  DEBUGASSERT(priv != NULL);
+
+  priv->cbevents = eventset;
+  cxd56_sdio_callback(priv);
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_registercallback
+ *
+ * Description:
+ *   Register a callback that that will be invoked on any media status
+ *   change.  Callbacks should not be made from interrupt handlers, rather
+ *   interrupt level events should be handled by calling back on the work
+ *   thread.
+ *
+ *   When this method is called, all callbacks should be disabled until they
+ *   are enabled via a call to SDIO_CALLBACKENABLE
+ *
+ * Input Parameters:
+ *   dev -      Device-specific state data
+ *   callback - The function to call on the media change
+ *   arg -      A caller provided value to return with the callback
+ *
+ * Returned Value:
+ *   0 on success; negated errno on failure.
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_registercallback(FAR struct sdio_dev_s *dev,
+                                  worker_t callback, void *arg)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+
+  /* Disable callbacks and register this callback and is argument */
+
+  mcinfo("Register %p(%p)\n", callback, arg);
+  DEBUGASSERT(priv != NULL);
+
+  priv->cbevents = 0;
+  priv->cbarg    = arg;
+  priv->callback = callback;
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_admasetup
+ *
+ * Description:
+ *   Setup to perform ADMA.  If the processor supports a data cache,
+ *   then this method will also make sure that the contents of the DMA memory
+ *   and the data cache are coherent.
+ *
+ * Input Parameters:
+ *   buffer - The memory to/from DMA
+ *   buflen - The size of the DMA transfer in bytes
+ *
+ * Returned Value:
+ *   OK on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SDIO_DMA
+static int cxd56_sdio_admasetup(FAR const uint8_t *buffer, size_t buflen)
+{
+  uint32_t dscr_top = (uint32_t)cxd56_sdhci_adma_dscr;
+  uint32_t dscr_l;
+  uint32_t i, remaining, len;
+  uint32_t data_addr = (uint32_t)buffer;
+  remaining = buflen;
+
+  putreg32(0x0, CXD56_SDHCI_ADSADDR_H);
+  putreg32(dscr_top, CXD56_SDHCI_ADSADDR);
+  for (i=0;i 0)
+    {
+      return -EIO;
+    }
+  else
+    {
+      return OK;
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: cxd56_sdio_dmarecvsetup
+ *
+ * Description:
+ *   Setup to perform a read DMA.  If the processor supports a data cache,
+ *   then this method will also make sure that the contents of the DMA memory
+ *   and the data cache are coherent.  For read transfers this may mean
+ *   invalidating the data cache.
+ *
+ * Input Parameters:
+ *   dev    - An instance of the SDIO device interface
+ *   buffer - The memory to DMA from
+ *   buflen - The size of the DMA transfer in bytes
+ *
+ * Returned Value:
+ *   OK on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SDIO_DMA
+static int cxd56_sdio_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
+                              size_t buflen)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+  unsigned int blocksize;
+  int          ret = OK;
+
+  DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
+  DEBUGASSERT(((uint32_t)buffer & 3) == 0);
+
+  if ((uint32_t)buffer & 3)
+    {
+      if (priv->aligned_buffer)
+        {
+          /* If buffer not freed,  free it */
+
+          kmm_free(priv->aligned_buffer);
+
+          priv->aligned_buffer = NULL;
+        }
+
+      /* Allocate aligned buffer */
+
+      priv->aligned_buffer = (uint8_t *) kmm_malloc(sizeof(uint8_t) * buflen);
+
+      /* Keep receive buffer address */
+
+      priv->receive_buffer = buffer;
+
+      /* Keep receive data size */
+
+      priv->receive_size = buflen;
+
+      /* Switch to aligned buffer */
+
+      buffer = priv->aligned_buffer;
+    }
+
+  /* Reset the DPSM configuration */
+
+  cxd56_datadisable();
+
+  /* Begin sampling register values */
+
+  cxd56_sampleinit();
+  cxd56_sample(priv, SAMPLENDX_BEFORE_SETUP);
+
+  /* Save the destination buffer information for use by the interrupt handler */
+
+  priv->buffer    = (uint32_t *)buffer;
+  priv->remaining = buflen;
+
+  /* Then set up the SDIO data path */
+
+  blocksize = getreg32(CXD56_SDHCI_BLKATTR) & SDHCI_BLKATTR_SIZE_MASK;
+  if (blocksize == 0)
+    {
+      if (priv->blocksize != 0)
+        {
+          blocksize = priv->blocksize;
+        }
+      else
+        {
+          ret = -EIO;
+          goto error;
+        }
+    }
+  cxd56_dataconfig(priv, false,  blocksize, buflen / blocksize, SDHCI_DTOCV_DATATIMEOUT);
+
+  /* Configure the RX DMA */
+
+  cxd56_sdio_admasetup(buffer,  buflen);
+  priv->usedma = true;
+
+  cxd56_configxfrints(priv, SDHCI_DMADONE_INTS);
+  putreg32((uint32_t)buffer, CXD56_SDHCI_DSADDR);
+
+  /* Sample the register state */
+
+  cxd56_sample(priv, SAMPLENDX_AFTER_SETUP);
+  return OK;
+error:
+  /* Free allocated align buffer */
+
+  kmm_free(priv->aligned_buffer);
+
+  priv->aligned_buffer = NULL;
+  return ret;
+}
+#endif
+
+/****************************************************************************
+ * Name: cxd56_sdio_dmasendsetup
+ *
+ * Description:
+ *   Setup to perform a write DMA.  If the processor supports a data cache,
+ *   then this method will also make sure that the contents of the DMA memory
+ *   and the data cache are coherent.  For write transfers, this may mean
+ *   flushing the data cache.
+ *
+ * Input Parameters:
+ *   dev    - An instance of the SDIO device interface
+ *   buffer - The memory to DMA into
+ *   buflen - The size of the DMA transfer in bytes
+ *
+ * Returned Value:
+ *   OK on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SDIO_DMA
+static int cxd56_sdio_dmasendsetup(FAR struct sdio_dev_s *dev,
+                              FAR const uint8_t *buffer, size_t buflen)
+{
+  uint32_t r1;
+  int      ret = OK;
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+  unsigned int blocksize;
+
+  DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
+  DEBUGASSERT(((uint32_t)buffer & 3) == 0);
+
+  if ((uint32_t)buffer & 3)
+    {
+      if (priv->aligned_buffer)
+        {
+          /* If buffer not freed,  free it */
+
+          kmm_free(priv->aligned_buffer);
+
+          priv->aligned_buffer = NULL;
+        }
+
+      /* Allocate aligned buffer */
+
+      priv->aligned_buffer = (uint8_t *) kmm_malloc(sizeof(uint8_t) * buflen);
+
+      /* Copy buffer to aligned address */
+
+      memcpy(priv->aligned_buffer, buffer, buflen);
+
+      /* Switch to aligned buffer */
+
+      buffer = priv->aligned_buffer;
+    }
+
+  /* Reset the DPSM configuration */
+
+  cxd56_datadisable();
+
+  /* Begin sampling register values */
+
+  cxd56_sampleinit();
+  cxd56_sample(priv, SAMPLENDX_BEFORE_SETUP);
+
+  /* Save the source buffer information for use by the interrupt handler */
+
+  priv->buffer    = (uint32_t *)buffer;
+  priv->remaining = buflen;
+
+  /* Then set up the SDIO data path */
+
+  blocksize = getreg32(CXD56_SDHCI_BLKATTR) & SDHCI_BLKATTR_SIZE_MASK;
+  if (blocksize == 0)
+    {
+      if (priv->blocksize != 0)
+        {
+          blocksize = priv->blocksize;
+        }
+      else
+        {
+          ret = -EIO;
+          goto error;
+        }
+    }
+  cxd56_dataconfig(priv, true, blocksize, buflen / blocksize, SDHCI_DTOCV_DATATIMEOUT);
+
+  /* Configure the TX DMA */
+
+  cxd56_sdio_admasetup(buffer, buflen);
+  priv->usedma = true;
+  if (priv->dmasend_prepare)
+    {
+      putreg32(priv->dmasend_regcmd, CXD56_SDHCI_XFERTYP);
+      priv->dmasend_prepare = false;
+      cxd56_sdio_waitresponse(dev, priv->dmasend_cmd);
+      ret = cxd56_sdio_recvshortcrc(dev, priv->dmasend_cmd, &r1);
+      if (ret != OK)
+        {
+          goto error;
+        }
+    }
+
+  /* Sample the register state */
+
+  cxd56_sample(priv, SAMPLENDX_AFTER_SETUP);
+
+  /* Enable TX interrupts */
+
+  cxd56_configxfrints(priv, SDHCI_DMADONE_INTS);
+
+  return OK;
+error:
+  /* Free allocated align buffer */
+
+  kmm_free(priv->aligned_buffer);
+
+  priv->aligned_buffer = NULL;
+  return ret;
+}
+#endif
+
+/****************************************************************************
+ * Initialization/uninitialization/reset
+ ****************************************************************************/
+static inline void cxd56_sdio_poweron(void *arg)
+{
+  uint32_t regval;
+
+  /* Power ON for SDCARD */
+
+  regval = getreg32(CXD56_SDHCI_PROCTL);
+  regval |= 0xf << 8;
+  putreg32(regval, CXD56_SDHCI_PROCTL);
+
+  board_sdcard_pin_enable();
+}
+
+static inline void cxd56_sdio_poweroff(void *arg)
+{
+  uint32_t regval;
+
+  board_sdcard_pin_disable();
+
+  /* Power OFF for SDCARD */
+
+  regval = getreg32(CXD56_SDHCI_PROCTL);
+  regval &= ~(0x1 << 8);
+  putreg32(regval, CXD56_SDHCI_PROCTL);
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_callback
+ *
+ * Description:
+ *   Perform callback.
+ *
+ * Assumptions:
+ *   This function does not execute in the context of an interrupt handler.
+ *   It may be invoked on any user thread or scheduled on the work thread
+ *   from an interrupt handler.
+ *
+ ****************************************************************************/
+
+static void cxd56_sdio_callback(void *arg)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)arg;
+  uint32_t delay = 0;
+  irqstate_t flags;
+
+  /* Is a callback registered? */
+
+  DEBUGASSERT(priv != NULL);
+  mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
+        priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
+
+  flags = enter_critical_section();
+  if (priv->callback)
+    {
+      /* Yes.. Check for enabled callback events */
+
+      if ((priv->cdstatus & SDIO_STATUS_PRESENT) != 0)
+        {
+          /* Media is present.  Is the media inserted event enabled? */
+
+          if ((priv->cbevents & SDIOMEDIA_INSERTED) == 0)
+            {
+              /* No... return without performing the callback */
+
+              leave_critical_section(flags);
+              return;
+            }
+          /* Power ON for SDCARD */
+          cxd56_sdio_poweron(priv);
+          putreg32(SDHCI_INT_CINS, CXD56_SDHCI_IRQSTAT);
+          delay = SDHCI_WAIT_POWERON;
+        }
+      else
+        {
+          /* Media is not present.  Is the media eject event enabled? */
+
+          if ((priv->cbevents & SDIOMEDIA_EJECTED) == 0)
+            {
+              /* No... return without performing the callback */
+
+              leave_critical_section(flags);
+              return;
+            }
+          /* Power OFF for SDCARD */
+          cxd56_sdio_poweroff(arg);
+          putreg32(SDHCI_INT_CRM | SDHCI_INT_CINT, CXD56_SDHCI_IRQSTAT);
+          delay = SDHCI_WAIT_POWEROFF;
+        }
+
+      /* Perform the callback, disabling further callbacks.  Of course, the
+       * the callback can (and probably should) re-enable callbacks.
+       */
+
+      priv->cbevents = 0;
+      leave_critical_section(flags);
+
+      /* Callbacks cannot be performed in the context of an interrupt handler.
+       * If we are in an interrupt handler, then queue the callback to be
+       * performed later on the work thread.
+       */
+
+      if (up_interrupt_context())/* (1) */
+        {
+          /* Yes.. queue it */
+          work_cancel(HPWORK, &priv->cbwork);//
+          mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
+          (void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, delay);
+        }
+      else
+        {
+          /* No.. then just call the callback here */
+
+          up_mdelay(delay);
+          mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg);
+          priv->callback(priv->cbarg);
+        }
+    }
+}
+
+#ifdef CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION
+static void cxd56_sdio_takesem(FAR struct cxd56_sdiodev_s *priv)
+{
+  /* Take the semaphore, giving exclusive access to the driver (perhaps
+   * waiting)
+   */
+
+  while (sem_wait(&priv->sc.sem) != 0)
+    {
+      /* The only case that an error should occur here is if the wait was
+       * awakened by a signal.
+       */
+
+      ASSERT(errno == EINTR);
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_make_cmd52arg
+ *
+ * Description:
+ *   Create argument parameters for CMD52
+ *
+ ****************************************************************************/
+
+static uint32_t cxd56_sdio_make_cmd52arg(uint32_t addr, uint8_t val_w, FAR uint8_t * out,
+                                         int32_t write, uint32_t func_num)
+{
+  uint32_t arg = 0;
+
+  arg = write ? SDIO_CMD5253_WRITE : SDIO_CMD5253_READ;
+  arg |= func_num << SDIO_CMD5253_FUNC_SHIFT;
+  arg |= (write && out) ? 0x08000000 : 0x00000000;
+  arg |= addr << SDIO_CMD52_REG_SHIFT;
+  if (write)
+    {
+      arg |= (val_w & SDIO_CMD52_DATA_MASK) << 0;
+    }
+
+  return arg;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_make_cmd53arg
+ *
+ * Description:
+ *   Create argument parameters for CMD53
+ *
+ ****************************************************************************/
+
+static uint32_t cxd56_sdio_make_cmd53arg(int32_t write, uint32_t func_num,
+                                         uint32_t addr, int32_t incr_addr,
+                                         uint32_t blocks, uint32_t bytesz)
+{
+  uint32_t arg = 0;
+
+  arg = write ? SDIO_CMD5253_WRITE : SDIO_CMD5253_READ;
+  arg |= func_num << SDIO_CMD5253_FUNC_SHIFT;
+  arg |= incr_addr ? 0x04000000 : 0x00000000;
+  arg |= addr << SDIO_CMD52_REG_SHIFT;
+  if (blocks == 0)
+    {
+      arg |= (bytesz == 512) ? 0 : bytesz;        /* byte mode */
+    }
+  else
+    {
+      arg |= 0x08000000 | blocks; /* block mode */
+    }
+
+  return arg;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_sendcmdpoll
+ *
+ * Description:
+ *   Send a command and poll-wait for the response.
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_sendcmdpoll(FAR struct cxd56_sdiodev_s *priv, uint32_t cmd,
+                                  uint32_t arg)
+{
+  int ret;
+
+  /* Send the command */
+
+  ret = cxd56_sdio_sendcmd(&priv->dev, cmd, arg);
+  if (ret == OK)
+    {
+      /* Then poll-wait until the response is available */
+
+      ret = cxd56_sdio_waitresponse(&priv->dev, cmd);
+      if (ret != OK)
+        {
+          mcerr("ERROR: Wait for response to cmd: %08x failed: %d\n", cmd, ret);
+        }
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_readb_internal
+ *
+ * Description:
+ *   Read a byte of data.
+ *
+ ****************************************************************************/
+
+static uint32_t cxd56_sdio_readb_internal(FAR struct sdio_function_s * sf, uint32_t addr,
+                                          FAR uint8_t * rdata)
+{
+  uint32_t response;
+  uint32_t cmd52arg;
+  struct cxd56_sdiodev_s *priv = &g_sdhcdev;
+  int ret;
+
+  DEBUGASSERT((NULL != rdata) && (NULL != sf));
+
+  cmd52arg = cxd56_sdio_make_cmd52arg(addr, 0, NULL, 0, sf->number);
+  ret = cxd56_sdio_sendcmdpoll(priv, SDIO_ACMD52, cmd52arg /* SDIO_ADD16_RD_CMD52 */ );
+  if (ret == OK)
+    {
+      cxd56_sdio_recvshort(&priv->dev, SDIO_ACMD52, &response);
+      if (ret != OK)
+        {
+          mcerr("ERROR: Addr:0x%x, recv R5 error\n", addr);
+          goto READB_ERR;
+        }
+    }
+  else
+    {
+      mcerr("ERROR: Send cmd52 addr:0x%x error\n", addr);
+      goto READB_ERR;
+    }
+  if ((!CMD52_RESP_OK(response)) || (response == 0xffffffff))
+    {
+      mcerr("ERROR: Fail resp %u\n", response);
+      goto READB_ERR;
+    }
+  if (rdata)
+    {
+      *rdata = response & 0xff;
+    }
+
+  return 0;
+
+READB_ERR:
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_writeb_internal
+ *
+ * Description:
+ *   Write a byte of data.
+ *
+ ****************************************************************************/
+
+static uint32_t cxd56_sdio_writeb_internal(FAR struct sdio_function_s * sf, uint32_t addr, uint8_t data,
+                                           FAR uint8_t * rdata)
+{
+  uint32_t response;
+  uint32_t cmd52arg;
+  struct cxd56_sdiodev_s *priv = &g_sdhcdev;
+  int ret;
+
+  DEBUGASSERT(NULL != sf);
+
+  cmd52arg = cxd56_sdio_make_cmd52arg(addr, data, rdata, 1, 0);
+  ret = cxd56_sdio_sendcmdpoll(priv, SDIO_ACMD52, cmd52arg);
+  if (ret == OK)
+    {
+      cxd56_sdio_recvshort(&priv->dev, SDIO_ACMD52, &response);
+      if (ret != OK)
+        {
+          mcerr("ERROR: Addr:0x%x, recv R5 error\n", addr);
+          goto WRITEB_ERR;
+        }
+    }
+  else
+    {
+      mcerr("ERROR: Send cmd52 addr:0x%x error\n", addr);
+      goto WRITEB_ERR;
+    }
+  if ((!CMD52_RESP_OK(response)) || (response == 0xffffffff))
+    {
+      mcerr("ERROR: Fail resp %u\n", response);
+      goto WRITEB_ERR;
+    }
+  if (rdata)
+    {
+      *rdata = response & 0xff;
+    }
+
+  return 0;
+WRITEB_ERR:
+  return ret;
+}
+
+/****************************************************************************
+ * Name: mmcsd_io_changeclock
+ *
+ * Description:
+ *   change the sdio clock.
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_changeclock(FAR struct cxd56_sdiodev_s *priv)
+{
+  int ret;
+  uint32_t response = 0;
+
+  ret = cxd56_sdio_sendcmdpoll(priv, SDIO_ACMD52, 0x08<<9);
+  if (ret == OK)
+    {
+      cxd56_sdio_recvshort(&priv->dev, SDIO_ACMD52, &response);
+    }
+  else
+    {
+      mcerr("ERROR: Send cmd52, getclock error\n");
+      return ret;
+    }
+#if 0
+    mcinfo("Force 400Khz SDIO clock\n");
+    if (TRUE || (response & 0x40) != 0)
+#else
+    if ((response & 0x40) != 0)
+#endif
+    {
+      mcinfo("Set clock to 400KHz\n");
+      cxd56_sdio_clock(&priv->dev, CLOCK_IDMODE);
+    }
+  else
+    {
+      mcinfo("Set clock to 25MHz\n");
+      cxd56_sdio_clock(&priv->dev, CLOCK_SD_TRANSFER_4BIT);
+    }
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_function_alloc
+ *
+ * Description:
+ *   Allocate space for each function.
+ *
+ ****************************************************************************/
+
+static FAR struct sdio_function_s *cxd56_sdio_function_alloc(FAR struct sdio_softc_s *sc)
+{
+  FAR struct sdio_function_s *sf;
+
+  DEBUGASSERT(sc);
+  sf = (FAR struct sdio_function_s *)kmm_malloc(sizeof(struct sdio_function_s));
+  if (!sf)
+    {
+      mcerr("ERROR: Failed\n");
+      return NULL;
+    }
+  memset(sf, 0, sizeof(struct sdio_function_s));
+  sf->sc = sc;
+  sf->number = -1;
+  sf->cis.manufacturer = 0xffff;
+  sf->cis.product = 0xffff;
+  sf->cis.function = 0xff;
+  sf->irq_callback = NULL;
+  return sf;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_read_cis
+ *
+ * Description:
+ *   Read the card information structure.
+ *
+ ****************************************************************************/
+
+static uint32_t cxd56_sdio_read_cis(FAR struct sdio_function_s * sf, FAR struct sdio_cis_s * cis)
+{
+  int i;
+  FAR struct sdio_function_s *sf0;
+  uint8_t tplcode;
+  uint8_t tpllen;
+  uint32_t ret;
+  uint32_t cisptr = 0;
+  uint8_t response = 0;
+  uint32_t addr;
+
+  mcinfo("I/O func's num:%d\n", sf->number);
+
+  DEBUGASSERT(sf && cis);
+  sf0 = sf->sc->fn[0];
+  addr = SDIO_CCCR_CCP + (sf->number * SDIO_CCCR_SIZE);
+  for(i=0; i<3; i++)
+  {
+    ret = cxd56_sdio_readb_internal(sf0, (addr+i), &response);
+    if (ret == 0)
+    {
+      cisptr |= (response << (8*i));
+    }
+  }
+  if ((cisptr < SDIO_CIS_START) || (cisptr >= SDIO_CIS_END))
+    {
+      mcerr("ERROR: Bad cis ptr %#x\n", cisptr);
+      return 1;
+    }
+  for(;;)
+    {
+      ret = cxd56_sdio_readb_internal(sf0, cisptr++, &tplcode);
+      if (ret != 0)
+        {
+          return ret;
+        }
+      if (tplcode == SDIO_CISTPL_END)
+        {
+          break;
+        }
+      else if (tplcode == SDIO_CISTPL_NULL)
+        {
+          continue;
+        }
+      ret = cxd56_sdio_readb_internal(sf0, cisptr++, &tpllen);
+      if (ret != 0)
+        {
+          return ret;
+        }
+      if (tpllen == 0)
+        {
+          mcerr("ERROR: Cis error reg %d tpl %#x len %d\n", cisptr, tplcode, tpllen);
+          break;
+        }
+
+      switch (tplcode)
+        {
+          case SDIO_CISTPL_FUNCID:
+            if (tpllen < 2)
+              {
+                mcerr("ERROR: Bad funcid length\n");
+                cisptr += tpllen;
+                break;
+              }
+            ret = cxd56_sdio_readb_internal(sf0, cisptr++, &response);
+            if (ret != 0)
+              {
+                return ret;
+              }
+            cis->function = response;
+            cisptr += tpllen;
+            mcinfo("get funcid 0x%x, len %d\n", cis->function, tpllen);
+          break;
+          case SDIO_CISTPL_MANFID:
+            if (tpllen < 4)
+              {
+                mcerr("ERROR: Bad manfid length\n");
+                cisptr += tpllen;
+                break;
+              }
+            ret = cxd56_sdio_readb_internal(sf0, cisptr++, &response);
+            if (ret != 0)
+              {
+                return ret;
+              }
+            cis->manufacturer = response;
+            ret = cxd56_sdio_readb_internal(sf0, cisptr++, &response);
+            if (ret != 0)
+              {
+                return ret;
+              }
+            cis->manufacturer |= response << 8;
+            ret = cxd56_sdio_readb_internal(sf0, cisptr++, &response);
+            if (ret != 0)
+              {
+                return ret;
+              }
+            cis->product = response;
+            ret = cxd56_sdio_readb_internal(sf0, cisptr++, &response);
+            if (ret != 0)
+              {
+                return ret;
+              }
+            cis->product = response << 8;
+            mcinfo("manufacturer/product ID: %x:%x, len %d\n",
+                   cis->manufacturer,
+                   cis->product,
+                   tpllen);
+          break;
+          default:
+          mcinfo("unknown tuple code %#x, length %d\n", tplcode, tpllen);
+          cisptr += tpllen;
+          break;
+        }
+    }
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_enable_cardint
+ *
+ * Description:
+ *   Enable the card interrupt bit of the CXD56_SDHCI_IRQSIGEN and
+ *   CXD56_SDHCI_IRQSTATEN register.
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_enable_cardint(void)
+{
+  irqstate_t flags;
+
+  flags = enter_critical_section();
+  putreg32(getreg32(CXD56_SDHCI_IRQSIGEN) | SDHCI_INT_CINT, CXD56_SDHCI_IRQSIGEN);
+  putreg32(getreg32(CXD56_SDHCI_IRQSTATEN) | SDHCI_INT_CINT, CXD56_SDHCI_IRQSTATEN);
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdhci_irq_handler
+ *
+ * Description:
+ *   Wait for the card interrupt and run the function's irq callback.
+ *
+ ****************************************************************************/
+
+static int cxd56_sdhci_irq_handler(FAR struct sdio_dev_s *dev)
+{
+  int ret = 0;
+  FAR struct sdio_softc_s *sc;
+  FAR struct sdio_function_s *sf0;
+  FAR struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+  uint8_t response;
+  int i;
+
+  sc = &priv->sc;
+  sf0 = priv->sc.fn[0];
+  ret = cxd56_sdio_readb_internal(sf0, SDIO_CCCR_INTPEND, &response);
+  for (i=1; i<8; i++)
+    {
+      if (response & (1<fn[i]->irq_callback)
+            {
+              sc->fn[i]->irq_callback(&priv->dev);
+            }
+        }
+    }
+  cxd56_sdio_enable_cardint();
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_register_irq
+ *
+ * Description:
+ *   Register the func interrupt handler.
+ *
+ * Input Parameters:
+ *   dev - An instance of the SDIO driver device state structure.
+ *   func_num - I/O Function's num
+ *   handler - The function's irq callback handler
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_register_irq(FAR struct sdio_dev_s *dev, int func_num,
+                                   FAR sdio_irqhandler_t * handler)
+{
+  int ret;
+  uint8_t reg, regorg;
+  FAR struct sdio_function_s *sf0;
+  FAR struct sdio_function_s *sf;
+  FAR struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+
+  DEBUGASSERT(handler);
+
+  sf = priv->sc.fn[func_num];
+  sf0 = priv->sc.fn[0];
+
+  if (NULL != sf->irq_callback)
+    {
+      mcerr("ERROR: Already registered a sdio callback, fn number: %d\n",
+                 sf->number);
+      return -EBUSY;
+    }
+  cxd56_sdio_takesem(priv);
+  /* enable irq in device side */
+  ret = cxd56_sdio_readb_internal(sf0, SDIO_CCCR_INTEN, ®);
+  if (ret)
+    {
+      goto REG_IRQ_FAIL;
+    }
+
+  sf->irq_callback = handler;
+
+  regorg = reg;
+  reg |= ((1 << sf->number) | (1 << 0));
+
+  ret = cxd56_sdio_writeb_internal(sf0, SDIO_CCCR_INTEN, reg, NULL);
+  if (ret)
+    {
+      cxd56_sdio_writeb_internal(sf0, SDIO_CCCR_INTEN, regorg, NULL);
+      goto REG_IRQ_FAIL;
+    }
+  sem_post(&priv->sc.sem);
+  return ret;
+
+REG_IRQ_FAIL:
+  sf->irq_callback = NULL;
+  mcerr("ERROR: Ret: %d\n", ret);
+  sem_post(&priv->sc.sem);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_blocksize
+ *
+ * Description:
+ *   Set I/O block size for Function.
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_blocksize(FAR struct sdio_function_s * sf, uint32_t size)
+{
+  uint32_t cmd52arg;
+  uint32_t blksz_addr;
+  struct cxd56_sdiodev_s *priv = &g_sdhcdev;
+
+  blksz_addr = sf->number * SDIO_FBR_START + 0x10;
+
+  cmd52arg = cxd56_sdio_make_cmd52arg(blksz_addr, (size & 0xFF), NULL, true, 0);
+  cxd56_sdio_sendcmdpoll(priv, SDIO_ACMD52, cmd52arg);
+
+  cmd52arg = cxd56_sdio_make_cmd52arg(blksz_addr+1, ((size >> 8) & 0xFF), NULL, true, 0);
+  cxd56_sdio_sendcmdpoll(priv, SDIO_ACMD52, cmd52arg);
+
+  return 0;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_func_ready
+ *
+ * Description:
+ *   Function will become ready, and FN0 is always ready.
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_func_ready(FAR struct sdio_function_s * sf)
+{
+  FAR struct sdio_softc_s *sc;
+  FAR struct sdio_function_s *sf0;
+  uint8_t rv;
+  int ret;
+
+  DEBUGASSERT(NULL != sf);
+  if (sf->number == 0)
+  {
+    return 1;                   /* FN0 is always ready */
+  }
+
+  sc = sf->sc;
+  sf0 = sc->fn[0];
+  ret = cxd56_sdio_readb_internal(sf0, SDIO_CCCR_IORDY, &rv);
+  if (0 == ret)
+    {
+      return (rv & (1 << sf->number)) != 0;
+    }
+  return 0;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_function_disable
+ *
+ * Description:
+ *   Function will be disabled, and FN0 is always enabled.
+ *
+ * Input Parameters:
+ *   dev - An instance of the SDIO driver device state structure.
+ *   func_num - I/O Function's num
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_function_disable(FAR struct sdio_dev_s *dev, int func_num)
+{
+  FAR struct sdio_function_s *sf0;
+  FAR struct sdio_function_s *sf;
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+  uint8_t rv;
+  int ret;
+
+  sf = priv->sc.fn[func_num];
+  sf0 = priv->sc.fn[0];
+  mcinfo("I/O func's num:%d\n", sf->number);
+
+  cxd56_sdio_takesem(priv);
+  ret = cxd56_sdio_readb_internal(sf0, SDIO_CCCR_IOEN, &rv);
+  if (ret)
+    {
+      goto FUNC_DIS_ERR;
+    }
+
+  rv &= ~(1 << sf->number);
+  ret = cxd56_sdio_writeb_internal(sf0, SDIO_CCCR_IOEN, rv, NULL);
+  if (ret)
+    {
+      goto FUNC_DIS_ERR;
+    }
+  sem_post(&priv->sc.sem);
+  return 0;
+FUNC_DIS_ERR:
+  mcerr("ERROR: Io fail ret %u\n", ret);
+  sem_post(&priv->sc.sem);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_function_enable
+ *
+ * Description:
+ *   Function will be enabled.
+ *
+ * Input Parameters:
+ *   dev - An instance of the SDIO driver device state structure.
+ *   func_num - I/O Function's num
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_function_enable(FAR struct sdio_dev_s *dev, int func_num)
+{
+  FAR struct sdio_function_s *sf0;
+  FAR struct sdio_function_s *sf;
+  uint8_t rv;
+  int retry = 10;
+  int ret = 0;
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+
+  sf = priv->sc.fn[func_num];
+  sf0 = priv->sc.fn[0];
+  mcinfo("I/O func's num:%d\n", sf->number);
+  if (sf->number == 0)
+    {
+      return 0;
+    }
+  cxd56_sdio_takesem(priv);
+  ret = cxd56_sdio_readb_internal(sf0, SDIO_CCCR_IOEN, &rv);
+  if (ret)
+    {
+      goto FUNC_EN_ERR;
+    }
+  rv |= (1 << sf->number);
+  /* according to sdio_rw_direct(), set NULL to rdata */
+  ret = cxd56_sdio_writeb_internal(sf0, SDIO_CCCR_IOEN, rv, NULL);
+  if (ret)
+    {
+      goto FUNC_EN_ERR;
+    }
+  cxd56_sdio_blocksize(sf, priv->blocksize);/* Optimize SDIO transmission speed, so set blocksize here */
+
+  while (!cxd56_sdio_func_ready(sf) && retry-- > 0)
+    {
+      up_udelay(5 * 1000);
+    }
+  ret = (retry >= 0) ? 0 : -ETIMEDOUT;
+
+  if (0 == ret)
+    {
+      sem_post(&priv->sc.sem);
+      return 0;
+    }
+FUNC_EN_ERR:
+  mcerr("ERROR: Io fail ret %u\n", ret);
+  sem_post(&priv->sc.sem);
+  return -EIO;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_readb
+ *
+ * Description:
+ *   Read a byte of data.
+ *
+ * Input Parameters:
+ *   dev - An instance of the SDIO driver device state structure.
+ *   func_num - I/O Function's num
+ *   addr - This is the address of the byte of data inside of the selected
+ *     function to read or write
+ *   rdata - the actual value read from that I/O location is returned
+ *     in this field
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_readb(FAR struct sdio_dev_s *dev, int func_num,
+                            uint32_t addr, FAR uint8_t * rdata)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+  int ret;
+
+  cxd56_sdio_takesem(priv);
+  ret = cxd56_sdio_readb_internal(priv->sc.fn[func_num], addr, rdata);
+  sem_post(&priv->sc.sem);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_writeb
+ *
+ * Description:
+ *   Write a byte of data.
+ *
+ * Input Parameters:
+ *   dev - An instance of the SDIO driver device state structure.
+ *   func_num - I/O Function's num
+ *   addr - This is the address of the byte of data inside of the selected
+ *     function to read or write
+ *   data - This is the byte that is written to the selected address
+ *   rdata - The value of the register after the write
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_writeb(FAR struct sdio_dev_s *dev, int func_num,
+                             uint32_t addr, uint8_t data, FAR uint8_t * rdata)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+  int ret;
+
+  cxd56_sdio_takesem(priv);
+  ret = cxd56_sdio_writeb_internal(priv->sc.fn[func_num], addr, data, rdata);
+  sem_post(&priv->sc.sem);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_write
+ *
+ * Description:
+ *   Write large number data.
+ *
+ * Input Parameters:
+ *   dev - An instance of the SDIO driver device state structure.
+ *   func_num - I/O Function's num
+ *   addr - Start Address of I/O register to write
+ *   data - This is the large number data that is written to the selected
+ *     address
+ *   size - The size of the written data
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_write(FAR struct sdio_dev_s *dev, int func_num, uint32_t addr,
+                            FAR uint8_t * data, uint32_t size)
+{
+  uint32_t remainder = size;
+  int ret;
+  uint32_t cmd53arg;
+  sdio_eventset_t wkupevent;
+  FAR struct sdio_function_s *sf;
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+
+  sf = priv->sc.fn[func_num];
+  mcinfo("sf->number = %d\n", sf->number);
+  /* Do the bulk of the transfer using block mode (if supported). */
+  cxd56_sdio_takesem(priv);
+  if (size >= SDIO_BLOCK_SIZE)
+    {
+      while (remainder >= SDIO_BLOCK_SIZE)
+        {
+          uint32_t blocks;
+          blocks = MIN(remainder / SDIO_BLOCK_SIZE, 8);
+          size = blocks * SDIO_BLOCK_SIZE;
+          cxd56_blocksetup(&priv->dev, SDIO_BLOCK_SIZE, blocks);
+          cxd56_sdio_waitenable(&priv->dev, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR);
+#ifdef CONFIG_SDIO_DMA
+          if (priv->sc.dma)
+            {
+              ret = cxd56_sdio_dmasendsetup(&priv->dev, data, size);
+              if (ret != OK)
+                {
+                  mcerr("ERROR: SDIO_DMASENDSETUP: error %d\n", ret);
+                  goto WRITE_ERR;
+                }
+            }
+          else
+#endif
+            {
+              cxd56_sdio_sendsetup(&priv->dev, data, size);
+            }
+          cmd53arg = cxd56_sdio_make_cmd53arg(1, sf->number, addr, 1, blocks, priv->blocksize);
+          ret = cxd56_sdio_sendcmdpoll(priv, SDIO_ACMD53 | MMCSD_MULTIBLOCK | MMCSD_WRDATAXFR, cmd53arg);
+          if (ret != OK)
+            {
+              mcerr("ERROR: Send cmd53 error\n");
+              goto WRITE_ERR;
+            }
+          wkupevent = cxd56_sdio_eventwait(&priv->dev, SDIO_BLOCK_TIMEOUT * blocks);
+          if ((wkupevent & (SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR)) != 0)
+            {
+              mcerr("ERROR: Sdio write time out %x\n", wkupevent);
+              goto WRITE_TIME_OUT;
+            }
+          remainder -= size;
+          data += size;
+          addr += size;
+        }
+    }
+
+  /* Write the remainder using byte mode. */
+  while (remainder > 0)
+    {
+      size = MIN(remainder, 64);
+      cxd56_blocksetup(&priv->dev, size, 1);
+      cxd56_sdio_waitenable(&priv->dev, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR);
+#ifdef CONFIG_SDIO_DMA
+      if (priv->sc.dma)
+        {
+          ret = cxd56_sdio_dmasendsetup(&priv->dev, data, size);
+          if (ret != OK)
+            {
+              mcerr("ERROR: SDIO_DMASENDSETUP: error %d\n", ret);
+              goto WRITE_ERR;
+            }
+        }
+      else
+#endif
+        {
+          cxd56_sdio_sendsetup(&priv->dev, data, size);
+        }
+      cmd53arg = cxd56_sdio_make_cmd53arg(1, sf->number, addr, 1, 0, size);
+      ret = cxd56_sdio_sendcmdpoll(priv, SDIO_ACMD53 | MMCSD_WRDATAXFR, cmd53arg);
+      if (ret != OK)
+        {
+          mcerr("ERROR: Send cmd53 error\n");
+          goto WRITE_ERR;
+        }
+      wkupevent = cxd56_sdio_eventwait(&priv->dev, SDIO_BLOCK_TIMEOUT);
+      if ((wkupevent & (SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR)) != 0)
+        {
+          mcerr("ERROR: Sdio write time out %x\n", wkupevent);
+          goto WRITE_TIME_OUT;
+        }
+      remainder -= size;
+      data += size;
+      addr += size;
+    }
+  sem_post(&priv->sc.sem);
+  return 0;
+WRITE_TIME_OUT:
+  sem_post(&priv->sc.sem);
+  return wkupevent & SDIOWAIT_TIMEOUT ? -ETIMEDOUT : -EIO;
+WRITE_ERR:
+  sem_post(&priv->sc.sem);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_read
+ *
+ * Description:
+ *   Read large number data.
+ *
+ * Input Parameters:
+ *   dev - An instance of the SDIO driver device state structure.
+ *   func_num - I/O Function's num
+ *   addr - Start Address of I/O register to read
+ *   data - the large number data read from that I/O location is returned
+ *     in this field
+ *   size - The size of the read data
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_read(FAR struct sdio_dev_s *dev, int func_num, uint32_t addr,
+                           FAR uint8_t * data, uint32_t size)
+{
+  uint32_t remainder = size;
+  int ret;
+  uint32_t cmd53arg;
+  sdio_eventset_t wkupevent;
+  FAR struct sdio_function_s *sf;
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+
+  sf = priv->sc.fn[func_num];
+  mcinfo("sf->number = %d\n", sf->number);
+  /* Do the bulk of the transfer using block mode (if supported). */
+  cxd56_sdio_takesem(priv);
+  if (size >= SDIO_BLOCK_SIZE)
+    {
+      while (remainder >= SDIO_BLOCK_SIZE)
+        {
+          uint32_t blocks;
+          blocks = MIN(remainder / SDIO_BLOCK_SIZE, 8);
+          size = blocks * SDIO_BLOCK_SIZE;
+          cxd56_blocksetup(&priv->dev, SDIO_BLOCK_SIZE, blocks);
+          cxd56_sdio_waitenable(&priv->dev, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR);
+#ifdef CONFIG_SDIO_DMA
+          if (priv->sc.dma)
+            {
+              ret = cxd56_sdio_dmarecvsetup(&priv->dev, data, size);
+              if (ret != OK)
+                {
+                  mcerr("ERROR: SDIO_DMASENDSETUP: error %d\n", ret);
+                  goto READ_ERR;
+                }
+            }
+          else
+#endif
+            {
+              cxd56_sdio_recvsetup(&priv->dev, data, size);
+            }
+          cmd53arg = cxd56_sdio_make_cmd53arg(0, sf->number, addr, 1, blocks, priv->blocksize);
+          ret = cxd56_sdio_sendcmdpoll(priv, SDIO_ACMD53 | MMCSD_MULTIBLOCK | MMCSD_RDDATAXFR, cmd53arg);
+          if (ret != OK)
+            {
+              mcerr("ERROR: Send cmd53 error\n");
+              goto READ_ERR;
+            }
+          wkupevent = cxd56_sdio_eventwait(&priv->dev, SDIO_BLOCK_TIMEOUT * blocks);
+          if ((wkupevent & (SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR)) != 0)
+            {
+              mcerr("ERROR: Sdio read time out %x\n", wkupevent);
+              goto READ_TIME_OUT;
+            }
+          remainder -= size;
+          data += size;
+          addr += size;
+        }
+    }
+
+  /* Write the remainder using byte mode. */
+  while (remainder > 0)
+    {
+      size = MIN(remainder, 64);
+      cxd56_blocksetup(&priv->dev, size, 1);
+      cxd56_sdio_waitenable(&priv->dev, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR);
+#ifdef CONFIG_SDIO_DMA
+      if (priv->sc.dma)
+        {
+          ret = cxd56_sdio_dmarecvsetup(&priv->dev, data, size);
+          if (ret != OK)
+            {
+              mcerr("ERROR: SDIO_DMASENDSETUP: error %d\n", ret);
+              goto READ_ERR;
+            }
+        }
+      else
+#endif
+        {
+          cxd56_sdio_recvsetup(&priv->dev, data, size);
+        }
+      cmd53arg = cxd56_sdio_make_cmd53arg(0, sf->number, addr, 1, 0, size);
+      ret = cxd56_sdio_sendcmdpoll(priv, SDIO_ACMD53 | MMCSD_RDDATAXFR, cmd53arg);
+      if (ret != OK)
+        {
+          mcerr("ERROR: Send cmd53 error\n");
+          goto READ_ERR;
+        }
+      wkupevent = cxd56_sdio_eventwait(&priv->dev, SDIO_BLOCK_TIMEOUT);
+      if ((wkupevent & (SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR)) != 0)
+        {
+          mcerr("ERROR: Sdio read time out %x\n", wkupevent);
+          goto READ_TIME_OUT;
+        }
+      remainder -= size;
+      data += size;
+      addr += size;
+    }
+  sem_post(&priv->sc.sem);
+  return 0;
+READ_TIME_OUT:
+  sem_post(&priv->sc.sem);
+  return wkupevent & SDIOWAIT_TIMEOUT ? -ETIMEDOUT : -EIO;
+READ_ERR:
+  sem_post(&priv->sc.sem);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_get_cis
+ *
+ * Description:
+ *   get SDIO Card Information Structure.
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_get_cis(FAR struct sdio_dev_s *dev, int func_num, FAR struct sdio_cis_s * cis)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+
+  if (cis)
+    {
+      *cis = priv->sc.fn[func_num]->cis;
+    }
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdio_initialize
+ *
+ * Description:
+ *   We believe that there is A sdio device in the slot.initialize the sdio
+ *   device.
+ *
+ ****************************************************************************/
+
+static int cxd56_sdio_initialize(struct cxd56_sdiodev_s *priv)
+{
+  int ret, i;
+  uint32_t response;
+  FAR struct sdio_function_s *fn;
+
+  priv->sc.func_num = 1;
+  priv->sc.full_speed = false;
+  priv->blocksize = SDIO_BLOCK_SIZE;
+
+  sem_init(&priv->sc.sem, 0, 1);
+#ifdef CONFIG_SDIO_DMA
+  priv->sc.dma = true;
+#endif
+  cxd56_sdio_attach(&priv->dev);
+  ret = cxd56_sdio_sendcmdpoll(priv, SDIO_CMD5, 0x0);
+
+  if (ret == OK)
+    {
+      ret = cxd56_sdio_recvshort(&priv->dev, SDIO_CMD5, &response);
+      if (ret != OK)
+        {
+          mcerr("ERROR: Recv R4 error\n");
+          return ret;
+        }
+    }
+  else
+    {
+      mcerr("ERROR: Send cmd5 error\n");
+      return ret;
+    }
+  mcinfo("response = 0x%x, card has %d function\n", response, (response >> 28) & 7);
+  mcinfo("send cmd5 again to set card ready\n");
+  if (response != 0xffffffff)
+    {
+      do
+        {
+          ret = cxd56_sdio_sendcmdpoll(priv, SDIO_CMD5, 0x300000);
+          if (ret == OK)
+            {
+              cxd56_sdio_recvshort(&priv->dev, SDIO_CMD5, &response);
+            }
+          usleep(4000);
+        }
+      while ((response == 0xffffffff) ||
+                ((response & 0x80000000) == 0));
+      mcinfo("response = 0x%x, card is ready(MSB=1)\n", response);
+      priv->sc.func_num = SDIO_OCR_NUM_FUNCTIONS(response) + 1;
+    }
+  mcinfo("send CMD3 to enter standby state\n");
+  cxd56_sdio_sendcmdpoll(priv, SD_CMD3, 0);
+  ret = cxd56_sdio_recvshortcrc(&priv->dev, SD_CMD3, &response);
+  if (ret != OK)
+    {
+      return ret;
+    }
+
+  mcinfo("RCA: 0x%x\n", (response >> 16));
+  if (response & 0xffff)
+    {
+      mcerr("ERROR: CMD3 resp error: 0x%x\n", (response & 0xffff));
+      if (response & 0x8000)
+        mcerr("ERROR: CRC error on previous command\n");
+    }
+
+  cxd56_sdio_sendcmdpoll(priv, MMCSD_CMD7S, response & 0xffff0000);
+  mcinfo("send cmd7(RCA:%x, %x) OK\n", (response >> 16), response & 0xffff0000);
+  ret = cxd56_sdio_recvshortcrc(&priv->dev, MMCSD_CMD7S, &response);
+  if (ret != OK)
+    {
+      mcerr("ERROR: mmcsd_recvR1 for CMD7 failed: %d\n", ret);
+      return ret;
+    }
+
+  cxd56_sdio_changeclock(priv);
+
+  ret = cxd56_sdio_sendcmdpoll(priv, SDIO_ACMD52, 0x7<<9);
+  if (ret == OK)
+    {
+      ret = cxd56_sdio_recvshort(&priv->dev, SDIO_ACMD52, &response);
+      if (ret != OK)
+        {
+          mcerr("ERROR: Addr:0x7, recv R5 error\n");
+          return ret;
+        }
+      mcinfo("Bus interface ctrl (@0x7):0x%x\n", response);
+      // 0x80: CD disable = 1, we should set it be true before issue CMD53
+      cxd56_sdio_sendcmdpoll(priv, SDIO_ACMD52, 0x7<<9 | (response & 0xFF) | 0x80);
+      mcinfo("set CD disable = 1\n");
+    }
+  else
+    {
+      mcerr("ERROR: Send cmd52 addr:0x7 error\n");
+      return ret;
+    }
+
+  ret = cxd56_sdio_sendcmdpoll(priv, SDIO_ACMD52, 0x8<<9);
+  if (ret == OK)
+    {
+      cxd56_sdio_recvshort(&priv->dev, SDIO_ACMD52, &response);
+      if (ret != OK)
+        {
+          mcerr("ERROR: Addr:0x8, recv R5 error\n");
+          return ret;
+        }
+      mcinfo("Card capability(@0x8):0x%x\n", response);
+
+      mcinfo("It's a %s card\n", (response & 0x40)? "low speed": "full speed");
+      if ((response & 0x40) == 0)
+        {
+          priv->sc.full_speed = true;
+        }
+    }
+  else
+    {
+      mcerr("ERROR: Send cmd52 addr:0x8 error\n");
+      return ret;
+    }
+
+  mcinfo("func_num = %d\n", priv->sc.func_num);
+  for (i = 0; i < priv->sc.func_num; i++)
+    {
+      fn = cxd56_sdio_function_alloc(&priv->sc);
+      if (!fn)
+        {
+          goto SDIO_INIT_ERR;
+        }
+      fn->number = i;
+
+      priv->sc.fn[i] = fn;
+    }
+
+  for (i = 1; i < priv->sc.func_num; i++)
+    {
+      fn = priv->sc.fn[i];
+      if (cxd56_sdio_read_cis(fn, &fn->cis) != 0)
+        {
+          mcerr("ERROR: Can't read CIS\n");
+          goto SDIO_INIT_CIS_ERR;
+        }
+    }
+
+  if (priv->sc.full_speed)
+    {
+      uint8_t bus_ctrl;
+
+      /* enable 4-bits bus */
+      cxd56_sdio_readb_internal(priv->sc.fn[0], SDIO_CCCR_BUS_IF, &bus_ctrl);
+      bus_ctrl = (bus_ctrl & ~0x3) | 0x2;
+      cxd56_sdio_writeb_internal(priv->sc.fn[0], SDIO_CCCR_BUS_IF, bus_ctrl, &bus_ctrl);
+
+      if ((bus_ctrl & 0x3) == 2)
+        {
+          mcinfo("Set card to 4-bits mode\n");
+          cxd56_sdio_widebus(&priv->dev, true);
+          mcinfo("Set controller to 4-bits mode\n");
+        }
+      else
+        {
+          mcinfo("Failed to enter 4-bits mode\n");
+        }
+    }
+
+  return OK;
+
+SDIO_INIT_ERR:
+  return -ENOMEM;
+
+SDIO_INIT_CIS_ERR:
+  return -EIO;
+}
+#endif /* CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_sdhci_initialize
+ *
+ * Description:
+ *   Initialize SDIO for operation.
+ *
+ * Input Parameters:
+ *   slotno - Not used.
+ *
+ * Returned Values:
+ *   A reference to an SDIO interface structure.  NULL is returned on failures.
+ *
+ ****************************************************************************/
+
+FAR struct sdio_dev_s *cxd56_sdhci_initialize(int slotno)
+{
+  uint32_t regval;
+#ifdef CONFIG_SDIO_DMA
+  uint32_t i;
+#endif
+
+  /* There is only one slot */
+
+  struct cxd56_sdiodev_s *priv = &g_sdhcdev;
+  DEBUGASSERT(slotno == 0);
+
+  /* Initalize the pins */
+
+  board_sdcard_pin_initialize();
+
+  /* Enable clocking to the SDHC module.  Clocking is still disabled in
+   * the SYSCTRL register.
+   */
+
+  cxd56_sdio_clock_enable();
+
+  //putreg32(getreg32(CXD56_SDHCI_BASE+0x230) >> 3 ,CXD56_SDHCI_BASE+0x230);
+  putreg32(getreg32(CXD56_SDHCI_SYSCTL) | SDHCI_SYSCTL_ICLKEN, CXD56_SDHCI_SYSCTL);
+
+  /* Command Line Pre Drive Enable */
+  regval = getreg32(CXD56_SDHCI_VENDSPEC);
+  putreg32(regval | 0x00000040, CXD56_SDHCI_VENDSPEC);
+
+  /* Configure the pins */
+
+  board_sdcard_pin_configuraton();
+
+  /* Software reset */
+  regval = getreg32(CXD56_SDHCI_SYSCTL);
+  putreg32(regval | SDHCI_SYSCTL_RSTA, CXD56_SDHCI_SYSCTL);
+  while ((getreg32(CXD56_SDHCI_SYSCTL) & SDHCI_SYSCTL_RSTA) != 0);
+
+  putreg32(0xffffffff, CXD56_SDHCI_IRQSTATEN);
+
+  cxd56_sdio_sdhci_reset(&(priv->dev));
+
+#ifdef CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION
+  /* Power ON for SDIO */
+
+  regval = getreg32(CXD56_SDHCI_PROCTL);
+  regval |= 0xf << 8;
+  putreg32(regval, CXD56_SDHCI_PROCTL);
+
+  up_mdelay(25);
+
+  /* SD clock enable */
+
+  cxd56_sdio_clock(&(priv->dev), CLOCK_IDMODE);
+#endif /* CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION */
+
+#ifdef CONFIG_SDIO_DMA
+  for(i=0;iusedma = false;
+  priv->dmasend_prepare = false;
+  priv->dmasend_cmd = 0;
+  priv->dmasend_regcmd = 0;
+
+#endif
+
+#ifdef CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION
+  cxd56_sdio_initialize(priv);
+#endif /* CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION */
+
+  /* In addition to the system clock, the SDHC module needs a clock for the
+   * base for the external card clock.  There are four possible sources for
+   * this clock, selected by the SIM's SOPT2 register:
+   *
+   * - Core/system clock
+   * - MCGPLLCLK/MCGFLLCLK clock
+   * - OSCERCLK EXTAL clock
+   * - External bypass clock from off-chip (SCHC0_CLKINB)
+   */
+
+  return &g_sdhcdev.dev;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_sdhci_finalize
+ *
+ * Description:
+ *   Finalize SDIO for operation.
+ *
+ * Input Parameters:
+ *   slotno - Not used.
+ *
+ * Returned Values:
+ *   A reference to an SDIO interface structure.  NULL is returned on failures.
+ *
+ ****************************************************************************/
+
+FAR struct sdio_dev_s *cxd56_sdhci_finalize(int slotno)
+{
+  uint32_t regval;
+
+  /* There is only one slot */
+
+  struct cxd56_sdiodev_s *priv = &g_sdhcdev;
+  DEBUGASSERT(slotno == 0);
+
+  /* Enable clocking to the SDHC module.  Clocking is still disabled in
+   * the SYSCTRL register.
+   */
+
+  /* SD clock disable */
+
+  cxd56_sdio_clock(&(priv->dev), CLOCK_SDIO_DISABLED);
+
+  /* Power OFF for SDIO */
+
+  regval = getreg32(CXD56_SDHCI_PROCTL);
+  regval &= ~(0xf << 8);
+  putreg32(regval, CXD56_SDHCI_PROCTL);
+
+  /* Disable Internal Clock */
+
+  putreg32(getreg32(CXD56_SDHCI_SYSCTL) & ~SDHCI_SYSCTL_ICLKEN, CXD56_SDHCI_SYSCTL);
+
+  /* Command Line Pre Drive Disable */
+
+  regval = getreg32(CXD56_SDHCI_VENDSPEC);
+  putreg32(regval & ~0x00000040, CXD56_SDHCI_VENDSPEC);
+
+  /* SDIO Clock Disable */
+
+  cxd56_sdio_clock_disable();
+
+  return &g_sdhcdev.dev;
+}
+
+/****************************************************************************
+ * Name: cxd56_sdhci_mediachange
+ *
+ * Description:
+ *   Called by board-specific logic -- possible from an interrupt handler --
+ *   in order to signal to the driver that a card has been inserted or
+ *   removed from the slot
+ *
+ * Input Parameters:
+ *   dev        - An instance of the SDIO driver device state structure.
+ *
+ * Returned Values:
+ *   None
+ *
+ ****************************************************************************/
+
+void cxd56_sdhci_mediachange(FAR struct sdio_dev_s *dev)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+  sdio_statset_t cdstatus;
+  irqstate_t flags;
+  uint8_t mediachange = 0;
+  int32_t timeout = SDHCI_CARDSTATETIMEOUT;
+
+  /* Update card status */
+  if (getreg32(CXD56_SDHCI_PRSSTAT) & SDHCI_PRSSTAT_SDCD)
+    {
+      while ((getreg32(CXD56_SDHCI_PRSSTAT) & SDHCI_PRSSTAT_CSTS) == 0)
+        {
+          if (timeout < 1)
+            {
+              break;
+            }
+          usleep(100000);
+          timeout -= 100000;
+        }
+    }
+
+  flags = enter_critical_section();
+  cdstatus = priv->cdstatus;
+
+  if (getreg32(CXD56_SDHCI_PRSSTAT) & SDHCI_PRSSTAT_CINS)
+    {
+      priv->cdstatus |= SDIO_STATUS_PRESENT;
+    }
+  else
+    {
+      priv->cdstatus &= ~SDIO_STATUS_PRESENT;
+    }
+
+  mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
+
+  /* Perform any requested callback if the status has changed */
+
+  if (cdstatus != priv->cdstatus)
+    {
+      if (priv->cdstatus & SDIO_STATUS_PRESENT)
+        {
+          priv->cbevents &= SDIOMEDIA_INSERTED;
+        }
+      mediachange = 1;//cxd56_sdio_callback(priv);
+    }
+  leave_critical_section(flags);
+  if (mediachange)
+    {
+      cxd56_sdio_callback(priv);
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_sdhci_wrprotect
+ *
+ * Description:
+ *   Called by board-specific logic to report if the card in the slot is
+ *   mechanically write protected.
+ *
+ * Input Parameters:
+ *   dev       - An instance of the SDIO driver device state structure.
+ *   wrprotect - true is a card is writeprotected.
+ *
+ * Returned Values:
+ *   None
+ *
+ ****************************************************************************/
+
+void cxd56_sdhci_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
+{
+  struct cxd56_sdiodev_s *priv = (struct cxd56_sdiodev_s *)dev;
+  irqstate_t flags;
+
+  /* Update card status */
+
+  flags = enter_critical_section();
+  if (wrprotect)
+    {
+      priv->cdstatus |= SDIO_STATUS_WRPROTECTED;
+    }
+  else
+    {
+      priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
+    }
+
+  mcinfo("cdstatus: %02x\n", priv->cdstatus);
+  leave_critical_section(flags);
+}
+#endif /* CONFIG_CXD56_SDIO */
diff --git a/arch/arm/src/cxd56xx/cxd56_sdhci.h b/arch/arm/src/cxd56xx/cxd56_sdhci.h
new file mode 100644
index 00000000000..e53807d08ea
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_sdhci.h
@@ -0,0 +1,463 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_sdhci.h
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_SDHCI_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56_SDHCI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include "chip.h"
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define CXD56_SDHCI_DSADDR_OFFSET     (0x0000) /* DMA System Address Register */
+#define CXD56_SDHCI_BLKATTR_OFFSET    (0x0004) /* Block Attributes Register */
+#define CXD56_SDHCI_CMDARG_OFFSET     (0x0008) /* Command Argument Register */
+#define CXD56_SDHCI_XFERTYP_OFFSET    (0x000c) /* Transfer Type Register */
+#define CXD56_SDHCI_CMDRSP0_OFFSET    (0x0010) /* Command Response 0 */
+#define CXD56_SDHCI_CMDRSP1_OFFSET    (0x0014) /* Command Response 1 */
+#define CXD56_SDHCI_CMDRSP2_OFFSET    (0x0018) /* Command Response 2 */
+#define CXD56_SDHCI_CMDRSP3_OFFSET    (0x001c) /* Command Response 3 */
+#define CXD56_SDHCI_DATPORT_OFFSET    (0x0020) /* Buffer Data Port Register */
+#define CXD56_SDHCI_PRSSTAT_OFFSET    (0x0024) /* Present State Register */
+#define CXD56_SDHCI_PROCTL_OFFSET     (0x0028) /* Protocol Control Register */
+#define CXD56_SDHCI_SYSCTL_OFFSET     (0x002c) /* System Control Register */
+#define CXD56_SDHCI_IRQSTAT_OFFSET    (0x0030) /* Interrupt Status Register */
+#define CXD56_SDHCI_IRQSTATEN_OFFSET  (0x0034) /* Interrupt Status Enable Register */
+#define CXD56_SDHCI_IRQSIGEN_OFFSET   (0x0038) /* Interrupt Signal Enable Register */
+#define CXD56_SDHCI_AC12ERR_OFFSET    (0x003c) /* Auto CMD12 Error Status Register */
+#define CXD56_SDHCI_HTCAPBLT_OFFSET   (0x0040) /* Host Controller Capabilities */
+#define CXD56_SDHCI_FEVT_OFFSET       (0x0050) /* Force Event Register */
+#define CXD56_SDHCI_ADMAES_OFFSET     (0x0054) /* ADMA Error Status Register */
+#define CXD56_SDHCI_ADSADDR_OFFSET    (0x0058) /* ADMA System Address Register */
+#define CXD56_SDHCI_HOSTVER_OFFSET    (0x00fc) /* Host Controller Version */
+#define CXD56_SDHCI_VENDSPEC_OFFSET   (0x0110) /* Vender Specific Control */
+#define CXD56_SDHCI_OTHERIOLL_OFFSET  (0x021C) /* IO Pin Control       */
+#define CXD56_SDHCI_USERDEF1CTL_OFFSET (0x0270) /* User Define1 Control Register */
+#define CXD56_SDHCI_USERDEF2CTL_OFFSET (0x0274) /* User Define2 Control Register */
+
+/* Register Addresses *******************************************************/
+#define CXD56_SDHCI_BASE              CXD56_SDIO_BASE
+
+#define CXD56_SDHCI_DSADDR            (CXD56_SDHCI_BASE+CXD56_SDHCI_DSADDR_OFFSET)
+#define CXD56_SDHCI_BLKATTR           (CXD56_SDHCI_BASE+CXD56_SDHCI_BLKATTR_OFFSET)
+#define CXD56_SDHCI_CMDARG            (CXD56_SDHCI_BASE+CXD56_SDHCI_CMDARG_OFFSET)
+#define CXD56_SDHCI_XFERTYP           (CXD56_SDHCI_BASE+CXD56_SDHCI_XFERTYP_OFFSET)
+#define CXD56_SDHCI_CMDRSP0           (CXD56_SDHCI_BASE+CXD56_SDHCI_CMDRSP0_OFFSET)
+#define CXD56_SDHCI_CMDRSP1           (CXD56_SDHCI_BASE+CXD56_SDHCI_CMDRSP1_OFFSET)
+#define CXD56_SDHCI_CMDRSP2           (CXD56_SDHCI_BASE+CXD56_SDHCI_CMDRSP2_OFFSET)
+#define CXD56_SDHCI_CMDRSP3           (CXD56_SDHCI_BASE+CXD56_SDHCI_CMDRSP3_OFFSET)
+#define CXD56_SDHCI_DATPORT           (CXD56_SDHCI_BASE+CXD56_SDHCI_DATPORT_OFFSET)
+#define CXD56_SDHCI_PRSSTAT           (CXD56_SDHCI_BASE+CXD56_SDHCI_PRSSTAT_OFFSET)
+#define CXD56_SDHCI_PROCTL            (CXD56_SDHCI_BASE+CXD56_SDHCI_PROCTL_OFFSET)
+#define CXD56_SDHCI_SYSCTL            (CXD56_SDHCI_BASE+CXD56_SDHCI_SYSCTL_OFFSET)
+#define CXD56_SDHCI_IRQSTAT           (CXD56_SDHCI_BASE+CXD56_SDHCI_IRQSTAT_OFFSET)
+#define CXD56_SDHCI_IRQSTATEN         (CXD56_SDHCI_BASE+CXD56_SDHCI_IRQSTATEN_OFFSET)
+#define CXD56_SDHCI_IRQSIGEN          (CXD56_SDHCI_BASE+CXD56_SDHCI_IRQSIGEN_OFFSET)
+#define CXD56_SDHCI_AC12ERR           (CXD56_SDHCI_BASE+CXD56_SDHCI_AC12ERR_OFFSET)
+#define CXD56_SDHCI_HTCAPBLT          (CXD56_SDHCI_BASE+CXD56_SDHCI_HTCAPBLT_OFFSET)
+#define CXD56_SDHCI_FEVT              (CXD56_SDHCI_BASE+CXD56_SDHCI_FEVT_OFFSET)
+#define CXD56_SDHCI_ADMAES            (CXD56_SDHCI_BASE+CXD56_SDHCI_ADMAES_OFFSET)
+#define CXD56_SDHCI_ADSADDR           (CXD56_SDHCI_BASE+CXD56_SDHCI_ADSADDR_OFFSET)
+#define CXD56_SDHCI_HOSTVER           (CXD56_SDHCI_BASE+CXD56_SDHCI_HOSTVER_OFFSET)
+#define CXD56_SDHCI_VENDSPEC          (CXD56_SDHCI_BASE+CXD56_SDHCI_VENDSPEC_OFFSET)
+#define CXD56_SDHCI_OTHERIOLL         (CXD56_SDHCI_BASE+CXD56_SDHCI_OTHERIOLL_OFFSET)
+#define CXD56_SDHCI_USERDEF1CTL       (CXD56_SDHCI_BASE+CXD56_SDHCI_USERDEF1CTL_OFFSET)
+#define CXD56_SDHCI_USERDEF2CTL       (CXD56_SDHCI_BASE+CXD56_SDHCI_USERDEF2CTL_OFFSET)
+
+/* Register Bit Definitions *************************************************/
+
+/* DMA System Address Register */
+
+#define SDHCI_DSADDR_SHIFT               (1)       /* Bits 1-31: DMA System Address */
+#define SDHCI_DSADDR_MASK                (0xfffffffe)
+                                                  /* Bits 0-1: Reserved */
+/* Block Attributes Register */
+
+#define SDHCI_BLKATTR_SIZE_SHIFT         (0)       /* Bits 0-12: Transfer Block Size */
+#define SDHCI_BLKATTR_SIZE_MASK          (0x1fff << SDHCI_BLKATTR_SIZE_SHIFT)
+                                                  /* Bits 13-15: Reserved */
+#define SDHCI_BLKATTR_CNT_SHIFT          (16)      /* Bits 16-31: Blocks Count For Current Transfer */
+#define SDHCI_BLKATTR_CNT_MASK           (0xffff << SDHCI_BLKATTR_CNT_SHIFT)
+
+/* Command Argument Register (32-bit cmd/arg data) */
+
+/* Transfer Type Register */
+
+#define SDHCI_XFERTYP_DMAEN              (1 << 0)  /* Bit 0:  DMA Enable */
+#define SDHCI_XFERTYP_BCEN               (1 << 1)  /* Bit 1:  Block Count Enable */
+#define SDHCI_XFERTYP_AC12EN             (1 << 2)  /* Bit 2:  Auto CMD12 Enable */
+                                                  /* Bit 3: Reserved */
+#define SDHCI_XFERTYP_DTDSEL             (1 << 4)  /* Bit 4:  Data Transfer Direction Select */
+#define SDHCI_XFERTYP_MSBSEL             (1 << 5)  /* Bit 5:  Multi/Single Block Select */
+                                                  /* Bits 6-15: Reserved */
+#define SDHCI_XFERTYP_RSPTYP_SHIFT       (16)      /* Bits 16-17: Response Type Select */
+#define SDHCI_XFERTYP_RSPTYP_MASK        (3 << SDHCI_XFERTYP_RSPTYP_SHIFT)
+#  define SDHCI_XFERTYP_RSPTYP_NONE      (0 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* No response */
+#  define SDHCI_XFERTYP_RSPTYP_LEN136    (1 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* Response length 136 */
+#  define SDHCI_XFERTYP_RSPTYP_LEN48     (2 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* Response length 48 */
+#  define SDHCI_XFERTYP_RSPTYP_LEN48BSY  (3 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* Response length 48, check busy */
+                                                  /* Bit 18: Reserved */
+#define SDHCI_XFERTYP_CCCEN              (1 << 19) /* Bit 19: Command CRC Check Enable */
+#define SDHCI_XFERTYP_CICEN              (1 << 20) /* Bit 20: Command Index Check Enable */
+#define SDHCI_XFERTYP_DPSEL              (1 << 21) /* Bit 21: Data Present Select */
+#define SDHCI_XFERTYP_CMDTYP_SHIFT       (22)      /* Bits 22-23: Command Type */
+#define SDHCI_XFERTYP_CMDTYP_MASK        (3 << SDHCI_XFERTYP_CMDTYP_SHIFT)
+#  define SDHCI_XFERTYP_CMDTYP_NORMAL    (0 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Normal other commands */
+#  define SDHCI_XFERTYP_CMDTYP_SUSPEND   (1 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Suspend CMD52 for writing bus suspend in CCCR */
+#  define SDHCI_XFERTYP_CMDTYP_RESUME    (2 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Resume CMD52 for writing function select in CCCR */
+#  define SDHCI_XFERTYP_CMDTYP_ABORT     (3 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Abort CMD12, CMD52 for writing I/O abort in CCCR */
+#define SDHCI_XFERTYP_CMDINX_SHIFT       (24)      /* Bits 24-29: Command Index */
+#define SDHCI_XFERTYP_CMDINX_MASK        (63 << SDHCI_XFERTYP_CMDINX_SHIFT)
+                                                  /* Bits 30-31: Reserved */
+/* Command Response 0-3 (32-bit response data) */
+
+/* Buffer Data Port Register (32-bit data content) */
+
+/* Present State Register */
+
+#define SDHCI_PRSSTAT_CIHB               (1 << 0)  /* Bit 0:  Command Inhibit (CMD) */
+#define SDHCI_PRSSTAT_CDIHB              (1 << 1)  /* Bit 1:  Command Inhibit (DAT) */
+#define SDHCI_PRSSTAT_DLA                (1 << 2)  /* Bit 2:  Data Line Active */
+#define SDHCI_PRSSTAT_SDSTB              (1 << 3)  /* Bit 3:  SD Clock Stable */
+#define SDHCI_PRSSTAT_IPGOFF             (1 << 4)  /* Bit 4:  Bus Clock */
+#define SDHCI_PRSSTAT_HCKOFF             (1 << 5)  /* Bit 5:  System Clock */
+#define SDHCI_PRSSTAT_PEROFF             (1 << 6)  /* Bit 6:  SDHC clock */
+#define SDHCI_PRSSTAT_SDOFF              (1 << 7)  /* Bit 7:  SD Clock Gated Off Internally */
+#define SDHCI_PRSSTAT_WTA                (1 << 8)  /* Bit 8:  Write Transfer Active */
+#define SDHCI_PRSSTAT_RTA                (1 << 9)  /* Bit 9:  Read Transfer Active */
+#define SDHCI_PRSSTAT_BWEN               (1 << 10) /* Bit 10: Buffer Write Enable */
+#define SDHCI_PRSSTAT_BREN               (1 << 11) /* Bit 11: Buffer Read Enable */
+                                                  /* Bits 12-15: Reserved */
+#define SDHCI_PRSSTAT_CINS               (1 << 16) /* Bit 16: Card Inserted */
+#define SDHCI_PRSSTAT_CSTS               (1 << 17) /* Bit 17: Card State Stable */
+#define SDHCI_PRSSTAT_SDCD               (1 << 18) /* Bit 18: Card Detect Pin Level */
+#define SDHCI_PRSSTAT_SDWPN               (1 << 19) /* Bit 19: Write Protect Switch Pin Level*/
+#define SDHCI_PRSSTAT_DLSL_SHIFT         (20)      /* Bits 20-23: DAT Line Signal Level */
+#define SDHCI_PRSSTAT_DLSL_MASK          (0xf << SDHCI_PRSSTAT_DLSL_SHIFT)
+#  define SDHCI_PRSSTAT_DLSL_DAT0        (0x1 << SDHCI_PRSSTAT_DLSL_SHIFT)
+#  define SDHCI_PRSSTAT_DLSL_DAT1        (0x2 << SDHCI_PRSSTAT_DLSL_SHIFT)
+#  define SDHCI_PRSSTAT_DLSL_DAT2        (0x4 << SDHCI_PRSSTAT_DLSL_SHIFT)
+#  define SDHCI_PRSSTAT_DLSL_DAT3        (0x8 << SDHCI_PRSSTAT_DLSL_SHIFT)
+#define SDHCI_PRSSTAT_CLSL               (1 << 24) /* Bit 23: CMD Line Signal Level */
+
+/* Protocol Control Register */
+
+#define SDHCI_PROCTL_LCTL                (1 << 0)  /* Bit 0:  LED Control */
+#define SDHCI_PROCTL_DTW_SHIFT           (1)       /* Bits 1-2: Data Transfer Width */
+#define SDHCI_PROCTL_DTW_MASK            (1 << SDHCI_PROCTL_DTW_SHIFT)
+#  define SDHCI_PROCTL_DTW_1BIT          (0 << SDHCI_PROCTL_DTW_SHIFT) /* 1-bit mode */
+#  define SDHCI_PROCTL_DTW_4BIT          (1 << SDHCI_PROCTL_DTW_SHIFT) /* 4-bit mode */
+#define SDHCI_PROCTL_DMAS_SHIFT          (3)       /* Bits 8-9: DMA Select */
+#define SDHCI_PROCTL_DMAS_MASK           (3 << SDHCI_PROCTL_DMAS_SHIFT)
+#  define SDHCI_PROCTL_DMAS_NODMA        (0 << SDHCI_PROCTL_DMAS_SHIFT) /* No DMA or simple DMA is selected */
+#  define SDHCI_PROCTL_DMAS_ADMA2        (2 << SDHCI_PROCTL_DMAS_SHIFT) /* ADMA2 is selected */
+#define SDHCI_PROCTL_CDTL                (1 << 6)  /* Bit 6:  Card Detect Test Level */
+#define SDHCI_PROCTL_CDSS                (1 << 7)  /* Bit 7:  Card Detect Signal Selection */
+                                                  /* Bits 10-15: Reserved */
+#define SDHCI_PROCTL_SABGREQ             (1 << 16) /* Bit 16: Stop At Block Gap Request */
+#define SDHCI_PROCTL_CREQ                (1 << 17) /* Bit 17: Continue Request */
+#define SDHCI_PROCTL_RWCTL               (1 << 18) /* Bit 18: Read Wait Control */
+#define SDHCI_PROCTL_IABG                (1 << 19) /* Bit 19: Interrupt At Block Gap */
+                                                  /* Bits 20-23: Reserved */
+#define SDHCI_PROCTL_WECINT              (1 << 24) /* Bit 24: Wakeup Event Enable On Card Interrupt */
+#define SDHCI_PROCTL_WECINS              (1 << 25) /* Bit 25: Wakeup Event Enable On SD Card Insertion */
+#define SDHCI_PROCTL_WECRM               (1 << 26) /* Bit 26: Wakeup Event Enable On SD Card Removal */
+                                                  /* Bits 27-31: Reserved */
+/* System Control Register */
+
+#define SDHCI_SYSCTL_ICLKEN              (1 << 0)  /* Bit 0:  Internal Clock Enable */
+#define SDHCI_SYSCTL_ICLKSTA             (1 << 1)  /* Bit 1:  Internal Clock Stable */
+#define SDHCI_SYSCTL_SDCLKEN             (1 << 2)  /* Bit 2:  SD Clock Enable */
+#define SDHCI_SYSCTL_GENSEL              (1 << 5)  /* Bit 5:  Clock Generetor Select */
+#define SDHCI_SYSCTL_SDCLKFSUP_SHIFT     (6)       /* Bits 6-7: Divisor */
+#define SDHCI_SYSCTL_SDCLKFSUP_MASK      (3 << SDHCI_SYSCTL_SDCLKFSUP_SHIFT)
+#define SDHCI_SYSCTL_SDCLKFS_SHIFT       (8)       /* Bits 8-15: SDCLK Frequency Select */
+#define SDHCI_SYSCTL_SDCLKFS_MASK        (0xff << SDHCI_SYSCTL_SDCLKFS_SHIFT)
+#define SDHCI_SYSCTL_DTOCV_SHIFT         (16)      /* Bits 16-19: Data Timeout Counter Value */
+#define SDHCI_SYSCTL_DTOCV_MASK          (0xf << SDHCI_SYSCTL_DTOCV_SHIFT)
+#  define SDHCI_SYSCTL_DTOCV_MUL(n)      (((n)-213) << SDHCI_SYSCTL_DTOCV_SHIFT) /* SDCLK x n, n=213..227 */
+                                                  /* Bits 20-23: Reserved */
+#define SDHCI_SYSCTL_RSTA                (1 << 24) /* Bit 24: Software Reset For ALL */
+#define SDHCI_SYSCTL_RSTC                (1 << 25) /* Bit 25: Software Reset For CMD Line */
+#define SDHCI_SYSCTL_RSTD                (1 << 26) /* Bit 26: Software Reset For DAT Line */
+#define SDHCI_SYSCTL_INITA               (1 << 27) /* Bit 27: Initialization Active */
+                                                  /* Bits 28-31: Reserved */
+/* Interrupt Status Register, Interrupt Status Enable Register, and Interrupt Signal Enable Register
+ * Common interrupt bit definitions
+ */
+
+#define SDHCI_INT_CC                     (1 << 0)  /* Bit 0:  Command Complete */
+#define SDHCI_INT_TC                     (1 << 1)  /* Bit 1:  Transfer Complete */
+#define SDHCI_INT_BGE                    (1 << 2)  /* Bit 2:  Block Gap Event */
+#define SDHCI_INT_DINT                   (1 << 3)  /* Bit 3:  DMA Interrupt */
+#define SDHCI_INT_BWR                    (1 << 4)  /* Bit 4:  Buffer Write Ready */
+#define SDHCI_INT_BRR                    (1 << 5)  /* Bit 5:  Buffer Read Ready */
+#define SDHCI_INT_CINS                   (1 << 6)  /* Bit 6:  Card Insertion */
+#define SDHCI_INT_CRM                    (1 << 7)  /* Bit 7:  Card Removal */
+#define SDHCI_INT_CINT                   (1 << 8)  /* Bit 8:  Card Interrupt */
+                                                  /* Bits 9-15: Reserved */
+#define SDHCI_INT_CTOE                   (1 << 16) /* Bit 16: Command Timeout Error */
+#define SDHCI_INT_CCE                    (1 << 17) /* Bit 17: Command CRC Error */
+#define SDHCI_INT_CEBE                   (1 << 18) /* Bit 18: Command End Bit Error */
+#define SDHCI_INT_CIE                    (1 << 19) /* Bit 19: Command Index Error */
+#define SDHCI_INT_DTOE                   (1 << 20) /* Bit 20: Data Timeout Error */
+#define SDHCI_INT_DCE                    (1 << 21) /* Bit 21: Data CRC Error */
+#define SDHCI_INT_DEBE                   (1 << 22) /* Bit 22: Data End Bit Error */
+                                                  /* Bit 23: Reserved */
+#define SDHCI_INT_AC12E                  (1 << 24) /* Bit 24: Auto CMD12 Error */
+                                                  /* Bits 25-27: Reserved */
+#define SDHCI_INT_DMAE                   (1 << 28) /* Bit 28: DMA Error */
+                                                  /* Bits 29-31: Reserved */
+#define SDHCI_INT_ALL                    0x117f01ff
+
+/* Auto CMD12 Error Status Register */
+
+#define SDHCI_AC12ERR_NE                 (1 << 0)  /* Bit 0:  Auto CMD12 Not Executed */
+#define SDHCI_AC12ERR_TOE                (1 << 1)  /* Bit 1:  Auto CMD12 Timeout Error */
+#define SDHCI_AC12ERR_EBE                (1 << 2)  /* Bit 2:  Auto CMD12 End Bit Error */
+#define SDHCI_AC12ERR_CE                 (1 << 3)  /* Bit 3:  Auto CMD12 CRC Error */
+#define SDHCI_AC12ERR_IE                 (1 << 4)  /* Bit 4:  Auto CMD12 Index Error */
+                                                  /* Bits 5-6: Reserved */
+#define SDHCI_AC12ERR_CNI                (1 << 7)  /* Bit 7: Command Not Issued By Auto CMD12 Error */
+                                                  /* Bits 8-31: Reserved */
+/* Host Controller Capabilities */
+                                                  /* Bits 0-15: Reserved */
+#define SDHCI_HTCAPBLT_MBL_SHIFT         (16)      /* Bits 16-18: Max Block Length */
+#define SDHCI_HTCAPBLT_MBL_MASK          (7 << SDHCI_HTCAPBLT_MBL_SHIFT)
+#  define SDHCI_HTCAPBLT_MBL_512BYTES    (0 << SDHCI_HTCAPBLT_MBL_SHIFT)
+#  define SDHCI_HTCAPBLT_MBL_1KB         (1 << SDHCI_HTCAPBLT_MBL_SHIFT)
+#  define SDHCI_HTCAPBLT_MBL_2KB         (2 << SDHCI_HTCAPBLT_MBL_SHIFT)
+#  define SDHCI_HTCAPBLT_MBL_4KB         (3 << SDHCI_HTCAPBLT_MBL_SHIFT)
+                                                  /* Bit 19: Reserved */
+#define SDHCI_HTCAPBLT_ADMAS             (1 << 20) /* Bit 20: ADMA Support */
+#define SDHCI_HTCAPBLT_HSS               (1 << 21) /* Bit 21: High Speed Support */
+#define SDHCI_HTCAPBLT_DMAS              (1 << 22) /* Bit 22: DMA Support */
+#define SDHCI_HTCAPBLT_SRS               (1 << 23) /* Bit 23: Suspend/Resume Support */
+#define SDHCI_HTCAPBLT_VS33              (1 << 24) /* Bit 24: Voltage Support 3.3 V */
+#define SDHCI_HTCAPBLT_VS30              (1 << 25) /* Bit 25: Voltage Support 3.0 V */
+#define SDHCI_HTCAPBLT_VS18              (1 << 26) /* Bit 26: Voltage Support 1.8 */
+                                                  /* Bits 27-31: Reserved */
+/* Force Event Register */
+
+#define SDHCI_FEVT_AC12NE                (1 << 0)  /* Bit 0:  Force Event Auto Command 12 Not Executed */
+#define SDHCI_FEVT_AC12TOE               (1 << 1)  /* Bit 1:  Force Event Auto Command 12 Time Out Error */
+#define SDHCI_FEVT_AC12CE                (1 << 2)  /* Bit 2:  Force Event Auto Command 12 CRC Error */
+#define SDHCI_FEVT_AC12EBE               (1 << 3)  /* Bit 3:  Force Event Auto Command 12 End Bit Error */
+#define SDHCI_FEVT_AC12IE                (1 << 4)  /* Bit 4:  Force Event Auto Command 12 Index Error */
+                                                  /* Bits 5-6: Reserved */
+#define SDHCI_FEVT_CNIBAC12E             (1 << 7)  /* Bit 7:  Force Event Command Not Executed By Auto Command 12 Error */
+                                                  /* Bits 8-15: Reserved */
+#define SDHCI_FEVT_CTOE                  (1 << 16) /* Bit 16: Force Event Command Time Out Error */
+#define SDHCI_FEVT_CCE                   (1 << 17) /* Bit 17: Force Event Command CRC Error */
+#define SDHCI_FEVT_CEBE                  (1 << 18) /* Bit 18: Force Event Command End Bit Error */
+#define SDHCI_FEVT_CIE                   (1 << 19) /* Bit 19: Force Event Command Index Error */
+#define SDHCI_FEVT_DTOE                  (1 << 20) /* Bit 20: Force Event Data Time Out Error */
+#define SDHCI_FEVT_DCE                   (1 << 21) /* Bit 21: Force Event Data CRC Error */
+#define SDHCI_FEVT_DEBE                  (1 << 22) /* Bit 22: Force Event Data End Bit Error */
+                                                  /* Bit 23: Reserved */
+#define SDHCI_FEVT_AC12E                 (1 << 24) /* Bit 24: Force Event Auto Command 12 Error */
+                                                  /* Bits 25-27: Reserved */
+#define SDHCI_FEVT_DMAE                  (1 << 28) /* Bit 28: Force Event DMA Error */
+                                                  /* Bits 29-30: Reserved */
+#define SDHCI_FEVT_CINT                  (1 << 31) /* Bit 31: Force Event Card Interrupt */
+
+/* ADMA Error Status Register */
+
+#define SDHCI_ADMAES_SHIFT               (0)       /* Bits 0-1: ADMA Error State (when ADMA Error is occurred) */
+#define SDHCI_ADMAES_MASK                (3 << SDHCI_ADMAES_ADMAES_SHIFT)
+#  define SDHCI_ADMAES_STOP              (0 << SDHCI_ADMAES_ADMAES_SHIFT) /* Stop DMA */
+#  define SDHCI_ADMAES_FDS               (1 << SDHCI_ADMAES_ADMAES_SHIFT) /* Fetch descriptor */
+#  define SDHCI_ADMAES_CADR              (2 << SDHCI_ADMAES_ADMAES_SHIFT) /* Change address */
+#  define SDHCI_ADMAES_TFR               (3 << SDHCI_ADMAES_ADMAES_SHIFT) /* Transfer data */
+#define SDHCI_ADMAES_LME                 (1 << 2)  /* Bit 2:  ADMA Length Mismatch Error */
+#define SDHCI_ADMAES_DCE                 (1 << 3)  /* Bit 3:  ADMA Descriptor Error */
+                                                  /* Bits 4-31: Reserved */
+/* ADMA System Address Register */
+
+#define SDHCI_ADSADDR_SHIFT              (1)       /* Bits 1-31: ADMA System Address */
+#define SDHCI_ADSADDR_MASK               (0xfffffffe)
+                                                  /* Bits 0-1: Reserved */
+
+/* Vendor Specific Register */
+
+#define SDHCI_VENDOR_EXTDMAEN            (1 << 0)  /* Bit 0:  External DMA Request Enable */
+#define SDHCI_VENDOR_EXBLKNU             (1 << 1)  /* Bit 1:  Exact block number block read enable for SDIO CMD53 */
+                                                  /* Bits 2-15: Reserved */
+#define SDHCI_VENDOR_INTSTVAL_SHIFT      (16)      /* Bits 16-23: Internal State Value */
+#define SDHCI_VENDOR_INTSTVAL_MASK       (0xff << SDHCI_VENDOR_INTSTVAL_SHIFT)
+                                                  /* Bits 24-31: Reserved */
+
+/* User Define1 Control Register */
+
+#define SDHCI_UDEF1_SDCLKI_SEL           (1 << 0)
+#define SDHCI_UDEF1_SDCLKI_SEL_EXT       (1 << 0)
+#define SDHCI_UDEF1_SDCLKI_SEL_INT       (0 << 0)
+#define SDHCI_UDEF1_SDCLK_SEL            (1 << 1)
+#define SDHCI_UDEF1_SDCLK_SEL_EXT        (1 << 1)
+#define SDHCI_UDEF1_SDCLK_SEL_INT        (0 << 1)
+#define SDHCI_UDEF1_TAP_SEL_SHIFT        (4)
+#define SDHCI_UDEF1_TAP_SEL_MASK         (0x1f << SDHCI_UDEF1_TAP_SEL_SHIFT)
+#define SDHCI_UDEF1_TAP_SEL              (1 << 12)
+#define SDHCI_UDEF1_TAP_SEL_SW           (1 << 12)
+#define SDHCI_UDEF1_TAP_SEL_HW           (0 << 12)
+#define SDHCI_UDEF1_DAT_DLY_BUF          (1 << 24)
+#define SDHCI_UDEF1_DAT_DLY_BUF_ON       (1 << 24)
+#define SDHCI_UDEF1_DAT_DLY_BUF_OFF      (0 << 24)
+
+/* User Define2 Control Register */
+
+#define SDHCI_UDEF2_CLK_DLY_SHIFT        (0)
+#define SDHCI_UDEF2_CLK_DLY_MASK         (0x7 << SDHCI_UDEF2_CLK_DLY_SHIFT)
+#define SDHCI_UDEF2_CMD_EDGE_DET_ON      (1 << 4)
+#define SDHCI_UDEF2_CMD_EDGE_DET_OFF     (0 << 4)
+#define SDHCI_UDEF2_DAT_DIR_ACT_HI       (0x0 << 8)
+#define SDHCI_UDEF2_DAT_DIR_ACT_LOW      (0x7 << 8)
+#define SDHCI_UDEF2_TTCLK_DIV1           (1 << 16)
+#define SDHCI_UDEF2_TTCLK_DIV2           (0 << 16)
+#define SDHCI_UDEF2_CLKI_SEL             (1 << 20)
+#define SDHCI_UDEF2_CLKI_SEL_EXT         (1 << 20)
+#define SDHCI_UDEF2_CLKI_SEL_INT         (0 << 20)
+#define SDHCI_UDEF2_CMD_SEL              (1 << 24)
+#define SDHCI_UDEF2_CMD_SEL_CLKI         (1 << 24)
+#define SDHCI_UDEF2_CMD_SEL_INT          (0 << 24)
+#define SDHCI_UDEF2_FORCE_1p8V_EN        (1 << 31)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+struct sdio_dev_s;
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+
+/****************************************************************************
+ * Name: cxd56_sdhci_initialize
+ *
+ * Description:
+ *   Initialize SDIO for operation.
+ *
+ * Input Parameters:
+ *   slotno - Not used.
+ *
+ * Returned Values:
+ *   A reference to an SDIO interface structure.  NULL is returned on failures.
+ *
+ ****************************************************************************/
+
+FAR struct sdio_dev_s *cxd56_sdhci_initialize(int slotno);
+
+/****************************************************************************
+ * Name: cxd56_sdhci_finalize
+ *
+ * Description:
+ *   Finalize SDIO for operation.
+ *
+ * Input Parameters:
+ *   slotno - Not used.
+ *
+ * Returned Values:
+ *   A reference to an SDIO interface structure.  NULL is returned on failures.
+ *
+ ****************************************************************************/
+
+FAR struct sdio_dev_s *cxd56_sdhci_finalize(int slotno);
+
+/****************************************************************************
+ * Name: cxd56_sdhci_mediachange
+ *
+ * Description:
+ *   Called by board-specific logic -- posssible from an interrupt handler --
+ *   in order to signal to the driver that a card has been inserted or
+ *   removed from the slot
+ *
+ * Input Parameters:
+ *   dev        - An instance of the SDIO driver device state structure.
+ *
+ * Returned Values:
+ *   None
+ *
+ ****************************************************************************/
+void cxd56_sdhci_mediachange(FAR struct sdio_dev_s *dev);
+
+/****************************************************************************
+ * Name: sdio_wrprotect
+ *
+ * Description:
+ *   Called by board-specific logic to report if the card in the slot is
+ *   mechanically write protected.
+ *
+ * Input Parameters:
+ *   dev       - An instance of the SDIO driver device state structure.
+ *   wrprotect - true is a card is writeprotected.
+ *
+ * Returned Values:
+ *   None
+ *
+ ****************************************************************************/
+void cxd56_sdhci_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_SDHCI_H */
diff --git a/arch/arm/src/cxd56xx/cxd56_serial.c b/arch/arm/src/cxd56xx/cxd56_serial.c
new file mode 100644
index 00000000000..8c3811c3f98
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_serial.c
@@ -0,0 +1,997 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_serial.c
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ *   Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_SERIAL_TERMIOS
+#  include 
+#endif
+
+#include 
+#include 
+#include 
+
+#include 
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "cxd56_config.h"
+#include "cxd56_serial.h"
+
+/****************************************************************************
+ * Pre-processor definitions
+ ****************************************************************************/
+
+/* If we are not using the serial driver for the console, then we still must
+ * provide some minimal implementation of up_putc.
+ */
+
+#if defined(USE_SERIALDRIVER) && defined(HAVE_UART)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct up_dev_s
+{
+  uintptr_t uartbase; /* Base address of UART registers */
+  uint32_t basefreq;  /* Base frequency of input clock */
+  uint32_t baud;      /* Configured baud */
+  uint32_t ier;       /* Saved IER value */
+  uint8_t id;         /* ID=0,1,2,3 */
+  uint8_t irq;        /* IRQ associated with this UART */
+  uint8_t parity;     /* 0=none, 1=odd, 2=even */
+  uint8_t bits;       /* Number of bits (7 or 8) */
+  bool stopbits2;     /* true: Configure with 2 stop bits instead of 1 */
+#ifdef HAVE_RS485
+  bool dtrdir;        /* DTR pin is the direction bit */
+#endif
+  void *pmhandle;
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int up_setup(FAR struct uart_dev_s *dev);
+static void up_shutdown(FAR struct uart_dev_s *dev);
+static int up_attach(FAR struct uart_dev_s *dev);
+static void up_detach(FAR struct uart_dev_s *dev);
+static int up_interrupt(int irq, FAR void *context, FAR void *arg);
+static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_UART2_IFLOWCONTROL
+static bool up_rxflowcontrol(FAR struct uart_dev_s *dev,
+                             unsigned int nbuffered, bool upper);
+#endif
+static int up_receive(FAR struct uart_dev_s *dev, FAR uint32_t *status);
+static void up_rxint(FAR struct uart_dev_s *dev, bool enable);
+static bool up_rxavailable(FAR struct uart_dev_s *dev);
+static void up_send(FAR struct uart_dev_s *dev, int ch);
+static void up_txint(FAR struct uart_dev_s *dev, bool enable);
+static bool up_txready(FAR struct uart_dev_s *dev);
+static bool up_txempty(FAR struct uart_dev_s *dev);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct uart_ops_s g_uart_ops =
+{
+  .setup         = up_setup,
+  .shutdown      = up_shutdown,
+  .attach        = up_attach,
+  .detach        = up_detach,
+  .ioctl         = up_ioctl,
+  .receive       = up_receive,
+  .rxint         = up_rxint,
+  .rxavailable   = up_rxavailable,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+  .rxflowcontrol = NULL,
+#endif
+  .send          = up_send,
+  .txint         = up_txint,
+  .txready       = up_txready,
+  .txempty       = up_txempty,
+};
+
+#ifdef CONFIG_CXD56_UART2
+static const struct uart_ops_s g_uart2_ops =
+{
+  .setup         = up_setup,
+  .shutdown      = up_shutdown,
+  .attach        = up_attach,
+  .detach        = up_detach,
+  .ioctl         = up_ioctl,
+  .receive       = up_receive,
+  .rxint         = up_rxint,
+  .rxavailable   = up_rxavailable,
+#ifdef CONFIG_UART2_IFLOWCONTROL
+  .rxflowcontrol = up_rxflowcontrol,
+#endif
+  .send          = up_send,
+  .txint         = up_txint,
+  .txready       = up_txready,
+  .txempty       = up_txempty,
+};
+#endif
+
+/* I/O buffers */
+
+#ifdef CONFIG_CXD56_UART1
+static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
+#endif
+#ifdef CONFIG_CXD56_UART2
+static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
+static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
+#endif
+
+/* This describes the state of the CXD56xx uart1 port. */
+
+#ifdef CONFIG_CXD56_UART1
+static struct up_dev_s g_uart1priv =
+{
+  .uartbase  = CXD56_UART1_BASE,
+  .basefreq  = BOARD_UART1_BASEFREQ,
+  .baud      = CONFIG_UART1_BAUD,
+  .id        = 1,
+  .irq       = CXD56_IRQ_UART1,
+  .parity    = CONFIG_UART1_PARITY,
+  .bits      = CONFIG_UART1_BITS,
+  .stopbits2 = CONFIG_UART1_2STOP,
+};
+
+static uart_dev_t g_uart1port =
+{
+  .recv =
+    {
+      .size   = CONFIG_UART1_RXBUFSIZE,
+      .buffer = g_uart1rxbuffer,
+    },
+  .xmit =
+    {
+      .size   = CONFIG_UART1_TXBUFSIZE,
+      .buffer = g_uart1txbuffer,
+    },
+  .ops  = &g_uart_ops,
+  .priv = &g_uart1priv,
+};
+#  define TTYS0_DEV g_uart1port /* UART1=ttyS0 */
+#endif
+
+/* This describes the state of the CXD56xx uart1 port. */
+
+#ifdef CONFIG_CXD56_UART2
+static struct up_dev_s g_uart2priv =
+{
+  .uartbase  = CXD56_UART2_BASE,
+  .basefreq  = BOARD_UART2_BASEFREQ,
+  .baud      = CONFIG_UART2_BAUD,
+  .id        = 2,
+  .irq       = CXD56_IRQ_APP_UART,
+  .parity    = CONFIG_UART2_PARITY,
+  .bits      = CONFIG_UART2_BITS,
+  .stopbits2 = CONFIG_UART2_2STOP,
+};
+
+static uart_dev_t g_uart2port =
+{
+  .recv =
+    {
+      .size   = CONFIG_UART2_RXBUFSIZE,
+      .buffer = g_uart2rxbuffer,
+    },
+  .xmit =
+    {
+      .size   = CONFIG_UART2_TXBUFSIZE,
+      .buffer = g_uart2txbuffer,
+    },
+  .ops  = &g_uart2_ops,
+  .priv = &g_uart2priv,
+};
+
+#  define TTYS2_DEV g_uart2port /* UART2=ttyS2 */
+#endif
+
+/* Which UART with be tty0/console and which tty1? tty2? tty3? */
+
+#ifdef HAVE_CONSOLE
+#  if defined(CONFIG_UART1_SERIAL_CONSOLE)
+#    define CONSOLE_DEV     g_uart1port /* UART1=console */
+#  elif defined(CONFIG_UART2_SERIAL_CONSOLE)
+#    define CONSOLE_DEV     g_uart2port /* UART2=console */
+#  endif
+#endif /* HAVE_CONSOLE */
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialin
+ ****************************************************************************/
+
+static inline uint32_t up_serialin(FAR struct up_dev_s *priv, int offset)
+{
+  return getreg32(priv->uartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_serialout
+ ****************************************************************************/
+
+static inline void up_serialout(FAR struct up_dev_s *priv, int offset,
+                                uint32_t value)
+{
+  putreg32(value, priv->uartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_disableuartint
+ ****************************************************************************/
+
+static inline void up_disableuartint(FAR struct up_dev_s *priv,
+                                     FAR uint32_t *ier)
+{
+  irqstate_t flags;
+
+  flags = enter_critical_section();
+  if (ier)
+    {
+      *ier = priv->ier & UART_INTR_ALL;
+    }
+
+  priv->ier &= ~UART_INTR_ALL;
+  up_serialout(priv, CXD56_UART_IMSC, priv->ier);
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: up_restoreuartint
+ ****************************************************************************/
+
+static inline void up_restoreuartint(FAR struct up_dev_s *priv, uint32_t ier)
+{
+  irqstate_t flags;
+
+  flags = enter_critical_section();
+  priv->ier |= ier & UART_INTR_ALL;
+  up_serialout(priv, CXD56_UART_IMSC, priv->ier);
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: up_enablebreaks
+ ****************************************************************************/
+
+static inline void up_enablebreaks(FAR struct up_dev_s *priv, bool enable)
+{
+  uint32_t lcr = up_serialin(priv, CXD56_UART_LCR_H);
+  if (enable)
+    {
+      lcr |= UART_LCR_BRK;
+    }
+  else
+    {
+      lcr &= ~UART_LCR_BRK;
+    }
+
+  up_serialout(priv, CXD56_UART_LCR_H, lcr);
+}
+
+/****************************************************************************
+ * Name: up_setup
+ *
+ * Description:
+ *   Configure the UART baud, bits, parity, fifos, etc. This method is
+ *   called the first time that the serial port is opened.
+ *
+ ****************************************************************************/
+
+static int up_setup(FAR struct uart_dev_s *dev)
+{
+#ifndef CONFIG_SUPPRESS_UART_CONFIG
+  FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->priv;
+  uint32_t lcr;
+  uint32_t cr;
+
+  cxd56_uart_setup(priv->id);
+
+  /* Init HW */
+
+  up_serialout(priv, CXD56_UART_CR, 0);
+  up_serialout(priv, CXD56_UART_LCR_H, 0);
+  up_serialout(priv, CXD56_UART_DMACR, 0);
+  up_serialout(priv, CXD56_UART_RSR_ECR, 0xf);
+
+  /* Set up the IER */
+
+  priv->ier = up_serialin(priv, CXD56_UART_IMSC);
+
+  /* Set the BAUD divisor */
+
+  cxd56_setbaud(priv->uartbase, priv->basefreq, priv->baud);
+
+  /* Set up the LCR */
+
+  lcr = 0;
+  if (priv->bits == 7)
+    {
+      lcr |= UART_LCR_WLEN(7);
+    }
+  else
+    {
+      lcr |= UART_LCR_WLEN(8);
+    }
+
+  if (priv->stopbits2)
+    {
+      lcr |= UART_LCR_STP2;
+    }
+
+  if (priv->parity == 1)
+    {
+      lcr |= (UART_LCR_PEN);
+    }
+  else if (priv->parity == 2)
+    {
+      lcr |= (UART_LCR_PEN | UART_LCR_EPS);
+    }
+
+  /* Save the LCR */
+
+  up_serialout(priv, CXD56_UART_LCR_H, lcr);
+
+  up_serialout(priv, CXD56_UART_IFLS, 0);
+  up_serialout(priv, CXD56_UART_ICR, 0x7ff);
+
+  cr = UART_CR_RXE | UART_CR_TXE;
+
+  /* Enable Auto-RTS and Auto-CS Flow Control in the Modem Control Register */
+
+#  ifdef CONFIG_UART1_FLOWCONTROL
+  if (priv->uartbase == CXD56_UART1_BASE)
+    {
+      cr |= UART_CR_CTSEN | UART_CR_RTSEN;
+    }
+#  endif
+
+  /* Enable Auto-RTS and Auto-CS Flow Control in UART2 */
+
+#  ifdef CONFIG_UART2_IFLOWCONTROL
+  if (priv->uartbase == CXD56_UART2_BASE)
+    {
+      cr |= UART_CR_RTSEN;
+    }
+#  endif
+#  ifdef CONFIG_UART2_OFLOWCONTROL
+  if (priv->uartbase == CXD56_UART2_BASE)
+    {
+      cr |= UART_CR_CTSEN;
+    }
+#  endif
+  up_serialout(priv, CXD56_UART_CR, cr);
+
+  /* Enable FIFO and UART in the last */
+
+  lcr |= UART_LCR_FEN;
+  up_serialout(priv, CXD56_UART_LCR_H, lcr);
+  cr |= UART_CR_EN;
+  up_serialout(priv, CXD56_UART_CR, cr);
+#endif
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_shutdown
+ *
+ * Description:
+ *   Disable the UART.  This method is called when the serial port is closed
+ *
+ ****************************************************************************/
+
+static void up_shutdown(FAR struct uart_dev_s *dev)
+{
+  FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->priv;
+
+  /* Disable further interrupts from the UART */
+
+  up_disableuartint(priv, NULL);
+
+  /* Put the UART hardware back its reset state */
+
+  switch (priv->id)
+    {
+      case 0:
+      case 1:
+      case 2:
+        cxd56_uart_reset(priv->id);
+        break;
+
+      default:
+        break;
+    }
+}
+
+/****************************************************************************
+ * Name: up_attach
+ *
+ * Description:
+ *   Configure the UART to operation in interrupt driven mode.  This method is
+ *   called when the serial port is opened.  Normally, this is just after the
+ *   the setup() method is called, however, the serial console may operate in
+ *   a non-interrupt driven mode during the boot phase.
+ *
+ *   RX and TX interrupts are not enabled when by the attach method (unless
+ *   the hardware supports multiple levels of interrupt enabling).  The RX and
+ *   TX interrupts are not enabled until the txint() and rxint() methods are
+ *   called.
+ *
+ ****************************************************************************/
+
+static int up_attach(FAR struct uart_dev_s *dev)
+{
+  FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->priv;
+  int ret;
+
+  /* Attach and enable the IRQ */
+
+  ret = irq_attach(priv->irq, up_interrupt, dev);
+  if (ret == OK)
+    {
+      /* Enable the interrupt (RX and TX interrupts are still disabled
+       * in the UART
+       */
+
+      up_enable_irq(priv->irq);
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_detach
+ *
+ * Description:
+ *   Detach UART interrupts.  This method is called when the serial port is
+ *   closed normally just before the shutdown method is called.  The exception
+ *   is the serial console which is never shutdown.
+ *
+ ****************************************************************************/
+
+static void up_detach(FAR struct uart_dev_s *dev)
+{
+  FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->priv;
+  up_disable_irq(priv->irq);
+  irq_detach(priv->irq);
+}
+
+/****************************************************************************
+ * Name: up_rxflowcontrol
+ *
+ * Description:
+ *   Called when Rx buffer is full (or exceeds configured watermark levels
+ *   if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined).
+ *   Return true if UART activated RX flow control to block more incoming
+ *   data
+ *
+ * Input parameters:
+ *   dev       - UART device instance
+ *   nbuffered - the number of characters currently buffered
+ *               (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is
+ *               not defined the value will be 0 for an empty buffer or the
+ *               defined buffer size for a full buffer)
+ *   upper     - true indicates the upper watermark was crossed where
+ *               false indicates the lower watermark has been crossed
+ *
+ * Returned Value:
+ *   true if RX flow control activated.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool up_rxflowcontrol(FAR struct uart_dev_s *dev,
+                             unsigned int nbuffered, bool upper)
+{
+  (void)nbuffered;
+
+  up_rxint(dev, !upper);
+
+  return true;
+}
+#endif /* CONFIG_SERIAL_IFLOWCONTROL */
+
+/****************************************************************************
+ * Name: up_interrupt
+ *
+ * Description:
+ *   This is the UART interrupt handler.  It will be invoked when an
+ *   interrupt received on the 'irq'  It should call uart_transmitchars or
+ *   uart_receivechar to perform the appropriate data transfers.  The
+ *   interrupt handling logic must be able to map the 'irq' number into the
+ *   appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int up_interrupt(int irq, FAR void *context, FAR void *arg)
+{
+  FAR struct uart_dev_s *dev = (FAR struct uart_dev_s *)arg;
+  FAR struct up_dev_s *priv;
+  uint32_t status;
+  int passes;
+
+  priv = (FAR struct up_dev_s *)dev->priv;
+
+  /* Loop until there are no characters to be transferred or,
+   * until we have been looping for a long time.
+   */
+
+  for (passes = 0; passes < 256; passes++)
+    {
+      /* Get the current UART status and check for loop
+       * termination conditions
+       */
+
+      status = up_serialin(priv, CXD56_UART_MIS);
+      if (status == 0)
+        {
+          return OK;
+        }
+
+      up_serialout(priv, CXD56_UART_ICR, status);
+      if (status & UART_INTR_RI)
+        {
+        }
+
+      if (status & UART_INTR_CTS)
+        {
+        }
+
+      if (status & UART_INTR_DCD)
+        {
+        }
+
+      if (status & UART_INTR_DSR)
+        {
+        }
+
+      if (status & (UART_INTR_RX | UART_INTR_RT))
+        {
+          uart_recvchars(dev);
+        }
+
+      if (status & UART_INTR_TX)
+        {
+          uart_xmitchars(dev);
+        }
+
+      if (status & UART_INTR_FE)
+        {
+        }
+
+      if (status & UART_INTR_PE)
+        {
+        }
+
+      if (status & UART_INTR_BE)
+        {
+        }
+
+      if (status & UART_INTR_OE)
+        {
+        }
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_ioctl
+ *
+ * Description:
+ *   All ioctl calls will be routed through this method
+ *
+ ****************************************************************************/
+
+static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
+{
+  FAR struct inode *inode    = filep->f_inode;
+  FAR struct uart_dev_s *dev = inode->i_private;
+  FAR struct up_dev_s *priv  = (FAR struct up_dev_s *)dev->priv;
+  int ret                = OK;
+
+  switch (cmd)
+    {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+      case TIOCSERGSTRUCT:
+        {
+          FAR struct up_dev_s *user = (FAR struct up_dev_s *)arg;
+          if (!user)
+            {
+              ret = -EINVAL;
+            }
+          else
+            {
+              memcpy(user, dev, sizeof(struct up_dev_s));
+            }
+        }
+        break;
+#endif
+
+#ifdef CONFIG_SERIAL_TERMIOS
+      case TCGETS:
+        {
+          FAR struct termios *termiosp = (FAR struct termios *)arg;
+
+          if (!termiosp)
+            {
+              ret = -EINVAL;
+              break;
+            }
+
+          /* TODO:  Other termios fields are not yet returned.
+           * Note that only cfsetospeed is not necessary because we have
+           * knowledge that only one speed is supported.
+           */
+
+          cfsetispeed(termiosp, priv->baud);
+        }
+        break;
+
+      case TCSETS:
+        {
+          FAR struct termios *termiosp = (FAR struct termios *)arg;
+
+          if (!termiosp)
+            {
+              ret = -EINVAL;
+              break;
+            }
+
+          /* TODO:  Handle other termios settings.
+           * Note that only cfgetispeed is used besued we have knowledge
+           * that only one speed is supported.
+           */
+
+          priv->baud = cfgetispeed(termiosp);
+          cxd56_setbaud(priv->uartbase, priv->basefreq, priv->baud);
+        }
+        break;
+#endif
+
+      case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */
+        {
+          irqstate_t flags = enter_critical_section();
+          up_enablebreaks(priv, true);
+          leave_critical_section(flags);
+        }
+        break;
+
+      case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */
+        {
+          irqstate_t flags;
+          flags = enter_critical_section();
+          up_enablebreaks(priv, false);
+          leave_critical_section(flags);
+        }
+        break;
+
+      case TCFLSH: /* Flush TX fifo etc. */
+        {
+          while (!up_txempty(dev));
+        }
+        break;
+
+      default:
+        ret = -ENOTTY;
+        break;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_receive
+ *
+ * Description:
+ *   Called (usually) from the interrupt level to receive one
+ *   character from the UART.  Error bits associated with the
+ *   receipt are provided in the return 'status'.
+ *
+ ****************************************************************************/
+
+static int up_receive(FAR struct uart_dev_s *dev, FAR uint32_t *status)
+{
+  FAR struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+  uint32_t rbr;
+
+  rbr     = up_serialin(priv, CXD56_UART_DR);
+  *status = rbr & 0xf00;
+  return rbr & 0xff;
+}
+
+/****************************************************************************
+ * Name: up_rxint
+ *
+ * Description:
+ *   Call to enable or disable RX interrupts
+ *
+ ****************************************************************************/
+
+static void up_rxint(FAR struct uart_dev_s *dev, bool enable)
+{
+  FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->priv;
+  irqstate_t flags;
+
+  flags = enter_critical_section();
+  if (enable)
+    {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->ier |= (UART_INTR_RX | UART_INTR_RT);
+#endif
+    }
+  else
+    {
+      priv->ier &= ~(UART_INTR_RX | UART_INTR_RT);
+    }
+
+  up_serialout(priv, CXD56_UART_IMSC, priv->ier);
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: up_rxavailable
+ *
+ * Description:
+ *   Return true if the receive fifo is not empty
+ *
+ ****************************************************************************/
+
+static bool up_rxavailable(FAR struct uart_dev_s *dev)
+{
+  FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->priv;
+  return ((up_serialin(priv, CXD56_UART_FR) & UART_FLAG_RXFE) == 0);
+}
+
+/****************************************************************************
+ * Name: up_send
+ *
+ * Description:
+ *   This method will send one byte on the UART
+ *
+ ****************************************************************************/
+
+static void up_send(FAR struct uart_dev_s *dev, int ch)
+{
+  FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->priv;
+  up_serialout(priv, CXD56_UART_DR, (uint32_t)ch);
+}
+
+/****************************************************************************
+ * Name: up_txint
+ *
+ * Description:
+ *   Call to enable or disable TX interrupts
+ *
+ ****************************************************************************/
+
+static void up_txint(FAR struct uart_dev_s *dev, bool enable)
+{
+  FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->priv;
+  irqstate_t flags;
+
+  flags = enter_critical_section();
+  if (enable)
+    {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      priv->ier |= UART_INTR_TX;
+      up_serialout(priv, CXD56_UART_IMSC, priv->ier);
+
+      /* Fake a TX interrupt here by just calling uart_xmitchars() with
+       * interrupts disabled (note this may recurse).
+       */
+
+      uart_xmitchars(dev);
+#endif
+    }
+  else
+    {
+      priv->ier &= ~UART_INTR_TX;
+      up_serialout(priv, CXD56_UART_IMSC, priv->ier);
+    }
+
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: up_txready
+ *
+ * Description:
+ *   Return true if the tranmsit fifo is not full
+ *
+ ****************************************************************************/
+
+static bool up_txready(FAR struct uart_dev_s *dev)
+{
+  FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->priv;
+  return ((up_serialin(priv, CXD56_UART_FR) & UART_FLAG_TXFF) == 0);
+}
+
+/****************************************************************************
+ * Name: up_txempty
+ *
+ * Description:
+ *   Return true if the transmit fifo is empty
+ *
+ ****************************************************************************/
+
+static bool up_txempty(FAR struct uart_dev_s *dev)
+{
+  FAR struct up_dev_s *priv = (FAR struct up_dev_s *)dev->priv;
+  uint32_t rbr = 0;
+  rbr = up_serialin(priv, CXD56_UART_FR);
+  return (((rbr & UART_FLAG_TXFE) != 0) && ((rbr & UART_FLAG_BUSY) == 0));
+}
+
+/****************************************************************************
+ * Public Funtions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Performs the low level UART initialization early in debug so that the
+ *   serial console will be available during bootup.  This must be called
+ *   before up_serialinit.
+ *
+ *   NOTE: Configuration of the CONSOLE UART was performed by up_lowsetup()
+ *   very early in the boot sequence.
+ *
+ ****************************************************************************/
+
+#ifdef USE_EARLYSERIALINIT
+void up_earlyserialinit(void)
+{
+  /* Configuration whichever one is the console */
+
+#  ifdef CONSOLE_DEV
+  CONSOLE_DEV.isconsole = true;
+  up_setup(&CONSOLE_DEV);
+#  endif
+}
+#endif
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Register serial console and serial ports.  This assumes that
+ *   up_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+void up_serialinit(void)
+{
+#ifdef CONSOLE_DEV
+  (void)uart_register("/dev/console", &CONSOLE_DEV);
+#endif
+#ifdef TTYS0_DEV
+  (void)uart_register("/dev/ttyS0", &TTYS0_DEV);
+#endif
+#ifdef TTYS2_DEV
+  (void)uart_register("/dev/ttyS2", &TTYS2_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug  writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_CONSOLE
+  struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv;
+  uint32_t ier;
+  up_disableuartint(priv, &ier);
+#endif
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_lowputc('\r');
+    }
+
+  up_lowputc(ch);
+#ifdef HAVE_CONSOLE
+  up_restoreuartint(priv, ier);
+#endif
+
+  return ch;
+}
+
+#else /* USE_SERIALDRIVER */
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_UART
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_lowputc('\r');
+    }
+
+  up_lowputc(ch);
+#endif
+  return ch;
+}
+
+#endif /* USE_SERIALDRIVER */
diff --git a/arch/arm/src/cxd56xx/cxd56_serial.h b/arch/arm/src/cxd56xx/cxd56_serial.h
new file mode 100644
index 00000000000..58368cdfd8e
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_serial.h
@@ -0,0 +1,66 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_serial.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_SERIAL_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56_SERIAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include "cxd56_uart.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_SERIAL_H */
diff --git a/arch/arm/src/cxd56xx/cxd56_start.c b/arch/arm/src/cxd56xx/cxd56_start.c
new file mode 100644
index 00000000000..c786536492b
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_start.c
@@ -0,0 +1,362 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_start.c
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ *   Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* Power-Up Reset Overview
+ * -----------------------
+ *
+ * The ARM core starts executing code on reset with the program counter set
+ * to 0x0000:0000.  The CXD56xx contains a shadow pointer register that
+ * allows areas of memory to be mapped to address 0x0000:0000. The default,
+ * reset value of the shadow pointer is 0x1040:0000 so that on reset code in
+ * the boot ROM is always executed first.
+ *
+ * The boot starts after reset is released.  The IRC is selected as CPU clock
+ * and the Cortex-M4 starts the boot loader. By default the JTAG access to the
+ * chip is disabled at reset.  The boot ROM determines the boot mode based on
+ * the OTP BOOT_SRC value or reset state pins.  For flash-based parts, the part
+ * boots from internal flash by default.  Otherwse, the boot ROM copies the
+ * image to internal SRAM at location 0x1000:0000, sets the ARM's shadow
+ * pointer to 0x1000:0000, and jumps to that location.
+ *
+ * However, using JTAG the executable image can be also loaded directly into
+ * and executed from SRAM.
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+#include "nvic.h"
+#include "sched/sched.h"
+#include "init/init.h"
+
+#include "cxd56_uart.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CXD56_BOOT_ENTRY_POINT      (0x04100000 + 0x1400)
+
+/* XXX */
+
+void weak_function up_cpuctxload(void);
+
+/****************************************************************************
+ * Private Function prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_STACK_COLORATION
+static void go_nx_start(void *pv, unsigned int nbytes)
+  __attribute__((naked, no_instrument_function, noreturn));
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: showprogress
+ *
+ * Description:
+ *   Print a character on the UART to show boot status.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_FEATURES
+#  define showprogress(c) up_lowputc(c)
+#else
+#  define showprogress(c)
+#endif
+
+#define DEFPRIORITY32 \
+  (CXD56M4_SYSH_PRIORITY_DEFAULT << 24 | CXD56M4_SYSH_PRIORITY_DEFAULT << 16 | \
+   CXD56M4_SYSH_PRIORITY_DEFAULT << 8 | CXD56M4_SYSH_PRIORITY_DEFAULT)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+extern uint32_t _vectors[];
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: fpuconfig
+ *
+ * Description:
+ *   Configure the FPU.  Relative bit settings:
+ *
+ *     CPACR:  Enables access to CP10 and CP11
+ *     CONTROL.FPCA: Determines whether the FP extension is active in the
+ *       current context:
+ *     FPCCR.ASPEN:  Enables automatic FP state preservation, then the
+ *       processor sets this bit to 1 on successful completion of any FP
+ *       instruction.
+ *     FPCCR.LSPEN:  Enables lazy context save of FP state. When this is
+ *       done, the processor reserves space on the stack for the FP state,
+ *       but does not save that state information to the stack.
+ *
+ *  Software must not change the value of the ASPEN bit or LSPEN bit while
+ *  either:
+ *   - the CPACR permits access to CP10 and CP11, that give access to the FP
+ *     extension, or
+ *   - the CONTROL.FPCA bit is set to 1
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_FPU
+#  ifndef CONFIG_ARMV7M_LAZYFPU
+
+static inline void fpuconfig(void)
+{
+  uint32_t regval;
+
+  /* Set CONTROL.FPCA so that we always get the extended context frame
+   * with the volatile FP registers stacked above the basic context.
+   */
+
+  regval  = getcontrol();
+  regval |= (1 << 2);
+  setcontrol(regval);
+
+  /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
+   * with the lazy FP context save behaviour.  Clear FPCCR.ASPEN since we
+   * are going to turn on CONTROL.FPCA for all contexts.
+   */
+
+  regval  = getreg32(NVIC_FPCCR);
+  regval &= ~((1 << 31) | (1 << 30));
+  putreg32(regval, NVIC_FPCCR);
+
+  /* Enable full access to CP10 and CP11 */
+
+  regval  = getreg32(NVIC_CPACR);
+  regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
+  putreg32(regval, NVIC_CPACR);
+}
+
+#  else
+
+static inline void fpuconfig(void)
+{
+  uint32_t regval;
+
+  /* Clear CONTROL.FPCA so that we do not get the extended context frame
+   * with the volatile FP registers stacked in the saved context.
+   */
+
+  regval  = getcontrol();
+  regval &= ~(1 << 2);
+  setcontrol(regval);
+
+  /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
+   * with the lazy FP context save behaviour.  Clear FPCCR.ASPEN since we
+   * are going to keep CONTROL.FPCA off for all contexts.
+   */
+
+  regval  = getreg32(NVIC_FPCCR);
+  regval &= ~((1 << 31) | (1 << 30));
+  putreg32(regval, NVIC_FPCCR);
+
+  /* Enable full access to CP10 and CP11 */
+
+  regval  = getreg32(NVIC_CPACR);
+  regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
+  putreg32(regval, NVIC_CPACR);
+}
+
+#  endif
+
+#else
+#  define fpuconfig()
+#endif
+
+/****************************************************************************
+ * Name: go_nx_start
+ *
+ * Description:
+ *   Set the IDLE stack to the
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STACK_COLORATION
+static void go_nx_start(void *pv, unsigned int nbytes)
+{
+  /* Set the IDLE stack to the stack coloration value then jump to
+   * nx_start().  We take extreme care here because were currently
+   * executing on this stack.
+   *
+   * We want to avoid sneak stack access generated by the compiler.
+   */
+
+  __asm__ __volatile__
+  (
+    "\tmovs r1, r1, lsr #2\n"   /* R1 = nwords = nbytes >> 2 */
+    "\tbeq  2f\n"               /* (should not happen) */
+
+    "\tbic  r0, r0, #3\n"       /* R0 = Aligned stackptr */
+    "\tmovw r2, #0xbeef\n"      /* R2 = STACK_COLOR = 0xdeadbeef */
+    "\tmovt r2, #0xdead\n"
+
+    "1:\n"                      /* Top of the loop */
+    "\tsub  r1, r1, #1\n"       /* R1 nwords-- */
+    "\tcmp  r1, #0\n"           /* Check (nwords == 0) */
+    "\tstr  r2, [r0], #4\n"     /* Save stack color word, increment stackptr */
+    "\tbne  1b\n"               /* Bottom of the loop */
+
+    "2:\n"
+    "\tmov  r14, #0\n"          /* LR = return address (none) */
+    "\tb    nx_start\n"         /* Branch to nx_start */
+  );
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _start
+ *
+ * Description:
+ *   This is the reset entry point.
+ *
+ ****************************************************************************/
+
+void __start(void)
+{
+  uint32_t *dest;
+
+  /* Set MSP/PSP to IDLE stack */
+
+  __asm__ __volatile__("\tmsr msp, %0\n" :
+                       : "r" ((uint32_t)&_ebss +
+                              CONFIG_IDLETHREAD_STACKSIZE - 4));
+  __asm__ __volatile__("\tmsr psp, %0\n" :
+                       : "r" ((uint32_t)&_ebss +
+                              CONFIG_IDLETHREAD_STACKSIZE - 4));
+
+  up_irq_disable();
+
+  if (*((uint32_t *)CXD56_BOOT_ENTRY_POINT))
+    {
+#ifdef CONFIG_HAVE_WEAKFUNCTIONS
+      if (up_cpuctxload)
+#endif
+        {
+          up_cpuctxload();
+        }
+    }
+
+  /* Enable bus snoop */
+
+  putreg32(0, CXD56_EXCCONF_BASE + 0);
+
+  cxd56_lowsetup();
+  showprogress('A');
+
+  /* Clear .bss.  We'll do this inline (vs. calling memset) just to be
+   * certain that there are no issues with the state of global variables.
+   */
+
+  for (dest = &_sbss; dest < &_ebss; )
+    {
+      *dest++ = 0;
+    }
+
+  /* Initialize the FPU (if configured) */
+
+  fpuconfig();
+
+  /* Perform early serial initialization */
+
+#ifdef USE_EARLYSERIALINIT
+  up_earlyserialinit();
+#endif
+  showprogress('E');
+
+  /* For the case of the separate user-/kernel-space build, perform whatever
+   * platform specific initialization of the user memory is required.
+   * Normally this just means initializing the user space .data and .bss
+   * segments.
+   */
+
+#ifdef CONFIG_BUILD_PROTECTED
+  showprogress('F');
+#endif
+
+  /* Initialize onboard resources */
+
+  cxd56_boardinitialize();
+  showprogress('G');
+
+  /* Then start NuttX */
+
+  showprogress('\r');
+  showprogress('\n');
+
+#ifdef CONFIG_STACK_COLORATION
+  /* Set the IDLE stack to the coloration value and jump into nx_start() */
+
+  go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE);
+#else
+  /* Call nx_start() */
+
+  nx_start();
+
+  /* Shouldn't get here */
+
+  for (; ; );
+#endif
+}
diff --git a/arch/arm/src/cxd56xx/cxd56_timerisr.c b/arch/arm/src/cxd56xx/cxd56_timerisr.c
new file mode 100644
index 00000000000..f7f66ab08e9
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_timerisr.c
@@ -0,0 +1,152 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_timerisr.c
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "nvic.h"
+#include "clock/clock.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The desired timer interrupt frequency is provided by the definition
+ * CLK_TCK (see include/time.h).  CLK_TCK defines the desired number of
+ * system clock ticks per second.  That value is a user configurable setting
+ * that defaults to 100 (100 ticks per second = 10 MS interval).
+ *
+ * The Clock Source: Either the internal CCLK or external STCLK (P3.26) clock
+ * as the source in the STCTRL register.  This file alwyays configures the
+ * timer to use CCLK as its source.
+ */
+
+static uint32_t g_systrvr;
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int cxd56_timerisr(int irq, uint32_t *regs, FAR void *arg);
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  cxd56_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for various portions
+ *   of the systems.
+ *
+ ****************************************************************************/
+
+static int cxd56_timerisr(int irq, uint32_t *regs, FAR void *arg)
+{
+  /* Process timer interrupt */
+
+  nxsched_process_timer();
+  return 0;
+}
+
+/****************************************************************************
+ * Function:  arm_timer_initialize
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ****************************************************************************/
+
+void arm_timer_initialize(void)
+{
+  uint32_t regval;
+
+  /* Set the SysTick interrupt to the default priority */
+
+  regval = getreg32(NVIC_SYSH12_15_PRIORITY);
+  regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
+  regval |= (CXD56M4_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
+  putreg32(regval, NVIC_SYSH12_15_PRIORITY);
+
+  /* Make sure that the SYSTICK clock source is set to use the CXD56xx CCLK */
+
+  regval = getreg32(NVIC_SYSTICK_CTRL);
+  regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
+  putreg32(regval, NVIC_SYSTICK_CTRL);
+
+  /* Configure SysTick to interrupt at the requested rate */
+
+  g_systrvr = (CXD56_CCLK / CLK_TCK) - 1;
+  putreg32(g_systrvr, NVIC_SYSTICK_RELOAD);
+
+  /* Attach the timer interrupt vector */
+
+  (void)irq_attach(CXD56_IRQ_SYSTICK, (xcpt_t)cxd56_timerisr, NULL);
+
+  /* Enable SysTick interrupts */
+
+  putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
+            NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
+
+  /* And enable the timer interrupt */
+
+  up_enable_irq(CXD56_IRQ_SYSTICK);
+}
diff --git a/arch/arm/src/cxd56xx/cxd56_timerisr.h b/arch/arm/src/cxd56xx/cxd56_timerisr.h
new file mode 100644
index 00000000000..67531f57680
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_timerisr.h
@@ -0,0 +1,89 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_timerisr.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_TIMERISR_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56_TIMERISR_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_timerisr_initialize
+ *
+ * Description:
+ *   initialize timerisr
+ *
+ *
+ ****************************************************************************/
+
+int cxd56_timerisr_initialize(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_TIMERISR_H */
diff --git a/arch/arm/src/cxd56xx/cxd56_uart.c b/arch/arm/src/cxd56xx/cxd56_uart.c
new file mode 100644
index 00000000000..7b596c28d83
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_uart.c
@@ -0,0 +1,328 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_uart.c
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include 
+#include 
+
+#include 
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "cxd56_config.h"
+#include "cxd56_uart.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Select UART parameters for the selected console */
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#  define CONSOLE_BASE     CXD56_UART0_BASE
+#  define CONSOLE_BASEFREQ BOARD_UART0_BASEFREQ
+#  define CONSOLE_BAUD     CONFIG_UART0_BAUD
+#  define CONSOLE_BITS     CONFIG_UART0_BITS
+#  define CONSOLE_PARITY   CONFIG_UART0_PARITY
+#  define CONSOLE_2STOP    CONFIG_UART0_2STOP
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#  define CONSOLE_BASE     CXD56_UART1_BASE
+#  define CONSOLE_BASEFREQ BOARD_UART1_BASEFREQ
+#  define CONSOLE_BAUD     CONFIG_UART1_BAUD
+#  define CONSOLE_BITS     CONFIG_UART1_BITS
+#  define CONSOLE_PARITY   CONFIG_UART1_PARITY
+#  define CONSOLE_2STOP    CONFIG_UART1_2STOP
+#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
+#  define CONSOLE_BASE     CXD56_UART2_BASE
+#  define CONSOLE_BASEFREQ BOARD_UART2_BASEFREQ
+#  define CONSOLE_BAUD     CONFIG_UART2_BAUD
+#  define CONSOLE_BITS     CONFIG_UART2_BITS
+#  define CONSOLE_PARITY   CONFIG_UART2_PARITY
+#  define CONSOLE_2STOP    CONFIG_UART2_2STOP
+#elif defined(HAVE_CONSOLE)
+#  error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
+#endif
+
+/* Get word length setting for the console */
+
+#if CONSOLE_BITS >= 5 && CONSOLE_BITS <= 8
+#  define CONSOLE_LCR_WLS UART_LCR_WLEN(CONSOLE_BITS)
+#elif defined(HAVE_CONSOLE)
+#  error "Invalid CONFIG_UARTn_BITS setting for console "
+#endif
+
+/* Get parity setting for the console */
+
+#if CONSOLE_PARITY == 0
+#  define CONSOLE_LCR_PAR 0
+#elif CONSOLE_PARITY == 1
+#  define CONSOLE_LCR_PAR (UART_LCR_PEN)
+#elif CONSOLE_PARITY == 2
+#  define CONSOLE_LCR_PAR (UART_LCR_PEN | UART_LCR_EPS)
+#elif CONSOLE_PARITY == 3
+#  define CONSOLE_LCR_PAR (UART_LCR_PEN | UART_LCR_SPS)
+#elif CONSOLE_PARITY == 4
+#  define CONSOLE_LCR_PAR (UART_LCR_PEN | UART_LCR_EPS | UART_LCR_SPS)
+#elif defined(HAVE_CONSOLE)
+#  error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE"
+#endif
+
+/* Get stop-bit setting for the console and UART0/1/2 */
+
+#if CONSOLE_2STOP != 0
+#  define CONSOLE_LCR_STOP UART_LCR_STP2
+#else
+#  define CONSOLE_LCR_STOP 0
+#endif
+
+/* LCR and FCR values for the console */
+
+#define CONSOLE_LCR_VALUE (CONSOLE_LCR_WLS | CONSOLE_LCR_PAR | CONSOLE_LCR_STOP)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct uartdev
+{
+  uintptr_t uartbase; /* Base address of UART registers */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static struct uartdev g_uartdevs[] =
+{
+  {
+    CXD56_UART0_BASE
+  },
+  {
+    CXD56_UART1_BASE
+  },
+  {
+    CXD56_UART2_BASE
+  }
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_lowputc
+ *
+ * Description:
+ *   Output one byte on the serial console
+ *
+ ****************************************************************************/
+
+void up_lowputc(char ch)
+{
+#if defined HAVE_UART && defined HAVE_CONSOLE
+  /* Wait for the transmitter to be available */
+
+  while ((getreg32(CONSOLE_BASE + CXD56_UART_FR) & UART_FLAG_TXFF));
+
+  /* Send the character */
+
+  putreg32((uint32_t)ch, CONSOLE_BASE + CXD56_UART_DR);
+#endif
+}
+
+/****************************************************************************
+ * Name: cxd56_lowsetup
+ *
+ * Description:
+ *   This performs basic initialization of the UART used for the serial
+ *   console.  Its purpose is to get the console output availabe as soon
+ *   as possible.
+ *
+ *   The USART0/2/3 and UART1 peripherals are configured using the following
+ *   registers:
+ *   1. Baud rate: In the LCR register, set bit DLAB = 1. This enables access
+ *      to registers DLL and DLM for setting the baud rate. Also, if needed,
+ *      set the fractional baud rate in the fractional divider
+ *   2. UART FIFO: Use bit FIFO enable (bit 0) in FCR register to
+ *      enable FIFO.
+ *   3. Pins: Select UART pins through the PINSEL registers and pin modes
+ *      through the PINMODE registers. UART receive pins should not have
+ *      pull-down resistors enabled.
+ *   4. Interrupts: To enable UART interrupts set bit DLAB = 0 in the LCRF
+ *      register. This enables access to IER. Interrupts are enabled
+ *      in the NVIC using the appropriate Interrupt Set Enable register.
+ *   5. DMA: UART transmit and receive functions can operate with the
+ *      GPDMA controller.
+ *
+ ****************************************************************************/
+
+void cxd56_lowsetup(void)
+{
+#ifdef HAVE_UART
+  /* Enable clocking and  for all console UART and disable power for
+   * other UARTs
+   */
+
+#  if defined(CONFIG_UART0_SERIAL_CONSOLE)
+  cxd56_uart_setup(0);
+#  elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+  cxd56_uart_setup(1);
+#  elif defined(CONFIG_UART2_SERIAL_CONSOLE)
+  cxd56_uart_setup(2);
+#  endif
+
+  /* Configure the console (only) */
+
+#  if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
+  {
+    uint32_t val;
+
+    val = getreg32(CONSOLE_BASE + CXD56_UART_CR);
+    if (val & UART_CR_EN)
+      {
+        return;
+      }
+  }
+
+  putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE + CXD56_UART_LCR_H);
+  cxd56_setbaud(CONSOLE_BASE, CONSOLE_BASEFREQ, CONSOLE_BAUD);
+  putreg32(0, CONSOLE_BASE + CXD56_UART_IFLS);
+  putreg32(UART_INTR_ALL, CONSOLE_BASE + CXD56_UART_ICR);
+
+#  endif
+#endif /* HAVE_UART */
+}
+
+/****************************************************************************
+ * Name: cxd56_uart_reset
+ *
+ * Description:
+ *   Reset a UART.  These functions are used by the serial driver when a
+ *   UART is closed.
+ *
+ ****************************************************************************/
+
+void cxd56_uart_reset(int ch)
+{
+}
+
+void cxd56_uart_setup(int ch)
+{
+  uint32_t cr;
+  uint32_t lcr;
+
+  /* TODO: clock configuration */
+
+#ifdef CONFIG_CXD56_UART2
+  if (ch == 2)
+    {
+      /* Not supported yet. */
+
+      return;
+    }
+#endif /* CONFIG_CXD56_UART2 */
+
+  cr = getreg32(g_uartdevs[ch].uartbase + CXD56_UART_CR);
+  putreg32(cr & ~(1 << 0), g_uartdevs[ch].uartbase + CXD56_UART_CR);
+
+  lcr = getreg32(g_uartdevs[ch].uartbase + CXD56_UART_LCR_H);
+  putreg32(lcr & ~(1 << 4), g_uartdevs[ch].uartbase + CXD56_UART_LCR_H);
+
+  putreg32(cr, g_uartdevs[ch].uartbase + CXD56_UART_CR);
+}
+
+/****************************************************************************
+ * Name: cxd56_setbaud
+ *
+ ****************************************************************************/
+
+void cxd56_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud)
+{
+  uint32_t ibrd;
+  uint32_t fbrd;
+  uint32_t div;
+  uint32_t lcr_h;
+  irqstate_t flags = enter_critical_section();
+
+  div  = basefreq / (16 * baud / 100);
+  ibrd = div / 100;
+
+  /* fbrd will be up to 63.
+   * ((99 * 64 + 50) / 100 = 6386 / 100 = 63)
+   */
+
+  fbrd = (((div % 100) * 64) + 50) / 100;
+
+  /* Check invalid baud rate divider setting combination. */
+
+  if (ibrd == 0 || (ibrd == 65535 && fbrd != 0))
+    {
+      goto finish;
+    }
+
+  putreg32(ibrd, uartbase + CXD56_UART_IBRD);
+  putreg32(fbrd, uartbase + CXD56_UART_FBRD);
+
+  /* Baud rate is updated by writing to LCR_H. */
+
+  lcr_h = getreg32(uartbase + CXD56_UART_LCR_H);
+  putreg32(lcr_h, uartbase + CXD56_UART_LCR_H);
+
+finish:
+  leave_critical_section(flags);
+}
diff --git a/arch/arm/src/cxd56xx/cxd56_uart.h b/arch/arm/src/cxd56xx/cxd56_uart.h
new file mode 100644
index 00000000000..d3d2e079f41
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_uart.h
@@ -0,0 +1,142 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_uart.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ *   Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_UART_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56_UART_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include "chip.h"
+#include "hardware/cxd56_uart.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_lowsetup
+ *
+ * Description:
+ *   Called at the very beginning of _start.  Performs low level
+ *   initialization of the serial console.
+ *
+ ****************************************************************************/
+
+void cxd56_lowsetup(void);
+
+/****************************************************************************
+ * Name: cxd56_uart_reset
+ *
+ * Description:
+ *   Reset a U[S]ART.  These functions are used by the serial driver when a
+ *   U[S]ART is closed.
+ *
+ ****************************************************************************/
+
+void cxd56_uart_reset(int ch);
+
+/****************************************************************************
+ * Name: cxd56_uart_setup
+ *
+ * Description:
+ *   Configure the UART.  This involves:
+ *
+ *   1. Connecting the input clock to the UART as specified in the
+ *      board.h file,
+ *   2. Configuring the UART pins
+ *
+ ****************************************************************************/
+
+void cxd56_uart_setup(int);
+
+/****************************************************************************
+ * Name: cxd56_setbaud
+ *
+ * Description:
+ *   Configure the U[S]ART divisors to accomplish the desired BAUD given the
+ *   U[S]ART base frequency.
+ *
+ *   This computationally intensive algorithm is based on the same logic
+ *   used in the NXP sample code.
+ *
+ ****************************************************************************/
+
+void cxd56_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud);
+
+/****************************************************************************
+ * Name: cxd56_uart_initialize
+ *
+ * Description:
+ *   Various initial registration
+ *
+ ****************************************************************************/
+
+int cxd56_uart_initialize(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_UART_H */
diff --git a/arch/arm/src/cxd56xx/cxd56_usbdev.c b/arch/arm/src/cxd56xx/cxd56_usbdev.c
new file mode 100644
index 00000000000..4620a5ae09f
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_usbdev.c
@@ -0,0 +1,3497 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_usbdev.c
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+#include "cxd56_clock.h"
+#include "cxd56_usbdev.h"
+#include "hardware/cxd5602_topreg.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* TOPREG VBUS regsiter */
+
+#define CLR_EDGE (1 << 9)
+#define CLR_EN   (1 << 8)
+#define VBUS_DET (1 << 0)
+
+/* Configuration ************************************************************/
+
+#ifndef CONFIG_USBDEV_MAXPOWER
+#  define CONFIG_USBDEV_MAXPOWER 100  /* mA */
+#endif
+
+/* Vendor ID & Product ID of the USB device */
+
+#ifndef CONFIG_CXD56_VENDORID
+#  define CONFIG_CXD56_VENDORID     0x054c
+#endif
+
+#ifndef CONFIG_CXD56_PRODUCTID
+#  define CONFIG_CXD56_PRODUCTID    0x0bc2
+#endif
+
+#ifndef CONFIG_USBDEV_EP0_MAXSIZE
+#  define CONFIG_USBDEV_EP0_MAXSIZE 64
+#endif
+
+#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE
+#  define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE
+#endif
+
+#define CONFIG_DEFAULT_PHY_CFG0 \
+  (PHY_STAGSELECT | PHY_HSFALLCNTRL | PHY_IHSTX(0xc) | PHY_INHSRFRED | \
+   PHY_INHSIPLUS | PHY_INHSDRVSLEW| PHY_INLFSFBCAP)
+
+#ifndef __aligned
+#  define __aligned(x) __attribute__((aligned(x)))
+#endif
+
+/* Debug **********************************************************************/
+
+/* Trace error codes */
+
+#define CXD56_TRACEERR_ALLOCFAIL         0x0001
+#define CXD56_TRACEERR_ATTACHIRQREG      0x0002
+#define CXD56_TRACEERR_BINDFAILED        0x0003
+#define CXD56_TRACEERR_COREIRQREG        0x0004
+#define CXD56_TRACEERR_DRIVER            0x0005
+#define CXD56_TRACEERR_DRIVERREGISTERED  0x0006
+#define CXD56_TRACEERR_EPREAD            0x0007
+#define CXD56_TRACEERR_EWRITE            0x0008
+#define CXD56_TRACEERR_INVALIDPARMS      0x0009
+#define CXD56_TRACEERR_NOEP              0x000a
+#define CXD56_TRACEERR_NOTCONFIGURED     0x000b
+#define CXD56_TRACEERR_NULLPACKET        0x000c
+#define CXD56_TRACEERR_NULLREQUEST       0x000d
+#define CXD56_TRACEERR_REQABORTED        0x000e
+#define CXD56_TRACEERR_STALLEDCLRFEATURE 0x000f
+#define CXD56_TRACEERR_STALLEDISPATCH    0x0010
+#define CXD56_TRACEERR_STALLEDGETST      0x0011
+#define CXD56_TRACEERR_STALLEDGETSTEP    0x0012
+#define CXD56_TRACEERR_STALLEDGETSTRECIP 0x0013
+#define CXD56_TRACEERR_STALLEDREQUEST    0x0014
+#define CXD56_TRACEERR_STALLEDSETFEATURE 0x0015
+#define CXD56_TRACEERR_TXREQLOST         0x0016
+#define CXD56_TRACEERR_RXREQLOST         0x0017
+#define CXD56_TRACEERR_VBUSIRQREG        0x0018
+#define CXD56_TRACEERR_VBUSNIRQREG       0x0019
+
+/* Trace interrupt codes */
+
+#define CXD56_TRACEINTID_USB             0x0001
+#define CXD56_TRACEINTID_SYS             0x0002
+#define CXD56_TRACEINTID_VBUS            0x0004
+#define CXD56_TRACEINTID_VBUSN           0x0008
+
+#define CXD56_TRACEINTID_RMTWKP          1
+#define CXD56_TRACEINTID_ENUM            2
+#define CXD56_TRACEINTID_SOF             3
+#define CXD56_TRACEINTID_US              4
+#define CXD56_TRACEINTID_UR              5
+#define CXD56_TRACEINTID_ES              6
+#define CXD56_TRACEINTID_SI              7
+#define CXD56_TRACEINTID_SC              8
+#define CXD56_TRACEINTID_GETSTATUS       9
+#define CXD56_TRACEINTID_GETIFDEV        10
+#define CXD56_TRACEINTID_CLEARFEATURE    11
+#define CXD56_TRACEINTID_SETFEATURE      12
+#define CXD56_TRACEINTID_TESTMODE        13
+#define CXD56_TRACEINTID_SETADDRESS      14
+#define CXD56_TRACEINTID_GETSETDESC      15
+#define CXD56_TRACEINTID_GETSETIFCONFIG  16
+#define CXD56_TRACEINTID_SYNCHFRAME      17
+#define CXD56_TRACEINTID_DISPATCH        18
+#define CXD56_TRACEINTID_GETENDPOINT     19
+#define CXD56_TRACEINTID_RESUME          20
+#define CXD56_TRACEINTID_CDCCLEAR        21
+#define CXD56_TRACEINTID_TXDMAERROR      22
+#define CXD56_TRACEINTID_RXDMAERROR      23
+#define CXD56_TRACEINTID_TXBNA           24
+#define CXD56_TRACEINTID_RXBNA           25
+#define CXD56_TRACEINTID_XFERDONE        26
+#define CXD56_TRACEINTID_TXEMPTY         27
+#define CXD56_TRACEINTID_TDC             28
+#define CXD56_TRACEINTID_IN              29
+#define CXD56_TRACEINTID_EPOUTQEMPTY     31
+#define CXD56_TRACEINTID_OUTSETUP        32
+#define CXD56_TRACEINTID_OUTDATA         33
+
+#ifdef CONFIG_USBDEV_TRACE_STRINGS
+const struct trace_msg_t g_usb_trace_strings_intdecode[] =
+{
+  TRACE_STR(CXD56_TRACEINTID_RMTWKP),
+  TRACE_STR(CXD56_TRACEINTID_ENUM),
+  TRACE_STR(CXD56_TRACEINTID_SOF),
+  TRACE_STR(CXD56_TRACEINTID_US),
+  TRACE_STR(CXD56_TRACEINTID_UR),
+  TRACE_STR(CXD56_TRACEINTID_ES),
+  TRACE_STR(CXD56_TRACEINTID_SI),
+  TRACE_STR(CXD56_TRACEINTID_SC),
+  TRACE_STR(CXD56_TRACEINTID_GETSTATUS),
+  TRACE_STR(CXD56_TRACEINTID_GETIFDEV),
+  TRACE_STR(CXD56_TRACEINTID_CLEARFEATURE),
+  TRACE_STR(CXD56_TRACEINTID_SETFEATURE),
+  TRACE_STR(CXD56_TRACEINTID_TESTMODE),
+  TRACE_STR(CXD56_TRACEINTID_SETADDRESS),
+  TRACE_STR(CXD56_TRACEINTID_GETSETDESC),
+  TRACE_STR(CXD56_TRACEINTID_GETSETIFCONFIG),
+  TRACE_STR(CXD56_TRACEINTID_SYNCHFRAME),
+  TRACE_STR(CXD56_TRACEINTID_DISPATCH),
+  TRACE_STR(CXD56_TRACEINTID_GETENDPOINT),
+  TRACE_STR(CXD56_TRACEINTID_RESUME),
+  TRACE_STR(CXD56_TRACEINTID_CDCCLEAR),
+  TRACE_STR(CXD56_TRACEINTID_TXDMAERROR),
+  TRACE_STR(CXD56_TRACEINTID_RXDMAERROR),
+  TRACE_STR(CXD56_TRACEINTID_TXBNA),
+  TRACE_STR(CXD56_TRACEINTID_RXBNA),
+  TRACE_STR(CXD56_TRACEINTID_XFERDONE),
+  TRACE_STR(CXD56_TRACEINTID_TXEMPTY),
+  TRACE_STR(CXD56_TRACEINTID_TDC),
+  TRACE_STR(CXD56_TRACEINTID_IN),
+  TRACE_STR(CXD56_TRACEINTID_EPOUTQEMPTY),
+  TRACE_STR(CXD56_TRACEINTID_OUTSETUP),
+  TRACE_STR(CXD56_TRACEINTID_OUTDATA),
+  TRACE_STR_END
+};
+
+const struct trace_msg_t g_usb_trace_strings_deverror[] =
+{
+  TRACE_STR(CXD56_TRACEERR_ALLOCFAIL),
+  TRACE_STR(CXD56_TRACEERR_ATTACHIRQREG),
+  TRACE_STR(CXD56_TRACEERR_BINDFAILED),
+  TRACE_STR(CXD56_TRACEERR_COREIRQREG),
+  TRACE_STR(CXD56_TRACEERR_DRIVER),
+  TRACE_STR(CXD56_TRACEERR_DRIVERREGISTERED),
+  TRACE_STR(CXD56_TRACEERR_EPREAD),
+  TRACE_STR(CXD56_TRACEERR_EWRITE),
+  TRACE_STR(CXD56_TRACEERR_INVALIDPARMS),
+  TRACE_STR(CXD56_TRACEERR_NOEP),
+  TRACE_STR(CXD56_TRACEERR_NOTCONFIGURED),
+  TRACE_STR(CXD56_TRACEERR_NULLPACKET),
+  TRACE_STR(CXD56_TRACEERR_NULLREQUEST),
+  TRACE_STR(CXD56_TRACEERR_REQABORTED),
+  TRACE_STR(CXD56_TRACEERR_STALLEDCLRFEATURE),
+  TRACE_STR(CXD56_TRACEERR_STALLEDISPATCH),
+  TRACE_STR(CXD56_TRACEERR_STALLEDGETST),
+  TRACE_STR(CXD56_TRACEERR_STALLEDGETSTEP),
+  TRACE_STR(CXD56_TRACEERR_STALLEDGETSTRECIP),
+  TRACE_STR(CXD56_TRACEERR_STALLEDREQUEST),
+  TRACE_STR(CXD56_TRACEERR_STALLEDSETFEATURE),
+  TRACE_STR(CXD56_TRACEERR_TXREQLOST),
+  TRACE_STR(CXD56_TRACEERR_RXREQLOST),
+  TRACE_STR(CXD56_TRACEERR_VBUSIRQREG),
+  TRACE_STR(CXD56_TRACEERR_VBUSNIRQREG),
+  TRACE_STR_END
+};
+#endif
+
+/* Hardware interface **********************************************************/
+
+/* The CXD56 hardware supports 8 configurable endpoints EP1-4, IN and OUT
+ * (in addition to EP0 IN and OUT).  This driver, however, does not exploit
+ * the full configuratability of the hardware at this time but, instead,
+ * supports the one interrupt IN, one bulk IN and one bulk OUT endpoint.
+ */
+
+/* Hardware dependent sizes and numbers */
+
+#define CXD56_EP0MAXPACKET       64   /* EP0 max packet size */
+#define CXD56_BULKMAXPACKET      512  /* Bulk endpoint max packet */
+#define CXD56_INTRMAXPACKET      64   /* Interrupt endpoint max packet */
+#define CXD56_EP0BUFSIZE         64   /* EP0 max packet size */
+#define CXD56_BULKBUFSIZE        1024 /* Bulk endpoint max packet */
+#define CXD56_INTRBUFSIZE        64   /* Interrupt endpoint max packet */
+#define CXD56_NENDPOINTS         7    /* Includes EP0 */
+
+/* Endpoint numbers */
+
+#define CXD56_EP0                0          /* Control endpoint */
+#define CXD56_EPBULKIN0          1          /* Bulk EP for send to host */
+#define CXD56_EPBULKOUT0         2          /* Bulk EP for recv to host */
+#define CXD56_EPINTRIN0          3          /* Intr EP for host poll */
+#define CXD56_EPBULKIN1          4          /* Bulk EP for send to host */
+#define CXD56_EPBULKOUT1         5          /* Bulk EP for recv to host */
+#define CXD56_EPINTRIN1          6          /* Intr EP for host poll */
+
+/* Request queue operations ****************************************************/
+
+#define cxd56_rqempty(ep)       ((ep)->head == NULL)
+#define cxd56_rqpeek(ep)        ((ep)->head)
+
+#define CXD56_USBDEV_LINELEN 32
+#define CXD56_USBDEV_TIMEOUT 1000
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct cxd56_setup_desc_s
+{
+  volatile uint32_t status;
+  volatile uint32_t reserved;
+  volatile uint32_t setup_1;
+  volatile uint32_t setup_2;
+};
+
+struct cxd56_data_desc_s
+{
+  volatile uint32_t status;
+  volatile uint32_t reserved;
+  volatile uint32_t buf;
+  volatile uint32_t next;
+};
+
+/* A container for a request so that the request make be retained in a list */
+
+struct cxd56_req_s
+{
+  struct usbdev_req_s req;   /* Standard USB request */
+  struct cxd56_req_s *flink; /* Supports a singly linked list */
+};
+
+/* This is the internal representation of an endpoint */
+
+struct cxd56_ep_s
+{
+  /* Common endpoint fields.  This must be the first thing defined in the
+   * structure so that it is possible to simply cast from struct usbdev_ep_s
+   * to struct cxd56_ep_s.
+   */
+
+  struct usbdev_ep_s ep; /* Standard endpoint structure */
+
+  /* CXD56-specific fields */
+
+  struct cxd56_usbdev_s *dev; /* Reference to private driver data */
+  struct cxd56_req_s *head;   /* Request list for this endpoint */
+  struct cxd56_req_s *tail;
+  struct cxd56_data_desc_s *desc; /* DMA descriptor */
+  void *buffer;                   /* OUT only, receiving data buffer */
+  uint8_t epphy;                  /* Physical EP address/index */
+  uint8_t stalled : 1;            /* Endpoint is halted */
+  uint8_t in : 1;                 /* Endpoint is IN only */
+  uint8_t halted : 1;             /* Endpoint feature halted */
+  uint8_t txnullpkt : 1;          /* Null packet needed at end of transfer */
+  uint8_t txwait : 1;             /* IN transaction already requested from host */
+};
+
+/* This structure encapsulates the overall driver state */
+
+struct cxd56_usbdev_s
+{
+  /* Common device fields.  This must be the first thing defined in the
+   * structure so that it is possible to simply cast from struct usbdev_s
+   * to struct cxd56_usbdev_s.
+   */
+
+  struct usbdev_s usbdev;
+
+  /* The bound device class driver */
+
+  struct usbdevclass_driver_s *driver;
+
+  /* CXD56-specific fields */
+
+  uint8_t stalled : 1;     /* 1: Protocol stalled */
+  uint8_t selfpowered : 1; /* 1: Device is self powered */
+  uint8_t paddrset : 1;    /* 1: Peripheral addr has been set */
+  uint8_t attached : 1;    /* 1: Host attached */
+  uint8_t paddr;           /* Peripheral address */
+  uint8_t avail;
+
+  /* E0 SETUP data buffering.
+   *
+   * ctrl
+   *   The 8-byte SETUP request is received on the EP0 OUT endpoint and is
+   *   saved.
+   *
+   * ep0data
+   *   For OUT SETUP requests, the SETUP data phase must also complete before
+   *   the SETUP command can be processed.
+   *
+   * ep0datlen
+   *   Lenght of OUT DATA received in ep0data[]
+   */
+
+  struct usb_ctrlreq_s ctrl; /* Last EP0 request */
+
+  uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE];
+  uint16_t ep0datlen;
+
+  /* The endpoint list */
+
+  struct cxd56_ep_s eplist[CXD56_NENDPOINTS];
+
+  /* attach status */
+
+  int state;
+  int power;
+
+  /* signal */
+
+  int signo;
+  int pid;
+};
+
+/* For maintaining tables of endpoint info */
+
+struct cxd56_epinfo_s
+{
+  uint8_t addr;       /* Logical endpoint address */
+  uint8_t attr;       /* Endpoint attributes */
+  uint16_t maxpacket; /* Max packet size */
+  uint16_t bufsize;   /* Buffer size */
+};
+
+/* This structure describes one open "file" */
+
+struct cxd56_usbdev_file_s
+{
+  struct procfs_file_s base; /* Base open file structure */
+  unsigned int linesize;     /* Number of valid characters in line[] */
+
+  /* Pre-allocated buffer for formatted lines */
+
+  char line[CXD56_USBDEV_LINELEN];
+};
+
+static struct pm_cpu_freqlock_s g_hv_lock =
+  PM_CPUFREQLOCK_INIT(PM_CPUFREQLOCK_TAG('U', 'S', 0), PM_CPUFREQLOCK_FLAG_HV);
+static struct pm_cpu_wakelock_s g_wake_lock =
+{
+  .count = 0,
+  .info  = PM_CPUWAKELOCK_TAG('U', 'S', 0),
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Request queue operations *************************************************/
+
+static FAR struct cxd56_req_s *cxd56_rqdequeue(FAR struct cxd56_ep_s *privep);
+static void cxd56_rqenqueue(FAR struct cxd56_ep_s *privep,
+                            FAR struct cxd56_req_s *req);
+
+/* Low level data transfers and request operations */
+
+static int cxd56_epwrite(FAR struct cxd56_ep_s *privep, FAR uint8_t *buf,
+                         uint16_t nbytes);
+static inline void cxd56_abortrequest(FAR struct cxd56_ep_s *privep,
+                                      FAR struct cxd56_req_s *privreq,
+                                      int16_t result);
+static void cxd56_reqcomplete(FAR struct cxd56_ep_s *privep, int16_t result);
+static int cxd56_wrrequest(FAR struct cxd56_ep_s *privep);
+static int cxd56_rdrequest(FAR struct cxd56_ep_s *privep);
+static void cxd56_cancelrequests(FAR struct cxd56_ep_s *privep);
+static void cxd56_usbdevreset(FAR struct cxd56_usbdev_s *priv);
+static void cxd56_usbreset(FAR struct cxd56_usbdev_s *priv);
+
+/* Interrupt handling */
+
+static FAR struct cxd56_ep_s *
+  cxd56_epfindbyaddr(FAR struct cxd56_usbdev_s *priv, uint16_t eplog);
+static void cxd56_dispatchrequest(FAR struct cxd56_usbdev_s *priv);
+static inline void cxd56_ep0setup(FAR struct cxd56_usbdev_s *priv);
+static int cxd56_usbinterrupt(int irq, FAR void *context, FAR void *arg);
+static int cxd56_sysinterrupt(int irq, FAR void *context, FAR void *arg);
+static int cxd56_vbusinterrupt(int irq, FAR void *context, FAR void *arg);
+static int cxd56_vbusninterrupt(int irq, FAR void *context, FAR void *arg);
+
+/* Initialization operations */
+
+static inline void cxd56_ep0hwinitialize(FAR struct cxd56_usbdev_s *priv);
+static void cxd56_ctrlinitialize(FAR struct cxd56_usbdev_s *priv);
+static void cxd56_epinitialize(FAR struct cxd56_usbdev_s *priv);
+
+/* Un-initialization operations */
+
+static void cxd56_usbhwuninit(void);
+
+/* Endpoint methods */
+
+static int cxd56_epconfigure(FAR struct usbdev_ep_s *ep,
+                             FAR const struct usb_epdesc_s *desc, bool last);
+static int cxd56_epdisable(FAR struct usbdev_ep_s *ep);
+static FAR struct usbdev_req_s *cxd56_epallocreq(FAR struct usbdev_ep_s *ep);
+static void cxd56_epfreereq(FAR struct usbdev_ep_s *ep,
+                            FAR struct usbdev_req_s *req);
+#ifdef CONFIG_USBDEV_DMA
+static FAR void *cxd56_epallocbuffer(FAR struct usbdev_ep_s *ep,
+                                     uint16_t nbytes);
+static void cxd56_epfreebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf);
+#endif
+static int cxd56_epsubmit(FAR struct usbdev_ep_s *ep,
+                          FAR struct usbdev_req_s *privreq);
+static int cxd56_epcancel(FAR struct usbdev_ep_s *ep,
+                          FAR struct usbdev_req_s *privreq);
+static int cxd56_epstall(FAR struct usbdev_ep_s *ep, bool resume);
+
+/* USB device controller methods */
+
+static FAR struct usbdev_ep_s *cxd56_allocep(FAR struct usbdev_s *dev,
+                                             uint8_t epno, bool in,
+                                             uint8_t eptype);
+static void cxd56_freeep(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep);
+static int cxd56_getframe(FAR struct usbdev_s *dev);
+static int cxd56_wakeup(FAR struct usbdev_s *dev);
+static int cxd56_selfpowered(FAR struct usbdev_s *dev, bool selfpowered);
+static int cxd56_pullup(FAR struct usbdev_s *dev, bool enable);
+
+/* Notify USB device attach/detach signal */
+
+static void cxd56_notify_signal(uint16_t state, uint16_t power);
+
+#ifdef CONFIG_FS_PROCFS
+
+/* procfs methods */
+
+static int cxd56_usbdev_open(FAR struct file *filep, FAR const char *relpath,
+                             int oflags, mode_t mode);
+static int cxd56_usbdev_close(FAR struct file *filep);
+static ssize_t cxd56_usbdev_read(FAR struct file *filep, FAR char *buffer,
+                                 size_t buflen);
+static int cxd56_usbdev_dup(FAR const struct file *oldp, FAR struct file *newp);
+static int cxd56_usbdev_stat(FAR const char *relpath, FAR struct stat *buf);
+
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Endpoint methods */
+
+static const struct usbdev_epops_s g_epops =
+{
+  .configure   = cxd56_epconfigure,
+  .disable     = cxd56_epdisable,
+  .allocreq    = cxd56_epallocreq,
+  .freereq     = cxd56_epfreereq,
+#ifdef CONFIG_USBDEV_DMA
+  .allocbuffer = cxd56_epallocbuffer,
+  .freebuffer  = cxd56_epfreebuffer,
+#endif
+  .submit      = cxd56_epsubmit,
+  .cancel      = cxd56_epcancel,
+  .stall       = cxd56_epstall,
+};
+
+/* USB controller device methods */
+
+static const struct usbdev_ops_s g_devops =
+{
+  .allocep     = cxd56_allocep,
+  .freeep      = cxd56_freeep,
+  .getframe    = cxd56_getframe,
+  .wakeup      = cxd56_wakeup,
+  .selfpowered = cxd56_selfpowered,
+  .pullup      = cxd56_pullup,
+};
+
+/* There is only one, single, pre-allocated instance of the driver structure */
+
+static struct cxd56_usbdev_s g_usbdev;
+
+/* DMA Descriptors for each endpoints */
+
+static struct cxd56_setup_desc_s __aligned(4) g_ep0setup;
+static struct cxd56_data_desc_s __aligned(4) g_ep0in;
+static struct cxd56_data_desc_s __aligned(4) g_ep0out;
+
+/* Summarizes information about all CXD56 endpoints */
+
+static const struct cxd56_epinfo_s g_epinfo[CXD56_NENDPOINTS] =
+{
+  {
+    CXD56_EP0,                /* EP0 */
+    USB_EP_ATTR_XFER_CONTROL, /* Type: Control IN/OUT */
+    CXD56_EP0MAXPACKET,       /* Max packet size */
+    CXD56_EP0BUFSIZE,         /* Buffer size */
+  },
+  {
+    CXD56_EPBULKIN0 | USB_DIR_IN, /* Logical endpoint number: 1 IN */
+    USB_EP_ATTR_XFER_BULK,        /* Type: Bulk */
+    CXD56_BULKMAXPACKET,          /* Max packet size */
+    CXD56_BULKBUFSIZE,            /* Buffer size */
+  },
+  {
+    CXD56_EPBULKOUT0 | USB_DIR_OUT, /* Logical endpoint number: 2 OUT */
+    USB_EP_ATTR_XFER_BULK,          /* Type: Bulk */
+    CXD56_BULKMAXPACKET,            /* Max packet size */
+    CXD56_BULKBUFSIZE,              /* Buffer size */
+  },
+  {
+    CXD56_EPINTRIN0 | USB_DIR_IN, /* Logical endpoint number: 3 IN */
+    USB_EP_ATTR_XFER_INT,         /* Type: Interrupt */
+    CXD56_INTRMAXPACKET,          /* Max packet size */
+    CXD56_INTRBUFSIZE,            /* Buffer size */
+  },
+  {
+    CXD56_EPBULKIN1 | USB_DIR_IN, /* Logical endpoint number: 4 IN */
+    USB_EP_ATTR_XFER_BULK,        /* Type: Bulk */
+    CXD56_BULKMAXPACKET,          /* Max packet size */
+    CXD56_BULKBUFSIZE,            /* Buffer size */
+  },
+  {
+    CXD56_EPBULKOUT1 | USB_DIR_OUT, /* Logical endpoint number: 5 OUT */
+    USB_EP_ATTR_XFER_BULK,          /* Type: Bulk */
+    CXD56_BULKMAXPACKET,            /* Max packet size */
+    CXD56_BULKBUFSIZE,              /* Buffer size */
+  },
+  {
+    CXD56_EPINTRIN1 | USB_DIR_IN, /* Logical endpoint number: 6 IN */
+    USB_EP_ATTR_XFER_INT,         /* Type: Interrupt */
+    CXD56_INTRMAXPACKET,          /* Max packet size */
+    CXD56_INTRBUFSIZE,            /* Buffer size */
+  }};
+
+static uint8_t g_ep0outbuffer[CXD56_EP0MAXPACKET];
+
+#ifdef CONFIG_FS_PROCFS
+
+/* See include/nutts/fs/procfs.h
+ * We use the old-fashioned kind of initializers so that this will compile
+ * with any compiler.
+ */
+
+const struct procfs_operations cxd56_usbdev_operations =
+{
+  cxd56_usbdev_open,  /* open */
+  cxd56_usbdev_close, /* close */
+  cxd56_usbdev_read,  /* read */
+  NULL,               /* write */
+  cxd56_usbdev_dup,   /* dup */
+
+  NULL,               /* opendir */
+  NULL,               /* closedir */
+  NULL,               /* readdir */
+  NULL,               /* rewinddir */
+
+  cxd56_usbdev_stat   /* stat */
+};
+
+#  ifdef CONFIG_FS_PROCFS_REGISTER
+static const struct procfs_entry_s g_procfs_usbdev =
+{
+  "usbdev",
+  &cxd56_usbdev_operations
+};
+#  endif
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_cablestatus
+ *
+ * Description:
+ *   Set VBUS connected status to system register
+ *
+ ****************************************************************************/
+
+static inline void cxd56_cableconnected(bool connected)
+{
+  uint32_t val;
+
+  val = getreg32(CXD56_TOPREG_USB_VBUS);
+  if (connected)
+    {
+      putreg32(val | VBUS_DET, CXD56_TOPREG_USB_VBUS);
+    }
+  else
+    {
+      putreg32(val & ~VBUS_DET, CXD56_TOPREG_USB_VBUS);
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_iscableconnected
+ *
+ * Description:
+ *   Return the cable status. (true is connected)
+ *
+ ****************************************************************************/
+
+static inline bool cxd56_iscableconnected(void)
+{
+  return getreg32(CXD56_TOPREG_USB_VBUS) & VBUS_DET;
+}
+
+/****************************************************************************
+ * Name: cxd56_rqdequeue
+ *
+ * Description:
+ *   Remove a request from an endpoint request queue
+ *
+ ****************************************************************************/
+
+static FAR struct cxd56_req_s *cxd56_rqdequeue(FAR struct cxd56_ep_s *privep)
+{
+  FAR struct cxd56_req_s *ret = privep->head;
+
+  if (ret)
+    {
+      privep->head = ret->flink;
+      if (!privep->head)
+        {
+          privep->tail = NULL;
+        }
+
+      ret->flink = NULL;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_rqenqueue
+ *
+ * Description:
+ *   Add a request from an endpoint request queue
+ *
+ ****************************************************************************/
+
+static void cxd56_rqenqueue(FAR struct cxd56_ep_s *privep,
+                            FAR struct cxd56_req_s *req)
+{
+  req->flink = NULL;
+  if (!privep->head)
+    {
+      privep->head = req;
+      privep->tail = req;
+    }
+  else
+    {
+      privep->tail->flink = req;
+      privep->tail        = req;
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_epwrite
+ *
+ * Description:
+ *   Endpoint write (IN)
+ *
+ ****************************************************************************/
+
+static int cxd56_epwrite(FAR struct cxd56_ep_s *privep, FAR uint8_t *buf,
+                         uint16_t nbytes)
+{
+  FAR struct cxd56_data_desc_s *desc;
+  uint32_t ctrl;
+  uint8_t epphy = privep->epphy;
+
+  /* Setup IN descriptor */
+
+  desc = epphy == 0 ? &g_ep0in : privep->desc;
+
+  if (IS_BS_DMA_BUSY(desc))
+    {
+      return 0;
+    }
+
+  desc->buf    = (uint32_t)(uintptr_t)buf;
+  desc->status = nbytes | DESC_LAST; /* always last descriptor */
+
+  /* Set Poll bit to ready to send */
+
+  ctrl = getreg32(CXD56_USB_IN_EP_CONTROL(epphy));
+
+  /* Send NULL packet request */
+
+  if (privep->txnullpkt)
+    {
+      ctrl |= USB_SENDNULL;
+    }
+
+  putreg32(ctrl | USB_P | USB_CNAK, CXD56_USB_IN_EP_CONTROL(epphy));
+
+  return nbytes;
+}
+
+/****************************************************************************
+ * Name: cxd56_abortrequest
+ *
+ * Description:
+ *   Discard a request
+ *
+ ****************************************************************************/
+
+static inline void cxd56_abortrequest(FAR struct cxd56_ep_s *privep,
+                                      FAR struct cxd56_req_s *privreq,
+                                      int16_t result)
+{
+  usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_REQABORTED), (uint16_t)privep->epphy);
+
+  /* Save the result in the request structure */
+
+  privreq->req.result = result;
+
+  /* Callback to the request completion handler */
+
+  privreq->req.callback(&privep->ep, &privreq->req);
+}
+
+/****************************************************************************
+ * Name: cxd56_reqcomplete
+ *
+ * Description:
+ *   Handle termination of a request.
+ *
+ ****************************************************************************/
+
+static void cxd56_reqcomplete(FAR struct cxd56_ep_s *privep, int16_t result)
+{
+  FAR struct cxd56_req_s *privreq;
+  int stalled = privep->stalled;
+  irqstate_t flags;
+
+  /* Remove the completed request at the head of the endpoint request list */
+
+  flags   = enter_critical_section();
+  privreq = cxd56_rqdequeue(privep);
+  leave_critical_section(flags);
+
+  if (privreq)
+    {
+      /* If endpoint 0, temporarily reflect the state of protocol stalled
+       * in the callback.
+       */
+
+      if (privep->epphy == CXD56_EP0)
+        {
+          privep->stalled = privep->dev->stalled;
+        }
+
+      /* Save the result in the request structure */
+
+      privreq->req.result = result;
+
+      /* Callback to the request completion handler */
+
+      privreq->flink = NULL;
+      privreq->req.callback(&privep->ep, &privreq->req);
+
+      /* Restore the stalled indication */
+
+      privep->stalled = stalled;
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_txdmacomplete
+ *
+ * Description:
+ *   DMA transfer to TxFIFO is completed.
+ *   if exist queued request, do the next transfer request.
+ *
+ ****************************************************************************/
+
+static void cxd56_txdmacomplete(FAR struct cxd56_ep_s *privep)
+{
+  FAR struct cxd56_data_desc_s *desc;
+  FAR struct cxd56_req_s *privreq;
+
+  desc = privep->epphy == CXD56_EP0 ? &g_ep0in : privep->desc;
+
+  /* Avoid invalid transfer by USB Core */
+
+  DEBUGASSERT(IS_BS_DMA_DONE(desc));
+
+  desc->status |= DESC_BS_HOST_BUSY;
+
+  privreq = cxd56_rqpeek(privep);
+  if (!privreq)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_TXREQLOST), privep->epphy);
+    }
+  else
+    {
+      privreq->req.xfrd += desc->status & DESC_SIZE_MASK;
+
+      if (privreq->req.xfrd >= privreq->req.len && !privep->txnullpkt)
+        {
+          usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd);
+          privep->txnullpkt = 0;
+          cxd56_reqcomplete(privep, OK);
+        }
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_wrrequest
+ *
+ * Description:
+ *   Send from the next queued write request
+ *
+ * Returned Value:
+ *  0:not finished; 1:completed; <0:error
+ *
+ ****************************************************************************/
+
+static int cxd56_wrrequest(FAR struct cxd56_ep_s *privep)
+{
+  FAR struct cxd56_req_s *privreq;
+  FAR uint8_t *buf;
+  int nbytes;
+  int bytesleft;
+
+  /* Check the request from the head of the endpoint request queue */
+
+  privreq = cxd56_rqpeek(privep);
+  if (!privreq)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_NULLREQUEST), 0);
+      return OK;
+    }
+
+  /* Ignore any attempt to send a zero length packet on anything but EP0IN */
+
+  if (privreq->req.len == 0)
+    {
+      if (privep->epphy == CXD56_EP0)
+        {
+          cxd56_epwrite(privep, NULL, 0);
+        }
+      else
+        {
+          usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_NULLPACKET), 0);
+        }
+      return OK;
+    }
+
+  /* Get the number of bytes left to be sent in the packet */
+
+  bytesleft = privreq->req.len - privreq->req.xfrd;
+
+  /* Send the next packet if (1) there are more bytes to be sent, or
+   * (2) the last packet sent was exactly maxpacketsize (bytesleft == 0)
+   */
+
+  usbtrace(TRACE_WRITE(privep->epphy), (uint16_t)bytesleft);
+  if (bytesleft > 0 || privep->txnullpkt)
+    {
+      /* Try to send maxpacketsize -- unless we don't have that many
+       * bytes to send.
+       */
+
+      privep->txnullpkt = 0;
+      if (bytesleft > privep->ep.maxpacket)
+        {
+          nbytes = privep->ep.maxpacket;
+        }
+      else
+        {
+          nbytes = bytesleft;
+          if ((privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0)
+            {
+              privep->txnullpkt = (bytesleft == privep->ep.maxpacket);
+            }
+        }
+
+      /* Send the largest number of bytes that we can in this packet */
+
+      buf = privreq->req.buf + privreq->req.xfrd;
+      cxd56_epwrite(privep, buf, nbytes);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_rxdmacomplete
+ *
+ * Description:
+ *   Notify the upper layer and continue to next receive request.
+ *
+ ****************************************************************************/
+
+static void cxd56_rxdmacomplete(FAR struct cxd56_ep_s *privep)
+{
+  FAR struct cxd56_data_desc_s *desc = privep->desc;
+  FAR struct cxd56_req_s *privreq;
+  uint32_t status = desc->status;
+  uint16_t nrxbytes;
+
+  nrxbytes = status & DESC_SIZE_MASK;
+
+  privreq = cxd56_rqpeek(privep);
+  if (!privreq)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_RXREQLOST), privep->epphy);
+      return;
+    }
+
+  desc->status = DESC_BS_HOST_BUSY;
+
+  if ((status & DESC_BS_MASK) == DESC_BS_DMA_DONE)
+    {
+      privreq->req.xfrd += nrxbytes;
+
+      if (privreq->req.xfrd >= privreq->req.len ||
+          nrxbytes < privep->ep.maxpacket)
+        {
+          usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd);
+          cxd56_reqcomplete(privep, OK);
+        }
+    }
+  else
+    {
+      uerr("Descriptor status error %08x\n", status);
+    }
+
+  cxd56_rdrequest(privep);
+}
+
+/****************************************************************************
+ * Name: cxd56_rdrequest
+ *
+ * Description:
+ *   Receive to the next queued read request
+ *
+ ****************************************************************************/
+
+static int cxd56_rdrequest(FAR struct cxd56_ep_s *privep)
+{
+  FAR struct cxd56_data_desc_s *desc = privep->desc;
+  FAR struct cxd56_req_s *privreq;
+  uint32_t ctrl;
+
+  /* Check the request from the head of the endpoint request queue */
+
+  privreq = cxd56_rqpeek(privep);
+  if (!privreq)
+    {
+      usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_EPOUTQEMPTY), 0);
+      return OK;
+    }
+
+  /* Receive the next packet */
+
+  if (!IS_BS_HOST_BUSY(desc))
+    {
+      return OK;
+    }
+
+  usbtrace(TRACE_READ(privep->epphy), privep->ep.maxpacket);
+
+  desc->buf    = (uint32_t)(uintptr_t)privreq->req.buf;
+  desc->status = privep->ep.maxpacket | DESC_LAST;
+
+  /* Ready to receive next packet */
+
+  ctrl = getreg32(CXD56_USB_OUT_EP_CONTROL(privep->epphy));
+  putreg32(ctrl | USB_RRDY | USB_CNAK, CXD56_USB_OUT_EP_CONTROL(privep->epphy));
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_stopinep
+ *
+ * Description:
+ *   Stop IN endpoint forcibly
+ *
+ ****************************************************************************/
+
+static void cxd56_stopinep(FAR struct cxd56_ep_s *privep)
+{
+  uint32_t ctrl;
+
+  /* Stop TX */
+
+  ctrl = getreg32(CXD56_USB_IN_EP_CONTROL(privep->epphy));
+  ctrl |= USB_F;
+  putreg32(ctrl, CXD56_USB_IN_EP_CONTROL(privep->epphy));
+}
+
+/****************************************************************************
+ * Name: cxd56_stopoutep
+ *
+ * Description:
+ *   Stop OUT endpoint forcibly
+ *
+ ****************************************************************************/
+
+static void cxd56_stopoutep(FAR struct cxd56_ep_s *privep)
+{
+  uint32_t ctrl;
+  uint32_t stat;
+
+  /* Stop RX if FIFO not empty */
+
+  stat = getreg32(CXD56_USB_OUT_EP_STATUS(privep->epphy));
+  if (stat & USB_INT_MRXFIFOEMPTY)
+    {
+      return;
+    }
+
+  ctrl = getreg32(CXD56_USB_OUT_EP_CONTROL(privep->epphy));
+  ctrl |= USB_CLOSEDESC | USB_MRXFLUSH;
+  putreg32(ctrl, CXD56_USB_OUT_EP_CONTROL(privep->epphy));
+}
+
+/****************************************************************************
+ * Name: cxd56_cancelrequests
+ *
+ * Description:
+ *   Cancel all pending requests for an endpoint
+ *
+ ****************************************************************************/
+
+static void cxd56_cancelrequests(FAR struct cxd56_ep_s *privep)
+{
+  if (privep->epphy > 0)
+    {
+      if (privep->in)
+        {
+          cxd56_stopinep(privep);
+        }
+      else
+        {
+          cxd56_stopoutep(privep);
+        }
+    }
+
+  while (!cxd56_rqempty(privep))
+    {
+      usbtrace(TRACE_COMPLETE(privep->epphy), (cxd56_rqpeek(privep))->req.xfrd);
+      cxd56_reqcomplete(privep, -ESHUTDOWN);
+    }
+
+  if (privep->epphy > 0)
+    {
+      if (privep->in)
+        {
+          putreg32(0, CXD56_USB_IN_EP_DATADESC(privep->epphy));
+        }
+      else
+        {
+          putreg32(0, CXD56_USB_OUT_EP_DATADESC(privep->epphy));
+        }
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_epfindbyaddr
+ *
+ * Description:
+ *   Find the physical endpoint structure corresponding to a logic endpoint
+ *   address
+ *
+ ****************************************************************************/
+
+static FAR struct cxd56_ep_s *
+cxd56_epfindbyaddr(FAR struct cxd56_usbdev_s *priv, uint16_t eplog)
+{
+  FAR struct cxd56_ep_s *privep;
+  int i;
+
+  /* Endpoint zero is a special case */
+
+  if (USB_EPNO(eplog) == 0)
+    {
+      return &priv->eplist[0];
+    }
+
+  /* Handle the remaining */
+
+  for (i = 1; i < CXD56_NENDPOINTS; i++)
+    {
+      privep = &priv->eplist[i];
+
+      /* Same logical endpoint number? (includes direction bit) */
+
+      if (eplog == privep->ep.eplog)
+        {
+          /* Return endpoint found */
+
+          return privep;
+        }
+    }
+
+  /* Return endpoint not found */
+
+  return NULL;
+}
+
+/****************************************************************************
+ * Name: cxd56_dispatchrequest
+ *
+ * Description:
+ *   Provide unhandled setup actions to the class driver
+ *
+ ****************************************************************************/
+
+static void cxd56_dispatchrequest(FAR struct cxd56_usbdev_s *priv)
+{
+  int ret;
+
+  usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_DISPATCH), 0);
+  if (priv && priv->driver)
+    {
+      ret = CLASS_SETUP(priv->driver, &priv->usbdev, &priv->ctrl, priv->ep0data,
+                        priv->ep0datlen);
+      if (ret < 0)
+        {
+          /* Stall on failure */
+
+          usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_STALLEDISPATCH),
+                   priv->ctrl.req);
+          priv->stalled = 1;
+        }
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_ep0setup
+ *
+ * Description:
+ *   USB Ctrl EP Setup Event
+ *
+ ****************************************************************************/
+
+static inline void cxd56_ep0setup(FAR struct cxd56_usbdev_s *priv)
+{
+  FAR struct cxd56_ep_s *ep0      = &priv->eplist[0];
+  FAR struct cxd56_req_s *privreq = cxd56_rqpeek(ep0);
+  FAR struct cxd56_ep_s *privep;
+  uint16_t index;
+  uint16_t value;
+  uint16_t len;
+  uint32_t reg;
+
+  /* Terminate any pending requests */
+
+  while (!cxd56_rqempty(ep0))
+    {
+      int16_t result = OK;
+      if (privreq->req.xfrd != privreq->req.len)
+        {
+          result = -EPROTO;
+        }
+
+      usbtrace(TRACE_COMPLETE(ep0->epphy), privreq->req.xfrd);
+      cxd56_reqcomplete(ep0, result);
+    }
+
+  /* Assume NOT stalled */
+
+  ep0->stalled  = 0;
+  priv->stalled = 0;
+
+  /* Read EP0 SETUP data */
+
+  memcpy(&priv->ctrl, (void *)&g_ep0setup.setup_1, USB_SIZEOF_CTRLREQ);
+  memset(&g_ep0setup, 0, USB_SIZEOF_CTRLREQ);
+
+  index = GETUINT16(priv->ctrl.index);
+  value = GETUINT16(priv->ctrl.value);
+  len   = GETUINT16(priv->ctrl.len);
+
+  uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+        priv->ctrl.type, priv->ctrl.req, value, index, len);
+
+  ep0->in = (priv->ctrl.type & USB_DIR_IN) != 0;
+
+  /* Is this an setup with OUT and data of length > 0 */
+
+  if (USB_REQ_ISOUT(priv->ctrl.type) && len != priv->ep0datlen)
+    {
+      /* At this point priv->ctrl is the setup packet. */
+
+      return;
+    }
+
+  /* Dispatch any non-standard requests */
+
+  if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD)
+    {
+      cxd56_dispatchrequest(priv);
+    }
+  else
+    {
+      /* Handle standard request.  Pick off the things of interest to the
+       * USB device controller driver; pass what is left to the class driver
+       */
+
+      switch (priv->ctrl.req)
+        {
+          case USB_REQ_GETSTATUS:
+            {
+              /* type:  device-to-host; recipient = device, interface, endpoint
+               * value: 0
+               * index: zero interface endpoint
+               * len:   2; data = status
+               */
+
+              usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_GETSTATUS), 0);
+
+              if (len != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 || value != 0)
+                {
+                  usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_STALLEDGETST),
+                           priv->ctrl.req);
+                  priv->stalled = 1;
+                }
+              else
+                {
+                  switch (priv->ctrl.type & USB_REQ_RECIPIENT_MASK)
+                    {
+                      case USB_REQ_RECIPIENT_ENDPOINT:
+                        {
+                          usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_GETENDPOINT),
+                                   0);
+                          privep = cxd56_epfindbyaddr(priv, index);
+                          if (!privep)
+                            {
+                              usbtrace(
+                                TRACE_DEVERROR(CXD56_TRACEERR_STALLEDGETSTEP),
+                                priv->ctrl.type);
+                              priv->stalled = 1;
+                            }
+                        }
+                        break;
+
+                      case USB_REQ_RECIPIENT_DEVICE:
+                      case USB_REQ_RECIPIENT_INTERFACE:
+                        usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_GETIFDEV), 0);
+                        break;
+
+                      default:
+                        {
+                          usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_STALLEDGETSTRECIP),
+                                   priv->ctrl.type);
+                          priv->stalled = 1;
+                        }
+                        break;
+                    }
+                }
+            }
+            break;
+
+          case USB_REQ_CLEARFEATURE:
+            {
+              /* type:  host-to device; recipient = device, interface or endpoint
+               * value: feature selector
+               * index: zero interface endpoint;
+               * len:   zero, data = none
+               */
+
+              usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_CLEARFEATURE),
+                       (uint16_t)priv->ctrl.req);
+              if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) !=
+                  USB_REQ_RECIPIENT_ENDPOINT)
+                {
+                  cxd56_dispatchrequest(priv);
+                }
+              else if (priv->paddrset != 0 && value == USB_FEATURE_ENDPOINTHALT &&
+                       len == 0 &&
+                       (privep = cxd56_epfindbyaddr(priv, index)) != NULL)
+                {
+                  privep->halted = 0;
+                  cxd56_epstall(&privep->ep, true);
+                  cxd56_epwrite(ep0, NULL, 0);
+                }
+              else
+                {
+                  usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_STALLEDCLRFEATURE),
+                           priv->ctrl.type);
+                  priv->stalled = 1;
+                }
+            }
+            break;
+
+          case USB_REQ_SETFEATURE:
+            {
+              /* type:  host-to-device; recipient = device, interface, endpoint
+               * value: feature selector
+               * index: zero interface endpoint;
+               * len:   0; data = none
+               */
+
+              usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_SETFEATURE), 0);
+              if (priv->ctrl.type == USB_REQ_RECIPIENT_DEVICE &&
+                  value == USB_FEATURE_TESTMODE)
+                {
+                  usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_TESTMODE), index);
+                }
+              else if (priv->ctrl.type != USB_REQ_RECIPIENT_ENDPOINT)
+                {
+                  cxd56_dispatchrequest(priv);
+                }
+              else if (value == USB_FEATURE_ENDPOINTHALT && len == 0 &&
+                       (privep = cxd56_epfindbyaddr(priv, index)) != NULL)
+                {
+                  privep->halted = 1;
+                }
+              else
+                {
+                  usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_STALLEDSETFEATURE),
+                           priv->ctrl.type);
+                  priv->stalled = 1;
+                }
+            }
+            break;
+
+          case USB_REQ_SETADDRESS:
+            {
+              /* type:  host-to-device; recipient = device
+               * value: device address
+               * index: 0
+               * len:   0; data = none
+               */
+
+              usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_SETADDRESS), 0);
+              priv->paddr = value & 0xff;
+            }
+            break;
+
+          case USB_REQ_GETDESCRIPTOR:
+            /* type:  device-to-host; recipient = device
+             * value: descriptor type and index
+             * index: 0 or language ID;
+             * len:   descriptor len; data = descriptor
+             */
+          case USB_REQ_SETDESCRIPTOR:
+            /* type:  host-to-device; recipient = device
+             * value: descriptor type and index
+             * index: 0 or language ID;
+             * len:   descriptor len; data = descriptor
+             */
+            {
+              usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_GETSETDESC), 0);
+              cxd56_dispatchrequest(priv);
+            }
+            break;
+
+          case USB_REQ_GETCONFIGURATION:
+            /* type:  device-to-host; recipient = device
+             * value: 0;
+             * index: 0;
+             * len:   1; data = configuration value
+             */
+          case USB_REQ_SETCONFIGURATION:
+            /* type:  host-to-device; recipient = device
+             * value: configuration value
+             * index: 0;
+             * len:   0; data = none
+             */
+          case USB_REQ_GETINTERFACE:
+            /* type:  device-to-host; recipient = interface
+             * value: 0
+             * index: interface;
+             * len:   1; data = alt interface
+             */
+          case USB_REQ_SETINTERFACE:
+            /* type:  host-to-device; recipient = interface
+             * value: alternate setting
+             * index: interface;
+             * len:   0; data = none
+             */
+            {
+              usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_GETSETIFCONFIG), 0);
+              cxd56_dispatchrequest(priv);
+            }
+            break;
+
+          case USB_REQ_SYNCHFRAME:
+            {
+              /* type:  device-to-host; recipient = endpoint
+               * value: 0
+               * index: endpoint;
+               * len:   2; data = frame number
+               */
+
+              usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_SYNCHFRAME), 0);
+            }
+            break;
+
+          default:
+            {
+              usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_STALLEDREQUEST),
+                       priv->ctrl.req);
+              priv->stalled = 1;
+            }
+            break;
+        }
+    }
+
+  /* Check if the setup processing resulted in a STALL */
+
+  if (priv->stalled)
+    {
+      reg = getreg32(CXD56_USB_IN_EP_CONTROL(0));
+      putreg32(reg | USB_STALL, CXD56_USB_IN_EP_CONTROL(0));
+      reg = getreg32(CXD56_USB_OUT_EP_CONTROL(0));
+      putreg32(reg | USB_STALL, CXD56_USB_OUT_EP_CONTROL(0));
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_epinterrupt
+ *
+ * Description:
+ *   Handle USB endpoint interrupts
+ *
+ ****************************************************************************/
+
+static int cxd56_epinterrupt(int irq, FAR void *context)
+{
+  FAR struct cxd56_usbdev_s *priv = &g_usbdev;
+  FAR struct cxd56_ep_s *privep;
+  uint32_t eps;
+  uint32_t stat;
+  uint32_t ctrl;
+  int n;
+
+  eps = getreg32(CXD56_USB_DEV_EP_INTR);
+  {
+    for (n = 0; n < CXD56_NENDPOINTS; n++)
+      {
+        /* Determine IN endpoint interrupts */
+
+        privep = &priv->eplist[n];
+
+        if (eps & (1 << n))
+          {
+            stat = getreg32(CXD56_USB_IN_EP_STATUS(n));
+
+            if (stat & USB_INT_RCS)
+              {
+                /* Handle Clear_Feature */
+
+                usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_CLEARFEATURE), n);
+                ctrl = getreg32(CXD56_USB_IN_EP_CONTROL(n));
+                putreg32(ctrl | USB_F, CXD56_USB_IN_EP_CONTROL(n));
+                putreg32(ctrl | USB_CNAK, CXD56_USB_IN_EP_CONTROL(n));
+                ctrl = getreg32(CXD56_USB_IN_EP_CONTROL(n));
+                putreg32(USB_INT_RCS, CXD56_USB_IN_EP_STATUS(n));
+
+                privep->stalled = 0;
+                privep->halted = 0;
+              }
+
+            if (stat & USB_INT_RSS)
+              {
+                /* Handle Set_Feature */
+
+                usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_SETFEATURE), n);
+                putreg32(USB_INT_RSS, CXD56_USB_IN_EP_STATUS(n));
+                privep->halted = 1;
+              }
+
+            if (stat & USB_INT_TXEMPTY)
+              {
+                /* Transmit FIFO Empty detected */
+
+                usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_TXEMPTY), n);
+                putreg32(USB_INT_TXEMPTY, CXD56_USB_IN_EP_STATUS(n));
+              }
+
+            if (stat & USB_INT_TDC)
+              {
+                /* DMA Transmit complete for TxFIFO */
+
+                usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_TDC), n);
+                putreg32(USB_INT_TDC, CXD56_USB_IN_EP_STATUS(n));
+              }
+
+            if (stat & USB_INT_XFERDONE)
+              {
+                /* Transfer Done/Transmit FIFO Empty */
+
+                usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_XFERDONE), n);
+
+                /* Set NAK during processing IN request completion */
+
+                ctrl = getreg32(CXD56_USB_IN_EP_CONTROL(n));
+                putreg32(ctrl | USB_SNAK, CXD56_USB_IN_EP_CONTROL(n));
+
+                putreg32(USB_INT_XFERDONE, CXD56_USB_IN_EP_STATUS(n));
+
+                cxd56_txdmacomplete(privep);
+
+                /* Clear NAK to raise IN interrupt for send next IN
+                 * packets.
+                 */
+
+                putreg32(ctrl | USB_CNAK, CXD56_USB_IN_EP_CONTROL(n));
+              }
+
+            if (stat & USB_INT_IN)
+              {
+                /* Reply NAK for IN token when TxFIFO empty */
+
+                usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_IN), n);
+
+                ctrl = getreg32(CXD56_USB_IN_EP_CONTROL(n));
+                putreg32(ctrl | USB_SNAK, CXD56_USB_IN_EP_CONTROL(n));
+
+                /* If IN request is ready, then send it. */
+
+                if (!cxd56_rqempty(privep))
+                  {
+                    cxd56_wrrequest(privep);
+                  }
+                else
+                  {
+                    privep->txwait = 1;
+                  }
+
+                putreg32(USB_INT_IN, CXD56_USB_IN_EP_STATUS(n));
+              }
+
+            if (stat & USB_INT_HE)
+              {
+                /* Detect AHB Bus error */
+
+                usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_TXDMAERROR), n);
+                putreg32(USB_INT_HE, CXD56_USB_IN_EP_STATUS(n));
+              }
+
+            if (stat & USB_INT_BNA)
+              {
+                usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_TXBNA), n);
+                putreg32(USB_INT_BNA, CXD56_USB_IN_EP_STATUS(n));
+              }
+            putreg32(1 << n, CXD56_USB_DEV_EP_INTR);
+          }
+
+        /* Determine OUT endpoint interrupts */
+
+        if (eps & (1 << (n + 16)))
+          {
+            stat = getreg32(CXD56_USB_OUT_EP_STATUS(n));
+
+            if (USB_INT_OUT(stat) == USB_INT_OUT_SETUP)
+              {
+                putreg32(USB_INT_OUT_SETUP, CXD56_USB_OUT_EP_STATUS(n));
+                if (n == 0)
+                  {
+                    usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_OUTSETUP), 0);
+
+                    ctrl = getreg32(CXD56_USB_OUT_EP_CONTROL(0));
+                    putreg32(ctrl | USB_SNAK, CXD56_USB_OUT_EP_CONTROL(0));
+
+                    cxd56_ep0setup(priv);
+
+                    putreg32(ctrl | USB_CNAK | USB_RRDY,
+                             CXD56_USB_OUT_EP_CONTROL(0));
+
+                    ctrl = getreg32(CXD56_USB_IN_EP_CONTROL(0));
+                    putreg32(ctrl | USB_CNAK, CXD56_USB_IN_EP_CONTROL(0));
+                  }
+              }
+
+            if (USB_INT_OUT(stat) == USB_INT_OUT_DATA)
+              {
+                usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_OUTDATA), n);
+                putreg32(USB_INT_OUT_DATA, CXD56_USB_OUT_EP_STATUS(n));
+                if (n == 0)
+                  {
+                    priv->ep0datlen = g_ep0out.status & DESC_SIZE_MASK;
+
+                    /* Reset DMA descriptor for next packet */
+
+                    g_ep0out.status = privep->ep.maxpacket | DESC_LAST;
+
+                    /* Ready to receive the next SETUP packet */
+
+                    ctrl = getreg32(CXD56_USB_OUT_EP_CONTROL(0));
+                    putreg32(ctrl | USB_SNAK | USB_RRDY,
+                             CXD56_USB_OUT_EP_CONTROL(0));
+
+                    /* Dispatch setup packet and out transaction */
+
+                    if (priv->ep0datlen > 0)
+                      {
+                        memcpy(priv->ep0data, (const void *)g_ep0out.buf,
+                               priv->ep0datlen);
+
+                        if (((priv->ctrl.type & USB_REQ_TYPE_MASK) !=
+                             USB_REQ_TYPE_STANDARD) &&
+                            USB_REQ_ISOUT(priv->ctrl.type))
+                          {
+                            cxd56_ep0setup(priv);
+                            priv->ep0datlen = 0;
+                          }
+                      }
+                  }
+                else
+                  {
+                    cxd56_rxdmacomplete(privep);
+                  }
+              }
+
+            if (stat & USB_INT_CDC_CLEAR)
+              {
+                usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_CDCCLEAR), n);
+                putreg32(USB_INT_CDC_CLEAR, CXD56_USB_OUT_EP_STATUS(n));
+              }
+
+            if (stat & USB_INT_RSS)
+              {
+                usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_SETFEATURE), n);
+                ctrl = getreg32(CXD56_USB_OUT_EP_CONTROL(0));
+                putreg32(USB_INT_RSS, CXD56_USB_OUT_EP_STATUS(n));
+                privep->halted = 1;
+              }
+
+            if (stat & USB_INT_RCS)
+              {
+                uint32_t status;
+
+                usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_CLEARFEATURE), n);
+
+                ctrl = getreg32(CXD56_USB_OUT_EP_CONTROL(n));
+
+                /* Make sure want to be DMA transfer stopped.
+                 *
+                 * XXX: S bit needs to be clear by hand, it is not found in
+                 * the specification documents.
+                 */
+
+                ctrl &= ~USB_STALL;
+
+                putreg32(ctrl | USB_CLOSEDESC, CXD56_USB_OUT_EP_CONTROL(n));
+                do
+                  {
+                    status = getreg32(CXD56_USB_OUT_EP_STATUS(n));
+                  }
+                while (!(status & USB_INT_CDC_CLEAR));
+                putreg32(USB_INT_CDC_CLEAR, CXD56_USB_OUT_EP_STATUS(n));
+
+                if (!(stat & USB_INT_MRXFIFOEMPTY))
+                  {
+                    /* Flush Recieve FIFO and clear NAK to finish status stage */
+
+                    putreg32(ctrl | USB_MRXFLUSH, CXD56_USB_OUT_EP_CONTROL(n));
+                  }
+                putreg32(ctrl | USB_CNAK, CXD56_USB_OUT_EP_CONTROL(n));
+                putreg32(USB_INT_RCS, CXD56_USB_OUT_EP_STATUS(n));
+                privep->stalled = 0;
+                privep->halted = 0;
+              }
+
+            if (stat & USB_INT_HE)
+              {
+                usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_RXDMAERROR), n);
+                putreg32(USB_INT_HE, CXD56_USB_OUT_EP_STATUS(n));
+              }
+
+            if (stat & USB_INT_BNA)
+              {
+                usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_RXBNA), n);
+                cxd56_rdrequest(privep);
+                putreg32(USB_INT_BNA, CXD56_USB_OUT_EP_STATUS(n));
+              }
+
+            putreg32(1 << (n + 16), CXD56_USB_DEV_EP_INTR);
+          }
+      }
+  }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_usbinterrupt
+ *
+ * Description:
+ *   Handle USB controller core interrupts
+ *
+ ****************************************************************************/
+
+static int cxd56_usbinterrupt(int irq, FAR void *context, FAR void *arg)
+{
+  struct usb_ctrlreq_s ctrl;
+  uint32_t intr;
+  uint32_t status;
+  int ret;
+
+  intr = getreg32(CXD56_USB_DEV_INTR);
+  putreg32(intr, CXD56_USB_DEV_INTR);
+
+  usbtrace(TRACE_INTENTRY(CXD56_TRACEINTID_USB), intr & 0xff);
+
+  /* Set/Clear Remove Wakeup is received by the core */
+
+  if (intr & USB_INT_RMTWKP_STATE)
+    {
+      usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_RMTWKP), 0);
+    }
+
+  /* Speed enumeration is complete */
+
+  if (intr & USB_INT_ENUM)
+    {
+      FAR struct cxd56_usbdev_s *priv = &g_usbdev;
+      uint32_t speed;
+      uint32_t config;
+
+      /* Read established speed type (high or full) */
+
+      speed = USB_STATUS_SPD(getreg32(CXD56_USB_DEV_STATUS));
+      usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_ENUM), speed);
+
+      /* Set established speed type to device configuration and device
+       * instance.
+       */
+
+      config = getreg32(CXD56_USB_DEV_CONFIG) & ~USB_CONFIG_SPD_MASK;
+      if (speed == USB_CONFIG_HS)
+        {
+          priv->usbdev.speed = USB_SPEED_HIGH;
+          config |= USB_CONFIG_HS;
+        }
+      else if (speed == USB_CONFIG_FS)
+        {
+          priv->usbdev.speed = USB_SPEED_FULL;
+          config |= USB_CONFIG_FS;
+        }
+      putreg32(config, CXD56_USB_DEV_CONFIG);
+    }
+
+  /* An SOF token is detected */
+
+  if (intr & USB_INT_SOF)
+    {
+      usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_SOF), 0);
+    }
+
+  /* A suspend state is detected */
+
+  if (intr & USB_INT_US)
+    {
+      usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_US), 0);
+    }
+
+  /* A USB Reset is detected */
+
+  if (intr & USB_INT_UR)
+    {
+      int i;
+
+      usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_UR), 0);
+
+      for (i = 1; i < CXD56_NENDPOINTS; i++)
+        {
+          FAR struct cxd56_ep_s *privep =
+            (FAR struct cxd56_ep_s *)&g_usbdev.eplist[i];
+
+          cxd56_cancelrequests(privep);
+        }
+
+      cxd56_pullup(&g_usbdev.usbdev, false);
+      if (g_usbdev.driver)
+        {
+          CLASS_DISCONNECT(g_usbdev.driver, &g_usbdev.usbdev);
+        }
+    }
+
+  /* An idle state is detected */
+
+  if (intr & USB_INT_ES)
+    {
+      usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_ES), 0);
+    }
+
+  /* The device has received a Set_Interface command */
+
+  if (intr & USB_INT_SI)
+    {
+      usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_SI), 0);
+      status = getreg32(CXD56_USB_DEV_STATUS);
+      memset(&ctrl, 0, USB_SIZEOF_CTRLREQ);
+      ctrl.type     = USB_REQ_RECIPIENT_INTERFACE;
+      ctrl.req      = USB_REQ_SETINTERFACE;
+      ctrl.value[0] = USB_STATUS_ALT(status);
+      ctrl.index[0] = USB_STATUS_INTF(status);
+      g_usbdev.ctrl = ctrl;
+      ret = CLASS_SETUP(g_usbdev.driver, &g_usbdev.usbdev, &ctrl, NULL, 0);
+      if (ret < 0)
+        {
+          usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_STALLEDISPATCH),
+                   USB_REQ_SETINTERFACE);
+          g_usbdev.stalled = 1;
+        }
+      putreg32(getreg32(CXD56_USB_DEV_CONTROL) | USB_CTRL_CSR_DONE,
+               CXD56_USB_DEV_CONTROL);
+    }
+
+  /* The device has received a Set_Configuration command */
+
+  if (intr & USB_INT_SC)
+    {
+      usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_SC), 0);
+      status = getreg32(CXD56_USB_DEV_STATUS);
+      memset(&ctrl, 0, USB_SIZEOF_CTRLREQ);
+      ctrl.req      = USB_REQ_SETCONFIGURATION;
+      ctrl.value[0] = USB_STATUS_CFG(status);
+      g_usbdev.ctrl = ctrl;
+      ret = CLASS_SETUP(g_usbdev.driver, &g_usbdev.usbdev, &ctrl, NULL, 0);
+      if (ret < 0)
+        {
+          usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_STALLEDISPATCH),
+                   USB_REQ_SETCONFIGURATION);
+          g_usbdev.stalled = 1;
+        }
+      putreg32(getreg32(CXD56_USB_DEV_CONTROL) | USB_CTRL_CSR_DONE,
+               CXD56_USB_DEV_CONTROL);
+    }
+
+  /* Handle each EP interrupts */
+
+  cxd56_epinterrupt(irq, context);
+
+  usbtrace(TRACE_INTEXIT(CXD56_TRACEINTID_USB), 0);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_sysinterrupt
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+static int cxd56_sysinterrupt(int irq, FAR void *context, FAR void *arg)
+{
+  FAR struct cxd56_usbdev_s *priv = (FAR struct cxd56_usbdev_s *)arg;
+  uint32_t status;
+
+  UNUSED(priv);
+
+  usbtrace(TRACE_INTENTRY(CXD56_TRACEINTID_SYS), 0);
+
+  status = getreg32(CXD56_USB_SYS_INTR);
+  putreg32(status, CXD56_USB_SYS_INTR);
+
+  if (status & USB_INT_RESUME)
+    {
+      usbtrace(TRACE_INTDECODE(CXD56_TRACEINTID_RESUME), 0);
+    }
+
+  usbtrace(TRACE_INTEXIT(CXD56_TRACEINTID_SYS), 0);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_ep0hwinitialize
+ *
+ * Description:
+ *   Initialize endpoints.  This is logically a part of cxd56_ctrlinitialize
+ *
+ ****************************************************************************/
+
+static void cxd56_ep0hwinitialize(FAR struct cxd56_usbdev_s *priv)
+{
+  uint32_t maxp  = g_epinfo[0].maxpacket;
+  uint32_t bufsz = g_epinfo[0].bufsize / 4;
+  uint32_t status;
+
+  /* Initialize DMA descriptors */
+
+  memset(&g_ep0setup, 0, sizeof(g_ep0setup));
+  memset(&g_ep0in, 0, sizeof(g_ep0in));
+  memset(&g_ep0out, 0, sizeof(g_ep0out));
+
+  g_ep0out.buf    = (uint32_t)(uintptr_t)g_ep0outbuffer;
+  g_ep0out.status = CXD56_EP0MAXPACKET | DESC_LAST;
+
+  putreg32((uint32_t)(uintptr_t)&g_ep0setup, CXD56_USB_OUT_EP_SETUP(0));
+  putreg32((uint32_t)(uintptr_t)&g_ep0in, CXD56_USB_IN_EP_DATADESC(0));
+  putreg32((uint32_t)(uintptr_t)&g_ep0out, CXD56_USB_OUT_EP_DATADESC(0));
+
+  /* Clear all interrupts */
+
+  status = getreg32(CXD56_USB_IN_EP_STATUS(0));
+  putreg32(status, CXD56_USB_IN_EP_STATUS(0));
+  status = getreg32(CXD56_USB_OUT_EP_STATUS(0));
+  putreg32(status, CXD56_USB_OUT_EP_STATUS(0));
+
+  /* EP0 setup for control */
+
+  putreg32(maxp, CXD56_USB_IN_EP_MAXPKTSIZE(0));
+  putreg32(bufsz, CXD56_USB_IN_EP_BUFSIZE(0));
+  putreg32(maxp | (bufsz << 16), CXD56_USB_OUT_EP_BUFSIZE(0));
+  putreg32(USB_ET(USB_EP_CONTROL) | USB_F, CXD56_USB_IN_EP_CONTROL(0));
+  putreg32(USB_ET(USB_EP_CONTROL) | USB_SNAK, CXD56_USB_OUT_EP_CONTROL(0));
+  putreg32(maxp << 19, CXD56_USB_DEV_UDC_EP(0));
+}
+
+/****************************************************************************
+ * Name: cxd56_ctrlinitialize
+ *
+ * Description:
+ *   Initialize the CXD56 USB controller for peripheral mode operation .
+ *
+ ****************************************************************************/
+
+static void cxd56_ctrlinitialize(FAR struct cxd56_usbdev_s *priv)
+{
+  uint32_t ctrl;
+  uint32_t config;
+
+  config = USB_CONFIG_CSR_PRG | USB_CONFIG_PI | USB_CONFIG_RWKP;
+#ifdef CONFIG_USBDEV_SELFPOWERED
+  config |= USB_CONFIG_SP;
+#endif
+  putreg32(config, CXD56_USB_DEV_CONFIG);
+  ctrl = USB_CTRL_SD | USB_CTRL_RES;
+  putreg32(ctrl, CXD56_USB_DEV_CONTROL);
+
+  /* Polling wait for resumed */
+
+  while (getreg32(CXD56_USB_DEV_STATUS) & USB_STATUS_SUSP);
+
+  ctrl |= USB_CTRL_MODE | USB_CTRL_RDE | USB_CTRL_TDE;
+  putreg32(ctrl, CXD56_USB_DEV_CONTROL);
+}
+
+/****************************************************************************
+ * Name: cxd56_usbdevreset
+ *
+ * Description:
+ *   Reset USB engine
+ *
+ ****************************************************************************/
+
+static void cxd56_usbdevreset(FAR struct cxd56_usbdev_s *priv)
+{
+  uint32_t mask;
+  int i;
+  int timeout = 0;
+
+  /* Initialize USB Device controller */
+
+  putreg32(0, CXD56_USB_RESET);
+  putreg32(1, CXD56_USB_RESET);
+  putreg32(getreg32(CXD56_USB_PHY_CONFIG1) | PHY_PLLENABLE,
+           CXD56_USB_PHY_CONFIG1);
+
+  while (!(getreg32(CXD56_USB_SYS_INTR) & USB_INT_READY))
+    {
+      timeout++;
+      if (timeout > CXD56_USBDEV_TIMEOUT)
+        {
+          uinfo("usb reset timeout.\n");
+          break;
+        }
+      up_mdelay(1);
+    }
+
+  /* Workaround for recovery from reset to slow issue.
+   * Wait to recover from usb reset condition,
+   * until any register value can read correctly.
+   */
+
+  while (getreg32(CXD56_USB_DEV_INTR_MASK) == 0)
+    {
+      timeout++;
+      if (timeout > CXD56_USBDEV_TIMEOUT)
+        {
+          uinfo("intr mask register timeout.\n");
+          break;
+        }
+      up_mdelay(1);
+    }
+
+  putreg32(USB_INT_READY, CXD56_USB_SYS_INTR);
+  putreg32(1 << 24, CXD56_USB_PJ_DEMAND); /* XXX */
+
+  cxd56_pullup(&priv->usbdev, false);
+
+  /* Initialize the CXD56 USB controller for DMA mode operation. */
+
+  cxd56_ctrlinitialize(priv);
+
+  cxd56_ep0hwinitialize(priv);
+
+  for (i = 1; i < CXD56_NENDPOINTS; i++)
+    {
+      const struct cxd56_epinfo_s *info = &g_epinfo[i];
+      uint32_t stat;
+
+      if (USB_ISEPIN(info->addr))
+        {
+          stat = getreg32(CXD56_USB_IN_EP_STATUS(i));
+          putreg32(stat, CXD56_USB_IN_EP_STATUS(i));
+          putreg32(info->maxpacket, CXD56_USB_IN_EP_MAXPKTSIZE(i));
+          putreg32(info->bufsize / 4, CXD56_USB_IN_EP_BUFSIZE(i));
+          putreg32(USB_ET(info->attr) | USB_F, CXD56_USB_IN_EP_CONTROL(i));
+        }
+      else
+        {
+          stat = getreg32(CXD56_USB_OUT_EP_STATUS(i));
+          putreg32(stat, CXD56_USB_OUT_EP_STATUS(i));
+          putreg32(info->maxpacket | ((info->bufsize / 4) << 16),
+                   CXD56_USB_OUT_EP_BUFSIZE(i));
+          putreg32(USB_ET(info->attr) | USB_SNAK, CXD56_USB_OUT_EP_CONTROL(i));
+        }
+    }
+
+  /* Enable device interrupts */
+
+  mask = getreg32(CXD56_USB_DEV_INTR_MASK);
+  mask &= ~(USB_INT_RMTWKP_STATE | USB_INT_ENUM | USB_INT_UR | USB_INT_SI |
+            USB_INT_SC);
+  putreg32(mask, CXD56_USB_DEV_INTR_MASK);
+
+  /* Enable EP0 IN/OUT */
+
+  mask = getreg32(CXD56_USB_DEV_EP_INTR_MASK);
+  mask &= ~(1 << 16 | 1);
+  putreg32(mask, CXD56_USB_DEV_EP_INTR_MASK);
+}
+
+/****************************************************************************
+ * Endpoint Methods
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_epconfigure
+ *
+ * Description:
+ *   Configure endpoint, making it usable
+ *
+ * Input Parameters:
+ *   ep   - the struct usbdev_ep_s instance obtained from allocep()
+ *   desc - A struct usb_epdesc_s instance describing the endpoint
+ *   last - true if this this last endpoint to be configured.  Some hardware
+ *          needs to take special action when all of the endpoints have been
+ *          configured.
+ *
+ ****************************************************************************/
+
+static int cxd56_epconfigure(FAR struct usbdev_ep_s *ep,
+                             FAR const struct usb_epdesc_s *desc, bool last)
+{
+  FAR struct cxd56_ep_s *privep = (FAR struct cxd56_ep_s *)ep;
+  int n;
+  int eptype;
+  uint16_t maxpacket;
+  uint32_t status;
+  uint32_t udc;
+  uint32_t addr;
+  uint32_t ctrl;
+
+  usbtrace(TRACE_EPCONFIGURE, privep->epphy);
+  DEBUGASSERT(desc->addr == ep->eplog);
+
+  n         = privep->epphy;
+  eptype    = desc->attr & USB_EP_ATTR_XFERTYPE_MASK;
+  maxpacket = GETUINT16(desc->mxpacketsize);
+  ep->maxpacket = maxpacket;
+
+  status = getreg32(CXD56_USB_DEV_STATUS);
+
+  uinfo("config: EP%d %s %d maxpacket=%d (status: %08x)\n", n,
+        privep->in ? "IN" : "OUT", eptype, maxpacket, status);
+
+  udc = n;
+  udc |= privep->in ? (1 << 4) : 0;
+  udc |= eptype << 5;
+  udc |= USB_STATUS_CFG(status) << 7;
+  udc |= USB_STATUS_INTF(status) << 11;
+  udc |= USB_STATUS_ALT(status) << 15;
+  udc |= maxpacket << 19;
+  uinfo("UDC: %08x\n", udc);
+
+  /* This register is write-only (why?) */
+
+  putreg32(udc, CXD56_USB_DEV_UDC_EP(n));
+
+  /* Write to UDC EP register takes time, so wait for the USBBusy bit */
+
+  while (getreg32(CXD56_USB_BUSY));
+
+  /* Off STALL bit and enable receive */
+
+  addr = USB_ISEPIN(ep->eplog) ? CXD56_USB_IN_EP_CONTROL(privep->epphy)
+                               : CXD56_USB_OUT_EP_CONTROL(privep->epphy);
+  ctrl = getreg32(addr);
+
+  putreg32((ctrl & ~USB_STALL), addr);
+
+  privep->stalled = 0;
+
+  /* Clear and setup DMA descriptor */
+
+  privep->desc->status = DESC_BS_HOST_BUSY;
+  privep->desc->buf    = 0;
+
+  if (privep->in)
+    {
+      putreg32((uint32_t)(uintptr_t)privep->desc,
+               CXD56_USB_IN_EP_DATADESC(privep->epphy));
+    }
+  else
+    {
+      putreg32((uint32_t)(uintptr_t)privep->desc,
+               CXD56_USB_OUT_EP_DATADESC(privep->epphy));
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_epdisable
+ *
+ * Description:
+ *   The endpoint will no longer be used
+ *
+ ****************************************************************************/
+
+static int cxd56_epdisable(FAR struct usbdev_ep_s *ep)
+{
+  FAR struct cxd56_ep_s *privep = (FAR struct cxd56_ep_s *)ep;
+  irqstate_t flags;
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!ep)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_INVALIDPARMS), 0);
+      return -EINVAL;
+    }
+#endif
+  usbtrace(TRACE_EPDISABLE, privep->epphy);
+  uinfo("EP%d\n", ((FAR struct cxd56_ep_s *)ep)->epphy);
+
+  /* Cancel any ongoing activity and reset the endpoint */
+
+  flags = enter_critical_section();
+  cxd56_epstall(&privep->ep, false);
+  cxd56_cancelrequests(privep);
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_epallocreq
+ *
+ * Description:
+ *   Allocate an I/O request
+ *
+ ****************************************************************************/
+
+static FAR struct usbdev_req_s *cxd56_epallocreq(FAR struct usbdev_ep_s *ep)
+{
+  FAR struct cxd56_req_s *privreq;
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!ep)
+    {
+      return NULL;
+    }
+#endif
+  usbtrace(TRACE_EPALLOCREQ, ((FAR struct cxd56_ep_s *)ep)->epphy);
+
+  privreq = (FAR struct cxd56_req_s *)kmm_malloc(sizeof(struct cxd56_req_s));
+  if (!privreq)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_ALLOCFAIL), 0);
+      return NULL;
+    }
+
+  memset(privreq, 0, sizeof(struct cxd56_req_s));
+  return &privreq->req;
+}
+
+/****************************************************************************
+ * Name: cxd56_epfreereq
+ *
+ * Description:
+ *   Free an I/O request
+ *
+ ****************************************************************************/
+
+static void cxd56_epfreereq(FAR struct usbdev_ep_s *ep,
+                            FAR struct usbdev_req_s *req)
+{
+  FAR struct cxd56_req_s *privreq = (FAR struct cxd56_req_s *)req;
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!ep || !req)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_INVALIDPARMS), 0);
+      return;
+    }
+#endif
+
+  usbtrace(TRACE_EPFREEREQ, ((FAR struct cxd56_ep_s *)ep)->epphy);
+  kmm_free(privreq);
+}
+
+/****************************************************************************
+ * Name: cxd56_epallocbuffer
+ *
+ * Description:
+ *   Allocate an I/O buffer
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBDEV_DMA
+static FAR void *cxd56_epallocbuffer(FAR struct usbdev_ep_s *ep, uint16_t bytes)
+{
+  FAR struct cxd56_ep_s *privep = (FAR struct cxd56_ep_s *)ep;
+
+  UNUSED(privep);
+  usbtrace(TRACE_EPALLOCBUFFER, privep->epphy);
+
+  return kmm_malloc(bytes);
+}
+#endif
+
+/****************************************************************************
+ * Name: cxd56_epfreebuffer
+ *
+ * Description:
+ *   Free an I/O buffer
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBDEV_DMA
+static void cxd56_epfreebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf)
+{
+  FAR struct cxd56_ep_s *privep = (FAR struct cxd56_ep_s *)ep;
+
+  UNUSED(privep);
+  usbtrace(TRACE_EPFREEBUFFER, privep->epphy);
+
+  kmm_free(buf);
+}
+#endif
+
+/****************************************************************************
+ * Name: cxd56_epsubmit
+ *
+ * Description:
+ *   Submit an I/O request to the endpoint
+ *
+ ****************************************************************************/
+
+static int cxd56_epsubmit(FAR struct usbdev_ep_s *ep,
+                          FAR struct usbdev_req_s *req)
+{
+  FAR struct cxd56_req_s *privreq = (FAR struct cxd56_req_s *)req;
+  FAR struct cxd56_ep_s *privep   = (FAR struct cxd56_ep_s *)ep;
+  FAR struct cxd56_usbdev_s *priv;
+  uint32_t ctrl;
+  irqstate_t flags;
+  int ret = OK;
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!req || !req->callback || !req->buf || !ep)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_INVALIDPARMS), 0);
+      return -EINVAL;
+    }
+#endif
+  usbtrace(TRACE_EPSUBMIT, privep->epphy);
+  priv = privep->dev;
+
+  if (!priv->driver || priv->usbdev.speed == USB_SPEED_UNKNOWN)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_NOTCONFIGURED), 0);
+      return -ESHUTDOWN;
+    }
+
+  req->result = -EINPROGRESS;
+  req->xfrd   = 0;
+  flags       = enter_critical_section();
+
+  /* If we are stalled, then drop all requests on the floor, except OUT */
+
+  if (privep->stalled && privep->in)
+    {
+      cxd56_abortrequest(privep, privreq, -EBUSY);
+      ret = -EBUSY;
+    }
+
+  /* Handle control requests.
+   * Submit on endpoint 0 is always IN request
+   */
+
+  else if (privep->epphy == 0)
+    {
+      cxd56_rqenqueue(privep, privreq);
+
+      /* SetConfiguration and SetInterface are handled by hardware, USB device IP
+       * a  utomatically returns NULL packet to host, so I drop this request and
+       * indicate complete to upper driver.
+       */
+
+      if (priv->ctrl.req == USB_REQ_SETCONFIGURATION ||
+          priv->ctrl.req == USB_REQ_SETINTERFACE)
+        {
+          /* Nothing to transfer -- exit success, with zero bytes transferred */
+
+          usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd);
+          cxd56_reqcomplete(privep, OK);
+        }
+
+      if (priv->ctrl.req == USB_REQ_SETCONFIGURATION)
+        {
+          /* Notify attach signal.
+           * max supply current is returned in response to GET_CONFIGURATION
+           * from the device. host receives the response and determines the
+           * supply current value.
+           */
+
+          cxd56_notify_signal(USBDEV_STATE_ATTACH, priv->power);
+        }
+
+      /* Get max supply current value from GET_CONFIGURATION response.
+       * max supply current value is stored in units of 2 mA.
+       */
+
+      if (priv->ctrl.req == USB_REQ_GETDESCRIPTOR &&
+          priv->ctrl.value[1] == USB_DESC_TYPE_CONFIG)
+        {
+          FAR struct usb_cfgdesc_s *cfgdesc;
+
+          cfgdesc     = (FAR struct usb_cfgdesc_s *)req->buf;
+          priv->power = cfgdesc->mxpower * 2;
+        }
+
+      /* If IN transaction has been requested, clear NAK bit to be able
+       * to raise IN interrupt to start IN packets.
+       */
+
+      if (privep->txwait)
+        {
+          ctrl = getreg32(CXD56_USB_IN_EP_CONTROL(privep->epphy));
+          putreg32(ctrl | USB_CNAK, CXD56_USB_IN_EP_CONTROL(privep->epphy));
+        }
+    }
+
+  /* Handle IN (device-to-host) requests */
+
+  else if (privep->in)
+    {
+      /* Add the new request to the request queue for the IN endpoint */
+
+      cxd56_rqenqueue(privep, privreq);
+      usbtrace(TRACE_INREQQUEUED(privep->epphy), privreq->req.len);
+
+      /* If IN transaction has been requested, clear NAK bit to be able
+       * to raise IN interrupt to start IN packets.
+       */
+
+      if (privep->txwait)
+        {
+          ctrl = getreg32(CXD56_USB_IN_EP_CONTROL(privep->epphy));
+          putreg32(ctrl | USB_CNAK, CXD56_USB_IN_EP_CONTROL(privep->epphy));
+        }
+    }
+
+  /* Handle OUT (host-to-device) requests */
+
+  else
+    {
+      /* Add the new request to the request queue for the OUT endpoint */
+
+      privep->txnullpkt = 0;
+      cxd56_rqenqueue(privep, privreq);
+      usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len);
+
+      /* This there a incoming data pending the availability of a request? */
+
+      ret = cxd56_rdrequest(privep);
+    }
+
+  leave_critical_section(flags);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_epcancel
+ *
+ * Description:
+ *   Cancel an I/O request previously sent to an endpoint
+ *
+ ****************************************************************************/
+
+static int cxd56_epcancel(FAR struct usbdev_ep_s *ep,
+                          FAR struct usbdev_req_s *req)
+{
+  FAR struct cxd56_ep_s *privep = (FAR struct cxd56_ep_s *)ep;
+  irqstate_t flags;
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!ep || !req)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_INVALIDPARMS), 0);
+      return -EINVAL;
+    }
+#endif
+
+  usbtrace(TRACE_EPCANCEL, privep->epphy);
+
+  flags = enter_critical_section();
+  cxd56_cancelrequests(privep);
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_epstall
+ *
+ * Description:
+ *   Stall or resume and endpoint
+ *
+ ****************************************************************************/
+
+static int cxd56_epstall(FAR struct usbdev_ep_s *ep, bool resume)
+{
+  FAR struct cxd56_ep_s *privep = (FAR struct cxd56_ep_s *)ep;
+  uint32_t ctrl;
+  uint32_t addr;
+
+  addr = USB_ISEPIN(ep->eplog) ? CXD56_USB_IN_EP_CONTROL(privep->epphy)
+                               : CXD56_USB_OUT_EP_CONTROL(privep->epphy);
+
+  if (resume)
+    {
+      usbtrace(TRACE_EPRESUME, privep->epphy);
+      ctrl = getreg32(addr);
+      putreg32(ctrl & ~USB_STALL, addr);
+      privep->stalled = 0;
+    }
+  else
+    {
+      usbtrace(TRACE_EPSTALL, privep->epphy);
+      ctrl = getreg32(addr);
+      putreg32(ctrl | USB_STALL, addr);
+      privep->stalled = 1;
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Device Methods
+ ****************************************************************************/
+
+static int cxd56_allocepbuffer(FAR struct cxd56_ep_s *privep)
+{
+  DEBUGASSERT(!privep->desc && !privep->buffer);
+  DEBUGASSERT(privep->epphy); /* Do not use for EP0 */
+
+  privep->desc =
+    (struct cxd56_data_desc_s *)kmm_malloc(sizeof(struct cxd56_data_desc_s));
+  if (!privep->desc)
+    {
+      return -1;
+    }
+
+  privep->buffer       = NULL;
+  privep->desc->status = DESC_BS_HOST_BUSY;
+  privep->desc->buf    = 0;
+  privep->desc->next   = 0;
+
+  if (privep->in)
+    {
+      putreg32((uint32_t)(uintptr_t)privep->desc,
+               CXD56_USB_IN_EP_DATADESC(privep->epphy));
+    }
+  else
+    {
+      putreg32((uint32_t)(uintptr_t)privep->desc,
+               CXD56_USB_OUT_EP_DATADESC(privep->epphy));
+    }
+  return 0;
+}
+
+static void cxd56_freeepbuffer(FAR struct cxd56_ep_s *privep)
+{
+  DEBUGASSERT(privep->epphy); /* Do not use for EP0 */
+
+  if (privep->in)
+    {
+      putreg32(0, CXD56_USB_IN_EP_DATADESC(privep->epphy));
+    }
+  else
+    {
+      putreg32(0, CXD56_USB_OUT_EP_DATADESC(privep->epphy));
+    }
+
+  if (privep->desc)
+    {
+      kmm_free(privep->desc);
+      privep->desc = NULL;
+    }
+
+  if (privep->buffer)
+    {
+      kmm_free(privep->buffer);
+      privep->buffer = NULL;
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_allocep
+ *
+ * Description:
+ *   Allocate an endpoint matching the parameters
+ *
+ * Input Parameters:
+ *   eplog  - 7-bit logical endpoint number (direction bit ignored).  Zero means
+ *            that any endpoint matching the other requirements will suffice.  The
+ *            assigned endpoint can be found in the eplog field.
+ *   in     - true: IN (device-to-host) endpoint requested
+ *   eptype - Endpoint type.  One of {USB_EP_ATTR_XFER_ISOC, USB_EP_ATTR_XFER_BULK,
+ *            USB_EP_ATTR_XFER_INT}
+ *
+ ****************************************************************************/
+
+static FAR struct usbdev_ep_s *cxd56_allocep(FAR struct usbdev_s *dev,
+                                             uint8_t eplog, bool in,
+                                             uint8_t eptype)
+{
+  FAR struct cxd56_usbdev_s *priv = (FAR struct cxd56_usbdev_s *)dev;
+  int ndx;
+
+  usbtrace(TRACE_DEVALLOCEP, eplog);
+
+  /* Ignore any direction bits in the logical address */
+
+  eplog = USB_EPNO(eplog);
+
+  /* Check all endpoints (except EP0) */
+
+  for (ndx = 1; ndx < CXD56_NENDPOINTS; ndx++)
+    {
+      /* if not used? */
+
+      if (!(priv->avail & (1 << ndx)))
+        {
+          continue;
+        }
+
+      /* Does this match the endpoint number (if one was provided?) */
+
+      if (eplog != 0 && eplog != USB_EPNO(priv->eplist[ndx].ep.eplog))
+        {
+          continue;
+        }
+
+      /* Does the direction match */
+
+      if (in)
+        {
+          if (!USB_ISEPIN(g_epinfo[ndx].addr))
+            {
+              continue;
+            }
+        }
+      else
+        {
+          if (!USB_ISEPOUT(g_epinfo[ndx].addr))
+            {
+              continue;
+            }
+        }
+
+      /* Does the type match? */
+
+      if (g_epinfo[ndx].attr == eptype)
+        {
+          /* Success! */
+
+          irqstate_t flags;
+          uint32_t mask;
+
+          if (cxd56_allocepbuffer(&priv->eplist[ndx]) < 0)
+            {
+              continue;
+            }
+
+          flags = enter_critical_section();
+          priv->avail &= ~(1 << ndx);
+          mask = getreg32(CXD56_USB_DEV_EP_INTR_MASK);
+          mask &= ~(1 << ndx << (in ? 0 : 16));
+          putreg32(mask, CXD56_USB_DEV_EP_INTR_MASK);
+          leave_critical_section(flags);
+          return &priv->eplist[ndx].ep;
+        }
+    }
+
+  usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_NOEP), 0);
+  return NULL;
+}
+
+/****************************************************************************
+ * Name: cxd56_freeep
+ *
+ * Description:
+ *   Free the previously allocated endpoint
+ *
+ ****************************************************************************/
+
+static void cxd56_freeep(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep)
+{
+  FAR struct cxd56_ep_s *privep   = (FAR struct cxd56_ep_s *)ep;
+  FAR struct cxd56_usbdev_s *pdev = privep->dev;
+  irqstate_t flags;
+
+  usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy);
+
+  cxd56_freeepbuffer(privep);
+
+  flags = enter_critical_section();
+  pdev->avail |= 1 << privep->epphy;
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: cxd56_getframe
+ *
+ * Description:
+ *   Returns the current frame number
+ *
+ ****************************************************************************/
+
+static int cxd56_getframe(FAR struct usbdev_s *dev)
+{
+  irqstate_t flags;
+  int ret = 0;
+
+  usbtrace(TRACE_DEVGETFRAME, 0);
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!dev)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_INVALIDPARMS), 0);
+      return -ENODEV;
+    }
+#endif
+
+  /* Return the contents of the frame register.  Interrupts must be disabled
+   * because the operation is not atomic.
+   */
+
+  flags = enter_critical_section();
+  ret   = getreg32(CXD56_USB_DEV_STATUS) >> 18;
+  leave_critical_section(flags);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_wakeup
+ *
+ * Description:
+ *   Tries to wake up the host connected to this device
+ *
+ ****************************************************************************/
+
+static int cxd56_wakeup(FAR struct usbdev_s *dev)
+{
+  irqstate_t flags;
+
+  usbtrace(TRACE_DEVWAKEUP, 0);
+
+  flags = enter_critical_section();
+  putreg32(getreg32(CXD56_USB_DEV_CONTROL) | 1, CXD56_USB_DEV_CONTROL);
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_selfpowered
+ *
+ * Description:
+ *   Sets/clears the device selfpowered feature
+ *
+ ****************************************************************************/
+
+static int cxd56_selfpowered(FAR struct usbdev_s *dev, bool selfpowered)
+{
+  FAR struct cxd56_usbdev_s *priv = &g_usbdev;
+
+  usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!dev)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_INVALIDPARMS), 0);
+      return -ENODEV;
+    }
+#endif
+
+  priv->selfpowered = selfpowered;
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_pullup
+ *
+ * Description:
+ *    Software-controlled connect to/disconnect from USB host
+ *
+ ****************************************************************************/
+
+static int cxd56_pullup(FAR struct usbdev_s *dev, bool enable)
+{
+  uint32_t ctrl;
+  uint32_t ep;
+
+  usbtrace(TRACE_DEVPULLUP, (uint16_t)enable);
+
+  ctrl = getreg32(CXD56_USB_DEV_CONTROL);
+  ep   = getreg32(CXD56_USB_OUT_EP_CONTROL(0));
+
+  if (enable)
+    {
+      ctrl &= ~(USB_CTRL_SD | USB_CTRL_RES);
+      ep |= USB_RRDY;
+    }
+  else
+    {
+      ctrl |= USB_CTRL_SD | USB_CTRL_RES;
+      ep &= USB_RRDY;
+    }
+
+  putreg32(ctrl, CXD56_USB_DEV_CONTROL);
+  putreg32(ep, CXD56_USB_OUT_EP_CONTROL(0));
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_epinitialize
+ *
+ * Description:
+ *   Initialize all of the endpoint data
+ *
+ ****************************************************************************/
+
+static void cxd56_epinitialize(FAR struct cxd56_usbdev_s *priv)
+{
+  int i;
+
+  /* Initialize the device state structure */
+
+  priv->usbdev.ops = &g_devops;
+
+  /* Set up the standard stuff */
+
+  memset(&priv->eplist[0], 0, sizeof(struct cxd56_ep_s));
+  priv->eplist[0].ep.ops = &g_epops;
+  priv->eplist[0].dev    = priv;
+
+  /* The index, i, is the physical endpoint address;  Map this
+   * to a logical endpoint address usable by the class driver.
+   */
+
+  priv->eplist[0].epphy    = 0;
+  priv->eplist[0].ep.eplog = g_epinfo[0].addr;
+
+  /* Setup the endpoint-specific stuff */
+
+  priv->eplist[0].ep.maxpacket = g_epinfo[0].maxpacket;
+
+  /* Expose only the standard EP0 */
+
+  priv->usbdev.ep0 = &priv->eplist[0].ep;
+
+  /* Initilialize USB hardware */
+
+  for (i = 1; i < CXD56_NENDPOINTS; i++)
+    {
+      FAR const struct cxd56_epinfo_s *info = &g_epinfo[i];
+      FAR struct cxd56_ep_s *privep;
+
+      /* Set up the standard stuff */
+
+      privep = &priv->eplist[i];
+      memset(privep, 0, sizeof(struct cxd56_ep_s));
+      privep->ep.ops = &g_epops;
+      privep->dev    = priv;
+      privep->desc   = NULL;
+      privep->buffer = NULL;
+
+      /* The index, i, is the physical endpoint address;  Map this
+       * to a logical endpoint address usable by the class driver.
+       */
+
+      privep->epphy    = i;
+      privep->ep.eplog = info->addr;
+
+      /* Setup the endpoint-specific stuff */
+
+      privep->ep.maxpacket = g_epinfo[i].maxpacket;
+
+      if (USB_ISEPIN(info->addr))
+        {
+          privep->in = 1;
+        }
+    }
+}
+
+/****************************************************************************
+ * Name: cxd56_usbhwuninit
+ ****************************************************************************/
+
+static void cxd56_usbhwuninit(void)
+{
+  /* Un-initilialize USB hardware */
+
+  putreg32(getreg32(CXD56_USB_PHY_CONFIG1) & ~PHY_PLLENABLE,
+           CXD56_USB_PHY_CONFIG1);
+  putreg32(getreg32(CXD56_USB_PJ_DEMAND) & ~(1 << 24), CXD56_USB_PJ_DEMAND);
+
+  /* USB Device Reset */
+
+  putreg32(0, CXD56_USB_RESET);
+}
+
+/****************************************************************************
+ * Name: cxd56_vbusinterrupt
+ ****************************************************************************/
+
+static int cxd56_vbusinterrupt(int irq, FAR void *context, FAR void *arg)
+{
+  FAR struct cxd56_usbdev_s *priv = (FAR struct cxd56_usbdev_s *)arg;
+
+  cxd56_cableconnected(true);
+
+  usbtrace(TRACE_INTENTRY(CXD56_TRACEINTID_VBUS), 0);
+  uinfo("irq=%d context=%08x\n", irq, context);
+
+  /* Toggle vbus interrupts */
+
+  up_disable_irq(CXD56_IRQ_USB_VBUS);
+  up_enable_irq(CXD56_IRQ_USB_VBUSN);
+
+  /* Enable interrupts */
+
+  up_enable_irq(CXD56_IRQ_USB_SYS);
+  up_enable_irq(CXD56_IRQ_USB_INT);
+
+  /* reconstruct Endpoints and restart Configuration */
+
+  if (priv->driver)
+    {
+      cxd56_usbreset(priv);
+    }
+
+  /* Notify attach signal.
+   * if class driver not binded, can't get supply curret value.
+   */
+
+  if (!priv->driver)
+    {
+      cxd56_notify_signal(USBDEV_STATE_ATTACH, 0);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_vbusninterrupt
+ ****************************************************************************/
+
+static int cxd56_vbusninterrupt(int irq, FAR void *context, FAR void *arg)
+{
+  FAR struct cxd56_usbdev_s *priv = (FAR struct cxd56_usbdev_s *)arg;
+  FAR struct cxd56_ep_s *privep;
+  int i;
+
+  cxd56_cableconnected(false);
+
+  usbtrace(TRACE_INTENTRY(CXD56_TRACEINTID_VBUSN), 0);
+
+  uinfo("irq=%d context=%08x\n", irq, context);
+
+  /* Toggle vbus interrupts */
+
+  up_disable_irq(CXD56_IRQ_USB_VBUSN);
+  up_enable_irq(CXD56_IRQ_USB_VBUS);
+
+  /* Disconnect device */
+
+  for (i = 1; i < CXD56_NENDPOINTS; i++)
+    {
+      privep = (FAR struct cxd56_ep_s *)&priv->eplist[i];
+
+      cxd56_epstall(&privep->ep, false);
+      cxd56_cancelrequests(privep);
+    }
+
+  if (g_usbdev.driver)
+    {
+      CLASS_DISCONNECT(priv->driver, &priv->usbdev);
+    }
+
+  /* Disable USB_INT interrupt */
+
+  up_disable_irq(CXD56_IRQ_USB_INT);
+  up_disable_irq(CXD56_IRQ_USB_SYS);
+
+  /* Notify dettach signal */
+
+  priv->power = 0;
+  cxd56_notify_signal(USBDEV_STATE_DETACH, priv->power);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_usbinitialize
+ *
+ * Description:
+ *   Initialize USB hardware
+ *
+ ****************************************************************************/
+
+void up_usbinitialize(void)
+{
+  usbtrace(TRACE_DEVINIT, 0);
+
+  /* Enable USB clock */
+
+  cxd56_usb_clock_enable();
+
+  if (irq_attach(CXD56_IRQ_USB_SYS, cxd56_sysinterrupt, &g_usbdev) != 0)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_ATTACHIRQREG), 0);
+      goto errout;
+    }
+
+  if (irq_attach(CXD56_IRQ_USB_INT, cxd56_usbinterrupt, &g_usbdev) != 0)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_COREIRQREG), 0);
+      goto errout;
+    }
+
+  if (irq_attach(CXD56_IRQ_USB_VBUS, cxd56_vbusinterrupt, &g_usbdev) != 0)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_VBUSIRQREG), 0);
+      goto errout;
+    }
+
+  if (irq_attach(CXD56_IRQ_USB_VBUSN, cxd56_vbusninterrupt, &g_usbdev) != 0)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_VBUSNIRQREG), 0);
+      goto errout;
+    }
+
+  /* Initialize driver instance */
+
+  memset(&g_usbdev, 0, sizeof(struct cxd56_usbdev_s));
+  g_usbdev.avail = 0xff;
+
+  /* Initialize endpoint data */
+
+  cxd56_epinitialize(&g_usbdev);
+
+  /* Enable interrupts */
+
+  up_enable_irq(CXD56_IRQ_USB_VBUS);
+
+  return;
+
+errout:
+  up_usbuninitialize();
+}
+
+/****************************************************************************
+ * Name: up_usbuninitialize
+ ****************************************************************************/
+
+void up_usbuninitialize(void)
+{
+  FAR struct cxd56_usbdev_s *priv = &g_usbdev;
+  irqstate_t flags;
+
+  usbtrace(TRACE_DEVUNINIT, 0);
+  if (priv->driver)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_DRIVERREGISTERED), 0);
+      usbdev_unregister(priv->driver);
+    }
+
+  flags = enter_critical_section();
+  cxd56_pullup(&priv->usbdev, false);
+  priv->usbdev.speed = USB_SPEED_UNKNOWN;
+
+  /* Disable and detach IRQs */
+
+  up_disable_irq(CXD56_IRQ_USB_INT);
+  up_disable_irq(CXD56_IRQ_USB_SYS);
+  up_disable_irq(CXD56_IRQ_USB_VBUS);
+  up_disable_irq(CXD56_IRQ_USB_VBUSN);
+
+  irq_detach(CXD56_IRQ_USB_INT);
+  irq_detach(CXD56_IRQ_USB_SYS);
+  irq_detach(CXD56_IRQ_USB_VBUS);
+  irq_detach(CXD56_IRQ_USB_VBUSN);
+
+  cxd56_usb_clock_disable();
+  leave_critical_section(flags);
+
+  /* Clear signal */
+
+  priv->signo = 0;
+  priv->pid   = 0;
+}
+
+/************************************************************************************
+ * Name: usbdevclass_register
+ *
+ * Description:
+ *   Register a USB device class driver. The class driver's bind() method will be
+ *   called to bind it to a USB device driver.
+ *
+ ************************************************************************************/
+
+int usbdev_register(FAR struct usbdevclass_driver_s *driver)
+{
+  int ret;
+
+  usbtrace(TRACE_DEVREGISTER, 0);
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!driver || !driver->ops->bind || !driver->ops->unbind ||
+      !driver->ops->setup)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_INVALIDPARMS), 0);
+      return -EINVAL;
+    }
+
+  if (g_usbdev.driver)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_DRIVER), 0);
+      return -EBUSY;
+    }
+#endif
+
+  /* Take freqlock to keep clock faster */
+
+  up_pm_acquire_freqlock(&g_hv_lock);
+  up_pm_acquire_wakelock(&g_wake_lock);
+
+  /* Hook up the driver */
+
+  g_usbdev.driver = driver;
+
+  /* Then bind the class driver */
+
+  ret = CLASS_BIND(driver, &g_usbdev.usbdev);
+  if (ret)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_BINDFAILED), (uint16_t)-ret);
+      g_usbdev.driver = NULL;
+      return ret;
+    }
+
+  /* Enable interrupts */
+
+  up_enable_irq(CXD56_IRQ_USB_VBUS);
+
+  return OK;
+}
+
+/************************************************************************************
+ * Name: usbdev_unregister
+ *
+ * Description:
+ *   Un-register usbdev class driver.If the USB device is connected to a USB
+ *   host, it will first disconnect().  The driver is also requested to unbind()
+ *   and clean up any device state, before this procedure finally returns.
+ *
+ ************************************************************************************/
+
+int usbdev_unregister(FAR struct usbdevclass_driver_s *driver)
+{
+  FAR struct cxd56_usbdev_s *priv = &g_usbdev;
+  irqstate_t flags;
+
+  usbtrace(TRACE_DEVUNREGISTER, 0);
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (driver != g_usbdev.driver)
+    {
+      usbtrace(TRACE_DEVERROR(CXD56_TRACEERR_INVALIDPARMS), 0);
+      return -EINVAL;
+    }
+#endif
+
+  /* Unbind the class driver */
+
+  CLASS_UNBIND(driver, &g_usbdev.usbdev);
+
+  flags = enter_critical_section();
+
+  /* Disable IRQs */
+
+  up_disable_irq(CXD56_IRQ_USB_INT);
+  up_disable_irq(CXD56_IRQ_USB_SYS);
+
+  /* Disconnect device */
+
+  cxd56_pullup(&priv->usbdev, false);
+  priv->usbdev.speed = USB_SPEED_UNKNOWN;
+
+  /* Unhook the driver */
+
+  g_usbdev.driver = NULL;
+
+  /* Un-initialize USB hardware */
+
+  cxd56_usbhwuninit();
+
+  leave_critical_section(flags);
+
+  up_pm_release_freqlock(&g_hv_lock);
+  up_pm_release_wakelock(&g_wake_lock);
+
+  return OK;
+}
+
+/************************************************************************************
+ * Name: cxd56_usbreset
+ *
+ * Description:
+ *   Reinitialize the endpoint and restore the EP configuration
+ *   before disconnecting the host. Then start the Configuration again.
+ *
+ ************************************************************************************/
+
+static void cxd56_usbreset(FAR struct cxd56_usbdev_s *priv)
+{
+  uint32_t mask;
+  int i;
+
+  /* USB reset assert */
+
+  cxd56_usbdevreset(priv);
+
+  /* Check all endpoints (except EP0) */
+
+  for (i = 1; i < CXD56_NENDPOINTS; i++)
+    {
+      /* skip unused EP */
+
+      if (priv->avail & (1 << i))
+        {
+          continue;
+        }
+
+      mask = getreg32(CXD56_USB_DEV_EP_INTR_MASK);
+      mask &= ~(1 << i << (priv->eplist[i].in ? 0 : 16));
+      putreg32(mask, CXD56_USB_DEV_EP_INTR_MASK);
+
+      /* DMA descripter setting */
+
+      priv->eplist[i].buffer       = NULL;
+      priv->eplist[i].desc->status = DESC_BS_HOST_BUSY;
+      priv->eplist[i].desc->buf    = 0;
+      priv->eplist[i].desc->next   = 0;
+
+      if (priv->eplist[i].in)
+        {
+          putreg32((uint32_t)(uintptr_t)priv->eplist[i].desc,
+                   CXD56_USB_IN_EP_DATADESC(priv->eplist[i].epphy));
+        }
+      else
+        {
+          putreg32((uint32_t)(uintptr_t)priv->eplist[i].desc,
+                   CXD56_USB_OUT_EP_DATADESC(priv->eplist[i].epphy));
+        }
+
+      /* resume EP stall */
+
+      cxd56_epstall(&priv->eplist[i].ep, true);
+    }
+
+  cxd56_pullup(&priv->usbdev, true);
+}
+
+/****************************************************************************
+ * Name: cxd56_usbdev_setsigno
+ ****************************************************************************/
+
+int cxd56_usbdev_setsigno(int signo)
+{
+  FAR struct cxd56_usbdev_s *priv = &g_usbdev;
+
+  uinfo("signo = %d\n", signo);
+
+  priv->signo = signo;
+  priv->pid   = getpid();
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_notify_signal
+ *
+ * Description:
+ *   Notify the application of USB attach/detach event
+ *
+ ****************************************************************************/
+
+static void cxd56_notify_signal(uint16_t state, uint16_t power)
+{
+  FAR struct cxd56_usbdev_s *priv = &g_usbdev;
+
+  if (priv->signo > 0)
+    {
+#ifdef CONFIG_CAN_PASS_STRUCTS
+      union sigval value;
+      value.sival_int = state << 16 | power;
+      (void)sigqueue(priv->pid, priv->signo, value);
+#else
+      (void)sigqueue(priv->pid, priv->signo, state << 16 | power);
+#endif
+    }
+}
+
+#ifdef CONFIG_FS_PROCFS
+
+/****************************************************************************
+ * Name: cxd56_usbdev_open
+ ****************************************************************************/
+
+static int cxd56_usbdev_open(FAR struct file *filep, FAR const char *relpath,
+                             int oflags, mode_t mode)
+{
+  FAR struct cxd56_usbdev_file_s *priv;
+
+  uinfo("Open '%s'\n", relpath);
+
+  /* PROCFS is read-only.  Any attempt to open with any kind of write
+   * access is not permitted.
+   *
+   * REVISIT:  Write-able proc files could be quite useful.
+   */
+
+  if (((oflags & O_WRONLY) != 0 || (oflags & O_RDONLY) == 0))
+    {
+      uerr("ERROR: Only O_RDONLY supported\n");
+      return -EACCES;
+    }
+
+  /* Allocate the open file structure */
+
+  priv = (FAR struct cxd56_usbdev_file_s *)kmm_zalloc(
+    sizeof(struct cxd56_usbdev_file_s));
+  if (!priv)
+    {
+      uerr("ERROR: Failed to allocate file attributes\n");
+      return -ENOMEM;
+    }
+
+  /* Save the open file structure as the open-specific state in
+   * filep->f_priv.
+   */
+
+  filep->f_priv = (FAR void *)priv;
+  return OK;
+}
+
+/****************************************************************************
+ * Name: modprocfs_close
+ ****************************************************************************/
+
+static int cxd56_usbdev_close(FAR struct file *filep)
+{
+  FAR struct cxd56_usbdev_file_s *priv;
+
+  /* Recover our private data from the struct file instance */
+
+  priv = (FAR struct cxd56_usbdev_file_s *)filep->f_priv;
+  DEBUGASSERT(priv);
+
+  /* Release the file attributes structure */
+
+  kmm_free(priv);
+  filep->f_priv = NULL;
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_usbdev_read
+ ****************************************************************************/
+
+static ssize_t cxd56_usbdev_read(FAR struct file *filep, FAR char *buffer,
+                                 size_t buflen)
+{
+  FAR struct cxd56_usbdev_file_s *attr;
+  FAR struct cxd56_usbdev_s *priv = &g_usbdev;
+  off_t offset;
+  int ret;
+
+  uinfo("buffer=%p buflen=%lu\n", buffer, (unsigned long)buflen);
+
+  /* Recover our private data from the struct file instance */
+
+  attr = (FAR struct cxd56_usbdev_file_s *)filep->f_priv;
+  DEBUGASSERT(attr);
+
+  /* Traverse all installed modules */
+
+  attr->linesize = snprintf(attr->line, CXD56_USBDEV_LINELEN, "%-12s%d mA\n",
+                            "Power:", priv->power);
+
+  /* Transfer the system up time to user receive buffer */
+
+  offset = filep->f_pos;
+  ret    = procfs_memcpy(attr->line, attr->linesize, buffer, buflen, &offset);
+
+  /* Update the file offset */
+
+  if (ret > 0)
+    {
+      filep->f_pos += ret;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: cxd56_usbdev_dup
+ ****************************************************************************/
+
+static int cxd56_usbdev_dup(FAR const struct file *oldp, FAR struct file *newp)
+{
+  FAR struct cxd56_usbdev_file_s *oldattr;
+  FAR struct cxd56_usbdev_file_s *newattr;
+
+  uinfo("Dup %p->%p\n", oldp, newp);
+
+  /* Recover our private data from the old struct file instance */
+
+  oldattr = (FAR struct cxd56_usbdev_file_s *)oldp->f_priv;
+  DEBUGASSERT(oldattr);
+
+  /* Allocate a new container to hold the task and attribute selection */
+
+  newattr = (FAR struct cxd56_usbdev_file_s *)kmm_malloc(
+    sizeof(struct cxd56_usbdev_file_s));
+  if (!newattr)
+    {
+      uerr("ERROR: Failed to allocate file attributes\n");
+      return -ENOMEM;
+    }
+
+  /* The copy the file attributes from the old attributes to the new */
+
+  memcpy(newattr, oldattr, sizeof(struct cxd56_usbdev_file_s));
+
+  /* Save the new attributes in the new file structure */
+
+  newp->f_priv = (FAR void *)newattr;
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_usbdev_stat
+ ****************************************************************************/
+
+static int cxd56_usbdev_stat(FAR const char *relpath, FAR struct stat *buf)
+{
+  buf->st_mode    = S_IFREG | S_IROTH | S_IRGRP | S_IRUSR;
+  buf->st_size    = 0;
+  buf->st_blksize = 0;
+  buf->st_blocks  = 0;
+  return OK;
+}
+
+/****************************************************************************
+ * Name: cxd56_usbdev_procfs_register
+ *
+ * Description:
+ *   Register the usbdev procfs file system entry
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_FS_PROCFS_REGISTER
+int cxd56_usbdev_procfs_register(void)
+{
+  return procfs_register(&g_procfs_usbdev);
+}
+#endif
+
+#endif
diff --git a/arch/arm/src/cxd56xx/cxd56_usbdev.h b/arch/arm/src/cxd56xx/cxd56_usbdev.h
new file mode 100644
index 00000000000..14330071a95
--- /dev/null
+++ b/arch/arm/src/cxd56xx/cxd56_usbdev.h
@@ -0,0 +1,292 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/cxd56_usbdev.h
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_USB_H
+#define __ARCH_ARM_SRC_CXD56XX_CXD56_USB_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include 
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+/* Register offsets *************************************************************************/
+/* Common Register Offsets */
+
+#define CXD56_USB_IN_EP_CONTROL(x)    (CXD56_USBDEV_BASE + 0x0000 + ((x) * 0x20))
+#define CXD56_USB_IN_EP_STATUS(x)     (CXD56_USBDEV_BASE + 0x0004 + ((x) * 0x20))
+#define CXD56_USB_IN_EP_BUFSIZE(x)    (CXD56_USBDEV_BASE + 0x0008 + ((x) * 0x20))
+#define CXD56_USB_IN_EP_MAXPKTSIZE(x) (CXD56_USBDEV_BASE + 0x000c + ((x) * 0x20))
+#define CXD56_USB_IN_EP_DATADESC(x)   (CXD56_USBDEV_BASE + 0x0014 + ((x) * 0x20))
+
+#define CXD56_USB_OUT_EP_CONTROL(x)   (CXD56_USBDEV_BASE + 0x0200 + ((x) * 0x20))
+#define CXD56_USB_OUT_EP_STATUS(x)    (CXD56_USBDEV_BASE + 0x0204 + ((x) * 0x20))
+#define CXD56_USB_OUT_EP_BUFSIZE(x)   (CXD56_USBDEV_BASE + 0x020c + ((x) * 0x20))
+#define CXD56_USB_OUT_EP_SETUP(x)     (CXD56_USBDEV_BASE + 0x0210 + ((x) * 0x20))
+#define CXD56_USB_OUT_EP_DATADESC(x)  (CXD56_USBDEV_BASE + 0x0214 + ((x) * 0x20))
+
+#define CXD56_USB_DEV_CONFIG          (CXD56_USBDEV_BASE + 0x0400)
+#define CXD56_USB_DEV_CONTROL         (CXD56_USBDEV_BASE + 0x0404)
+#define CXD56_USB_DEV_STATUS          (CXD56_USBDEV_BASE + 0x0408)
+#define CXD56_USB_DEV_INTR            (CXD56_USBDEV_BASE + 0x040c)
+#define CXD56_USB_DEV_INTR_MASK       (CXD56_USBDEV_BASE + 0x0410)
+#define CXD56_USB_DEV_EP_INTR         (CXD56_USBDEV_BASE + 0x0414)
+#define CXD56_USB_DEV_EP_INTR_MASK    (CXD56_USBDEV_BASE + 0x0418)
+
+#define CXD56_USB_DEV_UDC_EP0         (CXD56_USBDEV_BASE + 0x0504)
+#define CXD56_USB_DEV_UDC_EP1         (CXD56_USBDEV_BASE + 0x0508)
+#define CXD56_USB_DEV_UDC_EP2         (CXD56_USBDEV_BASE + 0x050c)
+#define CXD56_USB_DEV_UDC_EP3         (CXD56_USBDEV_BASE + 0x0510)
+#define CXD56_USB_DEV_UDC_EP4         (CXD56_USBDEV_BASE + 0x0514)
+#define CXD56_USB_DEV_UDC_EP5         (CXD56_USBDEV_BASE + 0x0518)
+#define CXD56_USB_DEV_UDC_EP6         (CXD56_USBDEV_BASE + 0x051c)
+#define CXD56_USB_DEV_UDC_EP(x)       (CXD56_USB_DEV_UDC_EP0 + ((x) * 4))
+
+#define CXD56_USB_SYS_INTR            (CXD56_USBDEV_BASE + 0x0800)
+#define CXD56_USB_SYS_INTR_MASK       (CXD56_USBDEV_BASE + 0x0804)
+#define CXD56_USB_BUSY                (CXD56_USBDEV_BASE + 0x0808)
+#define CXD56_USB_VBUS_CTRL           (CXD56_USBDEV_BASE + 0x080c)
+#define CXD56_USB_RESET               (CXD56_USBDEV_BASE + 0x0810)
+
+#define CXD56_USB_SUSPEND_MASK        (CXD56_USBDEV_BASE + 0x081c)
+
+#define CXD56_USB_PJ_DEMAND           (CXD56_USBDEV_BASE + 0x0830)
+
+#define CXD56_USB_PHY_CONFIG0         (CXD56_USBDEV_BASE + 0x083c)
+#define CXD56_USB_PHY_CONFIG1         (CXD56_USBDEV_BASE + 0x0840)
+#define CXD56_USB_PHY_CONFIG2         (CXD56_USBDEV_BASE + 0x0844)
+
+/* EP types */
+
+#define USB_EP_CONTROL     0
+#define USB_EP_ISOCHRONOUS 1
+#define USB_EP_BULK        2
+#define USB_EP_INTERRUPT   3
+
+/* EP control bits */
+
+#define USB_MRXFLUSH    (1<<12)
+#define USB_CLOSEDESC   (1<<11)
+#define USB_SENDNULL    (1<<10)
+#define USB_RRDY        (1<<9)
+#define USB_CNAK        (1<<8)
+#define USB_SNAK        (1<<7)
+#define USB_NAK         (1<<6)
+#define USB_ET(x)       ((x)<<4)
+#define USB_P           (1<<3)
+#define USB_SN          (1<<2)
+#define USB_F           (1<<1)
+#define USB_STALL       (1<<0)
+
+/* USB device configuration */
+
+#define USB_CONFIG_DDR                 (1<<19)
+#define USB_CONFIG_SET_DESC            (1<<18)
+#define USB_CONFIG_CSR_PRG             (1<<17)
+#define USB_CONFIG_HALT_STATUS         (1<<16)
+#define USB_CONFIG_HS_TIMEOUT_CALIB(x) (((x)&7)<<13)
+#define USB_CONFIG_FS_TIMEOUT_CALIB(x) (((x)&7)<<10)
+#define USB_CONFIG_PHY_ERROR_DETECT    (1<<9)
+#define USB_CONFIG_STATUS_1            (1<<8)
+#define USB_CONFIG_STATUS              (1<<7)
+#define USB_CONFIG_DIR                 (1<<6)
+#define USB_CONFIG_PI                  (1<<5)
+#define USB_CONFIG_SS                  (1<<4)
+#define USB_CONFIG_SP                  (1<<3)
+#define USB_CONFIG_RWKP                (1<<2)
+#define USB_CONFIG_SPD(x)              (((x)&3))
+#define USB_CONFIG_HS                  0
+#define USB_CONFIG_FS                  1
+#define USB_CONFIG_SPD_MASK            3
+
+/* USB device control */
+
+#define USB_CTRL_THLEN(x)              (((x)&0xff)<<24)
+#define USB_CTRL_BRLEN(x)              (((x)&0xff)<<16)
+#define USB_CTRL_SRXFLUSH              (1<<14)
+#define USB_CTRL_CSR_DONE              (1<<13)
+#define USB_CTRL_DEVNAK                (1<<12)
+#define USB_CTRL_SCALE                 (1<<11)
+#define USB_CTRL_SD                    (1<<10)
+#define USB_CTRL_MODE                  (1<<9)
+#define USB_CTRL_BREN                  (1<<8)
+#define USB_CTRL_THE                   (1<<7)
+#define USB_CTRL_BF                    (1<<6)
+#define USB_CTRL_BE                    (1<<5)
+#define USB_CTRL_DU                    (1<<4)
+#define USB_CTRL_TDE                   (1<<3)
+#define USB_CTRL_RDE                   (1<<2)
+#define USB_CTRL_RES                   (1<<0)
+
+/* USB device status bits */
+
+#define USB_STATUS_RMTWKP_STATE        (1<<17)
+#define USB_STATUS_PHYERROR            (1<<16)
+#define USB_STATUS_RXFIFOEMPTY         (1<<15)
+#define USB_STATUS_SPD_SHIFT           13
+#define USB_STATUS_SPD_MASK            (3<> USB_STATUS_SPD_SHIFT)
+#define USB_STATUS_SUSP                (1<<12)
+#define USB_STATUS_ALT(x)              (((x)>>8)&0xf)
+#define USB_STATUS_INTF(x)             (((x)>>4)&0xf)
+#define USB_STATUS_CFG(x)              (((x)>>0)&0xf)
+
+/* USB device interrupt bits */
+
+#define USB_INT_RMTWKP_STATE  (1<<7)
+#define USB_INT_ENUM          (1<<6)
+#define USB_INT_SOF           (1<<5)
+#define USB_INT_US            (1<<4)
+#define USB_INT_UR            (1<<3)
+#define USB_INT_ES            (1<<2)
+#define USB_INT_SI            (1<<1)
+#define USB_INT_SC            (1<<0)
+
+/* USB system interrupt bits */
+
+#define USB_INT_VBUS_DISC   (1<<3)
+#define USB_INT_VBUS_CONN   (1<<2)
+#define USB_INT_RESUME      (1<<1)
+#define USB_INT_READY       (1<<0)
+
+/* USB endpoint interrupt bits */
+
+#define USB_INT_CDC_CLEAR   (1<<28)              /*  */
+#define USB_INT_XFERDONE    (1<<27)              /* Tfansfer Done/Transmit FIFO Empty */
+#define USB_INT_RSS         (1<<26)              /* Recieved Set Stall Indication */
+#define USB_INT_RCS         (1<<25)              /* Received Clear Stall Indication */
+#define USB_INT_TXEMPTY     (1<<24)              /* Transmit FIFO Empty */
+#define USB_INT_ISO_IN_DONE (1<<23)              /* Isochronous IN transaction for the current microframe is complete */
+#define USB_INT_RX_PKT_SIZE(x) (((x)>>11)&0xfff) /* Receive Packet Size */
+#define USB_INT_TDC         (1<<10)              /* Transmit DMA Completion */
+#define USB_INT_HE          (1<<9)               /* Error response on the host bus */
+#define USB_INT_MRXFIFOEMPTY (1<<8)              /* Receive Address FIFO Empty Status */
+#define USB_INT_BNA         (1<<7)               /* Buffer Not Available */
+#define USB_INT_IN          (1<<6)               /* IN token has been received */
+#define USB_INT_OUT(x)      ((x) & (3 << 4))     /* OUT packet has been received. */
+#define   USB_INT_OUT_DATA  (1 << 4)
+#define   USB_INT_OUT_SETUP (2 << 4)
+
+/* PHY Configuration 0 bits */
+
+#define PHY_STAGSELECT      (1u<<31)
+#define PHY_SHORTCKT_PROT   (1u<<30)
+#define PHY_HSFALLCNTRL     (1u<<29)
+#define PHY_HSRXOFFSET(x)   (((x)&3)<<27)
+#define PHY_HSRXEQUALIZE    (1u<<26)
+#define PHY_INSQUETUNE(x)   (((x)&3)<<24)
+#define PHY_ZHSDRV(x)       (((x)&3)<<22)
+#define PHY_IHSTX(x)        (((x)&0xf)<<18)
+#define PHY_INHSRFRED       (1u<<17)
+#define PHY_INFSRFCNTL      (1u<<16)
+#define PHY_INHSIPLUSENABLE (1u<<15)
+#define PHY_INHSIPLUS       (1u<<14)
+#define PHY_INHSIMINUS      (1u<<13)
+#define PHY_INHSDRVSLEW     (1u<<12)
+#define PHY_INLFSFBCAP      (1u<<11)
+#define PHY_INTRCC1MA       (1u<<10)
+#define PHY_INCURRENTENABLE (1u<<9)
+#define PHY_INAFETRIM(x)    ((x)&0x1ff)
+
+/* PHY Configuration 1 bits */
+
+#define PHY_STRB_BYPASS     (1u<<31)
+#define PHY_STRB            (1u<<30)
+#define PHY_DITHER_DISABLE_RECT (1u<<29)
+#define PHY_DITHER_DISABLE_TRI  (1u<<28)
+#define PHY_FRAC_CONTROL    (1u<<27)
+#define PHY_PLLENABLE       (1u<<26)
+#define PHY_FRAC_INPUT(x)   (((x)&0xffff)<<10)
+#define PHY_ODF(x)          (((x)&0x7)<<7)
+#define PHY_NDIV(x)         ((x)&0x3f)
+
+/* DMA descriptor status bits */
+
+#define DESC_BS_SHIFT       30
+#define DESC_BS_MASK        (3 << DESC_BS_SHIFT)
+#define DESC_BS_HOST_READY  (0 << DESC_BS_SHIFT)
+#define DESC_BS_DMA_BUSY    (1 << DESC_BS_SHIFT)
+#define DESC_BS_DMA_DONE    (2 << DESC_BS_SHIFT)
+#define DESC_BS_HOST_BUSY   (3 << DESC_BS_SHIFT)
+#define IS_BS_HOST_READY(desc) (((desc)->status & DESC_BS_MASK) == DESC_BS_HOST_READY)
+#define IS_BS_DMA_BUSY(desc)   (((desc)->status & DESC_BS_MASK) == DESC_BS_DMA_BUSY)
+#define IS_BS_DMA_DONE(desc)   (((desc)->status & DESC_BS_MASK) == DESC_BS_DMA_DONE)
+#define IS_BS_HOST_BUSY(desc)  (((desc)->status & DESC_BS_MASK) == DESC_BS_HOST_BUSY)
+
+/* There is same definitions for TX/RX */
+
+#define DESC_STS_SHIFT      28
+#define DESC_STS_MASK       (3 << DESC_STS_SHIFT)
+#define DESC_STS_SUCCESS    (0 << DESC_STS_SHIFT)
+#define DESC_STS_DESERR     (1 << DESC_STS_SHIFT)
+#define DESC_STS_BUFERR     (3 << DESC_STS_SHIFT)
+#define IS_STS_SUCCESS(desc)  (((desc)->status & DESC_STS_MASK) == DESC_STS_SUCCESS)
+#define IS_STS_DESERR(desc)   (((desc)->status & DESC_STS_MASK) == DESC_STS_DESERR)
+#define IS_STS_BUFERR(desc)   (((desc)->status & DESC_STS_MASK) == DESC_STS_BUFERR)
+
+#define DESC_LAST           (1 << 27)
+
+#define DESC_SIZE_MASK      (0xffff)
+
+/****************************************************************************
+ * Name: cxd56_usbdev_setsigno
+ *
+ * Description:
+ *   cxd56xx usb device driver attach / detach event signal
+ *
+ ****************************************************************************/
+
+int cxd56_usbdev_setsigno(int signo);
+
+/****************************************************************************
+ * Name: cxd56_usbdev_procfs_register
+ *
+ * Description:
+ *   Register the usbdev procfs file system entry
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_FS_PROCFS_REGISTER
+int cxd56_usbdev_procfs_register(void);
+#endif
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_USBDEV_H */
diff --git a/arch/arm/src/cxd56xx/hardware/cxd5602_backupmem.h b/arch/arm/src/cxd56xx/hardware/cxd5602_backupmem.h
new file mode 100644
index 00000000000..d4951ca1904
--- /dev/null
+++ b/arch/arm/src/cxd56xx/hardware/cxd5602_backupmem.h
@@ -0,0 +1,87 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/hardware/cxd5602_backupmem.h
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_BACKUPMEM_H
+#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_BACKUPMEM_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+#define CXD56_BKUP_SRAM_BASE (0x04400000)
+#define BKUP ((backup_info_t*)CXD56_BKUP_SRAM_BASE)
+
+/********************************************************************************************
+ * Public Types
+ ********************************************************************************************/
+
+typedef struct {
+  uint32_t rcosc_clock;                 /* 0x04400000 ~ 0x04400003 */
+  uint32_t chip_revision;               /* 0x04400004 ~ 0x04400007 */
+  uint32_t sbl_version;                 /* 0x04400008 ~ 0x0440000b */
+  uint32_t sysfw_version;               /* 0x0440000c ~ 0x0440000f */
+  uint32_t reserved_version[4];         /* 0x04400010 ~ 0x0440001f */
+  uint32_t bootcause;                   /* 0x04400020 ~ 0x04400023 */
+  uint32_t bootmask;                    /* 0x04400024 ~ 0x04400027 */
+  uint32_t bootreserve;                 /* 0x04400028 ~ 0x0440002b */
+  uint32_t systemconfig;                /* 0x0440002c ~ 0x0440002f */
+  uint8_t  rtc_saved_data[32];          /* 0x04400030 ~ 0x0440004f */
+  uint32_t irq_wake_map[4];             /* 0x04400050 ~ 0x0440005f */
+  uint32_t irq_inv_map[4];              /* 0x04400060 ~ 0x0440006f */
+  uint8_t  reserved0[0x100 - 0x70];     /* 0x04400070 ~ 0x044000ff */
+  uint8_t  power_monitor_data[0x420];   /* 0x04400100 ~ 0x0440051f */
+  uint8_t  reserved1[2 * 1024 - 0x520]; /* 0x04400520 ~ 0x044007ff (2KB-0x520)*/
+  uint8_t  gnss_backup_data[24 * 1024]; /* 0x04400800 ~ 0x044067ff (24KB) */
+  uint8_t  gnss_pvtlog_data[ 4 * 1024]; /* 0x04406800 ~ 0x044077ff (4KB) */
+  uint8_t  reserved_romcode[ 2 * 1024]; /* 0x04407800 ~ 0x04407fff (2KB) */
+  uint8_t  log[32 * 1024];              /* 0x04408000 ~ 0x0440ffff (32KB) */
+} backup_info_t;
+
+/********************************************************************************************
+ * Public Data
+ ********************************************************************************************/
+
+/********************************************************************************************
+ * Public Functions
+ ********************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_BACKUPMEM_H */
diff --git a/arch/arm/src/cxd56xx/hardware/cxd5602_memorymap.h b/arch/arm/src/cxd56xx/hardware/cxd5602_memorymap.h
new file mode 100644
index 00000000000..45241b3e5d3
--- /dev/null
+++ b/arch/arm/src/cxd56xx/hardware/cxd5602_memorymap.h
@@ -0,0 +1,123 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/hardware/cxd5602_memorymap.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD5602_MEMORYMAP_H
+#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD5602_MEMORYMAP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CXD56_ADSP_BASE           0x4c000000
+#define CXD56_SYS_MIRROR         0x04000000
+
+#define CXD56_SYS_RAM_BASE        0x05000000
+#define CXD56_GDSP_RAM_BASE       0x09000000
+#define CXD56_ADSP_RAM_BASE       0x0d000000
+#define CXD56_RAM_BASE            0x0d000000
+#define CXD56_RAM_SIZE            0x00180000
+#define CXD56_ARM_BASE            0xe0000000
+#define CXD56_TIMER_BASE          0xe0043000
+#define CXD56_WDOG_BASE           0xe0044000
+#define CXD56_INTC_BASE           0xe0045000
+
+#define CXD56_SWINT_BASE          0x4600c000
+#define CXD56_CPUFIFO_BASE        0x4600c400
+#define CXD56_SPH_BASE            0x4600c800
+
+/* Peripheral and system configuration */
+
+#define CXD56_ROM_BASE            (CXD56_SYS_MIRROR + 0x00000000)
+#define CXD56_TOPREG_BASE         (CXD56_SYS_MIRROR + 0x00100000)
+#define CXD56_TOPREG_SUB_BASE     (CXD56_SYS_MIRROR + 0x00103000)
+#define CXD56_PMU_SUB_BASE        (CXD56_SYS_MIRROR + 0x00106000)
+#define CXD56_FREQDISC_BASE       (CXD56_SYS_MIRROR + 0x00107000)
+#define CXD56_RTC0_BASE           (CXD56_SYS_MIRROR + 0x00108000)
+#define CXD56_RTC1_BASE           (CXD56_SYS_MIRROR + 0x00109000)
+#define CXD56_TDC_BASE            (CXD56_SYS_MIRROR + 0x0010B000)
+
+/* reserved 0x0010c000 - 0x00110fff */
+
+#define CXD56_SPIFLASH_BASE       (CXD56_SYS_MIRROR + 0x00110000)
+
+/* reserved 0x00111000 - 0x0011ffff */
+
+#define CXD56_DMAC0_BASE          (CXD56_SYS_MIRROR + 0x00120000) /* SDMAC */
+#define CXD56_DMAC1_BASE          (CXD56_SYS_MIRROR + 0x00121000) /* HDMAC */
+#define CXD56_DMAC2_BASE          (CXD56_SYS_MIRROR + 0x00122000) /* SYDMAC */
+#define CXD56_DMAC3_BASE          (CXD56_SYS_MIRROR + 0x00123000) /* SYSUB */
+
+/* reserved 0x00124000 - 0x0017ffff */
+
+#define CXD56_SCU_FIFO_REG_BASE   (CXD56_SYS_MIRROR + 0x00180000)
+#define CXD56_SCU_FIFO_4K_BASE    (CXD56_SYS_MIRROR + 0x00182000)
+#define CXD56_SCU_FIFO_8K_BASE    (CXD56_SYS_MIRROR + 0x00183000)
+#define CXD56_SCU_FIFO_32K_BASE   (CXD56_SYS_MIRROR + 0x00185000)
+#define CXD56_SCU_SPI_BASE        (CXD56_SYS_MIRROR + 0x0018d000)
+#define CXD56_SCU_I2C0_BASE       (CXD56_SYS_MIRROR + 0x0018d400)
+#define CXD56_SCU_I2C1_BASE       (CXD56_SYS_MIRROR + 0x0018d800)
+#define CXD56_SCU_ADCIF_BASE      (CXD56_SYS_MIRROR + 0x0018dc00)
+#define CXD56_SCU_SEQ_IRAM_BASE   (CXD56_SYS_MIRROR + 0x00190000)
+#define CXD56_SCU_SEQ_IRAM_MIRROR (CXD56_SYS_MIRROR + 0x00192000)
+#define CXD56_SCU_SEQ_DRAM_BASE   (CXD56_SYS_MIRROR + 0x00194000)
+#define CXD56_SCU_SEQ_DRAM_MIRROR (CXD56_SYS_MIRROR + 0x00194800)
+#define CXD56_SCU_BASE            (CXD56_SYS_MIRROR + 0x00195000)
+#define CXD56_UART0_BASE          (CXD56_SYS_MIRROR + 0x001a9000)
+
+#define CXD56_I2CM_BASE           (CXD56_SYS_MIRROR + 0x001aa000)
+#define CXD56_SPIM_BASE           (CXD56_SYS_MIRROR + 0x001ab000)
+#define CXD56_UART1_BASE          (CXD56_SYS_MIRROR + 0x001ac000)
+
+#define CXD56_CPU_BASE            (CXD56_ADSP_BASE  + 0x02002000)
+#define CXD56_CRG_BASE            (CXD56_ADSP_BASE  + 0x02011000)
+#define CXD56_ADR_CONV_BASE       (CXD56_ADSP_BASE  + 0x02012000)
+#define CXD56_EXCCONF_BASE        (CXD56_ADSP_BASE  + 0x02013000)
+#define CXD56_CISIF_BASE          (CXD56_ADSP_BASE  + 0x02100000)
+#define CXD56_GE2D_BASE           (CXD56_ADSP_BASE  + 0x02101000)
+#define CXD56_ROT_BASE            (CXD56_ADSP_BASE  + 0x02101400)
+#define CXD56_UART2_BASE          (CXD56_ADSP_BASE  + 0x02103000)
+#define CXD56_IMG_SPI_BASE        (CXD56_ADSP_BASE  + 0x02103400) /* IMG_SSP (Display) */
+#define CXD56_IMG_WSPI_BASE       (CXD56_ADSP_BASE  + 0x02103c00) /* IMG_SSP (WiFi) */
+#define CXD56_USBDEV_BASE         (CXD56_ADSP_BASE  + 0x02200000)
+#define CXD56_EMMC_BASE           (CXD56_ADSP_BASE  + 0x02201000)
+#define CXD56_SDIO_BASE           (CXD56_ADSP_BASE  + 0x02202000)
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD5602_MEMORYMAP_H */
diff --git a/arch/arm/src/cxd56xx/hardware/cxd5602_pinconfig.h b/arch/arm/src/cxd56xx/hardware/cxd5602_pinconfig.h
new file mode 100644
index 00000000000..5b796a964a8
--- /dev/null
+++ b/arch/arm/src/cxd56xx/hardware/cxd5602_pinconfig.h
@@ -0,0 +1,659 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/hardware/cxd5602_pinconfig.h
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_PINCONFIG_H
+#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_PINCONFIG_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include 
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+/* Set the standard pinconf macro Definitions
+ *  - If it's used as input pin, then set 1. Otherwise set 0 (default).
+ *  - If it's drived in 4mA, then set 1. Otherwise set 0 (default 2mA).
+ *  - If it's used as weak pull-up/down, then set PINCONF_PULLUP/PINCONF_PULLDOWN.
+ *    Otherwise set 0 (default).
+ *
+ */
+#define PINCONF(pin, mode, input, drive, pull) \
+  ( \
+    (PINCONF_SET_PIN(pin)) | \
+    (PINCONF_SET_MODE(mode)) | \
+    ((input) ? PINCONF_INPUT_ENABLE : PINCONF_INPUT_DISABLE) | \
+    ((drive) ?  PINCONF_DRIVE_HIGH : PINCONF_DRIVE_NORMAL) | \
+    ((pull) ? (pull) : PINCONF_FLOAT) \
+    )
+
+/* CXD5602 Pin Configuration Table
+ *
+ * Group            Pin             100 185 Mode0   Mode1           Mode2           Mode3
+ * ================ =============== === === ======= =============== =============== ===============
+ * I2C4             I2C4_BCK        o   o   GPIO    I2C4(PMIC)      -               -
+ *                  I2C4_BDT        o   o   GPIO    I2C4(PMIC)      -               -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * PMIC_INT         PMIC_INT        o   o   GPIO    PMIC_INT        PMIC_INT(OD)    -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * RTC_IRQ_OUT      RTC_IRQ_OUT     -   o   GPIO    RTC_IRQ_OUT     RTC_IRQ_OUT(OD) -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * AP_CLK           AP_CLK          o   o   GPIO    AP_CLK          PMU_WDT         PMU_WDT(OD)
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * GNSS_1PPS_OUT    GNSS_1PPS_OUT   -   o   GPIO    GNSS_1PPS_OUT   CPU_WDT         CPU_WDT(OD)
+ * ---------------- --------------- --- --- --------------- ------- --------------- ---------------
+ * SPI0A            SPI0_CS_X       o   o   GPIO    UART1(DBG)      SPI0(CFG)       SYS_MONOUT0
+ *                  SPI0_SCK        o   o   GPIO    UART1(DBG)      SPI0(CFG)       SYS_MONOUT1
+ * ---------------- --------------- --- --- ------- ---------------                 ---------------
+ * SPI0B            SPI0_MOSI       -   o   GPIO    I2C2(CFG)       SPI0(CFG)       SYS_MONOUT2
+ *                  SPI0_MISO       -   o   GPIO    I2C2(CFG)       SPI0(CFG)       SYS_MONOUT3
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * SPI1A            SPI1_CS_X       o   o   GPIO    SPI1(Flash)     SPI0(CFG)       SYS_MONOUT4
+ *                  SPI1_SCK        o   o   GPIO    SPI1(Flash)     SPI0(CFG)       SYS_MONOUT5
+ *                  SPI1_IO0        o   o   GPIO    SPI1(Flash)     SPI0(CFG)       SYS_MONOUT6
+ *                  SPI1_IO1        o   o   GPIO    SPI1(Flash)     SPI0(CFG)       SYS_MONOUT7
+ * ---------------- --------------- --- --- -------                 --------------- ---------------
+ * SPI1B            SPI1_IO2        o   o   GPIO    SPI1(Flash)     -               SYS_MONOUT8
+ *                  SPI1_IO3        o   o   GPIO    SPI1(Flash)     -               SYS_MONOUT9
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * SPI2A            SPI2_CS_X       o   o   GPIO    SPI2(HostIF)    UART0(HostIF)   I2C3(HostIF)
+ *                  SPI2_SCK        o   o   GPIO    SPI2(HostIF)    UART0(HostIF)   I2C3(HostIF)
+ * ---------------- --------------- --- --- -------                 --------------- ---------------
+ * SPI2B            SPI2_MOSI       o   o   GPIO    SPI2(HostIF)    UART0(HostIF)   -
+ *                  SPI2_MISO       o   o   GPIO    SPI2(HostIF)    UART0(HostIF)   -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * HIFIRQ           HIF_IRQ_OUT     o   o   GPIO    HIF_IRQ_OUT     HIF_IRQ_OUT(OD) GNSS_1PPS_OUT
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * HIFEXT           HIF_GPIO0       -   o   GPIO    -               -               GPS_EXTLD
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * SEN_IRQ_IN       SEN_IRQ_IN      o   o   GPIO    SEN_IRQ_IN      SYS_MONOUT0     DBG_LOGGER
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * SPI3_CS0_X       SPI3_CS0_X      o   o   GPIO    SPI3_CS0_X      SYS_MONOUT1     DBG_LOGGER
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * SPI3_CS1_X       SPI3_CS1_X      o   o   GPIO    SPI3_CS1_X      SYS_MONOUT2     DBG_LOGGER
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * SPI3_CS2_X       SPI3_CS2_X      o   o   GPIO    SPI3_CS2_X      SYS_MONOUT3     DBG_LOGGER
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * SPI3             SPI3_SCK        o   o   GPIO    SPI3(Sensor)    SYS_MONOUT4     DBG_LOGGER
+ *                  SPI3_MOSI       o   o   GPIO    SPI3(Sensor)    SYS_MONOUT5     DBG_LOGGER
+ *                  SPI3_MISO       o   o   GPIO    SPI3(Sensor)    SYS_MONOUT6     DBG_LOGGER
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * I2C0             I2C0_BCK        o   o   GPIO    I2C0(Sensor)    SYS_MONOUT7     DBG_LOGGER
+ *                  I2C0_BDT        o   o   GPIO    I2C0(Sensor)    SYS_MONOUT8     DBG_LOGGER
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * PWMA             PWM0            o   o   GPIO    PWMA            SYS_MONOUT9     DBG_LOGGER
+ *                  PWM1            o   o   GPIO    PWMA            GPIO            DBG_LOGGER
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * PWMB             PWM2            o   o   GPIO    PWMB            I2C1(Sensor)    DBG_LOGGER
+ *                  PWM3            o   o   GPIO    PWMB            I2C1(Sensor)    DBG_LOGGER
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * IS               IS_CLK          -   o   GPIO    IS              -               -
+ *                  IS_VSYNC        -   o   GPIO    IS              -               -
+ *                  IS_HSYNC        -   o   GPIO    IS              -               -
+ *                  IS_DATA0        -   o   GPIO    IS              -               -
+ *                  IS_DATA1        -   o   GPIO    IS              -               -
+ *                  IS_DATA2        -   o   GPIO    IS              -               -
+ *                  IS_DATA3        -   o   GPIO    IS              -               -
+ *                  IS_DATA4        -   o   GPIO    IS              -               -
+ *                  IS_DATA5        -   o   GPIO    IS              -               -
+ *                  IS_DATA6        -   o   GPIO    IS              -               -
+ *                  IS_DATA7        -   o   GPIO    IS              -               -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * UART2            UART2_TXD       o   o   GPIO    UART2(APP)      APP_MONOUT0     -
+ *                  UART2_RXD       o   o   GPIO    UART2(APP)      APP_MONOUT1     -
+ *                  UART2_CTS       o   o   GPIO    UART2(APP)      APP_MONOUT2     -
+ *                  UART2_RTS       o   o   GPIO    UART2(APP)      APP_MONOUT3     -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * SPI4             SPI4_CS_X       o   o   GPIO    SPI4(APP)       APP_MONOUT4     -
+ *                  SPI4_SCK        o   o   GPIO    SPI4(APP)       APP_MONOUT5     -
+ *                  SPI4_MOSI       o   o   GPIO    SPI4(APP)       APP_MONOUT6     -
+ *                  SPI4_MISO       o   o   GPIO    SPI4(APP)       APP_MONOUT7     -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * EMMCA            EMMC_CLK        o   o   GPIO    EMMC            SPI5(APP)       -
+ *                  EMMC_CMD        o   o   GPIO    EMMC            SPI5(APP)       -
+ *                  EMMC_DATA0      o   o   GPIO    EMMC            SPI5(APP)       -
+ *                  EMMC_DATA1      o   o   GPIO    EMMC            SPI5(APP)       -
+ * ---------------- --------------- --- --- -------                 --------------- ---------------
+ * EMMCB            EMMC_DATA2      o   o   GPIO    EMMC            APP_MONOUT8     -
+ *                  EMMC_DATA3      o   o   GPIO    EMMC            APP_MONOUT9     -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * SDIOA            SDIO_CLK        -   o   GPIO    SDIO            SPI5(APP)       -
+ *                  SDIO_CMD        -   o   GPIO    SDIO            SPI5(APP)       -
+ *                  SDIO_DATA0      -   o   GPIO    SDIO            SPI5(APP)       -
+ *                  SDIO_DATA1      -   o   GPIO    SDIO            SPI5(APP)       -
+ *                  SDIO_DATA2      -   o   GPIO    SDIO            GPIO            -
+ *                  SDIO_DATA3      -   o   GPIO    SDIO            GPIO            -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * SDIOB            SDIO_CD         -   o   GPIO    SDIO            -               -
+ *                  SDIO_WP         -   o   GPIO    SDIO            -               -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * SDIOC            SDIO_CMDDIR     -   o   GPIO    SDIO            -               -
+ *                  SDIO_DIR0       -   o   GPIO    SDIO            -               -
+ *                  SDIO_DIR1_3     -   o   GPIO    SDIO            -               -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * SDIOD            SDIO_CLKI       -   o   GPIO    SDIO            -               -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * I2S0             I2S0_BCK        o   o   GPIO    I2S0            APP_MONOUT0     -
+ *                  I2S0_LRCK       o   o   GPIO    I2S0            APP_MONOUT1     -
+ *                  I2S0_DATA_IN    o   o   GPIO    I2S0            APP_MONOUT2     -
+ *                  I2S0_DATA_OUT   o   o   GPIO    I2S0            APP_MONOUT3     -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * I2S1             I2S1_BCK        -   o   GPIO    I2S1            APP_MONOUT4     -
+ *                  I2S1_LRCK       -   o   GPIO    I2S1            APP_MONOUT5     -
+ *                  I2S1_DATA_IN    -   o   GPIO    I2S1            APP_MONOUT6     -
+ *                  I2S1_DATA_OUT   -   o   GPIO    I2S1            APP_MONOUT7     -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * MCLK             MCLK            o   o   GPIO    MCLK            APP_MONOUT8     -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * PDM              PDM_CLK         o   o   GPIO    PDM             APP_MONOUT9     -
+ *                  PDM_IN          o   o   GPIO    PDM             GPIO            -
+ *                  PDM_OUT         o   o   GPIO    PDM             GPIO            -
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ * USBVBUS          USB_VBUSINT     o   o   GPIO    USB_VBUSINT     -               DBG_LOGGER
+ * ---------------- --------------- --- --- ------- --------------- --------------- ---------------
+ */
+
+/* Default pin configurations
+ *  Mode: shared pin function mode
+ *  ENZI: 1=Input Enable, 0=Input Disable
+ *  4mA : Drive Current 1=4mA, 0=2mA
+ *  Pull: 0=HiZ floating, PINCONF_PULLUP, PINCONF_PULLDOWN
+ *                                                                      M  E     P
+ *                                                  P                   o  N  4  u
+ *                                                  i                   d  Z  m  l
+ *                                                  n                   e  I  A  l
+ */
+#define PINCONF_I2C4_BCK_GPIO               PINCONF(PIN_I2C4_BCK,       0, 0, 0, 0)
+#define PINCONF_I2C4_BCK                    PINCONF(PIN_I2C4_BCK,       1, 1, 0, 0)
+#define PINCONF_I2C4_BDT_GPIO               PINCONF(PIN_I2C4_BDT,       0, 0, 0, 0)
+#define PINCONF_I2C4_BDT                    PINCONF(PIN_I2C4_BDT,       1, 1, 0, 0)
+#define PINCONF_PMIC_INT_GPIO               PINCONF(PIN_PMIC_INT,       0, 0, 0, 0)
+#define PINCONF_PMIC_INT                    PINCONF(PIN_PMIC_INT,       1, 1, 0, 0)
+#define PINCONF_PMIC_INT_OD                 PINCONF(PIN_PMIC_INT,       2, 1, 0, 0)
+#ifdef CONFIG_CXD56_FCBGA
+#define PINCONF_RTC_IRQ_OUT_GPIO            PINCONF(PIN_RTC_IRQ_OUT,    0, 0, 0, 0)
+#define PINCONF_RTC_IRQ_OUT                 PINCONF(PIN_RTC_IRQ_OUT,    1, 0, 0, 0)
+#define PINCONF_RTC_IRQ_OUT_OD              PINCONF(PIN_RTC_IRQ_OUT,    2, 0, 0, 0)
+#endif /* CONFIG_CXD56_FCBGA */
+#define PINCONF_AP_CLK_GPIO                 PINCONF(PIN_AP_CLK,         0, 0, 0, 0)
+#define PINCONF_AP_CLK                      PINCONF(PIN_AP_CLK,         1, 1, 0, 0)
+#define PINCONF_AP_CLK_PMU_WDT              PINCONF(PIN_AP_CLK,         2, 0, 0, 0)
+#define PINCONF_AP_CLK_PMU_WDT_OD           PINCONF(PIN_AP_CLK,         3, 0, 0, 0)
+#ifdef CONFIG_CXD56_FCBGA
+#define PINCONF_GNSS_1PPS_OUT_GPIO          PINCONF(PIN_GNSS_1PPS_OUT,  0, 0, 0, 0)
+#define PINCONF_GNSS_1PPS_OUT               PINCONF(PIN_GNSS_1PPS_OUT,  1, 0, 0, 0)
+#define PINCONF_GNSS_1PPS_OUT_CPU_WDT       PINCONF(PIN_GNSS_1PPS_OUT,  2, 0, 0, 0)
+#define PINCONF_GNSS_1PPS_OUT_CPU_WDT_OD    PINCONF(PIN_GNSS_1PPS_OUT,  3, 0, 0, 0)
+#endif /* CONFIG_CXD56_FCBGA */
+#define PINCONF_SPI0_CS_X_GPIO              PINCONF(PIN_SPI0_CS_X,      0, 0, 0, 0)
+#define PINCONF_SPI0_CS_X_UART1_TXD         PINCONF(PIN_SPI0_CS_X,      1, 0, 0, 0)
+#define PINCONF_SPI0_CS_X                   PINCONF(PIN_SPI0_CS_X,      2, 0, 0, 0)
+#define PINCONF_SPI0_CS_X_SYS_MONOUT0       PINCONF(PIN_SPI0_CS_X,      3, 0, 0, 0)
+#define PINCONF_SPI0_SCK_GPIO               PINCONF(PIN_SPI0_SCK,       0, 0, 0, 0)
+#define PINCONF_SPI0_SCK_UART1_RXD          PINCONF(PIN_SPI0_SCK,       1, 1, 0, 0)
+#define PINCONF_SPI0_SCK                    PINCONF(PIN_SPI0_SCK,       2, 0, 0, 0)
+#define PINCONF_SPI0_SCK_SYS_MONOUT1        PINCONF(PIN_SPI0_SCK,       3, 0, 0, 0)
+#ifdef CONFIG_CXD56_FCBGA
+#define PINCONF_SPI0_MOSI_GPIO              PINCONF(PIN_SPI0_MOSI,      0, 0, 0, 0)
+#define PINCONF_SPI0_MOSI_I2C2_BCK          PINCONF(PIN_SPI0_MOSI,      1, 1, 0, 0)
+#define PINCONF_SPI0_MOSI                   PINCONF(PIN_SPI0_MOSI,      2, 0, 0, 0)
+#define PINCONF_SPI0_MOSI_SYS_MONOUT2       PINCONF(PIN_SPI0_MOSI,      3, 0, 0, 0)
+#define PINCONF_SPI0_MISO_GPIO              PINCONF(PIN_SPI0_MISO,      0, 0, 0, 0)
+#define PINCONF_SPI0_MISO_I2C2_BDT          PINCONF(PIN_SPI0_MISO,      1, 1, 0, 0)
+#define PINCONF_SPI0_MISO                   PINCONF(PIN_SPI0_MISO,      2, 1, 0, 0)
+#define PINCONF_SPI0_MISO_SYS_MONOUT3       PINCONF(PIN_SPI0_MISO,      3, 0, 0, 0)
+#endif /* CONFIG_CXD56_FCBGA */
+#define PINCONF_SPI1_CS_X_GPIO              PINCONF(PIN_SPI1_CS_X,      0, 0, 0, 0)
+#define PINCONF_SPI1_CS_X                   PINCONF(PIN_SPI1_CS_X,      1, 0, 1, 0)
+#define PINCONF_SPI1_CS_X_SPI0_CS_X         PINCONF(PIN_SPI1_CS_X,      2, 0, 0, 0)
+#define PINCONF_SPI1_CS_X_SYS_MONOUT4       PINCONF(PIN_SPI1_CS_X,      3, 0, 0, 0)
+#define PINCONF_SPI1_SCK_GPIO               PINCONF(PIN_SPI1_SCK,       0, 0, 0, 0)
+#define PINCONF_SPI1_SCK                    PINCONF(PIN_SPI1_SCK,       1, 0, 1, 0)
+#define PINCONF_SPI1_SCK_SPI0_SCK           PINCONF(PIN_SPI1_SCK,       2, 0, 0, 0)
+#define PINCONF_SPI1_SCK_SYS_MONOUT5        PINCONF(PIN_SPI1_SCK,       3, 0, 0, 0)
+#define PINCONF_SPI1_IO0_GPIO               PINCONF(PIN_SPI1_IO0,       0, 0, 0, 0)
+#define PINCONF_SPI1_IO0                    PINCONF(PIN_SPI1_IO0,       1, 1, 1, 0)
+#define PINCONF_SPI1_IO0_SPI0_MOSI          PINCONF(PIN_SPI1_IO0,       2, 0, 0, 0)
+#define PINCONF_SPI1_IO0_SYS_MONOUT6        PINCONF(PIN_SPI1_IO0,       3, 0, 0, 0)
+#define PINCONF_SPI1_IO1_GPIO               PINCONF(PIN_SPI1_IO1,       0, 0, 0, 0)
+#define PINCONF_SPI1_IO1                    PINCONF(PIN_SPI1_IO1,       1, 1, 1, 0)
+#define PINCONF_SPI1_IO1_SPI0_MISO          PINCONF(PIN_SPI1_IO1,       2, 1, 0, 0)
+#define PINCONF_SPI1_IO1_SYS_MONOUT7        PINCONF(PIN_SPI1_IO1,       3, 0, 0, 0)
+#define PINCONF_SPI1_IO2_GPIO               PINCONF(PIN_SPI1_IO2,       0, 0, 0, 0)
+#define PINCONF_SPI1_IO2                    PINCONF(PIN_SPI1_IO2,       1, 1, 1, 0)
+#define PINCONF_SPI1_IO2_SYS_MONOUT8        PINCONF(PIN_SPI1_IO2,       3, 0, 0, 0)
+#define PINCONF_SPI1_IO3_GPIO               PINCONF(PIN_SPI1_IO3,       0, 0, 0, 0)
+#define PINCONF_SPI1_IO3                    PINCONF(PIN_SPI1_IO3,       1, 1, 1, 0)
+#define PINCONF_SPI1_IO3_SYS_MONOUT9        PINCONF(PIN_SPI1_IO3,       3, 0, 0, 0)
+#define PINCONF_SPI2_CS_X_GPIO              PINCONF(PIN_SPI2_CS_X,      0, 0, 0, 0)
+#define PINCONF_SPI2_CS_X                   PINCONF(PIN_SPI2_CS_X,      1, 1, 0, 0)
+#define PINCONF_SPI2_CS_X_UART0_TXD         PINCONF(PIN_SPI2_CS_X,      2, 0, 0, 0)
+#define PINCONF_SPI2_CS_X_I2C3_BCK          PINCONF(PIN_SPI2_CS_X,      3, 1, 0, 0)
+#define PINCONF_SPI2_SCK_GPIO               PINCONF(PIN_SPI2_SCK,       0, 0, 0, 0)
+#define PINCONF_SPI2_SCK                    PINCONF(PIN_SPI2_SCK,       1, 1, 0, 0)
+#define PINCONF_SPI2_SCK_UART0_RXD          PINCONF(PIN_SPI2_SCK,       2, 1, 0, 0)
+#define PINCONF_SPI2_SCK_I2C3_BDT           PINCONF(PIN_SPI2_SCK,       3, 1, 0, 0)
+#define PINCONF_SPI2_MOSI_GPIO              PINCONF(PIN_SPI2_MOSI,      0, 0, 0, 0)
+#define PINCONF_SPI2_MOSI                   PINCONF(PIN_SPI2_MOSI,      1, 1, 0, 0)
+#define PINCONF_SPI2_MOSI_UART0_CTS         PINCONF(PIN_SPI2_MOSI,      2, 1, 0, 0)
+#define PINCONF_SPI2_MISO_GPIO              PINCONF(PIN_SPI2_MISO,      0, 0, 0, 0)
+#define PINCONF_SPI2_MISO                   PINCONF(PIN_SPI2_MISO,      1, 0, 0, 0)
+#define PINCONF_SPI2_MISO_UART0_RTS         PINCONF(PIN_SPI2_MISO,      2, 0, 0, 0)
+#define PINCONF_HIF_IRQ_OUT_GPIO            PINCONF(PIN_HIF_IRQ_OUT,    0, 0, 0, 0)
+#define PINCONF_HIF_IRQ_OUT                 PINCONF(PIN_HIF_IRQ_OUT,    1, 0, 0, 0)
+#define PINCONF_HIF_IRQ_OUT_OD              PINCONF(PIN_HIF_IRQ_OUT,    2, 0, 0, 0)
+#define PINCONF_HIF_IRQ_OUT_GNSS_1PPS_OUT   PINCONF(PIN_HIF_IRQ_OUT,    3, 0, 0, 0)
+#ifdef CONFIG_CXD56_FCBGA
+#define PINCONF_HIF_GPIO0_GPIO              PINCONF(PIN_HIF_GPIO0,      0, 0, 0, 0)
+#define PINCONF_HIF_GPIO0_GPS_EXTLD         PINCONF(PIN_HIF_GPIO0,      3, 0, 0, 0)
+#endif /* CONFIG_CXD56_FCBGA */
+#define PINCONF_SEN_IRQ_IN_GPIO             PINCONF(PIN_SEN_IRQ_IN,     0, 0, 0, 0)
+#define PINCONF_SEN_IRQ_IN                  PINCONF(PIN_SEN_IRQ_IN,     1, 1, 0, 0)
+#define PINCONF_SEN_IRQ_IN_SYS_MONOUT0      PINCONF(PIN_SEN_IRQ_IN,     2, 0, 0, 0)
+#define PINCONF_SEN_IRQ_IN_DBG_LOGGERI3     PINCONF(PIN_SEN_IRQ_IN,     3, 0, 0, 0)
+#define PINCONF_SPI3_CS0_X_GPIO             PINCONF(PIN_SPI3_CS0_X,     0, 0, 0, 0)
+#define PINCONF_SPI3_CS0_X                  PINCONF(PIN_SPI3_CS0_X,     1, 0, 0, 0)
+#define PINCONF_SPI3_CS0_X_SYS_MONOUT1      PINCONF(PIN_SPI3_CS0_X,     2, 0, 0, 0)
+#define PINCONF_SPI3_CS0_X_DBG_LOGGERI2     PINCONF(PIN_SPI3_CS0_X,     3, 0, 0, 0)
+#define PINCONF_SPI3_CS1_X_GPIO             PINCONF(PIN_SPI3_CS1_X,     0, 0, 0, 0)
+#define PINCONF_SPI3_CS1_X                  PINCONF(PIN_SPI3_CS1_X,     1, 0, 0, 0)
+#define PINCONF_SPI3_CS1_X_SYS_MONOUT2      PINCONF(PIN_SPI3_CS1_X,     2, 0, 0, 0)
+#define PINCONF_SPI3_CS1_X_DBG_LOGGERI1     PINCONF(PIN_SPI3_CS1_X,     3, 0, 0, 0)
+#define PINCONF_SPI3_CS2_X_GPIO             PINCONF(PIN_SPI3_CS2_X,     0, 0, 0, 0)
+#define PINCONF_SPI3_CS2_X                  PINCONF(PIN_SPI3_CS2_X,     1, 0, 0, 0)
+#define PINCONF_SPI3_CS2_X_SYS_MONOUT3      PINCONF(PIN_SPI3_CS2_X,     2, 0, 0, 0)
+#define PINCONF_SPI3_CS2_X_DBG_LOGGERI0     PINCONF(PIN_SPI3_CS2_X,     3, 0, 0, 0)
+#define PINCONF_SPI3_SCK_GPIO               PINCONF(PIN_SPI3_SCK,       0, 0, 0, 0)
+#define PINCONF_SPI3_SCK                    PINCONF(PIN_SPI3_SCK,       1, 0, 0, 0)
+#define PINCONF_SPI3_SCK_SYS_MONOUT4        PINCONF(PIN_SPI3_SCK,       2, 0, 0, 0)
+#define PINCONF_SPI3_SCK_DBG_LOGGERQ5       PINCONF(PIN_SPI3_SCK,       3, 0, 0, 0)
+#define PINCONF_SPI3_MOSI_GPIO              PINCONF(PIN_SPI3_MOSI,      0, 0, 0, 0)
+#define PINCONF_SPI3_MOSI                   PINCONF(PIN_SPI3_MOSI,      1, 0, 0, 0)
+#define PINCONF_SPI3_MOSI_SYS_MONOUT5       PINCONF(PIN_SPI3_MOSI,      2, 0, 0, 0)
+#define PINCONF_SPI3_MOSI_DBG_LOGGERQ4      PINCONF(PIN_SPI3_MOSI,      3, 0, 0, 0)
+#define PINCONF_SPI3_MISO_GPIO              PINCONF(PIN_SPI3_MISO,      0, 0, 0, 0)
+#define PINCONF_SPI3_MISO                   PINCONF(PIN_SPI3_MISO,      1, 1, 0, 0)
+#define PINCONF_SPI3_MISO_SYS_MONOUT6       PINCONF(PIN_SPI3_MISO,      2, 0, 0, 0)
+#define PINCONF_SPI3_MISO_DBG_LOGGERQ3      PINCONF(PIN_SPI3_MISO,      3, 0, 0, 0)
+#define PINCONF_I2C0_BCK_GPIO               PINCONF(PIN_I2C0_BCK,       0, 0, 0, 0)
+#define PINCONF_I2C0_BCK                    PINCONF(PIN_I2C0_BCK,       1, 1, 0, 0)
+#define PINCONF_I2C0_BCK_SYS_MONOUT7        PINCONF(PIN_I2C0_BCK,       2, 0, 0, 0)
+#define PINCONF_I2C0_BCK_DBG_LOGGERQ2       PINCONF(PIN_I2C0_BCK,       3, 0, 0, 0)
+#define PINCONF_I2C0_BDT_GPIO               PINCONF(PIN_I2C0_BDT,       0, 0, 0, 0)
+#define PINCONF_I2C0_BDT                    PINCONF(PIN_I2C0_BDT,       1, 1, 0, 0)
+#define PINCONF_I2C0_BDT_SYS_MONOUT8        PINCONF(PIN_I2C0_BDT,       2, 0, 0, 0)
+#define PINCONF_I2C0_BDT_DBG_LOGGERQ1       PINCONF(PIN_I2C0_BDT,       3, 0, 0, 0)
+#define PINCONF_PWM0_GPIO                   PINCONF(PIN_PWM0,           0, 0, 0, 0)
+#define PINCONF_PWM0                        PINCONF(PIN_PWM0,           1, 0, 0, 0)
+#define PINCONF_PWM0_SYS_MONOUT9            PINCONF(PIN_PWM0,           2, 0, 0, 0)
+#define PINCONF_PWM0_DBG_LOGGERQ0           PINCONF(PIN_PWM0,           3, 0, 0, 0)
+#define PINCONF_PWM1_GPIO                   PINCONF(PIN_PWM1,           0, 0, 0, 0)
+#define PINCONF_PWM1                        PINCONF(PIN_PWM1,           1, 0, 0, 0)
+#define PINCONF_PWM1_SYS_MONOUT_GPIO        PINCONF(PIN_PWM1,           2, 0, 0, 0)
+#define PINCONF_PWM1_DBG_LOGGERSEL          PINCONF(PIN_PWM1,           3, 0, 0, 0)
+#define PINCONF_PWM2_GPIO                   PINCONF(PIN_PWM2,           0, 0, 0, 0)
+#define PINCONF_PWM2                        PINCONF(PIN_PWM2,           1, 0, 0, 0)
+#define PINCONF_PWM2_I2C1_BCK               PINCONF(PIN_PWM2,           2, 1, 0, 0)
+#define PINCONF_PWM2_DBG_LOGGERI5           PINCONF(PIN_PWM2,           3, 0, 0, 0)
+#define PINCONF_PWM3_GPIO                   PINCONF(PIN_PWM3,           0, 0, 0, 0)
+#define PINCONF_PWM3                        PINCONF(PIN_PWM3,           1, 0, 0, 0)
+#define PINCONF_PWM3_I2C1_BDT               PINCONF(PIN_PWM3,           2, 1, 0, 0)
+#define PINCONF_PWM3_DBG_LOGGERI4           PINCONF(PIN_PWM3,           3, 0, 0, 0)
+#ifdef CONFIG_CXD56_FCBGA
+#define PINCONF_IS_CLK_GPIO                 PINCONF(PIN_IS_CLK,         0, 0, 0, 0)
+#define PINCONF_IS_CLK                      PINCONF(PIN_IS_CLK,         1, 1, 0, 0)
+#define PINCONF_IS_VSYNC_GPIO               PINCONF(PIN_IS_VSYNC,       0, 0, 0, 0)
+#define PINCONF_IS_VSYNC                    PINCONF(PIN_IS_VSYNC,       1, 1, 0, 0)
+#define PINCONF_IS_HSYNC_GPIO               PINCONF(PIN_IS_HSYNC,       0, 0, 0, 0)
+#define PINCONF_IS_HSYNC                    PINCONF(PIN_IS_HSYNC,       1, 1, 0, 0)
+#define PINCONF_IS_DATA0_GPIO               PINCONF(PIN_IS_DATA0,       0, 0, 0, 0)
+#define PINCONF_IS_DATA0                    PINCONF(PIN_IS_DATA0,       1, 1, 0, 0)
+#define PINCONF_IS_DATA1_GPIO               PINCONF(PIN_IS_DATA1,       0, 0, 0, 0)
+#define PINCONF_IS_DATA1                    PINCONF(PIN_IS_DATA1,       1, 1, 0, 0)
+#define PINCONF_IS_DATA2_GPIO               PINCONF(PIN_IS_DATA2,       0, 0, 0, 0)
+#define PINCONF_IS_DATA2                    PINCONF(PIN_IS_DATA2,       1, 1, 0, 0)
+#define PINCONF_IS_DATA3_GPIO               PINCONF(PIN_IS_DATA3,       0, 0, 0, 0)
+#define PINCONF_IS_DATA3                    PINCONF(PIN_IS_DATA3,       1, 1, 0, 0)
+#define PINCONF_IS_DATA4_GPIO               PINCONF(PIN_IS_DATA4,       0, 0, 0, 0)
+#define PINCONF_IS_DATA4                    PINCONF(PIN_IS_DATA4,       1, 1, 0, 0)
+#define PINCONF_IS_DATA5_GPIO               PINCONF(PIN_IS_DATA5,       0, 0, 0, 0)
+#define PINCONF_IS_DATA5                    PINCONF(PIN_IS_DATA5,       1, 1, 0, 0)
+#define PINCONF_IS_DATA6_GPIO               PINCONF(PIN_IS_DATA6,       0, 0, 0, 0)
+#define PINCONF_IS_DATA6                    PINCONF(PIN_IS_DATA6,       1, 1, 0, 0)
+#define PINCONF_IS_DATA7_GPIO               PINCONF(PIN_IS_DATA7,       0, 0, 0, 0)
+#define PINCONF_IS_DATA7                    PINCONF(PIN_IS_DATA7,       1, 1, 0, 0)
+#endif /* CONFIG_CXD56_FCBGA */
+#define PINCONF_UART2_TXD_GPIO              PINCONF(PIN_UART2_TXD,      0, 0, 0, 0)
+#define PINCONF_UART2_TXD                   PINCONF(PIN_UART2_TXD,      1, 0, 0, 0)
+#define PINCONF_UART2_TXD_APP_MONOUT0       PINCONF(PIN_UART2_TXD,      2, 0, 0, 0)
+#define PINCONF_UART2_RXD_GPIO              PINCONF(PIN_UART2_RXD,      0, 0, 0, 0)
+#define PINCONF_UART2_RXD                   PINCONF(PIN_UART2_RXD,      1, 1, 0, 0)
+#define PINCONF_UART2_RXD_APP_MONOUT1       PINCONF(PIN_UART2_RXD,      2, 0, 0, 0)
+#define PINCONF_UART2_CTS_GPIO              PINCONF(PIN_UART2_CTS,      0, 0, 0, 0)
+#define PINCONF_UART2_CTS                   PINCONF(PIN_UART2_CTS,      1, 1, 0, 0)
+#define PINCONF_UART2_CTS_APP_MONOUT2       PINCONF(PIN_UART2_CTS,      2, 0, 0, 0)
+#define PINCONF_UART2_RTS_GPIO              PINCONF(PIN_UART2_RTS,      0, 0, 0, 0)
+#define PINCONF_UART2_RTS                   PINCONF(PIN_UART2_RTS,      1, 0, 0, 0)
+#define PINCONF_UART2_RTS_APP_MONOUT3       PINCONF(PIN_UART2_RTS,      2, 0, 0, 0)
+#define PINCONF_SPI4_CS_X_GPIO              PINCONF(PIN_SPI4_CS_X,      0, 0, 0, 0)
+#define PINCONF_SPI4_CS_X                   PINCONF(PIN_SPI4_CS_X,      1, 0, 0, 0)
+#define PINCONF_SPI4_CS_X_APP_MONOUT4       PINCONF(PIN_SPI4_CS_X,      2, 0, 0, 0)
+#define PINCONF_SPI4_SCK_GPIO               PINCONF(PIN_SPI4_SCK,       0, 0, 0, 0)
+#define PINCONF_SPI4_SCK                    PINCONF(PIN_SPI4_SCK,       1, 0, 0, 0)
+#define PINCONF_SPI4_SCK_APP_MONOUT5        PINCONF(PIN_SPI4_SCK,       2, 0, 0, 0)
+#define PINCONF_SPI4_MOSI_GPIO              PINCONF(PIN_SPI4_MOSI,      0, 0, 0, 0)
+#define PINCONF_SPI4_MOSI                   PINCONF(PIN_SPI4_MOSI,      1, 0, 0, 0)
+#define PINCONF_SPI4_MOSI_APP_MONOUT6       PINCONF(PIN_SPI4_MOSI,      2, 0, 0, 0)
+#define PINCONF_SPI4_MISO_GPIO              PINCONF(PIN_SPI4_MISO,      0, 0, 0, 0)
+#define PINCONF_SPI4_MISO                   PINCONF(PIN_SPI4_MISO,      1, 1, 0, 0)
+#define PINCONF_SPI4_MISO_APP_MONOUT7       PINCONF(PIN_SPI4_MISO,      2, 0, 0, 0)
+#define PINCONF_EMMC_CLK_GPIO               PINCONF(PIN_EMMC_CLK,       0, 0, 0, 0)
+#define PINCONF_EMMC_CLK                    PINCONF(PIN_EMMC_CLK,       1, 0, 0, 0)
+#define PINCONF_EMMC_CLK_SPI5_SCK           PINCONF(PIN_EMMC_CLK,       2, 0, 0, 0)
+#define PINCONF_EMMC_CMD_GPIO               PINCONF(PIN_EMMC_CMD,       0, 0, 0, 0)
+#define PINCONF_EMMC_CMD                    PINCONF(PIN_EMMC_CMD,       1, 1, 0, 0)
+#define PINCONF_EMMC_CMD_SPI5_CS_X          PINCONF(PIN_EMMC_CMD,       2, 0, 0, 0)
+#define PINCONF_EMMC_DATA0_GPIO             PINCONF(PIN_EMMC_DATA0,     0, 0, 0, 0)
+#define PINCONF_EMMC_DATA0                  PINCONF(PIN_EMMC_DATA0,     1, 1, 0, 0)
+#define PINCONF_EMMC_DATA0_SPI5_MOSI        PINCONF(PIN_EMMC_DATA0,     2, 0, 0, 0)
+#define PINCONF_EMMC_DATA1_GPIO             PINCONF(PIN_EMMC_DATA1,     0, 0, 0, 0)
+#define PINCONF_EMMC_DATA1                  PINCONF(PIN_EMMC_DATA1,     1, 1, 0, 0)
+#define PINCONF_EMMC_DATA1_SPI5_MISO        PINCONF(PIN_EMMC_DATA1,     2, 1, 0, 0)
+#define PINCONF_EMMC_DATA2_GPIO             PINCONF(PIN_EMMC_DATA2,     0, 0, 0, 0)
+#define PINCONF_EMMC_DATA2                  PINCONF(PIN_EMMC_DATA2,     1, 1, 0, 0)
+#define PINCONF_EMMC_DATA2_APP_MONOUT8      PINCONF(PIN_EMMC_DATA2,     2, 0, 0, 0)
+#define PINCONF_EMMC_DATA3_GPIO             PINCONF(PIN_EMMC_DATA3,     0, 0, 0, 0)
+#define PINCONF_EMMC_DATA3                  PINCONF(PIN_EMMC_DATA3,     1, 1, 0, 0)
+#define PINCONF_EMMC_DATA3_APP_MONOUT9      PINCONF(PIN_EMMC_DATA3,     2, 0, 0, 0)
+#ifdef CONFIG_CXD56_FCBGA
+#define PINCONF_SDIO_CLK_GPIO               PINCONF(PIN_SDIO_CLK,       0, 0, 0, 0)
+#define PINCONF_SDIO_CLK                    PINCONF(PIN_SDIO_CLK,       1, 1, 1, 0)
+#define PINCONF_SDIO_CLK_SDCARD             PINCONF(PIN_SDIO_CLK,       1, 0, 1, 0)
+#define PINCONF_SDIO_CLK_SPI5_SCK           PINCONF(PIN_SDIO_CLK,       2, 0, 0, 0)
+#define PINCONF_SDIO_CMD_GPIO               PINCONF(PIN_SDIO_CMD,       0, 0, 0, 0)
+#define PINCONF_SDIO_CMD                    PINCONF(PIN_SDIO_CMD,       1, 1, 1, 0)
+#define PINCONF_SDIO_CMD_SPI5_CS_X          PINCONF(PIN_SDIO_CMD,       2, 0, 0, 0)
+#define PINCONF_SDIO_DATA0_GPIO             PINCONF(PIN_SDIO_DATA0,     0, 0, 0, 0)
+#define PINCONF_SDIO_DATA0                  PINCONF(PIN_SDIO_DATA0,     1, 1, 1, 0)
+#define PINCONF_SDIO_DATA0_SPI5_MOSI        PINCONF(PIN_SDIO_DATA0,     2, 0, 0, 0)
+#define PINCONF_SDIO_DATA1_GPIO             PINCONF(PIN_SDIO_DATA1,     0, 0, 0, 0)
+#define PINCONF_SDIO_DATA1                  PINCONF(PIN_SDIO_DATA1,     1, 1, 1, 0)
+#define PINCONF_SDIO_DATA1_SPI5_MISO        PINCONF(PIN_SDIO_DATA1,     2, 1, 0, 0)
+#define PINCONF_SDIO_DATA2_GPIO             PINCONF(PIN_SDIO_DATA2,     0, 0, 0, 0)
+#define PINCONF_SDIO_DATA2                  PINCONF(PIN_SDIO_DATA2,     1, 1, 1, 0)
+#define PINCONF_SDIO_DATA2_SPI5_GPIO        PINCONF(PIN_SDIO_DATA2,     2, 0, 0, 0)
+#define PINCONF_SDIO_DATA3_GPIO             PINCONF(PIN_SDIO_DATA3,     0, 0, 0, 0)
+#define PINCONF_SDIO_DATA3                  PINCONF(PIN_SDIO_DATA3,     1, 1, 1, 0)
+#define PINCONF_SDIO_DATA3_SPI5_GPIO        PINCONF(PIN_SDIO_DATA3,     2, 0, 0, 0)
+#define PINCONF_SDIO_CD_GPIO                PINCONF(PIN_SDIO_CD,        0, 0, 0, 0)
+#define PINCONF_SDIO_CD                     PINCONF(PIN_SDIO_CD,        1, 1, 0, 0)
+#define PINCONF_SDIO_WP_GPIO                PINCONF(PIN_SDIO_WP,        0, 0, 0, 0)
+#define PINCONF_SDIO_WP                     PINCONF(PIN_SDIO_WP,        1, 1, 0, 0)
+#define PINCONF_SDIO_CMDDIR_GPIO            PINCONF(PIN_SDIO_CMDDIR,    0, 0, 0, 0)
+#define PINCONF_SDIO_CMDDIR                 PINCONF(PIN_SDIO_CMDDIR,    1, 0, 1, 0)
+#define PINCONF_SDIO_DIR0_GPIO              PINCONF(PIN_SDIO_DIR0,      0, 0, 0, 0)
+#define PINCONF_SDIO_DIR0                   PINCONF(PIN_SDIO_DIR0,      1, 0, 1, 0)
+#define PINCONF_SDIO_DIR1_3_GPIO            PINCONF(PIN_SDIO_DIR1_3,    0, 0, 0, 0)
+#define PINCONF_SDIO_DIR1_3                 PINCONF(PIN_SDIO_DIR1_3,    1, 0, 1, 0)
+#define PINCONF_SDIO_CLKI_GPIO              PINCONF(PIN_SDIO_CLKI,      0, 0, 0, 0)
+#define PINCONF_SDIO_CLKI                   PINCONF(PIN_SDIO_CLKI,      1, 1, 0, 0) /* only for SD Card */
+#endif /* CONFIG_CXD56_FCBGA */
+#define PINCONF_I2S0_BCK_GPIO               PINCONF(PIN_I2S0_BCK,       0, 0, 0, 0)
+#define PINCONF_I2S0_BCK_M_HIGH             PINCONF(PIN_I2S0_BCK,       1, 0, 1, 0)
+#define PINCONF_I2S0_BCK_M_NORM             PINCONF(PIN_I2S0_BCK,       1, 0, 0, 0)
+#define PINCONF_I2S0_BCK_S                  PINCONF(PIN_I2S0_BCK,       1, 1, 0, 0)
+#define PINCONF_I2S0_BCK_APP_MONOUT0        PINCONF(PIN_I2S0_BCK,       2, 0, 0, 0)
+#define PINCONF_I2S0_LRCK_GPIO              PINCONF(PIN_I2S0_LRCK,      0, 0, 0, 0)
+#define PINCONF_I2S0_LRCK_M_HIGH            PINCONF(PIN_I2S0_LRCK,      1, 0, 1, 0)
+#define PINCONF_I2S0_LRCK_M_NORM            PINCONF(PIN_I2S0_LRCK,      1, 0, 0, 0)
+#define PINCONF_I2S0_LRCK_S                 PINCONF(PIN_I2S0_LRCK,      1, 1, 0, 0)
+#define PINCONF_I2S0_LRCK_APP_MONOUT1       PINCONF(PIN_I2S0_LRCK,      2, 0, 0, 0)
+#define PINCONF_I2S0_DATA_IN_GPIO           PINCONF(PIN_I2S0_DATA_IN,   0, 0, 0, 0)
+#define PINCONF_I2S0_DATA_IN                PINCONF(PIN_I2S0_DATA_IN,   1, 1, 0, 0)
+#define PINCONF_I2S0_DATA_IN_APP_MONOUT2    PINCONF(PIN_I2S0_DATA_IN,   2, 0, 0, 0)
+#define PINCONF_I2S0_DATA_OUT_GPIO          PINCONF(PIN_I2S0_DATA_OUT,  0, 0, 0, 0)
+#define PINCONF_I2S0_DATA_OUT_HIGH          PINCONF(PIN_I2S0_DATA_OUT,  1, 0, 1, 0)
+#define PINCONF_I2S0_DATA_OUT_NORM          PINCONF(PIN_I2S0_DATA_OUT,  1, 0, 0, 0)
+#define PINCONF_I2S0_DATA_OUT_APP_MONOUT3   PINCONF(PIN_I2S0_DATA_OUT,  2, 0, 0, 0)
+#ifdef CONFIG_CXD56_FCBGA
+#define PINCONF_I2S1_BCK_GPIO               PINCONF(PIN_I2S1_BCK,       0, 0, 0, 0)
+#define PINCONF_I2S1_BCK_M_HIGH             PINCONF(PIN_I2S1_BCK,       1, 0, 1, 0)
+#define PINCONF_I2S1_BCK_M_NORM             PINCONF(PIN_I2S1_BCK,       1, 0, 0, 0)
+#define PINCONF_I2S1_BCK_S                  PINCONF(PIN_I2S1_BCK,       1, 1, 0, 0)
+#define PINCONF_I2S1_BCK_APP_MONOUT4        PINCONF(PIN_I2S1_BCK,       2, 0, 0, 0)
+#define PINCONF_I2S1_LRCK_GPIO              PINCONF(PIN_I2S1_LRCK,      0, 0, 0, 0)
+#define PINCONF_I2S1_LRCK_M_HIGH            PINCONF(PIN_I2S1_LRCK,      1, 0, 1, 0)
+#define PINCONF_I2S1_LRCK_M_NORM            PINCONF(PIN_I2S1_LRCK,      1, 0, 0, 0)
+#define PINCONF_I2S1_LRCK_S                 PINCONF(PIN_I2S1_LRCK,      1, 1, 0, 0)
+#define PINCONF_I2S1_LRCK_APP_MONOUT5       PINCONF(PIN_I2S1_LRCK,      2, 0, 0, 0)
+#define PINCONF_I2S1_DATA_IN_GPIO           PINCONF(PIN_I2S1_DATA_IN,   0, 0, 0, 0)
+#define PINCONF_I2S1_DATA_IN                PINCONF(PIN_I2S1_DATA_IN,   1, 1, 0, 0)
+#define PINCONF_I2S1_DATA_IN_APP_MONOUT6    PINCONF(PIN_I2S1_DATA_IN,   2, 0, 0, 0)
+#define PINCONF_I2S1_DATA_OUT_GPIO          PINCONF(PIN_I2S1_DATA_OUT,  0, 0, 0, 0)
+#define PINCONF_I2S1_DATA_OUT_HIGH          PINCONF(PIN_I2S1_DATA_OUT,  1, 0, 1, 0)
+#define PINCONF_I2S1_DATA_OUT_NORM          PINCONF(PIN_I2S1_DATA_OUT,  1, 0, 0, 0)
+#define PINCONF_I2S1_DATA_OUT_APP_MONOUT7   PINCONF(PIN_I2S1_DATA_OUT,  2, 0, 0, 0)
+#endif /* CONFIG_CXD56_FCBGA */
+#define PINCONF_MCLK_GPIO                   PINCONF(PIN_MCLK,           0, 0, 0, 0)
+#define PINCONF_MCLK                        PINCONF(PIN_MCLK,           1, 1, 0, 0)
+#define PINCONF_MCLK_APP_MONOUT8            PINCONF(PIN_MCLK,           2, 0, 0, 0)
+#define PINCONF_PDM_CLK_GPIO                PINCONF(PIN_PDM_CLK,        0, 0, 0, 0)
+#define PINCONF_PDM_CLK_HIGH                PINCONF(PIN_PDM_CLK,        1, 0, 1, 0)
+#define PINCONF_PDM_CLK_NORM                PINCONF(PIN_PDM_CLK,        1, 0, 0, 0)
+#define PINCONF_PDM_CLK_APP_MONOUT9         PINCONF(PIN_PDM_CLK,        2, 0, 0, 0)
+#define PINCONF_PDM_IN_GPIO                 PINCONF(PIN_PDM_IN,         0, 0, 0, 0)
+#define PINCONF_PDM_IN                      PINCONF(PIN_PDM_IN,         1, 1, 0, 0)
+#define PINCONF_PDM_OUT_GPIO                PINCONF(PIN_PDM_OUT,        0, 0, 0, 0)
+#define PINCONF_PDM_OUT_HIGH                PINCONF(PIN_PDM_OUT,        1, 0, 1, 0)
+#define PINCONF_PDM_OUT_NORM                PINCONF(PIN_PDM_OUT,        1, 0, 0, 0)
+#define PINCONF_USB_VBUSINT_GPIO            PINCONF(PIN_USB_VBUSINT,    0, 0, 0, 0)
+#define PINCONF_USB_VBUSINT                 PINCONF(PIN_USB_VBUSINT,    1, 1, 0, 0)
+#define PINCONF_USB_VBUSINT_DBG_LOGGERCLK   PINCONF(PIN_USB_VBUSINT,    3, 0, 0, 0)
+
+/* Reference set of multiple pinconfigs
+ *
+ */
+#define PINCONFS_I2C4_GPIO                  { PINCONF_I2C4_BCK_GPIO, PINCONF_I2C4_BDT_GPIO }
+#define PINCONFS_I2C4                       { PINCONF_I2C4_BCK,      PINCONF_I2C4_BDT      }
+#define PINCONFS_PMIC_INT_GPIO              { PINCONF_PMIC_INT_GPIO }
+#define PINCONFS_PMIC_INT                   { PINCONF_PMIC_INT }
+#define PINCONFS_PMIC_INT_OD                { PINCONF_PMIC_INT_OD }
+#ifdef CONFIG_CXD56_FCBGA
+#define PINCONFS_RTC_IRQ_OUT_GPIO           { PINCONF_RTC_IRQ_OUT_GPIO }
+#define PINCONFS_RTC_IRQ_OUT                { PINCONF_RTC_IRQ_OUT }
+#define PINCONFS_RTC_IRQ_OUT_OD             { PINCONF_RTC_IRQ_OUT_OD   }
+#endif /* CONFIG_CXD56_FCBGA */
+#define PINCONFS_AP_CLK_GPIO                { PINCONF_AP_CLK_GPIO }
+#define PINCONFS_AP_CLK                     { PINCONF_AP_CLK }
+#define PINCONFS_AP_CLK_PMU_WDT             { PINCONF_AP_CLK_PMU_WDT }
+#define PINCONFS_AP_CLK_PMU_WDT_OD          { PINCONF_AP_CLK_PMU_WDT_OD }
+#ifdef CONFIG_CXD56_FCBGA
+#define PINCONFS_GNSS_1PPS_OUT_GPIO         { PINCONF_GNSS_1PPS_OUT_GPIO }
+#define PINCONFS_GNSS_1PPS_OUT              { PINCONF_GNSS_1PPS_OUT }
+#define PINCONFS_GNSS_1PPS_OUT_CPU_WDT      { PINCONF_GNSS_1PPS_OUT_CPU_WDT }
+#define PINCONFS_GNSS_1PPS_OUT_CPU_WDT_OD   { PINCONF_GNSS_1PPS_OUT_CPU_WDT_OD }
+#endif /* CONFIG_CXD56_FCBGA */
+#define PINCONFS_SPI0A_GPIO                 { PINCONF_SPI0_CS_X_GPIO, PINCONF_SPI0_SCK_GPIO }
+#ifdef CONFIG_CXD56_FCBGA
+#define PINCONFS_SPI0B_GPIO                 { PINCONF_SPI0_MOSI_GPIO, PINCONF_SPI0_MISO_GPIO }
+#endif /* CONFIG_CXD56_FCBGA */
+#define PINCONFS_SPI0A_UART1                { PINCONF_SPI0_CS_X_UART1_TXD, PINCONF_SPI0_SCK_UART1_RXD }
+#ifdef CONFIG_CXD56_FCBGA
+#define PINCONFS_SPI0B_I2C2                 { PINCONF_SPI0_MOSI_I2C2_BCK,  PINCONF_SPI0_MISO_I2C2_BDT }
+#define PINCONFS_SPI0_GPIO                  { PINCONF_SPI0_CS_X_GPIO, PINCONF_SPI0_SCK_GPIO, \
+                                               PINCONF_SPI0_MOSI_GPIO, PINCONF_SPI0_MISO_GPIO }
+#define PINCONFS_SPI0                       { PINCONF_SPI0_CS_X, PINCONF_SPI0_SCK, \
+                                               PINCONF_SPI0_MOSI, PINCONF_SPI0_MISO }
+#endif /* CONFIG_CXD56_FCBGA */
+#define PINCONFS_SPI1A_GPIO                 { PINCONF_SPI1_CS_X_GPIO, PINCONF_SPI1_SCK_GPIO, \
+                                               PINCONF_SPI1_IO0_GPIO, PINCONF_SPI1_IO1_GPIO }
+#define PINCONFS_SPI1B_GPIO                 { PINCONF_SPI1_IO2_GPIO, PINCONF_SPI1_IO3_GPIO }
+#define PINCONFS_SPI1A_SPI0                 { PINCONF_SPI1_CS_X_SPI0_CS_X, PINCONF_SPI1_SCK_SPI0_SCK, \
+                                               PINCONF_SPI1_IO0_SPI0_MOSI, PINCONF_SPI1_IO1_SPI0_MISO }
+#define PINCONFS_SPI1_GPIO                  { PINCONF_SPI1_CS_X_GPIO, PINCONF_SPI1_SCK_GPIO, PINCONF_SPI1_IO0_GPIO, \
+                                               PINCONF_SPI1_IO1_GPIO, PINCONF_SPI1_IO2_GPIO, PINCONF_SPI1_IO3_GPIO }
+#define PINCONFS_SPI1                       { PINCONF_SPI1_CS_X, PINCONF_SPI1_SCK, PINCONF_SPI1_IO0, \
+                                               PINCONF_SPI1_IO1, PINCONF_SPI1_IO2, PINCONF_SPI1_IO3 }
+#define PINCONFS_SPI2A_GPIO                 { PINCONF_SPI2_CS_X_GPIO, PINCONF_SPI2_SCK_GPIO }
+#define PINCONFS_SPI2B_GPIO                 { PINCONF_SPI2_MOSI_GPIO, PINCONF_SPI2_MISO_GPIO }
+#define PINCONFS_SPI2A_UART0                { PINCONF_SPI2_CS_X_UART0_TXD, PINCONF_SPI2_SCK_UART0_RXD }
+#define PINCONFS_SPI2B_UART0                { PINCONF_SPI2_MOSI_UART0_CTS, PINCONF_SPI2_MISO_UART0_RTS }
+#define PINCONFS_SPI2A_I2C3                 { PINCONF_SPI2_CS_X_I2C3_BCK, PINCONF_SPI2_SCK_I2C3_BDT }
+#define PINCONFS_SPI2_GPIO                  { PINCONF_SPI2_CS_X_GPIO, PINCONF_SPI2_SCK_GPIO, \
+                                               PINCONF_SPI2_MOSI_GPIO, PINCONF_SPI2_MISO_GPIO }
+#define PINCONFS_SPI2                       { PINCONF_SPI2_CS_X, PINCONF_SPI2_SCK, \
+                                               PINCONF_SPI2_MOSI, PINCONF_SPI2_MISO }
+#define PINCONFS_SPI2_UART0                 { PINCONF_SPI2_CS_X_UART0_TXD, PINCONF_SPI2_SCK_UART0_RXD, \
+                                               PINCONF_SPI2_MOSI_UART0_CTS, PINCONF_SPI2_MISO_UART0_RTS }
+#define PINCONFS_HIF_IRQ_OUT_GPIO           { PINCONF_HIF_IRQ_OUT_GPIO }
+#define PINCONFS_HIF_IRQ_OUT                { PINCONF_HIF_IRQ_OUT }
+#define PINCONFS_HIF_IRQ_OUT_OD             { PINCONF_HIF_IRQ_OUT_OD }
+#define PINCONFS_HIF_IRQ_OUT_GNSS_1PPS_OUT  { PINCONF_HIF_IRQ_OUT_GNSS_1PPS_OUT }
+#ifdef CONFIG_CXD56_FCBGA
+#define PINCONFS_HIF_GPIO0_GPIO             { PINCONF_HIF_GPIO0_GPIO }
+#define PINCONFS_HIF_GPIO0_GPS_EXTLD        { PINCONF_HIF_GPIO0_GPS_EXTLD }
+#endif /* CONFIG_CXD56_FCBGA */
+#define PINCONFS_SEN_IRQ_IN_GPIO            { PINCONF_SEN_IRQ_IN_GPIO }
+#define PINCONFS_SEN_IRQ_IN                 { PINCONF_SEN_IRQ_IN }
+#define PINCONFS_SPI3_CS0_X_GPIO            { PINCONF_SPI3_CS0_X_GPIO }
+#define PINCONFS_SPI3_CS0_X                 { PINCONF_SPI3_CS0_X }
+#define PINCONFS_SPI3_CS1_X_GPIO            { PINCONF_SPI3_CS1_X_GPIO }
+#define PINCONFS_SPI3_CS1_X                 { PINCONF_SPI3_CS1_X }
+#define PINCONFS_SPI3_CS2_X_GPIO            { PINCONF_SPI3_CS2_X_GPIO }
+#define PINCONFS_SPI3_CS2_X                 { PINCONF_SPI3_CS2_X }
+#define PINCONFS_SPI3_GPIO                  { PINCONF_SPI3_SCK_GPIO, \
+                                               PINCONF_SPI3_MOSI_GPIO, PINCONF_SPI3_MISO_GPIO }
+#define PINCONFS_SPI3                       { PINCONF_SPI3_SCK, \
+                                               PINCONF_SPI3_MOSI, PINCONF_SPI3_MISO }
+#define PINCONFS_I2C0_GPIO                  { PINCONF_I2C0_BCK_GPIO, PINCONF_I2C0_BDT_GPIO }
+#define PINCONFS_I2C0                       { PINCONF_I2C0_BCK, PINCONF_I2C0_BDT }
+#define PINCONFS_PWMA_GPIO                  { PINCONF_PWM0_GPIO, PINCONF_PWM1_GPIO }
+#define PINCONFS_PWMA                       { PINCONF_PWM0, PINCONF_PWM1 }
+#define PINCONFS_PWMB_GPIO                  { PINCONF_PWM2_GPIO, PINCONF_PWM3_GPIO }
+#define PINCONFS_PWMB                       { PINCONF_PWM2, PINCONF_PWM3 }
+#define PINCONFS_PWMB_I2C1                  { PINCONF_PWM2_I2C1_BCK, PINCONF_PWM3_I2C1_BDT }
+#ifdef CONFIG_CXD56_FCBGA
+#define PINCONFS_IS_GPIO                    { PINCONF_IS_CLK_GPIO, PINCONF_IS_VSYNC_GPIO, PINCONF_IS_HSYNC_GPIO, \
+                                               PINCONF_IS_DATA0_GPIO, PINCONF_IS_DATA1_GPIO, PINCONF_IS_DATA2_GPIO, \
+                                               PINCONF_IS_DATA3_GPIO, PINCONF_IS_DATA4_GPIO, PINCONF_IS_DATA5_GPIO, \
+                                               PINCONF_IS_DATA6_GPIO, PINCONF_IS_DATA7_GPIO }
+#define PINCONFS_IS                         { PINCONF_IS_CLK, PINCONF_IS_VSYNC, PINCONF_IS_HSYNC, \
+                                               PINCONF_IS_DATA0, PINCONF_IS_DATA1, PINCONF_IS_DATA2, \
+                                               PINCONF_IS_DATA3, PINCONF_IS_DATA4, PINCONF_IS_DATA5, \
+                                               PINCONF_IS_DATA6, PINCONF_IS_DATA7 }
+#endif /* CONFIG_CXD56_FCBGA */
+#define PINCONFS_UART2_GPIO                 { PINCONF_UART2_TXD_GPIO, PINCONF_UART2_RXD_GPIO, \
+                                               PINCONF_UART2_CTS_GPIO, PINCONF_UART2_RTS_GPIO }
+#define PINCONFS_UART2                      { PINCONF_UART2_TXD, PINCONF_UART2_RXD, \
+                                               PINCONF_UART2_CTS, PINCONF_UART2_RTS }
+#define PINCONFS_SPI4_GPIO                  { PINCONF_SPI4_CS_X_GPIO, PINCONF_SPI4_SCK_GPIO, \
+                                               PINCONF_SPI4_MOSI_GPIO, PINCONF_SPI4_MISO_GPIO }
+#define PINCONFS_SPI4                       { PINCONF_SPI4_CS_X, PINCONF_SPI4_SCK, \
+                                               PINCONF_SPI4_MOSI, PINCONF_SPI4_MISO }
+#define PINCONFS_EMMCA_GPIO                 { PINCONF_EMMC_CLK_GPIO, PINCONF_EMMC_CMD_GPIO, \
+                                               PINCONF_EMMC_DATA0_GPIO, PINCONF_EMMC_DATA1_GPIO }
+#define PINCONFS_EMMCB_GPIO                 { PINCONF_EMMC_DATA2_GPIO, PINCONF_EMMC_DATA3_GPIO }
+#define PINCONFS_EMMCA_SPI5                 { PINCONF_EMMC_CLK_SPI5_SCK, PINCONF_EMMC_CMD_SPI5_CS_X, \
+                                               PINCONF_EMMC_DATA0_SPI5_MOSI, PINCONF_EMMC_DATA1_SPI5_MISO }
+#define PINCONFS_EMMC_GPIO                  { PINCONF_EMMC_CLK_GPIO, PINCONF_EMMC_CMD_GPIO, \
+                                               PINCONF_EMMC_DATA0_GPIO, PINCONF_EMMC_DATA1_GPIO, \
+                                               PINCONF_EMMC_DATA2_GPIO, PINCONF_EMMC_DATA3_GPIO }
+#define PINCONFS_EMMC                       { PINCONF_EMMC_CLK, PINCONF_EMMC_CMD, \
+                                               PINCONF_EMMC_DATA0, PINCONF_EMMC_DATA1, \
+                                               PINCONF_EMMC_DATA2, PINCONF_EMMC_DATA3 }
+#ifdef CONFIG_CXD56_FCBGA
+#define PINCONFS_SDIOA_GPIO                 { PINCONF_SDIO_CLK_GPIO, PINCONF_SDIO_CMD_GPIO, \
+                                               PINCONF_SDIO_DATA0_GPIO, PINCONF_SDIO_DATA1_GPIO, \
+                                               PINCONF_SDIO_DATA2_GPIO, PINCONF_SDIO_DATA3_GPIO }
+#define PINCONFS_SDIOA_SDIO                 { PINCONF_SDIO_CLK, PINCONF_SDIO_CMD, \
+                                               PINCONF_SDIO_DATA0, PINCONF_SDIO_DATA1, \
+                                               PINCONF_SDIO_DATA2, PINCONF_SDIO_DATA3 }
+#define PINCONFS_SDIOA_SDCARD               { PINCONF_SDIO_CLK_SDCARD, PINCONF_SDIO_CMD, \
+                                               PINCONF_SDIO_DATA0, PINCONF_SDIO_DATA1, \
+                                               PINCONF_SDIO_DATA2, PINCONF_SDIO_DATA3 }
+#define PINCONFS_SDIOA_SPI5                 { PINCONF_SDIO_CLK_SPI5_SCK, PINCONF_SDIO_CMD_SPI5_CS_X, \
+                                               PINCONF_SDIO_DATA0_SPI5_MOSI, PINCONF_SDIO_DATA1_SPI5_MISO, \
+                                               PINCONF_SDIO_DATA2_SPI5_GPIO, PINCONF_SDIO_DATA3_SPI5_GPIO }
+#define PINCONFS_SDIOB_GPIO                 { PINCONF_SDIO_CD_GPIO, PINCONF_SDIO_WP_GPIO }
+#define PINCONFS_SDIOB_SDCARD               { PINCONF_SDIO_CD, PINCONF_SDIO_WP }
+#define PINCONFS_SDIOC_GPIO                 { PINCONF_SDIO_CMDDIR_GPIO, PINCONF_SDIO_DIR0_GPIO, PINCONF_SDIO_DIR1_3_GPIO }
+#define PINCONFS_SDIOC_SDIO                 { PINCONF_SDIO_CMDDIR, PINCONF_SDIO_DIR0, PINCONF_SDIO_DIR1_3 }
+#define PINCONFS_SDIOD_GPIO                 { PINCONF_SDIO_CLKI_GPIO }
+#define PINCONFS_SDIOD_SDIO                 { PINCONF_SDIO_CLKI }
+#endif /* CONFIG_CXD56_FCBGA */
+#define PINCONFS_I2S0_GPIO                  { PINCONF_I2S0_BCK_GPIO, PINCONF_I2S0_LRCK_GPIO, \
+                                               PINCONF_I2S0_DATA_IN_GPIO, PINCONF_I2S0_DATA_OUT_GPIO }
+#define PINCONFS_I2S0_M_HIGH                { PINCONF_I2S0_BCK_M_HIGH, PINCONF_I2S0_LRCK_M_HIGH, \
+                                               PINCONF_I2S0_DATA_IN, PINCONF_I2S0_DATA_OUT_HIGH }
+#define PINCONFS_I2S0_M_NORM                { PINCONF_I2S0_BCK_M_NORM, PINCONF_I2S0_LRCK_M_NORM, \
+                                               PINCONF_I2S0_DATA_IN, PINCONF_I2S0_DATA_OUT_NORM }
+#define PINCONFS_I2S0_S_HIGH                { PINCONF_I2S0_BCK_S, PINCONF_I2S0_LRCK_S, \
+                                               PINCONF_I2S0_DATA_IN, PINCONF_I2S0_DATA_OUT_HIGH }
+#define PINCONFS_I2S0_S_NORM                { PINCONF_I2S0_BCK_S, PINCONF_I2S0_LRCK_S, \
+                                               PINCONF_I2S0_DATA_IN, PINCONF_I2S0_DATA_OUT_NORM }
+#ifdef CONFIG_CXD56_FCBGA
+#define PINCONFS_I2S1_GPIO                  { PINCONF_I2S1_BCK_GPIO, PINCONF_I2S1_LRCK_GPIO, \
+                                               PINCONF_I2S1_DATA_IN_GPIO, PINCONF_I2S1_DATA_OUT_GPIO }
+#define PINCONFS_I2S1_M_HIGH                { PINCONF_I2S1_BCK_M_HIGH, PINCONF_I2S1_LRCK_M_HIGH, \
+                                               PINCONF_I2S1_DATA_IN, PINCONF_I2S1_DATA_OUT_HIGH }
+#define PINCONFS_I2S1_M_NORM                { PINCONF_I2S1_BCK_M_NORM, PINCONF_I2S1_LRCK_M_NORM, \
+                                               PINCONF_I2S1_DATA_IN, PINCONF_I2S1_DATA_OUT_NORM }
+#define PINCONFS_I2S1_S_HIGH                { PINCONF_I2S1_BCK_S, PINCONF_I2S1_LRCK_S, \
+                                               PINCONF_I2S1_DATA_IN, PINCONF_I2S1_DATA_OUT_HIGH }
+#define PINCONFS_I2S1_S_NORM                { PINCONF_I2S1_BCK_S, PINCONF_I2S1_LRCK_S, \
+                                               PINCONF_I2S1_DATA_IN, PINCONF_I2S1_DATA_OUT_NORM }
+#endif /* CONFIG_CXD56_FCBGA */
+#define PINCONFS_MCLK_GPIO                  { PINCONF_MCLK_GPIO }
+#define PINCONFS_MCLK                       { PINCONF_MCLK }
+#define PINCONFS_PDM_GPIO                   { PINCONF_PDM_CLK_GPIO, PINCONF_PDM_IN_GPIO, PINCONF_PDM_OUT_GPIO }
+#define PINCONFS_PDM_HIGH                   { PINCONF_PDM_CLK_HIGH, PINCONF_PDM_IN, PINCONF_PDM_OUT_HIGH }
+#define PINCONFS_PDM_NORM                   { PINCONF_PDM_CLK_NORM, PINCONF_PDM_IN, PINCONF_PDM_OUT_NORM }
+#define PINCONFS_USB_VBUSINT_GPIO           { PINCONF_USB_VBUSINT_GPIO }
+#define PINCONFS_USB_VBUSINT                { PINCONF_USB_VBUSINT }
+
+#ifdef CONFIG_BOARD_CUSTOM_PINCONFIG
+/* Change the pin configuration depending on each board */
+
+#  include 
+
+#endif /* CONFIG_BOARD_CUSTOM_PINCONFIG */
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_PINCONFIG_H */
diff --git a/arch/arm/src/cxd56xx/hardware/cxd5602_topreg.h b/arch/arm/src/cxd56xx/hardware/cxd5602_topreg.h
new file mode 100644
index 00000000000..c66783306b0
--- /dev/null
+++ b/arch/arm/src/cxd56xx/hardware/cxd5602_topreg.h
@@ -0,0 +1,718 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/hardware/cxd5602_topreg.h
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_TOPREG_H
+#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD5602_TOPREG_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include 
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+#define CXD56_TOPREG_PWD_CTL	(CXD56_TOPREG_BASE + 0x0)
+#define CXD56_TOPREG_ANA_PW_CTL	(CXD56_TOPREG_BASE + 0x4)
+#define CXD56_TOPREG_ANA_EN_CTL	(CXD56_TOPREG_BASE + 0x8)
+#define CXD56_TOPREG_SYSCPU_RAMMODE_SEL	(CXD56_TOPREG_BASE + 0x10)
+#define CXD56_TOPREG_TOP_SCU_RAMMODE_SEL	(CXD56_TOPREG_BASE + 0x18)
+#define CXD56_TOPREG_HOSTIFC_RAMMODE_SEL	(CXD56_TOPREG_BASE + 0x1c)
+#define CXD56_TOPREG_PMU_FAST	(CXD56_TOPREG_BASE + 0x20)
+#define CXD56_TOPREG_PMU_PW_CTL	(CXD56_TOPREG_BASE + 0x30)
+#define CXD56_TOPREG_PMU_INT_STAT	(CXD56_TOPREG_BASE + 0x40)
+#define CXD56_TOPREG_PMU_RAW_INT_STAT	(CXD56_TOPREG_BASE + 0x44)
+#define CXD56_TOPREG_PMU_INT_CLR	(CXD56_TOPREG_BASE + 0x48)
+#define CXD56_TOPREG_PMU_INT_MASK	(CXD56_TOPREG_BASE + 0x4c)
+#define CXD56_TOPREG_PWD_RESET0	(CXD56_TOPREG_BASE + 0x60)
+#define CXD56_TOPREG_PMU_DBG	(CXD56_TOPREG_BASE + 0x70)
+#define CXD56_TOPREG_PMU_TIMEOUT_CTL0	(CXD56_TOPREG_BASE + 0x74)
+#define CXD56_TOPREG_PMU_TIMEOUT_CTL1	(CXD56_TOPREG_BASE + 0x78)
+#define CXD56_TOPREG_PMU_TIMEOUT_CTL2	(CXD56_TOPREG_BASE + 0x7c)
+#define CXD56_TOPREG_PMU_FSM	(CXD56_TOPREG_BASE + 0x80)
+#define CXD56_TOPREG_PMU_PW_STAT	(CXD56_TOPREG_BASE + 0x84)
+#define CXD56_TOPREG_PMU_WAIT0	(CXD56_TOPREG_BASE + 0x88)
+#define CXD56_TOPREG_PMU_WAIT1	(CXD56_TOPREG_BASE + 0x8c)
+#define CXD56_TOPREG_PMU_WAIT2	(CXD56_TOPREG_BASE + 0x90)
+#define CXD56_TOPREG_PMU_WAIT3	(CXD56_TOPREG_BASE + 0x94)
+#define CXD56_TOPREG_PMU_WAIT4	(CXD56_TOPREG_BASE + 0x98)
+#define CXD56_TOPREG_PMU_WAIT5	(CXD56_TOPREG_BASE + 0x9c)
+#define CXD56_TOPREG_PMU_WAIT6	(CXD56_TOPREG_BASE + 0xa0)
+#define CXD56_TOPREG_PMU_WAIT7	(CXD56_TOPREG_BASE + 0xa4)
+#define CXD56_TOPREG_PMU_WAIT8	(CXD56_TOPREG_BASE + 0xa8)
+#define CXD56_TOPREG_PMU_WAIT9	(CXD56_TOPREG_BASE + 0xac)
+#define CXD56_TOPREG_PMU_DBG_INITEN	(CXD56_TOPREG_BASE + 0xb0)
+#define CXD56_TOPREG_PMU_DBG_ON_ORDER0	(CXD56_TOPREG_BASE + 0xb4)
+#define CXD56_TOPREG_PMU_DBG_ON_ORDER1	(CXD56_TOPREG_BASE + 0xb8)
+#define CXD56_TOPREG_PMU_DBG_ON_ORDER2	(CXD56_TOPREG_BASE + 0xbc)
+#define CXD56_TOPREG_PMU_DBG_ON_ORDER3	(CXD56_TOPREG_BASE + 0xc0)
+#define CXD56_TOPREG_PMU_DBG_ON_ORDER4	(CXD56_TOPREG_BASE + 0xc4)
+#define CXD56_TOPREG_PMU_DBG_ON_ORDER5	(CXD56_TOPREG_BASE + 0xc8)
+#define CXD56_TOPREG_PMU_DBG_ON_ORDER6	(CXD56_TOPREG_BASE + 0xcc)
+#define CXD56_TOPREG_PMU_DBG_ON_ORDER7	(CXD56_TOPREG_BASE + 0xd0)
+#define CXD56_TOPREG_PMU_DBG_OFF_ORDER0	(CXD56_TOPREG_BASE + 0xd4)
+#define CXD56_TOPREG_PMU_DBG_OFF_ORDER1	(CXD56_TOPREG_BASE + 0xd8)
+#define CXD56_TOPREG_PMU_DBG_OFF_ORDER2	(CXD56_TOPREG_BASE + 0xdc)
+#define CXD56_TOPREG_PMU_DBG_OFF_ORDER3	(CXD56_TOPREG_BASE + 0xe0)
+#define CXD56_TOPREG_PMU_DBG_OFF_ORDER4	(CXD56_TOPREG_BASE + 0xe4)
+#define CXD56_TOPREG_PMU_DBG_OFF_ORDER5	(CXD56_TOPREG_BASE + 0xe8)
+#define CXD56_TOPREG_PMU_DBG_OFF_ORDER6	(CXD56_TOPREG_BASE + 0xec)
+#define CXD56_TOPREG_PMU_DBG_OFF_ORDER7	(CXD56_TOPREG_BASE + 0xf0)
+#define CXD56_TOPREG_PMU_DBG_LUMPEN	(CXD56_TOPREG_BASE + 0xf4)
+#define CXD56_TOPREG_PMU_DBG_ADD	(CXD56_TOPREG_BASE + 0xfc)
+#define CXD56_TOPREG_PMU_DBG_ADD_WAIT0	(CXD56_TOPREG_BASE + 0x100)
+#define CXD56_TOPREG_PMU_DBG_ADD_WAIT1	(CXD56_TOPREG_BASE + 0x104)
+#define CXD56_TOPREG_PWD_STAT	(CXD56_TOPREG_BASE + 0x200)
+#define CXD56_TOPREG_PWD_PGACK_STAT	(CXD56_TOPREG_BASE + 0x204)
+#define CXD56_TOPREG_ANA_PW_STAT	(CXD56_TOPREG_BASE + 0x208)
+#define CXD56_TOPREG_SYSCPU_RAMMODE_STAT	(CXD56_TOPREG_BASE + 0x20c)
+#define CXD56_TOPREG_TOP_SCU_RAMMODE_STAT	(CXD56_TOPREG_BASE + 0x214)
+#define CXD56_TOPREG_HOSTIFC_RAMMODE_STAT	(CXD56_TOPREG_BASE + 0x218)
+#define CXD56_TOPREG_PMU_HW_STAT	(CXD56_TOPREG_BASE + 0x21c)
+#define CXD56_TOPREG_YOBI2_0	(CXD56_TOPREG_BASE + 0x230)
+#define CXD56_TOPREG_ANA_PW_CTL_SEL_WAKE	(CXD56_TOPREG_BASE + 0x400)
+#define CXD56_TOPREG_SYSCPU_RAMMODE_SEL_WAKE	(CXD56_TOPREG_BASE + 0x404)
+#define CXD56_TOPREG_TOP_SCU_RAMMODE_SEL_WAKE	(CXD56_TOPREG_BASE + 0x410)
+#define CXD56_TOPREG_CLSELDIV_WAKE	(CXD56_TOPREG_BASE + 0x414)
+#define CXD56_TOPREG_CKDIV_CPU_DSP_BUS_WAKE	(CXD56_TOPREG_BASE + 0x418)
+#define CXD56_TOPREG_CKSEL_ROOT_WAKE	(CXD56_TOPREG_BASE + 0x41c)
+#define CXD56_TOPREG_PMIC_SLEEP_I2C0	(CXD56_TOPREG_BASE + 0x420)
+#define CXD56_TOPREG_PMIC_SLEEP_I2C1	(CXD56_TOPREG_BASE + 0x424)
+#define CXD56_TOPREG_PMIC_SLEEP_I2C2	(CXD56_TOPREG_BASE + 0x428)
+#define CXD56_TOPREG_PMIC_SLEEP_I2C3	(CXD56_TOPREG_BASE + 0x42c)
+#define CXD56_TOPREG_PMIC_WAKE_I2C0	(CXD56_TOPREG_BASE + 0x430)
+#define CXD56_TOPREG_PMIC_WAKE_I2C1	(CXD56_TOPREG_BASE + 0x434)
+#define CXD56_TOPREG_PMIC_WAKE_I2C2	(CXD56_TOPREG_BASE + 0x438)
+#define CXD56_TOPREG_PMIC_WAKE_I2C3	(CXD56_TOPREG_BASE + 0x43c)
+#define CXD56_TOPREG_PMIC_UNEXP_I2C0	(CXD56_TOPREG_BASE + 0x440)
+#define CXD56_TOPREG_PMIC_UNEXP_I2C1	(CXD56_TOPREG_BASE + 0x444)
+#define CXD56_TOPREG_PMIC_UNEXP_I2C2	(CXD56_TOPREG_BASE + 0x448)
+#define CXD56_TOPREG_PMIC_UNEXP_I2C3	(CXD56_TOPREG_BASE + 0x44c)
+#define CXD56_TOPREG_PMIC_UNEXP_I2C	(CXD56_TOPREG_BASE + 0x450)
+#define CXD56_TOPREG_PMU_WAKE_TRIG_EN0	(CXD56_TOPREG_BASE + 0x454)
+#define CXD56_TOPREG_PMU_WAKE_TRIG_EN1	(CXD56_TOPREG_BASE + 0x458)
+#define CXD56_TOPREG_PMU_WAKE_TRIG_NEGEN0	(CXD56_TOPREG_BASE + 0x45c)
+#define CXD56_TOPREG_PMU_WAKE_TRIG_NEGEN1	(CXD56_TOPREG_BASE + 0x460)
+#define CXD56_TOPREG_PMU_WAKE_TRIG_NOISECUTEN0	(CXD56_TOPREG_BASE + 0x464)
+#define CXD56_TOPREG_PMU_WAKE_TRIG_CPUINTSEL0	(CXD56_TOPREG_BASE + 0x468)
+#define CXD56_TOPREG_PMU_WAKE_TRIG_CPUINTSEL1	(CXD56_TOPREG_BASE + 0x46c)
+#define CXD56_TOPREG_PMU_WAKE_TRIG_CPUINTSEL2	(CXD56_TOPREG_BASE + 0x470)
+#define CXD56_TOPREG_PMU_WAKE_TRIG_INTDET0	(CXD56_TOPREG_BASE + 0x474)
+#define CXD56_TOPREG_PMU_WAKE_TRIG_INTDET1	(CXD56_TOPREG_BASE + 0x478)
+#define CXD56_TOPREG_PMU_WAKE_TRIG_INTDET2	(CXD56_TOPREG_BASE + 0x47c)
+#define CXD56_TOPREG_PMU_WAKE_PMIC_I2C	(CXD56_TOPREG_BASE + 0x480)
+#define CXD56_TOPREG_BOOT_CAUSE	(CXD56_TOPREG_BASE + 0x484)
+#define CXD56_TOPREG_PMU_CORE_CKEN	(CXD56_TOPREG_BASE + 0x4c0)
+#define CXD56_TOPREG_CKSEL_ROOT	(CXD56_TOPREG_BASE + 0x4c4)
+#define CXD56_TOPREG_CKSEL_PMU	(CXD56_TOPREG_BASE + 0x4c8)
+#define CXD56_TOPREG_CKSEL_SYSIOP	(CXD56_TOPREG_BASE + 0x4cc)
+#define CXD56_TOPREG_CKSEL_SYSIOP_SUB	(CXD56_TOPREG_BASE + 0x4d0)
+#define CXD56_TOPREG_CKSEL_SCU	(CXD56_TOPREG_BASE + 0x4d4)
+#define CXD56_TOPREG_CKDIV_CPU_DSP_BUS	(CXD56_TOPREG_BASE + 0x4d8)
+#define CXD56_TOPREG_CKDIV_COM	(CXD56_TOPREG_BASE + 0x4dc)
+#define CXD56_TOPREG_CKDIV_HOSTIFC	(CXD56_TOPREG_BASE + 0x4e0)
+#define CXD56_TOPREG_CKDIV_SCU	(CXD56_TOPREG_BASE + 0x4e4)
+#define CXD56_TOPREG_CKDIV_PMU	(CXD56_TOPREG_BASE + 0x4e8)
+#define CXD56_TOPREG_CRG_INT_CLR0	(CXD56_TOPREG_BASE + 0x4ec)
+#define CXD56_TOPREG_CRG_INT_MASK0	(CXD56_TOPREG_BASE + 0x4f0)
+#define CXD56_TOPREG_CRG_INT_STAT_MSK0	(CXD56_TOPREG_BASE + 0x4f4)
+#define CXD56_TOPREG_CRG_INT_STAT_RAW0	(CXD56_TOPREG_BASE + 0x4f8)
+#define CXD56_TOPREG_CRG_INT_CLR1	(CXD56_TOPREG_BASE + 0x4fc)
+#define CXD56_TOPREG_CRG_INT_MASK1	(CXD56_TOPREG_BASE + 0x500)
+#define CXD56_TOPREG_CRG_INT_STAT_MSK1	(CXD56_TOPREG_BASE + 0x504)
+#define CXD56_TOPREG_CRG_INT_STAT_RAW1	(CXD56_TOPREG_BASE + 0x508)
+#define CXD56_TOPREG_CPU_GATECLK	(CXD56_TOPREG_BASE + 0x50c)
+#define CXD56_TOPREG_USBPHY_CKEN	(CXD56_TOPREG_BASE + 0x510)
+#define CXD56_TOPREG_CRG_MON	(CXD56_TOPREG_BASE + 0x514)
+#define CXD56_TOPREG_GEAR_STAT	(CXD56_TOPREG_BASE + 0x518)
+#define CXD56_TOPREG_XOSC_CTRL	(CXD56_TOPREG_BASE + 0x580)
+#define CXD56_TOPREG_XOSC_CTRL2	(CXD56_TOPREG_BASE + 0x584)
+#define CXD56_TOPREG_SYS_PLL_CTRL1	(CXD56_TOPREG_BASE + 0x588)
+#define CXD56_TOPREG_SYS_PLL_CTRL2	(CXD56_TOPREG_BASE + 0x58c)
+#define CXD56_TOPREG_RCOSC_CTRL1	(CXD56_TOPREG_BASE + 0x590)
+#define CXD56_TOPREG_RCOSC_CTRL2	(CXD56_TOPREG_BASE + 0x594)
+#define CXD56_TOPREG_RF_GPMBI_EN	(CXD56_TOPREG_BASE + 0x598)
+#define CXD56_TOPREG_BUSPROT_SDMAC	(CXD56_TOPREG_BASE + 0x5c0)
+#define CXD56_TOPREG_BUSPROT_HDMAC	(CXD56_TOPREG_BASE + 0x5c4)
+#define CXD56_TOPREG_BUSPROT_SYDMAC	(CXD56_TOPREG_BASE + 0x5c8)
+#define CXD56_TOPREG_BUSPROT_SYSUBDMAC	(CXD56_TOPREG_BASE + 0x5cc)
+#define CXD56_TOPREG_BUSPROT_SAKE	(CXD56_TOPREG_BASE + 0x5d0)
+#define CXD56_TOPREG_BUSPROT_KAKI	(CXD56_TOPREG_BASE + 0x5d4)
+#define CXD56_TOPREG_BUSPROT_BKUPSRAM	(CXD56_TOPREG_BASE + 0x5d8)
+#define CXD56_TOPREG_BUSPROT_SPIFLAIF	(CXD56_TOPREG_BASE + 0x5dc)
+#define CXD56_TOPREG_BUSPROT_TOPREG_0	(CXD56_TOPREG_BASE + 0x5e0)
+#define CXD56_TOPREG_BUSPROT_TOPREG_1	(CXD56_TOPREG_BASE + 0x5e4)
+#define CXD56_TOPREG_BUSPROT_TOPREG_2	(CXD56_TOPREG_BASE + 0x5e8)
+#define CXD56_TOPREG_BUSPROT_TOPREG_3	(CXD56_TOPREG_BASE + 0x5ec)
+#define CXD56_TOPREG_BUSPROT_TOPREG_4	(CXD56_TOPREG_BASE + 0x5f0)
+#define CXD56_TOPREG_GPIO_PROT_0	(CXD56_TOPREG_BASE + 0x5f4)
+#define CXD56_TOPREG_GPIO_PROT_1	(CXD56_TOPREG_BASE + 0x5f8)
+#define CXD56_TOPREG_GPIO_PROT_2	(CXD56_TOPREG_BASE + 0x5fc)
+#define CXD56_TOPREG_GPIO_PROT_3	(CXD56_TOPREG_BASE + 0x600)
+#define CXD56_TOPREG_BUSPROT_CHECKER	(CXD56_TOPREG_BASE + 0x610)
+#define CXD56_TOPREG_WDT_SRST_EN	(CXD56_TOPREG_BASE + 0x640)
+#define CXD56_TOPREG_FORCE_CKEN	(CXD56_TOPREG_BASE + 0x644)
+#define CXD56_TOPREG_SDEBUG_PASS_BYPASS	(CXD56_TOPREG_BASE + 0x648)
+#define CXD56_TOPREG_SDEBUG_CTRL	(CXD56_TOPREG_BASE + 0x64c)
+#define CXD56_TOPREG_DBG_HOSTIF_SEL	(CXD56_TOPREG_BASE + 0x650)
+#define CXD56_TOPREG_WDT_MASK	(CXD56_TOPREG_BASE + 0x654)
+#define CXD56_TOPREG_CKGATE_CTL	(CXD56_TOPREG_BASE + 0x660)
+#define CXD56_TOPREG_M0_BOOT_MODE	(CXD56_TOPREG_BASE + 0x680)
+#define CXD56_TOPREG_M0_BOOT_MODE_EN	(CXD56_TOPREG_BASE + 0x684)
+#define CXD56_TOPREG_M0_BOOT_ENTRY_POINT	(CXD56_TOPREG_BASE + 0x688)
+#define CXD56_TOPREG_M0_BOOT_MODE_EXT	(CXD56_TOPREG_BASE + 0x690)
+#define CXD56_TOPREG_M0_BOOT_REC	(CXD56_TOPREG_BASE + 0x694)
+#define CXD56_TOPREG_I2CRPT_SADR	(CXD56_TOPREG_BASE + 0x6c0)
+#define CXD56_TOPREG_I2CRPT_REP	(CXD56_TOPREG_BASE + 0x6c4)
+#define CXD56_TOPREG_PMIC_I2C	(CXD56_TOPREG_BASE + 0x6d0)
+#define CXD56_TOPREG_RAMMODE	(CXD56_TOPREG_BASE + 0x6e4)
+#define CXD56_TOPREG_SWRESET_BUS	(CXD56_TOPREG_BASE + 0x700)
+#define CXD56_TOPREG_SWRESET_SCU	(CXD56_TOPREG_BASE + 0x704)
+#define CXD56_TOPREG_BUSROM_CKEN	(CXD56_TOPREG_BASE + 0x710)
+#define CXD56_TOPREG_SYSIOP_CKEN	(CXD56_TOPREG_BASE + 0x714)
+#define CXD56_TOPREG_SCU_CKEN	(CXD56_TOPREG_BASE + 0x71c)
+#define CXD56_TOPREG_RTC0_CTL	(CXD56_TOPREG_BASE + 0x730)
+#define CXD56_TOPREG_FUSERDCFG0	(CXD56_TOPREG_BASE + 0x740)
+#define CXD56_TOPREG_FUSERDCFG1	(CXD56_TOPREG_BASE + 0x744)
+#define CXD56_TOPREG_FUSERDCFG2	(CXD56_TOPREG_BASE + 0x748)
+#define CXD56_TOPREG_VID0	(CXD56_TOPREG_BASE + 0x750)
+#define CXD56_TOPREG_VID1	(CXD56_TOPREG_BASE + 0x754)
+#define CXD56_TOPREG_M0_BOOT_FLASH_DIS	(CXD56_TOPREG_BASE + 0x758)
+#define CXD56_TOPREG_LDOADJ0	(CXD56_TOPREG_BASE + 0x760)
+#define CXD56_TOPREG_LDOADJ1	(CXD56_TOPREG_BASE + 0x764)
+#define CXD56_TOPREG_FQFIX_CTL0	(CXD56_TOPREG_BASE + 0x770)
+#define CXD56_TOPREG_FQFIX_AUTO	(CXD56_TOPREG_BASE + 0x774)
+#define CXD56_TOPREG_FQFIX_SINGLE	(CXD56_TOPREG_BASE + 0x778)
+#define CXD56_TOPREG_FQFIX_STATUS	(CXD56_TOPREG_BASE + 0x77c)
+#define CXD56_TOPREG_SYSTEM_CONFIG	(CXD56_TOPREG_BASE + 0x790)
+#define CXD56_TOPREG_MON_SEL	(CXD56_TOPREG_BASE + 0x7a0)
+#define CXD56_TOPREG_IOCSYS_MONSEL0	(CXD56_TOPREG_BASE + 0x7a4)
+#define CXD56_TOPREG_IOCSYS_MONSEL1	(CXD56_TOPREG_BASE + 0x7a8)
+#define CXD56_TOPREG_IOCSYS_INTSEL0	(CXD56_TOPREG_BASE + 0x7b0)
+#define CXD56_TOPREG_IOCSYS_INTSEL1	(CXD56_TOPREG_BASE + 0x7b4)
+#define CXD56_TOPREG_IOCSYS_IOMD0	(CXD56_TOPREG_BASE + 0x7c0)
+#define CXD56_TOPREG_IOCSYS_IOMD1	(CXD56_TOPREG_BASE + 0x7c4)
+#define CXD56_TOPREG_IOOEN_SYS	(CXD56_TOPREG_BASE + 0x7e0)
+#define CXD56_TOPREG_IO_RTC_CLK_IN	(CXD56_TOPREG_BASE + 0x800)
+#define CXD56_TOPREG_IO_I2C4_BCK	(CXD56_TOPREG_BASE + 0x804)
+#define CXD56_TOPREG_IO_I2C4_BDT	(CXD56_TOPREG_BASE + 0x808)
+#define CXD56_TOPREG_IO_PMIC_INT	(CXD56_TOPREG_BASE + 0x80c)
+#define CXD56_TOPREG_IO_RTC_IRQ_OUT	(CXD56_TOPREG_BASE + 0x810)
+#define CXD56_TOPREG_IO_AP_CLK	(CXD56_TOPREG_BASE + 0x814)
+#define CXD56_TOPREG_IO_GNSS_1PPS_OUT	(CXD56_TOPREG_BASE + 0x818)
+#define CXD56_TOPREG_IO_SPI0_CS_X	(CXD56_TOPREG_BASE + 0x844)
+#define CXD56_TOPREG_IO_SPI0_SCK	(CXD56_TOPREG_BASE + 0x848)
+#define CXD56_TOPREG_IO_SPI0_MOSI	(CXD56_TOPREG_BASE + 0x84c)
+#define CXD56_TOPREG_IO_SPI0_MISO	(CXD56_TOPREG_BASE + 0x850)
+#define CXD56_TOPREG_IO_SPI1_CS_X	(CXD56_TOPREG_BASE + 0x854)
+#define CXD56_TOPREG_IO_SPI1_SCK	(CXD56_TOPREG_BASE + 0x858)
+#define CXD56_TOPREG_IO_SPI1_IO0	(CXD56_TOPREG_BASE + 0x85c)
+#define CXD56_TOPREG_IO_SPI1_IO1	(CXD56_TOPREG_BASE + 0x860)
+#define CXD56_TOPREG_IO_SPI1_IO2	(CXD56_TOPREG_BASE + 0x864)
+#define CXD56_TOPREG_IO_SPI1_IO3	(CXD56_TOPREG_BASE + 0x868)
+#define CXD56_TOPREG_IO_SPI2_CS_X	(CXD56_TOPREG_BASE + 0x86c)
+#define CXD56_TOPREG_IO_SPI2_SCK	(CXD56_TOPREG_BASE + 0x870)
+#define CXD56_TOPREG_IO_SPI2_MOSI	(CXD56_TOPREG_BASE + 0x874)
+#define CXD56_TOPREG_IO_SPI2_MISO	(CXD56_TOPREG_BASE + 0x878)
+#define CXD56_TOPREG_IO_HIF_IRQ_OUT	(CXD56_TOPREG_BASE + 0x87c)
+#define CXD56_TOPREG_IO_HIF_GPIO0	(CXD56_TOPREG_BASE + 0x880)
+#define CXD56_TOPREG_IO_SEN_IRQ_IN	(CXD56_TOPREG_BASE + 0x894)
+#define CXD56_TOPREG_IO_SPI3_CS0_X	(CXD56_TOPREG_BASE + 0x898)
+#define CXD56_TOPREG_IO_SPI3_CS1_X	(CXD56_TOPREG_BASE + 0x89c)
+#define CXD56_TOPREG_IO_SPI3_CS2_X	(CXD56_TOPREG_BASE + 0x8a0)
+#define CXD56_TOPREG_IO_SPI3_SCK	(CXD56_TOPREG_BASE + 0x8a4)
+#define CXD56_TOPREG_IO_SPI3_MOSI	(CXD56_TOPREG_BASE + 0x8a8)
+#define CXD56_TOPREG_IO_SPI3_MISO	(CXD56_TOPREG_BASE + 0x8ac)
+#define CXD56_TOPREG_IO_I2C0_BCK	(CXD56_TOPREG_BASE + 0x8b0)
+#define CXD56_TOPREG_IO_I2C0_BDT	(CXD56_TOPREG_BASE + 0x8b4)
+#define CXD56_TOPREG_IO_PWM0	(CXD56_TOPREG_BASE + 0x8b8)
+#define CXD56_TOPREG_IO_PWM1	(CXD56_TOPREG_BASE + 0x8bc)
+#define CXD56_TOPREG_IO_PWM2	(CXD56_TOPREG_BASE + 0x8c0)
+#define CXD56_TOPREG_IO_PWM3	(CXD56_TOPREG_BASE + 0x8c4)
+#define CXD56_TOPREG_IO_DBG_SWOCLK	(CXD56_TOPREG_BASE + 0x8d4)
+#define CXD56_TOPREG_IO_DBG_SWO	(CXD56_TOPREG_BASE + 0x8d8)
+#define CXD56_TOPREG_IO_IS_CLK	(CXD56_TOPREG_BASE + 0x8e0)
+#define CXD56_TOPREG_IO_IS_VSYNC	(CXD56_TOPREG_BASE + 0x8e4)
+#define CXD56_TOPREG_IO_IS_HSYNC	(CXD56_TOPREG_BASE + 0x8e8)
+#define CXD56_TOPREG_IO_IS_DATA0	(CXD56_TOPREG_BASE + 0x8ec)
+#define CXD56_TOPREG_IO_IS_DATA1	(CXD56_TOPREG_BASE + 0x8f0)
+#define CXD56_TOPREG_IO_IS_DATA2	(CXD56_TOPREG_BASE + 0x8f4)
+#define CXD56_TOPREG_IO_IS_DATA3	(CXD56_TOPREG_BASE + 0x8f8)
+#define CXD56_TOPREG_IO_IS_DATA4	(CXD56_TOPREG_BASE + 0x8fc)
+#define CXD56_TOPREG_IO_IS_DATA5	(CXD56_TOPREG_BASE + 0x900)
+#define CXD56_TOPREG_IO_IS_DATA6	(CXD56_TOPREG_BASE + 0x904)
+#define CXD56_TOPREG_IO_IS_DATA7	(CXD56_TOPREG_BASE + 0x908)
+#define CXD56_TOPREG_IO_UART2_TXD	(CXD56_TOPREG_BASE + 0x90c)
+#define CXD56_TOPREG_IO_UART2_RXD	(CXD56_TOPREG_BASE + 0x910)
+#define CXD56_TOPREG_IO_UART2_CTS	(CXD56_TOPREG_BASE + 0x914)
+#define CXD56_TOPREG_IO_UART2_RTS	(CXD56_TOPREG_BASE + 0x918)
+#define CXD56_TOPREG_IO_SPI4_CS_X	(CXD56_TOPREG_BASE + 0x91c)
+#define CXD56_TOPREG_IO_SPI4_SCK	(CXD56_TOPREG_BASE + 0x920)
+#define CXD56_TOPREG_IO_SPI4_MOSI	(CXD56_TOPREG_BASE + 0x924)
+#define CXD56_TOPREG_IO_SPI4_MISO	(CXD56_TOPREG_BASE + 0x928)
+#define CXD56_TOPREG_IO_EMMC_CLK	(CXD56_TOPREG_BASE + 0x92c)
+#define CXD56_TOPREG_IO_EMMC_CMD	(CXD56_TOPREG_BASE + 0x930)
+#define CXD56_TOPREG_IO_EMMC_DATA0	(CXD56_TOPREG_BASE + 0x934)
+#define CXD56_TOPREG_IO_EMMC_DATA1	(CXD56_TOPREG_BASE + 0x938)
+#define CXD56_TOPREG_IO_EMMC_DATA2	(CXD56_TOPREG_BASE + 0x93c)
+#define CXD56_TOPREG_IO_EMMC_DATA3	(CXD56_TOPREG_BASE + 0x940)
+#define CXD56_TOPREG_IO_SDIO_CLK	(CXD56_TOPREG_BASE + 0x944)
+#define CXD56_TOPREG_IO_SDIO_CMD	(CXD56_TOPREG_BASE + 0x948)
+#define CXD56_TOPREG_IO_SDIO_DATA0	(CXD56_TOPREG_BASE + 0x94c)
+#define CXD56_TOPREG_IO_SDIO_DATA1	(CXD56_TOPREG_BASE + 0x950)
+#define CXD56_TOPREG_IO_SDIO_DATA2	(CXD56_TOPREG_BASE + 0x954)
+#define CXD56_TOPREG_IO_SDIO_DATA3	(CXD56_TOPREG_BASE + 0x958)
+#define CXD56_TOPREG_IO_SDIO_CD	(CXD56_TOPREG_BASE + 0x95c)
+#define CXD56_TOPREG_IO_SDIO_WP	(CXD56_TOPREG_BASE + 0x960)
+#define CXD56_TOPREG_IO_SDIO_CMDDIR	(CXD56_TOPREG_BASE + 0x964)
+#define CXD56_TOPREG_IO_SDIO_DIR0	(CXD56_TOPREG_BASE + 0x968)
+#define CXD56_TOPREG_IO_SDIO_DIR1_3	(CXD56_TOPREG_BASE + 0x96c)
+#define CXD56_TOPREG_IO_SDIO_CLKI	(CXD56_TOPREG_BASE + 0x970)
+#define CXD56_TOPREG_IO_I2S0_BCK	(CXD56_TOPREG_BASE + 0x974)
+#define CXD56_TOPREG_IO_I2S0_LRCK	(CXD56_TOPREG_BASE + 0x978)
+#define CXD56_TOPREG_IO_I2S0_DATA_IN	(CXD56_TOPREG_BASE + 0x97c)
+#define CXD56_TOPREG_IO_I2S0_DATA_OUT	(CXD56_TOPREG_BASE + 0x980)
+#define CXD56_TOPREG_IO_I2S1_BCK	(CXD56_TOPREG_BASE + 0x984)
+#define CXD56_TOPREG_IO_I2S1_LRCK	(CXD56_TOPREG_BASE + 0x988)
+#define CXD56_TOPREG_IO_I2S1_DATA_IN	(CXD56_TOPREG_BASE + 0x98c)
+#define CXD56_TOPREG_IO_I2S1_DATA_OUT	(CXD56_TOPREG_BASE + 0x990)
+#define CXD56_TOPREG_IO_MCLK	(CXD56_TOPREG_BASE + 0x994)
+#define CXD56_TOPREG_IO_PDM_CLK	(CXD56_TOPREG_BASE + 0x998)
+#define CXD56_TOPREG_IO_PDM_IN	(CXD56_TOPREG_BASE + 0x99c)
+#define CXD56_TOPREG_IO_PDM_OUT	(CXD56_TOPREG_BASE + 0x9a0)
+#define CXD56_TOPREG_IO_USB_VBUSINT	(CXD56_TOPREG_BASE + 0x9a4)
+#define CXD56_TOPREG_FUSEWRST	(CXD56_TOPREG_BASE + 0xa00)
+#define CXD56_TOPREG_FUSEWRAD	(CXD56_TOPREG_BASE + 0xa04)
+#define CXD56_TOPREG_FUSEWRDT	(CXD56_TOPREG_BASE + 0xa08)
+#define CXD56_TOPREG_FUSEWRPG	(CXD56_TOPREG_BASE + 0xa0c)
+#define CXD56_TOPREG_YOBI2_1	(CXD56_TOPREG_BASE + 0xb00)
+#define CXD56_TOPREG_GNSSDSP_RAMMODE_SEL	(CXD56_TOPREG_BASE + 0xc00)
+#define CXD56_TOPREG_CKSEL_GNSS_BB	(CXD56_TOPREG_BASE + 0xc04)
+#define CXD56_TOPREG_CKDIV_ITP	(CXD56_TOPREG_BASE + 0xc0c)
+#define CXD56_TOPREG_GNS_ITP_CKEN	(CXD56_TOPREG_BASE + 0xc10)
+#define CXD56_TOPREG_RF_CTRL	(CXD56_TOPREG_BASE + 0xc20)
+#define CXD56_TOPREG_GDSP_BOOT_ENTRY_POINT	(CXD56_TOPREG_BASE + 0xc30)
+#define CXD56_TOPREG_GNSSDSP_RAMMODE_STAT	(CXD56_TOPREG_BASE + 0xc40)
+#define CXD56_TOPREG_LOGGERIF	(CXD56_TOPREG_BASE + 0xc50)
+#define CXD56_TOPREG_YOBI2_2	(CXD56_TOPREG_BASE + 0xc60)
+#define CXD56_TOPREG_ADSP1_BOOT_ENTRY_POINT	(CXD56_TOPREG_BASE + 0x1010)
+#define CXD56_TOPREG_ADSP2_BOOT_ENTRY_POINT	(CXD56_TOPREG_BASE + 0x1014)
+#define CXD56_TOPREG_ADSP3_BOOT_ENTRY_POINT	(CXD56_TOPREG_BASE + 0x1018)
+#define CXD56_TOPREG_ADSP4_BOOT_ENTRY_POINT	(CXD56_TOPREG_BASE + 0x101c)
+#define CXD56_TOPREG_ADSP5_BOOT_ENTRY_POINT	(CXD56_TOPREG_BASE + 0x1020)
+#define CXD56_TOPREG_YOBI2_3	(CXD56_TOPREG_BASE + 0x1040)
+#define CXD56_TOPREG_ADSP0_BOOT_ENTRY_POINT	(CXD56_TOPREG_BASE + 0x1400)
+#define CXD56_TOPREG_USB_VBUS	(CXD56_TOPREG_BASE + 0x1410)
+#define CXD56_TOPREG_FUSERD00	(CXD56_TOPREG_BASE + 0x1420)
+#define CXD56_TOPREG_FUSERD01	(CXD56_TOPREG_BASE + 0x1424)
+#define CXD56_TOPREG_FUSERD02	(CXD56_TOPREG_BASE + 0x1428)
+#define CXD56_TOPREG_FUSERD03	(CXD56_TOPREG_BASE + 0x142c)
+#define CXD56_TOPREG_FUSERD04	(CXD56_TOPREG_BASE + 0x1430)
+#define CXD56_TOPREG_FUSERD05	(CXD56_TOPREG_BASE + 0x1434)
+#define CXD56_TOPREG_FUSERD06	(CXD56_TOPREG_BASE + 0x1438)
+#define CXD56_TOPREG_FUSERD07	(CXD56_TOPREG_BASE + 0x143c)
+#define CXD56_TOPREG_FUSERD08	(CXD56_TOPREG_BASE + 0x1440)
+#define CXD56_TOPREG_FUSERD09	(CXD56_TOPREG_BASE + 0x1444)
+#define CXD56_TOPREG_FUSERD10	(CXD56_TOPREG_BASE + 0x1448)
+#define CXD56_TOPREG_FUSERD11	(CXD56_TOPREG_BASE + 0x144c)
+#define CXD56_TOPREG_FUSERD12	(CXD56_TOPREG_BASE + 0x1450)
+#define CXD56_TOPREG_FUSERD13	(CXD56_TOPREG_BASE + 0x1454)
+#define CXD56_TOPREG_FUSERD14	(CXD56_TOPREG_BASE + 0x1458)
+#define CXD56_TOPREG_FUSERD15	(CXD56_TOPREG_BASE + 0x145c)
+#define CXD56_TOPREG_AUDIO_IF_SEL	(CXD56_TOPREG_BASE + 0x1470)
+#define CXD56_TOPREG_IOOEN_APP	(CXD56_TOPREG_BASE + 0x1474)
+#define CXD56_TOPREG_IOFIX_APP	(CXD56_TOPREG_BASE + 0x1478)
+#define CXD56_TOPREG_IOCAPP_MONSEL0	(CXD56_TOPREG_BASE + 0x1480)
+#define CXD56_TOPREG_IOCAPP_MONSEL1	(CXD56_TOPREG_BASE + 0x1484)
+#define CXD56_TOPREG_IOCAPP_INTSEL0	(CXD56_TOPREG_BASE + 0x1490)
+#define CXD56_TOPREG_IOCAPP_INTSEL1	(CXD56_TOPREG_BASE + 0x1494)
+#define CXD56_TOPREG_IOCAPP_IOMD	(CXD56_TOPREG_BASE + 0x14a0)
+#define CXD56_TOPREG_YOBI2_4	(CXD56_TOPREG_BASE + 0x14c0)
+#define CXD56_TOPREG_GP_I2C4_BCK	(CXD56_TOPREG_BASE + 0x2000)
+#define CXD56_TOPREG_GP_I2C4_BDT	(CXD56_TOPREG_BASE + 0x2004)
+#define CXD56_TOPREG_GP_PMIC_INT	(CXD56_TOPREG_BASE + 0x2008)
+#define CXD56_TOPREG_GP_RTC_IRQ_OUT	(CXD56_TOPREG_BASE + 0x200c)
+#define CXD56_TOPREG_GP_AP_CLK	(CXD56_TOPREG_BASE + 0x2010)
+#define CXD56_TOPREG_GP_GNSS_1PPS_OUT	(CXD56_TOPREG_BASE + 0x2014)
+#define CXD56_TOPREG_GP_SPI0_CS_X	(CXD56_TOPREG_BASE + 0x2040)
+#define CXD56_TOPREG_GP_SPI0_SCK	(CXD56_TOPREG_BASE + 0x2044)
+#define CXD56_TOPREG_GP_SPI0_MOSI	(CXD56_TOPREG_BASE + 0x2048)
+#define CXD56_TOPREG_GP_SPI0_MISO	(CXD56_TOPREG_BASE + 0x204c)
+#define CXD56_TOPREG_GP_SPI1_CS_X	(CXD56_TOPREG_BASE + 0x2050)
+#define CXD56_TOPREG_GP_SPI1_SCK	(CXD56_TOPREG_BASE + 0x2054)
+#define CXD56_TOPREG_GP_SPI1_IO0	(CXD56_TOPREG_BASE + 0x2058)
+#define CXD56_TOPREG_GP_SPI1_IO1	(CXD56_TOPREG_BASE + 0x205c)
+#define CXD56_TOPREG_GP_SPI1_IO2	(CXD56_TOPREG_BASE + 0x2060)
+#define CXD56_TOPREG_GP_SPI1_IO3	(CXD56_TOPREG_BASE + 0x2064)
+#define CXD56_TOPREG_GP_SPI2_CS_X	(CXD56_TOPREG_BASE + 0x2068)
+#define CXD56_TOPREG_GP_SPI2_SCK	(CXD56_TOPREG_BASE + 0x206c)
+#define CXD56_TOPREG_GP_SPI2_MOSI	(CXD56_TOPREG_BASE + 0x2070)
+#define CXD56_TOPREG_GP_SPI2_MISO	(CXD56_TOPREG_BASE + 0x2074)
+#define CXD56_TOPREG_GP_HIF_IRQ_OUT	(CXD56_TOPREG_BASE + 0x2078)
+#define CXD56_TOPREG_GP_HIF_GPIO0	(CXD56_TOPREG_BASE + 0x207c)
+#define CXD56_TOPREG_GP_SEN_IRQ_IN	(CXD56_TOPREG_BASE + 0x2090)
+#define CXD56_TOPREG_GP_SPI3_CS0_X	(CXD56_TOPREG_BASE + 0x2094)
+#define CXD56_TOPREG_GP_SPI3_CS1_X	(CXD56_TOPREG_BASE + 0x2098)
+#define CXD56_TOPREG_GP_SPI3_CS2_X	(CXD56_TOPREG_BASE + 0x209c)
+#define CXD56_TOPREG_GP_SPI3_SCK	(CXD56_TOPREG_BASE + 0x20a0)
+#define CXD56_TOPREG_GP_SPI3_MOSI	(CXD56_TOPREG_BASE + 0x20a4)
+#define CXD56_TOPREG_GP_SPI3_MISO	(CXD56_TOPREG_BASE + 0x20a8)
+#define CXD56_TOPREG_GP_I2C0_BCK	(CXD56_TOPREG_BASE + 0x20ac)
+#define CXD56_TOPREG_GP_I2C0_BDT	(CXD56_TOPREG_BASE + 0x20b0)
+#define CXD56_TOPREG_GP_PWM0	(CXD56_TOPREG_BASE + 0x20b4)
+#define CXD56_TOPREG_GP_PWM1	(CXD56_TOPREG_BASE + 0x20b8)
+#define CXD56_TOPREG_GP_PWM2	(CXD56_TOPREG_BASE + 0x20bc)
+#define CXD56_TOPREG_GP_PWM3	(CXD56_TOPREG_BASE + 0x20c0)
+#define CXD56_TOPREG_GP_IS_CLK	(CXD56_TOPREG_BASE + 0x20c4)
+#define CXD56_TOPREG_GP_IS_VSYNC	(CXD56_TOPREG_BASE + 0x20c8)
+#define CXD56_TOPREG_GP_IS_HSYNC	(CXD56_TOPREG_BASE + 0x20cc)
+#define CXD56_TOPREG_GP_IS_DATA0	(CXD56_TOPREG_BASE + 0x20d0)
+#define CXD56_TOPREG_GP_IS_DATA1	(CXD56_TOPREG_BASE + 0x20d4)
+#define CXD56_TOPREG_GP_IS_DATA2	(CXD56_TOPREG_BASE + 0x20d8)
+#define CXD56_TOPREG_GP_IS_DATA3	(CXD56_TOPREG_BASE + 0x20dc)
+#define CXD56_TOPREG_GP_IS_DATA4	(CXD56_TOPREG_BASE + 0x20e0)
+#define CXD56_TOPREG_GP_IS_DATA5	(CXD56_TOPREG_BASE + 0x20e4)
+#define CXD56_TOPREG_GP_IS_DATA6	(CXD56_TOPREG_BASE + 0x20e8)
+#define CXD56_TOPREG_GP_IS_DATA7	(CXD56_TOPREG_BASE + 0x20ec)
+#define CXD56_TOPREG_GP_UART2_TXD	(CXD56_TOPREG_BASE + 0x20f0)
+#define CXD56_TOPREG_GP_UART2_RXD	(CXD56_TOPREG_BASE + 0x20f4)
+#define CXD56_TOPREG_GP_UART2_CTS	(CXD56_TOPREG_BASE + 0x20f8)
+#define CXD56_TOPREG_GP_UART2_RTS	(CXD56_TOPREG_BASE + 0x20fc)
+#define CXD56_TOPREG_GP_SPI4_CS_X	(CXD56_TOPREG_BASE + 0x2100)
+#define CXD56_TOPREG_GP_SPI4_SCK	(CXD56_TOPREG_BASE + 0x2104)
+#define CXD56_TOPREG_GP_SPI4_MOSI	(CXD56_TOPREG_BASE + 0x2108)
+#define CXD56_TOPREG_GP_SPI4_MISO	(CXD56_TOPREG_BASE + 0x210c)
+#define CXD56_TOPREG_GP_EMMC_CLK	(CXD56_TOPREG_BASE + 0x2110)
+#define CXD56_TOPREG_GP_EMMC_CMD	(CXD56_TOPREG_BASE + 0x2114)
+#define CXD56_TOPREG_GP_EMMC_DATA0	(CXD56_TOPREG_BASE + 0x2118)
+#define CXD56_TOPREG_GP_EMMC_DATA1	(CXD56_TOPREG_BASE + 0x211c)
+#define CXD56_TOPREG_GP_EMMC_DATA2	(CXD56_TOPREG_BASE + 0x2120)
+#define CXD56_TOPREG_GP_EMMC_DATA3	(CXD56_TOPREG_BASE + 0x2124)
+#define CXD56_TOPREG_GP_SDIO_CLK	(CXD56_TOPREG_BASE + 0x2128)
+#define CXD56_TOPREG_GP_SDIO_CMD	(CXD56_TOPREG_BASE + 0x212c)
+#define CXD56_TOPREG_GP_SDIO_DATA0	(CXD56_TOPREG_BASE + 0x2130)
+#define CXD56_TOPREG_GP_SDIO_DATA1	(CXD56_TOPREG_BASE + 0x2134)
+#define CXD56_TOPREG_GP_SDIO_DATA2	(CXD56_TOPREG_BASE + 0x2138)
+#define CXD56_TOPREG_GP_SDIO_DATA3	(CXD56_TOPREG_BASE + 0x213c)
+#define CXD56_TOPREG_GP_SDIO_CD	(CXD56_TOPREG_BASE + 0x2140)
+#define CXD56_TOPREG_GP_SDIO_WP	(CXD56_TOPREG_BASE + 0x2144)
+#define CXD56_TOPREG_GP_SDIO_CMDDIR	(CXD56_TOPREG_BASE + 0x2148)
+#define CXD56_TOPREG_GP_SDIO_DIR0	(CXD56_TOPREG_BASE + 0x214c)
+#define CXD56_TOPREG_GP_SDIO_DIR1_3	(CXD56_TOPREG_BASE + 0x2150)
+#define CXD56_TOPREG_GP_SDIO_CLKI	(CXD56_TOPREG_BASE + 0x2154)
+#define CXD56_TOPREG_GP_I2S0_BCK	(CXD56_TOPREG_BASE + 0x2158)
+#define CXD56_TOPREG_GP_I2S0_LRCK	(CXD56_TOPREG_BASE + 0x215c)
+#define CXD56_TOPREG_GP_I2S0_DATA_IN	(CXD56_TOPREG_BASE + 0x2160)
+#define CXD56_TOPREG_GP_I2S0_DATA_OUT	(CXD56_TOPREG_BASE + 0x2164)
+#define CXD56_TOPREG_GP_I2S1_BCK	(CXD56_TOPREG_BASE + 0x2168)
+#define CXD56_TOPREG_GP_I2S1_LRCK	(CXD56_TOPREG_BASE + 0x216c)
+#define CXD56_TOPREG_GP_I2S1_DATA_IN	(CXD56_TOPREG_BASE + 0x2170)
+#define CXD56_TOPREG_GP_I2S1_DATA_OUT	(CXD56_TOPREG_BASE + 0x2174)
+#define CXD56_TOPREG_GP_MCLK	(CXD56_TOPREG_BASE + 0x2178)
+#define CXD56_TOPREG_GP_PDM_CLK	(CXD56_TOPREG_BASE + 0x217c)
+#define CXD56_TOPREG_GP_PDM_IN	(CXD56_TOPREG_BASE + 0x2180)
+#define CXD56_TOPREG_GP_PDM_OUT	(CXD56_TOPREG_BASE + 0x2184)
+#define CXD56_TOPREG_GP_USB_VBUSINT	(CXD56_TOPREG_BASE + 0x2188)
+#define CXD56_TOPREG_YOBI3	(CXD56_TOPREG_BASE + 0x21fc)
+
+/* Topreg sub */
+#define CXD56_TOPREG_PSW_CHECK	        (CXD56_TOPREG_SUB_BASE + 0x0000)
+#define CXD56_TOPREG_UNEXP_PSW_DIG	    (CXD56_TOPREG_SUB_BASE + 0x0004)
+#define CXD56_TOPREG_UNEXP_PSW_ANA	    (CXD56_TOPREG_SUB_BASE + 0x0008)
+#define CXD56_TOPREG_UNEXP_OTHER	    (CXD56_TOPREG_SUB_BASE + 0x000c)
+#define CXD56_TOPREG_UNEXP_CLR	        (CXD56_TOPREG_SUB_BASE + 0x0010)
+#define CXD56_TOPREG_PMU_WAIT10	        (CXD56_TOPREG_SUB_BASE + 0x0020)
+#define CXD56_TOPREG_PMU_WAIT11	        (CXD56_TOPREG_SUB_BASE + 0x0024)
+#if 0
+#define CXD56_TOPREG_PMU_DBG_INITEN	    (CXD56_TOPREG_SUB_BASE + 0x0030)
+#define CXD56_TOPREG_PMU_DBG_LUMPEN	    (CXD56_TOPREG_SUB_BASE + 0x0034)
+#endif
+#define CXD56_TOPREG_SWRESET_DBG	    (CXD56_TOPREG_SUB_BASE + 0x0400)
+#define CXD56_TOPREG_SWRESET_GNSDSP	    (CXD56_TOPREG_SUB_BASE + 0x0404)
+#define CXD56_TOPREG_SWRESET_APP	    (CXD56_TOPREG_SUB_BASE + 0x0408)
+#define CXD56_TOPREG_SYSCPU_CKEN	    (CXD56_TOPREG_SUB_BASE + 0x0410)
+#define CXD56_TOPREG_APP_CKEN	        (CXD56_TOPREG_SUB_BASE + 0x0414)
+#define CXD56_TOPREG_APP_CKSEL	        (CXD56_TOPREG_SUB_BASE + 0x0418)
+#define CXD56_TOPREG_APP_DIV	        (CXD56_TOPREG_SUB_BASE + 0x041c)
+#define CXD56_TOPREG_SYSIOP_SUB_CKEN	(CXD56_TOPREG_SUB_BASE + 0x0420)
+#define CXD56_TOPREG_ROSC_MON	        (CXD56_TOPREG_SUB_BASE + 0x0428)
+#define CXD56_TOPREG_TDC_MON	        (CXD56_TOPREG_SUB_BASE + 0x042c)
+#define CXD56_TOPREG_PMU_WAKE_TRIG0_CLR	(CXD56_TOPREG_SUB_BASE + 0x0430)
+#define CXD56_TOPREG_PMU_WAKE_TRIG1_CLR	(CXD56_TOPREG_SUB_BASE + 0x0434)
+#define CXD56_TOPREG_PMU_WAKE_TRIG0_RAW	(CXD56_TOPREG_SUB_BASE + 0x0438)
+#define CXD56_TOPREG_PMU_WAKE_TRIG1_RAW	(CXD56_TOPREG_SUB_BASE + 0x043c)
+#define CXD56_TOPREG_PMU_WAKE_TRIG0	    (CXD56_TOPREG_SUB_BASE + 0x0440)
+#define CXD56_TOPREG_PMU_WAKE_TRIG1	    (CXD56_TOPREG_SUB_BASE + 0x0444)
+#define CXD56_TOPREG_RTC1_CTL	        (CXD56_TOPREG_SUB_BASE + 0x0470)
+#define CXD56_TOPREG_GNSS_RAMMODE_SEL	(CXD56_TOPREG_SUB_BASE + 0x0c00)
+#define CXD56_TOPREG_SWRESET_GNSDSP2	(CXD56_TOPREG_SUB_BASE + 0x0c10)
+#define CXD56_TOPREG_SWRESET_BB	        (CXD56_TOPREG_SUB_BASE + 0x0c14)
+#define CXD56_TOPREG_GNSDSP_CKEN	    (CXD56_TOPREG_SUB_BASE + 0x0c20)
+#define CXD56_TOPREG_GNSS_BB_CKEN	    (CXD56_TOPREG_SUB_BASE + 0x0c24)
+#define CXD56_TOPREG_GNSS_DIV           (CXD56_TOPREG_SUB_BASE + 0x0c28)
+#define CXD56_TOPREG_GNSS_RAMMODE_STAT	(CXD56_TOPREG_SUB_BASE + 0x0c30)
+#define CXD56_TOPREG_APPDSP_RAMMODE_SEL0 (CXD56_TOPREG_SUB_BASE + 0x1400)
+#define CXD56_TOPREG_APPDSP_RAMMODE_SEL1 (CXD56_TOPREG_SUB_BASE + 0x1404)
+#define CXD56_TOPREG_APPDSP_RAMMODE_STAT0 (CXD56_TOPREG_SUB_BASE + 0x1420)
+#define CXD56_TOPREG_APPDSP_RAMMODE_STAT1 (CXD56_TOPREG_SUB_BASE + 0x1424)
+#define CXD56_TOPREG_BUSERR0            (CXD56_TOPREG_SUB_BASE + 0x1470)
+#define CXD56_TOPREG_BUSERR1            (CXD56_TOPREG_SUB_BASE + 0x1474)
+#define CXD56_TOPREG_BUSERR2            (CXD56_TOPREG_SUB_BASE + 0x1478)
+#define CXD56_TOPREG_CHIP_ID            (CXD56_TOPREG_SUB_BASE + 0x1490)
+#define CXD56_TOPREG_CUID0              (CXD56_TOPREG_SUB_BASE + 0x1494)
+#define CXD56_TOPREG_CUID1              (CXD56_TOPREG_SUB_BASE + 0x1498)
+#define CXD56_TOPREG_UDID0              (CXD56_TOPREG_SUB_BASE + 0x149c)
+#define CXD56_TOPREG_UDID1              (CXD56_TOPREG_SUB_BASE + 0x14a0)
+#define CXD56_TOPREG_FUSE_STATUS        (CXD56_TOPREG_SUB_BASE + 0x14a4)
+#define CXD56_TOPREG_SDBG_ENB           (CXD56_TOPREG_SUB_BASE + 0x14a8)
+#define CXD56_TOPREG_DBG_MONSEL         (CXD56_TOPREG_SUB_BASE + 0x14c0)
+
+/* PWD_CTL, PWD_STAT */
+
+#define PWD_APP_AUDIO  (1u<<14)
+#define PWD_GNSS       (1u<<13)
+#define PWD_GNSS_ITP   (1u<<12)
+#define PWD_APP_SUB    (1u<<10)
+#define PWD_APP_DSP    (1u<<9)
+#define PWD_APP        (1u<<8)
+#define PWD_SYSIOP_SUB (1u<<6)
+#define PWD_SYSIOP     (1u<<5)
+#define PWD_CORE       (1u<<4)
+#define PWD_SCU        (1u<<0)
+
+/* ANA_PW_CTL */
+
+#define ANA_PW_LPADC  (1u<<13)
+#define ANA_PW_HPADC  (1u<<12)
+#define ANA_PW_RF_PLL (1u<<9)
+#define ANA_PW_RF_LO  (1u<<8)
+#define ANA_PW_RF_ADC (1u<<7)
+#define ANA_PW_RF_IF  (1u<<6)
+#define ANA_PW_RF_MIX (1u<<5)
+#define ANA_PW_RF_LNA (1u<<4)
+#define ANA_PW_SYSPLL (1u<<2)
+#define ANA_PW_XOSC   (1u<<1)
+#define ANA_PW_RCOSC  (1u<<0)
+
+/* ANA_EN_CTL */
+
+#define ON_GP_MBI_EN_SET (1u<<27)
+#define OFF_GP_MBI_EN_CLR (1u<<26)
+#define ON_XO_OSC_EN_SET (1u<<25)
+#define OFF_XO_OSC_EN_CLR (1u<<24)
+#define ON_XO_OSCOUT_EN_SET (1u<<20)
+#define OFF_XO_OSCOUT_EN_CLR (1u<<19)
+#define ON_XO_EXT_EN_SET (1u<<18)
+#define OFF_XO_EXT_EN_CLR (1u<<17)
+#define OFF_XO_CLK_EN_CLR (1u<<16)
+#define ON_SP_ENPLL_SET (1u<<8)
+#define OFF_SP_ENCLK_CLR (1u<<7)
+#define ON_SP_ENOTHER_SET (1u<<6)
+#define OFF_SP_ENOTHER_CLR (1u<<5)
+#define OFF_SP_ENPLL_CLR (1u<<4)
+#define ON_RO_XEN_CLR (1u<<2)
+#define OFF_RO_XEN_SET (1u<<1)
+#define OFF_RO_CLK_XEN_SET (1u<<0)
+
+/* PMU_INT_STAT */
+
+#define PMU_INT_BOOTEN (1u<<4)
+#define PMU_INT_UNEXP_I2C_PMIC (1u<<3)
+#define PMU_INT_UNEXP_TIMEOUT  (1u<<2)
+#define PMU_INT_NOGO           (1u<<1)
+#define PMU_INT_DONE           (1u<<0)
+
+/* CKSEL_ROOT */
+
+#define STATUS_RTC_MASK (3u<<30)
+#define STATUS_RTC_SEL  (2u<<30)
+#define ENABLE_RF_PLL1 (1u<<4)
+#define ENABLE_SOURCE_SEL (1u<<16)
+
+/* CRG_INT_CLR0 */
+
+#define CRG_CK_PCLK_UART0    (1u<<0)
+#define CRG_CK_UART0         (1u<<1)
+#define CRG_CK_BRG_HOST      (1u<<2)
+#define CRG_CK_PCLK_HOSTIFC  (1u<<3)
+#define CRG_CK_HOSTIFC_SEQ   (1u<<4)
+#define CRG_CK_I2CS          (1u<<5)
+#define CRG_CK_RTC_ORG       (1u<<6)
+#define CRG_CK_SYSIOP_RTC    (1u<<7)
+#define CRG_CK_BRG_SCU       (1u<<8)
+#define CRG_CK_SCU           (1u<<9)
+#define CRG_CK_SCU_SPI       (1u<<10)
+#define CRG_CK_SCU_I2C0      (1u<<11)
+#define CRG_CK_SCU_I2C1      (1u<<12)
+#define CRG_CK_SCU_SEQ       (1u<<13)
+#define CRG_CK_SCU_SC        (1u<<14)
+#define CRG_CK_32K           (1u<<15)
+#define CRG_CK_U32KH         (1u<<16)
+#define CRG_CK_U32KL         (1u<<17)
+#define CRG_CK_TADC          (1u<<18)
+#define CRG_CK_RTC_PCLK      (1u<<19)
+#define CRG_CK_PMU_RTC_PCLK  (1u<<20)
+#define CRG_CK_APP           (1u<<21)
+
+/* CRG_INT_CLR1 */
+
+#define CRG_CK_CPU_BUS       (1u<<0)
+#define CRG_CK_CPU_BUS_TO    (1u<<1)
+#define CRG_CK_RFPLL1        (1u<<2)
+#define CRG_CK_RFPLL1_TO     (1u<<3)
+#define CRG_CK_RTC_PRE       (1u<<4)
+#define CRG_CK_RTC_PRE_TO    (1u<<5)
+#define CRG_CK_APP_PRE       (1u<<6)
+#define CRG_CK_APP_PRE_TO    (1u<<7)
+#define CRG_CK_SEL_SP        (1u<<8)
+#define CRG_CK_SEL_SP_TO     (1u<<9)
+#define CRG_CK_SEL_RO_RTC    (1u<<10)
+#define CRG_FREQFIX_ERR      (1u<<11)
+
+/* SYS_PLL_CTRL1 */
+
+#define ENABLE_DSPCLK (1u<<3)
+#define ENABLE_GPADCLK (1u<<1)
+
+/* RCOSC_CTRL2 */
+
+#define DISABLE_SENSCLK (1u<<14)
+#define DISABLE_LOGICLK (1u<<13)
+
+/* SWRESET_BUS */
+
+#define XRST_PMU_I2CM     (1u<<16)
+#define XRST_I2CM         (1u<<11)
+#define XRST_UART0        (1u<<10)
+#define XRST_HOSTIFC_ISOP (1u<<9)
+#define XRST_HOSTIFC      (1u<<8)
+#define XRST_KAKI         (1u<<6)
+#define XRST_UART1        (1u<<5)
+#define XRST_SAKE         (1u<<2)
+#define XRST_SFC          (1u<<1)
+#define XRST_SPIM         (1u<<0)
+
+/* SWRESET_SCU */
+
+#define XRST_SCU_SPI      (1u<<8)
+#define XRST_SCU_ISOP     (1u<<7)
+#define XRST_SCU_I2C1     (1u<<6)
+#define XRST_SCU_I2C2     (1u<<5)
+#define XRST_SCU_LPADC    (1u<<4)
+#define XRST_SCU_HPADC    (1u<<2)
+
+/* SYSIOP_CKEN */
+
+#define CKEN_HOSSPI        (1u<<17)
+#define CKEN_HOSI2C        (1u<<16)
+#define CKEN_HOSTIFC_SEQ   (1u<<15)
+#define CKEN_BRG_SCU       (1u<<14)
+#define CKEN_SYSIOP_RTC    (1u<<13)
+#define CKEN_RCOSC_OUT     (1u<<12)
+#define CKEN_AP_CLK        (1u<<11)
+#define CKEN_RTC_ORG       (1u<<10)
+#define CKEN_FREQDIS       (1u<<9)
+#define CKEN_APB           (1u<<8)
+#define CKEN_AHB_DMAC2     (1u<<7)
+#define CKEN_AHB_DMAC1     (1u<<6)
+#define CKEN_AHB_DMAC0     (1u<<5)
+#define CKEN_BRG_HOST      (1u<<4)
+#define CKEN_I2CS          (1u<<3)
+#define CKEN_PCLK_HOSTIFC  (1u<<2)
+#define CKEN_PCLK_UART0    (1u<<1)
+#define CKEN_UART0         (1u<<0)
+
+/* IOOEN_APP */
+
+#define I2S1_LRCK (1u<<5)
+#define I2S1_BCK (1u<<4)
+#define I2S0_LRCK (1u<<1)
+#define I2S0_BCK (1u<<0)
+
+/* SYSIOP_SUB_CKEN */
+
+#define CK_COM_UART_PCLK (1u<<16)
+#define CK_SFC_HCLK_LOW  (1u<<9)
+#define CK_SFC_SFCLK     (1u<<8)
+#define CK_SFC_HCLK      (1u<<7)
+#define CK_SFC           (CK_SFC_HCLK | CK_SFC_SFCLK | CK_SFC_HCLK_LOW)
+#define CK_HCLK_SAKE     (1u<<6)
+#define CK_I2CM          (1u<<5)
+#define CK_SPIM          (1u<<4)
+#define CK_UART1         (1u<<3)
+#define CK_AHB_DMAC3     (1u<<2)
+#define CK_COM_BRG       (1u<<1)
+#define CK_AHB_BRG_COMIF (1u<<0)
+
+/* PWD_CTL */
+
+#define PWD_CTL_APP_SUB  (1u<<10)
+
+/* SCU_CKEN */
+
+#define SCU_SCU          (1u<<0)
+#define SCU_I2C0         (1u<<1)
+#define SCU_I2C1         (1u<<2)
+#define SCU_SPI          (1u<<3)
+#define SCU_SEQ          (1u<<4)
+#define SCU_32K          (1u<<5)
+#define SCU_U32KL        (1u<<6)
+#define SCU_U32KH        (1u<<7)
+#define SCU_SC           (1u<<8)
+
+/* APP_CKEN */
+
+#define APP_CKEN_CPU     (1u<<0)
+#define APP_CKEN_MCLK    (1u<<1)
+#define APP_CKEN_AHB     (1u<<3)
+
+/* APP_CKSEL */
+
+#define AUD_MCLK_MASK    (3u<<16)
+#define AUD_MCLK_EXT     (0u<<16) /* External XTAL */
+#define AUD_MCLK_XOSC    (1u<<16) /* Internal XOSC */
+#define AUD_MCLK_RCOSC   (2u<<16) /* Internal RCOSC */
+
+/* GNSDSP_CKEN */
+
+#define GNSDSP_CKEN_P1   (1u<<5)
+#define GNSDSP_CKEN_COP  (1u<<7)
+
+#endif
diff --git a/arch/arm/src/cxd56xx/hardware/cxd56_cpufifo.h b/arch/arm/src/cxd56xx/hardware/cxd56_cpufifo.h
new file mode 100644
index 00000000000..d6c496821bc
--- /dev/null
+++ b/arch/arm/src/cxd56xx/hardware/cxd56_cpufifo.h
@@ -0,0 +1,58 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/hardware/cxd56_cpufifo.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_CPUFIFO_H
+#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_CPUFIFO_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+#define CXD56_FIF_PUSH_FULL    (CXD56_CPUFIFO_BASE + 0x00)
+#define CXD56_FIF_PUSH_WRD0    (CXD56_CPUFIFO_BASE + 0x04)
+#define CXD56_FIF_PUSH_WRD1    (CXD56_CPUFIFO_BASE + 0x08)
+#define CXD56_FIF_PUSH_CMP     (CXD56_CPUFIFO_BASE + 0x0c)
+#define CXD56_FIF_PULL_EMP     (CXD56_CPUFIFO_BASE + 0x10)
+#define CXD56_FIF_PULL_WRD0    (CXD56_CPUFIFO_BASE + 0x14)
+#define CXD56_FIF_PULL_WRD1    (CXD56_CPUFIFO_BASE + 0x18)
+#define CXD56_FIF_PULL_CMP     (CXD56_CPUFIFO_BASE + 0x1c)
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_CPUFIFO_H */
diff --git a/arch/arm/src/cxd56xx/hardware/cxd56_crg.h b/arch/arm/src/cxd56xx/hardware/cxd56_crg.h
new file mode 100644
index 00000000000..52f6eb0eae4
--- /dev/null
+++ b/arch/arm/src/cxd56xx/hardware/cxd56_crg.h
@@ -0,0 +1,89 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/hardware/cxd56_crg.h
+ *
+ *   Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_CRG_H
+#define __ARCH_ARM_SRC_CXD56XX_CHIP_CXD56_CRG_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include 
+#include "chip.h"
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+#define CXD56_CRG_GEAR_AHB              (CXD56_CRG_BASE + 0x0000)
+#define CXD56_CRG_GEAR_IMG_UART         (CXD56_CRG_BASE + 0x0004)
+#define CXD56_CRG_GEAR_IMG_SPI          (CXD56_CRG_BASE + 0x0008)
+#define CXD56_CRG_GEAR_PER_SDIO         (CXD56_CRG_BASE + 0x000c)
+#define CXD56_CRG_GEAR_PER_USB          (CXD56_CRG_BASE + 0x0010)
+#define CXD56_CRG_GEAR_M_IMG_VENB       (CXD56_CRG_BASE + 0x0014)
+#define CXD56_CRG_GEAR_N_IMG_VENB       (CXD56_CRG_BASE + 0x0018)
+#define CXD56_CRG_GEAR_IMG_WSPI         (CXD56_CRG_BASE + 0x001c)
+#define CXD56_CRG_CKEN_EMMC             (CXD56_CRG_BASE + 0x0020)
+
+#define CXD56_CRG_RESET                 (CXD56_CRG_BASE + 0x0030)
+
+#define CXD56_CRG_CK_GATE_AHB           (CXD56_CRG_BASE + 0x0040)
+
+#define CXD56_CRG_CK_MON_EN             (CXD56_CRG_BASE + 0x0050)
+
+#define CXD56_CRG_APP_TILE_CLK_GATING_ENB  (CXD56_ADSP_BASE + 0x02001084)
+
+/* RESET register bits **********************************************************************/
+
+#define XRS_AUD     (1<<0)
+#define XRS_IMG     (1<<4)
+#define XRS_USB     (1<<8)
+#define XRS_SDIO    (1<<9)
+#define XRS_MMC     (1<<10)
+#define XRS_MMC_CRG (1<<11)
+#define XRS_DSP_GEN (1<<22)
+
+/* CK_GATE_AHB register bits ****************************************************************/
+
+#define CK_GATE_AUD  (1<<0)
+#define CK_GATE_IMG  (1<<4)
+#define CK_GATE_USB  (1<<8)
+#define CK_GATE_SDIO (1<<9)
+#define CK_GATE_MMC  (1<<10)
+
+#endif
diff --git a/arch/arm/src/cxd56xx/hardware/cxd56_uart.h b/arch/arm/src/cxd56xx/hardware/cxd56_uart.h
new file mode 100644
index 00000000000..5d272b6b5d4
--- /dev/null
+++ b/arch/arm/src/cxd56xx/hardware/cxd56_uart.h
@@ -0,0 +1,134 @@
+/****************************************************************************
+ * arch/arm/src/cxd56xx/hardware/cxd56_uart.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_UART_H
+#define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_UART_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+/* Common Register Offsets */
+
+#define CXD56_UART_DR       0x000    /* Data register */
+#define CXD56_UART_RSR_ECR  0x004    /* Recieve status/error clear register */
+#define CXD56_UART_FR       0x018    /* Flag register */
+#define CXD56_UART_ILPR     0x020    /* IrDA low-power counter register */
+#define CXD56_UART_IBRD     0x024    /* Integer baud rate register */
+#define CXD56_UART_FBRD     0x028    /* Fractional baud rate register */
+#define CXD56_UART_LCR_H    0x02c    /* Line control register */
+#define CXD56_UART_CR       0x030    /* Control register */
+#define CXD56_UART_IFLS     0x034    /* Interrupt FIFO level select register */
+#define CXD56_UART_IMSC     0x038    /* Interrupt mask set/clear register */
+#define CXD56_UART_RIS      0x03c    /* Raw Interrupt status register */
+#define CXD56_UART_MIS      0x040    /* Masked interrupt status register */
+#define CXD56_UART_ICR      0x044    /* Interrupt clear register */
+#define CXD56_UART_DMACR    0x048    /* DMA control register */
+
+#define  UART_FR_RI         (0x1 << 8)
+#define  UART_FR_TXFE       (0x1 << 7)
+#define  UART_FR_RXFF       (0x1 << 6)
+#define  UART_FR_TXFF       (0x1 << 5)
+#define  UART_FR_RXFE       (0x1 << 4)
+#define  UART_FR_BUSY       (0x1 << 3)
+#define  UART_FR_DCD        (0x1 << 2)
+#define  UART_FR_DSR        (0x1 << 1)
+#define  UART_FR_CTS        (0x1 << 0)
+
+#define UART_LCR_SPS        (1u << 7)
+#define UART_LCR_WLEN(x)    ((((x)-5)&3)<<5)
+#define UART_LCR_FEN        (1u << 4)
+#define UART_LCR_STP2       (1u << 3)
+#define UART_LCR_EPS        (1u << 2)
+#define UART_LCR_PEN        (1u << 1)
+#define UART_LCR_BRK        (1u << 0)
+
+#define UART_CR_CTSEN       (1u << 15)
+#define UART_CR_RTSEN       (1u << 14)
+#define UART_CR_OUT2        (1u << 13)
+#define UART_CR_OUT1        (1u << 12)
+#define UART_CR_RTS         (1u << 11)
+#define UART_CR_DTR         (1u << 10)
+#define UART_CR_RXE         (1u << 9)
+#define UART_CR_TXE         (1u << 8)
+#define UART_CR_LBE         (1u << 7)
+#define UART_CR_SIRLP       (1u << 2)
+#define UART_CR_SIREN       (1u << 1)
+#define UART_CR_EN          (1u << 0)
+
+#define UART_INTR_RI        (1u << 0)  /* nUARTRI modem interrupt */
+#define UART_INTR_CTS       (1u << 1)  /* nUARTCTS modem interrupt */
+#define UART_INTR_DCD       (1u << 2)  /* nUARTDCD modem interrupt */
+#define UART_INTR_DSR       (1u << 3)  /* nUARTDSR modem interrupt */
+#define UART_INTR_RX        (1u << 4)  /* Receive interrupt */
+#define UART_INTR_TX        (1u << 5)  /* Transmit interrupt */
+#define UART_INTR_RT        (1u << 6)  /* Receive timeout interrupt */
+#define UART_INTR_FE        (1u << 7)  /* Framing error interrupt */
+#define UART_INTR_PE        (1u << 8)  /* Parity error interrupt */
+#define UART_INTR_BE        (1u << 9)  /* Break error interrupt */
+#define UART_INTR_OE        (1u << 10) /* Overrun error interrupt */
+#define UART_INTR_ALL       (0x7ff)  /* All of interrupts */
+
+#define UART_FLAG_RI        (1u << 8)  /* Ring indicator */
+#define UART_FLAG_TXFE      (1u << 7)  /* Transmit FIFO empty */
+#define UART_FLAG_RXFF      (1u << 6)  /* Receive FIFO full */
+#define UART_FLAG_TXFF      (1u << 5)  /* Transmit FIFO full */
+#define UART_FLAG_RXFE      (1u << 4)  /* Receive FIFO empty */
+#define UART_FLAG_BUSY      (1u << 3)  /* UART busy */
+#define UART_FLAG_DCD       (1u << 2)  /* Data carrier detect */
+#define UART_FLAG_DSR       (1u << 1)  /* Data set ready */
+#define UART_FLAG_CTS       (1u << 0)  /* Cleart to send */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_UART_H */
diff --git a/arch/arm/src/efm32/Make.defs b/arch/arm/src/efm32/Make.defs
index 4c7a42486d3..9cc149ae7e3 100644
--- a/arch/arm/src/efm32/Make.defs
+++ b/arch/arm/src/efm32/Make.defs
@@ -63,11 +63,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
diff --git a/arch/arm/src/efm32/efm32_adc.h b/arch/arm/src/efm32/efm32_adc.h
index 9b892c0663e..53ef6a62f83 100644
--- a/arch/arm/src/efm32/efm32_adc.h
+++ b/arch/arm/src/efm32/efm32_adc.h
@@ -44,7 +44,7 @@
 
 #include "chip.h"
 
-#include "chip/efm32_adc.h"
+#include "hardware/efm32_adc.h"
 
 #include 
 
diff --git a/arch/arm/src/efm32/efm32_bitband.h b/arch/arm/src/efm32/efm32_bitband.h
index 9c655de78a4..e84a7ff05d4 100644
--- a/arch/arm/src/efm32/efm32_bitband.h
+++ b/arch/arm/src/efm32/efm32_bitband.h
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/efm32/efm32_clockconfig.c b/arch/arm/src/efm32/efm32_clockconfig.c
index 2ff0670f510..2d2bd907b40 100644
--- a/arch/arm/src/efm32/efm32_clockconfig.c
+++ b/arch/arm/src/efm32/efm32_clockconfig.c
@@ -50,9 +50,9 @@
 #include "chip.h"
 #include "itm_syslog.h"
 #include "efm32_gpio.h"
-#include "chip/efm32_msc.h"
-#include "chip/efm32_cmu.h"
-#include "chip/efm32_gpio.h"
+#include "hardware/efm32_msc.h"
+#include "hardware/efm32_cmu.h"
+#include "hardware/efm32_gpio.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/efm32/efm32_dma.c b/arch/arm/src/efm32/efm32_dma.c
index 7efc1d20219..ddb2e23fd01 100644
--- a/arch/arm/src/efm32/efm32_dma.c
+++ b/arch/arm/src/efm32/efm32_dma.c
@@ -50,8 +50,8 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/efm32_cmu.h"
-#include "chip/efm32_dma.h"
+#include "hardware/efm32_cmu.h"
+#include "hardware/efm32_dma.h"
 #include "efm32_dma.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/efm32/efm32_dma.h b/arch/arm/src/efm32/efm32_dma.h
index 19eec8b0e93..8d323336273 100644
--- a/arch/arm/src/efm32/efm32_dma.h
+++ b/arch/arm/src/efm32/efm32_dma.h
@@ -47,7 +47,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/efm32_dma.h"
+#include "hardware/efm32_dma.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/efm32/efm32_flash.c b/arch/arm/src/efm32/efm32_flash.c
index 66cae06ab34..24d74aca8a5 100644
--- a/arch/arm/src/efm32/efm32_flash.c
+++ b/arch/arm/src/efm32/efm32_flash.c
@@ -80,8 +80,8 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/efm32_msc.h"
-#include "chip/efm32_devinfo.h"
+#include "hardware/efm32_msc.h"
+#include "hardware/efm32_devinfo.h"
 
 #include "efm32_bitband.h"
 
diff --git a/arch/arm/src/efm32/efm32_gpio.c b/arch/arm/src/efm32/efm32_gpio.c
index 7ffc58cf344..2366a26c212 100644
--- a/arch/arm/src/efm32/efm32_gpio.c
+++ b/arch/arm/src/efm32/efm32_gpio.c
@@ -45,7 +45,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/efm32_gpio.h"
+#include "hardware/efm32_gpio.h"
 #include "efm32_gpio.h"
 
 /************************************************************************************
diff --git a/arch/arm/src/efm32/efm32_gpioirq.c b/arch/arm/src/efm32/efm32_gpioirq.c
index 1b317582811..dd31f639ed6 100644
--- a/arch/arm/src/efm32/efm32_gpioirq.c
+++ b/arch/arm/src/efm32/efm32_gpioirq.c
@@ -47,7 +47,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/efm32_gpio.h"
+#include "hardware/efm32_gpio.h"
 #include "efm32_gpio.h"
 #include "efm32_bitband.h"
 
diff --git a/arch/arm/src/efm32/efm32_i2c.c b/arch/arm/src/efm32/efm32_i2c.c
index 87e6b827478..8f2e0e98cfe 100644
--- a/arch/arm/src/efm32/efm32_i2c.c
+++ b/arch/arm/src/efm32/efm32_i2c.c
@@ -80,8 +80,8 @@
 #include "up_arch.h"
 
 #include "efm32_gpio.h"
-#include "chip/efm32_cmu.h"
-#include "chip/efm32_i2c.h"
+#include "hardware/efm32_cmu.h"
+#include "hardware/efm32_i2c.h"
 
 /* At least one I2C peripheral must be enabled */
 
diff --git a/arch/arm/src/efm32/efm32_leserial.c b/arch/arm/src/efm32/efm32_leserial.c
index 2303f7ce72a..dee04cef0d4 100644
--- a/arch/arm/src/efm32/efm32_leserial.c
+++ b/arch/arm/src/efm32/efm32_leserial.c
@@ -57,7 +57,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/efm32_leuart.h"
+#include "hardware/efm32_leuart.h"
 #include "efm32_config.h"
 #include "efm32_lowputc.h"
 
diff --git a/arch/arm/src/efm32/efm32_lowputc.c b/arch/arm/src/efm32/efm32_lowputc.c
index 26ec02884aa..466f7c93f21 100644
--- a/arch/arm/src/efm32/efm32_lowputc.c
+++ b/arch/arm/src/efm32/efm32_lowputc.c
@@ -47,10 +47,10 @@
 
 #include "up_arch.h"
 
-#include "chip/efm32_memorymap.h"
-#include "chip/efm32_usart.h"
-#include "chip/efm32_leuart.h"
-#include "chip/efm32_cmu.h"
+#include "hardware/efm32_memorymap.h"
+#include "hardware/efm32_usart.h"
+#include "hardware/efm32_leuart.h"
+#include "hardware/efm32_cmu.h"
 
 #include "efm32_gpio.h"
 #include "efm32_lowputc.h"
diff --git a/arch/arm/src/efm32/efm32_pwm.c b/arch/arm/src/efm32/efm32_pwm.c
index e619f805692..5cfaab505b2 100644
--- a/arch/arm/src/efm32/efm32_pwm.c
+++ b/arch/arm/src/efm32/efm32_pwm.c
@@ -53,8 +53,8 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/efm32_cmu.h"
-#include "chip/efm32_timer.h"
+#include "hardware/efm32_cmu.h"
+#include "hardware/efm32_timer.h"
 #include "efm32_timer.h"
 #include "efm32_config.h"
 #include "efm32_gpio.h"
diff --git a/arch/arm/src/efm32/efm32_pwm.h b/arch/arm/src/efm32/efm32_pwm.h
index 909137c9c07..9b987267ec4 100644
--- a/arch/arm/src/efm32/efm32_pwm.h
+++ b/arch/arm/src/efm32/efm32_pwm.h
@@ -82,7 +82,7 @@
     defined(CONFIG_EFM32_TIMER3_PWM)
 
 #include 
-#include "chip/efm32_timer.h"
+#include "hardware/efm32_timer.h"
 
 /* For each timer that is enabled for PWM usage, we need the following additional
  * configuration settings:
diff --git a/arch/arm/src/efm32/efm32_rmu.c b/arch/arm/src/efm32/efm32_rmu.c
index fbed325339e..744fbd17275 100644
--- a/arch/arm/src/efm32/efm32_rmu.c
+++ b/arch/arm/src/efm32/efm32_rmu.c
@@ -50,8 +50,8 @@
 
 #include "up_arch.h"
 
-#include "chip/efm32_emu.h"
-#include "chip/efm32_rmu.h"
+#include "hardware/efm32_emu.h"
+#include "hardware/efm32_rmu.h"
 
 #include "efm32_rmu.h"
 
diff --git a/arch/arm/src/efm32/efm32_rmu.h b/arch/arm/src/efm32/efm32_rmu.h
index 9a7a32dbdc8..7fb44beaa4b 100644
--- a/arch/arm/src/efm32/efm32_rmu.h
+++ b/arch/arm/src/efm32/efm32_rmu.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/efm32_rmu.h"
+#include "hardware/efm32_rmu.h"
 
 #ifdef CONFIG_EFM32_RMU
 
diff --git a/arch/arm/src/efm32/efm32_rtc_burtc.c b/arch/arm/src/efm32/efm32_rtc_burtc.c
index d0028b6a11f..9ce34673e41 100644
--- a/arch/arm/src/efm32/efm32_rtc_burtc.c
+++ b/arch/arm/src/efm32/efm32_rtc_burtc.c
@@ -53,7 +53,7 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/efm32_burtc.h"
+#include "hardware/efm32_burtc.h"
 
 #include "efm32_rmu.h"
 #include "efm32_rtc.h"
diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c
index e1ecd7a837d..80eb14c3fdd 100644
--- a/arch/arm/src/efm32/efm32_serial.c
+++ b/arch/arm/src/efm32/efm32_serial.c
@@ -61,7 +61,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/efm32_usart.h"
+#include "hardware/efm32_usart.h"
 #include "efm32_config.h"
 #include "efm32_gpio.h"
 #include "efm32_lowputc.h"
diff --git a/arch/arm/src/efm32/efm32_spi.c b/arch/arm/src/efm32/efm32_spi.c
index 7fe5139666d..843519157d8 100644
--- a/arch/arm/src/efm32/efm32_spi.c
+++ b/arch/arm/src/efm32/efm32_spi.c
@@ -62,7 +62,7 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/efm32_usart.h"
+#include "hardware/efm32_usart.h"
 #include "efm32_config.h"
 #include "efm32_dma.h"
 #include "efm32_lowputc.h"
diff --git a/arch/arm/src/efm32/efm32_start.c b/arch/arm/src/efm32/efm32_start.c
index 2f8d8be39bf..d5b61d91a0c 100644
--- a/arch/arm/src/efm32/efm32_start.c
+++ b/arch/arm/src/efm32/efm32_start.c
@@ -57,9 +57,7 @@
 #include "efm32_clockconfig.h"
 #include "efm32_start.h"
 
-#ifdef CONFIG_ARCH_FPU
-#  include "nvic.h"
-#endif
+#include "nvic.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/efm32/efm32_timer.c b/arch/arm/src/efm32/efm32_timer.c
index f8c1b1eaafe..86121c2d75b 100644
--- a/arch/arm/src/efm32/efm32_timer.c
+++ b/arch/arm/src/efm32/efm32_timer.c
@@ -51,7 +51,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/efm32_timer.h"
+#include "hardware/efm32_timer.h"
 #include "efm32_config.h"
 #include "efm32_gpio.h"
 
diff --git a/arch/arm/src/efm32/efm32_timer.h b/arch/arm/src/efm32/efm32_timer.h
index 3ed36baad78..ebafbef1ddb 100644
--- a/arch/arm/src/efm32/efm32_timer.h
+++ b/arch/arm/src/efm32/efm32_timer.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/efm32_timer.h"
+#include "hardware/efm32_timer.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/efm32/efm32_usb.h b/arch/arm/src/efm32/efm32_usb.h
index 4f0e25d8d91..9236e7ae37f 100644
--- a/arch/arm/src/efm32/efm32_usb.h
+++ b/arch/arm/src/efm32/efm32_usb.h
@@ -44,7 +44,7 @@
 
 #include 
 
-#include "chip/efm32_usb.h"
+#include "hardware/efm32_usb.h"
 
 #if defined(CONFIG_EFM32_OTGFS)
 
diff --git a/arch/arm/src/efm32/efm32_usbdev.c b/arch/arm/src/efm32/efm32_usbdev.c
index eedec628e97..e0de5b08fa3 100644
--- a/arch/arm/src/efm32/efm32_usbdev.c
+++ b/arch/arm/src/efm32/efm32_usbdev.c
@@ -60,7 +60,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/efm32_cmu.h"
+#include "hardware/efm32_cmu.h"
 
 #include "efm32_usb.h"
 
diff --git a/arch/arm/src/efm32/chip/efm32_acmp.h b/arch/arm/src/efm32/hardware/efm32_acmp.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_acmp.h
rename to arch/arm/src/efm32/hardware/efm32_acmp.h
index e9956ba8e48..177ac49f556 100644
--- a/arch/arm/src/efm32/chip/efm32_acmp.h
+++ b/arch/arm/src/efm32/hardware/efm32_acmp.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_adc.h b/arch/arm/src/efm32/hardware/efm32_adc.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_adc.h
rename to arch/arm/src/efm32/hardware/efm32_adc.h
index 8245acffab8..2d12977102d 100644
--- a/arch/arm/src/efm32/chip/efm32_adc.h
+++ b/arch/arm/src/efm32/hardware/efm32_adc.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_aes.h b/arch/arm/src/efm32/hardware/efm32_aes.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_aes.h
rename to arch/arm/src/efm32/hardware/efm32_aes.h
index 3376edaec31..dd7f580436d 100644
--- a/arch/arm/src/efm32/chip/efm32_aes.h
+++ b/arch/arm/src/efm32/hardware/efm32_aes.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_burtc.h b/arch/arm/src/efm32/hardware/efm32_burtc.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_burtc.h
rename to arch/arm/src/efm32/hardware/efm32_burtc.h
index 7cdc5cd347a..817f2b74ba9 100644
--- a/arch/arm/src/efm32/chip/efm32_burtc.h
+++ b/arch/arm/src/efm32/hardware/efm32_burtc.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_calibrate.h b/arch/arm/src/efm32/hardware/efm32_calibrate.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_calibrate.h
rename to arch/arm/src/efm32/hardware/efm32_calibrate.h
index 508d0b56e98..f5c21edf6ef 100644
--- a/arch/arm/src/efm32/chip/efm32_calibrate.h
+++ b/arch/arm/src/efm32/hardware/efm32_calibrate.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_cmu.h b/arch/arm/src/efm32/hardware/efm32_cmu.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_cmu.h
rename to arch/arm/src/efm32/hardware/efm32_cmu.h
index ffefddd6939..67780485be2 100644
--- a/arch/arm/src/efm32/chip/efm32_cmu.h
+++ b/arch/arm/src/efm32/hardware/efm32_cmu.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG) && !defined(CONFIG_EFM32_EFM32G)
 #  warning This is the EFM32GG/G header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_dac.h b/arch/arm/src/efm32/hardware/efm32_dac.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_dac.h
rename to arch/arm/src/efm32/hardware/efm32_dac.h
index 58aec484dc0..8e8d3e46b8d 100644
--- a/arch/arm/src/efm32/chip/efm32_dac.h
+++ b/arch/arm/src/efm32/hardware/efm32_dac.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_devinfo.h b/arch/arm/src/efm32/hardware/efm32_devinfo.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_devinfo.h
rename to arch/arm/src/efm32/hardware/efm32_devinfo.h
index 024b5b2674a..455a4d7a2cb 100644
--- a/arch/arm/src/efm32/chip/efm32_devinfo.h
+++ b/arch/arm/src/efm32/hardware/efm32_devinfo.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_dma.h b/arch/arm/src/efm32/hardware/efm32_dma.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_dma.h
rename to arch/arm/src/efm32/hardware/efm32_dma.h
index d7ef85e3112..3ede28072c3 100644
--- a/arch/arm/src/efm32/chip/efm32_dma.h
+++ b/arch/arm/src/efm32/hardware/efm32_dma.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG) && !defined(CONFIG_EFM32_EFM32G)
 #  warning This is the EFM32GG/G header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_emu.h b/arch/arm/src/efm32/hardware/efm32_emu.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_emu.h
rename to arch/arm/src/efm32/hardware/efm32_emu.h
index 9cd1c67bd9c..9b8c68d1c1f 100644
--- a/arch/arm/src/efm32/chip/efm32_emu.h
+++ b/arch/arm/src/efm32/hardware/efm32_emu.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_flash.h b/arch/arm/src/efm32/hardware/efm32_flash.h
similarity index 100%
rename from arch/arm/src/efm32/chip/efm32_flash.h
rename to arch/arm/src/efm32/hardware/efm32_flash.h
diff --git a/arch/arm/src/efm32/chip/efm32_gpio.h b/arch/arm/src/efm32/hardware/efm32_gpio.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_gpio.h
rename to arch/arm/src/efm32/hardware/efm32_gpio.h
index f631de0409e..6f4f9f3b35a 100644
--- a/arch/arm/src/efm32/chip/efm32_gpio.h
+++ b/arch/arm/src/efm32/hardware/efm32_gpio.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG) && !defined(CONFIG_EFM32_EFM32G)
 #  warning This is the EFM32GG/G header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_i2c.h b/arch/arm/src/efm32/hardware/efm32_i2c.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_i2c.h
rename to arch/arm/src/efm32/hardware/efm32_i2c.h
index df8382a2a93..c0a5af072ce 100644
--- a/arch/arm/src/efm32/chip/efm32_i2c.h
+++ b/arch/arm/src/efm32/hardware/efm32_i2c.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_lcd.h b/arch/arm/src/efm32/hardware/efm32_lcd.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_lcd.h
rename to arch/arm/src/efm32/hardware/efm32_lcd.h
index f00a4706f3f..62615a35e29 100644
--- a/arch/arm/src/efm32/chip/efm32_lcd.h
+++ b/arch/arm/src/efm32/hardware/efm32_lcd.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_lesense.h b/arch/arm/src/efm32/hardware/efm32_lesense.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_lesense.h
rename to arch/arm/src/efm32/hardware/efm32_lesense.h
index 512a7095bb2..84d48702c16 100644
--- a/arch/arm/src/efm32/chip/efm32_lesense.h
+++ b/arch/arm/src/efm32/hardware/efm32_lesense.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_letimer.h b/arch/arm/src/efm32/hardware/efm32_letimer.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_letimer.h
rename to arch/arm/src/efm32/hardware/efm32_letimer.h
index 3b877d448f1..5d2fa051e9f 100644
--- a/arch/arm/src/efm32/chip/efm32_letimer.h
+++ b/arch/arm/src/efm32/hardware/efm32_letimer.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_leuart.h b/arch/arm/src/efm32/hardware/efm32_leuart.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_leuart.h
rename to arch/arm/src/efm32/hardware/efm32_leuart.h
index be5b1bc0de4..fbf0de77222 100644
--- a/arch/arm/src/efm32/chip/efm32_leuart.h
+++ b/arch/arm/src/efm32/hardware/efm32_leuart.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG) && !defined(CONFIG_EFM32_EFM32G)
 #  warning This is the EFM32GG/G header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_memorymap.h b/arch/arm/src/efm32/hardware/efm32_memorymap.h
similarity index 95%
rename from arch/arm/src/efm32/chip/efm32_memorymap.h
rename to arch/arm/src/efm32/hardware/efm32_memorymap.h
index 62e0a24f820..384927a2c84 100644
--- a/arch/arm/src/efm32/chip/efm32_memorymap.h
+++ b/arch/arm/src/efm32/hardware/efm32_memorymap.h
@@ -44,11 +44,11 @@
 #include "chip.h"
 
 #if defined(CONFIG_EFM32_EFM32TG)
-#  include "chip/efm32tg_memorymap.h"
+#  include "hardware/efm32tg_memorymap.h"
 #elif defined(CONFIG_EFM32_EFM32G)
-#  include "chip/efm32g_memorymap.h"
+#  include "hardware/efm32g_memorymap.h"
 #elif defined(CONFIG_EFM32_EFM32GG)
-#  include "chip/efm32gg_memorymap.h"
+#  include "hardware/efm32gg_memorymap.h"
 #else
 #  error "Unsupported EFM32 memory map"
 #endif
diff --git a/arch/arm/src/efm32/chip/efm32_msc.h b/arch/arm/src/efm32/hardware/efm32_msc.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_msc.h
rename to arch/arm/src/efm32/hardware/efm32_msc.h
index 27b806743ca..f6dd0e08f1f 100644
--- a/arch/arm/src/efm32/chip/efm32_msc.h
+++ b/arch/arm/src/efm32/hardware/efm32_msc.h
@@ -65,7 +65,7 @@
  * Included Files
  *******************************************************************************************************************************/
 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 /*******************************************************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/efm32/chip/efm32_pcnt.h b/arch/arm/src/efm32/hardware/efm32_pcnt.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_pcnt.h
rename to arch/arm/src/efm32/hardware/efm32_pcnt.h
index e9947f5ba74..1fa10362e67 100644
--- a/arch/arm/src/efm32/chip/efm32_pcnt.h
+++ b/arch/arm/src/efm32/hardware/efm32_pcnt.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_prs.h b/arch/arm/src/efm32/hardware/efm32_prs.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_prs.h
rename to arch/arm/src/efm32/hardware/efm32_prs.h
index b0d8d6e0161..8c83310f760 100644
--- a/arch/arm/src/efm32/chip/efm32_prs.h
+++ b/arch/arm/src/efm32/hardware/efm32_prs.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_rmu.h b/arch/arm/src/efm32/hardware/efm32_rmu.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_rmu.h
rename to arch/arm/src/efm32/hardware/efm32_rmu.h
index e383cce1352..2e34fb59575 100644
--- a/arch/arm/src/efm32/chip/efm32_rmu.h
+++ b/arch/arm/src/efm32/hardware/efm32_rmu.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_romtable.h b/arch/arm/src/efm32/hardware/efm32_romtable.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_romtable.h
rename to arch/arm/src/efm32/hardware/efm32_romtable.h
index 42ed83cbc84..467675c4a80 100644
--- a/arch/arm/src/efm32/chip/efm32_romtable.h
+++ b/arch/arm/src/efm32/hardware/efm32_romtable.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_rtc.h b/arch/arm/src/efm32/hardware/efm32_rtc.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_rtc.h
rename to arch/arm/src/efm32/hardware/efm32_rtc.h
index 044efae971e..0231a6b59dc 100644
--- a/arch/arm/src/efm32/chip/efm32_rtc.h
+++ b/arch/arm/src/efm32/hardware/efm32_rtc.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_timer.h b/arch/arm/src/efm32/hardware/efm32_timer.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_timer.h
rename to arch/arm/src/efm32/hardware/efm32_timer.h
index 86b9aaa51a7..55d23e014a1 100644
--- a/arch/arm/src/efm32/chip/efm32_timer.h
+++ b/arch/arm/src/efm32/hardware/efm32_timer.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this architecture
diff --git a/arch/arm/src/efm32/chip/efm32_usart.h b/arch/arm/src/efm32/hardware/efm32_usart.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_usart.h
rename to arch/arm/src/efm32/hardware/efm32_usart.h
index 6cd1372c3be..613664eaf80 100644
--- a/arch/arm/src/efm32/chip/efm32_usart.h
+++ b/arch/arm/src/efm32/hardware/efm32_usart.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG) && !defined(CONFIG_EFM32_EFM32G)
 #  warning This is the EFM32GG/G header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_usb.h b/arch/arm/src/efm32/hardware/efm32_usb.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_usb.h
rename to arch/arm/src/efm32/hardware/efm32_usb.h
index 92c53e77a62..51213550c0c 100644
--- a/arch/arm/src/efm32/chip/efm32_usb.h
+++ b/arch/arm/src/efm32/hardware/efm32_usb.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_vcmp.h b/arch/arm/src/efm32/hardware/efm32_vcmp.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_vcmp.h
rename to arch/arm/src/efm32/hardware/efm32_vcmp.h
index ec71abd8784..8439fffb726 100644
--- a/arch/arm/src/efm32/chip/efm32_vcmp.h
+++ b/arch/arm/src/efm32/hardware/efm32_vcmp.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32_wdog.h b/arch/arm/src/efm32/hardware/efm32_wdog.h
similarity index 99%
rename from arch/arm/src/efm32/chip/efm32_wdog.h
rename to arch/arm/src/efm32/hardware/efm32_wdog.h
index 4568dee1593..c01c8c93841 100644
--- a/arch/arm/src/efm32/chip/efm32_wdog.h
+++ b/arch/arm/src/efm32/hardware/efm32_wdog.h
@@ -66,7 +66,7 @@
  *******************************************************************************************************************************/
 
 #include 
-#include "chip/efm32_memorymap.h"
+#include "hardware/efm32_memorymap.h"
 
 #if !defined(CONFIG_EFM32_EFM32GG)
 #  warning This is the EFM32GG header file; Review/modification needed for this archtecture
diff --git a/arch/arm/src/efm32/chip/efm32g_memorymap.h b/arch/arm/src/efm32/hardware/efm32g_memorymap.h
similarity index 100%
rename from arch/arm/src/efm32/chip/efm32g_memorymap.h
rename to arch/arm/src/efm32/hardware/efm32g_memorymap.h
diff --git a/arch/arm/src/efm32/chip/efm32gg_memorymap.h b/arch/arm/src/efm32/hardware/efm32gg_memorymap.h
similarity index 100%
rename from arch/arm/src/efm32/chip/efm32gg_memorymap.h
rename to arch/arm/src/efm32/hardware/efm32gg_memorymap.h
diff --git a/arch/arm/src/efm32/chip/efm32tg_memorymap.h b/arch/arm/src/efm32/hardware/efm32tg_memorymap.h
similarity index 100%
rename from arch/arm/src/efm32/chip/efm32tg_memorymap.h
rename to arch/arm/src/efm32/hardware/efm32tg_memorymap.h
diff --git a/arch/arm/src/imx6/chip.h b/arch/arm/src/imx6/chip.h
index 27ec41854c2..8aa0dd2e9eb 100644
--- a/arch/arm/src/imx6/chip.h
+++ b/arch/arm/src/imx6/chip.h
@@ -46,7 +46,7 @@
 #  include 
 #endif
 
-#include "chip/imx_memorymap.h"
+#include "hardware/imx_memorymap.h"
 #include "imx_irq.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/imx6/chip/imx_ccm.h b/arch/arm/src/imx6/hardware/imx_ccm.h
similarity index 99%
rename from arch/arm/src/imx6/chip/imx_ccm.h
rename to arch/arm/src/imx6/hardware/imx_ccm.h
index 73faa18365e..9f51d617f55 100644
--- a/arch/arm/src/imx6/chip/imx_ccm.h
+++ b/arch/arm/src/imx6/hardware/imx_ccm.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imx6/imx_ccm.h
+ * arch/arm/src/imx6/hardware/imx_ccm.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,15 +37,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMX6_CHIP_IMX_CCM_H
-#define __ARCH_ARM_SRC_IMX6_CHIP_IMX_CCM_H
+#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_CCM_H
+#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_CCM_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include 
+#include "hardware/imx_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -1032,4 +1032,4 @@
 #define CCM_CMEOR_MOD_EN_OV_CAN2_CPI    (1 << 28) /* Bit 28: Overide clock enable signal from CAN2 */
 #define CCM_CMEOR_MOD_EN_OV_CAN1_CPI    (1 << 30) /* Bit 30: Overide clock enable signal from CAN1 */
 
-#endif /* __ARCH_ARM_SRC_IMX6_CHIP_IMX_CCM_H */
+#endif /* __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_CCM_H */
diff --git a/arch/arm/src/imx6/chip/imx_ecspi.h b/arch/arm/src/imx6/hardware/imx_ecspi.h
similarity index 98%
rename from arch/arm/src/imx6/chip/imx_ecspi.h
rename to arch/arm/src/imx6/hardware/imx_ecspi.h
index 2d7864132d0..62ad9eaaac6 100644
--- a/arch/arm/src/imx6/chip/imx_ecspi.h
+++ b/arch/arm/src/imx6/hardware/imx_ecspi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imx6/imx_ecspi.h
+ * arch/arm/src/imx6/hardware/imx_ecspi.h
  *
  *   Copyright (C) 2009-2010, 2015-2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_IMX6_CHIP_ECSPI_H
-#define __ARCH_ARM_IMX6_CHIP_ECSPI_H
+#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_ECSPI_H
+#define __ARCH_ARM_SRC_IMX6_HARDWARE_ECSPI_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/imx_memorymap.h"
+#include "hardware/imx_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -287,4 +287,4 @@
  * Public Function Prototypes
  ************************************************************************************/
 
-#endif  /* __ARCH_ARM_IMX6_CHIP_ECSPI_H */
+#endif  /* __ARCH_ARM_SRC_IMX6_HARDWARE_ECSPI_H */
diff --git a/arch/arm/src/imx6/chip/imx_gpio.h b/arch/arm/src/imx6/hardware/imx_gpio.h
similarity index 97%
rename from arch/arm/src/imx6/chip/imx_gpio.h
rename to arch/arm/src/imx6/hardware/imx_gpio.h
index 88aa0675c31..2ccd23acff7 100644
--- a/arch/arm/src/imx6/chip/imx_gpio.h
+++ b/arch/arm/src/imx6/hardware/imx_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imx6/imx_gpio.h
+ * arch/arm/src/imx6/hardware/imx_gpio.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,15 +37,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMX6_CHIP_IMX_GPIO_H
-#define __ARCH_ARM_SRC_IMX6_CHIP_IMX_GPIO_H
+#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPIO_H
+#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPIO_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include 
+#include "hardware/imx_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -167,4 +167,4 @@
 #define GPIO_ICR_MASK(n)         (3 << GPIO_ICR_SHIFT(n))
 #define GPIO_ICR(i,n)            ((uint32_t)(i) << GPIO_ICR_SHIFT(n))
 
-#endif /* __ARCH_ARM_SRC_IMX6_CHIP_IMX_GPIO_H */
+#endif /* __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPIO_H */
diff --git a/arch/arm/src/imx6/chip/imx_gpt.h b/arch/arm/src/imx6/hardware/imx_gpt.h
similarity index 97%
rename from arch/arm/src/imx6/chip/imx_gpt.h
rename to arch/arm/src/imx6/hardware/imx_gpt.h
index ad741f19c87..f4658400c29 100644
--- a/arch/arm/src/imx6/chip/imx_gpt.h
+++ b/arch/arm/src/imx6/hardware/imx_gpt.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imx6/imx_gpt.h
+ * arch/arm/src/imx6/hardware/imx_gpt.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,15 +37,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMX6_CHIP_IMX_GPT_H
-#define __ARCH_ARM_SRC_IMX6_CHIP_IMX_GPT_H
+#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPT_H
+#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPT_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include 
+#include "hardware/imx_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -154,4 +154,4 @@
 /* GPT Input Capture Register 1,2 -- 32-bit capture registers */
 /* GPT Counter Register -- 32-bit counter */
 
-#endif /* __ARCH_ARM_SRC_IMX6_CHIP_IMX_GPT_H */
+#endif /* __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_GPT_H */
diff --git a/arch/arm/src/imx6/chip/imx_iomuxc.h b/arch/arm/src/imx6/hardware/imx_iomuxc.h
similarity index 99%
rename from arch/arm/src/imx6/chip/imx_iomuxc.h
rename to arch/arm/src/imx6/hardware/imx_iomuxc.h
index 96bea8e098f..226c68a9c3d 100644
--- a/arch/arm/src/imx6/chip/imx_iomuxc.h
+++ b/arch/arm/src/imx6/hardware/imx_iomuxc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imx6/chip/imx_iomuxc.h
+ * arch/arm/src/imx6/hardware/imx_iomuxc.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,15 +37,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMX6_CHIP_IMX_IOMUXC_H
-#define __ARCH_ARM_SRC_IMX6_CHIP_IMX_IOMUXC_H
+#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_IOMUXC_H
+#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_IOMUXC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include 
+#include "hardware/imx_memorymap.h"
 
 /* These definitions derive from specifications for the i.MX 6Quad/6Dual and require
  * review and modification in order to support other family members.
@@ -2271,4 +2271,4 @@
 /* Select Input Registers */
 
 #endif /* CONFIG_ARCH_CHIP_IMX6_6QUAD || CONFIG_ARCH_CHIP_IMX6_6DUAL */
-#endif /* __ARCH_ARM_SRC_IMX6_CHIP_IMX_IOMUXC_H */
+#endif /* __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_IOMUXC_H */
diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/hardware/imx_memorymap.h
similarity index 99%
rename from arch/arm/src/imx6/chip/imx_memorymap.h
rename to arch/arm/src/imx6/hardware/imx_memorymap.h
index c9ad19dfdf3..c8f7363228d 100644
--- a/arch/arm/src/imx6/chip/imx_memorymap.h
+++ b/arch/arm/src/imx6/hardware/imx_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imx6/chip/imx_memorymap.h
+ * arch/arm/src/imx6/hardware/imx_memorymap.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMX6_CHIP_IMX_MEMORYMAP_H
-#define __ARCH_ARM_SRC_IMX6_CHIP_IMX_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -1043,4 +1043,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_IMX6_CHIP_IMX_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_MEMORYMAP_H */
diff --git a/arch/arm/src/imx6/chip/imx_pinmux.h b/arch/arm/src/imx6/hardware/imx_pinmux.h
similarity index 99%
rename from arch/arm/src/imx6/chip/imx_pinmux.h
rename to arch/arm/src/imx6/hardware/imx_pinmux.h
index 2cd840b9a14..741648db757 100644
--- a/arch/arm/src/imx6/chip/imx_pinmux.h
+++ b/arch/arm/src/imx6/hardware/imx_pinmux.h
@@ -1,5 +1,5 @@
 /*****************************************************************************************************
- * arch/arm/src/imx6/imx_pinmux.h
+ * arch/arm/src/imx6/hardware/imx_pinmux.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  *****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMX6_CHIP_IMX_PINMUX_H
-#define __ARCH_ARM_SRC_IMX6_CHIP_IMX_PINMUX_H
+#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_PINMUX_H
+#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_PINMUX_H
 
 /*****************************************************************************************************
  * Pre-processor Definitions
@@ -964,4 +964,4 @@
 #define GPIO_XTALOSC_REF_CLK_24M_2    (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMX_PADMUX_RGMII_TXC_INDEX))
 #define GPIO_XTALOSC_REF_CLK_32K      (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMX_PADMUX_GPIO08_INDEX))
 
-#endif /* __ARCH_ARM_SRC_IMX6_CHIP_IMX_PINMUX_H */
+#endif /* __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_PINMUX_H */
diff --git a/arch/arm/src/imx6/chip/imx_src.h b/arch/arm/src/imx6/hardware/imx_src.h
similarity index 98%
rename from arch/arm/src/imx6/chip/imx_src.h
rename to arch/arm/src/imx6/hardware/imx_src.h
index b49a9b44254..d6e52cf7fc2 100644
--- a/arch/arm/src/imx6/chip/imx_src.h
+++ b/arch/arm/src/imx6/hardware/imx_src.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/imx6/imx_src.h
+ * arch/arm/src/imx6/hardware/imx_src.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,15 +37,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMX6_CHIP_IMX_SRC_H
-#define __ARCH_ARM_SRC_IMX6_CHIP_IMX_SRC_H
+#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_SRC_H
+#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_SRC_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include 
+#include "hardware/imx_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -209,4 +209,4 @@
 #define SRC_GPR10_RW2_MASK           (15 << SRC_GPR10_RW2_SHIFT)
 #  define SRC_GPR10_RW2(n)           ((uint32_t)(n) << SRC_GPR10_RW2_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_IMX6_CHIP_IMX_SRC_H */
+#endif /* __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_SRC_H */
diff --git a/arch/arm/src/imx6/chip/imx_uart.h b/arch/arm/src/imx6/hardware/imx_uart.h
similarity index 98%
rename from arch/arm/src/imx6/chip/imx_uart.h
rename to arch/arm/src/imx6/hardware/imx_uart.h
index 81c2801ca8e..9a3db18911b 100644
--- a/arch/arm/src/imx6/chip/imx_uart.h
+++ b/arch/arm/src/imx6/hardware/imx_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imx6/imx_uart.h
+ * arch/arm/src/imx6/hardware/imx_uart.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,15 +37,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMX6_CHIP_IMX_UART_H
-#define __ARCH_ARM_SRC_IMX6_CHIP_IMX_UART_H
+#ifndef __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_UART_H
+#define __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_UART_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include 
+#include "hardware/imx_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -364,4 +364,4 @@
 #define UART_UMCR_SLADDR_MASK  (0xff << UART_UMCR_SLADDR_SHIFT)
 #  define UART_UMCR_SLADDR(n)  ((uint32_t)(n) << UART_UMCR_SLADDR_SHIFT)
 
-#endif  /* __ARCH_ARM_SRC_IMX6_CHIP_IMX_UART_H */
+#endif  /* __ARCH_ARM_SRC_IMX6_HARDWARE_IMX_UART_H */
diff --git a/arch/arm/src/imx6/imx_clockconfig.c b/arch/arm/src/imx6/imx_clockconfig.c
index 68613e4c078..a0fdff14458 100644
--- a/arch/arm/src/imx6/imx_clockconfig.c
+++ b/arch/arm/src/imx6/imx_clockconfig.c
@@ -40,7 +40,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/imx_ccm.h"
+#include "hardware/imx_ccm.h"
 #include "imx_config.h"
 #include "imx_clockconfig.h"
 
diff --git a/arch/arm/src/imx6/imx_cpuboot.c b/arch/arm/src/imx6/imx_cpuboot.c
index e747b701cfa..b92c3b19d53 100644
--- a/arch/arm/src/imx6/imx_cpuboot.c
+++ b/arch/arm/src/imx6/imx_cpuboot.c
@@ -48,7 +48,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/imx_src.h"
+#include "hardware/imx_src.h"
 #include "sctlr.h"
 #include "smp.h"
 #include "scu.h"
diff --git a/arch/arm/src/imx6/imx_ecspi.h b/arch/arm/src/imx6/imx_ecspi.h
index 4e3f8b977e1..64d8429f9a9 100644
--- a/arch/arm/src/imx6/imx_ecspi.h
+++ b/arch/arm/src/imx6/imx_ecspi.h
@@ -46,7 +46,7 @@
 #include 
 #include 
 
-#include "chip/imx_ecspi.h"
+#include "hardware/imx_ecspi.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/imx6/imx_gpio.h b/arch/arm/src/imx6/imx_gpio.h
index a9054a50ace..2cb9d407334 100644
--- a/arch/arm/src/imx6/imx_gpio.h
+++ b/arch/arm/src/imx6/imx_gpio.h
@@ -45,7 +45,7 @@
 #include 
 #include 
 
-#include "chip/imx_gpio.h"
+#include "hardware/imx_gpio.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/imx6/imx_iomuxc.c b/arch/arm/src/imx6/imx_iomuxc.c
index 8d7562b4d17..ff5e9bc3b7d 100644
--- a/arch/arm/src/imx6/imx_iomuxc.c
+++ b/arch/arm/src/imx6/imx_iomuxc.c
@@ -39,6 +39,7 @@
 
 #include 
 
+#include 
 #include 
 #include 
 #include 
diff --git a/arch/arm/src/imx6/imx_iomuxc.h b/arch/arm/src/imx6/imx_iomuxc.h
index 3b3f822d274..15560c6991f 100644
--- a/arch/arm/src/imx6/imx_iomuxc.h
+++ b/arch/arm/src/imx6/imx_iomuxc.h
@@ -44,7 +44,7 @@
 
 #include 
 
-#include "chip/imx_iomuxc.h"
+#include "hardware/imx_iomuxc.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/imx6/imx_lowputc.c b/arch/arm/src/imx6/imx_lowputc.c
index 8bfabf70856..782861ce683 100644
--- a/arch/arm/src/imx6/imx_lowputc.c
+++ b/arch/arm/src/imx6/imx_lowputc.c
@@ -45,9 +45,9 @@
 
 #include "up_arch.h"
 
-#include "chip/imx_iomuxc.h"
-#include "chip/imx_ccm.h"
-#include "chip/imx_uart.h"
+#include "hardware/imx_iomuxc.h"
+#include "hardware/imx_ccm.h"
+#include "hardware/imx_uart.h"
 #include "imx_config.h"
 #include "imx_iomuxc.h"
 #include "imx_gpio.h"
@@ -55,7 +55,7 @@
 
 #include "up_internal.h"
 
-#include "chip/imx_pinmux.h"
+#include "hardware/imx_pinmux.h"
 #include  /* Include last:  has dependencies */
 
 /****************************************************************************
diff --git a/arch/arm/src/imx6/imx_memorymap.c b/arch/arm/src/imx6/imx_memorymap.c
index 1189dd5d7f8..3859cd925e2 100644
--- a/arch/arm/src/imx6/imx_memorymap.c
+++ b/arch/arm/src/imx6/imx_memorymap.c
@@ -41,7 +41,7 @@
 
 #include "mmu.h"
 
-#include "chip/imx_memorymap.h"
+#include "hardware/imx_memorymap.h"
 #include "imx_memorymap.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/imx6/imx_serial.c b/arch/arm/src/imx6/imx_serial.c
index 5145f5d6b9c..21557688f3c 100644
--- a/arch/arm/src/imx6/imx_serial.c
+++ b/arch/arm/src/imx6/imx_serial.c
@@ -59,7 +59,7 @@
 #include "up_internal.h"
 
 #include "gic.h"
-#include "chip/imx_uart.h"
+#include "hardware/imx_uart.h"
 #include "imx_config.h"
 #include "imx_lowputc.h"
 
diff --git a/arch/arm/src/imx6/imx_timerisr.c b/arch/arm/src/imx6/imx_timerisr.c
index 3b66f1f9ac0..c9ee3ce5be0 100644
--- a/arch/arm/src/imx6/imx_timerisr.c
+++ b/arch/arm/src/imx6/imx_timerisr.c
@@ -47,8 +47,8 @@
 
 #include "up_arch.h"
 #include "gic.h"
-#include "chip/imx_ccm.h"
-#include "chip/imx_gpt.h"
+#include "hardware/imx_ccm.h"
+#include "hardware/imx_gpt.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig
index 821665dfbda..6d3157eeb6e 100644
--- a/arch/arm/src/imxrt/Kconfig
+++ b/arch/arm/src/imxrt/Kconfig
@@ -12,6 +12,22 @@ choice
 	default ARCH_CHIP_MIMXRT1052DVL6A
 	depends on ARCH_CHIP_IMXRT
 
+config ARCH_CHIP_MIMXRT1021CAG4A
+	bool "MIMXRT1021CAG4A"
+	select ARCH_FAMILY_MIMXRT1021C
+
+config ARCH_CHIP_MIMXRT1021CAF4A
+	bool "MIMXRT1021CAF4A"
+	select ARCH_FAMILY_MIMXRT1021C
+
+config ARCH_CHIP_MIMXRT1021DAF5A
+	bool "MIMXRT1021DAF5A"
+	select ARCH_FAMILY_MIMXRT1021D
+
+config ARCH_CHIP_MIMXRT1021DAG5A
+	bool "MIMXRT1021DAG5A"
+	select ARCH_FAMILY_MIMXRT1021D
+
 config ARCH_CHIP_MIMXRT1051DVL6A
 	bool "MIMXRT1051DVL6A"
 	select ARCH_FAMILY_MXRT105xDVL6A
@@ -48,6 +64,30 @@ endchoice # i.MX RT Chip Selection
 
 # i.MX RT Families
 
+config ARCH_FAMILY_MIMXRT1021D
+	bool
+	default n
+	select ARCH_FAMILY_IMXRT102x
+	---help---
+		i.MX RT1020 Crossover Processors for Consumer Products
+
+config ARCH_FAMILY_MIMXRT1021C
+	bool
+	default n
+	select ARCH_FAMILY_IMXRT102x
+	---help---
+		i.MX RT1020 Crossover Processors for Industrial Products
+
+config ARCH_FAMILY_IMXRT102x
+	bool
+	default n
+	select ARCH_HAVE_FPU
+	select ARCH_HAVE_DPFPU # REVISIT
+	select ARMV7M_HAVE_ICACHE
+	select ARMV7M_HAVE_DCACHE
+	select ARMV7M_HAVE_ITCM
+	select ARMV7M_HAVE_DTCM
+
 config ARCH_FAMILY_MXRT105xDVL6A
 	bool
 	default n
@@ -348,7 +388,7 @@ menuconfig IMXRT_GPIO_IRQ
 if IMXRT_GPIO_IRQ
 
 config IMXRT_GPIO1_0_15_IRQ
-	bool "GPIO1 Pins 8-15 interrupts"
+	bool "GPIO1 Pins 0-15 interrupts"
 	default n
 
 config IMXRT_GPIO1_16_31_IRQ
diff --git a/arch/arm/src/imxrt/Make.defs b/arch/arm/src/imxrt/Make.defs
index de4e4b6abb8..6ec909c1546 100644
--- a/arch/arm/src/imxrt/Make.defs
+++ b/arch/arm/src/imxrt/Make.defs
@@ -69,11 +69,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
diff --git a/arch/arm/src/imxrt/chip.h b/arch/arm/src/imxrt/chip.h
index 9b2f23236e4..ed94fc67228 100644
--- a/arch/arm/src/imxrt/chip.h
+++ b/arch/arm/src/imxrt/chip.h
@@ -48,7 +48,7 @@
 
 #include 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /* If the common ARMv7-M vector handling logic is used, then it expects the following
  * definition in this file that provides the number of supported vectors external
diff --git a/arch/arm/src/imxrt/chip/imxrt_adc.h b/arch/arm/src/imxrt/hardware/imxrt_adc.h
similarity index 98%
rename from arch/arm/src/imxrt/chip/imxrt_adc.h
rename to arch/arm/src/imxrt/hardware/imxrt_adc.h
index 6b22c151290..de19fc85bf0 100644
--- a/arch/arm/src/imxrt/chip/imxrt_adc.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_adc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_adc.h
+ * arch/arm/src/imxrt/hardware/imxrt_adc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,15 +34,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ADC_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ADC_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_ADC_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_ADC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -260,4 +260,4 @@
 #define ADC_CAL_CAL_CODE_MASK                (0xf << ADC_CAL_CAL_CODE_SHIFT)
                                                         /* Bits: 4-31  Reserved */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ADC_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_ADC_H */
diff --git a/arch/arm/src/imxrt/hardware/imxrt_ccm.h b/arch/arm/src/imxrt/hardware/imxrt_ccm.h
new file mode 100644
index 00000000000..949e7b5737c
--- /dev/null
+++ b/arch/arm/src/imxrt/hardware/imxrt_ccm.h
@@ -0,0 +1,57 @@
+/*****************************************************************************
+ * arch/arm/src/imxrt/hardware/imxrt_ccm.h
+ *
+ *   Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
+ *   Authors:  Janne Rosberg 
+ *             David Sidrane 
+ *             Dave Marples 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_CCM_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_CCM_H
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include 
+#include "hardware/imxrt_memorymap.h"
+
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include "hardware/rt102x/imxrt102x_ccm.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#  include "hardware/rt105x/imxrt105x_ccm.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
+#  include "hardware/rt106x/imxrt106x_ccm.h"
+#else
+#  error Unrecognized i.MX RT architecture
+#endif
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_CCM_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_daisy.h b/arch/arm/src/imxrt/hardware/imxrt_daisy.h
similarity index 92%
rename from arch/arm/src/imxrt/chip/imxrt_daisy.h
rename to arch/arm/src/imxrt/hardware/imxrt_daisy.h
index 4ff29fc52df..3ea0641cd7d 100644
--- a/arch/arm/src/imxrt/chip/imxrt_daisy.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_daisy.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_daisy.h
+ * arch/arm/src/imxrt/hardware/imxrt_daisy.h
  *
  *   Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DAISY_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DAISY_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DAISY_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DAISY_H
 
 /************************************************************************************
  * Included Files
@@ -58,5 +58,5 @@
 
 void imxrt_daisy_select(unsigned int index, unsigned int alt);
 
-#endif  /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DAISY_H */
+#endif  /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DAISY_H */
 
diff --git a/arch/arm/src/imxrt/chip/imxrt_dcdc.h b/arch/arm/src/imxrt/hardware/imxrt_dcdc.h
similarity index 97%
rename from arch/arm/src/imxrt/chip/imxrt_dcdc.h
rename to arch/arm/src/imxrt/hardware/imxrt_dcdc.h
index 28d3c758adb..1c3d4820c88 100644
--- a/arch/arm/src/imxrt/chip/imxrt_dcdc.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_dcdc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/imxrt/imxrt_dcdc.h
+ * arch/arm/src/imxrt/hardware/imxrt_dcdc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Janne Rosberg 
@@ -33,15 +33,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DCDC_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DCDC_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DCDC_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DCDC_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -149,4 +149,4 @@
 #define DCDC_REG3_DISABLE_STEP              (1 << 30) /* Bit 30: Disable stepping */
                                                       /* Bit 31: Reserved */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DCDC_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DCDC_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_dmamux.h b/arch/arm/src/imxrt/hardware/imxrt_dmamux.h
similarity index 93%
rename from arch/arm/src/imxrt/chip/imxrt_dmamux.h
rename to arch/arm/src/imxrt/hardware/imxrt_dmamux.h
index ff58300b675..3b6c325e1e6 100644
--- a/arch/arm/src/imxrt/chip/imxrt_dmamux.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_dmamux.h
@@ -1,5 +1,5 @@
-/************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_dmamux.h
+/****************************************************************************
+ * arch/arm/src/imxrt/hardware/imxrt_dmamux.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -32,33 +32,35 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- ************************************************************************************/
+ ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DMAMUX_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DMAMUX_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DMAMUX_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DMAMUX_H
 
-/************************************************************************************
+/****************************************************************************
  * Included Files
- ************************************************************************************/
+ ****************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
-#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
-#  include "chip/imxrt105x_dmamux.h"
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include "hardware/rt102x/imxrt102x_dmamux.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#  include "hardware/rt105x/imxrt105x_dmamux.h"
 #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
-#  include "chip/imxrt106x_dmamux.h"
+#  include "hardware/rt106x/imxrt106x_dmamux.h"
 #else
 #  error Unrecognized i.MX RT architecture
 #endif
 
-/************************************************************************************
+/****************************************************************************
  * Pre-processor definitions
- ************************************************************************************/
+ ****************************************************************************/
 
 #define IMXRT_DMAMUX_NCHAN             32
 
-/* DMAMUX Register Offsets **********************************************************/
+/* DMAMUX Register Offsets **************************************************/
 
 #define IMXRT_DMAMUX_CHCFG_OFFSET(n)   ((uintptr_t)(n) << 2)
 #  define IMXRT_DMAMUX_CHCFG0_OFFSET   0x0000  /* Channel configuration register 0 */
@@ -94,7 +96,7 @@
 #  define IMXRT_DMAMUX_CHCFG30_OFFSET  0x0078  /* Channel configuration register 30 */
 #  define IMXRT_DMAMUX_CHCFG31_OFFSET  0x007c  /* Channel configuration register 31 */
 
-/* DMAMUX Register Addresses ********************************************************/
+/* DMAMUX Register Addresses ************************************************/
 
 #define IMXRT_DMAMUX_CHCFG(n)          (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG_OFFSET(n))
 #  define IMXRT_DMAMUX_CHCFG0          (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG0_OFFSET)
@@ -130,7 +132,7 @@
 #  define IMXRT_DMAMUX_CHCFG30         (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG30_OFFSET)
 #  define IMXRT_DMAMUX_CHCFG31         (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG31_OFFSET)
 
-/* DMAMUX Bit-Field Definitions *****************************************************/
+/* DMAMUX Bit-Field Definitions *********************************************/
 
 /* Channel configuration registers 0-31 */
 
@@ -142,4 +144,4 @@
 #define DMAMUX_CHCFG_TRIG              (1 << 30) /* Bit 30: DMA Channel Trigger Enable */
 #define DMAMUX_CHCFG_ENBL              (1 << 31) /* Bit 31: DMA Mux Channel Enable */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_DMAMUX_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_DMAMUX_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_edma.h b/arch/arm/src/imxrt/hardware/imxrt_edma.h
similarity index 99%
rename from arch/arm/src/imxrt/chip/imxrt_edma.h
rename to arch/arm/src/imxrt/hardware/imxrt_edma.h
index 46c809e045a..b46ddd58891 100644
--- a/arch/arm/src/imxrt/chip/imxrt_edma.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_edma.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_edma.h
+ * arch/arm/src/imxrt/hardware/imxrt_edma.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_EDMA_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_EDMA_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_EDMA_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_EDMA_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -1299,4 +1299,4 @@ struct imxrt_edmatcd_s
   uint16_t biter;         /* Offset: 0x001e  TCD Beginning Minor Loop Link, Major Loop Count */
 };
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_EDMA_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_EDMA_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_enet.h b/arch/arm/src/imxrt/hardware/imxrt_enet.h
similarity index 97%
rename from arch/arm/src/imxrt/chip/imxrt_enet.h
rename to arch/arm/src/imxrt/hardware/imxrt_enet.h
index 1e2ae7db667..f5fb1f6ef8a 100644
--- a/arch/arm/src/imxrt/chip/imxrt_enet.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_enet.h
@@ -1,5 +1,5 @@
-/********************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_enet.h
+/*****************************************************************************
+ * arch/arm/src/imxrt/hardware/imxrt_enet.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -31,24 +31,24 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- ********************************************************************************************/
+ *****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENET_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENET_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_ENET_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_ENET_H
 
-/********************************************************************************************
+/*****************************************************************************
  * Included Files
- ********************************************************************************************/
+ *****************************************************************************/
 
 #include 
 
 #include "chip.h"
 
-/********************************************************************************************
+/*****************************************************************************
  * Pre-processor Definitions
- ********************************************************************************************/
+ *****************************************************************************/
 
-/* Register Offsets *************************************************************************/
+/* Register Offsets **********************************************************/
 
 #define IMXRT_ENET_EIR_OFFSET      0x0004 /* Interrupt Event Register */
 #define IMXRT_ENET_EIMR_OFFSET     0x0008 /* Interrupt Mask Register */
@@ -103,7 +103,7 @@
 #define IMXRT_ENET_TCSR3_OFFSET    0x0620 /* Timer Control Status Register */
 #define IMXRT_ENET_TCCR3_OFFSET    0x0624 /* Timer Compare Capture Register */
 
-/* Register Addresses ***********************************************************************/
+/* Register Addresses ********************************************************/
 
 #define IMXRT_ENET_EIR             (IMXRT_ENET_BASE+IMXRT_ENET_EIR_OFFSET)
 #define IMXRT_ENET_EIMR            (IMXRT_ENET_BASE+IMXRT_ENET_EIMR_OFFSET)
@@ -156,7 +156,7 @@
 #define IMXRT_ENET_TCSR3           (IMXRT_ENET_BASE+IMXRT_ENET_TCSR3_OFFSET)
 #define IMXRT_ENET_TCCR3           (IMXRT_ENET_BASE+IMXRT_ENET_TCCR3_OFFSET)
 
-/* Register Bit Definitions *****************************************************************/
+/* Register Bit Definitions **************************************************/
 
 /* Interrupt Event Register, Interrupt Mask Register */
                                                /* Bits 0-14: Reserved */
@@ -199,6 +199,7 @@
 #define ENET_ECR_DBSWP               (1 << 8)  /* Bit 8:  Swap bytes */
 #endif
                                                /* Bits 9-31: Reserved */
+#define ECR_RESV_VAL                 (7 << 28) /* Reserve val to write */
 /* MII Management Frame Register */
 
 #define ENET_MMFR_DATA_SHIFT         (0)       /* Bits 0-15: Management frame data */
@@ -453,20 +454,20 @@
                                                /* Bits 8-31: Reserved */
 /* Timer Compare Capture Register (32-bit compare value) */
 
-/* Buffer Descriptors ***********************************************************************/
+/* Buffer Descriptors ********************************************************/
 /* Endian-independent descriptor offsets */
 
-#define DESC_STATUS1_OFFSET         (0)
-#define DESC_LENGTH_OFFSET          (2)
-#define DESC_DATAPTR_OFFSET         (4)
-#define DESC_LEGACY_LEN             (8)
+#define DESC_STATUS1_OFFSET          (0)
+#define DESC_LENGTH_OFFSET           (2)
+#define DESC_DATAPTR_OFFSET          (4)
+#define DESC_LEGACY_LEN              (8)
 
-#define DESC_STATUS2_OFFSET         (8)
-#define DESC_LENPROTO_OFFSET        (12)
-#define DESC_CHECKSUM_OFFSET        (14)
-#define DESC_BDU_OFFSET             (16)
-#define DESC_TIMESTAMP_OFFSET       (20)
-#define DESC_ENHANCED_LEN           (32)
+#define DESC_STATUS2_OFFSET          (8)
+#define DESC_LENPROTO_OFFSET         (12)
+#define DESC_CHECKSUM_OFFSET         (14)
+#define DESC_BDU_OFFSET              (16)
+#define DESC_TIMESTAMP_OFFSET        (20)
+#define DESC_ENHANCED_LEN            (32)
 
 /* Legacy/Common TX Buffer Descriptor Bit Definitions.
  *
@@ -599,10 +600,12 @@
 #  define RXDESC_BDU                 (1 << 7)
 #endif
 
-/********************************************************************************************
+/*****************************************************************************
  * Public Types
- ********************************************************************************************/
-/* Buffer Descriptors ***********************************************************************/
+ *****************************************************************************/
+
+/* Buffer Descriptors ********************************************************/
+
 /* Legacy Buffer Descriptor */
 
 #ifdef CONFIG_ENET_ENHANCEDBD
@@ -658,12 +661,12 @@ struct enet_desc_s
 #endif /* IMXRT_USE_DBSWAP */
 #endif /* CONFIG_ENET_ENHANCEDBD */
 
-/********************************************************************************************
+/*****************************************************************************
  * Public Data
- ********************************************************************************************/
+ *****************************************************************************/
 
-/********************************************************************************************
+/*****************************************************************************
  * Public Functions
- ********************************************************************************************/
+ *****************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_ENET_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_ENET_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_flexpwm.h b/arch/arm/src/imxrt/hardware/imxrt_flexpwm.h
similarity index 99%
rename from arch/arm/src/imxrt/chip/imxrt_flexpwm.h
rename to arch/arm/src/imxrt/hardware/imxrt_flexpwm.h
index 6a3a66edd28..a1b9ce99dcc 100644
--- a/arch/arm/src/imxrt/chip/imxrt_flexpwm.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_flexpwm.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_flexpwm.h
+ * arch/arm/src/imxrt/hardware/imxrt_flexpwm.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,15 +34,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_FLEXPWM_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_FLEXPWM_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_FLEXPWM_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_FLEXPWM_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -1814,4 +1814,4 @@
 #  define FCTRL20_NOCOMB_FAULT2              (4 << FCTRL20_NOCOMB_SHIFT)  /*  Disable direct combinational path from the FAULT2 input to the PWM output */
 #  define FCTRL20_NOCOMB_FAULT3              (8 << FCTRL20_NOCOMB_SHIFT)  /*  Disable direct combinational path from the FAULT3 input to the PWM output */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_FLEXPWM_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_FLEXPWM_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_gpio.h b/arch/arm/src/imxrt/hardware/imxrt_gpio.h
similarity index 90%
rename from arch/arm/src/imxrt/chip/imxrt_gpio.h
rename to arch/arm/src/imxrt/hardware/imxrt_gpio.h
index 9b030ad97d8..fd874650858 100644
--- a/arch/arm/src/imxrt/chip/imxrt_gpio.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_gpio.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/imxrt/imxrt_gpio.h
+ * arch/arm/src/imxrt/hardware/imxrt_gpio.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPIO_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPIO_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_GPIO_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_GPIO_H
 
 /********************************************************************************************
  * Included Files
@@ -43,10 +43,12 @@
 
 #include 
 
-#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
-#  include "chip/imxrt105x_gpio.h"
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include "hardware/rt102x/imxrt102x_gpio.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#  include "hardware/rt105x/imxrt105x_gpio.h"
 #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
-#  include "chip/imxrt106x_gpio.h"
+#  include "hardware/rt106x/imxrt106x_gpio.h"
 #else
 #  error Unrecognized i.MX RT architecture
 #endif
@@ -88,4 +90,4 @@
 #define GPIO_ICR_MASK(n)         (3 << GPIO_ICR_SHIFT(n))
 #define GPIO_ICR(i,n)            ((uint32_t)(i) << GPIO_ICR_SHIFT(n))
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPIO_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_GPIO_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_gpt.h b/arch/arm/src/imxrt/hardware/imxrt_gpt.h
similarity index 98%
rename from arch/arm/src/imxrt/chip/imxrt_gpt.h
rename to arch/arm/src/imxrt/hardware/imxrt_gpt.h
index ffee5865351..aa2e08fafd2 100644
--- a/arch/arm/src/imxrt/chip/imxrt_gpt.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_gpt.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_gpt.h
+ * arch/arm/src/imxrt/hardware/imxrt_gpt.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,15 +34,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPT_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPT_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_GPT_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_GPT_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -179,4 +179,4 @@
 #define GPT_IR_ROVIE               (1 << 5)   /* Bit: 5  Rollover Interrupt Enable. */
                                               /* Bits: 6-31  Reserved */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_GPT_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_GPT_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_iomuxc.h b/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h
similarity index 94%
rename from arch/arm/src/imxrt/chip/imxrt_iomuxc.h
rename to arch/arm/src/imxrt/hardware/imxrt_iomuxc.h
index 6d3aa454271..18799f3bcc4 100644
--- a/arch/arm/src/imxrt/chip/imxrt_iomuxc.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_iomuxc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/imxrt_iomuxc.h
+ * arch/arm/src/imxrt/hardware/imxrt_iomuxc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_IOMUXC_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_IOMUXC_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_IOMUXC_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_IOMUXC_H
 
 /************************************************************************************
  * Included Files
@@ -43,10 +43,12 @@
 
 #include 
 
-#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
-#  include "chip/imxrt105x_iomuxc.h"
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include "hardware/rt102x/imxrt102x_iomuxc.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#  include "hardware/rt105x/imxrt105x_iomuxc.h"
 #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
-#  include "chip/imxrt106x_iomuxc.h"
+#  include "hardware/rt106x/imxrt106x_iomuxc.h"
 #else
 #  error Unrecognized i.MX RT architecture
 #endif
@@ -119,4 +121,4 @@
 #  define PADCTL_PUS_UP_22K                   (3 << PADCTL_PUS_SHIFT) /*  22K Ohm Pull Up */
 #define PADCTL_HYS                            (1 << 16) /* Bit 16: Hysteresis Enable Field */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_IOMUXC_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_IOMUXC_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_lcd.h b/arch/arm/src/imxrt/hardware/imxrt_lcd.h
similarity index 99%
rename from arch/arm/src/imxrt/chip/imxrt_lcd.h
rename to arch/arm/src/imxrt/hardware/imxrt_lcd.h
index 4a7b94e254d..c77685ff345 100644
--- a/arch/arm/src/imxrt/chip/imxrt_lcd.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_lcd.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_lcd.h
+ * arch/arm/src/imxrt/hardware/imxrt_lcd.h
  *
  *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2016-2018 NXP. All rights reserved.
@@ -34,15 +34,15 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LCD_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LCD_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LCD_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LCD_H
 
 /************************************************************************************************
  * Included Files
  ************************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /************************************************************************************************
  * Pre-processor Definitions
@@ -1706,4 +1706,4 @@
 #define LCDIF_LUT1_DATA_DATA_SHIFT               (0U)
 #define LCDIF_LUT1_DATA_DATA(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LCD_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LCD_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_lpi2c.h b/arch/arm/src/imxrt/hardware/imxrt_lpi2c.h
similarity index 99%
rename from arch/arm/src/imxrt/chip/imxrt_lpi2c.h
rename to arch/arm/src/imxrt/hardware/imxrt_lpi2c.h
index a7d15b0b549..e48cd49d237 100644
--- a/arch/arm/src/imxrt/chip/imxrt_lpi2c.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_lpi2c.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/imxrt/imxrt_lpi2c.h
+ * arch/arm/src/imxrt/hardware/imxrt_lpi2c.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Ivan Ucherdzhiev 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPI2C_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPI2C_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LPI2C_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LPI2C_H
 
 /********************************************************************************************
  * Included Files
@@ -619,4 +619,4 @@
 #define LPI2C_STAR_RXEMPTY                  (1 << 15) /* Start Of Frame */
                                                       /* Bits 31-16 Reserved */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPI2C_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LPI2C_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_lpspi.h b/arch/arm/src/imxrt/hardware/imxrt_lpspi.h
similarity index 99%
rename from arch/arm/src/imxrt/chip/imxrt_lpspi.h
rename to arch/arm/src/imxrt/hardware/imxrt_lpspi.h
index 699e4eddf45..3f8e69d41ef 100644
--- a/arch/arm/src/imxrt/chip/imxrt_lpspi.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_lpspi.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/imxrt/imxrt_lpspi.h
+ * arch/arm/src/imxrt/hardware/imxrt_lpspi.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Pavlina Koleva 
@@ -33,15 +33,15 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPSPI_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPSPI_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LPSPI_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LPSPI_H
 
 /********************************************************************************************
  * Included Files
  ********************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -368,4 +368,4 @@
 #define LPSPI_RDR_DATA_SHIFT           (0)       /* Bits 0-31: Receive Data */
 #define LPSPI_RDR_DATA_MASK            (0xffffffff << LPSPI_RDR_DATA_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPSPI_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LPSPI_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_lpuart.h b/arch/arm/src/imxrt/hardware/imxrt_lpuart.h
similarity index 99%
rename from arch/arm/src/imxrt/chip/imxrt_lpuart.h
rename to arch/arm/src/imxrt/hardware/imxrt_lpuart.h
index 2ea9e584465..d3b481d8ede 100644
--- a/arch/arm/src/imxrt/chip/imxrt_lpuart.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_lpuart.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/imxrt/imxrt_lpuart.h
+ * arch/arm/src/imxrt/hardware/imxrt_lpuart.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPUART_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPUART_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LPUART_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LPUART_H
 
 /********************************************************************************************
  * Included Files
  ********************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -413,4 +413,4 @@
 #  define LPUART_WATER_RXCOUNT(n)      ((uint32_t)(n) << LPUART_WATER_RXCOUNT_SHIFT)
                                                  /* Bits 27-31:  Reserved */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPUART_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_LPUART_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_memorymap.h b/arch/arm/src/imxrt/hardware/imxrt_memorymap.h
similarity index 82%
rename from arch/arm/src/imxrt/chip/imxrt_memorymap.h
rename to arch/arm/src/imxrt/hardware/imxrt_memorymap.h
index e6352da0a16..3d320adf636 100644
--- a/arch/arm/src/imxrt/chip/imxrt_memorymap.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_memorymap.h
+ * arch/arm/src/imxrt/hardware/imxrt_memorymap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_MEMORYMAP_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_MEMORYMAP_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -42,12 +42,14 @@
 
 #include 
 
-#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
-#  include "chip/imxrt105x_memorymap.h"
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include "hardware/rt102x/imxrt102x_memorymap.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#  include "hardware/rt105x/imxrt105x_memorymap.h"
 #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
-#  include "chip/imxrt106x_memorymap.h"
+#  include "hardware/rt106x/imxrt106x_memorymap.h"
 #else
 #  error Unrecognized i.MX RT architecture
 #endif
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_MEMORYMAP_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_ocotp.h b/arch/arm/src/imxrt/hardware/imxrt_ocotp.h
similarity index 99%
rename from arch/arm/src/imxrt/chip/imxrt_ocotp.h
rename to arch/arm/src/imxrt/hardware/imxrt_ocotp.h
index d4d5d3f0cb4..296b6fef1b4 100644
--- a/arch/arm/src/imxrt/chip/imxrt_ocotp.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_ocotp.h
@@ -1,5 +1,5 @@
 /************************************************************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_ocotp.h
+ * arch/arm/src/imxrt/hardware/imxrt_ocotp.h
  *
  *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_OCOTP_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_OCOTP_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_OCOTP_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_OCOTP_H
 
 /* The OCOTP IP block provides a set of register to access the On Chip OPT.
  * It also provides a shadow image of the 64 OTP entries that are read only
@@ -48,7 +48,7 @@
  ************************************************************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /************************************************************************************************************************************
  * Pre-processor Definitions
@@ -426,4 +426,4 @@
 #define OCOTP_LOCK_FIELD_RETURN_MASK          (15 << OCOTP_LOCK_FIELD_RETURN_SHIFT)
 #  define OCOTP_LOCK_FIELD_RETURN(n)          ((uint32_t)(n) << OCOTP_LOCK_FIELD_RETURN_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_OCOTP_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_OCOTP_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_pinmux.h b/arch/arm/src/imxrt/hardware/imxrt_pinmux.h
similarity index 83%
rename from arch/arm/src/imxrt/chip/imxrt_pinmux.h
rename to arch/arm/src/imxrt/hardware/imxrt_pinmux.h
index c92b3d8cb85..61f4f608097 100644
--- a/arch/arm/src/imxrt/chip/imxrt_pinmux.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_pinmux.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_pinmux.h
+ * arch/arm/src/imxrt/hardware/imxrt_pinmux.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PINMUX_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PINMUX_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_PINMUX_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_PINMUX_H
 
 /************************************************************************************
  * Included Files
@@ -43,12 +43,14 @@
 
 #include 
 
-#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
-#  include "chip/imxrt105x_pinmux.h"
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include "hardware/rt102x/imxrt102x_pinmux.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#  include "hardware/rt105x/imxrt105x_pinmux.h"
 #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
-#  include "chip/imxrt106x_pinmux.h"
+#  include "hardware/rt106x/imxrt106x_pinmux.h"
 #else
 #  error Unrecognized i.MX RT architecture
 #endif
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PINMUX_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_PINMUX_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_pit.h b/arch/arm/src/imxrt/hardware/imxrt_pit.h
similarity index 96%
rename from arch/arm/src/imxrt/chip/imxrt_pit.h
rename to arch/arm/src/imxrt/hardware/imxrt_pit.h
index 69241853071..ce736f4408a 100644
--- a/arch/arm/src/imxrt/chip/imxrt_pit.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_pit.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_pit.h
+ * arch/arm/src/imxrt/hardware/imxrt_pit.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,15 +34,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PIT_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PIT_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_PIT_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_PIT_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -128,4 +128,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_PIT_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_PIT_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_snvs.h b/arch/arm/src/imxrt/hardware/imxrt_snvs.h
similarity index 98%
rename from arch/arm/src/imxrt/chip/imxrt_snvs.h
rename to arch/arm/src/imxrt/hardware/imxrt_snvs.h
index 7bead26f3e6..7db7bfde41b 100644
--- a/arch/arm/src/imxrt/chip/imxrt_snvs.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_snvs.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/imxrt/imxrt_snvs.h
+ * arch/arm/src/imxrt/hardware/imxrt_snvs.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SNVS_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SNVS_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_SNVS_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_SNVS_H
 
 /********************************************************************************************
  * Included Files
  ********************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -294,4 +294,4 @@
 #define SNVS_HPVIDR2_IPERA_SHIFT      (24)      /* Bits 24-31: IP Era */
 #define SNVS_HPVIDR2_IPERA_MASK       (0xff << SNVS_HPVIDR2_IPERA_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SNVS_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_SNVS_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_src.h b/arch/arm/src/imxrt/hardware/imxrt_src.h
similarity index 97%
rename from arch/arm/src/imxrt/chip/imxrt_src.h
rename to arch/arm/src/imxrt/hardware/imxrt_src.h
index 60beeedbe96..7458139332e 100644
--- a/arch/arm/src/imxrt/chip/imxrt_src.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_src.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/imxrt/imxrt_src.h
+ * arch/arm/src/imxrt/hardware/imxrt_src.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SRC_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SRC_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_SRC_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_SRC_H
 
 /********************************************************************************************
  * Included Files
  ********************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -153,5 +153,5 @@
  * software.
  */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_SRC_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_SRC_H */
 
diff --git a/arch/arm/src/imxrt/chip/imxrt_tmr.h b/arch/arm/src/imxrt/hardware/imxrt_tmr.h
similarity index 99%
rename from arch/arm/src/imxrt/chip/imxrt_tmr.h
rename to arch/arm/src/imxrt/hardware/imxrt_tmr.h
index ae24118fe99..283ba70910d 100644
--- a/arch/arm/src/imxrt/chip/imxrt_tmr.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_tmr.h
@@ -1,5 +1,5 @@
 /********************************************************************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_tmr.h
+ * arch/arm/src/imxrt/hardware/imxrt_tmr.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,15 +34,15 @@
  *
  ********************************************************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_TMR_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_TMR_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_TMR_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_TMR_H
 
 /********************************************************************************************************************************************
  * Included Files
  ********************************************************************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /********************************************************************************************************************************************
  * Pre-processor Definitions
@@ -659,4 +659,4 @@
 #  define TMR_ENBL_CHN4                (8 << TMR_ENBL_ENBL_SHIFT)  /* Channel 3 enable */
                                                   /* Bits: 4-15  Reserved */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_TMR_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_TMR_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_usb_analog.h b/arch/arm/src/imxrt/hardware/imxrt_usb_analog.h
similarity index 98%
rename from arch/arm/src/imxrt/chip/imxrt_usb_analog.h
rename to arch/arm/src/imxrt/hardware/imxrt_usb_analog.h
index a7ca8f96cd5..14b9031fe3a 100644
--- a/arch/arm/src/imxrt/chip/imxrt_usb_analog.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_usb_analog.h
@@ -1,5 +1,5 @@
 /************************************************************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_usb_analog.h
+ * arch/arm/src/imxrt/hardware/imxrt_usb_analog.h
  *
  *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,15 +34,15 @@
  *
  ************************************************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_USB_ANALOG_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_USB_ANALOG_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_ANALOG_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_ANALOG_H
 
 /************************************************************************************************************************************
  * Included Files
  ************************************************************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /************************************************************************************************************************************
  * Pre-processor Definitions
@@ -206,4 +206,4 @@
 
 #define USB_ANALOG_DIGPROG_SILICON_REVISION                0x006C0000 /* Silicon revision 1.0 */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_USB_ANALOG_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_ANALOG_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_usdhc.h b/arch/arm/src/imxrt/hardware/imxrt_usdhc.h
similarity index 99%
rename from arch/arm/src/imxrt/chip/imxrt_usdhc.h
rename to arch/arm/src/imxrt/hardware/imxrt_usdhc.h
index 9cc10b997c0..2a0ec097bd2 100644
--- a/arch/arm/src/imxrt/chip/imxrt_usdhc.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_usdhc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_usdhc.h
+ * arch/arm/src/imxrt/hardware/imxrt_usdhc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt  & Contributors
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_USDHC_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_USDHC_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USDHC_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USDHC_H
 
 /************************************************************************************
  * Included Files
@@ -552,4 +552,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_USDHC_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USDHC_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_wdog.h b/arch/arm/src/imxrt/hardware/imxrt_wdog.h
similarity index 96%
rename from arch/arm/src/imxrt/chip/imxrt_wdog.h
rename to arch/arm/src/imxrt/hardware/imxrt_wdog.h
index 1f1bfba62f7..5420a09653f 100644
--- a/arch/arm/src/imxrt/chip/imxrt_wdog.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_wdog.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/imxrt_wdog.h
+ * arch/arm/src/imxrt/hardware/imxrt_wdog.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Janne Rosberg 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_WDOG_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_WDOG_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_WDOG_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_WDOG_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -139,4 +139,4 @@
 #define RTWDOG_UPDATE_KEY           (0xd928c520)
 #define RTWDOG_REFRESH_KEY          (0xb480a602)
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_WDOG_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_WDOG_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt_xbar.h b/arch/arm/src/imxrt/hardware/imxrt_xbar.h
similarity index 83%
rename from arch/arm/src/imxrt/chip/imxrt_xbar.h
rename to arch/arm/src/imxrt/hardware/imxrt_xbar.h
index 8eb1e2f85f6..29c596d5479 100644
--- a/arch/arm/src/imxrt/chip/imxrt_xbar.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_xbar.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt_abar.h
+ * arch/arm/src/imxrt/hardware/imxrt_abar.h
  *
  *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_XBAR_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_XBAR_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_XBAR_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_XBAR_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,18 @@
 
 #include 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
+
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include "hardware/rt102x/imxrt102x_xbar.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#  include "hardware/rt105x/imxrt105x_xbar.h"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
+#  include "hardware/rt106x/imxrt106x_xbar.h"
+#else
+#  error Unrecognized i.MX RT architecture
+#endif
+
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -60,4 +71,4 @@
 #define IMXRT_SEL1_MASK      (0x7f << IMXRT_SEL1_SHIFTS)
                                   /* Bit 15 Reserved */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_XBAR_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_XBAR_H */
diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h
new file mode 100644
index 00000000000..642127a7cc0
--- /dev/null
+++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h
@@ -0,0 +1,970 @@
+/*****************************************************************************
+ * arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h
+ *
+ *   Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
+ *   Authors:  Janne Rosberg 
+ *             David Sidrane 
+ *             Dave Marples 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_CCM_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_CCM_H
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include 
+#include "hardware/imxrt_memorymap.h"
+
+/*****************************************************************************
+ * Pre-processor Definitions
+ *****************************************************************************/
+
+/* Register offsets **********************************************************/
+
+#define IMXRT_CCM_CCR_OFFSET                     0x0000  /* CCM Control Register */
+                                              /* 0x0004  Reserved */
+#define IMXRT_CCM_CSR_OFFSET                     0x0008  /* CCM Status Register */
+#define IMXRT_CCM_CCSR_OFFSET                    0x000c  /* CCM Clock Switcher Register */
+#define IMXRT_CCM_CACRR_OFFSET                   0x0010  /* CCM Arm Clock Root Register */
+#define IMXRT_CCM_CBCDR_OFFSET                   0x0014  /* CCM Bus Clock Divider Register */
+#define IMXRT_CCM_CBCMR_OFFSET                   0x0018  /* CCM Bus Clock Multiplexer Register */
+#define IMXRT_CCM_CSCMR1_OFFSET                  0x001c  /* CCM Serial Clock Multiplexer Register 1 */
+#define IMXRT_CCM_CSCMR2_OFFSET                  0x0020  /* CCM Serial Clock Multiplexer Register 2 */
+#define IMXRT_CCM_CSCDR1_OFFSET                  0x0024  /* CCM Serial Clock Divider Register 1 */
+#define IMXRT_CCM_CS1CDR_OFFSET                  0x0028  /* CCM Clock Divider Register */
+#define IMXRT_CCM_CS2CDR_OFFSET                  0x002c  /* CCM Clock Divider Register */
+#define IMXRT_CCM_CDCDR_OFFSET                   0x0030  /* CCM D1 Clock Divider Register */
+                                              /* 0x0034  Reserved */
+#define IMXRT_CCM_CSCDR2_OFFSET                  0x0038  /* CCM Serial Clock Divider Register 2 */
+#define IMXRT_CCM_CSCDR3_OFFSET                  0x003c  /* CCM Serial Clock Divider Register 3 */
+                                              /* 0x0040  Reserved */
+                                              /* 0x0044  Reserved */
+#define IMXRT_CCM_CDHIPR_OFFSET                  0x0048  /* CCM Divider Handshake In-Process Register */
+                                              /* 0x004c  Reserved */
+                                              /* 0x0050  Reserved */
+#define IMXRT_CCM_CLPCR_OFFSET                   0x0054  /* CCM Low Power Control Register */
+
+#define IMXRT_CCM_CISR_OFFSET                    0x0058  /* CCM Interrupt Status Register */
+#define IMXRT_CCM_CIMR_OFFSET                    0x005c  /* CCM Interrupt Mask Register */
+#define IMXRT_CCM_CCOSR_OFFSET                   0x0060  /* CCM Clock Output Source Register */
+#define IMXRT_CCM_CGPR_OFFSET                    0x0064  /* CCM General Purpose Register */
+#define IMXRT_CCM_CCGR0_OFFSET                   0x0068  /* CCM Clock Gating Register 0 */
+#define IMXRT_CCM_CCGR1_OFFSET                   0x006c  /* CCM Clock Gating Register 1 */
+#define IMXRT_CCM_CCGR2_OFFSET                   0x0070  /* CCM Clock Gating Register 2 */
+#define IMXRT_CCM_CCGR3_OFFSET                   0x0074  /* CCM Clock Gating Register 3 */
+#define IMXRT_CCM_CCGR4_OFFSET                   0x0078  /* CCM Clock Gating Register 4 */
+#define IMXRT_CCM_CCGR5_OFFSET                   0x007c  /* CCM Clock Gating Register 5 */
+#define IMXRT_CCM_CCGR6_OFFSET                   0x0080  /* CCM Clock Gating Register 6 */
+                                              /* 0x0084  Reserved */
+#define IMXRT_CCM_CMEOR_OFFSET                   0x0088  /* CCM Module Enable Overide Register */
+
+/* Analog */
+
+#define IMXRT_CCM_ANALOG_PLL_USB1_OFFSET         0x0010  /* Analog USB1 480MHz PLL Control Register */
+#define IMXRT_CCM_ANALOG_PLL_SYS_OFFSET          0x0030  /* Analog System PLL Control Register */
+#define IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET       0x0040  /* 528MHz System PLL Spread Spectrum Register */
+#define IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET      0x0050  /* Numerator of 528MHz System PLL Fractional Loop Divider */
+#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET    0x0060  /* Denominator of 528MHz System PLL Fractional Loop Divider */
+#define IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET        0x0070  /* Analog Audio PLL control Register */
+#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET    0x0080  /* Numerator of Audio PLL Fractional Loop Divider */
+#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET  0x0090  /* Denominator of Audio PLL Fractional Loop Divider */
+#define IMXRT_CCM_ANALOG_PLL_ENET_OFFSET         0x00e0  /* Analog ENET PLL Control Register */
+#define IMXRT_CCM_ANALOG_PFD_480_OFFSET          0x00f0  /* 480MHz Clock (PLL3) Phase Fractional Divider Control */
+#define IMXRT_CCM_ANALOG_PFD_528_OFFSET          0x0100  /* 528MHz Clock (PLL2) Phase Fractional Divider Control */
+#define IMXRT_CCM_ANALOG_MISC0_OFFSET            0x0150  /* Miscellaneous Register 0 */
+#define IMXRT_CCM_ANALOG_MISC1_OFFSET            0x0160  /* Miscellaneous Register 1 */
+#define IMXRT_CCM_ANALOG_MISC2_OFFSET            0x0170  /* Miscellaneous Register 2 */
+
+/* Register addresses ********************************************************/
+
+#define IMXRT_CCM_CCR                            (IMXRT_CCM_BASE + IMXRT_CCM_CCR_OFFSET)
+#define IMXRT_CCM_CSR                            (IMXRT_CCM_BASE + IMXRT_CCM_CSR_OFFSET)
+#define IMXRT_CCM_CCSR                           (IMXRT_CCM_BASE + IMXRT_CCM_CCSR_OFFSET)
+#define IMXRT_CCM_CACRR                          (IMXRT_CCM_BASE + IMXRT_CCM_CACRR_OFFSET)
+#define IMXRT_CCM_CBCDR                          (IMXRT_CCM_BASE + IMXRT_CCM_CBCDR_OFFSET)
+#define IMXRT_CCM_CBCMR                          (IMXRT_CCM_BASE + IMXRT_CCM_CBCMR_OFFSET)
+#define IMXRT_CCM_CSCMR1                         (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR1_OFFSET)
+#define IMXRT_CCM_CSCMR2                         (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR2_OFFSET)
+#define IMXRT_CCM_CSCDR1                         (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR1_OFFSET)
+#define IMXRT_CCM_CS1CDR                         (IMXRT_CCM_BASE + IMXRT_CCM_CS1CDR_OFFSET)
+#define IMXRT_CCM_CS2CDR                         (IMXRT_CCM_BASE + IMXRT_CCM_CS2CDR_OFFSET)
+#define IMXRT_CCM_CDCDR                          (IMXRT_CCM_BASE + IMXRT_CCM_CDCDR_OFFSET)
+#define IMXRT_CCM_CSCDR2                         (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR2_OFFSET)
+#define IMXRT_CCM_CSCDR3                         (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR3_OFFSET)
+#define IMXRT_CCM_CDHIPR                         (IMXRT_CCM_BASE + IMXRT_CCM_CDHIPR_OFFSET)
+#define IMXRT_CCM_CLPCR                          (IMXRT_CCM_BASE + IMXRT_CCM_CLPCR_OFFSET)
+#define IMXRT_CCM_CISR                           (IMXRT_CCM_BASE + IMXRT_CCM_CISR_OFFSET)
+#define IMXRT_CCM_CIMR                           (IMXRT_CCM_BASE + IMXRT_CCM_CIMR_OFFSET)
+#define IMXRT_CCM_CCOSR                          (IMXRT_CCM_BASE + IMXRT_CCM_CCOSR_OFFSET)
+#define IMXRT_CCM_CGPR                           (IMXRT_CCM_BASE + IMXRT_CCM_CGPR_OFFSET)
+#define IMXRT_CCM_CCGR0                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR0_OFFSET)
+#define IMXRT_CCM_CCGR1                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR1_OFFSET)
+#define IMXRT_CCM_CCGR2                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR2_OFFSET)
+#define IMXRT_CCM_CCGR3                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR3_OFFSET)
+#define IMXRT_CCM_CCGR4                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR4_OFFSET)
+#define IMXRT_CCM_CCGR5                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR5_OFFSET)
+#define IMXRT_CCM_CCGR6                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR6_OFFSET)
+#define IMXRT_CCM_CMEOR                          (IMXRT_CCM_BASE + IMXRT_CCM_CMEOR_OFFSET)
+
+#define IMXRT_CCM_ANALOG_PLL_ARM                 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ARM_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_USB1                (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB1_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_SYS                 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_SYS_SS              (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_SYS_NUM             (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM           (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_AUDIO               (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM           (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM         (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_ENET                (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ENET_OFFSET)
+#define IMXRT_CCM_ANALOG_PFD_480                 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_480_OFFSET)
+#define IMXRT_CCM_ANALOG_PFD_528                 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_528_OFFSET)
+#define IMXRT_CCM_ANALOG_MISC0                   (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC0_OFFSET)
+#define IMXRT_CCM_ANALOG_MISC1                   (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC1_OFFSET)
+#define IMXRT_CCM_ANALOG_MISC2                   (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC2_OFFSET)
+
+/* Helper Macros *************************************************************/
+
+#define CCM_PODF_FROM_DIVISOR(n)                   ((n)-1)  /* PODF Values are divisor-1 */
+
+/* Register bit definitions **************************************************/
+
+/* Control Register */
+
+#define CCM_CCR_OSCNT_SHIFT                      (0)       /* Bits 0-7:   Oscillator ready counter value */
+#define CCM_CCR_OSCNT_MASK                       (0xff << CCM_CCR_OSCNT_SHIFT)
+#  define CCM_CCR_OSCNT(n)                       ((uint32_t)(n) << CCM_CCR_OSCNT_SHIFT)
+                                                           /* Bits 8-11:  Reserved */
+#define CCM_CCR_COSC_EN                          (1 << 12) /* Bit  12:    On chip oscillator enable */
+                                                           /* Bits 13-20: Reserved */
+#define CCM_CCR_REG_BYPASS_COUNT_SHIFT           (21)      /* Bits 21-26: Counter for analog_reg_bypass */
+#define CCM_CCR_REG_BYPASS_COUNT_MASK            (0x3f << CCM_CCR_REG_BYPASS_COUNT_SHIFT)
+#  define CCM_CCR_REG_BYPASS_COUNT(n)            ((uint32_t)(n) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)
+#define CCM_CCR_RBC_EN                           (1 << 27) /* Bit  27:    Enable for REG_BYPASS_COUNTER */
+                                                           /* Bits 28-31: Reserved */
+/*  Status Register  */
+
+#define CCM_CSR_REF_EN_B                         (1 << 0)  /* Bit 0:      Status of the value of CCM_REF_EN_B */
+                                                           /* Bits 1-2:   Reserved */
+#define CCM_CSR_CAMP2_READY                      (3 << 0)  /* Bit 3:      Status indication of CAMP2 */
+                                                           /* Bit 4:      Reserved */
+#define CCM_CSR_COSC_READY                       (5 << 0)  /* Bit 5:      Status indication of on board oscillator */
+                                                           /* Bits 6-31:  Reserved */
+/* Clock Switcher Register */
+
+#define CCM_CCSR_PLL3_SW_CLK_SEL                 (1 << 0)  /* Bit 0: Selects source to generate pll3_sw_clk */
+
+/* Arm Clock Root Register */
+
+#define CCM_CACRR_ARM_PODF_SHIFT                 (0)       /* Bits 0-2:   Divider for ARM clock root */
+#define CCM_CACRR_ARM_PODF_MASK                  (0x7 << CCM_CACRR_ARM_PODF_SHIFT)
+#  define CCM_CACRR_ARM_PODF(n)                  ((uint32_t)(n) << CCM_CACRR_ARM_PODF_SHIFT)
+
+/* Bus Clock Divider Register */
+
+                                                           /* Bits 0-5:   Reserved */
+#define CCM_CBCDR_SEMC_CLK_SEL                   (1 << 6)  /* Bit 6:      SEMC clock source select */
+#define CCM_CBCDR_SEMC_ALT_CLK_SEL               (1 << 7)  /* Bit 7:      SEMC alternative clock select */
+#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2          (0 << 7)  /* Bit 7:      PLL2 PFD2 will be selected */
+#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL3          (1 << 7)  /* Bit 7:      PLL3 PFD1 will be selected  */
+#define CCM_CBCDR_IPG_PODF_SHIFT                 (8)       /* Bits 8-9:   Divider for ipg podf */
+#define CCM_CBCDR_IPG_PODF_MASK                  (0x3 << CCM_CBCDR_IPG_PODF_SHIFT)
+#  define CCM_CBCDR_IPG_PODF(n)                  ((uint32_t)(n) << CCM_CBCDR_IPG_PODF_SHIFT)
+#define CCM_CBCDR_AHB_PODF_SHIFT                 (10)      /* Bits 10-12: Divider for AHB PODF */
+#define CCM_CBCDR_AHB_PODF_MASK                  (0x7 << CCM_CBCDR_AHB_PODF_SHIFT)
+#  define CCM_CBCDR_AHB_PODF(n)                  ((uint32_t)(n) << CCM_CBCDR_AHB_PODF_SHIFT)
+                                                           /* Bits 13-15: Reserved */
+#define CCM_CBCDR_SEMC_PODF_SHIFT                (16)      /* Bits 16-18: Post divider for SEMC clock */
+#define CCM_CBCDR_SEMC_PODF_MASK                 (0x7 << CCM_CBCDR_SEMC_PODF_SHIFT)
+# define CCM_CBCDR_SEMC_PODF(n)                  ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT)
+                                                           /* Bits 19-24: Reserved */
+#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT           (25)      /* Bit 25:     Selector for peripheral main clock */
+#define CCM_CBCDR_PERIPH_CLK_SEL_MASK            (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)
+#  define CCM_CBCDR_PERIPH_CLK_SEL(n)            ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)
+#  define CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH    (0)
+#  define CCM_CBCDR_PERIPH_CLK_SEL_PERIPH_CLK2   (1)
+
+                                                           /* Bit 26:     Reserved */
+#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT         (27)      /* Bits 27-29: Divider for periph_clk2_podf */
+#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK          (0x7 << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)
+#  define CCM_CBCDR_PERIPH_CLK2_PODF(n)          ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)
+                                                          /* Bits 30-31: Reserved */
+
+/* Bus Clock Multiplexer Register */
+
+                                                           /* Bits 0-3:   Reserved */
+#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT            (4)       /* Bits 4-5:   Selector for lpspi clock multiplexer */
+#define CCM_CBCMR_LPSPI_CLK_SEL_MASK             (0x3 << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_LPSPI_CLK_SEL(n)             ((uint32_t)(n) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD1      ((uint32_t)(0) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0      ((uint32_t)(1) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_LPSPI_CLK_SEL_PLL2           ((uint32_t)(2) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_LPSPI_CLK_SEL_PLL2_PFD2      ((uint32_t)(3) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)
+                                                           /* Bits 6-11:  Reserved */
+#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT          (12)      /* Bits 12-13: Selector for peripheral clk2 clock multiplexer */
+#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK           (0x3 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)
+#  define CCM_CBCMR_PERIPH_CLK2_SEL(n)           ((uint32_t)(n) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)
+#  define CCM_CBCMR_PERIPH_CLK2_SEL_PLL3_SW      ((uint32_t)(0) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)
+#  define CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK      ((uint32_t)(1) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)
+#  define CCM_CBCMR_PERIPH_CLK2_SEL_PLL2_BP      ((uint32_t)(2) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)
+#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT            (14)      /* Bits 14-15: Selector for Trace clock multiplexer */
+#define CCM_CBCMR_TRACE_CLK_SEL_MASK             (0x3 << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_TRACE_CLK_SEL(n)             ((uint32_t)(n) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_TRACE_CLK_SEL_PLL2           ((uint32_t)(0) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD2      ((uint32_t)(1) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD0      ((uint32_t)(2) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD1      ((uint32_t)(3) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)
+                                                           /* Bits 16-17: Reserved */
+#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT       (18)      /* Bits 18-19: Selector for pre_periph clock multiplexer */
+#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK        (0x3 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_PRE_PERIPH_CLK_SEL(n)        ((uint32_t)(n) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2      (0)
+#  define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL3_PFD3 (1)
+#  define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD3 (2)
+#  define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL6      (3)
+                                                           /* Bits 20-25: Reserved */
+#define CCM_CBCMR_LPSPI_PODF_SHIFT               (26)      /* Bits 26-28: Divider for LPSPI */
+#define CCM_CBCMR_LPSPI_PODF_MASK                (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT)
+#  define CCM_CBCMR_LPSPI_PODF(n)                ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT)
+
+/* Serial Clock Multiplexer Register 1 */
+
+#define CCM_CSCMR1_PERCLK_PODF_SHIFT             (0)       /* Bits 0-5:   Divider for perclk podf  */
+#define CCM_CSCMR1_PERCLK_PODF_MASK              (0x3f << CCM_CSCMR1_PERCLK_PODF_SHIFT)
+#  define CCM_CSCMR1_PERCLK_PODF(n)              ((uint32_t)(n) << CCM_CSCMR1_PERCLK_PODF_SHIFT)
+#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT          (6)       /* Bit 6:      Selector for the perclk clock multiplexer */
+#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK           (1 << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_PERCLK_CLK_SEL(n)           ((uint32_t)(n) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_PERCLK_CLK_SEL_IPG_CLK_ROOT (0)
+#  define CCM_CSCMR1_PERCLK_CLK_SEL_OSC_CLK      (1)
+                                                           /* Bits 7-9:   Reserved */
+#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT            (10)      /* Bits 10-11: Selector for sai1 clock multiplexer */
+#define CCM_CSCMR1_SAI1_CLK_SEL_MASK             (0x3 << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI1_CLK_SEL(n)             ((uint32_t)(n) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI1_CLK_SEL_PLL3_PFD2      ((uint32_t)(0) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI1_CLK_SEL_PLL4           ((uint32_t)(2) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)
+#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT            (12)      /* Bits 12-13: Selector for sai2 clock multiplexer */
+#define CCM_CSCMR1_SAI2_CLK_SEL_MASK             (0x3 << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI2_CLK_SEL(n)             ((uint32_t)(n) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI2_CLK_SEL_PLL3_PFD2      ((uint32_t)(0) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI2_CLK_SEL_PLL4           ((uint32_t)(2) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)
+#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT            (14)      /* Bits 14-15: Selector for sai3 clock multiplexer */
+#define CCM_CSCMR1_SAI3_CLK_SEL_MASK             (0x3 << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI3_CLK_SEL(n)             ((uint32_t)(n) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI3_CLK_SEL_PLL3_PFD2      ((uint32_t)(0) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI3_CLK_SEL_PLL4           ((uint32_t)(2) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)
+#define CCM_CSCMR1_USDHC1_CLK_SEL                (1 << 16) /* Bit 16:     Selector for usdhc1 clock multiplexer */
+#  define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD2    (0 << 16) /* derive clock from PLL2 PFD2 */
+#  define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD0    (1 << 16) /* derive clock from PLL2 PFD0 */
+#define CCM_CSCMR1_USDHC2_CLK_SEL                (1 << 17) /* Bit 17:     Selector for usdhc2 clock multiplexer */
+#  define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD2    (0 << 17) /* derive clock from PLL2 PFD2 */
+#  define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD0    (1 << 17) /* derive clock from PLL2 PFD0 */
+                                                           /* Bits 18-22: Reserved */
+#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT            (23)      /* Bits 23-25: Divider for flexspi clock root */
+#define CCM_CSCMR1_FLEXSPI_PODF_MASK             (0x7 << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)
+#  define CCM_CSCMR1_FLEXSPI_PODF(n)             ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)
+                                                           /* Bits 26-28: Reserved */
+#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT         (29)      /* Bits 29-30: Selector for flexspi clock multiplexer */
+#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK          (0x3 << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_FLEXSPI_CLK_SEL(n)          ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_FLEXSPI_CLK_SEL_SEMC_CLK    ((uint32_t)(0) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_SW     ((uint32_t)(1) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL2_PFD2   ((uint32_t)(2) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_PFD0   ((uint32_t)(3) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)
+                                                           /* Bit 31:     Reserved */
+/* Serial Clock Multiplexer Register 2 */
+
+#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT            (2)       /* Bits 2-7:   Divider for can clock podf */
+#define CCM_CSCMR2_CAN_CLK_PODF_MASK             (0x3f << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)
+#  define CCM_CSCMR2_CAN_CLK_PODF(n)             ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)
+#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT             (8)       /* Bits 8-9:   Selector for FlexCAN clock multiplexer */
+#define CCM_CSCMR2_CAN_CLK_SEL_MASK              (0x3 << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_CAN_CLK_SEL(n)              ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_60      ((uint32_t)(0) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_CAN_CLK_SEL_OSC_CLK         ((uint32_t)(1) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_80      ((uint32_t)(2) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)
+                                                           /* Bits 10-18: Reserved */
+#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT         (19)      /* Bits 19-20: Selector for flexio2 clock multiplexer */
+#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK          (0x3 << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_FLEXIO2_CLK_SEL(n)          ((uint32_t)(n) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL4        ((uint32_t)(0) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_PFD2   ((uint32_t)(1) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_SW     ((uint32_t)(3) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)
+                                                           /* Bits 21-31: Reserved */
+
+/* Serial Clock Divider Register 1 */
+
+#define CCM_CSCDR1_UART_CLK_PODF_SHIFT           (0)       /* Bits 0-5:   Divider for uart clock podf */
+#define CCM_CSCDR1_UART_CLK_PODF_MASK            (0x3f << CCM_CSCDR1_UART_CLK_PODF_SHIFT)
+#  define CCM_CSCDR1_UART_CLK_PODF(n)            ((uint32_t)(n) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)
+#define CCM_CSCDR1_UART_CLK_SEL                  (1 << 6)  /* Bit 6:      Selector for the UART clock multiplexer */
+#  define CCM_CSCDR1_UART_CLK_SEL_PLL3_80        (0 << 6)  /* derive clock from pll3_80m */
+#  define CCM_CSCDR1_UART_CLK_SEL_OSC_CLK        (1 << 6)  /* derive clock from osc_clk */
+                                                           /* Bits 7-10:  Reserved */
+#define CCM_CSCDR1_USDHC1_PODF_SHIFT             (11)      /* Bits 11-13: Divider for usdhc1 clock podf */
+#define CCM_CSCDR1_USDHC1_PODF_MASK              (0x7 << CCM_CSCDR1_USDHC1_PODF_SHIFT)
+#  define CCM_CSCDR1_USDHC1_PODF(n)              ((uint32_t)(n) << CCM_CSCDR1_USDHC1_PODF_SHIFT)
+                                                           /* Bits 14-15: Reserved */
+#define CCM_CSCDR1_USDHC2_PODF_SHIFT             (16)      /* Bits 16-18: Divider for usdhc2 clock */
+#define CCM_CSCDR1_USDHC2_PODF_MASK              (0x7 << CCM_CSCDR1_USDHC2_PODF_SHIFT)
+#  define CCM_CSCDR1_USDHC2_PODF(n)              ((uint32_t)(n) << CCM_CSCDR1_USDHC2_PODF_SHIFT)
+                                                           /* Bits 19-24: Reserved */
+#define CCM_CSCDR1_TRACE_PODF_SHIFT              (25)      /* Bits 25-27: Divider for trace clock */
+#  define CCM_CSCDR1_TRACE_PODF_MASK             (0x3 << CCM_CSCDR1_TRACE_PODF_SHIFT)
+                                                           /* Bits 27-31: Reserved */
+#  define CCM_CSCDR1_TRACE_PODF(n)               ((uint32_t)(n) << CCM_CSCDR1_TRACE_PODF_SHIFT)
+
+/*  Clock Divider Register 1 */
+
+#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT           (0)       /* Bits 0-5:   Divider for sai1 clock podf */
+#define CCM_CS1CDR_SAI1_CLK_PODF_MASK            (0x3f << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)
+#  define CCM_CS1CDR_SAI1_CLK_PODF(n)            ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)
+#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT           (6)       /* Bits 6-8:   Divider for sai1 clock pred */
+#define CCM_CS1CDR_SAI1_CLK_PRED_MASK            (0x7 << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)
+#  define CCM_CS1CDR_SAI1_CLK_PRED(n)            ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)
+#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT        (9)       /* Bits 9-11:  Divider for flexio2 clock */
+#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK         (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)
+#  define CCM_CS1CDR_FLEXIO2_CLK_PRED(n)         ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)
+                                                           /* Bits 12-15: Reserved */
+#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT           (16)      /* Bits 16-21: Divider for sai3 clock podf */
+#define CCM_CS1CDR_SAI3_CLK_PODF_MASK            (0x3f << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)
+#  define CCM_CS1CDR_SAI3_CLK_PODF(n)            ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)
+#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT           (22)      /* Bits 22-24:   Divider for sai3 clock pred */
+#define CCM_CS1CDR_SAI3_CLK_PRED_MASK            (0x7 << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)
+#  define CCM_CS1CDR_SAI3_CLK_PRED(n)            ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)
+#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT        (25)      /* Bits 25-27:  Divider for flexio2 clock */
+#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK         (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)
+#  define CCM_CS1CDR_FLEXIO2_CLK_PODF(n)         ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)
+                                                           /* Bits 28-31: Reserved */
+/*  Clock Divider Register 2 */
+
+#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT           (0)       /* Bits 0-5:   Divider for sai2 clock podf */
+#define CCM_CS2CDR_SAI2_CLK_PODF_MASK            (0x3f << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)
+#  define CCM_CS2CDR_SAI2_CLK_PODF(n)            ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)
+#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT           (6)       /* Bits 6-8:   Divider for sai2 clock pred */
+#define CCM_CS2CDR_SAI2_CLK_PRED_MASK            (0x7 << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)
+#  define CCM_CS2CDR_SAI2_CLK_PRED(n)            ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)
+
+/* D1 Clock Divider Register */
+
+#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT           (20)      /* Bits 20-21: Selector for spdif0 clock multiplexer */
+#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK            (0x3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)
+#  define CCM_CDCDR_SPDIF0_CLK_SEL(n)            ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)
+#  define CCM_CDCDR_SPDIF0_CLK_SEL_PLL4          ((uint32_t)(0) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)
+#  define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD2     ((uint32_t)(1) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)
+#  define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL3_SW  ((uint32_t)(3) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)
+#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT          (22)      /* Bits 22-24: Divider for spdif0 clock podf */
+#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK           (0x7 << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)
+#  define CCM_CDCDR_SPDIF0_CLK_PODF(n)           ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)
+#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT          (25)      /* Bits 25-27: Divider for spdif0 clock pred */
+#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK           (0x7 << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)
+#  define CCM_CDCDR_SPDIF0_CLK_PRED(n)           ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)
+
+/* Serial Clock Divider Register 2 */
+
+                                                           /* Bits 0-17:  Reserved */
+#define CCM_CSCDR2_LPI2C_CLK_SEL                 (1 << 18) /* Bit 18:     Selector for the LPI2C clock multiplexer */
+#  define CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M      (0 << 18) /*  derive clock from pll3_60m */
+#  define CCM_CSCDR2_LPI2C_CLK_SEL_OSC_CLK       (1 << 18) /*  derive clock from ock_clk */
+#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT          (19)      /* Bits 19-24: Divider for lpi2c clock podf */
+#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK           (0x3f << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)
+#  define CCM_CSCDR2_LPI2C_CLK_PODF(n)           ((uint32_t)(n) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)
+                                                           /* Bits 25-31: Reserved */
+
+/* Divider Handshake In-Process Register */
+
+#define CCM_CDHIPR_SEMC_PODF_BUSY                (1 << 0)  /* Bit 0:      Busy indicator for semc_podf */
+#define CCM_CDHIPR_AHB_PODF_BUSY                 (1 << 1)  /* Bit 1:      Busy indicator for ahb_podf */
+                                                           /* Bit 2:      Reserved */
+#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY          (1 << 3)  /* Bit 3:      Busy indicator for periph2_clk_sel mux control */
+                                                           /* Bit 4:      Reserved */
+#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY           (1 << 5)  /* Bit 5:      Busy indicator for periph_clk_sel mux control */
+                                                           /* Bits 6-15:  Reserved */
+#define CCM_CDHIPR_ARM_PODF_BUSY                 (1 << 16) /* Bit 16:     Busy indicator for arm_podf */
+                                                           /* Bits 17-31: Reserved */
+
+/* Low Power Control Register */
+
+#define CCM_CLPCR_LPM_SHIFT                      (0)       /* Bits 0-1:   Setting the low power mode */
+#define CCM_CLPCR_LPM_MASK                       (0x3 << CCM_CLPCR_LPM_SHIFT)
+#  define CCM_CLPCR_LPM(n)                       ((uint32_t)(n) << CCM_CLPCR_LPM_SHIFT)
+#  define CCM_CLPCR_LPM_RUN                      ((uint32_t)(0) << CCM_CLPCR_LPM_SHIFT) /* Remain in run mode */
+#  define CCM_CLPCR_LPM_WAIT                     ((uint32_t)(1) << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */
+#  define CCM_CLPCR_LPM_STOP                     ((uint32_t)(2) << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */
+                                                           /* Bits 2-4:   Reserved */
+#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM             (1 << 5)  /* Bit 5:      ARM clocks disabled on wait mode */
+#define CCM_CLPCR_SBYOS                          (1 << 6)  /* Bit 6:      Standby clock oscillator bit */
+#define CCM_CLPCR_DIS_REF_OSC                    (1 << 7)  /* Bit 7:      external high frequency oscillator disable */
+#define CCM_CLPCR_VSTBY                          (1 << 8)  /* Bit 8:      Voltage standby request bit */
+#define CCM_CLPCR_STBY_COUNT_SHIFT               (9)       /* Bits 9-10:  Standby counter definition */
+#define CCM_CLPCR_STBY_COUNT_MASK                (0x3 << CCM_CLPCR_STBY_COUNT_SHIFT)
+#  define CCM_CLPCR_STBY_COUNT(n)                ((uint32_t)(n) << CCM_CLPCR_STBY_COUNT_SHIFT)
+#define CCM_CLPCR_COSC_PWRDOWN                   (1 << 11) /* Bit 11:     On chip oscillator power down */
+                                                           /* Bits 12-18: Reserved */
+#define CCM_CLPCR_BYPASS_LPM_HS1                 (1 << 19) /* Bit 19:     Bypass low power mode handshake */
+                                                           /* Bit 20:     Reserved */
+#define CCM_CLPCR_BYPASS_LPM_HS0                 (1 << 21) /* Bit 21:     Bypass low power mode handshake */
+#define CCM_CLPCR_MASK_CORE0_WFI                 (1 << 22) /* Bit 22:     Mask WFI of core0 for entering low power mode */
+                                                           /* Bits 23-25: Reserved */
+#define CCM_CLPCR_MASK_SCU_IDLE                  (1 << 26) /* Bit 26:     Mask SCU IDLE for entering low power mode */
+#define CCM_CLPCR_MASK_L2CC_IDLE                 (1 << 27) /* Bit 27:     Mask L2CC IDLE for entering low power mode */
+                                                           /* Bits 28-31: Reserved */
+
+/* Interrupt Status Register */
+
+#define CCM_CISR_LRF_PLL                         (1 << 0)  /* Bit 0:      CCM irq2, lock of all enabled and not bypassed PLLs */
+                                                           /* Bits 1-5:   Reserved */
+#define CCM_CISR_COSC_READY                      (1 << 6)  /* Bit 6:      CCM irq2, on board oscillator ready */
+                                                           /* Bits 7-16:  Reserved */
+#define CCM_CISR_SEMC_PODF_LOADED                (1 << 17) /* Bit 17:     CCM irq1, frequency change of semc_podf */
+                                                           /* Bit 18:     Reserved */
+#define CCM_CISR_PERIPH2_CLK_SEL_LOADED          (1 << 19) /* Bit 19:     CCM irq1, frequency change of periph2_clk_sel */
+#define CCM_CISR_AHB_PODF_LOADED                 (1 << 20) /* Bit 20:     CCM irq1, frequency change of ahb_podf */
+                                                           /* Bit 21:     Reserved */
+#define CCM_CISR_PERIPH_CLK_SEL_LOADED           (1 << 22) /* Bit 22:     CCM irq1, update of periph_clk_sel */
+                                                           /* Bits 23-25: Reserved */
+#define CCM_CISR_ARM_PODF_LOADED                 (1 << 26) /* Bit 26:     CCM irq1, frequency change of arm_podf */
+                                                           /* Bits 27-31: Reserved */
+
+/* Interrupt Mask Register */
+
+#define CCM_CIMR_MASK_LRF_PLL                    (1 << 0)  /* Bit 0:      mask interrupt generation due to lrf of PLLs */
+                                                           /* Bits 1-5:   Reserved */
+#define CCM_CIMR_MASK_COSC_READY                 (1 << 6)  /* Bit 6:      mask interrupt generation due to on board oscillator ready */
+                                                           /* Bits 7-16:  Reserved */
+#define CCM_CIMR_MASK_SEMC_PODF_LOADED           (1 << 17) /* Bit 17:     mask interrupt generation due to frequency change of semc_podf */
+                                                           /* Bit 18:     Reserved */
+#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED     (1 << 19) /* Bit 19:     mask interrupt generation due to update of periph2_clk_sel */
+#define CCM_CIMR_MASK_AHB_PODF_LOADED            (1 << 20) /* Bit 20:     mask interrupt generation due to frequency change of ahb_podf */
+                                                           /* Bit 21:     Reserved */
+#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED      (1 << 22) /* Bit 22:     mask interrupt generation due to update of periph_clk_sel */
+                                                           /* Bits 23-25: Reserved */
+#define CCM_CIMR_MASK_ARM_PODF_LOADED            (1 << 26) /* Bit 26:     mask interrupt generation due to frequency change of arm_podf */
+                                                           /* Bits 27-31: Reserved */
+
+/*  Clock Output Source Register */
+
+#define CCM_CCOSR_CLKO1_SEL_SHIFT                (0)       /* Bits 0-3:   Selection of the clock to be generated on CCM_CLKO1 */
+#define CCM_CCOSR_CLKO1_SEL_MASK                 (0xF << CCM_CCOSR_CLKO1_SEL_SHIFT)
+
+#  define CCM_CCOSR_CLKO1_SEL_PLL3_SW_DIV2_CLK   ((uint32_t)(0) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO1_SEL_PLL2_DIV2_CLK      ((uint32_t)(1) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO1_SEL_ENET_PLL_DIV2_CLK  ((uint32_t)(2) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO1_SEL_SEMC_CLK           ((uint32_t)(5) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO1_SEL_AHB_CLK            ((uint32_t)(11) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO1_SEL_IPG_CLK            ((uint32_t)(12) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO1_SEL_PER_CLK            ((uint32_t)(13) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO1_SEL_PLL4_MAIN_CLK      ((uint32_t)(15) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+
+#define CCM_CCOSR_CLKO1_DIV_SHIFT                (4)       /* Bits 4-6:   Setting the divider of CCM_CLKO1 */
+#define CCM_CCOSR_CLKO1_DIV_MASK                 (0x7 << CCM_CCOSR_CLKO1_DIV_SHIFT)
+#  define CCM_CCOSR_CLKO1_DIV(n)                 ((uint32_t)(n) << CCM_CCOSR_CLKO1_DIV_SHIFT)
+#define CCM_CCOSR_CLKO1_EN                       (1 << 7)  /* Bit 7:      Enable of CCM_CLKO1 clock */
+#define CCM_CCOSR_CLK_OUT_SEL                    (1 << 8)  /* Bit 8:      CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks */
+                                                           /* Bits 9-15:  Reserved */
+#define CCM_CCOSR_CLKO2_SEL_SHIFT                (16)      /* Bits 16-20: Selection of the clock to be generated on CCM_CLKO2 */
+#define CCM_CCOSR_CLKO2_SEL_MASK                 (0x1F << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_USDHC1_CLK         ((uint32_t)(3) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_LPI2C_CLK          ((uint32_t)(6) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_OSC_CLK            ((uint32_t)(14) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_USDHC2_CLK         ((uint32_t)(17) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_SAI1_CLK           ((uint32_t)(18) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_SAI2_CLK           ((uint32_t)(19) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_SAI3_CLK           ((uint32_t)(20) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_TRACE_CLK          ((uint32_t)(22) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_CAN_CLK            ((uint32_t)(23) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_FLEXSPI_CLK        ((uint32_t)(27) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_UART_CLK           ((uint32_t)(28) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_SPDIF0_CLK         ((uint32_t)(29) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+
+#define CCM_CCOSR_CLKO2_DIV_SHIFT                (21)      /* Bits 21-23: Setting the divider of CCM_CLKO2 */
+#define CCM_CCOSR_CLKO2_DIV_MASK                 (0x7 << CCM_CCOSR_CLKO2_DIV_SHIFT)
+#  define CCM_CCOSR_CLKO2_DIV(n)                 ((uint32_t)(n) << CCM_CCOSR_CLKO2_DIV_SHIFT)
+#define CCM_CCOSR_CLKO2_EN                       (1 << 24) /* Bit 24:     Enable of CCM_CLKO2 clock */
+                                                           /* Bits 25-31: Reserved */
+
+/* General Purpose Register */
+
+#define CCM_CGPR_PMIC_DELAY_SCALER               (1 << 0)  /* Bit 0:      Defines clock division of clock for stby_count */
+                                                           /* Bits 1-3:   Reserved */
+#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE          (1 << 4)  /* Bit 4:      allow fuse programing */
+                                                           /* Bits 5-13:  Reserved */
+#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT           (14)      /* Bits 14-15: System memory DS control */
+#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK            (0x7 << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)
+#  define CCM_CGPR_SYS_MEM_DS_CTRL(n)            ((uint32_t)(n) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)
+#define CCM_CGPR_FPL                             (1 << 16) /* Bit 16:     Fast PLL enable */
+#define CCM_CGPR_INT_MEM_CLK_LPM                 (1 << 17) /* Bit 17:     Control for the Deep Sleep signal to the ARM Platform memories */
+                                                           /* Bits 18-31: Reserved */
+
+/* Clock Gating Register 0-6 */
+
+#define CCM_CG_OFF                               (0)  /* Clock is off during all modes */
+#define CCM_CG_RUN                               (1)  /* Clock is on in run mode, but off in WAIT and STOP modes */
+#define CCM_CG_ALL                               (3)  /* Clock is on during all modes, except STOP mode. */
+
+#define CCM_CCGRX_CG_SHIFT(r)                    ((r) << 1)
+#define CCM_CCGRX_CG_MASK(r)                     (0x3 << CCM_CCGRX_CG_SHIFT(r))
+#  define CCM_CCGRX_CG(r,v)                      ((uint32_t)(v) << CCM_CCGRX_CG_SHIFT(r))
+
+#define CCM_CCGRX_CG0_SHIFT                      (0)
+#define CCM_CCGRX_CG0_MASK                       (0x3 << CCM_CCGRX_CG0_SHIFT)
+#  define CCM_CCGRX_CG0(n)                       ((uint32_t)(n) << CCM_CCGRX_CG0_SHIFT)
+#define CCM_CCGRX_CG1_SHIFT                      (2)
+#define CCM_CCGRX_CG1_MASK                       (0x3 << CCM_CCGRX_CG1_SHIFT)
+#  define CCM_CCGRX_CG1(n)                       ((uint32_t)(n) << CCM_CCGRX_CG1_SHIFT)
+#define CCM_CCGRX_CG2_SHIFT                      (4)
+#define CCM_CCGRX_CG2_MASK                       (0x3 << CCM_CCGRX_CG2_SHIFT)
+#  define CCM_CCGRX_CG2(n)                       ((uint32_t)(n) << CCM_CCGRX_CG2_SHIFT)
+#define CCM_CCGRX_CG3_SHIFT                      (6)
+#define CCM_CCGRX_CG3_MASK                       (0x3 << CCM_CCGRX_CG3_SHIFT)
+#  define CCM_CCGRX_CG3(n)                       ((uint32_t)(n) << CCM_CCGRX_CG3_SHIFT)
+#define CCM_CCGRX_CG4_SHIFT                      (8)
+#define CCM_CCGRX_CG4_MASK                       (0x3 << CCM_CCGRX_CG4_SHIFT)
+#  define CCM_CCGRX_CG4(n)                       ((uint32_t)(n) << CCM_CCGRX_CG4_SHIFT)
+#define CCM_CCGRX_CG5_SHIFT                      (10)
+#define CCM_CCGRX_CG5_MASK                       (0x3 << CCM_CCGRX_CG5_SHIFT)
+#  define CCM_CCGRX_CG5(n)                       ((uint32_t)(n) << CCM_CCGRX_CG5_SHIFT)
+#define CCM_CCGRX_CG6_SHIFT                      (12)
+#define CCM_CCGRX_CG6_MASK                       (0x3 << CCM_CCGRX_CG6_SHIFT)
+#  define CCM_CCGRX_CG6(n)                       ((uint32_t)(n) << CCM_CCGRX_CG6_SHIFT)
+#define CCM_CCGRX_CG7_SHIFT                      (14)
+#define CCM_CCGRX_CG7_MASK                       (0x3 << CCM_CCGRX_CG7_SHIFT)
+#  define CCM_CCGRX_CG7(n)                       ((uint32_t)(n) << CCM_CCGRX_CG7_SHIFT)
+#define CCM_CCGRX_CG8_SHIFT                      (16)
+#define CCM_CCGRX_CG8_MASK                       (0x3 << CCM_CCGRX_CG8_SHIFT)
+#  define CCM_CCGRX_CG8(n)                       ((uint32_t)(n) << CCM_CCGRX_CG8_SHIFT)
+#define CCM_CCGRX_CG9_SHIFT                      (18)
+#define CCM_CCGRX_CG9_MASK                       (0x3 << CCM_CCGRX_CG9_SHIFT)
+#  define CCM_CCGRX_CG9(n)                       ((uint32_t)(n) << CCM_CCGRX_CG9_SHIFT)
+#define CCM_CCGRX_CG10_SHIFT                     (20)
+#define CCM_CCGRX_CG10_MASK                      (0x3 << CCM_CCGRX_CG10_SHIFT)
+#  define CCM_CCGRX_CG10(n)                      ((uint32_t)(n) << CCM_CCGRX_CG10_SHIFT)
+#define CCM_CCGRX_CG11_SHIFT                     (22)
+#define CCM_CCGRX_CG11_MASK                      (0x3 << CCM_CCGRX_CG11_SHIFT)
+#  define CCM_CCGRX_CG11(n)                      ((uint32_t)(n) << CCM_CCGRX_CG11_SHIFT)
+#define CCM_CCGRX_CG12_SHIFT                     (24)
+#define CCM_CCGRX_CG12_MASK                      (0x3 << CCM_CCGRX_CG12_SHIFT)
+#  define CCM_CCGRX_CG12(n)                      ((uint32_t)(n) << CCM_CCGRX_CG12_SHIFT)
+#define CCM_CCGRX_CG13_SHIFT                     (26)
+#define CCM_CCGRX_CG13_MASK                      (0x3 << CCM_CCGRX_CG13_SHIFT)
+#  define CCM_CCGRX_CG13(n)                      ((uint32_t)(n) << CCM_CCGRX_CG13_SHIFT)
+#define CCM_CCGRX_CG14_SHIFT                     (28)
+#define CCM_CCGRX_CG14_MASK                      (0x3 << CCM_CCGRX_CG14_SHIFT)
+#  define CCM_CCGRX_CG14(n)                      ((uint32_t)(n) << CCM_CCGRX_CG14_SHIFT)
+#define CCM_CCGRX_CG15_SHIFT                     (30)
+#define CCM_CCGRX_CG15_MASK                      (0x3 << CCM_CCGRX_CG15_SHIFT)
+#  define CCM_CCGRX_CG15(n)                      ((uint32_t)(n) << CCM_CCGRX_CG15_SHIFT)
+
+/* Macros used by imxrt_periphclks.h */
+
+#define CCM_CCGR_GPIO2                           IMXRT_CCM_CCGR0, 15
+#define CCM_CCGR_LPUART2                         IMXRT_CCM_CCGR0, 14
+#define CCM_CCGR_GPT2_SERIAL                     IMXRT_CCM_CCGR0, 13
+#define CCM_CCGR_GPT2_BUS                        IMXRT_CCM_CCGR0, 12
+#define CCM_CCGR_TRACE                           IMXRT_CCM_CCGR0, 11
+#define CCM_CCGR_CAN2_SERIAL                     IMXRT_CCM_CCGR0, 10
+#define CCM_CCGR_CAN2                            IMXRT_CCM_CCGR0, 9
+#define CCM_CCGR_CAN1_SERIAL                     IMXRT_CCM_CCGR0, 8
+#define CCM_CCGR_CAN1                            IMXRT_CCM_CCGR0, 7
+#define CCM_CCGR_LPUART3                         IMXRT_CCM_CCGR0, 6
+#define CCM_CCGR_DCP                             IMXRT_CCM_CCGR0, 5
+#  define CCM_CCGR_SIM_M_CLK_R_CLK               IMXRT_CCM_CCGR0, 4
+                                                 /* 3 : Reserved */
+#define CCM_CCGR_MQS                             IMXRT_CCM_CCGR0, 2
+#define CCM_CCGR_AIPS_TZ2                        IMXRT_CCM_CCGR0, 1
+#define CCM_CCGR_AIPS_TZ1                        IMXRT_CCM_CCGR0, 0
+
+#  define CCM_CCGR_GPIO5                         IMXRT_CCM_CCGR1, 15
+#define CCM_CCGR_CSU                             IMXRT_CCM_CCGR1, 14
+#define CCM_CCGR_GPIO1                           IMXRT_CCM_CCGR1, 13
+#define CCM_CCGR_LPUART4                         IMXRT_CCM_CCGR1, 12
+#define CCM_CCGR_GPT_SERIAL                      IMXRT_CCM_CCGR1, 11
+#define CCM_CCGR_GPT_BUS                         IMXRT_CCM_CCGR1, 10
+#define CCM_CCGR_SEMC_EXSC                       IMXRT_CCM_CCGR1, 9
+#define CCM_CCGR_ADC1                            IMXRT_CCM_CCGR1, 8
+                                                 /* 7 : Reserved */
+#define CCM_CCGR_PIT                             IMXRT_CCM_CCGR1, 6
+#define CCM_CCGR_ENET                            IMXRT_CCM_CCGR1, 5
+#define CCM_CCGR_ADC2                            IMXRT_CCM_CCGR1, 4
+#define CCM_CCGR_LPSPI4                          IMXRT_CCM_CCGR1, 3
+#define CCM_CCGR_LPSPI3                          IMXRT_CCM_CCGR1, 2
+#define CCM_CCGR_LPSPI2                          IMXRT_CCM_CCGR1, 1
+#define CCM_CCGR_LPSPI1                          IMXRT_CCM_CCGR1, 0
+
+                                                 /* 15 : Reserved */
+                                                 /* 14 : Reserved */
+#define CCM_CCGR_GPIO3                           IMXRT_CCM_CCGR2, 13
+#define CCM_CCGR_XBAR2                           IMXRT_CCM_CCGR2, 12
+#define CCM_CCGR_XBAR1                           IMXRT_CCM_CCGR2, 11
+                                                 /* 10 : Reserved */
+                                                 /* 9  : Reserved */
+                                                 /* 8  : Reserved */
+                                                 /* 7  : Reserved */
+#define CCM_CCGR_OCOTP_CTRL                      IMXRT_CCM_CCGR2, 6
+#define CCM_CCGR_LPI2C3                          IMXRT_CCM_CCGR2, 5
+#define CCM_CCGR_LPI2C2                          IMXRT_CCM_CCGR2, 4
+#define CCM_CCGR_LPI2C1                          IMXRT_CCM_CCGR2, 3
+#define CCM_CCGR_IOMUXC_SNVS                     IMXRT_CCM_CCGR2, 2
+                                                 /* 1  : Reserved */
+#define CCM_CCGR_OCRAM_EXSC                      IMXRT_CCM_CCGR2, 0
+
+#define CCM_CCGR_IOMUXC_SNVS_GPR                 IMXRT_CCM_CCGR3, 15
+                                                 /* 14 : Reserved */
+#define CCM_CCGR_ACMP4                           IMXRT_CCM_CCGR3, 13
+#define CCM_CCGR_ACMP3                           IMXRT_CCM_CCGR3, 12
+#define CCM_CCGR_ACMP2                           IMXRT_CCM_CCGR3, 11
+#define CCM_CCGR_ACMP1                           IMXRT_CCM_CCGR3, 10
+#define CCM_CCGR_FLEXRAM                         IMXRT_CCM_CCGR3, 9
+#define CCM_CCGR_WDOG1                           IMXRT_CCM_CCGR3, 8
+#define CCM_CCGR_EWM                             IMXRT_CCM_CCGR3, 7
+                                                 /* 6  : Reserved */
+                                                 /* 5  : Reserved */
+#define CCM_CCGR_AOI1                            IMXRT_CCM_CCGR3, 4
+#define CCM_CCGR_LPUART6                         IMXRT_CCM_CCGR3, 3
+#define CCM_CCGR_SEMC                            IMXRT_CCM_CCGR3, 2
+#define CCM_CCGR_LPUART5                         IMXRT_CCM_CCGR3, 1
+                                                 /* 0  : Reserved */
+
+                                                 /* 15  : Reserved */
+                                                 /* 14  : Reserved */
+#define CCM_CCGR_ENC2                            IMXRT_CCM_CCGR4, 13
+#define CCM_CCGR_ENC1                            IMXRT_CCM_CCGR4, 12
+                                                 /* 11  : Reserved */
+                                                 /* 10  : Reserved */
+#define CCM_CCGR_PWM2                            IMXRT_CCM_CCGR4, 9
+#define CCM_CCGR_PWM1                            IMXRT_CCM_CCGR4, 8
+#define CCM_CCGR_SIM_EMS                         IMXRT_CCM_CCGR4, 7
+#define CCM_CCGR_SIM_M                           IMXRT_CCM_CCGR4, 6
+                                                 /* 5   : Reserved */
+#define CCM_CCGR_SIM_M7                          IMXRT_CCM_CCGR4, 4
+#define CCM_CCGR_BEE                             IMXRT_CCM_CCGR4, 3
+#define CCM_CCGR_IOMUXC_GPR                      IMXRT_CCM_CCGR4, 2
+#define CCM_CCGR_IOMUXC                          IMXRT_CCM_CCGR4, 1
+#define CCM_CCGR_SIM_M7_R_EN                     IMXRT_CCM_CCGR4, 0
+
+#define CCM_CCGR_SNVS_LP                         IMXRT_CCM_CCGR5, 15
+#define CCM_CCGR_SNVS_HP                         IMXRT_CCM_CCGR5, 14
+#define CCM_CCGR_LPUART7                         IMXRT_CCM_CCGR5, 13
+#define CCM_CCGR_LPUART1                         IMXRT_CCM_CCGR5, 12
+#define CCM_CCGR_SAI3                            IMXRT_CCM_CCGR5, 11
+#define CCM_CCGR_SAI2                            IMXRT_CCM_CCGR5, 10
+#define CCM_CCGR_SAI1                            IMXRT_CCM_CCGR5, 9
+                                                 /* 8   : Reserved */
+#define CCM_CCGR_SPDIF                           IMXRT_CCM_CCGR5, 7
+#define CCM_CCGR_AIPSTZ4                         IMXRT_CCM_CCGR5, 6
+#define CCM_CCGR_WDOG2                           IMXRT_CCM_CCGR5, 5
+#define CCM_CCGR_KPP                             IMXRT_CCM_CCGR5, 4
+#define CCM_CCGR_DMA                             IMXRT_CCM_CCGR5, 3
+#define CCM_CCGR_WDOG3                           IMXRT_CCM_CCGR5, 2
+#define CCM_CCGR_FLEXIO1                         IMXRT_CCM_CCGR5, 1
+#define CCM_CCGR_ROM                             IMXRT_CCM_CCGR5, 0
+
+                                                 /* 15  : Reserved */
+#define CCM_CCGR_TIMER2                          IMXRT_CCM_CCGR6, 14
+#define CCM_CCGR_TIMER1                          IMXRT_CCM_CCGR6, 13
+#define CCM_CCGR_LPI2C4_SERIAL                   IMXRT_CCM_CCGR6, 12
+#define CCM_CCGR_ANADIG                          IMXRT_CCM_CCGR6, 11
+#define CCM_CCGR_SIM_PER                         IMXRT_CCM_CCGR6, 10
+#define CCM_CCGR_AIPS_TZ3                        IMXRT_CCM_CCGR6, 9
+                                                 /* 8   : Reserved */
+#define CCM_CCGR_LPUART8                         IMXRT_CCM_CCGR6, 7
+#define CCM_CCGR_TRNG                            IMXRT_CCM_CCGR6, 6
+#define CCM_CCGR_FLEXSPI                         IMXRT_CCM_CCGR6, 5
+                                                 /* 4   : Reserved */
+#define CCM_CCGR_DCDC                            IMXRT_CCM_CCGR6, 3
+#define CCM_CCGR_USDHC2                          IMXRT_CCM_CCGR6, 2
+#define CCM_CCGR_USDHC1                          IMXRT_CCM_CCGR6, 1
+#define CCM_CCGR_USBOH3                          IMXRT_CCM_CCGR6, 0
+
+/* Module Enable Override Register */
+
+                                                           /* Bits 0-4: Reserved */
+#define CCM_CMEOR_MOD_EN_OV_GPT                  (1 << 5)  /* Bit 5:      Overide clock enable signal from GPT */
+#define CCM_CMEOR_MOD_EN_OV_PIT                  (1 << 6)  /* Bit 6:      Overide clock enable signal from PIT */
+#define CCM_CMEOR_MOD_EN_OV_USDHC                (1 << 7)  /* Bit 7:      Overide clock enable signal from USDHC */
+#define CCM_CMEOR_MOD_EN_OV_TRNG                 (1 << 9)  /* Bit 9:      Overide clock enable signal from TRNG */
+                                                           /* Bits 10-27: Reserved */
+#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI             (1 << 28) /* Bit 28:     Overide clock enable signal from CAN2 */
+#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI             (1 << 30) /* Bit 30:     Overide clock enable signal from CAN1 */
+                                                           /* Bit 31:     Reserved */
+
+/*  Analog System PLL (2) Control Register **********************************/
+
+#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT             (0)       /* Bits 0:   This field controls the PLL loop divider 20 or 22 */
+#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK              (0x3 << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_SYS_DIV_SELECT(n)              ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_SYS_DIV_SELECT_20              (0)
+#  define CCM_ANALOG_PLL_SYS_DIV_SELECT_22              (1)
+#define CCM_ANALOG_PLL_SYS_DIV_VAL(n)                  (((n)==CCM_ANALOG_PLL_SYS_DIV_SELECT_20)?20:22)
+                                                                  /* Bit 1-11:   Reserved */
+#define CCM_ANALOG_PLL_SYS_POWERDOWN                    (1 << 12) /* Bit 12:     Powers down the PLL */
+#define CCM_ANALOG_PLL_SYS_ENABLE                       (1 << 13) /* Bit 13:     Enable the PLL clock output */
+#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT         (14)      /* Bits 14-15: Determines the bypass source */
+#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK          (0x3 << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)
+#  define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_REF_24M     ((uint32_t)(0) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
+#define CCM_ANALOG_PLL_SYS_BYPASS                       (1 << 16) /* Bit 16:     Bypass the PLL */
+                                                                  /* Bits 17-30  Reserved */
+#define CCM_ANALOG_PLL_SYS_LOCK                         (1 << 31) /* Bit 31:     PLL is currently locked */
+
+/* Analog USB1 480MHz PLL (3) Control Register **********************************/
+                                                                  /* Bit 0: Reserved */
+#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT            (1)       /* Bit 1:   This field controls the PLL loop divider 20 or 22 */
+#define CCM_ANALOG_PLL_USB1_DIV_SELECT(n)               ((uint32_t)(n) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)
+#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK             CCM_ANALOG_PLL_USB1_DIV_SELECT(1)
+#define CCM_ANALOG_PLL_USB1_DIV_VAL(n)                  (((n)==CCM_ANALOG_PLL_USB1_DIV_SELECT_20)?20:22)
+#  define CCM_ANALOG_PLL_USB1_DIV_SELECT_20             (0)
+#  define CCM_ANALOG_PLL_USB1_DIV_SELECT_22             (1)
+                                                                  /* Bits 2-5    Reserved */
+#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS                 (1 << 6)  /* Bit 6:      Enable PLL outputs for USBPHYn */
+                                                                  /* Bits 7-11   Reserved */
+#define CCM_ANALOG_PLL_USB1_POWER                       (1 << 12) /* Bit 12:     Powers up the PLL */
+#define CCM_ANALOG_PLL_USB1_ENABLE                      (1 << 13) /* Bit 13:     Enable the PLL clock output */
+#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT        (14)      /* Bits 14-15: Determines the bypass source */
+#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK         (0x3 << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)
+#  define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_REF_24M    ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
+#define CCM_ANALOG_PLL_USB1_BYPASS                      (1 << 16) /* Bit 16:     Bypass the PLL */
+                                                                  /* Bits 17-30  Reserved */
+#define CCM_ANALOG_PLL_USB1_LOCK                        (1 << 31) /* Bit 31:     PLL is currently locked */
+
+/* 528MHz System PLL Spread Spectrum Register */
+
+#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT                (0)       /* Bits 0-14:  Frequency change step */
+#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK                 (0x3FFF << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)
+#  define CCM_ANALOG_PLL_SYS_SS_STEP(n)                 ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)
+#define CCM_ANALOG_PLL_SYS_SS_ENABLE                    (1 << 15) /* Bit 15:  Enable bit */
+#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT                (0)       /* Bits 16-31:  Frequency change */
+#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK                 (0xFFFF << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)
+#  define CCM_ANALOG_PLL_SYS_SS_STOP(n)                 ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)
+
+/* Numerator of 528MHz System PLL Fractional Loop Divider Register */
+
+#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT                  (0)       /* Bits 0-29:   30 bit numerator (A) */
+#define CCM_ANALOG_PLL_SYS_NUM_A_MASK                   (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)
+#define CCM_ANALOG_PLL_SYS_NUM_A(n)                     ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)
+                                                                  /* Bits 30-31:  Reserved */
+
+/* Denominator of 528MHz System PLL Fractional Loop Divider Register */
+
+#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT                (0)       /* Bits 0-29:   30 bit numerator (A) */
+#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK                 (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)
+#define CCM_ANALOG_PLL_SYS_DENOM_B(n)                   ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)
+                                                                  /* Bits 30-31:  Reserved */
+
+/*  Analog Audio PLL control Register */
+
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT           (0)       /* Bits 0-6:    This field controls the PLL loop divider: 27-54 */
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK            (0x7f << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(n)            ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)
+                                                                  /* Bits 7-11:  Reserved */
+#define CCM_ANALOG_PLL_AUDIO_POWERDOWN                  (1 << 12) /* Bit 12:     Powers down the PLL */
+#define CCM_ANALOG_PLL_AUDIO_ENABLE                     (1 << 13) /* Bit 13:     Enable PLL output */
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT       (14)      /* Bits 14-15: Determines the bypass source */
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK        (0x3 << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)
+#  define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_REF_24M   ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
+#define CCM_ANALOG_PLL_AUDIO_BYPASS                     (1 << 16) /* Bit 16:     Bypass the PLL */
+                                                                  /* Bit 17-18:  Reserved */
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT      (19)      /* Bits 19-20: These bits implement a divider after the PLL */
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK       (0x7f << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV4     ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV2     ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV1     ((uint32_t)(2) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)
+                                                                  /* Bits 21-30:  Reserved */
+#define CCM_ANALOG_PLL_AUDIO_LOCK                       (1 << 31) /* Bit 31:     PLL is currently locked */
+
+/* Numerator of Audio PLL Fractional Loop Divider Register */
+
+#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT                (0)       /* Bits 0-29:   30 bit numerator (A) */
+#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK                 (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)
+#define CCM_ANALOG_PLL_AUDIO_NUM_A(n)                   ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)
+/* Bits 30-31:  Reserved */
+
+/* Denominator of Audio PLL Fractional Loop Divider Register */
+
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT              (0)       /* Bits 0-29:   30 bit numerator (A) */
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK               (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B(n)                 ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)
+                                                                    /* Bits 30-31:  Reserved */
+/* Analog ENET PLL Control Register */
+
+#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT      (0)       /* Bits 0-1:    Controls the frequency of the ethernet0 reference clock */
+#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK       (0x3 << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_25MHZ    ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ    ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_100MHZ   ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_125MHZ   ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
+
+                                                                  /* Bits 2-11:  Reserved */
+#define CCM_ANALOG_PLL_ENET_POWERDOWN                   (1 << 12) /* Bit 12:     Powers down the PLL */
+#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN               (1 << 13) /* Bit 13:     Enable the PLL providing the ENET1 125 MHz reference clock */
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT       (14)      /* Bits 14-15: Determines the bypass source */
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK        (0x3 << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M   ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
+#define CCM_ANALOG_PLL_ENET_BYPASS                     (1 << 16) /* Bit 16:     Bypass the PLL */
+                                                                 /* Bit 17-20:  Reserved */
+#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN            (1 << 21) /* Bit 21:     Enable the PLL providing ENET 25 MHz reference clock */
+#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN           (1 << 22) /* Bit 22:     Enable the PLL providing NET 500 MHz reference clock */
+#define CCM_ANALOG_PLL_ENET_LOCK                       (1 << 31) /* Bit 31:     PLL is currently locked */
+
+/* 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
+
+#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT             (0)       /* Bits 0-5:   This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_480_PFD0_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_480_PFD0_STABLE                 (1 << 6)  /* Bit 6:      */
+#define CCM_ANALOG_PFD_480_PFD0_CLKGATE                (1 << 7)  /* Bit 7:      If set to 1, the IO fractional divider clock is off */
+#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT             (8)       /* Bits 8-13:  This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_480_PFD1_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_480_PFD1_STABLE                 (1 << 14) /* Bit 14:     */
+#define CCM_ANALOG_PFD_480_PFD1_CLKGATE                (1 << 15) /* Bit 15:     If set to 1, the IO fractional divider clock is off */
+#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT             (16)      /* Bits 8-21:  This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_480_PFD2_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_480_PFD2_STABLE                 (1 << 22) /* Bit 22:     */
+#define CCM_ANALOG_PFD_480_PFD2_CLKGATE                (1 << 23) /* Bit 23:     If set to 1, the IO fractional divider clock is off */
+#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT             (24)      /* Bits 24-29:  This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_480_PFD3_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_480_PFD3_STABLE                 (1 << 30) /* Bit 30:     */
+#define CCM_ANALOG_PFD_480_PFD3_CLKGATE                (1 << 31) /* Bit 31:     If set to 1, the IO fractional divider clock is off */
+
+/* 528MHz Clock (PLL2) Phase Fractional Divider Control */
+
+#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT             (0)       /* Bits 0-5:   This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_528_PFD0_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_528_PFD0_STABLE                 (1 << 6)  /* Bit 6:      */
+#define CCM_ANALOG_PFD_528_PFD0_CLKGATE                (1 << 7)  /* Bit 7:      If set to 1, the IO fractional divider clock is off */
+#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT             (8)       /* Bits 8-13:  This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_528_PFD1_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_528_PFD1_STABLE                 (1 << 14) /* Bit 14:     */
+#define CCM_ANALOG_PFD_528_PFD1_CLKGATE                (1 << 15) /* Bit 15:     If set to 1, the IO fractional divider clock is off */
+#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT             (16)      /* Bits 8-21:  This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_528_PFD2_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_528_PFD2_STABLE                 (1 << 22) /* Bit 22:     */
+#define CCM_ANALOG_PFD_528_PFD2_CLKGATE                (1 << 23) /* Bit 23:     If set to 1, the IO fractional divider clock is off */
+#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT             (24)      /* Bits 24-29:  This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_528_PFD3_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_528_PFD3_STABLE                 (1 << 30) /* Bit 30:     */
+#define CCM_ANALOG_PFD_528_PFD3_CLKGATE                (1 << 31) /* Bit 31:     If set to 1, the IO fractional divider clock is off */
+
+/* Miscellaneous Register 0 */
+
+#define CCM_ANALOG_MISC0_REFTOP_PWD                    (1 << 0)  /* Bit 0:      Control bit to power-down the analog bandgap reference circuitry */
+                                                                 /* Bits 1-2:   Reserved */
+#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF            (1 << 2)  /* Bit 3:      Control bit to disable the self-bias circuit in the analog bandgap */
+#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT           (4)       /* Bits 4-6:   VBG (PMU) */
+#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK            (0x7 << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)
+#  define CCM_ANALOG_MISC0_REFTOP_VBGADJ(n)            ((uint32_t)(n) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)
+#define CCM_ANALOG_MISC0_REFTOP_VBGUP                  (1 << 7)  /* Bit 7:      Status bit that signals the analog bandgap voltage is up and stable */
+                                                                 /* Bits 8-9:   Reserved */
+#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT        (10)      /* Bits 10-11: Configure the analog behavior in stop mode */
+#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK         (0x3 << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)
+#  define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(n)         ((uint32_t)(n) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)
+#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS              (1 << 12) /* Bit 12:     This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN */
+#define CCM_ANALOG_MISC0_OSC_I_SHIFT                   (13)      /* Bits 13-14: This field determines the bias current in the 24MHz oscillator */
+#define CCM_ANALOG_MISC0_OSC_I_MASK                    (0x3 << CCM_ANALOG_MISC0_OSC_I_SHIFT)
+#  define CCM_ANALOG_MISC0_OSC_I(n)                    ((uint32_t)(n) << CCM_ANALOG_MISC0_OSC_I_SHIFT)
+#define CCM_ANALOG_MISC0_OSC_XTALOK                    (1 << 15) /* Bit 15:     bit that signals 24-MHz crystal oscillator is stable */
+#define CCM_ANALOG_MISC0_OSC_XTALOK_EN                 (1 << 16) /* Bit 16:     enables the detector that signals 24MHz crystal oscillator is stable */
+                                                                 /* Bits 17-24: Reserved */
+#define CCM_ANALOG_MISC0_CLKGATE_CTRL                  (1 << 25) /* Bit 25:     This bit allows disabling the clock gate */
+#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT           (26)      /* Bits 26-28: delay powering up the XTAL 24MHz */
+#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK            (0x7 << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)
+#  define CCM_ANALOG_MISC0_CLKGATE_DELAY(n)            ((uint32_t)(n) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)
+#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE               (1 << 29) /* Bit 29:     which chip source is being used for the rtc clock */
+#define CCM_ANALOG_MISC0_XTAL_24M_PWD                  (1 << 30) /* Bit 30:     power down the 24M crystal oscillator if set true */
+                                                                 /* Bit 31:     Reserved */
+
+/* Miscellaneous Register 1 */
+
+                                                                 /* Bits 0-15:   Reserved */
+#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN           (1 << 16) /* Bit 16:      */
+#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN           (1 << 17) /* Bit 17:      */
+                                                                 /* Bits 18-26: Reserved */
+#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC                 (1 << 27) /* Bit 27:     temperature sensor panic interrupt */
+#define CCM_ANALOG_MISC1_IRQ_TEMPLOW                   (1 << 28) /* Bit 28:     temperature sensor low interrupt */
+#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH                  (1 << 29) /* Bit 29:     temperature sensor high interrupt */
+#define CCM_ANALOG_MISC1_IRQ_ANA_BO                    (1 << 30) /* Bit 30:     analog regulator brownout interrupt */
+#define CCM_ANALOG_MISC1_IRQ_DIG_BO                    (1 << 31) /* Bit 31:     digital regulator brownout interrupt */
+
+/* Miscellaneous Register 2 */
+                                                                 /* Bit 0-4:    Reserved */
+#define CCM_ANALOG_MISC2_REG0_ENABLE_BO                (1 << 5)  /* Bit 5:      Enables the brownout detection */
+#define CCM_ANALOG_MISC2_REG0_OK                       (1 << 6)  /* Bit 6:      ARM supply */
+#define CCM_ANALOG_MISC2_PLL3_DISABLE                  (1 << 7)  /* Bit 7:      PLL3 can be disabled when the SoC is not in any low power mode */
+#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT          (8)       /* Bits 8-10:  This field defines the brown out voltage offset */
+#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK           (0x7 << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)
+#  define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_100        ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)
+#  define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_175        ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)
+#define CCM_ANALOG_MISC2_REG1_BO_STATUS                (1 << 11) /* Bit 11:     Reg1 brownout status bit */
+                                                                 /* Bit 12:     Reserved */
+#define CCM_ANALOG_MISC2_REG1_ENABLE_BO                (1 << 13) /* Bit 13:     Enables the brownout detection */
+#define CCM_ANALOG_MISC2_REG1_OK                       (1 << 14) /* Bit 14:     GPU/VPU supply */
+#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB                 (1 << 15) /* Bit 15:     LSB of Post-divider for Audio PLL */
+
+#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT          (16)      /* Bits 16-18: This field defines the brown out voltage offset */
+#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK           (0x7 << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)
+#  define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_100        ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)
+#  define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_175        ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)
+#define CCM_ANALOG_MISC2_REG2_BO_STATUS                (1 << 19) /* Bit 19:     Reg2 brownout status bit */
+                                                                 /* Bit 20:     Reserved */
+#define CCM_ANALOG_MISC2_REG2_ENABLE_BO                (1 << 21) /* Bit 21:     Enables the brownout detection */
+#define CCM_ANALOG_MISC2_REG2_OK                       (1 << 22) /* Bit 22:     voltage is above the brownout level for the SOC supply */
+#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB                 (1 << 23) /* Bit 23:     MSB of Post-divider for Audio PLL */
+#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT          (24)      /* Bits 24-25: Number of clock periods (24MHz clock) */
+#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK           (0x3 << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG0_STEP_TIME_64           ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG0_STEP_TIME_128          ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG0_STEP_TIME_256          ((uint32_t)(2) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG0_STEP_TIME_512          ((uint32_t)(3) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)
+#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT          (26)      /* Bits 26-27: Number of clock periods (24MHz clock) */
+#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK           (0x3 << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG1_STEP_TIME_64           ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG1_STEP_TIME_128          ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG1_STEP_TIME_256          ((uint32_t)(2) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG1_STEP_TIME_512          ((uint32_t)(3) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)
+#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT          (28)      /* Bits 28-29: Number of clock periods (24MHz clock) */
+#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK           (0x3 << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG2_STEP_TIME_64           ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG2_STEP_TIME_128          ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG2_STEP_TIME_256          ((uint32_t)(2) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG2_STEP_TIME_512          ((uint32_t)(3) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)
+
+#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT               (30)      /* Bits 30-31: Post-divider for video */
+#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK                (0x3 << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)
+#  define CCM_ANALOG_MISC2_VIDEO_DIV(n)                ((uint32_t)(n) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_CCM_H */
diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_dmamux.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_dmamux.h
new file mode 100644
index 00000000000..b666d5846a8
--- /dev/null
+++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_dmamux.h
@@ -0,0 +1,143 @@
+/*****************************************************************************
+ * arch/arm/src/imxrt/hardware/rt102x/imxrt102x_dmamux.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *           Dave Marples 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_DMAMUX_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_DMAMUX_H
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include 
+
+/*****************************************************************************
+ * Preprocessor Definitions
+ *****************************************************************************/
+
+/* Peripheral DMA request channels */
+
+#define IMXRT_DMACHAN_FLEXIO1_01       0  /* FlexIO1 DMA 0/1, Async DMA 0/1 */
+#define IMXRT_DMACHAN_FLEXIO1_45       1  /* FlexIO1 DMA 4/5, Async DMA 4/5 */
+#define IMXRT_DMACHAN_LPUART1_TX       2  /* LPUART1 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART1_RX       3  /* LPUART1 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART3_TX       4  /* LPUART3 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART3_RX       5  /* LPUART3 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART5_TX       6  /* LPUART5 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART5_RX       7  /* LPUART5 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART7_TX       8  /* LPUART7 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART7_RX       9  /* LPUART7 RX FIFO DMA / Async DMA */
+
+#define IMXRT_DMACHAN_LPSPI1_RX       13  /* LPSPI1 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPSPI1_TX       14  /* LPSPI1 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPSPI3_RX       15  /* LPSPI3 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPSPI3_TX       16  /* LPSPI3 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPI2C1          17  /* LPI2C1 Master/Slave RX/TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPI2C3          18  /* LPI2C3 Master/Slave RX/TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_SAI1_RX         19  /* SAI1 RX FIFO DMA */
+#define IMXRT_DMACHAN_SAI1_TX         20  /* SAI1 TX FIFO DMA */
+#define IMXRT_DMACHAN_SAI2_RX         21  /* SAI2 RX FIFO DMA */
+#define IMXRT_DMACHAN_SAI2_TX         22  /* SAI2 TX FIFO DMA */
+#define IMXRT_DMACHAN_ADC_ETC         23  /* ADC ETC DMA */
+#define IMXRT_DMACHAN_ADC1            24  /* ADC1 DMA */
+#define IMXRT_DMACHAN_ACMP1           25  /* ACMP1 DMA */
+#define IMXRT_DMACHAN_ACMP3           26  /* ACMP3 DMA */
+#define IMXRT_DMACHAN_FLEXSPI_RX      28  /* FlexSPI RX FIFO DMA */
+#define IMXRT_DMACHAN_FLEXSPI_TX      29  /* FlexSPI TX FIFO DMA */
+#define IMXRT_DMACHAN_XBAR1_0         30  /* XBAR1 DMA 0 */
+#define IMXRT_DMACHAN_XBAR1_1         31  /* XBAR1 DMA 1 */
+#define IMXRT_DMACHAN_FLEXPWM1_RX0    32  /* FlexPWM1 RX sub-module0 capture */
+#define IMXRT_DMACHAN_FLEXPWM1_RX1    33  /* FlexPWM1 RX sub-module1 capture */
+#define IMXRT_DMACHAN_FLEXPWM1_RX2    34  /* FlexPWM1 RX sub-module2 capture */
+#define IMXRT_DMACHAN_FLEXPWM1_RX3    35  /* FlexPWM1 RX sub-module3 capture */
+#define IMXRT_DMACHAN_FLEXPWM1_TX0    36  /* FlexPWM1 TX sub-module0 value */
+#define IMXRT_DMACHAN_FLEXPWM1_TX1    37  /* FlexPWM1 TX sub-module1 value */
+#define IMXRT_DMACHAN_FLEXPWM1_TX2    38  /* FlexPWM1 TX sub-module2 value */
+#define IMXRT_DMACHAN_FLEXPWM1_TX3    39  /* FlexPWM1 TX sub-module3 value */
+#define IMXRT_DMACHAN_QTIMER1_RX0     48  /* QTimer1 RX capture timer 0 */
+#define IMXRT_DMACHAN_QTIMER1_RX1     49  /* QTimer1 RX capture timer 1 */
+#define IMXRT_DMACHAN_QTIMER1_RX2     50  /* QTimer1 RX capture timer 2 */
+#define IMXRT_DMACHAN_QTIMER1_RX3     51  /* QTimer1 RX capture timer 3 */
+#define IMXRT_DMACHAN_QTIMER1_TX0     52  /* QTimer1 TX cmpld1 timer 0 / cmld2 timer 1 */
+#define IMXRT_DMACHAN_QTIMER1_TX1     53  /* QTimer1 TX cmpld1 timer 1 / cmld2 timer 0 */
+#define IMXRT_DMACHAN_QTIMER1_TX2     54  /* QTimer1 TX cmpld1 timer 2 / cmld2 timer 3 */
+#define IMXRT_DMACHAN_QTIMER1_TX3     55  /* QTimer1 TX cmpld1 timer 3 / cmld2 timer 2 */
+#define IMXRT_DMACHAN_FLEXIO1_23      64  /* FlexIO1 DMA 2 / Async DMA 2 / DMA 3 / Async DMA 3 */
+#define IMXRT_DMACHAN_FLEXIO1_67      65  /* FlexIO1 DMA 6 / Async DMA 6 / DMA 7 / Async DMA 7 */
+#define IMXRT_DMACHAN_LPUART2_TX      66  /* LPUART2 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART2_RX      67  /* LPUART2 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART4_TX      68  /* LPUART4 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART4_RX      69  /* LPUART4 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART6_TX      70  /* LPUART6 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART6_RX      71  /* LPUART6 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART8_TX      72  /* LPUART8 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPUART8_RX      73  /* LPUART8 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPSPI2_RX       77  /* LPSPI2 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPSPI2_TX       78  /* LPSPI2 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPSPI4_RX       79  /* LPSPI4 RX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPSPI4_TX       80  /* LPSPI4 TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPI2C2          81  /* LPI2C2 Master/Slave RX/TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_LPI2C4          82  /* LPI2C4 Master/Slave RX/TX FIFO DMA / Async DMA */
+#define IMXRT_DMACHAN_SAI3_RX         83  /* SAI3 RX FIFO DMA */
+#define IMXRT_DMACHAN_SAI3_TX         84  /* SAI3 RX FIFO DMA */
+#define IMXRT_DMACHAN_SPDIF_RX        85  /* SPDIF RX DMA */
+#define IMXRT_DMACHAN_SPDIF_TX        86  /* SPDIF TX DMA */
+#define IMXRT_DMACHAN_ADC2            88  /* ADC2 DMA */
+#define IMXRT_DMACHAN_ACMP2           89  /* ACMP2 DMA */
+#define IMXRT_DMACHAN_ACMP4           90  /* ACMP4 DMA */
+#define IMXRT_DMACHAN_ENET_0          92  /* ENET Timer DMA 0 */
+#define IMXRT_DMACHAN_ENET_1          93  /* ENET Timer DMA 1 */
+#define IMXRT_DMACHAN_XBAR1_2         94  /* XBAR1 DMA 2 */
+#define IMXRT_DMACHAN_XBAR1_3         95  /* XBAR1 DMA 3 */
+#define IMXRT_DMACHAN_FLEXPWM2_RX0    96  /* FlexPWM2 RX sub-module0 capture */
+#define IMXRT_DMACHAN_FLEXPWM2_RX1    97  /* FlexPWM2 RX sub-module1 capture */
+#define IMXRT_DMACHAN_FLEXPWM2_RX2    98  /* FlexPWM2 RX sub-module2 capture */
+#define IMXRT_DMACHAN_FLEXPWM2_RX3    99  /* FlexPWM2 RX sub-module3 capture */
+#define IMXRT_DMACHAN_FLEXPWM2_TX0   100  /* FlexPWM2 TX sub-module0 value */
+#define IMXRT_DMACHAN_FLEXPWM2_TX1   101  /* FlexPWM2 TX sub-module1 value */
+#define IMXRT_DMACHAN_FLEXPWM2_TX2   102  /* FlexPWM2 TX sub-module2 value */
+#define IMXRT_DMACHAN_FLEXPWM2_TX3   103  /* FlexPWM2 TX sub-module3 value */
+#define IMXRT_DMACHAN_QTIMER2_RX0    112  /* QTimer2 RX capture timer 0 */
+#define IMXRT_DMACHAN_QTIMER2_RX1    113  /* QTimer2 RX capture timer 1 */
+#define IMXRT_DMACHAN_QTIMER2_RX2    114  /* QTimer2 RX capture timer 2 */
+#define IMXRT_DMACHAN_QTIMER2_RX3    115  /* QTimer2 RX capture timer 3 */
+#define IMXRT_DMACHAN_QTIMER2_TX0    116  /* QTimer2 TX cmpld1 timer 0 / cmld2 timer 1 */
+#define IMXRT_DMACHAN_QTIMER2_TX1    117  /* QTimer2 TX cmpld1 timer 1 / cmld2 timer 0 */
+#define IMXRT_DMACHAN_QTIMER2_TX2    118  /* QTimer2 TX cmpld1 timer 2 / cmld2 timer 3 */
+#define IMXRT_DMACHAN_QTIMER2_TX3    119  /* QTimer2 TX cmpld1 timer 3 / cmld2 timer 2 */
+
+#define IMXRT_DMA_NCHANNELS          128  /* Includes reserved channels */
+
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_DMAMUX_H */
diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_gpio.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_gpio.h
new file mode 100644
index 00000000000..e7f749e5e4d
--- /dev/null
+++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_gpio.h
@@ -0,0 +1,116 @@
+/*****************************************************************************
+ * arch/arm/src/imxrt/hardware/rt102x/imxrt105x_gpio.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *            David Sidrane 
+ *            Dave Marples 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_GPIO_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_GPIO_H
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include 
+#include "hardware/imxrt_memorymap.h"
+
+/*****************************************************************************
+ * Pre-processor Definitions
+ *****************************************************************************/
+
+/* Register offsets **********************************************************/
+
+#define IMXRT_GPIO_DR_OFFSET     0x0000  /* GPIO data register */
+#define IMXRT_GPIO_GDIR_OFFSET   0x0004  /* GPIO direction register */
+#define IMXRT_GPIO_PSR_OFFSET    0x0008  /* GPIO pad status register */
+#define IMXRT_GPIO_ICR1_OFFSET   0x000c  /* GPIO interrupt configuration register1 */
+#define IMXRT_GPIO_ICR2_OFFSET   0x0010  /* GPIO interrupt configuration register2 */
+#define IMXRT_GPIO_IMR_OFFSET    0x0014  /* GPIO interrupt mask register */
+#define IMXRT_GPIO_ISR_OFFSET    0x0018  /* GPIO interrupt status register */
+#define IMXRT_GPIO_EDGE_OFFSET   0x001c  /* GPIO edge select register */
+#define IMXRT_GPIO_SET_OFFSET    0x0084  /* GPIO data register SET */
+#define IMXRT_GPIO_CLEAR_OFFSET  0x0088  /* GPIO data register CLEAR */
+#define IMXRT_GPIO_TOGGLE_OFFSET 0x008c  /* GPIO data register TOGGLE */
+
+/* Register addresses ********************************************************/
+
+#define IMXRT_GPIO1_DR           (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET)
+#define IMXRT_GPIO1_GDIR         (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET)
+#define IMXRT_GPIO1_PSR          (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET)
+#define IMXRT_GPIO1_ICR1         (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET)
+#define IMXRT_GPIO1_ICR2         (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET)
+#define IMXRT_GPIO1_IMR          (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET)
+#define IMXRT_GPIO1_ISR          (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET)
+#define IMXRT_GPIO1_EDGE         (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET)
+#define IMXRT_GPIO1_SET          (IMXRT_GPIO1_BASE + IMXRT_GPIO_SET_OFFSET)
+#define IMXRT_GPIO1_CLEAR        (IMXRT_GPIO1_BASE + IMXRT_GPIO_CLEAR_OFFSET)
+#define IMXRT_GPIO1_TOGGLE       (IMXRT_GPIO1_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
+
+#define IMXRT_GPIO2_DR           (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET)
+#define IMXRT_GPIO2_GDIR         (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET)
+#define IMXRT_GPIO2_PSR          (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET)
+#define IMXRT_GPIO2_ICR1         (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET)
+#define IMXRT_GPIO2_ICR2         (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET)
+#define IMXRT_GPIO2_IMR          (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET)
+#define IMXRT_GPIO2_ISR          (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET)
+#define IMXRT_GPIO2_EDGE         (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET)
+#define IMXRT_GPIO2_SET          (IMXRT_GPIO2_BASE + IMXRT_GPIO_SET_OFFSET)
+#define IMXRT_GPIO2_CLEAR        (IMXRT_GPIO2_BASE + IMXRT_GPIO_CLEAR_OFFSET)
+#define IMXRT_GPIO2_TOGGLE       (IMXRT_GPIO2_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
+
+#define IMXRT_GPIO3_DR           (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET)
+#define IMXRT_GPIO3_GDIR         (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET)
+#define IMXRT_GPIO3_PSR          (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET)
+#define IMXRT_GPIO3_ICR1         (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET)
+#define IMXRT_GPIO3_ICR2         (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET)
+#define IMXRT_GPIO3_IMR          (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET)
+#define IMXRT_GPIO3_ISR          (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET)
+#define IMXRT_GPIO3_EDGE         (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET)
+#define IMXRT_GPIO3_SET          (IMXRT_GPIO3_BASE + IMXRT_GPIO_SET_OFFSET)
+#define IMXRT_GPIO3_CLEAR        (IMXRT_GPIO3_BASE + IMXRT_GPIO_CLEAR_OFFSET)
+#define IMXRT_GPIO3_TOGGLE       (IMXRT_GPIO3_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
+
+#define IMXRT_GPIO5_DR           (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET)
+#define IMXRT_GPIO5_GDIR         (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET)
+#define IMXRT_GPIO5_PSR          (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET)
+#define IMXRT_GPIO5_ICR1         (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET)
+#define IMXRT_GPIO5_ICR2         (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET)
+#define IMXRT_GPIO5_IMR          (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET)
+#define IMXRT_GPIO5_ISR          (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET)
+#define IMXRT_GPIO5_EDGE         (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET)
+#define IMXRT_GPIO5_SET          (IMXRT_GPIO5_BASE + IMXRT_GPIO_SET_OFFSET)
+#define IMXRT_GPIO5_CLEAR        (IMXRT_GPIO5_BASE + IMXRT_GPIO_CLEAR_OFFSET)
+#define IMXRT_GPIO5_TOGGLE       (IMXRT_GPIO5_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
+
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_GPIO_H */
diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h
new file mode 100644
index 00000000000..43080701b09
--- /dev/null
+++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h
@@ -0,0 +1,1606 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author:  Gregory Nutt 
+ *            David Sidrane 
+ *            Dave Marples 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_IOMUXC_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_IOMUXC_H
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include 
+#include "hardware/imxrt_memorymap.h"
+
+/*****************************************************************************
+ * Pre-processor Definitions
+ *****************************************************************************/
+
+/* Register offsets **********************************************************/
+
+#define IMXRT_IOMUXC_GPR_GPR0_OFFSET                    0x0000 /* GPR0 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR1_OFFSET                    0x0004 /* GPR1 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR2_OFFSET                    0x0008 /* GPR2 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR3_OFFSET                    0x000c /* GPR3 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR4_OFFSET                    0x0010 /* GPR4 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR5_OFFSET                    0x0014 /* GPR5 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR6_OFFSET                    0x0018 /* GPR6 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR7_OFFSET                    0x001c /* GPR7 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR8_OFFSET                    0x0020 /* GPR8 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR9_OFFSET                    0x0024 /* GPR9 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR10_OFFSET                   0x0028 /* GPR10 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR11_OFFSET                   0x002c /* GPR11 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR12_OFFSET                   0x0030 /* GPR12 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR13_OFFSET                   0x0034 /* GPR13 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR14_OFFSET                   0x0038 /* GPR14 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR15_OFFSET                   0x003c /* GPR15 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR16_OFFSET                   0x0040 /* GPR16 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR17_OFFSET                   0x0044 /* GPR17 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR18_OFFSET                   0x0048 /* GPR18 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR19_OFFSET                   0x004c /* GPR19 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR20_OFFSET                   0x0050 /* GPR20 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR21_OFFSET                   0x0054 /* GPR21 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR22_OFFSET                   0x0058 /* GPR22 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR23_OFFSET                   0x005c /* GPR23 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR24_OFFSET                   0x0060 /* GPR24 General Purpose Register*/
+#define IMXRT_IOMUXC_GPR_GPR25_OFFSET                   0x0064 /* GPR25 General Purpose Register*/
+
+#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET         0x0000 /* SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */
+#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET    0x0004 /* SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */
+#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET  0x0008 /* SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */
+#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET      0x000c /* SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */
+#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET          0x0010 /* SW_PAD_CTL_PAD_POR_B SW PAD Control Register */
+#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET          0x0014 /* SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */
+#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET         0x0018 /* SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */
+#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET    0x001c /* SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */
+#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET  0x0020 /* SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */
+
+#define IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET                      0x0000 /* SNVC GPR0 General Purpose Register */
+#define IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET                      0x0004 /* SNVC GPR1 General Purpose Register */
+#define IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET                      0x0008 /* SNVC GPR2 General Purpose Register */
+#define IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET                      0x000c /* SNVC GPR3 General Purpose Register */
+
+/* Pad Mux Register Indices (used by software for table lookups) */
+
+#define IMXRT_PADMUX_GPIO_EMC_00_INDEX              0
+#define IMXRT_PADMUX_GPIO_EMC_01_INDEX              1
+#define IMXRT_PADMUX_GPIO_EMC_02_INDEX              2
+#define IMXRT_PADMUX_GPIO_EMC_03_INDEX              3
+#define IMXRT_PADMUX_GPIO_EMC_04_INDEX              4
+#define IMXRT_PADMUX_GPIO_EMC_05_INDEX              5
+#define IMXRT_PADMUX_GPIO_EMC_06_INDEX              6
+#define IMXRT_PADMUX_GPIO_EMC_07_INDEX              7
+#define IMXRT_PADMUX_GPIO_EMC_08_INDEX              8
+#define IMXRT_PADMUX_GPIO_EMC_09_INDEX              9
+#define IMXRT_PADMUX_GPIO_EMC_10_INDEX              10
+#define IMXRT_PADMUX_GPIO_EMC_11_INDEX              11
+#define IMXRT_PADMUX_GPIO_EMC_12_INDEX              12
+#define IMXRT_PADMUX_GPIO_EMC_13_INDEX              13
+#define IMXRT_PADMUX_GPIO_EMC_14_INDEX              14
+#define IMXRT_PADMUX_GPIO_EMC_15_INDEX              15
+#define IMXRT_PADMUX_GPIO_EMC_16_INDEX              16
+#define IMXRT_PADMUX_GPIO_EMC_17_INDEX              17
+#define IMXRT_PADMUX_GPIO_EMC_18_INDEX              18
+#define IMXRT_PADMUX_GPIO_EMC_19_INDEX              19
+#define IMXRT_PADMUX_GPIO_EMC_20_INDEX              20
+#define IMXRT_PADMUX_GPIO_EMC_21_INDEX              21
+#define IMXRT_PADMUX_GPIO_EMC_22_INDEX              22
+#define IMXRT_PADMUX_GPIO_EMC_23_INDEX              23
+#define IMXRT_PADMUX_GPIO_EMC_24_INDEX              24
+#define IMXRT_PADMUX_GPIO_EMC_25_INDEX              25
+#define IMXRT_PADMUX_GPIO_EMC_26_INDEX              26
+#define IMXRT_PADMUX_GPIO_EMC_27_INDEX              27
+#define IMXRT_PADMUX_GPIO_EMC_28_INDEX              28
+#define IMXRT_PADMUX_GPIO_EMC_29_INDEX              29
+#define IMXRT_PADMUX_GPIO_EMC_30_INDEX              30
+#define IMXRT_PADMUX_GPIO_EMC_31_INDEX              31
+#define IMXRT_PADMUX_GPIO_EMC_32_INDEX              32
+#define IMXRT_PADMUX_GPIO_EMC_33_INDEX              33
+#define IMXRT_PADMUX_GPIO_EMC_34_INDEX              34
+#define IMXRT_PADMUX_GPIO_EMC_35_INDEX              35
+#define IMXRT_PADMUX_GPIO_EMC_36_INDEX              36
+#define IMXRT_PADMUX_GPIO_EMC_37_INDEX              37
+#define IMXRT_PADMUX_GPIO_EMC_38_INDEX              38
+#define IMXRT_PADMUX_GPIO_EMC_39_INDEX              39
+#define IMXRT_PADMUX_GPIO_EMC_40_INDEX              40
+#define IMXRT_PADMUX_GPIO_EMC_41_INDEX              41
+#define IMXRT_PADMUX_GPIO_AD_B0_00_INDEX            42
+#define IMXRT_PADMUX_GPIO_AD_B0_01_INDEX            43
+#define IMXRT_PADMUX_GPIO_AD_B0_02_INDEX            44
+#define IMXRT_PADMUX_GPIO_AD_B0_03_INDEX            45
+#define IMXRT_PADMUX_GPIO_AD_B0_04_INDEX            46
+#define IMXRT_PADMUX_GPIO_AD_B0_05_INDEX            47
+#define IMXRT_PADMUX_GPIO_AD_B0_06_INDEX            48
+#define IMXRT_PADMUX_GPIO_AD_B0_07_INDEX            49
+#define IMXRT_PADMUX_GPIO_AD_B0_08_INDEX            50
+#define IMXRT_PADMUX_GPIO_AD_B0_09_INDEX            51
+#define IMXRT_PADMUX_GPIO_AD_B0_10_INDEX            52
+#define IMXRT_PADMUX_GPIO_AD_B0_11_INDEX            53
+#define IMXRT_PADMUX_GPIO_AD_B0_12_INDEX            54
+#define IMXRT_PADMUX_GPIO_AD_B0_13_INDEX            55
+#define IMXRT_PADMUX_GPIO_AD_B0_14_INDEX            56
+#define IMXRT_PADMUX_GPIO_AD_B0_15_INDEX            57
+#define IMXRT_PADMUX_GPIO_AD_B1_00_INDEX            58
+#define IMXRT_PADMUX_GPIO_AD_B1_01_INDEX            59
+#define IMXRT_PADMUX_GPIO_AD_B1_02_INDEX            60
+#define IMXRT_PADMUX_GPIO_AD_B1_03_INDEX            61
+#define IMXRT_PADMUX_GPIO_AD_B1_04_INDEX            62
+#define IMXRT_PADMUX_GPIO_AD_B1_05_INDEX            63
+#define IMXRT_PADMUX_GPIO_AD_B1_06_INDEX            64
+#define IMXRT_PADMUX_GPIO_AD_B1_07_INDEX            65
+#define IMXRT_PADMUX_GPIO_AD_B1_08_INDEX            66
+#define IMXRT_PADMUX_GPIO_AD_B1_09_INDEX            67
+#define IMXRT_PADMUX_GPIO_AD_B1_10_INDEX            68
+#define IMXRT_PADMUX_GPIO_AD_B1_11_INDEX            69
+#define IMXRT_PADMUX_GPIO_AD_B1_12_INDEX            70
+#define IMXRT_PADMUX_GPIO_AD_B1_13_INDEX            71
+#define IMXRT_PADMUX_GPIO_AD_B1_14_INDEX            72
+#define IMXRT_PADMUX_GPIO_AD_B1_15_INDEX            73
+#define IMXRT_PADMUX_GPIO_SD_B0_00_INDEX            74
+#define IMXRT_PADMUX_GPIO_SD_B0_01_INDEX            75
+#define IMXRT_PADMUX_GPIO_SD_B0_02_INDEX            76
+#define IMXRT_PADMUX_GPIO_SD_B0_03_INDEX            77
+#define IMXRT_PADMUX_GPIO_SD_B0_04_INDEX            78
+#define IMXRT_PADMUX_GPIO_SD_B0_05_INDEX            79
+#define IMXRT_PADMUX_GPIO_SD_B0_06_INDEX            80
+#define IMXRT_PADMUX_GPIO_SD_B1_00_INDEX            81
+#define IMXRT_PADMUX_GPIO_SD_B1_01_INDEX            82
+#define IMXRT_PADMUX_GPIO_SD_B1_02_INDEX            83
+#define IMXRT_PADMUX_GPIO_SD_B1_03_INDEX            84
+#define IMXRT_PADMUX_GPIO_SD_B1_04_INDEX            85
+#define IMXRT_PADMUX_GPIO_SD_B1_05_INDEX            86
+#define IMXRT_PADMUX_GPIO_SD_B1_06_INDEX            87
+#define IMXRT_PADMUX_GPIO_SD_B1_07_INDEX            88
+#define IMXRT_PADMUX_GPIO_SD_B1_08_INDEX            89
+#define IMXRT_PADMUX_GPIO_SD_B1_09_INDEX            90
+#define IMXRT_PADMUX_GPIO_SD_B1_10_INDEX            91
+#define IMXRT_PADMUX_GPIO_SD_B1_11_INDEX            92
+#define IMXRT_PADMUX_WAKEUP_INDEX                   93
+#define IMXRT_PADMUX_PMIC_ON_REQ_INDEX              94
+#define IMXRT_PADMUX_PMIC_STBY_REQ_INDEX            95
+
+#define IMXRT_PADMUX_NREGISTERS                     96
+
+/* Pad Mux Register Offsets */
+
+#define IMXRT_PADMUX_OFFSET(n)                      (0x0014 + ((unsigned int)(n) << 2))
+#define IMXRT_PADMUX_OFFSET_SNVS(n)                 ((unsigned int)(n) << 2)
+
+#define IMXRT_PADMUX_GPIO_EMC_00_OFFSET             0x0014
+#define IMXRT_PADMUX_GPIO_EMC_01_OFFSET             0x0018
+#define IMXRT_PADMUX_GPIO_EMC_02_OFFSET             0x001c
+#define IMXRT_PADMUX_GPIO_EMC_03_OFFSET             0x0020
+#define IMXRT_PADMUX_GPIO_EMC_04_OFFSET             0x0024
+#define IMXRT_PADMUX_GPIO_EMC_05_OFFSET             0x0028
+#define IMXRT_PADMUX_GPIO_EMC_06_OFFSET             0x002c
+#define IMXRT_PADMUX_GPIO_EMC_07_OFFSET             0x0030
+#define IMXRT_PADMUX_GPIO_EMC_08_OFFSET             0x0034
+#define IMXRT_PADMUX_GPIO_EMC_09_OFFSET             0x0038
+#define IMXRT_PADMUX_GPIO_EMC_10_OFFSET             0x003c
+#define IMXRT_PADMUX_GPIO_EMC_11_OFFSET             0x0040
+#define IMXRT_PADMUX_GPIO_EMC_12_OFFSET             0x0044
+#define IMXRT_PADMUX_GPIO_EMC_13_OFFSET             0x0048
+#define IMXRT_PADMUX_GPIO_EMC_14_OFFSET             0x004c
+#define IMXRT_PADMUX_GPIO_EMC_15_OFFSET             0x0050
+#define IMXRT_PADMUX_GPIO_EMC_16_OFFSET             0x0054
+#define IMXRT_PADMUX_GPIO_EMC_17_OFFSET             0x0058
+#define IMXRT_PADMUX_GPIO_EMC_18_OFFSET             0x005c
+#define IMXRT_PADMUX_GPIO_EMC_19_OFFSET             0x0060
+#define IMXRT_PADMUX_GPIO_EMC_20_OFFSET             0x0064
+#define IMXRT_PADMUX_GPIO_EMC_21_OFFSET             0x0068
+#define IMXRT_PADMUX_GPIO_EMC_22_OFFSET             0x006c
+#define IMXRT_PADMUX_GPIO_EMC_23_OFFSET             0x0070
+#define IMXRT_PADMUX_GPIO_EMC_24_OFFSET             0x0074
+#define IMXRT_PADMUX_GPIO_EMC_25_OFFSET             0x0078
+#define IMXRT_PADMUX_GPIO_EMC_26_OFFSET             0x007c
+#define IMXRT_PADMUX_GPIO_EMC_27_OFFSET             0x0080
+#define IMXRT_PADMUX_GPIO_EMC_28_OFFSET             0x0084
+#define IMXRT_PADMUX_GPIO_EMC_29_OFFSET             0x0088
+#define IMXRT_PADMUX_GPIO_EMC_30_OFFSET             0x008c
+#define IMXRT_PADMUX_GPIO_EMC_31_OFFSET             0x0090
+#define IMXRT_PADMUX_GPIO_EMC_32_OFFSET             0x0094
+#define IMXRT_PADMUX_GPIO_EMC_33_OFFSET             0x0098
+#define IMXRT_PADMUX_GPIO_EMC_34_OFFSET             0x009c
+#define IMXRT_PADMUX_GPIO_EMC_35_OFFSET             0x00a0
+#define IMXRT_PADMUX_GPIO_EMC_36_OFFSET             0x00a4
+#define IMXRT_PADMUX_GPIO_EMC_37_OFFSET             0x00a8
+#define IMXRT_PADMUX_GPIO_EMC_38_OFFSET             0x00ac
+#define IMXRT_PADMUX_GPIO_EMC_39_OFFSET             0x00b0
+#define IMXRT_PADMUX_GPIO_EMC_40_OFFSET             0x00b4
+#define IMXRT_PADMUX_GPIO_EMC_41_OFFSET             0x00b8
+#define IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET           0x00bc
+#define IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET           0x00c0
+#define IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET           0x00c4
+#define IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET           0x00c8
+#define IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET           0x00cc
+#define IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET           0x00d0
+#define IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET           0x00d4
+#define IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET           0x00d8
+#define IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET           0x00dc
+#define IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET           0x00e0
+#define IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET           0x00e4
+#define IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET           0x00e8
+#define IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET           0x00ec
+#define IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET           0x00f0
+#define IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET           0x00f4
+#define IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET           0x00f8
+#define IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET           0x00fc
+#define IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET           0x0100
+#define IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET           0x0104
+#define IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET           0x0108
+#define IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET           0x010c
+#define IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET           0x0110
+#define IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET           0x0114
+#define IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET           0x0118
+#define IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET           0x011c
+#define IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET           0x0120
+#define IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET           0x0124
+#define IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET           0x0128
+#define IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET           0x012c
+#define IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET           0x0130
+#define IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET           0x0134
+#define IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET           0x0138
+#define IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET           0x013c
+#define IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET           0x0140
+#define IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET           0x0144
+#define IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET           0x0148
+#define IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET           0x014c
+#define IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET           0x0150
+#define IMXRT_PADMUX_GPIO_SD_B0_06_OFFSET           0x0154
+#define IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET           0x0158
+#define IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET           0x015c
+#define IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET           0x0160
+#define IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET           0x0164
+#define IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET           0x0168
+#define IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET           0x016c
+#define IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET           0x0170
+#define IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET           0x0174
+#define IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET           0x0178
+#define IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET           0x017c
+#define IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET           0x0180
+#define IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET           0x0184
+
+/* Pad Control Registers
+ * Pad Control Register Indices (used by software for table lookups)
+ */
+
+#define IMXRT_PADCTL_GPIO_EMC_00_INDEX              0
+#define IMXRT_PADCTL_GPIO_EMC_01_INDEX              1
+#define IMXRT_PADCTL_GPIO_EMC_02_INDEX              2
+#define IMXRT_PADCTL_GPIO_EMC_03_INDEX              3
+#define IMXRT_PADCTL_GPIO_EMC_04_INDEX              4
+#define IMXRT_PADCTL_GPIO_EMC_05_INDEX              5
+#define IMXRT_PADCTL_GPIO_EMC_06_INDEX              6
+#define IMXRT_PADCTL_GPIO_EMC_07_INDEX              7
+#define IMXRT_PADCTL_GPIO_EMC_08_INDEX              8
+#define IMXRT_PADCTL_GPIO_EMC_09_INDEX              9
+#define IMXRT_PADCTL_GPIO_EMC_10_INDEX              10
+#define IMXRT_PADCTL_GPIO_EMC_11_INDEX              11
+#define IMXRT_PADCTL_GPIO_EMC_12_INDEX              12
+#define IMXRT_PADCTL_GPIO_EMC_13_INDEX              13
+#define IMXRT_PADCTL_GPIO_EMC_14_INDEX              14
+#define IMXRT_PADCTL_GPIO_EMC_15_INDEX              15
+#define IMXRT_PADCTL_GPIO_EMC_16_INDEX              16
+#define IMXRT_PADCTL_GPIO_EMC_17_INDEX              17
+#define IMXRT_PADCTL_GPIO_EMC_18_INDEX              18
+#define IMXRT_PADCTL_GPIO_EMC_19_INDEX              19
+#define IMXRT_PADCTL_GPIO_EMC_20_INDEX              20
+#define IMXRT_PADCTL_GPIO_EMC_21_INDEX              21
+#define IMXRT_PADCTL_GPIO_EMC_22_INDEX              22
+#define IMXRT_PADCTL_GPIO_EMC_23_INDEX              23
+#define IMXRT_PADCTL_GPIO_EMC_24_INDEX              24
+#define IMXRT_PADCTL_GPIO_EMC_25_INDEX              25
+#define IMXRT_PADCTL_GPIO_EMC_26_INDEX              26
+#define IMXRT_PADCTL_GPIO_EMC_27_INDEX              27
+#define IMXRT_PADCTL_GPIO_EMC_28_INDEX              28
+#define IMXRT_PADCTL_GPIO_EMC_29_INDEX              29
+#define IMXRT_PADCTL_GPIO_EMC_30_INDEX              30
+#define IMXRT_PADCTL_GPIO_EMC_31_INDEX              31
+#define IMXRT_PADCTL_GPIO_EMC_32_INDEX              32
+#define IMXRT_PADCTL_GPIO_EMC_33_INDEX              33
+#define IMXRT_PADCTL_GPIO_EMC_34_INDEX              34
+#define IMXRT_PADCTL_GPIO_EMC_35_INDEX              35
+#define IMXRT_PADCTL_GPIO_EMC_36_INDEX              36
+#define IMXRT_PADCTL_GPIO_EMC_37_INDEX              37
+#define IMXRT_PADCTL_GPIO_EMC_38_INDEX              38
+#define IMXRT_PADCTL_GPIO_EMC_39_INDEX              39
+#define IMXRT_PADCTL_GPIO_EMC_40_INDEX              40
+#define IMXRT_PADCTL_GPIO_EMC_41_INDEX              41
+#define IMXRT_PADCTL_GPIO_AD_B0_00_INDEX            42
+#define IMXRT_PADCTL_GPIO_AD_B0_01_INDEX            43
+#define IMXRT_PADCTL_GPIO_AD_B0_02_INDEX            44
+#define IMXRT_PADCTL_GPIO_AD_B0_03_INDEX            45
+#define IMXRT_PADCTL_GPIO_AD_B0_04_INDEX            46
+#define IMXRT_PADCTL_GPIO_AD_B0_05_INDEX            47
+#define IMXRT_PADCTL_GPIO_AD_B0_06_INDEX            48
+#define IMXRT_PADCTL_GPIO_AD_B0_07_INDEX            49
+#define IMXRT_PADCTL_GPIO_AD_B0_08_INDEX            50
+#define IMXRT_PADCTL_GPIO_AD_B0_09_INDEX            51
+#define IMXRT_PADCTL_GPIO_AD_B0_10_INDEX            52
+#define IMXRT_PADCTL_GPIO_AD_B0_11_INDEX            53
+#define IMXRT_PADCTL_GPIO_AD_B0_12_INDEX            54
+#define IMXRT_PADCTL_GPIO_AD_B0_13_INDEX            55
+#define IMXRT_PADCTL_GPIO_AD_B0_14_INDEX            56
+#define IMXRT_PADCTL_GPIO_AD_B0_15_INDEX            57
+#define IMXRT_PADCTL_GPIO_AD_B1_00_INDEX            58
+#define IMXRT_PADCTL_GPIO_AD_B1_01_INDEX            59
+#define IMXRT_PADCTL_GPIO_AD_B1_02_INDEX            60
+#define IMXRT_PADCTL_GPIO_AD_B1_03_INDEX            61
+#define IMXRT_PADCTL_GPIO_AD_B1_04_INDEX            62
+#define IMXRT_PADCTL_GPIO_AD_B1_05_INDEX            63
+#define IMXRT_PADCTL_GPIO_AD_B1_06_INDEX            64
+#define IMXRT_PADCTL_GPIO_AD_B1_07_INDEX            65
+#define IMXRT_PADCTL_GPIO_AD_B1_08_INDEX            66
+#define IMXRT_PADCTL_GPIO_AD_B1_09_INDEX            67
+#define IMXRT_PADCTL_GPIO_AD_B1_10_INDEX            68
+#define IMXRT_PADCTL_GPIO_AD_B1_11_INDEX            69
+#define IMXRT_PADCTL_GPIO_AD_B1_12_INDEX            70
+#define IMXRT_PADCTL_GPIO_AD_B1_13_INDEX            71
+#define IMXRT_PADCTL_GPIO_AD_B1_14_INDEX            72
+#define IMXRT_PADCTL_GPIO_AD_B1_15_INDEX            73
+#define IMXRT_PADCTL_GPIO_SD_B0_00_INDEX            74
+#define IMXRT_PADCTL_GPIO_SD_B0_01_INDEX            75
+#define IMXRT_PADCTL_GPIO_SD_B0_02_INDEX            76
+#define IMXRT_PADCTL_GPIO_SD_B0_03_INDEX            77
+#define IMXRT_PADCTL_GPIO_SD_B0_04_INDEX            78
+#define IMXRT_PADCTL_GPIO_SD_B0_05_INDEX            79
+#define IMXRT_PADCTL_GPIO_SD_B0_06_INDEX            80
+#define IMXRT_PADCTL_GPIO_SD_B1_00_INDEX            81
+#define IMXRT_PADCTL_GPIO_SD_B1_01_INDEX            82
+#define IMXRT_PADCTL_GPIO_SD_B1_02_INDEX            83
+#define IMXRT_PADCTL_GPIO_SD_B1_03_INDEX            84
+#define IMXRT_PADCTL_GPIO_SD_B1_04_INDEX            85
+#define IMXRT_PADCTL_GPIO_SD_B1_05_INDEX            86
+#define IMXRT_PADCTL_GPIO_SD_B1_06_INDEX            87
+#define IMXRT_PADCTL_GPIO_SD_B1_07_INDEX            88
+#define IMXRT_PADCTL_GPIO_SD_B1_08_INDEX            89
+#define IMXRT_PADCTL_GPIO_SD_B1_09_INDEX            90
+#define IMXRT_PADCTL_GPIO_SD_B1_10_INDEX            91
+#define IMXRT_PADCTL_GPIO_SD_B1_11_INDEX            92
+
+#define IMXRT_PADCTL_WAKEUP_INDEX                   93
+#define IMXRT_PADCTL_PMIC_ON_REQ_INDEX              94
+#define IMXRT_PADCTL_PMIC_STBY_REQ_INDEX            95
+
+#define IMXRT_PADCTL_NREGISTERS                     96
+
+/* Pad Control Register Offsets */
+
+#define IMXRT_PADCTL_OFFSET(n)                      (0x0188 + ((unsigned int)(n) << 2))
+#define IMXRT_PADCTL_OFFSET_SNVS(n)                 (0x18 + ((unsigned int)(n-IMXRT_PADCTL_WAKEUP_INDEX) << 2))
+
+#define IMXRT_PADCTL_GPIO_EMC_00_OFFSET             0x0188
+#define IMXRT_PADCTL_GPIO_EMC_01_OFFSET             0x018c
+#define IMXRT_PADCTL_GPIO_EMC_02_OFFSET             0x0190
+#define IMXRT_PADCTL_GPIO_EMC_03_OFFSET             0x0194
+#define IMXRT_PADCTL_GPIO_EMC_04_OFFSET             0x0198
+#define IMXRT_PADCTL_GPIO_EMC_05_OFFSET             0x019c
+#define IMXRT_PADCTL_GPIO_EMC_06_OFFSET             0x01a0
+#define IMXRT_PADCTL_GPIO_EMC_07_OFFSET             0x01a4
+#define IMXRT_PADCTL_GPIO_EMC_08_OFFSET             0x01a8
+#define IMXRT_PADCTL_GPIO_EMC_09_OFFSET             0x01ac
+#define IMXRT_PADCTL_GPIO_EMC_10_OFFSET             0x01b0
+#define IMXRT_PADCTL_GPIO_EMC_11_OFFSET             0x01b4
+#define IMXRT_PADCTL_GPIO_EMC_12_OFFSET             0x01b8
+#define IMXRT_PADCTL_GPIO_EMC_13_OFFSET             0x01bc
+#define IMXRT_PADCTL_GPIO_EMC_14_OFFSET             0x01c0
+#define IMXRT_PADCTL_GPIO_EMC_15_OFFSET             0x01c4
+#define IMXRT_PADCTL_GPIO_EMC_16_OFFSET             0x01c8
+#define IMXRT_PADCTL_GPIO_EMC_17_OFFSET             0x01cc
+#define IMXRT_PADCTL_GPIO_EMC_18_OFFSET             0x01d0
+#define IMXRT_PADCTL_GPIO_EMC_19_OFFSET             0x01d4
+#define IMXRT_PADCTL_GPIO_EMC_20_OFFSET             0x01d8
+#define IMXRT_PADCTL_GPIO_EMC_21_OFFSET             0x01dc
+#define IMXRT_PADCTL_GPIO_EMC_22_OFFSET             0x01e0
+#define IMXRT_PADCTL_GPIO_EMC_23_OFFSET             0x01e4
+#define IMXRT_PADCTL_GPIO_EMC_24_OFFSET             0x01e8
+#define IMXRT_PADCTL_GPIO_EMC_25_OFFSET             0x01ec
+#define IMXRT_PADCTL_GPIO_EMC_26_OFFSET             0x01f0
+#define IMXRT_PADCTL_GPIO_EMC_27_OFFSET             0x01f4
+#define IMXRT_PADCTL_GPIO_EMC_28_OFFSET             0x01f8
+#define IMXRT_PADCTL_GPIO_EMC_29_OFFSET             0x01fc
+#define IMXRT_PADCTL_GPIO_EMC_30_OFFSET             0x0200
+#define IMXRT_PADCTL_GPIO_EMC_31_OFFSET             0x0204
+#define IMXRT_PADCTL_GPIO_EMC_32_OFFSET             0x0208
+#define IMXRT_PADCTL_GPIO_EMC_33_OFFSET             0x020c
+#define IMXRT_PADCTL_GPIO_EMC_34_OFFSET             0x0210
+#define IMXRT_PADCTL_GPIO_EMC_35_OFFSET             0x0214
+#define IMXRT_PADCTL_GPIO_EMC_36_OFFSET             0x0218
+#define IMXRT_PADCTL_GPIO_EMC_37_OFFSET             0x021c
+#define IMXRT_PADCTL_GPIO_EMC_38_OFFSET             0x0220
+#define IMXRT_PADCTL_GPIO_EMC_39_OFFSET             0x0224
+#define IMXRT_PADCTL_GPIO_EMC_40_OFFSET             0x0228
+#define IMXRT_PADCTL_GPIO_EMC_41_OFFSET             0x022c
+#define IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET           0x0230
+#define IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET           0x0234
+#define IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET           0x0238
+#define IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET           0x023c
+#define IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET           0x0240
+#define IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET           0x0244
+#define IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET           0x0248
+#define IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET           0x024c
+#define IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET           0x0250
+#define IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET           0x0254
+#define IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET           0x0258
+#define IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET           0x025c
+#define IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET           0x0260
+#define IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET           0x0264
+#define IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET           0x0268
+#define IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET           0x026c
+#define IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET           0x0270
+#define IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET           0x0274
+#define IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET           0x0278
+#define IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET           0x027c
+#define IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET           0x0280
+#define IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET           0x0284
+#define IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET           0x0288
+#define IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET           0x028c
+#define IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET           0x0290
+#define IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET           0x0294
+#define IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET           0x0298
+#define IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET           0x029c
+#define IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET           0x02a0
+#define IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET           0x02a4
+#define IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET           0x02a8
+#define IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET           0x02ac
+#define IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET           0x02b0
+#define IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET           0x02b4
+#define IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET           0x02b8
+#define IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET           0x02bc
+#define IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET           0x02c0
+#define IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET           0x02c4
+#define IMXRT_PADCTL_GPIO_SD_B0_06_OFFSET           0x02c8
+#define IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET           0x02cc
+#define IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET           0x02d0
+#define IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET           0x02d4
+#define IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET           0x02d8
+#define IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET           0x02dc
+#define IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET           0x02e0
+#define IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET           0x02e4
+#define IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET           0x02e8
+#define IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET           0x02ec
+#define IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET           0x02f0
+#define IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET           0x02f4
+#define IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET           0x02f8
+
+/* Select Input Daisy Register Offsets */
+
+#define IMXRT_INPUT_INDEX2OFFSET(n)                 (0x02fc + ((unsigned int)(n) << 2))
+#define IMXRT_INPUT_OFFSET2INDEX(o)                 (((unsigned int)(o) - 0x02fc) >> 2)
+
+#define IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET       0x02fc
+#define IMXRT_INPUT_CCM_PMIC_READY_OFFSET           0x0300
+#define IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET        0x0304
+#define IMXRT_INPUT_ENET_MDIO_OFFSET                0x0308
+#define IMXRT_INPUT_ENET_RXDATA0_OFFSET             0x030c
+#define IMXRT_INPUT_ENET_RXDATA1_OFFSET             0x0310
+#define IMXRT_INPUT_ENET_RXEN_OFFSET                0x0314
+#define IMXRT_INPUT_ENET_RXERR_OFFSET               0x0318
+#define IMXRT_INPUT_ENET_TXCLK_OFFSET               0x031c
+#define IMXRT_INPUT_FLEXCAN1_RX_OFFSET              0x0320
+#define IMXRT_INPUT_FLEXCAN2_RX_OFFSET              0x0324
+#define IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET           0x0328
+#define IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET           0x032c
+#define IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET           0x0330
+#define IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET           0x0334
+#define IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET           0x0338
+#define IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET           0x033c
+#define IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET           0x0340
+#define IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET           0x0344
+#define IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET           0x0348
+#define IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET           0x034c
+#define IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET           0x0350
+#define IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET           0x0354
+#define IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET           0x0358
+#define IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET           0x035c
+#define IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET           0x0360
+#define IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET           0x0364
+#define IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET           0x0368
+#define IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET           0x036c
+#define IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET           0x0370
+#define IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET           0x0374
+#define IMXRT_INPUT_FLEXSPIA_SCK_OFFSET             0x0378
+#define IMXRT_INPUT_LPI2C1_SCL_OFFSET               0x037c
+#define IMXRT_INPUT_LPI2C1_SDA_OFFSET               0x0380
+#define IMXRT_INPUT_LPI2C2_SCL_OFFSET               0x0384
+#define IMXRT_INPUT_LPI2C2_SDA_OFFSET               0x0388
+#define IMXRT_INPUT_LPI2C3_SCL_OFFSET               0x038c
+#define IMXRT_INPUT_LPI2C3_SDA_OFFSET               0x0390
+#define IMXRT_INPUT_LPI2C4_SCL_OFFSET               0x0394
+#define IMXRT_INPUT_LPI2C4_SDA_OFFSET               0x0398
+#define IMXRT_INPUT_LPSPI1_PCS0_OFFSET              0x039c
+#define IMXRT_INPUT_LPSPI1_SCK_OFFSET               0x03a0
+#define IMXRT_INPUT_LPSPI1_SDI_OFFSET               0x03a4
+#define IMXRT_INPUT_LPSPI1_SDO_OFFSET               0x03a8
+#define IMXRT_INPUT_LPSPI2_PCS0_OFFSET              0x03ac
+#define IMXRT_INPUT_LPSPI2_SCK_OFFSET               0x03b0
+#define IMXRT_INPUT_LPSPI2_SDI_OFFSET               0x03b4
+#define IMXRT_INPUT_LPSPI2_SDO_OFFSET               0x03b8
+#define IMXRT_INPUT_LPSPI4_PCS0_OFFSET              0x03bc
+#define IMXRT_INPUT_LPSPI4_SCK_OFFSET               0x03c0
+#define IMXRT_INPUT_LPSPI4_SDI_OFFSET               0x03c4
+#define IMXRT_INPUT_LPSPI4_SDO_OFFSET               0x03c8
+#define IMXRT_INPUT_LPUART3_CTS_B_OFFSET            0x03cc
+#define IMXRT_INPUT_LPUART2_RX_OFFSET               0x03d0
+#define IMXRT_INPUT_LPUART2_TX_OFFSET               0x03d4
+#define IMXRT_INPUT_LPUART3_RX_OFFSET               0x03d8
+#define IMXRT_INPUT_LPUART3_TX_OFFSET               0x03dc
+#define IMXRT_INPUT_LPUART4_CTS_B_OFFSET            0x03e0
+#define IMXRT_INPUT_LPUART4_RX_OFFSET               0x03e4
+#define IMXRT_INPUT_LPUART4_TX_OFFSET               0x03e8
+#define IMXRT_INPUT_LPUART5_RX_OFFSET               0x03ec
+#define IMXRT_INPUT_LPUART5_TX_OFFSET               0x03f0
+#define IMXRT_INPUT_LPUART6_RX_OFFSET               0x03f4
+#define IMXRT_INPUT_LPUART6_TX_OFFSET               0x03f8
+#define IMXRT_INPUT_LPUART7_RX_OFFSET               0x03fc
+#define IMXRT_INPUT_LPUART7_TX_OFFSET               0x0400
+#define IMXRT_INPUT_LPUART8_RX_OFFSET               0x0404
+#define IMXRT_INPUT_LPUART8_TX_OFFSET               0x0408
+#define IMXRT_INPUT_NMI_GLUE_NMI_OFFSET             0x040c
+#define IMXRT_INPUT_QTIMER1_TIMER0_OFFSET           0x0410
+#define IMXRT_INPUT_QTIMER1_TIMER1_OFFSET           0x0414
+#define IMXRT_INPUT_QTIMER1_TIMER2_OFFSET           0x0418
+#define IMXRT_INPUT_QTIMER1_TIMER3_OFFSET           0x041c
+#define IMXRT_INPUT_QTIMER2_TIMER0_OFFSET           0x0420
+#define IMXRT_INPUT_QTIMER2_TIMER1_OFFSET           0x0424
+#define IMXRT_INPUT_QTIMER2_TIMER2_OFFSET           0x0428
+#define IMXRT_INPUT_QTIMER2_TIMER3_OFFSET           0x042c
+#define IMXRT_INPUT_SAI1_MCLK_OFFSET                0x0430
+#define IMXRT_INPUT_SAI1_RX_BCLK_OFFSET             0x0434
+#define IMXRT_INPUT_SAI1_RX_DATA0_OFFSET            0x0438
+#define IMXRT_INPUT_SAI1_RX_DATA1_OFFSET            0x043c
+#define IMXRT_INPUT_SAI1_RX_DATA2_OFFSET            0x0440
+#define IMXRT_INPUT_SAI1_RX_DATA3_OFFSET            0x0444
+#define IMXRT_INPUT_SAI1_RX_SYNC_OFFSET             0x0448
+#define IMXRT_INPUT_SAI1_TX_BCLK_OFFSET             0x044c
+#define IMXRT_INPUT_SAI1_TX_SYNC_OFFSET             0x0450
+#define IMXRT_INPUT_SAI2_MCLK_OFFSET                0x0454
+#define IMXRT_INPUT_SAI2_RX_BCLK_OFFSET             0x0458
+#define IMXRT_INPUT_SAI2_RX_DATA0_OFFSET            0x045c
+#define IMXRT_INPUT_SAI2_RX_SYNC_OFFSET             0x0460
+#define IMXRT_INPUT_SAI2_TX_BCLK_OFFSET             0x0464
+#define IMXRT_INPUT_SAI2_TX_SYNC_OFFSET             0x0468
+#define IMXRT_INPUT_SAI3_MCLK_OFFSET                0x046c
+#define IMXRT_INPUT_SAI3_RX_BCLK_OFFSET             0x0470
+#define IMXRT_INPUT_SAI3_RX_DATA0_OFFSET            0x0474
+#define IMXRT_INPUT_SAI3_RX_SYNC_OFFSET             0x0478
+#define IMXRT_INPUT_SAI3_TX_BCLK_OFFSET             0x047c
+#define IMXRT_INPUT_SAI3_TX_SYNC_OFFSET             0x0480
+#define IMXRT_INPUT_SEMC_READY_OFFSET               0x0484
+#define IMXRT_INPUT_SPDIF_IN_OFFSET                 0x0488
+#define IMXRT_INPUT_USB_OTG1_OC_OFFSET              0x048c
+#define IMXRT_INPUT_USDHC1_CD_B_OFFSET              0x0490
+#define IMXRT_INPUT_USDHC1_WP_OFFSET                0x0494
+#define IMXRT_INPUT_USDHC2_CD_B_OFFSET              0x0498
+#define IMXRT_INPUT_USDHC2_CMD_OFFSET               0x049c
+#define IMXRT_INPUT_XBAR1_IN14_OFFSET               0x04a0
+#define IMXRT_INPUT_XBAR1_IN15_OFFSET               0x04a4
+#define IMXRT_INPUT_XBAR1_IN16_OFFSET               0x04a8
+#define IMXRT_INPUT_XBAR1_IN17_OFFSET               0x04ac
+#define IMXRT_INPUT_XBAR1_IN10_OFFSET               0x04b0
+#define IMXRT_INPUT_XBAR1_IN12_OFFSET               0x04b4
+#define IMXRT_INPUT_XBAR1_IN13_OFFSET               0x04b8
+#define IMXRT_INPUT_XBAR1_IN18_OFFSET               0x04bc
+#define IMXRT_INPUT_XBAR1_IN19_OFFSET               0x04c0
+
+/* Register addresses ********************************************************/
+
+#define IMXRT_IOMUXC_GPR_GPR0            (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR0_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR1            (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR1_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR2            (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR2_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR3            (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR3_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR4            (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR4_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR5            (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR5_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR6            (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR6_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR7            (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR7_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR8            (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR8_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR9            (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR9_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR10           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR10_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR11           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR11_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR12           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR12_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR13           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR13_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR14           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR14_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR15           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR15_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR16           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR16_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR17           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR17_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR18           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR18_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR19           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR19_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR20           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR20_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR21           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR21_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR22           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR22_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR23           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR23_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR24           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR24_OFFSET)
+#define IMXRT_IOMUXC_GPR_GPR25           (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR25_OFFSET)
+
+#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP        (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET)
+#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ   (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET)
+#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET)
+#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE     (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET)
+#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B         (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET)
+#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF         (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET)
+#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP        (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET)
+#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ   (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET)
+#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET)
+
+#define IMXRT_IOMUXC_SNVS_GPR_GPR0       (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET)
+#define IMXRT_IOMUXC_SNVS_GPR_GPR1       (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET)
+#define IMXRT_IOMUXC_SNVS_GPR_GPR2       (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET)
+#define IMXRT_IOMUXC_SNVS_GPR_GPR3       (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET)
+
+/* Pad Mux Registers */
+
+#define IMXRT_PADMUX_ADDRESS(n)          (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_OFFSET(n))
+#define IMXRT_PADMUX_ADDRESS_SNVS(n)     (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADMUX_OFFSET_SNVS(n))
+
+#define IMXRT_PADMUX_GPIO_EMC_00         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_00_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_01         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_01_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_02         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_02_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_03         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_03_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_04         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_04_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_05         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_05_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_06         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_06_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_07         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_07_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_08         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_08_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_09         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_09_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_10         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_10_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_11         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_11_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_12         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_12_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_13         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_13_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_14         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_14_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_15         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_15_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_16         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_16_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_17         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_17_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_18         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_18_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_19         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_19_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_20         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_20_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_21         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_21_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_22         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_22_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_23         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_23_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_24         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_24_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_25         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_25_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_26         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_26_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_27         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_27_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_28         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_28_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_29         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_29_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_30         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_30_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_31         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_31_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_32         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_32_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_33         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_33_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_34         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_34_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_35         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_35_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_36         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_36_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_37         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_37_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_38         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_38_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_39         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_39_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_40         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_40_OFFSET)
+#define IMXRT_PADMUX_GPIO_EMC_41         (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_41_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_00       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_01       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_02       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_03       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_04       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_05       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_06       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_07       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_08       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_09       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_10       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_11       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_12       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_13       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_14       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B0_15       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_00       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_01       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_02       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_03       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_04       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_05       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_06       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_07       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_08       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_09       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_10       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_11       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_12       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_13       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_14       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET)
+#define IMXRT_PADMUX_GPIO_AD_B1_15       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B0_00       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B0_01       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B0_02       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B0_03       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B0_04       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B0_05       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B0_06       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_06_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B1_00       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B1_01       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B1_02       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B1_03       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B1_04       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B1_05       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B1_06       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B1_07       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B1_08       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B1_09       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B1_10       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET)
+#define IMXRT_PADMUX_GPIO_SD_B1_11       (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET)
+
+/* Pad Control Registers */
+
+#define IMXRT_PADCTL_ADDRESS(n)          (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_OFFSET(n))
+#define IMXRT_PADCTL_ADDRESS_SNVS(n)     (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADCTL_OFFSET_SNVS(n))
+
+#define IMXRT_PADCTL_GPIO_EMC_00         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_00_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_01         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_01_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_02         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_02_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_03         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_03_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_04         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_04_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_05         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_05_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_06         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_06_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_07         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_07_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_08         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_08_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_09         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_09_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_10         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_10_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_11         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_11_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_12         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_12_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_13         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_13_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_14         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_14_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_15         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_15_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_16         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_16_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_17         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_17_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_18         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_18_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_19         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_19_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_20         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_20_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_21         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_21_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_22         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_22_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_23         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_23_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_24         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_24_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_25         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_25_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_26         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_26_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_27         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_27_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_28         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_28_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_29         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_29_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_30         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_30_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_31         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_31_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_32         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_32_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_33         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_33_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_34         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_34_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_35         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_35_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_36         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_36_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_37         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_37_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_38         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_38_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_39         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_39_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_40         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_40_OFFSET)
+#define IMXRT_PADCTL_GPIO_EMC_41         (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_41_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_00       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_01       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_02       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_03       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_04       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_05       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_06       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_07       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_08       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_09       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_10       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_11       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_12       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_13       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_14       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B0_15       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_00       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_01       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_02       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_03       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_04       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_05       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_06       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_07       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_08       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_09       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_10       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_11       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_12       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_13       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_14       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET)
+#define IMXRT_PADCTL_GPIO_AD_B1_15       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B0_00       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B0_01       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B0_02       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B0_03       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B0_04       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B0_05       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B0_06       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_06_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B1_00       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B1_01       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B1_02       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B1_03       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B1_04       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B1_05       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B1_06       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B1_07       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B1_08       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B1_09       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B1_10       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET)
+#define IMXRT_PADCTL_GPIO_SD_B1_11       (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET)
+
+/* Select Input Registers */
+
+#define IMXRT_INPUT_ANATOP_USB_OTG1_ID   (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET)
+#define IMXRT_INPUT_CCM_PMIC_READY       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CCM_PMIC_READY_OFFSET)
+#define IMXRT_INPUT_ENET_IPG_CLK_RMII    (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET)
+#define IMXRT_INPUT_ENET_MDIO            (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_MDIO_OFFSET)
+#define IMXRT_INPUT_ENET0_RXDATA         (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET0_RXDATA_OFFSET)
+#define IMXRT_INPUT_ENET1_RXDATA         (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET1_RXDATA_OFFSET)
+#define IMXRT_INPUT_ENET_RXEN            (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXEN_OFFSET)
+#define IMXRT_INPUT_ENET_RXERR           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXERR_OFFSET)
+#define IMXRT_INPUT_ENET_TXCLK           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_TXCLK_OFFSET)
+#define IMXRT_INPUT_FLEXCAN1_RX          (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN1_RX_OFFSET)
+#define IMXRT_INPUT_FLEXCAN2_RX          (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN2_RX_OFFSET)
+#define IMXRT_INPUT_FLEXPWM1_PWMA0       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET)
+#define IMXRT_INPUT_FLEXPWM1_PWMA1       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET)
+#define IMXRT_INPUT_FLEXPWM1_PWMA2       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET)
+#define IMXRT_INPUT_FLEXPWM1_PWMA3       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET)
+#define IMXRT_INPUT_FLEXPWM1_PWMB0       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET)
+#define IMXRT_INPUT_FLEXPWM1_PWMB1       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET)
+#define IMXRT_INPUT_FLEXPWM1_PWMB2       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET)
+#define IMXRT_INPUT_FLEXPWM1_PWMB3       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET)
+#define IMXRT_INPUT_FLEXPWM2_PWMA0       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET)
+#define IMXRT_INPUT_FLEXPWM2_PWMA1       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET)
+#define IMXRT_INPUT_FLEXPWM2_PWMA2       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET)
+#define IMXRT_INPUT_FLEXPWM2_PWMA3       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET)
+#define IMXRT_INPUT_FLEXPWM2_PWMB0       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET)
+#define IMXRT_INPUT_FLEXPWM2_PWMB1       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET)
+#define IMXRT_INPUT_FLEXPWM2_PWMB2       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET)
+#define IMXRT_INPUT_FLEXPWM2_PWMB3       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET)
+#define IMXRT_INPUT_FLEXSPIA_DATA0       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET)
+#define IMXRT_INPUT_FLEXSPIA_DATA1       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET)
+#define IMXRT_INPUT_FLEXSPIA_DATA2       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET)
+#define IMXRT_INPUT_FLEXSPIA_DATA3       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET)
+#define IMXRT_INPUT_FLEXSPIA_SCK         (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_SCK_OFFSET)
+#define IMXRT_INPUT_LPI2C1_SCL           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SCL_OFFSET)
+#define IMXRT_INPUT_LPI2C1_SDA           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SDA_OFFSET)
+#define IMXRT_INPUT_LPI2C2_SCL           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SCL_OFFSET)
+#define IMXRT_INPUT_LPI2C2_SDA           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SDA_OFFSET)
+#define IMXRT_INPUT_LPI2C3_SCL           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SCL_OFFSET)
+#define IMXRT_INPUT_LPI2C3_SDA           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SDA_OFFSET)
+#define IMXRT_INPUT_LPI2C4_SCL           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SCL_OFFSET)
+#define IMXRT_INPUT_LPI2C4_SDA           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SDA_OFFSET)
+#define IMXRT_INPUT_LPSPI1_PCS0          (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_PCS0_OFFSET)
+#define IMXRT_INPUT_LPSPI1_SCK           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SCK_OFFSET)
+#define IMXRT_INPUT_LPSPI1_SDI           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDI_OFFSET)
+#define IMXRT_INPUT_LPSPI1_SDO           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDO_OFFSET)
+#define IMXRT_INPUT_LPSPI2_PCS0          (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_PCS0_OFFSET)
+#define IMXRT_INPUT_LPSPI2_SCK           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SCK_OFFSET)
+#define IMXRT_INPUT_LPSPI2_SDI           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDI_OFFSET)
+#define IMXRT_INPUT_LPSPI2_SDO           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDO_OFFSET)
+#define IMXRT_INPUT_LPSPI4_PCS0          (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_PCS0_OFFSET)
+#define IMXRT_INPUT_LPSPI4_SCK           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SCK_OFFSET)
+#define IMXRT_INPUT_LPSPI4_SDI           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDI_OFFSET)
+#define IMXRT_INPUT_LPSPI4_SDO           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDO_OFFSET)
+#define IMXRT_INPUT_LPUART2_RX           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_RX_OFFSET)
+#define IMXRT_INPUT_LPUART2_TX           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_TX_OFFSET)
+#define IMXRT_INPUT_LPUART3_CTS_B        (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_CTS_B_OFFSET)
+#define IMXRT_INPUT_LPUART3_RX           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_RX_OFFSET)
+#define IMXRT_INPUT_LPUART3_TX           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_TX_OFFSET)
+#define IMXRT_INPUT_LPUART4_RX           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_RX_OFFSET)
+#define IMXRT_INPUT_LPUART4_TX           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_TX_OFFSET)
+#define IMXRT_INPUT_LPUART5_RX           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_RX_OFFSET)
+#define IMXRT_INPUT_LPUART5_TX           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_TX_OFFSET)
+#define IMXRT_INPUT_LPUART6_RX           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_RX_OFFSET)
+#define IMXRT_INPUT_LPUART6_TX           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_TX_OFFSET)
+#define IMXRT_INPUT_LPUART7_RX           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_RX_OFFSET)
+#define IMXRT_INPUT_LPUART7_TX           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_TX_OFFSET)
+#define IMXRT_INPUT_LPUART8_RX           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_RX_OFFSET)
+#define IMXRT_INPUT_LPUART8_TX           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_TX_OFFSET)
+#define IMXRT_INPUT_NMI_GLUE_NMI         (IMXRT_IOMUXC_BASE + IMXRT_INPUT_NMI_GLUE_NMI_OFFSET)
+#define IMXRT_INPUT_QTIMER1_TIMER0       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER1_TIMER0_OFFSET)
+#define IMXRT_INPUT_QTIMER1_TIMER1       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER1_TIMER1_OFFSET)
+#define IMXRT_INPUT_QTIMER1_TIMER2       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER1_TIMER2_OFFSET)
+#define IMXRT_INPUT_QTIMER1_TIMER3       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER1_TIMER3_OFFSET)
+#define IMXRT_INPUT_QTIMER2_TIMER0       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER0_OFFSET)
+#define IMXRT_INPUT_QTIMER2_TIMER1       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER1_OFFSET)
+#define IMXRT_INPUT_QTIMER2_TIMER2       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER2_OFFSET)
+#define IMXRT_INPUT_QTIMER2_TIMER3       (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER3_OFFSET)
+#define IMXRT_INPUT_SAI1_MCLK2           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_MCLK2_OFFSET)
+#define IMXRT_INPUT_SAI1_RX_BCLK         (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_BCLK_OFFSET)
+#define IMXRT_INPUT_SAI1_RX_DATA0        (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA0_OFFSET)
+#define IMXRT_INPUT_SAI1_RX_DATA1        (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA1_OFFSET)
+#define IMXRT_INPUT_SAI1_RX_DATA2        (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA2_OFFSET)
+#define IMXRT_INPUT_SAI1_RX_DATA3        (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA3_OFFSET)
+#define IMXRT_INPUT_SAI1_RX_SYNC         (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_SYNC_OFFSET)
+#define IMXRT_INPUT_SAI1_TX_BCLK         (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_BCLK_OFFSET)
+#define IMXRT_INPUT_SAI1_TX_SYNC         (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_SYNC_OFFSET)
+#define IMXRT_INPUT_SAI2_MCLK2           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_MCLK2_OFFSET)
+#define IMXRT_INPUT_SAI2_RX_BCLK         (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_BCLK_OFFSET)
+#define IMXRT_INPUT_SAI2_RX_DATA0        (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_DATA0_OFFSET)
+#define IMXRT_INPUT_SAI2_RX_SYNC         (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_SYNC_OFFSET)
+#define IMXRT_INPUT_SAI2_TX_BCLK         (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_BCLK_OFFSET)
+#define IMXRT_INPUT_SAI2_TX_SYNC         (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_SYNC_OFFSET)
+#define IMXRT_INPUT_SPDIF_IN             (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SPDIF_IN_OFFSET)
+#define IMXRT_INPUT_USB_OTG1_OC          (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USB_OTG1_OC_OFFSET)
+#define IMXRT_INPUT_USDHC1_CD_B          (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_CD_B_OFFSET)
+#define IMXRT_INPUT_USDHC1_WP            (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_WP_OFFSET)
+#define IMXRT_INPUT_USDHC2_CLK           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CLK_OFFSET)
+#define IMXRT_INPUT_USDHC2_CD_B          (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CD_B_OFFSET)
+#define IMXRT_INPUT_XBAR1_IN14           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN14_OFFSET)
+#define IMXRT_INPUT_XBAR1_IN15           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN15_OFFSET)
+#define IMXRT_INPUT_XBAR1_IN16           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN16_OFFSET)
+#define IMXRT_INPUT_XBAR1_IN17           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN17_OFFSET)
+#define IMXRT_INPUT_XBAR1_IN10           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN10_OFFSET)
+#define IMXRT_INPUT_XBAR1_IN12           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN12_OFFSET)
+#define IMXRT_INPUT_XBAR1_IN13           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN13_OFFSET)
+#define IMXRT_INPUT_XBAR1_IN18           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN18_OFFSET)
+#define IMXRT_INPUT_XBAR1_IN19           (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN19_OFFSET)
+
+/* Register bit definitions **************************************************/
+
+/* General Purpose Register 0 (GPR0) - Reserved */
+
+/* General Purpose Register 1 (GPR1) */
+
+#define GPR_GPR1_SAI1_MCLK1_SEL_SHIFT                           (0)
+#define GPR_GPR1_SAI1_MCLK1_SEL_MASK                            (7 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI1_CLK_ROOT             (0 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI2_CLK_ROOT             (1 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI3_CLK_ROOT             (2 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2  (3 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2  (4 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2  (5 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)
+#define GPR_GPR1_SAI1_MCLK2_SEL_SHIFT                           (3)
+#define GPR_GPR1_SAI1_MCLK2_SEL_MASK                            (7 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI1_CLK_ROOT             (0 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI2_CLK_ROOT             (1 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI3_CLK_ROOT             (2 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2  (3 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2  (4 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2  (5 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)
+#define GPR_GPR1_SAI1_MCLK3_SEL_SHIFT                           (6)
+#define GPR_GPR1_SAI1_MCLK3_SEL_MASK                            (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT           (0 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2           (1 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_SRCLK             (2 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)
+#  define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK          (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)
+#define GPR_GPR1_SAI2_MCLK3_SEL_SHIFT                           (8)
+#define GPR_GPR1_SAI2_MCLK3_SEL_MASK                            (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)
+#  define GPR_GPR1_SAI2_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT           (0 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)
+#  define GPR_GPR1_SAI2_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2           (1 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)
+#  define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_SRCLK             (2 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)
+#  define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK          (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)
+#define GPR_GPR1_SAI3_MCLK3_SEL_SHIFT                           (10)
+#define GPR_GPR1_SAI3_MCLK3_SEL_MASK                            (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)
+#  define GPR_GPR1_SAI3_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT           (0 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)
+#  define GPR_GPR1_SAI3_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2           (1 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)
+#  define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_SRCLK             (2 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)
+#  define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK          (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)
+#define GPR_GPR1_GINT                                           (1 << 12)
+#define GPR_GPR1_ENET1_CLK_SEL                                  (1 << 13)
+#define GPR_GPR1_USB_EXP_MODE_EN                                (1 << 15)
+#define GPR_GPR1_ENET1_TX_CLK_OUT_EN                            (1 << 17)
+#define GPR_GPR1_SAI1_MCLK_DIR_IN                               (0 << 19)
+#define GPR_GPR1_SAI1_MCLK_DIR_OUT                              (1 << 19)
+#define GPR_GPR1_SAI2_MCLK_DIR_IN                               (0 << 20)
+#define GPR_GPR1_SAI2_MCLK_DIR_OUT                              (1 << 20)
+#define GPR_GPR1_SAI3_MCLK_DIR_IN                               (0 << 21)
+#define GPR_GPR1_SAI3_MCLK_DIR_OUT                              (1 << 21)
+#define GPR_GPR1_EXC_MON_OKAY                                   (0 << 22)
+#define GPR_GPR1_EXC_MON_SLVERR                                 (1 << 22)
+#define GPR_GPR1_ENET_IMG_CLS_S_EN                              (1 << 23)
+#define GPR_GPR1_CM7_FORCE_HCLK_EN                              (1 << 31)
+
+/* General Purpose Register 2 (GPR2) */
+
+#define GPR_GPR2_L2_MEM_POWERSAVE_EN                            (1 << 12)
+#define GPR_GPR2_RAM_AUTO_CLK_GATING_EN                         (1 << 13)
+#define GPR_GPR2_L2_MEM_FORCE_DEEPSLEEP                         (1 << 14)
+#define GPR_GPR2_MQS_CLK_DIV_SHIFT                              (16)
+#define GPR_GPR2_MQS_CLK_DIV_MASK                               (255 << GPR_GPR2_MQS_CLK_DIV_SHIFT)
+# define GPR_GPR2_MQS_CLK_DIV(n)                                ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT)
+#define GPR_GPR2_MQS_SW_RST_EN                                  (1 << 24)
+#define GPR_GPR2_MQS_EN                                         (1 << 25)
+#define GPR_GPR2_MQS_OVERSAMPLE32                               (0 << 26)
+#define GPR_GPR2_MQS_OVERSAMPLE64                               (1 << 26)
+#define GPR_GPR2_QTIM1_TMR_RESET                                (1 << 28)
+#define GPR_GPR2_QTIM2_TMR_RESET                                (1 << 29)
+
+/* General Purpose Register 3 (GPR3) */
+
+#define GPR_GPR3_OCRAM_CTL_SHIFT                                (0)
+#define GPR_GPR3_OCRAM_CTL_MASK                                 (15 << GPR_GPR3_OCRAM_CTL_SHIFT)
+#  define GPR_GPR3_OCRAM_CTL_READ_DATA_PIPELINE_EN              (1 << GPR_GPR3_OCRAM_CTL_SHIFT)
+#  define GPR_GPR3_OCRAM_CTL_READ_ADDR_PIPELINE_EN              (2 << GPR_GPR3_OCRAM_CTL_SHIFT)
+#  define GPR_GPR3_OCRAM_CTL_WRITE_DATA_PIPELINE_EN             (4 << GPR_GPR3_OCRAM_CTL_SHIFT)
+#  define GPR_GPR3_OCRAM_CTL_WRITE_ADDR_PIPELINE_EN             (8 << GPR_GPR3_OCRAM_CTL_SHIFT)
+#define GPR_GPR3_DCP_KEY_SEL_128                                (0 << 4)
+#define GPR_GPR3_DCP_KEY_SEL_256                                (1 << 4)
+#define GPR_GPR3_OCRAM_STATUS_SHIFT                             (16)
+#define GPR_GPR3_OCRAM_STATUS_MASK                              (15 << GPR_GPR3_OCRAM_STATUS_SHIFT)
+#  define GPR_GPR3_OCRAM_STATUS_READ_DATA_PIPELINE_EN           (1 << GPR_GPR3_OCRAM_STATUS_SHIFT)
+#  define GPR_GPR3_OCRAM_STATUS_READ_ADDR_PIPELINE_EN           (2 << GPR_GPR3_OCRAM_STATUS_SHIFT)
+#  define GPR_GPR3_OCRAM_STATUS_WRITE_DATA_PIPELINE_EN          (4 << GPR_GPR3_OCRAM_STATUS_SHIFT)
+#  define GPR_GPR3_OCRAM_STATUS_WRITE_ADDR_PIPELINE_EN          (8 << GPR_GPR3_OCRAM_STATUS_SHIFT)
+
+/* General Purpose Register 4 (GPR4) */
+
+#define GPR_GRP4_EDMA_STOP_REQ                                  (1 << 0)
+#define GPR_GPR4_CAN1_STOP_REQ                                  (1 << 1)
+#define GPR_GPR4_CAN2_STOP_REQ                                  (1 << 2)
+#define GPR_GPR4_TRNG_STOP_REQ                                  (1 << 3)
+#define GPR_GPR4_ENET_STOP_REQ                                  (1 << 4)
+#define GPR_GPR4_SAI1_STOP_REQ                                  (1 << 5)
+#define GPR_GPR4_SAI2_STOP_REQ                                  (1 << 6)
+#define GPR_GPR4_SAI3_STOP_REQ                                  (1 << 7)
+#define GPR_GPR4_SEMC_STOP_REQ                                  (1 << 9)
+#define GPR_GPR4_PIT_STOP_REQ                                   (1 << 10)
+#define GPR_GPR4_FLEXSPI_STOP_REQ                               (1 << 11)
+#define GPR_GPR4_FLEXIO1_STOP_REQ                               (1 << 12)
+#define GPR_GRP4_EDMA_STOP_ACK                                  (1 << 16)
+#define GPR_GPR4_CAN1_STOP_ACK                                  (1 << 17)
+#define GPR_GPR4_CAN2_STOP_ACK                                  (1 << 18)
+#define GPR_GPR4_TRNG_STOP_ACK                                  (1 << 19)
+#define GPR_GPR4_ENET_STOP_ACK                                  (1 << 20)
+#define GPR_GPR4_SAI1_STOP_ACK                                  (1 << 21)
+#define GPR_GPR4_SAI2_STOP_ACK                                  (1 << 22)
+#define GPR_GPR4_SAI3_STOP_ACK                                  (1 << 23)
+#define GPR_GPR4_SEMC_STOP_ACK                                  (1 << 25)
+#define GPR_GPR4_PIT_STOP_ACK                                   (1 << 26)
+#define GPR_GPR4_FLEXSPI_STOP_ACK                               (1 << 27)
+#define GPR_GPR4_FLEXIO1_STOP_ACK                               (1 << 28)
+
+/* General Purpose Register 5 (GPR5) */
+
+#define GPR_GPR5_WDOG1_MASK                                     (1 << 6)
+#define GPR_GPR5_WDOG2_MASK                                     (1 << 7)
+#define GPR_GPR5_GPT2_CAPIN1_SEL_PAD                            (0 << 23)
+#define GPR_GPR5_GPT2_CAPIN1_SEL_ENET1                          (1 << 23)
+#define GPR_GPR5_ENET_EVENT3IN_SEL_ENET                         (0 << 25)
+#define GPR_GPR5_ENET_EVENT3IN_SEL_GPT2CMP1                     (1 << 25)
+#define GPR_GPR5_VREF_1M_CLK_GPT1_IPG_PERCLK                    (0 << 28)
+#define GPR_GPR5_VREF_1M_CLK_GPT1_ANATOP                        (1 << 28)
+#define GPR_GPR5_VREF_1M_CLK_GPT2_IPG_PERCLK                    (0 << 29)
+#define GPR_GPR5_VREF_1M_CLK_GPT2_ANATOP                        (1 << 29)
+
+/* General Purpose Register 6 (GPR6) */
+
+#define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT                   (0)
+#define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK                    (1 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_IOMUX                 (0 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_XBAR                  (1 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)
+#define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT                   (1)
+#define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK                    (1 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_IOMUX                 (0 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_XBAR                  (1 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)
+#define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT                   (2)
+#define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK                    (1 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_IOMUX                 (0 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_XBAR                  (1 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)
+#define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT                   (3)
+#define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK                    (1 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_IOMUX                 (0 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_XBAR                  (1 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)
+#define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT                   (4)
+#define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK                    (1 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_IOMUX                 (0 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_XBAR                  (1 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)
+#define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT                   (5)
+#define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK                    (1 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_IOMUX                 (0 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_XBAR                  (1 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)
+#define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT                   (6)
+#define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK                    (1 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_IOMUX                 (0 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_XBAR                  (1 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)
+#define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT                   (7)
+#define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK                    (1 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_IOMUX                 (0 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)
+#  define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_XBAR                  (1 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT                    (16)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK                     (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_IN                     (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_OUT                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT                    (17)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK                     (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_IN                     (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_OUT                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT                    (18)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK                     (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_IN                     (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_OUT                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT                    (19)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK                     (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_IN                     (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_OUT                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT                    (20)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK                     (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_IN                     (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_OUT                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT                    (21)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK                     (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_IN                     (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_OUT                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT                   (22)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_IN                    (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_OUT                   (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT                   (23)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_IN                    (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_OUT                   (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT                   (24)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_IN                    (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_OUT                   (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT                   (25)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_IN                    (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_OUT                   (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT                   (26)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_IN                    (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_OUT                   (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT                   (27)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_IN                    (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_OUT                   (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT                   (28)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_IN                    (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_OUT                   (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT                   (29)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_IN                    (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_OUT                   (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT                   (30)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_IN                    (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_OUT                   (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT                   (31)
+#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK                    (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_IN                    (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)
+#  define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_OUT                   (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)
+
+/* General Purpose Register 7 (GPR7) */
+
+#define GPR_GPR7_LPI2C1_STOP_REQ                                (1 << 0)
+#define GPR_GPR7_LPI2C2_STOP_REQ                                (1 << 1)
+#define GPR_GPR7_LPI2C3_STOP_REQ                                (1 << 2)
+#define GPR_GPR7_LPI2C4_STOP_REQ                                (1 << 3)
+#define GPR_GPR7_LPSPI1_STOP_REQ                                (1 << 4)
+#define GPR_GPR7_LPSPI2_STOP_REQ                                (1 << 5)
+#define GPR_GPR7_LPSPI3_STOP_REQ                                (1 << 6)
+#define GPR_GPR7_LPSPI4_STOP_REQ                                (1 << 7)
+#define GPR_GPR7_LPUART1_STOP_REQ                               (1 << 8)
+#define GPR_GPR7_LPUART2_STOP_REQ                               (1 << 9)
+#define GPR_GPR7_LPUART3_STOP_REQ                               (1 << 10)
+#define GPR_GPR7_LPUART4_STOP_REQ                               (1 << 11)
+#define GPR_GPR7_LPUART5_STOP_REQ                               (1 << 12)
+#define GPR_GPR7_LPUART6_STOP_REQ                               (1 << 13)
+#define GPR_GPR7_LPUART7_STOP_REQ                               (1 << 14)
+#define GPR_GPR7_LPUART8_STOP_REQ                               (1 << 15)
+#define GPR_GPR7_LPI2C1_STOP_ACK                                (1 << 16)
+#define GPR_GPR7_LPI2C2_STOP_ACK                                (1 << 17)
+#define GPR_GPR7_LPI2C3_STOP_ACK                                (1 << 18)
+#define GPR_GPR7_LPI2C4_STOP_ACK                                (1 << 19)
+#define GPR_GPR7_LPSPI1_STOP_ACK                                (1 << 20)
+#define GPR_GPR7_LPSPI2_STOP_ACK                                (1 << 21)
+#define GPR_GPR7_LPSPI3_STOP_ACK                                (1 << 22)
+#define GPR_GPR7_LPSPI4_STOP_ACK                                (1 << 23)
+#define GPR_GPR7_LPUART1_STOP_ACK                               (1 << 24)
+#define GPR_GPR7_LPUART2_STOP_ACK                               (1 << 25)
+#define GPR_GPR7_LPUART3_STOP_ACK                               (1 << 26)
+#define GPR_GPR7_LPUART4_STOP_ACK                               (1 << 27)
+#define GPR_GPR7_LPUART5_STOP_ACK                               (1 << 28)
+#define GPR_GPR7_LPUART6_STOP_ACK                               (1 << 29)
+#define GPR_GPR7_LPUART7_STOP_ACK                               (1 << 30)
+#define GPR_GPR7_LPUART8_STOP_ACK                               (1 << 31)
+
+/* General Purpose Register 8 (GPR8) */
+
+#define GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT                     (0)
+#define GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK                      (1 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPI2C1_IPG_ON_IN_STOP                        (0 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPI2C1_IPG_OFF_IN_STOP                       (1 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT                          (1)
+#define GPR_GPR8_LPI2C1_IPG_DOZE_MASK                           (1 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPI2C1_IPG_NOT_DOZED                         (0 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPI2C1_IPG_DOZED                             (1 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)
+#define GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT                     (2)
+#define GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK                      (1 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPI2C2_IPG_ON_IN_STOP                        (0 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPI2C2_IPG_OFF_IN_STOP                       (1 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT                          (3)
+#define GPR_GPR8_LPI2C2_IPG_DOZE_MASK                           (1 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPI2C2_IPG_NOT_DOZED                         (0 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPI2C2_IPG_DOZED                             (1 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)
+#define GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT                     (4)
+#define GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK                      (1 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPI2C3_IPG_ON_IN_STOP                        (0 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPI2C3_IPG_OFF_IN_STOP                       (1 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT                          (5)
+#define GPR_GPR8_LPI2C3_IPG_DOZE_MASK                           (1 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPI2C3_IPG_NOT_DOZED                         (0 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPI2C3_IPG_DOZED                             (1 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)
+#define GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT                     (6)
+#define GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK                      (1 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPI2C4_IPG_ON_IN_STOP                        (0 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPI2C4_IPG_OFF_IN_STOP                       (1 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT                          (7)
+#define GPR_GPR8_LPI2C4_IPG_DOZE_MASK                           (1 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPI2C4_IPG_NOT_DOZED                         (0 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPI2C4_IPG_DOZED                             (1 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)
+#define GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT                     (8)
+#define GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK                      (1 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPSPI1_IPG_ON_IN_STOP                        (0 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPSPI1_IPG_OFF_IN_STOP                       (1 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT                          (9)
+#define GPR_GPR8_LPSPI1_IPG_DOZE_MASK                           (1 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPSPI1_IPG_NOT_DOZED                         (0 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPSPI1_IPG_DOZED                             (1 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)
+#define GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT                     (10)
+#define GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK                      (1 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPSPI2_IPG_ON_IN_STOP                        (0 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPSPI2_IPG_OFF_IN_STOP                       (1 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT                          (11)
+#define GPR_GPR8_LPSPI2_IPG_DOZE_MASK                           (1 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPSPI2_IPG_NOT_DOZED                         (0 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPSPI2_IPG_DOZED                             (1 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)
+#define GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT                     (12)
+#define GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK                      (1 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPSPI3_IPG_ON_IN_STOP                        (0 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPSPI3_IPG_OFF_IN_STOP                       (1 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT                          (13)
+#define GPR_GPR8_LPSPI3_IPG_DOZE_MASK                           (1 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPSPI3_IPG_NOT_DOZED                         (0 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPSPI3_IPG_DOZED                             (1 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)
+#define GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT                     (14)
+#define GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK                      (1 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPSPI4_IPG_ON_IN_STOP                        (0 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPSPI4_IPG_OFF_IN_STOP                       (1 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT                          (15)
+#define GPR_GPR8_LPSPI4_IPG_DOZE_MASK                           (1 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPSPI4_IPG_NOT_DOZED                         (0 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPSPI4_IPG_DOZED                             (1 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)
+#define GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT                    (16)
+#define GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK                     (1 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART1_IPG_ON_IN_STOP                       (0 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART1_IPG_OFF_IN_STOP                      (1 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPUART1_IPG_DOZE_SHIFT                         (17)
+#define GPR_GPR8_LPUART1_IPG_DOZE_MASK                          (1 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART1_IPG_NOT_DOZED                        (0 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART1_IPG_DOZED                            (1 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)
+#define GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT                    (18)
+#define GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK                     (1 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART2_IPG_ON_IN_STOP                       (0 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART2_IPG_OFF_IN_STOP                      (1 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPUART2_IPG_DOZE_SHIFT                         (19)
+#define GPR_GPR8_LPUART2_IPG_DOZE_MASK                          (1 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART2_IPG_NOT_DOZED                        (0 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART2_IPG_DOZED                            (1 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)
+#define GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT                    (20)
+#define GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK                     (1 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART3_IPG_ON_IN_STOP                       (0 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART3_IPG_OFF_IN_STOP                      (1 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPUART3_IPG_DOZE_SHIFT                         (21)
+#define GPR_GPR8_LPUART3_IPG_DOZE_MASK                          (1 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART3_IPG_NOT_DOZED                        (0 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART3_IPG_DOZED                            (1 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)
+#define GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT                    (22)
+#define GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK                     (1 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART4_IPG_ON_IN_STOP                       (0 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART4_IPG_OFF_IN_STOP                      (1 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPUART4_IPG_DOZE_SHIFT                         (23)
+#define GPR_GPR8_LPUART4_IPG_DOZE_MASK                          (1 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART4_IPG_NOT_DOZED                        (0 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART4_IPG_DOZED                            (1 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)
+#define GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT                    (24)
+#define GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK                     (1 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART5_IPG_ON_IN_STOP                       (0 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART5_IPG_OFF_IN_STOP                      (1 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPUART5_IPG_DOZE_SHIFT                         (25)
+#define GPR_GPR8_LPUART5_IPG_DOZE_MASK                          (1 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART5_IPG_NOT_DOZED                        (0 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART5_IPG_DOZED                            (1 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)
+#define GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT                    (26)
+#define GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK                     (1 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART6_IPG_ON_IN_STOP                       (0 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART6_IPG_OFF_IN_STOP                      (1 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPUART6_IPG_DOZE_SHIFT                         (27)
+#define GPR_GPR8_LPUART6_IPG_DOZE_MASK                          (1 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART6_IPG_NOT_DOZED                        (0 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART6_IPG_DOZED                            (1 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)
+#define GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT                    (28)
+#define GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK                     (1 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART7_IPG_ON_IN_STOP                       (0 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART7_IPG_OFF_IN_STOP                      (1 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPUART7_IPG_DOZE_SHIFT                         (29)
+#define GPR_GPR8_LPUART7_IPG_DOZE_MASK                          (1 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART7_IPG_NOT_DOZED                        (0 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART7_IPG_DOZED                            (1 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)
+#define GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT                    (30)
+#define GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK                     (1 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART8_IPG_ON_IN_STOP                       (0 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR8_LPUART8_IPG_OFF_IN_STOP                      (1 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR8_LPUART8_IPG_DOZE_SHIFT                         (31)
+#define GPR_GPR8_LPUART8_IPG_DOZE_MASK                          (1 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART8_IPG_NOT_DOZED                        (0 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)
+#  define GPR_GPR8_LPUART8_IPG_DOZED                            (1 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)
+
+/* General Purpose Register 9 (GPR9) - Reserved */
+
+/* General Purpose Register 10 (GPR10) */
+
+#define GPR_GPR10_NIDEN                                         (1 << 0)
+#define GPR_GPR10_DBG_EN                                        (1 << 1)
+#define GPR_GPR10_SEC_ERR_RESP                                  (1 << 2)
+#define GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX                        (1 << 4)
+#define GPR_GPR10_OCRAM_TZ_EN                                   (1 << 8)
+#define GPR_GPR10_OCRAM_TZ_ADDR_SHIFT                           (9)
+#define GPR_GPR10_OCRAM_TZ_ADDR_MASK                            (0x3f << GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)
+#  define GPR_GPR10_OCRAM_TZ_ADDR(n)                            ((uint32_t)(n) << GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)
+#define GPR_GPR10_LOCK_NIDEN                                    (1 << 16)
+#define GPR_GPR10_LOCK_DBG_EN                                   (1 << 17)
+#define GPR_GPR10_LOCK_SEC_ERR_RESP                             (1 << 18)
+#define GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX                   (1 << 20)
+#define GPR_GPR10_LOCK_OCRAM_TZ_EN                              (1 << 24)
+#define GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT                      (25)
+#define GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK                       (0x3f << GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)
+#  define GPR_GPR10_LOCK_OCRAM_TZ_ADDR(n)                       ((uint32_t)(n) << GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)
+
+/* General Purpose Register 11 (GPR11) */
+
+#define GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS                      (0)
+#define GPR_GPR11_M7_APC_AC_R0_CTRL_MASK                        (3 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS)
+#  define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_ACCESS                 (0 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS)
+#  define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_DEBUG                  (1 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS)
+#define GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS                      (2)
+#define GPR_GPR11_M7_APC_AC_R1_CTRL_MASK                        (3 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS)
+#  define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_ACCESS                 (0 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS)
+#  define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_DEBUG                  (1 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS)
+#define GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS                      (4)
+#define GPR_GPR11_M7_APC_AC_R2_CTRL_MASK                        (3 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS)
+#  define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_ACCESS                 (0 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS)
+#  define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_DEBUG                  (1 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS)
+#define GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS                      (6)
+#define GPR_GPR11_M7_APC_AC_R3_CTRL_MASK                        (3 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS)
+#  define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_ACCESS                 (0 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS)
+#  define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_DEBUG                  (1 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS)
+#define GPR_GPR11_BEE_DE_RX_EN_SHIFTS                           (8)
+#define GPR_GPR11_BEE_DE_RX_EN_MASK                             (0xf << GPR_GPR11_BEE_DE_RX_EN_SHIFTS)
+#  define GPR_GPR11_BEE_DE_RX_EN(n)                             ((uint32_t)(n) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS)
+#  define GPR_GPR11_BEE_DE_R0_EN                                (1) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS)
+#  define GPR_GPR11_BEE_DE_R1_EN                                (2) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS)
+#  define GPR_GPR11_BEE_DE_R2_EN                                (4) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS)
+#  define GPR_GPR11_BEE_DE_R3_EN                                (8) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS)
+#define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS                 (16)
+#define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK                   (3 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS)
+#  define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_NO_ACCESS            (0 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS)
+#  define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_NO_DEBUG             (1 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS)
+#define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS                 (18)
+#define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK                   (3 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS)
+#  define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_NO_ACCESS            (0 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS)
+#  define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_NO_DEBUG             (1 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS)
+#define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS                 (20)
+#define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK                   (3 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS)
+#  define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_NO_ACCESS            (0 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS)
+#  define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_NO_DEBUG             (1 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS)
+#define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS                 (22)
+#define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK                   (3 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS)
+#  define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_NO_ACCESS            (0 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS)
+#  define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_NO_DEBUG             (1 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS)
+#define GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS                      (24)
+#define GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK                        (0xf << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS)
+#  define GPR_GPR11_LOCK_BEE_DE_RX_EN(n)                        ((uint32_t)(n) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS)
+#  define GPR_GPR11_LOCK_BEE_DE_R0_EN                           (1) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS)
+#  define GPR_GPR11_LOCK_BEE_DE_R1_EN                           (2) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS)
+#  define GPR_GPR11_LOCK_BEE_DE_R2_EN                           (4) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS)
+#  define GPR_GPR11_LOCK_BEE_DE_R3_EN                           (8) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS)
+
+/* General Purpose Register 12 (GPR12) */
+
+#define GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT                   (0)
+#define GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK                    (1 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR12_FLEXIO1_IPG_ON_IN_STOP                      (0 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR12_FLEXIO1_IPG_OFF_IN_STOP                     (1 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)
+#define GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT                        (1)
+#define GPR_GPR12_FLEXIO1_IPG_DOZE_MASK                         (1 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)
+#  define GPR_GPR12_FLEXIO1_IPG_NOT_DOZED                       (0 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)
+#  define GPR_GPR12_FLEXIO1_IPG_DOZED                           (1 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)
+#define GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT                      (4)
+#define GPR_GPR12_ACMP_IPG_STOP_MODE_MASK                       (1 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR12_ACMP_IPG_ON_IN_STOP                         (0 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)
+#  define GPR_GPR12_ACMP_IPG_OFF_IN_STOP                        (1 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)
+
+/* General Purpose Register 13 (GPR13) */
+
+#define GPR_GPR13_ARCACHE_USDHC_CACHEABLE                       (1 << 0)
+#define GPR_GPR13_AWCACHE_USDHC_CACHEABLE                       (1 << 1)
+#define GPR_GPR13_CACHE_ENET_CACHEABLE                          (1 << 7)
+#define GPR_GPR13_CACHE_USB_CACHEABLE                           (1 << 13)
+
+/* General Purpose Register 14 (GPR14) */
+
+#define GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN                        (1 << 0)
+#define GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN                        (1 << 1)
+#define GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN                        (1 << 2)
+#define GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN                        (1 << 3)
+#define GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP                        (1 << 4)
+#define GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP                        (1 << 5)
+#define GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP                        (1 << 6)
+#define GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP                        (1 << 7)
+#define GPR_GPR14_ACMP1_SAMPLE_SYNC_EN                          (1 << 8)
+#define GPR_GPR14_ACMP2_SAMPLE_SYNC_EN                          (1 << 9)
+#define GPR_GPR14_ACMP3_SAMPLE_SYNC_EN                          (1 << 10)
+#define GPR_GPR14_ACMP4_SAMPLE_SYNC_EN                          (1 << 11)
+#define GPR_GPR14_CM7_CFGITCMSZ_SHIFT                           (16)
+#define GPR_GPR14_CM7_CFGITCMSZ_MASK                            (0x4 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGITCMSZ_0KB                           (0 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGITCMSZ_4KB                           (3 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGITCMSZ_8KB                           (4 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGITCMSZ_16KB                          (6 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGITCMSZ_32KB                          (6 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGITCMSZ_64KB                          (7 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGITCMSZ_128KB                         (8 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGITCMSZ_256KB                         (9 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT)
+#define GPR_GPR14_CM7_CFGDTCMSZ_SHIFT                           (20)
+#define GPR_GPR14_CM7_CFGDTCMSZ_MASK                            (0xf << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGDTCMSZ_0KB                           (0 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGDTCMSZ_4KB                           (3 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGDTCMSZ_8KB                           (4 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGDTCMSZ_16KB                          (6 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGDTCMSZ_32KB                          (6 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGDTCMSZ_64KB                          (7 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGDTCMSZ_128KB                         (8 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)
+#  define GPR_GPR14_CM7_CFGDTCMSZ_256KB                         (9 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)
+
+/* General Purpose Register 15 (GPR16) - Reserved */
+
+/* General Purpose Register 16 (GPR16) */
+
+#define GPR_GPR16_INIT_ITCM_EN                                  (1 << 0)
+#define GPR_GPR16_INIT_DTCM_EN                                  (1 << 1)
+#define GPR_GPR16_FLEXRAM_BANK_CFG_SELF                         (1 << 2)
+
+/* General Purpose Register 17 (GPR17) */
+
+#define GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT                        (0)
+#define GPR_GPR17_FLEXRAM_BANK_CFG_MASK                         (0xffffffff << GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)
+#define GPR_GPR17_FLEXRAM_BANK_CFG(n)                           ((uint32_t)(n)) << GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)
+#define GPR_GPR17_FLEXRAM_BANK0_SHIFT                           (0)
+#define GPR_GPR17_FLEXRAM_BANK0_MASK                            (3 << GPR_GPR17_FLEXRAM_BANK0_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK0_NOTUSED                       (0 << GPR_GPR17_FLEXRAM_BANK0_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK0_OCRAM                         (1 << GPR_GPR17_FLEXRAM_BANK0_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK0_DTCM                          (2 << GPR_GPR17_FLEXRAM_BANK0_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK0_ITCM                          (3 << GPR_GPR17_FLEXRAM_BANK0_SHIFT)
+#define GPR_GPR17_FLEXRAM_BANK1_SHIFT                           (2)
+#define GPR_GPR17_FLEXRAM_BANK1_MASK                            (3 << GPR_GPR17_FLEXRAM_BANK1_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK1_NOTUSED                       (0 << GPR_GPR17_FLEXRAM_BANK1_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK1_OCRAM                         (1 << GPR_GPR17_FLEXRAM_BANK1_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK1_DTCM                          (2 << GPR_GPR17_FLEXRAM_BANK1_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK1_ITCM                          (3 << GPR_GPR17_FLEXRAM_BANK1_SHIFT)
+#define GPR_GPR17_FLEXRAM_BANK2_SHIFT                           (4)
+#define GPR_GPR17_FLEXRAM_BANK2_MASK                            (3 << GPR_GPR17_FLEXRAM_BANK2_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK2_NOTUSED                       (0 << GPR_GPR17_FLEXRAM_BANK2_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK2_OCRAM                         (1 << GPR_GPR17_FLEXRAM_BANK2_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK2_DTCM                          (2 << GPR_GPR17_FLEXRAM_BANK2_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK2_ITCM                          (3 << GPR_GPR17_FLEXRAM_BANK2_SHIFT)
+#define GPR_GPR17_FLEXRAM_BANK3_SHIFT                           (6)
+#define GPR_GPR17_FLEXRAM_BANK3_MASK                            (3 << GPR_GPR17_FLEXRAM_BANK3_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK3_NOTUSED                       (0 << GPR_GPR17_FLEXRAM_BANK3_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK3_OCRAM                         (1 << GPR_GPR17_FLEXRAM_BANK3_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK3_DTCM                          (2 << GPR_GPR17_FLEXRAM_BANK3_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK3_ITCM                          (3 << GPR_GPR17_FLEXRAM_BANK3_SHIFT)
+#define GPR_GPR17_FLEXRAM_BANK4_SHIFT                           (8)
+#define GPR_GPR17_FLEXRAM_BANK4_MASK                            (3 << GPR_GPR17_FLEXRAM_BANK4_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK4_NOTUSED                       (0 << GPR_GPR17_FLEXRAM_BANK4_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK4_OCRAM                         (1 << GPR_GPR17_FLEXRAM_BANK4_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK4_DTCM                          (2 << GPR_GPR17_FLEXRAM_BANK4_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK4_ITCM                          (3 << GPR_GPR17_FLEXRAM_BANK4_SHIFT)
+#define GPR_GPR17_FLEXRAM_BANK5_SHIFT                           (10)
+#define GPR_GPR17_FLEXRAM_BANK5_MASK                            (3 << GPR_GPR17_FLEXRAM_BANK5_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK5_NOTUSED                       (0 << GPR_GPR17_FLEXRAM_BANK5_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK5_OCRAM                         (1 << GPR_GPR17_FLEXRAM_BANK5_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK5_DTCM                          (2 << GPR_GPR17_FLEXRAM_BANK5_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK5_ITCM                          (3 << GPR_GPR17_FLEXRAM_BANK5_SHIFT)
+#define GPR_GPR17_FLEXRAM_BANK6_SHIFT                           (12)
+#define GPR_GPR17_FLEXRAM_BANK6_MASK                            (3 << GPR_GPR17_FLEXRAM_BANK6_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK6_NOTUSED                       (0 << GPR_GPR17_FLEXRAM_BANK6_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK6_OCRAM                         (1 << GPR_GPR17_FLEXRAM_BANK6_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK6_DTCM                          (2 << GPR_GPR17_FLEXRAM_BANK6_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK6_ITCM                          (3 << GPR_GPR17_FLEXRAM_BANK6_SHIFT)
+#define GPR_GPR17_FLEXRAM_BANK7_SHIFT                           (14)
+#define GPR_GPR17_FLEXRAM_BANK7_MASK                            (3 << GPR_GPR17_FLEXRAM_BANK7_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK7_NOTUSED                       (0 << GPR_GPR17_FLEXRAM_BANK7_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK7_OCRAM                         (1 << GPR_GPR17_FLEXRAM_BANK7_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK7_DTCM                          (2 << GPR_GPR17_FLEXRAM_BANK7_SHIFT)
+#  define GPR_GPR17_FLEXRAM_BANK7_ITCM                          (3 << GPR_GPR17_FLEXRAM_BANK7_SHIFT)
+
+/* General Purpose Register 18 (GPR18) */
+
+#define GPR_GPR18_LOCK_M7_APC_AC_R0_BOT                         (1 << 0)
+#define GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT                        (3)
+#define GPR_GPR18_M7_APC_AC_R0_BOT_MASK                         (0x1fffffff << GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)
+#define GPR_GPR18_M7_APC_AC_R0_BOT(n)                           ((uint32_t)(n)) << GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)
+
+/* General Purpose Register 19 (GPR19) */
+
+#define GPR_GPR19_LOCK_M7_APC_AC_R0_TOP                         (1 << 0)
+#define GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT                        (3)
+#define GPR_GPR19_M7_APC_AC_R0_TOP_MASK                         (0x1fffffff << GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)
+#define GPR_GPR19_M7_APC_AC_R0_TOP(n)                           ((uint32_t)(n)) << GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)
+
+/* General Purpose Register 20 (GPR20) */
+
+#define GPR_GPR20_LOCK_M7_APC_AC_R1_BOT                         (1 << 0)
+#define GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT                        (3)
+#define GPR_GPR20_M7_APC_AC_R1_BOT_MASK                         (0x1fffffff << GPR_GPR18_M7_APC_AC_R1_BOT_SHIFT)
+#define GPR_GPR20_M7_APC_AC_R1_BOT(n)                           ((uint32_t)(n)) << GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)
+
+/* General Purpose Register 21 (GPR21) */
+
+#define GPR_GPR21_LOCK_M7_APC_AC_R1_TOP                         (1 << 0)
+#define GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT                        (3)
+#define GPR_GPR21_M7_APC_AC_R1_TOP_MASK                         (0x1fffffff << GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)
+#define GPR_GPR21_M7_APC_AC_R1_TOP(n)                           ((uint32_t)(n)) << GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)
+
+/* General Purpose Register 22 (GPR22) */
+
+#define GPR_GPR22_LOCK_M7_APC_AC_R2_BOT                         (1 << 0)
+#define GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT                        (3)
+#define GPR_GPR22_M7_APC_AC_R2_BOT_MASK                         (0x1fffffff << GPR_GPR18_M7_APC_AC_R2_BOT_SHIFT)
+#define GPR_GPR22_M7_APC_AC_R2_BOT(n)                           ((uint32_t)(n)) << GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)
+
+/* General Purpose Register 23 (GPR23) */
+
+#define GPR_GPR23_LOCK_M7_APC_AC_R2_TOP                         (1 << 0)
+#define GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT                        (3)
+#define GPR_GPR23_M7_APC_AC_R2_TOP_MASK                         (0x1fffffff << GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)
+#define GPR_GPR23_M7_APC_AC_R2_TOP(n)                           ((uint32_t)(n)) << GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)
+
+/* General Purpose Register 24 (GPR24) */
+
+#define GPR_GPR24_LOCK_M7_APC_AC_R3_BOT                         (1 << 0)
+#define GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT                        (3)
+#define GPR_GPR24_M7_APC_AC_R3_BOT_MASK                         (0x1fffffff << GPR_GPR18_M7_APC_AC_R3_BOT_SHIFT)
+#define GPR_GPR24_M7_APC_AC_R3_BOT(n)                           ((uint32_t)(n)) << GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)
+
+/* General Purpose Register 25 (GPR25) */
+
+#define GPR_GPR25_LOCK_M7_APC_AC_R3_TOP                         (1 << 0)
+#define GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT                        (3)
+#define GPR_GPR25_M7_APC_AC_R3_TOP_MASK                         (0x1fffffff << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)
+#define GPR_GPR25_M7_APC_AC_R3_TOP(n)                           ((uint32_t)(n)) << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_IOMUXC_H */
diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_memorymap.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_memorymap.h
new file mode 100644
index 00000000000..c27907cecd4
--- /dev/null
+++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_memorymap.h
@@ -0,0 +1,261 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/hardware/rt102x/imxrt102x_memorymap.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *           Dave Marples 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_MEMORYMAP_H
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include 
+
+/*****************************************************************************
+ * Pre-processor Definitions
+ *****************************************************************************/
+
+/* System memory map */
+
+#define IMXRT_ITCM_BASE           0x00000000  /* 256KB ITCM */
+                               /* 0x00040000     768KB ITCM Reserved */
+                               /* 0x00100000     1MB ITCM Reserved */
+#define IMXRT_ROMCP_BASE          0x00200000  /* 96KB ROMCP */
+                               /* 0x00218000     416KB ROMCP Reserved */
+                               /* 0x00280000     1536KB Reserved */
+                               /* 0x00400000     124MB Reserved */
+                               /* 0x00800000     1527MB Reserved */
+#define IMXRT_FLEXSPI_BASE        0x06000000  /* 128MB FlexSPI (Aliased) */
+#define IMXRT_SEMCA_BASE          0x06800000  /* 639MB SEMC (Aliased) */
+                               /* 0x90000000 256MB SEMC (Aliased) */
+#define IMXRT_DTCM_BASE           0x20000000  /* 256KB DTCM */
+                               /* 0x20040000     768KB DTCM Reserved */
+                               /* 0x20100000     1MB Reserved */
+#define IMXRT_OCRAM_BASE          0x20200000  /* 256KB OCRAM */
+                               /* 0x20240000     1792KB OCRAM Reserved */
+                               /* 0x20400000     252MB Reserved */
+                               /* 0x30000000     256MB Reserved */
+#define IMXRT_AIPS1_BASE          0x40000000  /* 1MB AIPS-1 */
+#define IMXRT_AIPS2_BASE          0x40100000  /* 1MB AIPS-2 */
+#define IMXRT_AIPS3_BASE          0x40200000  /* 1MB AIPS-3 */
+#define IMXRT_AIPS4_BASE          0x40300000  /* 1MB AIPS-4 */
+                               /* 0x40400000     12MB Reserved */
+                               /* 0x41000000     1MB Reserved */
+#define IMXRT_MCNF_BASE           0x41100000  /* 1MB "m" configuration port */
+                               /* 41200000       1MB Reserved for "per" GPV */
+                               /* 41300000       1MB Reserved for "ems" GPV */
+#define IMXRT_CPUCNF_BASE         0x41400000  /* 1MB "cpu" configuration port */
+                               /* 0x41500000     1MB GPV Reserved */
+                               /* 0x41600000     1MB GPV Reserved */
+                               /* 0x41700000     1MB GPV Reserved */
+                               /* 0x41800000     8MB Reserved */
+                               /* 0x42000000     32MB Reserved */
+                               /* 0x44000000     64MB Reserved */
+                               /* 0x48000000     384MB Reserved */
+#define IMXRT_FLEXCIPHER_BASE     0x60000000  /* 504MB FlexSPI/ FlexSPI ciphertext */
+#define IMXRT_FLEXSPITX_BASE      0x7f800000  /* 4MB FlexSPI TX FIFO */
+#define IMXRT_FLEXSPIRX_BASE      0x7fc00000  /* 4MB FlexSPI RX FIFO */
+#define IMXRT_EXTMEM_BASE         0x80000000  /* 1.5GB SEMC external memories shared memory space */
+#define IMXRT_CM7_BASE            0xe0000000  /* 1MB CM7 PPB */
+                               /* 0xe0100000     511MB Reserved */
+
+/* AIPS-1 memory map */
+
+                               /* 0x40000000     256KB Reserved */
+                               /* 0x40040000     240KB Reserved */
+#define IMXRT_AIPS1CNF_BASE       0x4007c000  /* 16KB AIPS-1 Configuration */
+#define IMXRT_DCDC_BASE           0x40080000  /* 16KB DCDC */
+#define IMXRT_PIT_BASE            0x40084000  /* 16KB PIT */
+                               /* 0x40088000     16KB Reserved */
+                               /* 0x4008c000     16KB Reserved */
+                               /* 0x40090000     16KB Reserved */
+#define IMXRT_ACMP_BASE           0x40094000  /* 16KB ACMP */
+                               /* 0x40098000     16KB Reserved */
+                               /* 0x4009c000     16KB Reserved */
+                               /* 0x400a0000     16KB Reserved */
+#define IMXRT_IOMUXCSNVSGPR_BASE  0x400a4000  /* 16KB IOMUXC_SNVS_GPR */
+#define IMXRT_IOMUXCSNVS_BASE     0x400a8000  /* 16KB IOMUXC_SNVS */
+#define IMXRT_IOMUXCGPR_BASE      0x400ac000  /* 16KB IOMUXC_GPR */
+#define IMXRT_FLEXRAM_BASE        0x400b0000  /* 16KB CM7_MXRT(FLEXRAM) */
+#define IMXRT_EWM_BASE            0x400b4000  /* 16KB EWM */
+#define IMXRT_WDOG1_BASE          0x400b8000  /* 16KB WDOG1 */
+#define IMXRT_WDOG3_BASE          0x400bc000  /* 16KB WDOG3 */
+#define IMXRT_GPIO5_BASE          0x400c0000  /* 16KB GPIO5 */
+#define IMXRT_ADC1_BASE           0x400c4000  /* 16KB ADC1 */
+#define IMXRT_ADC2_BASE           0x400c8000  /* 16KB ADC2 */
+#define IMXRT_TRNG_BASE           0x400cc000  /* 16KB TRNG */
+#define IMXRT_WDOG2_BASE          0x400d0000  /* 16KB WDOG2 */
+#define IMXRT_SNVSHP_BASE         0x400d4000  /* 16KB SNVS_HP */
+#define IMXRT_ANATOP_BASE         0x400d8000  /* 16KB ANATOP */
+#define IMXRT_CSU_BASE            0x400dc000  /* 16KB CSU */
+                               /* 0x400e0000     16KB Reserved */
+                               /* 0x400e4000     16KB Reserved */
+#define IMXRT_EDMA_BASE           0x400e8000  /* 16KB EDMA */
+#define IMXRT_DMAMUX_BASE         0x400ec000  /* 16KB DMA_CH_MUX */
+                               /* 400f0000       16KB Reserved */
+#define IMXRT_GPC_BASE            0x400f4000  /* 16KB GPC */
+#define IMXRT_SRC_BASE            0x400f8000  /* 16KB SRC */
+#define IMXRT_CCM_BASE            0x400fc000  /* 16KB CCM */
+
+/* AIPS-2 memory map */
+
+                               /* 0x40100000     256KB Reserved */
+                               /* 0x40140000     240KB Reserved */
+#define IMXRT_AIPS2CNF_BASE       0x4017c000  /* 16KB AIPS-2 Configuration */
+#define IMXRT_ROMCPC_BASE         0x40180000  /* 16KB ROMCP controller*/
+#define IMXRT_LPUART1_BASE        0x40184000  /* 16KB LPUART1 */
+#define IMXRT_LPUART2_BASE        0x40188000  /* 16KB LPUART2 */
+#define IMXRT_LPUART3_BASE        0x4018c000  /* 16KB LPUART3 */
+#define IMXRT_LPUART4_BASE        0x40190000  /* 16KB LPUART4 */
+#define IMXRT_LPUART5_BASE        0x40194000  /* 16KB LPUART5 */
+#define IMXRT_LPUART6_BASE        0x40198000  /* 16KB LPUART6 */
+#define IMXRT_LPUART7_BASE        0x4019c000  /* 16KB LPUART7 */
+#define IMXRT_LPUART8_BASE        0x401a0000  /* 16KB LPUART8 */
+                               /* 0x401a4000     16KB Reserved */
+                               /* 0x401a8000     16KB Reserved */
+#define IMXRT_FLEXIO1_BASE        0x401ac000  /* 16KB FlexIO1 */
+                               /* 0x401b0000     16KB Reserved */
+                               /* 0x401b4000     16KB Reserved */
+#define IMXRT_GPIO1_BASE          0x401b8000  /* 16KB GPIO1 */
+#define IMXRT_GPIO2_BASE          0x401bc000  /* 16KB GPIO2 */
+#define IMXRT_GPIO3_BASE          0x401c0000  /* 16KB GPIO3 */
+                               /* 0x401c4000     16KB Reserved */
+                               /* 0x401c8000     16KB Reserved */
+                               /* 0x401cc000     16KB Reserved */
+#define IMXRT_CAN1_BASE           0x401d0000  /* 16KB CAN1 */
+#define IMXRT_CAN2_BASE           0x401d4000  /* 16KB CAN2 */
+                               /* 0x401d8000     16KB Reserved */
+#define IMXRT_QTIMER1_BASE        0x401dc000  /* 16KB QTimer1 */
+#define IMXRT_QTIMER2_BASE        0x401e0000  /* 16KB QTimer2 */
+                               /* 0x401e4000     16KB Reserved */
+                               /* 0x401e8000     16KB Reserved */
+#define IMXRT_GPT1_BASE           0x401ec000  /* 16KB GPT1 */
+#define IMXRT_GPT2_BASE           0x401f0000  /* 16KB GPT2 */
+#define IMXRT_OCOTP_BASE          0x401f4000  /* 16KB OCOTP */
+#define IMXRT_IOMUXC_BASE         0x401f8000  /* 16KB IOMUXC */
+#define IMXRT_KPP_BASE            0x401fc000  /* 16KB KPP */
+
+/* AIPS-3 memory map */
+
+                               /* 0x40200000     256KB Reserved */
+                               /* 0x40240000     240KB Reserved */
+#define IMXRT_AIOS3CNF_BASE       0x4027c000  /* 16KB AIPS-3 Configuration */
+                               /* 0x40280000     16KB Reserved */
+                               /* 0x40284000     16KB Reserved */
+                               /* 0x40288000     16KB Reserved */
+                               /* 0x4028c000     16KB Reserved */
+                               /* 0x40290000     16KB Reserved */
+                               /* 0x40294000     16KB Reserved */
+                               /* 0x40298000     16KB Reserved */
+                               /* 0x4029c000     16KB Reserved */
+                               /* 0x402a0000     16KB Reserved */
+                               /* 0x402a4000     16KB Reserved */
+#define IMXRT_FLEXSPIC_BASE       0x402a8000  /* 16KB FlexSPI controller */
+                               /* 0x402ac000     16KB Reserved */
+                               /* 0x402b0000     16KB Reserved */
+                               /* 0x402b4000     16KB Reserved */
+                               /* 0x402b8000     16KB Reserved */
+                               /* 0x402bc000     16KB Reserved */
+#define IMXRT_USDHC1_BASE         0x402c0000  /* 16KB USDHC1 */
+#define IMXRT_USDHC2_BASE         0x402c4000  /* 16KB USDHC2 */
+                               /* 0x402c8000     16KB Reserved */
+                               /* 0x402cc000     16KB Reserved */
+                               /* 0x402d0000     16KB Reserved */
+                               /* 0x402d4000     16KB Reserved */
+#define IMXRT_ENET_BASE           0x402d8000  /* 16KB ENET */
+                              /*  0x402dc000     16KB Reserved */
+#define IMXRT_USB_BASE            0x402e0000  /* 16KB USB(USB) */
+                               /* 0x402e4000     16KB Reserved */
+                               /* 0x402e8000     16KB Reserved */
+                               /* 0x402ec000     16KB Reserved */
+#define IMXRT_SEMC_BASE           0x402f0000  /* 16KB SEMC */
+                               /* 0x402f4000     16KB Reserved */
+                               /* 0x402f8000     16KB Reserved */
+#define IMXRT_DCP_BASE            0x402fc000  /* 16KB DCP */
+
+/* AIPS-4 memory map */
+
+                               /* 0x40300000     256KB Reserved */
+                               /* 0x40340000     240KB Reserved */
+#define IMXRT_AIPS4CNF_BASE       0x4037c000  /* 16KB AIPS-4 Configuration */
+#define IMXRT_SPDIF_BASE          0x40380000  /* 16KB SPDIF */
+#define IMXRT_SAI1_BASE           0x40384000  /* 16KB SAI1 */
+#define IMXRT_SAI2_BASE           0x40388000  /* 16KB SAI2 */
+#define IMXRT_SAI3_BASE           0x4038c000  /* 16KB SAI3 */
+                               /* 0x40390000     16KB Reserved */
+#define IMXRT_LPSPI1_BASE         0x40394000  /* 16KB LPSPI1 */
+#define IMXRT_LPSPI2_BASE         0x40398000  /* 16KB LPSPI2 */
+#define IMXRT_LPSPI3_BASE         0x4039c000  /* 16KB LPSPI3 */
+#define IMXRT_LPSPI4_BASE         0x403a0000  /* 16KB LPSPI4 */
+                               /* 0x403a4000     16KB Reserved */
+                               /* 0x403a8000     16KB Reserved */
+                               /* 0x403ac000     16KB Reserved */
+#define IMXRT_ADCETC_BASE         0x403b0000  /* 16KB ADC_ETC */
+#define IMXRT_AOI1_BASE           0x403b4000  /* 16KB AOI1 */
+                               /* 0x403b8000     16KB Reserved */
+#define IMXRT_XBAR1_BASE          0x403bc000  /* 16KB XBAR1 */
+#define IMXRT_XBAR2_BASE          0x403c0000  /* 16KB XBAR2 */
+                               /* 0x403c4000     16KB Reserved */
+#define IMXRT_ENC1_BASE           0x403c8000  /* 16KB ENC1 */
+#define IMXRT_ENC2_BASE           0x403cc000  /* 16KB ENC2 */
+                               /* 0x403d0000     16KB Reserved */
+                               /* 0x403d4000     16KB Reserved */
+                               /* 0x403d8000     16KB Reserved */
+#define IMXRT_FLEXPWM1_BASE       0x403dc000  /* 16KB FLEXPWM1 */
+#define IMXRT_FLEXPWM2_BASE       0x403e0000  /* 16KB FLEXPWM2 */
+                               /* 0x403e4000     16KB Reserved */
+                               /* 0x403e8000     16KB Reserved */
+#define IMXRT_BEE_BASE            0x403ec000  /* 16KB BEE */
+#define IMXRT_LPI2C1_BASE         0x403f0000  /* 16KB  */
+#define IMXRT_LPI2C2_BASE         0x403f4000  /* 16KB LPI2C2 */
+#define IMXRT_LPI2C3_BASE         0x403f8000  /* 16KB LPI2C3 */
+#define IMXRT_LPI2C4_BASE         0x403fc000  /* 16KB LPI2C4 */
+
+/* PPB memory map */
+
+#define IMXRT_TPIU_BASE           0xe0040000  /* 4KB TPIU */
+#define IMXRT_ETM_BASE            0xe0041000  /* 4KB ETM */
+#define IMXRT_CTI_BASE            0xe0042000  /* 4KB CTI */
+#define IMXRT_TSGEN_BASE          0xe0043000  /* 4KB TSGEN */
+#define IMXRT_PPBRES_BASE         0xe0044000  /* 4KB PPB RES */
+                               /* 0xe0045000     236KB PPB Reserved */
+#define IMXRT_MCM_BASE            0xe0080000  /* 4KB MCM */
+                               /* 0xe0081000     444KB PPB Reserved */
+                               /* 0xe00f0000     52KB PPB Reserved */
+#define IMXRT_SYSROM_BASE         0xe00fd000  /* 4KB SYS ROM */
+#define IMXRT_PROCROM_BASE        0xe00fe000  /* 4KB Processor ROM */
+#define IMXRT_PPBROM_BASE         0xe00ff000  /* 4KB PPB ROM */
+
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_MEMORYMAP_H */
diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_pinmux.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_pinmux.h
new file mode 100644
index 00000000000..023e087f1bc
--- /dev/null
+++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_pinmux.h
@@ -0,0 +1,914 @@
+/*****************************************************************************
+ * arch/arm/src/imxrt/hardware/rt102x/imxrt102x_pinmux.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *           Dave Marples 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_PINMUX_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_PINMUX_H
+
+/*****************************************************************************
+ * Included Files
+ *****************************************************************************/
+
+#include 
+#include "imxrt_iomuxc.h"
+
+/*****************************************************************************
+ * Pre-processor Definitions
+ *****************************************************************************/
+
+/* Alternate Pin Functions.
+ *
+ * Alternative pin selections are provided with a numeric suffix like _1, _2,
+ * etc.  Drivers, however, will use the pin selection without the numeric
+ * suffix.  Additional definitions are required in the board.h file.
+ * For example, if LPUART1 CTS connects via the AD_B1_04 pin, then the
+ * following definition should appear in the board.h header file for
+ * that board:
+ *
+ *   #define GPIO_LPUART3_CTS GPIO_LPUART3_CTS_1
+ *
+ * The driver will then automatically configure to use the AD_B1_04 pin
+ * for LPUART1 CTS.
+ */
+
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific IOMUX options such as
+ * frequency, open-drain, push-pull, and pull-up/down!  Just the basics are
+ * defined for most pins in this file.  See the upper imxrt_gpio.h and
+ * imxrt_iomuxc.h header files for available definitions.
+ */
+
+/* Analog Comparator (ACMP) */
+
+#define GPIO_ACMP_OUT00                (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX))
+#define GPIO_ACMP_OUT01                (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX))
+#define GPIO_ACMP_OUT02                (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX))
+#define GPIO_ACMP_OUT03                (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX))
+
+/* ARM */
+
+#define GPIO_ARM_CM7_RXEV              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX))
+#define GPIO_ARM_CM7_TXEV              (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX))
+
+/* Clock Controller Module (CCM) */
+
+#define GPIO_CCM_CLKO1                 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX))
+#define GPIO_CCM_CLKO2                 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX))
+#define GPIO_CCM_PMIC_RDY              (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX))
+#define GPIO_CCM_PMIC_READY_1          (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX))
+#define GPIO_CCM_PMIC_READY_2          (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX))
+#define GPIO_CCM_PMIC_READY_3          (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX))
+
+#define GPIO_CCM_PMIC_VSTBY_REQ        (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_STBY_REQ_INDEX))
+#define GPIO_CCM_REF_EN                (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX))
+#define GPIO_CCM_STOP                  (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX))
+#define GPIO_CCM_WAIT                  (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX))
+
+/* Ethernet (ENET) */
+
+#define GPIO_ENET_1588_EVENT0_IN       (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX))
+#define GPIO_ENET_1588_EVENT0_OUT      (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX))
+#define GPIO_ENET_1588_EVENT1_IN       (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX))
+#define GPIO_ENET_1588_EVENT1_OUT      (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX))
+#define GPIO_ENET_1588_EVENT2_IN       (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX))
+#define GPIO_ENET_1588_EVENT2_OUT      (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX))
+#define GPIO_ENET_1588_EVENT3_IN       (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX))
+#define GPIO_ENET_1588_EVENT3_OUT      (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX))
+#define GPIO_ENET_COL                  (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX))
+#define GPIO_ENET_CRS                  (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX))
+#define GPIO_ENET_MDC_1                (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX) | \
+					IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \
+                                        IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_MDC_2                (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \
+                                        IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_MDC_3                (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \
+                                        IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_MDIO_1               (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)  | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_OPENDRAIN | \
+                                        IOMUX_SPEED_LOW | IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_MDIO_2               (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_OPENDRAIN | \
+                                        IOMUX_SPEED_LOW | IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_MDIO_3               (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_OPENDRAIN | \
+                                        IOMUX_SPEED_LOW | IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_RDATA00              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX))
+#define GPIO_ENET_RDATA01              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX))
+
+#define GPIO_ENET_REF_CLK_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \
+                                        IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP)
+#define GPIO_ENET_REF_CLK_2            (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \
+                                        IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP)
+#define GPIO_ENET_RX_CLK               (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC36_INDEX))
+#define GPIO_ENET_RX_DATA00            (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \
+                                        IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_RX_DATA01            (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \
+                                        IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_RX_DATA02            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX))
+#define GPIO_ENET_RX_DATA03            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX))
+#define GPIO_ENET_RX_EN_1              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \
+                                        IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_RX_EN_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX) | \
+					IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \
+                                        IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_RX_ER_1              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \
+                                        IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_RX_ER_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)  | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \
+                                        IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_TDATA00              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX )
+#define GPIO_ENET_TDATA01              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)  | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX )
+#define GPIO_ENET_TX_CLK_1             (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \
+                                        IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP | GPIO_SION_ENABLE )
+#define GPIO_ENET_TX_CLK_2             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)  | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \
+                                        IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP | GPIO_SION_ENABLE )
+#define GPIO_ENET_TX_DATA00            (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \
+                                        IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_TX_DATA01            (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \
+                                        IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_TX_DATA02            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX))
+#define GPIO_ENET_TX_DATA03            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX))
+#define GPIO_ENET_TX_EN_1              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \
+                                        IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_TX_EN_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX) | \
+                                        IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \
+                                        IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE)
+#define GPIO_ENET_TX_ER                (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX))
+
+/* External Watchdog Monitor (EWM) */
+
+#define GPIO_EWM_OUT_1                 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX))
+#define GPIO_EWM_OUT_2                 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX))
+#define GPIO_EWM_OUT_3                 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX))
+
+/* Flexible Controller Area Network (FLEXCAN) */
+
+#define GPIO_FLEXCAN1_RX_1             (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX))
+#define GPIO_FLEXCAN1_RX_2             (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX))
+#define GPIO_FLEXCAN1_RX_3             (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX))
+#define GPIO_FLEXCAN1_RX_4             (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX))
+#define GPIO_FLEXCAN1_TX_1             (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX))
+#define GPIO_FLEXCAN1_TX_2             (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX))
+#define GPIO_FLEXCAN1_TX_3             (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX))
+#define GPIO_FLEXCAN1_TX_4             (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX))
+#define GPIO_FLEXCAN2_RX_1             (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX))
+#define GPIO_FLEXCAN2_RX_2             (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX))
+#define GPIO_FLEXCAN2_RX_3             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX))
+#define GPIO_FLEXCAN2_RX_4             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX))
+#define GPIO_FLEXCAN2_TX_1             (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX))
+#define GPIO_FLEXCAN2_TX_2             (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX))
+#define GPIO_FLEXCAN2_TX_3             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX))
+#define GPIO_FLEXCAN2_TX_4             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX))
+
+/* Flexible I/O (FlexIO) */
+
+#define GPIO_FLEXIO1_FLEXIO00          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX))
+#define GPIO_FLEXIO1_FLEXIO01          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX))
+#define GPIO_FLEXIO1_FLEXIO02          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX))
+#define GPIO_FLEXIO1_FLEXIO03          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX))
+#define GPIO_FLEXIO1_FLEXIO04          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX))
+#define GPIO_FLEXIO1_FLEXIO05          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX))
+#define GPIO_FLEXIO1_FLEXIO06          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX))
+#define GPIO_FLEXIO1_FLEXIO07          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX))
+#define GPIO_FLEXIO1_FLEXIO08          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX))
+#define GPIO_FLEXIO1_FLEXIO09          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX))
+#define GPIO_FLEXIO1_FLEXIO10          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX))
+#define GPIO_FLEXIO1_FLEXIO11          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX))
+#define GPIO_FLEXIO1_FLEXIO12          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX))
+#define GPIO_FLEXIO1_FLEXIO13          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX))
+#define GPIO_FLEXIO1_FLEXIO14          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX))
+#define GPIO_FLEXIO1_FLEXIO15          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX))
+#define GPIO_FLEXIO1_FLEXIO16          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX))
+#define GPIO_FLEXIO1_FLEXIO17          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX))
+#define GPIO_FLEXIO1_FLEXIO18          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX))
+#define GPIO_FLEXIO1_FLEXIO19          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX))
+#define GPIO_FLEXIO1_FLEXIO20          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX))
+#define GPIO_FLEXIO1_FLEXIO21          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX))
+#define GPIO_FLEXIO1_FLEXIO22          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX))
+#define GPIO_FLEXIO1_FLEXIO23          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX))
+#define GPIO_FLEXIO1_FLEXIO24          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX))
+#define GPIO_FLEXIO1_FLEXIO25          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX))
+#define GPIO_FLEXIO1_FLEXIO26          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX))
+#define GPIO_FLEXIO1_FLEXIO27          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX))
+#define GPIO_FLEXIO1_FLEXIO28          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX))
+#define GPIO_FLEXIO1_FLEXIO29          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX))
+#define GPIO_FLEXIO1_FLEXIO30          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX))
+#define GPIO_FLEXIO1_FLEXIO31          (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX))
+
+/* Enhanced Flex Pulse Width Modulator (eFlexPWM) */
+
+#define GPIO_FLEXPWM1_PWMA00_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX))
+#define GPIO_FLEXPWM1_PWMA00_2         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX))
+#define GPIO_FLEXPWM1_PWMA01_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX))
+#define GPIO_FLEXPWM1_PWMA01_2         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX))
+#define GPIO_FLEXPWM1_PWMA02_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX))
+#define GPIO_FLEXPWM1_PWMA02_2         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX))
+#define GPIO_FLEXPWM1_PWMA03_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX))
+#define GPIO_FLEXPWM1_PWMA03_2         (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX))
+#define GPIO_FLEXPWM1_PWMB00_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX))
+#define GPIO_FLEXPWM1_PWMB00_2         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX))
+#define GPIO_FLEXPWM1_PWMB01_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX))
+#define GPIO_FLEXPWM1_PWMB01_2         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX))
+#define GPIO_FLEXPWM1_PWMB02_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX))
+#define GPIO_FLEXPWM1_PWMB02_2         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX))
+#define GPIO_FLEXPWM1_PWMB03_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX))
+#define GPIO_FLEXPWM1_PWMB03_2         (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX))
+#define GPIO_FLEXPWM1_PWMX00           (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX))
+#define GPIO_FLEXPWM1_PWMX01           (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX))
+#define GPIO_FLEXPWM1_PWMX02           (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX))
+#define GPIO_FLEXPWM1_PWMX03           (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX))
+#define GPIO_FLEXPWM2_PWMA00_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX))
+#define GPIO_FLEXPWM2_PWMA00_2         (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX))
+#define GPIO_FLEXPWM2_PWMA01_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX))
+#define GPIO_FLEXPWM2_PWMA01_2         (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX))
+#define GPIO_FLEXPWM2_PWMA02_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX))
+#define GPIO_FLEXPWM2_PWMA02_2         (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX))
+#define GPIO_FLEXPWM2_PWMA03_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX))
+#define GPIO_FLEXPWM2_PWMA03_2         (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX))
+#define GPIO_FLEXPWM2_PWMB00_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX))
+#define GPIO_FLEXPWM2_PWMB00_2         (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX))
+#define GPIO_FLEXPWM2_PWMB01_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX))
+#define GPIO_FLEXPWM2_PWMB01_2         (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX))
+#define GPIO_FLEXPWM2_PWMB02_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX))
+#define GPIO_FLEXPWM2_PWMB02_2         (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX))
+#define GPIO_FLEXPWM2_PWMB03_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX))
+#define GPIO_FLEXPWM2_PWMB03_2         (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX))
+#define GPIO_FLEXPWM2_PWMX00           (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX))
+#define GPIO_FLEXPWM2_PWMX01           (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX))
+#define GPIO_FLEXPWM2_PWMX02           (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX))
+#define GPIO_FLEXPWM2_PWMX03           (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX))
+
+/* Flexible SPI (FlexSPI) */
+
+#define GPIO_FLEXSPIA_DATA00_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX))
+#define GPIO_FLEXSPIA_DATA00_2         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX))
+#define GPIO_FLEXSPIA_DATA01_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX))
+#define GPIO_FLEXSPIA_DATA01_2         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX))
+#define GPIO_FLEXSPIA_DATA02_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX))
+#define GPIO_FLEXSPIA_DATA02_2         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX))
+#define GPIO_FLEXSPIA_DATA03_1         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX))
+#define GPIO_FLEXSPIA_DATA03_2         (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX))
+#define GPIO_FLEXSPIA_DQS              (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX))
+#define GPIO_FLEXSPIA_SCLK_1           (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX))
+#define GPIO_FLEXSPIA_SCLK_2           (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX))
+#define GPIO_FLEXSPIA_SS0_1            (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX))
+#define GPIO_FLEXSPIA_SS0_2            (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX))
+#define GPIO_FLEXSPIA_SS1_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX))
+#define GPIO_FLEXSPIA_SS1_2            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX))
+
+#define GPIO_FLEXSPIB_DATA00           (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX))
+#define GPIO_FLEXSPIB_DATA01           (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX))
+#define GPIO_FLEXSPIB_DATA02           (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX))
+#define GPIO_FLEXSPIB_DATA03           (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX))
+#define GPIO_FLEXSPIB_DQS              (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX))
+#define GPIO_FLEXSPIB_SCLK             (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX))
+#define GPIO_FLEXSPIB_SS0_1            (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX))
+#define GPIO_FLEXSPIB_SS0_2            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX))
+#define GPIO_FLEXSPIB_SS1              (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX))
+
+/* GPIO */
+
+#define GPIO_GPIO1_IO00                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX))
+#define GPIO_GPIO1_IO01                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX))
+#define GPIO_GPIO1_IO02                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX))
+#define GPIO_GPIO1_IO03                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX))
+#define GPIO_GPIO1_IO04                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX))
+#define GPIO_GPIO1_IO05                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX))
+#define GPIO_GPIO1_IO06                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX))
+#define GPIO_GPIO1_IO07                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX))
+#define GPIO_GPIO1_IO08                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX))
+#define GPIO_GPIO1_IO09                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX))
+#define GPIO_GPIO1_IO10                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX))
+#define GPIO_GPIO1_IO11                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX))
+#define GPIO_GPIO1_IO12                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX))
+#define GPIO_GPIO1_IO13                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX))
+#define GPIO_GPIO1_IO14                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX))
+#define GPIO_GPIO1_IO15                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX))
+#define GPIO_GPIO1_IO16                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX))
+#define GPIO_GPIO1_IO17                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX))
+#define GPIO_GPIO1_IO18                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX))
+#define GPIO_GPIO1_IO19                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX))
+#define GPIO_GPIO1_IO20                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX))
+#define GPIO_GPIO1_IO21                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX))
+#define GPIO_GPIO1_IO22                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX))
+#define GPIO_GPIO1_IO23                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX))
+#define GPIO_GPIO1_IO24                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX))
+#define GPIO_GPIO1_IO25                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX))
+#define GPIO_GPIO1_IO26                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX))
+#define GPIO_GPIO1_IO27                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX))
+#define GPIO_GPIO1_IO28                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX))
+#define GPIO_GPIO1_IO29                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX))
+#define GPIO_GPIO1_IO30                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX))
+#define GPIO_GPIO1_IO31                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX))
+
+#define GPIO_GPIO2_IO00                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX))
+#define GPIO_GPIO2_IO01                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX))
+#define GPIO_GPIO2_IO02                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX))
+#define GPIO_GPIO2_IO03                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX))
+#define GPIO_GPIO2_IO04                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX))
+#define GPIO_GPIO2_IO05                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX))
+#define GPIO_GPIO2_IO06                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX))
+#define GPIO_GPIO2_IO07                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX))
+#define GPIO_GPIO2_IO08                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX))
+#define GPIO_GPIO2_IO09                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX))
+#define GPIO_GPIO2_IO10                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX))
+#define GPIO_GPIO2_IO11                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX))
+#define GPIO_GPIO2_IO12                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX))
+#define GPIO_GPIO2_IO13                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX))
+#define GPIO_GPIO2_IO14                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX))
+#define GPIO_GPIO2_IO15                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX))
+#define GPIO_GPIO2_IO16                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX))
+#define GPIO_GPIO2_IO17                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX))
+#define GPIO_GPIO2_IO18                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX))
+#define GPIO_GPIO2_IO19                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX))
+#define GPIO_GPIO2_IO20                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX))
+#define GPIO_GPIO2_IO21                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX))
+#define GPIO_GPIO2_IO22                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX))
+#define GPIO_GPIO2_IO23                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX))
+#define GPIO_GPIO2_IO24                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX))
+#define GPIO_GPIO2_IO25                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX))
+#define GPIO_GPIO2_IO26                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX))
+#define GPIO_GPIO2_IO27                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX))
+#define GPIO_GPIO2_IO28                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX))
+#define GPIO_GPIO2_IO29                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX))
+#define GPIO_GPIO2_IO30                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX))
+#define GPIO_GPIO2_IO31                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX))
+
+#define GPIO_GPIO3_IO00                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC32_INDEX))
+#define GPIO_GPIO3_IO01                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC33_INDEX))
+#define GPIO_GPIO3_IO02                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC34_INDEX))
+#define GPIO_GPIO3_IO03                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC39_INDEX))
+#define GPIO_GPIO3_IO04                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC36_INDEX))
+#define GPIO_GPIO3_IO05                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC37_INDEX))
+#define GPIO_GPIO3_IO06                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC38_INDEX))
+#define GPIO_GPIO3_IO07                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC39_INDEX))
+#define GPIO_GPIO3_IO08                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC40_INDEX))
+#define GPIO_GPIO3_IO09                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC41_INDEX))
+#define GPIO_GPIO3_IO13                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX))
+#define GPIO_GPIO3_IO14                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX))
+#define GPIO_GPIO3_IO15                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX))
+#define GPIO_GPIO3_IO16                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX))
+#define GPIO_GPIO3_IO17                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX))
+#define GPIO_GPIO3_IO18                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX))
+#define GPIO_GPIO3_IO19                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX))
+#define GPIO_GPIO3_IO20                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX))
+#define GPIO_GPIO3_IO21                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX))
+#define GPIO_GPIO3_IO22                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX))
+#define GPIO_GPIO3_IO23                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX))
+#define GPIO_GPIO3_IO24                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX))
+#define GPIO_GPIO3_IO25                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX))
+#define GPIO_GPIO3_IO26                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX))
+#define GPIO_GPIO3_IO27                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX))
+#define GPIO_GPIO3_IO28                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX))
+#define GPIO_GPIO3_IO29                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX))
+#define GPIO_GPIO3_IO30                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX))
+#define GPIO_GPIO3_IO31                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX))
+
+#define GPIO_GPIO5_IO00                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_WAKEUP_INDEX))
+#define GPIO_GPIO5_IO01                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_ON_REQ_INDEX))
+#define GPIO_GPIO5_IO02                (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_STBY_REQ_INDEX))
+
+/* General Purpose Timer (GPT) */
+
+#define GPIO_GPT1_CAPTURE1             (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX))
+#define GPIO_GPT1_CAPTURE2             (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX))
+#define GPIO_GPT1_CLK                  (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC39_INDEX))
+#define GPIO_GPT1_COMPARE1             (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX))
+#define GPIO_GPT1_COMPARE2             (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX))
+#define GPIO_GPT1_COMPARE3             (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX))
+
+#define GPIO_GPT2_CAPTURE1             (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX))
+#define GPIO_GPT2_CAPTURE2             (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX))
+#define GPIO_GPT2_CLK                  (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX))
+#define GPIO_GPT2_COMPARE1             (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX))
+#define GPIO_GPT2_COMPARE2             (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX))
+#define GPIO_GPT2_COMPARE3             (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX))
+
+/* JTAG */
+
+#define GPIO_JTAG_MOD                  (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX))
+#define GPIO_JTAG_TCK                  (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX))
+#define GPIO_JTAG_TDI                  (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_3_INDEX))
+#define GPIO_JTAG_TDO                  (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX))
+#define GPIO_JTAG_TMS                  (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) 
+#define GPIO_JTAG_TRSTB                (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX))
+
+/* Keypad Port (KPP) */
+
+#define GPIO_KPP_COL00                 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX))
+#define GPIO_KPP_COL01                 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX))
+#define GPIO_KPP_COL02                 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX))
+#define GPIO_KPP_COL03                 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX))
+#define GPIO_KPP_COL04                 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX))
+#define GPIO_KPP_COL05                 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX))
+#define GPIO_KPP_COL06                 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX))
+#define GPIO_KPP_COL07                 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX))
+#define GPIO_KPP_ROW00                 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX))
+#define GPIO_KPP_ROW01                 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX))
+#define GPIO_KPP_ROW02                 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX))
+#define GPIO_KPP_ROW03                 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX))
+#define GPIO_KPP_ROW04                 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX))
+#define GPIO_KPP_ROW05                 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX))
+#define GPIO_KPP_ROW06                 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX))
+#define GPIO_KPP_ROW07                 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX))
+
+/* Low Power Inter-Integrated Circuit (LPI2C) */
+
+#define GPIO_LPI2C1_HREQ               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX))
+#define GPIO_LPI2C1_SCL_1              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX))
+#define GPIO_LPI2C1_SCL_2              (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX) | \
+                                        GPIO_SION_ENABLE | IOMUX_PULL_UP_22K | IOMUX_OPENDRAIN | \
+                                        IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM)
+#define GPIO_LPI2C1_SDA_1              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX))
+#define GPIO_LPI2C1_SDA_2              (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX) | \
+                                        GPIO_SION_ENABLE | IOMUX_PULL_UP_22K | IOMUX_OPENDRAIN | \
+                                        IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM)
+
+#define GPIO_LPI2C2_SCL_1              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX))
+#define GPIO_LPI2C2_SCL_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX))
+#define GPIO_LPI2C2_SDA_1              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX))
+#define GPIO_LPI2C2_SDA_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX))
+
+#define GPIO_LPI2C3_SCL_1              (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX))
+#define GPIO_LPI2C3_SCL_2              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX) | \
+                                        GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM)
+#define GPIO_LPI2C3_SDA_1              (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX))
+#define GPIO_LPI2C3_SDA_2              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX) | \
+                                        GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM)
+
+#define GPIO_LPI2C4_SCL_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX) | \
+					IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM)
+#define GPIO_LPI2C4_SDA_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX) | \
+					GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM)
+#define GPIO_LPI2C4_SDA_2              (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX) | \
+                                        GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM)
+
+/* Low Power Serial Peripheral Interface (LPSPI) */
+
+#define IOMUX_LPSPI                    (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \
+                                        IOMUX_SLEW_FAST | IOMUX_SPEED_MEDIUM)
+
+#define GPIO_LPSPI1_PCS0_1             (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI1_PCS0_2             (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI1_PCS1               (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI1_PCS2               (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI1_PCS3               (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI1_SCK_1              (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI1_SCK_2              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI1_SDI_1              (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI1_SDI_2              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI1_SDO_1              (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI1_SDO_2              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX) | IOMUX_LPSPI)
+
+#define GPIO_LPSPI2_PCS0_1             (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI2_PCS0_2             (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI2_PCS0_3             (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI2_PCS1               (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI2_PCS2               (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI2_PCS3               (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI2_SCK_1              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI2_SCK_2              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI2_SCK_3              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI2_SDI_1              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI2_SDI_2              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI2_SDI_3              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX) | IOMUX_LPSPI)  
+#define GPIO_LPSPI2_SDO_1              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI2_SDO_2              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI2_SDO_3              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX) | IOMUX_LPSPI)
+
+#define GPIO_LPSPI3_PCS0               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI3_PCS1               (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI3_PCS2               (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI3_PCS3               (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI3_SCK                (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI3_SDI                (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI3_SDO                (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX) | IOMUX_LPSPI)
+
+#define GPIO_LPSPI4_PCS0_1             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI4_PCS0_2             (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI4_PCS1               (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI4_PCS2               (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI4_PCS3               (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI4_SCK_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI4_SCK_2              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI4_SDI_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI4_SDI_2              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI4_SDO_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX) | IOMUX_LPSPI)
+#define GPIO_LPSPI4_SDO_2              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX) | IOMUX_LPSPI)
+
+/* Low Power Universal Asynchronous Receiver/Transmitter (LPUART) */
+
+#define IOMUX_UART                     (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \
+                                        IOMUX_SLEW_FAST | IOMUX_SPEED_MEDIUM | IOMUX_SCHMITT_TRIGGER)
+
+#define GPIO_LPUART1_CTS               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX))
+#define GPIO_LPUART1_RTS               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX))
+#define GPIO_LPUART1_RX                (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX) | IOMUX_UART)
+#define GPIO_LPUART1_TX                (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX) | IOMUX_UART)
+
+#define GPIO_LPUART2_CTS_1             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX))
+#define GPIO_LPUART2_CTS_2             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX))
+#define GPIO_LPUART2_RTS_1             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX))
+#define GPIO_LPUART2_RTS_2             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX))
+#define GPIO_LPUART2_RX_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)   | IOMUX_UART)
+#define GPIO_LPUART2_RX_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX) | IOMUX_UART)
+#define GPIO_LPUART2_TX_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)   | IOMUX_UART)
+#define GPIO_LPUART2_TX_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX) | IOMUX_UART)
+
+#define GPIO_LPUART3_CTS               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX))
+#define GPIO_LPUART3_RTS               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX))
+#define GPIO_LPUART3_RX_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)   | IOMUX_UART)
+#define GPIO_LPUART3_RX_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX) | IOMUX_UART)
+#define GPIO_LPUART3_TX_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)   | IOMUX_UART)
+#define GPIO_LPUART3_TX_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX) | IOMUX_UART)
+
+#define GPIO_LPUART4_CTS_1             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX))
+#define GPIO_LPUART4_CTS_2             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX))
+#define GPIO_LPUART4_RTS_1             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX))
+#define GPIO_LPUART4_RTS_2             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX))
+#define GPIO_LPUART4_RX_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)   | IOMUX_UART)
+#define GPIO_LPUART4_RX_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)   | IOMUX_UART)
+#define GPIO_LPUART4_RX_3              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX) | IOMUX_UART)
+#define GPIO_LPUART4_TX_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)   | IOMUX_UART)
+#define GPIO_LPUART4_TX_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)   | IOMUX_UART)
+#define GPIO_LPUART4_TX_3              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX) | IOMUX_UART)
+
+#define GPIO_LPUART5_CTS               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX))
+#define GPIO_LPUART5_RTS               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX))
+#define GPIO_LPUART5_RX_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)    | IOMUX_UART)
+#define GPIO_LPUART5_RX_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX))
+#define GPIO_LPUART5_TX_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)    | IOMUX_UART)
+#define GPIO_LPUART5_TX_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX))
+
+#define GPIO_LPUART6_CTS               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX))
+#define GPIO_LPUART6_RTS               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX))
+#define GPIO_LPUART6_RX_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)    | IOMUX_UART)
+#define GPIO_LPUART6_RX_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)  | IOMUX_UART)
+#define GPIO_LPUART6_TX_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)    | IOMUX_UART)
+#define GPIO_LPUART6_TX_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)  | IOMUX_UART)
+
+#define GPIO_LPUART7_CTS               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX))
+#define GPIO_LPUART7_RTS               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX))
+#define GPIO_LPUART7_RX_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX))
+#define GPIO_LPUART7_RX_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX))
+#define GPIO_LPUART7_TX_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX))
+#define GPIO_LPUART7_TX_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX))
+
+#define GPIO_LPUART8_CTS               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX))
+#define GPIO_LPUART8_RTS               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX))
+#define GPIO_LPUART8_RX_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)    | IOMUX_UART)
+#define GPIO_LPUART8_RX_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)  | IOMUX_UART)
+#define GPIO_LPUART8_TX_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)    | IOMUX_UART)
+#define GPIO_LPUART8_TX_2              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)  | IOMUX_UART)
+
+/* Medium Quality Sound (MQS) */
+
+#define GPIO_MQS_LEFT_1                (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX))
+#define GPIO_MQS_LEFT_2                (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX))
+#define GPIO_MQS_LEFT_3                (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX))
+#define GPIO_MQS_RIGHT_1               (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX))
+#define GPIO_MQS_RIGHT_2               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX))
+#define GPIO_MQS_RIGHT_3               (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX))
+
+/* NMI */
+
+#define GPIO_NMI_GLUE_NMI_1            (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_WAKEUP_INDEX))
+#define GPIO_NMI_GLUE_NMI_2            (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_BO_05_INDEX))
+
+/* Periodic Interrupt Timer (PIT) */
+
+#define GPIO_PIT_TRIGGER0              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX))
+#define GPIO_PIT_TRIGGER1              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX))
+#define GPIO_PIT_TRIGGER2              (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX))
+#define GPIO_PIT_TRIGGER3              (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX))
+
+/* Quad Timer (QTimer) */
+
+#define GPIO_QTIMER1_TIMER0_1          (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX))
+#define GPIO_QTIMER1_TIMER0_2          (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00INDEX))
+#define GPIO_QTIMER1_TIMER1_1          (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX))
+#define GPIO_QTIMER1_TIMER1_2          (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX))
+#define GPIO_QTIMER1_TIMER2_1          (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX))
+#define GPIO_QTIMER1_TIMER2_2          (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX))
+#define GPIO_QTIMER1_TIMER3_1          (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX))
+#define GPIO_QTIMER1_TIMER3_2          (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX))
+
+#define GPIO_QTIMER2_TIMER0_1          (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX))
+#define GPIO_QTIMER2_TIMER0_2          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX))
+#define GPIO_QTIMER2_TIMER1_1          (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX))
+#define GPIO_QTIMER2_TIMER1_2          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX))
+#define GPIO_QTIMER2_TIMER2_1          (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX))
+#define GPIO_QTIMER2_TIMER2_2          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX))
+#define GPIO_QTIMER2_TIMER3_1          (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX))
+#define GPIO_QTIMER2_TIMER3_2          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_BO_07_INDEX))
+
+/* Synchronous Audio Interface (SAI) */
+
+#define GPIO_SAI1_MCLK_1               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX))
+#define GPIO_SAI1_MCLK_2               (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX))
+#define GPIO_SAI1_MCLK_3               (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX))
+#define GPIO_SAI1_MCLK_4               (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX))
+#define GPIO_SAI1_RX_BCLK_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX))
+#define GPIO_SAI1_RX_BCLK_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX))
+#define GPIO_SAI1_RX_BCLK_3            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX))
+#define GPIO_SAI1_RX_DATA00_1          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX))
+#define GPIO_SAI1_RX_DATA00_2          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX))
+#define GPIO_SAI1_RX_DATA00_3          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX))
+#define GPIO_SAI1_RX_SYNC_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX))
+#define GPIO_SAI1_RX_SYNC_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX))
+#define GPIO_SAI1_RX_SYNC_3            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX))
+#define GPIO_SAI1_TX_BCLK_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX))
+#define GPIO_SAI1_TX_BCLK_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX))
+#define GPIO_SAI1_TX_BCLK_3            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX))
+#define GPIO_SAI1_TX_DATA00_1          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX))
+#define GPIO_SAI1_TX_DATA00_2          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX))
+#define GPIO_SAI1_TX_DATA00_3          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX))
+#define GPIO_SAI1_TX_DATA01_1          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX))
+#define GPIO_SAI1_TX_DATA01_2          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX))
+#define GPIO_SAI1_TX_DATA02_1          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX))
+#define GPIO_SAI1_TX_DATA02_2          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX))
+#define GPIO_SAI1_TX_DATA03_1          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX))
+#define GPIO_SAI1_TX_DATA03_2          (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX))
+#define GPIO_SAI1_TX_SYNC_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX))
+#define GPIO_SAI1_TX_SYNC_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX))
+#define GPIO_SAI1_TX_SYNC_3            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX))
+
+#define GPIO_SAI2_MCLK_1               (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX))
+#define GPIO_SAI2_MCLK_2               (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX))
+#define GPIO_SAI2_RX_BCLK_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX))
+#define GPIO_SAI2_RX_BCLK_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX))
+#define GPIO_SAI2_RX_DATA_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX))
+#define GPIO_SAI2_RX_DATA_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX))
+#define GPIO_SAI2_RX_SYNC_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX))
+#define GPIO_SAI2_RX_SYNC_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX))
+#define GPIO_SAI2_TX_BCLK_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX))
+#define GPIO_SAI2_TX_BCLK_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX))
+#define GPIO_SAI2_TX_DATA_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX))
+#define GPIO_SAI2_TX_DATA_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX))
+#define GPIO_SAI2_TX_SYNC_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX))
+#define GPIO_SAI2_TX_SYNC_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX))
+
+#define GPIO_SAI3_MCLK_1               (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX))
+#define GPIO_SAI3_MCLK_2               (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX))
+#define GPIO_SAI3_MCLK_3               (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX))
+#define GPIO_SAI3_RX_BCLK_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX))
+#define GPIO_SAI3_RX_BCLK_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX))
+#define GPIO_SAI3_RX_DATA_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX))
+#define GPIO_SAI3_RX_DATA_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX))
+#define GPIO_SAI3_RX_SYNC_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX))
+#define GPIO_SAI3_RX_SYNC_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX))
+#define GPIO_SAI3_TX_BCLK_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX))
+#define GPIO_SAI3_TX_BCLK_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX))
+#define GPIO_SAI3_TX_DATA_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX))
+#define GPIO_SAI3_TX_DATA_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX))
+#define GPIO_SAI3_TX_SYNC_1            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX))
+#define GPIO_SAI3_TX_SYNC_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX))
+
+/* Smart External Memory Controller (SEMC) */
+
+#define GPIO_SEMC_ADDR00               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX))
+#define GPIO_SEMC_ADDR01               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX))
+#define GPIO_SEMC_ADDR02               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX))
+#define GPIO_SEMC_ADDR03               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX))
+#define GPIO_SEMC_ADDR04               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX))
+#define GPIO_SEMC_ADDR05               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX))
+#define GPIO_SEMC_ADDR06               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX))
+#define GPIO_SEMC_ADDR07               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX))
+#define GPIO_SEMC_ADDR08               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX))
+#define GPIO_SEMC_ADDR09               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX))
+#define GPIO_SEMC_ADDR10               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX))
+#define GPIO_SEMC_ADDR11               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX))
+#define GPIO_SEMC_ADDR12               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX))
+#define GPIO_SEMC_BA0                  (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX))
+#define GPIO_SEMC_BA1                  (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX))
+#define GPIO_SEMC_CAS                  (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX))
+#define GPIO_SEMC_CKE                  (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX))
+#define GPIO_SEMC_CLK                  (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX))
+#define GPIO_SEMC_CS0                  (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX))
+#define GPIO_SEMC_CSX00_1              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX))
+#define GPIO_SEMC_CSX00_2              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX))
+#define GPIO_SEMC_CSX01                (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX))
+#define GPIO_SEMC_CSX02                (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX))
+#define GPIO_SEMC_CSX03                (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX))
+#define GPIO_SEMC_DATA00               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX))
+#define GPIO_SEMC_DATA01               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX))
+#define GPIO_SEMC_DATA02               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX))
+#define GPIO_SEMC_DATA03               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX))
+#define GPIO_SEMC_DATA04               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX))
+#define GPIO_SEMC_DATA05               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX))
+#define GPIO_SEMC_DATA06               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX))
+#define GPIO_SEMC_DATA07               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX))
+#define GPIO_SEMC_DATA08               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX))
+#define GPIO_SEMC_DATA09               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX))
+#define GPIO_SEMC_DATA10               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX))
+#define GPIO_SEMC_DATA11               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX))
+#define GPIO_SEMC_DATA12               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX))
+#define GPIO_SEMC_DATA13               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX))
+#define GPIO_SEMC_DATA14               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX))
+#define GPIO_SEMC_DATA15               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX))
+#define GPIO_SEMC_DM00                 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX))
+#define GPIO_SEMC_DM01                 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX))
+#define GPIO_SEMC_DQS                  (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX))
+#define GPIO_SEMC_RAS                  (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX))
+#define GPIO_SEMC_RDY_1                (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX))
+#define GPIO_SEMC_RDY_2                (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX))
+#define GPIO_SEMC_WE                   (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX))
+
+/* Secure Non-Volatile Storage (SNVS) */
+
+#define GPIO_SNVS_LP_PMIC_ON_REQ       (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_ON_REQ_INDEX))
+#define GPIO_SNVS_VIO_5                (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX))
+#define GPIO_SNVS_VIO_5_CTL            (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX))
+
+/* Sony/Philips Digital Interface (SPDIF) */
+
+#define GPIO_SPDIF_EXT_CLK             (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX))
+#define GPIO_SPDIF_IN_1                (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX))
+#define GPIO_SPDIF_IN_2                (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX))
+#define GPIO_SPDIF_LOCK                (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX))
+#define GPIO_SPDIF_OUT_1               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX))
+#define GPIO_SPDIF_OUT_2               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX))
+#define GPIO_SPDIF_OUT_3               (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX))
+#define GPIO_SPDIF_SR_CLK              (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX))
+
+/* Boot Configuration */
+
+#define GPIO_SRC_BOOT_MODE00           (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX))
+#define GPIO_SRC_BOOT_MODE01           (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX))
+
+#define GPIO_SRC_BOOT_CFG00            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX))
+#define GPIO_SRC_BOOT_CFG01            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX))
+#define GPIO_SRC_BOOT_CFG02            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX))
+#define GPIO_SRC_BOOT_CFG03            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX))
+#define GPIO_SRC_BOOT_CFG04            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX))
+#define GPIO_SRC_BOOT_CFG05            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX))
+#define GPIO_SRC_BOOT_CFG06            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX))
+#define GPIO_SRC_BOOT_CFG07            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX))
+#define GPIO_SRC_BOOT_CFG08            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX))
+#define GPIO_SRC_BOOT_CFG09            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX))
+
+#define GPIO_SRC_EARLY_RESET           (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX))
+#define GPIO_SRC_POR_B                 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_POR_B))
+#define GPIO_SRC_RESET_B               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_ONOFF)) 
+#define GPIO_SRC_SYSTEM_RESET          (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX))
+#define GPIO_SRC_TESTER_ACK            (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX))
+
+/* USB OTG */
+
+#define GPIO_USB_OTG_ID_1             (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX))
+#define GPIO_USB_OTG_ID_2             (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX))
+#define GPIO_USB_OTG_ID_3             (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX))
+#define GPIO_USB_OTG_OC_1             (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX))
+#define GPIO_USB_OTG_OC_2             (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX))
+#define GPIO_USB_OTG_OC_3             (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX))
+#define GPIO_USB_OTG_PWR_1            (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX))
+#define GPIO_USB_OTG_PWR_2            (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX))
+#define GPIO_USB_OTG_PWR_3            (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX))
+
+#define GPIO_USBPHY1_TSTI_TX_DN       (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX))
+#define GPIO_USBPHY1_TSTI_TX_DP       (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX))
+#define GPIO_USBPHY1_TSTI_TX_EN       (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX))
+#define GPIO_USBPHY1_TSTI_TX_HIZ      (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX))
+#define GPIO_USBPHY1_TSTI_TX_HS_MODE  (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX))
+#define GPIO_USBPHY1_TSTI_TX_LS_MODE  (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX))
+#define GPIO_USBPHY1_TSTO_PLL_CLK20DIV (GPIO_PERIPH | GPIO_ALT6  | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX))
+#define GPIO_USBPHY1_TSTO_RX_DISC_DET (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX))
+#define GPIO_USBPHY1_TSTO_RX_FS_RXD   (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX))
+#define GPIOUSBPHY1_TSTO_RX_HS_RXD    (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX))
+#define GPIO_USBPHY1_TSTO_RX_SQUELCH  (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX))
+
+/* Ultra Secured Digital Host Controller (uSDHC) */
+
+#define GPIO_USDHC1_CD_1               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX))
+#define GPIO_USDHC1_CD_2               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX))
+#define GPIO_USDHC1_CD_3               (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX))
+#define GPIO_USDHC1_CD_4               (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX))
+#define GPIO_USDHC1_CLK                (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX))
+#define GPIO_USDHC1_CMD                (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX))
+#define GPIO_USDHC1_DATA0              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX))
+#define GPIO_USDHC1_DATA1              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX))
+#define GPIO_USDHC1_DATA2              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX))
+#define GPIO_USDHC1_DATA3              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX))
+#define GPIO_USDHC1_RESET_1            (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX))
+#define GPIO_USDHC1_RESET_2            (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX))
+#define GPIO_USDHC1_VSELECT_1          (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX))
+#define GPIO_USDHC1_VSELECT_2          (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX))
+#define GPIO_USDHC1_WP_1               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX))
+#define GPIO_USDHC1_WP_2               (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX))
+#define GPIO_USDHC1_WP_3               (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX))
+#define GPIO_USDHC1_WP_4               (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX))
+#define GPIO_USDHC1_WP_5               (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) 
+
+#define GPIO_USDHC2_CD_1               (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX))
+#define GPIO_USDHC2_CD_2               (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX))
+#define GPIO_USDHC2_CD_3               (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX))
+#define GPIO_USDHC2_CLK                (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX))
+#define GPIO_USDHC2_CMD                (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX))
+#define GPIO_USDHC2_DATA0              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX))
+#define GPIO_USDHC2_DATA1              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX))
+#define GPIO_USDHC2_DATA2              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX))
+#define GPIO_USDHC2_DATA3              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX))
+#define GPIO_USDHC2_DATA4              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX))
+#define GPIO_USDHC2_DATA5              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX))
+#define GPIO_USDHC2_DATA6              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX))
+#define GPIO_USDHC2_DATA7              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX))
+#define GPIO_USDHC2_RESET              (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX))
+#define GPIO_USDHC2_WP_1               (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX))
+#define GPIO_USDHC2_WP_2               (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX))
+
+/* Watchdog Timer (WDOG1-2) */
+
+#define GPIO_WDOG1_ANY                 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX))
+#define GPIO_WDOG1_WDOG_1              (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX))
+#define GPIO_WDOG1_WDOG_2              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX))
+#define GPIO_WDOG1_WDOG_3              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX))
+#define GPIO_WDOG1_WDOG_4              (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX))
+#define GPIO_WDOG1_WDOG_RST_DEB        (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX))
+
+#define GPIO_WDOG2_WDOG                (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX))
+#define GPIO_WDOG2_RESET_DEB           (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX))
+
+/* Inter-Peripheral Crossbar Switch (XBAR) */
+
+#define GPIO_XBAR1_INOUT04             (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX))
+#define GPIO_XBAR1_INOUT05             (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX))
+#define GPIO_XBAR1_INOUT06             (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX))
+#define GPIO_XBAR1_INOUT07             (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX))
+#define GPIO_XBAR1_INOUT08             (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX))
+#define GPIO_XBAR1_INOUT09             (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX))
+#define GPIO_XBAR1_INOUT10_1           (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX))
+#define GPIO_XBAR1_INOUT10_2           (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX))
+#define GPIO_XBAR1_INOUT11             (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX))
+#define GPIO_XBAR1_INOUT12_1           (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX))
+#define GPIO_XBAR1_INOUT12_2           (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX))
+#define GPIO_XBAR1_INOUT13_1           (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX))
+#define GPIO_XBAR1_INOUT13_2           (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX))
+#define GPIO_XBAR1_INOUT14_1           (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX))
+#define GPIO_XBAR1_INOUT14_2           (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX))
+#define GPIO_XBAR1_INOUT15_1           (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX))
+#define GPIO_XBAR1_INOUT15_2           (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX))
+#define GPIO_XBAR1_INOUT16_1           (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX))
+#define GPIO_XBAR1_INOUT16_2           (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX))
+#define GPIO_XBAR1_INOUT17_1           (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX))
+#define GPIO_XBAR1_INOUT17_2           (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX))
+#define GPIO_XBAR1_INOUT18_1           (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX))
+#define GPIO_XBAR1_INOUT18_2           (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX))
+#define GPIO_XBAR1_INOUT19_1           (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX))
+#define GPIO_XBAR1_INOUT19_2           (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX))
+
+/* XTAL Osc */
+
+#define GPIO_REF_24M_OUT_1             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX))
+#define GPIO_REF_24M_OUT_2             (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX))
+#define GPIO_REF_24M_OUT_3             (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX))
+#define GPIO_REF_32K_OUT_1             (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_06_INDEX))
+#define GPIO_REF_32K_OUT_2             (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX))
+
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT102X_PINMUX_H */
diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_xbar.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_xbar.h
new file mode 100644
index 00000000000..f8d6aefd1f1
--- /dev/null
+++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_xbar.h
@@ -0,0 +1,324 @@
+/* XBAR Defines for IMXRT102x */
+
+/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/
+
+#define IMXRT_XBARA1_IN_LOGIC_LOW                        IMXRT_XBARA1(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARA1_IN0 input. */
+#define IMXRT_XBARA1_IN_LOGIC_HIGH                       IMXRT_XBARA1(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 2)    RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 3)    RESERVED */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04                  IMXRT_XBARA1(XBAR_INPUT, 4)    /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05                  IMXRT_XBARA1(XBAR_INPUT, 5)    /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06                  IMXRT_XBARA1(XBAR_INPUT, 6)    /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07                  IMXRT_XBARA1(XBAR_INPUT, 7)    /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08                  IMXRT_XBARA1(XBAR_INPUT, 8)    /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09                  IMXRT_XBARA1(XBAR_INPUT, 9)    /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10                  IMXRT_XBARA1(XBAR_INPUT, 10)   /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11                  IMXRT_XBARA1(XBAR_INPUT, 11)   /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12                  IMXRT_XBARA1(XBAR_INPUT, 12)   /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13                  IMXRT_XBARA1(XBAR_INPUT, 13)   /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14                  IMXRT_XBARA1(XBAR_INPUT, 14)   /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15                  IMXRT_XBARA1(XBAR_INPUT, 15)   /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16                  IMXRT_XBARA1(XBAR_INPUT, 16)   /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17                  IMXRT_XBARA1(XBAR_INPUT, 17)   /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18                  IMXRT_XBARA1(XBAR_INPUT, 18)   /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19                  IMXRT_XBARA1(XBAR_INPUT, 19)   /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 20)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 21)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 22)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 23)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 24)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 25)   RESERVED */
+#define IMXRT_XBARA1_IN_ACMP1_OUT                        IMXRT_XBARA1(XBAR_INPUT, 26)   /* ACMP1_OUT output assigned to XBARA1_IN26 input. */
+#define IMXRT_XBARA1_IN_ACMP2_OUT                        IMXRT_XBARA1(XBAR_INPUT, 27)   /* ACMP2_OUT output assigned to XBARA1_IN27 input. */
+#define IMXRT_XBARA1_IN_ACMP3_OUT                        IMXRT_XBARA1(XBAR_INPUT, 28)   /* ACMP3_OUT output assigned to XBARA1_IN28 input. */
+#define IMXRT_XBARA1_IN_ACMP4_OUT                        IMXRT_XBARA1(XBAR_INPUT, 29)   /* ACMP4_OUT output assigned to XBARA1_IN29 input. */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 30)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 31)   RESERVED */
+#define IMXRT_XBARA1_IN_QTIMER1_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 32)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
+#define IMXRT_XBARA1_IN_QTIMER1_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 33)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
+#define IMXRT_XBARA1_IN_QTIMER1_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 34)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
+#define IMXRT_XBARA1_IN_QTIMER1_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 35)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
+#define IMXRT_XBARA1_IN_QTIMER2_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 36)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
+#define IMXRT_XBARA1_IN_QTIMER2_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 37)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
+#define IMXRT_XBARA1_IN_QTIMER2_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 38)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
+#define IMXRT_XBARA1_IN_QTIMER2_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 39)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 40)   /* FLEXPWM1_PWM1_OUT_TRIG0 output OR assigned to XBARA1_IN40 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 40)   /* FLEXPWM1_PWM1_OUT_TRIG1 output OR assigned to XBARA1_IN40 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 41)   /* FLEXPWM1_PWM2_OUT_TRIG0 output OR assigned to XBARA1_IN41 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 41)   /* FLEXPWM1_PWM2_OUT_TRIG1 output OR assigned to XBARA1_IN41 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 42)   /* FLEXPWM1_PWM3_OUT_TRIG0 output OR assigned to XBARA1_IN42 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 42)   /* FLEXPWM1_PWM3_OUT_TRIG1 output OR assigned to XBARA1_IN42 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 43)   /* FLEXPWM1_PWM4_OUT_TRIG0 output OR assigned to XBARA1_IN43 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 43)   /* FLEXPWM1_PWM4_OUT_TRIG1 output OR assigned to XBARA1_IN43 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 44)   /* FLEXPWM2_PWM1_OUT_TRIG0 output OR assigned to XBARA1_IN44 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 44)   /* FLEXPWM2_PWM1_OUT_TRIG1 output OR assigned to XBARA1_IN44 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 45)   /* FLEXPWM2_PWM2_OUT_TRIG0 output OR assigned to XBARA1_IN45 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 45)   /* FLEXPWM2_PWM2_OUT_TRIG1 output OR assigned to XBARA1_IN45 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 46)   /* FLEXPWM2_PWM3_OUT_TRIG0 output OR assigned to XBARA1_IN46 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 46)   /* FLEXPWM2_PWM3_OUT_TRIG1 output OR assigned to XBARA1_IN46 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG0          IMXRT_XBARA1(XBAR_INPUT, 47)   /* FLEXPWM2_PWM4_OUT_TRIG0 output OR assigned to XBARA1_IN47 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG1          IMXRT_XBARA1(XBAR_INPUT, 47)   /* FLEXPWM2_PWM4_OUT_TRIG1 output OR assigned to XBARA1_IN47 input. */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 48)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 49)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 50)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 51)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 52)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 53)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 54)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 55)   RESERVED */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER0                     IMXRT_XBARA1(XBAR_INPUT, 56)   /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER1                     IMXRT_XBARA1(XBAR_INPUT, 57)   /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER2                     IMXRT_XBARA1(XBAR_INPUT, 58)   /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER3                     IMXRT_XBARA1(XBAR_INPUT, 59)   /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
+#define IMXRT_XBARA1_IN_ENC1_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 60)   /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
+#define IMXRT_XBARA1_IN_ENC2_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 61)   /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 62)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 63)   RESERVED */
+#define IMXRT_XBARA1_IN_DMA_DONE0                        IMXRT_XBARA1(XBAR_INPUT, 64)   /* DMA_DONE0 output assigned to XBARA1_IN64 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE1                        IMXRT_XBARA1(XBAR_INPUT, 65)   /* DMA_DONE1 output assigned to XBARA1_IN65 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE2                        IMXRT_XBARA1(XBAR_INPUT, 66)   /* DMA_DONE2 output assigned to XBARA1_IN66 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE3                        IMXRT_XBARA1(XBAR_INPUT, 67)   /* DMA_DONE3 output assigned to XBARA1_IN67 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE4                        IMXRT_XBARA1(XBAR_INPUT, 68)   /* DMA_DONE4 output assigned to XBARA1_IN68 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE5                        IMXRT_XBARA1(XBAR_INPUT, 69)   /* DMA_DONE5 output assigned to XBARA1_IN69 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE6                        IMXRT_XBARA1(XBAR_INPUT, 70)   /* DMA_DONE6 output assigned to XBARA1_IN70 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE7                        IMXRT_XBARA1(XBAR_INPUT, 71)   /* DMA_DONE7 output assigned to XBARA1_IN71 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT0                        IMXRT_XBARA1(XBAR_INPUT, 72)   /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT1                        IMXRT_XBARA1(XBAR_INPUT, 73)   /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT2                        IMXRT_XBARA1(XBAR_INPUT, 74)   /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT3                        IMXRT_XBARA1(XBAR_INPUT, 75)   /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 76)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 77)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 78)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_INPUT, 79)   RESERVED */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARA1(XBAR_INPUT, 80)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARA1(XBAR_INPUT, 81)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARA1(XBAR_INPUT, 82)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARA1(XBAR_INPUT, 83)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARA1(XBAR_INPUT, 84)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARA1(XBAR_INPUT, 85)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARA1(XBAR_INPUT, 86)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARA1(XBAR_INPUT, 87)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
+
+/* XBARA1 Mux Output  (M Muxes) ***************************************************************************************************************/
+
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 0)    /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 1)    /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 2)    /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 3)    /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 4)    /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 5)    /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 6)    /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 7)    /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 8)    /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 9)    /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 10)   /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 11)   /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 12)   /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 13)   /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 14)   /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 15)   /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 16)   /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 17)   /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 18)   /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 19)   /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
+#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 20)   /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 21)   /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 22)   /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 23)   /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 24)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 25)   RESERVED */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 26)   /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 27)   /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 28)   /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 29)   /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 30)   /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 31)   /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 32)   /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 33)   /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 34)   /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 35)   /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 36)   /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM12_FAULT2_SEL_OFFSET     IMXXRT_XBARA1(XBAR_OUTPUT,37)   /* XBARA1_OUT37 output assigned to FLEXPWM1_2_FAULT2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM12_FAULT3_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 38)   /* XBARA1_OUT38 output assigned to FLEXPWM1_2_FAULT3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 39)   /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA0_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 40)   /* XBARA1_OUT40 output assigned to FLEXPWM2_EXTA0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA1_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 41)   /* XBARA1_OUT41 output assigned to FLEXPWM2_EXTA1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA2_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 42)   /* XBARA1_OUT42 output assigned to FLEXPWM2_EXTA2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXTA3_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 43)   /* XBARA1_OUT43 output assigned to FLEXPWM2_EXTA3 */
+
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 44)   /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 45)   /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 46)   /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 47)   /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_CLK_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 48)   /* XBARA1_OUT48 output assigned to FLEXPWM2_EXT_CLK */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 49)   /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 50)   /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 51)   /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 52)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 53)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 54)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 55)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 56)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 57)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 58)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 59)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 60)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 61)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 62)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 63)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 64)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 65)   RESERVED */
+#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 66)   /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN */
+#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 67)   /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN */
+#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 68)   /* XBARA1_OUT68 output assigned to ENC1_INDEX */
+#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 69)   /* XBARA1_OUT69 output assigned to ENC1_HOME */
+#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 70)   /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */
+#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 71)   /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN */
+#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 72)   /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN */
+#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 73)   /* XBARA1_OUT73 output assigned to ENC2_INDEX */
+#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 74)   /* XBARA1_OUT74 output assigned to ENC2_HOME */
+#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 75)   /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 76)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 77)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 78)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 79)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 80)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 81)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 82)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 83)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 84)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 85)   RESERVED */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 86)   /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 87)   /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 88)   /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 89)   /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 90)   /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 91)   /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 92)   /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 93)   /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 94)   /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 95)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 96)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 97)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 98)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 99)   RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 100)  RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 101)  RESERVED */
+#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 102)  /* XBARA1_OUT102 output assigned to EWM_EWM_IN */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 103)  /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 104)  /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 105)  /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 106)  /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG10_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 107)  /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG10 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG11_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 108)  /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG11 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG12_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 109)  /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG12 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG13_SEL_OFFSET IMXRT_XBARA1(XBAR_OUTPUT, 110)  /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG13 */
+#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 111)  /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 112)  /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 113)  /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 114)  /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 115)  /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 116)  /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 117)  /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 118)  /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 119)  /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 120)  /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 121)  /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 122)  /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 123)  /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 124)  /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 125)  /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN */
+#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 126)  /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN */
+#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 127)  /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
+#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 128)  /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 129)  RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 130)  RESERVED */
+/* RESERVED                                              IMXRT_XBARA1(XBAR_OUTPUT, 131)  RESERVED */
+
+/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/
+
+#define IMXRT_XBARB2_IN_LOGIC_LOW                        IMXRT_XBARB2(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARB2_IN0 input. */
+#define IMXRT_XBARB2_IN_LOGIC_HIGH                       IMXRT_XBARB2(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 2)    RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 3)    RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 4)    RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 5)    RESERVED */
+#define IMXRT_XBARB2_IN_ACMP1_OUT                        IMXRT_XBARB2(XBAR_INPUT, 6)    /* ACMP1_OUT output assigned to XBARB2_IN6 input. */
+#define IMXRT_XBARB2_IN_ACMP2_OUT                        IMXRT_XBARB2(XBAR_INPUT, 7)    /* ACMP2_OUT output assigned to XBARB2_IN7 input. */
+#define IMXRT_XBARB2_IN_ACMP3_OUT                        IMXRT_XBARB2(XBAR_INPUT, 8)    /* ACMP3_OUT output assigned to XBARB2_IN8 input. */
+#define IMXRT_XBARB2_IN_ACMP4_OUT                        IMXRT_XBARB2(XBAR_INPUT, 9)    /* ACMP4_OUT output assigned to XBARB2_IN9 input. */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 10)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 11)   RESERVED */
+#define IMXRT_XBARB2_IN_QTIMER1_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 12)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
+#define IMXRT_XBARB2_IN_QTIMER1_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 13)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
+#define IMXRT_XBARB2_IN_QTIMER1_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 14)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
+#define IMXRT_XBARB2_IN_QTIMER1_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 15)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
+#define IMXRT_XBARB2_IN_QTIMER2_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 16)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
+#define IMXRT_XBARB2_IN_QTIMER2_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 17)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
+#define IMXRT_XBARB2_IN_QTIMER2_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 18)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
+#define IMXRT_XBARB2_IN_QTIMER2_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 19)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG0 output OR assigned to XBARB2_IN20 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG1 output OR assigned to XBARB2_IN20 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG0 output OR assigned to XBARB2_IN21 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG1 output OR assigned to XBARB2_IN21 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG0 output OR assigned to XBARB2_IN22 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG1 output OR assigned to XBARB2_IN22 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG0 output OR assigned to XBARB2_IN23 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG1 output OR assigned to XBARB2_IN23 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG0 output OR assigned to XBARB2_IN24 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG1 output OR assigned to XBARB2_IN24 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG0 output OR assigned to XBARB2_IN25 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG1 output OR assigned to XBARB2_IN25 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG0 output OR assigned to XBARB2_IN26 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG1 output OR assigned to XBARB2_IN26 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG0          IMXRT_XBARB2(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG0 output OR assigned to XBARB2_IN27 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG1          IMXRT_XBARB2(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG1 output OR assigned to XBARB2_IN27 input. */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 28)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 29)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 30)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 31)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 32)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 33)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 34)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 35)   RESERVED */
+#define IMXRT_XBARB2_IN_PIT_TRIGGER0                     IMXRT_XBARB2(XBAR_INPUT, 36)   /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
+#define IMXRT_XBARB2_IN_PIT_TRIGGER1                     IMXRT_XBARB2(XBAR_INPUT, 37)   /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARB2(XBAR_INPUT, 38)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARB2(XBAR_INPUT, 39)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARB2(XBAR_INPUT, 40)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARB2(XBAR_INPUT, 41)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARB2(XBAR_INPUT, 42)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARB2(XBAR_INPUT, 43)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARB2(XBAR_INPUT, 44)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARB2(XBAR_INPUT, 45)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
+#define IMXRT_XBARB2_IN_ENC1_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 46)   /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
+#define IMXRT_XBARB2_IN_ENC2_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 47)   /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 48)   RESERVED */
+/* RESERVED                                              IMXRT_XBARB2(XBAR_INPUT, 49)   RESERVED */
+#define IMXRT_XBARB2_IN_DMA_DONE0                        IMXRT_XBARB2(XBAR_INPUT, 50)   /* DMA_DONE0 output assigned to XBARB2_IN50 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE1                        IMXRT_XBARB2(XBAR_INPUT, 51)   /* DMA_DONE1 output assigned to XBARB2_IN51 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE2                        IMXRT_XBARB2(XBAR_INPUT, 52)   /* DMA_DONE2 output assigned to XBARB2_IN52 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE3                        IMXRT_XBARB2(XBAR_INPUT, 53)   /* DMA_DONE3 output assigned to XBARB2_IN53 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE4                        IMXRT_XBARB2(XBAR_INPUT, 54)   /* DMA_DONE4 output assigned to XBARB2_IN54 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE5                        IMXRT_XBARB2(XBAR_INPUT, 55)   /* DMA_DONE5 output assigned to XBARB2_IN55 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE6                        IMXRT_XBARB2(XBAR_INPUT, 56)   /* DMA_DONE6 output assigned to XBARB2_IN56 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE7                        IMXRT_XBARB2(XBAR_INPUT, 57)   /* DMA_DONE7 output assigned to XBARB2_IN57 input. */
+
+/* XBARB2 Mux Output  (M Muxes) ********************************************************************************************************************/
+
+#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 0)    /* XBARB2_OUT0 output assigned to AOI1_IN00 */
+#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 1)    /* XBARB2_OUT1 output assigned to AOI1_IN01 */
+#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 2)    /* XBARB2_OUT2 output assigned to AOI1_IN02 */
+#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 3)    /* XBARB2_OUT3 output assigned to AOI1_IN03 */
+#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 4)    /* XBARB2_OUT4 output assigned to AOI1_IN04 */
+#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 5)    /* XBARB2_OUT5 output assigned to AOI1_IN05 */
+#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 6)    /* XBARB2_OUT6 output assigned to AOI1_IN06 */
+#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 7)    /* XBARB2_OUT7 output assigned to AOI1_IN07 */
+#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 8)    /* XBARB2_OUT8 output assigned to AOI1_IN08 */
+#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 9)    /* XBARB2_OUT9 output assigned to AOI1_IN09 */
+#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 10)   /* XBARB2_OUT10 output assigned to AOI1_IN10 */
+#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 11)   /* XBARB2_OUT11 output assigned to AOI1_IN11 */
+#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 12)   /* XBARB2_OUT12 output assigned to AOI1_IN12 */
+#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 13)   /* XBARB2_OUT13 output assigned to AOI1_IN13 */
+#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 14)   /* XBARB2_OUT14 output assigned to AOI1_IN14 */
+#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 15)   /* XBARB2_OUT15 output assigned to AOI1_IN15 */
diff --git a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h
new file mode 100644
index 00000000000..40bd07a635c
--- /dev/null
+++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h
@@ -0,0 +1,1145 @@
+/************************************************************************************************************
+ * arch/arm/src/imxrt/hardware/rt105x/imxrt_ccm.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Authors:  Janne Rosberg 
+ *             David Sidrane 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_CCM_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_CCM_H
+
+/************************************************************************************************************
+ * Included Files
+ ************************************************************************************************************/
+
+#include 
+#include "hardware/imxrt_memorymap.h"
+
+/************************************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************************************/
+
+/* Register offsets *****************************************************************************************/
+
+#define IMXRT_CCM_CCR_OFFSET                     0x0000  /* CCM Control Register */
+                                              /* 0x0004  Reserved */
+#define IMXRT_CCM_CSR_OFFSET                     0x0008  /* CCM Status Register */
+#define IMXRT_CCM_CCSR_OFFSET                    0x000c  /* CCM Clock Switcher Register */
+#define IMXRT_CCM_CACRR_OFFSET                   0x0010  /* CCM Arm Clock Root Register */
+#define IMXRT_CCM_CBCDR_OFFSET                   0x0014  /* CCM Bus Clock Divider Register */
+#define IMXRT_CCM_CBCMR_OFFSET                   0x0018  /* CCM Bus Clock Multiplexer Register */
+#define IMXRT_CCM_CSCMR1_OFFSET                  0x001c  /* CCM Serial Clock Multiplexer Register 1 */
+#define IMXRT_CCM_CSCMR2_OFFSET                  0x0020  /* CCM Serial Clock Multiplexer Register 2 */
+#define IMXRT_CCM_CSCDR1_OFFSET                  0x0024  /* CCM Serial Clock Divider Register 1 */
+#define IMXRT_CCM_CS1CDR_OFFSET                  0x0028  /* CCM Clock Divider Register */
+#define IMXRT_CCM_CS2CDR_OFFSET                  0x002c  /* CCM Clock Divider Register */
+#define IMXRT_CCM_CDCDR_OFFSET                   0x0030  /* CCM D1 Clock Divider Register */
+                                              /* 0x0034  Reserved */
+#define IMXRT_CCM_CSCDR2_OFFSET                  0x0038  /* CCM Serial Clock Divider Register 2 */
+#define IMXRT_CCM_CSCDR3_OFFSET                  0x003c  /* CCM Serial Clock Divider Register 3 */
+                                              /* 0x0040  Reserved */
+                                              /* 0x0044  Reserved */
+#define IMXRT_CCM_CDHIPR_OFFSET                  0x0048  /* CCM Divider Handshake In-Process Register */
+                                              /* 0x004c  Reserved */
+                                              /* 0x0050  Reserved */
+#define IMXRT_CCM_CLPCR_OFFSET                   0x0054  /* CCM Low Power Control Register */
+
+#define IMXRT_CCM_CISR_OFFSET                    0x0058  /* CCM Interrupt Status Register */
+#define IMXRT_CCM_CIMR_OFFSET                    0x005c  /* CCM Interrupt Mask Register */
+#define IMXRT_CCM_CCOSR_OFFSET                   0x0060  /* CCM Clock Output Source Register */
+#define IMXRT_CCM_CGPR_OFFSET                    0x0064  /* CCM General Purpose Register */
+#define IMXRT_CCM_CCGR0_OFFSET                   0x0068  /* CCM Clock Gating Register 0 */
+#define IMXRT_CCM_CCGR1_OFFSET                   0x006c  /* CCM Clock Gating Register 1 */
+#define IMXRT_CCM_CCGR2_OFFSET                   0x0070  /* CCM Clock Gating Register 2 */
+#define IMXRT_CCM_CCGR3_OFFSET                   0x0074  /* CCM Clock Gating Register 3 */
+#define IMXRT_CCM_CCGR4_OFFSET                   0x0078  /* CCM Clock Gating Register 4 */
+#define IMXRT_CCM_CCGR5_OFFSET                   0x007c  /* CCM Clock Gating Register 5 */
+#define IMXRT_CCM_CCGR6_OFFSET                   0x0080  /* CCM Clock Gating Register 6 */
+                                              /* 0x0084  Reserved */
+#define IMXRT_CCM_CMEOR_OFFSET                   0x0088  /* CCM Module Enable Overide Register */
+
+/* Analog */
+
+#define IMXRT_CCM_ANALOG_PLL_ARM_OFFSET          0x0000  /* Analog ARM PLL control Register */
+#define IMXRT_CCM_ANALOG_PLL_USB1_OFFSET         0x0010  /* Analog USB1 480MHz PLL Control Register */
+#define IMXRT_CCM_ANALOG_PLL_USB2_OFFSET         0x0020  /* Analog USB2 480MHz PLL Control Register */
+#define IMXRT_CCM_ANALOG_PLL_SYS_OFFSET          0x0030  /* Analog System PLL Control Register */
+#define IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET       0x0040  /* 528MHz System PLL Spread Spectrum Register */
+#define IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET      0x0050  /* Numerator of 528MHz System PLL Fractional Loop Divider */
+#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET    0x0060  /* Denominator of 528MHz System PLL Fractional Loop Divider */
+#define IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET        0x0070  /* Analog Audio PLL control Register */
+#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET    0x0080  /* Numerator of Audio PLL Fractional Loop Divider */
+#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET  0x0090  /* Denominator of Audio PLL Fractional Loop Divider */
+#define IMXRT_CCM_ANALOG_PLL_VIDEO_OFFSET        0x00a0  /* Analog Video PLL control Register */
+#define IMXRT_CCM_ANALOG_PLL_VIDEO_NUM_OFFSET    0x00b0  /* Numerator of Video PLL Fractional Loop Divider */
+#define IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM_OFFSET  0x00c0  /* Denominator of Video PLL Fractional Loop Divider */
+#define IMXRT_CCM_ANALOG_PLL_ENET_OFFSET         0x00e0  /* Analog ENET PLL Control Register */
+#define IMXRT_CCM_ANALOG_PFD_480_OFFSET          0x00f0  /* 480MHz Clock (PLL3) Phase Fractional Divider Control */
+#define IMXRT_CCM_ANALOG_PFD_528_OFFSET          0x0100  /* 528MHz Clock (PLL2) Phase Fractional Divider Control */
+#define IMXRT_CCM_ANALOG_MISC0_OFFSET            0x0150  /* Miscellaneous Register 0 */
+#define IMXRT_CCM_ANALOG_MISC1_OFFSET            0x0160  /* Miscellaneous Register 1 */
+#define IMXRT_CCM_ANALOG_MISC2_OFFSET            0x0170  /* Miscellaneous Register 2 */
+
+/* Register addresses ***************************************************************************************/
+
+#define IMXRT_CCM_CCR                            (IMXRT_CCM_BASE + IMXRT_CCM_CCR_OFFSET)
+#define IMXRT_CCM_CSR                            (IMXRT_CCM_BASE + IMXRT_CCM_CSR_OFFSET)
+#define IMXRT_CCM_CCSR                           (IMXRT_CCM_BASE + IMXRT_CCM_CCSR_OFFSET)
+#define IMXRT_CCM_CACRR                          (IMXRT_CCM_BASE + IMXRT_CCM_CACRR_OFFSET)
+#define IMXRT_CCM_CBCDR                          (IMXRT_CCM_BASE + IMXRT_CCM_CBCDR_OFFSET)
+#define IMXRT_CCM_CBCMR                          (IMXRT_CCM_BASE + IMXRT_CCM_CBCMR_OFFSET)
+#define IMXRT_CCM_CSCMR1                         (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR1_OFFSET)
+#define IMXRT_CCM_CSCMR2                         (IMXRT_CCM_BASE + IMXRT_CCM_CSCMR2_OFFSET)
+#define IMXRT_CCM_CSCDR1                         (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR1_OFFSET)
+#define IMXRT_CCM_CS1CDR                         (IMXRT_CCM_BASE + IMXRT_CCM_CS1CDR_OFFSET)
+#define IMXRT_CCM_CS2CDR                         (IMXRT_CCM_BASE + IMXRT_CCM_CS2CDR_OFFSET)
+#define IMXRT_CCM_CDCDR                          (IMXRT_CCM_BASE + IMXRT_CCM_CDCDR_OFFSET)
+#define IMXRT_CCM_CSCDR2                         (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR2_OFFSET)
+#define IMXRT_CCM_CSCDR3                         (IMXRT_CCM_BASE + IMXRT_CCM_CSCDR3_OFFSET)
+#define IMXRT_CCM_CDHIPR                         (IMXRT_CCM_BASE + IMXRT_CCM_CDHIPR_OFFSET)
+#define IMXRT_CCM_CLPCR                          (IMXRT_CCM_BASE + IMXRT_CCM_CLPCR_OFFSET)
+#define IMXRT_CCM_CISR                           (IMXRT_CCM_BASE + IMXRT_CCM_CISR_OFFSET)
+#define IMXRT_CCM_CIMR                           (IMXRT_CCM_BASE + IMXRT_CCM_CIMR_OFFSET)
+#define IMXRT_CCM_CCOSR                          (IMXRT_CCM_BASE + IMXRT_CCM_CCOSR_OFFSET)
+#define IMXRT_CCM_CGPR                           (IMXRT_CCM_BASE + IMXRT_CCM_CGPR_OFFSET)
+#define IMXRT_CCM_CCGR0                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR0_OFFSET)
+#define IMXRT_CCM_CCGR1                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR1_OFFSET)
+#define IMXRT_CCM_CCGR2                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR2_OFFSET)
+#define IMXRT_CCM_CCGR3                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR3_OFFSET)
+#define IMXRT_CCM_CCGR4                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR4_OFFSET)
+#define IMXRT_CCM_CCGR5                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR5_OFFSET)
+#define IMXRT_CCM_CCGR6                          (IMXRT_CCM_BASE + IMXRT_CCM_CCGR6_OFFSET)
+#define IMXRT_CCM_CMEOR                          (IMXRT_CCM_BASE + IMXRT_CCM_CMEOR_OFFSET)
+
+#define IMXRT_CCM_ANALOG_PLL_ARM                 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ARM_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_USB1                (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB1_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_USB2                (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_USB2_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_SYS                 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_SYS_SS              (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_SS_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_SYS_NUM             (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_NUM_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_SYS_DENOM           (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_SYS_DENOM_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_AUDIO               (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_AUDIO_NUM           (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_NUM_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM         (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_AUDIO_DENOM_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_VIDEO               (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_VIDEO_NUM           (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_NUM_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM         (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM_OFFSET)
+#define IMXRT_CCM_ANALOG_PLL_ENET                (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PLL_ENET_OFFSET)
+#define IMXRT_CCM_ANALOG_PFD_480                 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_480_OFFSET)
+#define IMXRT_CCM_ANALOG_PFD_528                 (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_PFD_528_OFFSET)
+#define IMXRT_CCM_ANALOG_MISC0                   (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC0_OFFSET)
+#define IMXRT_CCM_ANALOG_MISC1                   (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC1_OFFSET)
+#define IMXRT_CCM_ANALOG_MISC2                   (IMXRT_ANATOP_BASE + IMXRT_CCM_ANALOG_MISC2_OFFSET)
+
+/* Helper Macros *********************************************************************************/
+
+#define CCM_PODF_FROM_DIVISOR(n)                   ((n)-1)  /* PODF Values are divisor-1 */
+
+/* Register bit definitions *********************************************************************************/
+
+/* Control Register */
+
+#define CCM_CCR_OSCNT_SHIFT                      (0)       /* Bits 0-7:   Oscillator ready counter value */
+#define CCM_CCR_OSCNT_MASK                       (0xff << CCM_CCR_OSCNT_SHIFT)
+#  define CCM_CCR_OSCNT(n)                       ((uint32_t)(n) << CCM_CCR_OSCNT_SHIFT)
+                                                           /* Bits 8-11:  Reserved */
+#define CCM_CCR_COSC_EN                          (1 << 12) /* Bit  12:    On chip oscillator enable */
+                                                           /* Bits 13-20: Reserved */
+#define CCM_CCR_REG_BYPASS_COUNT_SHIFT           (21)      /* Bits 21-26: Counter for analog_reg_bypass */
+#define CCM_CCR_REG_BYPASS_COUNT_MASK            (0x3f << CCM_CCR_REG_BYPASS_COUNT_SHIFT)
+#  define CCM_CCR_REG_BYPASS_COUNT(n)            ((uint32_t)(n) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)
+#define CCM_CCR_RBC_EN                           (1 << 27) /* Bit  27:    Enable for REG_BYPASS_COUNTER */
+                                                           /* Bits 28-31: Reserved */
+/*  Status Register  */
+
+#define CCM_CSR_REF_EN_B                         (1 << 0)  /* Bit 0:      Status of the value of CCM_REF_EN_B */
+                                                           /* Bits 1-2:   Reserved */
+#define CCM_CSR_CAMP2_READY                      (3 << 0)  /* Bit 3:      Status indication of CAMP2 */
+                                                           /* Bit 4:      Reserved */
+#define CCM_CSR_COSC_READY                       (5 << 0)  /* Bit 5:      Status indication of on board oscillator */
+                                                           /* Bits 6-31:  Reserved */
+/* Clock Switcher Register */
+
+#define CCM_CCSR_PLL3_SW_CLK_SEL                 (1 << 0)  /* Bit 0: Selects source to generate pll3_sw_clk */
+
+/* Arm Clock Root Register */
+
+#define CCM_CACRR_ARM_PODF_SHIFT                 (0)       /* Bits 0-2:   Divider for ARM clock root */
+#define CCM_CACRR_ARM_PODF_MASK                  (0x3 << CCM_CACRR_ARM_PODF_SHIFT)
+#  define CCM_CACRR_ARM_PODF(n)                  ((uint32_t)(n) << CCM_CACRR_ARM_PODF_SHIFT)
+
+/* Bus Clock Divider Register */
+
+                                                           /* Bits 0-5:   Reserved */
+#define CCM_CBCDR_SEMC_CLK_SEL                   (1 << 6)  /* Bit 6:      SEMC clock source select */
+#define CCM_CBCDR_SEMC_ALT_CLK_SEL               (1 << 7)  /* Bit 7:      SEMC alternative clock select */
+#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL2          (0 << 7)  /* Bit 7:      PLL2 PFD2 will be selected */
+#define CCM_CBCDR_SEMC_ALT_CLK_SEL_PLL3          (1 << 7)  /* Bit 7:      PLL3 PFD1 will be selected  */
+#define CCM_CBCDR_IPG_PODF_SHIFT                 (8)       /* Bits 8-9:   Divider for ipg podf */
+#define CCM_CBCDR_IPG_PODF_MASK                  (0x3 << CCM_CBCDR_IPG_PODF_SHIFT)
+#  define CCM_CBCDR_IPG_PODF(n)                  ((uint32_t)(n) << CCM_CBCDR_IPG_PODF_SHIFT)
+#define CCM_CBCDR_AHB_PODF_SHIFT                 (10)      /* Bits 10-12: Divider for AHB PODF */
+#define CCM_CBCDR_AHB_PODF_MASK                  (0x3 << CCM_CBCDR_AHB_PODF_SHIFT)
+#  define CCM_CBCDR_AHB_PODF(n)                  ((uint32_t)(n) << CCM_CBCDR_AHB_PODF_SHIFT)
+                                                           /* Bits 13-15: Reserved */
+#define CCM_CBCDR_SEMC_PODF_SHIFT                (16)      /* Bits 16-18: Post divider for SEMC clock */
+#define CCM_CBCDR_SEMC_PODF_MASK                 (0x3 << CCM_CBCDR_SEMC_PODF_SHIFT)
+# define CCM_CBCDR_SEMC_PODF(n)                  ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT)
+                                                           /* Bits 19-24: Reserved */
+#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT           (25)      /* Bit 25:     Selector for peripheral main clock */
+#define CCM_CBCDR_PERIPH_CLK_SEL_MASK            (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)
+#  define CCM_CBCDR_PERIPH_CLK_SEL(n)            ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)
+#  define CCM_CBCDR_PERIPH_CLK_SEL_PRE_PERIPH    (0)
+#  define CCM_CBCDR_PERIPH_CLK_SEL_PERIPH_CLK2   (1)
+
+                                                           /* Bit 26:     Reserved */
+#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT         (27)      /* Bits 27-29: Divider for periph_clk2_podf */
+#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK          (0x7 << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)
+#  define CCM_CBCDR_PERIPH_CLK2_PODF(n)          ((uint32_t)(n) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)
+                                                          /* Bits 30-31: Reserved */
+
+/* Bus Clock Multiplexer Register */
+
+                                                           /* Bits 0-3:   Reserved */
+#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT            (4)       /* Bits 4-5:   Selector for lpspi clock multiplexer */
+#define CCM_CBCMR_LPSPI_CLK_SEL_MASK             (0x3 << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_LPSPI_CLK_SEL(n)             ((uint32_t)(n) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD1      ((uint32_t)(0) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_LPSPI_CLK_SEL_PLL3_PFD0      ((uint32_t)(1) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_LPSPI_CLK_SEL_PLL2           ((uint32_t)(2) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_LPSPI_CLK_SEL_PLL2_PFD2      ((uint32_t)(3) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)
+                                                           /* Bits 6-11:  Reserved */
+#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT          (12)      /* Bits 12-13: Selector for peripheral clk2 clock multiplexer */
+#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK           (0x3 << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)
+#  define CCM_CBCMR_PERIPH_CLK2_SEL(n)           ((uint32_t)(n) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)
+#  define CCM_CBCMR_PERIPH_CLK2_SEL_PLL3_SW      ((uint32_t)(0) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)
+#  define CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK      ((uint32_t)(1) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)
+#  define CCM_CBCMR_PERIPH_CLK2_SEL_PLL2_BP      ((uint32_t)(2) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)
+#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT            (14)      /* Bits 14-15: Selector for Trace clock multiplexer */
+#define CCM_CBCMR_TRACE_CLK_SEL_MASK             (0x3 << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_TRACE_CLK_SEL(n)             ((uint32_t)(n) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_TRACE_CLK_SEL_PLL2           ((uint32_t)(0) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD2      ((uint32_t)(1) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD0      ((uint32_t)(2) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_TRACE_CLK_SEL_PLL2_PFD1      ((uint32_t)(3) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)
+                                                           /* Bits 16-17: Reserved */
+#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT       (18)      /* Bits 18-19: Selector for pre_periph clock multiplexer */
+#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK        (0x3 << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_PRE_PERIPH_CLK_SEL(n)        ((uint32_t)(n) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)
+#  define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2      (0)
+#  define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD2 (1)
+#  define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL2_PFD0 (2)
+#  define CCM_CBCMR_PRE_PERIPH_CLK_SEL_PLL1      (3)
+                                                           /* Bits 20-22: Reserved */
+#define CCM_CBCMR_LCDIF_PODF_SHIFT               (23)      /* Bits 23-25: Post-divider for LCDIF clock */
+#define CCM_CBCMR_LCDIF_PODF_MASK                (0x7 << CCM_CBCMR_LCDIF_PODF_SHIFT)
+# define CCM_CBCMR_LCDIF_PODF(n)                 ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT)
+#define CCM_CBCMR_LPSPI_PODF_SHIFT               (26)      /* Bits 26-28: Divider for LPSPI */
+#define CCM_CBCMR_LPSPI_PODF_MASK                (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT)
+#  define CCM_CBCMR_LPSPI_PODF(n)                ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT)
+
+/* Serial Clock Multiplexer Register 1 */
+
+#define CCM_CSCMR1_PERCLK_PODF_SHIFT             (0)       /* Bits 0-5:   Divider for perclk podf  */
+#define CCM_CSCMR1_PERCLK_PODF_MASK              (0x3f << CCM_CSCMR1_PERCLK_PODF_SHIFT)
+#  define CCM_CSCMR1_PERCLK_PODF(n)              ((uint32_t)(n) << CCM_CSCMR1_PERCLK_PODF_SHIFT)
+#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT          (6)       /* Bit 6:      Selector for the perclk clock multiplexer */
+#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK           (1 << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_PERCLK_CLK_SEL(n)           ((uint32_t)(n) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_PERCLK_CLK_SEL_IPG_CLK_ROOT (0)
+#  define CCM_CSCMR1_PERCLK_CLK_SEL_OSC_CLK      (1)
+                                                           /* Bits 7-9:   Reserved */
+#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT            (10)      /* Bits 10-11: Selector for sai1 clock multiplexer */
+#define CCM_CSCMR1_SAI1_CLK_SEL_MASK             (0x3 << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI1_CLK_SEL(n)             ((uint32_t)(n) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI1_CLK_SEL_PLL3_PFD2      ((uint32_t)(0) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI1_CLK_SEL_PLL5           ((uint32_t)(1) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI1_CLK_SEL_PLL4           ((uint32_t)(2) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)
+#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT            (12)      /* Bits 12-13: Selector for sai2 clock multiplexer */
+#define CCM_CSCMR1_SAI2_CLK_SEL_MASK             (0x3 << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI2_CLK_SEL(n)             ((uint32_t)(n) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI2_CLK_SEL_PLL3_PFD2      ((uint32_t)(0) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI2_CLK_SEL_PLL5           ((uint32_t)(1) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI2_CLK_SEL_PLL4           ((uint32_t)(2) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)
+#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT            (14)      /* Bits 14-15: Selector for sai3 clock multiplexer */
+#define CCM_CSCMR1_SAI3_CLK_SEL_MASK             (0x3 << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI3_CLK_SEL(n)             ((uint32_t)(n) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI3_CLK_SEL_PLL3_PFD2      ((uint32_t)(0) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI3_CLK_SEL_PLL5           ((uint32_t)(1) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_SAI3_CLK_SEL_PLL4           ((uint32_t)(2) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)
+#define CCM_CSCMR1_USDHC1_CLK_SEL                (1 << 16) /* Bit 16:     Selector for usdhc1 clock multiplexer */
+#  define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD2    (0 << 16) /* derive clock from PLL2 PFD2 */
+#  define CCM_CSCMR1_USDHC1_CLK_SEL_PLL2_PFD0    (1 << 16) /* derive clock from PLL2 PFD0 */
+#define CCM_CSCMR1_USDHC2_CLK_SEL                (1 << 17) /* Bit 17:     Selector for usdhc2 clock multiplexer */
+#  define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD2    (0 << 17) /* derive clock from PLL2 PFD2 */
+#  define CCM_CSCMR1_USDHC2_CLK_SEL_PLL2_PFD0    (1 << 17) /* derive clock from PLL2 PFD0 */
+                                                           /* Bits 18-22: Reserved */
+#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT            (23)      /* Bits 23-25: Divider for flexspi clock root */
+#define CCM_CSCMR1_FLEXSPI_PODF_MASK             (0x7 << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)
+#  define CCM_CSCMR1_FLEXSPI_PODF(n)             ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)
+                                                           /* Bits 26-28: Reserved */
+#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT         (29)      /* Bits 29-30: Selector for flexspi clock multiplexer */
+#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK          (0x3 << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_FLEXSPI_CLK_SEL(n)          ((uint32_t)(n) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_FLEXSPI_CLK_SEL_SEMC_CLK    ((uint32_t)(0) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_SW     ((uint32_t)(1) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL2_PFD2   ((uint32_t)(2) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)
+#  define CCM_CSCMR1_FLEXSPI_CLK_SEL_PLL3_PFD0   ((uint32_t)(3) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)
+                                                           /* Bit 31:     Reserved */
+
+/* Serial Clock Multiplexer Register 2 */
+
+#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT            (2)       /* Bits 2-7:   Divider for can clock podf */
+#define CCM_CSCMR2_CAN_CLK_PODF_MASK             (0x3f << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)
+#  define CCM_CSCMR2_CAN_CLK_PODF(n)             ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)
+#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT             (8)       /* Bits 8-9:   Selector for FlexCAN clock multiplexer */
+#define CCM_CSCMR2_CAN_CLK_SEL_MASK              (0x3 << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_CAN_CLK_SEL(n)              ((uint32_t)(n) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_60      ((uint32_t)(0) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_CAN_CLK_SEL_OSC_CLK         ((uint32_t)(1) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_CAN_CLK_SEL_PLL3_SW_80      ((uint32_t)(2) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)
+                                                           /* Bits 10-18: Reserved */
+#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT         (19)      /* Bits 19-20: Selector for flexio2 clock multiplexer */
+#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK          (0x3 << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_FLEXIO2_CLK_SEL(n)          ((uint32_t)(n) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL4        ((uint32_t)(0) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_PFD2   ((uint32_t)(1) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL5        ((uint32_t)(2) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)
+#  define CCM_CSCMR2_FLEXIO2_CLK_SEL_PLL3_SW     ((uint32_t)(3) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)
+                                                           /* Bits 21-31: Reserved */
+
+/* Serial Clock Divider Register 1 */
+
+#define CCM_CSCDR1_UART_CLK_PODF_SHIFT           (0)       /* Bits 0-5:   Divider for uart clock podf */
+#define CCM_CSCDR1_UART_CLK_PODF_MASK            (0x3f << CCM_CSCDR1_UART_CLK_PODF_SHIFT)
+#  define CCM_CSCDR1_UART_CLK_PODF(n)            ((uint32_t)(n) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)
+#define CCM_CSCDR1_UART_CLK_SEL                  (1 << 6)  /* Bit 6:      Selector for the UART clock multiplexer */
+#  define CCM_CSCDR1_UART_CLK_SEL_PLL3_80        (0 << 6)  /* derive clock from pll3_80m */
+#  define CCM_CSCDR1_UART_CLK_SEL_OSC_CLK        (1 << 6)  /* derive clock from osc_clk */
+                                                           /* Bits 7-10:  Reserved */
+#define CCM_CSCDR1_USDHC1_PODF_SHIFT             (11)      /* Bits 11-13: Divider for usdhc1 clock podf */
+#define CCM_CSCDR1_USDHC1_PODF_MASK              (0x7 << CCM_CSCDR1_USDHC1_PODF_SHIFT)
+#  define CCM_CSCDR1_USDHC1_PODF(n)              ((uint32_t)(n) << CCM_CSCDR1_USDHC1_PODF_SHIFT)
+                                                           /* Bits 14-15: Reserved */
+#define CCM_CSCDR1_USDHC2_PODF_SHIFT             (16)      /* Bits 16-18: Divider for usdhc2 clock */
+#define CCM_CSCDR1_USDHC2_PODF_MASK              (0x7 << CCM_CSCDR1_USDHC2_PODF_SHIFT)
+#  define CCM_CSCDR1_USDHC2_PODF(n)              ((uint32_t)(n) << CCM_CSCDR1_USDHC2_PODF_SHIFT)
+                                                           /* Bits 19-24: Reserved */
+#define CCM_CSCDR1_TRACE_PODF_SHIFT              (25)      /* Bits 25-27: Divider for trace clock */
+#define CCM_CSCDR1_TRACE_PODF_MASK               (0x7 << CCM_CSCDR1_TRACE_PODF_SHIFT)
+#  define CCM_CSCDR1_TRACE_PODF(n)               ((uint32_t)(n) << CCM_CSCDR1_TRACE_PODF_SHIFT)
+                                                           /* Bits 28-31: Reserved */
+
+/*  Clock Divider Register 1 */
+
+#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT           (0)       /* Bits 0-5:   Divider for sai1 clock podf */
+#define CCM_CS1CDR_SAI1_CLK_PODF_MASK            (0x3f << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)
+#  define CCM_CS1CDR_SAI1_CLK_PODF(n)            ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)
+#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT           (6)       /* Bits 6-8:   Divider for sai1 clock pred */
+#define CCM_CS1CDR_SAI1_CLK_PRED_MASK            (0x7 << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)
+#  define CCM_CS1CDR_SAI1_CLK_PRED(n)            ((uint32_t)(n) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)
+#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT        (9)       /* Bits 9-11:  Divider for flexio2 clock */
+#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK         (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)
+#  define CCM_CS1CDR_FLEXIO2_CLK_PRED(n)         ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)
+                                                           /* Bits 12-15: Reserved */
+#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT           (16)      /* Bits 16-21: Divider for sai3 clock podf */
+#define CCM_CS1CDR_SAI3_CLK_PODF_MASK            (0x3f << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)
+#  define CCM_CS1CDR_SAI3_CLK_PODF(n)            ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)
+#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT           (22)      /* Bits 22-24:   Divider for sai3 clock pred */
+#define CCM_CS1CDR_SAI3_CLK_PRED_MASK            (0x7 << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)
+#  define CCM_CS1CDR_SAI3_CLK_PRED(n)            ((uint32_t)(n) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)
+#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT        (25)      /* Bits 25-27:  Divider for flexio2 clock */
+#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK         (0x7 << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)
+#  define CCM_CS1CDR_FLEXIO2_CLK_PODF(n)         ((uint32_t)(n) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)
+                                                           /* Bits 28-31: Reserved */
+
+/*  Clock Divider Register 2 */
+
+#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT           (0)       /* Bits 0-5:   Divider for sai2 clock podf */
+#define CCM_CS2CDR_SAI2_CLK_PODF_MASK            (0x3f << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)
+#  define CCM_CS2CDR_SAI2_CLK_PODF(n)            ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)
+#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT           (6)       /* Bits 6-8:   Divider for sai2 clock pred */
+#define CCM_CS2CDR_SAI2_CLK_PRED_MASK            (0x7 << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)
+#  define CCM_CS2CDR_SAI2_CLK_PRED(n)            ((uint32_t)(n) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)
+
+/* D1 Clock Divider Register */
+
+#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT          (7)       /* Bits 7-8:   Selector for flexio1 clock multiplexer */
+#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK           (0x3 << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)
+#  define CCM_CDCDR_FLEXIO1_CLK_SEL(n)           ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)
+#  define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL4         ((uint32_t)(0) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)
+#  define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PFD2    ((uint32_t)(1) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)
+#  define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PLL5    ((uint32_t)(2) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)
+#  define CCM_CDCDR_FLEXIO1_CLK_SEL_PLL3_PLL3_SW ((uint32_t)(3) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)
+#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT         (9)       /* Bits 9-11:  Divider for flexio1 clock podf */
+#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK          (0x7 << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)
+#  define CCM_CDCDR_FLEXIO1_CLK_PODF(n)          ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)
+#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT         (12)      /* Bits 12-14:  Divider for flexio1 clock pred */
+#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK          (0x7 << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)
+#  define CCM_CDCDR_FLEXIO1_CLK_PRED(n)          ((uint32_t)(n) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)
+                                                           /* Bits 15-19: Reserved */
+#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT           (20)      /* Bits 20-21: Selector for spdif0 clock multiplexer */
+#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK            (0x3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)
+#  define CCM_CDCDR_SPDIF0_CLK_SEL(n)            ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)
+#  define CCM_CDCDR_SPDIF0_CLK_SEL_PLL4          ((uint32_t)(0) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)
+#  define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD2     ((uint32_t)(1) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)
+#  define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL5     ((uint32_t)(2) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)
+#  define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PLL3_SW  ((uint32_t)(3) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)
+#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT          (22)      /* Bits 22-24: Divider for spdif0 clock podf */
+#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK           (0x7 << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)
+#  define CCM_CDCDR_SPDIF0_CLK_PODF(n)           ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)
+#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT          (25)      /* Bits 25-27: Divider for spdif0 clock pred */
+#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK           (0x7 << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)
+#  define CCM_CDCDR_SPDIF0_CLK_PRED(n)           ((uint32_t)(n) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)
+
+/* Serial Clock Divider Register 2 */
+
+                                                           /* Bits 0-8:   Reserved */
+#define CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT           (9)       /* Bits 9-11:  Selector for LCDIF root clock multiplexer */
+#define CCM_CSCDR2_LCDIF_CLK_SEL_MASK            (0x7 << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT)
+#  define CCM_CSCDR2_LCDIF_CLK_SEL(n)            ((uint32_t)(n) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT)
+#  define CCM_CSCDR2_LCDIF_CLK_SEL_LCDIF         ((uint32_t)(0) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT)
+#  define CCM_CSCDR2_LCDIF_CLK_SEL_IPP_DI0_CLK   ((uint32_t)(1) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT)
+#  define CCM_CSCDR2_LCDIF_CLK_SEL_IPP_DI1_CLK   ((uint32_t)(2) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT)
+#  define CCM_CSCDR2_LCDIF_CLK_SEL_IDB_DI0_CLK   ((uint32_t)(3) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT)
+#  define CCM_CSCDR2_LCDIF_CLK_SEL_IDB_DI1_CLK   ((uint32_t)(4) << CCM_CSCDR2_LCDIF_CLK_SEL_SHIFT)
+#define CCM_CSCDR2_LCDIF_PRED_SHIFT              (12)      /* Bits 12-14: Pre-divider for lcdif clock */
+#define CCM_CSCDR2_LCDIF_PRED_MASK               (0x7 << CCM_CSCDR2_LCDIF_PRED_SHIFT)
+#  define CCM_CSCDR2_LCDIF_PRED(n)               ((uint32_t)(n) << CCM_CSCDR2_LCDIF_PRED_SHIFT)
+#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT       (15)      /* Bits 15-17: Selector for lcdif root clock pre-multiplexer */
+#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK        (0x7 << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)
+#  define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_(n)       ((uint32_t)(n) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)
+#  define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2      ((uint32_t)(0) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)
+#  define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL3_PFD3 ((uint32_t)(1) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)
+#  define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL5      ((uint32_t)(2) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)
+#  define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD0 ((uint32_t)(3) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)
+#  define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL2_PFD1 ((uint32_t)(4) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)
+#  define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL3_PFD1 ((uint32_t)(5) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)
+#define CCM_CSCDR2_LPI2C_CLK_SEL                 (1 << 18) /* Bit 18:     Selector for the LPI2C clock multiplexer */
+#  define CCM_CSCDR2_LPI2C_CLK_SEL_PLL3_60M      (0 << 18) /*  derive clock from pll3_60m */
+#  define CCM_CSCDR2_LPI2C_CLK_SEL_OSC_CLK       (1 << 18) /*  derive clock from ock_clk */
+#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT          (19)      /* Bits 19-24: Divider for lpi2c clock podf */
+#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK           (0x3f << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)
+#  define CCM_CSCDR2_LPI2C_CLK_PODF(n)           ((uint32_t)(n) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)
+                                                           /* Bits 25-31: Reserved */
+
+/* Serial Clock Divider Register 3 */
+
+                                                           /* Bits 0-8:   Reserved */
+#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT             (9)       /* Bits 9-10:  Selector for csi_mclk multiplexer */
+#define CCM_CSCDR3_CSI_CLK_SEL_MASK              (0x3 << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)
+#  define CCM_CSCDR3_CSI_CLK_SEL(n)              ((uint32_t)(n) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)
+#  define CCM_CSCDR3_CSI_CLK_SEL_OSC_CLK         ((uint32_t)(0) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)
+#  define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL2_PFD2   ((uint32_t)(1) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)
+#  define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL3_120M   ((uint32_t)(2) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)
+#  define CCM_CSCDR3_CSI_CLK_SEL_OSC_PLL3_PFD1   ((uint32_t)(3) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)
+#define CCM_CSCDR3_CSI_PODF_SHIFT                (11)      /* Bits 11-13: Post divider for csi_mclk */
+#define CCM_CSCDR3_CSI_PODF_MASK                 (0x3 << CCM_CSCDR3_CSI_PODF_SHIFT)
+#  define CCM_CSCDR3_CSI_PODF(n)                 ((uint32_t)(n) << CCM_CSCDR3_CSI_PODF_SHIFT)
+
+/* Divider Handshake In-Process Register */
+
+#define CCM_CDHIPR_SEMC_PODF_BUSY                (1 << 0)  /* Bit 0:      Busy indicator for semc_podf */
+#define CCM_CDHIPR_AHB_PODF_BUSY                 (1 << 1)  /* Bit 1:      Busy indicator for ahb_podf */
+                                                           /* Bit 2:      Reserved */
+#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY          (1 << 3)  /* Bit 3:      Busy indicator for periph2_clk_sel mux control */
+                                                           /* Bit 4:      Reserved */
+#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY           (1 << 5)  /* Bit 5:      Busy indicator for periph_clk_sel mux control */
+                                                           /* Bits 6-15:  Reserved */
+#define CCM_CDHIPR_ARM_PODF_BUSY                 (1 << 16) /* Bit 16:     Busy indicator for arm_podf */
+                                                           /* Bits 17-31: Reserved */
+
+/* Low Power Control Register */
+
+#define CCM_CLPCR_LPM_SHIFT                      (0)       /* Bits 0-1:   Setting the low power mode */
+#define CCM_CLPCR_LPM_MASK                       (0x3 << CCM_CLPCR_LPM_SHIFT)
+#  define CCM_CLPCR_LPM(n)                       ((uint32_t)(n) << CCM_CLPCR_LPM_SHIFT)
+#  define CCM_CLPCR_LPM_RUN                      ((uint32_t)(0) << CCM_CLPCR_LPM_SHIFT) /* Remain in run mode */
+#  define CCM_CLPCR_LPM_WAIT                     ((uint32_t)(1) << CCM_CLPCR_LPM_SHIFT) /* Transfer to wait mode */
+#  define CCM_CLPCR_LPM_STOP                     ((uint32_t)(2) << CCM_CLPCR_LPM_SHIFT) /* Transfer to stop mode */
+                                                           /* Bits 2-4:   Reserved */
+#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM             (1 << 5)  /* Bit 5:      ARM clocks disabled on wait mode */
+#define CCM_CLPCR_SBYOS                          (1 << 6)  /* Bit 6:      Standby clock oscillator bit */
+#define CCM_CLPCR_DIS_REF_OSC                    (1 << 7)  /* Bit 7:      external high frequency oscillator disable */
+#define CCM_CLPCR_VSTBY                          (1 << 8)  /* Bit 8:      Voltage standby request bit */
+#define CCM_CLPCR_STBY_COUNT_SHIFT               (9)       /* Bits 9-10:  Standby counter definition */
+#define CCM_CLPCR_STBY_COUNT_MASK                (0x3 << CCM_CLPCR_STBY_COUNT_SHIFT)
+#  define CCM_CLPCR_STBY_COUNT(n)                ((uint32_t)(n) << CCM_CLPCR_STBY_COUNT_SHIFT)
+#define CCM_CLPCR_COSC_PWRDOWN                   (1 << 11) /* Bit 11:     On chip oscillator power down */
+                                                           /* Bits 12-18: Reserved */
+#define CCM_CLPCR_BYPASS_LPM_HS1                 (1 << 19) /* Bit 19:     Bypass low power mode handshake */
+                                                           /* Bit 20:     Reserved */
+#define CCM_CLPCR_BYPASS_LPM_HS0                 (1 << 21) /* Bit 21:     Bypass low power mode handshake */
+#define CCM_CLPCR_MASK_CORE0_WFI                 (1 << 22) /* Bit 22:     Mask WFI of core0 for entering low power mode */
+                                                           /* Bits 23-25: Reserved */
+#define CCM_CLPCR_MASK_SCU_IDLE                  (1 << 26) /* Bit 26:     Mask SCU IDLE for entering low power mode */
+#define CCM_CLPCR_MASK_L2CC_IDLE                 (1 << 27) /* Bit 27:     Mask L2CC IDLE for entering low power mode */
+                                                           /* Bits 28-31: Reserved */
+
+/* Interrupt Status Register */
+
+#define CCM_CISR_LRF_PLL                         (1 << 0)  /* Bit 0:      CCM irq2, lock of all enabled and not bypassed PLLs */
+                                                           /* Bits 1-5:   Reserved */
+#define CCM_CISR_COSC_READY                      (1 << 6)  /* Bit 6:      CCM irq2, on board oscillator ready */
+                                                           /* Bits 7-16:  Reserved */
+#define CCM_CISR_SEMC_PODF_LOADED                (1 << 17) /* Bit 17:     CCM irq1, frequency change of semc_podf */
+                                                           /* Bit 18:     Reserved */
+#define CCM_CISR_PERIPH2_CLK_SEL_LOADED          (1 << 19) /* Bit 19:     CCM irq1, frequency change of periph2_clk_sel */
+#define CCM_CISR_AHB_PODF_LOADED                 (1 << 20) /* Bit 20:     CCM irq1, frequency change of ahb_podf */
+                                                           /* Bit 21:     Reserved */
+#define CCM_CISR_PERIPH_CLK_SEL_LOADED           (1 << 22) /* Bit 22:     CCM irq1, update of periph_clk_sel */
+                                                           /* Bits 23-25: Reserved */
+#define CCM_CISR_ARM_PODF_LOADED                 (1 << 26) /* Bit 26:     CCM irq1, frequency change of arm_podf */
+                                                           /* Bits 27-31: Reserved */
+
+/* Interrupt Mask Register */
+
+#define CCM_CIMR_MASK_LRF_PLL                    (1 << 0)  /* Bit 0:      mask interrupt generation due to lrf of PLLs */
+                                                           /* Bits 1-5:   Reserved */
+#define CCM_CIMR_MASK_COSC_READY                 (1 << 6)  /* Bit 6:      mask interrupt generation due to on board oscillator ready */
+                                                           /* Bits 7-16:  Reserved */
+#define CCM_CIMR_MASK_SEMC_PODF_LOADED           (1 << 17) /* Bit 17:     mask interrupt generation due to frequency change of semc_podf */
+                                                           /* Bit 18:     Reserved */
+#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED     (1 << 19) /* Bit 19:     mask interrupt generation due to update of periph2_clk_sel */
+#define CCM_CIMR_MASK_AHB_PODF_LOADED            (1 << 20) /* Bit 20:     mask interrupt generation due to frequency change of ahb_podf */
+                                                           /* Bit 21:     Reserved */
+#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED      (1 << 22) /* Bit 22:     mask interrupt generation due to update of periph_clk_sel */
+                                                           /* Bits 23-25: Reserved */
+#define CCM_CIMR_MASK_ARM_PODF_LOADED            (1 << 26) /* Bit 26:     mask interrupt generation due to frequency change of arm_podf */
+                                                           /* Bits 27-31: Reserved */
+
+/*  Clock Output Source Register */
+
+#define CCM_CCOSR_CLKO1_SEL_SHIFT                (0)       /* Bits 0-3:   Selection of the clock to be generated on CCM_CLKO1 */
+#define CCM_CCOSR_CLKO1_SEL_MASK                 (0xF << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO1_SEL_SEMC_CLK           ((uint32_t)(5) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO1_SEL_ENC_CLK            ((uint32_t)(6) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO1_SEL_LCDIF_PIX_CLK      ((uint32_t)(10) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO1_SEL_AHB_CLK            ((uint32_t)(11) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO1_SEL_IPG_CLK            ((uint32_t)(12) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO1_SEL_PER_CLK            ((uint32_t)(13) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO1_SEL_CKIL_SYNC_CLK      ((uint32_t)(14) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO1_SEL_PLL4_MAIN_CLK      ((uint32_t)(15) << CCM_CCOSR_CLKO1_SEL_SHIFT)
+#define CCM_CCOSR_CLKO1_DIV_SHIFT                (4)       /* Bits 4-6:   Setting the divider of CCM_CLKO1 */
+#define CCM_CCOSR_CLKO1_DIV_MASK                 (0x7 << CCM_CCOSR_CLKO1_DIV_SHIFT)
+#  define CCM_CCOSR_CLKO1_DIV(n)                 ((uint32_t)(n) << CCM_CCOSR_CLKO1_DIV_SHIFT)
+#define CCM_CCOSR_CLKO1_EN                       (1 << 7)  /* Bit 7:      Enable of CCM_CLKO1 clock */
+#define CCM_CCOSR_CLK_OUT_SEL                    (1 << 8)  /* Bit 8:      CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks */
+                                                           /* Bits 9-15:  Reserved */
+#define CCM_CCOSR_CLKO2_SEL_SHIFT                (16)      /* Bits 16-20: Selection of the clock to be generated on CCM_CLKO2 */
+#define CCM_CCOSR_CLKO2_SEL_MASK                 (0x1F << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_USDHC1_CLK         ((uint32_t)(3) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_WRCK_CLK           ((uint32_t)(5) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_LPI2C_CLK          ((uint32_t)(6) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_CSI_CORE           ((uint32_t)(11) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_OSC_CLK            ((uint32_t)(14) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_USDHC2_CLK         ((uint32_t)(17) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_SAI1_CLK           ((uint32_t)(18) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_SAI2_CLK           ((uint32_t)(19) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_SAI3_CLK           ((uint32_t)(20) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_CAN_CLK            ((uint32_t)(23) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_FLEXSPI_CLK        ((uint32_t)(27) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_UART_CLK           ((uint32_t)(28) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#  define CCM_CCOSR_CLKO2_SEL_SPDIF0_CLK         ((uint32_t)(29) << CCM_CCOSR_CLKO2_SEL_SHIFT)
+#define CCM_CCOSR_CLKO2_DIV_SHIFT                (21)      /* Bits 21-23: Setting the divider of CCM_CLKO2 */
+#define CCM_CCOSR_CLKO2_DIV_MASK                 (0x7 << CCM_CCOSR_CLKO2_DIV_SHIFT)
+#  define CCM_CCOSR_CLKO2_DIV(n)                 ((uint32_t)(n) << CCM_CCOSR_CLKO2_DIV_SHIFT)
+#define CCM_CCOSR_CLKO2_EN                       (1 << 24) /* Bit 24:     Enable of CCM_CLKO2 clock */
+                                                           /* Bits 25-31: Reserved */
+
+/* General Purpose Register */
+
+#define CCM_CGPR_PMIC_DELAY_SCALER               (1 << 0)  /* Bit 0:      Defines clock division of clock for stby_count */
+                                                           /* Bits 1-3:   Reserved */
+#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE          (1 << 4)  /* Bit 4:      allow fuse programing */
+                                                           /* Bits 5-13:  Reserved */
+#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT           (14)      /* Bits 14-15: System memory DS control */
+#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK            (0x7 << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)
+#  define CCM_CGPR_SYS_MEM_DS_CTRL(n)            ((uint32_t)(n) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)
+#define CCM_CGPR_FPL                             (1 << 16) /* Bit 16:     Fast PLL enable */
+#define CCM_CGPR_INT_MEM_CLK_LPM                 (1 << 17) /* Bit 17:     Control for the Deep Sleep signal to the ARM Platform memories */
+                                                           /* Bits 18-31: Reserved */
+
+/* Clock Gating Register 0-6 */
+
+#define CCM_CG_OFF                               (0)  /* Clock is off during all modes */
+#define CCM_CG_RUN                               (1)  /* Clock is on in run mode, but off in WAIT and STOP modes */
+#define CCM_CG_ALL                               (3)  /* Clock is on during all modes, except STOP mode. */
+
+#define CCM_CCGRX_CG_SHIFT(r)                    ((r) << 1)
+#define CCM_CCGRX_CG_MASK(r)                     (0x3 << CCM_CCGRX_CG_SHIFT(r))
+#  define CCM_CCGRX_CG(r,v)                      ((uint32_t)(v) << CCM_CCGRX_CG_SHIFT(r))
+
+#define CCM_CCGRX_CG0_SHIFT                      (0)
+#define CCM_CCGRX_CG0_MASK                       (0x3 << CCM_CCGRX_CG0_SHIFT)
+#  define CCM_CCGRX_CG0(n)                       ((uint32_t)(n) << CCM_CCGRX_CG0_SHIFT)
+#define CCM_CCGRX_CG1_SHIFT                      (2)
+#define CCM_CCGRX_CG1_MASK                       (0x3 << CCM_CCGRX_CG1_SHIFT)
+#  define CCM_CCGRX_CG1(n)                       ((uint32_t)(n) << CCM_CCGRX_CG1_SHIFT)
+#define CCM_CCGRX_CG2_SHIFT                      (4)
+#define CCM_CCGRX_CG2_MASK                       (0x3 << CCM_CCGRX_CG2_SHIFT)
+#  define CCM_CCGRX_CG2(n)                       ((uint32_t)(n) << CCM_CCGRX_CG2_SHIFT)
+#define CCM_CCGRX_CG3_SHIFT                      (6)
+#define CCM_CCGRX_CG3_MASK                       (0x3 << CCM_CCGRX_CG3_SHIFT)
+#  define CCM_CCGRX_CG3(n)                       ((uint32_t)(n) << CCM_CCGRX_CG3_SHIFT)
+#define CCM_CCGRX_CG4_SHIFT                      (8)
+#define CCM_CCGRX_CG4_MASK                       (0x3 << CCM_CCGRX_CG4_SHIFT)
+#  define CCM_CCGRX_CG4(n)                       ((uint32_t)(n) << CCM_CCGRX_CG4_SHIFT)
+#define CCM_CCGRX_CG5_SHIFT                      (10)
+#define CCM_CCGRX_CG5_MASK                       (0x3 << CCM_CCGRX_CG5_SHIFT)
+#  define CCM_CCGRX_CG5(n)                       ((uint32_t)(n) << CCM_CCGRX_CG5_SHIFT)
+#define CCM_CCGRX_CG6_SHIFT                      (12)
+#define CCM_CCGRX_CG6_MASK                       (0x3 << CCM_CCGRX_CG6_SHIFT)
+#  define CCM_CCGRX_CG6(n)                       ((uint32_t)(n) << CCM_CCGRX_CG6_SHIFT)
+#define CCM_CCGRX_CG7_SHIFT                      (14)
+#define CCM_CCGRX_CG7_MASK                       (0x3 << CCM_CCGRX_CG7_SHIFT)
+#  define CCM_CCGRX_CG7(n)                       ((uint32_t)(n) << CCM_CCGRX_CG7_SHIFT)
+#define CCM_CCGRX_CG8_SHIFT                      (16)
+#define CCM_CCGRX_CG8_MASK                       (0x3 << CCM_CCGRX_CG8_SHIFT)
+#  define CCM_CCGRX_CG8(n)                       ((uint32_t)(n) << CCM_CCGRX_CG8_SHIFT)
+#define CCM_CCGRX_CG9_SHIFT                      (18)
+#define CCM_CCGRX_CG9_MASK                       (0x3 << CCM_CCGRX_CG9_SHIFT)
+#  define CCM_CCGRX_CG9(n)                       ((uint32_t)(n) << CCM_CCGRX_CG9_SHIFT)
+#define CCM_CCGRX_CG10_SHIFT                     (20)
+#define CCM_CCGRX_CG10_MASK                      (0x3 << CCM_CCGRX_CG10_SHIFT)
+#  define CCM_CCGRX_CG10(n)                      ((uint32_t)(n) << CCM_CCGRX_CG10_SHIFT)
+#define CCM_CCGRX_CG11_SHIFT                     (22)
+#define CCM_CCGRX_CG11_MASK                      (0x3 << CCM_CCGRX_CG11_SHIFT)
+#  define CCM_CCGRX_CG11(n)                      ((uint32_t)(n) << CCM_CCGRX_CG11_SHIFT)
+#define CCM_CCGRX_CG12_SHIFT                     (24)
+#define CCM_CCGRX_CG12_MASK                      (0x3 << CCM_CCGRX_CG12_SHIFT)
+#  define CCM_CCGRX_CG12(n)                      ((uint32_t)(n) << CCM_CCGRX_CG12_SHIFT)
+#define CCM_CCGRX_CG13_SHIFT                     (26)
+#define CCM_CCGRX_CG13_MASK                      (0x3 << CCM_CCGRX_CG13_SHIFT)
+#  define CCM_CCGRX_CG13(n)                      ((uint32_t)(n) << CCM_CCGRX_CG13_SHIFT)
+#define CCM_CCGRX_CG14_SHIFT                     (28)
+#define CCM_CCGRX_CG14_MASK                      (0x3 << CCM_CCGRX_CG14_SHIFT)
+#  define CCM_CCGRX_CG14(n)                      ((uint32_t)(n) << CCM_CCGRX_CG14_SHIFT)
+#define CCM_CCGRX_CG15_SHIFT                     (30)
+#define CCM_CCGRX_CG15_MASK                      (0x3 << CCM_CCGRX_CG15_SHIFT)
+#  define CCM_CCGRX_CG15(n)                      ((uint32_t)(n) << CCM_CCGRX_CG15_SHIFT)
+
+/* Macros used by imxrt_periphclks.h */
+
+#define CCM_CCGR_GPIO2                           IMXRT_CCM_CCGR0, 15
+#define CCM_CCGR_LPUART2                         IMXRT_CCM_CCGR0, 14
+#define CCM_CCGR_GPT2_SERIAL                     IMXRT_CCM_CCGR0, 13
+#define CCM_CCGR_GPT2_BUS                        IMXRT_CCM_CCGR0, 12
+#define CCM_CCGR_TRACE                           IMXRT_CCM_CCGR0, 11
+#define CCM_CCGR_CAN2_SERIAL                     IMXRT_CCM_CCGR0, 10
+#define CCM_CCGR_CAN2                            IMXRT_CCM_CCGR0, 9
+#define CCM_CCGR_CAN1_SERIAL                     IMXRT_CCM_CCGR0, 8
+#define CCM_CCGR_CAN1                            IMXRT_CCM_CCGR0, 7
+#define CCM_CCGR_LPUART3                         IMXRT_CCM_CCGR0, 6
+#define CCM_CCGR_DCP                             IMXRT_CCM_CCGR0, 5
+#define CCM_CCGR_MQS                             IMXRT_CCM_CCGR0, 2
+#define CCM_CCGR_AIPS_TZ2                        IMXRT_CCM_CCGR0, 1
+#define CCM_CCGR_AIPS_TZ1                        IMXRT_CCM_CCGR0, 0
+
+#define CCM_CCGR_CSU                             IMXRT_CCM_CCGR1, 14
+#define CCM_CCGR_GPIO1                           IMXRT_CCM_CCGR1, 13
+#define CCM_CCGR_LPUART4                         IMXRT_CCM_CCGR1, 12
+#define CCM_CCGR_GPT_SERIAL                      IMXRT_CCM_CCGR1, 11
+#define CCM_CCGR_GPT_BUS                         IMXRT_CCM_CCGR1, 10
+#define CCM_CCGR_ADC1                            IMXRT_CCM_CCGR1, 8
+#define CCM_CCGR_AOI2                            IMXRT_CCM_CCGR1, 7
+#define CCM_CCGR_PIT                             IMXRT_CCM_CCGR1, 6
+#define CCM_CCGR_ENET                            IMXRT_CCM_CCGR1, 5
+#define CCM_CCGR_ADC2                            IMXRT_CCM_CCGR1, 4
+#define CCM_CCGR_LPSPI4                          IMXRT_CCM_CCGR1, 3
+#define CCM_CCGR_LPSPI3                          IMXRT_CCM_CCGR1, 2
+#define CCM_CCGR_LPSPI2                          IMXRT_CCM_CCGR1, 1
+#define CCM_CCGR_LPSPI1                          IMXRT_CCM_CCGR1, 0
+
+#define CCM_CCGR_PXP                             IMXRT_CCM_CCGR2, 15
+#define CCM_CCGR_LCD                             IMXRT_CCM_CCGR2, 14
+#define CCM_CCGR_GPIO3                           IMXRT_CCM_CCGR2, 13
+#define CCM_CCGR_XBAR2                           IMXRT_CCM_CCGR2, 12
+#define CCM_CCGR_XBAR1                           IMXRT_CCM_CCGR2, 11
+#define CCM_CCGR_IPMUX3                          IMXRT_CCM_CCGR2, 10
+#define CCM_CCGR_IPMUX2                          IMXRT_CCM_CCGR2, 9
+#define CCM_CCGR_IPMUX1                          IMXRT_CCM_CCGR2, 8
+#define CCM_CCGR_XBAR3                           IMXRT_CCM_CCGR2, 7
+#define CCM_CCGR_OCOTP_CTRL                      IMXRT_CCM_CCGR2, 6
+#define CCM_CCGR_LPI2C3                          IMXRT_CCM_CCGR2, 5
+#define CCM_CCGR_LPI2C2                          IMXRT_CCM_CCGR2, 4
+#define CCM_CCGR_LPI2C1                          IMXRT_CCM_CCGR2, 3
+#define CCM_CCGR_IOMUXC_SNVS                     IMXRT_CCM_CCGR2, 2
+#define CCM_CCGR_CSI                             IMXRT_CCM_CCGR2, 1
+
+#define CCM_CCGR_IOMUXC_SNVS_GPR                 IMXRT_CCM_CCGR3, 15
+#define CCM_CCGR_OCRAM                           IMXRT_CCM_CCGR3, 14
+#define CCM_CCGR_ACMP4                           IMXRT_CCM_CCGR3, 13
+#define CCM_CCGR_ACMP3                           IMXRT_CCM_CCGR3, 12
+#define CCM_CCGR_ACMP2                           IMXRT_CCM_CCGR3, 11
+#define CCM_CCGR_ACMP1                           IMXRT_CCM_CCGR3, 10
+#define CCM_CCGR_FLEXRAM                         IMXRT_CCM_CCGR3, 9
+#define CCM_CCGR_WDOG1                           IMXRT_CCM_CCGR3, 8
+#define CCM_CCGR_EWM                             IMXRT_CCM_CCGR3, 7
+#define CCM_CCGR_GPIO4                           IMXRT_CCM_CCGR3, 6
+#define CCM_CCGR_LCDIF_PIX                       IMXRT_CCM_CCGR3, 5
+#define CCM_CCGR_AOI1                            IMXRT_CCM_CCGR3, 4
+#define CCM_CCGR_LPUART6                         IMXRT_CCM_CCGR3, 3
+#define CCM_CCGR_SEMC                            IMXRT_CCM_CCGR3, 2
+#define CCM_CCGR_LPUART5                         IMXRT_CCM_CCGR3, 1
+#define CCM_CCGR_FLEXIO2                         IMXRT_CCM_CCGR3, 0
+
+#define CCM_CCGR_ENC4                            IMXRT_CCM_CCGR4, 15
+#define CCM_CCGR_ENC3                            IMXRT_CCM_CCGR4, 14
+#define CCM_CCGR_ENC2                            IMXRT_CCM_CCGR4, 13
+#define CCM_CCGR_ENC1                            IMXRT_CCM_CCGR4, 12
+#define CCM_CCGR_PWM4                            IMXRT_CCM_CCGR4, 11
+#define CCM_CCGR_PWM3                            IMXRT_CCM_CCGR4, 10
+#define CCM_CCGR_PWM2                            IMXRT_CCM_CCGR4, 9
+#define CCM_CCGR_PWM1                            IMXRT_CCM_CCGR4, 8
+#define CCM_CCGR_SIM_EMS                         IMXRT_CCM_CCGR4, 7
+#define CCM_CCGR_SIM_M                           IMXRT_CCM_CCGR4, 6
+#define CCM_CCGR_TSC_DIG                         IMXRT_CCM_CCGR4, 5
+#define CCM_CCGR_SIM_M7                          IMXRT_CCM_CCGR4, 4
+#define CCM_CCGR_BEE                             IMXRT_CCM_CCGR4, 3
+#define CCM_CCGR_IOMUXC_GPR                      IMXRT_CCM_CCGR4, 2
+#define CCM_CCGR_IOMUXC                          IMXRT_CCM_CCGR4, 1
+
+#define CCM_CCGR_SNVS_LP                         IMXRT_CCM_CCGR5, 15
+#define CCM_CCGR_SNVS_HP                         IMXRT_CCM_CCGR5, 14
+#define CCM_CCGR_LPUART7                         IMXRT_CCM_CCGR5, 13
+#define CCM_CCGR_LPUART1                         IMXRT_CCM_CCGR5, 12
+#define CCM_CCGR_SAI3                            IMXRT_CCM_CCGR5, 11
+#define CCM_CCGR_SAI2                            IMXRT_CCM_CCGR5, 10
+#define CCM_CCGR_SAI1                            IMXRT_CCM_CCGR5, 9
+#define CCM_CCGR_SIM_MAIN                        IMXRT_CCM_CCGR5, 8
+#define CCM_CCGR_SPDIF                           IMXRT_CCM_CCGR5, 7
+#define CCM_CCGR_AIPSTZ4                         IMXRT_CCM_CCGR5, 6
+#define CCM_CCGR_WDOG2                           IMXRT_CCM_CCGR5, 5
+#define CCM_CCGR_KPP                             IMXRT_CCM_CCGR5, 4
+#define CCM_CCGR_DMA                             IMXRT_CCM_CCGR5, 3
+#define CCM_CCGR_WDOG3                           IMXRT_CCM_CCGR5, 2
+#define CCM_CCGR_FLEXIO1                         IMXRT_CCM_CCGR5, 1
+#define CCM_CCGR_ROM                             IMXRT_CCM_CCGR5, 0
+
+#define CCM_CCGR_TIMER3                          IMXRT_CCM_CCGR6, 15
+#define CCM_CCGR_TIMER2                          IMXRT_CCM_CCGR6, 14
+#define CCM_CCGR_TIMER1                          IMXRT_CCM_CCGR6, 13
+#define CCM_CCGR_LPI2C4_SERIAL                   IMXRT_CCM_CCGR6, 12
+#define CCM_CCGR_ANADIG                          IMXRT_CCM_CCGR6, 11
+#define CCM_CCGR_SIM_PER                         IMXRT_CCM_CCGR6, 10
+#define CCM_CCGR_AIPS_TZ3                        IMXRT_CCM_CCGR6, 9
+#define CCM_CCGR_TIMER4                          IMXRT_CCM_CCGR6, 8
+#define CCM_CCGR_LPUART8                         IMXRT_CCM_CCGR6, 7
+#define CCM_CCGR_TRNG                            IMXRT_CCM_CCGR6, 6
+#define CCM_CCGR_FLEXSPI                         IMXRT_CCM_CCGR6, 5
+#define CCM_CCGR_IPMUX4                          IMXRT_CCM_CCGR6, 4
+#define CCM_CCGR_DCDC                            IMXRT_CCM_CCGR6, 3
+#define CCM_CCGR_USDHC2                          IMXRT_CCM_CCGR6, 2
+#define CCM_CCGR_USDHC1                          IMXRT_CCM_CCGR6, 1
+#define CCM_CCGR_USBOH3                          IMXRT_CCM_CCGR6, 0
+
+/* Module Enable Override Register */
+
+                                                           /* Bits 0-4: Reserved */
+#define CCM_CMEOR_MOD_EN_OV_GPT                  (1 << 5)  /* Bit 5:      Overide clock enable signal from GPT */
+#define CCM_CMEOR_MOD_EN_OV_PIT                  (1 << 6)  /* Bit 6:      Overide clock enable signal from PIT */
+#define CCM_CMEOR_MOD_EN_OV_USDHC                (1 << 7)  /* Bit 7:      Overide clock enable signal from USDHC */
+#define CCM_CMEOR_MOD_EN_OV_TRNG                 (1 << 9)  /* Bit 9:      Overide clock enable signal from TRNG */
+                                                           /* Bits 10-27: Reserved */
+#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI             (1 << 28) /* Bit 28:     Overide clock enable signal from CAN2 */
+#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI             (1 << 30) /* Bit 30:     Overide clock enable signal from CAN1 */
+                                                           /* Bit 31:     Reserved */
+
+/* Analog ARM PLL control Register */
+
+#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT             (0)       /* Bits 0-6:   This field controls the PLL loop divider 54-108 */
+#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK              (0x7f << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ARM_DIV_SELECT(n)              ((uint32_t)(n) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)
+                                                                  /* Bits 7-11   Reserved */
+#define CCM_ANALOG_PLL_ARM_POWERDOWN                    (1 << 12) /* Bit 12:     Powers down the PLL */
+#define CCM_ANALOG_PLL_ARM_ENABLE                       (1 << 13) /* Bit 13:     Enable the clock output */
+#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT         (14)      /* Bits 14-15: Determines the bypass source */
+#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK          (0x3 << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)
+#  define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_REF_24M     ((uint32_t)(0) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
+#  define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_CLK1        ((uint32_t)(1) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */
+#define CCM_ANALOG_PLL_ARM_BYPASS                       (1 << 16) /* Bit 16:     Bypass the PLL */
+                                                                  /* Bits 17-18  Reserved */
+#define CCM_ANALOG_PLL_ARM_PLL_SEL                      (1 << 39) /* Bit 19:     ? */
+#define CCM_ANALOG_PLL_ARM_LOCK                         (1 << 31) /* Bit 31:     PLL is currently locked */
+
+/* Analog USB1 480MHz PLL Control Register */
+
+#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT            (1)       /* Bits 0-1:   This field controls the PLL loop divider 20 or 22 */
+#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK             (0x1 << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_USB1_DIV_SELECT_20             ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_USB1_DIV_SELECT_22             ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)
+                                                                  /* Bits 2-5    Reserved */
+#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS                 (1 << 6)  /* Bit 6:      Enable PLL outputs for USBPHYn */
+#define CCM_ANALOG_PLL_USB1_POWER                       (1 << 12) /* Bit 12:     Powers up the PLL */
+#define CCM_ANALOG_PLL_USB1_ENABLE                      (1 << 13) /* Bit 13:     Enable the PLL clock output */
+#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT        (14)      /* Bits 14-15: Determines the bypass source */
+#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK         (0x3 << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)
+#  define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_REF_24M    ((uint32_t)(0) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
+#  define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CLK1       ((uint32_t)(1) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */
+#  define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_GPANAIO    ((uint32_t)(2) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /*  */
+#  define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_CHRG_DET_B ((uint32_t)(3) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) /*  */
+#define CCM_ANALOG_PLL_USB1_BYPASS                      (1 << 16) /* Bit 16:     Bypass the PLL */
+                                                                  /* Bits 17-30  Reserved */
+#define CCM_ANALOG_PLL_USB1_LOCK                        (1 << 31) /* Bit 31:     PLL is currently locked */
+
+/* Analog USB2 480MHz PLL Control Register */
+
+#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT            (0)       /* Bits 0-1:   This field controls the PLL loop divider 20 or 22 */
+#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK             (0x3 << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_USB2_DIV_SELECT_20             ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_USB2_DIV_SELECT_22             ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)
+                                                                  /* Bits 2-5    Reserved */
+#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS                 (1 << 6)  /* Bit 6:      Enable PLL outputs for USBPHYn */
+#define CCM_ANALOG_PLL_USB2_POWER                       (1 << 12) /* Bit 12:     Powers up the PLL */
+#define CCM_ANALOG_PLL_USB2_ENABLE                      (1 << 13) /* Bit 13:     Enable the PLL clock output */
+#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT        (14)      /* Bits 14-15: Determines the bypass source */
+#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK         (0x3 << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)
+#  define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_REF_24M    ((uint32_t)(0) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
+#  define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_CLK1       ((uint32_t)(1) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */
+#define CCM_ANALOG_PLL_USB2_BYPASS                      (1 << 16) /* Bit 16:     Bypass the PLL */
+                                                                  /* Bits 17-30  Reserved */
+#define CCM_ANALOG_PLL_USB2_LOCK                        (1 << 31) /* Bit 31:     PLL is currently locked */
+
+/*  Analog System PLL Control Register */
+
+#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT             (0)       /* Bits 0-1:   This field controls the PLL loop divider 20 or 22 */
+#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK              (0x3 << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_SYS_DIV_SELECT(n)              ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_SYS_DIV_SELECT_20              (0)
+#  define CCM_ANALOG_PLL_SYS_DIV_SELECT_22              (1)
+#define CCM_ANALOG_PLL_SYS_POWERDOWN                    (1 << 12) /* Bit 12:     Powers down the PLL */
+#define CCM_ANALOG_PLL_SYS_ENABLE                       (1 << 13) /* Bit 13:     Enable the PLL clock output */
+#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT         (14)      /* Bits 14-15: Determines the bypass source */
+#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK          (0x3 << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)
+#  define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_REF_24M     ((uint32_t)(0) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
+#  define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CLK1        ((uint32_t)(1) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */
+#  define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_GPANAIO     ((uint32_t)(2) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /*  */
+#  define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_CHRG_DET_B  ((uint32_t)(3) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) /*  */
+#define CCM_ANALOG_PLL_SYS_BYPASS                       (1 << 16) /* Bit 16:     Bypass the PLL */
+                                                                  /* Bit 17:     Reserved */
+#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN                (1 << 18) /* Bit 18:     Enables an offset in the phase frequency detector */
+                                                                  /* Bits 19-30  Reserved */
+#define CCM_ANALOG_PLL_SYS_LOCK                         (1 << 31) /* Bit 31:     PLL is currently locked */
+
+/* 528MHz System PLL Spread Spectrum Register */
+
+#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT                (0)       /* Bits 0-14:  Frequency change step */
+#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK                 (0x3FFF << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)
+#  define CCM_ANALOG_PLL_SYS_SS_STEP(n)                 ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)
+#define CCM_ANALOG_PLL_SYS_SS_ENABLE                    (1 << 15) /* Bit 15:  Enable bit */
+#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT                (0)       /* Bits 16-31:  Frequency change */
+#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK                 (0xFFFF << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)
+#  define CCM_ANALOG_PLL_SYS_SS_STOP(n)                 ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)
+
+/* Numerator of 528MHz System PLL Fractional Loop Divider Register */
+
+#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT                  (0)       /* Bits 0-29:   30 bit numerator (A) */
+#define CCM_ANALOG_PLL_SYS_NUM_A_MASK                   (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)
+#define CCM_ANALOG_PLL_SYS_NUM_A(n)                     ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)
+                                                                  /* Bits 30-31:  Reserved */
+
+/* Denominator of 528MHz System PLL Fractional Loop Divider Register */
+
+#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT                (0)       /* Bits 0-29:   30 bit numerator (A) */
+#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK                 (0x3FFFFFFF << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)
+#define CCM_ANALOG_PLL_SYS_DENOM_B(n)                   ((uint32_t)(n) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)
+                                                                  /* Bits 30-31:  Reserved */
+
+/*  Analog Audio PLL control Register */
+
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT           (0)       /* Bits 0-6:    This field controls the PLL loop divider: 27-54 */
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK            (0x7f << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(n)            ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)
+                                                                  /* Bits 7-11:  Reserved */
+#define CCM_ANALOG_PLL_AUDIO_POWERDOWN                  (1 << 12) /* Bit 12:     Powers down the PLL */
+#define CCM_ANALOG_PLL_AUDIO_ENABLE                     (1 << 13) /* Bit 13:     Enable PLL output */
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT       (14)      /* Bits 14-15: Determines the bypass source */
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK        (0x3 << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)
+#  define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_REF_24M   ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
+#  define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_CLK1      ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */
+#define CCM_ANALOG_PLL_AUDIO_BYPASS                     (1 << 16) /* Bit 16:     Bypass the PLL */
+                                                                  /* Bit 17:     Reserved */
+#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN              (1 << 18) /* Bit 18:     Enables an offset in the phase frequency detector */
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT      (19)      /* Bits 19-20: These bits implement a divider after the PLL */
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK       (0x7f << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV4     ((uint32_t)(0) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV2     ((uint32_t)(1) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV1     ((uint32_t)(2) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)
+                                                                  /* Bits 21-30:  Reserved */
+#define CCM_ANALOG_PLL_AUDIO_LOCK                       (1 << 31) /* Bit 31:     PLL is currently locked */
+
+/* Numerator of Audio PLL Fractional Loop Divider Register */
+
+#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT                (0)       /* Bits 0-29:   30 bit numerator (A) */
+#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK                 (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)
+#define CCM_ANALOG_PLL_AUDIO_NUM_A(n)                   ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)
+/* Bits 30-31:  Reserved */
+
+/* Denominator of Audio PLL Fractional Loop Divider Register */
+
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT              (0)       /* Bits 0-29:   30 bit numerator (A) */
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK               (0x3FFFFFFF << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B(n)                 ((uint32_t)(n) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)
+                                                                    /* Bits 30-31:  Reserved */
+/*  Analog Video PLL control Register */
+
+#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT           (0)       /* Bits 0-6:    This field controls the PLL loop divider: 27-54 */
+#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK            (0x7f << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(n)            ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)
+                                                                  /* Bits 7-11:  Reserved */
+#define CCM_ANALOG_PLL_VIDEO_POWERDOWN                  (1 << 12) /* Bit 12:     Powers down the PLL */
+#define CCM_ANALOG_PLL_VIDEO_ENABLE                     (1 << 13) /* Bit 13:     Enable PLL output */
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT       (14)      /* Bits 14-15: Determines the bypass source */
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK        (0x3 << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)
+#  define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_REF_24M   ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
+#  define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_CLK1      ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */
+#define CCM_ANALOG_PLL_VIDEO_BYPASS                     (1 << 16) /* Bit 16:     Bypass the PLL */
+                                                                  /* Bit 17:     Reserved */
+#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN              (1 << 18) /* Bit 18:     Enables an offset in the phase frequency detector */
+#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT      (19)      /* Bits 19-20: These bits implement a divider after the PLL */
+#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK       (0x7f << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV4     ((uint32_t)(0) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2     ((uint32_t)(1) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1     ((uint32_t)(2) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)
+                                                                  /* Bits 21-30:  Reserved */
+#define CCM_ANALOG_PLL_VIDEO_LOCK                       (1 << 31) /* Bit 31:     PLL is currently locked */
+
+/* Numerator of Video PLL Fractional Loop Divider Register */
+
+#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT                (0)       /* Bits 0-29:   30 bit numerator (A) */
+#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK                 (0x3FFFFFFF << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)
+#define CCM_ANALOG_PLL_VIDEO_NUM_A(n)                   ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)
+                                                                  /* Bits 30-31:  Reserved */
+
+/* Denominator of Video PLL Fractional Loop Divider Register */
+
+#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT              (0)       /* Bits 0-29:   30 bit numerator (A) */
+#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK               (0x3FFFFFFF << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)
+#define CCM_ANALOG_PLL_VIDEO_DENOM_B(n)                 ((uint32_t)(n) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)
+                                                                  /* Bits 30-31:  Reserved */
+
+/* Analog ENET PLL Control Register */
+
+#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT      (0)       /* Bits 0-1:    Controls the frequency of the ethernet0 reference clock */
+#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK       (0x3 << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_25MHZ    ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ    ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_100MHZ   ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_125MHZ   ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)
+#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT      (2)       /* Bits 0-1:    Controls the frequency of the ethernet1 reference clock */
+#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK       (0x3 << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_25MHZ    ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ    ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_100MHZ   ((uint32_t)(2) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_125MHZ   ((uint32_t)(3) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)
+                                                                  /* Bits 4-11:  Reserved */
+#define CCM_ANALOG_PLL_ENET_POWERDOWN                   (1 << 12) /* Bit 12:     Powers down the PLL */
+#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN               (1 << 13) /* Bit 13:     Enable the PLL providing the ENET1 125 MHz reference clock */
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT       (14)      /* Bits 14-15: Determines the bypass source */
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK        (0x3 << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)
+#  define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M   ((uint32_t)(0) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select 24Mhz Osc as source */
+#  define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_CLK1      ((uint32_t)(1) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT) /* Select the CLK1_N / CLK1_P as source */
+#define CCM_ANALOG_PLL_ENET_BYPASS                     (1 << 16) /* Bit 16:     Bypass the PLL */
+                                                                 /* Bit 17:     Reserved */
+#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN              (1 << 18) /* Bit 18:     Enables an offset in the phase frequency detector */
+#define CCM_ANALOG_PLL_ENET_ENABLE_125M                (1 << 19) /* Bit 19:     */
+#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN              (1 << 20) /* Bit 20:     Enable the PLL providing the ENET2 125 MHz reference clock */
+#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN            (1 << 21) /* Bit 21:     Enable the PLL providing ENET 25 MHz reference clock */
+#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN           (1 << 22) /* Bit 22:     Enable the PLL providing NET 500 MHz reference clock */
+
+#define CCM_ANALOG_PLL_ENET_LOCK                       (1 << 31) /* Bit 31:     PLL is currently locked */
+
+/* 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
+
+#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT             (0)       /* Bits 0-5:   This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_480_PFD0_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_480_PFD0_STABLE                 (6)       /* Bit 6:      */
+#define CCM_ANALOG_PFD_480_PFD0_CLKGATE                (7)       /* Bit 7:      If set to 1, the IO fractional divider clock is off */
+#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT             (8)       /* Bits 8-13:  This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_480_PFD1_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_480_PFD1_STABLE                 (14)      /* Bit 14:     */
+#define CCM_ANALOG_PFD_480_PFD1_CLKGATE                (15)      /* Bit 15:     If set to 1, the IO fractional divider clock is off */
+#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT             (16)      /* Bits 8-21:  This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_480_PFD2_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_480_PFD2_STABLE                 (22)      /* Bit 22:     */
+#define CCM_ANALOG_PFD_480_PFD2_CLKGATE                (23)      /* Bit 23:     If set to 1, the IO fractional divider clock is off */
+#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT             (24)      /* Bits 24-29:  This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_480_PFD3_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_480_PFD3_STABLE                 (30)      /* Bit 30:     */
+#define CCM_ANALOG_PFD_480_PFD3_CLKGATE                (31)      /* Bit 31:     If set to 1, the IO fractional divider clock is off */
+
+/* 528MHz Clock (PLL2) Phase Fractional Divider Control */
+
+#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT             (0)       /* Bits 0-5:   This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_528_PFD0_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_528_PFD0_STABLE                 (6)       /* Bit 6:      */
+#define CCM_ANALOG_PFD_528_PFD0_CLKGATE                (7)       /* Bit 7:      If set to 1, the IO fractional divider clock is off */
+#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT             (8)       /* Bits 8-13:  This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_528_PFD1_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_481_PFD1_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_528_PFD1_STABLE                 (14)      /* Bit 14:     */
+#define CCM_ANALOG_PFD_528_PFD1_CLKGATE                (15)      /* Bit 15:     If set to 1, the IO fractional divider clock is off */
+#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT             (16)      /* Bits 8-21:  This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_528_PFD2_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD2_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_528_PFD2_STABLE                 (22)      /* Bit 22:     */
+#define CCM_ANALOG_PFD_528_PFD2_CLKGATE                (23)      /* Bit 23:     If set to 1, the IO fractional divider clock is off */
+#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT             (24)      /* Bits 24-29:  This field controls the fractional divide value */
+#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK              (0x3f << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)
+#  define CCM_ANALOG_PFD_528_PFD3_FRAC(n)              ((uint32_t)(n) << CCM_ANALOG_PFD_482_PFD3_FRAC_SHIFT)
+#define CCM_ANALOG_PFD_528_PFD3_STABLE                 (30)      /* Bit 30:     */
+#define CCM_ANALOG_PFD_528_PFD3_CLKGATE                (31)      /* Bit 31:     If set to 1, the IO fractional divider clock is off */
+
+/* Miscellaneous Register 0 */
+
+#define CCM_ANALOG_MISC0_REFTOP_PWD                    (1 << 0)  /* Bit 0:      Control bit to power-down the analog bandgap reference circuitry */
+                                                                 /* Bits 1-2:   Reserved */
+#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF            (1 << 2)  /* Bit 3:      Control bit to disable the self-bias circuit in the analog bandgap */
+#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT           (4)       /* Bits 4-6:   VBG (PMU) */
+#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK            (0x3 << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)
+#  define CCM_ANALOG_MISC0_REFTOP_VBGADJ(n)            ((uint32_t)(n) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)
+#define CCM_ANALOG_MISC0_REFTOP_VBGUP                  (1 << 7)  /* Bit 7:      Status bit that signals the analog bandgap voltage is up and stable */
+                                                                 /* Bits 8-9:   Reserved */
+#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT        (10)      /* Bits 10-11: Configure the analog behavior in stop mode */
+#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK         (0x3 << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)
+#  define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(n)         ((uint32_t)(n) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)
+#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS              (1 << 12) /* Bit 12:     This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN */
+#define CCM_ANALOG_MISC0_OSC_I_SHIFT                   (13)      /* Bits 13-14: This field determines the bias current in the 24MHz oscillator */
+#define CCM_ANALOG_MISC0_OSC_I_MASK                    (0x3 << CCM_ANALOG_MISC0_OSC_I_SHIFT)
+#  define CCM_ANALOG_MISC0_OSC_I(n)                    ((uint32_t)(n) << CCM_ANALOG_MISC0_OSC_I_SHIFT)
+#define CCM_ANALOG_MISC0_OSC_XTALOK                    (1 << 15) /* Bit 15:     bit that signals 24-MHz crystal oscillator is stable */
+#define CCM_ANALOG_MISC0_OSC_XTALOK_EN                 (1 << 16) /* Bit 16:     enables the detector that signals 24MHz crystal oscillator is stable */
+                                                                 /* Bits 17-24: Reserved */
+#define CCM_ANALOG_MISC0_CLKGATE_CTRL                  (1 << 25) /* Bit 25:     This bit allows disabling the clock gate */
+#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT           (26)      /* Bits 26-28: delay powering up the XTAL 24MHz */
+#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK            (0x7 << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)
+#  define CCM_ANALOG_MISC0_CLKGATE_DELAY(n)            ((uint32_t)(n) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)
+#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE               (1 << 29) /* Bit 29:     which chip source is being used for the rtc clock */
+#define CCM_ANALOG_MISC0_XTAL_24M_PWD                  (1 << 30) /* Bit 30:     power down the 24M crystal oscillator if set true */
+#define CCM_ANALOG_MISC0_VID_PLL_PREDIV                (1 << 31) /* Bit 31:     Predivider for the source clock of the PLL's */
+#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_1              (0 << 31) /* Bit 31:     Predivider for the source clock of the PLL's */
+#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_2              (1 << 31) /* Bit 31:     Predivider for the source clock of the PLL's */
+
+/* Miscellaneous Register 1 */
+
+#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT           (0)       /* Bits 0-4:   This field selects the clk to be routed to anaclk1/1b */
+#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK            (0x1f << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_ARM_PLL       ((uint32_t)(0) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SYS_PLL       ((uint32_t)(1) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD4          ((uint32_t)(2) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD5          ((uint32_t)(3) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD6          ((uint32_t)(4) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD7          ((uint32_t)(5) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_AUDIO_PLL     ((uint32_t)(6) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_VIDEO_PLL     ((uint32_t)(7) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_ETHERNET_REF  ((uint32_t)(9) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_USB1_PLL      ((uint32_t)(12) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_USB2_PLL      ((uint32_t)(13) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD0          ((uint32_t)(14) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD1          ((uint32_t)(15) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD2          ((uint32_t)(16) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_PFD3          ((uint32_t)(17) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+#  define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_XTAL          ((uint32_t)(18) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)
+                                                                 /* Bits 5-9:   Reserved */
+#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN                 (1 << 10) /* Bit 10:     This enables the LVDS output buffer for anaclk1/1b */
+                                                                 /* Bit 11:     Reserved */
+#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN                 (1 << 12) /* Bit 12:     This enables the LVDS input buffer for anaclk1/1b */
+                                                                 /* Bits 13-15: Reserved */
+#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN           (1 << 16) /* Bit 16:      */
+#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN           (1 << 17) /* Bit 17:      */
+                                                                 /* Bits 18-26: Reserved */
+#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC                 (1 << 27) /* Bit 27:     temperature sensor panic interrupt */
+#define CCM_ANALOG_MISC1_IRQ_TEMPLOW                   (1 << 28) /* Bit 28:     temperature sensor low interrupt */
+#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH                  (1 << 29) /* Bit 29:     temperature sensor high interrupt */
+#define CCM_ANALOG_MISC1_IRQ_ANA_BO                    (1 << 30) /* Bit 30:     analog regulator brownout interrupt */
+#define CCM_ANALOG_MISC1_IRQ_DIG_BO                    (1 << 31) /* Bit 31:     digital regulator brownout interrupt */
+
+/* Miscellaneous Register 2 */
+
+#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT          (0)       /* Bits 0-2:   This field defines the brown out voltage offset */
+#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK           (0x7 << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)
+#  define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_100        ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)
+#  define CCM_ANALOG_MISC2_REG0_BO_OFFSET_0_175        ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)
+#define CCM_ANALOG_MISC2_REG0_BO_STATUS                (1 << 3)  /* Bit 3:      Reg0 brownout status bit */
+                                                                 /* Bit 4:      Reserved */
+#define CCM_ANALOG_MISC2_REG0_ENABLE_BO                (1 << 5)  /* Bit 5:      Enables the brownout detection */
+#define CCM_ANALOG_MISC2_REG0_OK                       (1 << 6)  /* Bit 6:      ARM supply */
+#define CCM_ANALOG_MISC2_PLL3_DISABLE                  (1 << 7)  /* Bit 7:      PLL3 can be disabled when the SoC is not in any low power mode */
+#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT          (8)       /* Bits 8-10:  This field defines the brown out voltage offset */
+#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK           (0x7 << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)
+#  define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_100        ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)
+#  define CCM_ANALOG_MISC2_REG1_BO_OFFSET_0_175        ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)
+#define CCM_ANALOG_MISC2_REG1_BO_STATUS                (1 << 11) /* Bit 11:     Reg1 brownout status bit */
+                                                                 /* Bit 12:     Reserved */
+#define CCM_ANALOG_MISC2_REG1_ENABLE_BO                (1 << 13) /* Bit 13:     Enables the brownout detection */
+#define CCM_ANALOG_MISC2_REG1_OK                       (1 << 14) /* Bit 14:     GPU/VPU supply */
+#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB                 (1 << 15) /* Bit 15:     LSB of Post-divider for Audio PLL */
+
+#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT          (16)      /* Bits 16-18: This field defines the brown out voltage offset */
+#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK           (0x7 << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)
+#  define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_100        ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)
+#  define CCM_ANALOG_MISC2_REG2_BO_OFFSET_0_175        ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)
+#define CCM_ANALOG_MISC2_REG2_BO_STATUS                (1 << 19) /* Bit 19:     Reg2 brownout status bit */
+                                                                 /* Bit 20:     Reserved */
+#define CCM_ANALOG_MISC2_REG2_ENABLE_BO                (1 << 21) /* Bit 21:     Enables the brownout detection */
+#define CCM_ANALOG_MISC2_REG2_OK                       (1 << 22) /* Bit 22:     voltage is above the brownout level for the SOC supply */
+#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB                 (1 << 23) /* Bit 23:     MSB of Post-divider for Audio PLL */
+#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT          (24)      /* Bits 24-25: Number of clock periods (24MHz clock) */
+#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK           (0x3 << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG0_STEP_TIME_64           ((uint32_t)(0) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG0_STEP_TIME_128          ((uint32_t)(1) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG0_STEP_TIME_256          ((uint32_t)(2) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG0_STEP_TIME_512          ((uint32_t)(3) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)
+#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT          (26)      /* Bits 26-27: Number of clock periods (24MHz clock) */
+#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK           (0x3 << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG1_STEP_TIME_64           ((uint32_t)(0) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG1_STEP_TIME_128          ((uint32_t)(1) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG1_STEP_TIME_256          ((uint32_t)(2) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG1_STEP_TIME_512          ((uint32_t)(3) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)
+#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT          (28)      /* Bits 28-29: Number of clock periods (24MHz clock) */
+#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK           (0x3 << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG2_STEP_TIME_64           ((uint32_t)(0) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG2_STEP_TIME_128          ((uint32_t)(1) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG2_STEP_TIME_256          ((uint32_t)(2) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)
+#  define CCM_ANALOG_MISC2_REG2_STEP_TIME_512          ((uint32_t)(3) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)
+
+#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT               (30)      /* Bits 30-31: Post-divider for video */
+#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK                (0x3 << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)
+#  define CCM_ANALOG_MISC2_VIDEO_DIV(n)                ((uint32_t)(n) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_CCM_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt105x_dmamux.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_dmamux.h
similarity index 98%
rename from arch/arm/src/imxrt/chip/imxrt105x_dmamux.h
rename to arch/arm/src/imxrt/hardware/rt105x/imxrt105x_dmamux.h
index a1c9dae722b..c79e5b16d3a 100644
--- a/arch/arm/src/imxrt/chip/imxrt105x_dmamux.h
+++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_dmamux.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt105x_dmamux.h
+ * arch/arm/src/imxrt/hardware/imxrt105x_dmamux.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_DMAMUX_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_DMAMUX_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_DMAMUX_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_DMAMUX_H
 
 /************************************************************************************
  * Included Files
@@ -165,4 +165,4 @@
 
 #define IMXRT_DMA_NCHANNLES          128  /* Includes reserved channels */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_DMAMUX_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_DMAMUX_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt105x_gpio.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_gpio.h
similarity index 96%
rename from arch/arm/src/imxrt/chip/imxrt105x_gpio.h
rename to arch/arm/src/imxrt/hardware/rt105x/imxrt105x_gpio.h
index c2dea414066..a868493fe8b 100644
--- a/arch/arm/src/imxrt/chip/imxrt105x_gpio.h
+++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_gpio.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/imxrt/imxrt105x_gpio.h
+ * arch/arm/src/imxrt/hardware/rt105x/imxrt105x_gpio.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,15 +34,15 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_GPIO_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_GPIO_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_GPIO_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_GPIO_H
 
 /********************************************************************************************
  * Included Files
  ********************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -124,4 +124,4 @@
 #define IMXRT_GPIO5_CLEAR        (IMXRT_GPIO5_BASE + IMXRT_GPIO_CLEAR_OFFSET)
 #define IMXRT_GPIO5_TOGGLE       (IMXRT_GPIO5_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_GPIO_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_GPIO_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt105x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h
similarity index 99%
rename from arch/arm/src/imxrt/chip/imxrt105x_iomuxc.h
rename to arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h
index e079de8cfeb..dcffde20a46 100644
--- a/arch/arm/src/imxrt/chip/imxrt105x_iomuxc.h
+++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/imxrt105x_iomuxc.h
+ * arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Gregory Nutt 
@@ -34,15 +34,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_IOMUXC_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_IOMUXC_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_IOMUXC_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_IOMUXC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -1991,4 +1991,4 @@
 #define GPR_GPR25_M7_APC_AC_R3_TOP_MASK                         (0x1fffffff << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)
 #define GPR_GPR25_M7_APC_AC_R3_TOP(n)                           ((uint32_t)(n)) << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_IOMUXC_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_IOMUXC_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt105x_memorymap.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_memorymap.h
similarity index 98%
rename from arch/arm/src/imxrt/chip/imxrt105x_memorymap.h
rename to arch/arm/src/imxrt/hardware/rt105x/imxrt105x_memorymap.h
index fe0ed3fa189..a9a18f1199b 100644
--- a/arch/arm/src/imxrt/chip/imxrt105x_memorymap.h
+++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt105x_memorymap.h
+ * arch/arm/src/imxrt/hardware/rt105x/imxrt105x_memorymap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_MEMORYMAP_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -255,4 +255,4 @@
 #define IMXRT_PROCROM_BASE        0xe00fe000  /* 4KB Processor ROM */
 #define IMXRT_PPBROM_BASE         0xe00ff000  /* 4KB PPB ROM */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_MEMORYMAP_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt105x_pinmux.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_pinmux.h
similarity index 99%
rename from arch/arm/src/imxrt/chip/imxrt105x_pinmux.h
rename to arch/arm/src/imxrt/hardware/rt105x/imxrt105x_pinmux.h
index 089b54365ca..c0de8afabc0 100644
--- a/arch/arm/src/imxrt/chip/imxrt105x_pinmux.h
+++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_pinmux.h
@@ -1,5 +1,5 @@
 /*****************************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt105x_pinmux.h
+ * arch/arm/src/imxrt/hardware/rt105x/imxrt105x_pinmux.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  *****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_PINMUX_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_PINMUX_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_PINMUX_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_PINMUX_H
 
 /*****************************************************************************************************
  * Included Files
  *****************************************************************************************************/
 
 #include 
-#include "chip/imxrt_iomuxc.h"
+#include "imxrt_iomuxc.h"
 
 /*****************************************************************************************************
  * Pre-processor Definitions
@@ -1087,4 +1087,4 @@
 #define GPIO_XBAR1_INOUT19_4           (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX))
 #define GPIO_XBAR1_XBAR_IN02           (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX))
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_PINMUX_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_PINMUX_H */
diff --git a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_xbar.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_xbar.h
new file mode 100644
index 00000000000..697972163f6
--- /dev/null
+++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_xbar.h
@@ -0,0 +1,386 @@
+/* XBAR Defines for IMXRT1050 */
+
+/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/
+
+#define IMXRT_XBARA1_IN_LOGIC_LOW                        IMXRT_XBARA1(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARA1_IN0 input. */
+#define IMXRT_XBARA1_IN_LOGIC_HIGH                       IMXRT_XBARA1(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN02                  IMXRT_XBARA1(XBAR_INPUT, 2)    /* IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN03                  IMXRT_XBARA1(XBAR_INPUT, 3)    /* IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04                  IMXRT_XBARA1(XBAR_INPUT, 4)    /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05                  IMXRT_XBARA1(XBAR_INPUT, 5)    /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06                  IMXRT_XBARA1(XBAR_INPUT, 6)    /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07                  IMXRT_XBARA1(XBAR_INPUT, 7)    /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08                  IMXRT_XBARA1(XBAR_INPUT, 8)    /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09                  IMXRT_XBARA1(XBAR_INPUT, 9)    /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10                  IMXRT_XBARA1(XBAR_INPUT, 10)   /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11                  IMXRT_XBARA1(XBAR_INPUT, 11)   /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12                  IMXRT_XBARA1(XBAR_INPUT, 12)   /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13                  IMXRT_XBARA1(XBAR_INPUT, 13)   /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14                  IMXRT_XBARA1(XBAR_INPUT, 14)   /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15                  IMXRT_XBARA1(XBAR_INPUT, 15)   /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16                  IMXRT_XBARA1(XBAR_INPUT, 16)   /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17                  IMXRT_XBARA1(XBAR_INPUT, 17)   /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18                  IMXRT_XBARA1(XBAR_INPUT, 18)   /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19                  IMXRT_XBARA1(XBAR_INPUT, 19)   /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN20                  IMXRT_XBARA1(XBAR_INPUT, 20)   /* IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN21                  IMXRT_XBARA1(XBAR_INPUT, 21)   /* IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN22                  IMXRT_XBARA1(XBAR_INPUT, 22)   /* IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN23                  IMXRT_XBARA1(XBAR_INPUT, 23)   /* IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN24                  IMXRT_XBARA1(XBAR_INPUT, 24)   /* IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN25                  IMXRT_XBARA1(XBAR_INPUT, 25)   /* IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */
+#define IMXRT_XBARA1_IN_ACMP1_OUT                        IMXRT_XBARA1(XBAR_INPUT, 26)   /* ACMP1_OUT output assigned to XBARA1_IN26 input. */
+#define IMXRT_XBARA1_IN_ACMP2_OUT                        IMXRT_XBARA1(XBAR_INPUT, 27)   /* ACMP2_OUT output assigned to XBARA1_IN27 input. */
+#define IMXRT_XBARA1_IN_ACMP3_OUT                        IMXRT_XBARA1(XBAR_INPUT, 28)   /* ACMP3_OUT output assigned to XBARA1_IN28 input. */
+#define IMXRT_XBARA1_IN_ACMP4_OUT                        IMXRT_XBARA1(XBAR_INPUT, 29)   /* ACMP4_OUT output assigned to XBARA1_IN29 input. */
+#define IMXRT_XBARA1_IN_RESERVED30                       IMXRT_XBARA1(XBAR_INPUT, 30)   /* XBARA1_IN30 input is reserved. */
+#define IMXRT_XBARA1_IN_RESERVED31                       IMXRT_XBARA1(XBAR_INPUT, 31)   /* XBARA1_IN31 input is reserved. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 32)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 33)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 34)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 35)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 36)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 37)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 38)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 39)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 40)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 41)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 42)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 43)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 44)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 45)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 46)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 47)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 48)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 49)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 50)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 51)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 52)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 53)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 54)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 55)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER0                     IMXRT_XBARA1(XBAR_INPUT, 56)   /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER1                     IMXRT_XBARA1(XBAR_INPUT, 57)   /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER2                     IMXRT_XBARA1(XBAR_INPUT, 58)   /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER3                     IMXRT_XBARA1(XBAR_INPUT, 59)   /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
+#define IMXRT_XBARA1_IN_ENC1_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 60)   /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
+#define IMXRT_XBARA1_IN_ENC2_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 61)   /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
+#define IMXRT_XBARA1_IN_ENC3_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 62)   /* ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */
+#define IMXRT_XBARA1_IN_ENC4_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 63)   /* ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE0                        IMXRT_XBARA1(XBAR_INPUT, 64)   /* DMA_DONE0 output assigned to XBARA1_IN64 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE1                        IMXRT_XBARA1(XBAR_INPUT, 65)   /* DMA_DONE1 output assigned to XBARA1_IN65 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE2                        IMXRT_XBARA1(XBAR_INPUT, 66)   /* DMA_DONE2 output assigned to XBARA1_IN66 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE3                        IMXRT_XBARA1(XBAR_INPUT, 67)   /* DMA_DONE3 output assigned to XBARA1_IN67 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE4                        IMXRT_XBARA1(XBAR_INPUT, 68)   /* DMA_DONE4 output assigned to XBARA1_IN68 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE5                        IMXRT_XBARA1(XBAR_INPUT, 69)   /* DMA_DONE5 output assigned to XBARA1_IN69 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE6                        IMXRT_XBARA1(XBAR_INPUT, 70)   /* DMA_DONE6 output assigned to XBARA1_IN70 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE7                        IMXRT_XBARA1(XBAR_INPUT, 71)   /* DMA_DONE7 output assigned to XBARA1_IN71 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT0                        IMXRT_XBARA1(XBAR_INPUT, 72)   /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT1                        IMXRT_XBARA1(XBAR_INPUT, 73)   /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT2                        IMXRT_XBARA1(XBAR_INPUT, 74)   /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT3                        IMXRT_XBARA1(XBAR_INPUT, 75)   /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT0                        IMXRT_XBARA1(XBAR_INPUT, 76)   /* AOI2_OUT0 output assigned to XBARA1_IN76 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT1                        IMXRT_XBARA1(XBAR_INPUT, 77)   /* AOI2_OUT1 output assigned to XBARA1_IN77 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT2                        IMXRT_XBARA1(XBAR_INPUT, 78)   /* AOI2_OUT2 output assigned to XBARA1_IN78 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT3                        IMXRT_XBARA1(XBAR_INPUT, 79)   /* AOI2_OUT3 output assigned to XBARA1_IN79 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARA1(XBAR_INPUT, 80)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARA1(XBAR_INPUT, 81)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARA1(XBAR_INPUT, 82)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARA1(XBAR_INPUT, 83)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARA1(XBAR_INPUT, 84)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARA1(XBAR_INPUT, 85)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARA1(XBAR_INPUT, 86)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARA1(XBAR_INPUT, 87)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
+
+/* XBARA1 Mux Output  (M Muxes) ***************************************************************************************************************/
+
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 0)    /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 1)    /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 2)    /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 3)    /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 4)    /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 5)    /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 6)    /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 7)    /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 8)    /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 9)    /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 10)   /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 11)   /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 12)   /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 13)   /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 14)   /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 15)   /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 16)   /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 17)   /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 18)   /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 19)   /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
+#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 20)   /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 21)   /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 22)   /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 23)   /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
+#define IMXRT_XBARA1_OUT_RESERVED24_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 24)   /* XBARA1_OUT24 output is reserved. */
+#define IMXRT_XBARA1_OUT_RESERVED25_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 25)   /* XBARA1_OUT25 output is reserved. */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 26)   /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 27)   /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 28)   /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 29)   /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 30)   /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 31)   /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 32)   /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 33)   /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 34)   /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 35)   /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 36)   /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 37)   /* XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 38)   /* XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 39)   /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA0_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 40)   /* XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA1_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 41)   /* XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA2_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 42)   /* XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA3_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 43)   /* XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 44)   /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 45)   /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 46)   /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 47)   /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 48)   /* XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 49)   /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 50)   /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 51)   /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 52)   /* XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 53)   /* XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 54)   /* XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 55)   /* XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 56)   /* XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 57)   /* XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 58)   /* XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 59)   /* XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 60)   /* XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 61)   /* XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 62)   /* XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 63)   /* XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 64)   /* XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 65)   /* XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 66)   /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 67)   /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 68)   /* XBARA1_OUT68 output assigned to ENC1_INDEX */
+#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 69)   /* XBARA1_OUT69 output assigned to ENC1_HOME */
+#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 70)   /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */
+#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 71)   /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 72)   /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 73)   /* XBARA1_OUT73 output assigned to ENC2_INDEX */
+#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 74)   /* XBARA1_OUT74 output assigned to ENC2_HOME */
+#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 75)   /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */
+#define IMXRT_XBARA1_OUT_ENC3_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 76)   /* XBARA1_OUT76 output assigned to ENC3_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC3_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 77)   /* XBARA1_OUT77 output assigned to ENC3_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC3_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 78)   /* XBARA1_OUT78 output assigned to ENC3_INDEX */
+#define IMXRT_XBARA1_OUT_ENC3_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 79)   /* XBARA1_OUT79 output assigned to ENC3_HOME */
+#define IMXRT_XBARA1_OUT_ENC3_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 80)   /* XBARA1_OUT80 output assigned to ENC3_TRIGGER */
+#define IMXRT_XBARA1_OUT_ENC4_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 81)   /* XBARA1_OUT81 output assigned to ENC4_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC4_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 82)   /* XBARA1_OUT82 output assigned to ENC4_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC4_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 83)   /* XBARA1_OUT83 output assigned to ENC4_INDEX */
+#define IMXRT_XBARA1_OUT_ENC4_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 84)   /* XBARA1_OUT84 output assigned to ENC4_HOME */
+#define IMXRT_XBARA1_OUT_ENC4_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 85)   /* XBARA1_OUT85 output assigned to ENC4_TRIGGER */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 86)   /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 87)   /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 88)   /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 89)   /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 90)   /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 91)   /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 92)   /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 93)   /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 94)   /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 95)   /* XBARA1_OUT95 output assigned to QTIMER3_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 96)   /* XBARA1_OUT96 output assigned to QTIMER3_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 97)   /* XBARA1_OUT97 output assigned to QTIMER3_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 98)   /* XBARA1_OUT98 output assigned to QTIMER4_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 99)   /* XBARA1_OUT99 output assigned to QTIMER4_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 100)  /* XBARA1_OUT100 output assigned to QTIMER4_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 101)  /* XBARA1_OUT101 output assigned to QTIMER4_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 102)  /* XBARA1_OUT102 output assigned to EWM_EWM_IN */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 103)  /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 104)  /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 105)  /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 106)  /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 107)  /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 108)  /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG2_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 109)  /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG3_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 110)  /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */
+#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 111)  /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 112)  /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 113)  /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 114)  /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 115)  /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 116)  /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 117)  /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 118)  /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 119)  /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 120)  /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 121)  /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 122)  /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 123)  /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 124)  /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 125)  /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 126)  /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 127)  /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
+#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 128)  /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
+#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 129)  /* XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */
+#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 130)  /* XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */
+
+/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/
+
+#define IMXRT_XBARB2_IN_LOGIC_LOW                        IMXRT_XBARB2(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARB2_IN0 input. */
+#define IMXRT_XBARB2_IN_LOGIC_HIGH                       IMXRT_XBARB2(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */
+#define IMXRT_XBARB2_IN_RESERVED2                        IMXRT_XBARB2(XBAR_INPUT, 2)    /* XBARB2_IN2 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED3                        IMXRT_XBARB2(XBAR_INPUT, 3)    /* XBARB2_IN3 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED4                        IMXRT_XBARB2(XBAR_INPUT, 4)    /* XBARB2_IN4 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED5                        IMXRT_XBARB2(XBAR_INPUT, 5)    /* XBARB2_IN5 input is reserved. */
+#define IMXRT_XBARB2_IN_ACMP1_OUT                        IMXRT_XBARB2(XBAR_INPUT, 6)    /* ACMP1_OUT output assigned to XBARB2_IN6 input. */
+#define IMXRT_XBARB2_IN_ACMP2_OUT                        IMXRT_XBARB2(XBAR_INPUT, 7)    /* ACMP2_OUT output assigned to XBARB2_IN7 input. */
+#define IMXRT_XBARB2_IN_ACMP3_OUT                        IMXRT_XBARB2(XBAR_INPUT, 8)    /* ACMP3_OUT output assigned to XBARB2_IN8 input. */
+#define IMXRT_XBARB2_IN_ACMP4_OUT                        IMXRT_XBARB2(XBAR_INPUT, 9)    /* ACMP4_OUT output assigned to XBARB2_IN9 input. */
+#define IMXRT_XBARB2_IN_RESERVED10                       IMXRT_XBARB2(XBAR_INPUT, 10)   /* XBARB2_IN10 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED11                       IMXRT_XBARB2(XBAR_INPUT, 11)   /* XBARB2_IN11 input is reserved. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 12)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 13)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 14)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 15)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 16)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 17)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 18)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 19)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 28)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 29)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 30)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 31)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 32)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 33)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 34)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 35)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
+#define IMXRT_XBARB2_IN_PIT_TRIGGER0                     IMXRT_XBARB2(XBAR_INPUT, 36)   /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
+#define IMXRT_XBARB2_IN_PIT_TRIGGER1                     IMXRT_XBARB2(XBAR_INPUT, 37)   /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARB2(XBAR_INPUT, 38)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARB2(XBAR_INPUT, 39)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARB2(XBAR_INPUT, 40)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARB2(XBAR_INPUT, 41)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARB2(XBAR_INPUT, 42)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARB2(XBAR_INPUT, 43)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARB2(XBAR_INPUT, 44)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARB2(XBAR_INPUT, 45)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
+#define IMXRT_XBARB2_IN_ENC1_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 46)   /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
+#define IMXRT_XBARB2_IN_ENC2_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 47)   /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
+#define IMXRT_XBARB2_IN_ENC3_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 48)   /* ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */
+#define IMXRT_XBARB2_IN_ENC4_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 49)   /* ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE0                        IMXRT_XBARB2(XBAR_INPUT, 50)   /* DMA_DONE0 output assigned to XBARB2_IN50 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE1                        IMXRT_XBARB2(XBAR_INPUT, 51)   /* DMA_DONE1 output assigned to XBARB2_IN51 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE2                        IMXRT_XBARB2(XBAR_INPUT, 52)   /* DMA_DONE2 output assigned to XBARB2_IN52 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE3                        IMXRT_XBARB2(XBAR_INPUT, 53)   /* DMA_DONE3 output assigned to XBARB2_IN53 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE4                        IMXRT_XBARB2(XBAR_INPUT, 54)   /* DMA_DONE4 output assigned to XBARB2_IN54 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE5                        IMXRT_XBARB2(XBAR_INPUT, 55)   /* DMA_DONE5 output assigned to XBARB2_IN55 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE6                        IMXRT_XBARB2(XBAR_INPUT, 56)   /* DMA_DONE6 output assigned to XBARB2_IN56 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE7                        IMXRT_XBARB2(XBAR_INPUT, 57)   /* DMA_DONE7 output assigned to XBARB2_IN57 input. */
+
+/* XBARB2 Mux Output  (M Muxes) ********************************************************************************************************************/
+
+#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 0)    /* XBARB2_OUT0 output assigned to AOI1_IN00 */
+#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 1)    /* XBARB2_OUT1 output assigned to AOI1_IN01 */
+#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 2)    /* XBARB2_OUT2 output assigned to AOI1_IN02 */
+#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 3)    /* XBARB2_OUT3 output assigned to AOI1_IN03 */
+#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 4)    /* XBARB2_OUT4 output assigned to AOI1_IN04 */
+#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 5)    /* XBARB2_OUT5 output assigned to AOI1_IN05 */
+#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 6)    /* XBARB2_OUT6 output assigned to AOI1_IN06 */
+#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 7)    /* XBARB2_OUT7 output assigned to AOI1_IN07 */
+#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 8)    /* XBARB2_OUT8 output assigned to AOI1_IN08 */
+#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 9)    /* XBARB2_OUT9 output assigned to AOI1_IN09 */
+#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 10)   /* XBARB2_OUT10 output assigned to AOI1_IN10 */
+#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 11)   /* XBARB2_OUT11 output assigned to AOI1_IN11 */
+#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 12)   /* XBARB2_OUT12 output assigned to AOI1_IN12 */
+#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 13)   /* XBARB2_OUT13 output assigned to AOI1_IN13 */
+#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 14)   /* XBARB2_OUT14 output assigned to AOI1_IN14 */
+#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 15)   /* XBARB2_OUT15 output assigned to AOI1_IN15 */
+
+/* XBARB3 Mux inputs (I values) *******************************************************************************************************************/
+
+#define IMXRT_XBARB3_IN_LOGIC_LOW                        IMXRT_XBARB3(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARB3_IN0 input. */
+#define IMXRT_XBARB3_IN_LOGIC_HIGH                       IMXRT_XBARB3(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARB3_IN1 input. */
+#define IMXRT_XBARB3_IN_RESERVED2                        IMXRT_XBARB3(XBAR_INPUT, 2)    /* XBARB3_IN2 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED3                        IMXRT_XBARB3(XBAR_INPUT, 3)    /* XBARB3_IN3 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED4                        IMXRT_XBARB3(XBAR_INPUT, 4)    /* XBARB3_IN4 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED5                        IMXRT_XBARB3(XBAR_INPUT, 5)    /* XBARB3_IN5 input is reserved. */
+#define IMXRT_XBARB3_IN_ACMP1_OUT                        IMXRT_XBARB3(XBAR_INPUT, 6)    /* ACMP1_OUT output assigned to XBARB3_IN6 input. */
+#define IMXRT_XBARB3_IN_ACMP2_OUT                        IMXRT_XBARB3(XBAR_INPUT, 7)    /* ACMP2_OUT output assigned to XBARB3_IN7 input. */
+#define IMXRT_XBARB3_IN_ACMP3_OUT                        IMXRT_XBARB3(XBAR_INPUT, 8)    /* ACMP3_OUT output assigned to XBARB3_IN8 input. */
+#define IMXRT_XBARB3_IN_ACMP4_OUT                        IMXRT_XBARB3(XBAR_INPUT, 9)    /* ACMP4_OUT output assigned to XBARB3_IN9 input. */
+#define IMXRT_XBARB3_IN_RESERVED10                       IMXRT_XBARB3(XBAR_INPUT, 10)   /* XBARB3_IN10 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED11                       IMXRT_XBARB3(XBAR_INPUT, 11)   /* XBARB3_IN11 input is reserved. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARB3(XBAR_INPUT, 12)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARB3(XBAR_INPUT, 13)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARB3(XBAR_INPUT, 14)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARB3(XBAR_INPUT, 15)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARB3(XBAR_INPUT, 16)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARB3(XBAR_INPUT, 17)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARB3(XBAR_INPUT, 18)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARB3(XBAR_INPUT, 19)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 28)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 29)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 30)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 31)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 32)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 33)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 34)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 35)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
+#define IMXRT_XBARB3_IN_PIT_TRIGGER0                     IMXRT_XBARB3(XBAR_INPUT, 36)   /* PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */
+#define IMXRT_XBARB3_IN_PIT_TRIGGER1                     IMXRT_XBARB3(XBAR_INPUT, 37)   /* PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARB3(XBAR_INPUT, 38)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARB3(XBAR_INPUT, 39)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARB3(XBAR_INPUT, 40)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARB3(XBAR_INPUT, 41)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARB3(XBAR_INPUT, 42)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARB3(XBAR_INPUT, 43)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARB3(XBAR_INPUT, 44)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARB3(XBAR_INPUT, 45)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */
+#define IMXRT_XBARB3_IN_ENC1_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 46)   /* ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */
+#define IMXRT_XBARB3_IN_ENC2_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 47)   /* ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */
+#define IMXRT_XBARB3_IN_ENC3_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 48)   /* ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */
+#define IMXRT_XBARB3_IN_ENC4_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 49)   /* ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE0                        IMXRT_XBARB3(XBAR_INPUT, 50)   /* DMA_DONE0 output assigned to XBARB3_IN50 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE1                        IMXRT_XBARB3(XBAR_INPUT, 51)   /* DMA_DONE1 output assigned to XBARB3_IN51 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE2                        IMXRT_XBARB3(XBAR_INPUT, 52)   /* DMA_DONE2 output assigned to XBARB3_IN52 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE3                        IMXRT_XBARB3(XBAR_INPUT, 53)   /* DMA_DONE3 output assigned to XBARB3_IN53 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE4                        IMXRT_XBARB3(XBAR_INPUT, 54)   /* DMA_DONE4 output assigned to XBARB3_IN54 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE5                        IMXRT_XBARB3(XBAR_INPUT, 55)   /* DMA_DONE5 output assigned to XBARB3_IN55 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE6                        IMXRT_XBARB3(XBAR_INPUT, 56)   /* DMA_DONE6 output assigned to XBARB3_IN56 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE7                        IMXRT_XBARB3(XBAR_INPUT, 57)   /* DMA_DONE7 output assigned to XBARB3_IN57 input. */
+
+/* XBARB3 Mux Output  (M Muxes) ********************************************************************************************************************/
+
+#define IMXRT_XBARB3_OUT_AOI2_IN00_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 0)    /* XBARB3_OUT0 output assigned to AOI2_IN00 */
+#define IMXRT_XBARB3_OUT_AOI2_IN01_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 1)    /* XBARB3_OUT1 output assigned to AOI2_IN01 */
+#define IMXRT_XBARB3_OUT_AOI2_IN02_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 2)    /* XBARB3_OUT2 output assigned to AOI2_IN02 */
+#define IMXRT_XBARB3_OUT_AOI2_IN03_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 3)    /* XBARB3_OUT3 output assigned to AOI2_IN03 */
+#define IMXRT_XBARB3_OUT_AOI2_IN04_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 4)    /* XBARB3_OUT4 output assigned to AOI2_IN04 */
+#define IMXRT_XBARB3_OUT_AOI2_IN05_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 5)    /* XBARB3_OUT5 output assigned to AOI2_IN05 */
+#define IMXRT_XBARB3_OUT_AOI2_IN06_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 6)    /* XBARB3_OUT6 output assigned to AOI2_IN06 */
+#define IMXRT_XBARB3_OUT_AOI2_IN07_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 7)    /* XBARB3_OUT7 output assigned to AOI2_IN07 */
+#define IMXRT_XBARB3_OUT_AOI2_IN08_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 8)    /* XBARB3_OUT8 output assigned to AOI2_IN08 */
+#define IMXRT_XBARB3_OUT_AOI2_IN09_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 9)    /* XBARB3_OUT9 output assigned to AOI2_IN09 */
+#define IMXRT_XBARB3_OUT_AOI2_IN10_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 10)   /* XBARB3_OUT10 output assigned to AOI2_IN10 */
+#define IMXRT_XBARB3_OUT_AOI2_IN11_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 11)   /* XBARB3_OUT11 output assigned to AOI2_IN11 */
+#define IMXRT_XBARB3_OUT_AOI2_IN12_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 12)   /* XBARB3_OUT12 output assigned to AOI2_IN12 */
+#define IMXRT_XBARB3_OUT_AOI2_IN13_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 13)   /* XBARB3_OUT13 output assigned to AOI2_IN13 */
+#define IMXRT_XBARB3_OUT_AOI2_IN14_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 14)   /* XBARB3_OUT14 output assigned to AOI2_IN14 */
+#define IMXRT_XBARB3_OUT_AOI2_IN15_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 15)   /* XBARB3_OUT15 output assigned to AOI2_IN15 */
diff --git a/arch/arm/src/imxrt/chip/imxrt_ccm.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h
similarity index 99%
rename from arch/arm/src/imxrt/chip/imxrt_ccm.h
rename to arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h
index cc1ca0230fb..1196f0a1aac 100644
--- a/arch/arm/src/imxrt/chip/imxrt_ccm.h
+++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h
@@ -1,5 +1,5 @@
 /************************************************************************************************************
- * arch/arm/src/imxrt/imxrt_ccm.h
+ * arch/arm/src/imxrt/hardware/rt106x/imxrt_ccm.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors:  Janne Rosberg 
@@ -34,15 +34,15 @@
  *
  ************************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_CCM_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_CCM_H
 
 /************************************************************************************************************
  * Included Files
  ************************************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /************************************************************************************************************
  * Pre-processor Definitions
@@ -975,6 +975,7 @@
 #define CCM_ANALOG_PLL_ENET_ENABLE_125M                (1 << 19) /* Bit 19:     */
 #define CCM_ANALOG_PLL_ENET_ENET2_125M_EN              (1 << 20) /* Bit 20:     Enable the PLL providing the ENET2 125 MHz reference clock */
 #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN            (1 << 21) /* Bit 21:     Enable the PLL providing ENET 25 MHz reference clock */
+#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN           (1 << 22) /* Bit 22:     Enable the PLL providing NET 500 MHz reference clock */
 #define CCM_ANALOG_PLL_ENET_LOCK                       (1 << 31) /* Bit 31:     PLL is currently locked */
 
 /* 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
@@ -1140,4 +1141,4 @@
 #define CCM_ANALOG_MISC2_VIDEO_DIV_MASK                (0x3 << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)
 #  define CCM_ANALOG_MISC2_VIDEO_DIV(n)                ((uint32_t)(n) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_CCM_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_CCM_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt106x_dmamux.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_dmamux.h
similarity index 98%
rename from arch/arm/src/imxrt/chip/imxrt106x_dmamux.h
rename to arch/arm/src/imxrt/hardware/rt106x/imxrt106x_dmamux.h
index 52e9e84f296..b806c351699 100644
--- a/arch/arm/src/imxrt/chip/imxrt106x_dmamux.h
+++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_dmamux.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt106x_dmamux.h
+ * arch/arm/src/imxrt/hardware/rt106x/imxrt106x_dmamux.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_DMAMUX_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_DMAMUX_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_DMAMUX_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_DMAMUX_H
 
 /************************************************************************************
  * Included Files
@@ -171,4 +171,4 @@
 
 #define IMXRT_DMA_NCHANNLES          128  /* Includes reserved channels */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_DMAMUX_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_DMAMUX_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt106x_gpio.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_gpio.h
similarity index 97%
rename from arch/arm/src/imxrt/chip/imxrt106x_gpio.h
rename to arch/arm/src/imxrt/hardware/rt106x/imxrt106x_gpio.h
index 611ddfe3502..d6f830f6dd4 100644
--- a/arch/arm/src/imxrt/chip/imxrt106x_gpio.h
+++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_gpio.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/imxrt/imxrt106x_gpio.h
+ * arch/arm/src/imxrt/hardware/rt106x/imxrt106x_gpio.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,15 +34,15 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_GPIO_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_GPIO_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_GPIO_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_GPIO_H
 
 /********************************************************************************************
  * Included Files
  ********************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -172,4 +172,4 @@
 #  define IMXRT_GPIO9_CLEAR      (IMXRT_GPIO9_BASE + IMXRT_GPIO_CLEAR_OFFSET)
 #  define IMXRT_GPIO9_TOGGLE     (IMXRT_GPIO9_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_GPIO_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_GPIO_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt106x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h
similarity index 99%
rename from arch/arm/src/imxrt/chip/imxrt106x_iomuxc.h
rename to arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h
index 5ec7db7d714..0ffb0520094 100644
--- a/arch/arm/src/imxrt/chip/imxrt106x_iomuxc.h
+++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/imxrt_iomuxc.h
+ * arch/arm/src/imxrt/hardware/rt106x/imxrt106x_iomuxc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Gregory Nutt 
@@ -34,15 +34,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_IOMUXC_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_IOMUXC_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_IOMUXC_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_IOMUXC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -2543,4 +2543,4 @@
 #define GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL(n)                  ((uint32_t)(n) << GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT)
 #define GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN                      (1 << 8)
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_IOMUXC_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_IOMUXC_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt106x_memorymap.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_memorymap.h
similarity index 98%
rename from arch/arm/src/imxrt/chip/imxrt106x_memorymap.h
rename to arch/arm/src/imxrt/hardware/rt106x/imxrt106x_memorymap.h
index 35cdfde5fd6..5184a6134dc 100644
--- a/arch/arm/src/imxrt/chip/imxrt106x_memorymap.h
+++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt105x_memorymap.h
+ * arch/arm/src/imxrt/hardware/rt106x/imxrt106x_memorymap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_MEMORYMAP_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -298,4 +298,4 @@
 #define IMXRT_PROCROM_BASE        0xe00fe000  /* 4KB Processor ROM */
 #define IMXRT_PPBROM_BASE         0xe00ff000  /* 4KB PPB ROM */
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_MEMORYMAP_H */
diff --git a/arch/arm/src/imxrt/chip/imxrt106x_pinmux.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h
similarity index 99%
rename from arch/arm/src/imxrt/chip/imxrt106x_pinmux.h
rename to arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h
index 2a45b60d947..5da5d69ebb4 100644
--- a/arch/arm/src/imxrt/chip/imxrt106x_pinmux.h
+++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h
@@ -1,5 +1,5 @@
 /*****************************************************************************************************
- * arch/arm/src/imxrt/chip/imxrt105x_pinmux.h
+ * arch/arm/src/imxrt/hardware/rt106x/imxrt106x_pinmux.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,15 +34,15 @@
  *
  *****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_PINMUX_H
-#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_PINMUX_H
+#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_PINMUX_H
+#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_PINMUX_H
 
 /*****************************************************************************************************
  * Included Files
  *****************************************************************************************************/
 
 #include 
-#include "chip/imxrt_iomuxc.h"
+#include "imxrt_iomuxc.h"
 
 /*****************************************************************************************************
  * Pre-processor Definitions
@@ -1092,4 +1092,4 @@
 #define GPIO_XBAR1_INOUT19_4           (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX))
 #define GPIO_XBAR1_XBAR_IN02           (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX))
 
-#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_PINMUX_H */
+#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT106X_PINMUX_H */
diff --git a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_xbar.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_xbar.h
new file mode 100644
index 00000000000..3d697880494
--- /dev/null
+++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_xbar.h
@@ -0,0 +1,386 @@
+/* XBAR Defines for IMXRT1060 */
+
+/* XBARA1 Mux inputs (I values) ***************************************************************************************************************************************/
+
+#define IMXRT_XBARA1_IN_LOGIC_LOW                        IMXRT_XBARA1(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARA1_IN0 input. */
+#define IMXRT_XBARA1_IN_LOGIC_HIGH                       IMXRT_XBARA1(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN02                  IMXRT_XBARA1(XBAR_INPUT, 2)    /* IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN03                  IMXRT_XBARA1(XBAR_INPUT, 3)    /* IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04                  IMXRT_XBARA1(XBAR_INPUT, 4)    /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05                  IMXRT_XBARA1(XBAR_INPUT, 5)    /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06                  IMXRT_XBARA1(XBAR_INPUT, 6)    /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07                  IMXRT_XBARA1(XBAR_INPUT, 7)    /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08                  IMXRT_XBARA1(XBAR_INPUT, 8)    /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09                  IMXRT_XBARA1(XBAR_INPUT, 9)    /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10                  IMXRT_XBARA1(XBAR_INPUT, 10)   /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11                  IMXRT_XBARA1(XBAR_INPUT, 11)   /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12                  IMXRT_XBARA1(XBAR_INPUT, 12)   /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13                  IMXRT_XBARA1(XBAR_INPUT, 13)   /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14                  IMXRT_XBARA1(XBAR_INPUT, 14)   /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15                  IMXRT_XBARA1(XBAR_INPUT, 15)   /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16                  IMXRT_XBARA1(XBAR_INPUT, 16)   /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17                  IMXRT_XBARA1(XBAR_INPUT, 17)   /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18                  IMXRT_XBARA1(XBAR_INPUT, 18)   /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19                  IMXRT_XBARA1(XBAR_INPUT, 19)   /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN20                  IMXRT_XBARA1(XBAR_INPUT, 20)   /* IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN21                  IMXRT_XBARA1(XBAR_INPUT, 21)   /* IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN22                  IMXRT_XBARA1(XBAR_INPUT, 22)   /* IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN23                  IMXRT_XBARA1(XBAR_INPUT, 23)   /* IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN24                  IMXRT_XBARA1(XBAR_INPUT, 24)   /* IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */
+#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN25                  IMXRT_XBARA1(XBAR_INPUT, 25)   /* IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */
+#define IMXRT_XBARA1_IN_ACMP1_OUT                        IMXRT_XBARA1(XBAR_INPUT, 26)   /* ACMP1_OUT output assigned to XBARA1_IN26 input. */
+#define IMXRT_XBARA1_IN_ACMP2_OUT                        IMXRT_XBARA1(XBAR_INPUT, 27)   /* ACMP2_OUT output assigned to XBARA1_IN27 input. */
+#define IMXRT_XBARA1_IN_ACMP3_OUT                        IMXRT_XBARA1(XBAR_INPUT, 28)   /* ACMP3_OUT output assigned to XBARA1_IN28 input. */
+#define IMXRT_XBARA1_IN_ACMP4_OUT                        IMXRT_XBARA1(XBAR_INPUT, 29)   /* ACMP4_OUT output assigned to XBARA1_IN29 input. */
+#define IMXRT_XBARA1_IN_RESERVED30                       IMXRT_XBARA1(XBAR_INPUT, 30)   /* XBARA1_IN30 input is reserved. */
+#define IMXRT_XBARA1_IN_RESERVED31                       IMXRT_XBARA1(XBAR_INPUT, 31)   /* XBARA1_IN31 input is reserved. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 32)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 33)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 34)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
+#define IMXRT_XBARA1_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 35)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 36)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 37)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 38)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
+#define IMXRT_XBARA1_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 39)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 40)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 41)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 42)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 43)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 44)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 45)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 46)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 47)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 48)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 49)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 50)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 51)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 52)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 53)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 54)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */
+#define IMXRT_XBARA1_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 55)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER0                     IMXRT_XBARA1(XBAR_INPUT, 56)   /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER1                     IMXRT_XBARA1(XBAR_INPUT, 57)   /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER2                     IMXRT_XBARA1(XBAR_INPUT, 58)   /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
+#define IMXRT_XBARA1_IN_PIT_TRIGGER3                     IMXRT_XBARA1(XBAR_INPUT, 59)   /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
+#define IMXRT_XBARA1_IN_ENC1_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 60)   /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
+#define IMXRT_XBARA1_IN_ENC2_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 61)   /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
+#define IMXRT_XBARA1_IN_ENC3_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 62)   /* ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */
+#define IMXRT_XBARA1_IN_ENC4_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 63)   /* ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE0                        IMXRT_XBARA1(XBAR_INPUT, 64)   /* DMA_DONE0 output assigned to XBARA1_IN64 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE1                        IMXRT_XBARA1(XBAR_INPUT, 65)   /* DMA_DONE1 output assigned to XBARA1_IN65 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE2                        IMXRT_XBARA1(XBAR_INPUT, 66)   /* DMA_DONE2 output assigned to XBARA1_IN66 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE3                        IMXRT_XBARA1(XBAR_INPUT, 67)   /* DMA_DONE3 output assigned to XBARA1_IN67 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE4                        IMXRT_XBARA1(XBAR_INPUT, 68)   /* DMA_DONE4 output assigned to XBARA1_IN68 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE5                        IMXRT_XBARA1(XBAR_INPUT, 69)   /* DMA_DONE5 output assigned to XBARA1_IN69 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE6                        IMXRT_XBARA1(XBAR_INPUT, 70)   /* DMA_DONE6 output assigned to XBARA1_IN70 input. */
+#define IMXRT_XBARA1_IN_DMA_DONE7                        IMXRT_XBARA1(XBAR_INPUT, 71)   /* DMA_DONE7 output assigned to XBARA1_IN71 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT0                        IMXRT_XBARA1(XBAR_INPUT, 72)   /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT1                        IMXRT_XBARA1(XBAR_INPUT, 73)   /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT2                        IMXRT_XBARA1(XBAR_INPUT, 74)   /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */
+#define IMXRT_XBARA1_IN_AOI1_OUT3                        IMXRT_XBARA1(XBAR_INPUT, 75)   /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT0                        IMXRT_XBARA1(XBAR_INPUT, 76)   /* AOI2_OUT0 output assigned to XBARA1_IN76 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT1                        IMXRT_XBARA1(XBAR_INPUT, 77)   /* AOI2_OUT1 output assigned to XBARA1_IN77 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT2                        IMXRT_XBARA1(XBAR_INPUT, 78)   /* AOI2_OUT2 output assigned to XBARA1_IN78 input. */
+#define IMXRT_XBARA1_IN_AOI2_OUT3                        IMXRT_XBARA1(XBAR_INPUT, 79)   /* AOI2_OUT3 output assigned to XBARA1_IN79 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARA1(XBAR_INPUT, 80)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARA1(XBAR_INPUT, 81)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARA1(XBAR_INPUT, 82)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARA1(XBAR_INPUT, 83)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARA1(XBAR_INPUT, 84)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARA1(XBAR_INPUT, 85)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARA1(XBAR_INPUT, 86)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
+#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARA1(XBAR_INPUT, 87)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
+
+/* XBARA1 Mux Output  (M Muxes) ***************************************************************************************************************/
+
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 0)    /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 1)    /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 2)    /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
+#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 3)    /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 4)    /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 5)    /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 6)    /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 7)    /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 8)    /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 9)    /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 10)   /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 11)   /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 12)   /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 13)   /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 14)   /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 15)   /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 16)   /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 17)   /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 18)   /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
+#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 19)   /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
+#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 20)   /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 21)   /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 22)   /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
+#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 23)   /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
+#define IMXRT_XBARA1_OUT_RESERVED24_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 24)   /* XBARA1_OUT24 output is reserved. */
+#define IMXRT_XBARA1_OUT_RESERVED25_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 25)   /* XBARA1_OUT25 output is reserved. */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 26)   /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 27)   /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 28)   /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 29)   /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 30)   /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 31)   /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 32)   /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 33)   /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 34)   /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 35)   /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 36)   /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 37)   /* XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 38)   /* XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 39)   /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA0_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 40)   /* XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA1_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 41)   /* XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA2_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 42)   /* XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA3_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 43)   /* XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 44)   /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 45)   /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 46)   /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 47)   /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 48)   /* XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 49)   /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 50)   /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 51)   /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 52)   /* XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 53)   /* XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 54)   /* XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 55)   /* XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 56)   /* XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 57)   /* XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 58)   /* XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 59)   /* XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 60)   /* XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 61)   /* XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 62)   /* XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 63)   /* XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 64)   /* XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */
+#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 65)   /* XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */
+#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 66)   /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 67)   /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 68)   /* XBARA1_OUT68 output assigned to ENC1_INDEX */
+#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 69)   /* XBARA1_OUT69 output assigned to ENC1_HOME */
+#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 70)   /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */
+#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 71)   /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 72)   /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 73)   /* XBARA1_OUT73 output assigned to ENC2_INDEX */
+#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 74)   /* XBARA1_OUT74 output assigned to ENC2_HOME */
+#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 75)   /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */
+#define IMXRT_XBARA1_OUT_ENC3_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 76)   /* XBARA1_OUT76 output assigned to ENC3_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC3_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 77)   /* XBARA1_OUT77 output assigned to ENC3_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC3_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 78)   /* XBARA1_OUT78 output assigned to ENC3_INDEX */
+#define IMXRT_XBARA1_OUT_ENC3_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 79)   /* XBARA1_OUT79 output assigned to ENC3_HOME */
+#define IMXRT_XBARA1_OUT_ENC3_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 80)   /* XBARA1_OUT80 output assigned to ENC3_TRIGGER */
+#define IMXRT_XBARA1_OUT_ENC4_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 81)   /* XBARA1_OUT81 output assigned to ENC4_PHASE_A_IN_ */
+#define IMXRT_XBARA1_OUT_ENC4_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 82)   /* XBARA1_OUT82 output assigned to ENC4_PHASE_B_IN_ */
+#define IMXRT_XBARA1_OUT_ENC4_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 83)   /* XBARA1_OUT83 output assigned to ENC4_INDEX */
+#define IMXRT_XBARA1_OUT_ENC4_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 84)   /* XBARA1_OUT84 output assigned to ENC4_HOME */
+#define IMXRT_XBARA1_OUT_ENC4_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 85)   /* XBARA1_OUT85 output assigned to ENC4_TRIGGER */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 86)   /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 87)   /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 88)   /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 89)   /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 90)   /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 91)   /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 92)   /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 93)   /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 94)   /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 95)   /* XBARA1_OUT95 output assigned to QTIMER3_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 96)   /* XBARA1_OUT96 output assigned to QTIMER3_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER3_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 97)   /* XBARA1_OUT97 output assigned to QTIMER3_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 98)   /* XBARA1_OUT98 output assigned to QTIMER4_TMR0_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 99)   /* XBARA1_OUT99 output assigned to QTIMER4_TMR1_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 100)  /* XBARA1_OUT100 output assigned to QTIMER4_TMR2_IN_ */
+#define IMXRT_XBARA1_OUT_QTIMER4_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 101)  /* XBARA1_OUT101 output assigned to QTIMER4_TMR3_IN_ */
+#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 102)  /* XBARA1_OUT102 output assigned to EWM_EWM_IN */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 103)  /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 104)  /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 105)  /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 106)  /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 107)  /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 108)  /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG2_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 109)  /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */
+#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG3_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 110)  /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */
+#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 111)  /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 112)  /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 113)  /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 114)  /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 115)  /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 116)  /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 117)  /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 118)  /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 119)  /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 120)  /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 121)  /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 122)  /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 123)  /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 124)  /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 125)  /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 126)  /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN_ */
+#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 127)  /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
+#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 128)  /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
+#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 129)  /* XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */
+#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 130)  /* XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */
+
+/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/
+
+#define IMXRT_XBARB2_IN_LOGIC_LOW                        IMXRT_XBARB2(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARB2_IN0 input. */
+#define IMXRT_XBARB2_IN_LOGIC_HIGH                       IMXRT_XBARB2(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */
+#define IMXRT_XBARB2_IN_RESERVED2                        IMXRT_XBARB2(XBAR_INPUT, 2)    /* XBARB2_IN2 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED3                        IMXRT_XBARB2(XBAR_INPUT, 3)    /* XBARB2_IN3 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED4                        IMXRT_XBARB2(XBAR_INPUT, 4)    /* XBARB2_IN4 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED5                        IMXRT_XBARB2(XBAR_INPUT, 5)    /* XBARB2_IN5 input is reserved. */
+#define IMXRT_XBARB2_IN_ACMP1_OUT                        IMXRT_XBARB2(XBAR_INPUT, 6)    /* ACMP1_OUT output assigned to XBARB2_IN6 input. */
+#define IMXRT_XBARB2_IN_ACMP2_OUT                        IMXRT_XBARB2(XBAR_INPUT, 7)    /* ACMP2_OUT output assigned to XBARB2_IN7 input. */
+#define IMXRT_XBARB2_IN_ACMP3_OUT                        IMXRT_XBARB2(XBAR_INPUT, 8)    /* ACMP3_OUT output assigned to XBARB2_IN8 input. */
+#define IMXRT_XBARB2_IN_ACMP4_OUT                        IMXRT_XBARB2(XBAR_INPUT, 9)    /* ACMP4_OUT output assigned to XBARB2_IN9 input. */
+#define IMXRT_XBARB2_IN_RESERVED10                       IMXRT_XBARB2(XBAR_INPUT, 10)   /* XBARB2_IN10 input is reserved. */
+#define IMXRT_XBARB2_IN_RESERVED11                       IMXRT_XBARB2(XBAR_INPUT, 11)   /* XBARB2_IN11 input is reserved. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 12)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 13)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 14)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
+#define IMXRT_XBARB2_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 15)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 16)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 17)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 18)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
+#define IMXRT_XBARB2_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 19)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 28)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 29)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 30)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 31)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 32)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 33)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 34)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
+#define IMXRT_XBARB2_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 35)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
+#define IMXRT_XBARB2_IN_PIT_TRIGGER0                     IMXRT_XBARB2(XBAR_INPUT, 36)   /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
+#define IMXRT_XBARB2_IN_PIT_TRIGGER1                     IMXRT_XBARB2(XBAR_INPUT, 37)   /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARB2(XBAR_INPUT, 38)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARB2(XBAR_INPUT, 39)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARB2(XBAR_INPUT, 40)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARB2(XBAR_INPUT, 41)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARB2(XBAR_INPUT, 42)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARB2(XBAR_INPUT, 43)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARB2(XBAR_INPUT, 44)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
+#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARB2(XBAR_INPUT, 45)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
+#define IMXRT_XBARB2_IN_ENC1_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 46)   /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
+#define IMXRT_XBARB2_IN_ENC2_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 47)   /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
+#define IMXRT_XBARB2_IN_ENC3_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 48)   /* ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */
+#define IMXRT_XBARB2_IN_ENC4_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 49)   /* ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE0                        IMXRT_XBARB2(XBAR_INPUT, 50)   /* DMA_DONE0 output assigned to XBARB2_IN50 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE1                        IMXRT_XBARB2(XBAR_INPUT, 51)   /* DMA_DONE1 output assigned to XBARB2_IN51 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE2                        IMXRT_XBARB2(XBAR_INPUT, 52)   /* DMA_DONE2 output assigned to XBARB2_IN52 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE3                        IMXRT_XBARB2(XBAR_INPUT, 53)   /* DMA_DONE3 output assigned to XBARB2_IN53 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE4                        IMXRT_XBARB2(XBAR_INPUT, 54)   /* DMA_DONE4 output assigned to XBARB2_IN54 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE5                        IMXRT_XBARB2(XBAR_INPUT, 55)   /* DMA_DONE5 output assigned to XBARB2_IN55 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE6                        IMXRT_XBARB2(XBAR_INPUT, 56)   /* DMA_DONE6 output assigned to XBARB2_IN56 input. */
+#define IMXRT_XBARB2_IN_DMA_DONE7                        IMXRT_XBARB2(XBAR_INPUT, 57)   /* DMA_DONE7 output assigned to XBARB2_IN57 input. */
+
+/* XBARB2 Mux Output  (M Muxes) ********************************************************************************************************************/
+
+#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 0)    /* XBARB2_OUT0 output assigned to AOI1_IN00 */
+#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 1)    /* XBARB2_OUT1 output assigned to AOI1_IN01 */
+#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 2)    /* XBARB2_OUT2 output assigned to AOI1_IN02 */
+#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 3)    /* XBARB2_OUT3 output assigned to AOI1_IN03 */
+#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 4)    /* XBARB2_OUT4 output assigned to AOI1_IN04 */
+#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 5)    /* XBARB2_OUT5 output assigned to AOI1_IN05 */
+#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 6)    /* XBARB2_OUT6 output assigned to AOI1_IN06 */
+#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 7)    /* XBARB2_OUT7 output assigned to AOI1_IN07 */
+#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 8)    /* XBARB2_OUT8 output assigned to AOI1_IN08 */
+#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 9)    /* XBARB2_OUT9 output assigned to AOI1_IN09 */
+#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 10)   /* XBARB2_OUT10 output assigned to AOI1_IN10 */
+#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 11)   /* XBARB2_OUT11 output assigned to AOI1_IN11 */
+#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 12)   /* XBARB2_OUT12 output assigned to AOI1_IN12 */
+#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 13)   /* XBARB2_OUT13 output assigned to AOI1_IN13 */
+#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 14)   /* XBARB2_OUT14 output assigned to AOI1_IN14 */
+#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 15)   /* XBARB2_OUT15 output assigned to AOI1_IN15 */
+
+/* XBARB3 Mux inputs (I values) *******************************************************************************************************************/
+
+#define IMXRT_XBARB3_IN_LOGIC_LOW                        IMXRT_XBARB3(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARB3_IN0 input. */
+#define IMXRT_XBARB3_IN_LOGIC_HIGH                       IMXRT_XBARB3(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARB3_IN1 input. */
+#define IMXRT_XBARB3_IN_RESERVED2                        IMXRT_XBARB3(XBAR_INPUT, 2)    /* XBARB3_IN2 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED3                        IMXRT_XBARB3(XBAR_INPUT, 3)    /* XBARB3_IN3 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED4                        IMXRT_XBARB3(XBAR_INPUT, 4)    /* XBARB3_IN4 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED5                        IMXRT_XBARB3(XBAR_INPUT, 5)    /* XBARB3_IN5 input is reserved. */
+#define IMXRT_XBARB3_IN_ACMP1_OUT                        IMXRT_XBARB3(XBAR_INPUT, 6)    /* ACMP1_OUT output assigned to XBARB3_IN6 input. */
+#define IMXRT_XBARB3_IN_ACMP2_OUT                        IMXRT_XBARB3(XBAR_INPUT, 7)    /* ACMP2_OUT output assigned to XBARB3_IN7 input. */
+#define IMXRT_XBARB3_IN_ACMP3_OUT                        IMXRT_XBARB3(XBAR_INPUT, 8)    /* ACMP3_OUT output assigned to XBARB3_IN8 input. */
+#define IMXRT_XBARB3_IN_ACMP4_OUT                        IMXRT_XBARB3(XBAR_INPUT, 9)    /* ACMP4_OUT output assigned to XBARB3_IN9 input. */
+#define IMXRT_XBARB3_IN_RESERVED10                       IMXRT_XBARB3(XBAR_INPUT, 10)   /* XBARB3_IN10 input is reserved. */
+#define IMXRT_XBARB3_IN_RESERVED11                       IMXRT_XBARB3(XBAR_INPUT, 11)   /* XBARB3_IN11 input is reserved. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARB3(XBAR_INPUT, 12)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARB3(XBAR_INPUT, 13)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARB3(XBAR_INPUT, 14)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */
+#define IMXRT_XBARB3_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARB3(XBAR_INPUT, 15)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARB3(XBAR_INPUT, 16)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARB3(XBAR_INPUT, 17)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARB3(XBAR_INPUT, 18)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */
+#define IMXRT_XBARB3_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARB3(XBAR_INPUT, 19)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 28)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 29)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 30)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 31)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 32)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 33)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 34)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
+#define IMXRT_XBARB3_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 35)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
+#define IMXRT_XBARB3_IN_PIT_TRIGGER0                     IMXRT_XBARB3(XBAR_INPUT, 36)   /* PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */
+#define IMXRT_XBARB3_IN_PIT_TRIGGER1                     IMXRT_XBARB3(XBAR_INPUT, 37)   /* PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARB3(XBAR_INPUT, 38)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARB3(XBAR_INPUT, 39)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARB3(XBAR_INPUT, 40)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARB3(XBAR_INPUT, 41)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARB3(XBAR_INPUT, 42)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARB3(XBAR_INPUT, 43)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARB3(XBAR_INPUT, 44)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */
+#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARB3(XBAR_INPUT, 45)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */
+#define IMXRT_XBARB3_IN_ENC1_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 46)   /* ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */
+#define IMXRT_XBARB3_IN_ENC2_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 47)   /* ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */
+#define IMXRT_XBARB3_IN_ENC3_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 48)   /* ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */
+#define IMXRT_XBARB3_IN_ENC4_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 49)   /* ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE0                        IMXRT_XBARB3(XBAR_INPUT, 50)   /* DMA_DONE0 output assigned to XBARB3_IN50 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE1                        IMXRT_XBARB3(XBAR_INPUT, 51)   /* DMA_DONE1 output assigned to XBARB3_IN51 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE2                        IMXRT_XBARB3(XBAR_INPUT, 52)   /* DMA_DONE2 output assigned to XBARB3_IN52 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE3                        IMXRT_XBARB3(XBAR_INPUT, 53)   /* DMA_DONE3 output assigned to XBARB3_IN53 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE4                        IMXRT_XBARB3(XBAR_INPUT, 54)   /* DMA_DONE4 output assigned to XBARB3_IN54 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE5                        IMXRT_XBARB3(XBAR_INPUT, 55)   /* DMA_DONE5 output assigned to XBARB3_IN55 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE6                        IMXRT_XBARB3(XBAR_INPUT, 56)   /* DMA_DONE6 output assigned to XBARB3_IN56 input. */
+#define IMXRT_XBARB3_IN_DMA_DONE7                        IMXRT_XBARB3(XBAR_INPUT, 57)   /* DMA_DONE7 output assigned to XBARB3_IN57 input. */
+
+/* XBARB3 Mux Output  (M Muxes) ********************************************************************************************************************/
+
+#define IMXRT_XBARB3_OUT_AOI2_IN00_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 0)    /* XBARB3_OUT0 output assigned to AOI2_IN00 */
+#define IMXRT_XBARB3_OUT_AOI2_IN01_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 1)    /* XBARB3_OUT1 output assigned to AOI2_IN01 */
+#define IMXRT_XBARB3_OUT_AOI2_IN02_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 2)    /* XBARB3_OUT2 output assigned to AOI2_IN02 */
+#define IMXRT_XBARB3_OUT_AOI2_IN03_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 3)    /* XBARB3_OUT3 output assigned to AOI2_IN03 */
+#define IMXRT_XBARB3_OUT_AOI2_IN04_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 4)    /* XBARB3_OUT4 output assigned to AOI2_IN04 */
+#define IMXRT_XBARB3_OUT_AOI2_IN05_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 5)    /* XBARB3_OUT5 output assigned to AOI2_IN05 */
+#define IMXRT_XBARB3_OUT_AOI2_IN06_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 6)    /* XBARB3_OUT6 output assigned to AOI2_IN06 */
+#define IMXRT_XBARB3_OUT_AOI2_IN07_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 7)    /* XBARB3_OUT7 output assigned to AOI2_IN07 */
+#define IMXRT_XBARB3_OUT_AOI2_IN08_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 8)    /* XBARB3_OUT8 output assigned to AOI2_IN08 */
+#define IMXRT_XBARB3_OUT_AOI2_IN09_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 9)    /* XBARB3_OUT9 output assigned to AOI2_IN09 */
+#define IMXRT_XBARB3_OUT_AOI2_IN10_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 10)   /* XBARB3_OUT10 output assigned to AOI2_IN10 */
+#define IMXRT_XBARB3_OUT_AOI2_IN11_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 11)   /* XBARB3_OUT11 output assigned to AOI2_IN11 */
+#define IMXRT_XBARB3_OUT_AOI2_IN12_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 12)   /* XBARB3_OUT12 output assigned to AOI2_IN12 */
+#define IMXRT_XBARB3_OUT_AOI2_IN13_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 13)   /* XBARB3_OUT13 output assigned to AOI2_IN13 */
+#define IMXRT_XBARB3_OUT_AOI2_IN14_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 14)   /* XBARB3_OUT14 output assigned to AOI2_IN14 */
+#define IMXRT_XBARB3_OUT_AOI2_IN15_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 15)   /* XBARB3_OUT15 output assigned to AOI2_IN15 */
diff --git a/arch/arm/src/imxrt/imxrt102x_daisy.c b/arch/arm/src/imxrt/imxrt102x_daisy.c
new file mode 100644
index 00000000000..8d802651e7d
--- /dev/null
+++ b/arch/arm/src/imxrt/imxrt102x_daisy.c
@@ -0,0 +1,5419 @@
+/****************************************************************************
+ * arch/arm/src/imxrt/imxrt106x_daisy.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Dave Marples 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/*  Based on chip selection this file is included in imxrt_daisy.c */
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct imxrt_daisy_t g_daisy_select[] =
+{
+  /* index:0 GPIO_EMC_00 */
+
+  {
+    {
+      /* Index:0 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:0 Alt:1  GPIO EMC 00 QTIMER2 TIMER0 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER0_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:0 Alt:2  GPIO EMC 00 LPUART4 CTS B */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_CTS_B_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:0 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:0 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:0 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:0 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:0 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:0 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:0 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:1 GPIO_EMC_01 */
+
+  {
+    {
+      /* Index:1 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:1 Alt:1  GPIO EMC 01 QTIMER2 TIMER1 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER1_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:1 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:1 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:1 Alt:4  GPIO EMC 01 LPSPI2 PCS0 */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_PCS0_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:1 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:1 Alt:6  GPIO EMC 01 FLEXCAN1 RX */
+
+      [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET),
+      [ALT6].sel   = 0,
+
+      /* Index:1 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:1 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:1 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:2 GPIO_EMC_02 */
+
+  {
+    {
+      /* Index:2 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:2 Alt:1  GPIO EMC 02 QTIMER2 TIMER2 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER2_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:2 Alt:2  GPIO EMC 02 LPUART4 TX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_TX_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:2 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:2 Alt:4  GPIO EMC 02 LPSPI2 SDO */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_SDO_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:2 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:2 Alt:6  GPIO EMC 02 LPI2C1 SCL */
+
+      [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C1_SCL_OFFSET),
+      [ALT6].sel   = 0,
+
+      /* Index:2 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:2 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:2 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:3 GPIO_EMC_03 */
+
+  {
+    {
+      /* Index:3 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:3 Alt:1  GPIO EMC 03 QTIMER2 TIMER3 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER3_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:3 Alt:2  GPIO EMC 03 LPUART4 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_RX_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:3 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:3 Alt:4  GPIO EMC 03 LPSPI2 SDI */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_SDI_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:3 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:3 Alt:6  GPIO EMC 03 LPI2C1 SDA */
+
+      [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C1_SDA_OFFSET),
+      [ALT6].sel   = 0,
+
+      /* Index:3 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:3 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:3 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:4 GPIO_EMC_04 */
+
+  {
+    {
+      /* Index:4 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:4 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:4 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:4 Alt:3  GPIO EMC 04 SAI2 TX BCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_BCLK_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:4 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:4 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:4 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:4 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:4 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:4 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:5 GPIO_EMC_05 */
+
+  {
+    {
+      /* Index:5 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:5 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:5 Alt:2  GPIO EMC 05 SPDIF IN */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SPDIF_IN_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:5 Alt:3  GPIO EMC 05 SAI2 TX SYNC */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_SYNC_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:5 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:5 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:5 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:5 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:5 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:5 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:6 GPIO_EMC_06 */
+
+  {
+    {
+      /* Index:6 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:6 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:6 Alt:2  GPIO EMC 06 LPUART3 TX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_TX_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:6 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:6 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:6 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:6 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:6 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:6 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:6 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:7 GPIO_EMC_07 */
+
+  {
+    {
+      /* Index:7 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:7 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:7 Alt:2  GPIO EMC 07 LPUART3 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_RX_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:7 Alt:3  GPIO EMC 07 SAI2 RX SYNC */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_SYNC_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:7 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:7 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:7 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:7 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:7 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:7 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:8 GPIO_EMC_08 */
+
+  {
+    {
+      /* Index:8 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:8 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:8 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:8 Alt:3  GPIO EMC 08 SAI2 RX DATA */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_DATA0_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:8 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:8 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:8 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:8 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:8 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:8 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:9 GPIO_EMC_09 */
+
+  {
+    {
+      /* Index:9 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:9 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:9 Alt:2  GPIO EMC 09 FLEXCAN2 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:9 Alt:3  GPIO EMC 09 SAI2 RX BCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_BCLK_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:9 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:9 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:9 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:9 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:9 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:9 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:10 GPIO_EMC_10 */
+
+  {
+    {
+      /* Index:10 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:10 Alt:1  GPIO EMC 10 XBAR1 INOUT10 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN10_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:10 Alt:2  GPIO EMC 10 LPI2C4 SDA */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C4_SDA_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:10 Alt:3  GPIO EMC 10 SAI1 TX SYNC */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:10 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:10 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:10 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:10 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:10 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:10 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:11 GPIO_EMC_11 */
+
+  {
+    {
+      /* Index:11 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:11 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:11 Alt:2  GPIO EMC 11 LPI2C4 SCL */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C4_SCL_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:11 Alt:3  GPIO EMC 11 SAI1 TX BCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:11 Alt:4  GPIO EMC 11 LPSPI2 PCS0 */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_PCS0_OFFSET),
+      [ALT4].sel   = 1,
+
+      /* Index:11 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:11 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:11 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:11 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:11 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:12 GPIO_EMC_12 */
+
+  {
+    {
+      /* Index:12 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:12 Alt:1  GPIO EMC 12 XBAR1 INOUT12 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN12_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:12 Alt:2  GPIO EMC 12 LPUART6 TX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART6_TX_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:12 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:12 Alt:4  GPIO EMC 12 LPSPI2 SDO */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_SDO_OFFSET),
+      [ALT4].sel   = 1,
+
+      /* Index:12 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:12 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:12 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:12 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:12 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:13 GPIO_EMC_13 */
+
+  {
+    {
+      /* Index:13 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:13 Alt:1  GPIO EMC 13 XBAR1 INOUT13 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN13_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:13 Alt:2  GPIO EMC 13 LPUART6 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART6_RX_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:13 Alt:3  GPIO EMC 13 SAI1 RX DATA00 */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:13 Alt:4  GPIO EMC 13 LPSPI2 SDI */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_SDI_OFFSET),
+      [ALT4].sel   = 1,
+
+      /* Index:13 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:13 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:13 Alt:7  GPIO EMC 13 CCM PMIC RDY */
+
+      [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET),
+      [ALT7].sel   = 0,
+
+      /* Index:13 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:13 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:14 GPIO_EMC_14 */
+
+  {
+    {
+      /* Index:14 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:14 Alt:1  GPIO EMC 14 XBAR1 INOUT14 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN14_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:14 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:14 Alt:3  GPIO EMC 14 SAI1 RX BCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:14 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:14 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:14 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:14 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:14 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:14 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:15 GPIO_EMC_15 */
+
+  {
+    {
+      /* Index:15 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:15 Alt:1  GPIO EMC 15 XBAR1 INOUT15 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN15_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:15 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:15 Alt:3  GPIO EMC 15 SAI1 RX SYNC */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:15 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:15 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:15 Alt:6  GPIO EMC 15 FLEXCAN1 RX */
+
+      [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET),
+      [ALT6].sel   = 3,
+
+      /* Index:15 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:15 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:15 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:16 GPIO_EMC_16 */
+
+  {
+    {
+      /* Index:16 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:16 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:16 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:16 Alt:3  GPIO EMC 16 SAI2 MCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_MCLK_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:16 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:16 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:16 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:16 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:16 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:16 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:17 GPIO_EMC_17 */
+
+  {
+    {
+      /* Index:17 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:17 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:17 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:17 Alt:3  GPIO EMC 17 SAI3 MCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_MCLK_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:17 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:17 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:17 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:17 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:17 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:17 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:18 GPIO_EMC_18 */
+
+  {
+    {
+      /* Index:18 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:18 Alt:1  GPIO EMC 18 XBAR1 INOUT16 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN16_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:18 Alt:2  GPIO EMC 18 LPI2C2 SDA */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SDA_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:18 Alt:3  GPIO EMC 18 SAI1 RX SYNC */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET),
+      [ALT3].sel   = 2,
+
+      /* Index:18 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:18 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:18 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:18 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:18 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:18 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:19 GPIO_EMC_19 */
+
+  {
+    {
+      /* Index:19 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:19 Alt:1  GPIO EMC 19 XBAR1 INOUT17 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN17_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:19 Alt:2  GPIO EMC 19 LPI2C2 SCL */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SCL_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:19 Alt:3  GPIO EMC 19 SAI1 RX BCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET),
+      [ALT3].sel   = 2,
+
+      /* Index:19 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:19 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:19 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:19 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:19 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:19 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:20 GPIO_EMC_20 */
+
+  {
+    {
+      /* Index:20 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:20 Alt:1  GPIO EMC 20 FLEXPWM1 PWMA03 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:20 Alt:2  GPIO EMC 20 LPUART2 CTS B */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_CTS_B_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:20 Alt:3  GPIO EMC 20 SAI1 MCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_MCLK_OFFSET),
+      [ALT3].sel   = 3,
+
+      /* Index:20 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:20 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:20 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:20 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:20 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:20 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:21 GPIO_EMC_21 */
+
+  {
+    {
+      /* Index:21 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:21 Alt:1  GPIO EMC 21 FLEXPWM1 PWMB03 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:21 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:21 Alt:3  GPIO EMC 21 SAI1 RX DATA00 */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET),
+      [ALT3].sel   = 2,
+
+      /* Index:21 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:21 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:21 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:21 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:21 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:21 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:22 GPIO_EMC_22 */
+
+  {
+    {
+      /* Index:22 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:22 Alt:1  GPIO EMC 22 FLEXPWM1 PWMA02 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:22 Alt:2  GPIO EMC 22 LPUART2 TX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_TX_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:22 Alt:3  GPIO EMC 22 SAI1 TX DATA03 */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA1_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:22 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:22 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:22 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:22 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:22 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:22 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:23 GPIO_EMC_23 */
+
+  {
+    {
+      /* Index:23 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:23 Alt:1  GPIO EMC 23 FLEXPWM1 PWMB02 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:23 Alt:2  GPIO EMC 23 LPUART2 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_RX_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:23 Alt:3  GPIO EMC 23 SAI1 TX DATA02 */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA2_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:23 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:23 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:23 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:23 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:23 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:23 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:24 GPIO_EMC_24 */
+
+  {
+    {
+      /* Index:24 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:24 Alt:1  GPIO EMC 24 FLEXPWM1 PWMA01 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:24 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:24 Alt:3  GPIO EMC 24 SAI1 TX DATA01 */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA3_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:24 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:24 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:24 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:24 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:24 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:24 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:25 GPIO_EMC_25 */
+
+  {
+    {
+      /* Index:25 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:25 Alt:1  GPIO EMC 25 FLEXPWM1 PWMB01 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:25 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:25 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:25 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:25 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:25 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:25 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:25 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:25 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:26 GPIO_EMC_26 */
+
+  {
+    {
+      /* Index:26 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:26 Alt:1  GPIO EMC 26 FLEXPWM1 PWMA00 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:26 Alt:2  GPIO EMC 26 LPUART8 TX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_TX_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:26 Alt:3  GPIO EMC 26 SAI1 TX BCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET),
+      [ALT3].sel   = 2,
+
+      /* Index:26 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:26 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:26 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:26 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:26 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:26 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:27 GPIO_EMC_27 */
+
+  {
+    {
+      /* Index:27 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:27 Alt:1  GPIO EMC 27 FLEXPWM1 PWMB00 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:27 Alt:2  GPIO EMC 27 LPUART8 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_RX_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:27 Alt:3  GPIO EMC 27 SAI1 TX SYNC */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET),
+      [ALT3].sel   = 2,
+
+      /* Index:27 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:27 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:27 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:27 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:27 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:27 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:28 GPIO_EMC_28 */
+
+  {
+    {
+      /* Index:28 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:28 Alt:1  GPIO EMC 28 FLEXPWM2 PWMA03 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:28 Alt:2  GPIO EMC 28 XBAR1 INOUT18 */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN18_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:28 Alt:3  GPIO EMC 28 SAI3 MCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_MCLK_OFFSET),
+      [ALT3].sel   = 2,
+
+      /* Index:28 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:28 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:28 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:28 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:28 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:28 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:29 GPIO_EMC_29 */
+
+  {
+    {
+      /* Index:29 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:29 Alt:1  GPIO EMC 29 FLEXPWM2 PWMB03 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:29 Alt:2  GPIO EMC 29 XBAR1 INOUT19 */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN19_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:29 Alt:3  GPIO EMC 29 SAI3 RX BCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_RX_BCLK_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:29 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:29 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:29 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:29 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:29 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:29 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:30 GPIO_EMC_30 */
+
+  {
+    {
+      /* Index:30 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:30 Alt:1  GPIO EMC 30 FLEXPWM2 PWMA02 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:30 Alt:2  GPIO EMC 30 LPUART4 CTS B */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_CTS_B_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:30 Alt:3  GPIO EMC 30 SAI3 RX SYNC */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_RX_SYNC_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:30 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:30 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:30 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:30 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:30 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:30 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:31 GPIO_EMC_31 */
+
+  {
+    {
+      /* Index:31 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:31 Alt:1  GPIO EMC 31 FLEXPWM2 PWMB02 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:31 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:31 Alt:3  GPIO EMC 31 SAI3 RX DATA */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_RX_DATA0_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:31 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:31 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:31 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:31 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:31 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:31 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:32 GPIO_EMC_32 */
+
+  {
+    {
+      /* Index:32 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:32 Alt:1  GPIO EMC 32 QTIMER1 TIMER0 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER0_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:32 Alt:2  GPIO EMC 32 LPUART4 TX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_TX_OFFSET),
+      [ALT2].sel   = 2,
+
+      /* Index:32 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:32 Alt:4  GPIO EMC 32 LPSPI4 SCK */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SCK_OFFSET),
+      [ALT4].sel   = 1,
+
+      /* Index:32 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:32 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:32 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:32 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:32 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:33 GPIO_EMC_33 */
+
+  {
+    {
+      /* Index:33 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:33 Alt:1  GPIO EMC 33 QTIMER1 TIMER1 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER1_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:33 Alt:2  GPIO EMC 33 LPUART4 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_RX_OFFSET),
+      [ALT2].sel   = 2,
+
+      /* Index:33 Alt:3  GPIO EMC 33 SAI3 TX BCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_TX_BCLK_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:33 Alt:4  GPIO EMC 33 LPSPI4 PCS0 */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_PCS0_OFFSET),
+      [ALT4].sel   = 1,
+
+      /* Index:33 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:33 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:33 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:33 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:33 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:34 GPIO_EMC_34 */
+
+  {
+    {
+      /* Index:34 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:34 Alt:1  GPIO EMC 34 QTIMER1 TIMER2 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER2_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:34 Alt:2  GPIO EMC 34 LPUART7 TX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART7_TX_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:34 Alt:3  GPIO EMC 34 SAI3 TX SYNC */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_TX_SYNC_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:34 Alt:4  GPIO EMC 34 LPSPI4 SDO */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDO_OFFSET),
+      [ALT4].sel   = 1,
+
+      /* Index:34 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:34 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:34 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:34 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:34 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:35 GPIO_EMC_35 */
+
+  {
+    {
+      /* Index:35 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:35 Alt:1  GPIO EMC 35 QTIMER1 TIMER3 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER3_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:35 Alt:2  GPIO EMC 35 LPUART7 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART7_RX_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:35 Alt:3  GPIO EMC 35 USDHC2 WP */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CMD_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:35 Alt:4  GPIO EMC 35 LPSPI4 SDI */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDI_OFFSET),
+      [ALT4].sel   = 1,
+
+      /* Index:35 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:35 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:35 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:35 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:35 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:36 GPIO_EMC_36 */
+
+  {
+    {
+      /* Index:36 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:36 Alt:1  GPIO EMC 36 FLEXPWM2 PWMA01 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:36 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:36 Alt:3  GPIO EMC 36 CCM PMIC RDY */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET),
+      [ALT3].sel   = 3,
+
+      /* Index:36 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:36 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:36 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:36 Alt:7  GPIO EMC 36 USDHC1 WP */
+
+      [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_WP_OFFSET),
+      [ALT7].sel   = 4,
+
+      /* Index:36 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:36 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:37 GPIO_EMC_37 */
+
+  {
+    {
+      /* Index:37 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:37 Alt:1  GPIO EMC 37 FLEXPWM2 PWMB01 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:37 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:37 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:37 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:37 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:37 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:37 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:37 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:37 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:38 GPIO_EMC_38 */
+
+  {
+    {
+      /* Index:38 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:38 Alt:1  GPIO EMC 38 FLEXPWM2 PWMA00 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:38 Alt:2  GPIO EMC 38 LPUART5 TX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART5_TX_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:38 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:38 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:38 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:38 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:38 Alt:7  GPIO EMC 38 USDHC1 CD B */
+
+      [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET),
+      [ALT7].sel   = 3,
+
+      /* Index:38 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:38 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:39 GPIO_EMC_39 */
+
+  {
+    {
+      /* Index:39 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:39 Alt:1  GPIO EMC 39 FLEXPWM2 PWMB00 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:39 Alt:2  GPIO EMC 39 LPUART5 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART5_RX_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:39 Alt:3  GPIO EMC 39 USB OTG1 OC */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG1_OC_OFFSET),
+      [ALT3].sel   = 2,
+
+      /* Index:39 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:39 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:39 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:39 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:39 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:39 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:40 GPIO_EMC_40 */
+
+  {
+    {
+      /* Index:40 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:40 Alt:1  GPIO EMC 40 XBAR1 INOUT18 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN18_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:40 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:40 Alt:3  GPIO EMC 40 USB OTG1 ID */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET),
+      [ALT3].sel   = 2,
+
+      /* Index:40 Alt:4  GPIO EMC 40 ENET MDIO */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_MDIO_OFFSET),
+      [ALT4].sel   = 2,
+
+      /* Index:40 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:40 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:40 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:40 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:40 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:41 GPIO_EMC_41 */
+
+  {
+    {
+      /* Index:41 Alt:0  GPIO EMC 41 SEMC READY */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SEMC_READY_OFFSET),
+      [ALT0].sel   = 1,
+
+      /* Index:41 Alt:1  GPIO EMC 41 XBAR1 INOUT19 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN19_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:41 Alt:2  GPIO EMC 41 SPDIF IN */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SPDIF_IN_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:41 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:41 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:41 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:41 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:41 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:41 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:41 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:42 GPIO_AD_B0_00 */
+
+  {
+    {
+      /* Index:42 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:42 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:42 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:42 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:42 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:42 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:42 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:42 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:42 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:42 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:43 GPIO_AD_B0_01 */
+
+  {
+    {
+      /* Index:43 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:43 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:43 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:43 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:43 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:43 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:43 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:43 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:43 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:43 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:44 GPIO_AD_B0_02 */
+
+  {
+    {
+      /* Index:44 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:44 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:44 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:44 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:44 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:44 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:44 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:44 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:44 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:44 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:45 GPIO_AD_B0_03 */
+
+  {
+    {
+      /* Index:45 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:45 Alt:1  GPIO AD B0 03 USDHC2 CD B */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CD_B_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:45 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:45 Alt:3  GPIO AD B0 03 SAI1 MCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_MCLK_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:45 Alt:4  GPIO AD B0 03 USDHC1 WP */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_WP_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:45 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:45 Alt:6  GPIO AD B0 03 USB OTG1 OC */
+
+      [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG1_OC_OFFSET),
+      [ALT6].sel   = 0,
+
+      /* Index:45 Alt:7  GPIO AD B0 03 CCM PMIC RDY */
+
+      [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET),
+      [ALT7].sel   = 2,
+
+      /* Index:45 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:45 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:46 GPIO_AD_B0_04 */
+
+  {
+    {
+      /* Index:46 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:46 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:46 Alt:2  GPIO AD B0 04 USDHC1 WP */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_WP_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:46 Alt:3  GPIO AD B0 04 QTIMER2 TIMER0 */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER0_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:46 Alt:4  GPIO AD B0 04 ENET MDIO */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_MDIO_OFFSET),
+      [ALT4].sel   = 1,
+
+      /* Index:46 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:46 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:46 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:46 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:46 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:47 GPIO_AD_B0_05 */
+
+  {
+    {
+      /* Index:47 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:47 Alt:1  GPIO AD B0 05 FLEXCAN1 RX */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET),
+      [ALT1].sel   = 2,
+
+      /* Index:47 Alt:2  GPIO AD B0 05 USDHC1 CD B */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:47 Alt:3  GPIO AD B0 05 QTIMER2 TIMER1 */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER1_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:47 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:47 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:47 Alt:6  GPIO AD B0 05 USB OTG1 ID */
+
+      [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET),
+      [ALT6].sel   = 0,
+
+      /* Index:47 Alt:7  GPIO AD B0 05 NMI GLUE NMI */
+
+      [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_NMI_GLUE_NMI_OFFSET),
+      [ALT7].sel   = 0,
+
+      /* Index:47 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:47 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:48 GPIO_AD_B0_06 */
+
+  {
+    {
+      /* Index:48 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:48 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:48 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:48 Alt:3  GPIO AD B0 06 QTIMER2 TIMER2 */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER2_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:48 Alt:4  GPIO AD B0 06 FLEXPWM2 PWMA03 */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:48 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:48 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:48 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:48 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:48 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:49 GPIO_AD_B0_07 */
+
+  {
+    {
+      /* Index:49 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:49 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:49 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:49 Alt:3  GPIO AD B0 07 QTIMER2 TIMER3 */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER2_TIMER3_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:49 Alt:4  GPIO AD B0 07 FLEXPWM2 PWMB03 */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:49 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:49 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:49 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:49 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:49 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:50 GPIO_AD_B0_08 */
+
+  {
+    {
+      /* Index:50 Alt:0  GPIO AD B0 08 ENET TX CLK */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_TXCLK_OFFSET),
+      [ALT0].sel   = 1,
+
+      /* Index:50 Alt:1  GPIO AD B0 08 LPI2C3 SCL */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SCL_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:50 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:50 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:50 Alt:4  GPIO AD B0 08 ENET REF CLK1 */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET),
+      [ALT4].sel   = 1,
+
+      /* Index:50 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:50 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:50 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:50 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:50 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:51 GPIO_AD_B0_09 */
+
+  {
+    {
+      /* Index:51 Alt:0  GPIO AD B0 09 ENET RDATA01 */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXDATA1_OFFSET),
+      [ALT0].sel   = 1,
+
+      /* Index:51 Alt:1  GPIO AD B0 09 LPI2C3 SDA */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SDA_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:51 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:51 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:51 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:51 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:51 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:51 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:51 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:51 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:52 GPIO_AD_B0_10 */
+
+  {
+    {
+      /* Index:52 Alt:0  GPIO AD B0 10 ENET RDATA00 */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXDATA0_OFFSET),
+      [ALT0].sel   = 1,
+
+      /* Index:52 Alt:1  GPIO AD B0 10 LPSPI1 SCK */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SCK_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:52 Alt:2  GPIO AD B0 10 LPUART5 TX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART5_TX_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:52 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:52 Alt:4  GPIO AD B0 10 FLEXPWM2 PWMA02 */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:52 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:52 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:52 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:52 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:52 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:53 GPIO_AD_B0_11 */
+
+  {
+    {
+      /* Index:53 Alt:0  GPIO AD B0 11 ENET RX EN */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXEN_OFFSET),
+      [ALT0].sel   = 1,
+
+      /* Index:53 Alt:1  GPIO AD B0 11 LPSPI1 PCS0 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_PCS0_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:53 Alt:2  GPIO AD B0 11 LPUART5 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART5_RX_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:53 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:53 Alt:4  GPIO AD B0 11 FLEXPWM2 PWMB02 */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:53 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:53 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:53 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:53 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:53 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:54 GPIO_AD_B0_12 */
+
+  {
+    {
+      /* Index:54 Alt:0  GPIO AD B0 12 ENET RX ER */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXERR_OFFSET),
+      [ALT0].sel   = 1,
+
+      /* Index:54 Alt:1  GPIO AD B0 12 LPSPI1 SDO */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SDO_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:54 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:54 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:54 Alt:4  GPIO AD B0 12 FLEXPWM2 PWMA01 */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:54 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:54 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:54 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:54 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:54 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:55 GPIO_AD_B0_13 */
+
+  {
+    {
+      /* Index:55 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:55 Alt:1  GPIO AD B0 13 LPSPI1 SDI */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SDI_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:55 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:55 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:55 Alt:4  GPIO AD B0 13 FLEXPWM2 PWMB01 */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:55 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:55 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:55 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:55 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:55 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:56 GPIO_AD_B0_14 */
+
+  {
+    {
+      /* Index:56 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:56 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:56 Alt:2  GPIO AD B0 14 LPUART3 TX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_TX_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:56 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:56 Alt:4  GPIO AD B0 14 FLEXPWM2 PWMA00 */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:56 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:56 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:56 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:56 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:56 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:57 GPIO_AD_B0_15 */
+
+  {
+    {
+      /* Index:57 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:57 Alt:1  GPIO AD B0 15 FLEXCAN2 RX */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET),
+      [ALT1].sel   = 2,
+
+      /* Index:57 Alt:2  GPIO AD B0 15 LPUART3 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_RX_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:57 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:57 Alt:4  GPIO AD B0 15 FLEXPWM2 PWMB00 */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:57 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:57 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:57 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:57 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:57 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:58 GPIO_AD_B1_00 */
+
+  {
+    {
+      /* Index:58 Alt:0  GPIO AD B1 00 SEMC READY */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SEMC_READY_OFFSET),
+      [ALT0].sel   = 0,
+
+      /* Index:58 Alt:1  GPIO AD B1 00 FLEXSPI A DATA03 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:58 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:58 Alt:3  GPIO AD B1 00 SAI1 MCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_MCLK_OFFSET),
+      [ALT3].sel   = 2,
+
+      /* Index:58 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:58 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:58 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:58 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:58 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:58 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:59 GPIO_AD_B1_01 */
+
+  {
+    {
+      /* Index:59 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:59 Alt:1  GPIO AD B1 01 FLEXSPI A SCLK */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_SCK_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:59 Alt:2  GPIO AD B1 01 FLEXCAN2 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET),
+      [ALT2].sel   = 3,
+
+      /* Index:59 Alt:3  GPIO AD B1 01 SAI1 TX BCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_BCLK_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:59 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:59 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:59 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:59 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:59 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:59 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:60 GPIO_AD_B1_02 */
+
+  {
+    {
+      /* Index:60 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:60 Alt:1  GPIO AD B1 02 FLEXSPI A DATA00 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:60 Alt:2  GPIO AD B1 02 LPSPI4 SCK */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SCK_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:60 Alt:3  GPIO AD B1 02 SAI1 TX SYNC */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_TX_SYNC_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:60 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:60 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:60 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:60 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:60 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:60 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:61 GPIO_AD_B1_03 */
+
+  {
+    {
+      /* Index:61 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:61 Alt:1  GPIO AD B1 03 FLEXSPI A DATA02 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:61 Alt:2  GPIO AD B1 03 LPSPI4 PCS0 */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_PCS0_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:61 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:61 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:61 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:61 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:61 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:61 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:61 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:62 GPIO_AD_B1_04 */
+
+  {
+    {
+      /* Index:62 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:62 Alt:1  GPIO AD B1 04 FLEXSPI A DATA01 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET),
+      [ALT1].sel   = 1,
+
+      /* Index:62 Alt:2  GPIO AD B1 04 LPSPI4 SDO */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDO_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:62 Alt:3  GPIO AD B1 04 SAI1 RX SYNC */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_SYNC_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:62 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:62 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:62 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:62 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:62 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:62 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:63 GPIO_AD_B1_05 */
+
+  {
+    {
+      /* Index:63 Alt:0  GPIO AD B1 05 USDHC1 WP */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_WP_OFFSET),
+      [ALT0].sel   = 2,
+
+      /* Index:63 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:63 Alt:2  GPIO AD B1 05 LPSPI4 SDI */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI4_SDI_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:63 Alt:3  GPIO AD B1 05 SAI1 RX DATA00 */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA0_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:63 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:63 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:63 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:63 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:63 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:63 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:64 GPIO_AD_B1_06 */
+
+  {
+    {
+      /* Index:64 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:64 Alt:1  GPIO AD B1 06 FLEXPWM1 PWMA00 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:64 Alt:2  GPIO AD B1 06 LPUART2 CTS B */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART3_CTS_B_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:64 Alt:3  GPIO AD B1 06 SAI1 RX BCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_BCLK_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:64 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:64 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:64 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:64 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:64 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:64 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:65 GPIO_AD_B1_07 */
+
+  {
+    {
+      /* Index:65 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:65 Alt:1  GPIO AD B1 07 FLEXPWM1 PWMB00 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:65 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:65 Alt:3  GPIO AD B1 07 SAI1 TX DATA01 */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA3_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:65 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:65 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:65 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:65 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:65 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:65 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:66 GPIO_AD_B1_08 */
+
+  {
+    {
+      /* Index:66 Alt:0  GPIO AD B1 08 LPI2C2 SCL */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SCL_OFFSET),
+      [ALT0].sel   = 0,
+
+      /* Index:66 Alt:1  GPIO AD B1 08 FLEXPWM1 PWMA01 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:66 Alt:2  GPIO AD B1 08 LPUART2 TX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_TX_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:66 Alt:3  GPIO AD B1 08 SAI1 TX DATA02 */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA2_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:66 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:66 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:66 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:66 Alt:7  GPIO AD B1 08 XBAR1 INOUT12 */
+
+      [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN12_OFFSET),
+      [ALT7].sel   = 1,
+
+      /* Index:66 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:66 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:67 GPIO_AD_B1_09 */
+
+  {
+    {
+      /* Index:67 Alt:0  GPIO AD B1 09 LPI2C2 SDA */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C2_SDA_OFFSET),
+      [ALT0].sel   = 0,
+
+      /* Index:67 Alt:1  GPIO AD B1 09 FLEXPWM1 PWMB01 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:67 Alt:2  GPIO AD B1 09 LPUART2 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART2_RX_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:67 Alt:3  GPIO AD B1 09 SAI1 TX DATA03 */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_RX_DATA1_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:67 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:67 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:67 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:67 Alt:7  GPIO AD B1 09 XBAR1 INOUT13 */
+
+      [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN13_OFFSET),
+      [ALT7].sel   = 1,
+
+      /* Index:67 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:67 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:68 GPIO_AD_B1_10 */
+
+  {
+    {
+      /* Index:68 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:68 Alt:1  GPIO AD B1 10 FLEXPWM1 PWMA02 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:68 Alt:2  GPIO AD B1 10 LPUART4 TX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_TX_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:68 Alt:3  GPIO AD B1 10 USDHC1 CD B */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET),
+      [ALT3].sel   = 2,
+
+      /* Index:68 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:68 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:68 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:68 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:68 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:68 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:69 GPIO_AD_B1_11 */
+
+  {
+    {
+      /* Index:69 Alt:0  GPIO AD B1 11 USB OTG1 ID */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET),
+      [ALT0].sel   = 1,
+
+      /* Index:69 Alt:1  GPIO AD B1 11 FLEXPWM1 PWMB02 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:69 Alt:2  GPIO AD B1 11 LPUART4 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART4_RX_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:69 Alt:3  GPIO AD B1 11 USDHC1 WP */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_WP_OFFSET),
+      [ALT3].sel   = 3,
+
+      /* Index:69 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:69 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:69 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:69 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:69 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:69 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:70 GPIO_AD_B1_12 */
+
+  {
+    {
+      /* Index:70 Alt:0  GPIO AD B1 12 USB OTG1 OC */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USB_OTG1_OC_OFFSET),
+      [ALT0].sel   = 1,
+
+      /* Index:70 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:70 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:70 Alt:3  GPIO AD B1 12 USDHC2 CD B */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CD_B_OFFSET),
+      [ALT3].sel   = 2,
+
+      /* Index:70 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:70 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:70 Alt:6  GPIO AD B1 12 FLEXPWM1 PWMA03 */
+
+      [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET),
+      [ALT6].sel   = 0,
+
+      /* Index:70 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:70 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:70 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:71 GPIO_AD_B1_13 */
+
+  {
+    {
+      /* Index:71 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:71 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:71 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:71 Alt:3  GPIO AD B1 13 USDHC2 WP */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CMD_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:71 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:71 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:71 Alt:6  GPIO AD B1 13 FLEXPWM1 PWMB03 */
+
+      [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET),
+      [ALT6].sel   = 0,
+
+      /* Index:71 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:71 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:71 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:72 GPIO_AD_B1_14 */
+
+  {
+    {
+      /* Index:72 Alt:0  GPIO AD B1 14 LPI2C1 SCL */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C1_SCL_OFFSET),
+      [ALT0].sel   = 1,
+
+      /* Index:72 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:72 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:72 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:72 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:72 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:72 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:72 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:72 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:72 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:73 GPIO_AD_B1_15 */
+
+  {
+    {
+      /* Index:73 Alt:0  GPIO AD B1 15 LPI2C1 SDA */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C1_SDA_OFFSET),
+      [ALT0].sel   = 1,
+
+      /* Index:73 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:73 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:73 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:73 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:73 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:73 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:73 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:73 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:73 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:74 GPIO_SD_B0_00 */
+
+  {
+    {
+      /* Index:74 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:74 Alt:1  GPIO SD B0 00 QTIMER1 TIMER0 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER0_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:74 Alt:2  GPIO SD B0 00 SAI1 MCLK */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI1_MCLK_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:74 Alt:3  GPIO SD B0 00 SAI2 MCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_MCLK_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:74 Alt:4  GPIO SD B0 00 LPI2C3 SCL */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SCL_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:74 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:74 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:74 Alt:7  GPIO SD B0 00 XBAR1 INOUT14 */
+
+      [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN14_OFFSET),
+      [ALT7].sel   = 0,
+
+      /* Index:74 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:74 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:75 GPIO_SD_B0_01 */
+
+  {
+    {
+      /* Index:75 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:75 Alt:1  GPIO SD B0 01 QTIMER1 TIMER1 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER1_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:75 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:75 Alt:3  GPIO SD B0 01 SAI2 RX SYNC */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_SYNC_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:75 Alt:4  GPIO SD B0 01 LPI2C3 SDA */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C3_SDA_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:75 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:75 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:75 Alt:7  GPIO SD B0 01 XBAR1 INOUT15 */
+
+      [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN15_OFFSET),
+      [ALT7].sel   = 0,
+
+      /* Index:75 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:75 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:76 GPIO_SD_B0_02 */
+
+  {
+    {
+      /* Index:76 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:76 Alt:1  GPIO SD B0 02 QTIMER1 TIMER2 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER2_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:76 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:76 Alt:3  GPIO SD B0 02 SAI2 RX BCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_BCLK_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:76 Alt:4  GPIO SD B0 02 LPSPI1 SCK */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SCK_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:76 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:76 Alt:6  GPIO SD B0 02 ENET MDIO */
+
+      [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_MDIO_OFFSET),
+      [ALT6].sel   = 0,
+
+      /* Index:76 Alt:7  GPIO SD B0 02 XBAR1 INOUT16 */
+
+      [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN16_OFFSET),
+      [ALT7].sel   = 0,
+
+      /* Index:76 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:76 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:77 GPIO_SD_B0_03 */
+
+  {
+    {
+      /* Index:77 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:77 Alt:1  GPIO SD B0 03 QTIMER1 TIMER3 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_QTIMER1_TIMER3_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:77 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:77 Alt:3  GPIO SD B0 03 SAI2 RX DATA */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_RX_DATA0_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:77 Alt:4  GPIO SD B0 03 LPSPI1 PCS0 */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_PCS0_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:77 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:77 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:77 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:77 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:77 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:78 GPIO_SD_B0_04 */
+
+  {
+    {
+      /* Index:78 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:78 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:78 Alt:2  GPIO SD B0 04 LPUART7 TX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART7_TX_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:78 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:78 Alt:4  GPIO SD B0 04 LPSPI1 SDO */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SDO_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:78 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:78 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:78 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:78 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:78 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:79 GPIO_SD_B0_05 */
+
+  {
+    {
+      /* Index:79 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:79 Alt:1  GPIO SD B0 05 FLEXCAN2 RX */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN2_RX_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:79 Alt:2  GPIO SD B0 05 LPUART7 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART7_RX_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:79 Alt:3  GPIO SD B0 05 SAI2 TX BCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_BCLK_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:79 Alt:4  GPIO SD B0 05 LPSPI1 SDI */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI1_SDI_OFFSET),
+      [ALT4].sel   = 0,
+
+      /* Index:79 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:79 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:79 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:79 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:79 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:80 GPIO_SD_B0_06 */
+
+  {
+    {
+      /* Index:80 Alt:0  GPIO SD B0 06 USDHC1 CD B */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC1_CD_B_OFFSET),
+      [ALT0].sel   = 0,
+
+      /* Index:80 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:80 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:80 Alt:3  GPIO SD B0 06 SAI2 TX SYNC */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI2_TX_SYNC_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:80 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:80 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:80 Alt:6  GPIO SD B0 06 XBAR1 INOUT17 */
+
+      [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN17_OFFSET),
+      [ALT6].sel   = 0,
+
+      /* Index:80 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:80 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:80 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:81 GPIO_SD_B1_00 */
+
+  {
+    {
+      /* Index:81 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:81 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:81 Alt:2  GPIO SD B1 00 LPUART6 TX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART6_TX_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:81 Alt:3  GPIO SD B1 00 XBAR1 INOUT10 */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_XBAR1_IN10_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:81 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:81 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:81 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:81 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:81 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:81 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:82 GPIO_SD_B1_01 */
+
+  {
+    {
+      /* Index:82 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:82 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:82 Alt:2  GPIO SD B1 01 LPUART6 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART6_RX_OFFSET),
+      [ALT2].sel   = 1,
+
+      /* Index:82 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:82 Alt:4  GPIO SD B1 01 FLEXCAN1 RX */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXCAN1_RX_OFFSET),
+      [ALT4].sel   = 1,
+
+      /* Index:82 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:82 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:82 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:82 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:82 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:83 GPIO_SD_B1_02 */
+
+  {
+    {
+      /* Index:83 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:83 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:83 Alt:2  GPIO SD B1 02 LPUART8 TX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_TX_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:83 Alt:3  GPIO SD B1 02 LPI2C4 SCL */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C4_SCL_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:83 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:83 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:83 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:83 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:83 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:83 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:84 GPIO_SD_B1_03 */
+
+  {
+    {
+      /* Index:84 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:84 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:84 Alt:2  GPIO SD B1 03 LPUART8 RX */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPUART8_RX_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:84 Alt:3  GPIO SD B1 03 LPI2C4 SDA */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPI2C4_SDA_OFFSET),
+      [ALT3].sel   = 1,
+
+      /* Index:84 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:84 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:84 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:84 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:84 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:84 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:85 GPIO_SD_B1_04 */
+
+  {
+    {
+      /* Index:85 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:85 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:85 Alt:2  GPIO SD B1 04 ENET TX CLK */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_TXCLK_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:85 Alt:3  GPIO SD B1 04 ENET REF CLK1 */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:85 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:85 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:85 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:85 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:85 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:85 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:86 GPIO_SD_B1_05 */
+
+  {
+    {
+      /* Index:86 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:86 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:86 Alt:2  GPIO SD B1 05 ENET RDATA01 */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXDATA1_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:86 Alt:3  GPIO SD B1 05 SAI3 MCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_MCLK_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:86 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:86 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:86 Alt:6  GPIO SD B1 05 CCM PMIC RDY */
+
+      [ALT6].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_CCM_PMIC_READY_OFFSET),
+      [ALT6].sel   = 1,
+
+      /* Index:86 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:86 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:86 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:87 GPIO_SD_B1_06 */
+
+  {
+    {
+      /* Index:87 Alt:0  GPIO SD B1 06 USDHC2 CD B */
+
+      [ALT0].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_USDHC2_CD_B_OFFSET),
+      [ALT0].sel   = 0,
+
+      /* Index:87 Alt:1  GPIO SD B1 06 FLEXSPI A DATA03 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:87 Alt:2  GPIO SD B1 06 ENET RDATA00 */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXDATA0_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:87 Alt:3  GPIO SD B1 06 SAI3 TX BCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_TX_BCLK_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:87 Alt:4  GPIO SD B1 06 LPSPI2 PCS0 */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_PCS0_OFFSET),
+      [ALT4].sel   = 2,
+
+      /* Index:87 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:87 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:87 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:87 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:87 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:88 GPIO_SD_B1_07 */
+
+  {
+    {
+      /* Index:88 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:88 Alt:1  GPIO SD B1 07 FLEXSPI A SCLK */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_SCK_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:88 Alt:2  GPIO SD B1 07 ENET RX EN */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXEN_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:88 Alt:3  GPIO SD B1 07 SAI3 TX SYNC */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_TX_SYNC_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:88 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:88 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:88 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:88 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:88 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:88 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:89 GPIO_SD_B1_08 */
+
+  {
+    {
+      /* Index:89 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:89 Alt:1  GPIO SD B1 08 FLEXSPI A DATA00 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:89 Alt:2  GPIO SD B1 08 ENET RX ER */
+
+      [ALT2].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_ENET_RXERR_OFFSET),
+      [ALT2].sel   = 0,
+
+      /* Index:89 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:89 Alt:4  GPIO SD B1 08 LPSPI2 SDO */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_SDO_OFFSET),
+      [ALT4].sel   = 2,
+
+      /* Index:89 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:89 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:89 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:89 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:89 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:90 GPIO_SD_B1_09 */
+
+  {
+    {
+      /* Index:90 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:90 Alt:1  GPIO SD B1 09 FLEXSPI A DATA02 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:90 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:90 Alt:3  GPIO SD B1 09 SAI3 RX BCLK */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_RX_BCLK_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:90 Alt:4  GPIO SD B1 09 LPSPI2 SDI */
+
+      [ALT4].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_LPSPI2_SDI_OFFSET),
+      [ALT4].sel   = 2,
+
+      /* Index:90 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:90 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:90 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:90 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:90 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:91 GPIO_SD_B1_10 */
+
+  {
+    {
+      /* Index:91 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:91 Alt:1  GPIO SD B1 10 FLEXSPI A DATA01 */
+
+      [ALT1].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET),
+      [ALT1].sel   = 0,
+
+      /* Index:91 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:91 Alt:3  GPIO SD B1 10 SAI3 RX SYNC */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_RX_SYNC_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:91 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:91 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:91 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:91 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:91 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:91 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:92 GPIO_SD_B1_11 */
+
+  {
+    {
+      /* Index:92 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:92 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:92 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:92 Alt:3  GPIO SD B1 11 SAI3 RX DATA */
+
+      [ALT3].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_SAI3_RX_DATA0_OFFSET),
+      [ALT3].sel   = 0,
+
+      /* Index:92 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:92 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:92 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:92 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:92 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:92 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:93 WAKEUP */
+
+  {
+    {
+      /* Index:93 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:93 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:93 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:93 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:93 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:93 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:93 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:93 Alt:7  SNVS WAKEUP NMI GLUE NMI */
+
+      [ALT7].index = IMXRT_INPUT_OFFSET2INDEX(IMXRT_INPUT_NMI_GLUE_NMI_OFFSET),
+      [ALT7].sel   = 1,
+
+      /* Index:93 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:93 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:94 PMIC_ON_REQ */
+
+  {
+    {
+      /* Index:94 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:94 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:94 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:94 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:94 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:94 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:94 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:94 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:94 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:94 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+
+  /* index:95 PMIC_STBY_REQ */
+
+  {
+    {
+      /* Index:95 Alt:0 No input selection */
+
+      [ALT0].index = DAISY_INDEX_INVALID,
+      [ALT0].sel   = DAISY_SEL_INVALID,
+
+      /* Index:95 Alt:1 No input selection */
+
+      [ALT1].index = DAISY_INDEX_INVALID,
+      [ALT1].sel   = DAISY_SEL_INVALID,
+
+      /* Index:95 Alt:2 No input selection */
+
+      [ALT2].index = DAISY_INDEX_INVALID,
+      [ALT2].sel   = DAISY_SEL_INVALID,
+
+      /* Index:95 Alt:3 No input selection */
+
+      [ALT3].index = DAISY_INDEX_INVALID,
+      [ALT3].sel   = DAISY_SEL_INVALID,
+
+      /* Index:95 Alt:4 No input selection */
+
+      [ALT4].index = DAISY_INDEX_INVALID,
+      [ALT4].sel   = DAISY_SEL_INVALID,
+
+      /* Index:95 Alt:5 No input selection */
+
+      [ALT5].index = DAISY_INDEX_INVALID,
+      [ALT5].sel   = DAISY_SEL_INVALID,
+
+      /* Index:95 Alt:6 No input selection */
+
+      [ALT6].index = DAISY_INDEX_INVALID,
+      [ALT6].sel   = DAISY_SEL_INVALID,
+
+      /* Index:95 Alt:7 No input selection */
+
+      [ALT7].index = DAISY_INDEX_INVALID,
+      [ALT7].sel   = DAISY_SEL_INVALID,
+
+      /* Index:95 Alt:8 No input selection */
+
+      [ALT8].index = DAISY_INDEX_INVALID,
+      [ALT8].sel   = DAISY_SEL_INVALID,
+
+      /* Index:95 Alt:9 No input selection */
+
+      [ALT9].index = DAISY_INDEX_INVALID,
+      [ALT9].sel   = DAISY_SEL_INVALID,
+    },
+  },
+};
diff --git a/arch/arm/src/imxrt/imxrt_allocateheap.c b/arch/arm/src/imxrt/imxrt_allocateheap.c
index 8404f2d58c7..22a0a406d1d 100644
--- a/arch/arm/src/imxrt/imxrt_allocateheap.c
+++ b/arch/arm/src/imxrt/imxrt_allocateheap.c
@@ -54,7 +54,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 #include "imxrt_mpuinit.h"
 
 #include 
diff --git a/arch/arm/src/imxrt/imxrt_clockconfig.c b/arch/arm/src/imxrt/imxrt_clockconfig.c
index ba47f0dfeb1..9037d72020b 100644
--- a/arch/arm/src/imxrt/imxrt_clockconfig.c
+++ b/arch/arm/src/imxrt/imxrt_clockconfig.c
@@ -1,10 +1,11 @@
 /****************************************************************************
  * arch/arm/src/imxrt/imxrt_clockconfig.c
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
  *   Authors:  Janne Rosberg 
  *             Ivan Ucherdzhiev 
  *             David Sidrane 
+ *             Dave Marples 
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -43,11 +44,11 @@
 
 #include "up_arch.h"
 #include 
-#include "chip/imxrt_ccm.h"
-#include "chip/imxrt_dcdc.h"
+#include "hardware/imxrt_ccm.h"
+#include "hardware/imxrt_dcdc.h"
 #include "imxrt_clockconfig.h"
 #include "imxrt_lcd.h"
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 #include 
 
@@ -217,11 +218,124 @@ static void imxrt_lcd_clockconfig(void)
 
   modifyreg32(IMXRT_CCM_CBCMR, CCM_CBCMR_LCDIF_PODF_MASK,
       CCM_CBCMR_LCDIF_PODF(post_divider));
-
 }
 
 #endif
 
+/****************************************************************************
+ * Name: imxrt_pllsetup
+ ****************************************************************************/
+
+static void imxrt_pllsetup(void)
+
+{
+  uint32_t reg;
+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined (CONFIG_ARCH_FAMILY_IMXRT106x))
+
+  /* Init Arm PLL1 */
+
+  reg = CCM_ANALOG_PLL_ARM_DIV_SELECT(IMXRT_ARM_PLL_DIV_SELECT) |
+        CCM_ANALOG_PLL_ARM_ENABLE;
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_ARM);
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_ARM) & CCM_ANALOG_PLL_ARM_LOCK) == 0)
+    {
+    }
+
+  /* Init Sys PLL2 */
+
+  reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_SELECT) |
+        CCM_ANALOG_PLL_SYS_ENABLE;
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS);
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0)
+    {
+    }
+
+#ifdef CONFIG_IMXRT_LCD
+  /* Init Video PLL5 */
+
+  imxrt_lcd_clockconfig();
+#endif
+
+  /* Init ENET PLL6 */
+
+  reg    = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ | CCM_ANALOG_PLL_ENET_ENET1_125M_EN |
+           CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN | CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN |
+           CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ;
+
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_ENET);
+
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_ENET) & CCM_ANALOG_PLL_ENET_LOCK) == 0)
+    {
+    }
+
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+  /* Init Sys PLL2 */
+  /* First reset its fractional dividers */
+
+  uint32_t pll2reg=getreg32(IMXRT_CCM_ANALOG_PFD_528);
+    putreg32(pll2reg |
+             CCM_ANALOG_PFD_528_PFD0_CLKGATE |
+             CCM_ANALOG_PFD_528_PFD1_CLKGATE |
+             CCM_ANALOG_PFD_528_PFD2_CLKGATE |
+             CCM_ANALOG_PFD_528_PFD3_CLKGATE,
+             IMXRT_CCM_ANALOG_PFD_528 );
+
+  reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_DIV_SELECT) |
+        CCM_ANALOG_PLL_SYS_ENABLE;
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS);
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0)
+    {
+    }
+
+  putreg32(pll2reg,IMXRT_CCM_ANALOG_PFD_528);
+
+  /* Init USB PLL3 */
+  /* capture it's original value */
+
+  uint32_t pll3reg=getreg32(IMXRT_CCM_ANALOG_PFD_480);
+  putreg32(pll3reg |
+            CCM_ANALOG_PFD_480_PFD0_CLKGATE |
+            CCM_ANALOG_PFD_480_PFD1_CLKGATE |
+            CCM_ANALOG_PFD_480_PFD2_CLKGATE |
+            CCM_ANALOG_PFD_480_PFD3_CLKGATE,
+            IMXRT_CCM_ANALOG_PFD_480 );
+
+  reg = CCM_ANALOG_PLL_USB1_DIV_SELECT(IMXRT_USB1_PLL_DIV_SELECT) |
+        CCM_ANALOG_PLL_USB1_ENABLE | CCM_ANALOG_PLL_USB1_EN_USB_CLKS |
+        CCM_ANALOG_PLL_USB1_POWER;
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_USB1);
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_USB1) & CCM_ANALOG_PLL_USB1_LOCK) == 0)
+    {
+    }
+
+  putreg32(pll3reg,IMXRT_CCM_ANALOG_PFD_480);
+
+  /* Init Audio PLL4 */
+
+  reg = CCM_ANALOG_PLL_AUDIO_DIV_SELECT(IMXRT_AUDIO_PLL_DIV_SELECT) |
+        CCM_ANALOG_PLL_AUDIO_ENABLE;
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_AUDIO);
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_AUDIO) & CCM_ANALOG_PLL_AUDIO_LOCK) == 0)
+    {
+    }
+
+  /* Init ENET PLL6 */
+
+  reg = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ | CCM_ANALOG_PLL_ENET_ENET1_125M_EN |
+        CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN | CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN;
+
+  putreg32(reg, IMXRT_CCM_ANALOG_PLL_ENET);
+
+  while ((getreg32(IMXRT_CCM_ANALOG_PLL_ENET) & CCM_ANALOG_PLL_ENET_LOCK) == 0)
+    {
+    }
+
+#else
+#error Unrecognised IMXRT family member for clock config
+#endif
+
+}
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -276,31 +390,9 @@ void imxrt_clockconfig(void)
   reg |= DCDC_REG3_TRG(IMXRT_VDD_SOC);
   putreg32(reg, IMXRT_DCDC_REG3);
 
-  /* Init Arm PLL1 */
+  /* OK, now nothing is depending on us, configure the PLLs */
 
-  reg = CCM_ANALOG_PLL_ARM_DIV_SELECT(IMXRT_ARM_PLL_DIV_SELECT) |
-        CCM_ANALOG_PLL_ARM_ENABLE;
-  putreg32(reg, IMXRT_CCM_ANALOG_PLL_ARM);
-  while ((getreg32(IMXRT_CCM_ANALOG_PLL_ARM) & CCM_ANALOG_PLL_ARM_LOCK) == 0)
-    {
-    }
-
-  /* Init Sys PLL2 */
-
-  reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_SELECT) |
-        CCM_ANALOG_PLL_SYS_ENABLE;
-  putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS);
-  while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0)
-    {
-    }
-
-#ifdef CONFIG_IMXRT_LCD
-  /* Init Video PLL5 */
-
-  imxrt_lcd_clockconfig();
-#endif
-
-  /* TODO: other pll configs */
+  imxrt_pllsetup();
 
   /* Set Dividers */
 
@@ -325,7 +417,7 @@ void imxrt_clockconfig(void)
   putreg32(reg, IMXRT_CCM_CSCMR1);
 
 #ifndef CONFIG_IMXRT_SEMC_INIT_DONE
-  /* Configure SEMC Clock only if not already done by DCD SDRAM init. */
+  /* Configure SEMC Clock only if not already done by DCD SDR */
 
   reg  = getreg32(IMXRT_CCM_CBCDR);
   reg &= ~CCM_CBCDR_SEMC_PODF_MASK;
@@ -390,7 +482,7 @@ void imxrt_clockconfig(void)
 
   reg  = getreg32(IMXRT_CCM_CSCDR2);
   reg &= ~CCM_CSCDR2_LPI2C_CLK_PODF_MASK;
-  reg |= CCM_CSCDR2_LPI2C_CLK_PODF(5);
+  reg |= CCM_CSCDR2_LPI2C_CLK_PODF(5-1);
   putreg32(reg, IMXRT_CCM_CSCDR2);
 
   while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0)
diff --git a/arch/arm/src/imxrt/imxrt_daisy.c b/arch/arm/src/imxrt/imxrt_daisy.c
index 2267e5048d8..4fa9d42309d 100644
--- a/arch/arm/src/imxrt/imxrt_daisy.c
+++ b/arch/arm/src/imxrt/imxrt_daisy.c
@@ -42,7 +42,7 @@
 #include 
 #include "chip.h"
 #include "up_arch.h"
-#include "chip/imxrt_daisy.h"
+#include "hardware/imxrt_daisy.h"
 #include "imxrt_iomuxc.h"
 
 /****************************************************************************
@@ -79,7 +79,9 @@ struct imxrt_daisy_t
 
 /* Include chip-specific daisy input selection */
 
-#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
+#if defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+#  include "imxrt102x_daisy.c"
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT105x)
 #  include "imxrt105x_daisy.c"
 #elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
 #  include "imxrt106x_daisy.c"
diff --git a/arch/arm/src/imxrt/imxrt_edma.c b/arch/arm/src/imxrt/imxrt_edma.c
index e0c69ede70b..18c79019d60 100644
--- a/arch/arm/src/imxrt/imxrt_edma.c
+++ b/arch/arm/src/imxrt/imxrt_edma.c
@@ -62,8 +62,8 @@
 #include "sched/sched.h"
 
 #include "chip.h"
-#include "chip/imxrt_edma.h"
-#include "chip/imxrt_dmamux.h"
+#include "hardware/imxrt_edma.h"
+#include "hardware/imxrt_dmamux.h"
 #include "imxrt_periphclks.h"
 #include "imxrt_edma.h"
 
@@ -886,7 +886,7 @@ void weak_function up_dma_initialize(void)
  *
  * Input Parameters:
  *   dmamux - DMAMUX configuration see DMAMUX channel configuration register
- *            bit-field definitions in chip/imxrt_dmamux.h.  Settings include:
+ *            bit-field definitions in hardware/imxrt_dmamux.h.  Settings include:
  *
  *            DMAMUX_CHCFG_SOURCE     Chip-specific DMA source (required)
  *            DMAMUX_CHCFG_AON        DMA Channel Always Enable (optional)
@@ -896,7 +896,7 @@ void weak_function up_dma_initialize(void)
  *            A value of zero will disable the DMAMUX channel.
  *   dchpri - DCHPRI channel priority configuration.  See DCHPRI channel
  *            configuration register bit-field definitions in
- *            chip/imxrt_edma.h.  Meaningful settings include:
+ *            hardware/imxrt_edma.h.  Meaningful settings include:
  *
  *            EDMA_DCHPRI_CHPRI       Channel Arbitration Priority
  *            DCHPRI_DPA              Disable Preempt Ability
diff --git a/arch/arm/src/imxrt/imxrt_edma.h b/arch/arm/src/imxrt/imxrt_edma.h
index ed7713b6851..12813a8f127 100644
--- a/arch/arm/src/imxrt/imxrt_edma.h
+++ b/arch/arm/src/imxrt/imxrt_edma.h
@@ -100,7 +100,7 @@
 #include 
 
 #include 
-#include "chip/imxrt_edma.h"
+#include "hardware/imxrt_edma.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -145,7 +145,7 @@ struct imxrt_edma_xfrconfig_s
     int16_t  doff;       /* Sign-extended offset for current destination address. */
     uint16_t iter;       /* Major loop iteration count. */
     uint8_t  flags;      /* See EDMA_CONFIG_* definitions */
-    uint8_t  ssize;      /* Source data transfer size (see TCD_ATTR_SIZE_* definitions in chip/. */
+    uint8_t  ssize;      /* Source data transfer size (see TCD_ATTR_SIZE_* definitions in rdware/. */
     uint8_t  dsize;      /* Destination data transfer size. */
     uint8_t  ttype;      /* Transfer type (see enum imxrt_edma_xfrtype_e). */
 #ifdef CONFIG_IMXRT_EDMA_EMLIM
@@ -231,7 +231,7 @@ extern "C"
  *
  * Input Parameters:
  *   dmamux - DMAMUX configuration see DMAMUX channel configuration register
- *            bit-field definitions in chip/imxrt_dmamux.h.  Settings include:
+ *            bit-field definitions in hardware/imxrt_dmamux.h.  Settings include:
  *
  *            DMAMUX_CHCFG_SOURCE     Chip-specific DMA source (required)
  *            DMAMUX_CHCFG_AON        DMA Channel Always Enable (optional)
@@ -241,7 +241,7 @@ extern "C"
  *            A value of zero will disable the DMAMUX channel.
  *   dchpri - DCHPRI channel priority configuration.  See DCHPRI channel
  *            configuration register bit-field definitions in
- *            chip/imxrt_edma.h.  Meaningful settings include:
+ *            hardware/imxrt_edma.h.  Meaningful settings include:
  *
  *            EDMA_DCHPRI_CHPRI       Channel Arbitration Priority
  *            DCHPRI_DPA              Disable Preempt Ability
diff --git a/arch/arm/src/imxrt/imxrt_enet.c b/arch/arm/src/imxrt/imxrt_enet.c
index e9f4b9494d9..3b4eeb7ee5d 100644
--- a/arch/arm/src/imxrt/imxrt_enet.c
+++ b/arch/arm/src/imxrt/imxrt_enet.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/imxrt/imxrt_enet.c
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -66,9 +66,9 @@
 #include "up_arch.h"
 #include "chip.h"
 #include "imxrt_config.h"
-#include "chip/imxrt_enet.h"
-#include "chip/imxrt_ccm.h"
-#include "chip/imxrt_pinmux.h"
+#include "hardware/imxrt_enet.h"
+#include "hardware/imxrt_ccm.h"
+#include "hardware/imxrt_pinmux.h"
 #include "imxrt_periphclks.h"
 #include "imxrt_gpio.h"
 #include "imxrt_enet.h"
@@ -185,6 +185,9 @@
  *    value into a boolean: true=duplex mode, false=half-duplex mode
  *
  * The imxrt1050-evk board uses a KSZ8081 PHY
+ * The Versiboard2 uses a LAN8720 PHY
+ *
+ * ...and further PHY descriptions here.
  */
 
 #if defined(CONFIG_ETH0_PHY_KSZ8081)
@@ -196,6 +199,15 @@
 #  define BOARD_PHY_10BASET(s)  (((s) & MII_PHYCTRL1_MODE_10HDX) != 0)
 #  define BOARD_PHY_100BASET(s) (((s) & MII_PHYCTRL1_MODE_100HDX) != 0)
 #  define BOARD_PHY_ISDUPLEX(s) (((s) & MII_PHYCTRL1_MODE_DUPLEX) != 0)
+#elif defined(CONFIG_ETH0_PHY_LAN8720)
+#  define BOARD_PHY_NAME        "LAN8720"
+#  define BOARD_PHYID1          MII_PHYID1_LAN8720
+#  define BOARD_PHYID2          MII_PHYID2_LAN8720
+#  define BOARD_PHY_STATUS      MII_LAN8720_SCSR
+#  define BOARD_PHY_ADDR        (1)
+#  define BOARD_PHY_10BASET(s)  (((s)&MII_LAN8720_SPSCR_10MBPS) != 0)
+#  define BOARD_PHY_100BASET(s) (((s)&MII_LAN8720_SPSCR_100MBPS) != 0)
+#  define BOARD_PHY_ISDUPLEX(s) (((s)&MII_LAN8720_SPSCR_DUPLEX) != 0)
 #else
 #  error "Unrecognized or missing PHY selection"
 #endif
@@ -566,8 +578,9 @@ static int imxrt_transmit(FAR struct imxrt_driver_s *priv)
  * Function: imxrt_txpoll
  *
  * Description:
- *   The transmitter is available, check if the network has any outgoing packets ready
- *   to send.  This is a callback from devif_poll().  devif_poll() may be called:
+ *   The transmitter is available, check if the network has any outgoing
+ *   packets ready to send.  This is a callback from devif_poll().
+ *   devif_poll() may be called:
  *
  *   1. When the preceding TX packet send is complete,
  *   2. When the preceding TX packet send timesout and the interface is reset
@@ -627,8 +640,8 @@ static int imxrt_txpoll(struct net_driver_s *dev)
           priv->dev.d_buf =
             (uint8_t *)imxrt_swap32((uint32_t)priv->txdesc[priv->txhead].data);
 
-          /* Check if there is room in the device to hold another packet. If not,
-           * return a non-zero value to terminate the poll.
+          /* Check if there is room in the device to hold another packet. If
+           * not, return a non-zero value to terminate the poll.
            */
 
           if (imxrt_txringfull(priv))
@@ -976,8 +989,8 @@ static void imxrt_enet_interrupt_work(FAR void *arg)
   FAR struct imxrt_driver_s *priv = (FAR struct imxrt_driver_s *)arg;
   uint32_t pending;
 #ifdef CONFIG_NET_MCASTGROUP
-  uint32_t gaurStore;
-  uint32_t galrStore;
+  uint32_t gaurstore;
+  uint32_t galrstore;
 #endif
 
   /* Process pending Ethernet interrupts */
@@ -1017,8 +1030,8 @@ static void imxrt_enet_interrupt_work(FAR void *arg)
        * multicast hash table.
        */
 
-      gaurStore = getreg32(IMXRT_ENET_GAUR);
-      galrStore = getreg32(IMXRT_ENET_GALR);
+      gaurstore = getreg32(IMXRT_ENET_GAUR);
+      galrstore = getreg32(IMXRT_ENET_GALR);
 #endif
 
       (void)imxrt_ifdown(&priv->dev);
@@ -1027,8 +1040,8 @@ static void imxrt_enet_interrupt_work(FAR void *arg)
 #ifdef CONFIG_NET_MCASTGROUP
       /* Now write the multicast table back */
 
-      putreg32(gaurStore, IMXRT_ENET_GAUR);
-      putreg32(galrStore, IMXRT_ENET_GALR);
+      putreg32(gaurstore, IMXRT_ENET_GAUR);
+      putreg32(galrstore, IMXRT_ENET_GALR);
 #endif
 
       /* Then poll the network for new XMIT data */
@@ -1489,8 +1502,8 @@ static void imxrt_txavail_work(FAR void *arg)
 
       if (!imxrt_txringfull(priv))
         {
-          /* No, there is space for another transfer.  Poll the network for new
-           * XMIT data.
+          /* No, there is space for another transfer.  Poll the network for
+           * new XMIT data.
            */
 
           (void)devif_poll(&priv->dev, imxrt_txpoll);
@@ -1558,7 +1571,7 @@ static int imxrt_txavail(struct net_driver_s *dev)
 #ifdef CONFIG_NET_MCASTGROUP
 static uint32_t imxrt_calcethcrc(const uint8_t *data, size_t length)
 {
-  uint32_t crc    = 0xFFFFFFFFU;
+  uint32_t crc    = 0xffffffffu;
   uint32_t count1 = 0;
   uint32_t count2 = 0;
 
@@ -1568,13 +1581,13 @@ static uint32_t imxrt_calcethcrc(const uint8_t *data, size_t length)
     {
       uint8_t c = data[count1];
 
-      for (count2 = 0; count2 < 0x08U; count2++)
+      for (count2 = 0; count2 < 0x08u; count2++)
         {
           if ((c ^ crc) & 1U)
             {
               crc >>= 1U;
               c   >>= 1U;
-              crc  ^= 0xEDB88320U;
+              crc  ^= 0xedb88320u;
             }
           else
             {
@@ -1614,7 +1627,7 @@ static uint32_t imxrt_enet_hash_index(const uint8_t *mac)
         mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 
   crc = imxrt_calcethcrc(mac, 6);
-  hashindex = (crc >> 26) & 0x3F;
+  hashindex = (crc >> 26) & 0x3f;
 
   return hashindex;
 }
@@ -1672,8 +1685,8 @@ static int imxrt_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
  * Function: imxrt_rmmac
  *
  * Description:
- *   NuttX Callback: Remove the specified MAC address from the hardware multicast
- *   address filtering
+ *   NuttX Callback: Remove the specified MAC address from the hardware
+ *   multicast address filtering
  *
  * Input Parameters:
  *   dev  - Reference to the NuttX driver state structure
@@ -1747,9 +1760,10 @@ static int imxrt_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
     {
 #ifdef CONFIG_NETDEV_PHY_IOCTL
 #ifdef CONFIG_ARCH_PHY_INTERRUPT
-  case SIOCMIINOTIFY: /* Set up for PHY event notifications */
-    {
-          struct mii_ioctl_notify_s *req = (struct mii_ioctl_notify_s *)((uintptr_t)arg);
+      case SIOCMIINOTIFY: /* Set up for PHY event notifications */
+        {
+          struct mii_ioctl_notify_s *req =
+            (struct mii_ioctl_notify_s *)((uintptr_t)arg);
 
           ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event);
           if (ret == OK)
@@ -1834,7 +1848,7 @@ static int imxrt_phyintenable(struct imxrt_driver_s *priv)
       /* Enable link up/down interrupts */
 
       ret = imxrt_writemii(priv, priv->phyaddr, MII_KSZ8081_INT,
-                           (MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN));
+                           (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN));
     }
 
   return ret;
@@ -2025,7 +2039,8 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy)
   if (renogphy)
     {
       /* Loop (potentially infinitely?) until we successfully communicate with
-       * the PHY.
+       * the PHY. This is 'standard stuff' that should work for any PHY - we
+       * are not communicating with it's 'special' registers at this point.
        */
 
       ninfo("%s: Try phyaddr: %u\n", BOARD_PHY_NAME, phyaddr);
@@ -2047,7 +2062,7 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy)
 
       if (retries >= 3)
         {
-          nerr("ERROR: Failed to read %s PHYID1 at address %d\n", phyaddr);
+          nerr("ERROR: Failed to read %s PHYID1 at address %d\n", BOARD_PHY_NAME, phyaddr);
           return -ENOENT;
         }
 
@@ -2086,6 +2101,7 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy)
           return -ENXIO;
         }
 
+#ifdef CONFIG_ETH0_PHY_KSZ8081
       /* Reset PHY */
 
       imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET);
@@ -2116,6 +2132,31 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy)
       imxrt_writemii(priv, phyaddr, MII_KSZ8081_OMSO,
                      (phydata & ~(1 << 5)));
 
+      /* Set Ethernet led to green = activity and yellow = link and  */
+
+      ret = imxrt_readmii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, &phydata);
+      if (ret < 0)
+        {
+          nerr("ERROR: Failed to read MII_KSZ8081_PHYCTRL2\n");
+          return ret;
+        }
+
+      imxrt_writemii(priv, phyaddr, MII_KSZ8081_PHYCTRL2,
+                     (phydata | (1 << 4)));
+
+#elif defined (CONFIG_ETH0_PHY_LAN8720)
+
+        /* Make sure that PHY comes up in correct mode when it's reset */
+
+        imxrt_writemii(priv, phyaddr, MII_LAN8720_MODES,
+               MII_LAN8720_MODES_RESV | MII_LAN8720_MODES_ALL |
+               MII_LAN8720_MODES_PHYAD(BOARD_PHY_ADDR));
+
+        /* ...and reset PHY */
+
+        imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET);
+#endif
+
       /* Start auto negotiation */
 
       ninfo("%s: Start Autonegotiation...\n",  BOARD_PHY_NAME);
@@ -2163,18 +2204,6 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy)
 
           imxrt_writemii(priv, phyaddr, MII_MCR, 0);
         }
-
-      /* Set Ethernet led to green = activity and yellow = link and  */
-
-      ret = imxrt_readmii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, &phydata);
-      if (ret < 0)
-        {
-          nerr("ERROR: Failed to read MII_KSZ8081_PHYCTRL2\n");
-          return ret;
-        }
-
-      imxrt_writemii(priv, phyaddr, MII_KSZ8081_PHYCTRL2,
-                     (phydata | (1 << 4)));
     }
 
   /* When we get here we have a (negotiated) speed and duplex. This is also
@@ -2349,8 +2378,8 @@ static void imxrt_initbuffers(struct imxrt_driver_s *priv)
 
   /* Set the wrap bit in the last descriptors to form a ring */
 
-  priv->txdesc[CONFIG_IMXRT_ENET_NTXBUFFERS-1].status1 |= TXDESC_W;
-  priv->rxdesc[CONFIG_IMXRT_ENET_NRXBUFFERS-1].status1 |= RXDESC_W;
+  priv->txdesc[CONFIG_IMXRT_ENET_NTXBUFFERS - 1].status1 |= TXDESC_W;
+  priv->rxdesc[CONFIG_IMXRT_ENET_NRXBUFFERS - 1].status1 |= RXDESC_W;
 
   /* We start with RX descriptor 0 and with no TX descriptors in use */
 
@@ -2433,19 +2462,7 @@ int imxrt_netinitialize(int intf)
   DEBUGASSERT(intf < CONFIG_IMXRT_ENET_NETHIFS);
   priv = &g_enet[intf];
 
-  /* Init ENET PLL6 */
-
-  regval = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ |
-           CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ |
-           CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_REF_24M |
-           CCM_ANALOG_PLL_ENET_ENET1_125M_EN;
-  putreg32(regval, IMXRT_CCM_ANALOG_PLL_ENET);
-
-  while ((getreg32(IMXRT_CCM_ANALOG_PLL_ENET) & CCM_ANALOG_PLL_ENET_LOCK) == 0)
-    {
-    }
-
-  /* Enable ENET1_TX_CLK_DIR */
+  /* Enable ENET1_TX_CLK_DIR (Provides 50MHz clk OUT to PHY) */
 
   regval = getreg32(IMXRT_IOMUXC_GPR_GPR1);
   regval |= GPR_GPR1_ENET1_TX_CLK_OUT_EN;
@@ -2457,25 +2474,18 @@ int imxrt_netinitialize(int intf)
 
   /* Configure all ENET/MII pins */
 
-  imxrt_config_gpio(GPIO_ENET_MDIO_3);
-  imxrt_config_gpio(GPIO_ENET_MDC_3);
-  imxrt_config_gpio(GPIO_ENET_RX_EN_1);
-  imxrt_config_gpio(GPIO_ENET_RX_ER_1);
-  imxrt_config_gpio(GPIO_ENET_RX_DATA00);
-  imxrt_config_gpio(GPIO_ENET_RX_DATA01);
-  imxrt_config_gpio(GPIO_ENET_TX_DATA00);
-  imxrt_config_gpio(GPIO_ENET_TX_DATA01);
-  imxrt_config_gpio(GPIO_ENET_TX_CLK_1);
-  imxrt_config_gpio(GPIO_ENET_TX_EN_1);
-
-  /* Configure daisy chain pins */
-
-  putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET);
-  putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_MDIO_OFFSET);
-  putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET0_RXDATA_OFFSET);
-  putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET1_RXDATA_OFFSET);
-  putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_RXEN_OFFSET);
-  putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_RXERR_OFFSET);
+  imxrt_config_gpio(GPIO_ENET_MDIO);
+  imxrt_config_gpio(GPIO_ENET_MDC);
+  imxrt_config_gpio(GPIO_ENET_RX_EN);
+  imxrt_config_gpio(GPIO_ENET_RDATA00);
+  imxrt_config_gpio(GPIO_ENET_RDATA01);
+  imxrt_config_gpio(GPIO_ENET_TDATA00);
+  imxrt_config_gpio(GPIO_ENET_TDATA01);
+  imxrt_config_gpio(GPIO_ENET_TX_CLK);
+  imxrt_config_gpio(GPIO_ENET_TX_EN);
+#ifdef GPIO_ENET_RX_ER
+  imxrt_config_gpio(GPIO_ENET_RX_ER);
+#endif
 
   /* Attach the Ethernet MAC IEEE 1588 timer interrupt handler */
 
@@ -2533,7 +2543,7 @@ int imxrt_netinitialize(int intf)
   mac    = priv->dev.d_mac.ether.ether_addr_octet;
 
   uidml |= 0x00000200;
-  uidml &= 0x0000FEFF;
+  uidml &= 0x0000feff;
 
   mac[0] = (uidml & 0x0000ff00) >> 8;
   mac[1] = (uidml & 0x000000ff);
diff --git a/arch/arm/src/imxrt/imxrt_enet.h b/arch/arm/src/imxrt/imxrt_enet.h
index 311fda56adf..ac63fb1e94a 100644
--- a/arch/arm/src/imxrt/imxrt_enet.h
+++ b/arch/arm/src/imxrt/imxrt_enet.h
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/imxrt_enet.h"
+#include "hardware/imxrt_enet.h"
 
 #ifdef CONFIG_IMXRT_ENET
 
diff --git a/arch/arm/src/imxrt/imxrt_gpio.c b/arch/arm/src/imxrt/imxrt_gpio.c
index a8a956a94b3..35951e3e780 100644
--- a/arch/arm/src/imxrt/imxrt_gpio.c
+++ b/arch/arm/src/imxrt/imxrt_gpio.c
@@ -1,8 +1,9 @@
 /****************************************************************************
  * arch/arm/src/imxrt/imxrt_gpio.c
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
+ *           Dave Marples 
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -50,7 +51,7 @@
 #include "up_arch.h"
 #include "imxrt_iomuxc.h"
 #include "imxrt_gpio.h"
-#include "chip/imxrt_daisy.h"
+#include "hardware/imxrt_daisy.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -101,6 +102,7 @@ static const uint8_t g_gpio1_padmux[IMXRT_GPIO_NPINS] =
   IMXRT_PADMUX_GPIO_AD_B1_15_INDEX            /* GPIO1 Pin 31 */
 };
 
+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
 static const uint8_t g_gpio2_padmux[IMXRT_GPIO_NPINS] =
 {
   IMXRT_PADMUX_GPIO_B0_00_INDEX,              /* GPIO2 Pin 0 */
@@ -140,6 +142,50 @@ static const uint8_t g_gpio2_padmux[IMXRT_GPIO_NPINS] =
   IMXRT_PADMUX_GPIO_B1_15_INDEX               /* GPIO2 Pin 31 */
 };
 
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+static const uint8_t g_gpio2_padmux[IMXRT_GPIO_NPINS] =
+{
+  IMXRT_PADMUX_GPIO_EMC_00_INDEX,              /* GPIO2 Pin 0 */
+  IMXRT_PADMUX_GPIO_EMC_01_INDEX,              /* GPIO2 Pin 1 */
+  IMXRT_PADMUX_GPIO_EMC_02_INDEX,              /* GPIO2 Pin 2 */
+  IMXRT_PADMUX_GPIO_EMC_03_INDEX,              /* GPIO2 Pin 3 */
+  IMXRT_PADMUX_GPIO_EMC_04_INDEX,              /* GPIO2 Pin 4 */
+  IMXRT_PADMUX_GPIO_EMC_05_INDEX,              /* GPIO2 Pin 5 */
+  IMXRT_PADMUX_GPIO_EMC_06_INDEX,              /* GPIO2 Pin 6 */
+  IMXRT_PADMUX_GPIO_EMC_07_INDEX,              /* GPIO2 Pin 7 */
+
+  IMXRT_PADMUX_GPIO_EMC_08_INDEX,              /* GPIO2 Pin 8 */
+  IMXRT_PADMUX_GPIO_EMC_09_INDEX,              /* GPIO2 Pin 9 */
+  IMXRT_PADMUX_GPIO_EMC_10_INDEX,              /* GPIO2 Pin 10 */
+  IMXRT_PADMUX_GPIO_EMC_11_INDEX,              /* GPIO2 Pin 11 */
+  IMXRT_PADMUX_GPIO_EMC_12_INDEX,              /* GPIO2 Pin 12 */
+  IMXRT_PADMUX_GPIO_EMC_13_INDEX,              /* GPIO2 Pin 13 */
+  IMXRT_PADMUX_GPIO_EMC_14_INDEX,              /* GPIO2 Pin 14 */
+  IMXRT_PADMUX_GPIO_EMC_15_INDEX,              /* GPIO2 Pin 15 */
+
+  IMXRT_PADMUX_GPIO_EMC_16_INDEX,              /* GPIO2 Pin 16 */
+  IMXRT_PADMUX_GPIO_EMC_17_INDEX,              /* GPIO2 Pin 17 */
+  IMXRT_PADMUX_GPIO_EMC_18_INDEX,              /* GPIO2 Pin 18 */
+  IMXRT_PADMUX_GPIO_EMC_19_INDEX,              /* GPIO2 Pin 19 */
+  IMXRT_PADMUX_GPIO_EMC_20_INDEX,              /* GPIO2 Pin 20 */
+  IMXRT_PADMUX_GPIO_EMC_21_INDEX,              /* GPIO2 Pin 21 */
+  IMXRT_PADMUX_GPIO_EMC_22_INDEX,              /* GPIO2 Pin 22 */
+  IMXRT_PADMUX_GPIO_EMC_23_INDEX,              /* GPIO2 Pin 23 */
+
+  IMXRT_PADMUX_GPIO_EMC_24_INDEX,              /* GPIO2 Pin 24 */
+  IMXRT_PADMUX_GPIO_EMC_25_INDEX,              /* GPIO2 Pin 25 */
+  IMXRT_PADMUX_GPIO_EMC_26_INDEX,              /* GPIO2 Pin 26 */
+  IMXRT_PADMUX_GPIO_EMC_27_INDEX,              /* GPIO2 Pin 27 */
+  IMXRT_PADMUX_GPIO_EMC_28_INDEX,              /* GPIO2 Pin 28 */
+  IMXRT_PADMUX_GPIO_EMC_29_INDEX,              /* GPIO2 Pin 29 */
+  IMXRT_PADMUX_GPIO_EMC_30_INDEX,              /* GPIO2 Pin 30 */
+  IMXRT_PADMUX_GPIO_EMC_31_INDEX               /* GPIO2 Pin 31 */
+};
+#else
+#  error "Unrecognised IMXRT family member"
+#endif
+
+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
 static const uint8_t g_gpio3_padmux[IMXRT_GPIO_NPINS] =
 {
   IMXRT_PADMUX_GPIO_SD_B1_00_INDEX,           /* GPIO3 Pin 0 */
@@ -178,7 +224,48 @@ static const uint8_t g_gpio3_padmux[IMXRT_GPIO_NPINS] =
   IMXRT_PADMUX_INVALID,                       /* GPIO3 Pin 30 */
   IMXRT_PADMUX_INVALID                        /* GPIO3 Pin 31 */
 };
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+static const uint8_t g_gpio3_padmux[IMXRT_GPIO_NPINS] =
+{
+  IMXRT_PADMUX_GPIO_EMC_32_INDEX,             /* GPIO3 Pin 0 */
+  IMXRT_PADMUX_GPIO_EMC_33_INDEX,             /* GPIO3 Pin 1 */
+  IMXRT_PADMUX_GPIO_EMC_34_INDEX,             /* GPIO3 Pin 2 */
+  IMXRT_PADMUX_GPIO_EMC_35_INDEX,             /* GPIO3 Pin 3 */
+  IMXRT_PADMUX_GPIO_EMC_36_INDEX,             /* GPIO3 Pin 4 */
+  IMXRT_PADMUX_GPIO_EMC_37_INDEX,             /* GPIO3 Pin 5 */
+  IMXRT_PADMUX_GPIO_EMC_38_INDEX,             /* GPIO3 Pin 6 */
+  IMXRT_PADMUX_GPIO_EMC_39_INDEX,             /* GPIO3 Pin 7 */
 
+  IMXRT_PADMUX_GPIO_EMC_40_INDEX,             /* GPIO3 Pin 8 */
+  IMXRT_PADMUX_GPIO_EMC_41_INDEX,             /* GPIO3 Pin 9 */
+  IMXRT_PADMUX_INVALID,                       /* GPIO3 Pin 10 */
+  IMXRT_PADMUX_INVALID,                       /* GPIO3 Pin 11 */
+  IMXRT_PADMUX_INVALID,                       /* GPIO3 Pin 12 */
+  IMXRT_PADMUX_GPIO_SD_B0_00_INDEX,           /* GPIO3 Pin 13 */
+  IMXRT_PADMUX_GPIO_SD_B0_01_INDEX,           /* GPIO3 Pin 14 */
+  IMXRT_PADMUX_GPIO_SD_B0_02_INDEX,           /* GPIO3 Pin 15 */
+
+  IMXRT_PADMUX_GPIO_SD_B0_03_INDEX,           /* GPIO3 Pin 16 */
+  IMXRT_PADMUX_GPIO_SD_B0_04_INDEX,           /* GPIO3 Pin 17 */
+  IMXRT_PADMUX_GPIO_SD_B0_05_INDEX,           /* GPIO3 Pin 18 */
+  IMXRT_PADMUX_GPIO_SD_B0_06_INDEX,           /* GPIO3 Pin 19 */
+  IMXRT_PADMUX_GPIO_SD_B1_00_INDEX,           /* GPIO3 Pin 20 */
+  IMXRT_PADMUX_GPIO_SD_B1_01_INDEX,           /* GPIO3 Pin 21 */
+  IMXRT_PADMUX_GPIO_SD_B1_02_INDEX,           /* GPIO3 Pin 22 */
+  IMXRT_PADMUX_GPIO_SD_B1_03_INDEX,           /* GPIO3 Pin 23 */
+
+  IMXRT_PADMUX_GPIO_SD_B1_04_INDEX,           /* GPIO3 Pin 24 */
+  IMXRT_PADMUX_GPIO_SD_B1_05_INDEX,           /* GPIO3 Pin 25 */
+  IMXRT_PADMUX_GPIO_SD_B1_06_INDEX,           /* GPIO3 Pin 26 */
+  IMXRT_PADMUX_GPIO_SD_B1_07_INDEX,           /* GPIO3 Pin 27 */
+  IMXRT_PADMUX_GPIO_SD_B1_08_INDEX,           /* GPIO3 Pin 28 */
+  IMXRT_PADMUX_GPIO_SD_B1_09_INDEX,           /* GPIO3 Pin 29 */
+  IMXRT_PADMUX_GPIO_SD_B1_10_INDEX,           /* GPIO3 Pin 30 */
+  IMXRT_PADMUX_GPIO_SD_B1_11_INDEX,           /* GPIO3 Pin 31 */
+};
+#endif
+
+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
 static const uint8_t g_gpio4_padmux[IMXRT_GPIO_NPINS] =
 {
   IMXRT_PADMUX_GPIO_EMC_00_INDEX,             /* GPIO4 Pin 0 */
@@ -217,6 +304,7 @@ static const uint8_t g_gpio4_padmux[IMXRT_GPIO_NPINS] =
   IMXRT_PADMUX_GPIO_EMC_30_INDEX,             /* GPIO4 Pin 30 */
   IMXRT_PADMUX_GPIO_EMC_31_INDEX              /* GPIO4 Pin 31 */
 };
+#endif
 
 static const uint8_t g_gpio5_padmux[IMXRT_GPIO_NPINS] =
 {
@@ -262,7 +350,11 @@ static FAR const uint8_t *g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] =
   g_gpio1_padmux,                             /* GPIO1 */
   g_gpio2_padmux,                             /* GPIO2 */
   g_gpio3_padmux,                             /* GPIO3 */
+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
   g_gpio4_padmux,                             /* GPIO4 */
+#else
+  NULL,                                       /* GPIO4 doesn't exist on 102x */
+#endif
   g_gpio5_padmux,                             /* GPIO5 */
 #if IMXRT_GPIO_NPORTS > 5
   g_gpio1_padmux,                             /* GPIO6 */
@@ -289,7 +381,11 @@ uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS] =
   , IMXRT_GPIO3_BASE
 #endif
 #if IMXRT_GPIO_NPORTS > 3
+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
   , IMXRT_GPIO4_BASE
+#else
+  , 0
+#endif
 #endif
 #if IMXRT_GPIO_NPORTS > 4
   , IMXRT_GPIO5_BASE
diff --git a/arch/arm/src/imxrt/imxrt_gpio.h b/arch/arm/src/imxrt/imxrt_gpio.h
index 5afb822939e..825523836d3 100644
--- a/arch/arm/src/imxrt/imxrt_gpio.h
+++ b/arch/arm/src/imxrt/imxrt_gpio.h
@@ -47,7 +47,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/imxrt_gpio.h"
+#include "hardware/imxrt_gpio.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -164,7 +164,7 @@
 #  define GPIO_ALT2            (2 << GPIO_ALT_SHIFT)  /* Alternate function 2 */
 #  define GPIO_ALT3            (3 << GPIO_ALT_SHIFT)  /* Alternate function 3 */
 #  define GPIO_ALT4            (4 << GPIO_ALT_SHIFT)  /* Alternate function 4 */
-                                                      /* Alternate function 5 is GPIO */
+#  define GPIO_ALT5            (5 << GPIO_ALT_SHIFT)  /* Alternate function 5 is GPIO */
 #  define GPIO_ALT6            (6 << GPIO_ALT_SHIFT)  /* Alternate function 6 */
 #  define GPIO_ALT7            (7 << GPIO_ALT_SHIFT)  /* Alternate function 7 */
 #  define GPIO_ALT8            (8 << GPIO_ALT_SHIFT)  /* Alternate function 8 */
@@ -205,6 +205,7 @@
 #define GPIO_PADMUX_SHIFT      (16)      /* Bits 16-23: Peripheral alternate function */
 #define GPIO_PADMUX_MASK       (0xff << GPIO_PADMUX_SHIFT)
 #  define GPIO_PADMUX(n)       ((uint32_t)(n) << GPIO_PADMUX_SHIFT)
+#define GPIO_PADMUX_GET(n)     ((n&GPIO_PADMUX_MASK)>>GPIO_PADMUX_SHIFT)
 
 /* IOMUX Pin Configuration:
  *
diff --git a/arch/arm/src/imxrt/imxrt_gpioirq.c b/arch/arm/src/imxrt/imxrt_gpioirq.c
index 9d360087591..0b0461b09d4 100644
--- a/arch/arm/src/imxrt/imxrt_gpioirq.c
+++ b/arch/arm/src/imxrt/imxrt_gpioirq.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/imxrt/imxrt_gpioirq.c
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
  *   Author:  Gregory Nutt 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -123,13 +123,18 @@ static int imxrt_gpio_info(int irq, uintptr_t *regaddr, unsigned int *pin)
   else
 #endif
 #ifdef CONFIG_IMXRT_GPIO3_16_31_IRQ
+#ifdef IMXRT_GPIO4_IMR
   if (irq < _IMXRT_GPIO4_0_15_BASE)
+#else
+  if (irq < _IMXRT_GPIO5_0_15_BASE)
+#endif
     {
       *regaddr = IMXRT_GPIO3_IMR;
       *pin     = irq - _IMXRT_GPIO3_16_31_BASE + 16;
     }
   else
 #endif
+#ifdef IMXRT_GPIO4_IMR
 #ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ
   if (irq < _IMXRT_GPIO4_16_31_BASE)
     {
@@ -146,6 +151,7 @@ static int imxrt_gpio_info(int irq, uintptr_t *regaddr, unsigned int *pin)
     }
   else
 #endif
+#endif
 #ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
   if (irq < _IMXRT_GPIO5_16_31_BASE)
     {
@@ -463,6 +469,7 @@ static int imxrt_gpio3_16_31_interrupt(int irq, FAR void *context,
 }
 #endif
 
+#ifdef IMXRT_GPIO4_IMR
 #ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ
 static int imxrt_gpio4_0_15_interrupt(int irq, FAR void *context,
                                       FAR void *arg)
@@ -536,6 +543,7 @@ static int imxrt_gpio4_16_31_interrupt(int irq, FAR void *context,
   return OK;
 }
 #endif
+#endif
 
 #ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
 static int imxrt_gpio5_0_15_interrupt(int irq, FAR void *context,
@@ -629,7 +637,9 @@ void imxrt_gpioirq_initialize(void)
   putreg32(0, IMXRT_GPIO1_IMR);
   putreg32(0, IMXRT_GPIO2_IMR);
   putreg32(0, IMXRT_GPIO3_IMR);
+#if defined(IMXRT_GPIO4_IMR)
   putreg32(0, IMXRT_GPIO4_IMR);
+#endif
   putreg32(0, IMXRT_GPIO5_IMR);
 
   /* Disable all unconfigured GPIO interrupts at the NVIC */
@@ -652,12 +662,14 @@ void imxrt_gpioirq_initialize(void)
 #ifndef CONFIG_IMXRT_GPIO3_16_31_IRQ
   up_disable_irq(IMXRT_IRQ_GPIO3_16_31);
 #endif
+#ifdef IMXRT_GPIO4_IMR
 #ifndef CONFIG_IMXRT_GPIO4_0_15_IRQ
   up_disable_irq(IMXRT_IRQ_GPIO4_0_15);
 #endif
 #ifndef CONFIG_IMXRT_GPIO4_16_31_IRQ
   up_disable_irq(IMXRT_IRQ_GPIO4_16_31);
 #endif
+#endif
 #ifndef CONFIG_IMXRT_GPIO5_0_15_IRQ
   up_disable_irq(IMXRT_IRQ_GPIO5_0_15);
 #endif
@@ -705,6 +717,7 @@ void imxrt_gpioirq_initialize(void)
   up_enable_irq(IMXRT_IRQ_GPIO3_16_31);
 #endif
 
+#ifdef IMXRT_GPIO4_IMR
 #ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ
   DEBUGVERIFY(irq_attach(IMXRT_IRQ_GPIO4_0_15,
                          imxrt_gpio4_0_15_interrupt, NULL));
@@ -716,6 +729,7 @@ void imxrt_gpioirq_initialize(void)
                          imxrt_gpio4_16_31_interrupt, NULL));
   up_enable_irq(IMXRT_IRQ_GPIO4_16_31);
 #endif
+#endif
 
 #ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
   DEBUGVERIFY(irq_attach(IMXRT_IRQ_GPIO5_0_15,
diff --git a/arch/arm/src/imxrt/imxrt_hprtc.c b/arch/arm/src/imxrt/imxrt_hprtc.c
index 71cffbcc472..9d2488a1e73 100644
--- a/arch/arm/src/imxrt/imxrt_hprtc.c
+++ b/arch/arm/src/imxrt/imxrt_hprtc.c
@@ -54,7 +54,7 @@
 
 #include "up_arch.h"
 
-#include "chip/imxrt_snvs.h"
+#include "hardware/imxrt_snvs.h"
 #include "imxrt_periphclks.h"
 #include "imxrt_lpsrtc.h"
 #include "imxrt_hprtc.h"
diff --git a/arch/arm/src/imxrt/imxrt_iomuxc.c b/arch/arm/src/imxrt/imxrt_iomuxc.c
index a325715994f..89deb0c5695 100644
--- a/arch/arm/src/imxrt/imxrt_iomuxc.c
+++ b/arch/arm/src/imxrt/imxrt_iomuxc.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/imxrt/imxrt_irq.c
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -48,7 +48,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/imxrt_ccm.h"
+#include "hardware/imxrt_ccm.h"
 #include "imxrt_periphclks.h"
 #include "imxrt_iomuxc.h"
 
@@ -66,6 +66,7 @@
  * Mux Register index.
  */
 
+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
 static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] =
 {
   /* The first mappings are simple 1-to-1 mappings.  This may be a little wasteful */
@@ -198,6 +199,111 @@ static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] =
   IMXRT_PADCTL_PMIC_ON_REQ_INDEX,
   IMXRT_PADCTL_PMIC_STBY_REQ_INDEX
 };
+#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x)
+static const uint8_t g_mux2ctl_map[IMXRT_PADMUX_NREGISTERS] =
+{
+  /* The first mappings are simple 1-to-1 mappings.  This may be a little wasteful */
+
+  IMXRT_PADCTL_GPIO_EMC_00_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_01_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_02_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_03_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_04_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_05_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_06_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_07_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_08_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_09_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_10_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_11_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_12_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_13_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_14_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_15_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_16_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_17_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_18_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_19_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_20_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_21_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_22_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_23_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_24_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_25_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_26_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_27_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_28_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_29_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_30_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_31_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_32_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_33_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_34_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_35_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_36_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_37_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_38_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_39_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_40_INDEX,
+  IMXRT_PADCTL_GPIO_EMC_41_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_00_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_01_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_02_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_03_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_04_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_05_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_06_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_07_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_08_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_09_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_10_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_11_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_12_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_13_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_14_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B0_15_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_00_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_01_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_02_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_03_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_04_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_05_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_06_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_07_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_08_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_09_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_10_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_11_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_12_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_13_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_14_INDEX,
+  IMXRT_PADCTL_GPIO_AD_B1_15_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_00_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_01_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_02_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_03_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_04_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_05_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B0_06_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_00_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_01_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_02_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_03_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_04_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_05_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_06_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_07_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_08_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_09_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_10_INDEX,
+  IMXRT_PADCTL_GPIO_SD_B1_11_INDEX,
+  IMXRT_PADCTL_WAKEUP_INDEX,
+  IMXRT_PADCTL_PMIC_ON_REQ_INDEX,
+  IMXRT_PADCTL_PMIC_STBY_REQ_INDEX
+};
+#else
+#error Unrecognised IMXRT family
+#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/arch/arm/src/imxrt/imxrt_iomuxc.h b/arch/arm/src/imxrt/imxrt_iomuxc.h
index 994e9231be6..890cc5b4172 100644
--- a/arch/arm/src/imxrt/imxrt_iomuxc.h
+++ b/arch/arm/src/imxrt/imxrt_iomuxc.h
@@ -44,7 +44,7 @@
 
 #include 
 
-#include "chip/imxrt_iomuxc.h"
+#include "hardware/imxrt_iomuxc.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/imxrt/imxrt_lcd.c b/arch/arm/src/imxrt/imxrt_lcd.c
index 815f08a2e1b..884e54d7446 100644
--- a/arch/arm/src/imxrt/imxrt_lcd.c
+++ b/arch/arm/src/imxrt/imxrt_lcd.c
@@ -58,7 +58,7 @@
 #include "imxrt_gpio.h"
 #include "imxrt_iomuxc.h"
 
-#include "chip/imxrt_pinmux.h"
+#include "hardware/imxrt_pinmux.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/imxrt/imxrt_lcd.h b/arch/arm/src/imxrt/imxrt_lcd.h
index a383f5fcf9d..9561bc65467 100644
--- a/arch/arm/src/imxrt/imxrt_lcd.h
+++ b/arch/arm/src/imxrt/imxrt_lcd.h
@@ -44,7 +44,7 @@
  * Included Files
  ****************************************************************************/
 
-#include "chip/imxrt_lcd.h"
+#include "hardware/imxrt_lcd.h"
 
 #include 
 
diff --git a/arch/arm/src/imxrt/imxrt_lowputc.c b/arch/arm/src/imxrt/imxrt_lowputc.c
index 742d4bf1439..8d002d2995d 100644
--- a/arch/arm/src/imxrt/imxrt_lowputc.c
+++ b/arch/arm/src/imxrt/imxrt_lowputc.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/imxrt/imxrt_lowputc.c
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2018, 2019 Gregory Nutt. All rights reserved.
  *   Author: Ivan Ucherdzhiev 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -45,10 +45,10 @@
 
 #include "up_arch.h"
 
-#include "chip/imxrt_iomuxc.h"
-#include "chip/imxrt_pinmux.h"
-#include "chip/imxrt_ccm.h"
-#include "chip/imxrt_lpuart.h"
+#include "hardware/imxrt_iomuxc.h"
+#include "hardware/imxrt_pinmux.h"
+#include "hardware/imxrt_ccm.h"
+#include "hardware/imxrt_lpuart.h"
 #include "imxrt_config.h"
 #include "imxrt_periphclks.h"
 #include "imxrt_iomuxc.h"
@@ -118,7 +118,8 @@
 #endif
 
 /* Clocking *****************************************************************/
-/* the UART module receives two clocks, a peripheral_clock (ipg_clk) and the
+
+/* The UART module receives two clocks, a peripheral_clock (ipg_clk) and the
  * module_clock (ipg_perclk).   The peripheral_clock is used as write clock
  * of the TxFIFO, read clock of the RxFIFO and synchronization of the modem
  * control input pins. It must always be running when UART is enabled.
@@ -234,7 +235,8 @@ void imxrt_lowsetup(void)
 #ifdef CONFIG_LPUART1_OFLOWCONTROL
   (void)imxrt_config_gpio(GPIO_LPUART1_CTS);
 #endif
-#ifdef CONFIG_LPUART1_IFLOWCONTROL
+#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) || \
+     (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)))
   (void)imxrt_config_gpio(GPIO_LPUART1_RTS);
 #endif
 #endif
@@ -250,7 +252,8 @@ void imxrt_lowsetup(void)
 #ifdef CONFIG_LPUART2_OFLOWCONTROL
   (void)imxrt_config_gpio(GPIO_LPUART2_CTS);
 #endif
-#ifdef CONFIG_LPUART2_IFLOWCONTROL
+#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) || \
+     (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)))
   (void)imxrt_config_gpio(GPIO_LPUART2_RTS);
 #endif
 #endif
@@ -266,7 +269,8 @@ void imxrt_lowsetup(void)
 #ifdef CONFIG_LPUART3_OFLOWCONTROL
   (void)imxrt_config_gpio(GPIO_LPUART3_CTS);
 #endif
-#ifdef CONFIG_LPUART3_IFLOWCONTROL
+#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) || \
+     (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL)))
   (void)imxrt_config_gpio(GPIO_LPUART3_RTS);
 #endif
 #endif
@@ -282,7 +286,8 @@ void imxrt_lowsetup(void)
 #ifdef CONFIG_LPUART4_OFLOWCONTROL
   (void)imxrt_config_gpio(GPIO_LPUART4_CTS);
 #endif
-#ifdef CONFIG_LPUART4_IFLOWCONTROL
+#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) || \
+     (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL)))
   (void)imxrt_config_gpio(GPIO_LPUART4_RTS);
 #endif
 #endif
@@ -298,7 +303,8 @@ void imxrt_lowsetup(void)
 #ifdef CONFIG_LPUART5_OFLOWCONTROL
   (void)imxrt_config_gpio(GPIO_LPUART5_CTS);
 #endif
-#ifdef CONFIG_LPUART5_IFLOWCONTROL
+#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) || \
+     (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL)))
   (void)imxrt_config_gpio(GPIO_LPUART5_RTS);
 #endif
 #endif
@@ -314,7 +320,8 @@ void imxrt_lowsetup(void)
 #ifdef CONFIG_LPUART6_OFLOWCONTROL
   (void)imxrt_config_gpio(GPIO_LPUART6_CTS);
 #endif
-#ifdef CONFIG_LPUART6_IFLOWCONTROL
+#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) || \
+     (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL)))
   (void)imxrt_config_gpio(GPIO_LPUART6_RTS);
 #endif
 #endif
@@ -330,7 +337,8 @@ void imxrt_lowsetup(void)
 #ifdef CONFIG_LPUART7_OFLOWCONTROL
   (void)imxrt_config_gpio(GPIO_LPUART7_CTS);
 #endif
-#ifdef CONFIG_LPUART7_IFLOWCONTROL
+#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) || \
+     (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL)))
   (void)imxrt_config_gpio(GPIO_LPUART7_RTS);
 #endif
 #endif
@@ -346,7 +354,8 @@ void imxrt_lowsetup(void)
 #ifdef CONFIG_LPUART8_OFLOWCONTROL
   (void)imxrt_config_gpio(GPIO_LPUART8_CTS);
 #endif
-#ifdef CONFIG_LPUART8_IFLOWCONTROL
+#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) || \
+     (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL)))
   (void)imxrt_config_gpio(GPIO_LPUART8_RTS);
 #endif
 #endif
@@ -458,12 +467,12 @@ int imxrt_lpuart_configure(uint32_t base,
 
   if (baud_diff > ((config->baud / 100) * 3))
     {
-      /* Unacceptable baud rate difference of more than 3%*/
+      /* Unacceptable baud rate difference of more than 3% */
 
       return ERROR;
     }
 
-  /* Enable lpuart clock*/
+  /* Enable lpuart clock */
 
   imxrt_lpuart_clock_enable(base);
 
@@ -471,10 +480,40 @@ int imxrt_lpuart_configure(uint32_t base,
 
   regval  = getreg32(base + IMXRT_LPUART_GLOBAL_OFFSET);
   regval |= LPUART_GLOBAL_RST;
-  putreg32(regval,base + IMXRT_LPUART_GLOBAL_OFFSET);
+  putreg32(regval, base + IMXRT_LPUART_GLOBAL_OFFSET);
 
   regval &= ~LPUART_GLOBAL_RST;
-  putreg32(regval,base + IMXRT_LPUART_GLOBAL_OFFSET);
+  putreg32(regval, base + IMXRT_LPUART_GLOBAL_OFFSET);
+
+  /* Construct MODIR register */
+
+  regval = 0;
+
+  if (config->userts)
+    {
+      regval |= LPUART_MODIR_RXRTSE;
+    }
+  else if (config->users485)
+    {
+      /* Both TX and RX side can't control RTS, so this gives
+       * the RX side precidence. This should have been filtered
+       * in layers above anyway, but it's just a precaution.
+       */
+
+      regval |= LPUART_MODIR_TXRTSE;
+    }
+
+  if (config->usects)
+    {
+      regval |= LPUART_MODIR_TXCTSE;
+    }
+
+  if (config->invrts)
+    {
+      regval |= LPUART_MODIR_TXRTSPOL;
+    }
+
+  putreg32(regval, base + IMXRT_LPUART_MODIR_OFFSET);
 
   regval = 0;
 
@@ -524,20 +563,21 @@ int imxrt_lpuart_configure(uint32_t base,
 }
 #endif /* HAVE_LPUART_DEVICE */
 
-/************************************************************************************
+/****************************************************************************
  * Name: imxrt_lowputc
  *
  * Description:
- *   Output a byte with as few system dependencies as possible.  This will even work
- *   BEFORE the console is initialized if we are booting from U-Boot (and the same
- *   UART is used for the console, of course.)
+ *   Output a byte with as few system dependencies as possible.  This will
+ *   even work BEFORE the console is initialized if we are booting from U-
+ *   Boot (and the same UART is used for the console, of course.)
  *
- ************************************************************************************/
+ ****************************************************************************/
 
 #if defined(HAVE_LPUART_DEVICE) && defined(CONFIG_DEBUG_FEATURES)
 void imxrt_lowputc(int ch)
 {
-  while ((getreg32(IMXRT_CONSOLE_BASE + IMXRT_LPUART_STAT_OFFSET) & LPUART_STAT_TDRE) == 0)
+  while ((getreg32(IMXRT_CONSOLE_BASE + IMXRT_LPUART_STAT_OFFSET) &
+         LPUART_STAT_TDRE) == 0)
     {
     }
 
@@ -549,11 +589,12 @@ void imxrt_lowputc(int ch)
 
       putreg32((uint32_t)'\r', IMXRT_CONSOLE_BASE + IMXRT_LPUART_DATA_OFFSET);
 
-      /* Wait for the transmit register to be emptied. When the TXFE bit is non-zero,
-       * the TX Buffer FIFO is empty.
+      /* Wait for the transmit register to be emptied. When the TXFE bit is
+       * non-zero, the TX Buffer FIFO is empty.
        */
 
-      while ((getreg32(IMXRT_CONSOLE_BASE + IMXRT_LPUART_STAT_OFFSET) & LPUART_STAT_TDRE) == 0)
+      while ((getreg32(IMXRT_CONSOLE_BASE + IMXRT_LPUART_STAT_OFFSET) &
+             LPUART_STAT_TDRE) == 0)
         {
         }
     }
@@ -562,11 +603,12 @@ void imxrt_lowputc(int ch)
 
   putreg32((uint32_t)ch, IMXRT_CONSOLE_BASE + IMXRT_LPUART_DATA_OFFSET);
 
-  /* Wait for the transmit register to be emptied. When the TXFE bit is non-zero,
-   * the TX Buffer FIFO is empty.
+  /* Wait for the transmit register to be emptied. When the TXFE bit is
+   * non-zero, the TX Buffer FIFO is empty.
    */
 
-  while ((getreg32(IMXRT_CONSOLE_BASE + IMXRT_LPUART_STAT_OFFSET) & LPUART_STAT_TDRE) == 0)
+  while ((getreg32(IMXRT_CONSOLE_BASE + IMXRT_LPUART_STAT_OFFSET) &
+         LPUART_STAT_TDRE) == 0)
     {
     }
 }
diff --git a/arch/arm/src/imxrt/imxrt_lowputc.h b/arch/arm/src/imxrt/imxrt_lowputc.h
index 710fb92d4cb..b2f2adb10b7 100644
--- a/arch/arm/src/imxrt/imxrt_lowputc.h
+++ b/arch/arm/src/imxrt/imxrt_lowputc.h
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/imxrt/imxrt_lowputc.h
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2018, 2019 Gregory Nutt. All rights reserved.
  *   Author: Ivan Ucherdzhiev 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -64,6 +64,10 @@ struct uart_config_s
   uint8_t  parity;        /* 0=none, 1=odd, 2=even */
   uint8_t  bits;          /* Number of bits (5-9) */
   bool     stopbits2;     /* true: Configure with 2 stop bits instead of 1 */
+  bool     userts;        /* True: Assert RTS when there are data to be sent */
+  bool     invrts;        /* True: Invert sense of RTS pin (true=active high) */
+  bool     usects;        /* True: Condition transmission on CTS asserted */
+  bool     users485;      /* True: Assert RTS while transmission progresses */
 };
 #endif
 
@@ -84,27 +88,28 @@ struct uart_config_s
 
 void imxrt_lowsetup(void);
 
-/************************************************************************************
+/****************************************************************************
  * Name: imxrt_lpuart_configure
  *
  * Description:
  *   Configure a UART for non-interrupt driven operation
  *
- ************************************************************************************/
+ ****************************************************************************/
 
 #ifdef HAVE_LPUART_DEVICE
-int imxrt_lpuart_configure(uint32_t base, FAR const struct uart_config_s *config);
+int imxrt_lpuart_configure(uint32_t base,
+                           FAR const struct uart_config_s *config);
 #endif
 
-/************************************************************************************
+/****************************************************************************
  * Name: imxrt_lowputc
  *
  * Description:
- *   Output a byte with as few system dependencies as possible.  This will even work
- *   BEFORE the console is initialized if we are booting from U-Boot (and the same
- *   UART is used for the console, of course.)
+ *   Output a byte with as few system dependencies as possible.  This will
+ *   even work BEFORE the console is initialized if we are booting from U-
+ *   Boot (and the same UART is used for the console, of course.)
  *
- ************************************************************************************/
+ ****************************************************************************/
 
 #if defined(HAVE_LPUART_DEVICE) && defined(CONFIG_DEBUG_FEATURES)
 void imxrt_lowputc(int ch);
diff --git a/arch/arm/src/imxrt/imxrt_lpi2c.c b/arch/arm/src/imxrt/imxrt_lpi2c.c
index 2899d4e0559..8309b263f70 100644
--- a/arch/arm/src/imxrt/imxrt_lpi2c.c
+++ b/arch/arm/src/imxrt/imxrt_lpi2c.c
@@ -61,9 +61,9 @@
 #include "imxrt_lpi2c.h"
 #include "imxrt_gpio.h"
 
-#include "chip/imxrt_pinmux.h"
-#include "chip/imxrt_ccm.h"
-#include "chip/imxrt_periphclks.h"
+#include "hardware/imxrt_pinmux.h"
+#include "hardware/imxrt_ccm.h"
+#include "imxrt_periphclks.h"
 
 /* At least one I2C peripheral must be enabled */
 
@@ -1617,7 +1617,7 @@ static int imxrt_lpi2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg
   priv->msgc  = count;
   priv->flags = msgs->flags;
 
-  i2cinfo("Flags %d, len %d \n", msgs->flags, msgs->length);
+  i2cinfo("Flags %x, len %d \n", msgs->flags, msgs->length);
 
   /* Reset I2C trace logic */
 
@@ -1651,23 +1651,27 @@ static int imxrt_lpi2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg
         {
           /* Bus Error */
 
+          i2cerr("Bus error\n");
           ret = -EIO;
         }
       else if (status & LPI2C_MSR_ALF)
         {
           /* Arbitration Lost (master mode) */
 
+          i2cerr("Arbitration lost\n");
           ret = -EAGAIN;
         }
       else if (status & LPI2C_MSR_NDF)
         {
           /* Acknowledge Failure */
 
+          i2cerr("Ack failure\n");
           ret = -ENXIO;
         }
       else
         {
-          ret = -EINTR;
+            i2cerr("Unspecified error\n");
+            ret = -EINTR;
         }
     }
 
diff --git a/arch/arm/src/imxrt/imxrt_lpi2c.h b/arch/arm/src/imxrt/imxrt_lpi2c.h
index af11de8d340..d229547c228 100644
--- a/arch/arm/src/imxrt/imxrt_lpi2c.h
+++ b/arch/arm/src/imxrt/imxrt_lpi2c.h
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/imxrt_lpi2c.h"
+#include "hardware/imxrt_lpi2c.h"
 
 /****************************************************************************
  * Public Function Prototypes
diff --git a/arch/arm/src/imxrt/imxrt_lpspi.c b/arch/arm/src/imxrt/imxrt_lpspi.c
index 4b346381352..174aad18951 100644
--- a/arch/arm/src/imxrt/imxrt_lpspi.c
+++ b/arch/arm/src/imxrt/imxrt_lpspi.c
@@ -86,10 +86,10 @@
 
 #include "imxrt_lpspi.h"
 #include "imxrt_gpio.h"
-#include "chip/imxrt_pinmux.h"
-#include "chip/imxrt_lpspi.h"
-#include "chip/imxrt_ccm.h"
-#include "chip/imxrt_periphclks.h"
+#include "hardware/imxrt_pinmux.h"
+#include "hardware/imxrt_lpspi.h"
+#include "hardware/imxrt_ccm.h"
+#include "imxrt_periphclks.h"
 
 #if defined(CONFIG_IMXRT_LPSPI1) || defined(CONFIG_IMXRT_LPSPI2) || \
     defined(CONFIG_IMXRT_LPSPI3) || defined(CONFIG_IMXRT_LPSPI4)
diff --git a/arch/arm/src/imxrt/imxrt_lpspi.h b/arch/arm/src/imxrt/imxrt_lpspi.h
index 01368f90c86..e2266395820 100644
--- a/arch/arm/src/imxrt/imxrt_lpspi.h
+++ b/arch/arm/src/imxrt/imxrt_lpspi.h
@@ -47,7 +47,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/imxrt_lpspi.h"
+#include "hardware/imxrt_lpspi.h"
 
 /************************************************************************************
  * Public Functions
diff --git a/arch/arm/src/imxrt/imxrt_lpsrtc.c b/arch/arm/src/imxrt/imxrt_lpsrtc.c
index 219c3734ee4..32f67bd9735 100644
--- a/arch/arm/src/imxrt/imxrt_lpsrtc.c
+++ b/arch/arm/src/imxrt/imxrt_lpsrtc.c
@@ -54,7 +54,7 @@
 
 #include "up_arch.h"
 
-#include "chip/imxrt_snvs.h"
+#include "hardware/imxrt_snvs.h"
 #include "imxrt_periphclks.h"
 #include "imxrt_hprtc.h"
 #include "imxrt_lpsrtc.h"
diff --git a/arch/arm/src/imxrt/imxrt_mpuinit.c b/arch/arm/src/imxrt/imxrt_mpuinit.c
index 85b3a59116c..ebfebadca69 100644
--- a/arch/arm/src/imxrt/imxrt_mpuinit.c
+++ b/arch/arm/src/imxrt/imxrt_mpuinit.c
@@ -46,7 +46,7 @@
 #include "mpu.h"
 #include "barriers.h"
 
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_memorymap.h"
 
 #include "imxrt_mpuinit.h"
 
diff --git a/arch/arm/src/imxrt/imxrt_ocotp.h b/arch/arm/src/imxrt/imxrt_ocotp.h
index 646926cc1c5..800083ae961 100644
--- a/arch/arm/src/imxrt/imxrt_ocotp.h
+++ b/arch/arm/src/imxrt/imxrt_ocotp.h
@@ -42,7 +42,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/imxrt_ocotp.h"
+#include "hardware/imxrt_ocotp.h"
 
 #include 
 #include 
diff --git a/arch/arm/src/imxrt/imxrt_periphclks.h b/arch/arm/src/imxrt/imxrt_periphclks.h
index b259e85ac95..bde77d5bc14 100644
--- a/arch/arm/src/imxrt/imxrt_periphclks.h
+++ b/arch/arm/src/imxrt/imxrt_periphclks.h
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/imxrt_ccm.h"
+#include "hardware/imxrt_ccm.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/imxrt/imxrt_serial.c b/arch/arm/src/imxrt/imxrt_serial.c
index a0e64508eec..33ef10ca344 100644
--- a/arch/arm/src/imxrt/imxrt_serial.c
+++ b/arch/arm/src/imxrt/imxrt_serial.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/imxrt/imxrt_serial.c
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2018, 2019 Gregory Nutt. All rights reserved.
  *   Author: Ivan Ucherdzhiev 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -65,9 +65,9 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/imxrt_lpuart.h"
+#include "hardware/imxrt_lpuart.h"
 #include "imxrt_gpio.h"
-#include "chip/imxrt_pinmux.h"
+#include "hardware/imxrt_pinmux.h"
 #include "imxrt_config.h"
 #include "imxrt_lowputc.h"
 
@@ -315,18 +315,6 @@
 #  define PM_IDLE_DOMAIN      0 /* Revisit */
 #endif
 
-#ifdef CONFIG_SERIAL_IFLOWCONTROL
-#  define IFLOW  1
-#else
-#  define IFLOW  0
-#endif
-
-#ifdef CONFIG_SERIAL_OFLOWCONTROL
-#  define OFLOW  1
-#else
-#  define OFLOW  0
-#endif
-
 /****************************************************************************
  * Private Types
  ****************************************************************************/
@@ -339,7 +327,8 @@ struct imxrt_uart_s
   uint8_t  irq;         /* IRQ associated with this UART */
   uint8_t  parity;      /* 0=none, 1=odd, 2=even */
   uint8_t  bits;        /* Number of bits (7 or 8) */
-#ifdef CONFIG_SERIAL_IFLOWCONTROL
+#if defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)
+  uint8_t  inviflow:1;  /* Invert RTS sense */
   const uint32_t rts_gpio;  /* U[S]ART RTS GPIO pin configuration */
 #endif
 #ifdef CONFIG_SERIAL_OFLOWCONTROL
@@ -353,7 +342,9 @@ struct imxrt_uart_s
 #ifdef CONFIG_SERIAL_OFLOWCONTROL
   uint8_t  oflow:1;     /* output flow control (CTS) enabled */
 #endif
-  uint8_t  reserved:(7 - IFLOW + OFLOW);
+#ifdef CONFIG_SERIAL_RS485CONTROL
+  uint8_t rs485mode:1;  /* We are in RS485 (RTS on TX) mode */
+#endif
 };
 
 /****************************************************************************
@@ -474,8 +465,20 @@ static struct imxrt_uart_s g_uart1priv =
 #endif
 #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)
   .iflow        = 1,
+#endif
+# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) \
+   || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)))
   .rts_gpio     = GPIO_LPUART1_RTS,
 #endif
+
+#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
+    && defined(CONFIG_LPUART1_INVERTIFLOWCONTROL))
+  .inviflow     = 1,
+#endif
+
+#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)
+  .rs485mode    = 1,
+#endif
 };
 
 static struct uart_dev_s g_uart1port =
@@ -512,8 +515,19 @@ static struct imxrt_uart_s g_uart2priv =
 #endif
 #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)
   .iflow        = 1,
+#endif
+# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) \
+   || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)))
   .rts_gpio     = GPIO_LPUART2_RTS,
 #endif
+#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
+    && defined(CONFIG_LPUART2_INVERTIFLOWCONTROL))
+  .inviflow     = 1,
+#endif
+
+#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)
+  .rs485mode    = 1,
+#endif
 };
 
 static struct uart_dev_s g_uart2port =
@@ -548,8 +562,19 @@ static struct imxrt_uart_s g_uart3priv =
 #endif
 #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL)
   .iflow        = 1,
+#endif
+# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) \
+   || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL)))
   .rts_gpio     = GPIO_LPUART3_RTS,
 #endif
+#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
+    && defined(CONFIG_LPUART3_INVERTIFLOWCONTROL))
+  .inviflow     = 1,
+#endif
+
+#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)
+  .rs485mode    = 1,
+#endif
 };
 
 static struct uart_dev_s g_uart3port =
@@ -584,8 +609,19 @@ static struct imxrt_uart_s g_uart4priv =
 #endif
 #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL)
   .iflow        = 1,
+#endif
+# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) \
+   || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL)))
   .rts_gpio     = GPIO_LPUART4_RTS,
 #endif
+#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
+    && defined(CONFIG_LPUART4_INVERTIFLOWCONTROL))
+  .inviflow     = 1,
+#endif
+
+#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)
+  .rs485mode    = 1,
+#endif
 };
 
 static struct uart_dev_s g_uart4port =
@@ -620,8 +656,19 @@ static struct imxrt_uart_s g_uart5priv =
 #endif
 #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL)
   .iflow        = 1,
+#endif
+# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) \
+   || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL)))
   .rts_gpio     = GPIO_LPUART5_RTS,
 #endif
+#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
+    && defined(CONFIG_LPUART5_INVERTIFLOWCONTROL))
+  .inviflow     = 1,
+#endif
+
+#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)
+  .rs485mode    = 1,
+#endif
 };
 
 static struct uart_dev_s g_uart5port =
@@ -656,8 +703,19 @@ static struct imxrt_uart_s g_uart6priv =
 #endif
 #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL)
   .iflow        = 1,
+#endif
+# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) \
+   || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL)))
   .rts_gpio     = GPIO_LPUART6_RTS,
 #endif
+#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
+    && defined(CONFIG_LPUART6_INVERTIFLOWCONTROL))
+  .inviflow     = 1,
+#endif
+
+#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)
+  .rs485mode    = 1,
+#endif
 };
 
 static struct uart_dev_s g_uart6port =
@@ -692,8 +750,19 @@ static struct imxrt_uart_s g_uart7priv =
 #endif
 #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL)
   .iflow        = 1,
+#endif
+# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) \
+   || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL)))
   .rts_gpio     = GPIO_LPUART7_RTS,
 #endif
+#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
+    && defined(CONFIG_LPUART7_INVERTIFLOWCONTROL))
+  .inviflow     = 1,
+#endif
+
+#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)
+  .rs485mode    = 1,
+#endif
 };
 
 static struct uart_dev_s g_uart7port =
@@ -728,8 +797,19 @@ static struct imxrt_uart_s g_uart8priv =
 #endif
 #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL)
   .iflow        = 1,
+#endif
+# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) \
+   || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL)))
   .rts_gpio     = GPIO_LPUART8_RTS,
 #endif
+#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
+    && defined(CONFIG_LPUART8_INVERTIFLOWCONTROL))
+  .inviflow     = 1,
+#endif
+
+#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)
+  .rs485mode    = 1,
+#endif
 };
 
 static struct uart_dev_s g_uart8port =
@@ -842,7 +922,10 @@ static int imxrt_setup(struct uart_dev_s *dev)
 {
   struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv;
 #ifndef CONFIG_SUPPRESS_LPUART_CONFIG
-  struct uart_config_s config;
+  struct uart_config_s config =
+  {
+    0
+  };
   int ret;
 
   /* Configure the UART */
@@ -851,6 +934,18 @@ static int imxrt_setup(struct uart_dev_s *dev)
   config.parity     = priv->parity;     /* 0=none, 1=odd, 2=even */
   config.bits       = priv->bits;       /* Number of bits (5-9) */
   config.stopbits2  = priv->stopbits2;  /* true: Configure with 2 stop bits instead of 1 */
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+  config.usects     = priv->iflow;      /* Flow control on inbound side */
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+  config.userts     = priv->oflow;      /* Flow control on outbound side */
+#endif
+#ifdef CONFIG_SERIAL_RS485CONTROL
+  config.users485   = priv->rs485mode;  /* Switch into RS485 mode */
+#endif
+#if defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)
+  config.invrts     = priv->inviflow;   /* Inversion of outbound flow control */
+#endif
 
   ret = imxrt_lpuart_configure(priv->uartbase, &config);
 
@@ -1436,6 +1531,7 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain,
 
       default:
         /* Should not get here */
+
         break;
     }
 }
@@ -1577,8 +1673,8 @@ void up_serialinit(void)
 
 int up_putc(int ch)
 {
-#ifdef HAVE_USART_CONSOLE
-  struct lpc54_dev_s *priv = (struct lpc54_dev_s *)CONSOLE_DEV.priv;
+#ifdef CONSOLE_DEV
+  struct imxrt_uart_s *priv = (struct imxrt_uart_s *)CONSOLE_DEV.priv;
   uint32_t ie;
 
   imxrt_disableuartint(priv, &ie);
@@ -1589,11 +1685,11 @@ int up_putc(int ch)
     {
       /* Add CR */
 
-      up_lowputc('\r');
+      imxrt_lowputc('\r');
     }
 
-  up_lowputc(ch);
-  imxrt_restoreuartint(priv, intset);
+  imxrt_lowputc(ch);
+  imxrt_restoreuartint(priv, ie);
 #endif
 
   return ch;
diff --git a/arch/arm/src/imxrt/imxrt_start.c b/arch/arm/src/imxrt/imxrt_start.c
index 4a4edfb4880..419f928cbc9 100644
--- a/arch/arm/src/imxrt/imxrt_start.c
+++ b/arch/arm/src/imxrt/imxrt_start.c
@@ -50,10 +50,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 #include "barriers.h"
-
-#ifdef CONFIG_ARCH_FPU
-#  include "nvic.h"
-#endif
+#include "nvic.h"
 
 #include "imxrt_clockconfig.h"
 #include "imxrt_mpuinit.h"
diff --git a/arch/arm/src/imxrt/imxrt_timerisr.c b/arch/arm/src/imxrt/imxrt_timerisr.c
index 666d5e2e762..616ca519cba 100644
--- a/arch/arm/src/imxrt/imxrt_timerisr.c
+++ b/arch/arm/src/imxrt/imxrt_timerisr.c
@@ -54,6 +54,7 @@
 #include "up_arch.h"
 
 #include "chip.h"
+#include "hardware/imxrt_ccm.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/imxrt/imxrt_usdhc.c b/arch/arm/src/imxrt/imxrt_usdhc.c
index 77c0bb652d7..eaad361e771 100644
--- a/arch/arm/src/imxrt/imxrt_usdhc.c
+++ b/arch/arm/src/imxrt/imxrt_usdhc.c
@@ -64,10 +64,10 @@
 
 #include "imxrt_config.h"
 #include "imxrt_gpio.h"
-#include "chip/imxrt_pinmux.h"
-#include "chip/imxrt_ccm.h"
-#include "chip/imxrt_periphclks.h"
-#include "chip/imxrt_usdhc.h"
+#include "hardware/imxrt_pinmux.h"
+#include "hardware/imxrt_ccm.h"
+#include "imxrt_periphclks.h"
+#include "hardware/imxrt_usdhc.h"
 
 #ifdef CONFIG_IMXRT_USDHC
 
@@ -1294,11 +1294,11 @@ static sdio_statset_t imxrt_status(FAR struct sdio_dev_s *dev)
 {
   struct imxrt_dev_s *priv = (struct imxrt_dev_s *)dev;
 
-  /* This register reflects the state of CD no matter if it's a separate pin
-   * or DAT3
-   */
-
+#if defined(CONFIG_MMCSD_HAVE_CARDDETECT) && defined(PIN_USDHC1_CD)
+  if (!imxrt_gpio_read(PIN_USDHC1_CD))
+#else
   if ((getreg32(IMXRT_USDHC1_PRSSTAT) & USDHC_PRSSTAT_CINS) != 0)
+#endif
     {
       priv->cdstatus |= SDIO_STATUS_PRESENT;
     }
diff --git a/arch/arm/src/imxrt/imxrt_usdhc.h b/arch/arm/src/imxrt/imxrt_usdhc.h
index 983a66515b9..d2e6fd5d7f1 100644
--- a/arch/arm/src/imxrt/imxrt_usdhc.h
+++ b/arch/arm/src/imxrt/imxrt_usdhc.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/imxrt_usdhc.h"
+#include "hardware/imxrt_usdhc.h"
 
 /****************************************************************************
  * Public Function Prototypes
diff --git a/arch/arm/src/imxrt/imxrt_wdog.c b/arch/arm/src/imxrt/imxrt_wdog.c
index 8f9f2410ed1..c491e7b1311 100644
--- a/arch/arm/src/imxrt/imxrt_wdog.c
+++ b/arch/arm/src/imxrt/imxrt_wdog.c
@@ -45,7 +45,7 @@
 
 #include "up_arch.h"
 
-#include "chip/imxrt_wdog.h"
+#include "hardware/imxrt_wdog.h"
 #include "imxrt_config.h"
 #include  /* Include last:  has dependencies */
 
diff --git a/arch/arm/src/imxrt/imxrt_wdog.h b/arch/arm/src/imxrt/imxrt_wdog.h
index 03ae7a82760..efed2de0edf 100644
--- a/arch/arm/src/imxrt/imxrt_wdog.h
+++ b/arch/arm/src/imxrt/imxrt_wdog.h
@@ -49,7 +49,7 @@
 
 #include "up_internal.h"
 #include "chip.h"
-#include "chip/imxrt_wdog.h"
+#include "hardware/imxrt_wdog.h"
 
 /****************************************************************************
  * Public Types
diff --git a/arch/arm/src/imxrt/imxrt_xbar.c b/arch/arm/src/imxrt/imxrt_xbar.c
index 33ff302d556..43ae264d9e4 100644
--- a/arch/arm/src/imxrt/imxrt_xbar.c
+++ b/arch/arm/src/imxrt/imxrt_xbar.c
@@ -58,7 +58,9 @@ static const uintptr_t g_xbars_addresses[] =
 {
   IMXRT_XBAR1_BASE,
   IMXRT_XBAR2_BASE,
+#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined (CONFIG_ARCH_FAMILY_IMXRT106x))
   IMXRT_XBAR3_BASE
+#endif
 };
 
 /****************************************************************************
diff --git a/arch/arm/src/imxrt/imxrt_xbar.h b/arch/arm/src/imxrt/imxrt_xbar.h
index 11a299c4d46..24c615f89a5 100644
--- a/arch/arm/src/imxrt/imxrt_xbar.h
+++ b/arch/arm/src/imxrt/imxrt_xbar.h
@@ -43,8 +43,8 @@
 
 #include 
 #include 
-#include "chip/imxrt_xbar.h"
-#include "chip/imxrt_memorymap.h"
+#include "hardware/imxrt_xbar.h"
+#include "hardware/imxrt_memorymap.h"
 
 /**************************************************************************************************************************************************
  * Pre-processor Definitions
@@ -113,390 +113,8 @@
 #define IMXRT_XBAR(six)                                  ((six) & IMXRT_XBARA_INDEX_MASK) >> IMXRT_XBARA_INDEX_SHIFTS
 #define IMXRT_SIDE(six)                                  ((six) & IMXRT_XBARA_SIDE_MASK)  >> IMXRT_XBARA_SIDE_SHIFTS
 
-/* XBARA1 Mux inputs (I values) *********************************************************************************************************************************************************************************/
-
-#define IMXRT_XBARA1_IN_LOGIC_LOW                        IMXRT_XBARA1(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARA1_IN0 input. */
-#define IMXRT_XBARA1_IN_LOGIC_HIGH                       IMXRT_XBARA1(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARA1_IN1 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN02                  IMXRT_XBARA1(XBAR_INPUT, 2)    /* IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN03                  IMXRT_XBARA1(XBAR_INPUT, 3)    /* IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO04                  IMXRT_XBARA1(XBAR_INPUT, 4)    /* IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO05                  IMXRT_XBARA1(XBAR_INPUT, 5)    /* IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO06                  IMXRT_XBARA1(XBAR_INPUT, 6)    /* IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO07                  IMXRT_XBARA1(XBAR_INPUT, 7)    /* IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO08                  IMXRT_XBARA1(XBAR_INPUT, 8)    /* IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO09                  IMXRT_XBARA1(XBAR_INPUT, 9)    /* IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO10                  IMXRT_XBARA1(XBAR_INPUT, 10)   /* IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO11                  IMXRT_XBARA1(XBAR_INPUT, 11)   /* IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO12                  IMXRT_XBARA1(XBAR_INPUT, 12)   /* IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO13                  IMXRT_XBARA1(XBAR_INPUT, 13)   /* IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO14                  IMXRT_XBARA1(XBAR_INPUT, 14)   /* IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO15                  IMXRT_XBARA1(XBAR_INPUT, 15)   /* IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO16                  IMXRT_XBARA1(XBAR_INPUT, 16)   /* IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO17                  IMXRT_XBARA1(XBAR_INPUT, 17)   /* IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO18                  IMXRT_XBARA1(XBAR_INPUT, 18)   /* IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IO19                  IMXRT_XBARA1(XBAR_INPUT, 19)   /* IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN20                  IMXRT_XBARA1(XBAR_INPUT, 20)   /* IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN21                  IMXRT_XBARA1(XBAR_INPUT, 21)   /* IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN22                  IMXRT_XBARA1(XBAR_INPUT, 22)   /* IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN23                  IMXRT_XBARA1(XBAR_INPUT, 23)   /* IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN24                  IMXRT_XBARA1(XBAR_INPUT, 24)   /* IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */
-#define IMXRT_XBARA1_IN_IOMUX_XBAR_IN25                  IMXRT_XBARA1(XBAR_INPUT, 25)   /* IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */
-#define IMXRT_XBARA1_IN_ACMP1_OUT                        IMXRT_XBARA1(XBAR_INPUT, 26)   /* ACMP1_OUT output assigned to XBARA1_IN26 input. */
-#define IMXRT_XBARA1_IN_ACMP2_OUT                        IMXRT_XBARA1(XBAR_INPUT, 27)   /* ACMP2_OUT output assigned to XBARA1_IN27 input. */
-#define IMXRT_XBARA1_IN_ACMP3_OUT                        IMXRT_XBARA1(XBAR_INPUT, 28)   /* ACMP3_OUT output assigned to XBARA1_IN28 input. */
-#define IMXRT_XBARA1_IN_ACMP4_OUT                        IMXRT_XBARA1(XBAR_INPUT, 29)   /* ACMP4_OUT output assigned to XBARA1_IN29 input. */
-#define IMXRT_XBARA1_IN_RESERVED30                       IMXRT_XBARA1(XBAR_INPUT, 30)   /* XBARA1_IN30 input is reserved. */
-#define IMXRT_XBARA1_IN_RESERVED31                       IMXRT_XBARA1(XBAR_INPUT, 31)   /* XBARA1_IN31 input is reserved. */
-#define IMXRT_XBARA1_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 32)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
-#define IMXRT_XBARA1_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 33)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
-#define IMXRT_XBARA1_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 34)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
-#define IMXRT_XBARA1_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 35)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
-#define IMXRT_XBARA1_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARA1(XBAR_INPUT, 36)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
-#define IMXRT_XBARA1_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARA1(XBAR_INPUT, 37)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
-#define IMXRT_XBARA1_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARA1(XBAR_INPUT, 38)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
-#define IMXRT_XBARA1_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARA1(XBAR_INPUT, 39)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 40)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 41)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 42)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 43)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 44)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 45)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 46)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 47)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 48)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 49)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 50)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 51)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 52)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 53)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 54)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */
-#define IMXRT_XBARA1_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARA1(XBAR_INPUT, 55)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */
-#define IMXRT_XBARA1_IN_PIT_TRIGGER0                     IMXRT_XBARA1(XBAR_INPUT, 56)   /* PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
-#define IMXRT_XBARA1_IN_PIT_TRIGGER1                     IMXRT_XBARA1(XBAR_INPUT, 57)   /* PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
-#define IMXRT_XBARA1_IN_PIT_TRIGGER2                     IMXRT_XBARA1(XBAR_INPUT, 58)   /* PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
-#define IMXRT_XBARA1_IN_PIT_TRIGGER3                     IMXRT_XBARA1(XBAR_INPUT, 59)   /* PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
-#define IMXRT_XBARA1_IN_ENC1_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 60)   /* ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
-#define IMXRT_XBARA1_IN_ENC2_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 61)   /* ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
-#define IMXRT_XBARA1_IN_ENC3_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 62)   /* ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */
-#define IMXRT_XBARA1_IN_ENC4_POS_MATCH                   IMXRT_XBARA1(XBAR_INPUT, 63)   /* ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE0                        IMXRT_XBARA1(XBAR_INPUT, 64)   /* DMA_DONE0 output assigned to XBARA1_IN64 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE1                        IMXRT_XBARA1(XBAR_INPUT, 65)   /* DMA_DONE1 output assigned to XBARA1_IN65 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE2                        IMXRT_XBARA1(XBAR_INPUT, 66)   /* DMA_DONE2 output assigned to XBARA1_IN66 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE3                        IMXRT_XBARA1(XBAR_INPUT, 67)   /* DMA_DONE3 output assigned to XBARA1_IN67 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE4                        IMXRT_XBARA1(XBAR_INPUT, 68)   /* DMA_DONE4 output assigned to XBARA1_IN68 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE5                        IMXRT_XBARA1(XBAR_INPUT, 69)   /* DMA_DONE5 output assigned to XBARA1_IN69 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE6                        IMXRT_XBARA1(XBAR_INPUT, 70)   /* DMA_DONE6 output assigned to XBARA1_IN70 input. */
-#define IMXRT_XBARA1_IN_DMA_DONE7                        IMXRT_XBARA1(XBAR_INPUT, 71)   /* DMA_DONE7 output assigned to XBARA1_IN71 input. */
-#define IMXRT_XBARA1_IN_AOI1_OUT0                        IMXRT_XBARA1(XBAR_INPUT, 72)   /* AOI1_OUT0 output assigned to XBARA1_IN72 input. */
-#define IMXRT_XBARA1_IN_AOI1_OUT1                        IMXRT_XBARA1(XBAR_INPUT, 73)   /* AOI1_OUT1 output assigned to XBARA1_IN73 input. */
-#define IMXRT_XBARA1_IN_AOI1_OUT2                        IMXRT_XBARA1(XBAR_INPUT, 74)   /* AOI1_OUT2 output assigned to XBARA1_IN74 input. */
-#define IMXRT_XBARA1_IN_AOI1_OUT3                        IMXRT_XBARA1(XBAR_INPUT, 75)   /* AOI1_OUT3 output assigned to XBARA1_IN75 input. */
-#define IMXRT_XBARA1_IN_AOI2_OUT0                        IMXRT_XBARA1(XBAR_INPUT, 76)   /* AOI2_OUT0 output assigned to XBARA1_IN76 input. */
-#define IMXRT_XBARA1_IN_AOI2_OUT1                        IMXRT_XBARA1(XBAR_INPUT, 77)   /* AOI2_OUT1 output assigned to XBARA1_IN77 input. */
-#define IMXRT_XBARA1_IN_AOI2_OUT2                        IMXRT_XBARA1(XBAR_INPUT, 78)   /* AOI2_OUT2 output assigned to XBARA1_IN78 input. */
-#define IMXRT_XBARA1_IN_AOI2_OUT3                        IMXRT_XBARA1(XBAR_INPUT, 79)   /* AOI2_OUT3 output assigned to XBARA1_IN79 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARA1(XBAR_INPUT, 80)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARA1(XBAR_INPUT, 81)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARA1(XBAR_INPUT, 82)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARA1(XBAR_INPUT, 83)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARA1(XBAR_INPUT, 84)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARA1(XBAR_INPUT, 85)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARA1(XBAR_INPUT, 86)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
-#define IMXRT_XBARA1_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARA1(XBAR_INPUT, 87)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
-
-/* XBARA1 Mux Output  (M Muxes) ***************************************************************************************************************/
-
-#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ30_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 0)    /* XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
-#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ31_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 1)    /* XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
-#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ94_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 2)    /* XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
-#define IMXRT_XBARA1_OUT_DMA_CH_MUX_REQ95_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 3)    /* XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO04_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 4)    /* XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO05_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 5)    /* XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO06_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 6)    /* XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO07_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 7)    /* XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO08_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 8)    /* XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO09_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 9)    /* XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO10_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 10)   /* XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO11_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 11)   /* XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO12_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 12)   /* XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO13_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 13)   /* XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO14_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 14)   /* XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO15_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 15)   /* XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO16_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 16)   /* XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO17_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 17)   /* XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO18_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 18)   /* XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
-#define IMXRT_XBARA1_OUT_IOMUX_XBAR_IO19_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 19)   /* XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
-#define IMXRT_XBARA1_OUT_ACMP1_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 20)   /* XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
-#define IMXRT_XBARA1_OUT_ACMP2_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 21)   /* XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
-#define IMXRT_XBARA1_OUT_ACMP3_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 22)   /* XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
-#define IMXRT_XBARA1_OUT_ACMP4_SAMPLE_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 23)   /* XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
-#define IMXRT_XBARA1_OUT_RESERVED24_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 24)   /* XBARA1_OUT24 output is reserved. */
-#define IMXRT_XBARA1_OUT_RESERVED25_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 25)   /* XBARA1_OUT25 output is reserved. */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA0_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 26)   /* XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA1_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 27)   /* XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA2_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 28)   /* XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXTA3_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 29)   /* XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 30)   /* XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 31)   /* XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 32)   /* XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 33)   /* XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_CLK_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 34)   /* XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 35)   /* XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 36)   /* XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 37)   /* XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1234_FAULT3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 38)   /* XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */
-#define IMXRT_XBARA1_OUT_FLEXPWM1_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 39)   /* XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
-#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA0_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 40)   /* XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA1_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 41)   /* XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA2_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 42)   /* XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */
-#define IMXRT_XBARA1_OUT_FLEXPWM234_EXTA3_SEL_OFFSET     IMXRT_XBARA1(XBAR_OUTPUT, 43)   /* XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */
-#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 44)   /* XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 45)   /* XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 46)   /* XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
-#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 47)   /* XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
-#define IMXRT_XBARA1_OUT_FLEXPWM234_EXT_CLK_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 48)   /* XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */
-#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 49)   /* XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM2_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 50)   /* XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM2_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 51)   /* XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
-#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 52)   /* XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 53)   /* XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 54)   /* XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */
-#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 55)   /* XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */
-#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 56)   /* XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM3_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 57)   /* XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM3_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 58)   /* XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */
-#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC0_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 59)   /* XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC1_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 60)   /* XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC2_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 61)   /* XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */
-#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_SYNC3_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 62)   /* XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */
-#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT0_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 63)   /* XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */
-#define IMXRT_XBARA1_OUT_FLEXPWM4_FAULT1_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 64)   /* XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */
-#define IMXRT_XBARA1_OUT_FLEXPWM4_EXT_FORCE_SEL_OFFSET   IMXRT_XBARA1(XBAR_OUTPUT, 65)   /* XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */
-#define IMXRT_XBARA1_OUT_ENC1_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 66)   /* XBARA1_OUT66 output assigned to ENC1_PHASE_A_IN_ */
-#define IMXRT_XBARA1_OUT_ENC1_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 67)   /* XBARA1_OUT67 output assigned to ENC1_PHASE_B_IN_ */
-#define IMXRT_XBARA1_OUT_ENC1_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 68)   /* XBARA1_OUT68 output assigned to ENC1_INDEX */
-#define IMXRT_XBARA1_OUT_ENC1_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 69)   /* XBARA1_OUT69 output assigned to ENC1_HOME */
-#define IMXRT_XBARA1_OUT_ENC1_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 70)   /* XBARA1_OUT70 output assigned to ENC1_TRIGGER */
-#define IMXRT_XBARA1_OUT_ENC2_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 71)   /* XBARA1_OUT71 output assigned to ENC2_PHASE_A_IN_ */
-#define IMXRT_XBARA1_OUT_ENC2_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 72)   /* XBARA1_OUT72 output assigned to ENC2_PHASE_B_IN_ */
-#define IMXRT_XBARA1_OUT_ENC2_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 73)   /* XBARA1_OUT73 output assigned to ENC2_INDEX */
-#define IMXRT_XBARA1_OUT_ENC2_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 74)   /* XBARA1_OUT74 output assigned to ENC2_HOME */
-#define IMXRT_XBARA1_OUT_ENC2_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 75)   /* XBARA1_OUT75 output assigned to ENC2_TRIGGER */
-#define IMXRT_XBARA1_OUT_ENC3_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 76)   /* XBARA1_OUT76 output assigned to ENC3_PHASE_A_IN_ */
-#define IMXRT_XBARA1_OUT_ENC3_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 77)   /* XBARA1_OUT77 output assigned to ENC3_PHASE_B_IN_ */
-#define IMXRT_XBARA1_OUT_ENC3_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 78)   /* XBARA1_OUT78 output assigned to ENC3_INDEX */
-#define IMXRT_XBARA1_OUT_ENC3_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 79)   /* XBARA1_OUT79 output assigned to ENC3_HOME */
-#define IMXRT_XBARA1_OUT_ENC3_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 80)   /* XBARA1_OUT80 output assigned to ENC3_TRIGGER */
-#define IMXRT_XBARA1_OUT_ENC4_PHASE_AIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 81)   /* XBARA1_OUT81 output assigned to ENC4_PHASE_A_IN_ */
-#define IMXRT_XBARA1_OUT_ENC4_PHASE_BIN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 82)   /* XBARA1_OUT82 output assigned to ENC4_PHASE_B_IN_ */
-#define IMXRT_XBARA1_OUT_ENC4_INDEX_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 83)   /* XBARA1_OUT83 output assigned to ENC4_INDEX */
-#define IMXRT_XBARA1_OUT_ENC4_HOME_SEL_OFFSET            IMXRT_XBARA1(XBAR_OUTPUT, 84)   /* XBARA1_OUT84 output assigned to ENC4_HOME */
-#define IMXRT_XBARA1_OUT_ENC4_TRIGGER_SEL_OFFSET         IMXRT_XBARA1(XBAR_OUTPUT, 85)   /* XBARA1_OUT85 output assigned to ENC4_TRIGGER */
-#define IMXRT_XBARA1_OUT_QTIMER1_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 86)   /* XBARA1_OUT86 output assigned to QTIMER1_TMR0_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER1_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 87)   /* XBARA1_OUT87 output assigned to QTIMER1_TMR1_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER1_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 88)   /* XBARA1_OUT88 output assigned to QTIMER1_TMR2_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER1_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 89)   /* XBARA1_OUT89 output assigned to QTIMER1_TMR3_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER2_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 90)   /* XBARA1_OUT90 output assigned to QTIMER2_TMR0_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER2_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 91)   /* XBARA1_OUT91 output assigned to QTIMER2_TMR1_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER2_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 92)   /* XBARA1_OUT92 output assigned to QTIMER2_TMR2_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER2_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 93)   /* XBARA1_OUT93 output assigned to QTIMER2_TMR3_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER3_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 94)   /* XBARA1_OUT94 output assigned to QTIMER3_TMR0_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER3_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 95)   /* XBARA1_OUT95 output assigned to QTIMER3_TMR1_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER3_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 96)   /* XBARA1_OUT96 output assigned to QTIMER3_TMR2_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER3_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 97)   /* XBARA1_OUT97 output assigned to QTIMER3_TMR3_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER4_TMR0_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 98)   /* XBARA1_OUT98 output assigned to QTIMER4_TMR0_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER4_TMR1_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 99)   /* XBARA1_OUT99 output assigned to QTIMER4_TMR1_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER4_TMR2_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 100)  /* XBARA1_OUT100 output assigned to QTIMER4_TMR2_IN_ */
-#define IMXRT_XBARA1_OUT_QTIMER4_TMR3_IN_SEL_OFFSET      IMXRT_XBARA1(XBAR_OUTPUT, 101)  /* XBARA1_OUT101 output assigned to QTIMER4_TMR3_IN_ */
-#define IMXRT_XBARA1_OUT_EWM_EWM_IN_SEL_OFFSET           IMXRT_XBARA1(XBAR_OUTPUT, 102)  /* XBARA1_OUT102 output assigned to EWM_EWM_IN */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 103)  /* XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 104)  /* XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG2_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 105)  /* XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR0_TRIG3_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 106)  /* XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 107)  /* XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 108)  /* XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG2_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 109)  /* XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */
-#define IMXRT_XBARA1_OUT_ADC_ETC_XBAR1_TRIG3_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 110)  /* XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */
-#define IMXRT_XBARA1_OUT_LPI2C1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 111)  /* XBARA1_OUT111 output assigned to LPI2C1_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPI2C2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 112)  /* XBARA1_OUT112 output assigned to LPI2C2_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPI2C3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 113)  /* XBARA1_OUT113 output assigned to LPI2C3_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPI2C4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 114)  /* XBARA1_OUT114 output assigned to LPI2C4_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPSPI1_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 115)  /* XBARA1_OUT115 output assigned to LPSPI1_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPSPI2_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 116)  /* XBARA1_OUT116 output assigned to LPSPI2_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPSPI3_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 117)  /* XBARA1_OUT117 output assigned to LPSPI3_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPSPI4_TRG_IN_SEL_OFFSET        IMXRT_XBARA1(XBAR_OUTPUT, 118)  /* XBARA1_OUT118 output assigned to LPSPI4_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART1_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 119)  /* XBARA1_OUT119 output assigned to LPUART1_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART2_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 120)  /* XBARA1_OUT120 output assigned to LPUART2_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART3_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 121)  /* XBARA1_OUT121 output assigned to LPUART3_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART4_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 122)  /* XBARA1_OUT122 output assigned to LPUART4_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART5_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 123)  /* XBARA1_OUT123 output assigned to LPUART5_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART6_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 124)  /* XBARA1_OUT124 output assigned to LPUART6_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART7_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 125)  /* XBARA1_OUT125 output assigned to LPUART7_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_LPUART8_TRG_IN_SEL_OFFSET       IMXRT_XBARA1(XBAR_OUTPUT, 126)  /* XBARA1_OUT126 output assigned to LPUART8_TRG_IN_ */
-#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 127)  /* XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
-#define IMXRT_XBARA1_OUT_FLEXIO1_TRIGGER_IN1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 128)  /* XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
-#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN0_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 129)  /* XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */
-#define IMXRT_XBARA1_OUT_FLEXIO2_TRIGGER_IN1_SEL_OFFSET  IMXRT_XBARA1(XBAR_OUTPUT, 130)  /* XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */
-
-/* XBARB2 Mux inputs (I values) *******************************************************************************************************************/
-
-#define IMXRT_XBARB2_IN_LOGIC_LOW                        IMXRT_XBARB2(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARB2_IN0 input. */
-#define IMXRT_XBARB2_IN_LOGIC_HIGH                       IMXRT_XBARB2(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARB2_IN1 input. */
-#define IMXRT_XBARB2_IN_RESERVED2                        IMXRT_XBARB2(XBAR_INPUT, 2)    /* XBARB2_IN2 input is reserved. */
-#define IMXRT_XBARB2_IN_RESERVED3                        IMXRT_XBARB2(XBAR_INPUT, 3)    /* XBARB2_IN3 input is reserved. */
-#define IMXRT_XBARB2_IN_RESERVED4                        IMXRT_XBARB2(XBAR_INPUT, 4)    /* XBARB2_IN4 input is reserved. */
-#define IMXRT_XBARB2_IN_RESERVED5                        IMXRT_XBARB2(XBAR_INPUT, 5)    /* XBARB2_IN5 input is reserved. */
-#define IMXRT_XBARB2_IN_ACMP1_OUT                        IMXRT_XBARB2(XBAR_INPUT, 6)    /* ACMP1_OUT output assigned to XBARB2_IN6 input. */
-#define IMXRT_XBARB2_IN_ACMP2_OUT                        IMXRT_XBARB2(XBAR_INPUT, 7)    /* ACMP2_OUT output assigned to XBARB2_IN7 input. */
-#define IMXRT_XBARB2_IN_ACMP3_OUT                        IMXRT_XBARB2(XBAR_INPUT, 8)    /* ACMP3_OUT output assigned to XBARB2_IN8 input. */
-#define IMXRT_XBARB2_IN_ACMP4_OUT                        IMXRT_XBARB2(XBAR_INPUT, 9)    /* ACMP4_OUT output assigned to XBARB2_IN9 input. */
-#define IMXRT_XBARB2_IN_RESERVED10                       IMXRT_XBARB2(XBAR_INPUT, 10)   /* XBARB2_IN10 input is reserved. */
-#define IMXRT_XBARB2_IN_RESERVED11                       IMXRT_XBARB2(XBAR_INPUT, 11)   /* XBARB2_IN11 input is reserved. */
-#define IMXRT_XBARB2_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 12)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
-#define IMXRT_XBARB2_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 13)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
-#define IMXRT_XBARB2_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 14)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
-#define IMXRT_XBARB2_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 15)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
-#define IMXRT_XBARB2_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARB2(XBAR_INPUT, 16)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
-#define IMXRT_XBARB2_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARB2(XBAR_INPUT, 17)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
-#define IMXRT_XBARB2_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARB2(XBAR_INPUT, 18)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
-#define IMXRT_XBARB2_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARB2(XBAR_INPUT, 19)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 28)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 29)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 30)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 31)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 32)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 33)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 34)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
-#define IMXRT_XBARB2_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARB2(XBAR_INPUT, 35)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
-#define IMXRT_XBARB2_IN_PIT_TRIGGER0                     IMXRT_XBARB2(XBAR_INPUT, 36)   /* PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
-#define IMXRT_XBARB2_IN_PIT_TRIGGER1                     IMXRT_XBARB2(XBAR_INPUT, 37)   /* PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARB2(XBAR_INPUT, 38)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARB2(XBAR_INPUT, 39)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARB2(XBAR_INPUT, 40)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARB2(XBAR_INPUT, 41)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARB2(XBAR_INPUT, 42)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARB2(XBAR_INPUT, 43)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARB2(XBAR_INPUT, 44)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
-#define IMXRT_XBARB2_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARB2(XBAR_INPUT, 45)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
-#define IMXRT_XBARB2_IN_ENC1_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 46)   /* ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
-#define IMXRT_XBARB2_IN_ENC2_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 47)   /* ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
-#define IMXRT_XBARB2_IN_ENC3_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 48)   /* ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */
-#define IMXRT_XBARB2_IN_ENC4_POS_MATCH                   IMXRT_XBARB2(XBAR_INPUT, 49)   /* ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE0                        IMXRT_XBARB2(XBAR_INPUT, 50)   /* DMA_DONE0 output assigned to XBARB2_IN50 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE1                        IMXRT_XBARB2(XBAR_INPUT, 51)   /* DMA_DONE1 output assigned to XBARB2_IN51 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE2                        IMXRT_XBARB2(XBAR_INPUT, 52)   /* DMA_DONE2 output assigned to XBARB2_IN52 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE3                        IMXRT_XBARB2(XBAR_INPUT, 53)   /* DMA_DONE3 output assigned to XBARB2_IN53 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE4                        IMXRT_XBARB2(XBAR_INPUT, 54)   /* DMA_DONE4 output assigned to XBARB2_IN54 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE5                        IMXRT_XBARB2(XBAR_INPUT, 55)   /* DMA_DONE5 output assigned to XBARB2_IN55 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE6                        IMXRT_XBARB2(XBAR_INPUT, 56)   /* DMA_DONE6 output assigned to XBARB2_IN56 input. */
-#define IMXRT_XBARB2_IN_DMA_DONE7                        IMXRT_XBARB2(XBAR_INPUT, 57)   /* DMA_DONE7 output assigned to XBARB2_IN57 input. */
-
-/* XBARB2 Mux Output  (M Muxes) ********************************************************************************************************************/
-
-#define IMXRT_XBARB2_OUT_AOI1_IN00_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 0)    /* XBARB2_OUT0 output assigned to AOI1_IN00 */
-#define IMXRT_XBARB2_OUT_AOI1_IN01_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 1)    /* XBARB2_OUT1 output assigned to AOI1_IN01 */
-#define IMXRT_XBARB2_OUT_AOI1_IN02_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 2)    /* XBARB2_OUT2 output assigned to AOI1_IN02 */
-#define IMXRT_XBARB2_OUT_AOI1_IN03_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 3)    /* XBARB2_OUT3 output assigned to AOI1_IN03 */
-#define IMXRT_XBARB2_OUT_AOI1_IN04_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 4)    /* XBARB2_OUT4 output assigned to AOI1_IN04 */
-#define IMXRT_XBARB2_OUT_AOI1_IN05_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 5)    /* XBARB2_OUT5 output assigned to AOI1_IN05 */
-#define IMXRT_XBARB2_OUT_AOI1_IN06_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 6)    /* XBARB2_OUT6 output assigned to AOI1_IN06 */
-#define IMXRT_XBARB2_OUT_AOI1_IN07_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 7)    /* XBARB2_OUT7 output assigned to AOI1_IN07 */
-#define IMXRT_XBARB2_OUT_AOI1_IN08_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 8)    /* XBARB2_OUT8 output assigned to AOI1_IN08 */
-#define IMXRT_XBARB2_OUT_AOI1_IN09_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 9)    /* XBARB2_OUT9 output assigned to AOI1_IN09 */
-#define IMXRT_XBARB2_OUT_AOI1_IN10_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 10)   /* XBARB2_OUT10 output assigned to AOI1_IN10 */
-#define IMXRT_XBARB2_OUT_AOI1_IN11_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 11)   /* XBARB2_OUT11 output assigned to AOI1_IN11 */
-#define IMXRT_XBARB2_OUT_AOI1_IN12_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 12)   /* XBARB2_OUT12 output assigned to AOI1_IN12 */
-#define IMXRT_XBARB2_OUT_AOI1_IN13_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 13)   /* XBARB2_OUT13 output assigned to AOI1_IN13 */
-#define IMXRT_XBARB2_OUT_AOI1_IN14_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 14)   /* XBARB2_OUT14 output assigned to AOI1_IN14 */
-#define IMXRT_XBARB2_OUT_AOI1_IN15_SEL_OFFSET            IMXRT_XBARB2(XBAR_OUTPUT, 15)   /* XBARB2_OUT15 output assigned to AOI1_IN15 */
-
-/* XBARB3 Mux inputs (I values) *******************************************************************************************************************/
-
-#define IMXRT_XBARB3_IN_LOGIC_LOW                        IMXRT_XBARB3(XBAR_INPUT, 0)    /* LOGIC_LOW output assigned to XBARB3_IN0 input. */
-#define IMXRT_XBARB3_IN_LOGIC_HIGH                       IMXRT_XBARB3(XBAR_INPUT, 1)    /* LOGIC_HIGH output assigned to XBARB3_IN1 input. */
-#define IMXRT_XBARB3_IN_RESERVED2                        IMXRT_XBARB3(XBAR_INPUT, 2)    /* XBARB3_IN2 input is reserved. */
-#define IMXRT_XBARB3_IN_RESERVED3                        IMXRT_XBARB3(XBAR_INPUT, 3)    /* XBARB3_IN3 input is reserved. */
-#define IMXRT_XBARB3_IN_RESERVED4                        IMXRT_XBARB3(XBAR_INPUT, 4)    /* XBARB3_IN4 input is reserved. */
-#define IMXRT_XBARB3_IN_RESERVED5                        IMXRT_XBARB3(XBAR_INPUT, 5)    /* XBARB3_IN5 input is reserved. */
-#define IMXRT_XBARB3_IN_ACMP1_OUT                        IMXRT_XBARB3(XBAR_INPUT, 6)    /* ACMP1_OUT output assigned to XBARB3_IN6 input. */
-#define IMXRT_XBARB3_IN_ACMP2_OUT                        IMXRT_XBARB3(XBAR_INPUT, 7)    /* ACMP2_OUT output assigned to XBARB3_IN7 input. */
-#define IMXRT_XBARB3_IN_ACMP3_OUT                        IMXRT_XBARB3(XBAR_INPUT, 8)    /* ACMP3_OUT output assigned to XBARB3_IN8 input. */
-#define IMXRT_XBARB3_IN_ACMP4_OUT                        IMXRT_XBARB3(XBAR_INPUT, 9)    /* ACMP4_OUT output assigned to XBARB3_IN9 input. */
-#define IMXRT_XBARB3_IN_RESERVED10                       IMXRT_XBARB3(XBAR_INPUT, 10)   /* XBARB3_IN10 input is reserved. */
-#define IMXRT_XBARB3_IN_RESERVED11                       IMXRT_XBARB3(XBAR_INPUT, 11)   /* XBARB3_IN11 input is reserved. */
-#define IMXRT_XBARB3_IN_QTIMER3_TMR0_OUT                 IMXRT_XBARB3(XBAR_INPUT, 12)   /* QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */
-#define IMXRT_XBARB3_IN_QTIMER3_TMR1_OUT                 IMXRT_XBARB3(XBAR_INPUT, 13)   /* QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */
-#define IMXRT_XBARB3_IN_QTIMER3_TMR2_OUT                 IMXRT_XBARB3(XBAR_INPUT, 14)   /* QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */
-#define IMXRT_XBARB3_IN_QTIMER3_TMR3_OUT                 IMXRT_XBARB3(XBAR_INPUT, 15)   /* QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */
-#define IMXRT_XBARB3_IN_QTIMER4_TMR0_OUT                 IMXRT_XBARB3(XBAR_INPUT, 16)   /* QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */
-#define IMXRT_XBARB3_IN_QTIMER4_TMR1_OUT                 IMXRT_XBARB3(XBAR_INPUT, 17)   /* QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */
-#define IMXRT_XBARB3_IN_QTIMER4_TMR2_OUT                 IMXRT_XBARB3(XBAR_INPUT, 18)   /* QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */
-#define IMXRT_XBARB3_IN_QTIMER4_TMR3_OUT                 IMXRT_XBARB3(XBAR_INPUT, 19)   /* QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM1_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 20)   /* FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM1_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 21)   /* FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM1_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 22)   /* FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM1_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 23)   /* FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM2_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 24)   /* FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM2_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 25)   /* FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM2_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 26)   /* FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM2_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 27)   /* FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM3_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 28)   /* FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM3_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 29)   /* FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM3_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 30)   /* FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM3_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 31)   /* FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM4_PWM1_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 32)   /* FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM4_PWM2_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 33)   /* FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM4_PWM3_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 34)   /* FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
-#define IMXRT_XBARB3_IN_FLEXPWM4_PWM4_OUT_TRIG01         IMXRT_XBARB3(XBAR_INPUT, 35)   /* FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
-#define IMXRT_XBARB3_IN_PIT_TRIGGER0                     IMXRT_XBARB3(XBAR_INPUT, 36)   /* PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */
-#define IMXRT_XBARB3_IN_PIT_TRIGGER1                     IMXRT_XBARB3(XBAR_INPUT, 37)   /* PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO0              IMXRT_XBARB3(XBAR_INPUT, 38)   /* ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO1              IMXRT_XBARB3(XBAR_INPUT, 39)   /* ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO2              IMXRT_XBARB3(XBAR_INPUT, 40)   /* ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR0_COCO3              IMXRT_XBARB3(XBAR_INPUT, 41)   /* ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO0              IMXRT_XBARB3(XBAR_INPUT, 42)   /* ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO1              IMXRT_XBARB3(XBAR_INPUT, 43)   /* ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO2              IMXRT_XBARB3(XBAR_INPUT, 44)   /* ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */
-#define IMXRT_XBARB3_IN_ADC_ETC_XBAR1_COCO3              IMXRT_XBARB3(XBAR_INPUT, 45)   /* ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */
-#define IMXRT_XBARB3_IN_ENC1_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 46)   /* ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */
-#define IMXRT_XBARB3_IN_ENC2_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 47)   /* ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */
-#define IMXRT_XBARB3_IN_ENC3_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 48)   /* ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */
-#define IMXRT_XBARB3_IN_ENC4_POS_MATCH                   IMXRT_XBARB3(XBAR_INPUT, 49)   /* ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE0                        IMXRT_XBARB3(XBAR_INPUT, 50)   /* DMA_DONE0 output assigned to XBARB3_IN50 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE1                        IMXRT_XBARB3(XBAR_INPUT, 51)   /* DMA_DONE1 output assigned to XBARB3_IN51 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE2                        IMXRT_XBARB3(XBAR_INPUT, 52)   /* DMA_DONE2 output assigned to XBARB3_IN52 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE3                        IMXRT_XBARB3(XBAR_INPUT, 53)   /* DMA_DONE3 output assigned to XBARB3_IN53 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE4                        IMXRT_XBARB3(XBAR_INPUT, 54)   /* DMA_DONE4 output assigned to XBARB3_IN54 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE5                        IMXRT_XBARB3(XBAR_INPUT, 55)   /* DMA_DONE5 output assigned to XBARB3_IN55 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE6                        IMXRT_XBARB3(XBAR_INPUT, 56)   /* DMA_DONE6 output assigned to XBARB3_IN56 input. */
-#define IMXRT_XBARB3_IN_DMA_DONE7                        IMXRT_XBARB3(XBAR_INPUT, 57)   /* DMA_DONE7 output assigned to XBARB3_IN57 input. */
-
-/* XBARB3 Mux Output  (M Muxes) ********************************************************************************************************************/
-
-#define IMXRT_XBARB3_OUT_AOI2_IN00_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 0)    /* XBARB3_OUT0 output assigned to AOI2_IN00 */
-#define IMXRT_XBARB3_OUT_AOI2_IN01_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 1)    /* XBARB3_OUT1 output assigned to AOI2_IN01 */
-#define IMXRT_XBARB3_OUT_AOI2_IN02_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 2)    /* XBARB3_OUT2 output assigned to AOI2_IN02 */
-#define IMXRT_XBARB3_OUT_AOI2_IN03_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 3)    /* XBARB3_OUT3 output assigned to AOI2_IN03 */
-#define IMXRT_XBARB3_OUT_AOI2_IN04_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 4)    /* XBARB3_OUT4 output assigned to AOI2_IN04 */
-#define IMXRT_XBARB3_OUT_AOI2_IN05_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 5)    /* XBARB3_OUT5 output assigned to AOI2_IN05 */
-#define IMXRT_XBARB3_OUT_AOI2_IN06_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 6)    /* XBARB3_OUT6 output assigned to AOI2_IN06 */
-#define IMXRT_XBARB3_OUT_AOI2_IN07_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 7)    /* XBARB3_OUT7 output assigned to AOI2_IN07 */
-#define IMXRT_XBARB3_OUT_AOI2_IN08_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 8)    /* XBARB3_OUT8 output assigned to AOI2_IN08 */
-#define IMXRT_XBARB3_OUT_AOI2_IN09_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 9)    /* XBARB3_OUT9 output assigned to AOI2_IN09 */
-#define IMXRT_XBARB3_OUT_AOI2_IN10_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 10)   /* XBARB3_OUT10 output assigned to AOI2_IN10 */
-#define IMXRT_XBARB3_OUT_AOI2_IN11_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 11)   /* XBARB3_OUT11 output assigned to AOI2_IN11 */
-#define IMXRT_XBARB3_OUT_AOI2_IN12_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 12)   /* XBARB3_OUT12 output assigned to AOI2_IN12 */
-#define IMXRT_XBARB3_OUT_AOI2_IN13_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 13)   /* XBARB3_OUT13 output assigned to AOI2_IN13 */
-#define IMXRT_XBARB3_OUT_AOI2_IN14_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 14)   /* XBARB3_OUT14 output assigned to AOI2_IN14 */
-#define IMXRT_XBARB3_OUT_AOI2_IN15_SEL_OFFSET            IMXRT_XBARB3(XBAR_OUTPUT, 15)   /* XBARB3_OUT15 output assigned to AOI2_IN15 */
+/* Collect correct XBAR definitions from chip file */
+#include "hardware/imxrt_xbar.h"
 
 /**************************************************************************************************************************************************
  * Public Functions
diff --git a/arch/arm/src/kinetis/Make.defs b/arch/arm/src/kinetis/Make.defs
index ae74387a150..ec049fc15d8 100644
--- a/arch/arm/src/kinetis/Make.defs
+++ b/arch/arm/src/kinetis/Make.defs
@@ -67,11 +67,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
diff --git a/arch/arm/src/kinetis/chip.h b/arch/arm/src/kinetis/chip.h
index bcb17c2a13d..73206dfcb85 100644
--- a/arch/arm/src/kinetis/chip.h
+++ b/arch/arm/src/kinetis/chip.h
@@ -48,7 +48,7 @@
 
 #include 
 #include 
-#include "chip/kinetis_memorymap.h"
+#include "hardware/kinetis_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/kinetis/chip/kinetis_adc.h b/arch/arm/src/kinetis/hardware/kinetis_adc.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_adc.h
rename to arch/arm/src/kinetis/hardware/kinetis_adc.h
index 847bd9b7b73..90dfbd5ac2b 100644
--- a/arch/arm/src/kinetis/chip/kinetis_adc.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_adc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_adc.h
+ * arch/arm/src/kinetis/hardware/kinetis_adc.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ADC_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ADC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ADC_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ADC_H
 
 /********************************************************************************************
  * Included Files
@@ -320,4 +320,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ADC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ADC_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_aips.h b/arch/arm/src/kinetis/hardware/kinetis_aips.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_aips.h
rename to arch/arm/src/kinetis/hardware/kinetis_aips.h
index a8050fb6139..edde48cea27 100644
--- a/arch/arm/src/kinetis/chip/kinetis_aips.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_aips.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_aips.h
+ * arch/arm/src/kinetis/hardware/kinetis_aips.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AIPS_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AIPS_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AIPS_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AIPS_H
 
 /************************************************************************************
  * Included Files
@@ -214,4 +214,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AIPS_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AIPS_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_axbs.h b/arch/arm/src/kinetis/hardware/kinetis_axbs.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_axbs.h
rename to arch/arm/src/kinetis/hardware/kinetis_axbs.h
index 7aab308593c..50399f4365e 100644
--- a/arch/arm/src/kinetis/chip/kinetis_axbs.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_axbs.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_axbs.h
+ * arch/arm/src/kinetis/hardware/kinetis_axbs.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AXBS_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AXBS_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AXBS_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AXBS_H
 
 /************************************************************************************
  * Included Files
@@ -248,4 +248,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AXBS_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_AXBS_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_cmp.h b/arch/arm/src/kinetis/hardware/kinetis_cmp.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_cmp.h
rename to arch/arm/src/kinetis/hardware/kinetis_cmp.h
index 09e9eb19f6a..e0cf6a09639 100644
--- a/arch/arm/src/kinetis/chip/kinetis_cmp.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_cmp.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_cmp.h
+ * arch/arm/src/kinetis/hardware/kinetis_cmp.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMP_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMP_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMP_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMP_H
 
 /********************************************************************************************
  * Included Files
@@ -189,4 +189,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMP_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMP_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_cmt.h b/arch/arm/src/kinetis/hardware/kinetis_cmt.h
similarity index 97%
rename from arch/arm/src/kinetis/chip/kinetis_cmt.h
rename to arch/arm/src/kinetis/hardware/kinetis_cmt.h
index e86720db91e..ca988deee1e 100644
--- a/arch/arm/src/kinetis/chip/kinetis_cmt.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_cmt.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_cmt.h
+ * arch/arm/src/kinetis/hardware/kinetis_cmt.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMT_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMT_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMT_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMT_H
 
 /************************************************************************************
  * Included Files
@@ -135,4 +135,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMT_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CMT_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_crc.h b/arch/arm/src/kinetis/hardware/kinetis_crc.h
similarity index 96%
rename from arch/arm/src/kinetis/chip/kinetis_crc.h
rename to arch/arm/src/kinetis/hardware/kinetis_crc.h
index d2f0fc7fddb..bbde430513b 100644
--- a/arch/arm/src/kinetis/chip/kinetis_crc.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_crc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_crc.h
+ * arch/arm/src/kinetis/hardware/kinetis_crc.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CRC_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CRC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CRC_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CRC_H
 
 /************************************************************************************
  * Included Files
@@ -114,4 +114,4 @@
  ************************************************************************************/
 
 #endif /* KINETIS_NCRC && KINETIS_NCRC > 0 */
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CRC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_CRC_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_dac.h b/arch/arm/src/kinetis/hardware/kinetis_dac.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_dac.h
rename to arch/arm/src/kinetis/hardware/kinetis_dac.h
index bf218438263..bf41f77a6bf 100644
--- a/arch/arm/src/kinetis/chip/kinetis_dac.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_dac.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_dac.h
+ * arch/arm/src/kinetis/hardware/kinetis_dac.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DAC_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DAC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DAC_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DAC_H
 
 /********************************************************************************************
  * Included Files
@@ -232,4 +232,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DAC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DAC_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_dma.h b/arch/arm/src/kinetis/hardware/kinetis_dma.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_dma.h
rename to arch/arm/src/kinetis/hardware/kinetis_dma.h
index 8598e81185e..6529f236b8a 100644
--- a/arch/arm/src/kinetis/chip/kinetis_dma.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_dma.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_dma.h
+ * arch/arm/src/kinetis/hardware/kinetis_dma.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMA_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMA_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMA_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMA_H
 
 /****************************************************************************************************
  * Included Files
@@ -779,4 +779,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMA_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMA_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_dmamux.h b/arch/arm/src/kinetis/hardware/kinetis_dmamux.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_dmamux.h
rename to arch/arm/src/kinetis/hardware/kinetis_dmamux.h
index 20b3ed18256..d214d0da753 100644
--- a/arch/arm/src/kinetis/chip/kinetis_dmamux.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_dmamux.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_dmamux.h
+ * arch/arm/src/kinetis/hardware/kinetis_dmamux.h
  *
  *   Copyright (C) 2011, 2016, 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMAMUX_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMAMUX_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMAMUX_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMAMUX_H
 
 /********************************************************************************************
  * Included Files
@@ -270,4 +270,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMAMUX_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMAMUX_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_dspi.h b/arch/arm/src/kinetis/hardware/kinetis_dspi.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_dspi.h
rename to arch/arm/src/kinetis/hardware/kinetis_dspi.h
index 897e766cfcf..70dbd308f30 100644
--- a/arch/arm/src/kinetis/chip/kinetis_dspi.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_dspi.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_dspi.h
+ * arch/arm/src/kinetis/hardware/kinetis_dspi.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DSPI_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DSPI_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DSPI_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DSPI_H
 
 /********************************************************************************************
  * Included Files
@@ -322,4 +322,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DSPI_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DSPI_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_enet.h b/arch/arm/src/kinetis/hardware/kinetis_enet.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_enet.h
rename to arch/arm/src/kinetis/hardware/kinetis_enet.h
index 8f34d0c7f64..af8609bab41 100644
--- a/arch/arm/src/kinetis/chip/kinetis_enet.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_enet.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_enet.h
+ * arch/arm/src/kinetis/hardware/kinetis_enet.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ENET_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ENET_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ENET_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ENET_H
 
 /********************************************************************************************
  * Included Files
@@ -649,4 +649,4 @@ struct enet_desc_s
  ********************************************************************************************/
 
 #endif /* KINETIS_NENET &&  KINETIS_NENET > 0 */
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ENET_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_ENET_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_ewm.h b/arch/arm/src/kinetis/hardware/kinetis_ewm.h
similarity index 95%
rename from arch/arm/src/kinetis/chip/kinetis_ewm.h
rename to arch/arm/src/kinetis/hardware/kinetis_ewm.h
index e91bc28c2c6..2e3f101cd54 100644
--- a/arch/arm/src/kinetis/chip/kinetis_ewm.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_ewm.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_ewm.h
+ * arch/arm/src/kinetis/hardware/kinetis_ewm.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_EWM_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_EWM_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_EWM_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_EWM_H
 
 /************************************************************************************
  * Included Files
@@ -87,4 +87,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_EWM_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_EWM_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_flexbus.h b/arch/arm/src/kinetis/hardware/kinetis_flexbus.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_flexbus.h
rename to arch/arm/src/kinetis/hardware/kinetis_flexbus.h
index 7c063d08697..a52e2027f78 100644
--- a/arch/arm/src/kinetis/chip/kinetis_flexbus.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_flexbus.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_flexbus.h
+ * arch/arm/src/kinetis/hardware/kinetis_flexbus.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXBUS_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXBUS_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXBUS_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXBUS_H
 
 /************************************************************************************
  * Included Files
@@ -210,4 +210,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXBUS_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXBUS_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_flexcan.h b/arch/arm/src/kinetis/hardware/kinetis_flexcan.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_flexcan.h
rename to arch/arm/src/kinetis/hardware/kinetis_flexcan.h
index 2463eb6b71e..32f4fad1106 100644
--- a/arch/arm/src/kinetis/chip/kinetis_flexcan.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_flexcan.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_flexcan.h
+ * arch/arm/src/kinetis/hardware/kinetis_flexcan.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXCAN_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXCAN_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXCAN_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXCAN_H
 
 /****************************************************************************************************
  * Included Files
@@ -315,4 +315,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXCAN_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FLEXCAN_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_fmc.h b/arch/arm/src/kinetis/hardware/kinetis_fmc.h
similarity index 90%
rename from arch/arm/src/kinetis/chip/kinetis_fmc.h
rename to arch/arm/src/kinetis/hardware/kinetis_fmc.h
index b3bfd18c0b1..a48b621adaa 100644
--- a/arch/arm/src/kinetis/chip/kinetis_fmc.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_fmc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_fmc.h
+ * arch/arm/src/kinetis/hardware/kinetis_fmc.h
  *
  *   Copyright (C) 2016, 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FMC_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FMC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FMC_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FMC_H
 
 /********************************************************************************************
  * Included Files
@@ -49,11 +49,11 @@
  */
 
 #if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60)
-#  include "chip/kinetis_k20k40k60fmc.h"
+#  include "hardware/kinetis_k20k40k60fmc.h"
 #elif defined(KINETIS_K64)
-#  include "chip/kinetis_k64fmc.h"
+#  include "hardware/kinetis_k64fmc.h"
 #elif defined(KINETIS_K28) || defined(KINETIS_K66)
-#  include "chip/kinetis_k28k66fmc.h"
+#  include "hardware/kinetis_k28k66fmc.h"
 #else
 #  error "No FMC definitions for this Kinetis part"
 #endif
@@ -74,4 +74,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FMC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FMC_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_ftfe.h b/arch/arm/src/kinetis/hardware/kinetis_ftfe.h
similarity index 97%
rename from arch/arm/src/kinetis/chip/kinetis_ftfe.h
rename to arch/arm/src/kinetis/hardware/kinetis_ftfe.h
index 13794d97dbe..dad9e120a9a 100644
--- a/arch/arm/src/kinetis/chip/kinetis_ftfe.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_ftfe.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_ftfe.h
+ * arch/arm/src/kinetis/hardware/kinetis_ftfe.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTFE_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTFE_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTFE_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTFE_H
 
 /************************************************************************************
  * Included Files
@@ -156,4 +156,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTFE_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTFE_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_ftm.h b/arch/arm/src/kinetis/hardware/kinetis_ftm.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_ftm.h
rename to arch/arm/src/kinetis/hardware/kinetis_ftm.h
index 1402f5e8d8a..bdbe30d119c 100644
--- a/arch/arm/src/kinetis/chip/kinetis_ftm.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_ftm.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_ftm.h
+ * arch/arm/src/kinetis/hardware/kinetis_ftm.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTM_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTM_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTM_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTM_H
 
 /********************************************************************************************
  * Included Files
@@ -569,4 +569,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTM_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_FTM_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_gpio.h b/arch/arm/src/kinetis/hardware/kinetis_gpio.h
similarity index 96%
rename from arch/arm/src/kinetis/chip/kinetis_gpio.h
rename to arch/arm/src/kinetis/hardware/kinetis_gpio.h
index 1d3d10553fb..09e205a2c2e 100644
--- a/arch/arm/src/kinetis/chip/kinetis_gpio.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/kinetis_gpio.h
+ * arch/arm/src/kinetis/hardware/kinetis_gpio.h
  *
  *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_GPIO_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_GPIO_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_GPIO_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -139,4 +139,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_GPIO_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_GPIO_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_i2c.h b/arch/arm/src/kinetis/hardware/kinetis_i2c.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_i2c.h
rename to arch/arm/src/kinetis/hardware/kinetis_i2c.h
index 95cd965ca84..d2e007b10bb 100644
--- a/arch/arm/src/kinetis/chip/kinetis_i2c.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_i2c.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_i2c.h
+ * arch/arm/src/kinetis/hardware/kinetis_i2c.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2CE_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2CE_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2CE_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2CE_H
 
 /********************************************************************************************
  * Included Files
@@ -292,4 +292,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2CE_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2CE_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_i2s.h b/arch/arm/src/kinetis/hardware/kinetis_i2s.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_i2s.h
rename to arch/arm/src/kinetis/hardware/kinetis_i2s.h
index 5de08843bb0..c223ada35c6 100644
--- a/arch/arm/src/kinetis/chip/kinetis_i2s.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_i2s.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_i2s.h
+ * arch/arm/src/kinetis/hardware/kinetis_i2s.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2S_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2S_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2S_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2S_H
 
 /****************************************************************************************************
  * Included Files
@@ -294,4 +294,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2S_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_I2S_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k20k40k60fmc.h b/arch/arm/src/kinetis/hardware/kinetis_k20k40k60fmc.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_k20k40k60fmc.h
rename to arch/arm/src/kinetis/hardware/kinetis_k20k40k60fmc.h
index 8dce4d682ef..a8cf0ac2835 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k20k40k60fmc.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k20k40k60fmc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/kinetis_k20k40k60fmc.h
+ * arch/arm/src/kinetis/hardware/kinetis_k20k40k60fmc.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20K40K60FMC_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20K40K60FMC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60FMC_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60FMC_H
 
 /************************************************************************************
  * Included Files
@@ -386,4 +386,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20K40K60FMC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60FMC_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k20k40k60mpu.h b/arch/arm/src/kinetis/hardware/kinetis_k20k40k60mpu.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_k20k40k60mpu.h
rename to arch/arm/src/kinetis/hardware/kinetis_k20k40k60mpu.h
index f2b1bf91433..4bdf59b6563 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k20k40k60mpu.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k20k40k60mpu.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/kinetis/kinetis_mpu.h
+ * arch/arm/src/kinetis/hardware/kinetis_k20k40k60mpu.h
  *
  *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MPU_H
-#define __ARCH_ARM_SRC_KINETIS_KINETIS_MPU_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60MPU_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60MPU_H
 
 /****************************************************************************************************
  * Included Files
@@ -395,4 +395,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MPU_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20K40K60MPU_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k20memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k20memorymap.h
similarity index 97%
rename from arch/arm/src/kinetis/chip/kinetis_k20memorymap.h
rename to arch/arm/src/kinetis/hardware/kinetis_k20memorymap.h
index c21ba4d0985..144dafea121 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k20memorymap.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k20memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_k20memorymap.h
+ * arch/arm/src/kinetis/hardware/kinetis_k20memorymap.h
  *
  *   Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20MEMORYMAP_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20MEMORYMAP_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -177,4 +177,4 @@
  ************************************************************************************/
 
 #endif /* KINETIS_K20 */
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20MEMORYMAP_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k20pinmux.h b/arch/arm/src/kinetis/hardware/kinetis_k20pinmux.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_k20pinmux.h
rename to arch/arm/src/kinetis/hardware/kinetis_k20pinmux.h
index d77ea962704..647240db989 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k20pinmux.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k20pinmux.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_k20pinmux.h
+ * arch/arm/src/kinetis/hardware/kinetis_k20pinmux.h
  *
  *   Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20PINMUX_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20PINMUX_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20PINMUX_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20PINMUX_H
 
 /********************************************************************************************
  * Included Files
@@ -350,4 +350,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20PINMUX_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20PINMUX_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k28k64k66mpu.h b/arch/arm/src/kinetis/hardware/kinetis_k28k64k66mpu.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_k28k64k66mpu.h
rename to arch/arm/src/kinetis/hardware/kinetis_k28k64k66mpu.h
index 0e500e84bb4..650026b9192 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k28k64k66mpu.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k28k64k66mpu.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_k28k64k66mpu.h
+ * arch/arm/src/kinetis/hardware/kinetis_k28k64k66mpu.h
  *
  *   Copyright (C) 2011, 2017-2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K28K64K66MPU_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K28K64K66MPU_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28K64K66MPU_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28K64K66MPU_H
 
 /****************************************************************************************************
  * Included Files
@@ -388,4 +388,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K28K64K66MPU_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28K64K66MPU_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k28k66fmc.h b/arch/arm/src/kinetis/hardware/kinetis_k28k66fmc.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_k28k66fmc.h
rename to arch/arm/src/kinetis/hardware/kinetis_k28k66fmc.h
index 5f95bf99c1a..f4efeb64151 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k28k66fmc.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k28k66fmc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/kinetis_k28k66fmc.h
+ * arch/arm/src/kinetis/hardware/kinetis_k28k66fmc.h
  *
  *   Copyright (C) 2016-2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K28K66FMC_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K28K66FMC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28K66FMC_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28K66FMC_H
 
 /************************************************************************************
  * Included Files
@@ -361,4 +361,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K28K66FMC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28K66FMC_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k28memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_k28memorymap.h
rename to arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h
index 47b4c7239ff..89b02b8c026 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k28memorymap.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_k28memorymap.h
+ * arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K28MEMORYMAP_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K28MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28MEMORYMAP_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -226,4 +226,4 @@
  ************************************************************************************/
 
 #endif /* KINETIS_K28 */
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K28MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28MEMORYMAP_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k28pinmux.h b/arch/arm/src/kinetis/hardware/kinetis_k28pinmux.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_k28pinmux.h
rename to arch/arm/src/kinetis/hardware/kinetis_k28pinmux.h
index dc5400a5aa2..8ee6fe3b37e 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k28pinmux.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k28pinmux.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_k28pinmux.h
+ * arch/arm/src/kinetis/hardware/kinetis_k28pinmux.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHP_KINETIS_K28PINMUX_H
-#define __ARCH_ARM_SRC_KINETIS_CHP_KINETIS_K28PINMUX_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28PINMUX_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28PINMUX_H
 
 /********************************************************************************************
  * Included Files
@@ -830,4 +830,4 @@
  ********************************************************************************************/
 
 #endif /* KINETIS_K28 */
-#endif /* __ARCH_ARM_SRC_KINETIS_CHP_KINETIS_K28PINMUX_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28PINMUX_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k40memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h
similarity index 97%
rename from arch/arm/src/kinetis/chip/kinetis_k40memorymap.h
rename to arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h
index 68ce4e4a06c..35e0095faa2 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k40memorymap.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_k40memorymap.h
+ * arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h
  *
  *   Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40MEMORYMAP_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K40MEMORYMAP_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K40MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -196,4 +196,4 @@
  ************************************************************************************/
 
 #endif /* KINETIS_K40 */
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K40MEMORYMAP_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k40pinmux.h b/arch/arm/src/kinetis/hardware/kinetis_k40pinmux.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_k40pinmux.h
rename to arch/arm/src/kinetis/hardware/kinetis_k40pinmux.h
index c7570edaf9a..2a34264acaf 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k40pinmux.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k40pinmux.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_k40pinmux.h
+ * arch/arm/src/kinetis/hardware/kinetis_k40pinmux.h
  *
  *   Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40PINMUX_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40PINMUX_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K40PINMUX_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K40PINMUX_H
 
 /********************************************************************************************
  * Included Files
@@ -516,4 +516,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40PINMUX_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K40PINMUX_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k60memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k60memorymap.h
similarity index 97%
rename from arch/arm/src/kinetis/chip/kinetis_k60memorymap.h
rename to arch/arm/src/kinetis/hardware/kinetis_k60memorymap.h
index 0dc6888faee..e78c3efe20b 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k60memorymap.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k60memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_k60memorymap.h
+ * arch/arm/src/kinetis/hardware/kinetis_k60memorymap.h
  *
  *   Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60MEMORYMAP_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K60MEMORYMAP_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K60MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -193,4 +193,4 @@
  ************************************************************************************/
 
 #endif /* KINETIS_K60 */
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K60MEMORYMAP_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k60pinmux.h b/arch/arm/src/kinetis/hardware/kinetis_k60pinmux.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_k60pinmux.h
rename to arch/arm/src/kinetis/hardware/kinetis_k60pinmux.h
index b1ca87746f3..bb727a6f620 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k60pinmux.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k60pinmux.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_k60pinset.h
+ * arch/arm/src/kinetis/hardware/kinetis_k60pinset.h
  *
  *   Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60PINMUX_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60PINMUX_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K60PINMUX_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K60PINMUX_H
 
 /********************************************************************************************
  * Included Files
@@ -484,4 +484,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60PINMUX_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K60PINMUX_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k64fmc.h b/arch/arm/src/kinetis/hardware/kinetis_k64fmc.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_k64fmc.h
rename to arch/arm/src/kinetis/hardware/kinetis_k64fmc.h
index 036e38f1299..5aec3d34ec5 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k64fmc.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k64fmc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/kinetis_k64fmc.h
+ * arch/arm/src/kinetis/hardware/kinetis_k64fmc.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64FMC_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64FMC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64FMC_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64FMC_H
 
 /************************************************************************************
  * Included Files
@@ -290,4 +290,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64FMC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64FMC_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k64memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_k64memorymap.h
rename to arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h
index 247063981c5..7a8a86ca624 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k64memorymap.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_k64memorymap.h
+ * arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h
  *
  *   Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64MEMORYMAP_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64MEMORYMAP_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -210,4 +210,4 @@
  ************************************************************************************/
 
 #endif /* KINETIS_K64 */
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64MEMORYMAP_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k64pinmux.h b/arch/arm/src/kinetis/hardware/kinetis_k64pinmux.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_k64pinmux.h
rename to arch/arm/src/kinetis/hardware/kinetis_k64pinmux.h
index d9894b3ff70..d44541c9fde 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k64pinmux.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k64pinmux.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_k64pinmux.h
+ * arch/arm/src/kinetis/hardware/kinetis_k64pinmux.h
  *
  *   Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHP_KINETIS_K64PINMUX_H
-#define __ARCH_ARM_SRC_KINETIS_CHP_KINETIS_K64PINMUX_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64PINMUX_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64PINMUX_H
 
 /********************************************************************************************
  * Included Files
@@ -638,4 +638,4 @@
  ********************************************************************************************/
 
 #endif /* KINETIS_K64 */
-#endif /* __ARCH_ARM_SRC_KINETIS_CHP_KINETIS_K64PINMUX_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64PINMUX_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k66memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k66memorymap.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_k66memorymap.h
rename to arch/arm/src/kinetis/hardware/kinetis_k66memorymap.h
index 629b2140360..c2d0c7655f2 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k66memorymap.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k66memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_k66memorymap.h
+ * arch/arm/src/kinetis/hardware/kinetis_k66memorymap.h
  *
  *   Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K66MEMORYMAP_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K66MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K66MEMORYMAP_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K66MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -238,4 +238,4 @@
  ************************************************************************************/
 
 #endif /* KINETIS_K66 */
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K66MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K66MEMORYMAP_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_k66pinmux.h b/arch/arm/src/kinetis/hardware/kinetis_k66pinmux.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_k66pinmux.h
rename to arch/arm/src/kinetis/hardware/kinetis_k66pinmux.h
index 178b700feba..7a572229604 100644
--- a/arch/arm/src/kinetis/chip/kinetis_k66pinmux.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_k66pinmux.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_k66pinmux.h
+ * arch/arm/src/kinetis/hardware/kinetis_k66pinmux.h
  *
  *   Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHP_KINETIS_K66PINMUX_H
-#define __ARCH_ARM_SRC_KINETIS_CHP_KINETIS_K66PINMUX_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K66PINMUX_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K66PINMUX_H
 
 /********************************************************************************************
  * Included Files
@@ -759,4 +759,4 @@
  ********************************************************************************************/
 
 #endif /* KINETIS_K66 */
-#endif /* __ARCH_ARM_SRC_KINETIS_CHP_KINETIS_K66PINMUX_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K66PINMUX_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_kx6tpm.h b/arch/arm/src/kinetis/hardware/kinetis_kx6tpm.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_kx6tpm.h
rename to arch/arm/src/kinetis/hardware/kinetis_kx6tpm.h
index 2dd103c6566..00f81f54f9a 100644
--- a/arch/arm/src/kinetis/chip/kinetis_kx6tpm.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_kx6tpm.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_kx6tpm.h
+ * arch/arm/src/kinetis/hardware/kinetis_kx6tpm.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_KX6TPM_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_KX6TPM_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_KX6TPM_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_KX6TPM_H
 
 /****************************************************************************
  * Included Files
@@ -208,4 +208,4 @@
 # define TPM_CONF_TRGSEL_LPTMR      (14 << TPM_CONF_TRGSEL_SHIFT) /* LPTMR trigger */
 # define TPM_CONF_TRGSEL_SW         (15 << TPM_CONF_TRGSEL_SHIFT) /* Software Trigger */
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_KX6TPM_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_KX6TPM_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_llwu.h b/arch/arm/src/kinetis/hardware/kinetis_llwu.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_llwu.h
rename to arch/arm/src/kinetis/hardware/kinetis_llwu.h
index c4abaa74ddf..9f13500d0ca 100644
--- a/arch/arm/src/kinetis/chip/kinetis_llwu.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_llwu.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_llwu.h
+ * arch/arm/src/kinetis/hardware/kinetis_llwu.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LLWU_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LLWU_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LLWU_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LLWU_H
 
 /************************************************************************************
  * Included Files
@@ -251,4 +251,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LLWU_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LLWU_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_lptmr.h b/arch/arm/src/kinetis/hardware/kinetis_lptmr.h
similarity index 97%
rename from arch/arm/src/kinetis/chip/kinetis_lptmr.h
rename to arch/arm/src/kinetis/hardware/kinetis_lptmr.h
index f89aee13176..c953ff5c60c 100644
--- a/arch/arm/src/kinetis/chip/kinetis_lptmr.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_lptmr.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_lptmr.h
+ * arch/arm/src/kinetis/hardware/kinetis_lptmr.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPTMR_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPTMR_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LPTMR_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LPTMR_H
 
 /****************************************************************************************************
  * Included Files
@@ -135,4 +135,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPTMR_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LPTMR_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_lpuart.h b/arch/arm/src/kinetis/hardware/kinetis_lpuart.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_lpuart.h
rename to arch/arm/src/kinetis/hardware/kinetis_lpuart.h
index 5c373b5637a..876ab95e350 100644
--- a/arch/arm/src/kinetis/chip/kinetis_lpuart.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_lpuart.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_lpuart.h
+ * arch/arm/src/kinetis/hardware/kinetis_lpuart.h
  *
  *   Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPUART_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPUART_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LPUART_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LPUART_H
 
 /****************************************************************************************************
  * Included Files
@@ -353,4 +353,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPUART_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LPUART_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_mcg.h b/arch/arm/src/kinetis/hardware/kinetis_mcg.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_mcg.h
rename to arch/arm/src/kinetis/hardware/kinetis_mcg.h
index 6b7798c4f73..d2b140606b1 100644
--- a/arch/arm/src/kinetis/chip/kinetis_mcg.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_mcg.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_mcg.h
+ * arch/arm/src/kinetis/hardware/kinetis_mcg.h
  *
  *   Copyright (C) 2011, 2016-2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCG_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCG_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MCG_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MCG_H
 
 /************************************************************************************
  * Included Files
@@ -436,4 +436,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCG_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MCG_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_mcm.h b/arch/arm/src/kinetis/hardware/kinetis_mcm.h
similarity index 97%
rename from arch/arm/src/kinetis/chip/kinetis_mcm.h
rename to arch/arm/src/kinetis/hardware/kinetis_mcm.h
index f46305056ef..f7a8e9d3ee0 100644
--- a/arch/arm/src/kinetis/chip/kinetis_mcm.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_mcm.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_mcm.h
+ * arch/arm/src/kinetis/hardware/kinetis_mcm.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCM_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCM_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MCM_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MCM_H
 
 /************************************************************************************
  * Included Files
@@ -154,4 +154,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCM_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MCM_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_memorymap.h
similarity index 86%
rename from arch/arm/src/kinetis/chip/kinetis_memorymap.h
rename to arch/arm/src/kinetis/hardware/kinetis_memorymap.h
index 853edaa712d..dfd008684ac 100644
--- a/arch/arm/src/kinetis/chip/kinetis_memorymap.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_memorymap.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_memorymap.h
+ * arch/arm/src/kinetis/hardware/kinetis_memorymap.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MEMORYMAP_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MEMORYMAP_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MEMORYMAP_H
 
 /********************************************************************************************
  * Included Files
@@ -49,17 +49,17 @@
  */
 
 #if defined(KINETIS_K20)
-#  include "chip/kinetis_k20memorymap.h"
+#  include "hardware/kinetis_k20memorymap.h"
 #elif defined(KINETIS_K28)
-#  include "chip/kinetis_k28memorymap.h"
+#  include "hardware/kinetis_k28memorymap.h"
 #elif defined(KINETIS_K40)
-#  include "chip/kinetis_k40memorymap.h"
+#  include "hardware/kinetis_k40memorymap.h"
 #elif defined(KINETIS_K60)
-#  include "chip/kinetis_k60memorymap.h"
+#  include "hardware/kinetis_k60memorymap.h"
 #elif defined(KINETIS_K64)
-#  include "chip/kinetis_k64memorymap.h"
+#  include "hardware/kinetis_k64memorymap.h"
 #elif defined(KINETIS_K66)
-#  include "chip/kinetis_k66memorymap.h"
+#  include "hardware/kinetis_k66memorymap.h"
 #else
 #  error "No memory map for this Kinetis part"
 #endif
@@ -80,4 +80,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MEMORYMAP_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_mmcau.h b/arch/arm/src/kinetis/hardware/kinetis_mmcau.h
similarity index 96%
rename from arch/arm/src/kinetis/chip/kinetis_mmcau.h
rename to arch/arm/src/kinetis/hardware/kinetis_mmcau.h
index 90c9cf6552c..2cc645a32d1 100644
--- a/arch/arm/src/kinetis/chip/kinetis_mmcau.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_mmcau.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_mmcau.h
+ * arch/arm/src/kinetis/hardware/kinetis_mmcau.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MMCAU_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MMCAU_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MMCAU_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MMCAU_H
 
 /************************************************************************************
  * Included Files
@@ -139,4 +139,4 @@
  ************************************************************************************/
 
 #endif /* KINETIS_NMMCAU && KINETIS_NMMCAU > 0 */
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MMCAU_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MMCAU_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_mpu.h b/arch/arm/src/kinetis/hardware/kinetis_mpu.h
similarity index 91%
rename from arch/arm/src/kinetis/chip/kinetis_mpu.h
rename to arch/arm/src/kinetis/hardware/kinetis_mpu.h
index 9aa4b097c45..01cabaa1068 100644
--- a/arch/arm/src/kinetis/chip/kinetis_mpu.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_mpu.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_mpu.h
+ * arch/arm/src/kinetis/hardware/kinetis_mpu.h
  *
  *   Copyright (C) 2016, 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MPU_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MPU_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MPU_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MPU_H
 
 /********************************************************************************************
  * Included Files
@@ -49,9 +49,9 @@
  */
 
 #if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60)
-#  include "chip/kinetis_k20k40k60mpu.h"
+#  include "hardware/kinetis_k20k40k60mpu.h"
 #elif defined(KINETIS_K28) || defined(KINETIS_K64) || defined(KINETIS_K66)
-#  include "chip/kinetis_k28k64k66mpu.h"
+#  include "hardware/kinetis_k28k64k66mpu.h"
 #else
 #  error "No MPU definitions for this Kinetis part"
 #endif
@@ -72,4 +72,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MPU_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MPU_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_osc.h b/arch/arm/src/kinetis/hardware/kinetis_osc.h
similarity index 95%
rename from arch/arm/src/kinetis/chip/kinetis_osc.h
rename to arch/arm/src/kinetis/hardware/kinetis_osc.h
index e61f0a8c1c6..7bb5077a082 100644
--- a/arch/arm/src/kinetis/chip/kinetis_osc.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_osc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_osc.h
+ * arch/arm/src/kinetis/hardware/kinetis_osc.h
  *
  *   Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIHP_KINETIS_OSC_H
-#define __ARCH_ARM_SRC_KINETIS_CHIHP_KINETIS_OSC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_OSC_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_OSC_H
 
 /********************************************************************************************
  * Included Files
@@ -92,4 +92,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIHP_KINETIS_OSC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_OSC_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_pdb.h b/arch/arm/src/kinetis/hardware/kinetis_pdb.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_pdb.h
rename to arch/arm/src/kinetis/hardware/kinetis_pdb.h
index d0238240dfa..59450c839fa 100644
--- a/arch/arm/src/kinetis/chip/kinetis_pdb.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_pdb.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_pdb.h
+ * arch/arm/src/kinetis/hardware/kinetis_pdb.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PDB_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PDB_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PDB_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PDB_H
 
 /********************************************************************************************
  * Included Files
@@ -260,4 +260,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PDB_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PDB_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_pinmux.h b/arch/arm/src/kinetis/hardware/kinetis_pinmux.h
similarity index 87%
rename from arch/arm/src/kinetis/chip/kinetis_pinmux.h
rename to arch/arm/src/kinetis/hardware/kinetis_pinmux.h
index b94133b83a8..1b5cb3d28c0 100644
--- a/arch/arm/src/kinetis/chip/kinetis_pinmux.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_pinmux.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_pinmux.h
+ * arch/arm/src/kinetis/hardware/kinetis_pinmux.h
  *
  *   Copyright (C) 2011, 2015-2016, 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PINMUX_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PINMUX_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PINMUX_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PINMUX_H
 
 /********************************************************************************************
  * Included Files
@@ -49,17 +49,17 @@
  */
 
 #if defined(KINETIS_K20)
-#  include "chip/kinetis_k20pinmux.h"
+#  include "hardware/kinetis_k20pinmux.h"
 #elif defined(KINETIS_K28)
-#  include "chip/kinetis_k28pinmux.h"
+#  include "hardware/kinetis_k28pinmux.h"
 #elif defined(KINETIS_K40)
-#  include "chip/kinetis_k40pinmux.h"
+#  include "hardware/kinetis_k40pinmux.h"
 #elif defined(KINETIS_K60)
-#  include "chip/kinetis_k60pinmux.h"
+#  include "hardware/kinetis_k60pinmux.h"
 #elif defined(KINETIS_K64)
-#  include "chip/kinetis_k64pinmux.h"
+#  include "hardware/kinetis_k64pinmux.h"
 #elif defined(KINETIS_K66)
-#  include "chip/kinetis_k66pinmux.h"
+#  include "hardware/kinetis_k66pinmux.h"
 #else
 #  error "No pin multiplexing for this Kinetis part"
 #endif
@@ -80,4 +80,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PINMUX_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PINMUX_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_pit.h b/arch/arm/src/kinetis/hardware/kinetis_pit.h
similarity index 97%
rename from arch/arm/src/kinetis/chip/kinetis_pit.h
rename to arch/arm/src/kinetis/hardware/kinetis_pit.h
index 5ccd110a36c..e2f4b37414c 100644
--- a/arch/arm/src/kinetis/chip/kinetis_pit.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_pit.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_pit.h
+ * arch/arm/src/kinetis/hardware/kinetis_pit.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PIT_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PIT_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PIT_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PIT_H
 
 /************************************************************************************
  * Included Files
@@ -138,4 +138,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PIT_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PIT_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_pmc.h b/arch/arm/src/kinetis/hardware/kinetis_pmc.h
similarity index 97%
rename from arch/arm/src/kinetis/chip/kinetis_pmc.h
rename to arch/arm/src/kinetis/hardware/kinetis_pmc.h
index 549ce84d935..1c20902cbca 100644
--- a/arch/arm/src/kinetis/chip/kinetis_pmc.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_pmc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_pmc.h
+ * arch/arm/src/kinetis/hardware/kinetis_pmc.h
  *
  *   Copyright (C) 2011, 2016, 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PMC_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PMC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PMC_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PMC_H
 
 /********************************************************************************************
  * Included Files
@@ -150,4 +150,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PMC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PMC_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_port.h b/arch/arm/src/kinetis/hardware/kinetis_port.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_port.h
rename to arch/arm/src/kinetis/hardware/kinetis_port.h
index 36dfa4e0983..c8109dcacb8 100644
--- a/arch/arm/src/kinetis/chip/kinetis_port.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_port.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_port.h
+ * arch/arm/src/kinetis/hardware/kinetis_port.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PORT_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PORT_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PORT_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PORT_H
 
 /************************************************************************************
  * Included Files
@@ -426,4 +426,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PORT_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_PORT_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_rngb.h b/arch/arm/src/kinetis/hardware/kinetis_rngb.h
similarity index 97%
rename from arch/arm/src/kinetis/chip/kinetis_rngb.h
rename to arch/arm/src/kinetis/hardware/kinetis_rngb.h
index 1e005c08ae3..7c64b37bfb2 100644
--- a/arch/arm/src/kinetis/chip/kinetis_rngb.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_rngb.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_rngb.h
+ * arch/arm/src/kinetis/hardware/kinetis_rngb.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RNGB_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RNGB_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RNGB_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RNGB_H
 
 /************************************************************************************
  * Included Files
@@ -158,4 +158,4 @@
  ************************************************************************************/
 
 #endif /* KINETIS_NRNG && KINETIS_NRNG > 0 */
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RNGB_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RNGB_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_rtc.h b/arch/arm/src/kinetis/hardware/kinetis_rtc.h
similarity index 98%
rename from arch/arm/src/kinetis/chip/kinetis_rtc.h
rename to arch/arm/src/kinetis/hardware/kinetis_rtc.h
index 4ad016af6c0..11abeb16ff7 100644
--- a/arch/arm/src/kinetis/chip/kinetis_rtc.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_rtc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_rtc.h
+ * arch/arm/src/kinetis/hardware/kinetis_rtc.h
  *
  *   Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RTC_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RTC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RTC_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RTC_H
 
 /************************************************************************************
  * Included Files
@@ -274,4 +274,4 @@
  ************************************************************************************/
 
 #endif /* KINETIS_NRTC && KINETIS_NRTC > 0 */
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RTC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_RTC_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_sdhc.h b/arch/arm/src/kinetis/hardware/kinetis_sdhc.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_sdhc.h
rename to arch/arm/src/kinetis/hardware/kinetis_sdhc.h
index b57b85c94e7..f20e39f1a70 100644
--- a/arch/arm/src/kinetis/chip/kinetis_sdhc.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_sdhc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_sdhc.h
+ * arch/arm/src/kinetis/hardware/kinetis_sdhc.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SDHC_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SDHC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SDHC_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SDHC_H
 
 /************************************************************************************
  * Included Files
@@ -385,4 +385,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SDHC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SDHC_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_sim.h b/arch/arm/src/kinetis/hardware/kinetis_sim.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_sim.h
rename to arch/arm/src/kinetis/hardware/kinetis_sim.h
index 87dd39def75..8dddb9e1046 100644
--- a/arch/arm/src/kinetis/chip/kinetis_sim.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_sim.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_sim.h
+ * arch/arm/src/kinetis/hardware/kinetis_sim.h
  *
  *   Copyright (C) 2011, 2016-2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SIM_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SIM_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SIM_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SIM_H
 
 /************************************************************************************
  * Included Files
@@ -1397,4 +1397,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SIM_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SIM_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_slcd.h b/arch/arm/src/kinetis/hardware/kinetis_slcd.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_slcd.h
rename to arch/arm/src/kinetis/hardware/kinetis_slcd.h
index d4a68f07f5a..77a85856906 100644
--- a/arch/arm/src/kinetis/chip/kinetis_slcd.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_slcd.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_slcd.h
+ * arch/arm/src/kinetis/hardware/kinetis_slcd.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SLCD_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SLCD_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SLCD_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SLCD_H
 
 /************************************************************************************
  * Included Files
@@ -417,4 +417,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SLCD_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SLCD_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_smc.h b/arch/arm/src/kinetis/hardware/kinetis_smc.h
similarity index 96%
rename from arch/arm/src/kinetis/chip/kinetis_smc.h
rename to arch/arm/src/kinetis/hardware/kinetis_smc.h
index 19a9d9d14b8..5ab568bd382 100644
--- a/arch/arm/src/kinetis/chip/kinetis_smc.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_smc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_smc.h
+ * arch/arm/src/kinetis/hardware/kinetis_smc.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SMC_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SMC_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SMC_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SMC_H
 
 /************************************************************************************
  * Included Files
@@ -119,4 +119,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SMC_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SMC_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_tsi.h b/arch/arm/src/kinetis/hardware/kinetis_tsi.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_tsi.h
rename to arch/arm/src/kinetis/hardware/kinetis_tsi.h
index 6881150160f..fa4439136d1 100644
--- a/arch/arm/src/kinetis/chip/kinetis_tsi.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_tsi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_tsi.h
+ * arch/arm/src/kinetis/hardware/kinetis_tsi.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_TSI_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_TSI_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_TSI_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_TSI_H
 
 /************************************************************************************
  * Included Files
@@ -308,4 +308,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_TSI_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_TSI_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_uart.h b/arch/arm/src/kinetis/hardware/kinetis_uart.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_uart.h
rename to arch/arm/src/kinetis/hardware/kinetis_uart.h
index d7296ce7066..8331a32ff87 100644
--- a/arch/arm/src/kinetis/chip/kinetis_uart.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_uart.h
+ * arch/arm/src/kinetis/hardware/kinetis_uart.h
  *
  *   Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_UART_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_UART_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_UART_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_UART_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 
 #include 
 
-#include "chip/kinetis_memorymap.h"
+#include "hardware/kinetis_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -509,4 +509,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_UART_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_UART_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_usbdcd.h b/arch/arm/src/kinetis/hardware/kinetis_usbdcd.h
similarity index 97%
rename from arch/arm/src/kinetis/chip/kinetis_usbdcd.h
rename to arch/arm/src/kinetis/hardware/kinetis_usbdcd.h
index 6c4297ff7af..b0ca7e5315e 100644
--- a/arch/arm/src/kinetis/chip/kinetis_usbdcd.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_usbdcd.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_usbdcd.h
+ * arch/arm/src/kinetis/hardware/kinetis_usbdcd.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBDCD_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBDCD_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBDCD_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBDCD_H
 
 /************************************************************************************
  * Included Files
@@ -148,4 +148,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBDCD_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBDCD_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_usbhs.h b/arch/arm/src/kinetis/hardware/kinetis_usbhs.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_usbhs.h
rename to arch/arm/src/kinetis/hardware/kinetis_usbhs.h
index 097b8d2f8c6..539f91c8bd6 100644
--- a/arch/arm/src/kinetis/chip/kinetis_usbhs.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_usbhs.h
@@ -1,5 +1,5 @@
 /********************************************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_usbhs.h
+ * arch/arm/src/kinetis/hardware/kinetis_usbhs.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ******************************************************************************************************************* */
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBHS_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBHS_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBHS_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBHS_H
 
 /********************************************************************************************************************
  * Included Files
@@ -951,4 +951,4 @@
 #define USBPHY_TRIM_OVERRIDE_ENn_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE      (1 << 1)  /* Bit 1:  Override enable for ENV_TAIL_ADJ */
 #define USBPHY_TRIM_OVERRIDE_ENn_TRIM_DIV_SEL_OVERRIDE              (1 << 0)  /* Bit 0:  Override enable for PLL_DIV_SEL */
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBHS_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBHS_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_usbotg.h b/arch/arm/src/kinetis/hardware/kinetis_usbotg.h
similarity index 99%
rename from arch/arm/src/kinetis/chip/kinetis_usbotg.h
rename to arch/arm/src/kinetis/hardware/kinetis_usbotg.h
index 490eae1ff73..10091175d80 100644
--- a/arch/arm/src/kinetis/chip/kinetis_usbotg.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_usbotg.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_usbotg.h
+ * arch/arm/src/kinetis/hardware/kinetis_usbotg.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBOTG_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBOTG_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBOTG_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBOTG_H
 
 /********************************************************************************************
  * Included Files
@@ -374,4 +374,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBOTG_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_USBOTG_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_vrefv1.h b/arch/arm/src/kinetis/hardware/kinetis_vrefv1.h
similarity index 95%
rename from arch/arm/src/kinetis/chip/kinetis_vrefv1.h
rename to arch/arm/src/kinetis/hardware/kinetis_vrefv1.h
index 29c871dd22d..cdc28b0fb95 100644
--- a/arch/arm/src/kinetis/chip/kinetis_vrefv1.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_vrefv1.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_vrefv1.h
+ * arch/arm/src/kinetis/hardware/kinetis_vrefv1.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_VREFV1_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_VREFV1_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_VREFV1_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_VREFV1_H
 
 /********************************************************************************************
  * Included Files
@@ -89,4 +89,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_VREFV1_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_VREFV1_H */
diff --git a/arch/arm/src/kinetis/chip/kinetis_wdog.h b/arch/arm/src/kinetis/hardware/kinetis_wdog.h
similarity index 97%
rename from arch/arm/src/kinetis/chip/kinetis_wdog.h
rename to arch/arm/src/kinetis/hardware/kinetis_wdog.h
index 6f503860499..64629d5e1b2 100644
--- a/arch/arm/src/kinetis/chip/kinetis_wdog.h
+++ b/arch/arm/src/kinetis/hardware/kinetis_wdog.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kinetis/chip/kinetis_wdog.h
+ * arch/arm/src/kinetis/hardware/kinetis_wdog.h
  *
  *   Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_WDOG_H
-#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_WDOG_H
+#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_WDOG_H
+#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_WDOG_H
 
 /********************************************************************************************
  * Included Files
@@ -134,4 +134,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_WDOG_H */
+#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_WDOG_H */
diff --git a/arch/arm/src/kinetis/kinetis.h b/arch/arm/src/kinetis/kinetis.h
index 1cde44c4df0..0da3574d13f 100644
--- a/arch/arm/src/kinetis/kinetis.h
+++ b/arch/arm/src/kinetis/kinetis.h
@@ -53,7 +53,7 @@
 #include "up_internal.h"
 #include "kinetis_config.h"
 #include "chip.h"
-#include "chip/kinetis_port.h"
+#include "hardware/kinetis_port.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/kinetis/kinetis_clockconfig.c b/arch/arm/src/kinetis/kinetis_clockconfig.c
index 28218fcd86c..2da49e3246d 100644
--- a/arch/arm/src/kinetis/kinetis_clockconfig.c
+++ b/arch/arm/src/kinetis/kinetis_clockconfig.c
@@ -43,13 +43,13 @@
 #include "up_arch.h"
 
 #include "kinetis.h"
-#include "chip/kinetis_mcg.h"
-#include "chip/kinetis_sim.h"
-#include "chip/kinetis_fmc.h"
-#include "chip/kinetis_pmc.h"
-#include "chip/kinetis_llwu.h"
-#include "chip/kinetis_pinmux.h"
-#include "chip/kinetis_osc.h"
+#include "hardware/kinetis_mcg.h"
+#include "hardware/kinetis_sim.h"
+#include "hardware/kinetis_fmc.h"
+#include "hardware/kinetis_pmc.h"
+#include "hardware/kinetis_llwu.h"
+#include "hardware/kinetis_pinmux.h"
+#include "hardware/kinetis_osc.h"
 
 #include 
 
diff --git a/arch/arm/src/kinetis/kinetis_dma.c b/arch/arm/src/kinetis/kinetis_dma.c
index df7fc052cb3..254f2b727e7 100644
--- a/arch/arm/src/kinetis/kinetis_dma.c
+++ b/arch/arm/src/kinetis/kinetis_dma.c
@@ -58,8 +58,8 @@
 #include "kinetis_config.h"
 #include "chip.h"
 #include "kinetis_dma.h"
-#include "chip/kinetis_dmamux.h"
-#include "chip/kinetis_sim.h"
+#include "hardware/kinetis_dmamux.h"
+#include "hardware/kinetis_sim.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/kinetis/kinetis_dma.h b/arch/arm/src/kinetis/kinetis_dma.h
index 64ada268010..68aae63525c 100644
--- a/arch/arm/src/kinetis/kinetis_dma.h
+++ b/arch/arm/src/kinetis/kinetis_dma.h
@@ -45,7 +45,7 @@
 #include 
 #include 
 
-#include "chip/kinetis_dma.h"
+#include "hardware/kinetis_dma.h"
 
 /****************************************************************************
  * Pre-processor Declarations
diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c
index e7265c6a95d..21c60249813 100644
--- a/arch/arm/src/kinetis/kinetis_enet.c
+++ b/arch/arm/src/kinetis/kinetis_enet.c
@@ -68,10 +68,10 @@
 #include "chip.h"
 #include "kinetis.h"
 #include "kinetis_config.h"
-#include "chip/kinetis_pinmux.h"
-#include "chip/kinetis_sim.h"
-#include "chip/kinetis_mpu.h"
-#include "chip/kinetis_enet.h"
+#include "hardware/kinetis_pinmux.h"
+#include "hardware/kinetis_sim.h"
+#include "hardware/kinetis_mpu.h"
+#include "hardware/kinetis_enet.h"
 
 #if defined(KINETIS_NENET) && KINETIS_NENET > 0
 
diff --git a/arch/arm/src/kinetis/kinetis_i2c.c b/arch/arm/src/kinetis/kinetis_i2c.c
index 623921a0d45..e7524e9d371 100644
--- a/arch/arm/src/kinetis/kinetis_i2c.c
+++ b/arch/arm/src/kinetis/kinetis_i2c.c
@@ -61,9 +61,9 @@
 
 #include "kinetis_config.h"
 #include "chip.h"
-#include "chip/kinetis_i2c.h"
-#include "chip/kinetis_sim.h"
-#include "chip/kinetis_pinmux.h"
+#include "hardware/kinetis_i2c.h"
+#include "hardware/kinetis_sim.h"
+#include "hardware/kinetis_pinmux.h"
 #include "kinetis.h"
 #include "kinetis_i2c.h"
 
diff --git a/arch/arm/src/kinetis/kinetis_i2c.h b/arch/arm/src/kinetis/kinetis_i2c.h
index 8cb4246a17f..ff8b26db5ef 100644
--- a/arch/arm/src/kinetis/kinetis_i2c.h
+++ b/arch/arm/src/kinetis/kinetis_i2c.h
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/kinetis_i2c.h"
+#include "hardware/kinetis_i2c.h"
 
 /****************************************************************************
  * Public Function Prototypes
diff --git a/arch/arm/src/kinetis/kinetis_lowputc.c b/arch/arm/src/kinetis/kinetis_lowputc.c
index a7667f3c9a2..8661f952a7e 100644
--- a/arch/arm/src/kinetis/kinetis_lowputc.c
+++ b/arch/arm/src/kinetis/kinetis_lowputc.c
@@ -51,10 +51,10 @@
 
 #include "kinetis_config.h"
 #include "kinetis.h"
-#include "chip/kinetis_uart.h"
-#include "chip/kinetis_lpuart.h"
-#include "chip/kinetis_sim.h"
-#include "chip/kinetis_pinmux.h"
+#include "hardware/kinetis_uart.h"
+#include "hardware/kinetis_lpuart.h"
+#include "hardware/kinetis_sim.h"
+#include "hardware/kinetis_pinmux.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/kinetis/kinetis_lpserial.c b/arch/arm/src/kinetis/kinetis_lpserial.c
index 227acc06e01..177a4a7e6be 100644
--- a/arch/arm/src/kinetis/kinetis_lpserial.c
+++ b/arch/arm/src/kinetis/kinetis_lpserial.c
@@ -64,8 +64,8 @@
 #include "up_internal.h"
 
 #include "kinetis.h"
-#include "chip/kinetis_lpuart.h"
-#include "chip/kinetis_pinmux.h"
+#include "hardware/kinetis_lpuart.h"
+#include "hardware/kinetis_pinmux.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/kinetis/kinetis_mpuinit.c b/arch/arm/src/kinetis/kinetis_mpuinit.c
index 9618b5a071d..9817a4497f6 100644
--- a/arch/arm/src/kinetis/kinetis_mpuinit.c
+++ b/arch/arm/src/kinetis/kinetis_mpuinit.c
@@ -45,7 +45,7 @@
 
 #include "mpu.h"
 #include "kinetis_mpuinit.h"
-#include "chip/kinetis_mpu.h"
+#include "hardware/kinetis_mpu.h"
 
 #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU)
 
diff --git a/arch/arm/src/kinetis/kinetis_pin.c b/arch/arm/src/kinetis/kinetis_pin.c
index 4a084f6c275..9c76453dd4d 100644
--- a/arch/arm/src/kinetis/kinetis_pin.c
+++ b/arch/arm/src/kinetis/kinetis_pin.c
@@ -49,8 +49,8 @@
 #include "up_internal.h"
 
 #include "kinetis.h"
-#include "chip/kinetis_port.h"
-#include "chip/kinetis_gpio.h"
+#include "hardware/kinetis_port.h"
+#include "hardware/kinetis_gpio.h"
 
 /****************************************************************************
  * Public Functions
diff --git a/arch/arm/src/kinetis/kinetis_pindump.c b/arch/arm/src/kinetis/kinetis_pindump.c
index a660c87307c..c59d328321a 100644
--- a/arch/arm/src/kinetis/kinetis_pindump.c
+++ b/arch/arm/src/kinetis/kinetis_pindump.c
@@ -46,8 +46,8 @@
 #include "up_arch.h"
 
 #include "kinetis.h"
-#include "chip/kinetis_gpio.h"
-#include "chip/kinetis_port.h"
+#include "hardware/kinetis_gpio.h"
+#include "hardware/kinetis_port.h"
 
 #ifdef CONFIG_DEBUG_GPIO_INFO
 
diff --git a/arch/arm/src/kinetis/kinetis_pingpio.c b/arch/arm/src/kinetis/kinetis_pingpio.c
index b8879208164..1b7f6da5608 100644
--- a/arch/arm/src/kinetis/kinetis_pingpio.c
+++ b/arch/arm/src/kinetis/kinetis_pingpio.c
@@ -49,7 +49,7 @@
 #include "up_internal.h"
 
 #include "kinetis.h"
-#include "chip/kinetis_gpio.h"
+#include "hardware/kinetis_gpio.h"
 
 /****************************************************************************
  * Public Functions
diff --git a/arch/arm/src/kinetis/kinetis_pinirq.c b/arch/arm/src/kinetis/kinetis_pinirq.c
index 556bd518b56..f807a8be500 100644
--- a/arch/arm/src/kinetis/kinetis_pinirq.c
+++ b/arch/arm/src/kinetis/kinetis_pinirq.c
@@ -51,7 +51,7 @@
 #include "up_internal.h"
 
 #include "kinetis.h"
-#include "chip/kinetis_port.h"
+#include "hardware/kinetis_port.h"
 
 #ifdef CONFIG_KINETIS_GPIOIRQ
 
diff --git a/arch/arm/src/kinetis/kinetis_pwm.c b/arch/arm/src/kinetis/kinetis_pwm.c
index b4dd646c9a6..1aada49b726 100644
--- a/arch/arm/src/kinetis/kinetis_pwm.c
+++ b/arch/arm/src/kinetis/kinetis_pwm.c
@@ -60,9 +60,9 @@
 
 #include "kinetis.h"
 #include "kinetis_pwm.h"
-#include "chip/kinetis_gpio.h"
-#include "chip/kinetis_ftm.h"
-#include "chip/kinetis_sim.h"
+#include "hardware/kinetis_gpio.h"
+#include "hardware/kinetis_ftm.h"
+#include "hardware/kinetis_sim.h"
 
 /* This module then only compiles if there is at least one enabled timer
  * intended for use with the PWM upper half driver.
diff --git a/arch/arm/src/kinetis/kinetis_pwm.h b/arch/arm/src/kinetis/kinetis_pwm.h
index 3caf77c6d2d..140fbf0f6e9 100644
--- a/arch/arm/src/kinetis/kinetis_pwm.h
+++ b/arch/arm/src/kinetis/kinetis_pwm.h
@@ -77,7 +77,7 @@
     defined(CONFIG_KINETIS_FTM2_PWM)  || defined(CONFIG_KINETIS_FTM3_PWM)
 
 #include 
-#include "chip/kinetis_pinmux.h"
+#include "hardware/kinetis_pinmux.h"
 
 /* For each timer that is enabled for PWM usage, we need the following additional
  * configuration settings:
diff --git a/arch/arm/src/kinetis/kinetis_rtc.c b/arch/arm/src/kinetis/kinetis_rtc.c
index d3e9a069f84..3617cd095f8 100644
--- a/arch/arm/src/kinetis/kinetis_rtc.c
+++ b/arch/arm/src/kinetis/kinetis_rtc.c
@@ -53,8 +53,8 @@
 
 #include "kinetis_config.h"
 #include "chip.h"
-#include "chip/kinetis_rtc.h"
-#include "chip/kinetis_sim.h"
+#include "hardware/kinetis_rtc.h"
+#include "hardware/kinetis_sim.h"
 #include "kinetis.h"
 #include "kinetis_alarm.h"
 
diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c
index 9f6fe29f39c..9820513274a 100644
--- a/arch/arm/src/kinetis/kinetis_sdhc.c
+++ b/arch/arm/src/kinetis/kinetis_sdhc.c
@@ -62,9 +62,9 @@
 #include "up_arch.h"
 
 #include "kinetis.h"
-#include "chip/kinetis_pinmux.h"
-#include "chip/kinetis_sim.h"
-#include "chip/kinetis_sdhc.h"
+#include "hardware/kinetis_pinmux.h"
+#include "hardware/kinetis_sim.h"
+#include "hardware/kinetis_sdhc.h"
 
 #ifdef CONFIG_KINETIS_SDHC
 
diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c
index 58c4b575b93..e6c50b260e5 100644
--- a/arch/arm/src/kinetis/kinetis_serial.c
+++ b/arch/arm/src/kinetis/kinetis_serial.c
@@ -66,9 +66,9 @@
 
 #include "kinetis_config.h"
 #include "chip.h"
-#include "chip/kinetis_dmamux.h"
-#include "chip/kinetis_uart.h"
-#include "chip/kinetis_pinmux.h"
+#include "hardware/kinetis_dmamux.h"
+#include "hardware/kinetis_uart.h"
+#include "hardware/kinetis_pinmux.h"
 #include "kinetis.h"
 #include "kinetis_dma.h"
 #include "kinetis_uart.h"
diff --git a/arch/arm/src/kinetis/kinetis_spi.c b/arch/arm/src/kinetis/kinetis_spi.c
index ce3971518e8..7b8280c90d5 100644
--- a/arch/arm/src/kinetis/kinetis_spi.c
+++ b/arch/arm/src/kinetis/kinetis_spi.c
@@ -83,10 +83,10 @@
 
 #include "kinetis.h"
 #include "kinetis_spi.h"
-#include "chip/kinetis_memorymap.h"
-#include "chip/kinetis_sim.h"
-#include "chip/kinetis_dspi.h"
-#include "chip/kinetis_pinmux.h"
+#include "hardware/kinetis_memorymap.h"
+#include "hardware/kinetis_sim.h"
+#include "hardware/kinetis_dspi.h"
+#include "hardware/kinetis_pinmux.h"
 
 #if defined(CONFIG_KINETIS_SPI0) || defined(CONFIG_KINETIS_SPI1) || \
     defined(CONFIG_KINETIS_SPI2)
diff --git a/arch/arm/src/kinetis/kinetis_spi.h b/arch/arm/src/kinetis/kinetis_spi.h
index 4d3ce60ce24..b384311f7a8 100644
--- a/arch/arm/src/kinetis/kinetis_spi.h
+++ b/arch/arm/src/kinetis/kinetis_spi.h
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/kinetis_dspi.h"
+#include "hardware/kinetis_dspi.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c
index de7b0194284..937bf95b878 100644
--- a/arch/arm/src/kinetis/kinetis_start.c
+++ b/arch/arm/src/kinetis/kinetis_start.c
@@ -49,13 +49,11 @@
 #include "up_internal.h"
 
 #include "kinetis.h"
-#include "chip/kinetis_smc.h"
+#include "hardware/kinetis_smc.h"
 #include "kinetis_mpuinit.h"
 #include "kinetis_userspace.h"
 
-#ifdef CONFIG_ARCH_FPU
-#  include "nvic.h"
-#endif
+#include "nvic.h"
 
 #include "kinetis_start.h"
 
diff --git a/arch/arm/src/kinetis/kinetis_tpm.h b/arch/arm/src/kinetis/kinetis_tpm.h
index 03fe3b13627..5d256cd2d3e 100644
--- a/arch/arm/src/kinetis/kinetis_tpm.h
+++ b/arch/arm/src/kinetis/kinetis_tpm.h
@@ -50,7 +50,7 @@
  */
 
 #if defined(KINETIS_K66)
-#  include "chip/kinetis_kx6tpm.h"
+#  include "hardware/kinetis_kx6tpm.h"
 #else
 #  error "No TMP definitions for this Kinetis part"
 #endif
diff --git a/arch/arm/src/kinetis/kinetis_uid.c b/arch/arm/src/kinetis/kinetis_uid.c
index 954c667f418..6667a792a93 100644
--- a/arch/arm/src/kinetis/kinetis_uid.c
+++ b/arch/arm/src/kinetis/kinetis_uid.c
@@ -38,8 +38,8 @@
 
 #include 
 
-#include 
-#include 
+#include "hardware/kinetis_k64memorymap.h"
+#include "hardware/kinetis_sim.h"
 #include "kinetis_uid.h"
 
 #ifdef CONFIG_BOARDCTL_UNIQUEID
diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c
index 20ebd6d2301..c3a668592af 100644
--- a/arch/arm/src/kinetis/kinetis_usbdev.c
+++ b/arch/arm/src/kinetis/kinetis_usbdev.c
@@ -71,8 +71,8 @@
 #include "up_arch.h"
 #include "kinetis.h"
 #include "kinetis_usbotg.h"
-#include "chip/kinetis_sim.h"
-#include "chip/kinetis_fmc.h"
+#include "hardware/kinetis_sim.h"
+#include "hardware/kinetis_fmc.h"
 
 #if defined(CONFIG_USBDEV)
 
diff --git a/arch/arm/src/kinetis/kinetis_usbotg.h b/arch/arm/src/kinetis/kinetis_usbotg.h
index 6353cf7f467..f31d3426af1 100644
--- a/arch/arm/src/kinetis/kinetis_usbotg.h
+++ b/arch/arm/src/kinetis/kinetis_usbotg.h
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/kinetis_usbotg.h"
+#include "hardware/kinetis_usbotg.h"
 
 /************************************************************************************
  * Public Types
diff --git a/arch/arm/src/kinetis/kinetis_wdog.c b/arch/arm/src/kinetis/kinetis_wdog.c
index 3beaad8d4bc..463150bc139 100644
--- a/arch/arm/src/kinetis/kinetis_wdog.c
+++ b/arch/arm/src/kinetis/kinetis_wdog.c
@@ -43,7 +43,7 @@
 
 #include "up_arch.h"
 #include "kinetis.h"
-#include "chip/kinetis_wdog.h"
+#include "hardware/kinetis_wdog.h"
 
 /****************************************************************************
  * Private Functions
diff --git a/arch/arm/src/kl/Make.defs b/arch/arm/src/kl/Make.defs
index 2eee8cd6021..47cda3b01d3 100644
--- a/arch/arm/src/kl/Make.defs
+++ b/arch/arm/src/kl/Make.defs
@@ -49,11 +49,9 @@ CMN_CSRCS += up_hardfault.c up_svcall.c up_vectors.c up_vfork.c
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
diff --git a/arch/arm/src/kl/chip.h b/arch/arm/src/kl/chip.h
index 0f4df66c96a..4d4b01bad0a 100644
--- a/arch/arm/src/kl/chip.h
+++ b/arch/arm/src/kl/chip.h
@@ -54,7 +54,7 @@
  * this file for the proper setup.
  */
 
-#include "chip/kl_memorymap.h"
+#include "hardware/kl_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/kl/chip/k25z128_pinmux.h b/arch/arm/src/kl/hardware/k25z128_pinmux.h
similarity index 99%
rename from arch/arm/src/kl/chip/k25z128_pinmux.h
rename to arch/arm/src/kl/hardware/k25z128_pinmux.h
index 597b55581c2..dd16c20bbe1 100644
--- a/arch/arm/src/kl/chip/k25z128_pinmux.h
+++ b/arch/arm/src/kl/hardware/k25z128_pinmux.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kl/k25z128_pinmux.h
+ * arch/arm/src/kl/hardware/k25z128_pinmux.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -336,4 +336,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_K40PINMUX_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_K25PINMUX_H */
diff --git a/arch/arm/src/kl/chip/kl_fmc.h b/arch/arm/src/kl/hardware/kl_fmc.h
similarity index 99%
rename from arch/arm/src/kl/chip/kl_fmc.h
rename to arch/arm/src/kl/hardware/kl_fmc.h
index d11aedc6b1a..4d196235702 100644
--- a/arch/arm/src/kl/chip/kl_fmc.h
+++ b/arch/arm/src/kl/hardware/kl_fmc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kl/kl_fmc.h
+ * arch/arm/src/kl/hardware/kl_fmc.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KL_KL_FMC_H
-#define __ARCH_ARM_SRC_KL_KL_FMC_H
+#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_FMC_H
+#define __ARCH_ARM_SRC_KL_HARDWARE_KL_FMC_H
 
 /************************************************************************************
  * Included Files
@@ -386,4 +386,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KL_KL_FMC_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_FMC_H */
diff --git a/arch/arm/src/kl/chip/kl_gpio.h b/arch/arm/src/kl/hardware/kl_gpio.h
similarity index 97%
rename from arch/arm/src/kl/chip/kl_gpio.h
rename to arch/arm/src/kl/hardware/kl_gpio.h
index c2ea98ed25e..4371103aea5 100644
--- a/arch/arm/src/kl/chip/kl_gpio.h
+++ b/arch/arm/src/kl/hardware/kl_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kl/chip/kl_gpio.h
+ * arch/arm/src/kl/hardware/kl_gpio.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KL_CHIP_KL_GPIO_H
-#define __ARCH_ARM_SRC_KL_CHIP_KL_GPIO_H
+#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_GPIO_H
+#define __ARCH_ARM_SRC_KL_HARDWARE_KL_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -159,4 +159,4 @@ extern "C"
 }
 #endif
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_KL_CHIP_KL_GPIO_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_GPIO_H */
diff --git a/arch/arm/src/kl/chip/kl_i2c.h b/arch/arm/src/kl/hardware/kl_i2c.h
similarity index 98%
rename from arch/arm/src/kl/chip/kl_i2c.h
rename to arch/arm/src/kl/hardware/kl_i2c.h
index a2c1941ddab..f6e9291e40c 100644
--- a/arch/arm/src/kl/chip/kl_i2c.h
+++ b/arch/arm/src/kl/hardware/kl_i2c.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kl/chip/kl_i2c.h
+ * arch/arm/src/kl/hardware/kl_i2c.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KL_CHIP_KL_I2C_H
-#define __ARCH_ARM_SRC_KL_CHIP_KL_I2C_H
+#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_I2C_H
+#define __ARCH_ARM_SRC_KL_HARDWARE_KL_I2C_H
 
 /********************************************************************************************
  * Included Files
@@ -185,4 +185,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KL_CHIP_KL_I2C_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_I2C_H */
diff --git a/arch/arm/src/kl/chip/kl_llwu.h b/arch/arm/src/kl/hardware/kl_llwu.h
similarity index 98%
rename from arch/arm/src/kl/chip/kl_llwu.h
rename to arch/arm/src/kl/hardware/kl_llwu.h
index d843689639c..51ac66ebc89 100644
--- a/arch/arm/src/kl/chip/kl_llwu.h
+++ b/arch/arm/src/kl/hardware/kl_llwu.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kl/kl_llwu.h
+ * arch/arm/src/kl/hardware/kl_llwu.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KL_KL_LLWU_H
-#define __ARCH_ARM_SRC_KL_KL_LLWU_H
+#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_LLWU_H
+#define __ARCH_ARM_SRC_KL_HARDWARE_KL_LLWU_H
 
 /************************************************************************************
  * Included Files
@@ -249,4 +249,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KL_KL_LLWU_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_LLWU_H */
diff --git a/arch/arm/src/kl/chip/kl_mcg.h b/arch/arm/src/kl/hardware/kl_mcg.h
similarity index 98%
rename from arch/arm/src/kl/chip/kl_mcg.h
rename to arch/arm/src/kl/hardware/kl_mcg.h
index 4e6f2d9dfea..7b14eb67637 100644
--- a/arch/arm/src/kl/chip/kl_mcg.h
+++ b/arch/arm/src/kl/hardware/kl_mcg.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kl/kl_mcg.h
+ * arch/arm/src/kl/hardware/kl_mcg.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KL_KL_MCG_H
-#define __ARCH_ARM_SRC_KL_KL_MCG_H
+#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_MCG_H
+#define __ARCH_ARM_SRC_KL_HARDWARE_KL_MCG_H
 
 /************************************************************************************
  * Included Files
@@ -183,4 +183,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KL_KL_MCG_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_MCG_H */
diff --git a/arch/arm/src/kl/chip/kl_memorymap.h b/arch/arm/src/kl/hardware/kl_memorymap.h
similarity index 97%
rename from arch/arm/src/kl/chip/kl_memorymap.h
rename to arch/arm/src/kl/hardware/kl_memorymap.h
index c89f70f7308..3ce8ba8e4db 100644
--- a/arch/arm/src/kl/chip/kl_memorymap.h
+++ b/arch/arm/src/kl/hardware/kl_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kl/kl_memorymap.h
+ * arch/arm/src/kl/hardware/kl_memorymap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KL_KL_MEMORYMAP_H
-#define __ARCH_ARM_SRC_KL_KL_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_MEMORYMAP_H
+#define __ARCH_ARM_SRC_KL_HARDWARE_KL_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -137,4 +137,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KL_KL_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_MEMORYMAP_H */
diff --git a/arch/arm/src/kl/chip/kl_osc.h b/arch/arm/src/kl/hardware/kl_osc.h
similarity index 95%
rename from arch/arm/src/kl/chip/kl_osc.h
rename to arch/arm/src/kl/hardware/kl_osc.h
index 8edef1e3cdf..16487a1aa0b 100644
--- a/arch/arm/src/kl/chip/kl_osc.h
+++ b/arch/arm/src/kl/hardware/kl_osc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kl/kl_osc.h
+ * arch/arm/src/kl/hardware/kl_osc.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KL_KL_OSC_H
-#define __ARCH_ARM_SRC_KL_KL_OSC_H
+#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_OSC_H
+#define __ARCH_ARM_SRC_KL_HARDWARE_KL_OSC_H
 
 /********************************************************************************************
  * Included Files
@@ -81,4 +81,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KL_KL_OSC_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_OSC_H */
diff --git a/arch/arm/src/kl/chip/kl_pinmux.h b/arch/arm/src/kl/hardware/kl_pinmux.h
similarity index 94%
rename from arch/arm/src/kl/chip/kl_pinmux.h
rename to arch/arm/src/kl/hardware/kl_pinmux.h
index 6f8e8cfc4a0..a88d947e7a3 100644
--- a/arch/arm/src/kl/chip/kl_pinmux.h
+++ b/arch/arm/src/kl/hardware/kl_pinmux.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kl/kl_pinmux.h
+ * arch/arm/src/kl/hardware/kl_pinmux.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KL_KL_PINMUX_H
-#define __ARCH_ARM_SRC_KL_KL_PINMUX_H
+#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_PINMUX_H
+#define __ARCH_ARM_SRC_KL_HARDWARE_KL_PINMUX_H
 
 /********************************************************************************************
  * Included Files
@@ -66,4 +66,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KL_KL_PINMUX_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_PINMUX_H */
diff --git a/arch/arm/src/kl/chip/kl_pit.h b/arch/arm/src/kl/hardware/kl_pit.h
similarity index 96%
rename from arch/arm/src/kl/chip/kl_pit.h
rename to arch/arm/src/kl/hardware/kl_pit.h
index 204ceb0c34c..e92ac90da66 100644
--- a/arch/arm/src/kl/chip/kl_pit.h
+++ b/arch/arm/src/kl/hardware/kl_pit.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/kl/kl_pit.h
+ * arch/arm/src/kl/hardware/kl_pit.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KL_KL_PIT_H
-#define __ARCH_ARM_SRC_KL_KL_PIT_H
+#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_PIT_H
+#define __ARCH_ARM_SRC_KL_HARDWARE_KL_PIT_H
 
 /****************************************************************************
  * Included Files
@@ -96,4 +96,4 @@
  * Public Function Prototypes
  ****************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KL_KL_PIT_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_PIT_H */
diff --git a/arch/arm/src/kl/chip/kl_port.h b/arch/arm/src/kl/hardware/kl_port.h
similarity index 99%
rename from arch/arm/src/kl/chip/kl_port.h
rename to arch/arm/src/kl/hardware/kl_port.h
index 3311cd4e284..1d4fc8d8269 100644
--- a/arch/arm/src/kl/chip/kl_port.h
+++ b/arch/arm/src/kl/hardware/kl_port.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kl/kl_port.h
+ * arch/arm/src/kl/hardware/kl_port.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KL_KL_PORT_H
-#define __ARCH_ARM_SRC_KL_KL_PORT_H
+#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_PORT_H
+#define __ARCH_ARM_SRC_KL_HARDWARE_KL_PORT_H
 
 /************************************************************************************
  * Included Files
@@ -428,4 +428,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KL_KL_PORT_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_PORT_H */
diff --git a/arch/arm/src/kl/chip/kl_sim.h b/arch/arm/src/kl/hardware/kl_sim.h
similarity index 99%
rename from arch/arm/src/kl/chip/kl_sim.h
rename to arch/arm/src/kl/hardware/kl_sim.h
index 001324eb422..046b4105ad1 100644
--- a/arch/arm/src/kl/chip/kl_sim.h
+++ b/arch/arm/src/kl/hardware/kl_sim.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kl/kl_sim.h
+ * arch/arm/src/kl/hardware/kl_sim.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KL_KL_SIM_H
-#define __ARCH_ARM_SRC_KL_KL_SIM_H
+#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_SIM_H
+#define __ARCH_ARM_SRC_KL_HARDWARE_KL_SIM_H
 
 /************************************************************************************
  * Included Files
@@ -387,4 +387,4 @@
 /************************************************************************************
  * Public Functions
  ************************************************************************************/
-#endif /* __ARCH_ARM_SRC_KL_KL_SIM_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_SIM_H */
diff --git a/arch/arm/src/kl/chip/kl_spi.h b/arch/arm/src/kl/hardware/kl_spi.h
similarity index 97%
rename from arch/arm/src/kl/chip/kl_spi.h
rename to arch/arm/src/kl/hardware/kl_spi.h
index f24633457b7..6f1bf439ebb 100644
--- a/arch/arm/src/kl/chip/kl_spi.h
+++ b/arch/arm/src/kl/hardware/kl_spi.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/kl/kl_spi.h
+ * arch/arm/src/kl/hardware/kl_spi.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KL_CHIP_KL_SPI_H
-#define __ARCH_ARM_SRC_KL_CHIP_KL_SPI_H
+#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_SPI_H
+#define __ARCH_ARM_SRC_KL_HARDWARE_KL_SPI_H
 
 /********************************************************************************************
  * Included Files
@@ -136,4 +136,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KL_CHIP_KL_SPI_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_SPI_H */
diff --git a/arch/arm/src/kl/chip/kl_tpm.h b/arch/arm/src/kl/hardware/kl_tpm.h
similarity index 98%
rename from arch/arm/src/kl/chip/kl_tpm.h
rename to arch/arm/src/kl/hardware/kl_tpm.h
index 9f898ba1feb..e95a71d8aeb 100644
--- a/arch/arm/src/kl/chip/kl_tpm.h
+++ b/arch/arm/src/kl/hardware/kl_tpm.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/kl/kl_tpm.h
+ * arch/arm/src/kl/hardware/kl_tpm.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KL_KL_TPM_H
-#define __ARCH_ARM_SRC_KL_KL_TPM_H
+#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_TPM_H
+#define __ARCH_ARM_SRC_KL_HARDWARE_KL_TPM_H
 
 /****************************************************************************
  * Included Files
@@ -208,4 +208,4 @@
  * Public Function Prototypes
  ****************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KL_KL_TPM_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_TPM_H */
diff --git a/arch/arm/src/kl/chip/kl_tsi.h b/arch/arm/src/kl/hardware/kl_tsi.h
similarity index 98%
rename from arch/arm/src/kl/chip/kl_tsi.h
rename to arch/arm/src/kl/hardware/kl_tsi.h
index 8e0d87e905b..8773f34aca9 100644
--- a/arch/arm/src/kl/chip/kl_tsi.h
+++ b/arch/arm/src/kl/hardware/kl_tsi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kl/chip/kl_tsi.h
+ * arch/arm/src/kl/hardware/kl_tsi.h
  *
  *   Copyright (C) 2013 Alan Carvalho de Assis
  *   Author: Alan Carvalho de Assis 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KL_CHIP_KL_TSI_H
-#define __ARCH_ARM_SRC_KL_CHIP_KL_TSI_H
+#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_TSI_H
+#define __ARCH_ARM_SRC_KL_HARDWARE_KL_TSI_H
 
 /************************************************************************************
  * Included Files
@@ -151,4 +151,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KL_CHIP_KL_TSI_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_TSI_H */
diff --git a/arch/arm/src/kl/chip/kl_uart.h b/arch/arm/src/kl/hardware/kl_uart.h
similarity index 98%
rename from arch/arm/src/kl/chip/kl_uart.h
rename to arch/arm/src/kl/hardware/kl_uart.h
index 9b0cf80bae5..7fd9c883be3 100644
--- a/arch/arm/src/kl/chip/kl_uart.h
+++ b/arch/arm/src/kl/hardware/kl_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/kl/kl_uart.h
+ * arch/arm/src/kl/hardware/kl_uart.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_KL_KL_UART_H
-#define __ARCH_ARM_SRC_KL_KL_UART_H
+#ifndef __ARCH_ARM_SRC_KL_HARDWARE_KL_UART_H
+#define __ARCH_ARM_SRC_KL_HARDWARE_KL_UART_H
 
 /************************************************************************************
  * Included Files
@@ -219,4 +219,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_KL_KL_UART_H */
+#endif /* __ARCH_ARM_SRC_KL_HARDWARE_KL_UART_H */
diff --git a/arch/arm/src/kl/kl_clockconfig.c b/arch/arm/src/kl/kl_clockconfig.c
index b414500f2cd..1a5ac1463a7 100644
--- a/arch/arm/src/kl/kl_clockconfig.c
+++ b/arch/arm/src/kl/kl_clockconfig.c
@@ -47,12 +47,12 @@
 
 #include "chip.h"
 #include "kl_gpio.h"
-#include "chip/kl_mcg.h"
-#include "chip/kl_sim.h"
-#include "chip/kl_osc.h"
-#include "chip/kl_fmc.h"
-#include "chip/kl_llwu.h"
-#include "chip/kl_pinmux.h"
+#include "hardware/kl_mcg.h"
+#include "hardware/kl_sim.h"
+#include "hardware/kl_osc.h"
+#include "hardware/kl_fmc.h"
+#include "hardware/kl_llwu.h"
+#include "hardware/kl_pinmux.h"
 
 /****************************************************************************
  * Private Data
diff --git a/arch/arm/src/kl/kl_gpio.h b/arch/arm/src/kl/kl_gpio.h
index 2ea91c081a8..205981e49b0 100644
--- a/arch/arm/src/kl/kl_gpio.h
+++ b/arch/arm/src/kl/kl_gpio.h
@@ -47,8 +47,8 @@
 #include 
 
 #include "kl_config.h"
-#include "chip/kl_gpio.h"
-#include "chip/kl_port.h"
+#include "hardware/kl_gpio.h"
+#include "hardware/kl_port.h"
 
 /****************************************************************************
  * Pre-processor Declarations
diff --git a/arch/arm/src/kl/kl_gpioirq.c b/arch/arm/src/kl/kl_gpioirq.c
index cfd3f4a86f9..6261065e267 100644
--- a/arch/arm/src/kl/kl_gpioirq.c
+++ b/arch/arm/src/kl/kl_gpioirq.c
@@ -48,7 +48,7 @@
 
 #include "up_arch.h"
 
-#include "chip/kl_port.h"
+#include "hardware/kl_port.h"
 #include "kl_gpio.h"
 
 #ifdef CONFIG_KL_GPIOIRQ
diff --git a/arch/arm/src/kl/kl_lowputc.c b/arch/arm/src/kl/kl_lowputc.c
index 669d18b34ac..8dc8f24b129 100644
--- a/arch/arm/src/kl/kl_lowputc.c
+++ b/arch/arm/src/kl/kl_lowputc.c
@@ -51,11 +51,11 @@
 #include "kl_lowputc.h"
 #include "kl_gpio.h"
 
-#include "chip/kl_uart.h"
-#include "chip/kl_sim.h"
-#include "chip/kl_port.h"
-#include "chip/kl_uart.h"
-#include "chip/kl_pinmux.h"
+#include "hardware/kl_uart.h"
+#include "hardware/kl_sim.h"
+#include "hardware/kl_port.h"
+#include "hardware/kl_uart.h"
+#include "hardware/kl_pinmux.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/kl/kl_pwm.c b/arch/arm/src/kl/kl_pwm.c
index cfa024b4779..c51f3185bf2 100644
--- a/arch/arm/src/kl/kl_pwm.c
+++ b/arch/arm/src/kl/kl_pwm.c
@@ -57,8 +57,8 @@
 #include "chip.h"
 #include "kl_pwm.h"
 #include "kl_gpio.h"
-#include "chip/kl_tpm.h"
-#include "chip/kl_sim.h"
+#include "hardware/kl_tpm.h"
+#include "hardware/kl_sim.h"
 
 /* This module then only compiles if there is at least one enabled timer
  * intended for use with the PWM upper half driver.
diff --git a/arch/arm/src/kl/kl_pwm.h b/arch/arm/src/kl/kl_pwm.h
index 5b64e40967b..3ac83144565 100644
--- a/arch/arm/src/kl/kl_pwm.h
+++ b/arch/arm/src/kl/kl_pwm.h
@@ -71,7 +71,7 @@
     defined(CONFIG_KL_TPM2_PWM)
 
 #include 
-#include "chip/kl_pinmux.h"
+#include "hardware/kl_pinmux.h"
 
 /* For each timer that is enabled for PWM usage, we need the following additional
  * configuration settings:
diff --git a/arch/arm/src/kl/kl_serial.c b/arch/arm/src/kl/kl_serial.c
index a35328345ee..0b7d67df0f2 100644
--- a/arch/arm/src/kl/kl_serial.c
+++ b/arch/arm/src/kl/kl_serial.c
@@ -61,7 +61,7 @@
 #include "kl_lowputc.h"
 #include "chip.h"
 #include "kl_gpio.h"
-#include "chip/kl_uart.h"
+#include "hardware/kl_uart.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/kl/kl_spi.c b/arch/arm/src/kl/kl_spi.c
index 187ae75e9e1..6cd41bf7175 100644
--- a/arch/arm/src/kl/kl_spi.c
+++ b/arch/arm/src/kl/kl_spi.c
@@ -54,10 +54,10 @@
 #include "up_arch.h"
 #include "kl_spi.h"
 #include "kl_gpio.h"
-#include "chip/kl_memorymap.h"
-#include "chip/kl_sim.h"
-#include "chip/kl_spi.h"
-#include "chip/kl_pinmux.h"
+#include "hardware/kl_memorymap.h"
+#include "hardware/kl_sim.h"
+#include "hardware/kl_spi.h"
+#include "hardware/kl_pinmux.h"
 
 #if defined(CONFIG_KL_SPI0) || defined(CONFIG_KL_SPI1)
 
diff --git a/arch/arm/src/kl/kl_start.c b/arch/arm/src/kl/kl_start.c
index 27c1a71b81f..cc98e4e09d4 100644
--- a/arch/arm/src/kl/kl_start.c
+++ b/arch/arm/src/kl/kl_start.c
@@ -48,7 +48,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/kl_sim.h"
+#include "hardware/kl_sim.h"
 
 #include "kl_config.h"
 #include "kl_gpio.h"
diff --git a/arch/arm/src/lc823450/Make.defs b/arch/arm/src/lc823450/Make.defs
index 1c1e578e6ac..f0861a815ac 100644
--- a/arch/arm/src/lc823450/Make.defs
+++ b/arch/arm/src/lc823450/Make.defs
@@ -64,11 +64,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_ARCH_MEMCPY),y)
 CMN_ASRCS += memcpy-armv7m.S
diff --git a/arch/arm/src/lpc11xx/Make.defs b/arch/arm/src/lpc11xx/Make.defs
index dbe34a8788f..180cdf4fca7 100644
--- a/arch/arm/src/lpc11xx/Make.defs
+++ b/arch/arm/src/lpc11xx/Make.defs
@@ -49,11 +49,9 @@ CMN_CSRCS += up_hardfault.c up_svcall.c up_vectors.c up_vfork.c
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
diff --git a/arch/arm/src/lpc11xx/chip.h b/arch/arm/src/lpc11xx/chip.h
index 5057045b71f..e9a8f52c747 100644
--- a/arch/arm/src/lpc11xx/chip.h
+++ b/arch/arm/src/lpc11xx/chip.h
@@ -53,7 +53,7 @@
  * this file for the proper setup.
  */
 
-#include "chip/lpc11_memorymap.h"
+#include "hardware/lpc11_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc11xx/chip/lpc111x_iocon.h b/arch/arm/src/lpc11xx/hardware/lpc111x_iocon.h
similarity index 98%
rename from arch/arm/src/lpc11xx/chip/lpc111x_iocon.h
rename to arch/arm/src/lpc11xx/hardware/lpc111x_iocon.h
index 61fc8877a12..1836d35dc1e 100644
--- a/arch/arm/src/lpc11xx/chip/lpc111x_iocon.h
+++ b/arch/arm/src/lpc11xx/hardware/lpc111x_iocon.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc11xx/chip/lpc111x_iocon.h
+ * arch/arm/src/lpc11xx/hardware/lpc111x_iocon.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Rommel Marcelo
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC111X_IOCON_H
-#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC111X_IOCON_H
+#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_IOCON_H
+#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_IOCON_H
 
 /************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc11_memorymap.h"
+#include "hardware/lpc11_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -266,4 +266,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC118X_IOCON_H */
+#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC118X_IOCON_H */
diff --git a/arch/arm/src/lpc11xx/chip/lpc111x_memorymap.h b/arch/arm/src/lpc11xx/hardware/lpc111x_memorymap.h
similarity index 95%
rename from arch/arm/src/lpc11xx/chip/lpc111x_memorymap.h
rename to arch/arm/src/lpc11xx/hardware/lpc111x_memorymap.h
index 21c12d01b03..948d9e89945 100644
--- a/arch/arm/src/lpc11xx/chip/lpc111x_memorymap.h
+++ b/arch/arm/src/lpc11xx/hardware/lpc111x_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc11xx/lpc111x_memorymap.h
+ * arch/arm/src/lpc11xx/hardware/lpc111x_memorymap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC11XX_LPC111X_MEMORYMAP_H
-#define __ARCH_ARM_SRC_LPC11XX_LPC111X_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -104,4 +104,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC11XX_LPC116X_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC116X_MEMORYMAP_H */
diff --git a/arch/arm/src/lpc11xx/chip/lpc111x_pinconfig.h b/arch/arm/src/lpc11xx/hardware/lpc111x_pinconfig.h
similarity index 96%
rename from arch/arm/src/lpc11xx/chip/lpc111x_pinconfig.h
rename to arch/arm/src/lpc11xx/hardware/lpc111x_pinconfig.h
index 0c40b08ac54..e160b554b67 100644
--- a/arch/arm/src/lpc11xx/chip/lpc111x_pinconfig.h
+++ b/arch/arm/src/lpc11xx/hardware/lpc111x_pinconfig.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc11xx/chip/lpc111x_pinconfig.h
+ * arch/arm/src/lpc11xx/hardware/lpc111x_pinconfig.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC111X_PINCONFIG_H
-#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC111X_PINCONFIG_H
+#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_PINCONFIG_H
+#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC111X_PINCONFIG_H
 
 /************************************************************************************
  * Included Files
@@ -119,4 +119,4 @@
  * Public Function Prototypes
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC116X_PINCONFIG_H */
+#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC116X_PINCONFIG_H */
diff --git a/arch/arm/src/lpc11xx/chip/lpc11_adc.h b/arch/arm/src/lpc11xx/hardware/lpc11_adc.h
similarity index 97%
rename from arch/arm/src/lpc11xx/chip/lpc11_adc.h
rename to arch/arm/src/lpc11xx/hardware/lpc11_adc.h
index 1324bff6c22..a1566b05140 100644
--- a/arch/arm/src/lpc11xx/chip/lpc11_adc.h
+++ b/arch/arm/src/lpc11xx/hardware/lpc11_adc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc11xx/chip/lpc11_adc.h
+ * arch/arm/src/lpc11xx/hardware/lpc11_adc.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_ADC_H
-#define __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_ADC_H
+#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_ADC_H
+#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_ADC_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc11_memorymap.h"
+#include "hardware/lpc11_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -168,4 +168,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_ADC_H */
+#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_ADC_H */
diff --git a/arch/arm/src/lpc11xx/chip/lpc11_gpio.h b/arch/arm/src/lpc11xx/hardware/lpc11_gpio.h
similarity index 97%
rename from arch/arm/src/lpc11xx/chip/lpc11_gpio.h
rename to arch/arm/src/lpc11xx/hardware/lpc11_gpio.h
index 99daa2445f7..93ae758a090 100644
--- a/arch/arm/src/lpc11xx/chip/lpc11_gpio.h
+++ b/arch/arm/src/lpc11xx/hardware/lpc11_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc11xx/chip/lpc11_gpio.h
+ * arch/arm/src/lpc11xx/hardware/lpc11_gpio.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_GPIO_H
-#define __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_GPIO_H
+#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_GPIO_H
+#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc11_memorymap.h"
+#include "hardware/lpc11_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -143,4 +143,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_GPIO_H */
+#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_CHIP_GPIO_H */
diff --git a/arch/arm/src/lpc11xx/chip/lpc11_i2c.h b/arch/arm/src/lpc11xx/hardware/lpc11_i2c.h
similarity index 97%
rename from arch/arm/src/lpc11xx/chip/lpc11_i2c.h
rename to arch/arm/src/lpc11xx/hardware/lpc11_i2c.h
index 53c7089c6ee..84384fca051 100644
--- a/arch/arm/src/lpc11xx/chip/lpc11_i2c.h
+++ b/arch/arm/src/lpc11xx/hardware/lpc11_i2c.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc11xx/chip/lpc11_i2c.h
+ * arch/arm/src/lpc11xx/hardware/lpc11_i2c.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_I2C_H
-#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_I2C_H
+#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_I2C_H
+#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_I2C_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc11_memorymap.h"
+#include "hardware/lpc11_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -205,4 +205,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_I2C_H */
+#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_I2C_H */
diff --git a/arch/arm/src/lpc11xx/chip/lpc11_memorymap.h b/arch/arm/src/lpc11xx/hardware/lpc11_memorymap.h
similarity index 91%
rename from arch/arm/src/lpc11xx/chip/lpc11_memorymap.h
rename to arch/arm/src/lpc11xx/hardware/lpc11_memorymap.h
index c01a346c269..24f6cdf1cce 100644
--- a/arch/arm/src/lpc11xx/chip/lpc11_memorymap.h
+++ b/arch/arm/src/lpc11xx/hardware/lpc11_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc11xx/chip/lpc11_memorymap.h
+ * arch/arm/src/lpc11xx/hardware/lpc11_memorymap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_MEMORYMAP_H
-#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_MEMORYMAP_H
+#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -49,7 +49,7 @@
 #include 
 
 #if defined(LPC111x)
-#  include "chip/lpc111x_memorymap.h"
+#  include "hardware/lpc111x_memorymap.h"
 #else
 #  error "Unrecognized LPC11xx family"
 #endif
@@ -70,4 +70,4 @@
  * Public Function Prototypes
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_MEMORYMAP_H */
diff --git a/arch/arm/src/lpc11xx/chip/lpc11_pinconfig.h b/arch/arm/src/lpc11xx/hardware/lpc11_pinconfig.h
similarity index 91%
rename from arch/arm/src/lpc11xx/chip/lpc11_pinconfig.h
rename to arch/arm/src/lpc11xx/hardware/lpc11_pinconfig.h
index c53b6b3d37e..08c6ab11d1e 100644
--- a/arch/arm/src/lpc11xx/chip/lpc11_pinconfig.h
+++ b/arch/arm/src/lpc11xx/hardware/lpc11_pinconfig.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc11xx/chip/lpc11_pinconfig.h
+ * arch/arm/src/lpc11xx/hardware/lpc11_pinconfig.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PINCONFIG_H
-#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PINCONFIG_H
+#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PINCONFIG_H
+#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PINCONFIG_H
 
 /************************************************************************************
  * Included Files
@@ -49,7 +49,7 @@
 #include 
 
 #if defined(LPC111x)
-#  include "chip/lpc111x_pinconfig.h"
+#  include "hardware/lpc111x_pinconfig.h"
 #else
 #  error "Unrecognized LPC11xx family"
 #endif
@@ -70,4 +70,4 @@
  * Public Function Prototypes
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PINCONFIG_H */
+#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PINCONFIG_H */
diff --git a/arch/arm/src/lpc11xx/chip/lpc11_pmu.h b/arch/arm/src/lpc11xx/hardware/lpc11_pmu.h
similarity index 95%
rename from arch/arm/src/lpc11xx/chip/lpc11_pmu.h
rename to arch/arm/src/lpc11xx/hardware/lpc11_pmu.h
index 6a8b5a6865e..226405bc038 100644
--- a/arch/arm/src/lpc11xx/chip/lpc11_pmu.h
+++ b/arch/arm/src/lpc11xx/hardware/lpc11_pmu.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc11xx/chip/lpc11_pmu.h
+ * arch/arm/src/lpc11xx/hardware/lpc11_pmu.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PMU_H
-#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PMU_H
+#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PMU_H
+#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PMU_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc11_memorymap.h"
+#include "hardware/lpc11_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -103,4 +103,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PMU_H */
+#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_PMU_H */
diff --git a/arch/arm/src/lpc11xx/chip/lpc11_ssp.h b/arch/arm/src/lpc11xx/hardware/lpc11_ssp.h
similarity index 97%
rename from arch/arm/src/lpc11xx/chip/lpc11_ssp.h
rename to arch/arm/src/lpc11xx/hardware/lpc11_ssp.h
index 1c67102c044..ad64d838408 100644
--- a/arch/arm/src/lpc11xx/chip/lpc11_ssp.h
+++ b/arch/arm/src/lpc11xx/hardware/lpc11_ssp.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc11xx/chip/lpc11_ssp.h
+ * arch/arm/src/lpc11xx/hardware/lpc11_ssp.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SSP_H
-#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SSP_H
+#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SSP_H
+#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SSP_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc11_memorymap.h"
+#include "hardware/lpc11_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -179,4 +179,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SPI_H */
+#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SPI_H */
diff --git a/arch/arm/src/lpc11xx/chip/lpc11_syscon.h b/arch/arm/src/lpc11xx/hardware/lpc11_syscon.h
similarity index 99%
rename from arch/arm/src/lpc11xx/chip/lpc11_syscon.h
rename to arch/arm/src/lpc11xx/hardware/lpc11_syscon.h
index 62f48680535..ac9a15477c1 100644
--- a/arch/arm/src/lpc11xx/chip/lpc11_syscon.h
+++ b/arch/arm/src/lpc11xx/hardware/lpc11_syscon.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/lpc11xx/chip/lpc11_syscon.h
+ * arch/arm/src/lpc11xx/hardware/lpc11_syscon.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SYSCON_H
-#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SYSCON_H
+#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SYSCON_H
+#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SYSCON_H
 
 /********************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc11_memorymap.h"
+#include "hardware/lpc11_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -446,4 +446,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SYSCON_H */
+#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_SYSCON_H */
diff --git a/arch/arm/src/lpc11xx/chip/lpc11_timer.h b/arch/arm/src/lpc11xx/hardware/lpc11_timer.h
similarity index 98%
rename from arch/arm/src/lpc11xx/chip/lpc11_timer.h
rename to arch/arm/src/lpc11xx/hardware/lpc11_timer.h
index 28e1122323b..cc343f28c0a 100644
--- a/arch/arm/src/lpc11xx/chip/lpc11_timer.h
+++ b/arch/arm/src/lpc11xx/hardware/lpc11_timer.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc11xx/chip/lpc11_timer.h
+ * arch/arm/src/lpc11xx/hardware/lpc11_timer.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_TIMER_H
-#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_TIMER_H
+#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_TIMER_H
+#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_TIMER_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc11_memorymap.h"
+#include "hardware/lpc11_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -268,4 +268,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_TIMER_H */
+#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_TIMER_H */
diff --git a/arch/arm/src/lpc11xx/chip/lpc11_uart.h b/arch/arm/src/lpc11xx/hardware/lpc11_uart.h
similarity index 98%
rename from arch/arm/src/lpc11xx/chip/lpc11_uart.h
rename to arch/arm/src/lpc11xx/hardware/lpc11_uart.h
index 7d3dffd3b24..a8be2e9bbe0 100644
--- a/arch/arm/src/lpc11xx/chip/lpc11_uart.h
+++ b/arch/arm/src/lpc11xx/hardware/lpc11_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc11xx/chip/lpc11_uart.h
+ * arch/arm/src/lpc11xx/hardware/lpc11_uart.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_UART_H
-#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_UART_H
+#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_UART_H
+#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_UART_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc11_memorymap.h"
+#include "hardware/lpc11_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -258,4 +258,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_UART_H */
+#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_UART_H */
diff --git a/arch/arm/src/lpc11xx/chip/lpc11_wdt.h b/arch/arm/src/lpc11xx/hardware/lpc11_wdt.h
similarity index 95%
rename from arch/arm/src/lpc11xx/chip/lpc11_wdt.h
rename to arch/arm/src/lpc11xx/hardware/lpc11_wdt.h
index e17eb48048d..9f3f5a99dc4 100644
--- a/arch/arm/src/lpc11xx/chip/lpc11_wdt.h
+++ b/arch/arm/src/lpc11xx/hardware/lpc11_wdt.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc11xx/chip/lpc11_wdt.h
+ * arch/arm/src/lpc11xx/hardware/lpc11_wdt.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H
-#define __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H
+#ifndef __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_WDT_H
+#define __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_WDT_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc11_memorymap.h"
+#include "hardware/lpc11_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -99,4 +99,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H */
+#endif /* __ARCH_ARM_SRC_LPC11XX_HARDWARE_LPC11_WDT_H */
diff --git a/arch/arm/src/lpc11xx/lpc111x_gpio.c b/arch/arm/src/lpc11xx/lpc111x_gpio.c
index cba1ee71734..630d68f9b16 100644
--- a/arch/arm/src/lpc11xx/lpc111x_gpio.c
+++ b/arch/arm/src/lpc11xx/lpc111x_gpio.c
@@ -49,7 +49,7 @@
 
 #include "up_arch.h"
 #include "chip.h"
-#include "chip/lpc111x_iocon.h"
+#include "hardware/lpc111x_iocon.h"
 #include "lpc11_gpio.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/lpc11xx/lpc11_clockconfig.c b/arch/arm/src/lpc11xx/lpc11_clockconfig.c
index 804b6d29610..f906de18dd8 100644
--- a/arch/arm/src/lpc11xx/lpc11_clockconfig.c
+++ b/arch/arm/src/lpc11xx/lpc11_clockconfig.c
@@ -48,9 +48,9 @@
 #include "up_arch.h"
 #include "up_internal.h"
 #include "lpc11_clockconfig.h"
-#include "chip/lpc11_syscon.h"
-#include "chip/lpc111x_iocon.h"
-#include "chip/lpc11_gpio.h"
+#include "hardware/lpc11_syscon.h"
+#include "hardware/lpc111x_iocon.h"
+#include "hardware/lpc11_gpio.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc11xx/lpc11_gpio.h b/arch/arm/src/lpc11xx/lpc11_gpio.h
index f77b748613e..dea2a0cef8f 100644
--- a/arch/arm/src/lpc11xx/lpc11_gpio.h
+++ b/arch/arm/src/lpc11xx/lpc11_gpio.h
@@ -49,8 +49,8 @@
 
 #include 
 
-#include "chip/lpc11_gpio.h"
-#include "chip/lpc11_pinconfig.h"
+#include "hardware/lpc11_gpio.h"
+#include "hardware/lpc11_pinconfig.h"
 
 /* Include the GPIO definitions for the selected LPC17xx family. */
 
diff --git a/arch/arm/src/lpc11xx/lpc11_i2c.c b/arch/arm/src/lpc11xx/lpc11_i2c.c
index 5873a18ff3a..0fee3d96025 100644
--- a/arch/arm/src/lpc11xx/lpc11_i2c.c
+++ b/arch/arm/src/lpc11xx/lpc11_i2c.c
@@ -70,7 +70,7 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/lpc11_syscon.h"
+#include "hardware/lpc11_syscon.h"
 #include "lpc11_gpio.h"
 #include "lpc11_i2c.h"
 
diff --git a/arch/arm/src/lpc11xx/lpc11_i2c.h b/arch/arm/src/lpc11xx/lpc11_i2c.h
index cd739be1a3a..27a490b20ef 100644
--- a/arch/arm/src/lpc11xx/lpc11_i2c.h
+++ b/arch/arm/src/lpc11xx/lpc11_i2c.h
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/lpc11_i2c.h"
+#include "hardware/lpc11_i2c.h"
 
 /****************************************************************************
  * Public Functions
diff --git a/arch/arm/src/lpc11xx/lpc11_lowputc.c b/arch/arm/src/lpc11xx/lpc11_lowputc.c
index dcba013127f..8bf3759f488 100644
--- a/arch/arm/src/lpc11xx/lpc11_lowputc.c
+++ b/arch/arm/src/lpc11xx/lpc11_lowputc.c
@@ -47,8 +47,8 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/lpc11_syscon.h"
-#include "chip/lpc11_uart.h"
+#include "hardware/lpc11_syscon.h"
+#include "hardware/lpc11_uart.h"
 
 #include "lpc11_gpio.h"
 #include "lpc11_lowputc.h"
diff --git a/arch/arm/src/lpc11xx/lpc11_serial.c b/arch/arm/src/lpc11xx/lpc11_serial.c
index 95f3f17bc61..00ec359fb2f 100644
--- a/arch/arm/src/lpc11xx/lpc11_serial.c
+++ b/arch/arm/src/lpc11xx/lpc11_serial.c
@@ -62,7 +62,7 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/lpc11_uart.h"
+#include "hardware/lpc11_uart.h"
 #include "lpc11_gpio.h"
 #include "lpc11_serial.h"
 
diff --git a/arch/arm/src/lpc11xx/lpc11_serial.h b/arch/arm/src/lpc11xx/lpc11_serial.h
index 59e6cc36f08..82d4e59051a 100644
--- a/arch/arm/src/lpc11xx/lpc11_serial.h
+++ b/arch/arm/src/lpc11xx/lpc11_serial.h
@@ -43,8 +43,8 @@
 #include 
 #include 
 
-#include "chip/lpc11_uart.h"
-#include "chip/lpc11_syscon.h"
+#include "hardware/lpc11_uart.h"
+#include "hardware/lpc11_syscon.h"
 
 #include "lpc11_gpio.h"
 
diff --git a/arch/arm/src/lpc11xx/lpc11_spi.c b/arch/arm/src/lpc11xx/lpc11_spi.c
index e1bb8e0d6ca..78b306549ba 100644
--- a/arch/arm/src/lpc11xx/lpc11_spi.c
+++ b/arch/arm/src/lpc11xx/lpc11_spi.c
@@ -55,7 +55,7 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/lpc11_syscon.h"
+#include "hardware/lpc11_syscon.h"
 #include "lpc11_gpio.h"
 #include "lpc11_spi.h"
 
diff --git a/arch/arm/src/lpc11xx/lpc11_spi.h b/arch/arm/src/lpc11xx/lpc11_spi.h
index 30ee2bbecff..b17f5215080 100644
--- a/arch/arm/src/lpc11xx/lpc11_spi.h
+++ b/arch/arm/src/lpc11xx/lpc11_spi.h
@@ -44,16 +44,6 @@
 
 #include 
 
-#include "chip/lpc11_spi.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
 /************************************************************************************
  * Public Data
  ************************************************************************************/
diff --git a/arch/arm/src/lpc11xx/lpc11_ssp.c b/arch/arm/src/lpc11xx/lpc11_ssp.c
index c0c1498f7e6..780a8945626 100644
--- a/arch/arm/src/lpc11xx/lpc11_ssp.c
+++ b/arch/arm/src/lpc11xx/lpc11_ssp.c
@@ -55,7 +55,7 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/lpc11_syscon.h"
+#include "hardware/lpc11_syscon.h"
 #include "lpc11_gpio.h"
 #include "lpc11_ssp.h"
 
diff --git a/arch/arm/src/lpc11xx/lpc11_ssp.h b/arch/arm/src/lpc11xx/lpc11_ssp.h
index 825c67faa3a..c38b4dbdf2f 100644
--- a/arch/arm/src/lpc11xx/lpc11_ssp.h
+++ b/arch/arm/src/lpc11xx/lpc11_ssp.h
@@ -44,7 +44,7 @@
 
 #include 
 
-#include "chip/lpc11_ssp.h"
+#include "hardware/lpc11_ssp.h"
 
 #if defined(CONFIG_LPC11_SSP0) || defined(CONFIG_LPC11_SSP1)
 
diff --git a/arch/arm/src/lpc11xx/lpc11_start.c b/arch/arm/src/lpc11xx/lpc11_start.c
index 03199227e9f..a54dfee8e26 100644
--- a/arch/arm/src/lpc11xx/lpc11_start.c
+++ b/arch/arm/src/lpc11xx/lpc11_start.c
@@ -47,15 +47,12 @@
 
 #include "up_arch.h"
 #include "up_internal.h"
+#include "nvic.h"
 
 #include "lpc11_clockconfig.h"
 #include "lpc11_lowputc.h"
 #include "lpc11_userspace.h"
 
-#ifdef CONFIG_ARCH_FPU
-#  include "nvic.h"
-#endif
-
 #include "lpc11_start.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/lpc11xx/lpc11_timer.c b/arch/arm/src/lpc11xx/lpc11_timer.c
index 75d3d334a43..3af6342cd58 100644
--- a/arch/arm/src/lpc11xx/lpc11_timer.c
+++ b/arch/arm/src/lpc11xx/lpc11_timer.c
@@ -54,9 +54,9 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/lpc11_syscon.h"
+#include "hardware/lpc11_syscon.h"
 #include "lpc11_timer.h"
-#include "chip/lpc116x_pinconfig.h"
+#include "hardware/lpc116x_pinconfig.h"
 #include "lpc11_gpio.h"
 #include "lpc116x_gpio.h"
 
diff --git a/arch/arm/src/lpc11xx/lpc11_timer.h b/arch/arm/src/lpc11xx/lpc11_timer.h
index edfb621c169..02f58a50ca7 100644
--- a/arch/arm/src/lpc11xx/lpc11_timer.h
+++ b/arch/arm/src/lpc11xx/lpc11_timer.h
@@ -41,7 +41,7 @@
  ************************************************************************************/
 
 #include 
-#include "chip/lpc11_timer.h"
+#include "hardware/lpc11_timer.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc11xx/lpc11_wdt.h b/arch/arm/src/lpc11xx/lpc11_wdt.h
index d963b4b064e..f2b073b5833 100644
--- a/arch/arm/src/lpc11xx/lpc11_wdt.h
+++ b/arch/arm/src/lpc11xx/lpc11_wdt.h
@@ -41,7 +41,7 @@
  ************************************************************************************/
 
 #include 
-#include "chip/lpc11_wdt.h"
+#include "hardware/lpc11_wdt.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/Make.defs b/arch/arm/src/lpc17xx/Make.defs
index 7d76818df89..446330c022a 100644
--- a/arch/arm/src/lpc17xx/Make.defs
+++ b/arch/arm/src/lpc17xx/Make.defs
@@ -71,11 +71,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 # Use of common/up_etherstub.c is deprecated.  The preferred mechanism is to
 # use CONFIG_NETDEV_LATEINIT=y to suppress the call to up_netinitialize() in
diff --git a/arch/arm/src/lpc17xx/chip.h b/arch/arm/src/lpc17xx/chip.h
index 2f04b031d88..391901a2717 100644
--- a/arch/arm/src/lpc17xx/chip.h
+++ b/arch/arm/src/lpc17xx/chip.h
@@ -55,7 +55,7 @@
  * this file for the proper setup.
  */
 
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/chip/lpc176x_memorymap.h b/arch/arm/src/lpc17xx/hardware/lpc176x_memorymap.h
similarity index 96%
rename from arch/arm/src/lpc17xx/chip/lpc176x_memorymap.h
rename to arch/arm/src/lpc17xx/hardware/lpc176x_memorymap.h
index 094a47788fe..a99f93d754d 100644
--- a/arch/arm/src/lpc17xx/chip/lpc176x_memorymap.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc176x_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/lpc176x_memorymap.h
+ * arch/arm/src/lpc17xx/hardware/lpc176x_memorymap.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC176X_MEMORYMAP_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC176X_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -133,4 +133,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC176X_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_MEMORYMAP_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc176x_pinconfig.h b/arch/arm/src/lpc17xx/hardware/lpc176x_pinconfig.h
similarity index 98%
rename from arch/arm/src/lpc17xx/chip/lpc176x_pinconfig.h
rename to arch/arm/src/lpc17xx/hardware/lpc176x_pinconfig.h
index cd80c602a22..3adb293adc9 100644
--- a/arch/arm/src/lpc17xx/chip/lpc176x_pinconfig.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc176x_pinconfig.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc176x_pinconfig.h
+ * arch/arm/src/lpc17xx/hardware/lpc176x_pinconfig.h
  *
  *   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_PINCONFIG_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_PINCONFIG_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_PINCONFIG_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_PINCONFIG_H
 
 /************************************************************************************
  * Included Files
@@ -231,4 +231,4 @@
  * Public Function Prototypes
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_PINCONFIG_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_PINCONFIG_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc176x_pinconn.h b/arch/arm/src/lpc17xx/hardware/lpc176x_pinconn.h
similarity index 99%
rename from arch/arm/src/lpc17xx/chip/lpc176x_pinconn.h
rename to arch/arm/src/lpc17xx/hardware/lpc176x_pinconn.h
index 6d5b05ba9e3..fccf9e8854d 100644
--- a/arch/arm/src/lpc17xx/chip/lpc176x_pinconn.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc176x_pinconn.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc176x_pinconn.h
+ * arch/arm/src/lpc17xx/hardware/lpc176x_pinconn.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_PINCONN_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_PINCONN_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_PINCONN_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_PINCONN_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -632,4 +632,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_PINCONN_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_PINCONN_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc176x_syscon.h b/arch/arm/src/lpc17xx/hardware/lpc176x_syscon.h
similarity index 99%
rename from arch/arm/src/lpc17xx/chip/lpc176x_syscon.h
rename to arch/arm/src/lpc17xx/hardware/lpc176x_syscon.h
index bc3ae3c92eb..96b75be806b 100644
--- a/arch/arm/src/lpc17xx/chip/lpc176x_syscon.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc176x_syscon.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc176x_syscon.h
+ * arch/arm/src/lpc17xx/hardware/lpc176x_syscon.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_SYSCON_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_SYSCON_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_SYSCON_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_SYSCON_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -491,4 +491,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC176X_SYSCON_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC176X_SYSCON_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h b/arch/arm/src/lpc17xx/hardware/lpc178x_iocon.h
similarity index 98%
rename from arch/arm/src/lpc17xx/chip/lpc178x_iocon.h
rename to arch/arm/src/lpc17xx/hardware/lpc178x_iocon.h
index 690313f4db0..bb49cd13a87 100644
--- a/arch/arm/src/lpc17xx/chip/lpc178x_iocon.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc178x_iocon.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc178x_iocon.h
+ * arch/arm/src/lpc17xx/hardware/lpc178x_iocon.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Rommel Marcelo
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_IOCON_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_IOCON_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_IOCON_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_IOCON_H
 
 /************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -372,4 +372,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_IOCON_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_IOCON_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h b/arch/arm/src/lpc17xx/hardware/lpc178x_memorymap.h
similarity index 97%
rename from arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h
rename to arch/arm/src/lpc17xx/hardware/lpc178x_memorymap.h
index 35c51866562..76a87f182ca 100644
--- a/arch/arm/src/lpc17xx/chip/lpc178x_memorymap.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc178x_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/lpc178x_memorymap.h
+ * arch/arm/src/lpc17xx/hardware/lpc178x_memorymap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Authors: Rommel Marcelo
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC178X_MEMORYMAP_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC178X_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -155,4 +155,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC178X_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_MEMORYMAP_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h b/arch/arm/src/lpc17xx/hardware/lpc178x_pinconfig.h
similarity index 99%
rename from arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h
rename to arch/arm/src/lpc17xx/hardware/lpc178x_pinconfig.h
index f4007a89c98..acafae871ad 100644
--- a/arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc178x_pinconfig.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc178x_pinconfig.h
+ * arch/arm/src/lpc17xx/hardware/lpc178x_pinconfig.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Authors: Rommel Marcelo
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_PINCONFIG_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_PINCONFIG_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_PINCONFIG_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_PINCONFIG_H
 
 /************************************************************************************
  * Included Files
@@ -656,4 +656,4 @@
  * Public Function Prototypes
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_PINCONFIG_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_PINCONFIG_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h b/arch/arm/src/lpc17xx/hardware/lpc178x_syscon.h
similarity index 99%
rename from arch/arm/src/lpc17xx/chip/lpc178x_syscon.h
rename to arch/arm/src/lpc17xx/hardware/lpc178x_syscon.h
index bf5186abcb7..b6701ce6c2c 100644
--- a/arch/arm/src/lpc17xx/chip/lpc178x_syscon.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc178x_syscon.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc178x_syscon.h
+ * arch/arm/src/lpc17xx/hardware/lpc178x_syscon.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Authors: Rommel Marcelo
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_SYSCON_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_SYSCON_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_SYSCON_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_SYSCON_H
 
 /****************************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -633,4 +633,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC178X_SYSCON_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC178X_SYSCON_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_adc.h b/arch/arm/src/lpc17xx/hardware/lpc17_adc.h
similarity index 97%
rename from arch/arm/src/lpc17xx/chip/lpc17_adc.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_adc.h
index 8cec0d3250f..fc6fb80b000 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_adc.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_adc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_adc.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_adc.h
  *
  *   Copyright (C) 2010, 2012, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_ADC_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_ADC_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_ADC_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_ADC_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -177,4 +177,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_ADC_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_ADC_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_can.h b/arch/arm/src/lpc17xx/hardware/lpc17_can.h
similarity index 99%
rename from arch/arm/src/lpc17xx/chip/lpc17_can.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_can.h
index 74a21094421..2a9172ada94 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_can.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_can.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_can.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_can.h
  *
  *   Copyright (C) 2010-2012, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_CAN_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_CAN_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_CAN_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_CAN_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -507,4 +507,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_CAN_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_CAN_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_dac.h b/arch/arm/src/lpc17xx/hardware/lpc17_dac.h
similarity index 94%
rename from arch/arm/src/lpc17xx/chip/lpc17_dac.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_dac.h
index be78bef059b..9e39c1e9825 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_dac.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_dac.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_dac.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_dac.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_DAC_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_DAC_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_DAC_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_DAC_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -94,4 +94,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_DAC_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_DAC_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_eeprom.h b/arch/arm/src/lpc17xx/hardware/lpc17_eeprom.h
similarity index 97%
rename from arch/arm/src/lpc17xx/chip/lpc17_eeprom.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_eeprom.h
index 7f147704314..d202cb73175 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_eeprom.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_eeprom.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_eeprom.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_eeprom.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_EEPROM_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_EEPROM_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EEPROM_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EEPROM_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -183,4 +183,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_EEPROM_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EEPROM_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_emc.h b/arch/arm/src/lpc17xx/hardware/lpc17_emc.h
similarity index 98%
rename from arch/arm/src/lpc17xx/chip/lpc17_emc.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_emc.h
index 2454003a4e0..11e30a0cf4b 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_emc.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_emc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_emc
+ * arch/arm/src/lpc17xx/hardware/lpc17_emc
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_EMC_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_EMC_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EMC_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EMC_H
 
 /****************************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -347,4 +347,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_EMC_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_EMC_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_ethernet.h b/arch/arm/src/lpc17xx/hardware/lpc17_ethernet.h
similarity index 99%
rename from arch/arm/src/lpc17xx/chip/lpc17_ethernet.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_ethernet.h
index b0791ced96e..f60e5530f8b 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_ethernet.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_ethernet.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_ethernet.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_ethernet.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_ETHERNET_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_ETHERNET_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_ETHERNET_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_ETHERNET_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -594,4 +594,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_ETHERNET_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_ETHERNET_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_gpdma.h b/arch/arm/src/lpc17xx/hardware/lpc17_gpdma.h
similarity index 99%
rename from arch/arm/src/lpc17xx/chip/lpc17_gpdma.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_gpdma.h
index a915559b968..4a1f25bf91c 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_gpdma.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_gpdma.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_gpdma.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_gpdma.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_GPDMA_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_GPDMA_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_GPDMA_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_GPDMA_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -594,4 +594,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_GPDMA_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_GPDMA_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_gpio.h b/arch/arm/src/lpc17xx/hardware/lpc17_gpio.h
similarity index 97%
rename from arch/arm/src/lpc17xx/chip/lpc17_gpio.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_gpio.h
index aa5c0f57b00..2e9891058b1 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_gpio.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_gpio.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_gpio.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_GPIO_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_GPIO_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_GPIO_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -207,4 +207,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_CHIP_GPIO_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_CHIP_GPIO_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_i2c.h b/arch/arm/src/lpc17xx/hardware/lpc17_i2c.h
similarity index 97%
rename from arch/arm/src/lpc17xx/chip/lpc17_i2c.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_i2c.h
index 96b6f19b1ab..eb370fdd5dc 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_i2c.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_i2c.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_i2c.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_i2c.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_I2C_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_I2C_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2C_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2C_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -205,4 +205,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_I2C_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2C_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_i2s.h b/arch/arm/src/lpc17xx/hardware/lpc17_i2s.h
similarity index 97%
rename from arch/arm/src/lpc17xx/chip/lpc17_i2s.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_i2s.h
index 100d2f39f13..bb0f9ca4427 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_i2s.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_i2s.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_i2s
+ * arch/arm/src/lpc17xx/hardware/lpc17_i2s
  *
  *   Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_I2S_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_I2S_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2S_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2S_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -187,4 +187,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_I2S_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_I2S_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_lcd.h b/arch/arm/src/lpc17xx/hardware/lpc17_lcd.h
similarity index 98%
rename from arch/arm/src/lpc17xx/chip/lpc17_lcd.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_lcd.h
index ef334a1a672..af47bbd8a7e 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_lcd.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_lcd.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_lcd.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_lcd.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_LCD_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_LCD_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_LCD_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_LCD_H
 
 /************************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************************
  * Pre-processor Definitions
@@ -343,4 +343,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_LCD_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_LCD_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_mcpwm.h b/arch/arm/src/lpc17xx/hardware/lpc17_mcpwm.h
similarity index 98%
rename from arch/arm/src/lpc17xx/chip/lpc17_mcpwm.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_mcpwm.h
index 16a21a162c0..fc04e68ab9a 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_mcpwm.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_mcpwm.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_mcpwm.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_mcpwm.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_MCPWM_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_MCPWM_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_MCPWM_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_MCPWM_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -277,4 +277,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_MCPWM_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_MCPWM_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_memorymap.h b/arch/arm/src/lpc17xx/hardware/lpc17_memorymap.h
similarity index 90%
rename from arch/arm/src/lpc17xx/chip/lpc17_memorymap.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_memorymap.h
index 53214c8a5d9..54dcc06b75e 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_memorymap.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_memorymap.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_memorymap.h
  *
  *   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_MEMORYMAP_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_MEMORYMAP_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -49,9 +49,9 @@
 #include 
 
 #if defined(LPC176x)
-#  include "chip/lpc176x_memorymap.h"
+#  include "hardware/lpc176x_memorymap.h"
 #elif defined(LPC178x)
-#  include "chip/lpc178x_memorymap.h"
+#  include "hardware/lpc178x_memorymap.h"
 #else
 #  error "Unrecognized LPC17xx family"
 #endif
@@ -72,4 +72,4 @@
  * Public Function Prototypes
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_MEMORYMAP_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_pinconfig.h b/arch/arm/src/lpc17xx/hardware/lpc17_pinconfig.h
similarity index 90%
rename from arch/arm/src/lpc17xx/chip/lpc17_pinconfig.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_pinconfig.h
index c0090dbc1a4..39a9fe09082 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_pinconfig.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_pinconfig.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_pinconfig.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_pinconfig.h
  *
  *   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PINCONFIG_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PINCONFIG_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PINCONFIG_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PINCONFIG_H
 
 /************************************************************************************
  * Included Files
@@ -49,9 +49,9 @@
 #include 
 
 #if defined(LPC176x)
-#  include "chip/lpc176x_pinconfig.h"
+#  include "hardware/lpc176x_pinconfig.h"
 #elif defined(LPC178x)
-#  include "chip/lpc178x_pinconfig.h"
+#  include "hardware/lpc178x_pinconfig.h"
 #else
 #  error "Unrecognized LPC17xx family"
 #endif
@@ -72,4 +72,4 @@
  * Public Function Prototypes
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PINCONFIG_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PINCONFIG_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h b/arch/arm/src/lpc17xx/hardware/lpc17_pinconn.h
similarity index 91%
rename from arch/arm/src/lpc17xx/chip/lpc17_pinconn.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_pinconn.h
index 8b6829f9ba6..f9f46dfb5f4 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_pinconn.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_pinconn.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_pinconn.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_pinconn.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PINCONN_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PINCONN_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PINCONN_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PINCONN_H
 
 /************************************************************************************
  * Included Files
@@ -49,9 +49,9 @@
 #include 
 
 #if defined(LPC176x)
-#  include "chip/lpc176x_pinconn.h"
+#  include "hardware/lpc176x_pinconn.h"
 #elif defined(LPC178x)
-#  include "chip/lpc178x_iocon.h"
+#  include "hardware/lpc178x_iocon.h"
 #else
 #  error "Unrecognized LPC17xx family"
 #endif
@@ -72,4 +72,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PINCONN_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PINCONN_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_pwm.h b/arch/arm/src/lpc17xx/hardware/lpc17_pwm.h
similarity index 98%
rename from arch/arm/src/lpc17xx/chip/lpc17_pwm.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_pwm.h
index 610215bc026..4c158c9d0cf 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_pwm.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_pwm.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_pwm.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_pwm.h
  *
  *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PWM_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PWM_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PWM_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PWM_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -220,4 +220,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_PWM_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_PWM_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_qei.h b/arch/arm/src/lpc17xx/hardware/lpc17_qei.h
similarity index 97%
rename from arch/arm/src/lpc17xx/chip/lpc17_qei.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_qei.h
index af0d6924391..ab3e3fb98ac 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_qei.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_qei.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_qei.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_qei.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_QEI_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_QEI_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_QEI_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_QEI_H
 
 /********************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -211,4 +211,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_QEI_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_QEI_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_rit.h b/arch/arm/src/lpc17xx/hardware/lpc17_rit.h
similarity index 94%
rename from arch/arm/src/lpc17xx/chip/lpc17_rit.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_rit.h
index 00029f8fe7f..7ddf129e922 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_rit.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_rit.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_rit.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_rit.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_RIT_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_RIT_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RIT_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RIT_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -89,4 +89,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_RIT_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RIT_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_rtc.h b/arch/arm/src/lpc17xx/hardware/lpc17_rtc.h
similarity index 98%
rename from arch/arm/src/lpc17xx/chip/lpc17_rtc.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_rtc.h
index 56144c6cf26..08975f2e99c 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_rtc.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_rtc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_rtc.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_rtc.h
  *
  *   Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_RTC_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_RTC_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTC_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTC_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -274,4 +274,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_RTC_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTC_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_rtcevmr.h b/arch/arm/src/lpc17xx/hardware/lpc17_rtcevmr.h
similarity index 97%
rename from arch/arm/src/lpc17xx/chip/lpc17_rtcevmr.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_rtcevmr.h
index a16decd471c..5448a3b7cf5 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_rtcevmr.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_rtcevmr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_rtcevmr.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_rtcevmr.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_RTCEVMR_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_RTCEVMR_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTCEVMR_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTCEVMR_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -140,4 +140,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_RTCEVMR_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_RTCEVMR_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_sdcard.h b/arch/arm/src/lpc17xx/hardware/lpc17_sdcard.h
similarity index 98%
rename from arch/arm/src/lpc17xx/chip/lpc17_sdcard.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_sdcard.h
index 5e91435ef90..7140d186cf3 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_sdcard.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_sdcard.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_sdcard.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_sdcard.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SDCARD_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SDCARD_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SDCARD_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SDCARD_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -268,5 +268,5 @@
  * The FIFOs contain 16 entries on 16 sequential addresses.
  */
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SDCARD_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SDCARD_H */
 
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_spi.h b/arch/arm/src/lpc17xx/hardware/lpc17_spi.h
similarity index 96%
rename from arch/arm/src/lpc17xx/chip/lpc17_spi.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_spi.h
index 716e70cb541..dc9dce94385 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_spi.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_spi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_spi.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_spi.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SPI_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SPI_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SPI_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SPI_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -138,4 +138,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SPI_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SPI_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_ssp.h b/arch/arm/src/lpc17xx/hardware/lpc17_ssp.h
similarity index 97%
rename from arch/arm/src/lpc17xx/chip/lpc17_ssp.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_ssp.h
index dd791327fb1..c1d40a211f5 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_ssp.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_ssp.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_ssp.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_ssp.h
  *
  *   Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SSP_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SSP_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SSP_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SSP_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -182,4 +182,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SSP_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SSP_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_syscon.h b/arch/arm/src/lpc17xx/hardware/lpc17_syscon.h
similarity index 91%
rename from arch/arm/src/lpc17xx/chip/lpc17_syscon.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_syscon.h
index ebab3a1be5c..29d4380f29f 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_syscon.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_syscon.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_syscon.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_syscon.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SYSCON_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SYSCON_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SYSCON_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SYSCON_H
 
 /************************************************************************************
  * Included Files
@@ -49,9 +49,9 @@
 #include 
 
 #if defined(LPC176x)
-#  include "chip/lpc176x_syscon.h"
+#  include "hardware/lpc176x_syscon.h"
 #elif defined(LPC178x)
-#  include "chip/lpc178x_syscon.h"
+#  include "hardware/lpc178x_syscon.h"
 #else
 #  error "Unrecognized LPC17xx family"
 #endif
@@ -72,4 +72,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_SYSCON_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_SYSCON_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_timer.h b/arch/arm/src/lpc17xx/hardware/lpc17_timer.h
similarity index 98%
rename from arch/arm/src/lpc17xx/chip/lpc17_timer.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_timer.h
index 455133ee7e8..b66b3921ada 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_timer.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_timer.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_timer.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_timer.h
  *
  *   Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_TIMER_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_TIMER_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_TIMER_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_TIMER_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -247,4 +247,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_TIMER_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_TIMER_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_uart.h b/arch/arm/src/lpc17xx/hardware/lpc17_uart.h
similarity index 99%
rename from arch/arm/src/lpc17xx/chip/lpc17_uart.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_uart.h
index 478c18b70a2..175fedacfa6 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_uart.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_uart.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_uart.h
  *
  *   Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_UART_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_UART_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_UART_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_UART_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -411,4 +411,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_UART_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_UART_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_usb.h b/arch/arm/src/lpc17xx/hardware/lpc17_usb.h
similarity index 99%
rename from arch/arm/src/lpc17xx/chip/lpc17_usb.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_usb.h
index 32b02455c58..56b38e55a09 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_usb.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_usb.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_usb.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_usb.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_USB_H
-#define __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_USB_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_USB_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_USB_H
 
 /************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -775,4 +775,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_CHIP_LPC17_USB_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_USB_H */
diff --git a/arch/arm/src/lpc17xx/chip/lpc17_wdt.h b/arch/arm/src/lpc17xx/hardware/lpc17_wdt.h
similarity index 96%
rename from arch/arm/src/lpc17xx/chip/lpc17_wdt.h
rename to arch/arm/src/lpc17xx/hardware/lpc17_wdt.h
index d76ff176226..f740fe167c9 100644
--- a/arch/arm/src/lpc17xx/chip/lpc17_wdt.h
+++ b/arch/arm/src/lpc17xx/hardware/lpc17_wdt.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc17xx/chip/lpc17_wdt.h
+ * arch/arm/src/lpc17xx/hardware/lpc17_wdt.h
  *
  *   Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H
-#define __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H
+#ifndef __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_WDT_H
+#define __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_WDT_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -153,4 +153,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H */
+#endif /* __ARCH_ARM_SRC_LPC17XX_HARDWARE_LPC17_WDT_H */
diff --git a/arch/arm/src/lpc17xx/lpc176x_clockconfig.c b/arch/arm/src/lpc17xx/lpc176x_clockconfig.c
index a6f57b3a525..cc9cc89b8b3 100644
--- a/arch/arm/src/lpc17xx/lpc176x_clockconfig.c
+++ b/arch/arm/src/lpc17xx/lpc176x_clockconfig.c
@@ -49,7 +49,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 #include "lpc17_clockconfig.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc176x_rtc.c b/arch/arm/src/lpc17xx/lpc176x_rtc.c
index 82549159685..ae5a18949d7 100644
--- a/arch/arm/src/lpc17xx/lpc176x_rtc.c
+++ b/arch/arm/src/lpc17xx/lpc176x_rtc.c
@@ -52,7 +52,7 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 
 #include "lpc17_rtc.h"
 
diff --git a/arch/arm/src/lpc17xx/lpc178x_clockconfig.c b/arch/arm/src/lpc17xx/lpc178x_clockconfig.c
index efdca053d26..216d27012ff 100644
--- a/arch/arm/src/lpc17xx/lpc178x_clockconfig.c
+++ b/arch/arm/src/lpc17xx/lpc178x_clockconfig.c
@@ -49,7 +49,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 #include "lpc17_clockconfig.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_adc.c b/arch/arm/src/lpc17xx/lpc17_adc.c
index 9d476e48d30..b7d22b393b1 100644
--- a/arch/arm/src/lpc17xx/lpc17_adc.c
+++ b/arch/arm/src/lpc17xx/lpc17_adc.c
@@ -63,7 +63,7 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 #include "lpc17_gpio.h"
 #include "lpc17_adc.h"
 
diff --git a/arch/arm/src/lpc17xx/lpc17_adc.h b/arch/arm/src/lpc17xx/lpc17_adc.h
index 95d8a13d4b0..09f1b669840 100644
--- a/arch/arm/src/lpc17xx/lpc17_adc.h
+++ b/arch/arm/src/lpc17xx/lpc17_adc.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/lpc17_adc.h"
+#include "hardware/lpc17_adc.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_allocateheap.c b/arch/arm/src/lpc17xx/lpc17_allocateheap.c
index 39038742d7e..839c5a3987e 100644
--- a/arch/arm/src/lpc17xx/lpc17_allocateheap.c
+++ b/arch/arm/src/lpc17xx/lpc17_allocateheap.c
@@ -52,7 +52,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 #include "lpc17_emacram.h"
 #include "lpc17_ohciram.h"
 #include "lpc17_mpuinit.h"
diff --git a/arch/arm/src/lpc17xx/lpc17_can.c b/arch/arm/src/lpc17xx/lpc17_can.c
index 52be6268e5a..3d3069b0b55 100644
--- a/arch/arm/src/lpc17xx/lpc17_can.c
+++ b/arch/arm/src/lpc17xx/lpc17_can.c
@@ -63,7 +63,7 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 #include "lpc17_gpio.h"
 #include "lpc17_can.h"
 
diff --git a/arch/arm/src/lpc17xx/lpc17_can.h b/arch/arm/src/lpc17xx/lpc17_can.h
index 2cbb8014a9f..271339ff054 100644
--- a/arch/arm/src/lpc17xx/lpc17_can.h
+++ b/arch/arm/src/lpc17xx/lpc17_can.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/lpc17_can.h"
+#include "hardware/lpc17_can.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_dac.c b/arch/arm/src/lpc17xx/lpc17_dac.c
index 003d6092664..301dc4133f1 100644
--- a/arch/arm/src/lpc17xx/lpc17_dac.c
+++ b/arch/arm/src/lpc17xx/lpc17_dac.c
@@ -62,8 +62,8 @@
 
 #include "chip.h"
 
-#include "chip/lpc17_syscon.h"
-#include "chip/lpc17_pinconfig.h"
+#include "hardware/lpc17_syscon.h"
+#include "hardware/lpc17_pinconfig.h"
 #include "lpc17_gpio.h"
 #include "lpc17_dac.h"
 
diff --git a/arch/arm/src/lpc17xx/lpc17_dac.h b/arch/arm/src/lpc17xx/lpc17_dac.h
index ac8477507ce..a27b6a66d17 100644
--- a/arch/arm/src/lpc17xx/lpc17_dac.h
+++ b/arch/arm/src/lpc17xx/lpc17_dac.h
@@ -41,7 +41,7 @@
  ************************************************************************************/
 
 #include 
-#include "chip/lpc17_dac.h"
+#include "hardware/lpc17_dac.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_emacram.h b/arch/arm/src/lpc17xx/lpc17_emacram.h
index d1d0d8d4e51..f68e62734e4 100644
--- a/arch/arm/src/lpc17xx/lpc17_emacram.h
+++ b/arch/arm/src/lpc17xx/lpc17_emacram.h
@@ -42,8 +42,8 @@
 
 #include 
 #include "chip.h"
-#include "chip/lpc17_ethernet.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_ethernet.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_emc.c b/arch/arm/src/lpc17xx/lpc17_emc.c
index c2701947e61..ca24d060bd5 100644
--- a/arch/arm/src/lpc17xx/lpc17_emc.c
+++ b/arch/arm/src/lpc17xx/lpc17_emc.c
@@ -45,7 +45,7 @@
 
 #include "up_arch.h"
 
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 #include "lpc17_gpio.h"
 #include "lpc17_emc.h"
 
diff --git a/arch/arm/src/lpc17xx/lpc17_emc.h b/arch/arm/src/lpc17xx/lpc17_emc.h
index b5a90100385..4b020762fe1 100644
--- a/arch/arm/src/lpc17xx/lpc17_emc.h
+++ b/arch/arm/src/lpc17xx/lpc17_emc.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/lpc17_emc.h"
+#include "hardware/lpc17_emc.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c
index 983b2497430..de08bb75cd8 100644
--- a/arch/arm/src/lpc17xx/lpc17_ethernet.c
+++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c
@@ -65,7 +65,7 @@
 
 #include "up_arch.h"
 #include "chip.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 #include "lpc17_gpio.h"
 #include "lpc17_ethernet.h"
 #include "lpc17_emacram.h"
diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.h b/arch/arm/src/lpc17xx/lpc17_ethernet.h
index 77ce1cc0f44..9aebf2d7e78 100644
--- a/arch/arm/src/lpc17xx/lpc17_ethernet.h
+++ b/arch/arm/src/lpc17xx/lpc17_ethernet.h
@@ -41,7 +41,7 @@
  ************************************************************************************/
 
 #include 
-#include "chip/lpc17_ethernet.h"
+#include "hardware/lpc17_ethernet.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.c b/arch/arm/src/lpc17xx/lpc17_gpdma.c
index 19b828edc0f..9de5338a867 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpdma.c
+++ b/arch/arm/src/lpc17xx/lpc17_gpdma.c
@@ -55,7 +55,7 @@
 
 #include "chip.h"
 
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 #include "lpc17_gpdma.h"
 
 #ifdef CONFIG_LPC17_GPDMA
diff --git a/arch/arm/src/lpc17xx/lpc17_gpdma.h b/arch/arm/src/lpc17xx/lpc17_gpdma.h
index 7953bda182a..3c93379a9d8 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpdma.h
+++ b/arch/arm/src/lpc17xx/lpc17_gpdma.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/lpc17_gpdma.h"
+#include "hardware/lpc17_gpdma.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_gpio.h b/arch/arm/src/lpc17xx/lpc17_gpio.h
index 6aab5b9f84c..b794c3055b1 100644
--- a/arch/arm/src/lpc17xx/lpc17_gpio.h
+++ b/arch/arm/src/lpc17xx/lpc17_gpio.h
@@ -49,9 +49,9 @@
 
 #include 
 
-#include "chip/lpc17_gpio.h"
-#include "chip/lpc17_pinconn.h"
-#include "chip/lpc17_pinconfig.h"
+#include "hardware/lpc17_gpio.h"
+#include "hardware/lpc17_pinconn.h"
+#include "hardware/lpc17_pinconfig.h"
 
 /* Include the GPIO definitions for the selected LPC17xx family. */
 
diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.c b/arch/arm/src/lpc17xx/lpc17_i2c.c
index 522afae6836..d89c2c7f60b 100644
--- a/arch/arm/src/lpc17xx/lpc17_i2c.c
+++ b/arch/arm/src/lpc17xx/lpc17_i2c.c
@@ -70,7 +70,7 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 #include "lpc17_gpio.h"
 #include "lpc17_i2c.h"
 
diff --git a/arch/arm/src/lpc17xx/lpc17_i2c.h b/arch/arm/src/lpc17xx/lpc17_i2c.h
index 044f0560c77..3595c880dbf 100644
--- a/arch/arm/src/lpc17xx/lpc17_i2c.h
+++ b/arch/arm/src/lpc17xx/lpc17_i2c.h
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/lpc17_i2c.h"
+#include "hardware/lpc17_i2c.h"
 
 /****************************************************************************
  * Public Function Prototypes
diff --git a/arch/arm/src/lpc17xx/lpc17_i2s.h b/arch/arm/src/lpc17xx/lpc17_i2s.h
index f6cbe067751..49a02dbec5d 100644
--- a/arch/arm/src/lpc17xx/lpc17_i2s.h
+++ b/arch/arm/src/lpc17xx/lpc17_i2s.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/lpc17_i2s.h"
+#include "hardware/lpc17_i2s.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_lcd.c b/arch/arm/src/lpc17xx/lpc17_lcd.c
index 04a95d69c16..9894e05f6cb 100644
--- a/arch/arm/src/lpc17xx/lpc17_lcd.c
+++ b/arch/arm/src/lpc17xx/lpc17_lcd.c
@@ -48,7 +48,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 #include "lpc17_gpio.h"
 #include "lpc17_lcd.h"
 
@@ -160,12 +160,12 @@ static const struct fb_planeinfo_s g_planeinfo =
 /* Current cursor position */
 
 #ifdef CONFIG_FB_HWCURSOR
-static struct cursor_pos_s g_cpos;
+static struct fb_cursorpos_s g_cpos;
 
 /* Current cursor size */
 
 #ifdef CONFIG_FB_HWCURSORSIZE
-static struct cursor_size_s g_csize;
+static struct fb_cursorsize_s g_csize;
 #endif
 #endif
 
diff --git a/arch/arm/src/lpc17xx/lpc17_lcd.h b/arch/arm/src/lpc17xx/lpc17_lcd.h
index 99daa200691..103cf81bca1 100644
--- a/arch/arm/src/lpc17xx/lpc17_lcd.h
+++ b/arch/arm/src/lpc17xx/lpc17_lcd.h
@@ -46,7 +46,7 @@
 
 #include 
 
-#include "chip/lpc17_lcd.h"
+#include "hardware/lpc17_lcd.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_lowputc.c b/arch/arm/src/lpc17xx/lpc17_lowputc.c
index 8f163f34403..7970940f906 100644
--- a/arch/arm/src/lpc17xx/lpc17_lowputc.c
+++ b/arch/arm/src/lpc17xx/lpc17_lowputc.c
@@ -47,8 +47,8 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/lpc17_syscon.h"
-#include "chip/lpc17_uart.h"
+#include "hardware/lpc17_syscon.h"
+#include "hardware/lpc17_uart.h"
 
 #include "lpc17_gpio.h"
 #include "lpc17_lowputc.h"
diff --git a/arch/arm/src/lpc17xx/lpc17_mcpwm.c b/arch/arm/src/lpc17xx/lpc17_mcpwm.c
index c076a10ce5e..997a1b46fac 100644
--- a/arch/arm/src/lpc17xx/lpc17_mcpwm.c
+++ b/arch/arm/src/lpc17xx/lpc17_mcpwm.c
@@ -54,9 +54,9 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 #include "lpc17_pwm.h"
-#include "chip/lpc176x_pinconfig.h"
+#include "hardware/lpc176x_pinconfig.h"
 #include "lpc17_gpio.h"
 #include "lpc176x_gpio.h"
 
diff --git a/arch/arm/src/lpc17xx/lpc17_ohciram.h b/arch/arm/src/lpc17xx/lpc17_ohciram.h
index bddeaa02ea7..7aa894c8e0d 100644
--- a/arch/arm/src/lpc17xx/lpc17_ohciram.h
+++ b/arch/arm/src/lpc17xx/lpc17_ohciram.h
@@ -42,7 +42,7 @@
 
 #include 
 #include "chip.h"
-#include "chip/lpc17_memorymap.h"
+#include "hardware/lpc17_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -150,7 +150,7 @@
 #  error "Insufficent TDs"
 #endif
 
-/* Derived size of user trasnfer descriptor (TD) memory. */
+/* Derived size of user transfer descriptor (TD) memory. */
 
 #define LPC17_TDFREE_SIZE (CONFIG_LP17_USBHOST_NTDS * LPC17_TD_SIZE)
 
diff --git a/arch/arm/src/lpc17xx/lpc17_pwm.c b/arch/arm/src/lpc17xx/lpc17_pwm.c
index f28c0996267..dbbc8de2cd0 100644
--- a/arch/arm/src/lpc17xx/lpc17_pwm.c
+++ b/arch/arm/src/lpc17xx/lpc17_pwm.c
@@ -54,9 +54,9 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 #include "lpc17_pwm.h"
-#include "chip/lpc176x_pinconfig.h"
+#include "hardware/lpc176x_pinconfig.h"
 #include "lpc17_gpio.h"
 #include "lpc176x_gpio.h"
 
diff --git a/arch/arm/src/lpc17xx/lpc17_pwm.h b/arch/arm/src/lpc17xx/lpc17_pwm.h
index f0f26cea099..34fba32bdd7 100644
--- a/arch/arm/src/lpc17xx/lpc17_pwm.h
+++ b/arch/arm/src/lpc17xx/lpc17_pwm.h
@@ -41,8 +41,8 @@
  ************************************************************************************/
 
 #include 
-#include "chip/lpc17_pwm.h"
-#include "chip/lpc17_mcpwm.h"
+#include "hardware/lpc17_pwm.h"
+#include "hardware/lpc17_mcpwm.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_qei.h b/arch/arm/src/lpc17xx/lpc17_qei.h
index e2515b10286..dfa01ff3ffc 100644
--- a/arch/arm/src/lpc17xx/lpc17_qei.h
+++ b/arch/arm/src/lpc17xx/lpc17_qei.h
@@ -41,7 +41,7 @@
  ************************************************************************************/
 
 #include 
-#include "chip/lpc17_qei.h"
+#include "hardware/lpc17_qei.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_rit.h b/arch/arm/src/lpc17xx/lpc17_rit.h
index 4c0949a467e..99611ca5a37 100644
--- a/arch/arm/src/lpc17xx/lpc17_rit.h
+++ b/arch/arm/src/lpc17xx/lpc17_rit.h
@@ -41,7 +41,7 @@
  ************************************************************************************/
 
 #include 
-#include "chip/lpc17_rit.h"
+#include "hardware/lpc17_rit.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_rtc.h b/arch/arm/src/lpc17xx/lpc17_rtc.h
index 1ee2ea91b27..80523759b67 100644
--- a/arch/arm/src/lpc17xx/lpc17_rtc.h
+++ b/arch/arm/src/lpc17xx/lpc17_rtc.h
@@ -41,7 +41,7 @@
  ************************************************************************************/
 
 #include 
-#include "chip/lpc17_rtc.h"
+#include "hardware/lpc17_rtc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.c b/arch/arm/src/lpc17xx/lpc17_sdcard.c
index 1d21e582c58..04e48c44e0a 100644
--- a/arch/arm/src/lpc17xx/lpc17_sdcard.c
+++ b/arch/arm/src/lpc17xx/lpc17_sdcard.c
@@ -65,8 +65,8 @@
 #include "lpc17_gpio.h"
 #include "lpc17_sdcard.h"
 
-#include "chip/lpc17_syscon.h"
-#include "chip/lpc17_pinconfig.h"
+#include "hardware/lpc17_syscon.h"
+#include "hardware/lpc17_pinconfig.h"
 
 #ifdef CONFIG_LPC17_SDCARD
 
diff --git a/arch/arm/src/lpc17xx/lpc17_sdcard.h b/arch/arm/src/lpc17xx/lpc17_sdcard.h
index 82f94264c7c..1057bcb60db 100644
--- a/arch/arm/src/lpc17xx/lpc17_sdcard.h
+++ b/arch/arm/src/lpc17xx/lpc17_sdcard.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc17_sdcard.h"
+#include "hardware/lpc17_sdcard.h"
 
 /************************************************************************************
  * Public Functions
diff --git a/arch/arm/src/lpc17xx/lpc17_serial.c b/arch/arm/src/lpc17xx/lpc17_serial.c
index 484356657f8..cdd4ae29a9a 100644
--- a/arch/arm/src/lpc17xx/lpc17_serial.c
+++ b/arch/arm/src/lpc17xx/lpc17_serial.c
@@ -62,7 +62,7 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/lpc17_uart.h"
+#include "hardware/lpc17_uart.h"
 #include "lpc17_gpio.h"
 #include "lpc17_serial.h"
 
diff --git a/arch/arm/src/lpc17xx/lpc17_serial.h b/arch/arm/src/lpc17xx/lpc17_serial.h
index 3db62f7f8a0..9e0205182bb 100644
--- a/arch/arm/src/lpc17xx/lpc17_serial.h
+++ b/arch/arm/src/lpc17xx/lpc17_serial.h
@@ -43,8 +43,8 @@
 #include 
 #include 
 
-#include "chip/lpc17_uart.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_uart.h"
+#include "hardware/lpc17_syscon.h"
 
 #include "lpc17_gpio.h"
 
diff --git a/arch/arm/src/lpc17xx/lpc17_spi.c b/arch/arm/src/lpc17xx/lpc17_spi.c
index f653df2d368..c75a57fa80e 100644
--- a/arch/arm/src/lpc17xx/lpc17_spi.c
+++ b/arch/arm/src/lpc17xx/lpc17_spi.c
@@ -56,7 +56,7 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 #include "lpc17_gpio.h"
 #include "lpc17_spi.h"
 
diff --git a/arch/arm/src/lpc17xx/lpc17_spi.h b/arch/arm/src/lpc17xx/lpc17_spi.h
index f0be0e99781..c807b88a53f 100644
--- a/arch/arm/src/lpc17xx/lpc17_spi.h
+++ b/arch/arm/src/lpc17xx/lpc17_spi.h
@@ -44,7 +44,7 @@
 
 #include 
 
-#include "chip/lpc17_spi.h"
+#include "hardware/lpc17_spi.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_ssp.c b/arch/arm/src/lpc17xx/lpc17_ssp.c
index af8fb4bc422..477572c8695 100644
--- a/arch/arm/src/lpc17xx/lpc17_ssp.c
+++ b/arch/arm/src/lpc17xx/lpc17_ssp.c
@@ -55,7 +55,7 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 #include "lpc17_gpio.h"
 #include "lpc17_ssp.h"
 
diff --git a/arch/arm/src/lpc17xx/lpc17_ssp.h b/arch/arm/src/lpc17xx/lpc17_ssp.h
index dd8ba3c766f..d08e1b8d179 100644
--- a/arch/arm/src/lpc17xx/lpc17_ssp.h
+++ b/arch/arm/src/lpc17xx/lpc17_ssp.h
@@ -44,7 +44,7 @@
 
 #include 
 
-#include "chip/lpc17_ssp.h"
+#include "hardware/lpc17_ssp.h"
 
 #if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1)
 
diff --git a/arch/arm/src/lpc17xx/lpc17_start.c b/arch/arm/src/lpc17xx/lpc17_start.c
index 41a6e57bfaa..441a0a38e83 100644
--- a/arch/arm/src/lpc17xx/lpc17_start.c
+++ b/arch/arm/src/lpc17xx/lpc17_start.c
@@ -50,15 +50,11 @@
 
 #include "up_arch.h"
 #include "up_internal.h"
+#include "nvic.h"
 
 #include "lpc17_clockconfig.h"
 #include "lpc17_lowputc.h"
 #include "lpc17_userspace.h"
-
-#ifdef CONFIG_ARCH_FPU
-#  include "nvic.h"
-#endif
-
 #include "lpc17_start.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/lpc17xx/lpc17_timer.c b/arch/arm/src/lpc17xx/lpc17_timer.c
index 8540d1b3862..ea780238f77 100644
--- a/arch/arm/src/lpc17xx/lpc17_timer.c
+++ b/arch/arm/src/lpc17xx/lpc17_timer.c
@@ -54,9 +54,9 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 #include "lpc17_timer.h"
-#include "chip/lpc176x_pinconfig.h"
+#include "hardware/lpc176x_pinconfig.h"
 #include "lpc17_gpio.h"
 #include "lpc176x_gpio.h"
 
diff --git a/arch/arm/src/lpc17xx/lpc17_timer.h b/arch/arm/src/lpc17xx/lpc17_timer.h
index d548fada516..3f0e8af09ac 100644
--- a/arch/arm/src/lpc17xx/lpc17_timer.h
+++ b/arch/arm/src/lpc17xx/lpc17_timer.h
@@ -41,7 +41,7 @@
  ************************************************************************************/
 
 #include 
-#include "chip/lpc17_timer.h"
+#include "hardware/lpc17_timer.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc17xx/lpc17_usbdev.c b/arch/arm/src/lpc17xx/lpc17_usbdev.c
index 778679ed5b2..6bb27bc06c4 100644
--- a/arch/arm/src/lpc17xx/lpc17_usbdev.c
+++ b/arch/arm/src/lpc17xx/lpc17_usbdev.c
@@ -60,8 +60,8 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/lpc17_usb.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_usb.h"
+#include "hardware/lpc17_syscon.h"
 #include "lpc17_gpio.h"
 #include "lpc17_gpdma.h"
 
diff --git a/arch/arm/src/lpc17xx/lpc17_usbhost.c b/arch/arm/src/lpc17xx/lpc17_usbhost.c
index 6231c13ab51..e8954bbc68e 100644
--- a/arch/arm/src/lpc17xx/lpc17_usbhost.c
+++ b/arch/arm/src/lpc17xx/lpc17_usbhost.c
@@ -66,8 +66,8 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/lpc17_usb.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_usb.h"
+#include "hardware/lpc17_syscon.h"
 #include "lpc17_gpio.h"
 #include "lpc17_ohciram.h"
 
diff --git a/arch/arm/src/lpc17xx/lpc17_wdt.h b/arch/arm/src/lpc17xx/lpc17_wdt.h
index b9ef49fc35f..eb4d60834e3 100644
--- a/arch/arm/src/lpc17xx/lpc17_wdt.h
+++ b/arch/arm/src/lpc17xx/lpc17_wdt.h
@@ -41,7 +41,7 @@
  ************************************************************************************/
 
 #include 
-#include "chip/lpc17_wdt.h"
+#include "hardware/lpc17_wdt.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc214x/Make.defs b/arch/arm/src/lpc214x/Make.defs
index ccf6c4c7467..e1edb2cd015 100644
--- a/arch/arm/src/lpc214x/Make.defs
+++ b/arch/arm/src/lpc214x/Make.defs
@@ -45,16 +45,13 @@ CMN_CSRCS += up_exit.c up_initialize.c up_initialstate.c
 CMN_CSRCS += up_interruptcontext.c up_prefetchabort.c up_releasepending.c
 CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_stackframe.c
 CMN_CSRCS += up_syscall.c up_unblocktask.c up_undefinedinsn.c up_usestack.c
+CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c
 CMN_CSRCS += up_lowputs.c up_vfork.c
 
 ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
 CMN_CSRCS += up_idle.c
 endif
 
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
-CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c
-endif
-
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
 endif
diff --git a/arch/arm/src/lpc2378/Make.defs b/arch/arm/src/lpc2378/Make.defs
index b0f1f8b5c3e..15be9977b98 100644
--- a/arch/arm/src/lpc2378/Make.defs
+++ b/arch/arm/src/lpc2378/Make.defs
@@ -49,15 +49,12 @@ CMN_CSRCS += up_interruptcontext.c up_prefetchabort.c up_releasepending.c
 CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_stackframe.c
 CMN_CSRCS += up_syscall.c up_unblocktask.c up_undefinedinsn.c
 CMN_CSRCS += up_usestack.c up_lowputs.c up_vfork.c
+CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c
 
 ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
 CMN_CSRCS += up_idle.c
 endif
 
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
-CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c
-endif
-
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
 endif
diff --git a/arch/arm/src/lpc43xx/Make.defs b/arch/arm/src/lpc43xx/Make.defs
index 1892b721c22..b083bc3bdf1 100644
--- a/arch/arm/src/lpc43xx/Make.defs
+++ b/arch/arm/src/lpc43xx/Make.defs
@@ -60,11 +60,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
diff --git a/arch/arm/src/lpc43xx/chip.h b/arch/arm/src/lpc43xx/chip.h
index 59702c79484..dee6106b4fd 100644
--- a/arch/arm/src/lpc43xx/chip.h
+++ b/arch/arm/src/lpc43xx/chip.h
@@ -67,88 +67,88 @@
 
 #if defined(CONFIG_ARCH_CHIP_LPC4310FBD144)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc4310203050_memorymap.h"
-#  include "chip/lpc4310203050_pinconfig.h"
+#  include "hardware/lpc4310203050_memorymap.h"
+#  include "hardware/lpc4310203050_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4310FET100)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc4310203050_memorymap.h"
-#  include "chip/lpc4310203050_pinconfig.h"
+#  include "hardware/lpc4310203050_memorymap.h"
+#  include "hardware/lpc4310203050_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4320FBD144)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc4310203050_memorymap.h"
-#  include "chip/lpc4310203050_pinconfig.h"
+#  include "hardware/lpc4310203050_memorymap.h"
+#  include "hardware/lpc4310203050_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4320FET100)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc4310203050_memorymap.h"
-#  include "chip/lpc4310203050_pinconfig.h"
+#  include "hardware/lpc4310203050_memorymap.h"
+#  include "hardware/lpc4310203050_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4330FBD144)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc4310203050_memorymap.h"
-#  include "chip/lpc4310203050_pinconfig.h"
+#  include "hardware/lpc4310203050_memorymap.h"
+#  include "hardware/lpc4310203050_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4330FET100)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc4310203050_memorymap.h"
-#  include "chip/lpc4310203050_pinconfig.h"
+#  include "hardware/lpc4310203050_memorymap.h"
+#  include "hardware/lpc4310203050_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4330FET180)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc4310203050_memorymap.h"
-#  include "chip/lpc4310203050_pinconfig.h"
+#  include "hardware/lpc4310203050_memorymap.h"
+#  include "hardware/lpc4310203050_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4330FET256)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc4310203050_memorymap.h"
-#  include "chip/lpc4310203050_pinconfig.h"
+#  include "hardware/lpc4310203050_memorymap.h"
+#  include "hardware/lpc4310203050_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc435357_memorymap.h"
-#  include "chip/lpc4357fet256_pinconfig.h"
+#  include "hardware/lpc435357_memorymap.h"
+#  include "hardware/lpc4357fet256_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4337FET256)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc435357_memorymap.h"
-#  include "chip/lpc4310203050_pinconfig.h"
+#  include "hardware/lpc435357_memorymap.h"
+#  include "hardware/lpc4310203050_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc4310203050_memorymap.h"
-#  include "chip/lpc4310203050_pinconfig.h"
+#  include "hardware/lpc4310203050_memorymap.h"
+#  include "hardware/lpc4310203050_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4350FET180)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc4310203050_memorymap.h"
-#  include "chip/lpc4310203050_pinconfig.h"
+#  include "hardware/lpc4310203050_memorymap.h"
+#  include "hardware/lpc4310203050_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4350FET256)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc4310203050_memorymap.h"
-#  include "chip/lpc4310203050_pinconfig.h"
+#  include "hardware/lpc4310203050_memorymap.h"
+#  include "hardware/lpc4310203050_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4353FBD208)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc435357_memorymap.h"
-#  include "chip/lpc4353fbd208_pinconfig.h"
+#  include "hardware/lpc435357_memorymap.h"
+#  include "hardware/lpc4353fbd208_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4353FET180)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc435357_memorymap.h"
-#  include "chip/lpc4353fet180_pinconfig.h"
+#  include "hardware/lpc435357_memorymap.h"
+#  include "hardware/lpc4353fet180_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4353FET256)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc435357_memorymap.h"
-#  include "chip/lpc4353fet256_pinconfig.h"
+#  include "hardware/lpc435357_memorymap.h"
+#  include "hardware/lpc4353fet256_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4357FET180)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc435357_memorymap.h"
-#  include "chip/lpc4357fet180_pinconfig.h"
+#  include "hardware/lpc435357_memorymap.h"
+#  include "hardware/lpc4357fet180_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4357FBD208)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc435357_memorymap.h"
-#  include "chip/lpc4357fbd208_pinconfig.h"
+#  include "hardware/lpc435357_memorymap.h"
+#  include "hardware/lpc4357fbd208_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4357FET256)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc435357_memorymap.h"
-#  include "chip/lpc4357fet256_pinconfig.h"
+#  include "hardware/lpc435357_memorymap.h"
+#  include "hardware/lpc4357fet256_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4370FET100)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc435357_memorymap.h"
-#  include "chip/lpc4357fet256_pinconfig.h"
+#  include "hardware/lpc435357_memorymap.h"
+#  include "hardware/lpc4357fet256_pinconfig.h"
 #elif defined(CONFIG_ARCH_CHIP_LPC4337JET100)
 #  define  ARMV7M_PERIPHERAL_INTERRUPTS 53
-#  include "chip/lpc435357_memorymap.h"
-#  include "chip/lpc4337jet100_pinconfig.h"
+#  include "hardware/lpc435357_memorymap.h"
+#  include "hardware/lpc4337jet100_pinconfig.h"
 #else
 #  error "Unsupported LPC43xx chip"
 #endif
diff --git a/arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h b/arch/arm/src/lpc43xx/hardware/lpc4310203050_memorymap.h
similarity index 97%
rename from arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h
rename to arch/arm/src/lpc43xx/hardware/lpc4310203050_memorymap.h
index 33de4577d27..ea5669bd737 100644
--- a/arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc4310203050_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc4310203050_memorymap.h
+ * arch/arm/src/lpc43xx/hardware/lpc4310203050_memorymap.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4310203050_MEMORYMAP_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4310203050_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC4310203050_MEMORYMAP_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC4310203050_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -193,4 +193,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4310203050_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC4310203050_MEMORYMAP_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h b/arch/arm/src/lpc43xx/hardware/lpc4310203050_pinconfig.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h
rename to arch/arm/src/lpc43xx/hardware/lpc4310203050_pinconfig.h
index bd61476e89d..57a25b45c97 100644
--- a/arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc4310203050_pinconfig.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h
+ * arch/arm/src/lpc43xx/hardware/lpc4310203050_pinconfig.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4310203050_PINCONF_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4310203050_PINCONF_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC4310203050_PINCONF_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC4310203050_PINCONF_H
 
 /****************************************************************************************************
  * Included Files
@@ -65,7 +65,7 @@
  *
  *    #define PINCONF_CAN1_RD PINCONF_CAN1_RD_1
  *
- *    The driver will then automatically configre Pins1[18] as the CAN1 RD pin.
+ *    The driver will then automatically configure Pins1[18] as the CAN1 RD pin.
  */
 
 #define PINCONF_ADC0p0           (PINCONF_FUNC0|PINCONF_PINS4|PINCONF_PIN_3)
@@ -986,4 +986,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4310203050_PINCONF_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC4310203050_PINCONF_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h b/arch/arm/src/lpc43xx/hardware/lpc4337jet100_pinconfig.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h
rename to arch/arm/src/lpc43xx/hardware/lpc4337jet100_pinconfig.h
index 7f74cd821a1..96b96dccc61 100644
--- a/arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc4337jet100_pinconfig.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h
+ * arch/arm/src/lpc43xx/hardware/lpc4337jet100_pinconfig.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4337JET100_PINCONF_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4337JET100_PINCONF_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC4337JET100_PINCONF_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC4337JET100_PINCONF_H
 
 /****************************************************************************************************
  * Included Files
@@ -66,7 +66,7 @@
  *
  *    #define PINCONF_CAN1_RD PINCONF_CAN1_RD_1
  *
- *    The driver will then automatically configre Pins1[18] as the CAN1 RD pin.
+ *    The driver will then automatically configure Pins1[18] as the CAN1 RD pin.
  */
 
 #define PINCONF_ADC0p0           (PINCONF_FUNC0|PINCONF_PINS4|PINCONF_PIN_3)
@@ -985,4 +985,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4337JET100_PINCONF_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC4337JET100_PINCONF_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h b/arch/arm/src/lpc43xx/hardware/lpc435357_memorymap.h
similarity index 97%
rename from arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h
rename to arch/arm/src/lpc43xx/hardware/lpc435357_memorymap.h
index 852bd2a862e..956c869dfa2 100644
--- a/arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc435357_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc435357_memorymap.h
+ * arch/arm/src/lpc43xx/hardware/lpc435357_memorymap.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC435357_MEMORYMAP_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC435357_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC435357_MEMORYMAP_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC435357_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -199,4 +199,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC435357_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC435357_MEMORYMAP_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h b/arch/arm/src/lpc43xx/hardware/lpc4357fet256_pinconfig.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h
rename to arch/arm/src/lpc43xx/hardware/lpc4357fet256_pinconfig.h
index 0db1e919630..1b2ce2c7826 100644
--- a/arch/arm/src/lpc43xx/chip/lpc4357fet256_pinconfig.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc4357fet256_pinconfig.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc4310203050_pinconfig.h
+ * arch/arm/src/lpc43xx/hardware/lpc4310203050_pinconfig.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4357FET256_PINCONF_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4357FET256_PINCONF_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC4357FET256_PINCONF_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC4357FET256_PINCONF_H
 
 /****************************************************************************************************
  * Included Files
@@ -65,7 +65,7 @@
  *
  *    #define PINCONF_CAN1_RD PINCONF_CAN1_RD_1
  *
- *    The driver will then automatically configre Pins1[18] as the CAN1 RD pin.
+ *    The driver will then automatically configure Pins1[18] as the CAN1 RD pin.
  */
 
 #define PINCONF_ADC0p0           (PINCONF_FUNC0|PINCONF_PINS4|PINCONF_PIN_3)
@@ -984,4 +984,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC4357FET256_PINCONF_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC4357FET256_PINCONF_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_adc.h b/arch/arm/src/lpc43xx/hardware/lpc43_adc.h
similarity index 98%
rename from arch/arm/src/lpc43xx/chip/lpc43_adc.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_adc.h
index 523cbcb45c9..292589f1c48 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_adc.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_adc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/lpc43_adc.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_adc.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ADC_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ADC_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_ADC_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_ADC_H
 
 /************************************************************************************
  * Included Files
@@ -195,4 +195,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ADC_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_ADC_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_aes.h b/arch/arm/src/lpc43xx/hardware/lpc43_aes.h
similarity index 95%
rename from arch/arm/src/lpc43xx/chip/lpc43_aes.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_aes.h
index fbd557f3d48..087907ecab9 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_aes.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_aes.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_aes.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_aes.h
  *
  *   Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_AES_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_AES_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_AES_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_AES_H
 
 /************************************************************************************
  * Included Files
@@ -123,4 +123,4 @@ enum lpc43_aes_errorcodes_e
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_AES_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_AES_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_atimer.h b/arch/arm/src/lpc43xx/hardware/lpc43_atimer.h
similarity index 96%
rename from arch/arm/src/lpc43xx/chip/lpc43_atimer.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_atimer.h
index 1a5ef860274..40bfad4f72b 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_atimer.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_atimer.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_atimer.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_atimer.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ATIMER_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ATIMER_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_ATIMER_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_ATIMER_H
 
 /************************************************************************************
  * Included Files
@@ -114,4 +114,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ATIMER_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_ATIMER_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_can.h b/arch/arm/src/lpc43xx/hardware/lpc43_can.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc43_can.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_can.h
index c03ceab04bd..15195298824 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_can.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_can.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_can.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_can.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CAN_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CAN_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_CAN_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_CAN_H
 
 /************************************************************************************
  * Included Files
@@ -455,4 +455,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CAN_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_CAN_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_ccu.h b/arch/arm/src/lpc43xx/hardware/lpc43_ccu.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc43_ccu.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_ccu.h
index 51cdcdb9fc9..1bec32d81f4 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_ccu.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_ccu.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_ccu.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_ccu.h
  *
  *   Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CCU_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CCU_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_CCU_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_CCU_H
 
 /****************************************************************************************************
  * Included Files
@@ -373,4 +373,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CCU_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_CCU_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_cgu.h b/arch/arm/src/lpc43xx/hardware/lpc43_cgu.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc43_cgu.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_cgu.h
index 7f60f38836f..b2059f86a9e 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_cgu.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_cgu.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_cgu.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_cgu.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CGU_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CGU_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_CGU_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_CGU_H
 
 /****************************************************************************************************
  * Included Files
@@ -888,4 +888,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CGU_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_CGU_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_creg.h b/arch/arm/src/lpc43xx/hardware/lpc43_creg.h
similarity index 98%
rename from arch/arm/src/lpc43xx/chip/lpc43_creg.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_creg.h
index 61a62e69406..046be810dc5 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_creg.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_creg.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_creg.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_creg.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CREG_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CREG_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_CREG_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_CREG_H
 
 /************************************************************************************
  * Included Files
@@ -288,4 +288,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_CREG_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_CREG_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_dac.h b/arch/arm/src/lpc43xx/hardware/lpc43_dac.h
similarity index 95%
rename from arch/arm/src/lpc43xx/chip/lpc43_dac.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_dac.h
index e06ecf442c1..d1d08c6e87d 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_dac.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_dac.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/lpc43_dac.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_dac.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_DAC_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_DAC_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_DAC_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_DAC_H
 
 /************************************************************************************
  * Included Files
@@ -91,4 +91,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_DAC_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_DAC_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_eeprom.h b/arch/arm/src/lpc43xx/hardware/lpc43_eeprom.h
similarity index 97%
rename from arch/arm/src/lpc43xx/chip/lpc43_eeprom.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_eeprom.h
index 8b0398447ea..d5cf5615009 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_eeprom.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_eeprom.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_eeprom.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_eeprom.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EEPROM_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EEPROM_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_EEPROM_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_EEPROM_H
 
 /************************************************************************************
  * Included Files
@@ -155,4 +155,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EEPROM_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_EEPROM_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_emc.h b/arch/arm/src/lpc43xx/hardware/lpc43_emc.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc43_emc.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_emc.h
index b61cbcbc585..730df062717 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_emc.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_emc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_emc.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_emc.h
  *
  *   Copyright (C) 2012, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EMC_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EMC_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_EMC_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_EMC_H
 
 /****************************************************************************************************
  * Included Files
@@ -504,4 +504,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EMC_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_EMC_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h b/arch/arm/src/lpc43xx/hardware/lpc43_ethernet.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc43_ethernet.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_ethernet.h
index d03ed7123b0..c0d34d1b1bf 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_ethernet.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_ethernet.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_ethernet.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_ethernet.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ETHERNET_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ETHERNET_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_ETHERNET_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_ETHERNET_H
 
 /****************************************************************************************************
  * Included Files
@@ -654,4 +654,4 @@ struct eth_rxdesc_s
  ****************************************************************************************************/
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ETHERNET_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_ETHERNET_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_evntmntr.h b/arch/arm/src/lpc43xx/hardware/lpc43_evntmntr.h
similarity index 97%
rename from arch/arm/src/lpc43xx/chip/lpc43_evntmntr.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_evntmntr.h
index a12112ecedf..85854a94997 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_evntmntr.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_evntmntr.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_eventmntr.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_eventmntr.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTMNTR_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTMNTR_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_EVNTMNTR_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_EVNTMNTR_H
 
 /****************************************************************************************************
  * Included Files
@@ -147,4 +147,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTMNTR_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_EVNTMNTR_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h b/arch/arm/src/lpc43xx/hardware/lpc43_evntrtr.h
similarity index 97%
rename from arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_evntrtr.h
index 1287dfd8757..c4ce2e925db 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_evntrtr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_evntrtr.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_evntrtr.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTRTR_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTRTR_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_EVNTRTR_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_EVNTRTR_H
 
 /************************************************************************************
  * Included Files
@@ -156,4 +156,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_EVNTRTR_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_EVNTRTR_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_flash.h b/arch/arm/src/lpc43xx/hardware/lpc43_flash.h
similarity index 96%
rename from arch/arm/src/lpc43xx/chip/lpc43_flash.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_flash.h
index 4f99484dac7..1b8d2e9c350 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_flash.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_flash.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_flash.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_flash.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_FLASH_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_FLASH_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_FLASH_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_FLASH_H
 
 /************************************************************************************
  * Included Files
@@ -184,4 +184,4 @@ typedef void (*iap_t)(unsigned int *cmd, unsigned int *result);
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_FLASH_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_FLASH_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_gima.h b/arch/arm/src/lpc43xx/hardware/lpc43_gima.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc43_gima.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_gima.h
index 993242ebe49..58cbf9528ed 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_gima.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_gima.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_gima.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_gima.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GIMA_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GIMA_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_GIMA_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_GIMA_H
 
 /****************************************************************************************************
  * Included Files
@@ -333,4 +333,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GIMA_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_GIMA_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h b/arch/arm/src/lpc43xx/hardware/lpc43_gpdma.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc43_gpdma.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_gpdma.h
index 6becfe92223..ab1599d1fb2 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_gpdma.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_gpdma.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_gpdma.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GPDMA_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GPDMA_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_GPDMA_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_GPDMA_H
 
 /****************************************************************************************************
  * Included Files
@@ -469,4 +469,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GPDMA_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_GPDMA_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_gpio.h b/arch/arm/src/lpc43xx/hardware/lpc43_gpio.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc43_gpio.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_gpio.h
index a4d0ad7ad07..cf1c2555785 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_gpio.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_gpio.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_gpio.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_gpio.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GPIO_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GPIO_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_GPIO_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_GPIO_H
 
 /****************************************************************************************************
  * Included Files
@@ -438,4 +438,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_GPIO_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_GPIO_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_i2c.h b/arch/arm/src/lpc43xx/hardware/lpc43_i2c.h
similarity index 98%
rename from arch/arm/src/lpc43xx/chip/lpc43_i2c.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_i2c.h
index 000fbed5151..ebdef8c6fb4 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_i2c.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_i2c.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/lpc43_i2c.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_i2c.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2C_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2C_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_I2C_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_I2C_H
 
 /************************************************************************************
  * Included Files
@@ -202,4 +202,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2C_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_I2C_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_i2s.h b/arch/arm/src/lpc43xx/hardware/lpc43_i2s.h
similarity index 98%
rename from arch/arm/src/lpc43xx/chip/lpc43_i2s.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_i2s.h
index 71fc875e98f..861c8489f46 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_i2s.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_i2s.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/lpc43_i2s
+ * arch/arm/src/lpc43xx/hardware/lpc43_i2s
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2S_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2S_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_I2S_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_I2S_H
 
 /************************************************************************************
  * Included Files
@@ -199,4 +199,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_I2S_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_I2S_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_lcd.h b/arch/arm/src/lpc43xx/hardware/lpc43_lcd.h
similarity index 98%
rename from arch/arm/src/lpc43xx/chip/lpc43_lcd.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_lcd.h
index 5762bed5e26..0899235c097 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_lcd.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_lcd.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_lcd.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_lcd.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_LCD_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_LCD_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_LCD_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_LCD_H
 
 /****************************************************************************************************
  * Included Files
@@ -301,4 +301,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_LCD_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_LCD_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_mcpwm.h b/arch/arm/src/lpc43xx/hardware/lpc43_mcpwm.h
similarity index 98%
rename from arch/arm/src/lpc43xx/chip/lpc43_mcpwm.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_mcpwm.h
index 720b8affc42..76a67434b95 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_mcpwm.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_mcpwm.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/lpc43_mcpwm.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_mcpwm.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MCPWM_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MCPWM_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_MCPWM_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_MCPWM_H
 
 /************************************************************************************
  * Included Files
@@ -271,4 +271,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_MCPWM_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_MCPWM_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_otp.h b/arch/arm/src/lpc43xx/hardware/lpc43_otp.h
similarity index 97%
rename from arch/arm/src/lpc43xx/chip/lpc43_otp.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_otp.h
index 45a777fd943..549ad0f53ad 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_otp.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_otp.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_otp.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_otp.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_OTP_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_OTP_H
 
 /************************************************************************************
  * Included Files
@@ -189,4 +189,4 @@ struct lpc43_otp_s
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_OTP_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_OTP_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_pmc.h b/arch/arm/src/lpc43xx/hardware/lpc43_pmc.h
similarity index 94%
rename from arch/arm/src/lpc43xx/chip/lpc43_pmc.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_pmc.h
index 511c515a28e..dc239718307 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_pmc.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_pmc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_pmc.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_pmc.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_PMC_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_PMC_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_PMC_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_PMC_H
 
 /************************************************************************************
  * Included Files
@@ -79,4 +79,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_PMC_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_PMC_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_qei.h b/arch/arm/src/lpc43xx/hardware/lpc43_qei.h
similarity index 98%
rename from arch/arm/src/lpc43xx/chip/lpc43_qei.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_qei.h
index 9994c4e9e7f..acacade654e 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_qei.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_qei.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/lpc43_qei.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_qei.h
  *
  *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_QEI_H
-#define __ARCH_ARM_SRC_LPC43XX_LPC43_QEI_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43QEI_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43QEI_H
 
 /************************************************************************************
  * Included Files
@@ -208,4 +208,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_QEI_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43QEI_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_rgu.h b/arch/arm/src/lpc43xx/hardware/lpc43_rgu.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc43_rgu.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_rgu.h
index acf2fdc5d86..c560cec5f78 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_rgu.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_rgu.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_rgu.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_rgu.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RGU_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RGU_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_RGU_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_RGU_H
 
 /****************************************************************************************************
  * Included Files
@@ -666,4 +666,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RGU_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_RGU_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_rit.h b/arch/arm/src/lpc43xx/hardware/lpc43_rit.h
similarity index 95%
rename from arch/arm/src/lpc43xx/chip/lpc43_rit.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_rit.h
index 71671cd3ab0..d7541f7f110 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_rit.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_rit.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/lpc43_rit.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_rit.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Brandon Warhurst 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RIT_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RIT_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_RIT_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_RIT_H
 
 /************************************************************************************
  * Included Files
@@ -87,4 +87,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_RIT_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_RIT_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_rtc.h b/arch/arm/src/lpc43xx/hardware/lpc43_rtc.h
similarity index 98%
rename from arch/arm/src/lpc43xx/chip/lpc43_rtc.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_rtc.h
index 9713493543d..9c518b9bc30 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_rtc.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_rtc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/lpc43_rtc.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_rtc.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H
-#define __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43RTC_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43RTC_H
 
 /************************************************************************************
  * Included Files
@@ -368,4 +368,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_RTC_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43RTC_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_sct.h b/arch/arm/src/lpc43xx/hardware/lpc43_sct.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc43_sct.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_sct.h
index 4393d2cc417..1b38e3f9a0f 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_sct.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_sct.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_sct.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_sct.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SCT_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SCT_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SCT_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SCT_H
 
 /****************************************************************************************************
  * Included Files
@@ -1525,4 +1525,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SCT_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SCT_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_scu.h b/arch/arm/src/lpc43xx/hardware/lpc43_scu.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc43_scu.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_scu.h
index 0c0dea3cb49..4075dd918b2 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_scu.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_scu.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_scu.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_scu.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SCU_SCU_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SCU_SCU_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SCU_SCU_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SCU_SCU_H
 
 /****************************************************************************************************
  * Included Files
@@ -453,4 +453,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SCU_SCU_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SCU_SCU_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h b/arch/arm/src/lpc43xx/hardware/lpc43_sdmmc.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_sdmmc.h
index a61c254894c..05b8cbbd56c 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_sdmmc.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/lpc43xx/lpc43_sdmmc.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_sdmmc.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SDMMC_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SDMMC_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SDMMC_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SDMMC_H
 
 /************************************************************************************************
  * Included Files
@@ -406,4 +406,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SDMMC_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SDMMC_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_sgpio.h b/arch/arm/src/lpc43xx/hardware/lpc43_sgpio.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc43_sgpio.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_sgpio.h
index bb68b872a02..8b4c2b1ec18 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_sgpio.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_sgpio.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/lpc43xx/chip/lpc43_sgpio.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_sgpio.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SGPIO_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SGPIO_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SGPIO_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SGPIO_H
 
 /****************************************************************************************************
  * Included Files
@@ -686,4 +686,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SGPIO_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SGPIO_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_spi.h b/arch/arm/src/lpc43xx/hardware/lpc43_spi.h
similarity index 97%
rename from arch/arm/src/lpc43xx/chip/lpc43_spi.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_spi.h
index 5f6e26d6b90..18f155099be 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_spi.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_spi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/lpc43_spi.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_spi.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPI_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPI_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SPI_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SPI_H
 
 /************************************************************************************
  * Included Files
@@ -135,4 +135,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPI_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SPI_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_spifi.h b/arch/arm/src/lpc43xx/hardware/lpc43_spifi.h
similarity index 97%
rename from arch/arm/src/lpc43xx/chip/lpc43_spifi.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_spifi.h
index df70d727edf..d006f421ce7 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_spifi.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_spifi.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- *  arch/arm/src/lpc43/chip/lpc43_spifi.h
+ *  arch/arm/src/lpc43xx/hardware/lpc43_spifi.h
  *
  *   Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -58,8 +58,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPIFI_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPIFI_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SPIFI_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SPIFI_H
 
 /****************************************************************************
  * Included Files
@@ -292,4 +292,4 @@ int32_t spifi_erase(struct spifi_dev_s *dev,
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SPIFI_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SPIFI_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_ssp.h b/arch/arm/src/lpc43xx/hardware/lpc43_ssp.h
similarity index 97%
rename from arch/arm/src/lpc43xx/chip/lpc43_ssp.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_ssp.h
index 2bf9340973f..5286b79c752 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_ssp.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_ssp.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/lpc43_ssp.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_ssp.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SSP_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SSP_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SSP_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SSP_H
 
 /************************************************************************************
  * Included Files
@@ -168,4 +168,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_SSP_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_SSP_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_timer.h b/arch/arm/src/lpc43xx/hardware/lpc43_timer.h
similarity index 98%
rename from arch/arm/src/lpc43xx/chip/lpc43_timer.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_timer.h
index b62f1352a30..43a9dbffcb6 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_timer.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_timer.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/lpc43_timer.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_timer.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_TIMER_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_TIMER_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_TIMER_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_TIMER_H
 
 /************************************************************************************
  * Included Files
@@ -270,4 +270,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_TIMER_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_TIMER_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_uart.h b/arch/arm/src/lpc43xx/hardware/lpc43_uart.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc43_uart.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_uart.h
index de6944030eb..e841c57286f 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_uart.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_uart.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/lpc43xx/lpc43_uart.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_uart.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_UART_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_UART_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_UART_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_UART_H
 
 /********************************************************************************************
  * Included Files
@@ -416,4 +416,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_UART_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_UART_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_usb0.h b/arch/arm/src/lpc43xx/hardware/lpc43_usb0.h
similarity index 99%
rename from arch/arm/src/lpc43xx/chip/lpc43_usb0.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_usb0.h
index 0a89232bb9d..d0473461284 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_usb0.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_usb0.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/lpc43xx/lpc43_usb0.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_usb0.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_USB0_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_USB0_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_USB0_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_USB0_H
 
 /************************************************************************************************
  * Included Files
@@ -716,4 +716,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_USB0_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_USB0_H */
diff --git a/arch/arm/src/lpc43xx/chip/lpc43_wwdt.h b/arch/arm/src/lpc43xx/hardware/lpc43_wwdt.h
similarity index 96%
rename from arch/arm/src/lpc43xx/chip/lpc43_wwdt.h
rename to arch/arm/src/lpc43xx/hardware/lpc43_wwdt.h
index df9d172c756..09b04a54d36 100644
--- a/arch/arm/src/lpc43xx/chip/lpc43_wwdt.h
+++ b/arch/arm/src/lpc43xx/hardware/lpc43_wwdt.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/lpc43xx/lpc43_wwdt.h
+ * arch/arm/src/lpc43xx/hardware/lpc43_wwdt.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_WWDT_H
-#define __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_WWDT_H
+#ifndef __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_WWDT_H
+#define __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_WWDT_H
 
 /************************************************************************************
  * Included Files
@@ -108,4 +108,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_WWDT_H */
+#endif /* __ARCH_ARM_SRC_LPC43XX_HARDWARE_LPC43_WWDT_H */
diff --git a/arch/arm/src/lpc43xx/lpc43_adc.c b/arch/arm/src/lpc43xx/lpc43_adc.c
index 3217755a749..bcb3db15090 100644
--- a/arch/arm/src/lpc43xx/lpc43_adc.c
+++ b/arch/arm/src/lpc43xx/lpc43_adc.c
@@ -74,8 +74,8 @@
 #include "lpc43_ccu.h"
 #include "lpc43_creg.h"
 
-#include "chip/lpc43_gima.h"
-#include "chip/lpc43_timer.h"
+#include "hardware/lpc43_gima.h"
+#include "hardware/lpc43_timer.h"
 
 #include "lpc43_pinconfig.h"
 
diff --git a/arch/arm/src/lpc43xx/lpc43_adc.h b/arch/arm/src/lpc43xx/lpc43_adc.h
index 62b2cc5b855..ebfc2b21280 100644
--- a/arch/arm/src/lpc43xx/lpc43_adc.h
+++ b/arch/arm/src/lpc43xx/lpc43_adc.h
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/lpc43_adc.h"
+#include "hardware/lpc43_adc.h"
 
 #ifdef CONFIG_LPC43_ADC0
 
diff --git a/arch/arm/src/lpc43xx/lpc43_can.c b/arch/arm/src/lpc43xx/lpc43_can.c
index 630e00e0f19..a57bbf65be3 100644
--- a/arch/arm/src/lpc43xx/lpc43_can.c
+++ b/arch/arm/src/lpc43xx/lpc43_can.c
@@ -55,8 +55,8 @@
 
 #include "chip.h"
 #include "lpc43_gpio.h"
-#include "chip/lpc43_can.h"
-#include "chip/lpc43_rgu.h"
+#include "hardware/lpc43_can.h"
+#include "hardware/lpc43_rgu.h"
 #include "lpc43_ccu.h"
 #include "lpc43_cgu.h"
 
diff --git a/arch/arm/src/lpc43xx/lpc43_can.h b/arch/arm/src/lpc43xx/lpc43_can.h
index 37074c6df34..8fd1eaff3a3 100644
--- a/arch/arm/src/lpc43xx/lpc43_can.h
+++ b/arch/arm/src/lpc43xx/lpc43_can.h
@@ -45,7 +45,7 @@
 #include 
 #include 
 
-#include "chip/lpc43_can.h"
+#include "hardware/lpc43_can.h"
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/src/lpc43xx/lpc43_ccu.h b/arch/arm/src/lpc43xx/lpc43_ccu.h
index 21fd0b1b147..45914b62957 100644
--- a/arch/arm/src/lpc43xx/lpc43_ccu.h
+++ b/arch/arm/src/lpc43xx/lpc43_ccu.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/lpc43_ccu.h"
+#include "hardware/lpc43_ccu.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc43xx/lpc43_cgu.h b/arch/arm/src/lpc43xx/lpc43_cgu.h
index 6cdfff5ba74..294dc419014 100644
--- a/arch/arm/src/lpc43xx/lpc43_cgu.h
+++ b/arch/arm/src/lpc43xx/lpc43_cgu.h
@@ -42,7 +42,7 @@
 
 #include 
 #include "chip.h"
-#include "chip/lpc43_cgu.h"
+#include "hardware/lpc43_cgu.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc43xx/lpc43_creg.h b/arch/arm/src/lpc43xx/lpc43_creg.h
index d917bd63815..01b8360849d 100644
--- a/arch/arm/src/lpc43xx/lpc43_creg.h
+++ b/arch/arm/src/lpc43xx/lpc43_creg.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/lpc43_creg.h"
+#include "hardware/lpc43_creg.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc43xx/lpc43_dac.h b/arch/arm/src/lpc43xx/lpc43_dac.h
index f652d71c9b2..41983ea3788 100644
--- a/arch/arm/src/lpc43xx/lpc43_dac.h
+++ b/arch/arm/src/lpc43xx/lpc43_dac.h
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/lpc43_dac.h"
+#include "hardware/lpc43_dac.h"
 
 #ifdef CONFIG_LPC43_DAC
 
diff --git a/arch/arm/src/lpc43xx/lpc43_ehci.c b/arch/arm/src/lpc43xx/lpc43_ehci.c
index 91f6886710d..d7fa789fa43 100644
--- a/arch/arm/src/lpc43xx/lpc43_ehci.c
+++ b/arch/arm/src/lpc43xx/lpc43_ehci.c
@@ -62,12 +62,12 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc43_usb0.h"
+#include "hardware/lpc43_usb0.h"
 #include "up_arch.h"
 
 #include "lpc43_cgu.h"
-#include "chip/lpc43_creg.h"
-#include "chip/lpc43_evntrtr.h"
+#include "hardware/lpc43_creg.h"
+#include "hardware/lpc43_evntrtr.h"
 
 #if defined(CONFIG_LPC43_USBOTG) && defined(CONFIG_USBHOST)
 
diff --git a/arch/arm/src/lpc43xx/lpc43_emc.c b/arch/arm/src/lpc43xx/lpc43_emc.c
index a15ecb5610d..17273a5b5dc 100644
--- a/arch/arm/src/lpc43xx/lpc43_emc.c
+++ b/arch/arm/src/lpc43xx/lpc43_emc.c
@@ -30,9 +30,9 @@
 #include "chip.h"
 #include "lpc43_pinconfig.h"
 #include "lpc43_emc.h"
-#include "chip/lpc43_creg.h"
-#include "chip/lpc43_cgu.h"
-#include "chip/lpc43_ccu.h"
+#include "hardware/lpc43_creg.h"
+#include "hardware/lpc43_cgu.h"
+#include "hardware/lpc43_ccu.h"
 #include "lpc43_rgu.h"
 #include "lpc43_gpio.h"
 #include "up_arch.h"
diff --git a/arch/arm/src/lpc43xx/lpc43_emc.h b/arch/arm/src/lpc43xx/lpc43_emc.h
index 77b71d86120..576106b82bf 100644
--- a/arch/arm/src/lpc43xx/lpc43_emc.h
+++ b/arch/arm/src/lpc43xx/lpc43_emc.h
@@ -42,7 +42,7 @@
 
 #include 
 #include "chip.h"
-#include "chip/lpc43_emc.h"
+#include "hardware/lpc43_emc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c
index befb76174fd..d9f845ad859 100644
--- a/arch/arm/src/lpc43xx/lpc43_ethernet.c
+++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c
@@ -66,9 +66,9 @@
 #include "chip.h"
 #include "lpc43_pinconfig.h"
 #include "lpc43_ethernet.h"
-#include "chip/lpc43_creg.h"
-#include "chip/lpc43_cgu.h"
-#include "chip/lpc43_ccu.h"
+#include "hardware/lpc43_creg.h"
+#include "hardware/lpc43_cgu.h"
+#include "hardware/lpc43_ccu.h"
 #include "lpc43_rgu.h"
 #include "lpc43_gpio.h"
 #include "up_arch.h"
diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.h b/arch/arm/src/lpc43xx/lpc43_ethernet.h
index ca27e1739f8..010203f7e24 100644
--- a/arch/arm/src/lpc43xx/lpc43_ethernet.h
+++ b/arch/arm/src/lpc43xx/lpc43_ethernet.h
@@ -44,7 +44,7 @@
 
 #include "chip.h"
 
-#include "chip/lpc43_ethernet.h"
+#include "hardware/lpc43_ethernet.h"
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/src/lpc43xx/lpc43_gpdma.h b/arch/arm/src/lpc43xx/lpc43_gpdma.h
index d40e303f7a6..388e92367b1 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpdma.h
+++ b/arch/arm/src/lpc43xx/lpc43_gpdma.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/lpc43_gpdma.h"
+#include "hardware/lpc43_gpdma.h"
 
 #ifdef CONFIG_LPC43_GPDMA
 
diff --git a/arch/arm/src/lpc43xx/lpc43_gpio.h b/arch/arm/src/lpc43xx/lpc43_gpio.h
index 24a492beaed..cfc29adf96a 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpio.h
+++ b/arch/arm/src/lpc43xx/lpc43_gpio.h
@@ -46,7 +46,7 @@
 /* Include the chip capabilities and GPIO definitions file */
 
 #include "chip.h"
-#include "chip/lpc43_gpio.h"
+#include "hardware/lpc43_gpio.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc43xx/lpc43_gpioint.c b/arch/arm/src/lpc43xx/lpc43_gpioint.c
index e8726420c15..f7a9cbf4178 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpioint.c
+++ b/arch/arm/src/lpc43xx/lpc43_gpioint.c
@@ -66,8 +66,8 @@
 
 #include "up_arch.h"
 #include "chip.h"
-#include "chip/lpc43_scu.h"
-#include "chip/lpc43_gpio.h"
+#include "hardware/lpc43_scu.h"
+#include "hardware/lpc43_gpio.h"
 #include "lpc43_gpio.h"
 #include "lpc43_gpioint.h"
 
diff --git a/arch/arm/src/lpc43xx/lpc43_gpioint.h b/arch/arm/src/lpc43xx/lpc43_gpioint.h
index ae479f83c67..64ef43b222c 100644
--- a/arch/arm/src/lpc43xx/lpc43_gpioint.h
+++ b/arch/arm/src/lpc43xx/lpc43_gpioint.h
@@ -59,7 +59,7 @@
 
 #include 
 #include "chip.h"
-#include "chip/lpc43_gpio.h"
+#include "hardware/lpc43_gpio.h"
 
 #ifdef CONFIG_LPC43_GPIO_IRQ
 
diff --git a/arch/arm/src/lpc43xx/lpc43_i2c.h b/arch/arm/src/lpc43xx/lpc43_i2c.h
index 224fbaa593e..ec5b50679bb 100644
--- a/arch/arm/src/lpc43xx/lpc43_i2c.h
+++ b/arch/arm/src/lpc43xx/lpc43_i2c.h
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/lpc43_i2c.h"
+#include "hardware/lpc43_i2c.h"
 
 /****************************************************************************
  * Public Function Prototypes
diff --git a/arch/arm/src/lpc43xx/lpc43_pinconfig.h b/arch/arm/src/lpc43xx/lpc43_pinconfig.h
index 6b82878981a..7ba22670b0f 100644
--- a/arch/arm/src/lpc43xx/lpc43_pinconfig.h
+++ b/arch/arm/src/lpc43xx/lpc43_pinconfig.h
@@ -45,7 +45,7 @@
 /* Include the chip capabilities and SCU definitions file */
 
 #include "chip.h"
-#include "chip/lpc43_scu.h"
+#include "hardware/lpc43_scu.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc43xx/lpc43_rgu.h b/arch/arm/src/lpc43xx/lpc43_rgu.h
index f283a9aaf36..e1474e4bd25 100644
--- a/arch/arm/src/lpc43xx/lpc43_rgu.h
+++ b/arch/arm/src/lpc43xx/lpc43_rgu.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/lpc43_rgu.h"
+#include "hardware/lpc43_rgu.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc43xx/lpc43_rit.c b/arch/arm/src/lpc43xx/lpc43_rit.c
index b538cbbf0e1..f8324c069cf 100644
--- a/arch/arm/src/lpc43xx/lpc43_rit.c
+++ b/arch/arm/src/lpc43xx/lpc43_rit.c
@@ -55,7 +55,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/lpc43_rit.h"
+#include "hardware/lpc43_rit.h"
 #include "lpc43_rit.h"
 
 #ifdef CONFIG_LPC43_RIT
diff --git a/arch/arm/src/lpc43xx/lpc43_rtc.c b/arch/arm/src/lpc43xx/lpc43_rtc.c
index 9afc1529779..291ba8420e3 100644
--- a/arch/arm/src/lpc43xx/lpc43_rtc.c
+++ b/arch/arm/src/lpc43xx/lpc43_rtc.c
@@ -54,8 +54,8 @@
 #include "up_arch.h"
 #include "up_internal.h"
 #include "chip.h"
-#include "chip/lpc43_creg.h"
-#include "chip/lpc43_rtc.h"
+#include "hardware/lpc43_creg.h"
+#include "hardware/lpc43_rtc.h"
 #include "lpc43_rtc.h"
 
 #ifdef CONFIG_RTC
diff --git a/arch/arm/src/lpc43xx/lpc43_scu.h b/arch/arm/src/lpc43xx/lpc43_scu.h
index 4345a026088..108b38bf31e 100644
--- a/arch/arm/src/lpc43xx/lpc43_scu.h
+++ b/arch/arm/src/lpc43xx/lpc43_scu.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/lpc43_scu.h"
+#include "hardware/lpc43_scu.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc43xx/lpc43_sdmmc.c b/arch/arm/src/lpc43xx/lpc43_sdmmc.c
index c7a748f3f4e..3b86cdb3900 100644
--- a/arch/arm/src/lpc43xx/lpc43_sdmmc.c
+++ b/arch/arm/src/lpc43xx/lpc43_sdmmc.c
@@ -65,7 +65,7 @@
 
 #include "up_arch.h"
 
-#include "chip/lpc43_pinconfig.h"
+#include "hardware/lpc43_pinconfig.h"
 #include "lpc43_cgu.h"
 #include "lpc43_ccu.h"
 #include "lpc43_gpio.h"
diff --git a/arch/arm/src/lpc43xx/lpc43_sdmmc.h b/arch/arm/src/lpc43xx/lpc43_sdmmc.h
index 449ee0f7a50..81f061b7b19 100644
--- a/arch/arm/src/lpc43xx/lpc43_sdmmc.h
+++ b/arch/arm/src/lpc43xx/lpc43_sdmmc.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc43_sdmmc.h"
+#include "hardware/lpc43_sdmmc.h"
 
 /************************************************************************************
  * Public Functions
diff --git a/arch/arm/src/lpc43xx/lpc43_spi.h b/arch/arm/src/lpc43xx/lpc43_spi.h
index b642f9c4908..3be397df872 100644
--- a/arch/arm/src/lpc43xx/lpc43_spi.h
+++ b/arch/arm/src/lpc43xx/lpc43_spi.h
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/lpc43_spi.h"
+#include "hardware/lpc43_spi.h"
 
 #ifdef CONFIG_LPC43_SPI
 
diff --git a/arch/arm/src/lpc43xx/lpc43_spifi.h b/arch/arm/src/lpc43xx/lpc43_spifi.h
index 30f85b83282..a016d16f1d0 100644
--- a/arch/arm/src/lpc43xx/lpc43_spifi.h
+++ b/arch/arm/src/lpc43xx/lpc43_spifi.h
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc43_spifi.h"
+#include "hardware/lpc43_spifi.h"
 
 #ifdef CONFIG_LPC43_SPIFI
 
diff --git a/arch/arm/src/lpc43xx/lpc43_ssp.h b/arch/arm/src/lpc43xx/lpc43_ssp.h
index 27be5a5130b..8cddd3cdbb0 100644
--- a/arch/arm/src/lpc43xx/lpc43_ssp.h
+++ b/arch/arm/src/lpc43xx/lpc43_ssp.h
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/lpc43_ssp.h"
+#include "hardware/lpc43_ssp.h"
 
 #if defined(CONFIG_LPC43_SSP0) || defined(CONFIG_LPC43_SSP1)
 
diff --git a/arch/arm/src/lpc43xx/lpc43_start.c b/arch/arm/src/lpc43xx/lpc43_start.c
index 91ab197e97c..5d00f476887 100644
--- a/arch/arm/src/lpc43xx/lpc43_start.c
+++ b/arch/arm/src/lpc43xx/lpc43_start.c
@@ -66,7 +66,7 @@
 #include "up_internal.h"
 #include "nvic.h"
 
-#include "chip/lpc43_creg.h"
+#include "hardware/lpc43_creg.h"
 
 #include "lpc43_rgu.h"
 #include "lpc43_cgu.h"
diff --git a/arch/arm/src/lpc43xx/lpc43_tickless_rit.c b/arch/arm/src/lpc43xx/lpc43_tickless_rit.c
index 17f657ee876..f55dbbf32a8 100644
--- a/arch/arm/src/lpc43xx/lpc43_tickless_rit.c
+++ b/arch/arm/src/lpc43xx/lpc43_tickless_rit.c
@@ -56,7 +56,7 @@
 
 #include "up_arch.h"
 #include "chip.h"
-#include "chip/lpc43_rit.h"
+#include "hardware/lpc43_rit.h"
 
 #ifdef CONFIG_SCHED_TICKLESS
 
diff --git a/arch/arm/src/lpc43xx/lpc43_timer.h b/arch/arm/src/lpc43xx/lpc43_timer.h
index 7eed9b2dcd3..1224d29c5b5 100644
--- a/arch/arm/src/lpc43xx/lpc43_timer.h
+++ b/arch/arm/src/lpc43xx/lpc43_timer.h
@@ -44,8 +44,8 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc43_timer.h"
-#include "chip/lpc43_ccu.h"
+#include "hardware/lpc43_timer.h"
+#include "hardware/lpc43_ccu.h"
 
 #ifdef CONFIG_TIMER
 
diff --git a/arch/arm/src/lpc43xx/lpc43_uart.h b/arch/arm/src/lpc43xx/lpc43_uart.h
index b34efd73284..c8bc53196a9 100644
--- a/arch/arm/src/lpc43xx/lpc43_uart.h
+++ b/arch/arm/src/lpc43xx/lpc43_uart.h
@@ -42,7 +42,7 @@
 
 #include 
 #include "chip.h"
-#include "chip/lpc43_uart.h"
+#include "hardware/lpc43_uart.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.h b/arch/arm/src/lpc43xx/lpc43_usb0dev.h
index d9416320134..d145b380300 100644
--- a/arch/arm/src/lpc43xx/lpc43_usb0dev.h
+++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc43_usb0.h"
+#include "hardware/lpc43_usb0.h"
 
 /************************************************************************************
  * Public Functions
diff --git a/arch/arm/src/lpc43xx/lpc43_wdt.h b/arch/arm/src/lpc43xx/lpc43_wdt.h
index b006071db59..9255a8555e9 100644
--- a/arch/arm/src/lpc43xx/lpc43_wdt.h
+++ b/arch/arm/src/lpc43xx/lpc43_wdt.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc43_wwdt.h"
+#include "hardware/lpc43_wwdt.h"
 
 #ifdef CONFIG_WATCHDOG
 
diff --git a/arch/arm/src/lpc43xx/lpc43_wwdt.c b/arch/arm/src/lpc43xx/lpc43_wwdt.c
index 785be62145a..9e4414a9503 100644
--- a/arch/arm/src/lpc43xx/lpc43_wwdt.c
+++ b/arch/arm/src/lpc43xx/lpc43_wwdt.c
@@ -50,7 +50,7 @@
 
 #include "up_arch.h"
 #include "lpc43_wdt.h"
-#include "chip/lpc43_wwdt.h"
+#include "hardware/lpc43_wwdt.h"
 
 #if defined(CONFIG_WATCHDOG) && defined(CONFIG_LPC43_WWDT)
 
diff --git a/arch/arm/src/lpc54xx/Kconfig b/arch/arm/src/lpc54xx/Kconfig
index 5b401813608..2bec112e098 100644
--- a/arch/arm/src/lpc54xx/Kconfig
+++ b/arch/arm/src/lpc54xx/Kconfig
@@ -401,6 +401,12 @@ config LPC54_EMC
 	bool "External Memory Controller (EMC)"
 	default n
 
+config LPC54_OHCI
+	bool "USB0 OHCI"
+	select USBHOST
+	select USBHOST_HAVE_ASYNCH
+	default n
+
 config LPC54_ETHERNET
 	bool "Ethernet"
 	default n
@@ -686,6 +692,65 @@ config LPC54_SPI_WIDEDATA
 
 endmenu # SPI Master configuration
 
+menu "USB0 OHCI Options"
+	depends on LPC54_OHCI
+
+config LPC54_OHCI_NEDS
+	int "Number of Endpoint Descriptors"
+	default 2
+	---help---
+		Number of endpoint descriptors.  Default: 2
+
+config LPC54_OHCI_NTDS
+	int "Number of transfer descriptors"
+	default 3
+	---help---
+		Number of transfer descriptors. Default: 3
+
+config LPC54_OHCI_TDBUFFERS
+	int "Number of descriptor buffers"
+	default 2
+	---help---
+		Number of transfer descriptor buffers.  Default: 2
+
+config LPC54_OHCI_TDBUFSIZE
+	int "Descriptor buffer size"
+	default 128
+	---help---
+		Size of one transfer descriptor buffer.  Default 128
+
+config LPC54_OHCI_IOBUFSIZE
+	int "I/O buffer size"
+	default 512
+	---help---
+		Size of one end-user I/O buffer.
+
+config LPC54_OHCI_NIOBUFFERS
+	int "Number of I/O buffer"
+	default 8 if USBHOST_HUB
+	default 4 if !USBHOST_HUB
+	---help---
+		Size of one end-user I/O buffer.
+
+config LPC54_OHCI_NPREALLOC
+	int "Max concurrent transfers"
+	default 8 if USBHOST_HUB
+	default 4 if !USBHOST_HUB
+	---help---
+		This number represents a number of pre-allocated structures to support
+		concurrent data transfers.  This number limits that number of concurrent
+		asynchronous IN endpoint transfer that can be supported.
+
+config LPC54_OHCI_REGDEBUG
+	bool "Register level debug"
+	depends on DEBUG_USB_INFO
+	default n
+	---help---
+		Output detailed register-level USB host debug information.  Requires
+		also CONFIG_DEBUG_USB_INFO.
+
+endmenu
+
 menu "Ethernet configuration"
 	depends on LPC54_ETHERNET
 
diff --git a/arch/arm/src/lpc54xx/Make.defs b/arch/arm/src/lpc54xx/Make.defs
index 2957790ba00..04fe4b1d4fb 100644
--- a/arch/arm/src/lpc54xx/Make.defs
+++ b/arch/arm/src/lpc54xx/Make.defs
@@ -60,11 +60,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
diff --git a/arch/arm/src/lpc54xx/chip.h b/arch/arm/src/lpc54xx/chip.h
index 9e67179d0da..e4ebd9c9e45 100644
--- a/arch/arm/src/lpc54xx/chip.h
+++ b/arch/arm/src/lpc54xx/chip.h
@@ -48,7 +48,7 @@
 
 #include 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /* The common ARMv7-M vector handling logic expects the following definition in this
  * file.  ARMV7M_PERIPHERAL_INTERRUPTS provides the number of supported external
diff --git a/arch/arm/src/lpc54xx/chip/lpc546x_memorymap.h b/arch/arm/src/lpc54xx/hardware/lpc546x_memorymap.h
similarity index 97%
rename from arch/arm/src/lpc54xx/chip/lpc546x_memorymap.h
rename to arch/arm/src/lpc54xx/hardware/lpc546x_memorymap.h
index c6878580f8c..bfc7f1a7984 100644
--- a/arch/arm/src/lpc54xx/chip/lpc546x_memorymap.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc546x_memorymap.h
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC546X_MEMORYMAP_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC546X_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC546X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC546X_MEMORYMAP_H
 
 /****************************************************************************************************
  * Included Files
@@ -141,5 +141,5 @@
 #define LPC54_CTIMER3_BASE   0x40048000  /* CTIMER3 */
 #define LPC54_CTIMER4_BASE   0x40049000  /* CTIMER4 */
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC546X_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC546X_MEMORYMAP_H */
 
diff --git a/arch/arm/src/lpc54xx/chip/lpc546x_pinmux.h b/arch/arm/src/lpc54xx/hardware/lpc546x_pinmux.h
similarity index 99%
rename from arch/arm/src/lpc54xx/chip/lpc546x_pinmux.h
rename to arch/arm/src/lpc54xx/hardware/lpc546x_pinmux.h
index 5bfb7c66e13..f8cfc4c093c 100644
--- a/arch/arm/src/lpc54xx/chip/lpc546x_pinmux.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc546x_pinmux.h
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC546X_PINMUX_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC546X_PINMUX_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC546X_PINMUX_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC546X_PINMUX_H
 
 /************************************************************************************
  * Included Files
@@ -55,7 +55,7 @@
  *
  * #define GPIO_CAN0_RD GPIO_CAN0_RD_1
  *
- * The driver will then automatically configre P0.4 as the CAN0 RX pin.
+ * The driver will then automatically configure P0.4 as the CAN0 RX pin.
  *
  * All pins are Type D unless otherwise noted.
  */
@@ -904,4 +904,4 @@
 #define GPIO_UTICK_CAP3_3            (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN23) /* Type D+I */
 #define GPIO_UTICK_CAP3_5            (GPIO_ALT5 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN10)
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC546X_PINMUX_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC546X_PINMUX_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_dma.h b/arch/arm/src/lpc54xx/hardware/lpc54_dma.h
similarity index 98%
rename from arch/arm/src/lpc54xx/chip/lpc54_dma.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_dma.h
index f79b531f881..e11d28053f8 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_dma.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_dma.h
@@ -33,15 +33,15 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_DMA_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_DMA_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_DMA_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_DMA_H
 
 /********************************************************************************************
  * Included Files
  ********************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -275,4 +275,4 @@ struct lpc54_dmachan_desc_s
   uint32_t link;      /* Link to next descriptor */
 };
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_DMA_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_DMA_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_emc.h b/arch/arm/src/lpc54xx/hardware/lpc54_emc.h
similarity index 99%
rename from arch/arm/src/lpc54xx/chip/lpc54_emc.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_emc.h
index 9a722b86b2d..f2b21af8340 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_emc.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_emc.h
@@ -33,15 +33,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_EMC_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_EMC_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_EMC_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_EMC_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -340,4 +340,4 @@
 #define EMC_STATWAITTURN_MASK             (15 << EMC_STATWAITTURN_SHIFT)
 #  define EMC_STATWAITTURN(n)             ((uint32_t)((n)-1) << EMC_STATWAITTURN_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_EMC_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_EMC_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_ethernet.h b/arch/arm/src/lpc54xx/hardware/lpc54_ethernet.h
similarity index 99%
rename from arch/arm/src/lpc54xx/chip/lpc54_ethernet.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_ethernet.h
index a30cc0d6d72..7fb297e2b3f 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_ethernet.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_ethernet.h
@@ -33,15 +33,15 @@
  *
  ************************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_ETHERNET_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_ETHERNET_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_ETHERNET_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_ETHERNET_H
 
 /************************************************************************************************************
  * Included Files
  ************************************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /************************************************************************************************************
  * Pre-processor Definitions
@@ -863,4 +863,4 @@ struct enet_txdesc_s
   uint32_t ctrlstat;  /* TDES3 Control and status word */
 };
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_ETHERNET_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_ETHERNET_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_flexcomm.h b/arch/arm/src/lpc54xx/hardware/lpc54_flexcomm.h
similarity index 96%
rename from arch/arm/src/lpc54xx/chip/lpc54_flexcomm.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_flexcomm.h
index e1c5badc150..5e2045a63b3 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_flexcomm.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_flexcomm.h
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_FLEXCOMM_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_FLEXCOMM_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_FLEXCOMM_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_FLEXCOMM_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -113,4 +113,4 @@
 #define FLEXCOMM_PID_ID_SHIFT          (16)      /* Bits 15-31: Module ID for selected function */
 #define FLEXCOMM_PID_ID_MASK           (0xffff << FLEXCOMM_PID_ID_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_FLEXCOMM_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_FLEXCOMM_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_gint.h b/arch/arm/src/lpc54xx/hardware/lpc54_gint.h
similarity index 95%
rename from arch/arm/src/lpc54xx/chip/lpc54_gint.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_gint.h
index f0eb80db55d..abc8dd8dc94 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_gint.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_gint.h
@@ -33,15 +33,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GINT_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GINT_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_GINT_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_GINT_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -87,4 +87,4 @@
 #define GINT_PORT_ENA0(n)              (1 << (n)) /* Enable port0 pin for group interrupt */
 #define GINT_PORT_ENA1(n)              (1 << (n)) /* Enable port1 pin for group interrupt */
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GINT_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_GINT_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_gpio.h b/arch/arm/src/lpc54xx/hardware/lpc54_gpio.h
similarity index 96%
rename from arch/arm/src/lpc54xx/chip/lpc54_gpio.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_gpio.h
index f9fbcc2a2bd..745c54a8bfa 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_gpio.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_gpio.h
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GPIO_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GPIO_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_GPIO_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -105,4 +105,4 @@
 
 #define GPIO_PORT_BIT(n)            (1 << ((n) & 31))
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_GPIO_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_GPIO_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_i2c.h b/arch/arm/src/lpc54xx/hardware/lpc54_i2c.h
similarity index 99%
rename from arch/arm/src/lpc54xx/chip/lpc54_i2c.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_i2c.h
index 871f7959bc5..01178d2d2b8 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_i2c.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_i2c.h
@@ -33,15 +33,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_I2C_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_I2C_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_I2C_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_I2C_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -415,4 +415,4 @@
 /* I2C module Identification */
 #define I2C_ID_
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_I2C_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_I2C_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_inputmux.h b/arch/arm/src/lpc54xx/hardware/lpc54_inputmux.h
similarity index 99%
rename from arch/arm/src/lpc54xx/chip/lpc54_inputmux.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_inputmux.h
index c90250e9c53..e6a71093814 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_inputmux.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_inputmux.h
@@ -33,15 +33,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_INPUTMUX_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_INPUTMUX_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_INPUTMUX_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_INPUTMUX_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -295,4 +295,4 @@
 #  define MUX_FREQMEAS_TARGET_GPIOCLKA      (6 << MUX_FREQMEAS_TARGET_SHIFT) /* FREQME_GPIO_CLK_A */
 #  define MUX_FREQMEAS_TARGET_ PIOCLKB      (7 << MUX_FREQMEAS_TARGET_SHIFT) /* FREQME_GPIO_CLK_B */
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_INPUTMUX_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_INPUTMUX_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_iocon.h b/arch/arm/src/lpc54xx/hardware/lpc54_iocon.h
similarity index 99%
rename from arch/arm/src/lpc54xx/chip/lpc54_iocon.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_iocon.h
index 4a04936ffa1..e57fc6e7a5c 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_iocon.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_iocon.h
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC548X_IOCON_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC548X_IOCON_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC548X_IOCON_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC548X_IOCON_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -375,4 +375,4 @@
 #define IOCON_PIO4_TYPEA_MASK (0x00000000) /* None */
 #define IOCON_PIO5_TYPEA_MASK (0x00000000) /* None */
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC548X_IOCON_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC548X_IOCON_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_lcd.h b/arch/arm/src/lpc54xx/hardware/lpc54_lcd.h
similarity index 99%
rename from arch/arm/src/lpc54xx/chip/lpc54_lcd.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_lcd.h
index 57df5902690..e7373663928 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_lcd.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_lcd.h
@@ -33,15 +33,15 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_LCD_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_LCD_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_LCD_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_LCD_H
 
 /************************************************************************************************
  * Included Files
  ************************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /************************************************************************************************
  * Pre-processor Definitions
@@ -332,4 +332,4 @@
 #define LCD_CRSR_INTSTAT_CRSRMIS        (1 << 0)  /* Bit 0: Cursor mask interrupt status */
                                                   /* Bits 1-31: Reserved */
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_LCD_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_LCD_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_memorymap.h b/arch/arm/src/lpc54xx/hardware/lpc54_memorymap.h
similarity index 90%
rename from arch/arm/src/lpc54xx/chip/lpc54_memorymap.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_memorymap.h
index 42c7f82cfd4..7f7b9e27bcd 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_memorymap.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_memorymap.h
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_MEMORYMAP_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_MEMORYMAP_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -43,10 +43,10 @@
 #include 
 
 #if defined(CONFIG_ARCH_FAMILY_LPC546XX)
-#  include "chip/lpc546x_memorymap.h"
+#  include "hardware/lpc546x_memorymap.h"
 #else
 #  error "Unsupported LPC54 family"
 #endif
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_MEMORYMAP_H */
 
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_pinmux.h b/arch/arm/src/lpc54xx/hardware/lpc54_pinmux.h
similarity index 91%
rename from arch/arm/src/lpc54xx/chip/lpc54_pinmux.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_pinmux.h
index de259f200ed..493ff1dfee1 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_pinmux.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_pinmux.h
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINMUX_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINMUX_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_PINMUX_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_PINMUX_H
 
 /************************************************************************************
  * Included Files
@@ -44,10 +44,10 @@
 #include "lpc54_gpio.h"
 
 #if defined(CONFIG_ARCH_FAMILY_LPC546XX)
-#  include "chip/lpc546x_pinmux.h"
+#  include "hardware/lpc546x_pinmux.h"
 #else
 #  error "Unsupported LPC54 family"
 #endif
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINMUX_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_PINMUX_H */
 
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_pint.h b/arch/arm/src/lpc54xx/hardware/lpc54_pint.h
similarity index 98%
rename from arch/arm/src/lpc54xx/chip/lpc54_pint.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_pint.h
index 6e0f03501c3..8131f453970 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_pint.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_pint.h
@@ -33,15 +33,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINT_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINT_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_PINT_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_PINT_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -197,4 +197,4 @@
 #define PINT_PMCFG_CFG7_MASK      (7 << PINT_PMCFG_CFG7_SHIFT)
 #  define PINT_PMCFG_CFG7(n)      ((uint32_t)(n) << PINT_PMCFG_CFG7_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_PINT_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_PINT_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_rit.h b/arch/arm/src/lpc54xx/hardware/lpc54_rit.h
similarity index 95%
rename from arch/arm/src/lpc54xx/chip/lpc54_rit.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_rit.h
index 9c63be06ad8..5afda9c3e02 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_rit.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_rit.h
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_RIT_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_RIT_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_RIT_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_RIT_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -84,4 +84,4 @@
 /* LS 48-bit counter (Bits 0-31: 48-bit up counter) */
 /* MS 48-bit counter (Bits 32-47: 48-bit up counter) */
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_RIT_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_RIT_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_rom.h b/arch/arm/src/lpc54xx/hardware/lpc54_rom.h
similarity index 96%
rename from arch/arm/src/lpc54xx/chip/lpc54_rom.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_rom.h
index 32f5a32c610..698c8b876d2 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_rom.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_rom.h
@@ -33,15 +33,15 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_ROM_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_ROM_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_ROM_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_ROM_H
 
 /********************************************************************************************
  * Included Files
  ********************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -110,4 +110,4 @@ typedef CODE unsigned int (*rng_read_t)(void);
 
 #define LPC54_RNG_READ ((rng_read_t)(lpc54_otg_vtable[LPC54_OTP_API_RNGREAD_OFFSET >> 2]))
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_ROM_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_ROM_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_rtc.h b/arch/arm/src/lpc54xx/hardware/lpc54_rtc.h
similarity index 95%
rename from arch/arm/src/lpc54xx/chip/lpc54_rtc.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_rtc.h
index 5a6f730cdd5..958dcab27f0 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_rtc.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_rtc.h
@@ -33,15 +33,15 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_RTC_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_RTC_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_RTC_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_RTC_H
 
 /********************************************************************************************
  * Included Files
  ********************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -93,4 +93,4 @@
 
 /* General purpose registers (32-bit value) */
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_RTC_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_RTC_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_sdmmc.h b/arch/arm/src/lpc54xx/hardware/lpc54_sdmmc.h
similarity index 99%
rename from arch/arm/src/lpc54xx/chip/lpc54_sdmmc.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_sdmmc.h
index 9c94ef728f0..4dd2844a7f0 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_sdmmc.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_sdmmc.h
@@ -33,15 +33,15 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SDMMC_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SDMMC_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_SDMMC_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_SDMMC_H
 
 /************************************************************************************************
  * Included Files
  ************************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /************************************************************************************************
  * Pre-processor Definitions
@@ -398,4 +398,4 @@
 
 #define SDMMC_BACKENDPWRL                 (1 << 0)  /* Bit 0: Back-end Power control for card application. */
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SDMMC_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_SDMMC_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_spi.h b/arch/arm/src/lpc54xx/hardware/lpc54_spi.h
similarity index 99%
rename from arch/arm/src/lpc54xx/chip/lpc54_spi.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_spi.h
index 21071fbb371..4a4a7da42f7 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_spi.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_spi.h
@@ -33,15 +33,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SPI_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SPI_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_SPI_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_SPI_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -402,4 +402,4 @@
 #define SPI_ID_ID_SHIFT               (15)      /* Bits 16-31: Unique module identifier for this IP block */
 #define SPI_ID_ID_MASK                (0xffff << SPI_ID_ID_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SPI_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_SPI_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_syscon.h b/arch/arm/src/lpc54xx/hardware/lpc54_syscon.h
similarity index 99%
rename from arch/arm/src/lpc54xx/chip/lpc54_syscon.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_syscon.h
index 43e366139ac..a7e3ebb8567 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_syscon.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_syscon.h
@@ -33,15 +33,15 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SYSCON_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SYSCON_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_SYSCON_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_SYSCON_H
 
 /********************************************************************************************
  * Included Files
  ********************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -937,4 +937,4 @@
 /* Brown-Out Detect control */
 #define SYSCON_BODCTRL_
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SYSCON_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_SYSCON_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_usart.h b/arch/arm/src/lpc54xx/hardware/lpc54_usart.h
similarity index 99%
rename from arch/arm/src/lpc54xx/chip/lpc54_usart.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_usart.h
index 494f8d268f0..09b20875d3b 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_usart.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_usart.h
@@ -33,15 +33,15 @@
  *
  *****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_USART_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_USART_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_USART_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_USART_H
 
 /*****************************************************************************************************
  * Included Files
  *****************************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /*****************************************************************************************************
  * Pre-processor Definitions
@@ -417,4 +417,4 @@
 #define USART_ID_ID_SHIFT               (16)      /* Bits 16-31: ID Unique module identifier for this IP block */
 #define USART_ID_ID_MASKX               (0xffff << USART_ID_ID_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_USART_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_USART_H */
diff --git a/arch/arm/src/lpc54xx/hardware/lpc54_usb0_ohci.h b/arch/arm/src/lpc54xx/hardware/lpc54_usb0_ohci.h
new file mode 100644
index 00000000000..f2b28c39704
--- /dev/null
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_usb0_ohci.h
@@ -0,0 +1,129 @@
+/************************************************************************************
+ * arch/arm/src/lpc54xx/chip/lpc54_usb0_ohci.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_USB0_OHCI_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_USB0_OHCI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+#include 
+
+#include "chip.h"
+#include "hardware/lpc54_memorymap.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register offsets *****************************************************************/
+
+/* USB Host Controller (OHCI).  See include/nuttx/usb/ohci.h */
+
+/* Additional, non-standard register offsets */
+
+#define LPC54_OHCI_PORTMODE_OFFSET    0x005c /* Port mode register */
+
+/* Register addresses ***************************************************************/
+
+/* USB Host Controller (OHCI) */
+
+/* Control and status registers (section 7.1) */
+
+#define LPC54_OHCI_HCIREV             (LPC54_FSUSBHOST_BASE + OHCI_HCIREV_OFFSET)
+#define LPC54_OHCI_CTRL               (LPC54_FSUSBHOST_BASE + OHCI_CTRL_OFFSET)
+#define LPC54_OHCI_CMDST              (LPC54_FSUSBHOST_BASE + OHCI_CMDST_OFFSET)
+#define LPC54_OHCI_INTST              (LPC54_FSUSBHOST_BASE + OHCI_INTST_OFFSET)
+#define LPC54_OHCI_INTEN              (LPC54_FSUSBHOST_BASE + OHCI_INTEN_OFFSET)
+#define LPC54_OHCI_INTDIS             (LPC54_FSUSBHOST_BASE + OHCI_INTDIS_OFFSET)
+
+/* Memory pointers (section 7.2) */
+
+#define LPC54_OHCI_HCCA               (LPC54_FSUSBHOST_BASE + OHCI_HCCA_OFFSET)
+#define LPC54_OHCI_PERED              (LPC54_FSUSBHOST_BASE + OHCI_PERED_OFFSET)
+#define LPC54_OHCI_CTRLHEADED         (LPC54_FSUSBHOST_BASE + OHCI_CTRLHEADED_OFFSET)
+#define LPC54_OHCI_CTRLED             (LPC54_FSUSBHOST_BASE + OHCI_CTRLED_OFFSET)
+#define LPC54_OHCI_BULKHEADED         (LPC54_FSUSBHOST_BASE + OHCI_BULKHEADED_OFFSET)
+#define LPC54_OHCI_BULKED             (LPC54_FSUSBHOST_BASE + OHCI_BULKED_OFFSET)
+#define LPC54_OHCI_DONEHEAD           (LPC54_FSUSBHOST_BASE + OHCI_DONEHEAD_OFFSET)
+
+/* Frame counters (section 7.3) */
+
+#define LPC54_OHCI_FMINT              (LPC54_FSUSBHOST_BASE + OHCI_FMINT_OFFSET)
+#define LPC54_OHCI_FMREM              (LPC54_FSUSBHOST_BASE + OHCI_FMREM_OFFSET)
+#define LPC54_OHCI_FMNO               (LPC54_FSUSBHOST_BASE + OHCI_FMNO_OFFSET)
+#define LPC54_OHCI_PERSTART           (LPC54_FSUSBHOST_BASE + OHCI_PERSTART_OFFSET)
+
+/* Root hub ports (section 7.4) */
+
+#define LPC54_OHCI_LSTHRES            (LPC54_FSUSBHOST_BASE + OHCI_LSTHRES_OFFSET)
+#define LPC54_OHCI_RHDESCA            (LPC54_FSUSBHOST_BASE + OHCI_RHDESCA_OFFSET)
+#define LPC54_OHCI_RHDESCB            (LPC54_FSUSBHOST_BASE + OHCI_RHDESCB_OFFSET)
+#define LPC54_OHCI_RHSTATUS           (LPC54_FSUSBHOST_BASE + OHCI_RHSTATUS_OFFSET)
+#define LPC54_OHCI_RHPORTST1          (LPC54_FSUSBHOST_BASE + OHCI_RHPORTST1_OFFSET)
+#define LPC54_OHCI_RHPORTST2          (LPC54_FSUSBHOST_BASE + OHCI_RHPORTST2_OFFSET)
+
+/* Non-standard Registers */
+
+#define LPC54_OHCI_PORTMODE           (LPC54_FSUSBHOST_BASE + LPC54_OHCI_PORTMODE_OFFSET)
+
+/* Register bit definitions *********************************************************/
+
+/* USB Host Controller (OHCI). See include/nuttx/usb/ohci.h */
+
+/* Port mode register */
+
+#define OHCI_PORTMODE_ID              (1 << 0)  /* Bit 0:  Port ID pin value */
+                                                /* Bits 1-7: Reserved */
+#define OHCI_PORTMODE_IDEN            (1 << 8)  /* Bit 8:  Port ID pull-up enable */
+                                                /* Bits 9-15: Reserved */
+#define OHCI_PORTMODE_DEVENABLE       (1 << 16) /* Bit 16: Device mode enable */
+                                                /* Bits 17-31: Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_USB0_OHCI_H */
diff --git a/arch/arm/src/lpc54xx/chip/lpc54_wwdt.h b/arch/arm/src/lpc54xx/hardware/lpc54_wwdt.h
similarity index 96%
rename from arch/arm/src/lpc54xx/chip/lpc54_wwdt.h
rename to arch/arm/src/lpc54xx/hardware/lpc54_wwdt.h
index c292304d308..25c7525f80b 100644
--- a/arch/arm/src/lpc54xx/chip/lpc54_wwdt.h
+++ b/arch/arm/src/lpc54xx/hardware/lpc54_wwdt.h
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_WWDT_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_WWDT_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_WWDT_H
+#define __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_WWDT_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -98,4 +98,4 @@
 #define WWDT_WINDOW_MASK            0x00ffffff /* Bits 0-23: Watchdog window value */
                                                /* Bits 24-31: Reserved */
 
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_WWDT_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_HARDWARE_LPC54_WWDT_H */
diff --git a/arch/arm/src/lpc54xx/lpc546x_enableclk.h b/arch/arm/src/lpc54xx/lpc546x_enableclk.h
index 95e1d5bd18f..8d95aed5361 100644
--- a/arch/arm/src/lpc54xx/lpc546x_enableclk.h
+++ b/arch/arm/src/lpc54xx/lpc546x_enableclk.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "up_arch.h"
-#include 
+#include "hardware/lpc54_syscon.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc54xx/lpc546x_power.h b/arch/arm/src/lpc54xx/lpc546x_power.h
index 8bce39b6301..2a76cb5ec8e 100644
--- a/arch/arm/src/lpc54xx/lpc546x_power.h
+++ b/arch/arm/src/lpc54xx/lpc546x_power.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/lpc54_syscon.h"
+#include "hardware/lpc54_syscon.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc54xx/lpc546x_reset.h b/arch/arm/src/lpc54xx/lpc546x_reset.h
index 20ce44619b9..f00eb0fe611 100644
--- a/arch/arm/src/lpc54xx/lpc546x_reset.h
+++ b/arch/arm/src/lpc54xx/lpc546x_reset.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include 
+#include "hardware/lpc54_syscon.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc54xx/lpc54_allocateheap.c b/arch/arm/src/lpc54xx/lpc54_allocateheap.c
index cfd5a0719fe..d75660e8d1a 100644
--- a/arch/arm/src/lpc54xx/lpc54_allocateheap.c
+++ b/arch/arm/src/lpc54xx/lpc54_allocateheap.c
@@ -52,7 +52,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/lpc54_memorymap.h"
+#include "hardware/lpc54_memorymap.h"
 #include "lpc54_mpuinit.h"
 
 #include 
diff --git a/arch/arm/src/lpc54xx/lpc54_clockconfig.c b/arch/arm/src/lpc54xx/lpc54_clockconfig.c
index c513bd26edd..047742f00d2 100644
--- a/arch/arm/src/lpc54xx/lpc54_clockconfig.c
+++ b/arch/arm/src/lpc54xx/lpc54_clockconfig.c
@@ -55,7 +55,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/lpc54_syscon.h"
+#include "hardware/lpc54_syscon.h"
 #include "lpc54_power.h"
 #include "lpc54_clockconfig.h"
 
diff --git a/arch/arm/src/lpc54xx/lpc54_dma.c b/arch/arm/src/lpc54xx/lpc54_dma.c
index b21afdf436b..57f675e5016 100644
--- a/arch/arm/src/lpc54xx/lpc54_dma.c
+++ b/arch/arm/src/lpc54xx/lpc54_dma.c
@@ -50,8 +50,8 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/lpc54_inputmux.h"
-#include "chip/lpc54_dma.h"
+#include "hardware/lpc54_inputmux.h"
+#include "hardware/lpc54_dma.h"
 #include "lpc54_enableclk.h"
 #include "lpc54_reset.h"
 #include "lpc54_dma.h"
diff --git a/arch/arm/src/lpc54xx/lpc54_dma.h b/arch/arm/src/lpc54xx/lpc54_dma.h
index 36f938069df..b2a4de0969d 100644
--- a/arch/arm/src/lpc54xx/lpc54_dma.h
+++ b/arch/arm/src/lpc54xx/lpc54_dma.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/lpc54_dma.h"
+#include "hardware/lpc54_dma.h"
 
 #ifdef CONFIG_LPC54_DMA
 
diff --git a/arch/arm/src/lpc54xx/lpc54_emc.c b/arch/arm/src/lpc54xx/lpc54_emc.c
index 8c9ed357eca..08cd0efd310 100644
--- a/arch/arm/src/lpc54xx/lpc54_emc.c
+++ b/arch/arm/src/lpc54xx/lpc54_emc.c
@@ -52,8 +52,8 @@
 
 #include "up_arch.h"
 
-#include "chip/lpc54_syscon.h"
-#include "chip/lpc54_emc.h"
+#include "hardware/lpc54_syscon.h"
+#include "hardware/lpc54_emc.h"
 #include "lpc54_config.h"
 #include "lpc54_enableclk.h"
 #include "lpc54_reset.h"
diff --git a/arch/arm/src/lpc54xx/lpc54_ethernet.c b/arch/arm/src/lpc54xx/lpc54_ethernet.c
index 1f039902f19..bc453793538 100644
--- a/arch/arm/src/lpc54xx/lpc54_ethernet.c
+++ b/arch/arm/src/lpc54xx/lpc54_ethernet.c
@@ -88,9 +88,9 @@
 #endif
 
 #include "up_arch.h"
-#include "chip/lpc54_syscon.h"
-#include "chip/lpc54_pinmux.h"
-#include "chip/lpc54_ethernet.h"
+#include "hardware/lpc54_syscon.h"
+#include "hardware/lpc54_pinmux.h"
+#include "hardware/lpc54_ethernet.h"
 #include "lpc54_enableclk.h"
 #include "lpc54_reset.h"
 #include "lpc54_gpio.h"
diff --git a/arch/arm/src/lpc54xx/lpc54_gpio.c b/arch/arm/src/lpc54xx/lpc54_gpio.c
index b7794efcca9..192f3713862 100644
--- a/arch/arm/src/lpc54xx/lpc54_gpio.c
+++ b/arch/arm/src/lpc54xx/lpc54_gpio.c
@@ -48,8 +48,8 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/lpc54_iocon.h"
-#include "chip/lpc54_gpio.h"
+#include "hardware/lpc54_iocon.h"
+#include "hardware/lpc54_gpio.h"
 #include "lpc54_gpio.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/lpc54xx/lpc54_gpio.h b/arch/arm/src/lpc54xx/lpc54_gpio.h
index 8f44f82c86a..3c64a4012ca 100644
--- a/arch/arm/src/lpc54xx/lpc54_gpio.h
+++ b/arch/arm/src/lpc54xx/lpc54_gpio.h
@@ -49,8 +49,8 @@
 
 #include 
 
-#include "chip/lpc54_gpio.h"
-#include "chip/lpc54_iocon.h"
+#include "hardware/lpc54_gpio.h"
+#include "hardware/lpc54_iocon.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc54xx/lpc54_gpioirq.c b/arch/arm/src/lpc54xx/lpc54_gpioirq.c
index 8a0a9749c9c..edb51ae21f9 100644
--- a/arch/arm/src/lpc54xx/lpc54_gpioirq.c
+++ b/arch/arm/src/lpc54xx/lpc54_gpioirq.c
@@ -46,9 +46,9 @@
 
 #include "up_arch.h"
 
-#include "chip/lpc54_syscon.h"
-#include "chip/lpc54_inputmux.h"
-#include "chip/lpc54_pint.h"
+#include "hardware/lpc54_syscon.h"
+#include "hardware/lpc54_inputmux.h"
+#include "hardware/lpc54_pint.h"
 #include "lpc54_gpio.h"
 
 #ifdef CONFIG_LPC54_GPIOIRQ
diff --git a/arch/arm/src/lpc54xx/lpc54_i2c_master.c b/arch/arm/src/lpc54xx/lpc54_i2c_master.c
index 7de42790c64..a2fe53156ac 100644
--- a/arch/arm/src/lpc54xx/lpc54_i2c_master.c
+++ b/arch/arm/src/lpc54xx/lpc54_i2c_master.c
@@ -66,10 +66,10 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/lpc54_pinmux.h"
-#include "chip/lpc54_syscon.h"
-#include "chip/lpc54_flexcomm.h"
-#include "chip/lpc54_i2c.h"
+#include "hardware/lpc54_pinmux.h"
+#include "hardware/lpc54_syscon.h"
+#include "hardware/lpc54_flexcomm.h"
+#include "hardware/lpc54_i2c.h"
 #include "lpc54_config.h"
 #include "lpc54_clockconfig.h"
 #include "lpc54_enableclk.h"
diff --git a/arch/arm/src/lpc54xx/lpc54_i2c_master.h b/arch/arm/src/lpc54xx/lpc54_i2c_master.h
index fc9e80f662a..30e16f08a31 100644
--- a/arch/arm/src/lpc54xx/lpc54_i2c_master.h
+++ b/arch/arm/src/lpc54xx/lpc54_i2c_master.h
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/lpc54_i2c.h"
+#include "hardware/lpc54_i2c.h"
 
 /****************************************************************************
  * Public Function Prototypes
diff --git a/arch/arm/src/lpc54xx/lpc54_lcd.c b/arch/arm/src/lpc54xx/lpc54_lcd.c
index adc0a30e21b..9c6ef8d3761 100644
--- a/arch/arm/src/lpc54xx/lpc54_lcd.c
+++ b/arch/arm/src/lpc54xx/lpc54_lcd.c
@@ -50,8 +50,8 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/lpc54_syscon.h"
-#include "chip/lpc54_pinmux.h"
+#include "hardware/lpc54_syscon.h"
+#include "hardware/lpc54_pinmux.h"
 #include "lpc54_config.h"
 #include "lpc54_enableclk.h"
 #include "lpc54_gpio.h"
@@ -147,12 +147,12 @@ static const struct fb_planeinfo_s g_planeinfo =
 /* Current cursor position */
 
 #ifdef CONFIG_FB_HWCURSOR
-static struct cursor_pos_s g_cpos;
+static struct fb_cursorpos_s g_cpos;
 
 /* Current cursor size */
 
 #ifdef CONFIG_FB_HWCURSORSIZE
-static struct cursor_size_s g_csize;
+static struct fb_cursorsize_s g_csize;
 #endif
 #endif
 
diff --git a/arch/arm/src/lpc54xx/lpc54_lcd.h b/arch/arm/src/lpc54xx/lpc54_lcd.h
index 0ffb53ec813..c79929b6bb2 100644
--- a/arch/arm/src/lpc54xx/lpc54_lcd.h
+++ b/arch/arm/src/lpc54xx/lpc54_lcd.h
@@ -50,7 +50,7 @@
 
 #include 
 
-#include "chip/lpc54_lcd.h"
+#include "hardware/lpc54_lcd.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc54xx/lpc54_lowputc.c b/arch/arm/src/lpc54xx/lpc54_lowputc.c
index f6f41c96f11..d6c70127ae1 100644
--- a/arch/arm/src/lpc54xx/lpc54_lowputc.c
+++ b/arch/arm/src/lpc54xx/lpc54_lowputc.c
@@ -51,11 +51,11 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/lpc54_memorymap.h"
-#include "chip/lpc54_syscon.h"
-#include "chip/lpc54_flexcomm.h"
-#include "chip/lpc54_pinmux.h"
-#include "chip/lpc54_usart.h"
+#include "hardware/lpc54_memorymap.h"
+#include "hardware/lpc54_syscon.h"
+#include "hardware/lpc54_flexcomm.h"
+#include "hardware/lpc54_pinmux.h"
+#include "hardware/lpc54_usart.h"
 
 #include "lpc54_config.h"
 #include "lpc54_enableclk.h"
diff --git a/arch/arm/src/lpc54xx/lpc54_rng.c b/arch/arm/src/lpc54xx/lpc54_rng.c
index dfe9bace8e6..c61224d47d5 100644
--- a/arch/arm/src/lpc54xx/lpc54_rng.c
+++ b/arch/arm/src/lpc54xx/lpc54_rng.c
@@ -46,7 +46,7 @@
 #include 
 #include 
 
-#include "chip/lpc54_rom.h"
+#include "hardware/lpc54_rom.h"
 
 #if defined(CONFIG_LPC54_RNG)
 #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
@@ -79,10 +79,8 @@ static const struct file_operations g_rngops =
   lpc54_read,      /* read */
   NULL,            /* write */
   NULL,            /* seek */
-  NULL             /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL           /* poll */
-#endif
+  NULL,            /* ioctl */
+  NULL             /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL           /* unlink */
 #endif
diff --git a/arch/arm/src/lpc54xx/lpc54_rtc.c b/arch/arm/src/lpc54xx/lpc54_rtc.c
index ba23c2ad84f..90494c0edd2 100644
--- a/arch/arm/src/lpc54xx/lpc54_rtc.c
+++ b/arch/arm/src/lpc54xx/lpc54_rtc.c
@@ -54,7 +54,7 @@
 
 #include "up_arch.h"
 
-#include "chip/lpc54_rtc.h"
+#include "hardware/lpc54_rtc.h"
 #include "lpc54_enableclk.h"
 #include "lpc54_rtc.h"
 
diff --git a/arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c b/arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c
index 8ebaac9f867..beef333cd0d 100644
--- a/arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c
+++ b/arch/arm/src/lpc54xx/lpc54_rtc_lowerhalf.c
@@ -49,7 +49,7 @@
 
 #include "up_arch.h"
 
-#include "chip/lpc54_rtc.h"
+#include "hardware/lpc54_rtc.h"
 #include "lpc54_rtc.h"
 
 #ifdef CONFIG_RTC_DRIVER
diff --git a/arch/arm/src/lpc54xx/lpc54_sdmmc.c b/arch/arm/src/lpc54xx/lpc54_sdmmc.c
index 3b51f6a0e4e..e9564431eaf 100644
--- a/arch/arm/src/lpc54xx/lpc54_sdmmc.c
+++ b/arch/arm/src/lpc54xx/lpc54_sdmmc.c
@@ -69,8 +69,8 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/lpc54_pinmux.h"
-#include "chip/lpc54_syscon.h"
+#include "hardware/lpc54_pinmux.h"
+#include "hardware/lpc54_syscon.h"
 #include "lpc54_enableclk.h"
 #include "lpc54_gpio.h"
 #include "lpc54_sdmmc.h"
diff --git a/arch/arm/src/lpc54xx/lpc54_sdmmc.h b/arch/arm/src/lpc54xx/lpc54_sdmmc.h
index a56fe2095bc..a4e76b447b3 100644
--- a/arch/arm/src/lpc54xx/lpc54_sdmmc.h
+++ b/arch/arm/src/lpc54xx/lpc54_sdmmc.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc54_sdmmc.h"
+#include "hardware/lpc54_sdmmc.h"
 
 /************************************************************************************
  * Public Functions
diff --git a/arch/arm/src/lpc54xx/lpc54_serial.c b/arch/arm/src/lpc54xx/lpc54_serial.c
index 996affee4ca..1fc746dc97e 100644
--- a/arch/arm/src/lpc54xx/lpc54_serial.c
+++ b/arch/arm/src/lpc54xx/lpc54_serial.c
@@ -59,7 +59,7 @@
 
 #include "chip.h"
 #include "lpc54_config.h"
-#include "chip/lpc54_usart.h"
+#include "hardware/lpc54_usart.h"
 #include "lpc54_clockconfig.h"
 #include "lpc54_lowputc.h"
 #include "lpc54_serial.h"
diff --git a/arch/arm/src/lpc54xx/lpc54_spi_master.c b/arch/arm/src/lpc54xx/lpc54_spi_master.c
index 443bcb3333c..40ba2618e8d 100644
--- a/arch/arm/src/lpc54xx/lpc54_spi_master.c
+++ b/arch/arm/src/lpc54xx/lpc54_spi_master.c
@@ -63,10 +63,10 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/lpc54_pinmux.h"
-#include "chip/lpc54_syscon.h"
-#include "chip/lpc54_flexcomm.h"
-#include "chip/lpc54_spi.h"
+#include "hardware/lpc54_pinmux.h"
+#include "hardware/lpc54_syscon.h"
+#include "hardware/lpc54_flexcomm.h"
+#include "hardware/lpc54_spi.h"
 #include "lpc54_config.h"
 #include "lpc54_enableclk.h"
 #include "lpc54_gpio.h"
diff --git a/arch/arm/src/lpc54xx/lpc54_start.c b/arch/arm/src/lpc54xx/lpc54_start.c
index 89c818b1021..0506c71d1e8 100644
--- a/arch/arm/src/lpc54xx/lpc54_start.c
+++ b/arch/arm/src/lpc54xx/lpc54_start.c
@@ -47,7 +47,7 @@
 #include "up_internal.h"
 #include "nvic.h"
 
-#include "chip/lpc54_syscon.h"
+#include "hardware/lpc54_syscon.h"
 #include "lpc54_clockconfig.h"
 #include "lpc54_userspace.h"
 #include "lpc54_lowputc.h"
diff --git a/arch/arm/src/lpc54xx/lpc54_tickless.c b/arch/arm/src/lpc54xx/lpc54_tickless.c
index 69ef5d2f301..6d054f75937 100644
--- a/arch/arm/src/lpc54xx/lpc54_tickless.c
+++ b/arch/arm/src/lpc54xx/lpc54_tickless.c
@@ -51,7 +51,7 @@
 
 #include "up_arch.h"
 #include "chip.h"
-#include "chip/lpc54_rit.h"
+#include "hardware/lpc54_rit.h"
 
 #ifdef CONFIG_SCHED_TICKLESS
 
diff --git a/arch/arm/src/lpc54xx/lpc54_timerisr.c b/arch/arm/src/lpc54xx/lpc54_timerisr.c
index b6664ff0a9b..8035d3c3a91 100644
--- a/arch/arm/src/lpc54xx/lpc54_timerisr.c
+++ b/arch/arm/src/lpc54xx/lpc54_timerisr.c
@@ -51,7 +51,7 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/lpc54_syscon.h"
+#include "hardware/lpc54_syscon.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c b/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c
new file mode 100644
index 00000000000..0a0b8695219
--- /dev/null
+++ b/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c
@@ -0,0 +1,3995 @@
+/****************************************************************************
+ * arch/arm/src/lpc54xx/lpc54_usb0_ohci.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include  /* May redefine GPIO settings */
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "chip.h"
+#include "hardware/lpc54_usb.h"
+#include "hardware/lpc54_syscon.h"
+#include "lpc54_gpio.h"
+#include "lpc54_ohciram.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ***************************************************************/
+
+/* All I/O buffers must lie in AHB SRAM because of the OHCI DMA. It might be
+ * okay if no I/O buffers are used *IF* the application can guarantee that all
+ * end-user I/O buffers reside in AHB SRAM.
+ */
+
+#if LPC54_IOBUFFERS < 1
+#  warning "No IO buffers allocated"
+#endif
+
+#ifndef CONFIG_LPC54_OHCI_NPREALLOC
+#  define CONFIG_LPC54_OHCI_NPREALLOC 8
+#endif
+
+#ifndef CONFIG_DEBUG_USB_INFO
+#  undef CONFIG_LPC54_OHCI_REGDEBUG
+#endif
+
+/* OHCI Setup ******************************************************************/
+
+/* Frame Interval / Periodic Start */
+
+#define BITS_PER_FRAME          12000
+#define FI                     (BITS_PER_FRAME-1)
+#define FSMPS                  ((6 * (FI - 210)) / 7)
+#define DEFAULT_FMINTERVAL     ((FSMPS << OHCI_FMINT_FSMPS_SHIFT) | FI)
+#define DEFAULT_PERSTART       (((9 * BITS_PER_FRAME) / 10) - 1)
+
+/* CLKCTRL enable bits */
+
+#define LPC54_CLKCTRL_ENABLES   (USBOTG_CLK_HOSTCLK|USBOTG_CLK_PORTSELCLK|USBOTG_CLK_AHBCLK)
+
+/* Interrupt enable bits */
+
+#ifdef CONFIG_DEBUG_USB
+#  define LPC54_DEBUG_INTS      (OHCI_INT_SO|OHCI_INT_RD|OHCI_INT_UE|OHCI_INT_OC)
+#else
+#  define LPC54_DEBUG_INTS      0
+#endif
+
+#define LPC54_NORMAL_INTS       (OHCI_INT_WDH|OHCI_INT_RHSC)
+#define LPC54_ALL_INTS          (LPC54_NORMAL_INTS|LPC54_DEBUG_INTS)
+
+/* Dump GPIO registers */
+
+#ifdef CONFIG_LPC54_OHCI_REGDEBUG
+#  define usbhost_dumpgpio() \
+   do { \
+     lpc54_dumpgpio(GPIO_USB_DP, "D+ P0.29; D- P0.30"); \
+     lpc54_dumpgpio(GPIO_USB_UPLED, "LED P1:18; PPWR P1:19 PWRD P1:22 PVRCR P1:27"); \
+   } while (0);
+#else
+#  define usbhost_dumpgpio()
+#endif
+
+/* Numbers and Sizes of Things *************************************************/
+
+/* Fixed size of the OHCI control area */
+
+#define LPC54_HCCA_SIZE 256
+
+/* Fixed endpoint descriptor size.  The actual size required by the hardware is only
+ * 16 bytes, however, we set aside an additional 16 bytes for for internal use by
+ * the OHCI host driver.  16-bytes is set aside because the EDs must still be
+ * aligned to 16-byte boundaries.
+ */
+
+#define LPC54_ED_SIZE   32
+
+/* Configurable number of user endpoint descriptors (EDs).  This number excludes
+ * the control endpoint that is always allocated.
+ */
+
+#ifndef CONFIG_LP17_OHCI_NEDS
+#  define CONFIG_LP17_OHCI_NEDS 2
+#endif
+
+/* Derived size of user endpoint descriptor (ED) memory. */
+
+#define LPC54_EDFREE_SIZE (CONFIG_LP17_OHCI_NEDS * LPC54_ED_SIZE)
+
+/* Fixed transfer descriptor size.  The actual size required by the hardware is only
+ * 16 bytes, however, we set aside an additional 16 bytes for for internal use by
+ * the OHCI host driver.  16-bytes is set aside because the TDs must still be
+ * aligned to 16-byte boundaries.
+ */
+
+#define LPC54_TD_SIZE   32
+
+/* Configurable number of user transfer descriptors (TDs).  */
+
+#ifndef CONFIG_LP17_OHCI_NTDS
+#  define CONFIG_LP17_OHCI_NTDS 3
+#endif
+
+#if CONFIG_LP17_OHCI_NTDS < 2
+#  error "Insufficent TDs"
+#endif
+
+/* Derived size of user transfer descriptor (TD) memory. */
+
+#define LPC54_TDFREE_SIZE (CONFIG_LP17_OHCI_NTDS * LPC54_TD_SIZE)
+
+/* Configurable number of request/descriptor buffers (TDBUFFER) */
+
+#ifndef CONFIG_LPC54_OHCI_TDBUFFERS
+#  define CONFIG_LPC54_OHCI_TDBUFFERS 2
+#endif
+
+#if CONFIG_LPC54_OHCI_TDBUFFERS < 2
+#  error "At least two TD buffers are required"
+#endif
+
+/* Configurable size of a TD buffer */
+
+#if CONFIG_LPC54_OHCI_TDBUFFERS > 0 && !defined(CONFIG_LPC54_OHCI_TDBUFSIZE)
+#  define CONFIG_LPC54_OHCI_TDBUFSIZE 128
+#endif
+
+#if (CONFIG_LPC54_OHCI_TDBUFSIZE & 3) != 0
+#  error "TD buffer size must be an even number of 32-bit words"
+#endif
+
+#define LPC54_TBFREE_SIZE (CONFIG_LPC54_OHCI_TDBUFFERS * CONFIG_LPC54_OHCI_TDBUFSIZE)
+
+/* Configurable size of an IO buffer.  The number of IO buffers will be determined
+ * by what is left at the end of the BANK1 memory setup aside of OHCI RAM.
+ */
+
+#ifndef CONFIG_LPC54_OHCI_IOBUFSIZE
+#  define CONFIG_LPC54_OHCI_IOBUFSIZE 512
+#endif
+
+#if (CONFIG_LPC54_OHCI_IOBUFSIZE & 3) != 0
+#  error "IO buffer size must be an even number of 32-bit words"
+#endif
+
+/* USB Host Memory *************************************************************/
+
+/* Required Alignment */
+
+#define LPC54_ALIGN_SIZE 16
+
+/* How many pre-allocated I/O buffers */
+
+#if CONFIG_LPC54_OHCI_IOBUFSIZE > 0  && CONFIG_LPC54_OHCI_NIOBUFFERS > 0
+#  define LPC54_IOBUFFERS   CONFIG_LPC54_OHCI_NIOBUFFERS
+#  define LPC54_IOBUF_ALLOC \
+     (CONFIG_LPC54_OHCI_IOBUFSIZE * CONFIG_LPC54_OHCI_NIOBUFFERS)
+#else
+#  define LPC54_IOBUFFERS   0
+#  define LPC54_IOBUF_ALLOC 0
+#endif
+
+/* Helper definitions */
+
+#define HCCA             ((struct ohci_hcca_s *)g_hcca)
+#define TDTAIL           ((struct lpc54_gtd_s *)g_tdtail_alloc)
+#define EDCTRL           ((struct lpc54_ed_s *)g_edctrl_alloc)
+
+/* Periodic intervals 2, 4, 8, 16,and 32 supported */
+
+#define MIN_PERINTERVAL  2
+#define MAX_PERINTERVAL  32
+
+/* Descriptors *****************************************************************/
+
+/* TD delay interrupt value */
+
+#define TD_DELAY(n) (uint32_t)((n) << GTD_STATUS_DI_SHIFT)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure retains the state of the USB host controller */
+
+struct lpc54_usbhost_s
+{
+  /* Common device fields.  This must be the first thing defined in the
+   * structure so that it is possible to simply cast from struct usbhost_s
+   * to structlpc54_usbhost_s.
+   */
+
+  struct usbhost_driver_s drvr;
+
+  /* This is the hub port description understood by class drivers */
+
+  struct usbhost_roothubport_s rhport;
+
+  /* Driver status */
+
+  volatile bool    change;      /* Connection change */
+  volatile bool    connected;   /* Connected to device */
+  volatile bool    pscwait;     /* TRUE: Thread is waiting for a port status change */
+
+#ifndef CONFIG_OHCI_INT_DISABLE
+  uint8_t          ininterval;  /* Minimum periodic IN EP polling interval: 2, 4, 6, 16, or 32 */
+  uint8_t          outinterval; /* Minimum periodic IN EP polling interval: 2, 4, 6, 16, or 32 */
+#endif
+
+  sem_t            exclsem;     /* Support mutually exclusive access */
+  sem_t            pscsem;      /* Semaphore to wait Writeback Done Head event */
+
+#ifdef CONFIG_OHCI_HUB
+  /* Used to pass external hub port events */
+
+  volatile struct usbhost_hubport_s *hport;
+#endif
+};
+
+/* This structure describes one asynchronous transfer */
+
+struct lpc54_xfrinfo_s
+{
+  volatile bool wdhwait;      /* Thread is waiting for WDH interrupt */
+  volatile uint8_t tdstatus;  /* TD control status bits from last Writeback Done Head event */
+  uint8_t *buffer;            /* Transfer buffer start */
+  uint16_t buflen;            /* Buffer length */
+  uint16_t xfrd;              /* Number of bytes transferred */
+
+#ifdef CONFIG_OHCI_ASYNCH
+#if LPC54_IOBUFFERS > 0
+  /* Remember the allocated DMA buffer address so that it can be freed when
+   * the transfer completes.
+   */
+
+  uint8_t *alloc;             /* Allocated buffer */
+#endif
+
+  /* Retain the callback information for the asynchronous transfer
+   * completion.
+   */
+
+  usbhost_asynch_t callback;  /* Transfer complete callback */
+  void *arg;                  /* Argument that accompanies the callback */
+#endif
+};
+
+/* The OCHI expects the size of an endpoint descriptor to be 16 bytes.
+ * However, the size allocated for an endpoint descriptor is 32 bytes in
+ * lpc54_ohciram.h.  This extra 16-bytes is used by the OHCI host driver in
+ * order to maintain additional endpoint-specific data.
+ */
+
+struct lpc54_ed_s
+{
+  /* Hardware specific fields */
+
+  struct ohci_ed_s hw;        /* 0-15 */
+
+  /* Software specific fields */
+
+  uint8_t          xfrtype;   /* 16: Transfer type.  See SB_EP_ATTR_XFER_* in usb.h */
+  uint8_t          interval;  /* 17: Periodic EP polling interval: 2, 4, 6, 16, or 32 */
+  sem_t            wdhsem;    /* 18: Semaphore used to wait for Writeback Done Head event */
+                              /*    Unused bytes may follow, depending on the size of sem_t */
+  /* Pointer to structure that manages asynchronous transfers on this pipe */
+
+  struct lpc54_xfrinfo_s *xfrinfo;
+};
+
+/* The OCHI expects the size of an transfer descriptor to be 16 bytes.
+ * However, the size allocated for an endpoint descriptor is 32 bytes in
+ * lpc54_ohciram.h.  This extra 16-bytes is used by the OHCI host driver in
+ * order to maintain additional endpoint-specific data.
+ */
+
+struct lpc54_gtd_s
+{
+  /* Hardware specific fields */
+
+  struct ohci_gtd_s hw;
+
+  /* Software specific fields */
+
+  struct lpc54_ed_s *ed;      /* Pointer to parent ED */
+  uint8_t           pad[12];
+};
+
+/* The following is used to manage lists of free EDs, TDs, and TD buffers */
+
+struct lpc54_list_s
+{
+  struct lpc54_list_s *flink; /* Link to next buffer in the list */
+                              /* Variable length buffer data follows */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Register operations ********************************************************/
+
+#ifdef CONFIG_LPC54_OHCI_REGDEBUG
+static void lpc54_printreg(uint32_t addr, uint32_t val, bool iswrite);
+static void lpc54_checkreg(uint32_t addr, uint32_t val, bool iswrite);
+static uint32_t lpc54_getreg(uint32_t addr);
+static void lpc54_putreg(uint32_t val, uint32_t addr);
+#else
+# define lpc54_getreg(addr)     getreg32(addr)
+# define lpc54_putreg(val,addr) putreg32(val,addr)
+#endif
+
+/* Semaphores ******************************************************************/
+
+static void lpc54_takesem(sem_t *sem);
+#define lpc54_givesem(s) nxsem_post(s);
+
+/* Byte stream access helper functions *****************************************/
+
+static inline uint16_t lpc54_getle16(const uint8_t *val);
+#if 0 /* Not used */
+static void lpc54_putle16(uint8_t *dest, uint16_t val);
+#endif
+
+/* OHCI memory pool helper functions *******************************************/
+
+static inline void lpc54_edfree(struct lpc54_ed_s *ed);
+static  struct lpc54_gtd_s *lpc54_tdalloc(void);
+static void lpc54_tdfree(struct lpc54_gtd_s *buffer);
+static uint8_t *lpc54_tballoc(void);
+static void lpc54_tbfree(uint8_t *buffer);
+#if LPC54_IOBUFFERS > 0
+static uint8_t *lpc54_allocio(void);
+static void lpc54_freeio(uint8_t *buffer);
+#endif
+static struct lpc54_xfrinfo_s *lpc54_alloc_xfrinfo(void);
+static void lpc54_free_xfrinfo(struct lpc54_xfrinfo_s *xfrinfo);
+
+/* ED list helper functions ****************************************************/
+
+static inline int lpc54_addctrled(struct lpc54_usbhost_s *priv,
+                                  struct lpc54_ed_s *ed);
+static inline int lpc54_remctrled(struct lpc54_usbhost_s *priv,
+                                  struct lpc54_ed_s *ed);
+
+static inline int lpc54_addbulked(struct lpc54_usbhost_s *priv,
+                                  struct lpc54_ed_s *ed);
+static inline int lpc54_rembulked(struct lpc54_usbhost_s *priv,
+                                  struct lpc54_ed_s *ed);
+
+#if !defined(CONFIG_OHCI_INT_DISABLE) || !defined(CONFIG_OHCI_ISOC_DISABLE)
+static unsigned int lpc54_getinterval(uint8_t interval);
+static void lpc54_setinttab(uint32_t value, unsigned int interval, unsigned int offset);
+#endif
+
+static inline int lpc54_addinted(struct lpc54_usbhost_s *priv,
+                                 const struct usbhost_epdesc_s *epdesc,
+                                 struct lpc54_ed_s *ed);
+static inline int lpc54_reminted(struct lpc54_usbhost_s *priv,
+                                 struct lpc54_ed_s *ed);
+
+static inline int lpc54_addisoced(struct lpc54_usbhost_s *priv,
+                                  const struct usbhost_epdesc_s *epdesc,
+                                  struct lpc54_ed_s *ed);
+static inline int lpc54_remisoced(struct lpc54_usbhost_s *priv,
+                                  struct lpc54_ed_s *ed);
+
+/* Descriptor helper functions *************************************************/
+
+static int lpc54_enqueuetd(struct lpc54_usbhost_s *priv,
+                           struct lpc54_ed_s *ed, uint32_t dirpid,
+                           uint32_t toggle, volatile uint8_t *buffer,
+                           size_t buflen);
+static int lpc54_ctrltd(struct lpc54_usbhost_s *priv, struct lpc54_ed_s *ed,
+                        uint32_t dirpid, uint8_t *buffer, size_t buflen);
+
+/* Interrupt handling **********************************************************/
+
+static int lpc54_usbinterrupt(int irq, void *context, FAR void *arg);
+
+/* USB host controller operations **********************************************/
+
+static int lpc54_wait(struct usbhost_connection_s *conn,
+                      struct usbhost_hubport_s **hport);
+static int lpc54_rh_enumerate(struct usbhost_connection_s *conn,
+                              struct usbhost_hubport_s *hport);
+static int lpc54_enumerate(struct usbhost_connection_s *conn,
+                           struct usbhost_hubport_s *hport);
+
+static int lpc54_ep0configure(struct usbhost_driver_s *drvr,
+                              usbhost_ep_t ep0, uint8_t funcaddr, uint8_t speed,
+                              uint16_t maxpacketsize);
+static int lpc54_epalloc(struct usbhost_driver_s *drvr,
+                         const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep);
+static int lpc54_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep);
+static int lpc54_alloc(struct usbhost_driver_s *drvr,
+                       uint8_t **buffer, size_t *maxlen);
+static int lpc54_free(struct usbhost_driver_s *drvr, uint8_t *buffer);
+static int lpc54_ioalloc(struct usbhost_driver_s *drvr,
+                         uint8_t **buffer, size_t buflen);
+static int lpc54_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer);
+static int lpc54_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
+                        const struct usb_ctrlreq_s *req,
+                        uint8_t *buffer);
+static int lpc54_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
+                         const struct usb_ctrlreq_s *req,
+                         const uint8_t *buffer);
+static int lpc54_transfer_common(struct lpc54_usbhost_s *priv,
+                                 struct lpc54_ed_s *ed, uint8_t *buffer,
+                                 size_t buflen);
+#if LPC54_IOBUFFERS > 0
+static int lpc54_dma_alloc(struct lpc54_usbhost_s *priv,
+                           struct lpc54_ed_s *ed, uint8_t *userbuffer,
+                           size_t buflen, uint8_t **alloc);
+static void lpc54_dma_free(struct lpc54_usbhost_s *priv,
+                           struct lpc54_ed_s *ed, uint8_t *userbuffer,
+                           size_t buflen, uint8_t *alloc);
+#endif
+static ssize_t lpc54_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
+                              uint8_t *buffer, size_t buflen);
+#ifdef CONFIG_OHCI_ASYNCH
+static void lpc54_asynch_completion(struct lpc54_usbhost_s *priv,
+                                    struct lpc54_ed_s *ed);
+static int lpc54_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep,
+                        FAR uint8_t *buffer, size_t buflen,
+                        usbhost_asynch_t callback, FAR void *arg);
+#endif
+static int lpc54_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep);
+#ifdef CONFIG_OHCI_HUB
+static int lpc54_connect(FAR struct usbhost_driver_s *drvr,
+                         FAR struct usbhost_hubport_s *hport,
+                         bool connected);
+#endif
+static void lpc54_disconnect(struct usbhost_driver_s *drvr,
+                             struct usbhost_hubport_s *hport);
+
+/* Initialization **************************************************************/
+
+static inline void lpc54_ep0init(struct lpc54_usbhost_s *priv);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* In this driver implementation, support is provided for only a single a single
+ * USB device.  All status information can be simply retained in a single global
+ * instance.
+ */
+
+static struct lpc54_usbhost_s g_usbhost;
+
+/* This is the connection/enumeration interface */
+
+static struct usbhost_connection_s g_usbconn =
+{
+  .wait             = lpc54_wait,
+  .enumerate        = lpc54_enumerate,
+};
+
+/* Aligned static memory allocations */
+
+static uint8_t g_hcca[LPC54_HCCA_SIZE] \
+  __attribute__ ((aligned(LPC54_ALIGN_SIZE)));
+static uint8_t g_tdtail_alloc[LPC54_TD_SIZE] \
+  __attribute__ ((aligned(LPC54_ALIGN_SIZE)));
+static uint8_t g_edctrl_alloc[LPC54_ED_SIZE] \
+  __attribute__ ((aligned(LPC54_ALIGN_SIZE)));
+static uint8_t g_edfree_alloc[LPC54_EDFREE_SIZE] \
+  __attribute__ ((aligned(LPC54_ALIGN_SIZE)));
+static uint8_t g_tdfree_alloc[LPC54_TDFREE_SIZE] \
+  __attribute__ ((aligned(LPC54_ALIGN_SIZE)));
+static uint8_t g_tbfree_alloc[LPC54_TBFREE_SIZE] \
+  __attribute__ ((aligned(LPC54_ALIGN_SIZE)));
+
+#if LPC54_IOBUFFERS > 0
+static uint8_t g_iobuffers[LPC54_IOBUF_ALLOC] \
+  __attribute__ ((aligned(LPC54_ALIGN_SIZE)));
+#endif
+
+/* This is a free list of EDs and TD buffers */
+
+static struct lpc54_list_s *g_edfree; /* List of unused EDs */
+static struct lpc54_list_s *g_tdfree; /* List of unused TDs */
+static struct lpc54_list_s *g_tbfree; /* List of unused transfer buffers */
+#if LPC54_IOBUFFERS > 0
+static struct lpc54_list_s *g_iofree; /* List of unused I/O buffers */
+#endif
+
+/* Pool and freelist of transfer structures */
+
+static struct lpc54_list_s *g_xfrfree;
+static struct lpc54_xfrinfo_s g_xfrbuffers[CONFIG_LPC54_OHCI_NPREALLOC];
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc54_printreg
+ *
+ * Description:
+ *   Print the contents of an LPC54xx register operation
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LPC54_OHCI_REGDEBUG
+static void lpc54_printreg(uint32_t addr, uint32_t val, bool iswrite)
+{
+  uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val);
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc54_checkreg
+ *
+ * Description:
+ *   Get the contents of an LPC54xx register
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LPC54_OHCI_REGDEBUG
+static void lpc54_checkreg(uint32_t addr, uint32_t val, bool iswrite)
+{
+  static uint32_t prevaddr = 0;
+  static uint32_t preval = 0;
+  static uint32_t count = 0;
+  static bool     prevwrite = false;
+
+  /* Is this the same value that we read from/wrote to the same register last time?
+   * Are we polling the register?  If so, suppress the output.
+   */
+
+  if (addr == prevaddr && val == preval && prevwrite == iswrite)
+    {
+      /* Yes.. Just increment the count */
+
+      count++;
+    }
+  else
+    {
+      /* No this is a new address or value or operation. Were there any
+       * duplicate accesses before this one?
+       */
+
+      if (count > 0)
+        {
+          /* Yes.. Just one? */
+
+          if (count == 1)
+            {
+              /* Yes.. Just one */
+
+              lpc54_printreg(prevaddr, preval, prevwrite);
+            }
+          else
+            {
+              /* No.. More than one. */
+
+              uinfo("[repeats %d more times]\n", count);
+            }
+        }
+
+      /* Save the new address, value, count, and operation for next time */
+
+      prevaddr  = addr;
+      preval    = val;
+      count     = 0;
+      prevwrite = iswrite;
+
+      /* Show the new regisgter access */
+
+      lpc54_printreg(addr, val, iswrite);
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc54_getreg
+ *
+ * Description:
+ *   Get the contents of an LPC54xx register
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LPC54_OHCI_REGDEBUG
+static uint32_t lpc54_getreg(uint32_t addr)
+{
+  /* Read the value from the register */
+
+  uint32_t val = getreg32(addr);
+
+  /* Check if we need to print this value */
+
+  lpc54_checkreg(addr, val, false);
+  return val;
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc54_putreg
+ *
+ * Description:
+ *   Set the contents of an LPC54xx register to a value
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_LPC54_OHCI_REGDEBUG
+static void lpc54_putreg(uint32_t val, uint32_t addr)
+{
+  /* Check if we need to print this value */
+
+  lpc54_checkreg(addr, val, true);
+
+  /* Write the value */
+
+  putreg32(val, addr);
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc54_takesem
+ *
+ * Description:
+ *   This is just a wrapper to handle the annoying behavior of semaphore
+ *   waits that return due to the receipt of a signal.
+ *
+ ****************************************************************************/
+
+static void lpc54_takesem(sem_t *sem)
+{
+  int ret;
+
+  do
+    {
+      /* Take the semaphore (perhaps waiting) */
+
+      ret = nxsem_wait(sem);
+
+      /* The only case that an error should occur here is if the wait was
+       * awakened by a signal.
+       */
+
+      DEBUGASSERT(ret == OK || ret == -EINTR);
+    }
+  while (ret == -EINTR);
+}
+
+/****************************************************************************
+ * Name: lpc54_getle16
+ *
+ * Description:
+ *   Get a (possibly unaligned) 16-bit little endian value.
+ *
+ ****************************************************************************/
+
+static inline uint16_t lpc54_getle16(const uint8_t *val)
+{
+  return (uint16_t)val[1] << 8 | (uint16_t)val[0];
+}
+
+/****************************************************************************
+ * Name: lpc54_putle16
+ *
+ * Description:
+ *   Put a (possibly unaligned) 16-bit little endian value.
+ *
+ ****************************************************************************/
+
+#if 0 /* Not used */
+static void lpc54_putle16(uint8_t *dest, uint16_t val)
+{
+  dest[0] = val & 0xff; /* Little endian means LS byte first in byte stream */
+  dest[1] = val >> 8;
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc54_edfree
+ *
+ * Description:
+ *   Return an endpoint descriptor to the free list
+ *
+ ****************************************************************************/
+
+static inline void lpc54_edfree(struct lpc54_ed_s *ed)
+{
+  struct lpc54_list_s *entry = (struct lpc54_list_s *)ed;
+
+  /* Put the ED back into the free list */
+
+  entry->flink = g_edfree;
+  g_edfree     = entry;
+}
+
+/****************************************************************************
+ * Name: lpc54_tdalloc
+ *
+ * Description:
+ *   Allocate an transfer descriptor from the free list
+ *
+ * Assumptions:
+ *   - Never called from an interrupt handler.
+ *   - Protected from conconcurrent access to the TD pool by the interrupt
+ *     handler
+ *   - Protection from re-entrance must be assured by the caller
+ *
+ ****************************************************************************/
+
+static struct lpc54_gtd_s *lpc54_tdalloc(void)
+{
+  struct lpc54_gtd_s *ret;
+  irqstate_t flags;
+
+  /* Disable interrupts momentarily so that lpc54_tdfree is not called from the
+   * interrupt handler.
+   */
+
+  flags = enter_critical_section();
+  ret   = (struct lpc54_gtd_s *)g_tdfree;
+  if (ret)
+    {
+      g_tdfree = ((struct lpc54_list_s *)ret)->flink;
+    }
+
+  leave_critical_section(flags);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: lpc54_tdfree
+ *
+ * Description:
+ *   Return an transfer descriptor to the free list
+ *
+ * Assumptions:
+ *   - Only called from the WDH interrupt handler (and during initialization).
+ *   - Interrupts are disabled in any case.
+ *
+ ****************************************************************************/
+
+static void lpc54_tdfree(struct lpc54_gtd_s *td)
+{
+  struct lpc54_list_s *tdfree = (struct lpc54_list_s *)td;
+
+  /* This should not happen but just to be safe, don't free the common, pre-
+   * allocated tail TD.
+   */
+
+  if (tdfree != NULL && td != TDTAIL)
+    {
+      tdfree->flink = g_tdfree;
+      g_tdfree      = tdfree;
+    }
+}
+
+/****************************************************************************
+ * Name: lpc54_tballoc
+ *
+ * Description:
+ *   Allocate an request/descriptor transfer buffer from the free list
+ *
+ * Assumptions:
+ *   - Never called from an interrupt handler.
+ *   - Protection from re-entrance must be assured by the caller
+ *
+ ****************************************************************************/
+
+static uint8_t *lpc54_tballoc(void)
+{
+  uint8_t *ret = (uint8_t *)g_tbfree;
+  if (ret)
+    {
+      g_tbfree = ((struct lpc54_list_s *)ret)->flink;
+    }
+  return ret;
+}
+
+/****************************************************************************
+ * Name: lpc54_tbfree
+ *
+ * Description:
+ *   Return an request/descriptor transfer buffer to the free list
+ *
+ ****************************************************************************/
+
+static void lpc54_tbfree(uint8_t *buffer)
+{
+  struct lpc54_list_s *tbfree = (struct lpc54_list_s *)buffer;
+
+  if (tbfree)
+    {
+      tbfree->flink              = g_tbfree;
+      g_tbfree                   = tbfree;
+    }
+}
+
+/****************************************************************************
+ * Name: lpc54_allocio
+ *
+ * Description:
+ *   Allocate an IO buffer from the free list
+ *
+ * Assumptions:
+ *   - Never called from an interrupt handler.
+ *   - Protection from re-entrance must be assured by the caller
+ *
+ ****************************************************************************/
+
+#if LPC54_IOBUFFERS > 0
+static uint8_t *lpc54_allocio(void)
+{
+  uint8_t *ret;
+  irqstate_t flags;
+
+  /* lpc54_freeio() may be called from the interrupt level */
+
+  flags = enter_critical_section();
+  ret = (uint8_t *)g_iofree;
+  if (ret)
+    {
+      g_iofree = ((struct lpc54_list_s *)ret)->flink;
+    }
+
+  leave_critical_section(flags);
+  return ret;
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc54_freeio
+ *
+ * Description:
+ *   Return an TD buffer to the free list
+ *
+ ****************************************************************************/
+
+#if LPC54_IOBUFFERS > 0
+static void lpc54_freeio(uint8_t *buffer)
+{
+  struct lpc54_list_s *iofree;
+  irqstate_t flags;
+
+  /* Could be called from the interrupt level */
+
+  flags         = enter_critical_section();
+  iofree        = (struct lpc54_list_s *)buffer;
+  iofree->flink = g_iofree;
+  g_iofree      = iofree;
+  leave_critical_section(flags);
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc54_alloc_xfrinfo
+ *
+ * Description:
+ *   Allocate an asynchronous data structure from the free list
+ *
+ * Assumptions:
+ *   - Never called from an interrupt handler.
+ *   - Protection from re-entrance must be assured by the caller
+ *
+ ****************************************************************************/
+
+static struct lpc54_xfrinfo_s *lpc54_alloc_xfrinfo(void)
+{
+  struct lpc54_xfrinfo_s *ret;
+  irqstate_t flags;
+
+  /* lpc54_free_xfrinfo() may be called from the interrupt level */
+
+  flags = enter_critical_section();
+  ret = (struct lpc54_xfrinfo_s *)g_xfrfree;
+  if (ret)
+    {
+      g_xfrfree = ((struct lpc54_list_s *)ret)->flink;
+    }
+
+  leave_critical_section(flags);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: lpc54_freeio
+ *
+ * Description:
+ *   Return an TD buffer to the free list
+ *
+ ****************************************************************************/
+
+static void lpc54_free_xfrinfo(struct lpc54_xfrinfo_s *xfrinfo)
+{
+  struct lpc54_list_s *node;
+  irqstate_t flags;
+
+  /* Could be called from the interrupt level */
+
+  flags        = enter_critical_section();
+  node         = (struct lpc54_list_s *)xfrinfo;
+  node->flink  = g_xfrfree;
+  g_xfrfree    = node;
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: lpc54_addctrled
+ *
+ * Description:
+ *   Helper function to add an ED to the control list.
+ *
+ ****************************************************************************/
+
+static inline int lpc54_addctrled(struct lpc54_usbhost_s *priv,
+                                  struct lpc54_ed_s *ed)
+{
+  irqstate_t flags;
+  uint32_t regval;
+
+  /* Disable control list processing while we modify the list */
+
+  flags   = enter_critical_section();
+  regval = lpc54_getreg(LPC54_OHCI_CTRL);
+  regval &= ~OHCI_CTRL_CLE;
+  lpc54_putreg(regval, LPC54_OHCI_CTRL);
+
+  /* Add the new bulk ED to the head of the bulk list */
+
+  ed->hw.nexted = lpc54_getreg(LPC54_OHCI_CTRLHEADED);
+  lpc54_putreg((uint32_t)ed, LPC54_OHCI_CTRLHEADED);
+
+  /* Re-enable control list processing. */
+
+  lpc54_putreg(0, LPC54_OHCI_CTRLED);
+
+  regval = lpc54_getreg(LPC54_OHCI_CTRL);
+  regval |= OHCI_CTRL_CLE;
+  lpc54_putreg(regval, LPC54_OHCI_CTRL);
+
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: lpc54_remctrled
+ *
+ * Description:
+ *   Helper function remove an ED from the control list.
+ *
+ ****************************************************************************/
+
+static inline int lpc54_remctrled(struct lpc54_usbhost_s *priv,
+                                  struct lpc54_ed_s *ed)
+{
+  struct lpc54_ed_s *curr;
+  struct lpc54_ed_s *prev;
+  struct lpc54_ed_s *head;
+  irqstate_t flags;
+  uint32_t regval;
+
+  /* Disable control list processing while we modify the list */
+
+  flags   = enter_critical_section();
+  regval = lpc54_getreg(LPC54_OHCI_CTRL);
+  regval &= ~OHCI_CTRL_CLE;
+  lpc54_putreg(regval, LPC54_OHCI_CTRL);
+
+  /* Find the ED in the control list. */
+
+  head = (struct lpc54_ed_s *)lpc54_getreg(LPC54_OHCI_CTRLHEADED);
+  for (prev = NULL, curr = head;
+       curr && curr != ed;
+       prev = curr, curr = (struct lpc54_ed_s *)curr->hw.nexted);
+
+  /* It would be a bug if we do not find the ED in the control list. */
+
+  DEBUGASSERT(curr != NULL);
+
+  /* Remove the ED from the control list */
+
+  if (curr != NULL)
+    {
+      /* Is this ED the first on in the control list? */
+
+      if (prev == NULL)
+        {
+          /* Yes... set the head of the control list to skip over this ED */
+
+          head = (struct lpc54_ed_s *)ed->hw.nexted;
+          lpc54_putreg((uint32_t)head, LPC54_OHCI_CTRLHEADED);
+        }
+      else
+        {
+          /* No.. set the forward link of the previous ED in the list
+           * skip over this ED.
+           */
+
+          prev->hw.nexted = ed->hw.nexted;
+        }
+
+      /* Just in case the hardware happens to be processing this ed now...
+       * it should go back to the control list head.
+       */
+
+      ed->hw.nexted = 0;
+    }
+
+  /* Re-enable control list processing if the control list is still non-empty
+   * after removing the ED node.
+   */
+
+  lpc54_putreg(0, LPC54_OHCI_CTRLED);
+  if (lpc54_getreg(LPC54_OHCI_CTRLHEADED) != 0)
+    {
+      /* If the control list is now empty, then disable it */
+
+      regval  = lpc54_getreg(LPC54_OHCI_CTRL);
+      regval &= ~OHCI_CTRL_CLE;
+      lpc54_putreg(regval, LPC54_OHCI_CTRL);
+    }
+
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: lpc54_addbulked
+ *
+ * Description:
+ *   Helper function to add an ED to the bulk list.
+ *
+ ****************************************************************************/
+
+static inline int lpc54_addbulked(struct lpc54_usbhost_s *priv,
+                                  struct lpc54_ed_s *ed)
+{
+#ifndef CONFIG_OHCI_BULK_DISABLE
+  irqstate_t flags;
+  uint32_t regval;
+
+  /* Disable bulk list processing while we modify the list */
+
+  flags   = enter_critical_section();
+  regval  = lpc54_getreg(LPC54_OHCI_CTRL);
+  regval &= ~OHCI_CTRL_BLE;
+  lpc54_putreg(regval, LPC54_OHCI_CTRL);
+
+  /* Add the new bulk ED to the head of the bulk list */
+
+  ed->hw.nexted = lpc54_getreg(LPC54_OHCI_BULKHEADED);
+  lpc54_putreg((uint32_t)ed, LPC54_OHCI_BULKHEADED);
+
+  /* Re-enable bulk list processing. */
+
+  lpc54_putreg(0, LPC54_OHCI_BULKED);
+
+  regval  = lpc54_getreg(LPC54_OHCI_CTRL);
+  regval |= OHCI_CTRL_BLE;
+  lpc54_putreg(regval, LPC54_OHCI_CTRL);
+
+  leave_critical_section(flags);
+  return OK;
+#else
+  return -ENOSYS;
+#endif
+}
+
+/****************************************************************************
+ * Name: lpc54_rembulked
+ *
+ * Description:
+ *   Helper function remove an ED from the bulk list.
+ *
+ ****************************************************************************/
+
+static inline int lpc54_rembulked(struct lpc54_usbhost_s *priv,
+                                  struct lpc54_ed_s *ed)
+{
+#ifndef CONFIG_OHCI_BULK_DISABLE
+  struct lpc54_ed_s *curr;
+  struct lpc54_ed_s *prev;
+  struct lpc54_ed_s *head;
+  irqstate_t flags;
+  uint32_t regval;
+
+  /* Disable bulk list processing while we modify the list */
+
+  flags   = enter_critical_section();
+  regval  = lpc54_getreg(LPC54_OHCI_CTRL);
+  regval &= ~OHCI_CTRL_BLE;
+  lpc54_putreg(regval, LPC54_OHCI_CTRL);
+
+  /* Find the ED in the bulk list. */
+
+  head = (struct lpc54_ed_s *)lpc54_getreg(LPC54_OHCI_BULKHEADED);
+  for (prev = NULL, curr = head;
+       curr && curr != ed;
+       prev = curr, curr = (struct lpc54_ed_s *)curr->hw.nexted);
+
+  /* It would be a bug if we do not find the ED in the bulk list. */
+
+  DEBUGASSERT(curr != NULL);
+
+  /* Remove the ED from the bulk list */
+
+  if (curr != NULL)
+    {
+      /* Is this ED the first on in the bulk list? */
+
+      if (prev == NULL)
+        {
+          /* Yes... set the head of the bulk list to skip over this ED */
+
+          head = (struct lpc54_ed_s *)ed->hw.nexted;
+          lpc54_putreg((uint32_t)head, LPC54_OHCI_BULKHEADED);
+        }
+      else
+        {
+          /* No.. set the forward link of the previous ED in the list
+           * skip over this ED.
+           */
+
+          prev->hw.nexted = ed->hw.nexted;
+        }
+    }
+
+  /* Re-enable bulk list processing if the bulk list is still non-empty
+   * after removing the ED node.
+   */
+
+  lpc54_putreg(0, LPC54_OHCI_BULKED);
+  if (lpc54_getreg(LPC54_OHCI_BULKHEADED) != 0)
+    {
+      /* If the bulk list is now empty, then disable it */
+
+      regval  = lpc54_getreg(LPC54_OHCI_CTRL);
+      regval |= OHCI_CTRL_BLE;
+      lpc54_putreg(regval, LPC54_OHCI_CTRL);
+    }
+
+  leave_critical_section(flags);
+  return OK;
+#else
+  return -ENOSYS;
+#endif
+}
+
+/****************************************************************************
+ * Name: lpc54_getinterval
+ *
+ * Description:
+ *   Convert the endpoint polling interval into a HCCA table increment
+ *
+ ****************************************************************************/
+
+#if !defined(CONFIG_OHCI_INT_DISABLE) || !defined(CONFIG_OHCI_ISOC_DISABLE)
+static unsigned int lpc54_getinterval(uint8_t interval)
+{
+  /* The bInterval field of the endpoint descriptor contains the polling interval
+   * for interrupt and isochronous endpoints. For other types of endpoint, this
+   * value should be ignored. bInterval is provided in units of 1MS frames.
+   */
+
+  if (interval < 3)
+    {
+      return 2;
+    }
+  else if (interval < 7)
+    {
+      return 4;
+    }
+  else if (interval < 15)
+    {
+      return 8;
+    }
+  else if (interval < 31)
+    {
+      return 16;
+    }
+  else
+    {
+      return 32;
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc54_setinttab
+ *
+ * Description:
+ *   Set the interrupt table to the selected value using the provided interval
+ *   and offset.
+ *
+ ****************************************************************************/
+
+#if !defined(CONFIG_OHCI_INT_DISABLE) || !defined(CONFIG_OHCI_ISOC_DISABLE)
+static void lpc54_setinttab(uint32_t value, unsigned int interval, unsigned int offset)
+{
+  unsigned int i;
+  for (i = offset; i < HCCA_INTTBL_WSIZE; i += interval)
+    {
+      HCCA->inttbl[i] = value;
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc54_addinted
+ *
+ * Description:
+ *   Helper function to add an ED to the HCCA interrupt table.
+ *
+ *   To avoid reshuffling the table so much and to keep life simple in general,
+ *    the following rules are applied:
+ *
+ *     1. IN EDs get the even entries, OUT EDs get the odd entries.
+ *     2. Add IN/OUT EDs are scheduled together at the minimum interval of all
+ *        IN/OUT EDs.
+ *
+ *   This has the following consequences:
+ *
+ *     1. The minimum support polling rate is 2MS, and
+ *     2. Some devices may get polled at a much higher rate than they request.
+ *
+ ****************************************************************************/
+
+static inline int lpc54_addinted(struct lpc54_usbhost_s *priv,
+                                 const struct usbhost_epdesc_s *epdesc,
+                                 struct lpc54_ed_s *ed)
+{
+#ifndef CONFIG_OHCI_INT_DISABLE
+  unsigned int interval;
+  unsigned int offset;
+  uint32_t head;
+  uint32_t regval;
+
+  /* Disable periodic list processing.  Does this take effect immediately?  Or
+   * at the next SOF... need to check.
+   */
+
+  regval  = lpc54_getreg(LPC54_OHCI_CTRL);
+  regval &= ~OHCI_CTRL_PLE;
+  lpc54_putreg(regval, LPC54_OHCI_CTRL);
+
+  /* Get the quantized interval value associated with this ED and save it
+   * in the ED.
+   */
+
+  interval     = lpc54_getinterval(epdesc->interval);
+  ed->interval = interval;
+  uinfo("interval: %d->%d\n", epdesc->interval, interval);
+
+  /* Get the offset associated with the ED direction. IN EDs get the even
+   * entries, OUT EDs get the odd entries.
+   *
+   * Get the new, minimum interval. Add IN/OUT EDs are scheduled together
+   * at the minimum interval of all IN/OUT EDs.
+   */
+
+  if (epdesc->in)
+    {
+      offset = 0;
+      if (priv->ininterval > interval)
+        {
+          priv->ininterval = interval;
+        }
+      else
+        {
+          interval = priv->ininterval;
+        }
+    }
+  else
+    {
+      offset = 1;
+      if (priv->outinterval > interval)
+        {
+          priv->outinterval = interval;
+        }
+      else
+        {
+          interval = priv->outinterval;
+        }
+    }
+  uinfo("min interval: %d offset: %d\n", interval, offset);
+
+  /* Get the head of the first of the duplicated entries.  The first offset
+   * entry is always guaranteed to contain the common ED list head.
+   */
+
+  head = HCCA->inttbl[offset];
+
+  /* Clear all current entries in the interrupt table for this direction */
+
+  lpc54_setinttab(0, 2, offset);
+
+  /* Add the new ED before the old head of the periodic ED list and set the
+   * new ED as the head ED in all of the appropriate entries of the HCCA
+   * interrupt table.
+   */
+
+  ed->hw.nexted = head;
+  lpc54_setinttab((uint32_t)ed, interval, offset);
+  uinfo("head: %08x next: %08x\n", ed, head);
+
+  /* Re-enabled periodic list processing */
+
+  regval  = lpc54_getreg(LPC54_OHCI_CTRL);
+  regval |= OHCI_CTRL_PLE;
+  lpc54_putreg(regval, LPC54_OHCI_CTRL);
+  return OK;
+#else
+  return -ENOSYS;
+#endif
+}
+
+/****************************************************************************
+ * Name: lpc54_reminted
+ *
+ * Description:
+ *   Helper function to remove an ED from the HCCA interrupt table.
+ *
+ *   To avoid reshuffling the table so much and to keep life simple in general,
+ *    the following rules are applied:
+ *
+ *     1. IN EDs get the even entries, OUT EDs get the odd entries.
+ *     2. Add IN/OUT EDs are scheduled together at the minimum interval of all
+ *        IN/OUT EDs.
+ *
+ *   This has the following consequences:
+ *
+ *     1. The minimum support polling rate is 2MS, and
+ *     2. Some devices may get polled at a much higher rate than they request.
+ *
+ ****************************************************************************/
+
+static inline int lpc54_reminted(struct lpc54_usbhost_s *priv,
+                                 struct lpc54_ed_s *ed)
+{
+#ifndef CONFIG_OHCI_INT_DISABLE
+  struct lpc54_ed_s *head;
+  struct lpc54_ed_s *curr;
+  struct lpc54_ed_s *prev;
+  unsigned int       interval;
+  unsigned int       offset;
+  uint32_t           regval;
+
+  /* Disable periodic list processing.  Does this take effect immediately?  Or
+   * at the next SOF... need to check.
+   */
+
+  regval  = lpc54_getreg(LPC54_OHCI_CTRL);
+  regval &= ~OHCI_CTRL_PLE;
+  lpc54_putreg(regval, LPC54_OHCI_CTRL);
+
+  /* Get the offset associated with the ED direction. IN EDs get the even
+   * entries, OUT EDs get the odd entries.
+   */
+
+  if ((ed->hw.ctrl & ED_CONTROL_D_MASK) == ED_CONTROL_D_IN)
+    {
+      offset = 0;
+    }
+  else
+    {
+      offset = 1;
+    }
+
+  /* Get the head of the first of the duplicated entries.  The first offset
+   * entry is always guaranteed to contain the common ED list head.
+   */
+
+  head = (struct lpc54_ed_s *)HCCA->inttbl[offset];
+  uinfo("ed: %08x head: %08x next: %08x offset: %d\n",
+        ed, head, head ? head->hw.nexted : 0, offset);
+
+  /* Find the ED to be removed in the ED list */
+
+  for (curr = head, prev = NULL;
+       curr && curr != ed;
+       prev = curr, curr = (struct lpc54_ed_s *)curr->hw.nexted);
+
+  /* Hmmm.. It would be a bug if we do not find the ED in the bulk list. */
+
+  DEBUGASSERT(curr != NULL);
+  if (curr != NULL)
+    {
+      /* Clear all current entries in the interrupt table for this direction */
+
+      lpc54_setinttab(0, 2, offset);
+
+      /* Remove the ED from the list..  Is this ED the first on in the list? */
+
+      if (prev == NULL)
+        {
+          /* Yes... set the head of the bulk list to skip over this ED */
+
+          head = (struct lpc54_ed_s *)ed->hw.nexted;
+        }
+      else
+        {
+          /* No.. set the forward link of the previous ED in the list
+           * skip over this ED.
+           */
+
+          prev->hw.nexted = ed->hw.nexted;
+        }
+
+        uinfo("ed: %08x head: %08x next: %08x\n",
+              ed, head, head ? head->hw.nexted : 0);
+
+      /* Calculate the new minimum interval for this list */
+
+      interval = MAX_PERINTERVAL;
+      for (curr = head; curr; curr = (struct lpc54_ed_s *)curr->hw.nexted)
+        {
+          if (curr->interval < interval)
+            {
+              interval = curr->interval;
+            }
+        }
+
+      uinfo("min interval: %d offset: %d\n", interval, offset);
+
+      /* Save the new minimum interval */
+
+      if ((ed->hw.ctrl & ED_CONTROL_D_MASK) == ED_CONTROL_D_IN)
+        {
+          priv->ininterval  = interval;
+        }
+      else
+        {
+          priv->outinterval = interval;
+        }
+
+      /* Set the head ED in all of the appropriate entries of the HCCA interrupt
+       * table (head might be NULL).
+       */
+
+      lpc54_setinttab((uint32_t)head, interval, offset);
+    }
+
+  /* Re-enabled periodic list processing */
+
+  if (head != NULL)
+    {
+      regval  = lpc54_getreg(LPC54_OHCI_CTRL);
+      regval |= OHCI_CTRL_PLE;
+      lpc54_putreg(regval, LPC54_OHCI_CTRL);
+    }
+
+  return OK;
+#else
+  return -ENOSYS;
+#endif
+}
+
+/****************************************************************************
+ * Name: lpc54_addisoced
+ *
+ * Description:
+ *   Helper functions to add an ED to the periodic table.
+ *
+ ****************************************************************************/
+
+static inline int lpc54_addisoced(struct lpc54_usbhost_s *priv,
+                                  const struct usbhost_epdesc_s *epdesc,
+                                  struct lpc54_ed_s *ed)
+{
+#ifndef CONFIG_OHCI_ISOC_DISABLE
+#  warning "Isochronous endpoints not yet supported"
+#endif
+  return -ENOSYS;
+}
+
+/****************************************************************************
+ * Name: lpc54_remisoced
+ *
+ * Description:
+ *   Helper functions to remove an ED from the periodic table.
+ *
+ ****************************************************************************/
+
+static inline int lpc54_remisoced(struct lpc54_usbhost_s *priv,
+                                  struct lpc54_ed_s *ed)
+{
+#ifndef CONFIG_OHCI_ISOC_DISABLE
+#  warning "Isochronous endpoints not yet supported"
+#endif
+  return -ENOSYS;
+}
+
+/****************************************************************************
+ * Name: lpc54_enqueuetd
+ *
+ * Description:
+ *   Enqueue a transfer descriptor.  Notice that this function only supports
+ *   queue on TD per ED.
+ *
+ ****************************************************************************/
+
+static int lpc54_enqueuetd(struct lpc54_usbhost_s *priv,
+                           struct lpc54_ed_s *ed, uint32_t dirpid,
+                           uint32_t toggle, volatile uint8_t *buffer, size_t buflen)
+{
+  struct lpc54_gtd_s *td;
+  int ret = -ENOMEM;
+
+  /* Allocate a TD from the free list */
+
+  td = lpc54_tdalloc();
+  if (td != NULL)
+    {
+      /* Initialize the allocated TD and link it before the common tail TD. */
+
+      td->hw.ctrl         = (GTD_STATUS_R | dirpid | TD_DELAY(0) | toggle | GTD_STATUS_CC_MASK);
+      TDTAIL->hw.ctrl     = 0;
+      td->hw.cbp          = (uint32_t)buffer;
+      TDTAIL->hw.cbp      = 0;
+      td->hw.nexttd       = (uint32_t)TDTAIL;
+      TDTAIL->hw.nexttd   = 0;
+      td->hw.be           = (uint32_t)(buffer + (buflen - 1));
+      TDTAIL->hw.be       = 0;
+
+      /* Configure driver-only fields in the extended TD structure */
+
+      td->ed              = ed;
+
+      /* Link the td to the head of the ED's TD list */
+
+      ed->hw.headp        = (uint32_t)td | ((ed->hw.headp) & ED_HEADP_C);
+      ed->hw.tailp        = (uint32_t)TDTAIL;
+
+      ret                 = OK;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: lpc54_wdhwait
+ *
+ * Description:
+ *   Set the request for the Writeback Done Head event well BEFORE enabling the
+ *   transfer (as soon as we are absolutely committed to the to avoid transfer).
+ *   We do this to minimize race conditions.  This logic would have to be expanded
+ *   if we want to have more than one packet in flight at a time!
+ *
+ ****************************************************************************/
+
+static int lpc54_wdhwait(struct lpc54_usbhost_s *priv, struct lpc54_ed_s *ed)
+{
+  struct lpc54_xfrinfo_s *xfrinfo;
+  irqstate_t flags = enter_critical_section();
+  int        ret   = -ENODEV;
+
+  DEBUGASSERT(ed && ed->xfrinfo);
+  xfrinfo = ed->xfrinfo;
+
+  /* Is the device still connected? */
+
+  if (priv->connected)
+    {
+      /* Yes.. then set wdhwait to indicate that we expect to be informed when
+       * either (1) the device is disconnected, or (2) the transfer completed.
+       */
+
+      xfrinfo->wdhwait = true;
+      ret = OK;
+    }
+
+  leave_critical_section(flags);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: lpc54_ctrltd
+ *
+ * Description:
+ *   Process a IN or OUT request on the control endpoint.  This function
+ *   will enqueue the request and wait for it to complete.  Only one transfer
+ *   may be queued; Neither these methods nor the transfer() method can be
+ *   called again until the control transfer functions returns.
+ *
+ *   These are blocking methods; these functions will not return until the
+ *   control transfer has completed.
+ *
+ ****************************************************************************/
+
+static int lpc54_ctrltd(struct lpc54_usbhost_s *priv, struct lpc54_ed_s *ed,
+                        uint32_t dirpid, uint8_t *buffer, size_t buflen)
+{
+  struct lpc54_xfrinfo_s *xfrinfo;
+  uint32_t toggle;
+  uint32_t regval;
+  int ret;
+
+  /* Allocate a structure to retain the information needed when the transfer
+   * completes.
+   */
+
+  DEBUGASSERT(ed->xfrinfo == NULL);
+
+  xfrinfo = lpc54_alloc_xfrinfo();
+  if (xfrinfo == NULL)
+    {
+      uerr("ERROR: lpc54_alloc_xfrinfo failed\n");
+      return -ENOMEM;
+    }
+
+  /* Initialize the transfer structure */
+
+  memset(xfrinfo, 0, sizeof(struct lpc54_xfrinfo_s));
+  xfrinfo->buffer = buffer;
+  xfrinfo->buflen = buflen;
+
+  ed->xfrinfo = xfrinfo;
+
+  /* Set the request for the Writeback Done Head event well BEFORE enabling the
+   * transfer.
+   */
+
+  ret = lpc54_wdhwait(priv, ed);
+  if (ret < 0)
+    {
+      uerr("ERROR: Device disconnected\n");
+      goto errout_with_xfrinfo;
+    }
+
+  /* Configure the toggle field in the TD */
+
+  if (dirpid == GTD_STATUS_DP_SETUP)
+    {
+      toggle = GTD_STATUS_T_DATA0;
+    }
+  else
+    {
+      toggle = GTD_STATUS_T_DATA1;
+    }
+
+  /* Then enqueue the transfer */
+
+  xfrinfo->tdstatus = TD_CC_NOERROR;
+  ret = lpc54_enqueuetd(priv, ed, dirpid, toggle, buffer, buflen);
+  if (ret == OK)
+    {
+      /* Set ControlListFilled.  This bit is used to indicate whether there are
+       * TDs on the Control list.
+       */
+
+      regval = lpc54_getreg(LPC54_OHCI_CMDST);
+      regval |= OHCI_CMDST_CLF;
+      lpc54_putreg(regval, LPC54_OHCI_CMDST);
+
+      /* Wait for the Writeback Done Head interrupt */
+
+      lpc54_takesem(&ed->wdhsem);
+
+      /* Check the TD completion status bits */
+
+      if (xfrinfo->tdstatus == TD_CC_NOERROR)
+        {
+          ret = OK;
+        }
+      else
+        {
+          uerr("ERROR: Bad TD completion status: %d\n", xfrinfo->tdstatus);
+          ret = xfrinfo->tdstatus == TD_CC_STALL ? -EPERM : -EIO;
+        }
+    }
+
+  /* Make sure that there is no outstanding request on this endpoint */
+
+errout_with_xfrinfo:
+  lpc54_free_xfrinfo(xfrinfo);
+  ed->xfrinfo = NULL;
+  return ret;
+}
+
+/****************************************************************************
+ * Name: lpc54_usbinterrupt
+ *
+ * Description:
+ *   USB interrupt handler
+ *
+ ****************************************************************************/
+
+static int lpc54_usbinterrupt(int irq, void *context, FAR void *arg)
+{
+  struct lpc54_usbhost_s *priv = &g_usbhost;
+  struct lpc54_ed_s *ed;
+  struct lpc54_xfrinfo_s *xfrinfo;
+  uintptr_t tmp;
+  uint32_t intst;
+  uint32_t pending;
+  uint32_t regval;
+
+  /* Read Interrupt Status and mask out interrupts that are not enabled. */
+
+  intst  = lpc54_getreg(LPC54_OHCI_INTST);
+  regval = lpc54_getreg(LPC54_OHCI_INTEN);
+  uinfo("INST: %08x INTEN: %08x\n", intst, regval);
+
+  pending = intst & regval;
+  if (pending != 0)
+    {
+      /* Root hub status change interrupt */
+
+      if ((pending & OHCI_INT_RHSC) != 0)
+        {
+          uint32_t rhportst1 = lpc54_getreg(LPC54_OHCI_RHPORTST1);
+          uinfo("Root Hub Status Change, RHPORTST1: %08x\n", rhportst1);
+
+          if ((rhportst1 & OHCI_RHPORTST_CSC) != 0)
+            {
+              uint32_t rhstatus = lpc54_getreg(LPC54_OHCI_RHSTATUS);
+              uinfo("Connect Status Change, RHSTATUS: %08x\n", rhstatus);
+
+              /* If DRWE is set, Connect Status Change indicates a remote wake-up event */
+
+              if (rhstatus & OHCI_RHSTATUS_DRWE)
+                {
+                  uinfo("DRWE: Remote wake-up\n");
+                }
+
+              /* Otherwise... Not a remote wake-up event */
+
+              else
+                {
+                  /* Check current connect status */
+
+                  if ((rhportst1 & OHCI_RHPORTST_CCS) != 0)
+                    {
+                      /* Connected ... Did we just become connected? */
+
+                      if (!priv->connected)
+                        {
+                          /* Yes.. connected. */
+
+                          uinfo("Connected\n");
+                          priv->connected = true;
+                          priv->change    = true;
+
+                          /* Notify any waiters */
+
+                          if (priv->pscwait)
+                            {
+                              lpc54_givesem(&priv->pscsem);
+                              priv->pscwait = false;
+                            }
+                        }
+                      else
+                        {
+                          uwarn("WARNING: Spurious status change (connected)\n");
+                        }
+
+                      /* The LSDA (Low speed device attached) bit is valid
+                       * when CCS == 1.
+                       */
+
+                      if ((rhportst1 & OHCI_RHPORTST_LSDA) != 0)
+                        {
+                          priv->rhport.hport.speed = USB_SPEED_LOW;
+                        }
+                      else
+                        {
+                          priv->rhport.hport.speed = USB_SPEED_FULL;
+                        }
+
+                      uinfo("Speed:%d\n", priv->rhport.hport.speed);
+                    }
+
+                  /* Check if we are now disconnected */
+
+                  else if (priv->connected)
+                    {
+                      /* Yes.. disconnect the device */
+
+                      uinfo("Disconnected\n");
+                      priv->connected = false;
+                      priv->change    = true;
+
+                      /* Set the port speed to the default (FULL).  We cannot
+                       * yet free the function address.  That has to be done
+                       * by the class when responds to the disconnection.
+                       */
+
+                      priv->rhport.hport.speed = USB_SPEED_FULL;
+
+                      /* Are we bound to a class instance? */
+
+                      if (priv->rhport.hport.devclass)
+                        {
+                          /* Yes.. Disconnect the class */
+
+                          CLASS_DISCONNECTED(priv->rhport.hport.devclass);
+                          priv->rhport.hport.devclass = NULL;
+                        }
+
+                      /* Notify any waiters for the Root Hub Status change event */
+
+                      if (priv->pscwait)
+                        {
+                          lpc54_givesem(&priv->pscsem);
+                          priv->pscwait = false;
+                        }
+                    }
+                  else
+                    {
+                       uwarn("WARNING: Spurious status change (disconnected)\n");
+                    }
+                }
+
+              /* Clear the status change interrupt */
+
+              lpc54_putreg(OHCI_RHPORTST_CSC, LPC54_OHCI_RHPORTST1);
+            }
+
+          /* Check for port reset status change */
+
+          if ((rhportst1 & OHCI_RHPORTST_PRSC) != 0)
+            {
+              /* Release the RH port from reset */
+
+              lpc54_putreg(OHCI_RHPORTST_PRSC, LPC54_OHCI_RHPORTST1);
+            }
+        }
+
+      /* Writeback Done Head interrupt */
+
+      if ((pending & OHCI_INT_WDH) != 0)
+        {
+          struct lpc54_gtd_s *td;
+          struct lpc54_gtd_s *next;
+
+          /* The host controller just wrote the list of finished TDs into the HCCA
+           * done head.  This may include multiple packets that were transferred
+           * in the preceding frame.
+           *
+           * Remove the TD(s) from the Writeback Done Head in the HCCA and return
+           * them to the free list.  Note that this is safe because the hardware
+           * will not modify the writeback done head again until the WDH bit is
+           * cleared in the interrupt status register.
+           */
+
+          td = (struct lpc54_gtd_s *)(HCCA->donehead & HCCA_DONEHEAD_MASK);
+          HCCA->donehead = 0;
+          next = NULL;
+
+          /* Process each TD in the write done list */
+
+          for (; td; td = next)
+            {
+              /* REVISIT: I have encountered bad TDs in the done list linked
+               * after at least one good TD.  This is some consequence of how
+               * transfers are being cancelled.  But for now, I have only
+               * this work-around.
+               */
+
+              if ((uintptr_t)td < LPC54_TDFREE_BASE ||
+                  (uintptr_t)td >= (LPC54_TDFREE_BASE + LPC54_TD_SIZE*CONFIG_LP17_OHCI_NTDS))
+                {
+                  break;
+                }
+
+              /* Get the ED in which this TD was enqueued */
+
+              ed      = td->ed;
+              DEBUGASSERT(ed != NULL);
+
+              /* If there is a transfer in progress, then the xfrinfo pointer will be
+               * non-NULL.  But it appears that a NULL pointer may be received with a
+               * spurious interrupt such as may occur after a transfer is cancelled.
+               */
+
+              xfrinfo = ed->xfrinfo;
+              if (xfrinfo)
+                {
+                  /* Save the condition code from the (single) TD status/control
+                   * word.
+                   */
+
+                  xfrinfo->tdstatus = (td->hw.ctrl & GTD_STATUS_CC_MASK) >> GTD_STATUS_CC_SHIFT;
+
+#ifdef CONFIG_DEBUG_USB
+                  if (xfrinfo->tdstatus != TD_CC_NOERROR)
+                    {
+                      /* The transfer failed for some reason... dump some diagnostic info. */
+
+                      uerr("ERROR: ED xfrtype:%d TD CTRL:%08x/CC:%d RHPORTST1:%08x\n",
+                           ed->xfrtype, td->hw.ctrl, xfrinfo->tdstatus,
+                           lpc54_getreg(LPC54_OHCI_RHPORTST1));
+                    }
+#endif
+
+                  /* Determine the number of bytes actually transfer by
+                   * subtracting the buffer start address from the CBP.  A
+                   * value of zero means that all bytes were transferred.
+                   */
+
+                  tmp = (uintptr_t)td->hw.cbp;
+                  if (tmp == 0)
+                    {
+                      /* Set the (fake) CBP to the end of the buffer + 1 */
+
+                      tmp = xfrinfo->buflen;
+                    }
+                  else
+                    {
+                      DEBUGASSERT(tmp >= (uintptr_t)xfrinfo->buffer);
+
+                      /* Determine the size of the transfer by subtracting
+                       * the current buffer pointer (CBP) from the initial
+                       * buffer pointer (on packet receipt only).
+                       */
+
+                      tmp -= (uintptr_t)xfrinfo->buffer;
+                      DEBUGASSERT(tmp < UINT16_MAX);
+                    }
+
+                  xfrinfo->xfrd = (uint16_t)tmp;
+
+                  /* Return the TD to the free list */
+
+                  next = (struct lpc54_gtd_s *)td->hw.nexttd;
+                  lpc54_tdfree(td);
+
+                  if (xfrinfo->wdhwait)
+                    {
+                      /* Wake up the thread waiting for the WDH event */
+
+                      lpc54_givesem(&ed->wdhsem);
+                      xfrinfo->wdhwait = false;
+                    }
+
+#ifdef CONFIG_OHCI_ASYNCH
+                  /* Perform any pending callbacks for the case of
+                   * asynchronous transfers.
+                   */
+
+                  else if (xfrinfo->callback)
+                    {
+                      DEBUGASSERT(xfrinfo->wdhwait == false);
+                      lpc54_asynch_completion(priv, ed);
+                    }
+#endif
+                }
+            }
+        }
+
+#ifdef CONFIG_DEBUG_USB
+      if ((pending & LPC54_DEBUG_INTS) != 0)
+        {
+          uerr("ERROR: Unhandled interrupts INTST:%08x\n", intst);
+        }
+#endif
+
+      /* Clear interrupt status register */
+
+      lpc54_putreg(intst, LPC54_OHCI_INTST);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * USB Host Controller Operations
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc54_wait
+ *
+ * Description:
+ *   Wait for a device to be connected or disconnected to/from a hub port.
+ *
+ * Input Parameters:
+ *   conn - The USB host connection instance obtained as a parameter from the call to
+ *      the USB driver initialization logic.
+ *   hport - The location to return the hub port descriptor that detected the
+ *      connection related event.
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success when a device is connected or
+ *   disconnected. This function will not return until either (1) a device is
+ *   connected or disconnect to/from any hub port or until (2) some failure
+ *   occurs.  On a failure, a negated errno value is returned indicating the
+ *   nature of the failure
+ *
+ * Assumptions:
+ *   - Called from a single thread so no mutual exclusion is required.
+ *   - Never called from an interrupt handler.
+ *
+ ****************************************************************************/
+
+static int lpc54_wait(struct usbhost_connection_s *conn,
+                      struct usbhost_hubport_s **hport)
+{
+  struct lpc54_usbhost_s *priv = (struct lpc54_usbhost_s *)&g_usbhost;
+  struct usbhost_hubport_s *connport;
+  irqstate_t flags;
+
+  flags = enter_critical_section();
+  for (; ; )
+    {
+      /* Is there a change in the connection state of the single root hub
+       * port?
+       */
+
+      if (priv->change)
+        {
+          connport = &priv->rhport.hport;
+          priv->change = false;
+
+          /* Yes.. check for false alarms */
+
+          if (priv->connected != connport->connected)
+            {
+              /* Not a false alarm.. Remember the new state */
+
+              connport->connected = priv->connected;
+
+              /* And return the root hub port */
+
+              *hport = connport;
+              leave_critical_section(flags);
+
+              uinfo("RHport Connected: %s\n",
+                    connport->connected ? "YES" : "NO");
+
+              return OK;
+            }
+        }
+
+#ifdef CONFIG_OHCI_HUB
+      /* Is a device connected to an external hub? */
+
+      if (priv->hport)
+        {
+          /* Yes.. return the external hub port */
+
+          connport = (struct usbhost_hubport_s *)priv->hport;
+          priv->hport = NULL;
+
+          *hport = connport;
+          leave_critical_section(flags);
+
+          uinfo("Hub port Connected: %s\n", connport->connected ? "YES" : "NO");
+          return OK;
+        }
+#endif
+
+      /* Wait for the next connection event */
+
+      priv->pscwait = true;
+      lpc54_takesem(&priv->pscsem);
+    }
+}
+
+/****************************************************************************
+ * Name: lpc54_enumerate
+ *
+ * Description:
+ *   Enumerate the connected device.  As part of this enumeration process,
+ *   the driver will (1) get the device's configuration descriptor, (2)
+ *   extract the class ID info from the configuration descriptor, (3) call
+ *   usbhost_findclass() to find the class that supports this device, (4)
+ *   call the create() method on the struct usbhost_registry_s interface
+ *   to get a class instance, and finally (5) call the connect() method
+ *   of the struct usbhost_class_s interface.  After that, the class is in
+ *   charge of the sequence of operations.
+ *
+ * Input Parameters:
+ *   conn - The USB host connection instance obtained as a parameter from
+ *      the call to the USB driver initialization logic.
+ *   hport - The descriptor of the hub port that has the newly connected
+ *      device.
+ *
+ * Returned Value:
+ *   On success, zero (OK) is returned. On a failure, a negated errno value is
+ *   returned indicating the nature of the failure
+ *
+ * Assumptions:
+ *   This function will *not* be called from an interrupt handler.
+ *
+ ****************************************************************************/
+
+static int lpc54_rh_enumerate(struct usbhost_connection_s *conn,
+                              struct usbhost_hubport_s *hport)
+{
+  struct lpc54_usbhost_s *priv = (struct lpc54_usbhost_s *)&g_usbhost;
+  DEBUGASSERT(conn != NULL && hport != NULL && hport->port == 0);
+
+  /* Are we connected to a device?  The caller should have called the wait()
+   * method first to be assured that a device is connected.
+   */
+
+  while (!priv->connected)
+    {
+      /* No, return an error */
+
+      uwarn("WARNING: Not connected\n");
+      return -ENODEV;
+    }
+
+  /* USB 2.0 spec says at least 50ms delay before port reset */
+
+  (void)nxsig_usleep(100*1000);
+
+  /* Put RH port 1 in reset (the LPC546x supports only a single downstream port) */
+
+  lpc54_putreg(OHCI_RHPORTST_PRS, LPC54_OHCI_RHPORTST1);
+
+  /* Wait for the port reset to complete */
+
+  while ((lpc54_getreg(LPC54_OHCI_RHPORTST1) & OHCI_RHPORTST_PRS) != 0);
+
+  /* Release RH port 1 from reset and wait a bit */
+
+  lpc54_putreg(OHCI_RHPORTST_PRSC, LPC54_OHCI_RHPORTST1);
+  (void)nxsig_usleep(200*1000);
+  return OK;
+}
+
+static int lpc54_enumerate(FAR struct usbhost_connection_s *conn,
+                           FAR struct usbhost_hubport_s *hport)
+{
+  int ret;
+
+  DEBUGASSERT(hport);
+
+  /* If this is a connection on the root hub, then we need to go to
+   * little more effort to get the device speed.  If it is a connection
+   * on an external hub, then we already have that information.
+   */
+
+#ifdef CONFIG_OHCI_HUB
+  if (ROOTHUB(hport))
+#endif
+    {
+      ret = lpc54_rh_enumerate(conn, hport);
+      if (ret < 0)
+        {
+          return ret;
+        }
+    }
+
+  /* Then let the common usbhost_enumerate do the real enumeration. */
+
+  uinfo("Enumerate the device\n");
+  ret = usbhost_enumerate(hport, &hport->devclass);
+  if (ret < 0)
+    {
+      uerr("ERROR: Enumeration failed: %d\n", ret);
+    }
+
+  return ret;
+}
+
+/************************************************************************************
+ * Name: lpc54_ep0configure
+ *
+ * Description:
+ *   Configure endpoint 0.  This method is normally used internally by the
+ *   enumerate() method but is made available at the interface to support
+ *   an external implementation of the enumeration logic.
+ *
+ * Input Parameters:
+ *   drvr - The USB host driver instance obtained as a parameter from the call to
+ *      the class create() method.
+ *   ep0 - The (opaque) EP0 endpoint instance
+ *   funcaddr - The USB address of the function containing the endpoint that EP0
+ *     controls
+ *   speed - The speed of the port USB_SPEED_LOW, _FULL, or _HIGH
+ *   mps (maxpacketsize) - The maximum number of bytes that can be sent to or
+ *    received from the endpoint in a single data packet
+ *
+ * Returned Value:
+ *   On success, zero (OK) is returned. On a failure, a negated errno value is
+ *   returned indicating the nature of the failure
+ *
+ * Assumptions:
+ *   This function will *not* be called from an interrupt handler.
+ *
+ ************************************************************************************/
+
+static int lpc54_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
+                              uint8_t funcaddr, uint8_t speed, uint16_t maxpacketsize)
+{
+  struct lpc54_usbhost_s *priv = (struct lpc54_usbhost_s *)drvr;
+  struct lpc54_ed_s      *ed;
+  uint32_t hwctrl;
+
+  DEBUGASSERT(drvr != NULL && ep0 != NULL && funcaddr < 128 && maxpacketsize < 2048);
+  ed = (struct lpc54_ed_s *)ep0;
+
+  /* We must have exclusive access to EP0 and the control list */
+
+  lpc54_takesem(&priv->exclsem);
+
+  /* Set the EP0 ED control word */
+
+  hwctrl = (uint32_t)funcaddr << ED_CONTROL_FA_SHIFT |
+           (uint32_t)ED_CONTROL_D_TD1 |
+           (uint32_t)maxpacketsize << ED_CONTROL_MPS_SHIFT;
+
+  if (speed == USB_SPEED_LOW)
+    {
+      hwctrl |= ED_CONTROL_S;
+    }
+
+  ed->hw.ctrl = hwctrl;
+
+  lpc54_givesem(&priv->exclsem);
+
+  uinfo("EP0 CTRL:%08x\n", ed->hw.ctrl);
+  return OK;
+}
+
+/************************************************************************************
+ * Name: lpc54_epalloc
+ *
+ * Description:
+ *   Allocate and configure one endpoint.
+ *
+ * Input Parameters:
+ *   drvr - The USB host driver instance obtained as a parameter from the call to
+ *      the class create() method.
+ *   epdesc - Describes the endpoint to be allocated.
+ *   ep - A memory location provided by the caller in which to receive the
+ *      allocated endpoint descriptor.
+ *
+ * Returned Value:
+ *   On success, zero (OK) is returned. On a failure, a negated errno value is
+ *   returned indicating the nature of the failure
+ *
+ * Assumptions:
+ *   This function will *not* be called from an interrupt handler.
+ *
+ ************************************************************************************/
+
+static int lpc54_epalloc(struct usbhost_driver_s *drvr,
+                         const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep)
+{
+  struct lpc54_usbhost_s *priv = (struct lpc54_usbhost_s *)drvr;
+  struct usbhost_hubport_s *hport;
+  struct lpc54_ed_s *ed;
+  int ret  = -ENOMEM;
+
+  /* Sanity check.  NOTE that this method should only be called if a device is
+   * connected (because we need a valid low speed indication).
+   */
+
+  DEBUGASSERT(priv && epdesc && ep && priv->connected);
+
+  /* We must have exclusive access to the ED pool, the bulk list, the periodic list
+   * and the interrupt table.
+   */
+
+  lpc54_takesem(&priv->exclsem);
+
+  /* Take the next ED from the beginning of the free list */
+
+  ed = (struct lpc54_ed_s *)g_edfree;
+  if (ed)
+    {
+      /* Remove the ED from the freelist */
+
+      g_edfree = ((struct lpc54_list_s *)ed)->flink;
+
+      /* Configure the endpoint descriptor. */
+
+      memset((void *)ed, 0, sizeof(struct lpc54_ed_s));
+
+      hport = epdesc->hport;
+      ed->hw.ctrl = (uint32_t)(hport->funcaddr)      << ED_CONTROL_FA_SHIFT |
+                    (uint32_t)(epdesc->addr)         << ED_CONTROL_EN_SHIFT |
+                    (uint32_t)(epdesc->mxpacketsize) << ED_CONTROL_MPS_SHIFT;
+
+      /* Get the direction of the endpoint.  For control endpoints, the
+       * direction is in the TD.
+       */
+
+      if (epdesc->xfrtype == USB_EP_ATTR_XFER_CONTROL)
+        {
+          ed->hw.ctrl |= ED_CONTROL_D_TD1;
+        }
+      else if (epdesc->in)
+        {
+          ed->hw.ctrl |= ED_CONTROL_D_IN;
+        }
+      else
+        {
+          ed->hw.ctrl |= ED_CONTROL_D_OUT;
+        }
+
+      /* Check for a low-speed device */
+
+      if (hport->speed == USB_SPEED_LOW)
+        {
+          ed->hw.ctrl |= ED_CONTROL_S;
+        }
+
+      /* Set the transfer type */
+
+      ed->xfrtype = epdesc->xfrtype;
+
+      /* Special Case isochronous transfer types */
+
+#if 0 /* Isochronous transfers not yet supported */
+      if (ed->xfrtype == USB_EP_ATTR_XFER_ISOC)
+        {
+          ed->hw.ctrl |= ED_CONTROL_F;
+        }
+#endif
+      uinfo("EP%d CTRL:%08x\n", epdesc->addr, ed->hw.ctrl);
+
+      /* Initialize the semaphore that is used to wait for the endpoint
+       * WDH event. The wdhsem semaphore is used for signaling and, hence,
+       * should not have priority inheritance enabled.
+       */
+
+      nxsem_init(&ed->wdhsem, 0, 0);
+      nxsem_setprotocol(&ed->wdhsem, SEM_PRIO_NONE);
+
+      /* Link the common tail TD to the ED's TD list */
+
+      ed->hw.headp = (uint32_t)TDTAIL;
+      ed->hw.tailp = (uint32_t)TDTAIL;
+
+      /* Now add the endpoint descriptor to the appropriate list */
+
+      switch (ed->xfrtype)
+        {
+        case USB_EP_ATTR_XFER_CONTROL:
+          ret = lpc54_addctrled(priv, ed);
+          break;
+
+        case USB_EP_ATTR_XFER_BULK:
+          ret = lpc54_addbulked(priv, ed);
+          break;
+
+        case USB_EP_ATTR_XFER_INT:
+          ret = lpc54_addinted(priv, epdesc, ed);
+          break;
+
+        case USB_EP_ATTR_XFER_ISOC:
+          ret = lpc54_addisoced(priv, epdesc, ed);
+          break;
+
+        default:
+          ret = -EINVAL;
+          break;
+        }
+
+      /* Was the ED successfully added? */
+
+      if (ret < 0)
+        {
+          /* No.. destroy it and report the error */
+
+          uerr("ERROR: Failed to queue ED for transfer type: %d\n", ed->xfrtype);
+          nxsem_destroy(&ed->wdhsem);
+          lpc54_edfree(ed);
+        }
+      else
+        {
+          /* Yes.. return an opaque reference to the ED */
+
+          *ep = (usbhost_ep_t)ed;
+        }
+    }
+
+  lpc54_givesem(&priv->exclsem);
+  return ret;
+}
+
+/************************************************************************************
+ * Name: lpc54_epfree
+ *
+ * Description:
+ *   Free and endpoint previously allocated by DRVR_EPALLOC.
+ *
+ * Input Parameters:
+ *   drvr - The USB host driver instance obtained as a parameter from the call to
+ *      the class create() method.
+ *   ep - The endpint to be freed.
+ *
+ * Returned Value:
+ *   On success, zero (OK) is returned. On a failure, a negated errno value is
+ *   returned indicating the nature of the failure
+ *
+ * Assumptions:
+ *   This function will *not* be called from an interrupt handler.
+ *
+ ************************************************************************************/
+
+static int lpc54_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep)
+{
+  struct lpc54_usbhost_s *priv = (struct lpc54_usbhost_s *)drvr;
+  struct lpc54_ed_s      *ed   = (struct lpc54_ed_s *)ep;
+  int                     ret;
+
+  /* There should not be any pending, real TDs linked to this ED */
+
+  DEBUGASSERT(ed && (ed->hw.headp & ED_HEADP_ADDR_MASK) == LPC54_TDTAIL_ADDR);
+
+  /* We must have exclusive access to the ED pool, the bulk list, the periodic list
+   * and the interrupt table.
+   */
+
+  lpc54_takesem(&priv->exclsem);
+
+  /* Remove the ED to the correct list depending on the trasfer type */
+
+  switch (ed->xfrtype)
+    {
+    case USB_EP_ATTR_XFER_CONTROL:
+      ret = lpc54_remctrled(priv, ed);
+      break;
+
+    case USB_EP_ATTR_XFER_BULK:
+      ret = lpc54_rembulked(priv, ed);
+      break;
+
+    case USB_EP_ATTR_XFER_INT:
+      ret = lpc54_reminted(priv, ed);
+      break;
+
+    case USB_EP_ATTR_XFER_ISOC:
+      ret = lpc54_remisoced(priv, ed);
+      break;
+
+    default:
+      ret = -EINVAL;
+      break;
+    }
+
+  /* Destroy the semaphore */
+
+  nxsem_destroy(&ed->wdhsem);
+
+  /* Put the ED back into the free list */
+
+  lpc54_edfree(ed);
+  lpc54_givesem(&priv->exclsem);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: lpc54_alloc
+ *
+ * Description:
+ *   Some hardware supports special memory in which request and descriptor data can
+ *   be accessed more efficiently.  This method provides a mechanism to allocate
+ *   the request/descriptor memory.  If the underlying hardware does not support
+ *   such "special" memory, this functions may simply map to kmm_malloc.
+ *
+ *   This interface was optimized under a particular assumption.  It was assumed
+ *   that the driver maintains a pool of small, pre-allocated buffers for descriptor
+ *   traffic.  NOTE that size is not an input, but an output:  The size of the
+ *   pre-allocated buffer is returned.
+ *
+ * Input Parameters:
+ *   drvr - The USB host driver instance obtained as a parameter from the call to
+ *      the class create() method.
+ *   buffer - The address of a memory location provided by the caller in which to
+ *     return the allocated buffer memory address.
+ *   maxlen - The address of a memory location provided by the caller in which to
+ *     return the maximum size of the allocated buffer memory.
+ *
+ * Returned Value:
+ *   On success, zero (OK) is returned. On a failure, a negated errno value is
+ *   returned indicating the nature of the failure
+ *
+ * Assumptions:
+ *   - Called from a single thread so no mutual exclusion is required.
+ *   - Never called from an interrupt handler.
+ *
+ ****************************************************************************/
+
+static int lpc54_alloc(struct usbhost_driver_s *drvr,
+                       uint8_t **buffer, size_t *maxlen)
+{
+  struct lpc54_usbhost_s *priv = (struct lpc54_usbhost_s *)drvr;
+  DEBUGASSERT(priv && buffer && maxlen);
+  int ret = -ENOMEM;
+
+  /* We must have exclusive access to the transfer buffer pool */
+
+  lpc54_takesem(&priv->exclsem);
+
+  *buffer = lpc54_tballoc();
+  if (*buffer)
+    {
+      *maxlen = CONFIG_LPC54_OHCI_TDBUFSIZE;
+      ret = OK;
+    }
+
+  lpc54_givesem(&priv->exclsem);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: lpc54_free
+ *
+ * Description:
+ *   Some hardware supports special memory in which request and descriptor data can
+ *   be accessed more efficiently.  This method provides a mechanism to free that
+ *   request/descriptor memory.  If the underlying hardware does not support
+ *   such "special" memory, this functions may simply map to kmm_free().
+ *
+ * Input Parameters:
+ *   drvr - The USB host driver instance obtained as a parameter from the call to
+ *      the class create() method.
+ *   buffer - The address of the allocated buffer memory to be freed.
+ *
+ * Returned Value:
+ *   On success, zero (OK) is returned. On a failure, a negated errno value is
+ *   returned indicating the nature of the failure
+ *
+ * Assumptions:
+ *   - Never called from an interrupt handler.
+ *
+ ****************************************************************************/
+
+static int lpc54_free(struct usbhost_driver_s *drvr, uint8_t *buffer)
+{
+  struct lpc54_usbhost_s *priv = (struct lpc54_usbhost_s *)drvr;
+  DEBUGASSERT(buffer);
+
+  /* We must have exclusive access to the transfer buffer pool */
+
+  lpc54_takesem(&priv->exclsem);
+  lpc54_tbfree(buffer);
+  lpc54_givesem(&priv->exclsem);
+  return OK;
+}
+
+/************************************************************************************
+ * Name: lpc54_ioalloc
+ *
+ * Description:
+ *   Some hardware supports special memory in which larger IO buffers can
+ *   be accessed more efficiently.  This method provides a mechanism to allocate
+ *   the request/descriptor memory.  If the underlying hardware does not support
+ *   such "special" memory, this functions may simply map to kmm_malloc.
+ *
+ *   This interface differs from DRVR_ALLOC in that the buffers are variable-sized.
+ *
+ * Input Parameters:
+ *   drvr - The USB host driver instance obtained as a parameter from the call to
+ *      the class create() method.
+ *   buffer - The address of a memory location provided by the caller in which to
+ *     return the allocated buffer memory address.
+ *   buflen - The size of the buffer required.
+ *
+ * Returned Value:
+ *   On success, zero (OK) is returned. On a failure, a negated errno value is
+ *   returned indicating the nature of the failure
+ *
+ * Assumptions:
+ *   This function will *not* be called from an interrupt handler.
+ *
+ ************************************************************************************/
+
+static int lpc54_ioalloc(struct usbhost_driver_s *drvr,
+                         uint8_t **buffer, size_t buflen)
+{
+  DEBUGASSERT(drvr && buffer);
+
+#if LPC54_IOBUFFERS > 0
+  if (buflen <= CONFIG_LPC54_OHCI_IOBUFSIZE)
+    {
+      uint8_t *alloc = lpc54_allocio();
+      if (alloc)
+        {
+          *buffer = alloc;
+          return OK;
+        }
+    }
+
+  return -ENOMEM;
+#else
+  return -ENOSYS;
+#endif
+}
+
+/************************************************************************************
+ * Name: lpc54_iofree
+ *
+ * Description:
+ *   Some hardware supports special memory in which IO data can  be accessed more
+ *   efficiently.  This method provides a mechanism to free that IO buffer
+ *   memory.  If the underlying hardware does not support such "special" memory,
+ *   this functions may simply map to kmm_free().
+ *
+ * Input Parameters:
+ *   drvr - The USB host driver instance obtained as a parameter from the call to
+ *      the class create() method.
+ *   buffer - The address of the allocated buffer memory to be freed.
+ *
+ * Returned Value:
+ *   On success, zero (OK) is returned. On a failure, a negated errno value is
+ *   returned indicating the nature of the failure
+ *
+ * Assumptions:
+ *   This function will *not* be called from an interrupt handler.
+ *
+ ************************************************************************************/
+
+static int lpc54_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer)
+{
+  DEBUGASSERT(drvr && buffer);
+
+#if LPC54_IOBUFFERS > 0
+  lpc54_freeio(buffer);
+  return OK;
+#else
+  return -ENOSYS;
+#endif
+}
+
+/****************************************************************************
+ * Name: lpc54_ctrlin and lpc54_ctrlout
+ *
+ * Description:
+ * Description:
+ *   Process a IN or OUT request on the control endpoint.  These methods
+ *   will enqueue the request and wait for it to complete.  Only one transfer may be
+ *   queued; Neither these methods nor the transfer() method can be called again
+ *   until the control transfer functions returns.
+ *
+ *   These are blocking methods; these functions will not return until the
+ *   control transfer has completed.
+ *
+ * Input Parameters:
+ *   drvr - The USB host driver instance obtained as a parameter from the call to
+ *      the class create() method.
+ *   ep0 - The control endpoint to send/receive the control request.
+ *   req - Describes the request to be sent.  This request must lie in memory
+ *      created by DRVR_ALLOC.
+ *   buffer - A buffer used for sending the request and for returning any
+ *     responses.  This buffer must be large enough to hold the length value
+ *     in the request description. buffer must have been allocated using DRVR_ALLOC.
+ *
+ *   NOTE: On an IN transaction, req and buffer may refer to the same allocated
+ *   memory.
+ *
+ * Returned Value:
+ *   On success, zero (OK) is returned. On a failure, a negated errno value is
+ *   returned indicating the nature of the failure
+ *
+ * Assumptions:
+ *   - Called from a single thread so no mutual exclusion is required.
+ *   - Never called from an interrupt handler.
+ *
+ ****************************************************************************/
+
+static int lpc54_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
+                        const struct usb_ctrlreq_s *req,
+                        uint8_t *buffer)
+{
+  struct lpc54_usbhost_s *priv = (struct lpc54_usbhost_s *)drvr;
+  struct lpc54_ed_s *ed = (struct lpc54_ed_s *)ep0;
+  uint16_t len;
+  int  ret;
+
+  DEBUGASSERT(priv != NULL && ed != NULL && req != NULL);
+
+  uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
+        req->type, req->req, req->value[1], req->value[0],
+        req->index[1], req->index[0], req->len[1], req->len[0]);
+
+  /* We must have exclusive access to EP0 and the control list */
+
+  lpc54_takesem(&priv->exclsem);
+
+  len = lpc54_getle16(req->len);
+  ret = lpc54_ctrltd(priv, ed, GTD_STATUS_DP_SETUP, (uint8_t *)req, USB_SIZEOF_CTRLREQ);
+  if (ret == OK)
+    {
+      if (len)
+        {
+          ret = lpc54_ctrltd(priv, ed, GTD_STATUS_DP_IN, buffer, len);
+        }
+
+      if (ret == OK)
+        {
+          ret = lpc54_ctrltd(priv, ed, GTD_STATUS_DP_OUT, NULL, 0);
+        }
+    }
+
+  lpc54_givesem(&priv->exclsem);
+  return ret;
+}
+
+static int lpc54_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
+                         const struct usb_ctrlreq_s *req,
+                         const uint8_t *buffer)
+{
+  struct lpc54_usbhost_s *priv = (struct lpc54_usbhost_s *)drvr;
+  struct lpc54_ed_s *ed = (struct lpc54_ed_s *)ep0;
+  uint16_t len;
+  int  ret;
+
+  DEBUGASSERT(priv != NULL && ed != NULL && req != NULL);
+
+  uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n",
+        req->type, req->req, req->value[1], req->value[0],
+        req->index[1], req->index[0], req->len[1], req->len[0]);
+
+  /* We must have exclusive access to EP0 and the control list */
+
+  lpc54_takesem(&priv->exclsem);
+
+  len = lpc54_getle16(req->len);
+  ret = lpc54_ctrltd(priv, ed, GTD_STATUS_DP_SETUP, (uint8_t *)req, USB_SIZEOF_CTRLREQ);
+  if (ret == OK)
+    {
+      if (len)
+        {
+          ret = lpc54_ctrltd(priv, ed, GTD_STATUS_DP_OUT, (uint8_t *)buffer, len);
+        }
+
+      if (ret == OK)
+        {
+          ret = lpc54_ctrltd(priv, ed, GTD_STATUS_DP_IN, NULL, 0);
+        }
+    }
+
+  lpc54_givesem(&priv->exclsem);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: lpc54_transfer_common
+ *
+ * Description:
+ *   Initiate a request to handle a transfer descriptor.  This method will
+ *   enqueue the transfer request and return immediately
+ *
+ * Input Parameters:
+ *   priv - Internal driver state structure.
+ *   ed - The IN or OUT endpoint descriptor for the device endpoint on which to
+ *      perform the transfer.
+ *   buffer - A buffer containing the data to be sent (OUT endpoint) or received
+ *     (IN endpoint).  buffer must have been allocated using DRVR_ALLOC
+ *   buflen - The length of the data to be sent or received.
+ *
+ * Returned Value:
+ *   On success, zero (OK) is returned. On a failure, a negated errno value is
+ *   returned indicating the nature of the failure.
+ *
+ *
+ * Assumptions:
+ *   - Called from a single thread so no mutual exclusion is required.
+ *   - Never called from an interrupt handler.
+ *
+ ****************************************************************************/
+
+static int lpc54_transfer_common(struct lpc54_usbhost_s *priv,
+                                 struct lpc54_ed_s *ed, uint8_t *buffer,
+                                 size_t buflen)
+{
+  struct lpc54_xfrinfo_s *xfrinfo;
+  uint32_t dirpid;
+  uint32_t regval;
+  bool in;
+  int ret;
+
+  xfrinfo = ed->xfrinfo;
+  in      = (ed->hw.ctrl & ED_CONTROL_D_MASK) == ED_CONTROL_D_IN;
+
+  uinfo("EP%u %s toggle:%u maxpacket:%u buflen:%lu\n",
+        (ed->hw.ctrl  & ED_CONTROL_EN_MASK) >> ED_CONTROL_EN_SHIFT,
+        in ? "IN" : "OUT",
+        (ed->hw.headp & ED_HEADP_C) != 0 ? 1 : 0,
+        (ed->hw.ctrl  & ED_CONTROL_MPS_MASK) >> ED_CONTROL_MPS_SHIFT,
+        (unsigned long)buflen);
+
+  /* Get the direction of the endpoint */
+
+  if (in)
+    {
+      dirpid = GTD_STATUS_DP_IN;
+    }
+  else
+    {
+      dirpid = GTD_STATUS_DP_OUT;
+    }
+
+  /* Then enqueue the transfer */
+
+  xfrinfo->tdstatus = TD_CC_NOERROR;
+  ret = lpc54_enqueuetd(priv, ed, dirpid, GTD_STATUS_T_TOGGLE, buffer, buflen);
+  if (ret == OK)
+    {
+      /* BulkListFilled. This bit is used to indicate whether there are any
+       * TDs on the Bulk list.
+       */
+
+      if (ed->xfrtype == USB_EP_ATTR_XFER_BULK)
+        {
+          regval  = lpc54_getreg(LPC54_OHCI_CMDST);
+          regval |= OHCI_CMDST_BLF;
+          lpc54_putreg(regval, LPC54_OHCI_CMDST);
+        }
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: lpc54_dma_alloc
+ *
+ * Description:
+ *   Allocate DMA memory to perform a transfer, copying user data as necessary
+ *
+ * Input Parameters:
+ *   priv - Internal driver state structure.
+ *   ed - The IN or OUT endpoint descriptor for the device endpoint on which to
+ *      perform the transfer.
+ *   userbuffer - The user buffer containing the data to be sent (OUT endpoint)
+ *      or received (IN endpoint).
+ *   buflen - The length of the data to be sent or received.
+ *   alloc - The location to return the allocated DMA buffer.
+ *
+ * Returned Value:
+ *   On success, zero (OK) is returned. On a failure, a negated errno value is
+ *   returned indicating the nature of the failure.
+ *
+ * Assumptions:
+ *   - Called from a single thread so no mutual exclusion is required.
+ *   - Never called from an interrupt handler.
+ *
+ ****************************************************************************/
+
+#if LPC54_IOBUFFERS > 0
+static int lpc54_dma_alloc(struct lpc54_usbhost_s *priv,
+                           struct lpc54_ed_s *ed, uint8_t *userbuffer,
+                           size_t buflen, uint8_t **alloc)
+{
+  uint8_t *newbuffer;
+
+  if ((uintptr_t)userbuffer < LPC54_SRAM_BANK0 ||
+      (uintptr_t)userbuffer >= (LPC54_SRAM_BANK0 + LPC54_BANK0_SIZE + LPC54_BANK1_SIZE))
+    {
+      /* Will the transfer fit in an IO buffer? */
+
+      if (buflen > CONFIG_LPC54_OHCI_IOBUFSIZE)
+        {
+          uinfo("buflen (%d) > IO buffer size (%d)\n",
+                 buflen, CONFIG_LPC54_OHCI_IOBUFSIZE);
+          return -ENOMEM;
+        }
+
+      /* Allocate an IO buffer in AHB SRAM */
+
+      newbuffer = lpc54_allocio();
+      if (!newbuffer)
+        {
+          uinfo("IO buffer allocation failed\n");
+          return -ENOMEM;
+        }
+
+      /* If this is an OUT transaction, copy the user data into the AHB
+       * SRAM IO buffer.  Sad... so inefficient.  But without exposing
+       * the AHB SRAM to the final, end-user client I don't know of any
+       * way around this copy.
+       */
+
+      if ((ed->hw.ctrl & ED_CONTROL_D_MASK) != ED_CONTROL_D_IN)
+        {
+          memcpy(newbuffer, userbuffer, buflen);
+        }
+
+      /* Return the allocated buffer */
+
+      *alloc = newbuffer;
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: lpc54_dma_free
+ *
+ * Description:
+ *   Free allocated DMA memory.
+ *
+ * Input Parameters:
+ *   priv - Internal driver state structure.
+ *   ed - The IN or OUT endpoint descriptor for the device endpoint on which to
+ *      perform the transfer.
+ *   userbuffer - The user buffer containing the data to be sent (OUT endpoint)
+ *      or received (IN endpoint).
+ *   buflen - The length of the data to be sent or received.
+ *   alloc - The allocated DMA buffer to be freed.
+ *
+ * Returned Value:
+ *   On success, zero (OK) is returned. On a failure, a negated errno value is
+ *   returned indicating the nature of the failure.
+ *
+ * Assumptions:
+ *   - Called from a single thread so no mutual exclusion is required.
+ *   - Never called from an interrupt handler.
+ *
+ ****************************************************************************/
+
+static void lpc54_dma_free(struct lpc54_usbhost_s *priv,
+                           struct lpc54_ed_s *ed, uint8_t *userbuffer,
+                           size_t buflen, uint8_t *newbuffer)
+{
+  irqstate_t flags;
+
+  /* Could be called from the interrupt level */
+
+  flags = enter_critical_section();
+  if (userbuffer && newbuffer)
+    {
+      /* If this is an IN transaction, get the user data from the AHB
+       * SRAM IO buffer.  Sad... so inefficient.  But without exposing
+       * the AHB SRAM to the final, end-user client I don't know of any
+       * way around this copy.
+       */
+
+      if ((ed->hw.ctrl & ED_CONTROL_D_MASK) == ED_CONTROL_D_IN)
+        {
+          memcpy(userbuffer, newbuffer, buflen);
+        }
+
+      /* Then free the temporary I/O buffer */
+
+      lpc54_freeio(newbuffer);
+    }
+
+  leave_critical_section(flags);
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc54_transfer
+ *
+ * Description:
+ *   Process a request to handle a transfer descriptor.  This method will
+ *   enqueue the transfer request, blocking until the transfer completes. Only
+ *   one transfer may be  queued; Neither this method nor the ctrlin or
+ *   ctrlout methods can be called again until this function returns.
+ *
+ *   This is a blocking method; this functions will not return until the
+ *   transfer has completed.
+ *
+ * Input Parameters:
+ *   drvr - The USB host driver instance obtained as a parameter from the call to
+ *      the class create() method.
+ *   ep - The IN or OUT endpoint descriptor for the device endpoint on which to
+ *      perform the transfer.
+ *   buffer - A buffer containing the data to be sent (OUT endpoint) or received
+ *     (IN endpoint).  buffer must have been allocated using DRVR_ALLOC
+ *   buflen - The length of the data to be sent or received.
+ *
+ * Returned Value:
+ *   On success, a non-negative value is returned that indicates the number
+ *   of bytes successfully transferred.  On a failure, a negated errno value is
+ *   returned that indicates the nature of the failure:
+ *
+ *     EAGAIN - If devices NAKs the transfer (or NYET or other error where
+ *              it may be appropriate to restart the entire transaction).
+ *     EPERM  - If the endpoint stalls
+ *     EIO    - On a TX or data toggle error
+ *     EPIPE  - Overrun errors
+ *
+ * Assumptions:
+ *   - Called from a single thread so no mutual exclusion is required.
+ *   - Never called from an interrupt handler.
+ *
+ ****************************************************************************/
+
+static ssize_t lpc54_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
+                              uint8_t *buffer, size_t buflen)
+{
+  struct lpc54_usbhost_s *priv = (struct lpc54_usbhost_s *)drvr;
+  struct lpc54_ed_s *ed = (struct lpc54_ed_s *)ep;
+  struct lpc54_xfrinfo_s *xfrinfo;
+#if LPC54_IOBUFFERS > 0
+  uint8_t *alloc = NULL;
+  uint8_t *userbuffer = NULL;
+#endif
+  ssize_t nbytes;
+  int ret;
+
+  DEBUGASSERT(priv && ed && buffer && buflen > 0);
+
+  /* We must have exclusive access to the endpoint, the TD pool, the I/O buffer
+   * pool, the bulk and interrupt lists, and the HCCA interrupt table.
+   */
+
+  lpc54_takesem(&priv->exclsem);
+
+  /* Allocate a structure to retain the information needed when the transfer
+   * completes.
+   */
+
+  DEBUGASSERT(ed->xfrinfo == NULL);
+
+  xfrinfo = lpc54_alloc_xfrinfo();
+  if (xfrinfo == NULL)
+    {
+      uerr("ERROR: lpc54_alloc_xfrinfo failed\n");
+      nbytes = -ENOMEM;
+      goto errout_with_sem;
+    }
+
+  /* Initialize the transfer structure */
+
+  memset(xfrinfo, 0, sizeof(struct lpc54_xfrinfo_s));
+  xfrinfo->buffer = buffer;
+  xfrinfo->buflen = buflen;
+
+  ed->xfrinfo = xfrinfo;
+
+#if LPC54_IOBUFFERS > 0
+  /* Allocate an IO buffer if the user buffer does not lie in AHB SRAM */
+
+  ret = lpc54_dma_alloc(priv, ed, buffer, buflen, &alloc);
+  if (ret < 0)
+    {
+      uerr("ERROR: lpc54_dma_alloc failed: %d\n", ret);
+      nbytes = (ssize_t)ret;
+      goto errout_with_xfrinfo;
+    }
+
+  /* If a buffer was allocated, then use it instead of the callers buffer */
+
+  if (alloc)
+    {
+      userbuffer = buffer;
+      buffer  = alloc;
+    }
+#endif
+
+  /* Set the request for the Writeback Done Head event well BEFORE enabling the
+   * transfer.
+   */
+
+  ret = lpc54_wdhwait(priv, ed);
+  if (ret < 0)
+    {
+      uerr("ERROR: Device disconnected\n");
+      nbytes = (ssize_t)ret;
+      goto errout_with_buffers;
+    }
+
+  /* Set up the transfer */
+
+  ret = lpc54_transfer_common(priv, ed, buffer, buflen);
+  if (ret < 0)
+    {
+      uerr("ERROR: lpc54_transfer_common failed: %d\n", ret);
+      nbytes = (ssize_t)ret;
+      goto errout_with_wdhwait;
+    }
+
+  /* Wait for the Writeback Done Head interrupt */
+
+  lpc54_takesem(&ed->wdhsem);
+
+  /* Check the TD completion status bits */
+
+  if (xfrinfo->tdstatus == TD_CC_NOERROR)
+    {
+      /* Return the number of bytes successfully transferred */
+
+      nbytes = xfrinfo->xfrd;
+      DEBUGASSERT(nbytes >= 0 && nbytes <= buflen);
+    }
+  else
+    {
+      /* Map the bad completion status to something that a class driver
+       * might understand.
+       */
+
+      uerr("ERROR: Bad TD completion status: %d\n", xfrinfo->tdstatus);
+
+      switch (xfrinfo->tdstatus)
+        {
+        case TD_CC_STALL:
+          nbytes = -EPERM;
+          break;
+
+        case TD_CC_USER:
+          nbytes = -ESHUTDOWN;
+          break;
+
+        default:
+          nbytes = -EIO;
+          break;
+        }
+     }
+
+errout_with_wdhwait:
+  /* Make sure that there is no outstanding request on this endpoint */
+
+  xfrinfo->wdhwait = false;
+
+errout_with_buffers:
+#if LPC54_IOBUFFERS > 0
+  /* Free any temporary IO buffers */
+
+  lpc54_dma_free(priv, ed, userbuffer, buflen, alloc);
+#endif
+
+errout_with_xfrinfo:
+  /* Make sure that there is no outstanding request on this endpoint */
+
+  lpc54_free_xfrinfo(xfrinfo);
+  ed->xfrinfo = NULL;
+
+errout_with_sem:
+  lpc54_givesem(&priv->exclsem);
+  return nbytes;
+}
+
+/****************************************************************************
+ * Name: lpc54_asynch_completion
+ *
+ * Description:
+ *   This function is called at the interrupt level when an asynchronous
+ *   transfer completes.  It performs the pending callback.
+ *
+ * Input Parameters:
+ *   priv - Internal driver state structure.
+ *   ep - The IN or OUT endpoint descriptor for the device endpoint on which the
+ *      transfer was performed.
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   - Called from the interrupt level
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_OHCI_ASYNCH
+static void lpc54_asynch_completion(struct lpc54_usbhost_s *priv,
+                                    struct lpc54_ed_s *ed)
+{
+  struct lpc54_xfrinfo_s *xfrinfo;
+  usbhost_asynch_t callback;
+  void *arg;
+  ssize_t nbytes;
+
+  DEBUGASSERT(ed != NULL && ed->xfrinfo != NULL);
+  xfrinfo = ed->xfrinfo;
+
+  DEBUGASSERT(xfrinfo->wdhwait == false &&  xfrinfo->callback != NULL &&
+              xfrinfo->buffer != NULL && xfrinfo->buflen > 0);
+
+  /* Check the TD completion status bits */
+
+  if (xfrinfo->tdstatus == TD_CC_NOERROR)
+    {
+      /* Provide the number of bytes successfully transferred */
+
+      nbytes = xfrinfo->xfrd;
+    }
+  else
+    {
+      /* Map the bad completion status to something that a class driver
+       * might understand.
+       */
+
+      uerr("ERROR: Bad TD completion status: %d\n", xfrinfo->tdstatus);
+
+      switch (xfrinfo->tdstatus)
+        {
+        case TD_CC_STALL:
+          nbytes = -EPERM;
+          break;
+
+        case TD_CC_USER:
+          nbytes = -ESHUTDOWN;
+          break;
+
+        default:
+          nbytes = -EIO;
+          break;
+        }
+     }
+
+#if LPC54_IOBUFFERS > 0
+  /* Free any temporary IO buffers */
+
+  lpc54_dma_free(priv, ed, xfrinfo->buffer, xfrinfo->buflen, xfrinfo->alloc);
+#endif
+
+  /* Extract the callback information before freeing the buffer */
+
+  callback = xfrinfo->callback;
+  arg = xfrinfo->arg;
+
+  /* Make sure that there is no outstanding request on this endpoint */
+
+  lpc54_free_xfrinfo(xfrinfo);
+  ed->xfrinfo  = NULL;
+
+  /* Then perform the callback */
+
+  callback(arg, nbytes);
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc54_asynch
+ *
+ * Description:
+ *   Process a request to handle a transfer descriptor.  This method will
+ *   enqueue the transfer request and return immediately.  When the transfer
+ *   completes, the callback will be invoked with the provided transfer.
+ *   This method is useful for receiving interrupt transfers which may come
+ *   infrequently.
+ *
+ *   Only one transfer may be queued; Neither this method nor the ctrlin or
+ *   ctrlout methods can be called again until the transfer completes.
+ *
+ * Input Parameters:
+ *   drvr - The USB host driver instance obtained as a parameter from the call to
+ *      the class create() method.
+ *   ep - The IN or OUT endpoint descriptor for the device endpoint on which to
+ *      perform the transfer.
+ *   buffer - A buffer containing the data to be sent (OUT endpoint) or received
+ *     (IN endpoint).  buffer must have been allocated using DRVR_ALLOC
+ *   buflen - The length of the data to be sent or received.
+ *   callback - This function will be called when the transfer completes.
+ *   arg - The arbitrary parameter that will be passed to the callback function
+ *     when the transfer completes.
+ *
+ * Returned Value:
+ *   On success, zero (OK) is returned. On a failure, a negated errno value is
+ *   returned indicating the nature of the failure
+ *
+ * Assumptions:
+ *   - Called from a single thread so no mutual exclusion is required.
+ *   - Never called from an interrupt handler.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_OHCI_ASYNCH
+static int lpc54_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
+                        uint8_t *buffer, size_t buflen,
+                        usbhost_asynch_t callback, void *arg)
+{
+  struct lpc54_usbhost_s *priv = (struct lpc54_usbhost_s *)drvr;
+  struct lpc54_ed_s *ed = (struct lpc54_ed_s *)ep;
+  struct lpc54_xfrinfo_s *xfrinfo;
+  int ret;
+
+  DEBUGASSERT(priv && ed && ed->xfrinfo == NULL && buffer && buflen > 0 && callback);
+
+  /* We must have exclusive access to the endpoint, the TD pool, the I/O buffer
+   * pool, the bulk and interrupt lists, and the HCCA interrupt table.
+   */
+
+  lpc54_takesem(&priv->exclsem);
+
+  /* Allocate a structure to retain the information needed when the asynchronous
+   * transfer completes.
+   */
+
+  DEBUGASSERT(ed->xfrinfo == NULL);
+
+  xfrinfo = lpc54_alloc_xfrinfo();
+  if (xfrinfo == NULL)
+    {
+      uerr("ERROR: lpc54_alloc_xfrinfo failed\n");
+      ret = -ENOMEM;
+      goto errout_with_sem;
+    }
+
+  /* Initialize the transfer structure */
+
+  memset(xfrinfo, 0, sizeof(struct lpc54_xfrinfo_s));
+  xfrinfo->buffer   = buffer;
+  xfrinfo->buflen   = buflen;
+  xfrinfo->callback = callback;
+  xfrinfo->arg      = arg;
+
+  ed->xfrinfo       = xfrinfo;
+
+#if LPC54_IOBUFFERS > 0
+  /* Allocate an IO buffer if the user buffer does not lie in AHB SRAM */
+
+  ret = lpc54_dma_alloc(priv, ed, buffer, buflen, &xfrinfo->alloc);
+  if (ret < 0)
+    {
+      uerr("ERROR: lpc54_dma_alloc failed: %d\n", ret);
+      goto errout_with_sem;
+    }
+
+  /* If a buffer was allocated, then use it instead of the callers buffer */
+
+  if (xfrinfo->alloc)
+    {
+      buffer  = xfrinfo->alloc;
+    }
+#endif
+
+  /* Set up the transfer */
+
+  ret = lpc54_transfer_common(priv, ed, buffer, buflen);
+  if (ret < 0)
+    {
+      uerr("ERROR: lpc54_transfer_common failed: %d\n", ret);
+      goto errout_with_asynch;
+    }
+
+  /* And return now.  The callback will be invoked when the transfer
+   * completes.
+   */
+
+  lpc54_givesem(&priv->exclsem);
+  return OK;
+
+errout_with_asynch:
+#if LPC54_IOBUFFERS > 0
+  /* Free any temporary IO buffers */
+
+  lpc54_dma_free(priv, ed, buffer, buflen, xfrinfo->alloc);
+#endif
+
+  /* Free the transfer structure */
+
+  lpc54_free_xfrinfo(xfrinfo);
+  ed->xfrinfo = NULL;
+
+errout_with_sem:
+  lpc54_givesem(&priv->exclsem);
+  return ret;
+}
+#endif /* CONFIG_OHCI_ASYNCH */
+
+/************************************************************************************
+ * Name: lpc54_cancel
+ *
+ * Description:
+ *   Cancel a pending transfer on an endpoint.  Cancelled synchronous or
+ *   asynchronous transfer will complete normally with the error -ESHUTDOWN.
+ *
+ * Input Parameters:
+ *   drvr - The USB host driver instance obtained as a parameter from the call to
+ *      the class create() method.
+ *   ep - The IN or OUT endpoint descriptor for the device endpoint on which an
+ *      asynchronous transfer should be transferred.
+ *
+ * Returned Value:
+ *   On success, zero (OK) is returned. On a failure, a negated errno value is
+ *   returned indicating the nature of the failure.
+ *
+ ************************************************************************************/
+
+static int lpc54_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep)
+{
+#ifdef CONFIG_OHCI_ASYNCH
+  struct lpc54_usbhost_s *priv = (struct lpc54_usbhost_s *)drvr;
+#endif
+  struct lpc54_ed_s *ed = (struct lpc54_ed_s *)ep;
+  struct lpc54_gtd_s *td;
+  struct lpc54_gtd_s *next;
+  struct lpc54_xfrinfo_s *xfrinfo;
+  uint32_t ctrl;
+  irqstate_t flags;
+
+  DEBUGASSERT(drvr != NULL && ed != NULL);
+
+  /* These first steps must be atomic as possible */
+
+  flags = enter_critical_section();
+
+  /* It is possible there there is no transfer to be in progress */
+
+  xfrinfo = ed->xfrinfo;
+  if (xfrinfo)
+    {
+      /* It might be possible for no transfer to be in progress (callback == NULL
+       * and wdhwait == false)
+       */
+
+#ifdef CONFIG_OHCI_ASYNCH
+      if (xfrinfo->callback || xfrinfo->wdhwait)
+#else
+      if (xfrinfo->wdhwait)
+#endif
+        {
+          /* Control endpoints should not come through this path and
+           * isochronous endpoints are not yet implemented.  So we only have
+           * to distinguish bulk and interrupt endpoints.
+           */
+
+          if (ed->xfrtype == USB_EP_ATTR_XFER_BULK)
+            {
+              /* Disable bulk list processing while we modify the list */
+
+              ctrl  = lpc54_getreg(LPC54_OHCI_CTRL);
+              lpc54_putreg(ctrl & ~OHCI_CTRL_BLE, LPC54_OHCI_CTRL);
+
+              /* Remove the TDs attached to the ED, keeping the ED in the list */
+
+              td           = (struct lpc54_gtd_s *)(ed->hw.headp & ED_HEADP_ADDR_MASK);
+              ed->hw.headp = LPC54_TDTAIL_ADDR;
+              ed->xfrinfo  = NULL;
+
+              /* Re-enable bulk list processing, if it was enabled before */
+
+              lpc54_putreg(0, LPC54_OHCI_BULKED);
+              lpc54_putreg(ctrl, LPC54_OHCI_CTRL);
+            }
+          else
+            {
+              /* Remove the TDs attached to the ED, keeping the Ed in the list */
+
+              td           = (struct lpc54_gtd_s *)(ed->hw.headp & ED_HEADP_ADDR_MASK);
+              ed->hw.headp = LPC54_TDTAIL_ADDR;
+              ed->xfrinfo  = NULL;
+            }
+
+          /* Free all transfer descriptors that were connected to the ED.  In
+           * some race conditions with the hardware, this might be none.
+           */
+
+          while (td != (struct lpc54_gtd_s *)LPC54_TDTAIL_ADDR)
+            {
+              next = (struct lpc54_gtd_s *)td->hw.nexttd;
+              lpc54_tdfree(td);
+              td = next;
+            }
+
+          xfrinfo->tdstatus = TD_CC_USER;
+
+          /* If there is a thread waiting for the transfer to complete, then
+           * wake up the thread.
+           */
+
+          if (xfrinfo->wdhwait)
+            {
+#ifdef CONFIG_OHCI_ASYNCH
+              /* Yes.. there should not also be a callback scheduled */
+
+              DEBUGASSERT(xfrinfo->callback == NULL);
+#endif
+
+              /* Wake up the waiting thread */
+
+              lpc54_givesem(&ed->wdhsem);
+              xfrinfo->wdhwait = false;
+
+              /* And free the transfer structure */
+
+              lpc54_free_xfrinfo(xfrinfo);
+              ed->xfrinfo = NULL;
+            }
+#ifdef CONFIG_OHCI_ASYNCH
+          else
+            {
+              /* Otherwise, perform the callback and free the transfer structure */
+
+              lpc54_asynch_completion(priv, ed);
+            }
+#endif
+        }
+      else
+        {
+          /* Just free the transfer structure */
+
+          lpc54_free_xfrinfo(xfrinfo);
+          ed->xfrinfo = NULL;
+        }
+    }
+
+  /* Determine the return value */
+
+  leave_critical_section(flags);
+  return OK;
+}
+
+/************************************************************************************
+ * Name: lpc54_connect
+ *
+ * Description:
+ *   New connections may be detected by an attached hub.  This method is the
+ *   mechanism that is used by the hub class to introduce a new connection
+ *   and port description to the system.
+ *
+ * Input Parameters:
+ *   drvr - The USB host driver instance obtained as a parameter from the call to
+ *      the class create() method.
+ *   hport - The descriptor of the hub port that detected the connection
+ *      related event
+ *   connected - True: device connected; false: device disconnected
+ *
+ * Returned Value:
+ *   On success, zero (OK) is returned. On a failure, a negated errno value is
+ *   returned indicating the nature of the failure.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_OHCI_HUB
+static int lpc54_connect(FAR struct usbhost_driver_s *drvr,
+                         FAR struct usbhost_hubport_s *hport,
+                         bool connected)
+{
+  struct lpc54_usbhost_s *priv = (struct lpc54_usbhost_s *)drvr;
+  DEBUGASSERT(priv != NULL && hport != NULL);
+  irqstate_t flags;
+
+  /* Set the connected/disconnected flag */
+
+  hport->connected = connected;
+  uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO");
+
+  /* Report the connection event */
+
+  flags = enter_critical_section();
+  priv->hport = hport;
+  if (priv->pscwait)
+    {
+      priv->pscwait = false;
+      lpc54_givesem(&priv->pscsem);
+    }
+
+  leave_critical_section(flags);
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: lpc54_disconnect
+ *
+ * Description:
+ *   Called by the class when an error occurs and driver has been disconnected.
+ *   The USB host driver should discard the handle to the class instance (it is
+ *   stale) and not attempt any further interaction with the class driver instance
+ *   (until a new instance is received from the create() method).  The driver
+ *   should not called the class' disconnected() method.
+ *
+ * Input Parameters:
+ *   drvr - The USB host driver instance obtained as a parameter from the call to
+ *      the class create() method.
+ *   hport - The port from which the device is being disconnected.  Might be a port
+ *      on a hub.
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   - Only a single class bound to a single device is supported.
+ *   - Never called from an interrupt handler.
+ *
+ ****************************************************************************/
+
+static void lpc54_disconnect(struct usbhost_driver_s *drvr,
+                             struct usbhost_hubport_s *hport)
+{
+  DEBUGASSERT(hport != NULL);
+  hport->devclass = NULL;
+}
+
+/****************************************************************************
+ * Initialization
+ ****************************************************************************/
+/****************************************************************************
+ * Name: lpc54_ep0init
+ *
+ * Description:
+ *   Initialize ED for EP0, add it to the control ED list, and enable control
+ *   transfers.
+ *
+ * Input Parameters:
+ *   priv - private driver state instance.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void lpc54_ep0init(struct lpc54_usbhost_s *priv)
+{
+  /* Initialize the common tail TD. */
+
+  memset(TDTAIL, 0, sizeof(struct lpc54_gtd_s));
+  TDTAIL->ed              = EDCTRL;
+
+  /* Link the common tail TD to the ED's TD list */
+
+  memset(EDCTRL, 0, sizeof(struct lpc54_ed_s));
+  EDCTRL->hw.headp = (uint32_t)TDTAIL;
+  EDCTRL->hw.tailp = (uint32_t)TDTAIL;
+  EDCTRL->xfrtype  = USB_EP_ATTR_XFER_CONTROL;
+
+  /* Set the head of the control list to the NULL (for now). */
+
+  lpc54_putreg(0, LPC54_OHCI_CTRLHEADED);
+
+  /* Then add EP0 to the empty Control List */
+
+  lpc54_addctrled(priv, EDCTRL);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc54_usbhost_initialize
+ *
+ * Description:
+ *   Initialize USB host device controller hardware.
+ *
+ * Input Parameters:
+ *   controller -- If the device supports more than USB host controller, then
+ *     this identifies which controller is being initialized.  Normally, this
+ *     is just zero.
+ *
+ * Returned Value:
+ *   And instance of the USB host interface.  The controlling task should
+ *   use this interface to (1) call the wait() method to wait for a device
+ *   to be connected, and (2) call the enumerate() method to bind the device
+ *   to a class driver.
+ *
+ * Assumptions:
+ * - This function should called in the initialization sequence in order
+ *   to initialize the USB device functionality.
+ * - Class drivers should be initialized prior to calling this function.
+ *   Otherwise, there is a race condition if the device is already connected.
+ *
+ ****************************************************************************/
+
+struct usbhost_connection_s *lpc54_usbhost_initialize(int controller)
+{
+  struct lpc54_usbhost_s *priv = &g_usbhost;
+  struct usbhost_driver_s *drvr;
+  struct usbhost_hubport_s *hport;
+  struct lpc54_xfrinfo_s *xfrinfo;
+  uint32_t regval;
+  uint8_t *buffer;
+  irqstate_t flags;
+  int i;
+
+  /* Sanity checks.  NOTE: If certain OS features are enabled, it may be
+   * necessary to increase the size of LPC54_ED/TD_SIZE in lpc54_ohciram.h
+   */
+
+  DEBUGASSERT(controller == 0);
+  DEBUGASSERT(sizeof(struct lpc54_ed_s)  <= LPC54_ED_SIZE);
+  DEBUGASSERT(sizeof(struct lpc54_gtd_s) <= LPC54_TD_SIZE);
+
+  /* Initialize the state data structure */
+  /* Initialize the device operations */
+
+  drvr                 = &priv->drvr;
+  drvr->ep0configure   = lpc54_ep0configure;
+  drvr->epalloc        = lpc54_epalloc;
+  drvr->epfree         = lpc54_epfree;
+  drvr->alloc          = lpc54_alloc;
+  drvr->free           = lpc54_free;
+  drvr->ioalloc        = lpc54_ioalloc;
+  drvr->iofree         = lpc54_iofree;
+  drvr->ctrlin         = lpc54_ctrlin;
+  drvr->ctrlout        = lpc54_ctrlout;
+  drvr->transfer       = lpc54_transfer;
+#ifdef CONFIG_OHCI_ASYNCH
+  drvr->asynch         = lpc54_asynch;
+#endif
+  drvr->cancel         = lpc54_cancel;
+#ifdef CONFIG_OHCI_HUB
+  drvr->connect        = lpc54_connect;
+#endif
+  drvr->disconnect     = lpc54_disconnect;
+
+  /* Initialize the public port representation */
+
+  hport                = &priv->rhport.hport;
+  hport->drvr          = drvr;
+#ifdef CONFIG_OHCI_HUB
+  hport->parent        = NULL;
+#endif
+  hport->ep0           = EDCTRL;
+  hport->speed         = USB_SPEED_FULL;
+  hport->funcaddr      = 0;
+
+  /* Initialize function address generation logic */
+
+  usbhost_devaddr_initialize(&priv->rhport);
+
+  /* Initialize semaphores */
+
+  nxsem_init(&priv->pscsem,  0, 0);
+  nxsem_init(&priv->exclsem, 0, 1);
+
+  /* The pscsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  nxsem_setprotocol(&priv->pscsem, SEM_PRIO_NONE);
+
+#ifndef CONFIG_OHCI_INT_DISABLE
+  priv->ininterval  = MAX_PERINTERVAL;
+  priv->outinterval = MAX_PERINTERVAL;
+#endif
+  /* Enable the USB0 OHCI block:
+   *
+   * Power:  In the PDRUNCFG0 register, set bit PDEN_USB0_PHY. On reset, the
+   *   USB block is disabled (PDEN_USB0_PHY = 1).
+   * Clock:  To have the full-speed USB operating, select either the System
+   *   PLL, or USB PLL, or FRO clock output as the USB0 clock and the clock
+   *   must be 48 MHz. The CPU clock must be configured to a minimum
+   *   frequency of 12 MHz.  In AHBCLKCTRL2, enable both the USB0 host master
+   *   and host slave bits.
+   * Port control:  Clear DEV_ENABLE bit in Port Mode register to ensure that
+   *   the port is controlled by the USB0 host block. Set ID_EN to enable ID
+   *   pin pull-up.
+   * Configure GPIO pins.
+   * Reset: The USB0 Host AHB master and slave can be reset by toggling
+   *   USB0HMR_RST (bit 16) and USB0HSL_RST (bit17) in PRESETCTRL2.
+   * Wake-up:  Activity on the USB bus port can wake up the microcontroller
+   *   from deep-sleep mode.
+   * Interrupts: The USB0_IRQ interrupt is connected to interrupt slot #28
+   *   in the NVIC.  The USB0_NEEDCLK signal is connected to slot #27.
+   */
+#warning Missing logic
+
+  /* Set the OTG status and control register.  Bits 0:1 apparently mean:
+   *
+   *   00: U1=device, U2=host
+   *   01: U1=host, U2=host
+   *   10: reserved
+   *   11: U1=host, U2=device
+   *
+   * We need only select U1=host (Bit 0=1, Bit 1 is not used on LPC546x);
+   * NOTE: The PORTSEL clock needs to be enabled when accessing OTGSTCTRL
+   */
+
+  lpc54_putreg(1, LPC54_USBOTG_STCTRL);
+
+  /* Now we can turn off the PORTSEL clock */
+
+  lpc54_putreg((LPC54_CLKCTRL_ENABLES & ~USBOTG_CLK_PORTSELCLK), LPC54_USBOTG_CLKCTRL);
+
+  /* Configure I/O pins */
+
+  usbhost_dumpgpio();
+  lpc54_configgpio(GPIO_USB_DP);      /* Positive differential data */
+  lpc54_configgpio(GPIO_USB_DM);      /* Negative differential data */
+  lpc54_configgpio(GPIO_USB_UPLED);   /* GoodLink LED control signal */
+  lpc54_configgpio(GPIO_USB_PPWR);    /* Port Power enable signal for USB port */
+  lpc54_configgpio(GPIO_USB_PWRD);    /* Power Status for USB port (host power switch) */
+  lpc54_configgpio(GPIO_USB_OVRCR);   /* USB port Over-Current status */
+  usbhost_dumpgpio();
+
+  uinfo("Initializing Host Stack\n");
+
+  /* Show AHB SRAM memory map */
+
+#if 0 /* Useful if you have doubts about the layout */
+  uinfo("AHB SRAM:\n");
+  uinfo("  HCCA:   %08x %d\n", LPC54_HCCA_BASE,   LPC54_HCCA_SIZE);
+  uinfo("  TDTAIL: %08x %d\n", LPC54_TDTAIL_ADDR, LPC54_TD_SIZE);
+  uinfo("  EDCTRL: %08x %d\n", LPC54_EDCTRL_ADDR, LPC54_ED_SIZE);
+  uinfo("  EDFREE: %08x %d\n", LPC54_EDFREE_BASE, LPC54_ED_SIZE);
+  uinfo("  TDFREE: %08x %d\n", LPC54_TDFREE_BASE, LPC54_EDFREE_SIZE);
+  uinfo("  TBFREE: %08x %d\n", LPC54_TBFREE_BASE, LPC54_TBFREE_SIZE);
+  uinfo("  IOFREE: %08x %d\n", LPC54_IOFREE_BASE, LPC54_IOBUFFERS * CONFIG_LPC54_OHCI_IOBUFSIZE);
+#endif
+
+  /* Initialize all the TDs, EDs and HCCA to 0 */
+
+  memset((void *)HCCA,   0, sizeof(struct ohci_hcca_s));
+  memset((void *)TDTAIL, 0, sizeof(struct ohci_gtd_s));
+  memset((void *)EDCTRL, 0, sizeof(struct lpc54_ed_s));
+
+  /* The EDCTRL wdhsem semaphore is used for signaling and, hence, should
+   * not have priority inheritance enabled.
+   */
+
+  nxsem_init(&EDCTRL->wdhsem, 0, 0);
+  nxsem_setprotocol(&EDCTRL->wdhsem, SEM_PRIO_NONE);
+
+  /* Initialize user-configurable EDs */
+
+  buffer = (uint8_t *)LPC54_EDFREE_BASE;
+  for (i = 0; i < CONFIG_LP17_OHCI_NEDS; i++)
+    {
+      /* Put the ED in a free list */
+
+      lpc54_edfree((struct lpc54_ed_s *)buffer);
+      buffer += LPC54_ED_SIZE;
+    }
+
+  /* Initialize user-configurable TDs */
+
+  buffer = (uint8_t *)LPC54_TDFREE_BASE;
+  for (i = 0; i < CONFIG_LP17_OHCI_NTDS; i++)
+    {
+      /* Put the TD in a free list */
+
+      lpc54_tdfree((struct lpc54_gtd_s *)buffer);
+      buffer += LPC54_TD_SIZE;
+    }
+
+  /* Initialize user-configurable request/descriptor transfer buffers */
+
+  buffer = (uint8_t *)LPC54_TBFREE_BASE;
+  for (i = 0; i < CONFIG_LPC54_OHCI_TDBUFFERS; i++)
+    {
+      /* Put the TD buffer in a free list */
+
+      lpc54_tbfree(buffer);
+      buffer += CONFIG_LPC54_OHCI_TDBUFSIZE;
+    }
+
+#if LPC54_IOBUFFERS > 0
+  /* Initialize user-configurable IO buffers */
+
+  buffer = (uint8_t *)LPC54_IOFREE_BASE;
+  for (i = 0; i < LPC54_IOBUFFERS; i++)
+    {
+      /* Put the IO buffer in a free list */
+
+      lpc54_freeio(buffer);
+      buffer += CONFIG_LPC54_OHCI_IOBUFSIZE;
+    }
+#endif
+
+  /* Initialize transfer structures */
+
+  for (i = 0, xfrinfo = g_xfrbuffers;
+       i < CONFIG_LPC54_OHCI_NPREALLOC;
+       i++, xfrinfo++)
+    {
+      /* Put the transfer structure in a free list */
+
+      lpc54_free_xfrinfo(xfrinfo);
+    }
+
+  /* Wait 50MS then perform hardware reset */
+
+  up_mdelay(50);
+
+  lpc54_putreg(0, LPC54_OHCI_CTRL);        /* Hardware reset */
+  lpc54_putreg(0, LPC54_OHCI_CTRLHEADED);  /* Initialize control list head to Zero */
+  lpc54_putreg(0, LPC54_OHCI_BULKHEADED);  /* Initialize bulk list head to Zero */
+
+  /* Software reset */
+
+  lpc54_putreg(OHCI_CMDST_HCR, LPC54_OHCI_CMDST);
+
+  /* Write Fm interval (FI), largest data packet counter (FSMPS), and
+   * periodic start.
+   */
+
+  lpc54_putreg(DEFAULT_FMINTERVAL, LPC54_OHCI_FMINT);
+  lpc54_putreg(DEFAULT_PERSTART, LPC54_OHCI_PERSTART);
+
+  /* Put HC in operational state */
+
+  regval  = lpc54_getreg(LPC54_OHCI_CTRL);
+  regval &= ~OHCI_CTRL_HCFS_MASK;
+  regval |= OHCI_CTRL_HCFS_OPER;
+  lpc54_putreg(regval, LPC54_OHCI_CTRL);
+
+  /* Set global power in HcRhStatus */
+
+  lpc54_putreg(OHCI_RHSTATUS_SGP, LPC54_OHCI_RHSTATUS);
+
+  /* Set HCCA base address */
+
+  lpc54_putreg((uint32_t)HCCA, LPC54_OHCI_HCCA);
+
+  /* Set up the root hub port EP0 */
+
+  lpc54_ep0init(priv);
+
+  /* Clear pending interrupts */
+
+  regval = lpc54_getreg(LPC54_OHCI_INTST);
+  lpc54_putreg(regval, LPC54_OHCI_INTST);
+
+  /* Enable OHCI interrupts */
+
+  lpc54_putreg((LPC54_ALL_INTS | OHCI_INT_MIE), LPC54_OHCI_INTEN);
+
+  /* Attach USB host controller interrupt handler */
+
+  if (irq_attach(LPC54_IRQ_USB, lpc54_usbinterrupt, NULL) != 0)
+    {
+      uerr("ERROR: Failed to attach IRQ\n");
+      return NULL;
+    }
+
+  /* Enable USB interrupts at the SYCON controller.  Disable interrupts
+   * because this register may be shared with other drivers.
+   */
+
+  flags   = enter_critical_section();
+  regval  = lpc54_getreg(LPC54_SYSCON_USBINTST);
+  regval |= SYSCON_USBINTST_ENINTS;
+  lpc54_putreg(regval, LPC54_SYSCON_USBINTST);
+  leave_critical_section(flags);
+
+  /* If there is a USB device in the slot at power up, then we will not
+   * get the status change interrupt to signal us that the device is
+   * connected.  We need to set the initial connected state accordingly.
+   */
+
+  regval          = lpc54_getreg(LPC54_OHCI_RHPORTST1);
+  priv->connected = ((regval & OHCI_RHPORTST_CCS) != 0);
+
+  /* Enable interrupts at the interrupt controller */
+
+  up_enable_irq(LPC54_IRQ_USB); /* enable USB interrupt */
+  uinfo("USB host Initialized, Device connected:%s\n",
+        priv->connected ? "YES" : "NO");
+
+  return &g_usbconn;
+}
diff --git a/arch/arm/src/lpc54xx/lpc54_usb0_ohci.h b/arch/arm/src/lpc54xx/lpc54_usb0_ohci.h
new file mode 100644
index 00000000000..56062b3a205
--- /dev/null
+++ b/arch/arm/src/lpc54xx/lpc54_usb0_ohci.h
@@ -0,0 +1,96 @@
+/************************************************************************************
+ * arch/arm/src/lpc54xx/lpc54_usb0_ohci.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_OHCI_H
+#define __ARCH_ARM_SRC_LPC54XX_LPC54_OHCI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: lpc54_usbhost_initialize
+ *
+ * Description:
+ *   Initialize USB host device controller hardware.
+ *
+ * Input Parameters:
+ *   controller -- If the device supports more than USB host controller, then
+ *     this identifies which controller is being initializeed.  Normally, this
+ *     is just zero.
+ *
+ * Returned Value:
+ *   And instance of the USB host interface.  The controlling task should
+ *   use this interface to (1) call the wait() method to wait for a device
+ *   to be connected, and (2) call the enumerate() method to bind the device
+ *   to a class driver.
+ *
+ * Assumptions:
+ * - This function should called in the initialization sequence in order
+ *   to initialize the USB device functionality.
+ * - Class drivers should be initialized prior to calling this function.
+ *   Otherwise, there is a race condition if the device is already connected.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+struct usbhost_connection_s;
+FAR struct usbhost_connection_s *lpc54_usbhost_initialize(int controller);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_OHCI_H */
diff --git a/arch/arm/src/lpc54xx/lpc54_wwdt.c b/arch/arm/src/lpc54xx/lpc54_wwdt.c
index 867b2220e73..015e53a36a9 100644
--- a/arch/arm/src/lpc54xx/lpc54_wwdt.c
+++ b/arch/arm/src/lpc54xx/lpc54_wwdt.c
@@ -49,7 +49,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/lpc54_wwdt.h"
+#include "hardware/lpc54_wwdt.h"
 #include "lpc54_power.h"
 #include "lpc54_wdt.h"
 
diff --git a/arch/arm/src/lpc54xx/lpc54_wwdt.h b/arch/arm/src/lpc54xx/lpc54_wwdt.h
index baffd8c167e..e4f5122d9f2 100644
--- a/arch/arm/src/lpc54xx/lpc54_wwdt.h
+++ b/arch/arm/src/lpc54xx/lpc54_wwdt.h
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_WDT_H
-#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_WDT_H
+#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_WDT_H
+#define __ARCH_ARM_SRC_LPC54XX_LPC54_WDT_H
 
 /****************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/lpc54_wdt.h"
+#include "hardware/lpc54_wdt.h"
 
 #ifdef CONFIG_WATCHDOG
 
@@ -94,4 +94,4 @@ void lpc54_wwdt_initialize(FAR const char *devpath);
 
 #endif /* __ASSEMBLY__ */
 #endif /* CONFIG_WATCHDOG */
-#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_WDT_H */
+#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_WDT_H */
diff --git a/arch/arm/src/max326xx/Make.defs b/arch/arm/src/max326xx/Make.defs
index 0ab4bc426a0..fcb164e44eb 100644
--- a/arch/arm/src/max326xx/Make.defs
+++ b/arch/arm/src/max326xx/Make.defs
@@ -62,11 +62,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
diff --git a/arch/arm/src/nrf52/Make.defs b/arch/arm/src/nrf52/Make.defs
index 3e1bd43f854..96b992f4ded 100644
--- a/arch/arm/src/nrf52/Make.defs
+++ b/arch/arm/src/nrf52/Make.defs
@@ -60,11 +60,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
diff --git a/arch/arm/src/nrf52/chip.h b/arch/arm/src/nrf52/chip.h
index ab62e8c8ef4..1791918c29d 100644
--- a/arch/arm/src/nrf52/chip.h
+++ b/arch/arm/src/nrf52/chip.h
@@ -48,7 +48,7 @@
 
 #include 
 #include 
-#include "chip/nrf52_memorymap.h"
+#include "hardware/nrf52_memorymap.h"
 
 /* If the common ARMv7-M vector handling logic is used, then it expects the
  * following definition in this file that provides the number of supported external
diff --git a/arch/arm/src/nrf52/chip/nrf52_clock.h b/arch/arm/src/nrf52/hardware/nrf52_clock.h
similarity index 96%
rename from arch/arm/src/nrf52/chip/nrf52_clock.h
rename to arch/arm/src/nrf52/hardware/nrf52_clock.h
index 41ba551a527..7501481a148 100644
--- a/arch/arm/src/nrf52/chip/nrf52_clock.h
+++ b/arch/arm/src/nrf52/hardware/nrf52_clock.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/nrf52/chip/nrf52_clock.h
+ * arch/arm/src/nrf52/hardware/nrf52_clock.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Janne Rosberg 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_CLOCK_H
-#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_CLOCK_H
+#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_CLOCK_H
+#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_CLOCK_H
 
 /************************************************************************************************
  * Included Files
  ************************************************************************************************/
 
 #include 
-#include "chip/nrf52_memorymap.h"
+#include "hardware/nrf52_memorymap.h"
 
 /************************************************************************************************
  * Pre-processor Definitions
@@ -97,4 +97,4 @@
 
 /* Register Bitfield Definitions ****************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_LCD_H */
+#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_LCD_H */
diff --git a/arch/arm/src/nrf52/chip/nrf52_ficr.h b/arch/arm/src/nrf52/hardware/nrf52_ficr.h
similarity index 97%
rename from arch/arm/src/nrf52/chip/nrf52_ficr.h
rename to arch/arm/src/nrf52/hardware/nrf52_ficr.h
index 04230049ed4..e0475932299 100644
--- a/arch/arm/src/nrf52/chip/nrf52_ficr.h
+++ b/arch/arm/src/nrf52/hardware/nrf52_ficr.h
@@ -1,5 +1,5 @@
 /***************************************************************************************************
- * arch/arm/src/nrf52/chip/nrf52_ficr.h
+ * arch/arm/src/nrf52/hardware/nrf52_ficr.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Alan Carvalho de Assis 
@@ -33,15 +33,15 @@
  *
  ***************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_FICR_H
-#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_FICR_H
+#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_FICR_H
+#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_FICR_H
 
 /***************************************************************************************************
  * Included Files
  ***************************************************************************************************/
 
 #include 
-#include "chip/nrf52_memorymap.h"
+#include "hardware/nrf52_memorymap.h"
 
 /***************************************************************************************************
  * Pre-processor Definitions
@@ -160,4 +160,4 @@
 
 /* INTENSET Register */
 
-#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_FICR_H */
+#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_FICR_H */
diff --git a/arch/arm/src/nrf52/chip/nrf52_gpio.h b/arch/arm/src/nrf52/hardware/nrf52_gpio.h
similarity index 94%
rename from arch/arm/src/nrf52/chip/nrf52_gpio.h
rename to arch/arm/src/nrf52/hardware/nrf52_gpio.h
index ccee6375679..6c52462187f 100644
--- a/arch/arm/src/nrf52/chip/nrf52_gpio.h
+++ b/arch/arm/src/nrf52/hardware/nrf52_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/nrf52/chip/nrf52_gpio.h
+ * arch/arm/src/nrf52/hardware/nrf52_gpio.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Janne Rosberg 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_GPIO_H
-#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_GPIO_H
+#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_GPIO_H
+#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/nrf52_memorymap.h"
+#include "hardware/nrf52_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -84,4 +84,4 @@
 #  define NRF52_GPIO_CNF_PULL_DOWN      (1 << NRF52_GPIO_CNF_PULL_SHIFT)
 #  define NRF52_GPIO_CNF_PULL_UP        (3 << NRF52_GPIO_CNF_PULL_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_GPIO_H */
+#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_GPIO_H */
diff --git a/arch/arm/src/nrf52/chip/nrf52_memorymap.h b/arch/arm/src/nrf52/hardware/nrf52_memorymap.h
similarity index 95%
rename from arch/arm/src/nrf52/chip/nrf52_memorymap.h
rename to arch/arm/src/nrf52/hardware/nrf52_memorymap.h
index ca4a5c2a252..e32056c6927 100644
--- a/arch/arm/src/nrf52/chip/nrf52_memorymap.h
+++ b/arch/arm/src/nrf52/hardware/nrf52_memorymap.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/nrf52/chip/nrf52_memorymap.h
+ * arch/arm/src/nrf52/hardware/nrf52_memorymap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Janne Rosberg 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_MEMORYMAP_H
-#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_MEMORYMAP_H
+#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_MEMORYMAP_H
 
 /****************************************************************************
  * Included Files
@@ -130,4 +130,4 @@
 #define NRF52_GPIO_P0_BASE  0x50000000
 #define NRF52_GPIO_P1_BASE  0x50003000
 
-#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_MEMORYMAP_H */
diff --git a/arch/arm/src/nrf52/chip/nrf52_nvmc.h b/arch/arm/src/nrf52/hardware/nrf52_nvmc.h
similarity index 95%
rename from arch/arm/src/nrf52/chip/nrf52_nvmc.h
rename to arch/arm/src/nrf52/hardware/nrf52_nvmc.h
index 502a2406479..cef1537ae5a 100644
--- a/arch/arm/src/nrf52/chip/nrf52_nvmc.h
+++ b/arch/arm/src/nrf52/hardware/nrf52_nvmc.h
@@ -1,5 +1,5 @@
 /***************************************************************************************************
- * arch/arm/src/nrf52/chip/nrf52_nvmc.h
+ * arch/arm/src/nrf52/hardware/nrf52_nvmc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Alan Carvalho de Assis 
@@ -33,15 +33,15 @@
  *
  ***************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_NVMC_H
-#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_NVMC_H
+#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_NVMC_H
+#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_NVMC_H
 
 /***************************************************************************************************
  * Included Files
  ***************************************************************************************************/
 
 #include 
-#include "chip/nrf52_memorymap.h"
+#include "hardware/nrf52_memorymap.h"
 
 /***************************************************************************************************
  * Pre-processor Definitions
@@ -96,4 +96,4 @@
 
 /* INTENSET Register */
 
-#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_NVMC_H */
+#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_NVMC_H */
diff --git a/arch/arm/src/nrf52/chip/nrf52_rng.h b/arch/arm/src/nrf52/hardware/nrf52_rng.h
similarity index 94%
rename from arch/arm/src/nrf52/chip/nrf52_rng.h
rename to arch/arm/src/nrf52/hardware/nrf52_rng.h
index 34e1de5fc83..b322a097630 100644
--- a/arch/arm/src/nrf52/chip/nrf52_rng.h
+++ b/arch/arm/src/nrf52/hardware/nrf52_rng.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/nrf52/chip/nrf52_rng.h
+ * arch/arm/src/nrf52/hardware/nrf52_rng.h
  *
  *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Author: Zhiqiang Li 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_RNG_H
-#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_RNG_H
+#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_RNG_H
+#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_RNG_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/nrf52_memorymap.h"
+#include "hardware/nrf52_memorymap.h"
 #include "chip.h"
 
 /************************************************************************************
@@ -78,4 +78,4 @@
 
 #define NRF52_RNG_INT_EVENT_RDY         (1<<0)
 
-#endif  /* __ARCH_ARM_SRC_NRF52_CHIP_STM32_RNG_H */
+#endif  /* __ARCH_ARM_SRC_NRF52_HARDWARE_STM32_RNG_H */
diff --git a/arch/arm/src/nrf52/chip/nrf52_uarte.h b/arch/arm/src/nrf52/hardware/nrf52_uarte.h
similarity index 98%
rename from arch/arm/src/nrf52/chip/nrf52_uarte.h
rename to arch/arm/src/nrf52/hardware/nrf52_uarte.h
index b87de7d5a3c..f40e01bae16 100644
--- a/arch/arm/src/nrf52/chip/nrf52_uarte.h
+++ b/arch/arm/src/nrf52/hardware/nrf52_uarte.h
@@ -1,5 +1,5 @@
 /*****************************************************************************************************
- * arch/arm/src/nrf52/chip/nrf52_uarte.h
+ * arch/arm/src/nrf52/hardware/nrf52_uarte.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Janne Rosberg 
@@ -33,15 +33,15 @@
  *
  *****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_UARTE_H
-#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_UARTE_H
+#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_UARTE_H
+#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_UARTE_H
 
 /*****************************************************************************************************
  * Included Files
  *****************************************************************************************************/
 
 #include 
-#include "chip/nrf52_memorymap.h"
+#include "hardware/nrf52_memorymap.h"
 
 /*****************************************************************************************************
  * Pre-processor Definitions
@@ -185,4 +185,4 @@
 
 #define NRF52_UART_INTENSET_RXDRDY          (1 << 2)
 
-#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_UARTE_H */
+#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_UARTE_H */
diff --git a/arch/arm/src/nrf52/chip/nrf52_utils.h b/arch/arm/src/nrf52/hardware/nrf52_utils.h
similarity index 95%
rename from arch/arm/src/nrf52/chip/nrf52_utils.h
rename to arch/arm/src/nrf52/hardware/nrf52_utils.h
index 1b127b90f1f..a3c93edfd2b 100644
--- a/arch/arm/src/nrf52/chip/nrf52_utils.h
+++ b/arch/arm/src/nrf52/hardware/nrf52_utils.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/nrf52/nrf52_utils.h
+ * arch/arm/src/nrf52/hardware/nrf52_utils.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Zhiqiang Li 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_UTILS_H
-#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_UTILS_H
+#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_UTILS_H
+#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_UTILS_H
 
 /****************************************************************************
  * Included Files
@@ -122,5 +122,5 @@ static inline void nrf52_interrupt_disable(uint32_t reg_intenclr,
   putreg32(bitfield, reg_intenclr);
 }
 
-#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_UTILS_H */
+#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_UTILS_H */
 
diff --git a/arch/arm/src/nrf52/chip/nrf52_wdt.h b/arch/arm/src/nrf52/hardware/nrf52_wdt.h
similarity index 95%
rename from arch/arm/src/nrf52/chip/nrf52_wdt.h
rename to arch/arm/src/nrf52/hardware/nrf52_wdt.h
index 99573575442..2037c91b93c 100644
--- a/arch/arm/src/nrf52/chip/nrf52_wdt.h
+++ b/arch/arm/src/nrf52/hardware/nrf52_wdt.h
@@ -1,5 +1,5 @@
 /***************************************************************************************************
- * arch/arm/src/nrf52/chip/nrf52_wdt.h
+ * arch/arm/src/nrf52/hardware/nrf52_wdt.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author:  Alan Carvalho de Assis 
@@ -33,15 +33,15 @@
  *
  ***************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_WDT_H
-#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_WDT_H
+#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_WDT_H
+#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_WDT_H
 
 /***************************************************************************************************
  * Included Files
  ***************************************************************************************************/
 
 #include 
-#include "chip/nrf52_memorymap.h"
+#include "hardware/nrf52_memorymap.h"
 
 /***************************************************************************************************
  * Pre-processor Definitions
@@ -100,4 +100,4 @@
 
 #define NRF52_UART_INTENSET_RXDRDY          (1 << 2)
 
-#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_WDT_H */
+#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_WDT_H */
diff --git a/arch/arm/src/nrf52/nrf52832_errdata.c b/arch/arm/src/nrf52/nrf52832_errdata.c
index eca042ed9ac..ee0f79233b7 100644
--- a/arch/arm/src/nrf52/nrf52832_errdata.c
+++ b/arch/arm/src/nrf52/nrf52832_errdata.c
@@ -53,8 +53,8 @@
 
 #include "up_arch.h"
 #include "chip.h"
-#include "chip/nrf52_utils.h"
-#include "chip/nrf52_rng.h"
+#include "hardware/nrf52_utils.h"
+#include "hardware/nrf52_rng.h"
 #include "up_internal.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/nrf52/nrf52_allocateheap.c b/arch/arm/src/nrf52/nrf52_allocateheap.c
index 4ec0d0287fb..344d47fc3fe 100644
--- a/arch/arm/src/nrf52/nrf52_allocateheap.c
+++ b/arch/arm/src/nrf52/nrf52_allocateheap.c
@@ -52,7 +52,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/nrf52_memorymap.h"
+#include "hardware/nrf52_memorymap.h"
 
 #include 
 
diff --git a/arch/arm/src/nrf52/nrf52_flash.c b/arch/arm/src/nrf52/nrf52_flash.c
index d1f9ee66e7e..73073d8d219 100644
--- a/arch/arm/src/nrf52/nrf52_flash.c
+++ b/arch/arm/src/nrf52/nrf52_flash.c
@@ -54,8 +54,8 @@
 
 #include "up_arch.h"
 
-#include "chip/nrf52_ficr.h"
-#include "chip/nrf52_nvmc.h"
+#include "hardware/nrf52_ficr.h"
+#include "hardware/nrf52_nvmc.h"
 #include "nrf52_nvmc.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/nrf52/nrf52_gpio.c b/arch/arm/src/nrf52/nrf52_gpio.c
index 9a0198f57cd..a5c0a882793 100644
--- a/arch/arm/src/nrf52/nrf52_gpio.c
+++ b/arch/arm/src/nrf52/nrf52_gpio.c
@@ -48,7 +48,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/nrf52_gpio.h"
+#include "hardware/nrf52_gpio.h"
 #include "nrf52_gpio.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/nrf52/nrf52_gpio.h b/arch/arm/src/nrf52/nrf52_gpio.h
index c96fe5b4306..55f6580ecd8 100644
--- a/arch/arm/src/nrf52/nrf52_gpio.h
+++ b/arch/arm/src/nrf52/nrf52_gpio.h
@@ -48,7 +48,7 @@
 #endif
 
 #include 
-#include "chip/nrf52_gpio.h"
+#include "hardware/nrf52_gpio.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/nrf52/nrf52_lowputc.c b/arch/arm/src/nrf52/nrf52_lowputc.c
index d4fff9296d2..c0b7cd40cb6 100644
--- a/arch/arm/src/nrf52/nrf52_lowputc.c
+++ b/arch/arm/src/nrf52/nrf52_lowputc.c
@@ -44,8 +44,8 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/nrf52_memorymap.h"
-#include "chip/nrf52_uarte.h"
+#include "hardware/nrf52_memorymap.h"
+#include "hardware/nrf52_uarte.h"
 
 #include "nrf52_config.h"
 #include "nrf52_clockconfig.h"
diff --git a/arch/arm/src/nrf52/nrf52_nvmc.c b/arch/arm/src/nrf52/nrf52_nvmc.c
index dfa273bf8f2..82beb1fa432 100644
--- a/arch/arm/src/nrf52/nrf52_nvmc.c
+++ b/arch/arm/src/nrf52/nrf52_nvmc.c
@@ -48,8 +48,8 @@
 #include "up_arch.h"
 #include "barriers.h"
 
-#include "chip/nrf52_ficr.h"
-#include "chip/nrf52_nvmc.h"
+#include "hardware/nrf52_ficr.h"
+#include "hardware/nrf52_nvmc.h"
 #include "nrf52_nvmc.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/nrf52/nrf52_rng.c b/arch/arm/src/nrf52/nrf52_rng.c
index 991f4629957..0a120eac7fe 100644
--- a/arch/arm/src/nrf52/nrf52_rng.c
+++ b/arch/arm/src/nrf52/nrf52_rng.c
@@ -53,8 +53,8 @@
 
 #include "up_arch.h"
 #include "chip.h"
-#include "chip/nrf52_utils.h"
-#include "chip/nrf52_rng.h"
+#include "hardware/nrf52_utils.h"
+#include "hardware/nrf52_rng.h"
 #include "up_internal.h"
 
 #if defined(CONFIG_NRF52_RNG)
diff --git a/arch/arm/src/nrf52/nrf52_serial.c b/arch/arm/src/nrf52/nrf52_serial.c
index 653dcb32cbd..f1e4f4324fd 100644
--- a/arch/arm/src/nrf52/nrf52_serial.c
+++ b/arch/arm/src/nrf52/nrf52_serial.c
@@ -59,7 +59,7 @@
 
 #include "chip.h"
 #include "nrf52_config.h"
-#include "chip/nrf52_uarte.h"
+#include "hardware/nrf52_uarte.h"
 #include "nrf52_clockconfig.h"
 #include "nrf52_lowputc.h"
 #include "nrf52_serial.h"
diff --git a/arch/arm/src/nrf52/nrf52_start.c b/arch/arm/src/nrf52/nrf52_start.c
index 1ec79f0542c..d95a9a475fe 100644
--- a/arch/arm/src/nrf52/nrf52_start.c
+++ b/arch/arm/src/nrf52/nrf52_start.c
@@ -48,7 +48,7 @@
 #include "nvic.h"
 
 #include "nrf52_clockconfig.h"
-#include "chip/nrf52_utils.h"
+#include "hardware/nrf52_utils.h"
 #include "nrf52_lowputc.h"
 #include "nrf52_start.h"
 #include "nrf52_gpio.h"
diff --git a/arch/arm/src/nrf52/nrf52_utils.c b/arch/arm/src/nrf52/nrf52_utils.c
index 83f92589f56..1a23b912979 100644
--- a/arch/arm/src/nrf52/nrf52_utils.c
+++ b/arch/arm/src/nrf52/nrf52_utils.c
@@ -45,7 +45,7 @@
 #include "up_arch.h"
 
 #include "nrf52_irq.h"
-#include "chip/nrf52_utils.h"
+#include "hardware/nrf52_utils.h"
 
 /****************************************************************************
  * Public Functions
diff --git a/arch/arm/src/nrf52/nrf52_wdt.c b/arch/arm/src/nrf52/nrf52_wdt.c
index 7a7149a2961..873f48a5260 100644
--- a/arch/arm/src/nrf52/nrf52_wdt.c
+++ b/arch/arm/src/nrf52/nrf52_wdt.c
@@ -54,7 +54,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/nrf52_wdt.h"
+#include "hardware/nrf52_wdt.h"
 #include "nrf52_wdt.h"
 
 #if defined(CONFIG_WATCHDOG) && defined(CONFIG_NRF52_WDT)
diff --git a/arch/arm/src/nuc1xx/Make.defs b/arch/arm/src/nuc1xx/Make.defs
index 176743f97ce..440bf500675 100644
--- a/arch/arm/src/nuc1xx/Make.defs
+++ b/arch/arm/src/nuc1xx/Make.defs
@@ -49,11 +49,9 @@ CMN_CSRCS += up_hardfault.c up_svcall.c up_vectors.c up_vfork.c
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
diff --git a/arch/arm/src/nuc1xx/chip.h b/arch/arm/src/nuc1xx/chip.h
index d47f4f5e28c..618d9f1960e 100644
--- a/arch/arm/src/nuc1xx/chip.h
+++ b/arch/arm/src/nuc1xx/chip.h
@@ -54,7 +54,7 @@
  * this file for the proper setup.
  */
 
-#include "chip/nuc_memorymap.h"
+#include "hardware/nuc_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/nuc1xx/chip/nuc_adc.h b/arch/arm/src/nuc1xx/hardware/nuc_adc.h
similarity index 94%
rename from arch/arm/src/nuc1xx/chip/nuc_adc.h
rename to arch/arm/src/nuc1xx/hardware/nuc_adc.h
index cea74a0fd6f..e4918b7e0b0 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_adc.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_adc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_adc.h
+ * arch/arm/src/nuc1xx/hardware/nuc_adc.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_ADC_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_ADC_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_ADC_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_ADC_H
 
 /********************************************************************************************
  * Included Files
@@ -68,4 +68,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_ADC_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_ADC_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_clk.h b/arch/arm/src/nuc1xx/hardware/nuc_clk.h
similarity index 99%
rename from arch/arm/src/nuc1xx/chip/nuc_clk.h
rename to arch/arm/src/nuc1xx/hardware/nuc_clk.h
index 69c54b9ce0d..2c7b20ec7d5 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_clk.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_clk.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_clk.h
+ * arch/arm/src/nuc1xx/hardware/nuc_clk.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_CLK_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_CLK_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_CLK_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_CLK_H
 
 /********************************************************************************************
  * Included Files
@@ -285,4 +285,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_CLK_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_CLK_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_cmp.h b/arch/arm/src/nuc1xx/hardware/nuc_cmp.h
similarity index 94%
rename from arch/arm/src/nuc1xx/chip/nuc_cmp.h
rename to arch/arm/src/nuc1xx/hardware/nuc_cmp.h
index 64d11b31e02..1d130d9d736 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_cmp.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_cmp.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_cmp.h
+ * arch/arm/src/nuc1xx/hardware/nuc_cmp.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_CMP_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_CMP_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_CMP_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_CMP_H
 
 /********************************************************************************************
  * Included Files
@@ -68,4 +68,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_CMP_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_CMP_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_config.h b/arch/arm/src/nuc1xx/hardware/nuc_config.h
similarity index 96%
rename from arch/arm/src/nuc1xx/chip/nuc_config.h
rename to arch/arm/src/nuc1xx/hardware/nuc_config.h
index cfc15bae994..984121f9636 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_config.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_config.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_config.h
+ * arch/arm/src/nuc1xx/hardware/nuc_config.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_CONFIG_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_CONFIG_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_CONFIG_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_CONFIG_H
 
 /********************************************************************************************
  * Included Files
@@ -114,4 +114,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_CONFIG_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_CONFIG_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_ebi.h b/arch/arm/src/nuc1xx/hardware/nuc_ebi.h
similarity index 94%
rename from arch/arm/src/nuc1xx/chip/nuc_ebi.h
rename to arch/arm/src/nuc1xx/hardware/nuc_ebi.h
index 142ae60ab9a..f7d474f99de 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_ebi.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_ebi.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_ebi.h
+ * arch/arm/src/nuc1xx/hardware/nuc_ebi.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_EBI_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_EBI_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_EBI_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_EBI_H
 
 /********************************************************************************************
  * Included Files
@@ -68,4 +68,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_EBI_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_EBI_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_gcr.h b/arch/arm/src/nuc1xx/hardware/nuc_gcr.h
similarity index 99%
rename from arch/arm/src/nuc1xx/chip/nuc_gcr.h
rename to arch/arm/src/nuc1xx/hardware/nuc_gcr.h
index 9612dfac3ca..8486e59b34c 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_gcr.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_gcr.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_gcr.h
+ * arch/arm/src/nuc1xx/hardware/nuc_gcr.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_GCR_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_GCR_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_GCR_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_GCR_H
 
 /********************************************************************************************
  * Included Files
@@ -370,4 +370,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_GCR_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_GCR_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_gpio.h b/arch/arm/src/nuc1xx/hardware/nuc_gpio.h
similarity index 99%
rename from arch/arm/src/nuc1xx/chip/nuc_gpio.h
rename to arch/arm/src/nuc1xx/hardware/nuc_gpio.h
index 7d99118e0e8..362d345ca77 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_gpio.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_gpio.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_gpio.h
+ * arch/arm/src/nuc1xx/hardware/nuc_gpio.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_GPIO_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_GPIO_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_GPIO_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_GPIO_H
 
 /********************************************************************************************
  * Included Files
@@ -553,4 +553,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_GPIO_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_GPIO_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_i2c.h b/arch/arm/src/nuc1xx/hardware/nuc_i2c.h
similarity index 94%
rename from arch/arm/src/nuc1xx/chip/nuc_i2c.h
rename to arch/arm/src/nuc1xx/hardware/nuc_i2c.h
index 9b30e579799..6e761ecb3ac 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_i2c.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_i2c.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_i2c.h
+ * arch/arm/src/nuc1xx/hardware/nuc_i2c.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_I2C_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_I2C_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_I2C_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_I2C_H
 
 /********************************************************************************************
  * Included Files
@@ -68,4 +68,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_I2C_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_I2C_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_i2s.h b/arch/arm/src/nuc1xx/hardware/nuc_i2s.h
similarity index 94%
rename from arch/arm/src/nuc1xx/chip/nuc_i2s.h
rename to arch/arm/src/nuc1xx/hardware/nuc_i2s.h
index c94206324ac..95e89d2f946 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_i2s.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_i2s.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_i2s.h
+ * arch/arm/src/nuc1xx/hardware/nuc_i2s.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_I2S_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_I2S_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_I2S_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_I2S_H
 
 /********************************************************************************************
  * Included Files
@@ -68,4 +68,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_I2S_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_I2S_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_memorymap.h b/arch/arm/src/nuc1xx/hardware/nuc_memorymap.h
similarity index 96%
rename from arch/arm/src/nuc1xx/chip/nuc_memorymap.h
rename to arch/arm/src/nuc1xx/hardware/nuc_memorymap.h
index 4cdccfa7275..04a9e881ca6 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_memorymap.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_memorymap.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_memorymap.h
+ * arch/arm/src/nuc1xx/hardware/nuc_memorymap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_MEMORYMAP_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_MEMORYMAP_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_MEMORYMAP_H
 
 /********************************************************************************************
  * Included Files
@@ -109,4 +109,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_MEMORYMAP_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_pdma.h b/arch/arm/src/nuc1xx/hardware/nuc_pdma.h
similarity index 94%
rename from arch/arm/src/nuc1xx/chip/nuc_pdma.h
rename to arch/arm/src/nuc1xx/hardware/nuc_pdma.h
index 964c01f0d58..0433c5ffad3 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_pdma.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_pdma.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_pdma.h
+ * arch/arm/src/nuc1xx/hardware/nuc_pdma.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_PDMA_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_PDMA_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_PDMA_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_PDMA_H
 
 /********************************************************************************************
  * Included Files
@@ -68,4 +68,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_PDMA_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_PDMA_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_ps2d.h b/arch/arm/src/nuc1xx/hardware/nuc_ps2d.h
similarity index 94%
rename from arch/arm/src/nuc1xx/chip/nuc_ps2d.h
rename to arch/arm/src/nuc1xx/hardware/nuc_ps2d.h
index f011093324a..c6184611b3e 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_ps2d.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_ps2d.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_ps2d.h
+ * arch/arm/src/nuc1xx/hardware/nuc_ps2d.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_PS2D_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_PS2D_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_PS2D_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_PS2D_H
 
 /********************************************************************************************
  * Included Files
@@ -68,4 +68,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_PS2D_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_PS2D_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_pwm.h b/arch/arm/src/nuc1xx/hardware/nuc_pwm.h
similarity index 94%
rename from arch/arm/src/nuc1xx/chip/nuc_pwm.h
rename to arch/arm/src/nuc1xx/hardware/nuc_pwm.h
index 49f4f25a47f..06741e72acb 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_pwm.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_pwm.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_pwm.h
+ * arch/arm/src/nuc1xx/hardware/nuc_pwm.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_PWM_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_PWM_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_PWM_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_PWM_H
 
 /********************************************************************************************
  * Included Files
@@ -68,4 +68,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_PWM_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_PWM_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_rtc.h b/arch/arm/src/nuc1xx/hardware/nuc_rtc.h
similarity index 94%
rename from arch/arm/src/nuc1xx/chip/nuc_rtc.h
rename to arch/arm/src/nuc1xx/hardware/nuc_rtc.h
index 1ec5e2baef2..94280ab62ec 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_rtc.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_rtc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_rtc.h
+ * arch/arm/src/nuc1xx/hardware/nuc_rtc.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_RTC_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_RTC_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_RTC_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_RTC_H
 
 /********************************************************************************************
  * Included Files
@@ -68,4 +68,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_RTC_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_RTC_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_spi.h b/arch/arm/src/nuc1xx/hardware/nuc_spi.h
similarity index 94%
rename from arch/arm/src/nuc1xx/chip/nuc_spi.h
rename to arch/arm/src/nuc1xx/hardware/nuc_spi.h
index 74f46b1db5d..670128096d9 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_spi.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_spi.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_spi.h
+ * arch/arm/src/nuc1xx/hardware/nuc_spi.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_SPI_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_SPI_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_SPI_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_SPI_H
 
 /********************************************************************************************
  * Included Files
@@ -68,4 +68,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_SPI_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_SPI_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_tmr.h b/arch/arm/src/nuc1xx/hardware/nuc_tmr.h
similarity index 94%
rename from arch/arm/src/nuc1xx/chip/nuc_tmr.h
rename to arch/arm/src/nuc1xx/hardware/nuc_tmr.h
index e97615ce940..cc2c47808a8 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_tmr.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_tmr.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_tmr.h
+ * arch/arm/src/nuc1xx/hardware/nuc_tmr.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_TMR_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_TMR_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_TMR_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_TMR_H
 
 /********************************************************************************************
  * Included Files
@@ -68,4 +68,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_TMR_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_TMR_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_uart.h b/arch/arm/src/nuc1xx/hardware/nuc_uart.h
similarity index 98%
rename from arch/arm/src/nuc1xx/chip/nuc_uart.h
rename to arch/arm/src/nuc1xx/hardware/nuc_uart.h
index 18b0122b112..701eba048d4 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_uart.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_uart.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_uart.h
+ * arch/arm/src/nuc1xx/hardware/nuc_uart.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_UART_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_UART_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_UART_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_UART_H
 
 /********************************************************************************************
  * Included Files
@@ -287,4 +287,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_UART_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_UART_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_usbd.h b/arch/arm/src/nuc1xx/hardware/nuc_usbd.h
similarity index 94%
rename from arch/arm/src/nuc1xx/chip/nuc_usbd.h
rename to arch/arm/src/nuc1xx/hardware/nuc_usbd.h
index d950c3e8f79..8531407cdfc 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_usbd.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_usbd.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_usbd.h
+ * arch/arm/src/nuc1xx/hardware/nuc_usbd.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_USBD_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_USBD_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_USBD_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_USBD_H
 
 /********************************************************************************************
  * Included Files
@@ -68,4 +68,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_USBD_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_USBD_H */
diff --git a/arch/arm/src/nuc1xx/chip/nuc_wdt.h b/arch/arm/src/nuc1xx/hardware/nuc_wdt.h
similarity index 94%
rename from arch/arm/src/nuc1xx/chip/nuc_wdt.h
rename to arch/arm/src/nuc1xx/hardware/nuc_wdt.h
index 458efe9774d..b86775179b6 100644
--- a/arch/arm/src/nuc1xx/chip/nuc_wdt.h
+++ b/arch/arm/src/nuc1xx/hardware/nuc_wdt.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/nuc1xx/chip/nuc_wdt.h
+ * arch/arm/src/nuc1xx/hardware/nuc_wdt.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_WDT_H
-#define __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_WDT_H
+#ifndef __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_WDT_H
+#define __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_WDT_H
 
 /********************************************************************************************
  * Included Files
@@ -68,4 +68,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_NUC1XX_CHIP_NUC_WDT_H */
+#endif /* __ARCH_ARM_SRC_NUC1XX_HARDWARE_NUC_WDT_H */
diff --git a/arch/arm/src/nuc1xx/nuc_clockconfig.c b/arch/arm/src/nuc1xx/nuc_clockconfig.c
index 95e4332ce7a..29849fc4214 100644
--- a/arch/arm/src/nuc1xx/nuc_clockconfig.c
+++ b/arch/arm/src/nuc1xx/nuc_clockconfig.c
@@ -50,8 +50,8 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/chip/nuc_gcr.h"
-#include "chip/chip/nuc_clk.h"
+#include "hardware/nuc_gcr.h"
+#include "hardware/nuc_clk.h"
 
 #include "nuc_clockconfig.h"
 
diff --git a/arch/arm/src/nuc1xx/nuc_gpio.c b/arch/arm/src/nuc1xx/nuc_gpio.c
index e5c86c29347..98d08a6f5bf 100644
--- a/arch/arm/src/nuc1xx/nuc_gpio.c
+++ b/arch/arm/src/nuc1xx/nuc_gpio.c
@@ -49,7 +49,7 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/nuc_gpio.h"
+#include "hardware/nuc_gpio.h"
 
 #include "nuc_gpio.h"
 
diff --git a/arch/arm/src/nuc1xx/nuc_gpio.h b/arch/arm/src/nuc1xx/nuc_gpio.h
index 9d08dbac1ad..ba293fbb75f 100644
--- a/arch/arm/src/nuc1xx/nuc_gpio.h
+++ b/arch/arm/src/nuc1xx/nuc_gpio.h
@@ -50,7 +50,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/nuc_gpio.h"
+#include "hardware/nuc_gpio.h"
 
 /****************************************************************************
  * Pre-processor Declarations
diff --git a/arch/arm/src/nuc1xx/nuc_lowputc.c b/arch/arm/src/nuc1xx/nuc_lowputc.c
index be949b2c9a1..0ff3e8c525e 100644
--- a/arch/arm/src/nuc1xx/nuc_lowputc.c
+++ b/arch/arm/src/nuc1xx/nuc_lowputc.c
@@ -49,10 +49,10 @@
 
 #include "chip.h"
 #include "nuc_config.h"
-#include "chip/chip/nuc_clk.h"
-#include "chip/chip/nuc_uart.h"
+#include "hardware/nuc_clk.h"
+#include "hardware/nuc_uart.h"
 
-#include "chip/nuc_gcr.h"
+#include "hardware/nuc_gcr.h"
 #include "nuc_lowputc.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/nuc1xx/nuc_serial.c b/arch/arm/src/nuc1xx/nuc_serial.c
index 9791a6ae9a9..b9ff2fa1c7a 100644
--- a/arch/arm/src/nuc1xx/nuc_serial.c
+++ b/arch/arm/src/nuc1xx/nuc_serial.c
@@ -63,7 +63,7 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/nuc_uart.h"
+#include "hardware/nuc_uart.h"
 #include "nuc_lowputc.h"
 #include "nuc_serial.h"
 
diff --git a/arch/arm/src/nuc1xx/nuc_serial.h b/arch/arm/src/nuc1xx/nuc_serial.h
index 950e30d1a9e..5a67851ae1d 100644
--- a/arch/arm/src/nuc1xx/nuc_serial.h
+++ b/arch/arm/src/nuc1xx/nuc_serial.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "nuc_config.h"
-#include "chip/nuc_uart.h"
+#include "hardware/nuc_uart.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/nuc1xx/nuc_timerisr.c b/arch/arm/src/nuc1xx/nuc_timerisr.c
index d6ec1fa9491..338d2419add 100644
--- a/arch/arm/src/nuc1xx/nuc_timerisr.c
+++ b/arch/arm/src/nuc1xx/nuc_timerisr.c
@@ -51,8 +51,8 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/nuc_clk.h"
-#include "chip/nuc_gcr.h"
+#include "hardware/nuc_clk.h"
+#include "hardware/nuc_gcr.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sam34/Make.defs b/arch/arm/src/sam34/Make.defs
index 153d69a504c..c88098722b8 100644
--- a/arch/arm/src/sam34/Make.defs
+++ b/arch/arm/src/sam34/Make.defs
@@ -76,11 +76,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_ARCH_FPU),y)
 CMN_ASRCS += up_fpu.S
diff --git a/arch/arm/src/sam34/chip.h b/arch/arm/src/sam34/chip.h
index 96e26924f2d..0100d075fd9 100644
--- a/arch/arm/src/sam34/chip.h
+++ b/arch/arm/src/sam34/chip.h
@@ -47,7 +47,7 @@
  */
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /* Include the chip interrupt definition file */
 
diff --git a/arch/arm/src/sam34/chip/sam3u_memorymap.h b/arch/arm/src/sam34/hardware/sam3u_memorymap.h
similarity index 97%
rename from arch/arm/src/sam34/chip/sam3u_memorymap.h
rename to arch/arm/src/sam34/hardware/sam3u_memorymap.h
index ffcc5589fb3..4cf145fd712 100644
--- a/arch/arm/src/sam34/chip/sam3u_memorymap.h
+++ b/arch/arm/src/sam34/hardware/sam3u_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/sam34/chip/sam3u_memorymap.h
+ * arch/arm/src/sam34/hardware/sam3u_memorymap.h
  *
  *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_MEMORYMAP_H
 
 /************************************************************************************************
  * Included Files
@@ -142,4 +142,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_MEMORYMAP_H */
diff --git a/arch/arm/src/sam34/chip/sam3u_pinmap.h b/arch/arm/src/sam34/hardware/sam3u_pinmap.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam3u_pinmap.h
rename to arch/arm/src/sam34/hardware/sam3u_pinmap.h
index 166a5213dc6..5738684f1e9 100644
--- a/arch/arm/src/sam34/chip/sam3u_pinmap.h
+++ b/arch/arm/src/sam34/hardware/sam3u_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sam34/chip/sam3u_pinmap.h
+ * arch/arm/src/sam34/hardware/sam3u_pinmap.h
  *
  *   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PINMAP_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -220,4 +220,4 @@ extern "C"
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H */
diff --git a/arch/arm/src/sam34/chip/sam3u_pio.h b/arch/arm/src/sam34/hardware/sam3u_pio.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam3u_pio.h
rename to arch/arm/src/sam34/hardware/sam3u_pio.h
index aa5e32266ff..ffff788308e 100644
--- a/arch/arm/src/sam34/chip/sam3u_pio.h
+++ b/arch/arm/src/sam34/hardware/sam3u_pio.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam3u_pio.h
+ * arch/arm/src/sam34/hardware/sam3u_pio.h
  * Parallel Input/Output (PIO) Controller definitions for the SAM3U, SAM3X, and SAM3A.
  *
  *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PIO_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PIO_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PIO_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PIO_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -464,4 +464,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PIO_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PIO_H */
diff --git a/arch/arm/src/sam34/chip/sam3x_memorymap.h b/arch/arm/src/sam34/hardware/sam3x_memorymap.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam3x_memorymap.h
rename to arch/arm/src/sam34/hardware/sam3x_memorymap.h
index ba053d3c353..0193d2471b0 100644
--- a/arch/arm/src/sam34/chip/sam3x_memorymap.h
+++ b/arch/arm/src/sam34/hardware/sam3x_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/sam34/chip/sam3x_memorymap.h
+ * arch/arm/src/sam34/hardware/sam3x_memorymap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3X_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3X_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_MEMORYMAP_H
 
 /************************************************************************************************
  * Included Files
@@ -171,4 +171,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3X_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_MEMORYMAP_H */
diff --git a/arch/arm/src/sam34/chip/sam3x_pinmap.h b/arch/arm/src/sam34/hardware/sam3x_pinmap.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam3x_pinmap.h
rename to arch/arm/src/sam34/hardware/sam3x_pinmap.h
index 4b886dd53ff..bc9362c2938 100644
--- a/arch/arm/src/sam34/chip/sam3x_pinmap.h
+++ b/arch/arm/src/sam34/hardware/sam3x_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sam34/chip/sam3x_pinmap.h
+ * arch/arm/src/sam34/hardware/sam3x_pinmap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3X_PINMAP_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3X_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_PINMAP_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -60,7 +60,7 @@
  *
  * #define GPIO_PWM0_H GPIO_PWM0_H_1
  *
- * The driver will then automatically configre RE15 as the PWM0 H pin.
+ * The driver will then automatically configure RE15 as the PWM0 H pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -456,4 +456,4 @@ extern "C"
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3X_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_PINMAP_H */
diff --git a/arch/arm/src/sam34/chip/sam4cm_aes.h b/arch/arm/src/sam34/hardware/sam4cm_aes.h
similarity index 97%
rename from arch/arm/src/sam34/chip/sam4cm_aes.h
rename to arch/arm/src/sam34/hardware/sam4cm_aes.h
index 051318dd170..767384903e7 100644
--- a/arch/arm/src/sam34/chip/sam4cm_aes.h
+++ b/arch/arm/src/sam34/hardware/sam4cm_aes.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/sam34/chip/sam4cm_aes.h
+ * arch/arm/src/sam34/hardware/sam4cm_aes.h
  * AES hardware accelerator for SAM4CM
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_AES_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_AES_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_AES_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_AES_H
 
 /********************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -136,4 +136,4 @@
 
 #define AES_ISR_DATRDY                   (1 << 0)
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_AES_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_AES_H */
diff --git a/arch/arm/src/sam34/chip/sam4cm_ipc.h b/arch/arm/src/sam34/hardware/sam4cm_ipc.h
similarity index 95%
rename from arch/arm/src/sam34/chip/sam4cm_ipc.h
rename to arch/arm/src/sam34/hardware/sam4cm_ipc.h
index a4d9d3ec3a2..6b7ee34d5b8 100644
--- a/arch/arm/src/sam34/chip/sam4cm_ipc.h
+++ b/arch/arm/src/sam34/hardware/sam4cm_ipc.h
@@ -1,5 +1,5 @@
 /***********************************************************************************
- * arch/arm/src/sam34/chip/sam4cm_ipc.h
+ * arch/arm/src/sam34/hardware/sam4cm_ipc.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ***********************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_IPC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_IPC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_IPC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_IPC_H
 
 /***********************************************************************************
  * Included Files
@@ -77,4 +77,4 @@
 #define SAM_IPC1_IMR               (SAM_IPC1_BASE + SAM_IPC_IMR_OFFSET)
 #define SAM_IPC1_ISR               (SAM_IPC1_BASE + SAM_IPC_ISR_OFFSET)
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_IPC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_IPC_H */
diff --git a/arch/arm/src/sam34/chip/sam4cm_memorymap.h b/arch/arm/src/sam34/hardware/sam4cm_memorymap.h
similarity index 97%
rename from arch/arm/src/sam34/chip/sam4cm_memorymap.h
rename to arch/arm/src/sam34/hardware/sam4cm_memorymap.h
index d719e268c01..4b08759afde 100644
--- a/arch/arm/src/sam34/chip/sam4cm_memorymap.h
+++ b/arch/arm/src/sam34/hardware/sam4cm_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/sam34/chip/sam4cm_memorymap.h
+ * arch/arm/src/sam34/hardware/sam4cm_memorymap.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_MEMORYMAP_H
 
 /************************************************************************************************
  * Included Files
@@ -177,4 +177,4 @@ static inline unsigned long SAM_PION_BASE(int n)
 
 #endif /* __ASSEMBLY__ */
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_MEMORYMAP_H */
diff --git a/arch/arm/src/sam34/chip/sam4cm_pinmap.h b/arch/arm/src/sam34/hardware/sam4cm_pinmap.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam4cm_pinmap.h
rename to arch/arm/src/sam34/hardware/sam4cm_pinmap.h
index 1cf999b3ef7..990ba089ebd 100644
--- a/arch/arm/src/sam34/chip/sam4cm_pinmap.h
+++ b/arch/arm/src/sam34/hardware/sam4cm_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sam34/chip/sam4cm_pinmap.h
+ * arch/arm/src/sam34/hardware/sam4cm_pinmap.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_PINMAP_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_PINMAP_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -319,4 +319,4 @@ extern "C"
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PINMAP_H */
diff --git a/arch/arm/src/sam34/chip/sam4cm_slcdc.h b/arch/arm/src/sam34/hardware/sam4cm_slcdc.h
similarity index 97%
rename from arch/arm/src/sam34/chip/sam4cm_slcdc.h
rename to arch/arm/src/sam34/hardware/sam4cm_slcdc.h
index 2575119d5cf..babfcb7ecb6 100644
--- a/arch/arm/src/sam34/chip/sam4cm_slcdc.h
+++ b/arch/arm/src/sam34/hardware/sam4cm_slcdc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam4cm_slcdc.h
+ * arch/arm/src/sam34/hardware/sam4cm_slcdc.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_SLCDC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_SLCDC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SLCDC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SLCDC_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -179,4 +179,4 @@
 #define SLCDC_ISR_ENDFRAME         (1 << 0)                             /* End of Frame Interrupt occurred */
 #define SLCDC_ISR_DIS              (1 << 2)                             /* The "Disable" interrupt occurred */
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_SLCDC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SLCDC_H */
diff --git a/arch/arm/src/sam34/chip/sam4cm_supc.h b/arch/arm/src/sam34/hardware/sam4cm_supc.h
similarity index 97%
rename from arch/arm/src/sam34/chip/sam4cm_supc.h
rename to arch/arm/src/sam34/hardware/sam4cm_supc.h
index 54945823123..11951c9ddd6 100644
--- a/arch/arm/src/sam34/chip/sam4cm_supc.h
+++ b/arch/arm/src/sam34/hardware/sam4cm_supc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam4cm_supc.h
+ * arch/arm/src/sam34/hardware/sam4cm_supc.h
  * Supply Controller (SUPC) definitions for the SAM4CM
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_SUPC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_SUPC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SUPC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SUPC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -174,4 +174,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4CM_SUPC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SUPC_H */
diff --git a/arch/arm/src/sam34/chip/sam4e_memorymap.h b/arch/arm/src/sam34/hardware/sam4e_memorymap.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam4e_memorymap.h
rename to arch/arm/src/sam34/hardware/sam4e_memorymap.h
index 1cf95993996..3cee120bbe4 100644
--- a/arch/arm/src/sam34/chip/sam4e_memorymap.h
+++ b/arch/arm/src/sam34/hardware/sam4e_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/sam34/chip/sam4e_memorymap.h
+ * arch/arm/src/sam34/hardware/sam4e_memorymap.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4E_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4E_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_MEMORYMAP_H
 
 /************************************************************************************************
  * Included Files
@@ -176,4 +176,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4E_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_MEMORYMAP_H */
diff --git a/arch/arm/src/sam34/chip/sam4e_pinmap.h b/arch/arm/src/sam34/hardware/sam4e_pinmap.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam4e_pinmap.h
rename to arch/arm/src/sam34/hardware/sam4e_pinmap.h
index c97111e4e46..ce67099694b 100644
--- a/arch/arm/src/sam34/chip/sam4e_pinmap.h
+++ b/arch/arm/src/sam34/hardware/sam4e_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sam34/chip/sam4e_pinmap.h
+ * arch/arm/src/sam34/hardware/sam4e_pinmap.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4E_PINMAP_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4E_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PINMAP_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -334,4 +334,4 @@ extern "C"
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4E_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PINMAP_H */
diff --git a/arch/arm/src/sam34/chip/sam4e_pio.h b/arch/arm/src/sam34/hardware/sam4e_pio.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam4e_pio.h
rename to arch/arm/src/sam34/hardware/sam4e_pio.h
index 3918583a527..b04c4153674 100644
--- a/arch/arm/src/sam34/chip/sam4e_pio.h
+++ b/arch/arm/src/sam34/hardware/sam4e_pio.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam4e_pio.h
+ * arch/arm/src/sam34/hardware/sam4e_pio.h
  * Parallel Input/Output (PIO) Controller definitions for the SAM4E
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4E_PIO_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4E_PIO_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PIO_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PIO_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -551,4 +551,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4E_PIO_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PIO_H */
diff --git a/arch/arm/src/sam34/chip/sam4l_bpm.h b/arch/arm/src/sam34/hardware/sam4l_bpm.h
similarity index 97%
rename from arch/arm/src/sam34/chip/sam4l_bpm.h
rename to arch/arm/src/sam34/hardware/sam4l_bpm.h
index 12dba10629b..2dea825d830 100644
--- a/arch/arm/src/sam34/chip/sam4l_bpm.h
+++ b/arch/arm/src/sam34/hardware/sam4l_bpm.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam4l_bpm.h
+ * arch/arm/src/sam34/hardware/sam4l_bpm.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BPM_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BPM_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BPM_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BPM_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -175,4 +175,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BPM_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BPM_H */
diff --git a/arch/arm/src/sam34/chip/sam4l_bscif.h b/arch/arm/src/sam34/hardware/sam4l_bscif.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam4l_bscif.h
rename to arch/arm/src/sam34/hardware/sam4l_bscif.h
index 6389e05d6e4..4743f877953 100644
--- a/arch/arm/src/sam34/chip/sam4l_bscif.h
+++ b/arch/arm/src/sam34/hardware/sam4l_bscif.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam4l_bscif.h
+ * arch/arm/src/sam34/hardware/sam4l_bscif.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BSCIF_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BSCIF_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BSCIF_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BSCIF_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -313,4 +313,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_BSCIF_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BSCIF_H */
diff --git a/arch/arm/src/sam34/chip/sam4l_flashcalw.h b/arch/arm/src/sam34/hardware/sam4l_flashcalw.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam4l_flashcalw.h
rename to arch/arm/src/sam34/hardware/sam4l_flashcalw.h
index 6902578d77b..baacf9120fd 100644
--- a/arch/arm/src/sam34/chip/sam4l_flashcalw.h
+++ b/arch/arm/src/sam34/hardware/sam4l_flashcalw.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/avr/src/sam34/sam4l_flashcalw.h
+ * arch/arm/src/sam34/hardware/sam4l_flashcalw.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_FLASHCALW_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_FLASHCALW_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_FLASHCALW_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_FLASHCALW_H
 
 /************************************************************************************
  * Included Files
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -375,5 +375,5 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_FLASHCALW_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_FLASHCALW_H */
 
diff --git a/arch/arm/src/sam34/chip/sam4l_gpio.h b/arch/arm/src/sam34/hardware/sam4l_gpio.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam4l_gpio.h
rename to arch/arm/src/sam34/hardware/sam4l_gpio.h
index bda888c0ae2..e80b8c5870e 100644
--- a/arch/arm/src/sam34/chip/sam4l_gpio.h
+++ b/arch/arm/src/sam34/hardware/sam4l_gpio.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam4l_gpio.h
+ * arch/arm/src/sam34/hardware/sam4l_gpio.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_GPIO_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_GPIO_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_GPIO_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_GPIO_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -592,4 +592,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_GPIO_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_GPIO_H */
diff --git a/arch/arm/src/sam34/chip/sam4l_lcdca.h b/arch/arm/src/sam34/hardware/sam4l_lcdca.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam4l_lcdca.h
rename to arch/arm/src/sam34/hardware/sam4l_lcdca.h
index 7255ecda18e..1d007a5daab 100644
--- a/arch/arm/src/sam34/chip/sam4l_lcdca.h
+++ b/arch/arm/src/sam34/hardware/sam4l_lcdca.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam4l_lcdca.h
+ * arch/arm/src/sam34/hardware/sam4l_lcdca.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_LCDCA_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_LCDCA_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_LCDCA_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_LCDCA_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -381,4 +381,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_LCDCA_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_LCDCA_H */
diff --git a/arch/arm/src/sam34/chip/sam4l_memorymap.h b/arch/arm/src/sam34/hardware/sam4l_memorymap.h
similarity index 97%
rename from arch/arm/src/sam34/chip/sam4l_memorymap.h
rename to arch/arm/src/sam34/hardware/sam4l_memorymap.h
index 62a8c6a0c5c..d1aeee757c6 100644
--- a/arch/arm/src/sam34/chip/sam4l_memorymap.h
+++ b/arch/arm/src/sam34/hardware/sam4l_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/sam34/chip/sam4l_memorymap.h
+ * arch/arm/src/sam34/hardware/sam4l_memorymap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_MEMORYMAP_H
 
 /************************************************************************************************
  * Included Files
@@ -162,4 +162,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_MEMORYMAP_H */
diff --git a/arch/arm/src/sam34/chip/sam4l_pdca.h b/arch/arm/src/sam34/hardware/sam4l_pdca.h
similarity index 97%
rename from arch/arm/src/sam34/chip/sam4l_pdca.h
rename to arch/arm/src/sam34/hardware/sam4l_pdca.h
index 14b947de420..0181b4218f6 100644
--- a/arch/arm/src/sam34/chip/sam4l_pdca.h
+++ b/arch/arm/src/sam34/hardware/sam4l_pdca.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam4l_pdca.h
+ * arch/arm/src/sam34/hardware/sam4l_pdca.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PDCA_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PDCA_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PDCA_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PDCA_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -201,4 +201,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PDCA_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PDCA_H */
diff --git a/arch/arm/src/sam34/chip/sam4l_picouart.h b/arch/arm/src/sam34/hardware/sam4l_picouart.h
similarity index 95%
rename from arch/arm/src/sam34/chip/sam4l_picouart.h
rename to arch/arm/src/sam34/hardware/sam4l_picouart.h
index 50e2d1fbbd4..cf20264244f 100644
--- a/arch/arm/src/sam34/chip/sam4l_picouart.h
+++ b/arch/arm/src/sam34/hardware/sam4l_picouart.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam4l_picouart.h
+ * arch/arm/src/sam34/hardware/sam4l_picouart.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PICOUART_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PICOUART_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PICOUART_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PICOUART_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -118,4 +118,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PICOUART_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PICOUART_H */
diff --git a/arch/arm/src/sam34/chip/sam4l_pinmap.h b/arch/arm/src/sam34/hardware/sam4l_pinmap.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam4l_pinmap.h
rename to arch/arm/src/sam34/hardware/sam4l_pinmap.h
index 7cf80dd4ac1..476bdeeaba9 100644
--- a/arch/arm/src/sam34/chip/sam4l_pinmap.h
+++ b/arch/arm/src/sam34/hardware/sam4l_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sam34/chip/sam3u_pinmap.h
+ * arch/arm/src/sam34/hardware/sam3u_pinmap.h
  *
  *   Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PINMAP_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -58,7 +58,7 @@
  *
  * #define GPIO_SPI_MISO GPIO_SPI_MISO_1
  *
- * The driver will then automatically configre PA21 as the SPI MISO pin.
+ * The driver will then automatically configure PA21 as the SPI MISO pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -576,4 +576,4 @@ extern "C"
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H */
diff --git a/arch/arm/src/sam34/chip/sam4l_pm.h b/arch/arm/src/sam34/hardware/sam4l_pm.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam4l_pm.h
rename to arch/arm/src/sam34/hardware/sam4l_pm.h
index 86a55af8dc1..6b4eada8fca 100644
--- a/arch/arm/src/sam34/chip/sam4l_pm.h
+++ b/arch/arm/src/sam34/hardware/sam4l_pm.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/avr/src/sam34/sam4l_pm.h
+ * arch/arm/src/sam34/hardware/sam4l_pm.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PM_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PM_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PM_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PM_H
 
 /************************************************************************************
  * Included Files
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -347,5 +347,5 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_PM_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PM_H */
 
diff --git a/arch/arm/src/sam34/chip/sam4l_scif.h b/arch/arm/src/sam34/hardware/sam4l_scif.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam4l_scif.h
rename to arch/arm/src/sam34/hardware/sam4l_scif.h
index 191d786bc3f..6595cb1c031 100644
--- a/arch/arm/src/sam34/chip/sam4l_scif.h
+++ b/arch/arm/src/sam34/hardware/sam4l_scif.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam4l_scif.h
+ * arch/arm/src/sam34/hardware/sam4l_scif.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_SCIF_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_SCIF_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_SCIF_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_SCIF_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -429,4 +429,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_SCIF_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_SCIF_H */
diff --git a/arch/arm/src/sam34/chip/sam4l_usart.h b/arch/arm/src/sam34/hardware/sam4l_usart.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam4l_usart.h
rename to arch/arm/src/sam34/hardware/sam4l_usart.h
index 3c5bbd21ff4..4e7a3552fd9 100644
--- a/arch/arm/src/sam34/chip/sam4l_usart.h
+++ b/arch/arm/src/sam34/hardware/sam4l_usart.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/sam34/chip/sam4l_uart.h
+ * arch/arm/src/sam34/hardware/sam4l_uart.h
  * Universal Synchronous Asynchronous Receiver Transmitter (USART) definitions for the SAM4L
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_UART_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_UART_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_UART_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_UART_H
 
 /************************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************************
  * Pre-processor Definitions
@@ -445,4 +445,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_UART_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_UART_H */
diff --git a/arch/arm/src/sam34/chip/sam4l_wdt.h b/arch/arm/src/sam34/hardware/sam4l_wdt.h
similarity index 96%
rename from arch/arm/src/sam34/chip/sam4l_wdt.h
rename to arch/arm/src/sam34/hardware/sam4l_wdt.h
index 9c37c922a99..70de2c35362 100644
--- a/arch/arm/src/sam34/chip/sam4l_wdt.h
+++ b/arch/arm/src/sam34/hardware/sam4l_wdt.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam4l_wdt.h
+ * arch/arm/src/sam34/hardware/sam4l_wdt.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_WDT_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_WDT_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_WDT_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_WDT_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -134,4 +134,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_WDT_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_WDT_H */
diff --git a/arch/arm/src/sam34/chip/sam4s_memorymap.h b/arch/arm/src/sam34/hardware/sam4s_memorymap.h
similarity index 97%
rename from arch/arm/src/sam34/chip/sam4s_memorymap.h
rename to arch/arm/src/sam34/hardware/sam4s_memorymap.h
index 45e8a97a3f6..f13d5a89ceb 100644
--- a/arch/arm/src/sam34/chip/sam4s_memorymap.h
+++ b/arch/arm/src/sam34/hardware/sam4s_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/sam34/chip/sam4s_memorymap.h
+ * arch/arm/src/sam34/hardware/sam4s_memorymap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_MEMORYMAP_H
 
 /************************************************************************************************
  * Included Files
@@ -153,4 +153,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_MEMORYMAP_H */
diff --git a/arch/arm/src/sam34/chip/sam4s_pinmap.h b/arch/arm/src/sam34/hardware/sam4s_pinmap.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam4s_pinmap.h
rename to arch/arm/src/sam34/hardware/sam4s_pinmap.h
index b8fd5c46ecc..b0256e444f6 100644
--- a/arch/arm/src/sam34/chip/sam4s_pinmap.h
+++ b/arch/arm/src/sam34/hardware/sam4s_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sam34/chip/sam4s_pinmap.h
+ * arch/arm/src/sam34/hardware/sam4s_pinmap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PINMAP_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PINMAP_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -311,4 +311,4 @@ extern "C"
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PINMAP_H */
diff --git a/arch/arm/src/sam34/chip/sam4s_pio.h b/arch/arm/src/sam34/hardware/sam4s_pio.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam4s_pio.h
rename to arch/arm/src/sam34/hardware/sam4s_pio.h
index be65af3b57b..d599cf39a1a 100644
--- a/arch/arm/src/sam34/chip/sam4s_pio.h
+++ b/arch/arm/src/sam34/hardware/sam4s_pio.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam4s_pio.h
+ * arch/arm/src/sam34/hardware/sam4s_pio.h
  * Parallel Input/Output (PIO) Controller definitions for the SAM4S
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PIO_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PIO_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PIO_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PIO_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -398,4 +398,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4S_PIO_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PIO_H */
diff --git a/arch/arm/src/sam34/chip/sam_acc.h b/arch/arm/src/sam34/hardware/sam_acc.h
similarity index 97%
rename from arch/arm/src/sam34/chip/sam_acc.h
rename to arch/arm/src/sam34/hardware/sam_acc.h
index 1e546ac14a7..cff3627a0d9 100644
--- a/arch/arm/src/sam34/chip/sam_acc.h
+++ b/arch/arm/src/sam34/hardware/sam_acc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_rtt.h
+ * arch/arm/src/sam34/hardware/sam_rtt.h
  *Analog Comparator Controller (ACC) definitions for the SAM4E
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_ACC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_ACC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ACC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ACC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -151,4 +151,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_ACC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ACC_H */
diff --git a/arch/arm/src/sam34/chip/sam_adc.h b/arch/arm/src/sam34/hardware/sam_adc.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam_adc.h
rename to arch/arm/src/sam34/hardware/sam_adc.h
index dd53ba4012e..077ad273153 100644
--- a/arch/arm/src/sam34/chip/sam_adc.h
+++ b/arch/arm/src/sam34/hardware/sam_adc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_adc.h
+ * arch/arm/src/sam34/hardware/sam_adc.h
  *
  *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_ADC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_ADC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ADC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ADC_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -244,4 +244,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_ADC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ADC_H */
diff --git a/arch/arm/src/sam34/chip/sam_aes.h b/arch/arm/src/sam34/hardware/sam_aes.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam_aes.h
rename to arch/arm/src/sam34/hardware/sam_aes.h
index c5ef7ad9a67..22410d43b7d 100644
--- a/arch/arm/src/sam34/chip/sam_aes.h
+++ b/arch/arm/src/sam34/hardware/sam_aes.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_aes.h
+ * arch/arm/src/sam34/hardware/sam_aes.h
  * Advanced Encryption Standard (AES) for the SAM4E
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_AES_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_AES_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AES_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AES_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -185,4 +185,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_AES_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AES_H */
diff --git a/arch/arm/src/sam34/chip/sam_afec.h b/arch/arm/src/sam34/hardware/sam_afec.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam_afec.h
rename to arch/arm/src/sam34/hardware/sam_afec.h
index d5a8be44ab9..88c7181beb0 100644
--- a/arch/arm/src/sam34/chip/sam_afec.h
+++ b/arch/arm/src/sam34/hardware/sam_afec.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_afec.h
+ * arch/arm/src/sam34/hardware/sam_afec.h
  * Analog-Front-End Controller (AFEC) definitions for the SAM4E
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_AFEC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_AFEC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AFEC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AFEC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -535,4 +535,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_AFEC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AFEC_H */
diff --git a/arch/arm/src/sam34/chip/sam_can.h b/arch/arm/src/sam34/hardware/sam_can.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam_can.h
rename to arch/arm/src/sam34/hardware/sam_can.h
index 22548314e7d..05e92186188 100644
--- a/arch/arm/src/sam34/chip/sam_can.h
+++ b/arch/arm/src/sam34/hardware/sam_can.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_can.h
+ * arch/arm/src/sam34/hardware/sam_can.h
  * Controller Area Network (CAN) for the SAM4E
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_CAN_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_CAN_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CAN_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CAN_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -316,4 +316,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_CAN_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CAN_H */
diff --git a/arch/arm/src/sam34/chip/sam_chipid.h b/arch/arm/src/sam34/hardware/sam_chipid.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam_chipid.h
rename to arch/arm/src/sam34/hardware/sam_chipid.h
index c09e538367e..f578ac0ec69 100644
--- a/arch/arm/src/sam34/chip/sam_chipid.h
+++ b/arch/arm/src/sam34/hardware/sam_chipid.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_chipid.h
+ * arch/arm/src/sam34/hardware/sam_chipid.h
  * CHIPID Register Definitions for the SAM3U, SAM4S, and SAM4L
  *
  *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_CHIPID_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_CHIPID_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CHIPID_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CHIPID_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -198,4 +198,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_CHIPID_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CHIPID_H */
diff --git a/arch/arm/src/sam34/chip/sam_cmcc.h b/arch/arm/src/sam34/hardware/sam_cmcc.h
similarity index 97%
rename from arch/arm/src/sam34/chip/sam_cmcc.h
rename to arch/arm/src/sam34/hardware/sam_cmcc.h
index 0d0d96b9161..cfc471925b6 100644
--- a/arch/arm/src/sam34/chip/sam_cmcc.h
+++ b/arch/arm/src/sam34/hardware/sam_cmcc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_cmcc.h
+ * arch/arm/src/sam34/hardware/sam_cmcc.h
  * Cortex M Cache Controller (CMCC) for the SAM4E
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_CMCC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_CMCC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CMCC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CMCC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -178,4 +178,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_CMCC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CMCC_H */
diff --git a/arch/arm/src/sam34/chip/sam_dacc.h b/arch/arm/src/sam34/hardware/sam_dacc.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam_dacc.h
rename to arch/arm/src/sam34/hardware/sam_dacc.h
index 80a61d874a7..cdd06a30228 100644
--- a/arch/arm/src/sam34/chip/sam_dacc.h
+++ b/arch/arm/src/sam34/hardware/sam_dacc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_dacc.h
+ * arch/arm/src/sam34/hardware/sam_dacc.h
  * Digital-to-Analog Converter Controller (DACC) for the SAM4E
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_DACC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_DACC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DACC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DACC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -229,4 +229,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_DACC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DACC_H */
diff --git a/arch/arm/src/sam34/chip/sam_dmac.h b/arch/arm/src/sam34/hardware/sam_dmac.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam_dmac.h
rename to arch/arm/src/sam34/hardware/sam_dmac.h
index 1a02ab4ec8b..66a26546ae4 100644
--- a/arch/arm/src/sam34/chip/sam_dmac.h
+++ b/arch/arm/src/sam34/hardware/sam_dmac.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_dmac.h
+ * arch/arm/src/sam34/hardware/sam_dmac.h
  * DMA Controller (DMAC) definitions for the SAM3U, SAM3X, SAM3A, and SAM4E
  *
  *   Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_DMAC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_DMAC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DMAC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DMAC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -535,4 +535,4 @@ struct dma_linklist_s
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_DMAC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DMAC_H */
diff --git a/arch/arm/src/sam34/chip/sam_eefc.h b/arch/arm/src/sam34/hardware/sam_eefc.h
similarity index 97%
rename from arch/arm/src/sam34/chip/sam_eefc.h
rename to arch/arm/src/sam34/hardware/sam_eefc.h
index e247465f1c1..d5452ed614c 100644
--- a/arch/arm/src/sam34/chip/sam_eefc.h
+++ b/arch/arm/src/sam34/hardware/sam_eefc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_eefc.h
+ * arch/arm/src/sam34/hardware/sam_eefc.h
  * Enhanced Embedded Flash Controller (EEFC) definitions for the SAM3U, SAM3X, SAM3A,
  * SAM4E, and SAM4S
  *
@@ -35,8 +35,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_EEFC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_EEFC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EEFC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EEFC_H
 
 /****************************************************************************************
  * Included Files
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -164,4 +164,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_EEFC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EEFC_H */
diff --git a/arch/arm/src/sam34/chip/sam_emac.h b/arch/arm/src/sam34/hardware/sam_emac.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam_emac.h
rename to arch/arm/src/sam34/hardware/sam_emac.h
index d5e8bf037e9..ee99d4f4727 100644
--- a/arch/arm/src/sam34/chip/sam_emac.h
+++ b/arch/arm/src/sam34/hardware/sam_emac.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sam34/chip/sam_emac.h
+ * arch/arm/src/sam34/hardware/sam_emac.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_EMAC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_EMAC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EMAC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EMAC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -668,4 +668,4 @@ struct emac_txdesc_s
   uint32_t status;   /* TX status and controls */
 };
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_EMAC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EMAC_H */
diff --git a/arch/arm/src/sam34/chip/sam_gpbr.h b/arch/arm/src/sam34/hardware/sam_gpbr.h
similarity index 95%
rename from arch/arm/src/sam34/chip/sam_gpbr.h
rename to arch/arm/src/sam34/hardware/sam_gpbr.h
index 8e20925501f..1b67c55bc7c 100644
--- a/arch/arm/src/sam34/chip/sam_gpbr.h
+++ b/arch/arm/src/sam34/hardware/sam_gpbr.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_gpbr.h
+ * arch/arm/src/sam34/hardware/sam_gpbr.h
  *
  *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_GPBR_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_GPBR_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_GPBR_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_GPBR_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -119,4 +119,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_GPBR_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_GPBR_H */
diff --git a/arch/arm/src/sam34/chip/sam_hsmci.h b/arch/arm/src/sam34/hardware/sam_hsmci.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam_hsmci.h
rename to arch/arm/src/sam34/hardware/sam_hsmci.h
index fa3b375b7ac..db246e99c11 100644
--- a/arch/arm/src/sam34/chip/sam_hsmci.h
+++ b/arch/arm/src/sam34/hardware/sam_hsmci.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_hsmci.h
+ * arch/arm/src/sam34/hardware/sam_hsmci.h
  *
  *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_HSMCI_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_HSMCI_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_HSMCI_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_HSMCI_H
 
 /****************************************************************************************
  * Included Files
@@ -43,8 +43,8 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_pdc.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_pdc.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -363,4 +363,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_HSMCI_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_HSMCI_H */
diff --git a/arch/arm/src/sam34/chip/sam_matrix.h b/arch/arm/src/sam34/hardware/sam_matrix.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam_matrix.h
rename to arch/arm/src/sam34/hardware/sam_matrix.h
index f519d5c6332..975803b6dd5 100644
--- a/arch/arm/src/sam34/chip/sam_matrix.h
+++ b/arch/arm/src/sam34/hardware/sam_matrix.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_matrix.h
+ * arch/arm/src/sam34/hardware/sam_matrix.h
  * Bux matrix definitions for the SAM3U, SAM3X, SAM3A, SAM4E, and SAM4S
  *
  *   Copyright (C) 2009-2010, 2013-2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MATRIX_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MATRIX_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -368,4 +368,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_MATRIX_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MATRIX_H */
diff --git a/arch/arm/src/sam34/chip/sam_memorymap.h b/arch/arm/src/sam34/hardware/sam_memorymap.h
similarity index 83%
rename from arch/arm/src/sam34/chip/sam_memorymap.h
rename to arch/arm/src/sam34/hardware/sam_memorymap.h
index 8ec74f3b2df..e0ddc6650c2 100644
--- a/arch/arm/src/sam34/chip/sam_memorymap.h
+++ b/arch/arm/src/sam34/hardware/sam_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sam34/chip/sam_memorymap.h
+ * arch/arm/src/sam34/hardware/sam_memorymap.h
  *
  *   Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -44,20 +44,20 @@
 #include 
 
 #if defined(CONFIG_ARCH_CHIP_SAM3U)
-#  include "chip/sam3u_memorymap.h"
+#  include "hardware/sam3u_memorymap.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
-#  include "chip/sam3x_memorymap.h"
+#  include "hardware/sam3x_memorymap.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4CM)
-#  include "chip/sam4cm_memorymap.h"
+#  include "hardware/sam4cm_memorymap.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4E)
-#  include "chip/sam4e_memorymap.h"
+#  include "hardware/sam4e_memorymap.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4L)
-#  include "chip/sam4l_memorymap.h"
+#  include "hardware/sam4l_memorymap.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4S)
-#  include "chip/sam4s_memorymap.h"
+#  include "hardware/sam4s_memorymap.h"
 #else
 #  error Unrecognized SAM architecture
 #endif
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MEMORYMAP_H */
 
diff --git a/arch/arm/src/sam34/chip/sam_pdc.h b/arch/arm/src/sam34/hardware/sam_pdc.h
similarity index 96%
rename from arch/arm/src/sam34/chip/sam_pdc.h
rename to arch/arm/src/sam34/hardware/sam_pdc.h
index 2654508c13a..d9ceae6260a 100644
--- a/arch/arm/src/sam34/chip/sam_pdc.h
+++ b/arch/arm/src/sam34/hardware/sam_pdc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_pdc.h
+ * arch/arm/src/sam34/hardware/sam_pdc.h
  *
  *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PDC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PDC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PDC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PDC_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -116,4 +116,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PDC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PDC_H */
diff --git a/arch/arm/src/sam34/chip/sam_pinmap.h b/arch/arm/src/sam34/hardware/sam_pinmap.h
similarity index 84%
rename from arch/arm/src/sam34/chip/sam_pinmap.h
rename to arch/arm/src/sam34/hardware/sam_pinmap.h
index bf79625e88a..43ba17f1e6e 100644
--- a/arch/arm/src/sam34/chip/sam_pinmap.h
+++ b/arch/arm/src/sam34/hardware/sam_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sam34/chip/sam_pinmap.h
+ * arch/arm/src/sam34/hardware/sam_pinmap.h
  *
  *   Copyright (C) 2012-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PINMAP_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PINMAP_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -44,20 +44,20 @@
 #include "chip.h"
 
 #if defined(CONFIG_ARCH_CHIP_SAM3U)
-#  include "chip/sam3u_pinmap.h"
+#  include "hardware/sam3u_pinmap.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
-#  include "chip/sam3x_pinmap.h"
+#  include "hardware/sam3x_pinmap.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4CM)
-#  include "chip/sam4cm_pinmap.h"
+#  include "hardware/sam4cm_pinmap.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4E)
-#  include "chip/sam4e_pinmap.h"
+#  include "hardware/sam4e_pinmap.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4L)
-#  include "chip/sam4l_pinmap.h"
+#  include "hardware/sam4l_pinmap.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4S)
-#  include "chip/sam4s_pinmap.h"
+#  include "hardware/sam4s_pinmap.h"
 #else
 #  error Unrecognized SAM architecture
 #endif
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PINMAP_H */
 
diff --git a/arch/arm/src/sam34/chip/sam_pmc.h b/arch/arm/src/sam34/hardware/sam_pmc.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam_pmc.h
rename to arch/arm/src/sam34/hardware/sam_pmc.h
index d7a75f6b038..66a2fe5e893 100644
--- a/arch/arm/src/sam34/chip/sam_pmc.h
+++ b/arch/arm/src/sam34/hardware/sam_pmc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/sam34/chip/sam_pmc.h
+ * arch/arm/src/sam34/hardware/sam_pmc.h
  * Power Management Controller (PMC) for the SAM3U, SAM3X, SAM3A, SAM4CM, SAM4E, and
  * SAM4S
  *
@@ -35,8 +35,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PMC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PMC_H
 
 /********************************************************************************************
  * Included Files
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -622,4 +622,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PMC_H */
diff --git a/arch/arm/src/sam34/chip/sam_pwm.h b/arch/arm/src/sam34/hardware/sam_pwm.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam_pwm.h
rename to arch/arm/src/sam34/hardware/sam_pwm.h
index 79b9aa043a9..4571448a700 100644
--- a/arch/arm/src/sam34/chip/sam_pwm.h
+++ b/arch/arm/src/sam34/hardware/sam_pwm.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_pwm.h
+ * arch/arm/src/sam34/hardware/sam_pwm.h
  * Pulse Width Modulation Controller (PWM) definitions for the SAM3U, SAM4E and SAM4S
  *
  *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PWM_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PWM_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PWM_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PWM_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -846,4 +846,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PWM_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PWM_H */
diff --git a/arch/arm/src/sam34/chip/sam_rstc.h b/arch/arm/src/sam34/hardware/sam_rstc.h
similarity index 96%
rename from arch/arm/src/sam34/chip/sam_rstc.h
rename to arch/arm/src/sam34/hardware/sam_rstc.h
index 60250ef832f..911830c7438 100644
--- a/arch/arm/src/sam34/chip/sam_rstc.h
+++ b/arch/arm/src/sam34/hardware/sam_rstc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_rstc.h
+ * arch/arm/src/sam34/hardware/sam_rstc.h
  * Reset Controller (RSTC) definitions for the SAM3U, SAM4E, and SAM4S
  *
  *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_RSTC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_RSTC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSTC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSTC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -125,4 +125,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_RSTC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSTC_H */
diff --git a/arch/arm/src/sam34/chip/sam_rswdt.h b/arch/arm/src/sam34/hardware/sam_rswdt.h
similarity index 95%
rename from arch/arm/src/sam34/chip/sam_rswdt.h
rename to arch/arm/src/sam34/hardware/sam_rswdt.h
index 69ed294ea57..50903284907 100644
--- a/arch/arm/src/sam34/chip/sam_rswdt.h
+++ b/arch/arm/src/sam34/hardware/sam_rswdt.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_rswdt.h
+ * arch/arm/src/sam34/hardware/sam_rswdt.h
  * Reinforced Safety Watchdog Timer (RSWDT) for the SAM4E
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_RSWDT_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_RSWDT_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSWDT_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSWDT_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -102,4 +102,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_RSWDT_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSWDT_H */
diff --git a/arch/arm/src/sam34/chip/sam_rtc.h b/arch/arm/src/sam34/hardware/sam_rtc.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam_rtc.h
rename to arch/arm/src/sam34/hardware/sam_rtc.h
index b15cba7009b..5ad40ed0227 100644
--- a/arch/arm/src/sam34/chip/sam_rtc.h
+++ b/arch/arm/src/sam34/hardware/sam_rtc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_rtc.h
+ * arch/arm/src/sam34/hardware/sam_rtc.h
  * Real-time Clock (RTC) definitions for the SAM3U, SAM4E, and SAM4S
  *
  *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_RTC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_RTC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -280,4 +280,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_RTC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTC_H */
diff --git a/arch/arm/src/sam34/chip/sam_rtt.h b/arch/arm/src/sam34/hardware/sam_rtt.h
similarity index 95%
rename from arch/arm/src/sam34/chip/sam_rtt.h
rename to arch/arm/src/sam34/hardware/sam_rtt.h
index b0ddcb621be..8a87b3168ff 100644
--- a/arch/arm/src/sam34/chip/sam_rtt.h
+++ b/arch/arm/src/sam34/hardware/sam_rtt.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_rtt.h
+ * arch/arm/src/sam34/hardware/sam_rtt.h
  * Real-time Timer (RTT) definitions for the SAM3U, SAM4E, and SAM4S
  *
  *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_RTT_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_RTT_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTT_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTT_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -100,4 +100,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_RTT_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTT_H */
diff --git a/arch/arm/src/sam34/chip/sam_smc.h b/arch/arm/src/sam34/hardware/sam_smc.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam_smc.h
rename to arch/arm/src/sam34/hardware/sam_smc.h
index 6ed0ea98d98..a1b396baf2a 100644
--- a/arch/arm/src/sam34/chip/sam_smc.h
+++ b/arch/arm/src/sam34/hardware/sam_smc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_smc.h
+ * arch/arm/src/sam34/hardware/sam_smc.h
  * Static Memory Controller (SMC) definitions for the SAM3U, SAM4E, and SAM4S
  *
  *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_SMC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_SMC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SMC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SMC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -613,4 +613,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_SMC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SMC_H */
diff --git a/arch/arm/src/sam34/chip/sam_spi.h b/arch/arm/src/sam34/hardware/sam_spi.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam_spi.h
rename to arch/arm/src/sam34/hardware/sam_spi.h
index ce740c22e55..a22326cb302 100644
--- a/arch/arm/src/sam34/chip/sam_spi.h
+++ b/arch/arm/src/sam34/hardware/sam_spi.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_spi.h
+ * arch/arm/src/sam34/hardware/sam_spi.h
  * Serial Peripheral Interface (SPI) definitions for the SAM3U, SAM4S, SAM4E, and SAM4L
  *
  *   Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_SPI_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_SPI_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SPI_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SPI_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -287,4 +287,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_SPI_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SPI_H */
diff --git a/arch/arm/src/sam34/chip/sam_ssc.h b/arch/arm/src/sam34/hardware/sam_ssc.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam_ssc.h
rename to arch/arm/src/sam34/hardware/sam_ssc.h
index c1b6fd7ce36..5e28cc04208 100644
--- a/arch/arm/src/sam34/chip/sam_ssc.h
+++ b/arch/arm/src/sam34/hardware/sam_ssc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_ssc.h
+ * arch/arm/src/sam34/hardware/sam_ssc.h
  * Synchronous Serial Controller (SSC) definitions for the SAM3U and SAM4S
  *
  *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_SSC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_SSC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SSC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SSC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -292,4 +292,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_SSC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SSC_H */
diff --git a/arch/arm/src/sam34/chip/sam_supc.h b/arch/arm/src/sam34/hardware/sam_supc.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam_supc.h
rename to arch/arm/src/sam34/hardware/sam_supc.h
index d0095f42a69..6d571868e72 100644
--- a/arch/arm/src/sam34/chip/sam_supc.h
+++ b/arch/arm/src/sam34/hardware/sam_supc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_supc.h
+ * arch/arm/src/sam34/hardware/sam_supc.h
  * Supply Controller (SUPC) definitions for the SAM3U, SAM3X, SAM3A, SAM4E, and SAM4S
  *
  *   Copyright (C) 2009, 2013-2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_SUPC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_SUPC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SUPC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SUPC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -284,4 +284,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_SUPC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SUPC_H */
diff --git a/arch/arm/src/sam34/chip/sam_tc.h b/arch/arm/src/sam34/hardware/sam_tc.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam_tc.h
rename to arch/arm/src/sam34/hardware/sam_tc.h
index e5951fcdc9a..20bccbdf573 100644
--- a/arch/arm/src/sam34/chip/sam_tc.h
+++ b/arch/arm/src/sam34/hardware/sam_tc.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/sam34/chip/sam_tc.h
+ * arch/arm/src/sam34/hardware/sam_tc.h
  * Timer Counter (TC) definitions for the SAM3U, SAM4E, and SAM4S
  *
  *   Copyright (C) 2009, 2013-2014, 2016 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_TC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_TC_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TC_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TC_H
 
 /************************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************************
  * Pre-processor Definitions
@@ -594,4 +594,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_TC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TC_H */
diff --git a/arch/arm/src/sam34/chip/sam_twi.h b/arch/arm/src/sam34/hardware/sam_twi.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam_twi.h
rename to arch/arm/src/sam34/hardware/sam_twi.h
index 2f843dd07c3..9904fd10901 100644
--- a/arch/arm/src/sam34/chip/sam_twi.h
+++ b/arch/arm/src/sam34/hardware/sam_twi.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_twi.h
+ * arch/arm/src/sam34/hardware/sam_twi.h
  * Two-wire Interface (TWI) definitions for the SAM3U, SAM4E, and SAM4S
  *
  *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_TWI_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_TWI_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TWI_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TWI_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -229,4 +229,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_TWI_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TWI_H */
diff --git a/arch/arm/src/sam34/chip/sam_uart.h b/arch/arm/src/sam34/hardware/sam_uart.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam_uart.h
rename to arch/arm/src/sam34/hardware/sam_uart.h
index a80a898704e..87161c7de4f 100644
--- a/arch/arm/src/sam34/chip/sam_uart.h
+++ b/arch/arm/src/sam34/hardware/sam_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/sam34/chip/sam_uart.h
+ * arch/arm/src/sam34/hardware/sam_uart.h
  * Universal Asynchronous Receiver Transmitter (UART) and Universal Synchronous Asynchronous
  * Receiver Transmitter (USART) definitions for the SAM3U, SAM3X, SAM3A, SAM4S and SAM4E
  *
@@ -35,8 +35,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_UART_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_UART_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UART_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UART_H
 
 /************************************************************************************************
  * Included Files
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************************
  * Pre-processor Definitions
@@ -569,4 +569,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_UART_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UART_H */
diff --git a/arch/arm/src/sam34/chip/sam_udp.h b/arch/arm/src/sam34/hardware/sam_udp.h
similarity index 98%
rename from arch/arm/src/sam34/chip/sam_udp.h
rename to arch/arm/src/sam34/hardware/sam_udp.h
index 267bcc43ae8..af7becb07d0 100644
--- a/arch/arm/src/sam34/chip/sam_udp.h
+++ b/arch/arm/src/sam34/hardware/sam_udp.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_udp.h
+ * arch/arm/src/sam34/hardware/sam_udp.h
  * USB Device Port (UDP) definitions for the SAM4E
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_UDP_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_UDP_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDP_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDP_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -258,4 +258,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_UDP_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDP_H */
diff --git a/arch/arm/src/sam34/chip/sam_udphs.h b/arch/arm/src/sam34/hardware/sam_udphs.h
similarity index 99%
rename from arch/arm/src/sam34/chip/sam_udphs.h
rename to arch/arm/src/sam34/hardware/sam_udphs.h
index e359c555588..56666705a09 100644
--- a/arch/arm/src/sam34/chip/sam_udphs.h
+++ b/arch/arm/src/sam34/hardware/sam_udphs.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_udphs.h
+ * arch/arm/src/sam34/hardware/sam_udphs.h
  *
  *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_UDPHS_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_UDPHS_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDPHS_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDPHS_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -367,5 +367,5 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_UDPHS_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDPHS_H */
 
diff --git a/arch/arm/src/sam34/chip/sam_wdt.h b/arch/arm/src/sam34/hardware/sam_wdt.h
similarity index 95%
rename from arch/arm/src/sam34/chip/sam_wdt.h
rename to arch/arm/src/sam34/hardware/sam_wdt.h
index b2dd810b9d9..6c876c97da2 100644
--- a/arch/arm/src/sam34/chip/sam_wdt.h
+++ b/arch/arm/src/sam34/hardware/sam_wdt.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_wdt.h
+ * arch/arm/src/sam34/hardware/sam_wdt.h
  * Watchdog Timer (WDT) definitions for the SAM3U, SAM3X, SAM3A, SAM4E, and SAM4S
  *
  *   Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H
+#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_WDT_H
+#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_WDT_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -104,4 +104,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_WDT_H */
+#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_WDT_H */
diff --git a/arch/arm/src/sam34/sam3u_periphclks.h b/arch/arm/src/sam34/sam3u_periphclks.h
index 145ebe4ac48..c652ab67c7a 100644
--- a/arch/arm/src/sam34/sam3u_periphclks.h
+++ b/arch/arm/src/sam34/sam3u_periphclks.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 #include 
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pmc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sam34/sam3x_periphclks.h b/arch/arm/src/sam34/sam3x_periphclks.h
index f20a86a0e8d..a9f6ac690b4 100644
--- a/arch/arm/src/sam34/sam3x_periphclks.h
+++ b/arch/arm/src/sam34/sam3x_periphclks.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 #include 
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pmc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sam34/sam4cm_cpupause.c b/arch/arm/src/sam34/sam4cm_cpupause.c
index f2587811276..933509d81fc 100644
--- a/arch/arm/src/sam34/sam4cm_cpupause.c
+++ b/arch/arm/src/sam34/sam4cm_cpupause.c
@@ -52,7 +52,7 @@
 #include "up_arch.h"
 #include "sched/sched.h"
 #include "up_internal.h"
-#include "chip/sam4cm_ipc.h"
+#include "hardware/sam4cm_ipc.h"
 
 #ifdef CONFIG_SMP
 
diff --git a/arch/arm/src/sam34/sam4cm_cpustart.c b/arch/arm/src/sam34/sam4cm_cpustart.c
index 33dd5ef47a6..a66e1f5f200 100644
--- a/arch/arm/src/sam34/sam4cm_cpustart.c
+++ b/arch/arm/src/sam34/sam4cm_cpustart.c
@@ -55,9 +55,9 @@
 #include "sched/sched.h"
 #include "init/init.h"
 #include "up_internal.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_rstc.h"
-#include "chip/sam4cm_ipc.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_rstc.h"
+#include "hardware/sam4cm_ipc.h"
 #include "sam4cm_periphclks.h"
 
 #ifdef CONFIG_SMP
diff --git a/arch/arm/src/sam34/sam4cm_periphclks.h b/arch/arm/src/sam34/sam4cm_periphclks.h
index 9584c891705..400c1e94576 100644
--- a/arch/arm/src/sam34/sam4cm_periphclks.h
+++ b/arch/arm/src/sam34/sam4cm_periphclks.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 #include 
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pmc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sam34/sam4cm_supc.c b/arch/arm/src/sam34/sam4cm_supc.c
index 468466b80fe..5cb86181503 100644
--- a/arch/arm/src/sam34/sam4cm_supc.c
+++ b/arch/arm/src/sam34/sam4cm_supc.c
@@ -51,7 +51,7 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/sam_supc.h"
+#include "hardware/sam_supc.h"
 
 #include "sam4cm_supc.h"
 
diff --git a/arch/arm/src/sam34/sam4cm_tc.c b/arch/arm/src/sam34/sam4cm_tc.c
index 79cc61cfdbe..760a8a3bd01 100644
--- a/arch/arm/src/sam34/sam4cm_tc.c
+++ b/arch/arm/src/sam34/sam4cm_tc.c
@@ -63,8 +63,8 @@
 
 #include "up_arch.h"
 #include "sam_periphclks.h"
-#include "chip/sam_pinmap.h"
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
 #include "sam_gpio.h"
 
 #include "sam4cm_tc.h"
diff --git a/arch/arm/src/sam34/sam4cm_tc.h b/arch/arm/src/sam34/sam4cm_tc.h
index e474f2bc666..46f0f87ccbe 100644
--- a/arch/arm/src/sam34/sam4cm_tc.h
+++ b/arch/arm/src/sam34/sam4cm_tc.h
@@ -46,7 +46,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_tc.h"
+#include "hardware/sam_tc.h"
 
 #if defined(CONFIG_SAM34_TC0) || defined(CONFIG_SAM34_TC1) || defined(CONFIG_SAM34_TC2)
 
diff --git a/arch/arm/src/sam34/sam4e_periphclks.h b/arch/arm/src/sam34/sam4e_periphclks.h
index 5f41fee35fb..5ed9812ab7f 100644
--- a/arch/arm/src/sam34/sam4e_periphclks.h
+++ b/arch/arm/src/sam34/sam4e_periphclks.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 #include 
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pmc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sam34/sam4l_clockconfig.c b/arch/arm/src/sam34/sam4l_clockconfig.c
index 3b6ec2a7013..86c90a7b834 100644
--- a/arch/arm/src/sam34/sam4l_clockconfig.c
+++ b/arch/arm/src/sam34/sam4l_clockconfig.c
@@ -50,11 +50,11 @@
 #include "up_arch.h"
 
 #include "up_internal.h"
-#include "chip/sam4l_pm.h"
-#include "chip/sam4l_scif.h"
-#include "chip/sam4l_bpm.h"
-#include "chip/sam4l_bscif.h"
-#include "chip/sam4l_flashcalw.h"
+#include "hardware/sam4l_pm.h"
+#include "hardware/sam4l_scif.h"
+#include "hardware/sam4l_bpm.h"
+#include "hardware/sam4l_bscif.h"
+#include "hardware/sam4l_flashcalw.h"
 
 #include "sam4l_periphclks.h"
 #include "sam_clockconfig.h"
diff --git a/arch/arm/src/sam34/sam4l_gpio.c b/arch/arm/src/sam34/sam4l_gpio.c
index 02394a543fa..140ec42787f 100644
--- a/arch/arm/src/sam34/sam4l_gpio.c
+++ b/arch/arm/src/sam34/sam4l_gpio.c
@@ -53,7 +53,7 @@
 
 #include "chip.h"
 #include "sam_gpio.h"
-#include "chip/sam4l_gpio.h"
+#include "hardware/sam4l_gpio.h"
 
 /****************************************************************************
  * Private Data
diff --git a/arch/arm/src/sam34/sam4l_periphclks.c b/arch/arm/src/sam34/sam4l_periphclks.c
index 29e9d3cbf3a..2a9984b3d9a 100644
--- a/arch/arm/src/sam34/sam4l_periphclks.c
+++ b/arch/arm/src/sam34/sam4l_periphclks.c
@@ -47,7 +47,7 @@
 #include "up_arch.h"
 
 #include "up_internal.h"
-#include "chip/sam4l_pm.h"
+#include "hardware/sam4l_pm.h"
 
 #include "sam4l_periphclks.h"
 
diff --git a/arch/arm/src/sam34/sam4l_periphclks.h b/arch/arm/src/sam34/sam4l_periphclks.h
index c092e243aa4..e96704a36ca 100644
--- a/arch/arm/src/sam34/sam4l_periphclks.h
+++ b/arch/arm/src/sam34/sam4l_periphclks.h
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam4l_pm.h"
+#include "hardware/sam4l_pm.h"
 
 #ifdef CONFIG_ARCH_CHIP_SAM4L
 
diff --git a/arch/arm/src/sam34/sam4s_periphclks.h b/arch/arm/src/sam34/sam4s_periphclks.h
index 1477ef2532c..69c02c70376 100644
--- a/arch/arm/src/sam34/sam4s_periphclks.h
+++ b/arch/arm/src/sam34/sam4s_periphclks.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 #include 
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pmc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sam34/sam_aes.h b/arch/arm/src/sam34/sam_aes.h
index e0e6f114e23..428d7f7746f 100644
--- a/arch/arm/src/sam34/sam_aes.h
+++ b/arch/arm/src/sam34/sam_aes.h
@@ -47,7 +47,7 @@
 #include "chip.h"
 
 #ifdef CONFIG_ARCH_CHIP_SAM4CM
-#  include "chip/sam4cm_aes.h"
+#  include "hardware/sam4cm_aes.h"
 #else
 #  error "Unknown chip for AES"
 #endif
diff --git a/arch/arm/src/sam34/sam_clockconfig.c b/arch/arm/src/sam34/sam_clockconfig.c
index 3dce96b02e5..60889468f25 100644
--- a/arch/arm/src/sam34/sam_clockconfig.c
+++ b/arch/arm/src/sam34/sam_clockconfig.c
@@ -49,11 +49,11 @@
 #include "up_internal.h"
 
 #include "sam_clockconfig.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_eefc.h"
-#include "chip/sam_wdt.h"
-#include "chip/sam_supc.h"
-#include "chip/sam_matrix.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_eefc.h"
+#include "hardware/sam_wdt.h"
+#include "hardware/sam_supc.h"
+#include "hardware/sam_matrix.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sam34/sam_cmcc.c b/arch/arm/src/sam34/sam_cmcc.c
index 3ffee694749..676dda4bb0d 100644
--- a/arch/arm/src/sam34/sam_cmcc.c
+++ b/arch/arm/src/sam34/sam_cmcc.c
@@ -44,7 +44,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/sam_cmcc.h"
+#include "hardware/sam_cmcc.h"
 #include "sam_cmcc.h"
 
 #ifdef CONFIG_SAM34_CMCC
diff --git a/arch/arm/src/sam34/sam_dmac.c b/arch/arm/src/sam34/sam_dmac.c
index 75f0480839a..1e06148cfe1 100644
--- a/arch/arm/src/sam34/sam_dmac.c
+++ b/arch/arm/src/sam34/sam_dmac.c
@@ -57,8 +57,8 @@
 
 #include "sam_dmac.h"
 #include "sam_periphclks.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_dmac.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_dmac.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c
index bb7efc789b7..1d3f4f6f9c5 100644
--- a/arch/arm/src/sam34/sam_emac.c
+++ b/arch/arm/src/sam34/sam_emac.c
@@ -78,7 +78,7 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 #include "sam_gpio.h"
 #include "sam_periphclks.h"
 #include "sam_cmcc.h"
@@ -2504,7 +2504,7 @@ static int sam_phyintenable(struct sam_emac_s *priv)
       /* Enable link up/down interrupts */
 
       ret = sam_phywrite(priv, priv->phyaddr, MII_KSZ8081_INT,
-                        (MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN));
+                        (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN));
     }
 
   /* Disable management port (probably) */
diff --git a/arch/arm/src/sam34/sam_emac.h b/arch/arm/src/sam34/sam_emac.h
index 80c177bdcf0..a61dc539ecd 100644
--- a/arch/arm/src/sam34/sam_emac.h
+++ b/arch/arm/src/sam34/sam_emac.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_emac.h"
+#include "hardware/sam_emac.h"
 
 #ifdef CONFIG_SAM34_EMAC
 
diff --git a/arch/arm/src/sam34/sam_gpio.c b/arch/arm/src/sam34/sam_gpio.c
index d1dc1ef64bd..8c8250741d4 100644
--- a/arch/arm/src/sam34/sam_gpio.c
+++ b/arch/arm/src/sam34/sam_gpio.c
@@ -58,11 +58,11 @@
 
 #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
     defined(CONFIG_ARCH_CHIP_SAM3A)
-#  include "chip/sam3u_pio.h"
+#  include "hardware/sam3u_pio.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4E)
-#  include "chip/sam4e_pio.h"
+#  include "hardware/sam4e_pio.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S)
-#  include "chip/sam4s_pio.h"
+#  include "hardware/sam4s_pio.h"
 #else
 #  error Unrecognized SAM architecture
 #endif
diff --git a/arch/arm/src/sam34/sam_gpioirq.c b/arch/arm/src/sam34/sam_gpioirq.c
index e6091ee5110..f4936d8584f 100644
--- a/arch/arm/src/sam34/sam_gpioirq.c
+++ b/arch/arm/src/sam34/sam_gpioirq.c
@@ -55,15 +55,15 @@
 
 #include "sam_gpio.h"
 #include "sam_periphclks.h"
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pmc.h"
 
 #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
     defined(CONFIG_ARCH_CHIP_SAM3A)
-#  include "chip/sam3u_pio.h"
+#  include "hardware/sam3u_pio.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4E)
-#  include "chip/sam4e_pio.h"
+#  include "hardware/sam4e_pio.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S)
-#  include "chip/sam4s_pio.h"
+#  include "hardware/sam4s_pio.h"
 #else
 #  error Unrecognized SAM architecture
 #endif
diff --git a/arch/arm/src/sam34/sam_hsmci.c b/arch/arm/src/sam34/sam_hsmci.c
index 3e0a7276875..7127eaf41ea 100644
--- a/arch/arm/src/sam34/sam_hsmci.c
+++ b/arch/arm/src/sam34/sam_hsmci.c
@@ -70,15 +70,15 @@
 #  include "sam_dmac.h"
 #endif
 
-#include "chip/sam_pmc.h"
-#include "chip/sam_hsmci.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_hsmci.h"
+#include "hardware/sam_pinmap.h"
 
 #ifdef CONFIG_SAM34_DMAC
-#  include "chip/sam_dmac.h"
+#  include "hardware/sam_dmac.h"
 #endif
 #ifdef CONFIG_SAM34_PDCA
-#  include "chip/sam_pdc.h"
+#  include "hardware/sam_pdc.h"
 #endif
 
 #ifdef CONFIG_SAM34_HSMCI
diff --git a/arch/arm/src/sam34/sam_lowputc.c b/arch/arm/src/sam34/sam_lowputc.c
index 13d5046ef08..013901eb387 100644
--- a/arch/arm/src/sam34/sam_lowputc.c
+++ b/arch/arm/src/sam34/sam_lowputc.c
@@ -53,16 +53,16 @@
 #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
     defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4CM) || \
     defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
-#  include "chip/sam_uart.h"
+#  include "hardware/sam_uart.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4L)
-#  include "chip/sam4l_usart.h"
+#  include "hardware/sam4l_usart.h"
 #else
 #  error Unknown UART
 #endif
 
 /* The board.h file may redefine pin configurations defined in sam_pinmap.h */
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 #include 
 
 /****************************************************************************
diff --git a/arch/arm/src/sam34/sam_rtc.h b/arch/arm/src/sam34/sam_rtc.h
index 03ab3166935..93d6676decf 100644
--- a/arch/arm/src/sam34/sam_rtc.h
+++ b/arch/arm/src/sam34/sam_rtc.h
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_rtc.h"
+#include "hardware/sam_rtc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sam34/sam_rtt.h b/arch/arm/src/sam34/sam_rtt.h
index 3a00c17fbdd..325c25ce8c6 100644
--- a/arch/arm/src/sam34/sam_rtt.h
+++ b/arch/arm/src/sam34/sam_rtt.h
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_rtt.h"
+#include "hardware/sam_rtt.h"
 
 #ifdef CONFIG_TIMER
 
diff --git a/arch/arm/src/sam34/sam_serial.c b/arch/arm/src/sam34/sam_serial.c
index 866fd8cc1ea..0fae8f8f6e5 100644
--- a/arch/arm/src/sam34/sam_serial.c
+++ b/arch/arm/src/sam34/sam_serial.c
@@ -67,9 +67,9 @@
 #if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
     defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4CM) || \
     defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
-#  include "chip/sam_uart.h"
+#  include "hardware/sam_uart.h"
 #elif defined(CONFIG_ARCH_CHIP_SAM4L)
-#  include "chip/sam4l_usart.h"
+#  include "hardware/sam4l_usart.h"
 #else
 #  error Unknown UART
 #endif
diff --git a/arch/arm/src/sam34/sam_spi.c b/arch/arm/src/sam34/sam_spi.c
index df2be897165..76c7f589d38 100644
--- a/arch/arm/src/sam34/sam_spi.c
+++ b/arch/arm/src/sam34/sam_spi.c
@@ -69,10 +69,10 @@
 #include "sam_cmcc.h"
 #include "sam_periphclks.h"
 #include "sam_spi.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_dmac.h"
-#include "chip/sam_spi.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_dmac.h"
+#include "hardware/sam_spi.h"
+#include "hardware/sam_pinmap.h"
 
 #if defined(CONFIG_SAM34_SPI0) || defined(CONFIG_SAM34_SPI1)
 
diff --git a/arch/arm/src/sam34/sam_spi.h b/arch/arm/src/sam34/sam_spi.h
index b9cbcce76df..e31a2ad2b53 100644
--- a/arch/arm/src/sam34/sam_spi.h
+++ b/arch/arm/src/sam34/sam_spi.h
@@ -46,7 +46,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_spi.h"
+#include "hardware/sam_spi.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sam34/sam_start.c b/arch/arm/src/sam34/sam_start.c
index a711b4c9ffd..24232656c8b 100644
--- a/arch/arm/src/sam34/sam_start.c
+++ b/arch/arm/src/sam34/sam_start.c
@@ -48,16 +48,12 @@
 
 #include "up_arch.h"
 #include "up_internal.h"
+#include "nvic.h"
 
 #include "sam_clockconfig.h"
 #include "sam_lowputc.h"
 #include "sam_cmcc.h"
 #include "sam_userspace.h"
-
-#ifdef CONFIG_ARCH_FPU
-#  include "nvic.h"
-#endif
-
 #include "sam_start.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/sam34/sam_tc.h b/arch/arm/src/sam34/sam_tc.h
index 3667213d752..7ae228e882f 100644
--- a/arch/arm/src/sam34/sam_tc.h
+++ b/arch/arm/src/sam34/sam_tc.h
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_tc.h"
+#include "hardware/sam_tc.h"
 
 #ifdef CONFIG_TIMER
 
diff --git a/arch/arm/src/sam34/sam_twi.c b/arch/arm/src/sam34/sam_twi.c
index 7f733790f70..086bdd0d8a1 100644
--- a/arch/arm/src/sam34/sam_twi.c
+++ b/arch/arm/src/sam34/sam_twi.c
@@ -64,8 +64,8 @@
 
 #include "up_arch.h"
 
-#include "chip/sam_pmc.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_pinmap.h"
 
 #include "sam_periphclks.h"
 #include "sam_gpio.h"
diff --git a/arch/arm/src/sam34/sam_twi.h b/arch/arm/src/sam34/sam_twi.h
index 06868044b2a..3969982a0b9 100644
--- a/arch/arm/src/sam34/sam_twi.h
+++ b/arch/arm/src/sam34/sam_twi.h
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/sam_twi.h"
+#include "hardware/sam_twi.h"
 
 /****************************************************************************
  * Public Function Prototypes
diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c
index c2edada328c..1381f396289 100644
--- a/arch/arm/src/sam34/sam_udp.c
+++ b/arch/arm/src/sam34/sam_udp.c
@@ -72,7 +72,7 @@
 #include "up_internal.h"
 
 #include "sam_periphclks.h"
-#include "chip/sam_udp.h"
+#include "hardware/sam_udp.h"
 #include "sam_udp.h"
 
 #if defined(CONFIG_USBDEV) && defined(CONFIG_SAM34_UDP)
diff --git a/arch/arm/src/sam34/sam_udp.h b/arch/arm/src/sam34/sam_udp.h
index 38b665f865f..0284c844057 100644
--- a/arch/arm/src/sam34/sam_udp.h
+++ b/arch/arm/src/sam34/sam_udp.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_udp.h"
+#include "hardware/sam_udp.h"
 
 /************************************************************************************
  * Public Functions
diff --git a/arch/arm/src/sam34/sam_wdt.h b/arch/arm/src/sam34/sam_wdt.h
index 3330cc01e73..ab421e9fd6a 100644
--- a/arch/arm/src/sam34/sam_wdt.h
+++ b/arch/arm/src/sam34/sam_wdt.h
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_wdt.h"
+#include "hardware/sam_wdt.h"
 
 #ifdef CONFIG_WATCHDOG
 
diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig
index d6c158f57be..51a0a660337 100644
--- a/arch/arm/src/sama5/Kconfig
+++ b/arch/arm/src/sama5/Kconfig
@@ -3748,7 +3748,6 @@ config SAMA_TSD_RXP
 config SAMA5_TSD_NPOLLWAITERS
 	int "Number poll waiters"
 	default 4
-	depends on !DISABLE_POLL
 	---help---
 		Maximum number of threads that can be waiting on poll()
 
diff --git a/arch/arm/src/sama5/chip.h b/arch/arm/src/sama5/chip.h
index ab2bd4d681f..259c8b2e04f 100644
--- a/arch/arm/src/sama5/chip.h
+++ b/arch/arm/src/sama5/chip.h
@@ -46,7 +46,7 @@
 #  include 
 #endif
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/chip/_sama5d2x_memorymap.h b/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h
similarity index 99%
rename from arch/arm/src/sama5/chip/_sama5d2x_memorymap.h
rename to arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h
index 03a6ecfee68..ce9bd2263c6 100644
--- a/arch/arm/src/sama5/chip/_sama5d2x_memorymap.h
+++ b/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/_sama5d2x_memorymap.h
+ * arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D2X_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D2X_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -884,4 +884,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D2X_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_MEMORYMAP_H */
diff --git a/arch/arm/src/sama5/chip/_sama5d2x_pinmap.h b/arch/arm/src/sama5/hardware/_sama5d2x_pinmap.h
similarity index 99%
rename from arch/arm/src/sama5/chip/_sama5d2x_pinmap.h
rename to arch/arm/src/sama5/hardware/_sama5d2x_pinmap.h
index 1b4553cdc02..1c9d4d59928 100644
--- a/arch/arm/src/sama5/chip/_sama5d2x_pinmap.h
+++ b/arch/arm/src/sama5/hardware/_sama5d2x_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************************************
- * arch/arm/src/sama5/chip/_sama5d2x_pinmap.h
+ * arch/arm/src/sama5/hardware/_sama5d2x_pinmap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D2X_PINMAP_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D2X_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_PINMAP_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_PINMAP_H
 
 /************************************************************************************************************
  * Included Files
@@ -801,4 +801,4 @@
 #define PIO_UTMI_RXERR       (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOD | PIO_PIN8)
 #define PIO_UTMI_RXVAL       (PIO_PERIPHC | PIO_CFG_DEFAULT | PIO_PORT_PIOD | PIO_PIN7)
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D2X_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_PINMAP_H */
diff --git a/arch/arm/src/sama5/chip/_sama5d2x_pio.h b/arch/arm/src/sama5/hardware/_sama5d2x_pio.h
similarity index 99%
rename from arch/arm/src/sama5/chip/_sama5d2x_pio.h
rename to arch/arm/src/sama5/hardware/_sama5d2x_pio.h
index a821e56d84b..48273c0773d 100644
--- a/arch/arm/src/sama5/chip/_sama5d2x_pio.h
+++ b/arch/arm/src/sama5/hardware/_sama5d2x_pio.h
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D2X_PIO_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D2X_PIO_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_PIO_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_PIO_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -334,4 +334,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D2X_PIO_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D2X_PIO_H */
diff --git a/arch/arm/src/sama5/chip/_sama5d3x4x_pio.h b/arch/arm/src/sama5/hardware/_sama5d3x4x_pio.h
similarity index 99%
rename from arch/arm/src/sama5/chip/_sama5d3x4x_pio.h
rename to arch/arm/src/sama5/hardware/_sama5d3x4x_pio.h
index 0516d6981ed..75668484fb3 100644
--- a/arch/arm/src/sama5/chip/_sama5d3x4x_pio.h
+++ b/arch/arm/src/sama5/hardware/_sama5d3x4x_pio.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sama5/chip/_sama5d3x4x_pio.h
+ * arch/arm/src/sama5/hardware/_sama5d3x4x_pio.h
  * Parallel Input/Output (PIO) Controller definitions for the SAMA5D3x and SAMA5D4x
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D3DX4X_PIO_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D3DX4X_PIO_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3DX4X_PIO_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3DX4X_PIO_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -645,4 +645,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D3DX4X_PIO_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3DX4X_PIO_H */
diff --git a/arch/arm/src/sama5/chip/_sama5d3x_memorymap.h b/arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h
similarity index 99%
rename from arch/arm/src/sama5/chip/_sama5d3x_memorymap.h
rename to arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h
index ecac5f2056f..a0626540fb2 100644
--- a/arch/arm/src/sama5/chip/_sama5d3x_memorymap.h
+++ b/arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/_sama5d3x_memorymap.h
+ * arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D3X_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D3X_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3X_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -808,4 +808,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D3X_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3X_MEMORYMAP_H */
diff --git a/arch/arm/src/sama5/chip/_sama5d3x_mpddrc.h b/arch/arm/src/sama5/hardware/_sama5d3x_mpddrc.h
similarity index 99%
rename from arch/arm/src/sama5/chip/_sama5d3x_mpddrc.h
rename to arch/arm/src/sama5/hardware/_sama5d3x_mpddrc.h
index bbf21ce4642..85a481fa40d 100644
--- a/arch/arm/src/sama5/chip/_sama5d3x_mpddrc.h
+++ b/arch/arm/src/sama5/hardware/_sama5d3x_mpddrc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/_sama5d3x_mpddrc.h
+ * arch/arm/src/sama5/hardware/_sama5d3x_mpddrc.h
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D3X_MPDDRC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D3X_MPDDRC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3X_MPDDRC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3X_MPDDRC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -402,4 +402,4 @@
 #define MPDDRC_WPSR_WPVSRC_SHIFT        (8)       /* Bits 8-23: Write Protection Violation Source */
 #define MPDDRC_WPSR_WPVSRC_MASK         (0xffff << MPDDRC_WPSR_WPVSRC_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D3X_MPDDRC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3X_MPDDRC_H */
diff --git a/arch/arm/src/sama5/chip/_sama5d3x_pinmap.h b/arch/arm/src/sama5/hardware/_sama5d3x_pinmap.h
similarity index 99%
rename from arch/arm/src/sama5/chip/_sama5d3x_pinmap.h
rename to arch/arm/src/sama5/hardware/_sama5d3x_pinmap.h
index a18e7272aa5..8c7c581ff1e 100644
--- a/arch/arm/src/sama5/chip/_sama5d3x_pinmap.h
+++ b/arch/arm/src/sama5/hardware/_sama5d3x_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************************************
- * arch/arm/src/sama5/chip/_sama5d3x_pinmap.h
+ * arch/arm/src/sama5/hardware/_sama5d3x_pinmap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D3X_PINMAP_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D3X_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3X_PINMAP_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3X_PINMAP_H
 
 /************************************************************************************************************
  * Included Files
@@ -59,7 +59,7 @@
  *
  *   #define PIO_LCD_DAT16 PIO_LCD_DAT16_1
  *
- * The LCD driver will then automatically configre PA16 as the DAT16 pin.
+ * The LCD driver will then automatically configure PA16 as the DAT16 pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -410,4 +410,4 @@
 #define PIO_USART3_SCK    (PIO_PERIPHB | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN15) /* Type: EBI */
 #define PIO_USART3_TXD    (PIO_PERIPHB | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN19) /* Type: EBI */
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D3X_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D3X_PINMAP_H */
diff --git a/arch/arm/src/sama5/chip/_sama5d4x_memorymap.h b/arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h
similarity index 99%
rename from arch/arm/src/sama5/chip/_sama5d4x_memorymap.h
rename to arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h
index 46c203a2936..ceed872f787 100644
--- a/arch/arm/src/sama5/chip/_sama5d4x_memorymap.h
+++ b/arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/_sama5d4x_memorymap.h
+ * arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D4X_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D4X_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -802,4 +802,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D4X_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_MEMORYMAP_H */
diff --git a/arch/arm/src/sama5/chip/_sama5d4x_mpddrc.h b/arch/arm/src/sama5/hardware/_sama5d4x_mpddrc.h
similarity index 99%
rename from arch/arm/src/sama5/chip/_sama5d4x_mpddrc.h
rename to arch/arm/src/sama5/hardware/_sama5d4x_mpddrc.h
index 24880165bf7..8465ed9fd5b 100644
--- a/arch/arm/src/sama5/chip/_sama5d4x_mpddrc.h
+++ b/arch/arm/src/sama5/hardware/_sama5d4x_mpddrc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/sama5/chip/_sama5d4x_mpddrc.h
+ * arch/arm/src/sama5/hardware/_sama5d4x_mpddrc.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D4X_MPDDRC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D4X_MPDDRC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_MPDDRC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_MPDDRC_H
 
 /********************************************************************************************
  * Included Files
  ********************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -687,4 +687,4 @@
 #define MPDDRC_DLL_SAD_ADDCNT_MASK           (0xff < MPDDRC_DLL_SAD_ADDCNT_SHIFT)
 #  define MPDDRC_DLL_SAD_ADDCNT(n)           ((uint32_t)(n) < MPDDRC_DLL_SAD_ADDCNT_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D4X_MPDDRC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_MPDDRC_H */
diff --git a/arch/arm/src/sama5/chip/_sama5d4x_pinmap.h b/arch/arm/src/sama5/hardware/_sama5d4x_pinmap.h
similarity index 99%
rename from arch/arm/src/sama5/chip/_sama5d4x_pinmap.h
rename to arch/arm/src/sama5/hardware/_sama5d4x_pinmap.h
index 1262fa9c15e..75828935615 100644
--- a/arch/arm/src/sama5/chip/_sama5d4x_pinmap.h
+++ b/arch/arm/src/sama5/hardware/_sama5d4x_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************************************
- * arch/arm/src/sama5/chip/_sama5d4x_pinmap.h
+ * arch/arm/src/sama5/hardware/_sama5d4x_pinmap.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D4X_PINMAP_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D4X_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_PINMAP_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_PINMAP_H
 
 /************************************************************************************************************
  * Included Files
@@ -473,4 +473,4 @@
 #define PIO_USART4_SCK    (PIO_PERIPHB | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN25)
 #define PIO_USART4_TXD    (PIO_PERIPHB | PIO_CFG_DEFAULT | PIO_PORT_PIOE | PIO_PIN27)
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP__SAMA5D4X_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE__SAMA5D4X_PINMAP_H */
diff --git a/arch/arm/src/sama5/chip/sam_adc.h b/arch/arm/src/sama5/hardware/sam_adc.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_adc.h
rename to arch/arm/src/sama5/hardware/sam_adc.h
index 3d65aa214e8..208d529b720 100644
--- a/arch/arm/src/sama5/chip/sam_adc.h
+++ b/arch/arm/src/sama5/hardware/sam_adc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sama5/chip/sam_adc.h
+ * arch/arm/src/sama5/hardware/sam_adc.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_ADC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_ADC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_ADC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_ADC_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -603,4 +603,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_ADC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_ADC_H */
diff --git a/arch/arm/src/sama5/chip/sam_aic.h b/arch/arm/src/sama5/hardware/sam_aic.h
similarity index 97%
rename from arch/arm/src/sama5/chip/sam_aic.h
rename to arch/arm/src/sama5/hardware/sam_aic.h
index 776b74f6c3a..372c8de5333 100644
--- a/arch/arm/src/sama5/chip/sam_aic.h
+++ b/arch/arm/src/sama5/hardware/sam_aic.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_aic.h
+ * arch/arm/src/sama5/hardware/sam_aic.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_AIC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_AIC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_AIC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_AIC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -231,4 +231,4 @@
 #define AIC_WPSR_WPVSRC_SHIFT  (8)       /* Bits 8-23: Write Protect Violation Source */
 #define AIC_WPSR_WPVSRC_MASK   (0x0000ffff << AIC_WPSR_WPVSRC_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_AIC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_AIC_H */
diff --git a/arch/arm/src/sama5/chip/sam_aximx.h b/arch/arm/src/sama5/hardware/sam_aximx.h
similarity index 93%
rename from arch/arm/src/sama5/chip/sam_aximx.h
rename to arch/arm/src/sama5/hardware/sam_aximx.h
index 7f86cc15e90..130dbbec5fd 100644
--- a/arch/arm/src/sama5/chip/sam_aximx.h
+++ b/arch/arm/src/sama5/hardware/sam_aximx.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_aximx.h
+ * arch/arm/src/sama5/hardware/sam_aximx.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_AXIMX_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_AXIMX_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_AXIMX_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_AXIMX_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -73,4 +73,4 @@
 #  define AXIMX_REMAP_REMAP1   (1 << 1) /* Remap State 1 */
 #endif
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_AXIMX_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_AXIMX_H */
diff --git a/arch/arm/src/sama5/chip/sam_bsc.h b/arch/arm/src/sama5/hardware/sam_bsc.h
similarity index 92%
rename from arch/arm/src/sama5/chip/sam_bsc.h
rename to arch/arm/src/sama5/hardware/sam_bsc.h
index c51710feda9..9a464047f7d 100644
--- a/arch/arm/src/sama5/chip/sam_bsc.h
+++ b/arch/arm/src/sama5/hardware/sam_bsc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_bsc.h
+ * arch/arm/src/sama5/hardware/sam_bsc.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_BSC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_BSC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_BSC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_BSC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -64,4 +64,4 @@
 #define BSC_CR_BOOTKEY_MASK  (0xffff << BSC_CR_BOOTKEY_SHIFT)
 #  define BSC_CR_BOOTKEY     (0x6683 << BSC_CR_BOOTKEY_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_BSC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_BSC_H */
diff --git a/arch/arm/src/sama5/chip/sam_can.h b/arch/arm/src/sama5/hardware/sam_can.h
similarity index 98%
rename from arch/arm/src/sama5/chip/sam_can.h
rename to arch/arm/src/sama5/hardware/sam_can.h
index 8efbbd51c63..05313d9afa2 100644
--- a/arch/arm/src/sama5/chip/sam_can.h
+++ b/arch/arm/src/sama5/hardware/sam_can.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_can.h
+ * arch/arm/src/sama5/hardware/sam_can.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_CAN_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_CAN_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_CAN_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_CAN_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -374,4 +374,4 @@
 #define CAN_MCR_MACR             (1 << 22) /* Bit 22: Abort Request for Mailbox n */
 #define CAN_MCR_MTCR             (1 << 23) /* Bit 23: Mailbox Transfer Command */
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_CAN_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_CAN_H */
diff --git a/arch/arm/src/sama5/chip/sam_dbgu.h b/arch/arm/src/sama5/hardware/sam_dbgu.h
similarity index 98%
rename from arch/arm/src/sama5/chip/sam_dbgu.h
rename to arch/arm/src/sama5/hardware/sam_dbgu.h
index a2a11d18c41..1d7b041175b 100644
--- a/arch/arm/src/sama5/chip/sam_dbgu.h
+++ b/arch/arm/src/sama5/hardware/sam_dbgu.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/sama5/chip/sam3u_uart.h
+ * arch/arm/src/sama5/hardware/sam3u_uart.h
  * Debug Unit (DBGU) definitions for the SAMA5D3
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_DBGU_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_DBGU_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_DBGU_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_DBGU_H
 
 /************************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************************
  * Pre-processor Definitions
@@ -264,4 +264,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_DBGU_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_DBGU_H */
diff --git a/arch/arm/src/sama5/chip/sam_dmac.h b/arch/arm/src/sama5/hardware/sam_dmac.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_dmac.h
rename to arch/arm/src/sama5/hardware/sam_dmac.h
index 3dc39d3d4dd..f037819689e 100644
--- a/arch/arm/src/sama5/chip/sam_dmac.h
+++ b/arch/arm/src/sama5/hardware/sam_dmac.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sama5/chip/sam_dmac.h
+ * arch/arm/src/sama5/hardware/sam_dmac.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_DMAC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_DMAC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_DMAC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_DMAC_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -839,4 +839,4 @@ struct dma_crc16_linklist_s
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_DMAC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_DMAC_H */
diff --git a/arch/arm/src/sama5/chip/sam_ehci.h b/arch/arm/src/sama5/hardware/sam_ehci.h
similarity index 94%
rename from arch/arm/src/sama5/chip/sam_ehci.h
rename to arch/arm/src/sama5/hardware/sam_ehci.h
index e564b1ecc35..b06511dbaca 100644
--- a/arch/arm/src/sama5/chip/sam_ehci.h
+++ b/arch/arm/src/sama5/hardware/sam_ehci.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/sama5/chip/sam_ehci.h
+ * arch/arm/src/sama5/hardware/sam_ehci.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EHCI_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EHCI_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EHCI_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EHCI_H
 
 /****************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -93,4 +93,4 @@
  * Public Functions
  ****************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EHCI_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EHCI_H */
diff --git a/arch/arm/src/sama5/chip/sam_emac.h b/arch/arm/src/sama5/hardware/sam_emac.h
similarity index 90%
rename from arch/arm/src/sama5/chip/sam_emac.h
rename to arch/arm/src/sama5/hardware/sam_emac.h
index d131e51dc75..9174dac52d0 100644
--- a/arch/arm/src/sama5/chip/sam_emac.h
+++ b/arch/arm/src/sama5/hardware/sam_emac.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_emac.h
+ * arch/arm/src/sama5/hardware/sam_emac.h
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMAC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMAC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EMAC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EMAC_H
 
 /************************************************************************************
  * Included Files
@@ -50,9 +50,9 @@
  */
 
 #if defined(CONFIG_SAMA5_EMACA)
-#  include "chip/sam_emaca.h"
+#  include "hardware/sam_emaca.h"
 #elif defined(CONFIG_SAMA5_EMACB)
-#  include "chip/sam_emacb.h"
+#  include "hardware/sam_emacb.h"
 #endif
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMAC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EMAC_H */
diff --git a/arch/arm/src/sama5/chip/sam_emaca.h b/arch/arm/src/sama5/hardware/sam_emaca.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_emaca.h
rename to arch/arm/src/sama5/hardware/sam_emaca.h
index 3e4bb7409cb..aea425c7005 100644
--- a/arch/arm/src/sama5/chip/sam_emaca.h
+++ b/arch/arm/src/sama5/hardware/sam_emaca.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_emaca.h
+ * arch/arm/src/sama5/hardware/sam_emaca.h
  * This is the form of the EMAC interface used the SAMA5D3
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
@@ -34,15 +34,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMACA_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMACA_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EMACA_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EMACA_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -454,4 +454,4 @@ struct emac_txdesc_s
   uint32_t status;   /* TX status and controls */
 };
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMACA_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EMACA_H */
diff --git a/arch/arm/src/sama5/chip/sam_emacb.h b/arch/arm/src/sama5/hardware/sam_emacb.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_emacb.h
rename to arch/arm/src/sama5/hardware/sam_emacb.h
index 7cbc75d6af8..d8779e06e9a 100644
--- a/arch/arm/src/sama5/chip/sam_emacb.h
+++ b/arch/arm/src/sama5/hardware/sam_emacb.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_emacb.h
+ * arch/arm/src/sama5/hardware/sam_emacb.h
  * This is the form of the EMAC interface used the SAMA5D4 (and also the SAM43).
  * This is referred as GMAC in the documentation even though it does not support
  * Gibabit Ethernet.
@@ -36,15 +36,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMACB_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMACB_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EMACB_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EMACB_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -789,4 +789,4 @@ struct emac_txdesc_s
   uint32_t status;   /* TX status and controls */
 };
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EMACB_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_EMACB_H */
diff --git a/arch/arm/src/sama5/chip/sam_flexcom.h b/arch/arm/src/sama5/hardware/sam_flexcom.h
similarity index 93%
rename from arch/arm/src/sama5/chip/sam_flexcom.h
rename to arch/arm/src/sama5/hardware/sam_flexcom.h
index 990a73b1c7d..c18bc6df324 100644
--- a/arch/arm/src/sama5/chip/sam_flexcom.h
+++ b/arch/arm/src/sama5/hardware/sam_flexcom.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_flexcom.h
+ * arch/arm/src/sama5/hardware/sam_flexcom.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_FLEXCOM_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_FLEXCOM_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -114,14 +114,14 @@
 
 /* Flexcom USART Register Definitions ***********************************************/
 
-#include "chip/sam_flexcom_usart.h"
+#include "hardware/sam_flexcom_usart.h"
 
 /* Flexcom SPI Register Definitions *************************************************/
 
-#include "chip/sam_flexcom_spi.h"
+#include "hardware/sam_flexcom_spi.h"
 
 /* Flexcom TWI Register Definitions *************************************************/
 
-#include "chip/sam_flexcom_twi.h"
+#include "hardware/sam_flexcom_twi.h"
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_FLEXCOM_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_H */
diff --git a/arch/arm/src/sama5/chip/sam_flexcom_spi.h b/arch/arm/src/sama5/hardware/sam_flexcom_spi.h
similarity index 90%
rename from arch/arm/src/sama5/chip/sam_flexcom_spi.h
rename to arch/arm/src/sama5/hardware/sam_flexcom_spi.h
index 4dc4ccc8735..13c5ac1fe86 100644
--- a/arch/arm/src/sama5/chip/sam_flexcom_spi.h
+++ b/arch/arm/src/sama5/hardware/sam_flexcom_spi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_flexcom_spi.h
+ * arch/arm/src/sama5/hardware/sam_flexcom_spi.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_FLEXCOM_SPI_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_FLEXCOM_SPI_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_SPI_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_SPI_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -55,4 +55,4 @@
 
 /* Flexcom SPI Register Bit Field Definitions ***************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_FLEXCOM_SPI_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_SPI_H */
diff --git a/arch/arm/src/sama5/chip/sam_flexcom_twi.h b/arch/arm/src/sama5/hardware/sam_flexcom_twi.h
similarity index 90%
rename from arch/arm/src/sama5/chip/sam_flexcom_twi.h
rename to arch/arm/src/sama5/hardware/sam_flexcom_twi.h
index 69345a6decf..8cfd5bcb465 100644
--- a/arch/arm/src/sama5/chip/sam_flexcom_twi.h
+++ b/arch/arm/src/sama5/hardware/sam_flexcom_twi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_flexcom_twi.h
+ * arch/arm/src/sama5/hardware/sam_flexcom_twi.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_FLEXCOM_TWI_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_FLEXCOM_TWI_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_TWI_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_TWI_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -55,4 +55,4 @@
 
 /* Flexcom TWI Register Bit Field Definitions ***************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_FLEXCOM_TWI_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_TWI_H */
diff --git a/arch/arm/src/sama5/chip/sam_flexcom_usart.h b/arch/arm/src/sama5/hardware/sam_flexcom_usart.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_flexcom_usart.h
rename to arch/arm/src/sama5/hardware/sam_flexcom_usart.h
index 6331e06fb66..302eada4cd3 100644
--- a/arch/arm/src/sama5/chip/sam_flexcom_usart.h
+++ b/arch/arm/src/sama5/hardware/sam_flexcom_usart.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/sama5/chip/sam3u_uart.h
+ * arch/arm/src/sama5/hardware/sam3u_uart.h
  * Universal Synchronous Asynchronous Receiver Transmitter (FLEXUS) definitions for the SAMA5D2
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_FLEXCOM_FLEXUS_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_FLEXCOM_FLEXUS_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_FLEXUS_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_FLEXUS_H
 
 /************************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************************
  * Pre-processor Definitions
@@ -577,4 +577,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_FLEXCOM_FLEXUS_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_FLEXCOM_FLEXUS_H */
diff --git a/arch/arm/src/sama5/chip/sam_gmac.h b/arch/arm/src/sama5/hardware/sam_gmac.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_gmac.h
rename to arch/arm/src/sama5/hardware/sam_gmac.h
index 27496fec2ad..64ed40af5d5 100644
--- a/arch/arm/src/sama5/chip/sam_gmac.h
+++ b/arch/arm/src/sama5/hardware/sam_gmac.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_gmac.h
+ * arch/arm/src/sama5/hardware/sam_gmac.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_GMAC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_GMAC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_GMAC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_GMAC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -1011,4 +1011,4 @@ struct gmac_txdesc_s
   uint32_t status;   /* TX status and controls */
 };
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_GMAC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_GMAC_H */
diff --git a/arch/arm/src/sama5/chip/sam_gpbr.h b/arch/arm/src/sama5/hardware/sam_gpbr.h
similarity index 93%
rename from arch/arm/src/sama5/chip/sam_gpbr.h
rename to arch/arm/src/sama5/hardware/sam_gpbr.h
index e9e65880f3a..697b828d7eb 100644
--- a/arch/arm/src/sama5/chip/sam_gpbr.h
+++ b/arch/arm/src/sama5/hardware/sam_gpbr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_gpbr.h
+ * arch/arm/src/sama5/hardware/sam_gpbr.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_GPBR_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_GPBR_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_GPBR_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_GPBR_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -65,4 +65,4 @@
 /* GPBR Register Bit Definitions ****************************************************/
 /* All GPBR registers hold user-defined, 32-bit values */
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_GPBR_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_GPBR_H */
diff --git a/arch/arm/src/sama5/chip/sam_hsmc.h b/arch/arm/src/sama5/hardware/sam_hsmc.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_hsmc.h
rename to arch/arm/src/sama5/hardware/sam_hsmc.h
index 20b06294cae..cee2a3e437d 100644
--- a/arch/arm/src/sama5/chip/sam_hsmc.h
+++ b/arch/arm/src/sama5/hardware/sam_hsmc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_hsmc.h
+ * arch/arm/src/sama5/hardware/sam_hsmc.h
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_HSMC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_HSMC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_HSMC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_HSMC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -637,4 +637,4 @@
 #define NFCDATA_ADDT_CYCLE4_MASK      (0xff << NFCDATA_ADDT_CYCLE4_SHIFT)
 #  define NFCDATA_ADDT_CYCLE4(n)      ((uint32_t)(n) << NFCDATA_ADDT_CYCLE4_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_HSMC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_HSMC_H */
diff --git a/arch/arm/src/sama5/chip/sam_hsmci.h b/arch/arm/src/sama5/hardware/sam_hsmci.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_hsmci.h
rename to arch/arm/src/sama5/hardware/sam_hsmci.h
index 66173436847..3dfc888b63f 100644
--- a/arch/arm/src/sama5/chip/sam_hsmci.h
+++ b/arch/arm/src/sama5/hardware/sam_hsmci.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sama5/chip/sam_hsmci.h
+ * arch/arm/src/sama5/hardware/sam_hsmci.h
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_HSMCI_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_HSMCI_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_HSMCI_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_HSMCI_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -373,4 +373,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_HSMCI_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_HSMCI_H */
diff --git a/arch/arm/src/sama5/chip/sam_isi.h b/arch/arm/src/sama5/hardware/sam_isi.h
similarity index 98%
rename from arch/arm/src/sama5/chip/sam_isi.h
rename to arch/arm/src/sama5/hardware/sam_isi.h
index 5c7605a2add..40ef6d90c15 100644
--- a/arch/arm/src/sama5/chip/sam_isi.h
+++ b/arch/arm/src/sama5/hardware/sam_isi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_isi.h
+ * arch/arm/src/sama5/hardware/sam_isi.h
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_ISI_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_ISI_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_ISI_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_ISI_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -341,4 +341,4 @@ struct isi_dscr_s
   uint32_t dscr;  /* Next descriptor address */
 };
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_ISI_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_ISI_H */
diff --git a/arch/arm/src/sama5/chip/sam_lcdc.h b/arch/arm/src/sama5/hardware/sam_lcdc.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_lcdc.h
rename to arch/arm/src/sama5/hardware/sam_lcdc.h
index 8d311e06f93..2115599761b 100644
--- a/arch/arm/src/sama5/chip/sam_lcdc.h
+++ b/arch/arm/src/sama5/hardware/sam_lcdc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_lcdc.h
+ * arch/arm/src/sama5/hardware/sam_lcdc.h
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_LCDC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_LCDC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_LCDC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_LCDC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -1993,4 +1993,4 @@ struct sam_dscr_s
 };
 #define SIZEOF_SAM_DSCR_S 16
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_LCDC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_LCDC_H */
diff --git a/arch/arm/src/sama5/chip/sam_matrix.h b/arch/arm/src/sama5/hardware/sam_matrix.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_matrix.h
rename to arch/arm/src/sama5/hardware/sam_matrix.h
index f1da2826851..94bbac1aaa5 100644
--- a/arch/arm/src/sama5/chip/sam_matrix.h
+++ b/arch/arm/src/sama5/hardware/sam_matrix.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sama5/chip/sam_matrix.h
+ * arch/arm/src/sama5/hardware/sam_matrix.h
  * Bux matrix definitions for the SAMA5
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_MATRIX_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_MATRIX_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MATRIX_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MATRIX_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -1006,4 +1006,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_MATRIX_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MATRIX_H */
diff --git a/arch/arm/src/sama5/chip/sam_memorymap.h b/arch/arm/src/sama5/hardware/sam_memorymap.h
similarity index 86%
rename from arch/arm/src/sama5/chip/sam_memorymap.h
rename to arch/arm/src/sama5/hardware/sam_memorymap.h
index 73ecf13aecd..ed912692998 100644
--- a/arch/arm/src/sama5/chip/sam_memorymap.h
+++ b/arch/arm/src/sama5/hardware/sam_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_memorymap.h
+ * arch/arm/src/sama5/hardware/sam_memorymap.h
  *
  *   Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -44,13 +44,13 @@
 #include 
 
 #if defined(ATSAMA5D2)
-#  include "chip/_sama5d2x_memorymap.h"
+#  include "hardware/_sama5d2x_memorymap.h"
 #elif defined(ATSAMA5D3)
-#  include "chip/_sama5d3x_memorymap.h"
+#  include "hardware/_sama5d3x_memorymap.h"
 #elif defined(ATSAMA5D4)
-#  include "chip/_sama5d4x_memorymap.h"
+#  include "hardware/_sama5d4x_memorymap.h"
 #else
 #  error Unrecognized SAMA5 architecture
 #endif
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MEMORYMAP_H */
diff --git a/arch/arm/src/sama5/chip/sam_mpddrc.h b/arch/arm/src/sama5/hardware/sam_mpddrc.h
similarity index 88%
rename from arch/arm/src/sama5/chip/sam_mpddrc.h
rename to arch/arm/src/sama5/hardware/sam_mpddrc.h
index 06b217d8aaa..e8ba3515b70 100644
--- a/arch/arm/src/sama5/chip/sam_mpddrc.h
+++ b/arch/arm/src/sama5/hardware/sam_mpddrc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_mpddrc.h
+ * arch/arm/src/sama5/hardware/sam_mpddrc.h
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_MPDDRC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_MPDDRC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MPDDRC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MPDDRC_H
 
 /************************************************************************************
  * Included Files
@@ -44,11 +44,11 @@
 #include 
 
 #if defined(ATSAMA5D3)
-#  include "chip/_sama5d3x_mpddrc.h"
+#  include "hardware/_sama5d3x_mpddrc.h"
 #elif defined(ATSAMA5D4)
-#  include "chip/_sama5d4x_mpddrc.h"
+#  include "hardware/_sama5d4x_mpddrc.h"
 #else
 #  error Unrecognized SAMA5 architecture
 #endif
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_MPDDRC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_MPDDRC_H */
diff --git a/arch/arm/src/sama5/chip/sam_ohci.h b/arch/arm/src/sama5/hardware/sam_ohci.h
similarity index 95%
rename from arch/arm/src/sama5/chip/sam_ohci.h
rename to arch/arm/src/sama5/hardware/sam_ohci.h
index 4d3681de39e..b5aaa9d27ff 100644
--- a/arch/arm/src/sama5/chip/sam_ohci.h
+++ b/arch/arm/src/sama5/hardware/sam_ohci.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/sama5/chip/sam_ohci.h
+ * arch/arm/src/sama5/hardware/sam_ohci.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_OHCI_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_OHCI_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_OHCI_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_OHCI_H
 
 /****************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -109,4 +109,4 @@
  * Public Functions
  ****************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_OHCI_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_OHCI_H */
diff --git a/arch/arm/src/sama5/chip/sam_pinmap.h b/arch/arm/src/sama5/hardware/sam_pinmap.h
similarity index 86%
rename from arch/arm/src/sama5/chip/sam_pinmap.h
rename to arch/arm/src/sama5/hardware/sam_pinmap.h
index 461fb1f545b..52dd4945452 100644
--- a/arch/arm/src/sama5/chip/sam_pinmap.h
+++ b/arch/arm/src/sama5/hardware/sam_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_pinmap.h
+ * arch/arm/src/sama5/hardware/sam_pinmap.h
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PINMAP_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PINMAP_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -44,13 +44,13 @@
 #include 
 
 #if defined(ATSAMA5D2)
-#  include "chip/_sama5d2x_pinmap.h"
+#  include "hardware/_sama5d2x_pinmap.h"
 #elif defined(ATSAMA5D3)
-#  include "chip/_sama5d3x_pinmap.h"
+#  include "hardware/_sama5d3x_pinmap.h"
 #elif defined(ATSAMA5D4)
-#  include "chip/_sama5d4x_pinmap.h"
+#  include "hardware/_sama5d4x_pinmap.h"
 #else
 #  error Unrecognized SAMA5 architecture
 #endif
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PINMAP_H */
diff --git a/arch/arm/src/sama5/chip/sam_pio.h b/arch/arm/src/sama5/hardware/sam_pio.h
similarity index 88%
rename from arch/arm/src/sama5/chip/sam_pio.h
rename to arch/arm/src/sama5/hardware/sam_pio.h
index 7a37fe6cfa0..5fa606597b2 100644
--- a/arch/arm/src/sama5/chip/sam_pio.h
+++ b/arch/arm/src/sama5/hardware/sam_pio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_pio.h
+ * arch/arm/src/sama5/hardware/sam_pio.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PIO_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PIO_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PIO_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PIO_H
 
 /************************************************************************************
  * Included Files
@@ -44,11 +44,11 @@
 #include 
 
 #if defined(ATSAMA5D2)
-#  include "chip/_sama5d2x_pio.h"
+#  include "hardware/_sama5d2x_pio.h"
 #elif defined(ATSAMA5D3) || defined(ATSAMA5D4)
-#  include "chip/_sama5d3x4x_pio.h"
+#  include "hardware/_sama5d3x4x_pio.h"
 #else
 #  error Unrecognized SAMA5 architecture
 #endif
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PIO_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PIO_H */
diff --git a/arch/arm/src/sama5/chip/sam_pit.h b/arch/arm/src/sama5/hardware/sam_pit.h
similarity index 94%
rename from arch/arm/src/sama5/chip/sam_pit.h
rename to arch/arm/src/sama5/hardware/sam_pit.h
index 1f93f4b75cc..be1adfb9b0a 100644
--- a/arch/arm/src/sama5/chip/sam_pit.h
+++ b/arch/arm/src/sama5/hardware/sam_pit.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_pit.h
+ * arch/arm/src/sama5/hardware/sam_pit.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PIT_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PIT_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PIT_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PIT_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -82,4 +82,4 @@
 #define PIT_PICNT_SHIFT     (20) /* Bits 20-31: Periodic Interval Counter */
 #define PIT_PICNT_MASK      (0xfff << PIT_PIVR_PICNT_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PIT_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PIT_H */
diff --git a/arch/arm/src/sama5/chip/sam_pmc.h b/arch/arm/src/sama5/hardware/sam_pmc.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_pmc.h
rename to arch/arm/src/sama5/hardware/sam_pmc.h
index abe06ed86b1..aa5e9ee56ac 100644
--- a/arch/arm/src/sama5/chip/sam_pmc.h
+++ b/arch/arm/src/sama5/hardware/sam_pmc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/sama5/chip/sam_pmc.h
+ * arch/arm/src/sama5/hardware/sam_pmc.h
  * Power Management Controller (PMC) for the SAMA5
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PMC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PMC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PMC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PMC_H
 
 /********************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -680,4 +680,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PMC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PMC_H */
diff --git a/arch/arm/src/sama5/chip/sam_pwm.h b/arch/arm/src/sama5/hardware/sam_pwm.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_pwm.h
rename to arch/arm/src/sama5/hardware/sam_pwm.h
index 8aef808f293..307dc74117c 100644
--- a/arch/arm/src/sama5/chip/sam_pwm.h
+++ b/arch/arm/src/sama5/hardware/sam_pwm.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_pwm.h
+ * arch/arm/src/sama5/hardware/sam_pwm.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PWM_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PWM_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PWM_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PWM_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -750,4 +750,4 @@
 #  define PWM_CMUPD_CPOLINVUP      (1 << 13) /* Bit 13: Channel Polarity Inversion Update */
 #endif
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_PWM_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_PWM_H */
diff --git a/arch/arm/src/sama5/chip/sam_rtc.h b/arch/arm/src/sama5/hardware/sam_rtc.h
similarity index 98%
rename from arch/arm/src/sama5/chip/sam_rtc.h
rename to arch/arm/src/sama5/hardware/sam_rtc.h
index c6d81a8c309..0affabba932 100644
--- a/arch/arm/src/sama5/chip/sam_rtc.h
+++ b/arch/arm/src/sama5/hardware/sam_rtc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sama5d/chip/sam_rtc.h
+ * arch/arm/src/sama5/hardware/sam_rtc.h
  * Real-time Clock (RTC) definitions for the SAMA5D3
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_RTC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_RTC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_RTC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_RTC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -348,4 +348,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_RTC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_RTC_H */
diff --git a/arch/arm/src/sama5/chip/sam_rxlp.h b/arch/arm/src/sama5/hardware/sam_rxlp.h
similarity index 96%
rename from arch/arm/src/sama5/chip/sam_rxlp.h
rename to arch/arm/src/sama5/hardware/sam_rxlp.h
index b9bebee4434..bb31ff3bd56 100644
--- a/arch/arm/src/sama5/chip/sam_rxlp.h
+++ b/arch/arm/src/sama5/hardware/sam_rxlp.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/sama5/chip/sam_RXLP.h
+ * arch/arm/src/sama5/hardware/sam_RXLP.h
  * Low Power Asynchronous Receiver (RXLP) definitions for the SAMA5D3
  * and SAMAD4
  *
@@ -35,8 +35,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_RXLP_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_RXLP_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_RXLP_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_RXLP_H
 
 /************************************************************************************************
  * Included Files
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************************
  * Pre-processor Definitions
@@ -131,4 +131,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_RXLP_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_RXLP_H */
diff --git a/arch/arm/src/sama5/chip/sam_sckc.h b/arch/arm/src/sama5/hardware/sam_sckc.h
similarity index 92%
rename from arch/arm/src/sama5/chip/sam_sckc.h
rename to arch/arm/src/sama5/hardware/sam_sckc.h
index e9071585ae1..136cb865aa3 100644
--- a/arch/arm/src/sama5/chip/sam_sckc.h
+++ b/arch/arm/src/sama5/hardware/sam_sckc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_sckc.h
+ * arch/arm/src/sama5/hardware/sam_sckc.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SCKC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SCKC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SCKC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SCKC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -66,4 +66,4 @@
 
 #define SCKC_CR_OSCSEL        (1 << 3)  /* Bit 3:  Slow Clock Selector */
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SCKC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SCKC_H */
diff --git a/arch/arm/src/sama5/chip/sam_sfr.h b/arch/arm/src/sama5/hardware/sam_sfr.h
similarity index 98%
rename from arch/arm/src/sama5/chip/sam_sfr.h
rename to arch/arm/src/sama5/hardware/sam_sfr.h
index 03926e7bd62..fbd731ec16a 100644
--- a/arch/arm/src/sama5/chip/sam_sfr.h
+++ b/arch/arm/src/sama5/hardware/sam_sfr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_sfr.h
+ * arch/arm/src/sama5/hardware/sam_sfr.h
  *
  *   Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SFR_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SFR_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SFR_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SFR_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -310,4 +310,4 @@
 #    define SFR_QSPICLK_3p3V        (1 << 0)  /* Bit 0: 1=3.3V */
 #endif
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SFR_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SFR_H */
diff --git a/arch/arm/src/sama5/chip/sam_spi.h b/arch/arm/src/sama5/hardware/sam_spi.h
similarity index 98%
rename from arch/arm/src/sama5/chip/sam_spi.h
rename to arch/arm/src/sama5/hardware/sam_spi.h
index b9a7bcf17ca..a2dde6dd01f 100644
--- a/arch/arm/src/sama5/chip/sam_spi.h
+++ b/arch/arm/src/sama5/hardware/sam_spi.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sama5/chip/sam_spi.h
+ * arch/arm/src/sama5/hardware/sam_spi.h
  * Serial Peripheral Interface (SPI) definitions for the SAMA5
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SPI_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SPI_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SPI_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SPI_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -238,4 +238,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SPI_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SPI_H */
diff --git a/arch/arm/src/sama5/chip/sam_ssc.h b/arch/arm/src/sama5/hardware/sam_ssc.h
similarity index 98%
rename from arch/arm/src/sama5/chip/sam_ssc.h
rename to arch/arm/src/sama5/hardware/sam_ssc.h
index 558805027cf..bc13c238351 100644
--- a/arch/arm/src/sama5/chip/sam_ssc.h
+++ b/arch/arm/src/sama5/hardware/sam_ssc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_ssc.h
+ * arch/arm/src/sama5/hardware/sam_ssc.h
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SSC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SSC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SSC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SSC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -304,4 +304,4 @@
 #define SSC_WPSR_WPVSRC_SHIFT      (8)       /* Bits 8-23: Write Protect Violation Source */
 #define SSC_WPSR_WPVSRC_MASK       (0xffff << SSC_WPSR_WPVSRC_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SSC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_SSC_H */
diff --git a/arch/arm/src/sama5/chip/sam_tc.h b/arch/arm/src/sama5/hardware/sam_tc.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_tc.h
rename to arch/arm/src/sama5/hardware/sam_tc.h
index 0ecc9fab449..9fb7dc026fa 100644
--- a/arch/arm/src/sama5/chip/sam_tc.h
+++ b/arch/arm/src/sama5/hardware/sam_tc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_tc.h
+ * arch/arm/src/sama5/hardware/sam_tc.h
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_TC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_TC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -642,4 +642,4 @@
 #define TC_WPMR_WPKEY_MASK       (0xffffff << TC_WPMR_WPKEY_SHIFT)
 #  define TC_WPMR_WPKEY          (0x54494d << TC_WPMR_WPKEY_SHIFT) /* "TIM" in ASCII */
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_TC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TC_H */
diff --git a/arch/arm/src/sama5/chip/sam_trng.h b/arch/arm/src/sama5/hardware/sam_trng.h
similarity index 94%
rename from arch/arm/src/sama5/chip/sam_trng.h
rename to arch/arm/src/sama5/hardware/sam_trng.h
index 15ac49cb105..131c3a62557 100644
--- a/arch/arm/src/sama5/chip/sam_trng.h
+++ b/arch/arm/src/sama5/hardware/sam_trng.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_trng.h
+ * arch/arm/src/sama5/hardware/sam_trng.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_TRNG_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_TRNG_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TRNG_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TRNG_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -82,4 +82,4 @@
 
 /* Output Data Register (32-bit output data) */
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_TRNG_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TRNG_H */
diff --git a/arch/arm/src/sama5/chip/sam_twi.h b/arch/arm/src/sama5/hardware/sam_twi.h
similarity index 98%
rename from arch/arm/src/sama5/chip/sam_twi.h
rename to arch/arm/src/sama5/hardware/sam_twi.h
index daf1181be5c..536b0c721b1 100644
--- a/arch/arm/src/sama5/chip/sam_twi.h
+++ b/arch/arm/src/sama5/hardware/sam_twi.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sama5/chip/sam_twi.h
+ * arch/arm/src/sama5/hardware/sam_twi.h
  * Two-wire Interface (TWI) definitions for the SAMA5
  *
  *   Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_TWI_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_TWI_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TWI_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TWI_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -239,4 +239,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_TWI_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_TWI_H */
diff --git a/arch/arm/src/sama5/chip/sam_uart.h b/arch/arm/src/sama5/hardware/sam_uart.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_uart.h
rename to arch/arm/src/sama5/hardware/sam_uart.h
index 2ce0abbbf1b..a7e16a4dd2b 100644
--- a/arch/arm/src/sama5/chip/sam_uart.h
+++ b/arch/arm/src/sama5/hardware/sam_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/sama5/chip/sam_uart.h
+ * arch/arm/src/sama5/hardware/sam_uart.h
  * Universal Asynchronous Receiver Transmitter (UART) for the SAMA5D2, SAMA5D3, and SAMA5D4 and
  * Universal Synchronous Asynchronous Receiver Transmitter (USART) definitions for the SAMA5D3
  * and SAMAD4
@@ -36,8 +36,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_UART_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_UART_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_UART_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_UART_H
 
 /************************************************************************************************
  * Included Files
@@ -46,7 +46,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************************
  * Pre-processor Definitions
@@ -572,4 +572,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_UART_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_UART_H */
diff --git a/arch/arm/src/sama5/chip/sam_udphs.h b/arch/arm/src/sama5/hardware/sam_udphs.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_udphs.h
rename to arch/arm/src/sama5/hardware/sam_udphs.h
index 5b5becbfa4a..6045d2ee142 100644
--- a/arch/arm/src/sama5/chip/sam_udphs.h
+++ b/arch/arm/src/sama5/hardware/sam_udphs.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/sama5/chip/sam_udphs.h
+ * arch/arm/src/sama5/hardware/sam_udphs.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -36,8 +36,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_UDPHS_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_UDPHS_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_UDPHS_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_UDPHS_H
 
 /********************************************************************************************
  * Included Files
@@ -46,7 +46,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -478,4 +478,4 @@ struct udphs_dtd_s
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_UDPHS_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_UDPHS_H */
diff --git a/arch/arm/src/sama5/chip/sam_wdt.h b/arch/arm/src/sama5/hardware/sam_wdt.h
similarity index 95%
rename from arch/arm/src/sama5/chip/sam_wdt.h
rename to arch/arm/src/sama5/hardware/sam_wdt.h
index 657da369879..60746125463 100644
--- a/arch/arm/src/sama5/chip/sam_wdt.h
+++ b/arch/arm/src/sama5/hardware/sam_wdt.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sama5/chip/sam_wdt.h
+ * arch/arm/src/sama5/hardware/sam_wdt.h
  * Watchdog Timer (WDT) definitions for the SAMA5D3
  *
  *   Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_WDT_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_WDT_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_WDT_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_WDT_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -111,4 +111,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_WDT_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_WDT_H */
diff --git a/arch/arm/src/sama5/chip/sam_xdmac.h b/arch/arm/src/sama5/hardware/sam_xdmac.h
similarity index 99%
rename from arch/arm/src/sama5/chip/sam_xdmac.h
rename to arch/arm/src/sama5/hardware/sam_xdmac.h
index 41ed95453e7..a31ef737a7c 100644
--- a/arch/arm/src/sama5/chip/sam_xdmac.h
+++ b/arch/arm/src/sama5/hardware/sam_xdmac.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/sama5/chip/sam_xdmac.h
+ * arch/arm/src/sama5/hardware/sam_xdmac.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_XDMAC_H
-#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_XDMAC_H
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_XDMAC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_XDMAC_H
 
 /************************************************************************************
  * Included Files
@@ -541,4 +541,4 @@ struct chnext_view3_s
   uint32_t cdus; /* Destination Microblock Stride */
 };
 
-#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_XDMAC_H */
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_XDMAC_H */
diff --git a/arch/arm/src/sama5/sam_adc.c b/arch/arm/src/sama5/sam_adc.c
index b9c3c92d840..ce5072eefd9 100644
--- a/arch/arm/src/sama5/sam_adc.c
+++ b/arch/arm/src/sama5/sam_adc.c
@@ -71,9 +71,9 @@
 #include "up_arch.h"
 
 #include "chip.h"
-#include "chip/sam_adc.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_adc.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_pinmap.h"
 
 #include "sam_periphclks.h"
 #include "sam_memories.h"
diff --git a/arch/arm/src/sama5/sam_adc.h b/arch/arm/src/sama5/sam_adc.h
index 187fbf15e90..dcddc157415 100644
--- a/arch/arm/src/sama5/sam_adc.h
+++ b/arch/arm/src/sama5/sam_adc.h
@@ -44,7 +44,7 @@
 
 #include 
 
-#include "chip/sam_adc.h"
+#include "hardware/sam_adc.h"
 
 #ifdef CONFIG_SAMA5_ADC
 
diff --git a/arch/arm/src/sama5/sam_boot.c b/arch/arm/src/sama5/sam_boot.c
index 0a46bc6b2b3..31385596923 100644
--- a/arch/arm/src/sama5/sam_boot.c
+++ b/arch/arm/src/sama5/sam_boot.c
@@ -57,9 +57,9 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/sam_wdt.h"
-#include "chip/sam_aximx.h"
-#include "chip/sam_sfr.h"
+#include "hardware/sam_wdt.h"
+#include "hardware/sam_aximx.h"
+#include "hardware/sam_sfr.h"
 
 #include "sam_clockconfig.h"
 #include "sam_memorymap.h"
diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c
index b124666e190..1a3ac577a82 100644
--- a/arch/arm/src/sama5/sam_can.c
+++ b/arch/arm/src/sama5/sam_can.c
@@ -66,7 +66,7 @@
 #include "up_arch.h"
 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 #include "sam_periphclks.h"
 #include "sam_pio.h"
 #include "sam_can.h"
diff --git a/arch/arm/src/sama5/sam_can.h b/arch/arm/src/sama5/sam_can.h
index bff7c1efbf0..1f96747dcb2 100644
--- a/arch/arm/src/sama5/sam_can.h
+++ b/arch/arm/src/sama5/sam_can.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_can.h"
+#include "hardware/sam_can.h"
 
 #include 
 
diff --git a/arch/arm/src/sama5/sam_clockconfig.c b/arch/arm/src/sama5/sam_clockconfig.c
index f743c7ae9a2..17d8272fbb2 100644
--- a/arch/arm/src/sama5/sam_clockconfig.c
+++ b/arch/arm/src/sama5/sam_clockconfig.c
@@ -51,8 +51,8 @@
 
 #include "sam_periphclks.h"
 #include "sam_clockconfig.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_sfr.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_sfr.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/sam_dbgu.c b/arch/arm/src/sama5/sam_dbgu.c
index a136c9bd449..18f35033706 100644
--- a/arch/arm/src/sama5/sam_dbgu.c
+++ b/arch/arm/src/sama5/sam_dbgu.c
@@ -59,8 +59,8 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/sam_dbgu.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_dbgu.h"
+#include "hardware/sam_pinmap.h"
 #include "sam_pio.h"
 #include "sam_dbgu.h"
 
diff --git a/arch/arm/src/sama5/sam_dmac.c b/arch/arm/src/sama5/sam_dmac.c
index c1366419518..46aec6b848a 100644
--- a/arch/arm/src/sama5/sam_dmac.c
+++ b/arch/arm/src/sama5/sam_dmac.c
@@ -57,8 +57,8 @@
 #include "sam_dmac.h"
 #include "sam_periphclks.h"
 #include "sam_memories.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_dmac.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_dmac.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/sam_ehci.c b/arch/arm/src/sama5/sam_ehci.c
index 92367c8bbd0..6f631946b93 100644
--- a/arch/arm/src/sama5/sam_ehci.c
+++ b/arch/arm/src/sama5/sam_ehci.c
@@ -65,8 +65,8 @@
 #include "sam_periphclks.h"
 #include "sam_memories.h"
 #include "sam_usbhost.h"
-#include "chip/sam_sfr.h"
-#include "chip/sam_ehci.h"
+#include "hardware/sam_sfr.h"
+#include "hardware/sam_ehci.h"
 
 #ifdef CONFIG_SAMA5_EHCI
 
diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c
index 4447bddfe57..ddbc185d9be 100644
--- a/arch/arm/src/sama5/sam_emaca.c
+++ b/arch/arm/src/sama5/sam_emaca.c
@@ -79,7 +79,7 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 #include "sam_pio.h"
 #include "sam_periphclks.h"
 #include "sam_memories.h"
@@ -2539,7 +2539,7 @@ static int sam_phyintenable(struct sam_emac_s *priv)
       /* Enable link up/down interrupts */
 
       ret = sam_phywrite(priv, priv->phyaddr, MII_KSZ8081_INT,
-                        (MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN));
+                        (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN));
     }
 
   /* Disable management port (probably) */
diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c
index 6807fa4f6a6..ff39f84ab51 100644
--- a/arch/arm/src/sama5/sam_emacb.c
+++ b/arch/arm/src/sama5/sam_emacb.c
@@ -93,7 +93,7 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 #include "sam_pio.h"
 #include "sam_periphclks.h"
 #include "sam_memories.h"
@@ -2982,7 +2982,7 @@ static int sam_phyintenable(struct sam_emac_s *priv)
   uint16_t phyval;
   int ret;
 
-  /* Does this MAC support a KSZ80x1 PHY? */
+  /* Does this MAC support a KSZ80X1 PHY? */
 
   if (priv->phytype == SAMA5_PHY_KSZ8051 || priv->phytype == SAMA5_PHY_KSZ8081)
     {
@@ -3001,7 +3001,7 @@ static int sam_phyintenable(struct sam_emac_s *priv)
           /* Enable link up/down interrupts */
 
           ret = sam_phywrite(priv, priv->phyaddr, MII_KSZ8081_INT,
-                            (MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN));
+                            (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN));
         }
 
       /* Disable management port (probably) */
diff --git a/arch/arm/src/sama5/sam_ethernet.h b/arch/arm/src/sama5/sam_ethernet.h
index 4625556c45a..3b09839292b 100644
--- a/arch/arm/src/sama5/sam_ethernet.h
+++ b/arch/arm/src/sama5/sam_ethernet.h
@@ -43,8 +43,8 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_emac.h"
-#include "chip/sam_gmac.h"
+#include "hardware/sam_emac.h"
+#include "hardware/sam_gmac.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/sam_flexcom_serial.c b/arch/arm/src/sama5/sam_flexcom_serial.c
index 58c4121cac6..8a36fff8ec3 100644
--- a/arch/arm/src/sama5/sam_flexcom_serial.c
+++ b/arch/arm/src/sama5/sam_flexcom_serial.c
@@ -63,7 +63,7 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/sam_flexcom.h"
+#include "hardware/sam_flexcom.h"
 #include "sam_config.h"
 #include "sam_dbgu.h"
 #include "sam_serial.h"
diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c
index 95ef7e65e3f..a845c6ba6f0 100644
--- a/arch/arm/src/sama5/sam_gmac.c
+++ b/arch/arm/src/sama5/sam_gmac.c
@@ -76,7 +76,7 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 #include "sam_pio.h"
 #include "sam_periphclks.h"
 #include "sam_memories.h"
diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c
index 8ce3a251a02..966c0f442da 100644
--- a/arch/arm/src/sama5/sam_hsmci.c
+++ b/arch/arm/src/sama5/sam_hsmci.c
@@ -66,10 +66,10 @@
 #include "sam_periphclks.h"
 #include "sam_memories.h"
 #include "sam_hsmci.h"
-#include "chip/sam_dmac.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_hsmci.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_dmac.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_hsmci.h"
+#include "hardware/sam_pinmap.h"
 
 #if defined(CONFIG_SAMA5_HSMCI0) || defined(CONFIG_SAMA5_HSMCI1) || \
     defined(CONFIG_SAMA5_HSMCI2)
diff --git a/arch/arm/src/sama5/sam_hsmci_clkdiv.c b/arch/arm/src/sama5/sam_hsmci_clkdiv.c
index 4a56bed140f..b6fa5e84f02 100644
--- a/arch/arm/src/sama5/sam_hsmci_clkdiv.c
+++ b/arch/arm/src/sama5/sam_hsmci_clkdiv.c
@@ -48,7 +48,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_hsmci.h"
+#include "hardware/sam_hsmci.h"
 #include "sam_hsmci.h"
 
 #if defined(CONFIG_SAMA5_HSMCI0) || defined(CONFIG_SAMA5_HSMCI1) || \
diff --git a/arch/arm/src/sama5/sam_irq.c b/arch/arm/src/sama5/sam_irq.c
index 44cce23e13f..81b56bf6718 100644
--- a/arch/arm/src/sama5/sam_irq.c
+++ b/arch/arm/src/sama5/sam_irq.c
@@ -57,10 +57,10 @@
 #include "mmu.h"
 #include "cp15_cacheops.h"
 #include "sctlr.h"
-#include "chip/sam_aic.h"
-#include "chip/sam_matrix.h"
-#include "chip/sam_aximx.h"
-#include "chip/sam_sfr.h"
+#include "hardware/sam_aic.h"
+#include "hardware/sam_matrix.h"
+#include "hardware/sam_aximx.h"
+#include "hardware/sam_sfr.h"
 
 #include "sam_irq.h"
 
diff --git a/arch/arm/src/sama5/sam_irq.h b/arch/arm/src/sama5/sam_irq.h
index 5f462862d00..be1418b9a96 100644
--- a/arch/arm/src/sama5/sam_irq.h
+++ b/arch/arm/src/sama5/sam_irq.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/sam_aic.h"
+#include "hardware/sam_aic.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/sam_isi.h b/arch/arm/src/sama5/sam_isi.h
index 5b3bc7482fc..525eaef6e09 100644
--- a/arch/arm/src/sama5/sam_isi.h
+++ b/arch/arm/src/sama5/sam_isi.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_isi.h"
+#include "hardware/sam_isi.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/sam_lcd.c b/arch/arm/src/sama5/sam_lcd.c
index 2033e45861f..fb136d31a1b 100644
--- a/arch/arm/src/sama5/sam_lcd.c
+++ b/arch/arm/src/sama5/sam_lcd.c
@@ -59,8 +59,8 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/sam_lcdc.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_lcdc.h"
+#include "hardware/sam_pinmap.h"
 #include "sam_pio.h"
 #include "sam_periphclks.h"
 #include "sam_memories.h"
@@ -645,9 +645,9 @@ struct sam_lcdc_s
   struct sam_layer_s layer[LCDC_NLAYERS];
 
 #ifdef CONFIG_FB_HWCURSOR
-  struct cursor_pos_s cpos;       /* Current cursor position */
+  struct fb_cursorpos_s cpos;     /* Current cursor position */
 #ifdef CONFIG_FB_HWCURSORSIZE
-  struct cursor_size_s csize;     /* Current cursor size */
+  struct fb_cursorsize_s csize;   /* Current cursor size */
 #endif
 #endif
 
diff --git a/arch/arm/src/sama5/sam_lcd.h b/arch/arm/src/sama5/sam_lcd.h
index d16a2ec6f83..6fe2439c453 100644
--- a/arch/arm/src/sama5/sam_lcd.h
+++ b/arch/arm/src/sama5/sam_lcd.h
@@ -46,7 +46,7 @@
 
 #include 
 
-#include "chip/sam_lcdc.h"
+#include "hardware/sam_lcdc.h"
 
 #ifdef CONFIG_SAMA5_LCDC
 
diff --git a/arch/arm/src/sama5/sam_lowputc.c b/arch/arm/src/sama5/sam_lowputc.c
index f94f6f05167..484c2417e9c 100644
--- a/arch/arm/src/sama5/sam_lowputc.c
+++ b/arch/arm/src/sama5/sam_lowputc.c
@@ -52,10 +52,10 @@
 #include "sam_dbgu.h"
 #include "sam_lowputc.h"
 
-#include "chip/sam_uart.h"
-#include "chip/sam_flexcom.h"
-#include "chip/sam_dbgu.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_uart.h"
+#include "hardware/sam_flexcom.h"
+#include "hardware/sam_dbgu.h"
+#include "hardware/sam_pinmap.h"
 
 #include 
 
diff --git a/arch/arm/src/sama5/sam_nand.h b/arch/arm/src/sama5/sam_nand.h
index 69c6b729e9e..6d7101ad29a 100644
--- a/arch/arm/src/sama5/sam_nand.h
+++ b/arch/arm/src/sama5/sam_nand.h
@@ -52,7 +52,7 @@
 
 #include "up_arch.h"
 #include "chip.h"
-#include "chip/sam_hsmc.h"
+#include "hardware/sam_hsmc.h"
 
 #include "sam_dmac.h"
 
diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c
index ce5bbf87228..1cc36af7b7d 100644
--- a/arch/arm/src/sama5/sam_ohci.c
+++ b/arch/arm/src/sama5/sam_ohci.c
@@ -69,9 +69,9 @@
 #include "sam_periphclks.h"
 #include "sam_memories.h"
 #include "sam_usbhost.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_sfr.h"
-#include "chip/sam_ohci.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_sfr.h"
+#include "hardware/sam_ohci.h"
 
 #ifdef CONFIG_SAMA5_OHCI
 
diff --git a/arch/arm/src/sama5/sam_pck.c b/arch/arm/src/sama5/sam_pck.c
index dc96ab678c7..fc63e80425a 100644
--- a/arch/arm/src/sama5/sam_pck.c
+++ b/arch/arm/src/sama5/sam_pck.c
@@ -45,7 +45,7 @@
 
 #include 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 
 #include "up_arch.h"
 #include "sam_pio.h"
diff --git a/arch/arm/src/sama5/sam_pck.h b/arch/arm/src/sama5/sam_pck.h
index 0d8199e8ea8..b304c6f5b08 100644
--- a/arch/arm/src/sama5/sam_pck.h
+++ b/arch/arm/src/sama5/sam_pck.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pmc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/sam_pio.h b/arch/arm/src/sama5/sam_pio.h
index fbcf94d0340..b2cb5c70080 100644
--- a/arch/arm/src/sama5/sam_pio.h
+++ b/arch/arm/src/sama5/sam_pio.h
@@ -48,7 +48,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/sam_pioirq.c b/arch/arm/src/sama5/sam_pioirq.c
index 97aef6a0bce..36dc7d61c3f 100644
--- a/arch/arm/src/sama5/sam_pioirq.c
+++ b/arch/arm/src/sama5/sam_pioirq.c
@@ -53,8 +53,8 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/sam_pio.h"
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pio.h"
+#include "hardware/sam_pmc.h"
 
 #include "sam_pio.h"
 #include "sam_periphclks.h"
diff --git a/arch/arm/src/sama5/sam_pmc.c b/arch/arm/src/sama5/sam_pmc.c
index f6c6b555f6a..1c6596a7b1e 100644
--- a/arch/arm/src/sama5/sam_pmc.c
+++ b/arch/arm/src/sama5/sam_pmc.c
@@ -52,10 +52,10 @@
 #include "chip.h"
 
 #ifdef CONFIG_ARCH_HAVE_SDIO
-#  include "chip/sam_hsmci.h"
+#  include "hardware/sam_hsmci.h"
 #endif
 
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pmc.h"
 #include "sam_pmc.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c
index 1758bee1a79..af5086c1892 100644
--- a/arch/arm/src/sama5/sam_pwm.c
+++ b/arch/arm/src/sama5/sam_pwm.c
@@ -49,7 +49,7 @@
 #include 
 #include 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 #include 
 
 #include "up_internal.h"
diff --git a/arch/arm/src/sama5/sam_pwm.h b/arch/arm/src/sama5/sam_pwm.h
index b9615d64da6..3dbbffcc959 100644
--- a/arch/arm/src/sama5/sam_pwm.h
+++ b/arch/arm/src/sama5/sam_pwm.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_pwm.h"
+#include "hardware/sam_pwm.h"
 
 #ifdef CONFIG_SAMA5_PWM
 
diff --git a/arch/arm/src/sama5/sam_rtc.h b/arch/arm/src/sama5/sam_rtc.h
index bb97c5ea566..9007cb5ef6f 100644
--- a/arch/arm/src/sama5/sam_rtc.h
+++ b/arch/arm/src/sama5/sam_rtc.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_rtc.h"
+#include "hardware/sam_rtc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/sam_sckc.h b/arch/arm/src/sama5/sam_sckc.h
index 0dc2a2ed4ce..0c2524ec435 100644
--- a/arch/arm/src/sama5/sam_sckc.h
+++ b/arch/arm/src/sama5/sam_sckc.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_sckc.h"
+#include "hardware/sam_sckc.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/sam_serial.c b/arch/arm/src/sama5/sam_serial.c
index 1952cc839a4..a368140eb56 100644
--- a/arch/arm/src/sama5/sam_serial.c
+++ b/arch/arm/src/sama5/sam_serial.c
@@ -63,7 +63,7 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/sam_uart.h"
+#include "hardware/sam_uart.h"
 #include "sam_config.h"
 #include "sam_dbgu.h"
 #include "sam_serial.h"
diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c
index eaf58820206..3848709521d 100644
--- a/arch/arm/src/sama5/sam_spi.c
+++ b/arch/arm/src/sama5/sam_spi.c
@@ -72,9 +72,9 @@
 #include "sam_memories.h"
 #include "sam_periphclks.h"
 #include "sam_spi.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_spi.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_spi.h"
+#include "hardware/sam_pinmap.h"
 
 #if defined(CONFIG_SAMA5_SPI0) || defined(CONFIG_SAMA5_SPI1)
 
diff --git a/arch/arm/src/sama5/sam_ssc.c b/arch/arm/src/sama5/sam_ssc.c
index 5da89da2f9d..f9cca0ae4e6 100644
--- a/arch/arm/src/sama5/sam_ssc.c
+++ b/arch/arm/src/sama5/sam_ssc.c
@@ -69,9 +69,9 @@
 #include "sam_memories.h"
 #include "sam_periphclks.h"
 #include "sam_ssc.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_ssc.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_ssc.h"
+#include "hardware/sam_pinmap.h"
 
 #if defined(CONFIG_SAMA5_SSC0) || defined(CONFIG_SAMA5_SSC1)
 
diff --git a/arch/arm/src/sama5/sam_ssc.h b/arch/arm/src/sama5/sam_ssc.h
index 7ae4dafe079..ad74273a961 100644
--- a/arch/arm/src/sama5/sam_ssc.h
+++ b/arch/arm/src/sama5/sam_ssc.h
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_ssc.h"
+#include "hardware/sam_ssc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/sam_tc.c b/arch/arm/src/sama5/sam_tc.c
index a0a3f79198b..4ac41adf514 100644
--- a/arch/arm/src/sama5/sam_tc.c
+++ b/arch/arm/src/sama5/sam_tc.c
@@ -63,8 +63,8 @@
 
 #include "up_arch.h"
 #include "sam_periphclks.h"
-#include "chip/sam_pinmap.h"
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
 #include "sam_pio.h"
 #include "sam_tc.h"
 
diff --git a/arch/arm/src/sama5/sam_tc.h b/arch/arm/src/sama5/sam_tc.h
index 4cf53f9cc80..06ea59a7929 100644
--- a/arch/arm/src/sama5/sam_tc.h
+++ b/arch/arm/src/sama5/sam_tc.h
@@ -46,7 +46,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_tc.h"
+#include "hardware/sam_tc.h"
 
 #if defined(CONFIG_SAMA5_TC0) || defined(CONFIG_SAMA5_TC1) || defined(CONFIG_SAMA5_TC2)
 
diff --git a/arch/arm/src/sama5/sam_timerisr.c b/arch/arm/src/sama5/sam_timerisr.c
index 9a0216a42e9..1826f7956c0 100644
--- a/arch/arm/src/sama5/sam_timerisr.c
+++ b/arch/arm/src/sama5/sam_timerisr.c
@@ -49,7 +49,7 @@
 
 #include "up_arch.h"
 #include "sam_periphclks.h"
-#include "chip/sam_pit.h"
+#include "hardware/sam_pit.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/sam_trng.c b/arch/arm/src/sama5/sam_trng.c
index c224492539d..d81794f6964 100644
--- a/arch/arm/src/sama5/sam_trng.c
+++ b/arch/arm/src/sama5/sam_trng.c
@@ -99,15 +99,13 @@ static struct trng_dev_s g_trngdev;
 
 static const struct file_operations g_trngops =
 {
-  0,               /* open */
-  0,               /* close */
+  NULL,            /* open */
+  NULL,            /* close */
   sam_read,        /* read */
-  0,               /* write */
-  0,               /* seek */
-  0                /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0              /* poll */
-#endif
+  NULL,            /* write */
+  NULL,            /* seek */
+  NULL,            /* ioctl */
+  NULL             /* poll */
 };
 
 /****************************************************************************
diff --git a/arch/arm/src/sama5/sam_trng.h b/arch/arm/src/sama5/sam_trng.h
index d27186ac3cc..8b5c63b9d5f 100644
--- a/arch/arm/src/sama5/sam_trng.h
+++ b/arch/arm/src/sama5/sam_trng.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_trng.h"
+#include "hardware/sam_trng.h"
 
 #if defined(CONFIG_DEV_RANDOM) && defined(CONFIG_SAMA5_TRNG)
 
diff --git a/arch/arm/src/sama5/sam_tsd.c b/arch/arm/src/sama5/sam_tsd.c
index 3446500878b..91491d27d83 100644
--- a/arch/arm/src/sama5/sam_tsd.c
+++ b/arch/arm/src/sama5/sam_tsd.c
@@ -72,7 +72,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/sam_adc.h"
+#include "hardware/sam_adc.h"
 #include "sam_adc.h"
 #include "sam_tsd.h"
 
@@ -185,9 +185,7 @@ struct sam_tsd_s
    * retained in the f_priv field of the 'struct file'.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_SAMA5_TSD_NPOLLWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -210,9 +208,7 @@ static int  sam_tsd_open(struct file *filep);
 static int  sam_tsd_close(struct file *filep);
 static ssize_t sam_tsd_read(struct file *filep, char *buffer, size_t len);
 static int  sam_tsd_ioctl(struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int  sam_tsd_poll(struct file *filep, struct pollfd *fds, bool setup);
-#endif
 
 /* Initialization and configuration */
 
@@ -234,12 +230,10 @@ static const struct file_operations g_tsdops =
   sam_tsd_open,    /* open */
   sam_tsd_close,   /* close */
   sam_tsd_read,    /* read */
-  0,               /* write */
-  0,               /* seek */
-  sam_tsd_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , sam_tsd_poll   /* poll */
-#endif
+  NULL,            /* write */
+  NULL,            /* seek */
+  sam_tsd_ioctl,   /* ioctl */
+  sam_tsd_poll     /* poll */
 };
 
 /* The driver state structure is pre-allocated. */
@@ -256,9 +250,7 @@ static struct sam_tsd_s g_tsd;
 
 static void sam_tsd_notify(struct sam_tsd_s *priv)
 {
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   /* If there are threads waiting for read data, then signal one of them
    * that the read data is available.
@@ -279,7 +271,6 @@ static void sam_tsd_notify(struct sam_tsd_s *priv)
    * then some make end up blocking after all.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   for (i = 0; i < CONFIG_SAMA5_TSD_NPOLLWAITERS; i++)
     {
       struct pollfd *fds = priv->fds[i];
@@ -290,7 +281,6 @@ static void sam_tsd_notify(struct sam_tsd_s *priv)
           nxsem_post(fds->sem);
         }
     }
-#endif
 }
 
 /****************************************************************************
@@ -1071,7 +1061,6 @@ static int sam_tsd_ioctl(struct file *filep, int cmd, unsigned long arg)
  * Name: sam_tsd_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int sam_tsd_poll(struct file *filep, struct pollfd *fds, bool setup)
 {
   struct inode *inode;
@@ -1151,7 +1140,6 @@ errout:
   sam_adc_unlock(priv->adc);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Initialization and Configuration
diff --git a/arch/arm/src/sama5/sam_tsd.h b/arch/arm/src/sama5/sam_tsd.h
index ff0d6a5ead8..041b0811dd6 100644
--- a/arch/arm/src/sama5/sam_tsd.h
+++ b/arch/arm/src/sama5/sam_tsd.h
@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/sam_adc.h"
+#include "hardware/sam_adc.h"
 
 #if defined(CONFIG_SAMA5_ADC) && defined(CONFIG_SAMA5_TSD)
 
diff --git a/arch/arm/src/sama5/sam_twi.c b/arch/arm/src/sama5/sam_twi.c
index 7cc040f4655..05fb5c6e0bb 100644
--- a/arch/arm/src/sama5/sam_twi.c
+++ b/arch/arm/src/sama5/sam_twi.c
@@ -65,8 +65,8 @@
 
 #include "up_arch.h"
 
-#include "chip/sam_pmc.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_pinmap.h"
 
 #include "sam_periphclks.h"
 #include "sam_pio.h"
diff --git a/arch/arm/src/sama5/sam_twi.h b/arch/arm/src/sama5/sam_twi.h
index f966bec8f8b..078ba9cd1e1 100644
--- a/arch/arm/src/sama5/sam_twi.h
+++ b/arch/arm/src/sama5/sam_twi.h
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/sam_twi.h"
+#include "hardware/sam_twi.h"
 
 /****************************************************************************
  * Public Function Prototypes
diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c
index 5c1edc53fe6..0927669e42d 100644
--- a/arch/arm/src/sama5/sam_udphs.c
+++ b/arch/arm/src/sama5/sam_udphs.c
@@ -69,7 +69,7 @@
 
 #include "sam_periphclks.h"
 #include "sam_memories.h"
-#include "chip/sam_udphs.h"
+#include "hardware/sam_udphs.h"
 #include "sam_udphs.h"
 
 #if defined(CONFIG_USBDEV) && defined(CONFIG_SAMA5_UDPHS)
diff --git a/arch/arm/src/sama5/sam_udphs.h b/arch/arm/src/sama5/sam_udphs.h
index 1f8ec79dec9..2758adf0ad7 100644
--- a/arch/arm/src/sama5/sam_udphs.h
+++ b/arch/arm/src/sama5/sam_udphs.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_udphs.h"
+#include "hardware/sam_udphs.h"
 
 /************************************************************************************
  * Public Functions
diff --git a/arch/arm/src/sama5/sam_wdt.h b/arch/arm/src/sama5/sam_wdt.h
index ba3a067b1df..aea3e1a1f8e 100644
--- a/arch/arm/src/sama5/sam_wdt.h
+++ b/arch/arm/src/sama5/sam_wdt.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_wdt.h"
+#include "hardware/sam_wdt.h"
 
 #ifdef CONFIG_WATCHDOG
 
diff --git a/arch/arm/src/sama5/sam_xdmac.c b/arch/arm/src/sama5/sam_xdmac.c
index e903b0dd03f..b2c2e5a2467 100644
--- a/arch/arm/src/sama5/sam_xdmac.c
+++ b/arch/arm/src/sama5/sam_xdmac.c
@@ -57,8 +57,8 @@
 #include "sam_dmac.h"
 #include "sam_periphclks.h"
 #include "sam_memories.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_xdmac.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_xdmac.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/sama5d2x_memorymap.c b/arch/arm/src/sama5/sama5d2x_memorymap.c
index e73281cabd2..a9dc6cdabab 100644
--- a/arch/arm/src/sama5/sama5d2x_memorymap.c
+++ b/arch/arm/src/sama5/sama5d2x_memorymap.c
@@ -41,7 +41,7 @@
 
 #include "mmu.h"
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 #include "sam_lcd.h"
 #include "sam_memorymap.h"
 
diff --git a/arch/arm/src/sama5/sama5d2x_periphclks.h b/arch/arm/src/sama5/sama5d2x_periphclks.h
index 181169634ea..2867e5da6bf 100644
--- a/arch/arm/src/sama5/sama5d2x_periphclks.h
+++ b/arch/arm/src/sama5/sama5d2x_periphclks.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 #include 
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pmc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/sama5d2x_pio.c b/arch/arm/src/sama5/sama5d2x_pio.c
index 4907529be44..163d957085f 100644
--- a/arch/arm/src/sama5/sama5d2x_pio.c
+++ b/arch/arm/src/sama5/sama5d2x_pio.c
@@ -52,7 +52,7 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/_sama5d2x_pio.h"
+#include "hardware/_sama5d2x_pio.h"
 
 #include "chip.h"
 #include "sam_periphclks.h"
diff --git a/arch/arm/src/sama5/sama5d2x_pio.h b/arch/arm/src/sama5/sama5d2x_pio.h
index 4b0324dc963..2512af37f57 100644
--- a/arch/arm/src/sama5/sama5d2x_pio.h
+++ b/arch/arm/src/sama5/sama5d2x_pio.h
@@ -46,7 +46,7 @@
 #include 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/sama5d3x4x_pio.c b/arch/arm/src/sama5/sama5d3x4x_pio.c
index 5f979f3c856..af2d7a40af7 100644
--- a/arch/arm/src/sama5/sama5d3x4x_pio.c
+++ b/arch/arm/src/sama5/sama5d3x4x_pio.c
@@ -52,7 +52,7 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/_sama5d3x4x_pio.h"
+#include "hardware/_sama5d3x4x_pio.h"
 
 #include "chip.h"
 #include "sam_periphclks.h"
diff --git a/arch/arm/src/sama5/sama5d3x_memorymap.c b/arch/arm/src/sama5/sama5d3x_memorymap.c
index 229d2e81327..0f08951c4e4 100644
--- a/arch/arm/src/sama5/sama5d3x_memorymap.c
+++ b/arch/arm/src/sama5/sama5d3x_memorymap.c
@@ -41,7 +41,7 @@
 
 #include "mmu.h"
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 #include "sam_lcd.h"
 #include "sam_memorymap.h"
 
diff --git a/arch/arm/src/sama5/sama5d3x_periphclks.h b/arch/arm/src/sama5/sama5d3x_periphclks.h
index 2d2fe7c3e9d..c826aa6558b 100644
--- a/arch/arm/src/sama5/sama5d3x_periphclks.h
+++ b/arch/arm/src/sama5/sama5d3x_periphclks.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 #include 
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pmc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/sama5/sama5d4x_memorymap.c b/arch/arm/src/sama5/sama5d4x_memorymap.c
index 8d63ea70d53..548d3a1e79f 100644
--- a/arch/arm/src/sama5/sama5d4x_memorymap.c
+++ b/arch/arm/src/sama5/sama5d4x_memorymap.c
@@ -41,7 +41,7 @@
 
 #include "mmu.h"
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 #include "sam_lcd.h"
 #include "sam_memorymap.h"
 
diff --git a/arch/arm/src/sama5/sama5d4x_periphclks.h b/arch/arm/src/sama5/sama5d4x_periphclks.h
index c4e14eda63c..52386de68c5 100644
--- a/arch/arm/src/sama5/sama5d4x_periphclks.h
+++ b/arch/arm/src/sama5/sama5d4x_periphclks.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 #include 
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pmc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/samd2l2/Make.defs b/arch/arm/src/samd2l2/Make.defs
index e35d992c649..58244be81d3 100644
--- a/arch/arm/src/samd2l2/Make.defs
+++ b/arch/arm/src/samd2l2/Make.defs
@@ -49,11 +49,9 @@ CMN_CSRCS += up_hardfault.c up_svcall.c up_vectors.c up_vfork.c
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
diff --git a/arch/arm/src/samd2l2/chip.h b/arch/arm/src/samd2l2/chip.h
index 9e877a5d8f9..d49ae704ef6 100644
--- a/arch/arm/src/samd2l2/chip.h
+++ b/arch/arm/src/samd2l2/chip.h
@@ -55,11 +55,11 @@
  */
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20)
-#  include "chip/samd20_memorymap.h"
+#  include "hardware/samd20_memorymap.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd21_memorymap.h"
+#  include "hardware/samd21_memorymap.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml21_memorymap.h"
+#  include "hardware/saml21_memorymap.h"
 #else
 #  error Unrecognized SAMD/L architecture
 #endif
diff --git a/arch/arm/src/samd2l2/chip/samd20_memorymap.h b/arch/arm/src/samd2l2/hardware/samd20_memorymap.h
similarity index 96%
rename from arch/arm/src/samd2l2/chip/samd20_memorymap.h
rename to arch/arm/src/samd2l2/hardware/samd20_memorymap.h
index c34efc1e7d6..5a22a5361fe 100644
--- a/arch/arm/src/samd2l2/chip/samd20_memorymap.h
+++ b/arch/arm/src/samd2l2/hardware/samd20_memorymap.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd20_memorymap.h
+ * arch/arm/src/samd2l2/hardware/samd20_memorymap.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD20_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD20_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_MEMORYMAP_H
 
 /********************************************************************************************
  * Included Files
@@ -124,4 +124,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD20_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_MEMORYMAP_H */
diff --git a/arch/arm/src/samd2l2/chip/samd20_pinmap.h b/arch/arm/src/samd2l2/hardware/samd20_pinmap.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/samd20_pinmap.h
rename to arch/arm/src/samd2l2/hardware/samd20_pinmap.h
index be59294046d..a28f2ebf58a 100644
--- a/arch/arm/src/samd2l2/chip/samd20_pinmap.h
+++ b/arch/arm/src/samd2l2/hardware/samd20_pinmap.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd20_pinmap.h
+ * arch/arm/src/samd2l2/hardware/samd20_pinmap.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD20_PINMAP_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD20_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_PINMAP_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_PINMAP_H
 
 /********************************************************************************************
  * Included Files
@@ -362,4 +362,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD20_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD20_PINMAP_H */
diff --git a/arch/arm/src/samd2l2/chip/samd21_memorymap.h b/arch/arm/src/samd2l2/hardware/samd21_memorymap.h
similarity index 96%
rename from arch/arm/src/samd2l2/chip/samd21_memorymap.h
rename to arch/arm/src/samd2l2/hardware/samd21_memorymap.h
index 17f23d86eb9..e52a2fab42a 100644
--- a/arch/arm/src/samd2l2/chip/samd21_memorymap.h
+++ b/arch/arm/src/samd2l2/hardware/samd21_memorymap.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd21_memorymap.h
+ * arch/arm/src/samd2l2/hardware/samd21_memorymap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD21_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD21_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_MEMORYMAP_H
 
 /********************************************************************************************
  * Included Files
@@ -129,4 +129,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD21_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_MEMORYMAP_H */
diff --git a/arch/arm/src/samd2l2/chip/samd21_pinmap.h b/arch/arm/src/samd2l2/hardware/samd21_pinmap.h
similarity index 99%
rename from arch/arm/src/samd2l2/chip/samd21_pinmap.h
rename to arch/arm/src/samd2l2/hardware/samd21_pinmap.h
index a9a6ccd089e..a5ef79376e3 100644
--- a/arch/arm/src/samd2l2/chip/samd21_pinmap.h
+++ b/arch/arm/src/samd2l2/hardware/samd21_pinmap.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd21_pinmap.h
+ * arch/arm/src/samd2l2/hardware/samd21_pinmap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD21_PINMAP_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD21_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_PINMAP_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_PINMAP_H
 
 /********************************************************************************************
  * Included Files
@@ -413,4 +413,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD21_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD21_PINMAP_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_ac.h b/arch/arm/src/samd2l2/hardware/samd_ac.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/samd_ac.h
rename to arch/arm/src/samd2l2/hardware/samd_ac.h
index ea66654bbb6..a4a7b616350 100644
--- a/arch/arm/src/samd2l2/chip/samd_ac.h
+++ b/arch/arm/src/samd2l2/hardware/samd_ac.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_ac.h
+ * arch/arm/src/samd2l2/hardware/samd_ac.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Matt Thompson 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_AC_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_AC_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_AC_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_AC_H
 
 /********************************************************************************************
  * Included Files
@@ -206,4 +206,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_AC_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_AC_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_adc.h b/arch/arm/src/samd2l2/hardware/samd_adc.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/samd_adc.h
rename to arch/arm/src/samd2l2/hardware/samd_adc.h
index 6a081835d44..4cdba8819cb 100644
--- a/arch/arm/src/samd2l2/chip/samd_adc.h
+++ b/arch/arm/src/samd2l2/hardware/samd_adc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_adc.h
+ * arch/arm/src/samd2l2/hardware/samd_adc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Alexander Vasiljev 
@@ -36,8 +36,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_ADC_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_ADC_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_ADC_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_ADC_H
 
 /********************************************************************************************
  * Included Files
@@ -274,4 +274,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_ADC_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_ADC_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_dac.h b/arch/arm/src/samd2l2/hardware/samd_dac.h
similarity index 97%
rename from arch/arm/src/samd2l2/chip/samd_dac.h
rename to arch/arm/src/samd2l2/hardware/samd_dac.h
index 813ae97e915..2eed6a11ffa 100644
--- a/arch/arm/src/samd2l2/chip/samd_dac.h
+++ b/arch/arm/src/samd2l2/hardware/samd_dac.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_dac.h
+ * arch/arm/src/samd2l2/hardware/saml_dac.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_DAC_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_DAC_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DAC_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DAC_H
 
 /********************************************************************************************
  * Included Files
@@ -133,4 +133,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_DAC_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DAC_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_dmac.h b/arch/arm/src/samd2l2/hardware/samd_dmac.h
similarity index 99%
rename from arch/arm/src/samd2l2/chip/samd_dmac.h
rename to arch/arm/src/samd2l2/hardware/samd_dmac.h
index 7e5db664a74..bdf1c363168 100644
--- a/arch/arm/src/samd2l2/chip/samd_dmac.h
+++ b/arch/arm/src/samd2l2/hardware/samd_dmac.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_dmac.h
+ * arch/arm/src/samd2l2/hardware/samd_dmac.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -38,8 +38,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_DMAC_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_DMAC_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DMAC_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DMAC_H
 
 /********************************************************************************************
  * Included Files
@@ -396,4 +396,4 @@ struct dma_desc_s
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_DMAC_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_DMAC_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_eic.h b/arch/arm/src/samd2l2/hardware/samd_eic.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/samd_eic.h
rename to arch/arm/src/samd2l2/hardware/samd_eic.h
index 8f02bfc531e..a03b682715b 100644
--- a/arch/arm/src/samd2l2/chip/samd_eic.h
+++ b/arch/arm/src/samd2l2/hardware/samd_eic.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_eic.h
+ * arch/arm/src/samd2l2/hardware/samd_eic.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_EIC_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_EIC_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EIC_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EIC_H
 
 /********************************************************************************************
  * Included Files
@@ -187,4 +187,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_EIC_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EIC_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_evsys.h b/arch/arm/src/samd2l2/hardware/samd_evsys.h
similarity index 99%
rename from arch/arm/src/samd2l2/chip/samd_evsys.h
rename to arch/arm/src/samd2l2/hardware/samd_evsys.h
index 43745cc922c..50c6cdd6d47 100644
--- a/arch/arm/src/samd2l2/chip/samd_evsys.h
+++ b/arch/arm/src/samd2l2/hardware/samd_evsys.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_evsys.h
+ * arch/arm/src/samd2l2/hardware/samd_evsys.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_EVSYS_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_EVSYS_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EVSYS_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EVSYS_H
 
 /********************************************************************************************
  * Included Files
@@ -353,4 +353,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_EVSYS_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_EVSYS_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_fuses.h b/arch/arm/src/samd2l2/hardware/samd_fuses.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/samd_fuses.h
rename to arch/arm/src/samd2l2/hardware/samd_fuses.h
index 990f5f6f48b..7efe168b58c 100644
--- a/arch/arm/src/samd2l2/chip/samd_fuses.h
+++ b/arch/arm/src/samd2l2/hardware/samd_fuses.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_fuses.h
+ * arch/arm/src/samd2l2/hardware/samd_fuses.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -44,8 +44,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_FUSES_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_FUSES_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_FUSES_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_FUSES_H
 
 /********************************************************************************************
  * Included Files
@@ -295,4 +295,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_FUSES_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_FUSES_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_gclk.h b/arch/arm/src/samd2l2/hardware/samd_gclk.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/samd_gclk.h
rename to arch/arm/src/samd2l2/hardware/samd_gclk.h
index 54f957e6178..77ce4c3371d 100644
--- a/arch/arm/src/samd2l2/chip/samd_gclk.h
+++ b/arch/arm/src/samd2l2/hardware/samd_gclk.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_gclk.h
+ * arch/arm/src/samd2l2/hardware/samd_gclk.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -39,8 +39,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_GCLK_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_GCLK_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_GCLK_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_GCLK_H
 
 /********************************************************************************************
  * Included Files
@@ -256,4 +256,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_GCLK_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_GCLK_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_i2c_master.h b/arch/arm/src/samd2l2/hardware/samd_i2c_master.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/samd_i2c_master.h
rename to arch/arm/src/samd2l2/hardware/samd_i2c_master.h
index 62b5b2d8956..a3eebb8b00d 100644
--- a/arch/arm/src/samd2l2/chip/samd_i2c_master.h
+++ b/arch/arm/src/samd2l2/hardware/samd_i2c_master.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_i2c_master.h
+ * arch/arm/src/samd2l2/hardware/samd_i2c_master.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_I2C_MASTER_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_I2C_MASTER_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_MASTER_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_MASTER_H
 
 /********************************************************************************************
  * Included Files
@@ -47,7 +47,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/samd_sercom.h"
+#include "hardware/samd_sercom.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
 
@@ -338,4 +338,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_I2C_MASTER_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_MASTER_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_i2c_slave.h b/arch/arm/src/samd2l2/hardware/samd_i2c_slave.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/samd_i2c_slave.h
rename to arch/arm/src/samd2l2/hardware/samd_i2c_slave.h
index d944ff2d79d..5be25f2a1b9 100644
--- a/arch/arm/src/samd2l2/chip/samd_i2c_slave.h
+++ b/arch/arm/src/samd2l2/hardware/samd_i2c_slave.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_i2c_slave.h
+ * arch/arm/src/samd2l2/hardware/samd_i2c_slave.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_I2C_SLAVE_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_I2C_SLAVE_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_SLAVE_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_SLAVE_H
 
 /********************************************************************************************
  * Included Files
@@ -47,7 +47,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/samd_sercom.h"
+#include "hardware/samd_sercom.h"
 
 #ifdef CONFIG_ARCH_FAMILY_SAMD20
 
@@ -300,4 +300,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD20 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_I2C_SLAVE_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2C_SLAVE_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_i2s.h b/arch/arm/src/samd2l2/hardware/samd_i2s.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/samd_i2s.h
rename to arch/arm/src/samd2l2/hardware/samd_i2s.h
index 4a273612ac4..572e38faf88 100644
--- a/arch/arm/src/samd2l2/chip/samd_i2s.h
+++ b/arch/arm/src/samd2l2/hardware/samd_i2s.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_i2s.h
+ * arch/arm/src/samd2l2/hardware/samd_i2s.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Matt Thompson 
@@ -36,8 +36,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_I2S_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_I2S_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2S_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2S_H
 
 /********************************************************************************************
  * Included Files
@@ -200,4 +200,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_I2S_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_I2S_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_nvmctrl.h b/arch/arm/src/samd2l2/hardware/samd_nvmctrl.h
similarity index 97%
rename from arch/arm/src/samd2l2/chip/samd_nvmctrl.h
rename to arch/arm/src/samd2l2/hardware/samd_nvmctrl.h
index 3204074404b..88be8178161 100644
--- a/arch/arm/src/samd2l2/chip/samd_nvmctrl.h
+++ b/arch/arm/src/samd2l2/hardware/samd_nvmctrl.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_nvmctrl.h
+ * arch/arm/src/samd2l2/hardware/samd_nvmctrl.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -39,8 +39,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_NVMCTRL_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_NVMCTRL_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_NVMCTRL_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_NVMCTRL_H
 
 /********************************************************************************************
  * Included Files
@@ -184,4 +184,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_NVMCTRL_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_NVMCTRL_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_pm.h b/arch/arm/src/samd2l2/hardware/samd_pm.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/samd_pm.h
rename to arch/arm/src/samd2l2/hardware/samd_pm.h
index 71208157b43..75f4e79f3c0 100644
--- a/arch/arm/src/samd2l2/chip/samd_pm.h
+++ b/arch/arm/src/samd2l2/hardware/samd_pm.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_pm.h
+ * arch/arm/src/samd2l2/hardware/samd_pm.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -39,8 +39,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_PM_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_PM_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PM_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PM_H
 
 /********************************************************************************************
  * Included Files
@@ -261,4 +261,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_PM_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PM_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_port.h b/arch/arm/src/samd2l2/hardware/samd_port.h
similarity index 99%
rename from arch/arm/src/samd2l2/chip/samd_port.h
rename to arch/arm/src/samd2l2/hardware/samd_port.h
index 729d0ca4f31..abb771a299f 100644
--- a/arch/arm/src/samd2l2/chip/samd_port.h
+++ b/arch/arm/src/samd2l2/hardware/samd_port.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_port.h
+ * arch/arm/src/samd2l2/hardware/samd_port.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -39,8 +39,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_PORT_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_PORT_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PORT_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PORT_H
 
 /********************************************************************************************
  * Included Files
@@ -331,4 +331,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_PORT_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_PORT_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_sercom.h b/arch/arm/src/samd2l2/hardware/samd_sercom.h
similarity index 95%
rename from arch/arm/src/samd2l2/chip/samd_sercom.h
rename to arch/arm/src/samd2l2/hardware/samd_sercom.h
index 3ab4675f962..ef76104d484 100644
--- a/arch/arm/src/samd2l2/chip/samd_sercom.h
+++ b/arch/arm/src/samd2l2/hardware/samd_sercom.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_sercom.h
+ * arch/arm/src/samd2l2/hardware/samd_sercom.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_SERCOM_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_SERCOM_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SERCOM_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SERCOM_H
 
 /********************************************************************************************
  * Included Files
@@ -96,4 +96,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_SERCOM_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SERCOM_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_spi.h b/arch/arm/src/samd2l2/hardware/samd_spi.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/samd_spi.h
rename to arch/arm/src/samd2l2/hardware/samd_spi.h
index 152d099b3f7..fc3047c5008 100644
--- a/arch/arm/src/samd2l2/chip/samd_spi.h
+++ b/arch/arm/src/samd2l2/hardware/samd_spi.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_spi.h
+ * arch/arm/src/samd2l2/hardware/samd_spi.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_SPI_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_SPI_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SPI_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SPI_H
 
 /********************************************************************************************
  * Included Files
@@ -47,7 +47,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/samd_sercom.h"
+#include "hardware/samd_sercom.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
 
@@ -303,4 +303,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_SPI_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SPI_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_sysctrl.h b/arch/arm/src/samd2l2/hardware/samd_sysctrl.h
similarity index 99%
rename from arch/arm/src/samd2l2/chip/samd_sysctrl.h
rename to arch/arm/src/samd2l2/hardware/samd_sysctrl.h
index 3f29dd530b8..29b7777ea4e 100644
--- a/arch/arm/src/samd2l2/chip/samd_sysctrl.h
+++ b/arch/arm/src/samd2l2/hardware/samd_sysctrl.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_sysctrl.h
+ * arch/arm/src/samd2l2/hardware/samd_sysctrl.h
  *
  *   Copyright (C) 2014, 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -39,8 +39,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_SYSCTRL_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_SYSCTRL_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SYSCTRL_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SYSCTRL_H
 
 /********************************************************************************************
  * Included Files
@@ -432,4 +432,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_SYSCTRL_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_SYSCTRL_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_tc.h b/arch/arm/src/samd2l2/hardware/samd_tc.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/samd_tc.h
rename to arch/arm/src/samd2l2/hardware/samd_tc.h
index 5934710ab09..99aca04d4e0 100644
--- a/arch/arm/src/samd2l2/chip/samd_tc.h
+++ b/arch/arm/src/samd2l2/hardware/samd_tc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_tc.h
+ * arch/arm/src/samd2l2/hardware/samd_tc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Matt Thompson 
@@ -36,8 +36,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_TC_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_TC_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TC_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TC_H
 
 /********************************************************************************************
  * Included Files
@@ -251,4 +251,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_TC_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TC_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_tcc.h b/arch/arm/src/samd2l2/hardware/samd_tcc.h
similarity index 99%
rename from arch/arm/src/samd2l2/chip/samd_tcc.h
rename to arch/arm/src/samd2l2/hardware/samd_tcc.h
index e5b30afeb7e..7a9ebaa22f6 100644
--- a/arch/arm/src/samd2l2/chip/samd_tcc.h
+++ b/arch/arm/src/samd2l2/hardware/samd_tcc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_tcc.h
+ * arch/arm/src/samd2l2/hardware/samd_tcc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Matt Thompson 
@@ -36,8 +36,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_TCC_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_TCC_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TCC_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TCC_H
 
 /********************************************************************************************
  * Included Files
@@ -460,4 +460,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_TCC_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_TCC_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_usart.h b/arch/arm/src/samd2l2/hardware/samd_usart.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/samd_usart.h
rename to arch/arm/src/samd2l2/hardware/samd_usart.h
index ad28185c174..bdfba56578f 100644
--- a/arch/arm/src/samd2l2/chip/samd_usart.h
+++ b/arch/arm/src/samd2l2/hardware/samd_usart.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_usart.h
+ * arch/arm/src/samd2l2/hardware/samd_usart.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -39,8 +39,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_USART_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_USART_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_USART_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_USART_H
 
 /********************************************************************************************
  * Included Files
@@ -49,7 +49,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/samd_sercom.h"
+#include "hardware/samd_sercom.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
 
@@ -391,4 +391,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_USART_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAMD_USART_H */
diff --git a/arch/arm/src/samd2l2/chip/samd_wdt.h b/arch/arm/src/samd2l2/hardware/samd_wdt.h
similarity index 97%
rename from arch/arm/src/samd2l2/chip/samd_wdt.h
rename to arch/arm/src/samd2l2/hardware/samd_wdt.h
index 6173fa32f1b..bbb704423e3 100644
--- a/arch/arm/src/samd2l2/chip/samd_wdt.h
+++ b/arch/arm/src/samd2l2/hardware/samd_wdt.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd_wdt.h
+ * arch/arm/src/samd2l2/hardware/samd_wdt.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAM_WDT_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAM_WDT_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAM_WDT_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAM_WDT_H
 
 /********************************************************************************************
  * Included Files
@@ -159,4 +159,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAM_WDT_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAM_WDT_H */
diff --git a/arch/arm/src/samd2l2/chip/saml21_memorymap.h b/arch/arm/src/samd2l2/hardware/saml21_memorymap.h
similarity index 96%
rename from arch/arm/src/samd2l2/chip/saml21_memorymap.h
rename to arch/arm/src/samd2l2/hardware/saml21_memorymap.h
index 5721e9e6c6a..2aa3c2d87d4 100644
--- a/arch/arm/src/samd2l2/chip/saml21_memorymap.h
+++ b/arch/arm/src/samd2l2/hardware/saml21_memorymap.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml21_memorymap.h
+ * arch/arm/src/samd2l2/hardware/saml21_memorymap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML21_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML21_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_MEMORYMAP_H
 
 /********************************************************************************************
  * Included Files
@@ -139,4 +139,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML21_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_MEMORYMAP_H */
diff --git a/arch/arm/src/samd2l2/chip/saml21_pinmap.h b/arch/arm/src/samd2l2/hardware/saml21_pinmap.h
similarity index 99%
rename from arch/arm/src/samd2l2/chip/saml21_pinmap.h
rename to arch/arm/src/samd2l2/hardware/saml21_pinmap.h
index 63061a4cc7d..dbee0d2712c 100644
--- a/arch/arm/src/samd2l2/chip/saml21_pinmap.h
+++ b/arch/arm/src/samd2l2/hardware/saml21_pinmap.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/samd20_pinmap.h
+ * arch/arm/src/samd2l2/hardware/samd20_pinmap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML21_PINMAP_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML21_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_PINMAP_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_PINMAP_H
 
 /********************************************************************************************
  * Included Files
@@ -466,4 +466,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML21_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML21_PINMAP_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_adc.h b/arch/arm/src/samd2l2/hardware/saml_adc.h
similarity index 96%
rename from arch/arm/src/samd2l2/chip/saml_adc.h
rename to arch/arm/src/samd2l2/hardware/saml_adc.h
index e48edcfd735..48aaf7a3889 100644
--- a/arch/arm/src/samd2l2/chip/saml_adc.h
+++ b/arch/arm/src/samd2l2/hardware/saml_adc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_adc.h
+ * arch/arm/src/samd2l2/hardware/saml_adc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Alexander Vasiljev 
@@ -36,8 +36,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_ADC_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_ADC_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_ADC_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_ADC_H
 
 /********************************************************************************************
  * Included Files
@@ -103,4 +103,4 @@
 #define SAM_ADC_CALIB              (SAM_ADC_BASE + SAM_ADC_CALIB_OFFSET)
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_ADC_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_ADC_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_aes.h b/arch/arm/src/samd2l2/hardware/saml_aes.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/saml_aes.h
rename to arch/arm/src/samd2l2/hardware/saml_aes.h
index 30b3890aa5a..3b1610f6bbd 100644
--- a/arch/arm/src/samd2l2/chip/saml_aes.h
+++ b/arch/arm/src/samd2l2/hardware/saml_aes.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_aes.h
+ * arch/arm/src/samd2l2/hardware/saml_aes.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_AES_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_AES_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_AES_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_AES_H
 
 /********************************************************************************************
  * Included Files
@@ -208,4 +208,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_AES_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_AES_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_dac.h b/arch/arm/src/samd2l2/hardware/saml_dac.h
similarity index 97%
rename from arch/arm/src/samd2l2/chip/saml_dac.h
rename to arch/arm/src/samd2l2/hardware/saml_dac.h
index fcaa32c3152..4e5919f9ad8 100644
--- a/arch/arm/src/samd2l2/chip/saml_dac.h
+++ b/arch/arm/src/samd2l2/hardware/saml_dac.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_dac.h
+ * arch/arm/src/samd2l2/hardware/saml_dac.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_DAC_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_DAC_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DAC_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DAC_H
 
 /********************************************************************************************
  * Included Files
@@ -176,4 +176,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_DAC_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DAC_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_dmac.h b/arch/arm/src/samd2l2/hardware/saml_dmac.h
similarity index 99%
rename from arch/arm/src/samd2l2/chip/saml_dmac.h
rename to arch/arm/src/samd2l2/hardware/saml_dmac.h
index dab81f8e669..c747b97f532 100644
--- a/arch/arm/src/samd2l2/chip/saml_dmac.h
+++ b/arch/arm/src/samd2l2/hardware/saml_dmac.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_dmac.h
+ * arch/arm/src/samd2l2/hardware/saml_dmac.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_DMAC_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_DMAC_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DMAC_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DMAC_H
 
 /********************************************************************************************
  * Included Files
@@ -386,4 +386,4 @@ struct dma_desc_s
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_DMAC_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_DMAC_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_eic.h b/arch/arm/src/samd2l2/hardware/saml_eic.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/saml_eic.h
rename to arch/arm/src/samd2l2/hardware/saml_eic.h
index 2419f72e8c3..ec9d6f7e23b 100644
--- a/arch/arm/src/samd2l2/chip/saml_eic.h
+++ b/arch/arm/src/samd2l2/hardware/saml_eic.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_eic.h
+ * arch/arm/src/samd2l2/hardware/saml_eic.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_EIC_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_EIC_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EIC_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EIC_H
 
 /********************************************************************************************
  * Included Files
@@ -204,4 +204,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_EIC_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EIC_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_evsys.h b/arch/arm/src/samd2l2/hardware/saml_evsys.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/saml_evsys.h
rename to arch/arm/src/samd2l2/hardware/saml_evsys.h
index 49e0d55427c..896bbbbfefb 100644
--- a/arch/arm/src/samd2l2/chip/saml_evsys.h
+++ b/arch/arm/src/samd2l2/hardware/saml_evsys.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_evsys.h
+ * arch/arm/src/samd2l2/hardware/saml_evsys.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_EVSYS_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_EVSYS_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EVSYS_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EVSYS_H
 
 /********************************************************************************************
  * Included Files
@@ -257,4 +257,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_EVSYS_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_EVSYS_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_fuses.h b/arch/arm/src/samd2l2/hardware/saml_fuses.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/saml_fuses.h
rename to arch/arm/src/samd2l2/hardware/saml_fuses.h
index 2a18802b5d8..a6e7b130f79 100644
--- a/arch/arm/src/samd2l2/chip/saml_fuses.h
+++ b/arch/arm/src/samd2l2/hardware/saml_fuses.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/sam_fuses.h
+ * arch/arm/src/samd2l2/hardware/sam_fuses.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_FUSES_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_FUSES_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_FUSES_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_FUSES_H
 
 /********************************************************************************************
  * Included Files
@@ -203,4 +203,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_FUSES_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_FUSES_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_gclk.h b/arch/arm/src/samd2l2/hardware/saml_gclk.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/saml_gclk.h
rename to arch/arm/src/samd2l2/hardware/saml_gclk.h
index 37bb6c510a5..384b9280b60 100644
--- a/arch/arm/src/samd2l2/chip/saml_gclk.h
+++ b/arch/arm/src/samd2l2/hardware/saml_gclk.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_gclk.h
+ * arch/arm/src/samd2l2/hardware/saml_gclk.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_GCLK_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_GCLK_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_GCLK_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_GCLK_H
 
 /********************************************************************************************
  * Included Files
@@ -191,4 +191,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_GCLK_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_GCLK_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_i2c_master.h b/arch/arm/src/samd2l2/hardware/saml_i2c_master.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/saml_i2c_master.h
rename to arch/arm/src/samd2l2/hardware/saml_i2c_master.h
index 5a0ca665266..e841bb69c44 100644
--- a/arch/arm/src/samd2l2/chip/saml_i2c_master.h
+++ b/arch/arm/src/samd2l2/hardware/saml_i2c_master.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_i2c_master.h
+ * arch/arm/src/samd2l2/hardware/saml_i2c_master.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_I2C_MASTER_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_I2C_MASTER_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_MASTER_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_MASTER_H
 
 /********************************************************************************************
  * Included Files
@@ -47,7 +47,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/saml_sercom.h"
+#include "hardware/saml_sercom.h"
 
 #ifdef CONFIG_ARCH_FAMILY_SAML21
 
@@ -272,4 +272,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_I2C_MASTER_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_MASTER_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_i2c_slave.h b/arch/arm/src/samd2l2/hardware/saml_i2c_slave.h
similarity index 97%
rename from arch/arm/src/samd2l2/chip/saml_i2c_slave.h
rename to arch/arm/src/samd2l2/hardware/saml_i2c_slave.h
index 67554f3da07..22bf0f6655d 100644
--- a/arch/arm/src/samd2l2/chip/saml_i2c_slave.h
+++ b/arch/arm/src/samd2l2/hardware/saml_i2c_slave.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_i2c_slave.h
+ * arch/arm/src/samd2l2/hardware/saml_i2c_slave.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_I2C_SLAVE_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_I2C_SLAVE_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_SLAVE_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_SLAVE_H
 
 /********************************************************************************************
  * Included Files
@@ -47,7 +47,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/saml_sercom.h"
+#include "hardware/saml_sercom.h"
 
 #ifdef CONFIG_ARCH_FAMILY_SAML21
 
@@ -212,4 +212,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_I2C_SLAVE_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_I2C_SLAVE_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_mclk.h b/arch/arm/src/samd2l2/hardware/saml_mclk.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/saml_mclk.h
rename to arch/arm/src/samd2l2/hardware/saml_mclk.h
index 36f858282cb..c58522f69e5 100644
--- a/arch/arm/src/samd2l2/chip/saml_mclk.h
+++ b/arch/arm/src/samd2l2/hardware/saml_mclk.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_mclk.h
+ * arch/arm/src/samd2l2/hardware/saml_mclk.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_MCLK_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_MCLK_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_MCLK_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_MCLK_H
 
 /************************************************************************************
  * Included Files
@@ -213,4 +213,4 @@
  ************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_MCLK_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_MCLK_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_nvmctrl.h b/arch/arm/src/samd2l2/hardware/saml_nvmctrl.h
similarity index 97%
rename from arch/arm/src/samd2l2/chip/saml_nvmctrl.h
rename to arch/arm/src/samd2l2/hardware/saml_nvmctrl.h
index 3e6eccf962c..25d2edf7c26 100644
--- a/arch/arm/src/samd2l2/chip/saml_nvmctrl.h
+++ b/arch/arm/src/samd2l2/hardware/saml_nvmctrl.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_nvmctrl.h
+ * arch/arm/src/samd2l2/hardware/saml_nvmctrl.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_NVMCTRL_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_NVMCTRL_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_NVMCTRL_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_NVMCTRL_H
 
 /********************************************************************************************
  * Included Files
@@ -173,4 +173,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_NVMCTRL_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_NVMCTRL_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_opamp.h b/arch/arm/src/samd2l2/hardware/saml_opamp.h
similarity index 97%
rename from arch/arm/src/samd2l2/chip/saml_opamp.h
rename to arch/arm/src/samd2l2/hardware/saml_opamp.h
index a06773a958a..eb1254ec46a 100644
--- a/arch/arm/src/samd2l2/chip/saml_opamp.h
+++ b/arch/arm/src/samd2l2/hardware/saml_opamp.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_opamp.h
+ * arch/arm/src/samd2l2/hardware/saml_opamp.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_OPAMP_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_OPAMP_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OPAMP_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OPAMP_H
 
 /********************************************************************************************
  * Included Files
@@ -150,4 +150,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_OPAMP_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OPAMP_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_osc32kctrl.h b/arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h
similarity index 97%
rename from arch/arm/src/samd2l2/chip/saml_osc32kctrl.h
rename to arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h
index 16443d5e043..dba992f5ef4 100644
--- a/arch/arm/src/samd2l2/chip/saml_osc32kctrl.h
+++ b/arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_osc32kctrl.h
+ * arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_OSC32KCTRL_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_OSC32KCTRL_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OSC32KCTRL_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OSC32KCTRL_H
 
 /********************************************************************************************
  * Included Files
@@ -161,4 +161,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_OSC32KCTRL_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OSC32KCTRL_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_oscctrl.h b/arch/arm/src/samd2l2/hardware/saml_oscctrl.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/saml_oscctrl.h
rename to arch/arm/src/samd2l2/hardware/saml_oscctrl.h
index 08cb54b7f80..c37e8d43b05 100644
--- a/arch/arm/src/samd2l2/chip/saml_oscctrl.h
+++ b/arch/arm/src/samd2l2/hardware/saml_oscctrl.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_oscctrl.h
+ * arch/arm/src/samd2l2/hardware/saml_oscctrl.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_OSCCTRL_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_OSCCTRL_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OSCCTRL_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OSCCTRL_H
 
 /********************************************************************************************
  * Included Files
@@ -302,4 +302,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_OSCCTRL_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_OSCCTRL_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_pm.h b/arch/arm/src/samd2l2/hardware/saml_pm.h
similarity index 97%
rename from arch/arm/src/samd2l2/chip/saml_pm.h
rename to arch/arm/src/samd2l2/hardware/saml_pm.h
index 04a170c88de..d765e3bb7bb 100644
--- a/arch/arm/src/samd2l2/chip/saml_pm.h
+++ b/arch/arm/src/samd2l2/hardware/saml_pm.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_pm.h
+ * arch/arm/src/samd2l2/hardware/saml_pm.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_PM_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_PM_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_PM_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_PM_H
 
 /****************************************************************************************************
  * Included Files
@@ -147,4 +147,4 @@
  ****************************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_PM_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_PM_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_port.h b/arch/arm/src/samd2l2/hardware/saml_port.h
similarity index 99%
rename from arch/arm/src/samd2l2/chip/saml_port.h
rename to arch/arm/src/samd2l2/hardware/saml_port.h
index fd62b70cdc1..60b4908f57b 100644
--- a/arch/arm/src/samd2l2/chip/saml_port.h
+++ b/arch/arm/src/samd2l2/hardware/saml_port.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_port.h
+ * arch/arm/src/samd2l2/hardware/saml_port.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_PORT_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_PORT_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_PORT_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_PORT_H
 
 /********************************************************************************************
  * Included Files
@@ -451,4 +451,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_PORT_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_PORT_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_rstc.h b/arch/arm/src/samd2l2/hardware/saml_rstc.h
similarity index 97%
rename from arch/arm/src/samd2l2/chip/saml_rstc.h
rename to arch/arm/src/samd2l2/hardware/saml_rstc.h
index 5f294b874b9..7a923f0e3df 100644
--- a/arch/arm/src/samd2l2/chip/saml_rstc.h
+++ b/arch/arm/src/samd2l2/hardware/saml_rstc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_rstc.h
+ * arch/arm/src/samd2l2/hardware/saml_rstc.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_RSTC_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_RSTC_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_RSTC_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_RSTC_H
 
 /********************************************************************************************
  * Included Files
@@ -142,4 +142,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_RSTC_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_RSTC_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_sercom.h b/arch/arm/src/samd2l2/hardware/saml_sercom.h
similarity index 93%
rename from arch/arm/src/samd2l2/chip/saml_sercom.h
rename to arch/arm/src/samd2l2/hardware/saml_sercom.h
index fc9cfa327ac..d5d193d042c 100644
--- a/arch/arm/src/samd2l2/chip/saml_sercom.h
+++ b/arch/arm/src/samd2l2/hardware/saml_sercom.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_sercom.h
+ * arch/arm/src/samd2l2/hardware/saml_sercom.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_SERCOM_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_SERCOM_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SERCOM_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SERCOM_H
 
 /********************************************************************************************
  * Included Files
@@ -64,4 +64,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_SERCOM_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SERCOM_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_spi.h b/arch/arm/src/samd2l2/hardware/saml_spi.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/saml_spi.h
rename to arch/arm/src/samd2l2/hardware/saml_spi.h
index b675d8cefa7..30b0306e82e 100644
--- a/arch/arm/src/samd2l2/chip/saml_spi.h
+++ b/arch/arm/src/samd2l2/hardware/saml_spi.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_spi.h
+ * arch/arm/src/samd2l2/hardware/saml_spi.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_SPI_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_SPI_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SPI_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SPI_H
 
 /********************************************************************************************
  * Included Files
@@ -47,7 +47,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/saml_sercom.h"
+#include "hardware/saml_sercom.h"
 
 #ifdef CONFIG_ARCH_FAMILY_SAML21
 
@@ -248,4 +248,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_SPI_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SPI_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_supc.h b/arch/arm/src/samd2l2/hardware/saml_supc.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/saml_supc.h
rename to arch/arm/src/samd2l2/hardware/saml_supc.h
index e87a9f697a8..0fd6fbd3722 100644
--- a/arch/arm/src/samd2l2/chip/saml_supc.h
+++ b/arch/arm/src/samd2l2/hardware/saml_supc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_supc.h
+ * arch/arm/src/samd2l2/hardware/saml_supc.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_SUPC_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_SUPC_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SUPC_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SUPC_H
 
 /********************************************************************************************
  * Included Files
@@ -260,4 +260,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_SUPC_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_SUPC_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_trng.h b/arch/arm/src/samd2l2/hardware/saml_trng.h
similarity index 95%
rename from arch/arm/src/samd2l2/chip/saml_trng.h
rename to arch/arm/src/samd2l2/hardware/saml_trng.h
index a9e99662302..c2c09d5b4fd 100644
--- a/arch/arm/src/samd2l2/chip/saml_trng.h
+++ b/arch/arm/src/samd2l2/hardware/saml_trng.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_trng.h
+ * arch/arm/src/samd2l2/hardware/saml_trng.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_TRNG_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_TRNG_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_TRNG_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_TRNG_H
 
 /********************************************************************************************
  * Included Files
@@ -99,4 +99,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_TRNG_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_TRNG_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_usart.h b/arch/arm/src/samd2l2/hardware/saml_usart.h
similarity index 98%
rename from arch/arm/src/samd2l2/chip/saml_usart.h
rename to arch/arm/src/samd2l2/hardware/saml_usart.h
index db05661e64c..c77987f6f99 100644
--- a/arch/arm/src/samd2l2/chip/saml_usart.h
+++ b/arch/arm/src/samd2l2/hardware/saml_usart.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_usart.h
+ * arch/arm/src/samd2l2/hardware/saml_usart.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_USART_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_USART_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_USART_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_USART_H
 
 /********************************************************************************************
  * Included Files
@@ -47,7 +47,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/saml_sercom.h"
+#include "hardware/saml_sercom.h"
 
 #ifdef CONFIG_ARCH_FAMILY_SAML21
 
@@ -276,4 +276,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_USART_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_USART_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_usb.h b/arch/arm/src/samd2l2/hardware/saml_usb.h
similarity index 99%
rename from arch/arm/src/samd2l2/chip/saml_usb.h
rename to arch/arm/src/samd2l2/hardware/saml_usb.h
index 979151efc37..77639436924 100644
--- a/arch/arm/src/samd2l2/chip/saml_usb.h
+++ b/arch/arm/src/samd2l2/hardware/saml_usb.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_usb.h
+ * arch/arm/src/samd2l2/hardware/saml_usb.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -38,8 +38,8 @@
  ********************************************************************************************/
 
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_USB_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_USB_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_USB_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_USB_H
 
 /********************************************************************************************
  * Included Files
@@ -633,4 +633,4 @@ struct usbhost_pipedesc_s
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_USB_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_USB_H */
diff --git a/arch/arm/src/samd2l2/chip/saml_wdt.h b/arch/arm/src/samd2l2/hardware/saml_wdt.h
similarity index 97%
rename from arch/arm/src/samd2l2/chip/saml_wdt.h
rename to arch/arm/src/samd2l2/hardware/saml_wdt.h
index c8a3c075dc8..9ec3bb9714b 100644
--- a/arch/arm/src/samd2l2/chip/saml_wdt.h
+++ b/arch/arm/src/samd2l2/hardware/saml_wdt.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd2l2/chip/saml_wdt.h
+ * arch/arm/src/samd2l2/hardware/saml_wdt.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_WDT_H
-#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_WDT_H
+#ifndef __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_WDT_H
+#define __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_WDT_H
 
 /********************************************************************************************
  * Included Files
@@ -162,4 +162,4 @@
  ********************************************************************************************/
 
 #endif /* CONFIG_ARCH_FAMILY_SAML21 */
-#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_WDT_H */
+#endif /* __ARCH_ARM_SRC_SAMD2L2_HARDWARE_SAML_WDT_H */
diff --git a/arch/arm/src/samd2l2/sam_ac.h b/arch/arm/src/samd2l2/sam_ac.h
index 4ff28952496..96793bb3581 100644
--- a/arch/arm/src/samd2l2/sam_ac.h
+++ b/arch/arm/src/samd2l2/sam_ac.h
@@ -49,9 +49,9 @@
 #include "sam_port.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd_ac.h"
+#  include "hardware/samd_ac.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml_ac.h"
+#  include "hardware/saml_ac.h"
 #else
 #  error Unrecognized SAMD/L architecture
 #endif
diff --git a/arch/arm/src/samd2l2/sam_adc.h b/arch/arm/src/samd2l2/sam_adc.h
index 4d1c0c121a1..68ab6d2020e 100644
--- a/arch/arm/src/samd2l2/sam_adc.h
+++ b/arch/arm/src/samd2l2/sam_adc.h
@@ -49,9 +49,9 @@
 #include "sam_port.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd_adc.h"
+#  include "hardware/samd_adc.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml_adc.h"
+#  include "hardware/saml_adc.h"
 #else
 #  error Unrecognized SAMD/L architecture
 #endif
diff --git a/arch/arm/src/samd2l2/sam_dac.h b/arch/arm/src/samd2l2/sam_dac.h
index 981b5777e47..be4c76e082c 100644
--- a/arch/arm/src/samd2l2/sam_dac.h
+++ b/arch/arm/src/samd2l2/sam_dac.h
@@ -49,9 +49,9 @@
 #include "sam_port.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd_dac.h"
+#  include "hardware/samd_dac.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml_dac.h"
+#  include "hardware/saml_dac.h"
 #else
 #  error Unrecognized SAMD/L architecture
 #endif
diff --git a/arch/arm/src/samd2l2/sam_dmac.h b/arch/arm/src/samd2l2/sam_dmac.h
index 49eea2a9768..985a6f94a97 100644
--- a/arch/arm/src/samd2l2/sam_dmac.h
+++ b/arch/arm/src/samd2l2/sam_dmac.h
@@ -46,14 +46,14 @@
 
 #include "chip.h"
 
-#include "chip/sam_dmac.h"
+#include "hardware/sam_dmac.h"
 
 #ifdef CONFIG_SAMD2L2_DMAC
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd_dmac.h"
+#  include "hardware/samd_dmac.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml_dmac.h"
+#  include "hardware/saml_dmac.h"
 #else
 #  error Unrecognized SAMD/L architecture
 #endif
diff --git a/arch/arm/src/samd2l2/sam_eic.h b/arch/arm/src/samd2l2/sam_eic.h
index 4b732287b90..d1cffca0828 100644
--- a/arch/arm/src/samd2l2/sam_eic.h
+++ b/arch/arm/src/samd2l2/sam_eic.h
@@ -49,9 +49,9 @@
 #include "sam_port.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd_eic.h"
+#  include "hardware/samd_eic.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml_eic.h"
+#  include "hardware/saml_eic.h"
 #else
 #  error Unrecognized SAMD/L architecture
 #endif
diff --git a/arch/arm/src/samd2l2/sam_evsys.h b/arch/arm/src/samd2l2/sam_evsys.h
index 17f6836e164..eee072ce36c 100644
--- a/arch/arm/src/samd2l2/sam_evsys.h
+++ b/arch/arm/src/samd2l2/sam_evsys.h
@@ -49,9 +49,9 @@
 #include "sam_port.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd_evsys.h"
+#  include "hardware/samd_evsys.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml_evsys.h"
+#  include "hardware/saml_evsys.h"
 #else
 #  error Unrecognized SAMD/L architecture
 #endif
diff --git a/arch/arm/src/samd2l2/sam_fuses.h b/arch/arm/src/samd2l2/sam_fuses.h
index 69b6fa6d5a2..327068cdcfb 100644
--- a/arch/arm/src/samd2l2/sam_fuses.h
+++ b/arch/arm/src/samd2l2/sam_fuses.h
@@ -45,9 +45,9 @@
 #include "sam_config.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd_fuses.h"
+#  include "hardware/samd_fuses.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml_fuses.h"
+#  include "hardware/saml_fuses.h"
 #else
 #  error Unrecognized SAMD/L architecture
 #endif
diff --git a/arch/arm/src/samd2l2/sam_gclk.h b/arch/arm/src/samd2l2/sam_gclk.h
index 25e0d11c6e1..6fffa73572c 100644
--- a/arch/arm/src/samd2l2/sam_gclk.h
+++ b/arch/arm/src/samd2l2/sam_gclk.h
@@ -48,9 +48,9 @@
 #include "sam_config.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd_gclk.h"
+#  include "hardware/samd_gclk.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml_gclk.h"
+#  include "hardware/saml_gclk.h"
 #else
 #  error Unrecognized SAMD/L architecture
 #endif
diff --git a/arch/arm/src/samd2l2/sam_i2c_master.h b/arch/arm/src/samd2l2/sam_i2c_master.h
index 8831f0adfc7..76637a84bbd 100644
--- a/arch/arm/src/samd2l2/sam_i2c_master.h
+++ b/arch/arm/src/samd2l2/sam_i2c_master.h
@@ -45,9 +45,9 @@
 #include "sam_config.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd_i2c_master.h"
+#  include "hardware/samd_i2c_master.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml_i2c_master.h"
+#  include "hardware/saml_i2c_master.h"
 #endif
 
 /****************************************************************************
diff --git a/arch/arm/src/samd2l2/sam_i2c_slave.h b/arch/arm/src/samd2l2/sam_i2c_slave.h
index a4d2d427733..c1574305f01 100644
--- a/arch/arm/src/samd2l2/sam_i2c_slave.h
+++ b/arch/arm/src/samd2l2/sam_i2c_slave.h
@@ -45,9 +45,9 @@
 #include "sam_config.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd_i2c_slave.h"
+#  include "hardware/samd_i2c_slave.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml_i2c_slave.h"
+#  include "hardware/saml_i2c_slave.h"
 #endif
 
 /****************************************************************************
diff --git a/arch/arm/src/samd2l2/sam_pinmap.h b/arch/arm/src/samd2l2/sam_pinmap.h
index b9d380e9ccb..819b5fa36de 100644
--- a/arch/arm/src/samd2l2/sam_pinmap.h
+++ b/arch/arm/src/samd2l2/sam_pinmap.h
@@ -43,11 +43,11 @@
 #include 
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20)
-#  include "chip/samd20_pinmap.h"
+#  include "hardware/samd20_pinmap.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd21_pinmap.h"
+#  include "hardware/samd21_pinmap.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml21_pinmap.h"
+#  include "hardware/saml21_pinmap.h"
 #else
 #  error Unrecognized SAMD/L architecture
 #endif
diff --git a/arch/arm/src/samd2l2/sam_pm.h b/arch/arm/src/samd2l2/sam_pm.h
index 829318c07af..dd3a29e8611 100644
--- a/arch/arm/src/samd2l2/sam_pm.h
+++ b/arch/arm/src/samd2l2/sam_pm.h
@@ -45,9 +45,9 @@
 #include "sam_config.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd_pm.h"
+#  include "hardware/samd_pm.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml_pm.h"
+#  include "hardware/saml_pm.h"
 #endif
 
 /****************************************************************************
diff --git a/arch/arm/src/samd2l2/sam_port.h b/arch/arm/src/samd2l2/sam_port.h
index 2510b8c52da..defc45c16a1 100644
--- a/arch/arm/src/samd2l2/sam_port.h
+++ b/arch/arm/src/samd2l2/sam_port.h
@@ -52,9 +52,9 @@
 #include "chip.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd_port.h"
+#  include "hardware/samd_port.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml_port.h"
+#  include "hardware/saml_port.h"
 #else
 #  error Unrecognized SAMD/L architecture
 #endif
diff --git a/arch/arm/src/samd2l2/sam_sercom.h b/arch/arm/src/samd2l2/sam_sercom.h
index 24fefa2e17e..01ae4d94ba7 100644
--- a/arch/arm/src/samd2l2/sam_sercom.h
+++ b/arch/arm/src/samd2l2/sam_sercom.h
@@ -49,9 +49,9 @@
 #include "sam_periphclks.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd_sercom.h"
+#  include "hardware/samd_sercom.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml_sercom.h"
+#  include "hardware/saml_sercom.h"
 #else
 #  error Unrecognized SAMD/L architecture
 #endif
diff --git a/arch/arm/src/samd2l2/sam_spi.h b/arch/arm/src/samd2l2/sam_spi.h
index 9a19bd7c5ae..3af38668fe8 100644
--- a/arch/arm/src/samd2l2/sam_spi.h
+++ b/arch/arm/src/samd2l2/sam_spi.h
@@ -48,9 +48,9 @@
 #include "sam_config.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd_spi.h"
+#  include "hardware/samd_spi.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml_spi.h"
+#  include "hardware/saml_spi.h"
 #endif
 
 #ifdef SAMD2L2_HAVE_SPI
diff --git a/arch/arm/src/samd2l2/sam_usart.h b/arch/arm/src/samd2l2/sam_usart.h
index 71dc436d8a4..ebabab88ba8 100644
--- a/arch/arm/src/samd2l2/sam_usart.h
+++ b/arch/arm/src/samd2l2/sam_usart.h
@@ -50,9 +50,9 @@
 #include "up_arch.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
-#  include "chip/samd_usart.h"
+#  include "hardware/samd_usart.h"
 #elif defined(CONFIG_ARCH_FAMILY_SAML21)
-#  include "chip/saml_usart.h"
+#  include "hardware/saml_usart.h"
 #endif
 
 #include "sam_config.h"
diff --git a/arch/arm/src/samd2l2/sam_usb.h b/arch/arm/src/samd2l2/sam_usb.h
index c6c54c33d2b..9fdc48809f9 100644
--- a/arch/arm/src/samd2l2/sam_usb.h
+++ b/arch/arm/src/samd2l2/sam_usb.h
@@ -50,7 +50,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/saml_usb.h"
+#include "hardware/saml_usb.h"
 
 /*****************************************************************************
  * Public Function Prototypes
diff --git a/arch/arm/src/samd2l2/samd_clockconfig.c b/arch/arm/src/samd2l2/samd_clockconfig.c
index c6607dc1c77..3056334f7e3 100644
--- a/arch/arm/src/samd2l2/samd_clockconfig.c
+++ b/arch/arm/src/samd2l2/samd_clockconfig.c
@@ -56,10 +56,10 @@
 
 #include "up_arch.h"
 
-#include "chip/samd_pm.h"
-#include "chip/samd_sysctrl.h"
-#include "chip/samd_gclk.h"
-#include "chip/samd_nvmctrl.h"
+#include "hardware/samd_pm.h"
+#include "hardware/samd_sysctrl.h"
+#include "hardware/samd_gclk.h"
+#include "hardware/samd_nvmctrl.h"
 #include "sam_fuses.h"
 #include "sam_gclk.h"
 
diff --git a/arch/arm/src/samd2l2/samd_periphclks.h b/arch/arm/src/samd2l2/samd_periphclks.h
index 6faefbb6135..69226e0d332 100644
--- a/arch/arm/src/samd2l2/samd_periphclks.h
+++ b/arch/arm/src/samd2l2/samd_periphclks.h
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/samd_pm.h"
+#include "hardware/samd_pm.h"
 
 #if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
 
diff --git a/arch/arm/src/samd2l2/saml_clockconfig.c b/arch/arm/src/samd2l2/saml_clockconfig.c
index c75521ebd78..2d26c7c53c9 100644
--- a/arch/arm/src/samd2l2/saml_clockconfig.c
+++ b/arch/arm/src/samd2l2/saml_clockconfig.c
@@ -56,12 +56,12 @@
 
 #include "up_arch.h"
 
-#include "chip/saml_pm.h"
-#include "chip/saml_supc.h"
-#include "chip/saml_oscctrl.h"
-#include "chip/saml_osc32kctrl.h"
-#include "chip/saml_gclk.h"
-#include "chip/saml_nvmctrl.h"
+#include "hardware/saml_pm.h"
+#include "hardware/saml_supc.h"
+#include "hardware/saml_oscctrl.h"
+#include "hardware/saml_osc32kctrl.h"
+#include "hardware/saml_gclk.h"
+#include "hardware/saml_nvmctrl.h"
 #include "sam_gclk.h"
 
 #include 
diff --git a/arch/arm/src/samd2l2/saml_periphclks.h b/arch/arm/src/samd2l2/saml_periphclks.h
index 3e223305719..62b9aace1ee 100644
--- a/arch/arm/src/samd2l2/saml_periphclks.h
+++ b/arch/arm/src/samd2l2/saml_periphclks.h
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/saml_mclk.h"
+#include "hardware/saml_mclk.h"
 
 #ifdef CONFIG_ARCH_FAMILY_SAML21
 
diff --git a/arch/arm/src/samd5e5/Make.defs b/arch/arm/src/samd5e5/Make.defs
index c5313ccc5f6..40d9654f7a3 100644
--- a/arch/arm/src/samd5e5/Make.defs
+++ b/arch/arm/src/samd5e5/Make.defs
@@ -69,11 +69,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_ARCH_FPU),y)
 CMN_ASRCS += up_fpu.S
diff --git a/arch/arm/src/samd5e5/chip/sam_aes.h b/arch/arm/src/samd5e5/hardware/sam_aes.h
similarity index 98%
rename from arch/arm/src/samd5e5/chip/sam_aes.h
rename to arch/arm/src/samd5e5/hardware/sam_aes.h
index c6bab955b88..fc087e57144 100644
--- a/arch/arm/src/samd5e5/chip/sam_aes.h
+++ b/arch/arm/src/samd5e5/hardware/sam_aes.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_aes.h
+ * arch/arm/src/samd5e5/hardware/sam_aes.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_AES_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_AES_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_AES_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_AES_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -208,4 +208,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_AES_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_AES_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_cmcc.h b/arch/arm/src/samd5e5/hardware/sam_cmcc.h
similarity index 97%
rename from arch/arm/src/samd5e5/chip/sam_cmcc.h
rename to arch/arm/src/samd5e5/hardware/sam_cmcc.h
index ce8b53421ca..f1fe5a9fbfd 100644
--- a/arch/arm/src/samd5e5/chip/sam_cmcc.h
+++ b/arch/arm/src/samd5e5/hardware/sam_cmcc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_cmcc.h
+ * arch/arm/src/samd5e5/hardware/sam_cmcc.h
  * Cortex M Cache Controller (CMCC) for the SAMD5/E5
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_CMCC_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_CMCC_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_CMCC_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_CMCC_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -193,4 +193,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_CMCC_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_CMCC_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_dmac.h b/arch/arm/src/samd5e5/hardware/sam_dmac.h
similarity index 99%
rename from arch/arm/src/samd5e5/chip/sam_dmac.h
rename to arch/arm/src/samd5e5/hardware/sam_dmac.h
index 50e8f96cc14..763b0e1c4f7 100644
--- a/arch/arm/src/samd5e5/chip/sam_dmac.h
+++ b/arch/arm/src/samd5e5/hardware/sam_dmac.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_dmac.h
+ * arch/arm/src/samd5e5/hardware/sam_dmac.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_DMAC_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_DMAC_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_DMAC_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_DMAC_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -471,4 +471,4 @@ struct dma_desc_s
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_DMAC_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_DMAC_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_eic.h b/arch/arm/src/samd5e5/hardware/sam_eic.h
similarity index 98%
rename from arch/arm/src/samd5e5/chip/sam_eic.h
rename to arch/arm/src/samd5e5/hardware/sam_eic.h
index 5fce8fb2250..52fcbda0c48 100644
--- a/arch/arm/src/samd5e5/chip/sam_eic.h
+++ b/arch/arm/src/samd5e5/hardware/sam_eic.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_eic.h
+ * arch/arm/src/samd5e5/hardware/sam_eic.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_EIC_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_EIC_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_EIC_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_EIC_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -252,4 +252,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_EIC_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_EIC_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_evsys.h b/arch/arm/src/samd5e5/hardware/sam_evsys.h
similarity index 98%
rename from arch/arm/src/samd5e5/chip/sam_evsys.h
rename to arch/arm/src/samd5e5/hardware/sam_evsys.h
index f03691eec8a..ee7f513b1d6 100644
--- a/arch/arm/src/samd5e5/chip/sam_evsys.h
+++ b/arch/arm/src/samd5e5/hardware/sam_evsys.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_evsys.h
+ * arch/arm/src/samd5e5/hardware/sam_evsys.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_EVSYS_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_EVSYS_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_EVSYS_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_EVSYS_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -366,4 +366,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_EVSYS_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_EVSYS_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_fuses.h b/arch/arm/src/samd5e5/hardware/sam_fuses.h
similarity index 98%
rename from arch/arm/src/samd5e5/chip/sam_fuses.h
rename to arch/arm/src/samd5e5/hardware/sam_fuses.h
index eb3843e7f82..091daa27292 100644
--- a/arch/arm/src/samd5e5/chip/sam_fuses.h
+++ b/arch/arm/src/samd5e5/hardware/sam_fuses.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_fuses.h
+ * arch/arm/src/samd5e5/hardware/sam_fuses.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_FUSES_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_FUSES_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_FUSES_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_FUSES_H
 
 /********************************************************************************************
  * Included Files
@@ -273,4 +273,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_FUSES_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_FUSES_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_gclk.h b/arch/arm/src/samd5e5/hardware/sam_gclk.h
similarity index 98%
rename from arch/arm/src/samd5e5/chip/sam_gclk.h
rename to arch/arm/src/samd5e5/hardware/sam_gclk.h
index 1773fb20ade..e1a32fad4db 100644
--- a/arch/arm/src/samd5e5/chip/sam_gclk.h
+++ b/arch/arm/src/samd5e5/hardware/sam_gclk.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_gclk.h
+ * arch/arm/src/samd5e5/hardware/sam_gclk.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_GCLK_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_GCLK_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_GCLK_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_GCLK_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -220,4 +220,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_GCLK_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_GCLK_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_i2c_master.h b/arch/arm/src/samd5e5/hardware/sam_i2c_master.h
similarity index 98%
rename from arch/arm/src/samd5e5/chip/sam_i2c_master.h
rename to arch/arm/src/samd5e5/hardware/sam_i2c_master.h
index e03bca43e2b..8298f5fe415 100644
--- a/arch/arm/src/samd5e5/chip/sam_i2c_master.h
+++ b/arch/arm/src/samd5e5/hardware/sam_i2c_master.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_i2c_master.h
+ * arch/arm/src/samd5e5/hardware/sam_i2c_master.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_I2C_MASTER_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_I2C_MASTER_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_I2C_MASTER_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_I2C_MASTER_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -304,4 +304,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_I2C_MASTER_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_I2C_MASTER_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_i2c_slave.h b/arch/arm/src/samd5e5/hardware/sam_i2c_slave.h
similarity index 98%
rename from arch/arm/src/samd5e5/chip/sam_i2c_slave.h
rename to arch/arm/src/samd5e5/hardware/sam_i2c_slave.h
index 5066df85f31..2d968f41df2 100644
--- a/arch/arm/src/samd5e5/chip/sam_i2c_slave.h
+++ b/arch/arm/src/samd5e5/hardware/sam_i2c_slave.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_i2c_slave.h
+ * arch/arm/src/samd5e5/hardware/sam_i2c_slave.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_I2C_SLAVE_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_I2C_SLAVE_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_I2C_SLAVE_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_I2C_SLAVE_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -280,4 +280,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_I2C_SLAVE_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_I2C_SLAVE_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_mclk.h b/arch/arm/src/samd5e5/hardware/sam_mclk.h
similarity index 98%
rename from arch/arm/src/samd5e5/chip/sam_mclk.h
rename to arch/arm/src/samd5e5/hardware/sam_mclk.h
index 0000f249b91..6f3eca6c0e2 100644
--- a/arch/arm/src/samd5e5/chip/sam_mclk.h
+++ b/arch/arm/src/samd5e5/hardware/sam_mclk.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_mclk.h
+ * arch/arm/src/samd5e5/hardware/sam_mclk.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MCLK_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MCLK_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MCLK_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MCLK_H
 
 /************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -202,4 +202,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MCLK_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MCLK_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_memorymap.h b/arch/arm/src/samd5e5/hardware/sam_memorymap.h
similarity index 88%
rename from arch/arm/src/samd5e5/chip/sam_memorymap.h
rename to arch/arm/src/samd5e5/hardware/sam_memorymap.h
index ef034711f01..ef08130b633 100644
--- a/arch/arm/src/samd5e5/chip/sam_memorymap.h
+++ b/arch/arm/src/samd5e5/hardware/sam_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_memorymap.h
+ * arch/arm/src/samd5e5/hardware/sam_memorymap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -43,10 +43,10 @@
 #include 
 
 #if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
-#  include "chip/samd5e5_memorymap.h"
+#  include "hardware/samd5e5_memorymap.h"
 #else
 #  error "Unsupported SAMD5/E5 family"
 #endif
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_MEMORYMAP_H */
 
diff --git a/arch/arm/src/samd5e5/chip/sam_nvmctrl.h b/arch/arm/src/samd5e5/hardware/sam_nvmctrl.h
similarity index 98%
rename from arch/arm/src/samd5e5/chip/sam_nvmctrl.h
rename to arch/arm/src/samd5e5/hardware/sam_nvmctrl.h
index f526bc152a7..1d3ab602d44 100644
--- a/arch/arm/src/samd5e5/chip/sam_nvmctrl.h
+++ b/arch/arm/src/samd5e5/hardware/sam_nvmctrl.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_nvmctrl.h
+ * arch/arm/src/samd5e5/hardware/sam_nvmctrl.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_NVMCTRL_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_NVMCTRL_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_NVMCTRL_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_NVMCTRL_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -250,4 +250,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_NVMCTRL_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_NVMCTRL_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_osc32kctrl.h b/arch/arm/src/samd5e5/hardware/sam_osc32kctrl.h
similarity index 97%
rename from arch/arm/src/samd5e5/chip/sam_osc32kctrl.h
rename to arch/arm/src/samd5e5/hardware/sam_osc32kctrl.h
index 2ae23569cbc..263dc4910b1 100644
--- a/arch/arm/src/samd5e5/chip/sam_osc32kctrl.h
+++ b/arch/arm/src/samd5e5/hardware/sam_osc32kctrl.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_osc32kctrl.h
+ * arch/arm/src/samd5e5/hardware/sam_osc32kctrl.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_OSC32KCTRL_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_OSC32KCTRL_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_OSC32KCTRL_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_OSC32KCTRL_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -149,4 +149,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_OSC32KCTRL_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_OSC32KCTRL_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_oscctrl.h b/arch/arm/src/samd5e5/hardware/sam_oscctrl.h
similarity index 98%
rename from arch/arm/src/samd5e5/chip/sam_oscctrl.h
rename to arch/arm/src/samd5e5/hardware/sam_oscctrl.h
index e975dcb13b5..9528608eea5 100644
--- a/arch/arm/src/samd5e5/chip/sam_oscctrl.h
+++ b/arch/arm/src/samd5e5/hardware/sam_oscctrl.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_oscctrl.h
+ * arch/arm/src/samd5e5/hardware/sam_oscctrl.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_OSCCTRL_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_OSCCTRL_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_OSCCTRL_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_OSCCTRL_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -329,4 +329,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_OSCCTRL_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_OSCCTRL_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_pac.h b/arch/arm/src/samd5e5/hardware/sam_pac.h
similarity index 98%
rename from arch/arm/src/samd5e5/chip/sam_pac.h
rename to arch/arm/src/samd5e5/hardware/sam_pac.h
index cb76c78428b..1985ef427f7 100644
--- a/arch/arm/src/samd5e5/chip/sam_pac.h
+++ b/arch/arm/src/samd5e5/hardware/sam_pac.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_pac.h
+ * arch/arm/src/samd5e5/hardware/sam_pac.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PAC_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PAC_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PAC_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PAC_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -265,4 +265,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PAC_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PAC_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_pinmap.h b/arch/arm/src/samd5e5/hardware/sam_pinmap.h
similarity index 89%
rename from arch/arm/src/samd5e5/chip/sam_pinmap.h
rename to arch/arm/src/samd5e5/hardware/sam_pinmap.h
index 7bdc469634f..ac72745021c 100644
--- a/arch/arm/src/samd5e5/chip/sam_pinmap.h
+++ b/arch/arm/src/samd5e5/hardware/sam_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_memorymap.h
+ * arch/arm/src/samd5e5/hardware/sam_memorymap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PINMAP_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PINMAP_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -43,9 +43,9 @@
 #include 
 
 #if defined(CONFIG_ARCH_CHIP_SAMD5X) || defined(ARCH_CHIP_SAME5X)
-#  include "chip/samd5e5_pinmap.h"
+#  include "hardware/samd5e5_pinmap.h"
 #else
 #  error "Unsupported SAMD5/E5 family"
 #endif
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PINMAP_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_pm.h b/arch/arm/src/samd5e5/hardware/sam_pm.h
similarity index 97%
rename from arch/arm/src/samd5e5/chip/sam_pm.h
rename to arch/arm/src/samd5e5/hardware/sam_pm.h
index f229565fd1a..d1963b47891 100644
--- a/arch/arm/src/samd5e5/chip/sam_pm.h
+++ b/arch/arm/src/samd5e5/hardware/sam_pm.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_pm.h
+ * arch/arm/src/samd5e5/hardware/sam_pm.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PM_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PM_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PM_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PM_H
 
 /****************************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -144,4 +144,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PM_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PM_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_port.h b/arch/arm/src/samd5e5/hardware/sam_port.h
similarity index 99%
rename from arch/arm/src/samd5e5/chip/sam_port.h
rename to arch/arm/src/samd5e5/hardware/sam_port.h
index 4b684c6eae2..664fe02e15a 100644
--- a/arch/arm/src/samd5e5/chip/sam_port.h
+++ b/arch/arm/src/samd5e5/hardware/sam_port.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_port.h
+ * arch/arm/src/samd5e5/hardware/sam_port.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PORT_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PORT_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PORT_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PORT_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -523,4 +523,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_PORT_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_PORT_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_rstc.h b/arch/arm/src/samd5e5/hardware/sam_rstc.h
similarity index 94%
rename from arch/arm/src/samd5e5/chip/sam_rstc.h
rename to arch/arm/src/samd5e5/hardware/sam_rstc.h
index e984c3c4eda..0be89ceb846 100644
--- a/arch/arm/src/samd5e5/chip/sam_rstc.h
+++ b/arch/arm/src/samd5e5/hardware/sam_rstc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_rstc.h
+ * arch/arm/src/samd5e5/hardware/sam_rstc.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_RSTC_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_RSTC_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_RSTC_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_RSTC_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -88,4 +88,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_RSTC_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_RSTC_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_spi.h b/arch/arm/src/samd5e5/hardware/sam_spi.h
similarity index 98%
rename from arch/arm/src/samd5e5/chip/sam_spi.h
rename to arch/arm/src/samd5e5/hardware/sam_spi.h
index fe5ff0287ed..bd712062127 100644
--- a/arch/arm/src/samd5e5/chip/sam_spi.h
+++ b/arch/arm/src/samd5e5/hardware/sam_spi.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_spi.h
+ * arch/arm/src/samd5e5/hardware/sam_spi.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_SPI_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_SPI_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_SPI_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_SPI_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -302,4 +302,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_SPI_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_SPI_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_supc.h b/arch/arm/src/samd5e5/hardware/sam_supc.h
similarity index 98%
rename from arch/arm/src/samd5e5/chip/sam_supc.h
rename to arch/arm/src/samd5e5/hardware/sam_supc.h
index fda43b75f00..a47c2d707c9 100644
--- a/arch/arm/src/samd5e5/chip/sam_supc.h
+++ b/arch/arm/src/samd5e5/hardware/sam_supc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_supc.h
+ * arch/arm/src/samd5e5/hardware/sam_supc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_SUPC_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_SUPC_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_SUPC_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_SUPC_H
 
 /********************************************************************************************
  * Included Files
@@ -228,4 +228,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_SUPC_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_SUPC_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_trng.h b/arch/arm/src/samd5e5/hardware/sam_trng.h
similarity index 94%
rename from arch/arm/src/samd5e5/chip/sam_trng.h
rename to arch/arm/src/samd5e5/hardware/sam_trng.h
index b3b7d8a5289..71cff01fd24 100644
--- a/arch/arm/src/samd5e5/chip/sam_trng.h
+++ b/arch/arm/src/samd5e5/hardware/sam_trng.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_trng.h
+ * arch/arm/src/samd5e5/hardware/sam_trng.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_TRNG_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_TRNG_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_TRNG_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_TRNG_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -93,4 +93,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_TRNG_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_TRNG_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_usart.h b/arch/arm/src/samd5e5/hardware/sam_usart.h
similarity index 99%
rename from arch/arm/src/samd5e5/chip/sam_usart.h
rename to arch/arm/src/samd5e5/hardware/sam_usart.h
index ca82859366a..981dc7b4c08 100644
--- a/arch/arm/src/samd5e5/chip/sam_usart.h
+++ b/arch/arm/src/samd5e5/hardware/sam_usart.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_usart.h
+ * arch/arm/src/samd5e5/hardware/sam_usart.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_USART_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_USART_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_USART_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_USART_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -388,4 +388,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_USART_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_USART_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_usb.h b/arch/arm/src/samd5e5/hardware/sam_usb.h
similarity index 99%
rename from arch/arm/src/samd5e5/chip/sam_usb.h
rename to arch/arm/src/samd5e5/hardware/sam_usb.h
index a64a1ff1f89..5c100e34f08 100644
--- a/arch/arm/src/samd5e5/chip/sam_usb.h
+++ b/arch/arm/src/samd5e5/hardware/sam_usb.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_usb.h
+ * arch/arm/src/samd5e5/hardware/sam_usb.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  ********************************************************************************************/
 
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_USB_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_USB_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_USB_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_USB_H
 
 /********************************************************************************************
  * Included Files
@@ -630,4 +630,4 @@ struct usbhost_pipedesc_s
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_USB_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_USB_H */
diff --git a/arch/arm/src/samd5e5/chip/sam_wdt.h b/arch/arm/src/samd5e5/hardware/sam_wdt.h
similarity index 97%
rename from arch/arm/src/samd5e5/chip/sam_wdt.h
rename to arch/arm/src/samd5e5/hardware/sam_wdt.h
index 443aa160f18..53e2afd03fd 100644
--- a/arch/arm/src/samd5e5/chip/sam_wdt.h
+++ b/arch/arm/src/samd5e5/hardware/sam_wdt.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/sam_wdt.h
+ * arch/arm/src/samd5e5/hardware/sam_wdt.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_WDT_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_WDT_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_WDT_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_WDT_H
 
 /********************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -157,4 +157,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAM_WDT_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAM_WDT_H */
diff --git a/arch/arm/src/samd5e5/chip/samd5e5_memorymap.h b/arch/arm/src/samd5e5/hardware/samd5e5_memorymap.h
similarity index 97%
rename from arch/arm/src/samd5e5/chip/samd5e5_memorymap.h
rename to arch/arm/src/samd5e5/hardware/samd5e5_memorymap.h
index 992a1901773..28d4ed6460a 100644
--- a/arch/arm/src/samd5e5/chip/samd5e5_memorymap.h
+++ b/arch/arm/src/samd5e5/hardware/samd5e5_memorymap.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/samd5e5_memorymap.h
+ * arch/arm/src/samd5e5/hardware/samd5e5_memorymap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAMD5E5_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAMD5E5_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAMD5E5_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAMD5E5_MEMORYMAP_H
 
 /********************************************************************************************
  * Included Files
@@ -163,4 +163,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAMD5E5_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAMD5E5_MEMORYMAP_H */
diff --git a/arch/arm/src/samd5e5/chip/samd5e5_pinmap.h b/arch/arm/src/samd5e5/hardware/samd5e5_pinmap.h
similarity index 99%
rename from arch/arm/src/samd5e5/chip/samd5e5_pinmap.h
rename to arch/arm/src/samd5e5/hardware/samd5e5_pinmap.h
index f4d75df4517..59133ffccc5 100644
--- a/arch/arm/src/samd5e5/chip/samd5e5_pinmap.h
+++ b/arch/arm/src/samd5e5/hardware/samd5e5_pinmap.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samd5e5/chip/samd5e5_pinmap.h
+ * arch/arm/src/samd5e5/hardware/samd5e5_pinmap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMD5E5_CHIP_SAMD5E5_PINMAP_H
-#define __ARCH_ARM_SRC_SAMD5E5_CHIP_SAMD5E5_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAMD5E5_PINMAP_H
+#define __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAMD5E5_PINMAP_H
 
 /********************************************************************************************
  * Included Files
@@ -787,4 +787,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMD5E5_CHIP_SAMD5E5_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMD5E5_HARDWARE_SAMD5E5_PINMAP_H */
diff --git a/arch/arm/src/samd5e5/sam_clockconfig.c b/arch/arm/src/samd5e5/sam_clockconfig.c
index 9704758e03b..716d745f155 100644
--- a/arch/arm/src/samd5e5/sam_clockconfig.c
+++ b/arch/arm/src/samd5e5/sam_clockconfig.c
@@ -45,12 +45,12 @@
 
 #include "up_arch.h"
 
-#include "chip/sam_pm.h"
-#include "chip/sam_supc.h"
-#include "chip/sam_oscctrl.h"
-#include "chip/sam_osc32kctrl.h"
-#include "chip/sam_gclk.h"
-#include "chip/sam_nvmctrl.h"
+#include "hardware/sam_pm.h"
+#include "hardware/sam_supc.h"
+#include "hardware/sam_oscctrl.h"
+#include "hardware/sam_osc32kctrl.h"
+#include "hardware/sam_gclk.h"
+#include "hardware/sam_nvmctrl.h"
 #include "sam_gclk.h"
 
 #include "sam_periphclks.h"
diff --git a/arch/arm/src/samd5e5/sam_cmcc.c b/arch/arm/src/samd5e5/sam_cmcc.c
index 182a237c8a4..747c0d0bdde 100644
--- a/arch/arm/src/samd5e5/sam_cmcc.c
+++ b/arch/arm/src/samd5e5/sam_cmcc.c
@@ -44,7 +44,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/sam_cmcc.h"
+#include "hardware/sam_cmcc.h"
 #include "sam_cmcc.h"
 
 #ifdef CONFIG_SAMD5E5_CMCC
diff --git a/arch/arm/src/samd5e5/sam_dmac.h b/arch/arm/src/samd5e5/sam_dmac.h
index 64b60b8e879..2feebc96ff5 100644
--- a/arch/arm/src/samd5e5/sam_dmac.h
+++ b/arch/arm/src/samd5e5/sam_dmac.h
@@ -44,7 +44,7 @@
 
 #include 
 
-#include "chip/sam_dmac.h"
+#include "hardware/sam_dmac.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/samd5e5/sam_eic.h b/arch/arm/src/samd5e5/sam_eic.h
index 54084fa0df6..6b32abd40b0 100644
--- a/arch/arm/src/samd5e5/sam_eic.h
+++ b/arch/arm/src/samd5e5/sam_eic.h
@@ -47,7 +47,7 @@
 
 #include "sam_config.h"
 #include "sam_port.h"
-#include "chip/sam_eic.h"
+#include "hardware/sam_eic.h"
 
 #ifdef CONFIG_SAMD5E5_EIC
 
diff --git a/arch/arm/src/samd5e5/sam_gclk.h b/arch/arm/src/samd5e5/sam_gclk.h
index 58391a58133..dbfa61692a1 100644
--- a/arch/arm/src/samd5e5/sam_gclk.h
+++ b/arch/arm/src/samd5e5/sam_gclk.h
@@ -47,7 +47,7 @@
 
 #include "up_arch.h"
 #include "sam_config.h"
-#include "chip/sam_gclk.h"
+#include "hardware/sam_gclk.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/samd5e5/sam_i2c_master.c b/arch/arm/src/samd5e5/sam_i2c_master.c
index 3f9f283296e..66ef69adfee 100644
--- a/arch/arm/src/samd5e5/sam_i2c_master.c
+++ b/arch/arm/src/samd5e5/sam_i2c_master.c
@@ -60,8 +60,8 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/sam_i2c_master.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_i2c_master.h"
+#include "hardware/sam_pinmap.h"
 #include "sam_gclk.h"
 #include "sam_port.h"
 #include "sam_sercom.h"
diff --git a/arch/arm/src/samd5e5/sam_lowputc.c b/arch/arm/src/samd5e5/sam_lowputc.c
index 1eebdd70171..b6e3424cb93 100644
--- a/arch/arm/src/samd5e5/sam_lowputc.c
+++ b/arch/arm/src/samd5e5/sam_lowputc.c
@@ -46,7 +46,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/sam_pm.h"
+#include "hardware/sam_pm.h"
 #include "sam_config.h"
 #include "sam_gclk.h"
 #include "sam_sercom.h"
diff --git a/arch/arm/src/samd5e5/sam_periphclks.h b/arch/arm/src/samd5e5/sam_periphclks.h
index 1e059313802..30cb1364f7a 100644
--- a/arch/arm/src/samd5e5/sam_periphclks.h
+++ b/arch/arm/src/samd5e5/sam_periphclks.h
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/sam_mclk.h"
+#include "hardware/sam_mclk.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/samd5e5/sam_port.h b/arch/arm/src/samd5e5/sam_port.h
index b3fe29e292c..89af6538137 100644
--- a/arch/arm/src/samd5e5/sam_port.h
+++ b/arch/arm/src/samd5e5/sam_port.h
@@ -49,7 +49,7 @@
 
 #include 
 
-#include "chip/sam_port.h"
+#include "hardware/sam_port.h"
 
 /****************************************************************************
  * Pre-processor Declarations
diff --git a/arch/arm/src/samd5e5/sam_sercom.c b/arch/arm/src/samd5e5/sam_sercom.c
index a50d1a61e85..584ebe5844e 100644
--- a/arch/arm/src/samd5e5/sam_sercom.c
+++ b/arch/arm/src/samd5e5/sam_sercom.c
@@ -48,7 +48,7 @@
 #include "sam_config.h"
 
 #include "chip.h"
-#include "chip/sam_pm.h"
+#include "hardware/sam_pm.h"
 #include "sam_gclk.h"
 #include "sam_sercom.h"
 
diff --git a/arch/arm/src/samd5e5/sam_spi.c b/arch/arm/src/samd5e5/sam_spi.c
index 6bd0409918c..9d3e7e6779a 100644
--- a/arch/arm/src/samd5e5/sam_spi.c
+++ b/arch/arm/src/samd5e5/sam_spi.c
@@ -58,7 +58,7 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 #include "sam_gclk.h"
 #include "sam_port.h"
 #include "sam_sercom.h"
diff --git a/arch/arm/src/samd5e5/sam_spi.h b/arch/arm/src/samd5e5/sam_spi.h
index b1b1838205b..dba7a6ab134 100644
--- a/arch/arm/src/samd5e5/sam_spi.h
+++ b/arch/arm/src/samd5e5/sam_spi.h
@@ -40,7 +40,7 @@
 
 #include 
 #include 
-#include "chip/sam_spi.h"
+#include "hardware/sam_spi.h"
 
 #ifdef SAMD5E5_HAVE_SPI
 
diff --git a/arch/arm/src/samd5e5/sam_start.c b/arch/arm/src/samd5e5/sam_start.c
index 136988bfdb1..c991e7c37ad 100644
--- a/arch/arm/src/samd5e5/sam_start.c
+++ b/arch/arm/src/samd5e5/sam_start.c
@@ -47,6 +47,7 @@
 
 #include "up_arch.h"
 #include "up_internal.h"
+#include "nvic.h"
 
 #include   /* Depends on other definitions */
 #include "sam_clockconfig.h"   /* Depends on settings from board.h */
@@ -54,11 +55,6 @@
 #include "sam_lowputc.h"
 #include "sam_cmcc.h"
 #include "sam_userspace.h"
-
-#ifdef CONFIG_ARCH_FPU
-#  include "nvic.h"
-#endif
-
 #include "sam_start.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/samd5e5/sam_usart.c b/arch/arm/src/samd5e5/sam_usart.c
index 07526819315..2f6b273ab2a 100644
--- a/arch/arm/src/samd5e5/sam_usart.c
+++ b/arch/arm/src/samd5e5/sam_usart.c
@@ -45,8 +45,8 @@
 #include 
 #include 
 
-#include "chip/sam_memorymap.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_memorymap.h"
+#include "hardware/sam_pinmap.h"
 #include "sam_gclk.h"
 #include "sam_sercom.h"
 #include "sam_usart.h"
diff --git a/arch/arm/src/samd5e5/sam_usart.h b/arch/arm/src/samd5e5/sam_usart.h
index 78259ec8d50..b88f6f8ad1f 100644
--- a/arch/arm/src/samd5e5/sam_usart.h
+++ b/arch/arm/src/samd5e5/sam_usart.h
@@ -48,7 +48,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/sam_usart.h"
+#include "hardware/sam_usart.h"
 
 #include "sam_config.h"
 #include "sam_port.h"
diff --git a/arch/arm/src/samd5e5/sam_usb.c b/arch/arm/src/samd5e5/sam_usb.c
index 983feb761f4..41f9a28b027 100644
--- a/arch/arm/src/samd5e5/sam_usb.c
+++ b/arch/arm/src/samd5e5/sam_usb.c
@@ -106,8 +106,8 @@
 #include "up_internal.h"
 
 #include "chip.h"
-#include "chip/sam_pinmap.h"
-#include "chip/sam_fuses.h"
+#include "hardware/sam_pinmap.h"
+#include "hardware/sam_fuses.h"
 #include "sam_gclk.h"
 #include "sam_port.h"
 #include "sam_periphclks.h"
diff --git a/arch/arm/src/samd5e5/sam_usb.h b/arch/arm/src/samd5e5/sam_usb.h
index 50e6fb357fd..490827d4f2e 100644
--- a/arch/arm/src/samd5e5/sam_usb.h
+++ b/arch/arm/src/samd5e5/sam_usb.h
@@ -49,7 +49,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_usb.h"
+#include "hardware/sam_usb.h"
 
 /*****************************************************************************
  * Public Function Prototypes
diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs
index 448d56b9887..a1fd93883a1 100644
--- a/arch/arm/src/samv7/Make.defs
+++ b/arch/arm/src/samv7/Make.defs
@@ -87,12 +87,10 @@ ifeq ($(CONFIG_ARM_MPU),y)
 CMN_CSRCS += up_mpu.c
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
diff --git a/arch/arm/src/samv7/chip.h b/arch/arm/src/samv7/chip.h
index ff612a1080e..8b38809d25f 100644
--- a/arch/arm/src/samv7/chip.h
+++ b/arch/arm/src/samv7/chip.h
@@ -48,7 +48,7 @@
 
 #include 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /* If the common ARMv7-M vector handling logic is used, then it expects
  * the following definition in this file that provides the number of
diff --git a/arch/arm/src/samv7/chip/sam_afec.h b/arch/arm/src/samv7/hardware/sam_afec.h
similarity index 99%
rename from arch/arm/src/samv7/chip/sam_afec.h
rename to arch/arm/src/samv7/hardware/sam_afec.h
index 2f26bf79bc2..adc0be0514c 100644
--- a/arch/arm/src/samv7/chip/sam_afec.h
+++ b/arch/arm/src/samv7/hardware/sam_afec.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam_afec.h
+ * arch/arm/src/samv7/hardware/sam_afec.h
  * Analog-Front-End Controller (AFEC) definitions for the SAMV71
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_AFEC_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_AFEC_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_AFEC_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_AFEC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -567,4 +567,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_AFEC_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_AFEC_H */
diff --git a/arch/arm/src/samv7/chip/sam_chipid.h b/arch/arm/src/samv7/hardware/sam_chipid.h
similarity index 98%
rename from arch/arm/src/samv7/chip/sam_chipid.h
rename to arch/arm/src/samv7/hardware/sam_chipid.h
index bc73e9bc789..3379e86869b 100644
--- a/arch/arm/src/samv7/chip/sam_chipid.h
+++ b/arch/arm/src/samv7/hardware/sam_chipid.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam_chipid.h
+ * arch/arm/src/samv7/hardware/sam_chipid.h
  * CHIPID Register Definitions for the SAMV7
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_CHIPID_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_CHIPID_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_CHIPID_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_CHIPID_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 
 #include 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -183,4 +183,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_CHIPID_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_CHIPID_H */
diff --git a/arch/arm/src/samv7/chip/sam_dacc.h b/arch/arm/src/samv7/hardware/sam_dacc.h
similarity index 98%
rename from arch/arm/src/samv7/chip/sam_dacc.h
rename to arch/arm/src/samv7/hardware/sam_dacc.h
index a40b0d09e5a..a3098d80bbc 100644
--- a/arch/arm/src/samv7/chip/sam_dacc.h
+++ b/arch/arm/src/samv7/hardware/sam_dacc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam_dacc.h
+ * arch/arm/src/samv7/hardware/sam_dacc.h
  * Digital-to-Analog Converter Controller (DACC) for the SAMV7
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_DACC_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_DACC_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_DACC_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_DACC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -223,4 +223,4 @@
 #define DACC_WPSR_WPVSRC_SHIFT      (8)
 #define DACC_WPSR_WPVSRC_MASK       (0xffu << DACC_WPSR_WPVSRC_SHIFT) /* Write Protection Violation Source */
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_DACC_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_DACC_H */
diff --git a/arch/arm/src/samv7/chip/sam_eefc.h b/arch/arm/src/samv7/hardware/sam_eefc.h
similarity index 97%
rename from arch/arm/src/samv7/chip/sam_eefc.h
rename to arch/arm/src/samv7/hardware/sam_eefc.h
index 74d77f00b3e..af1b298fe58 100644
--- a/arch/arm/src/samv7/chip/sam_eefc.h
+++ b/arch/arm/src/samv7/hardware/sam_eefc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam_eefc.h
+ * arch/arm/src/samv7/hardware/sam_eefc.h
  * Enhanced Embedded Flash Controller (EEFC) definitions for the SAMV71
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_EEFC_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_EEFC_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_EEFC_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_EEFC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -163,4 +163,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_EEFC_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_EEFC_H */
diff --git a/arch/arm/src/samv7/chip/sam_emac.h b/arch/arm/src/samv7/hardware/sam_emac.h
similarity index 99%
rename from arch/arm/src/samv7/chip/sam_emac.h
rename to arch/arm/src/samv7/hardware/sam_emac.h
index c613c14f1c0..7ed859f257e 100644
--- a/arch/arm/src/samv7/chip/sam_emac.h
+++ b/arch/arm/src/samv7/hardware/sam_emac.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/samv7/chip/sam_emac.h
+ * arch/arm/src/samv7/hardware/sam_emac.h
  * This is the form of the EMAC interface used the SAMV7.
  * This is referred as GMAC in the documentation even though it does not support
  * Gibabit Ethernet.
@@ -36,8 +36,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_EMAC_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_EMAC_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_EMAC_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_EMAC_H
 
 /************************************************************************************
  * Included Files
@@ -46,7 +46,7 @@
 #include 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 #if SAMV7_NEMAC > 0
 
@@ -1043,4 +1043,4 @@ struct emac_txdesc_s
 };
 
 #endif /* SAMV7_NEMAC > 0 */
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_EMAC_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_EMAC_H */
diff --git a/arch/arm/src/samv7/chip/sam_hsmci.h b/arch/arm/src/samv7/hardware/sam_hsmci.h
similarity index 99%
rename from arch/arm/src/samv7/chip/sam_hsmci.h
rename to arch/arm/src/samv7/hardware/sam_hsmci.h
index 38b817ae8be..e7c23b1d125 100644
--- a/arch/arm/src/samv7/chip/sam_hsmci.h
+++ b/arch/arm/src/samv7/hardware/sam_hsmci.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam_hsmci.h
+ * arch/arm/src/samv7/hardware/sam_hsmci.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_HSMCI_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_HSMCI_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_HSMCI_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_HSMCI_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 #if SAMV7_NHSMCI4 > 0
 
@@ -363,4 +363,4 @@
  ****************************************************************************************/
 
 #endif /* SAMV7_NHSMCI4 > 0 */
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_HSMCI_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_HSMCI_H */
diff --git a/arch/arm/src/samv7/chip/sam_matrix.h b/arch/arm/src/samv7/hardware/sam_matrix.h
similarity index 98%
rename from arch/arm/src/samv7/chip/sam_matrix.h
rename to arch/arm/src/samv7/hardware/sam_matrix.h
index 2de2cd538c6..da3a91d62f6 100644
--- a/arch/arm/src/samv7/chip/sam_matrix.h
+++ b/arch/arm/src/samv7/hardware/sam_matrix.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam_matrix.h
+ * arch/arm/src/samv7/hardware/sam_matrix.h
  * Bux matrix definitions for the SAMV71
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_MATRIX_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_MATRIX_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MATRIX_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MATRIX_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -332,4 +332,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_MATRIX_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MATRIX_H */
diff --git a/arch/arm/src/samv7/chip/sam_mcan.h b/arch/arm/src/samv7/hardware/sam_mcan.h
similarity index 99%
rename from arch/arm/src/samv7/chip/sam_mcan.h
rename to arch/arm/src/samv7/hardware/sam_mcan.h
index 4212ca3c291..a452cc79d5c 100644
--- a/arch/arm/src/samv7/chip/sam_mcan.h
+++ b/arch/arm/src/samv7/hardware/sam_mcan.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam_mcan.h
+ * arch/arm/src/samv7/hardware/sam_mcan.h
  * Controller Area Network (MCAN) definitions for the SAMV71
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_MCAN_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_MCAN_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MCAN_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MCAN_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -810,4 +810,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_MCAN_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MCAN_H */
diff --git a/arch/arm/src/samv7/chip/sam_memorymap.h b/arch/arm/src/samv7/hardware/sam_memorymap.h
similarity index 87%
rename from arch/arm/src/samv7/chip/sam_memorymap.h
rename to arch/arm/src/samv7/hardware/sam_memorymap.h
index e3849a8500f..1d5aa34a738 100644
--- a/arch/arm/src/samv7/chip/sam_memorymap.h
+++ b/arch/arm/src/samv7/hardware/sam_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/samv7/chip/sam_memorymap.h
+ * arch/arm/src/samv7/hardware/sam_memorymap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -43,11 +43,11 @@
 #include 
 
 #if defined(CONFIG_ARCH_CHIP_SAMV71)
-#  include "chip/samv71_memorymap.h"
+#  include "hardware/samv71_memorymap.h"
 #elif defined(CONFIG_ARCH_CHIP_SAME70)
-#  include "chip/same70_memorymap.h"
+#  include "hardware/same70_memorymap.h"
 #else
 #  error Unrecognized SAMV7 architecture
 #endif
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_MEMORYMAP_H */
diff --git a/arch/arm/src/samv7/chip/sam_pinmap.h b/arch/arm/src/samv7/hardware/sam_pinmap.h
similarity index 88%
rename from arch/arm/src/samv7/chip/sam_pinmap.h
rename to arch/arm/src/samv7/hardware/sam_pinmap.h
index f0edd2218ea..71bfa1887be 100644
--- a/arch/arm/src/samv7/chip/sam_pinmap.h
+++ b/arch/arm/src/samv7/hardware/sam_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/samv7/chip/sam_pinmap.h
+ * arch/arm/src/samv7/hardware/sam_pinmap.h
  *
  *   Copyright (C) 2012-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_PINMAP_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_PINMAP_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -43,12 +43,12 @@
 #include 
 
 #if defined(CONFIG_ARCH_CHIP_SAMV71)
-#  include "chip/samv71_pinmap.h"
+#  include "hardware/samv71_pinmap.h"
 #elif defined(CONFIG_ARCH_CHIP_SAME70)
-#  include "chip/same70_pinmap.h"
+#  include "hardware/same70_pinmap.h"
 #else
 #  error Unrecognized SAMV7 architecture
 #endif
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_PINMAP_H */
 
diff --git a/arch/arm/src/samv7/chip/sam_pio.h b/arch/arm/src/samv7/hardware/sam_pio.h
similarity index 99%
rename from arch/arm/src/samv7/chip/sam_pio.h
rename to arch/arm/src/samv7/hardware/sam_pio.h
index 29a415eb410..978b8d7bad2 100644
--- a/arch/arm/src/samv7/chip/sam_pio.h
+++ b/arch/arm/src/samv7/hardware/sam_pio.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam4e_pio.h
+ * arch/arm/src/samv7/hardware/sam4e_pio.h
  * Parallel Input/Output (PIO) Controller definitions for the SAMV71
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM4E_PIO_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM4E_PIO_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM4E_PIO_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM4E_PIO_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 #if SAMV7_NPIO > 0
 
@@ -591,4 +591,4 @@
  ****************************************************************************************/
 
 #endif /* SAMV7_NPIO > 0 */
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM4E_PIO_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM4E_PIO_H */
diff --git a/arch/arm/src/samv7/chip/sam_pmc.h b/arch/arm/src/samv7/hardware/sam_pmc.h
similarity index 99%
rename from arch/arm/src/samv7/chip/sam_pmc.h
rename to arch/arm/src/samv7/hardware/sam_pmc.h
index ac4f570cbe8..c01e01a2afd 100644
--- a/arch/arm/src/samv7/chip/sam_pmc.h
+++ b/arch/arm/src/samv7/hardware/sam_pmc.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/samv7/chip/sam_pmc.h
+ * arch/arm/src/samv7/hardware/sam_pmc.h
  * Power Management Controller (PMC) for the SAMV71
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_PMC_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_PMC_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_PMC_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_PMC_H
 
 /********************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -463,4 +463,4 @@
  * Public Functions
  ********************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_PMC_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_PMC_H */
diff --git a/arch/arm/src/samv7/chip/sam_qspi.h b/arch/arm/src/samv7/hardware/sam_qspi.h
similarity index 98%
rename from arch/arm/src/samv7/chip/sam_qspi.h
rename to arch/arm/src/samv7/hardware/sam_qspi.h
index 55605634e44..fb5b47df0a0 100644
--- a/arch/arm/src/samv7/chip/sam_qspi.h
+++ b/arch/arm/src/samv7/hardware/sam_qspi.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam_qspi.h
+ * arch/arm/src/samv7/hardware/sam_qspi.h
  * Quad SPI (QSPI) definitions for the SAMV71
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_QSPI_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_QSPI_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_QSPI_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_QSPI_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 #if SAMV7_NQSPI > 0
 
@@ -271,4 +271,4 @@
  ****************************************************************************************/
 
 #endif /* SAMV7_NQSPI > 0 */
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_QSPI_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_QSPI_H */
diff --git a/arch/arm/src/samv7/chip/sam_rstc.h b/arch/arm/src/samv7/hardware/sam_rstc.h
similarity index 95%
rename from arch/arm/src/samv7/chip/sam_rstc.h
rename to arch/arm/src/samv7/hardware/sam_rstc.h
index ed15f430151..6b6cb9a111b 100644
--- a/arch/arm/src/samv7/chip/sam_rstc.h
+++ b/arch/arm/src/samv7/hardware/sam_rstc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv71/chip/sam_rstc.h
+ * arch/arm/src/samv7/hardware/sam_rstc.h
  * Reset Controller (RSTC) definitions for the SAMV71
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_RSTC_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_RSTC_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_RSTC_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_RSTC_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 
 #include 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -107,4 +107,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_RSTC_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_RSTC_H */
diff --git a/arch/arm/src/samv7/chip/sam_rtc.h b/arch/arm/src/samv7/hardware/sam_rtc.h
similarity index 98%
rename from arch/arm/src/samv7/chip/sam_rtc.h
rename to arch/arm/src/samv7/hardware/sam_rtc.h
index 1b1feeb881f..1d9b9360776 100644
--- a/arch/arm/src/samv7/chip/sam_rtc.h
+++ b/arch/arm/src/samv7/hardware/sam_rtc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam_rtc.h
+ * arch/arm/src/samv7/hardware/sam_rtc.h
  * Real-time Clock (RTC) definitions for the SAMV71
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_RTC_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_RTC_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_RTC_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_RTC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -267,4 +267,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_RTC_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_RTC_H */
diff --git a/arch/arm/src/samv7/chip/sam_sdramc.h b/arch/arm/src/samv7/hardware/sam_sdramc.h
similarity index 98%
rename from arch/arm/src/samv7/chip/sam_sdramc.h
rename to arch/arm/src/samv7/hardware/sam_sdramc.h
index 40653f52ee5..c94d068ef4d 100644
--- a/arch/arm/src/samv7/chip/sam_sdramc.h
+++ b/arch/arm/src/samv7/hardware/sam_sdramc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam_sdramc.h
+ * arch/arm/src/samv7/hardware/sam_sdramc.h
  * SDRAM Controler (SDRAMC) definitions for the SAMV71
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SDRAMC_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SDRAMC_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SDRAMC_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SDRAMC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -204,4 +204,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SDRAMC_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SDRAMC_H */
diff --git a/arch/arm/src/samv7/chip/sam_smc.h b/arch/arm/src/samv7/hardware/sam_smc.h
similarity index 98%
rename from arch/arm/src/samv7/chip/sam_smc.h
rename to arch/arm/src/samv7/hardware/sam_smc.h
index 3c69196711c..ab9a0947528 100644
--- a/arch/arm/src/samv7/chip/sam_smc.h
+++ b/arch/arm/src/samv7/hardware/sam_smc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/ssamv7/chip/sam_smc.h
+ * arch/arm/src/samv7/hardware/sam_smc.h
  * Static Memory Controller (SMC) definitions for the SAMV71
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SMC_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SMC_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SMC_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SMC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -210,4 +210,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SMC_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SMC_H */
diff --git a/arch/arm/src/samv7/chip/sam_spi.h b/arch/arm/src/samv7/hardware/sam_spi.h
similarity index 98%
rename from arch/arm/src/samv7/chip/sam_spi.h
rename to arch/arm/src/samv7/hardware/sam_spi.h
index fe738b2e184..0ce24e05d86 100644
--- a/arch/arm/src/samv7/chip/sam_spi.h
+++ b/arch/arm/src/samv7/hardware/sam_spi.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam_spi.h
+ * arch/arm/src/samv7/hardware/sam_spi.h
  * Serial Peripheral Interface (SPI) definitions for the SAMV71
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SPI_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SPI_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SPI_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SPI_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 #if SAMV7_NSPI > 0
 
@@ -229,4 +229,4 @@
  ****************************************************************************************/
 
 #endif /* SAMV7_NSPI > 0 */
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SPI_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SPI_H */
diff --git a/arch/arm/src/samv7/chip/sam_ssc.h b/arch/arm/src/samv7/hardware/sam_ssc.h
similarity index 98%
rename from arch/arm/src/samv7/chip/sam_ssc.h
rename to arch/arm/src/samv7/hardware/sam_ssc.h
index 98f34bc8373..481e99f4a98 100644
--- a/arch/arm/src/samv7/chip/sam_ssc.h
+++ b/arch/arm/src/samv7/hardware/sam_ssc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/samv7/chip/sam_ssc.h
+ * arch/arm/src/samv7/hardware/sam_ssc.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SSC_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SSC_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SSC_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SSC_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 #if SAMV7_NSSC > 0
 
@@ -315,4 +315,4 @@
 #define SSC_WPSR_WPVSRC_MASK       (0xffff << SSC_WPSR_WPVSRC_SHIFT)
 
 #endif /* SAMV7_NSSC > 0 */
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SSC_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SSC_H */
diff --git a/arch/arm/src/samv7/chip/sam_supc.h b/arch/arm/src/samv7/hardware/sam_supc.h
similarity index 98%
rename from arch/arm/src/samv7/chip/sam_supc.h
rename to arch/arm/src/samv7/hardware/sam_supc.h
index 878d3e464bd..451a1551a61 100644
--- a/arch/arm/src/samv7/chip/sam_supc.h
+++ b/arch/arm/src/samv7/hardware/sam_supc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam_supc.h
+ * arch/arm/src/samv7/hardware/sam_supc.h
  * Supply Controller (SUPC) definitions for the SAMV71
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SUPC_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SUPC_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SUPC_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SUPC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -182,4 +182,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SUPC_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SUPC_H */
diff --git a/arch/arm/src/samv7/chip/sam_sysc.h b/arch/arm/src/samv7/hardware/sam_sysc.h
similarity index 94%
rename from arch/arm/src/samv7/chip/sam_sysc.h
rename to arch/arm/src/samv7/hardware/sam_sysc.h
index d50a5239ce4..86c0b2ee359 100644
--- a/arch/arm/src/samv7/chip/sam_sysc.h
+++ b/arch/arm/src/samv7/hardware/sam_sysc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam_sysc.h
+ * arch/arm/src/samv7/hardware/sam_sysc.h
  * Supply Controller (SYSC) definitions for the SAMV71
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SYSC_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SYSC_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SYSC_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SYSC_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -78,4 +78,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SYSC_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_SYSC_H */
diff --git a/arch/arm/src/samv7/chip/sam_tc.h b/arch/arm/src/samv7/hardware/sam_tc.h
similarity index 99%
rename from arch/arm/src/samv7/chip/sam_tc.h
rename to arch/arm/src/samv7/hardware/sam_tc.h
index 0492bb028c9..2e57fb82116 100644
--- a/arch/arm/src/samv7/chip/sam_tc.h
+++ b/arch/arm/src/samv7/hardware/sam_tc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/samv7/chip/sam_tc.h
+ * arch/arm/src/samv7/hardware/sam_tc.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TC_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TC_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TC_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -638,4 +638,4 @@
 #define TC_WPMR_WPKEY_MASK       (0xffffff << TC_WPMR_WPKEY_SHIFT)
 #  define TC_WPMR_WPKEY          (0x54494d << TC_WPMR_WPKEY_SHIFT) /* "TIM" in ASCII */
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TC_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TC_H */
diff --git a/arch/arm/src/samv7/chip/sam_trng.h b/arch/arm/src/samv7/hardware/sam_trng.h
similarity index 94%
rename from arch/arm/src/samv7/chip/sam_trng.h
rename to arch/arm/src/samv7/hardware/sam_trng.h
index 5f4d2ef3a1e..fb2bfd08fd3 100644
--- a/arch/arm/src/samv7/chip/sam_trng.h
+++ b/arch/arm/src/samv7/hardware/sam_trng.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/samv7/chip/sam_trng.h
+ * arch/arm/src/samv7/hardware/sam_trng.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TRNG_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TRNG_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TRNG_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TRNG_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -82,4 +82,4 @@
 
 /* Output Data Register (32-bit output data) */
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TRNG_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TRNG_H */
diff --git a/arch/arm/src/samv7/chip/sam_twihs.h b/arch/arm/src/samv7/hardware/sam_twihs.h
similarity index 98%
rename from arch/arm/src/samv7/chip/sam_twihs.h
rename to arch/arm/src/samv7/hardware/sam_twihs.h
index c036812de53..417f465f3e7 100644
--- a/arch/arm/src/samv7/chip/sam_twihs.h
+++ b/arch/arm/src/samv7/hardware/sam_twihs.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam_twihs.h
+ * arch/arm/src/samv7/hardware/sam_twihs.h
  * Two-wire Interface (TWIHS) definitions for the SAMV71
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TWIHS_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TWIHS_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TWIHS_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TWIHS_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 #if SAMV7_NTWIHS > 0
 
@@ -303,4 +303,4 @@
  ****************************************************************************************/
 
 #endif /* SAMV7_NTWIHS > 0 */
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_TWIHS_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_TWIHS_H */
diff --git a/arch/arm/src/samv7/chip/sam_uart.h b/arch/arm/src/samv7/hardware/sam_uart.h
similarity index 99%
rename from arch/arm/src/samv7/chip/sam_uart.h
rename to arch/arm/src/samv7/hardware/sam_uart.h
index c0fdac8acf7..7d531c2ae3f 100644
--- a/arch/arm/src/samv7/chip/sam_uart.h
+++ b/arch/arm/src/samv7/hardware/sam_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/samv7/chip/sam_uart.h
+ * arch/arm/src/samv7/hardware/sam_uart.h
  * Universal Asynchronous Receiver Transmitter (UART) and Universal Synchronous Asynchronous
  * Receiver Transmitter (USART) definitions for the SAMV71.
  *
@@ -35,8 +35,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_UART_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_UART_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_UART_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_UART_H
 
 /************************************************************************************************
  * Included Files
@@ -45,7 +45,7 @@
 #include 
 
 #include "arch/samv7/chip.h"
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************************
  * Pre-processor Definitions
@@ -571,4 +571,4 @@
  * Public Functions
  ************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_UART_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_UART_H */
diff --git a/arch/arm/src/samv7/chip/sam_usbhs.h b/arch/arm/src/samv7/hardware/sam_usbhs.h
similarity index 99%
rename from arch/arm/src/samv7/chip/sam_usbhs.h
rename to arch/arm/src/samv7/hardware/sam_usbhs.h
index 3661ca91e7e..ec90166d743 100644
--- a/arch/arm/src/samv7/chip/sam_usbhs.h
+++ b/arch/arm/src/samv7/hardware/sam_usbhs.h
@@ -1,5 +1,5 @@
 /************************************************************************************************************
- * arch/arm/src/samv7/chip/sam_usbhs.h
+ * arch/arm/src/samv7/hardware/sam_usbhs.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -36,8 +36,8 @@
  *
  ************************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_USBHS_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_USBHS_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_USBHS_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_USBHS_H
 
 /************************************************************************************************************
  * Included Files
@@ -46,7 +46,7 @@
 #include 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************************************
  * Pre-processor Definitions
@@ -802,4 +802,4 @@ struct usbhs_dtd_s
  * Public Functions
  ************************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_USBHS_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_USBHS_H */
diff --git a/arch/arm/src/samv7/chip/sam_utmi.h b/arch/arm/src/samv7/hardware/sam_utmi.h
similarity index 95%
rename from arch/arm/src/samv7/chip/sam_utmi.h
rename to arch/arm/src/samv7/hardware/sam_utmi.h
index 6d65d5480ed..63b4d80ebce 100644
--- a/arch/arm/src/samv7/chip/sam_utmi.h
+++ b/arch/arm/src/samv7/hardware/sam_utmi.h
@@ -1,5 +1,5 @@
 /************************************************************************************************************
- * arch/arm/src/samv7/chip/sam_utmi.h
+ * arch/arm/src/samv7/hardware/sam_utmi.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -36,8 +36,8 @@
  *
  ************************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_UTMI_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_UTMI_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_UTMI_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_UTMI_H
 
 /************************************************************************************************************
  * Included Files
@@ -46,7 +46,7 @@
 #include 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /************************************************************************************************************
  * Pre-processor Definitions
@@ -89,4 +89,4 @@
  * Public Functions
  ************************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_UTMI_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_UTMI_H */
diff --git a/arch/arm/src/samv7/chip/sam_wdt.h b/arch/arm/src/samv7/hardware/sam_wdt.h
similarity index 96%
rename from arch/arm/src/samv7/chip/sam_wdt.h
rename to arch/arm/src/samv7/hardware/sam_wdt.h
index 3a949c3c97a..90e9d16a229 100644
--- a/arch/arm/src/samv7/chip/sam_wdt.h
+++ b/arch/arm/src/samv7/hardware/sam_wdt.h
@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/samv7/chip/sam_wdt.h
+ * arch/arm/src/samv7/hardware/sam_wdt.h
  * Watchdog Timer (WDT) definitions for the SAMV71
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_WDT_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_WDT_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_WDT_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_WDT_H
 
 /****************************************************************************************
  * Included Files
@@ -44,7 +44,7 @@
 #include 
 #include 
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -114,4 +114,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_WDT_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_WDT_H */
diff --git a/arch/arm/src/samv7/chip/sam_xdmac.h b/arch/arm/src/samv7/hardware/sam_xdmac.h
similarity index 99%
rename from arch/arm/src/samv7/chip/sam_xdmac.h
rename to arch/arm/src/samv7/hardware/sam_xdmac.h
index 1cf968fbd85..c35f5db6092 100644
--- a/arch/arm/src/samv7/chip/sam_xdmac.h
+++ b/arch/arm/src/samv7/hardware/sam_xdmac.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/samv7/chip/sam_xdmac.h
+ * arch/arm/src/samv7/hardware/sam_xdmac.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_XDMAC_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_XDMAC_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_XDMAC_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_XDMAC_H
 
 /************************************************************************************
  * Included Files
@@ -460,4 +460,4 @@ struct chnext_view3_s
   uint32_t cdus; /* Destination Microblock Stride */
 };
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_XDMAC_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM_XDMAC_H */
diff --git a/arch/arm/src/samv7/chip/same70_memorymap.h b/arch/arm/src/samv7/hardware/same70_memorymap.h
similarity index 98%
rename from arch/arm/src/samv7/chip/same70_memorymap.h
rename to arch/arm/src/samv7/hardware/same70_memorymap.h
index 421f93686fd..c5e86d850df 100644
--- a/arch/arm/src/samv7/chip/same70_memorymap.h
+++ b/arch/arm/src/samv7/hardware/same70_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/samv7/chip/same70_memorymap.h
+ * arch/arm/src/samv7/hardware/same70_memorymap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAME70_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAME70_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAME70_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAME70_MEMORYMAP_H
 
 /************************************************************************************************
  * Included Files
@@ -198,4 +198,4 @@ extern "C"
 
 #endif /* __ASSEMBLY__ */
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM4S_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM4S_MEMORYMAP_H */
diff --git a/arch/arm/src/samv7/chip/same70_pinmap.h b/arch/arm/src/samv7/hardware/same70_pinmap.h
similarity index 99%
rename from arch/arm/src/samv7/chip/same70_pinmap.h
rename to arch/arm/src/samv7/hardware/same70_pinmap.h
index 160963c00e8..d716f67ea52 100644
--- a/arch/arm/src/samv7/chip/same70_pinmap.h
+++ b/arch/arm/src/samv7/hardware/same70_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/samv7/chip/same70_pinmap.h
+ * arch/arm/src/samv7/hardware/same70_pinmap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAME70_PINMAP_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAME70_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAME70_PINMAP_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAME70_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -567,4 +567,4 @@ extern "C"
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAME70_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAME70_PINMAP_H */
diff --git a/arch/arm/src/samv7/chip/samv71_memorymap.h b/arch/arm/src/samv7/hardware/samv71_memorymap.h
similarity index 98%
rename from arch/arm/src/samv7/chip/samv71_memorymap.h
rename to arch/arm/src/samv7/hardware/samv71_memorymap.h
index 97742117a98..0e0185ebfef 100644
--- a/arch/arm/src/samv7/chip/samv71_memorymap.h
+++ b/arch/arm/src/samv7/hardware/samv71_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************************
- * arch/arm/src/samv7/chip/samv71_memorymap.h
+ * arch/arm/src/samv7/hardware/samv71_memorymap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAMV71_MEMORYMAP_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAMV71_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAMV71_MEMORYMAP_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAMV71_MEMORYMAP_H
 
 /************************************************************************************************
  * Included Files
@@ -198,4 +198,4 @@ extern "C"
 
 #endif /* __ASSEMBLY__ */
 
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM4S_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAM4S_MEMORYMAP_H */
diff --git a/arch/arm/src/samv7/chip/samv71_pinmap.h b/arch/arm/src/samv7/hardware/samv71_pinmap.h
similarity index 99%
rename from arch/arm/src/samv7/chip/samv71_pinmap.h
rename to arch/arm/src/samv7/hardware/samv71_pinmap.h
index 497035e70c3..47bf1091be6 100644
--- a/arch/arm/src/samv7/chip/samv71_pinmap.h
+++ b/arch/arm/src/samv7/hardware/samv71_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/samv7/chip/samv71_pinmap.h
+ * arch/arm/src/samv7/hardware/samv71_pinmap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAMV71_PINMAP_H
-#define __ARCH_ARM_SRC_SAMV7_CHIP_SAMV71_PINMAP_H
+#ifndef __ARCH_ARM_SRC_SAMV7_HARDWARE_SAMV71_PINMAP_H
+#define __ARCH_ARM_SRC_SAMV7_HARDWARE_SAMV71_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -573,4 +573,4 @@ extern "C"
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAMV71_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_SAMV7_HARDWARE_SAMV71_PINMAP_H */
diff --git a/arch/arm/src/samv7/sam_allocateheap.c b/arch/arm/src/samv7/sam_allocateheap.c
index 1e8dc087963..18f3ce59e25 100644
--- a/arch/arm/src/samv7/sam_allocateheap.c
+++ b/arch/arm/src/samv7/sam_allocateheap.c
@@ -59,6 +59,7 @@
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
+
 /* All SAM's have SRAM.  In addition, they may have external SRAM or SDRAM */
 
 #define HAVE_SDRAM_REGION     0 /* Assume no external SDRAM */
@@ -72,31 +73,31 @@
  */
 
 #if !defined(CONFIG_SAMV7_SDRAMC) || !defined(CONFIG_SAMV7_SDRAMHEAP)
-#  undef CONFIG_SAMV7_SDRAMSIZE
+#  undef  CONFIG_SAMV7_SDRAMSIZE
 #  define CONFIG_SAMV7_SDRAMSIZE 0
 #endif
 
-/* Check if external SRAM is supported and, if so, it is is intended
- * to be used as heap.
+/* Check if external SRAM is supported and, if so, is it intended to be used
+ * as heap memory?
  */
 
 #if !defined(CONFIG_SAMV7_EXTSRAM0) || !defined(CONFIG_SAMV7_EXTSRAM0HEAP)
-#  undef CONFIG_SAMV7_EXTSRAM0SIZE
+#  undef  CONFIG_SAMV7_EXTSRAM0SIZE
 #  define CONFIG_SAMV7_EXTSRAM0SIZE 0
 #endif
 
 #if !defined(CONFIG_SAMV7_EXTSRAM1) || !defined(CONFIG_SAMV7_EXTSRAM1HEAP)
-#  undef CONFIG_SAMV7_EXTSRAM1SIZE
+#  undef  CONFIG_SAMV7_EXTSRAM1SIZE
 #  define CONFIG_SAMV7_EXTSRAM1SIZE 0
 #endif
 
 #if !defined(CONFIG_SAMV7_EXTSRAM2) || !defined(CONFIG_SAMV7_EXTSRAM2HEAP)
-#  undef CONFIG_SAMV7_EXTSRAM2SIZE
+#  undef  CONFIG_SAMV7_EXTSRAM2SIZE
 #  define CONFIG_SAMV7_EXTSRAM2SIZE 0
 #endif
 
 #if !defined(CONFIG_SAMV7_EXTSRAM3) || !defined(CONFIG_SAMV7_EXTSRAM3HEAP)
-#  undef CONFIG_SAMV7_EXTSRAM3SIZE
+#  undef  CONFIG_SAMV7_EXTSRAM3SIZE
 #  define CONFIG_SAMV7_EXTSRAM3SIZE 0
 #endif
 
@@ -165,14 +166,6 @@
 #  warning "CONFIG_RAM_END is before end of SRAM... not all of SRAM used"
 #endif
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
diff --git a/arch/arm/src/samv7/sam_clockconfig.c b/arch/arm/src/samv7/sam_clockconfig.c
index 2538aadc75d..5e28a267893 100644
--- a/arch/arm/src/samv7/sam_clockconfig.c
+++ b/arch/arm/src/samv7/sam_clockconfig.c
@@ -49,12 +49,12 @@
 #include "up_internal.h"
 
 #include "sam_clockconfig.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_eefc.h"
-#include "chip/sam_wdt.h"
-#include "chip/sam_supc.h"
-#include "chip/sam_matrix.h"
-#include "chip/sam_utmi.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_eefc.h"
+#include "hardware/sam_wdt.h"
+#include "hardware/sam_supc.h"
+#include "hardware/sam_matrix.h"
+#include "hardware/sam_utmi.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/samv7/sam_dac.c b/arch/arm/src/samv7/sam_dac.c
index 74b3f97f698..1cf795d81e3 100644
--- a/arch/arm/src/samv7/sam_dac.c
+++ b/arch/arm/src/samv7/sam_dac.c
@@ -55,9 +55,9 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/sam_dacc.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_dacc.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_pinmap.h"
 
 #include "sam_gpio.h"
 #include "sam_xdmac.h"
diff --git a/arch/arm/src/samv7/sam_dac.h b/arch/arm/src/samv7/sam_dac.h
index 616d25b486c..660a37b48b9 100644
--- a/arch/arm/src/samv7/sam_dac.h
+++ b/arch/arm/src/samv7/sam_dac.h
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/sam_dacc.h"
+#include "hardware/sam_dacc.h"
 
 #if defined(CONFIG_SAMV7_DAC0) || defined(CONFIG_SAMV7_DAC1)
 
diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c
index 4432bf74451..a61e3f64f98 100644
--- a/arch/arm/src/samv7/sam_emac.c
+++ b/arch/arm/src/samv7/sam_emac.c
@@ -84,8 +84,8 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/sam_pinmap.h"
-#include "chip/sam_chipid.h"
+#include "hardware/sam_pinmap.h"
+#include "hardware/sam_chipid.h"
 #include "sam_gpio.h"
 #include "sam_periphclks.h"
 #include "sam_ethernet.h"
@@ -3462,7 +3462,7 @@ static int sam_phyintenable(struct sam_emac_s *priv)
   uint16_t phyval;
   int ret;
 
-  /* Does this MAC support a KSZ80x1 PHY? */
+  /* Does this MAC support a KSZ80X1 PHY? */
 
   if (priv->phytype == SAMV7_PHY_KSZ8051 ||
       priv->phytype == SAMV7_PHY_KSZ8061 ||
@@ -3483,7 +3483,7 @@ static int sam_phyintenable(struct sam_emac_s *priv)
           /* Enable link up/down interrupts */
 
           ret = sam_phywrite(priv, priv->phyaddr, MII_KSZ8081_INT,
-                            (MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN));
+                            (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN));
         }
 
       /* Disable management port (probably) */
diff --git a/arch/arm/src/samv7/sam_ethernet.h b/arch/arm/src/samv7/sam_ethernet.h
index adde127c852..c46c1b05487 100644
--- a/arch/arm/src/samv7/sam_ethernet.h
+++ b/arch/arm/src/samv7/sam_ethernet.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/sam_emac.h"
+#include "hardware/sam_emac.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/samv7/sam_gpio.c b/arch/arm/src/samv7/sam_gpio.c
index 1eac04d5765..342db5ba587 100644
--- a/arch/arm/src/samv7/sam_gpio.c
+++ b/arch/arm/src/samv7/sam_gpio.c
@@ -53,8 +53,8 @@
 #include "up_arch.h"
 
 #include "sam_gpio.h"
-#include "chip/sam_pio.h"
-#include "chip/sam_matrix.h"
+#include "hardware/sam_pio.h"
+#include "hardware/sam_matrix.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/samv7/sam_gpioirq.c b/arch/arm/src/samv7/sam_gpioirq.c
index 78cbc4c5ed7..cefcacc2399 100644
--- a/arch/arm/src/samv7/sam_gpioirq.c
+++ b/arch/arm/src/samv7/sam_gpioirq.c
@@ -55,8 +55,8 @@
 
 #include "sam_gpio.h"
 #include "sam_periphclks.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_pio.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_pio.h"
 
 #ifdef CONFIG_SAMV7_GPIO_IRQ
 
diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c
index 4f3760db1b9..49059d4db3e 100644
--- a/arch/arm/src/samv7/sam_hsmci.c
+++ b/arch/arm/src/samv7/sam_hsmci.c
@@ -65,10 +65,10 @@
 #include "sam_xdmac.h"
 #include "sam_periphclks.h"
 #include "sam_hsmci.h"
-#include "chip/sam_xdmac.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_hsmci.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_xdmac.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_hsmci.h"
+#include "hardware/sam_pinmap.h"
 
 #ifdef CONFIG_SAMV7_HSMCI
 
diff --git a/arch/arm/src/samv7/sam_hsmci_clkdiv.c b/arch/arm/src/samv7/sam_hsmci_clkdiv.c
index 0da38726216..7604150503b 100644
--- a/arch/arm/src/samv7/sam_hsmci_clkdiv.c
+++ b/arch/arm/src/samv7/sam_hsmci_clkdiv.c
@@ -48,7 +48,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_hsmci.h"
+#include "hardware/sam_hsmci.h"
 #include "sam_hsmci.h"
 
 #ifdef CONFIG_SAMV7_HSMCI0
diff --git a/arch/arm/src/samv7/sam_lowputc.c b/arch/arm/src/samv7/sam_lowputc.c
index 614a9defd9c..26345a7835b 100644
--- a/arch/arm/src/samv7/sam_lowputc.c
+++ b/arch/arm/src/samv7/sam_lowputc.c
@@ -52,9 +52,9 @@
 #include "sam_periphclks.h"
 #include "sam_lowputc.h"
 
-#include "chip/sam_uart.h"
-#include "chip/sam_pinmap.h"
-#include "chip/sam_matrix.h"
+#include "hardware/sam_uart.h"
+#include "hardware/sam_pinmap.h"
+#include "hardware/sam_matrix.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c
index f8d0a76c423..093fe29594a 100644
--- a/arch/arm/src/samv7/sam_mcan.c
+++ b/arch/arm/src/samv7/sam_mcan.c
@@ -61,8 +61,8 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/sam_matrix.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_matrix.h"
+#include "hardware/sam_pinmap.h"
 #include "sam_periphclks.h"
 #include "sam_gpio.h"
 #include "sam_mcan.h"
diff --git a/arch/arm/src/samv7/sam_mcan.h b/arch/arm/src/samv7/sam_mcan.h
index 0c5dc6c7260..a1e2d005568 100644
--- a/arch/arm/src/samv7/sam_mcan.h
+++ b/arch/arm/src/samv7/sam_mcan.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_mcan.h"
+#include "hardware/sam_mcan.h"
 
 #include 
 
diff --git a/arch/arm/src/samv7/sam_mpuinit.c b/arch/arm/src/samv7/sam_mpuinit.c
index 59f48fca5ee..82edf1ccc97 100644
--- a/arch/arm/src/samv7/sam_mpuinit.c
+++ b/arch/arm/src/samv7/sam_mpuinit.c
@@ -46,7 +46,7 @@
 #include "mpu.h"
 #include "barriers.h"
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 #include "sam_mpuinit.h"
 
diff --git a/arch/arm/src/samv7/sam_pck.c b/arch/arm/src/samv7/sam_pck.c
index 3511d0d9ce9..d372cbe916f 100644
--- a/arch/arm/src/samv7/sam_pck.c
+++ b/arch/arm/src/samv7/sam_pck.c
@@ -45,7 +45,7 @@
 
 #include 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 
 #include "up_arch.h"
 #include "sam_gpio.h"
diff --git a/arch/arm/src/samv7/sam_pck.h b/arch/arm/src/samv7/sam_pck.h
index 173fc0c53f5..bef406fef6d 100644
--- a/arch/arm/src/samv7/sam_pck.h
+++ b/arch/arm/src/samv7/sam_pck.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pmc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/samv7/sam_progmem.c b/arch/arm/src/samv7/sam_progmem.c
index 48c2e78a64f..d554429ed9a 100644
--- a/arch/arm/src/samv7/sam_progmem.c
+++ b/arch/arm/src/samv7/sam_progmem.c
@@ -49,7 +49,7 @@
 #include "up_arch.h"
 #include "barriers.h"
 
-#include "chip/sam_memorymap.h"
+#include "hardware/sam_memorymap.h"
 
 #include "sam_progmem.h"
 
diff --git a/arch/arm/src/samv7/sam_progmem.h b/arch/arm/src/samv7/sam_progmem.h
index 6c2deaff7f0..0f8e26097e6 100644
--- a/arch/arm/src/samv7/sam_progmem.h
+++ b/arch/arm/src/samv7/sam_progmem.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/sam_eefc.h"
+#include "hardware/sam_eefc.h"
 
 #include 
 
diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c
index 379c21d88fd..db7520434e0 100644
--- a/arch/arm/src/samv7/sam_qspi.c
+++ b/arch/arm/src/samv7/sam_qspi.c
@@ -66,10 +66,10 @@
 #include "sam_xdmac.h"
 #include "sam_periphclks.h"
 #include "sam_qspi.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_xdmac.h"
-#include "chip/sam_qspi.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_xdmac.h"
+#include "hardware/sam_qspi.h"
+#include "hardware/sam_pinmap.h"
 
 #ifdef CONFIG_SAMV7_QSPI
 
diff --git a/arch/arm/src/samv7/sam_serial.c b/arch/arm/src/samv7/sam_serial.c
index f13bab6f140..3248bcd90a4 100644
--- a/arch/arm/src/samv7/sam_serial.c
+++ b/arch/arm/src/samv7/sam_serial.c
@@ -62,7 +62,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 #include "sam_config.h"
-#include "chip/sam_uart.h"
+#include "hardware/sam_uart.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c
index 195258c3c25..ef5118334f8 100644
--- a/arch/arm/src/samv7/sam_spi.c
+++ b/arch/arm/src/samv7/sam_spi.c
@@ -66,10 +66,10 @@
 #include "sam_xdmac.h"
 #include "sam_periphclks.h"
 #include "sam_spi.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_xdmac.h"
-#include "chip/sam_spi.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_xdmac.h"
+#include "hardware/sam_spi.h"
+#include "hardware/sam_pinmap.h"
 
 #ifdef CONFIG_SAMV7_SPI_MASTER
 
diff --git a/arch/arm/src/samv7/sam_spi_slave.c b/arch/arm/src/samv7/sam_spi_slave.c
index 77a2cf67326..9206b4e4a50 100644
--- a/arch/arm/src/samv7/sam_spi_slave.c
+++ b/arch/arm/src/samv7/sam_spi_slave.c
@@ -59,8 +59,8 @@
 #include "sam_periphclks.h"
 #include "sam_spi.h"
 
-#include "chip/sam_spi.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_spi.h"
+#include "hardware/sam_pinmap.h"
 #include 
 
 #ifdef CONFIG_SAMV7_SPI_SLAVE
diff --git a/arch/arm/src/samv7/sam_ssc.c b/arch/arm/src/samv7/sam_ssc.c
index 78511b8f818..6e2c5c8d168 100644
--- a/arch/arm/src/samv7/sam_ssc.c
+++ b/arch/arm/src/samv7/sam_ssc.c
@@ -67,9 +67,9 @@
 #include "sam_xdmac.h"
 #include "sam_periphclks.h"
 #include "sam_ssc.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_ssc.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_ssc.h"
+#include "hardware/sam_pinmap.h"
 
 #if defined(CONFIG_SAMV7_SSC0) || defined(CONFIG_SAMV7_SSC1)
 
diff --git a/arch/arm/src/samv7/sam_ssc.h b/arch/arm/src/samv7/sam_ssc.h
index 0db57fe3615..fb4a6da4a2d 100644
--- a/arch/arm/src/samv7/sam_ssc.h
+++ b/arch/arm/src/samv7/sam_ssc.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/sam_ssc.h"
+#include "hardware/sam_ssc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/samv7/sam_start.c b/arch/arm/src/samv7/sam_start.c
index 94c8e7bef39..a1e111a368d 100644
--- a/arch/arm/src/samv7/sam_start.c
+++ b/arch/arm/src/samv7/sam_start.c
@@ -50,10 +50,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 #include "barriers.h"
-
-#ifdef CONFIG_ARCH_FPU
-#  include "nvic.h"
-#endif
+#include "nvic.h"
 
 #include "sam_clockconfig.h"
 #include "sam_mpuinit.h"
diff --git a/arch/arm/src/samv7/sam_systemreset.c b/arch/arm/src/samv7/sam_systemreset.c
index 14ff24ecda3..19ae8df8d5e 100644
--- a/arch/arm/src/samv7/sam_systemreset.c
+++ b/arch/arm/src/samv7/sam_systemreset.c
@@ -48,7 +48,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/sam_rstc.h"
+#include "hardware/sam_rstc.h"
 
 #ifdef CONFIG_SAMV7_SYSTEMRESET
 
diff --git a/arch/arm/src/samv7/sam_tc.c b/arch/arm/src/samv7/sam_tc.c
index e2b1961777f..535d3df5ad4 100644
--- a/arch/arm/src/samv7/sam_tc.c
+++ b/arch/arm/src/samv7/sam_tc.c
@@ -64,8 +64,8 @@
 
 #include "up_arch.h"
 #include "sam_periphclks.h"
-#include "chip/sam_pinmap.h"
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
 #include "sam_gpio.h"
 #include "sam_pck.h"
 #include "sam_tc.h"
diff --git a/arch/arm/src/samv7/sam_tc.h b/arch/arm/src/samv7/sam_tc.h
index d62ac212520..a2937cc925f 100644
--- a/arch/arm/src/samv7/sam_tc.h
+++ b/arch/arm/src/samv7/sam_tc.h
@@ -46,7 +46,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_tc.h"
+#include "hardware/sam_tc.h"
 
 #if defined(CONFIG_SAMV7_TC0) || defined(CONFIG_SAMV7_TC1) || \
     defined(CONFIG_SAMV7_TC2) || defined(CONFIG_SAMV7_TC3)
diff --git a/arch/arm/src/samv7/sam_trng.c b/arch/arm/src/samv7/sam_trng.c
index 824724ea1d6..d81bd71ec60 100644
--- a/arch/arm/src/samv7/sam_trng.c
+++ b/arch/arm/src/samv7/sam_trng.c
@@ -100,15 +100,13 @@ static struct trng_dev_s g_trngdev;
 
 static const struct file_operations g_trngops =
 {
-  0,               /* open */
-  0,               /* close */
+  NULL,            /* open */
+  NULL,            /* close */
   sam_read,        /* read */
-  0,               /* write */
-  0,               /* seek */
-  0                /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0              /* poll */
-#endif
+  NULL,            /* write */
+  NULL,            /* seek */
+  NULL,            /* ioctl */
+  NULL             /* poll */
 };
 
 /****************************************************************************
diff --git a/arch/arm/src/samv7/sam_trng.h b/arch/arm/src/samv7/sam_trng.h
index cd3c9f24b92..66fe9a54047 100644
--- a/arch/arm/src/samv7/sam_trng.h
+++ b/arch/arm/src/samv7/sam_trng.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_trng.h"
+#include "hardware/sam_trng.h"
 
 #if defined(CONFIG_DEV_RANDOM) && defined(CONFIG_SAMV7_TRNG)
 
diff --git a/arch/arm/src/samv7/sam_twihs.c b/arch/arm/src/samv7/sam_twihs.c
index d559f86ad4c..6dc4b139d6f 100644
--- a/arch/arm/src/samv7/sam_twihs.c
+++ b/arch/arm/src/samv7/sam_twihs.c
@@ -65,8 +65,8 @@
 
 #include "up_arch.h"
 
-#include "chip/sam_pmc.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_pinmap.h"
 
 #include "sam_periphclks.h"
 #include "sam_gpio.h"
diff --git a/arch/arm/src/samv7/sam_twihs.h b/arch/arm/src/samv7/sam_twihs.h
index abcaba9b7d2..afd928c09dc 100644
--- a/arch/arm/src/samv7/sam_twihs.h
+++ b/arch/arm/src/samv7/sam_twihs.h
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/sam_twihs.h"
+#include "hardware/sam_twihs.h"
 
 /****************************************************************************
  * Public Function Prototypes
diff --git a/arch/arm/src/samv7/sam_usbdev.h b/arch/arm/src/samv7/sam_usbdev.h
index 823871f1625..1c1fcef0908 100644
--- a/arch/arm/src/samv7/sam_usbdev.h
+++ b/arch/arm/src/samv7/sam_usbdev.h
@@ -47,7 +47,7 @@
 #include 
 #include 
 
-#include "chip/sam_usbhs.h"
+#include "hardware/sam_usbhs.h"
 
 /************************************************************************************
  * Public Functions
diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c
index 06fb0b66f8d..b474f334ec4 100644
--- a/arch/arm/src/samv7/sam_usbdevhs.c
+++ b/arch/arm/src/samv7/sam_usbdevhs.c
@@ -74,7 +74,7 @@
 
 #include "chip.h"
 #include "sam_periphclks.h"
-#include "chip/sam_usbhs.h"
+#include "hardware/sam_usbhs.h"
 #include "sam_clockconfig.h"
 #include "sam_usbdev.h"
 
diff --git a/arch/arm/src/samv7/sam_wdt.h b/arch/arm/src/samv7/sam_wdt.h
index 3fe31686caf..4241c6d0609 100644
--- a/arch/arm/src/samv7/sam_wdt.h
+++ b/arch/arm/src/samv7/sam_wdt.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/sam_wdt.h"
+#include "hardware/sam_wdt.h"
 
 #ifdef CONFIG_WATCHDOG
 
diff --git a/arch/arm/src/samv7/sam_xdmac.c b/arch/arm/src/samv7/sam_xdmac.c
index 44e43829f77..dcc6f3cef7a 100644
--- a/arch/arm/src/samv7/sam_xdmac.c
+++ b/arch/arm/src/samv7/sam_xdmac.c
@@ -56,8 +56,8 @@
 
 #include "sam_xdmac.h"
 #include "sam_periphclks.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_xdmac.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_xdmac.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/samv7/same70_periphclks.h b/arch/arm/src/samv7/same70_periphclks.h
index bf0dd59677f..a3e4cf16e43 100644
--- a/arch/arm/src/samv7/same70_periphclks.h
+++ b/arch/arm/src/samv7/same70_periphclks.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 #include 
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pmc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/samv7/samv71_periphclks.h b/arch/arm/src/samv7/samv71_periphclks.h
index 91f078fcbbd..c7df9def36e 100644
--- a/arch/arm/src/samv7/samv71_periphclks.h
+++ b/arch/arm/src/samv7/samv71_periphclks.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 #include 
-#include "chip/sam_pmc.h"
+#include "hardware/sam_pmc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig
index f52b820804f..0ed18256b07 100644
--- a/arch/arm/src/stm32/Kconfig
+++ b/arch/arm/src/stm32/Kconfig
@@ -566,45 +566,38 @@ config ARCH_CHIP_STM32F302K6
 	bool "STM32F302K6"
 	select STM32_STM32F30XX
 	select STM32_STM32F302
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_I2C3
 
 config ARCH_CHIP_STM32F302K8
 	bool "STM32F302K8"
 	select STM32_STM32F30XX
 	select STM32_STM32F302
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_I2C3
 
 config ARCH_CHIP_STM32F302C6
 	bool "STM32F302C6"
 	select STM32_STM32F30XX
 	select STM32_STM32F302
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F302C8
 	bool "STM32F302C8"
 	select STM32_STM32F30XX
 	select STM32_STM32F302
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F302R6
 	bool "STM32F302R6"
 	select STM32_STM32F30XX
 	select STM32_STM32F302
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F302R8
 	bool "STM32F302R8"
 	select STM32_STM32F30XX
 	select STM32_STM32F302
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F302CB
 	bool "STM32F302CB"
 	select STM32_STM32F30XX
 	select STM32_STM32F302
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC2
 	select STM32_HAVE_USART3
 
@@ -612,7 +605,6 @@ config ARCH_CHIP_STM32F302CC
 	bool "STM32F302CC"
 	select STM32_STM32F30XX
 	select STM32_STM32F302
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC2
 	select STM32_HAVE_USART3
 
@@ -620,7 +612,6 @@ config ARCH_CHIP_STM32F302RB
 	bool "STM32F302RB"
 	select STM32_STM32F30XX
 	select STM32_STM32F302
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC2
 	select STM32_HAVE_USART3
 	select STM32_HAVE_UART4
@@ -630,7 +621,6 @@ config ARCH_CHIP_STM32F302RC
 	bool "STM32F302RC"
 	select STM32_STM32F30XX
 	select STM32_STM32F302
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC2
 	select STM32_HAVE_USART3
 	select STM32_HAVE_UART4
@@ -640,7 +630,6 @@ config ARCH_CHIP_STM32F302VB
 	bool "STM32F302VB"
 	select STM32_STM32F30XX
 	select STM32_STM32F302
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC2
 	select STM32_HAVE_USART3
 	select STM32_HAVE_UART4
@@ -650,7 +639,6 @@ config ARCH_CHIP_STM32F302VC
 	bool "STM32F302VC"
 	select STM32_STM32F30XX
 	select STM32_STM32F302
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC2
 	select STM32_HAVE_USART3
 	select STM32_HAVE_UART4
@@ -660,21 +648,18 @@ config ARCH_CHIP_STM32F303K6
 	bool "STM32F303K6"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_DAC2
 
 config ARCH_CHIP_STM32F303K8
 	bool "STM32F303K8"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_DAC2
 
 config ARCH_CHIP_STM32F303C6
 	bool "STM32F303C6"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_DAC2
 	select STM32_HAVE_USART3
 
@@ -682,7 +667,6 @@ config ARCH_CHIP_STM32F303C8
 	bool "STM32F303C8"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_DAC2
 	select STM32_HAVE_USART3
 
@@ -690,7 +674,6 @@ config ARCH_CHIP_STM32F303CB
 	bool "STM32F303CB"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC3
 	select STM32_HAVE_ADC4
 	select STM32_HAVE_I2C2
@@ -705,7 +688,6 @@ config ARCH_CHIP_STM32F303CC
 	bool "STM32F303CC"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC3
 	select STM32_HAVE_ADC4
 	select STM32_HAVE_I2C2
@@ -720,7 +702,6 @@ config ARCH_CHIP_STM32F303RB
 	bool "STM32F303RB"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC3
 	select STM32_HAVE_ADC4
 	select STM32_HAVE_I2C2
@@ -737,7 +718,6 @@ config ARCH_CHIP_STM32F303RC
 	bool "STM32F303RC"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC3
 	select STM32_HAVE_ADC4
 	select STM32_HAVE_I2C2
@@ -754,7 +734,6 @@ config ARCH_CHIP_STM32F303RD
 	bool "STM32F303RD"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC3
 	select STM32_HAVE_ADC4
 	select STM32_HAVE_I2C2
@@ -773,7 +752,6 @@ config ARCH_CHIP_STM32F303RE
 	bool "STM32F303RE"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC3
 	select STM32_HAVE_ADC4
 	select STM32_HAVE_I2C2
@@ -792,7 +770,6 @@ config ARCH_CHIP_STM32F303VB
 	bool "STM32F303VB"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC3
 	select STM32_HAVE_ADC4
 	select STM32_HAVE_I2C2
@@ -809,7 +786,6 @@ config ARCH_CHIP_STM32F303VC
 	bool "STM32F303VC"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC3
 	select STM32_HAVE_ADC4
 	select STM32_HAVE_I2C2
@@ -826,7 +802,6 @@ config ARCH_CHIP_STM32F303RD
 	bool "STM32F303RD"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC3
 	select STM32_HAVE_ADC4
 	select STM32_HAVE_USART3
@@ -835,7 +810,6 @@ config ARCH_CHIP_STM32F303RE
 	bool "STM32F303RE"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC3
 	select STM32_HAVE_ADC4
 	select STM32_HAVE_USART3
@@ -844,7 +818,6 @@ config ARCH_CHIP_STM32F303VD
 	bool "STM32F303VD"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC3
 	select STM32_HAVE_ADC4
 	select STM32_HAVE_USART3
@@ -853,7 +826,6 @@ config ARCH_CHIP_STM32F303VE
 	bool "STM32F303VE"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC3
 	select STM32_HAVE_ADC4
 	select STM32_HAVE_USART3
@@ -862,7 +834,6 @@ config ARCH_CHIP_STM32F303ZD
 	bool "STM32F303ZD"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC3
 	select STM32_HAVE_ADC4
 	select STM32_HAVE_USART3
@@ -871,7 +842,6 @@ config ARCH_CHIP_STM32F303ZE
 	bool "STM32F303ZE"
 	select STM32_STM32F30XX
 	select STM32_STM32F303
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC3
 	select STM32_HAVE_ADC4
 	select STM32_HAVE_USART3
@@ -879,137 +849,110 @@ config ARCH_CHIP_STM32F303ZE
 config ARCH_CHIP_STM32F334K4
 	bool "STM32F334K4"
 	select STM32_STM32F33XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F334K6
 	bool "STM32F334K6"
 	select STM32_STM32F33XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F334K8
 	bool "STM32F334K8"
 	select STM32_STM32F33XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F334C4
 	bool "STM32F334C4"
 	select STM32_STM32F33XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F334C6
 	bool "STM32F334C6"
 	select STM32_STM32F33XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F334C8
 	bool "STM32F334C8"
 	select STM32_STM32F33XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F334R4
 	bool "STM32F334R4"
 	select STM32_STM32F33XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F334R6
 	bool "STM32F334R6"
 	select STM32_STM32F33XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F334R8
 	bool "STM32F334R8"
 	select STM32_STM32F33XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F372C8
 	bool "STM32F372C8"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F372R8
 	bool "STM32F372R8"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F372V8
 	bool "STM32F372V8"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F372CB
 	bool "STM32F372CB"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F372RB
 	bool "STM32F372RB"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F372VB
 	bool "STM32F372VB"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F372CC
 	bool "STM32F372CC"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F372RC
 	bool "STM32F372RC"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F372VC
 	bool "STM32F372VC"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F373C8
 	bool "STM32F373C8"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F373R8
 	bool "STM32F373R8"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F373V8
 	bool "STM32F373V8"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F373CB
 	bool "STM32F373CB"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F373RB
 	bool "STM32F373RB"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F373VB
 	bool "STM32F373VB"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F373CC
 	bool "STM32F373CC"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F373RC
 	bool "STM32F373RC"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F373VC
 	bool "STM32F373VC"
 	select STM32_STM32F37XX
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F401CB
 	bool "STM32F401CB"
@@ -1063,171 +1006,143 @@ config ARCH_CHIP_STM32F410RB
 	bool "STM32F410RB"
 	select STM32_STM32F4XXX
 	select STM32_STM32F410
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F411RE
 	bool "STM32F411RE"
 	select STM32_STM32F4XXX
 	select STM32_STM32F411
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F411VE
 	bool "STM32F411VE"
 	select STM32_STM32F4XXX
 	select STM32_STM32F411
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F405RG
 	bool "STM32F405RG"
 	select STM32_STM32F4XXX
 	select STM32_STM32F405
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F405VG
 	bool "STM32F405VG"
 	select STM32_STM32F4XXX
 	select STM32_STM32F405
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F405ZG
 	bool "STM32F405ZG"
 	select STM32_STM32F4XXX
 	select STM32_STM32F405
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F407VE
 	bool "STM32F407VE"
 	select STM32_STM32F4XXX
 	select STM32_STM32F407
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F407VG
 	bool "STM32F407VG"
 	select STM32_STM32F4XXX
 	select STM32_STM32F407
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F407ZE
 	bool "STM32F407ZE"
 	select STM32_STM32F4XXX
 	select STM32_STM32F407
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F407ZG
 	bool "STM32F407ZG"
 	select STM32_STM32F4XXX
 	select STM32_STM32F407
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F407IE
 	bool "STM32F407IE"
 	select STM32_STM32F4XXX
 	select STM32_STM32F407
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F407IG
 	bool "STM32F407IG"
 	select STM32_STM32F4XXX
 	select STM32_STM32F407
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F427V
 	bool "STM32F427V"
 	select STM32_STM32F4XXX
 	select STM32_STM32F427
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F427Z
 	bool "STM32F427Z"
 	select STM32_STM32F4XXX
 	select STM32_STM32F427
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F427I
 	bool "STM32F427I"
 	select STM32_STM32F4XXX
 	select STM32_STM32F427
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F429V
 	bool "STM32F429V"
 	select STM32_STM32F4XXX
 	select STM32_STM32F429
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F429Z
 	bool "STM32F429Z"
 	select STM32_STM32F4XXX
 	select STM32_STM32F429
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F429I
 	bool "STM32F429I"
 	select STM32_STM32F4XXX
 	select STM32_STM32F429
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F429B
 	bool "STM32F429B"
 	select STM32_STM32F4XXX
 	select STM32_STM32F429
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F429N
 	bool "STM32F429N"
 	select STM32_STM32F4XXX
 	select STM32_STM32F429
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F446M
 	bool "STM32F446M"
 	select STM32_STM32F4XXX
 	select STM32_STM32F446
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F446R
 	bool "STM32F446R"
 	select STM32_STM32F4XXX
 	select STM32_STM32F446
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F446V
 	bool "STM32F446V"
 	select STM32_STM32F4XXX
 	select STM32_STM32F446
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F446Z
 	bool "STM32F446Z"
 	select STM32_STM32F4XXX
 	select STM32_STM32F446
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F469A
 	bool "STM32F469A"
 	select STM32_STM32F4XXX
 	select STM32_STM32F469
-	select ARCH_HAVE_FPU
 
 config ARCH_CHIP_STM32F469I
 	bool "STM32F469I"
 	select STM32_STM32F4XXX
 	select STM32_STM32F469
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ETHMAC
 
 config ARCH_CHIP_STM32F469B
 	bool "STM32F469B"
 	select STM32_STM32F4XXX
 	select STM32_STM32F469
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ETHMAC
 
 config ARCH_CHIP_STM32F469N
 	bool "STM32F469N"
 	select STM32_STM32F4XXX
 	select STM32_STM32F469
-	select ARCH_HAVE_FPU
 	select STM32_HAVE_ETHMAC
 
 endchoice
@@ -1325,6 +1240,7 @@ config STM32_STM32L15XX
 	select STM32_HAVE_IP_TIMERS_V1
 	select STM32_HAVE_IP_ADC_V1
 	select STM32_HAVE_IP_DMA_V1
+	select STM32_HAVE_IP_I2C_V1
 
 config STM32_ENERGYLITE
 	bool
@@ -1343,6 +1259,7 @@ config STM32_STM32F10XX
 	select STM32_HAVE_IP_TIMERS_V1
 	select STM32_HAVE_IP_ADC_V1_BASIC
 	select STM32_HAVE_IP_DMA_V1
+	select STM32_HAVE_IP_I2C_V1
 
 config STM32_VALUELINE
 	bool
@@ -1404,6 +1321,10 @@ config STM32_USBACCESSLINE
 	select STM32_HAVE_USART3
 	select STM32_HAVE_SPI2
 
+config STM32_MEDIUMPLUSDENSITY
+	bool
+	default n
+
 config STM32_HIGHDENSITY
 	bool
 	default n
@@ -1453,14 +1374,7 @@ config STM32_STM32F20XX
 	bool
 	default n
 	select ARCH_CORTEXM3
-	select STM32_HAVE_IOCOMPENSATION
-	select STM32_HAVE_IP_TIMERS_V1
-	select STM32_HAVE_IP_ADC_V1
-	select STM32_HAVE_IP_DMA_V2
-
-config STM32_STM32F205
-	bool
-	default n
+	select STM32_HAVE_CRYP
 	select STM32_HAVE_OTGFS
 	select STM32_HAVE_OTGHS
 	select STM32_HAVE_USART3
@@ -1482,53 +1396,35 @@ config STM32_STM32F205
 	select STM32_HAVE_TIM14
 	select STM32_HAVE_ADC2
 	select STM32_HAVE_ADC3
-	select STM32_HAVE_CAN1
-	select STM32_HAVE_CAN2
 	select STM32_HAVE_DAC1
 	select STM32_HAVE_I2C2
 	select STM32_HAVE_I2C3
+	select STM32_HAVE_CAN1
+	select STM32_HAVE_CAN2
 	select STM32_HAVE_RNG
 	select STM32_HAVE_SPI2
 	select STM32_HAVE_SPI3
+	select STM32_HAVE_IOCOMPENSATION
+	select STM32_HAVE_IP_TIMERS_V1
+	select STM32_HAVE_IP_ADC_V1
+	select STM32_HAVE_IP_DMA_V2
+	select STM32_HAVE_IP_I2C_V1
+
+config STM32_STM32F205
+	bool
+	default n
 
 config STM32_STM32F207
 	bool
 	default n
-	select STM32_HAVE_OTGFS
 	select STM32_HAVE_FSMC
-	select STM32_HAVE_USART3
-	select STM32_HAVE_UART4
-	select STM32_HAVE_UART5
-	select STM32_HAVE_USART6
-	select STM32_HAVE_TIM1
-	select STM32_HAVE_TIM3
-	select STM32_HAVE_TIM4
-	select STM32_HAVE_TIM5
-	select STM32_HAVE_TIM6
-	select STM32_HAVE_TIM7
-	select STM32_HAVE_TIM8
-	select STM32_HAVE_TIM9
-	select STM32_HAVE_TIM10
-	select STM32_HAVE_TIM11
-	select STM32_HAVE_TIM12
-	select STM32_HAVE_TIM13
-	select STM32_HAVE_TIM14
-	select STM32_HAVE_ADC2
-	select STM32_HAVE_ADC3
-	select STM32_HAVE_CAN1
-	select STM32_HAVE_CAN2
-	select STM32_HAVE_DAC1
-	select STM32_HAVE_I2C2
-	select STM32_HAVE_I2C3
-	select STM32_HAVE_RNG
 	select STM32_HAVE_ETHMAC
-	select STM32_HAVE_SPI2
-	select STM32_HAVE_SPI3
 
 config STM32_STM32F30XX
 	bool
 	default n
 	select ARCH_CORTEXM4
+	select ARCH_HAVE_FPU
 	select STM32_HAVE_ADC1_DMA
 	select STM32_HAVE_CAN1
 	select STM32_HAVE_DAC1
@@ -1538,9 +1434,11 @@ config STM32_STM32F30XX
 	select STM32_HAVE_TIM15
 	select STM32_HAVE_TIM16
 	select STM32_HAVE_TIM17
+	select STM32_HAVE_TSC
 	select STM32_HAVE_IP_TIMERS_V2
 	select STM32_HAVE_IP_ADC_V2
 	select STM32_HAVE_IP_DMA_V1
+	select STM32_HAVE_IP_I2C_V2
 
 config STM32_STM32F302
 	bool
@@ -1565,6 +1463,7 @@ config STM32_STM32F33XX
 	bool
 	default n
 	select ARCH_CORTEXM4
+	select ARCH_HAVE_FPU
 	select STM32_HAVE_HRTIM1
 	select STM32_HAVE_COMP2
 	select STM32_HAVE_COMP4
@@ -1577,6 +1476,7 @@ config STM32_STM32F33XX
 	select STM32_HAVE_TIM15
 	select STM32_HAVE_TIM16
 	select STM32_HAVE_TIM17
+	select STM32_HAVE_TSC
 	select STM32_HAVE_ADC2
 	select STM32_HAVE_ADC1_DMA
 	select STM32_HAVE_ADC2_DMA
@@ -1587,11 +1487,13 @@ config STM32_STM32F33XX
 	select STM32_HAVE_IP_TIMERS_V2
 	select STM32_HAVE_IP_ADC_V2
 	select STM32_HAVE_IP_DMA_V1
+	select STM32_HAVE_IP_I2C_V2
 
 config STM32_STM32F37XX
 	bool
 	default n
 	select ARCH_CORTEXM4
+	select ARCH_HAVE_FPU
 	select STM32_HAVE_USBDEV
 	select STM32_HAVE_TIM3
 	select STM32_HAVE_TIM4
@@ -1601,6 +1503,7 @@ config STM32_STM32F37XX
 	select STM32_HAVE_TIM15
 	select STM32_HAVE_TIM16
 	select STM32_HAVE_TIM17
+	select STM32_HAVE_TSC
 	select STM32_HAVE_SDADC1
 	select STM32_HAVE_SDADC2
 	select STM32_HAVE_SDADC3
@@ -1614,17 +1517,21 @@ config STM32_STM32F37XX
 	select STM32_HAVE_IP_TIMERS_V1
 	select STM32_HAVE_IP_ADC_V1_BASIC
 	select STM32_HAVE_IP_DMA_V1
+	select STM32_HAVE_IP_I2C_V2
 
 config STM32_STM32F4XXX
 	bool
 	default n
 	select ARCH_CORTEXM4
+	select ARCH_HAVE_FPU
+	select STM32_HAVE_CRYP
 	select STM32_HAVE_SPI2
 	select STM32_HAVE_I2C2
 	select STM32_HAVE_IOCOMPENSATION
 	select STM32_HAVE_IP_TIMERS_V1
 	select STM32_HAVE_IP_ADC_V1
 	select STM32_HAVE_IP_DMA_V2
+	select STM32_HAVE_IP_I2C_V1
 
 config STM32_STM32F401xBC
 	bool
@@ -1640,7 +1547,6 @@ config STM32_STM32F401
 	bool
 	default n
 	select ARCH_CORTEXM4
-	select ARCH_HAVE_FPU
 	select STM32_STM32F4XXX
 	select STM32_HAVE_USART6
 	select STM32_HAVE_TIM1
@@ -1760,7 +1666,7 @@ config STM32_STM32F407
 config STM32_STM32F427
 	bool
 	default n
-	select STM32_HAVE_FSMC
+	select STM32_HAVE_FMC
 	select STM32_HAVE_CCM
 	select STM32_HAVE_USART3
 	select STM32_HAVE_UART4
@@ -1802,7 +1708,7 @@ config STM32_STM32F427
 config STM32_STM32F429
 	bool
 	default n
-	select STM32_HAVE_FSMC
+	select STM32_HAVE_FMC
 	select STM32_HAVE_LTDC
 	select STM32_HAVE_CCM
 	select STM32_HAVE_USART3
@@ -1880,7 +1786,7 @@ config STM32_STM32F446
 config STM32_STM32F469
 	bool
 	default n
-	select STM32_HAVE_FSMC
+	select STM32_HAVE_FMC
 	select STM32_HAVE_LTDC
 	select STM32_HAVE_CCM
 	select STM32_HAVE_USART3
@@ -1932,6 +1838,14 @@ menu "STM32 Peripheral Support"
 # These "hidden" settings determine is a peripheral option is available for the
 # selection MCU
 
+config STM32_HAVE_AES
+	bool
+	default n
+
+config STM32_HAVE_CRYP
+	bool
+	default n
+
 config STM32_HAVE_CCM
 	bool
 	default n
@@ -1944,6 +1858,10 @@ config STM32_HAVE_OTGFS
 	bool
 	default n
 
+config STM32_HAVE_FMC
+	bool
+	default n
+
 config STM32_HAVE_FSMC
 	bool
 	default n
@@ -2052,6 +1970,10 @@ config STM32_HAVE_TIM17
 	bool
 	default n
 
+config STM32_HAVE_TSC
+	bool
+	default n
+
 config STM32_HAVE_ADC2
 	bool
 	default n
@@ -2214,6 +2136,14 @@ config STM32_HAVE_OPAMP4
 
 # These are STM32 peripherals IP blocks
 
+config STM32_HAVE_IP_I2C_V1
+	bool
+	default n
+
+config STM32_HAVE_IP_I2C_V2
+	bool
+	default n
+
 config STM32_HAVE_IP_DMA_V1
 	bool
 	default n
@@ -2390,7 +2320,7 @@ config STM32_CRC
 config STM32_CRYP
 	bool "CRYP"
 	default n
-	depends on STM32_STM32F20XX || STM32_STM32F4XXX
+	depends on STM32_HAVE_CRYP
 
 config STM32_DMA1
 	bool "DMA1"
@@ -2452,6 +2382,11 @@ config STM32_FSMC
 	default n
 	depends on STM32_HAVE_FSMC
 
+config STM32_FMC
+	bool "FMC"
+	default n
+	depends on STM32_HAVE_FMC
+
 config STM32_HASH
 	bool "HASH"
 	default n
@@ -2763,7 +2698,7 @@ config STM32_TIM17
 config STM32_TSC
 	bool "TSC"
 	default n
-	depends on STM32_STM32F30XX
+	depends on STM32_HAVE_TSC
 
 config STM32_USART1
 	bool "USART1"
@@ -3180,13 +3115,13 @@ config STM32_DMACAPABLE
 		Drivers then may use this information to determine if they should
 		attempt the DMA or fall back to a different transfer method.
 
-config STM32_FSMC_SRAM
-	bool "External SRAM on FSMC"
+config STM32_EXTERNAL_RAM
+	bool "External RAM on FSMC/FMC"
 	default n
-	depends on STM32_FSMC
+	depends on STM32_FSMC || STM32_FMC
 	select ARCH_HAVE_HEAP2
 	---help---
-		In addition to internal SRAM, SRAM may also be available through the FSMC.
+		In addition to internal SRAM, external RAM may be available through the FSMC/FMC.
 
 menu "Timer Configuration"
 	depends on STM32_TIM
@@ -3299,11 +3234,11 @@ if STM32_TIM1_CHANNEL1
 
 config STM32_TIM1_CH1MODE
 	int "TIM1 Channel 1 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM1_CH1OUT
 	bool "TIM1 Channel 1 Output"
@@ -3329,11 +3264,11 @@ if STM32_TIM1_CHANNEL2
 
 config STM32_TIM1_CH2MODE
 	int "TIM1 Channel 2 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM1_CH2OUT
 	bool "TIM1 Channel 2 Output"
@@ -3359,11 +3294,11 @@ if STM32_TIM1_CHANNEL3
 
 config STM32_TIM1_CH3MODE
 	int "TIM1 Channel 3 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM1_CH3OUT
 	bool "TIM1 Channel 3 Output"
@@ -3389,11 +3324,11 @@ if STM32_TIM1_CHANNEL4
 
 config STM32_TIM1_CH4MODE
 	int "TIM1 Channel 4 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM1_CH4OUT
 	bool "TIM1 Channel 4 Output"
@@ -3414,10 +3349,10 @@ if STM32_TIM1_CHANNEL5
 
 config STM32_TIM1_CH5MODE
 	int "TIM1 Channel 5 Mode"
-	default 0
-	range 0 5
+	default 6
+	range 0 11
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM1_CH5OUT
 	bool "TIM1 Channel 5 Output"
@@ -3438,10 +3373,10 @@ if STM32_TIM1_CHANNEL6
 
 config STM32_TIM1_CH6MODE
 	int "TIM1 Channel 6 Mode"
-	default 0
-	range 0 5
+	default 6
+	range 0 11
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM1_CH6OUT
 	bool "TIM1 Channel 6 Output"
@@ -3523,11 +3458,11 @@ endif # STM32_TIM1_CHANNEL = 4
 
 config STM32_TIM1_CHMODE
 	int "TIM1 Channel Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 endif # !STM32_PWM_MULTICHAN
 
@@ -3568,11 +3503,11 @@ if STM32_TIM2_CHANNEL1
 
 config STM32_TIM2_CH1MODE
 	int "TIM2 Channel 1 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM2_CH1OUT
 	bool "TIM2 Channel 1 Output"
@@ -3592,11 +3527,11 @@ if STM32_TIM2_CHANNEL2
 
 config STM32_TIM2_CH2MODE
 	int "TIM2 Channel 2 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM2_CH2OUT
 	bool "TIM2 Channel 2 Output"
@@ -3616,11 +3551,11 @@ if STM32_TIM2_CHANNEL3
 
 config STM32_TIM2_CH3MODE
 	int "TIM2 Channel 3 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM2_CH3OUT
 	bool "TIM2 Channel 3 Output"
@@ -3640,11 +3575,11 @@ if STM32_TIM2_CHANNEL4
 
 config STM32_TIM2_CH4MODE
 	int "TIM2 Channel 4 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM2_CH4OUT
 	bool "TIM2 Channel 4 Output"
@@ -3708,11 +3643,11 @@ endif # STM32_TIM2_CHANNEL = 4
 
 config STM32_TIM2_CHMODE
 	int "TIM2 Channel Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 endif # !STM32_PWM_MULTICHAN
 
@@ -3753,11 +3688,11 @@ if STM32_TIM3_CHANNEL1
 
 config STM32_TIM3_CH1MODE
 	int "TIM3 Channel 1 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM3_CH1OUT
 	bool "TIM3 Channel 1 Output"
@@ -3777,11 +3712,11 @@ if STM32_TIM3_CHANNEL2
 
 config STM32_TIM3_CH2MODE
 	int "TIM3 Channel 2 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM3_CH2OUT
 	bool "TIM3 Channel 2 Output"
@@ -3801,11 +3736,11 @@ if STM32_TIM3_CHANNEL3
 
 config STM32_TIM3_CH3MODE
 	int "TIM3 Channel 3 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM3_CH3OUT
 	bool "TIM3 Channel 3 Output"
@@ -3825,11 +3760,11 @@ if STM32_TIM3_CHANNEL4
 
 config STM32_TIM3_CH4MODE
 	int "TIM3 Channel 4 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM3_CH4OUT
 	bool "TIM3 Channel 4 Output"
@@ -3893,11 +3828,11 @@ endif # STM32_TIM3_CHANNEL = 4
 
 config STM32_TIM3_CHMODE
 	int "TIM3 Channel Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 endif # !STM32_PWM_MULTICHAN
 
@@ -3938,11 +3873,11 @@ if STM32_TIM4_CHANNEL1
 
 config STM32_TIM4_CH1MODE
 	int "TIM4 Channel 1 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM4_CH1OUT
 	bool "TIM4 Channel 1 Output"
@@ -3962,11 +3897,11 @@ if STM32_TIM4_CHANNEL2
 
 config STM32_TIM4_CH2MODE
 	int "TIM4 Channel 2 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM4_CH2OUT
 	bool "TIM4 Channel 2 Output"
@@ -3986,11 +3921,11 @@ if STM32_TIM4_CHANNEL3
 
 config STM32_TIM4_CH3MODE
 	int "TIM4 Channel 3 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM4_CH3OUT
 	bool "TIM4 Channel 3 Output"
@@ -4010,11 +3945,11 @@ if STM32_TIM4_CHANNEL4
 
 config STM32_TIM4_CH4MODE
 	int "TIM4 Channel 4 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM4_CH4OUT
 	bool "TIM4 Channel 4 Output"
@@ -4078,11 +4013,11 @@ endif # STM32_TIM4_CHANNEL = 4
 
 config STM32_TIM4_CHMODE
 	int "TIM4 Channel Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 endif # !STM32_PWM_MULTICHAN
 
@@ -4123,11 +4058,11 @@ if STM32_TIM5_CHANNEL1
 
 config STM32_TIM5_CH1MODE
 	int "TIM5 Channel 1 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM5_CH1OUT
 	bool "TIM5 Channel 1 Output"
@@ -4147,11 +4082,11 @@ if STM32_TIM5_CHANNEL2
 
 config STM32_TIM5_CH2MODE
 	int "TIM5 Channel 2 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM5_CH2OUT
 	bool "TIM5 Channel 2 Output"
@@ -4171,11 +4106,11 @@ if STM32_TIM5_CHANNEL3
 
 config STM32_TIM5_CH3MODE
 	int "TIM5 Channel 3 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM5_CH3OUT
 	bool "TIM5 Channel 3 Output"
@@ -4195,11 +4130,11 @@ if STM32_TIM5_CHANNEL4
 
 config STM32_TIM5_CH4MODE
 	int "TIM5 Channel 4 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM5_CH4OUT
 	bool "TIM5 Channel 4 Output"
@@ -4263,11 +4198,11 @@ endif # STM32_TIM5_CHANNEL = 4
 
 config STM32_TIM5_CHMODE
 	int "TIM5 Channel Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 endif # !STM32_PWM_MULTICHAN
 
@@ -4329,11 +4264,17 @@ if STM32_TIM8_CHANNEL1
 
 config STM32_TIM8_CH1MODE
 	int "TIM8 Channel 1 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32_TIM8_CH1OUT
+        bool "TIM8 Channel 1 Output"
+        default n
+        ---help---
+                Enables channel 1 output.
 
 config STM32_TIM8_CH1NOUT
 	bool "TIM8 Channel 1 Complementary Output"
@@ -4353,11 +4294,11 @@ if STM32_TIM8_CHANNEL2
 
 config STM32_TIM8_CH2MODE
 	int "TIM8 Channel 2 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM8_CH2OUT
 	bool "TIM8 Channel 2 Output"
@@ -4383,11 +4324,11 @@ if STM32_TIM8_CHANNEL3
 
 config STM32_TIM8_CH3MODE
 	int "TIM8 Channel 3 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM8_CH3OUT
 	bool "TIM8 Channel 3 Output"
@@ -4413,11 +4354,11 @@ if STM32_TIM8_CHANNEL4
 
 config STM32_TIM8_CH4MODE
 	int "TIM8 Channel 4 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM8_CH4OUT
 	bool "TIM8 Channel 4 Output"
@@ -4438,10 +4379,10 @@ if STM32_TIM8_CHANNEL5
 
 config STM32_TIM8_CH5MODE
 	int "TIM8 Channel 5 Mode"
-	default 0
-	range 0 5
+	default 6
+	range 0 11
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM8_CH5OUT
 	bool "TIM8 Channel 5 Output"
@@ -4462,10 +4403,10 @@ if STM32_TIM8_CHANNEL6
 
 config STM32_TIM8_CH6MODE
 	int "TIM8 Channel 6 Mode"
-	default 0
-	range 0 5
+	default 6
+	range 0 11
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM8_CH6OUT
 	bool "TIM8 Channel 6 Output"
@@ -4547,11 +4488,11 @@ endif # STM32_TIM8_CHANNEL = 4
 
 config STM32_TIM8_CHMODE
 	int "TIM8 Channel Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 endif # !STM32_PWM_MULTICHAN
 
@@ -4585,11 +4526,11 @@ if STM32_TIM9_CHANNEL1
 
 config STM32_TIM9_CH1MODE
 	int "TIM9 Channel 1 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM9_CH1OUT
 	bool "TIM9 Channel 1 Output"
@@ -4609,11 +4550,11 @@ if STM32_TIM9_CHANNEL2
 
 config STM32_TIM9_CH2MODE
 	int "TIM9 Channel 2 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM9_CH2OUT
 	bool "TIM9 Channel 2 Output"
@@ -4657,11 +4598,11 @@ endif # STM32_TIM9_CHANNEL = 2
 
 config STM32_TIM9_CHMODE
 	int "TIM9 Channel Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 endif # !STM32_PWM_MULTICHAN
 
@@ -4695,11 +4636,11 @@ if STM32_TIM10_CHANNEL1
 
 config STM32_TIM10_CH1MODE
 	int "TIM10 Channel 1 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM10_CH1OUT
 	bool "TIM10 Channel 1 Output"
@@ -4733,11 +4674,11 @@ endif # STM32_TIM10_CHANNEL = 1
 
 config STM32_TIM10_CHMODE
 	int "TIM10 Channel Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 endif # !STM32_PWM_MULTICHAN
 
@@ -4771,11 +4712,11 @@ if STM32_TIM11_CHANNEL1
 
 config STM32_TIM11_CH1MODE
 	int "TIM11 Channel 1 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM11_CH1OUT
 	bool "TIM11 Channel 1 Output"
@@ -4809,11 +4750,11 @@ endif # STM32_TIM11_CHANNEL = 1
 
 config STM32_TIM11_CHMODE
 	int "TIM11 Channel Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 endif # !STM32_PWM_MULTICHAN
 
@@ -4847,11 +4788,11 @@ if STM32_TIM12_CHANNEL1
 
 config STM32_TIM12_CH1MODE
 	int "TIM12 Channel 1 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM12_CH1OUT
 	bool "TIM12 Channel 1 Output"
@@ -4871,11 +4812,11 @@ if STM32_TIM12_CHANNEL2
 
 config STM32_TIM12_CH2MODE
 	int "TIM12 Channel 2 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM12_CH2OUT
 	bool "TIM12 Channel 2 Output"
@@ -4897,7 +4838,7 @@ config STM32_TIM12_CHANNEL
 		If TIM12 is enabled for PWM usage, you also need specifies the timer output
 		channel {1,2}
 
-if STM32_TIM9_CHANNEL = 1
+if STM32_TIM12_CHANNEL = 1
 
 config STM32_TIM12_CH1OUT
 	bool "TIM12 Channel 1 Output"
@@ -4919,11 +4860,11 @@ endif # STM32_TIM12_CHANNEL = 2
 
 config STM32_TIM12_CHMODE
 	int "TIM12 Channel Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 endif # !STM32_PWM_MULTICHAN
 
@@ -4957,11 +4898,11 @@ if STM32_TIM13_CHANNEL1
 
 config STM32_TIM13_CH1MODE
 	int "TIM13 Channel 1 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM13_CH1OUT
 	bool "TIM13 Channel 1 Output"
@@ -4983,7 +4924,7 @@ config STM32_TIM13_CHANNEL
 		If TIM13 is enabled for PWM usage, you also need specifies the timer output
 		channel {1}
 
-if STM32_TIM14_CHANNEL = 1
+if STM32_TIM13_CHANNEL = 1
 
 config STM32_TIM13_CH1OUT
 	bool "TIM13 Channel 1 Output"
@@ -4995,11 +4936,11 @@ endif # STM32_TIM13_CHANNEL = 1
 
 config STM32_TIM13_CHMODE
 	int "TIM13 Channel Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 endif # !STM32_PWM_MULTICHAN
 
@@ -5033,11 +4974,11 @@ if STM32_TIM14_CHANNEL1
 
 config STM32_TIM14_CH1MODE
 	int "TIM14 Channel 1 Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM14_CH1OUT
 	bool "TIM14 Channel 1 Output"
@@ -5071,11 +5012,11 @@ endif # STM32_TIM14_CHANNEL = 1
 
 config STM32_TIM14_CHMODE
 	int "TIM14 Channel Mode"
-	default 0
-	range 0 5 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 11 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 endif # !STM32_PWM_MULTICHAN
 
@@ -5129,11 +5070,11 @@ if STM32_TIM15_CHANNEL1
 
 config STM32_TIM15_CH1MODE
 	int "TIM15 Channel 1 Mode"
-	default 0
-	range 0 3 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 9 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM15_CH1OUT
 	bool "TIM15 Channel 1 Output"
@@ -5159,11 +5100,11 @@ if STM32_TIM15_CHANNEL2
 
 config STM32_TIM15_CH2MODE
 	int "TIM15 Channel 2 Mode"
-	default 0
-	range 0 3 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 9 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM15_CH2OUT
 	bool "TIM15 Channel 2 Output"
@@ -5219,11 +5160,11 @@ endif # STM32_TIM15_CHANNEL = 2
 
 config STM32_TIM15_CHMODE
 	int "TIM15 Channel Mode"
-	default 0
-	range 0 3 if STM32_HAVE_IP_TIMERS_V2
-	range 0 1 if !STM32_HAVE_IP_TIMERS_V2
+	default 6
+	range 0 9 if STM32_HAVE_IP_TIMERS_V2
+	range 0 7 if !STM32_HAVE_IP_TIMERS_V2
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 endif # !STM32_PWM_MULTICHAN
 
@@ -5277,10 +5218,10 @@ if STM32_TIM16_CHANNEL1
 
 config STM32_TIM16_CH1MODE
 	int "TIM16 Channel 1 Mode"
-	default 0
-	range 0 1
+	default 6
+	range 0 7
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM16_CH1OUT
 	bool "TIM16 Channel 1 Output"
@@ -5314,10 +5255,10 @@ endif # STM32_TIM16_CHANNEL = 1
 
 config STM32_TIM16_CHMODE
 	int "TIM16 Channel Mode"
-	default 0
-	range 0 1
+	default 6
+	range 0 7
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 endif # !STM32_PWM_MULTICHAN
 
@@ -5371,10 +5312,10 @@ if STM32_TIM17_CHANNEL1
 
 config STM32_TIM17_CH1MODE
 	int "TIM17 Channel 1 Mode"
-	default 0
-	range 0 1
+	default 6
+	range 0 7
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 config STM32_TIM17_CH1OUT
 	bool "TIM17 Channel 1 Output"
@@ -5408,10 +5349,10 @@ endif # STM32_TIM17_CHANNEL = 1
 
 config STM32_TIM17_CHMODE
 	int "TIM17 Channel Mode"
-	default 0
-	range 0 1
+	default 6
+	range 0 7
 	---help---
-		Specifies the channel mode.
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
 
 endif # !STM32_PWM_MULTICHAN
 
@@ -5433,38 +5374,6 @@ config STM32_PWM_TRGO
 	---help---
 		Enable TRGO support for PWM driver
 
-config STM32_TIM1_PWM_ADC
-	bool "TIM1 PWM ADC "
-	default n
-	depends on STM32_TIM1 && STM32_ADC && STM32_TIM1_PWM
-	---help---
-		ADC trigger with TIM1 configured as PWM source
-
-choice
-	prompt "Select TIM1 PWM ADC channel"
-	default STM32_TIM1_PWM_ADC1
-	depends on STM32_TIM1_PWM_ADC
-
-config STM32_TIM1_PWM_ADC1
-	bool "TIM1 PWM ADC1"
-	depends on STM32_ADC1
-	---help---
-		Trigger ADC1 with PWM configured TIM1
-
-config STM32_TIM1_PWM_ADC2
-	bool "TIM1 PWM ADC2"
-	depends on STM32_ADC2
-	---help---
-		Trigger ADC2 with PWM configured TIM1
-
-config STM32_TIM1_PWM_ADC3
-	bool "TIM1 PWM ADC3"
-	depends on STM32_ADC3
-	---help---
-		Trigger ADC3 with PWM configured TIM1
-
-endchoice
-
 config STM32_TIM1_ADC
 	bool "TIM1 ADC"
 	default n
@@ -5726,6 +5635,9 @@ config STM32_HAVE_ADC2_TIMER
 config STM32_HAVE_ADC3_TIMER
 	bool
 
+config STM32_HAVE_ADC4_TIMER
+	bool
+
 config STM32_ADC1_SAMPLE_FREQUENCY
 	int "ADC1 Sampling Frequency"
 	default 100
@@ -5737,7 +5649,7 @@ config STM32_ADC1_TIMTRIG
 	int "ADC1 Timer Trigger"
 	default 0
 	range 0 4
-	depends on STM32_HAVE_ADC1_TIMER || STM32_TIM1_PWM_ADC1
+	depends on STM32_HAVE_ADC1_TIMER
 	---help---
 		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
 
@@ -5752,7 +5664,7 @@ config STM32_ADC2_TIMTRIG
 	int "ADC2 Timer Trigger"
 	default 0
 	range 0 4
-	depends on STM32_HAVE_ADC2_TIMER || STM32_TIM1_PWM_ADC2
+	depends on STM32_HAVE_ADC2_TIMER
 	---help---
 		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
 
@@ -5767,7 +5679,7 @@ config STM32_ADC3_TIMTRIG
 	int "ADC3 Timer Trigger"
 	default 0
 	range 0 4
-	depends on STM32_HAVE_ADC3_TIMER || STM32_TIM1_PWM_ADC3
+	depends on STM32_HAVE_ADC3_TIMER
 	---help---
 		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
 
@@ -9397,6 +9309,14 @@ config STM32_OTGHS_SOFINTR
 	---help---
 		Enable SOF interrupts.  Why would you ever want to do that?
 
+config STM32_OTGHS_VBUS_CONTROL
+	bool "Enable VBus Control"
+	default y
+	---help---
+		Enable VBus control.  Used when the board has VBus sensing and
+		a power switch for the OTG HS USB port.  Disable this config
+		if the board lacks this USB VBus control circuitry.
+
 endmenu
 
 menu "USB Host Debug Configuration"
@@ -9524,7 +9444,7 @@ config STM32_LTDC_FB_BASE
 	---help---
 		If you are using the LTDC, then you must provide the address
 		of the start of the framebuffer.  This address will typically
-		be in the SRAM or SDRAM memory region of the FSMC.
+		be in the SRAM or SDRAM memory region of the FSMC/FMC.
 
 config STM32_LTDC_FB_SIZE
 	int "Framebuffer memory size (bytes)"
@@ -9698,7 +9618,7 @@ config STM32_DMA2D_FB_BASE
 	---help---
 		If you are using the DMA2D, then you must provide the address
 		of the start of the DMA2D overlays framebuffer. This address will typically
-		be in the SRAM or SDRAM memory region of the FSMC.
+		be in the SRAM or SDRAM memory region of the FSMC/FMC.
 
 config STM32_DMA2D_FB_SIZE
 	int "Framebuffer memory size (bytes)"
diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs
index 5addfc93163..45a182cb7a1 100644
--- a/arch/arm/src/stm32/Make.defs
+++ b/arch/arm/src/stm32/Make.defs
@@ -54,6 +54,10 @@ ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
 CMN_CSRCS += up_stackcheck.c
 endif
 
+ifeq ($(CONFIG_ARM_LWL_CONSOLE),y)
+CMN_CSRCS += up_lwl_console.c
+endif
+
 ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
 CMN_ASRCS += up_lazyexception.S
 else
@@ -67,11 +71,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
@@ -121,17 +123,17 @@ ifeq ($(CONFIG_STM32_CCM_PROCFS),y)
 CHIP_CSRCS += stm32_procfs_ccm.c
 endif
 
+ifeq ($(CONFIG_STM32_HAVE_IP_I2C_V1),y)
 ifeq ($(CONFIG_STM32_I2C_ALT),y)
 CHIP_CSRCS += stm32_i2c_alt.c
-else ifeq ($(CONFIG_STM32_STM32F30XX),y)
-CHIP_CSRCS += stm32f30xxx_i2c.c
-else ifeq ($(CONFIG_STM32_STM32F37XX),y)
-CHIP_CSRCS += stm32f30xxx_i2c.c
 else ifeq ($(CONFIG_STM32_STM32F4XXX),y)
 CHIP_CSRCS += stm32f40xxx_i2c.c
 else
 CHIP_CSRCS += stm32_i2c.c
 endif
+else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_V2),y)
+CHIP_CSRCS += stm32_i2c_v2.c
+endif
 
 ifeq ($(CONFIG_USBDEV),y)
 ifeq ($(CONFIG_STM32_USB),y)
@@ -267,3 +269,11 @@ endif
 ifeq ($(CONFIG_STM32_BBSRAM),y)
 CHIP_CSRCS += stm32_bbsram.c
 endif
+
+ifeq ($(CONFIG_STM32_FMC),y)
+CHIP_CSRCS += stm32_fmc.c
+endif
+
+ifeq ($(CONFIG_STM32_FSMC),y)
+CHIP_CSRCS += stm32_fsmc.c
+endif
diff --git a/arch/arm/src/stm32/chip.h b/arch/arm/src/stm32/chip.h
index 36f6254ae80..d88b52a8042 100644
--- a/arch/arm/src/stm32/chip.h
+++ b/arch/arm/src/stm32/chip.h
@@ -50,103 +50,13 @@
 
 #include 
 
-/* Include the chip pin configuration file */
+/* Include the chip memory map */
 
-/* STM32L EnergyLite Line ***********************************************************/
+#include "hardware/stm32_memorymap.h"
 
-#if defined(CONFIG_STM32_ENERGYLITE)
+/* Include the chip pinmap */
 
-/* STM32L15xx family */
-
-#  if defined(CONFIG_STM32_STM32L15XX)
-#    include "chip/stm32l15xxx_pinmap.h"
-#  else
-#    error "Unsupported EnergyLite chip"
-#  endif
-
-/* STM32 F1 Family ******************************************************************/
-
-#elif defined(CONFIG_STM32_STM32F10XX)
-
-/* STM32F100 Value Line */
-
-#  if defined(CONFIG_STM32_VALUELINE)
-#    include "chip/stm32f100_pinmap.h"
-
-/* STM32 F102 USB Access Medium Density Family */
-#  elif defined(CONFIG_ARCH_CHIP_STM32F102CB)
-#    include "chip/stm32f102_pinmap.h"
-
-/* STM32 F103 Low / Medium Density Family */
-#  elif defined(CONFIG_ARCH_CHIP_STM32F103C4) || \
-        defined(CONFIG_ARCH_CHIP_STM32F103C8) || \
-        defined(CONFIG_ARCH_CHIP_STM32F103CB)
-#    include "chip/stm32f103c_pinmap.h"
-
-/* STM32 F103 High Density Family */
-/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin packages and differ
- * only in the available FLASH and SRAM.
- */
-
-#  elif defined(CONFIG_ARCH_CHIP_STM32F103RB) || \
-        defined(CONFIG_ARCH_CHIP_STM32F103RC) || \
-        defined(CONFIG_ARCH_CHIP_STM32F103RD) || \
-        defined(CONFIG_ARCH_CHIP_STM32F103RE) || \
-        defined(CONFIG_ARCH_CHIP_STM32F103RG)
-#    include "chip/stm32f103r_pinmap.h"
-
-/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin packages and differ
- * only in the available FLASH and SRAM.
- */
-
-#  elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE)
-#    include "chip/stm32f103v_pinmap.h"
-
-/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin packages and differ
- * only in the available FLASH and SRAM.
- */
-#  elif defined(CONFIG_ARCH_CHIP_STM32F103ZE)
-#    include "chip/stm32f103z_pinmap.h"
-
-/* STM32 F105/F107 Connectivity Line */
-
-#  elif defined(CONFIG_ARCH_CHIP_STM32F105VB)
-#    include "chip/stm32f105v_pinmap.h"
-
-#  elif defined(CONFIG_ARCH_CHIP_STM32F105RB)
-#    include "chip/stm32f105r_pinmap.h"
-
-#  elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
-#    include "chip/stm32f107v_pinmap.h"
-#  else
-#    error "Unsupported STM32F10XXX chip"
-#  endif
-
-/* STM32 F2 Family ******************************************************************/
-
-#elif defined(CONFIG_STM32_STM32F20XX)
-#  include "chip/stm32f20xxx_pinmap.h"
-
-/* STM32 F3 Family ******************************************************************/
-
-#elif defined(CONFIG_STM32_STM32F30XX)
-#  include "chip/stm32f30xxx_pinmap.h"
-#elif defined(CONFIG_STM32_STM32F33XX)
-#  include "chip/stm32f33xxx_pinmap.h"
-#elif defined(CONFIG_STM32_STM32F37XX)
-#  include "chip/stm32f37xxx_pinmap.h"
-
-/* STM32 F4 Family ******************************************************************/
-
-#elif defined(CONFIG_STM32_STM32F4XXX)
-#  include "chip/stm32f40xxx_pinmap.h"
-#else
-#  error "No pinmap file for this STM32 chip"
-#endif
-
-/* Include the chip memory map. */
-
-#include "chip/stm32_memorymap.h"
+#include "hardware/stm32_pinmap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32/chip/stm32_adc.h b/arch/arm/src/stm32/hardware/stm32_adc.h
similarity index 93%
rename from arch/arm/src/stm32/chip/stm32_adc.h
rename to arch/arm/src/stm32/hardware/stm32_adc.h
index 1e57fe3e738..af4c7d5dedc 100644
--- a/arch/arm/src/stm32/chip/stm32_adc.h
+++ b/arch/arm/src/stm32/hardware/stm32_adc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32_adc.h
+ * arch/arm/src/stm32/hardware/stm32_adc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H
 
 /****************************************************************************************************
  * Included Files
@@ -72,4 +72,4 @@
 #  error "STM32 ADC IP version not specified"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H */
diff --git a/arch/arm/src/stm32/chip/stm32_adc_v1.h b/arch/arm/src/stm32/hardware/stm32_adc_v1.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32_adc_v1.h
rename to arch/arm/src/stm32/hardware/stm32_adc_v1.h
index 27b3acbb664..db723d2818d 100644
--- a/arch/arm/src/stm32/chip/stm32_adc_v1.h
+++ b/arch/arm/src/stm32/hardware/stm32_adc_v1.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32_adc_v1.h
+ * arch/arm/src/stm32/hardware/stm32_adc_v1.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_V1_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_V1_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H
 
 /****************************************************************************************************
  * Included Files
@@ -626,4 +626,4 @@
  * Public Function Prototypes
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_V1_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H */
diff --git a/arch/arm/src/stm32/chip/stm32_adc_v1l1.h b/arch/arm/src/stm32/hardware/stm32_adc_v1l1.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32_adc_v1l1.h
rename to arch/arm/src/stm32/hardware/stm32_adc_v1l1.h
index b35716efabf..b0bf9589af2 100644
--- a/arch/arm/src/stm32/chip/stm32_adc_v1l1.h
+++ b/arch/arm/src/stm32/hardware/stm32_adc_v1l1.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32_adc_v1l1.h
+ * arch/arm/src/stm32/hardware/stm32_adc_v1l1.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_V1L1_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_V1L1_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H
 
 /****************************************************************************************************
  * Included Files
@@ -562,4 +562,4 @@
  * Public Function Prototypes
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_V1L1_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H */
diff --git a/arch/arm/src/stm32/chip/stm32_adc_v2.h b/arch/arm/src/stm32/hardware/stm32_adc_v2.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32_adc_v2.h
rename to arch/arm/src/stm32/hardware/stm32_adc_v2.h
index 2fd75a2c786..efd57a4fdcf 100644
--- a/arch/arm/src/stm32/chip/stm32_adc_v2.h
+++ b/arch/arm/src/stm32/hardware/stm32_adc_v2.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32_adc_v2.h
+ * arch/arm/src/stm32/hardware/stm32_adc_v2.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_V2_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_V2_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H
 
 /****************************************************************************************************
  * Included Files
@@ -734,4 +734,4 @@
  * Public Function Prototypes
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ADC_V2_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H */
diff --git a/arch/arm/src/stm32/chip/stm32_bkp.h b/arch/arm/src/stm32/hardware/stm32_bkp.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32_bkp.h
rename to arch/arm/src/stm32/hardware/stm32_bkp.h
index 5bda839a88d..142328e4e10 100644
--- a/arch/arm/src/stm32/chip/stm32_bkp.h
+++ b/arch/arm/src/stm32/hardware/stm32_bkp.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_bkp.h
+ * arch/arm/src/stm32/hardware/stm32_bkp.h
  *
  *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_BKP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_BKP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -187,4 +187,4 @@
 #define BKP_DR_SHIFT             (0)       /* Bits 1510: Backup data */
 #define BKP_DR_MASK              (0xffff << BKP_DR_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_BKP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H */
diff --git a/arch/arm/src/stm32/chip/stm32_can.h b/arch/arm/src/stm32/hardware/stm32_can.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32_can.h
rename to arch/arm/src/stm32/hardware/stm32_can.h
index 2f45b8152bf..5254c6703d3 100644
--- a/arch/arm/src/stm32/chip/stm32_can.h
+++ b/arch/arm/src/stm32/hardware/stm32_can.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_can.h
+ * arch/arm/src/stm32/hardware/stm32_can.h
  *
  *   Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_CAN_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_CAN_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H
 
 /************************************************************************************
  * Included Files
@@ -506,4 +506,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_CAN_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H */
diff --git a/arch/arm/src/stm32/chip/stm32_dac.h b/arch/arm/src/stm32/hardware/stm32_dac.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32_dac.h
rename to arch/arm/src/stm32/hardware/stm32_dac.h
index 4dbbd544ee1..7b0ea3865f9 100644
--- a/arch/arm/src/stm32/chip/stm32_dac.h
+++ b/arch/arm/src/stm32/hardware/stm32_dac.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_dac.h
+ * arch/arm/src/stm32/hardware/stm32_dac.h
  *
  *   Copyright (C) 2011, 2013-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DAC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DAC_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H
 
 /************************************************************************************
  * Included Files
@@ -317,4 +317,4 @@
 #define DAC_SR_DMAUDR1          (1 << 13)  /* Bit 13: DAC channel 1 DMA underrun flag */
 #define DAC_SR_DMAUDR2          (1 << 29)  /* Bit 29: DAC channel 2 DMA underrun flag */
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DAC_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H */
diff --git a/arch/arm/src/stm32/chip/stm32_dbgmcu.h b/arch/arm/src/stm32/hardware/stm32_dbgmcu.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32_dbgmcu.h
rename to arch/arm/src/stm32/hardware/stm32_dbgmcu.h
index 30e9d459602..68e8b627cb7 100644
--- a/arch/arm/src/stm32/chip/stm32_dbgmcu.h
+++ b/arch/arm/src/stm32/hardware/stm32_dbgmcu.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32_dbgmcu.h
+ * arch/arm/src/stm32/hardware/stm32_dbgmcu.h
  *
  *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DBGMCU_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DBGMCU_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H
 
 /****************************************************************************************************
  * Included Files
@@ -168,4 +168,4 @@
  * Public Functions
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DBGMCU_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H */
diff --git a/arch/arm/src/stm32/chip/stm32_dma.h b/arch/arm/src/stm32/hardware/stm32_dma.h
similarity index 92%
rename from arch/arm/src/stm32/chip/stm32_dma.h
rename to arch/arm/src/stm32/hardware/stm32_dma.h
index 9b46b62f24a..a823068e603 100644
--- a/arch/arm/src/stm32/chip/stm32_dma.h
+++ b/arch/arm/src/stm32/hardware/stm32_dma.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_dma.h
+ * arch/arm/src/stm32/hardware/stm32_dma.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H
 
 /************************************************************************************
  * Included Files
@@ -61,4 +61,4 @@
 #  error "STM32 DMA IP version not specified"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H */
diff --git a/arch/arm/src/stm32/chip/stm32_dma2d.h b/arch/arm/src/stm32/hardware/stm32_dma2d.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32_dma2d.h
rename to arch/arm/src/stm32/hardware/stm32_dma2d.h
index 6f6b67d33e9..9d0e3450d9d 100644
--- a/arch/arm/src/stm32/chip/stm32_dma2d.h
+++ b/arch/arm/src/stm32/hardware/stm32_dma2d.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32/chip/stm32_dma2d.h
+ * arch/arm/src/stm32/hardware/stm32_dma2d.h
  *
  *   Copyright (C) 2014-2015 Marco Krahl. All rights reserved.
  *   Author: Marco Krahl 
@@ -33,15 +33,15 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA2D_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA2D_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H
 
 /****************************************************************************
  * Included Files
  ****************************************************************************/
 
 #include 
-#include "chip/stm32_memorymap.h"
+#include "hardware/stm32_memorymap.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -247,4 +247,4 @@
  * Public Types
  ****************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA2D_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H */
diff --git a/arch/arm/src/stm32/chip/stm32_dma_v1.h b/arch/arm/src/stm32/hardware/stm32_dma_v1.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32_dma_v1.h
rename to arch/arm/src/stm32/hardware/stm32_dma_v1.h
index 62221b3b6ae..b4bde327830 100644
--- a/arch/arm/src/stm32/chip/stm32_dma_v1.h
+++ b/arch/arm/src/stm32/hardware/stm32_dma_v1.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_dma_v1.h
+ * arch/arm/src/stm32/hardware/stm32_dma_v1.h
  *
  *   Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V1_DMA_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V1_DMA_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_DMA_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_DMA_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -703,4 +703,4 @@
 #  error "Unknown DMA channel assignments"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V1_DMA_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_DMA_H */
diff --git a/arch/arm/src/stm32/chip/stm32_dma_v2.h b/arch/arm/src/stm32/hardware/stm32_dma_v2.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32_dma_v2.h
rename to arch/arm/src/stm32/hardware/stm32_dma_v2.h
index 690a88bdce6..f9b38addb7b 100644
--- a/arch/arm/src/stm32/chip/stm32_dma_v2.h
+++ b/arch/arm/src/stm32/hardware/stm32_dma_v2.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_dma_v2.h
+ * arch/arm/src/stm32/hardware/stm32_dma_v2.h
  *
  *   Copyright (C) 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
@@ -36,8 +36,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V2_DMA_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V2_DMA_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_DMA_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_DMA_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -563,4 +563,4 @@
 #define DMAMAP_TIM8_TRIG           STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
 #define DMAMAP_TIM8_COM            STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_V2_DMA_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_DMA_H */
diff --git a/arch/arm/src/stm32/chip/stm32_eth.h b/arch/arm/src/stm32/hardware/stm32_eth.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32_eth.h
rename to arch/arm/src/stm32/hardware/stm32_eth.h
index 5ac1f752d00..cccbe7ef306 100644
--- a/arch/arm/src/stm32/chip/stm32_eth.h
+++ b/arch/arm/src/stm32/hardware/stm32_eth.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32_eth.h
+ * arch/arm/src/stm32/hardware/stm32_eth.h
  *
  *   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_ETH_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_ETH_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H
 
 /****************************************************************************************************
  * Included Files
@@ -837,5 +837,5 @@ struct eth_rxdesc_s
 
 #endif /* __ASSEMBLY__ */
 #endif /* STM32_NETHERNET > 0 */
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ETH_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32_exti.h b/arch/arm/src/stm32/hardware/stm32_exti.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32_exti.h
rename to arch/arm/src/stm32/hardware/stm32_exti.h
index 2184b2375ba..269bbbdcb6b 100644
--- a/arch/arm/src/stm32/chip/stm32_exti.h
+++ b/arch/arm/src/stm32/hardware/stm32_exti.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_exti.h
+ * arch/arm/src/stm32/hardware/stm32_exti.h
  *
  *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_EXTI_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_EXTI_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H
 
 /************************************************************************************
  * Included Files
@@ -213,4 +213,4 @@
 #  define STM32_EXTI_PR          STM32_EXTI1_PR
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_EXTI_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H */
diff --git a/arch/arm/src/stm32/chip/stm32_flash.h b/arch/arm/src/stm32/hardware/stm32_flash.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32_flash.h
rename to arch/arm/src/stm32/hardware/stm32_flash.h
index 0e39d360807..75656f72ec6 100644
--- a/arch/arm/src/stm32/chip/stm32_flash.h
+++ b/arch/arm/src/stm32/hardware/stm32_flash.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_flash.h
+ * arch/arm/src/stm32/hardware/stm32_flash.h
  *
  *   Copyright (C) 2009, 2011, 2015, 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_FLASH_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_FLASH_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -502,4 +502,4 @@ void stm32_flash_unlock(void);
 int stm32_flash_writeprotect(size_t page, bool enabled);
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_FLASH_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H */
diff --git a/arch/arm/src/stm32/hardware/stm32_fmc.h b/arch/arm/src/stm32/hardware/stm32_fmc.h
new file mode 100644
index 00000000000..da9b33b3793
--- /dev/null
+++ b/arch/arm/src/stm32/hardware/stm32_fmc.h
@@ -0,0 +1,383 @@
+/************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32_fmc.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *            Jason T. Harris 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_FMC_BCR_OFFSET(n)  (8 * ((n) - 1))
+#define STM32_FMC_BCR1_OFFSET    0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */
+#define STM32_FMC_BCR2_OFFSET    0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */
+#define STM32_FMC_BCR3_OFFSET    0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */
+#define STM32_FMC_BCR4_OFFSET    0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */
+
+#define STM32_FMC_BTR_OFFSET(n)  (8 * ((n) - 1) + 0x0004)
+#define STM32_FMC_BTR1_OFFSET    0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */
+#define STM32_FMC_BTR2_OFFSET    0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */
+#define STM32_FMC_BTR3_OFFSET    0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */
+#define STM32_FMC_BTR4_OFFSET    0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */
+
+#define STM32_FMC_BWTR_OFFSET(n) (8 * ((n) - 1) + 0x0104)
+#define STM32_FMC_BWTR1_OFFSET   0x0104 /* SRAM/NOR-Flash write timing registers 1 */
+#define STM32_FMC_BWTR2_OFFSET   0x010c /* SRAM/NOR-Flash write timing registers 2 */
+#define STM32_FMC_BWTR3_OFFSET   0x0114 /* SRAM/NOR-Flash write timing registers 3 */
+#define STM32_FMC_BWTR4_OFFSET   0x011c /* SRAM/NOR-Flash write timing registers 4 */
+
+#define STM32_FMC_PCR_OFFSET(n)  (0x0020 * ((n) - 1) + 0x0040)
+#define STM32_FMC_PCR2_OFFSET    0x0060 /* NAND Flash/PC Card controller register 2 */
+#define STM32_FMC_PCR3_OFFSET    0x0080 /* NAND Flash/PC Card controller register 3 */
+#define STM32_FMC_PCR4_OFFSET    0x00a0 /* NAND Flash/PC Card controller register 4 */
+
+#define STM32_FMC_SR_OFFSET(n)   (0x0020 * ((n) - 1) + 0x0044)
+#define STM32_FMC_SR2_OFFSET     0x0064 /* NAND Flash/PC Card controller register 2 */
+#define STM32_FMC_SR3_OFFSET     0x0084 /* NAND Flash/PC Card controller register 3 */
+#define STM32_FMC_SR4_OFFSET     0x00a4 /* NAND Flash/PC Card controller register 4 */
+
+#define STM32_FMC_PMEM_OFFSET(n) (0x0020 * ((n) - 1) + 0x0048)
+#define STM32_FMC_PMEM2_OFFSET   0x0068 /* Common memory space timing register 2 */
+#define STM32_FMC_PMEM3_OFFSET   0x0088 /* Common memory space timing register 3 */
+#define STM32_FMC_PMEM4_OFFSET   0x00a8 /* Common memory space timing register 4 */
+
+#define STM32_FMC_PATT_OFFSET(n) (0x0020 * ((n) - 1) + 0x004c)
+#define STM32_FMC_PATT2_OFFSET   0x006c /* Attribute memory space timing register 2 */
+#define STM32_FMC_PATT3_OFFSET   0x008c /* Attribute memory space timing register 3 */
+#define STM32_FMC_PATT4_OFFSET   0x00ac /* Attribute memory space timing register 4 */
+
+#define STM32_FMC_PIO4_OFFSET    0x00b0 /* I/O space timing register 4 */
+
+#define STM32_FMC_ECCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0054)
+#define STM32_FMC_ECCR2_OFFSET   0x0074 /* ECC result register 2 */
+#define STM32_FMC_ECCR3_OFFSET   0x0094 /* ECC result register 3 */
+
+#define STM32_FMC_SDCR1_OFFSET   0x0140 /* SDRAM Control Register, Bank 1 */
+#define STM32_FMC_SDCR2_OFFSET   0x0144 /* SDRAM Control Register, Bank 2 */
+
+#define STM32_FMC_SDTR1_OFFSET   0x0148 /* SDRAM Timing Register, Bank 1 */
+#define STM32_FMC_SDTR2_OFFSET   0x014c /* SDRAM Timing Register, Bank 2 */
+
+#define STM32_FMC_SDCMR_OFFSET   0x0150 /* SDRAM Config Memory register */
+#define STM32_FMC_SDRTR_OFFSET   0x0154 /* SDRAM Refresh Timing Register maybe */
+#define STM32_FMC_SDSR_OFFSET    0x0158 /* SDRAM Status Register */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_FMC_BCR(n)         (STM32_FMC_BASE + STM32_FMC_BCR_OFFSET(n))
+#define STM32_FMC_BCR1           (STM32_FMC_BASE + STM32_FMC_BCR1_OFFSET)
+#define STM32_FMC_BCR2           (STM32_FMC_BASE + STM32_FMC_BCR2_OFFSET)
+#define STM32_FMC_BCR3           (STM32_FMC_BASE + STM32_FMC_BCR3_OFFSET)
+#define STM32_FMC_BCR4           (STM32_FMC_BASE + STM32_FMC_BCR4_OFFSET)
+
+#define STM32_FMC_BTR(n)         (STM32_FMC_BASE + STM32_FMC_BTR_OFFSET(n))
+#define STM32_FMC_BTR1           (STM32_FMC_BASE + STM32_FMC_BTR1_OFFSET)
+#define STM32_FMC_BTR2           (STM32_FMC_BASE + STM32_FMC_BTR2_OFFSET)
+#define STM32_FMC_BTR3           (STM32_FMC_BASE + STM32_FMC_BTR3_OFFSET)
+#define STM32_FMC_BTR4           (STM32_FMC_BASE + STM32_FMC_BTR4_OFFSET)
+
+#define STM32_FMC_BWTR(n)        (STM32_FMC_BASE + STM32_FMC_BWTR_OFFSET(n))
+#define STM32_FMC_BWTR1          (STM32_FMC_BASE + STM32_FMC_BWTR1_OFFSET)
+#define STM32_FMC_BWTR2          (STM32_FMC_BASE + STM32_FMC_BWTR2_OFFSET)
+#define STM32_FMC_BWTR3          (STM32_FMC_BASE + STM32_FMC_BWTR3_OFFSET)
+#define STM32_FMC_BWTR4          (STM32_FMC_BASE + STM32_FMC_BWTR4_OFFSET)
+
+#define STM32_FMC_PCR(n)         (STM32_FMC_BASE + STM32_FMC_PCR_OFFSET(n))
+#define STM32_FMC_PCR2           (STM32_FMC_BASE + STM32_FMC_PCR2_OFFSET)
+#define STM32_FMC_PCR3           (STM32_FMC_BASE + STM32_FMC_PCR3_OFFSET)
+#define STM32_FMC_PCR4           (STM32_FMC_BASE + STM32_FMC_PCR4_OFFSET)
+
+#define STM32_FMC_SR(n)          (STM32_FMC_BASE + STM32_FMC_SR_OFFSET(n))
+#define STM32_FMC_SR2            (STM32_FMC_BASE + STM32_FMC_SR2_OFFSET)
+#define STM32_FMC_SR3            (STM32_FMC_BASE + STM32_FMC_SR3_OFFSET)
+#define STM32_FMC_SR4            (STM32_FMC_BASE + STM32_FMC_SR4_OFFSET)
+
+#define STM32_FMC_PMEM(n)        (STM32_FMC_BASE + STM32_FMC_PMEM_OFFSET(n))
+#define STM32_FMC_PMEM2          (STM32_FMC_BASE + STM32_FMC_PMEM2_OFFSET)
+#define STM32_FMC_PMEM3          (STM32_FMC_BASE + STM32_FMC_PMEM3_OFFSET)
+#define STM32_FMC_PMEM4          (STM32_FMC_BASE + STM32_FMC_PMEM4_OFFSET)
+
+#define STM32_FMC_PATT(n)        (STM32_FMC_BASE + STM32_FMC_PATT_OFFSET(n))
+#define STM32_FMC_PATT2          (STM32_FMC_BASE + STM32_FMC_PATT2_OFFSET)
+#define STM32_FMC_PATT3          (STM32_FMC_BASE + STM32_FMC_PATT3_OFFSET)
+#define STM32_FMC_PATT4          (STM32_FMC_BASE + STM32_FMC_PATT4_OFFSET)
+
+#define STM32_FMC_PIO4           (STM32_FMC_BASE + STM32_FMC_PIO4_OFFSET)
+
+#define STM32_FMC_ECCR(n)        (STM32_FMC_BASE + STM32_FMC_ECCR_OFFSET(n))
+#define STM32_FMC_ECCR2          (STM32_FMC_BASE + STM32_FMC_ECCR2_OFFSET)
+#define STM32_FMC_ECCR3          (STM32_FMC_BASE + STM32_FMC_ECCR3_OFFSET)
+
+#define STM32_FMC_SDCR1          (STM32_FMC_BASE + STM32_FMC_SDCR1_OFFSET)
+#define STM32_FMC_SDCR2          (STM32_FMC_BASE + STM32_FMC_SDCR2_OFFSET)
+
+#define STM32_FMC_SDTR1          (STM32_FMC_BASE + STM32_FMC_SDTR1_OFFSET)
+#define STM32_FMC_SDTR2          (STM32_FMC_BASE + STM32_FMC_SDTR2_OFFSET)
+
+#define STM32_FMC_SDCMR          (STM32_FMC_BASE + STM32_FMC_SDCMR_OFFSET)
+#define STM32_FMC_SDRTR          (STM32_FMC_BASE + STM32_FMC_SDRTR_OFFSET)
+#define STM32_FMC_SDSR           (STM32_FMC_BASE + STM32_FMC_SDSR_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+#define FMC_BCR_MBKEN            (1 << 0)   /* Memory bank enable bit */
+#define FMC_BCR_MUXEN            (1 << 1)   /* Address/data multiplexing enable bit */
+#define FMC_BCR_MTYP_SHIFT       (2)        /* Memory type */
+#define FMC_BCR_MTYP_MASK        (3 << FMC_BCR_MTYP_SHIFT)
+#  define FMC_BCR_SRAM           (0 << FMC_BCR_MTYP_SHIFT)
+#  define FMC_BCR_ROM            (0 << FMC_BCR_MTYP_SHIFT)
+#  define FMC_BCR_PSRAM          (1 << FMC_BCR_MTYP_SHIFT)
+#  define FMC_BCR_CRAM           (1 << FMC_BCR_MTYP_SHIFT)
+#  define FMC_BCR_NOR            (2 << FMC_BCR_MTYP_SHIFT)
+#define FMC_BCR_MWID_SHIFT       (4)        /* Memory data bus width */
+#define FMC_BCR_MWID_MASK        (3 <<  FMC_BCR_MWID_SHIFT)
+#  define FMC_BCR_MWID8          (0 << FMC_BCR_MWID_SHIFT)
+#  define FMC_BCR_MWID16         (1 << FMC_BCR_MWID_SHIFT)
+#define FMC_BCR_FACCEN           (1 << 6)   /* Flash access enable */
+#define FMC_BCR_BURSTEN          (1 << 8)   /* Burst enable bit */
+#define FMC_BCR_WAITPOL          (1 << 9)   /* Wait signal polarity bit */
+#define FMC_BCR_WRAPMOD          (1 << 10)  /* Wrapped burst mode support */
+#define FMC_BCR_WAITCFG          (1 << 11)  /* Wait timing configuration */
+#define FMC_BCR_WREN             (1 << 12)  /* Write enable bit */
+#define FMC_BCR_WAITEN           (1 << 13)  /* Wait enable bit */
+#define FMC_BCR_EXTMOD           (1 << 14)  /* Extended mode enable */
+#define FMC_BCR_ASYNCWAIT        (1 << 15)  /* Wait signal during asynchronous transfers */
+#define FMC_BCR_CBURSTRW         (1 << 19)  /* Write burst enable */
+
+#define FMC_BCR_RSTVALUE         0x000003d2
+
+#define FMC_BTR_ADDSET_SHIFT     (0)        /* Address setup phase duration */
+#define FMC_BTR_ADDSET_MASK      (15 << FMC_BTR_ADDSET_SHIFT)
+#  define FMC_BTR_ADDSET(n)      ((n-1) << FMC_BTR_ADDSET_SHIFT)  /* (n)xHCLK n=1..16 */
+#define FMC_BTR_ADDHLD_SHIFT     (4)        /* Address-hold phase duration */
+#define FMC_BTR_ADDHLD_MASK      (15 << FMC_BTR_ADDHLD_SHIFT)
+#  define FMC_BTR_ADDHLD(n)      ((n-1) << FMC_BTR_ADDHLD_SHIFT)  /* (n)xHCLK n=2..16*/
+#define FMC_BTR_DATAST_SHIFT     (8)        /* Data-phase duration */
+#define FMC_BTR_DATAST_MASK      (255 << FMC_BTR_DATAST_SHIFT)
+#  define FMC_BTR_DATAST(n)      ((n-1) << FMC_BTR_DATAST_SHIFT)  /* (n)xHCLK n=2..256 */
+#define FMC_BTR_BUSTURN_SHIFT    (16)       /* Bus turnaround phase duration */
+#define FMC_BTR_BUSTURN_MASK     (15 << FMC_BTR1_BUSTURN_SHIFT)
+#  define FMC_BTR_BUSTURN(n)     ((n-1) << FMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */
+#define FMC_BTR_CLKDIV_SHIFT     (20)       /* Clock divide ratio */
+#define FMC_BTR_CLKDIV_MASK      (15 << FMC_BTR_CLKDIV_SHIFT)
+#  define FMC_BTR_CLKDIV(n)      ((n-1) << FMC_BTR_CLKDIV_SHIFT)  /* (n)xHCLK n=2..16 */
+#define FMC_BTR_DATLAT_SHIFT     (24)      /* Data latency */
+#define FMC_BTR_DATLAT_MASK      (15 << FMC_BTR_DATLAT_SHIFT)
+#  define FMC_BTR_DATLAT(n)      ((n-2) << FMC_BTR_DATLAT_SHIFT)  /* (n)xHCLK n=2..17 */
+#define FMC_BTR_ACCMOD_SHIFT     (28)      /* Access mode */
+#define FMC_BTR_ACCMOD_MASK      (3 << FMC_BTR_ACCMOD_SHIFT)
+#  define FMC_BTR_ACCMODA        (0 << FMC_BTR_ACCMOD_SHIFT)
+#  define FMC_BTR_ACCMODB        (1 << FMC_BTR_ACCMOD_SHIFT)
+#  define FMC_BTR_ACCMODC        (2 << FMC_BTR_ACCMOD_SHIFT)
+#  define FMC_BTR_ACCMODD        (3 << FMC_BTR_ACCMOD_SHIFT)
+
+#define FMC_BTR_RSTVALUE         0xffffffff
+
+#define FMC_BWTR_ADDSET_SHIFT    (0)        /* Address setup phase duration */
+#define FMC_BWTR_ADDSET_MASK     (15 << FMC_BWTR_ADDSET_SHIFT)
+#  define FMC_BWTR_ADDSET(n)     ((n-1) << FMC_BWTR_ADDSET_SHIFT)  /* (n)xHCLK n=1..16 */
+#define FMC_BWTR_ADDHLD_SHIFT    (4)        /* Address-hold phase duration */
+#define FMC_BWTR_ADDHLD_MASK     (15 << FMC_BWTR_ADDHLD_SHIFT)
+#  define FMC_BWTR_ADDHLD(n)     ((n-1) << FMC_BWTR_ADDHLD_SHIFT)  /* (n)xHCLK n=2..16*/
+#define FMC_BWTR_DATAST_SHIFT    (8)        /* Data-phase duration */
+#define FMC_BWTR_DATAST_MASK     (255 << FMC_BWTR_DATAST_SHIFT)
+#  define FMC_BWTR_DATAST(n)     ((n-1) << FMC_BWTR_DATAST_SHIFT)  /* (n)xHCLK n=2..256 */
+#define FMC_BWTR_CLKDIV_SHIFT    (20)       /* Clock divide ratio */
+#define FMC_BWTR_CLKDIV_MASK     (15 << FMC_BWTR_CLKDIV_SHIFT)
+#  define FMC_BWTR_CLKDIV(n)     ((n-1) << FMC_BWTR_CLKDIV_SHIFT)  /* (n)xHCLK n=2..16 */
+#define FMC_BWTR_DATLAT_SHIFT    (24)      /* Data latency */
+#define FMC_BWTR_DATLAT_MASK     (15 << FMC_BWTR_DATLAT_SHIFT)
+#  define FMC_BWTR_DATLAT(n)     ((n-2) << FMC_BWTR_DATLAT_SHIFT)  /* (n)xHCLK n=2..17 */
+#define FMC_BWTR_ACCMOD_SHIFT    (28)      /* Access mode */
+#define FMC_BWTR_ACCMOD_MASK     (3 << FMC_BWTR_ACCMOD_SHIFT)
+#  define FMC_BWTR_ACCMODA       (0 << FMC_BWTR_ACCMOD_SHIFT)
+#  define FMC_BWTR_ACCMODB       (1 << FMC_BWTR_ACCMOD_SHIFT)
+#  define FMC_BWTR_ACCMODC       (2 << FMC_BWTR_ACCMOD_SHIFT)
+#  define FMC_BWTR_ACCMODD       (3 << FMC_BTR_ACCMOD_SHIFT)
+
+#define FMC_PCR_PWAITEN          (1 << 1)  /* Wait feature enable bit */
+#define FMC_PCR_PBKEN            (1 << 2)  /* PC Card/NAND Flash memory bank enable bit */
+#define FMC_PCR_PTYP             (1 << 3)  /* Memory type */
+#define FMC_PCR_PWID_SHIFT       (4)       /* NAND Flash databus width */
+#define FMC_PCR_PWID_MASK        (3 <<  FMC_PCR_PWID_SHIFT)
+#  define FMC_PCR_PWID8          (0 <<  FMC_PCR_PWID_SHIFT)
+#  define FMC_PCR_PWID16         (1 <<  FMC_PCR_PWID_SHIFT)
+#define FMC_PCR_ECCEN            (1 << 6)  /* ECC computation logic enable bit */
+#define FMC_PCR_TCLR_SHIFT       (9)       /* CLE to RE delay */
+#define FMC_PCR_TCLR_MASK        (15 << FMC_PCR_TCLR_SHIFT)
+#  define FMC_PCR_TCLR(n)        ((n-1) << FMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */
+#define FMC_PCR_TAR_SHIFT        (13)      /* ALE to RE delay */
+#define FMC_PCR_TAR_MASK         (15 <<  FMC_PCR_TAR_MASK)
+#  define FMC_PCR_TAR(n)         ((n-1) << FMC_PCR_TAR_SHIFT)  /* (n)xHCLK n=1..16 */
+#define FMC_PCR_ECCPS_SHIFT      (17)      /* ECC page size */
+#define FMC_PCR_ECCPS_MASK       (7 << FMC_PCR_ECCPS_SHIFT)
+#  define FMC_PCR_ECCPS256       (0 << FMC_PCR_ECCPS_SHIFT) /* 256 bytes */
+#  define FMC_PCR_ECCPS512       (1 << FMC_PCR_ECCPS_SHIFT) /* 512 bytes */
+#  define FMC_PCR_ECCPS1024      (2 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
+#  define FMC_PCR_ECCPS2048      (3 << FMC_PCR_ECCPS_SHIFT) /* 2048 bytes */
+#  define FMC_PCR_ECCPS4096      (4 << FMC_PCR_ECCPS_SHIFT) /* 8192 bytes */
+#  define FMC_PCR_ECCPS8192      (5 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
+
+#define FMC_SR_IRS               (1 << 0)  /* Interrupt Rising Edge status */
+#define FMC_SR_ILS               (1 << 1)  /* Interrupt Level status */
+#define FMC_SR_IFS               (1 << 2)  /* Interrupt Falling Edge status */
+#define FMC_SR_IREN              (1 << 3)  /* Interrupt Rising Edge detection Enable bit */
+#define FMC_SR_ILEN              (1 << 4)  /* Interrupt Level detection Enable bit */
+#define FMC_SR_IFEN              (1 << 5)  /* Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT             (1 << 6)  /* FIFO empty */
+
+#define FMC_PMEM_MEMSET_SHIFT    (0)       /* Common memory setup time */
+#define FMC_PMEM_MEMSET_MASK     (255 << FMC_PMEM_MEMSET_SHIFT)
+#  define FMC_PMEM_MEMSET(n)     ((n-1) << FMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */
+#define FMC_PMEM_MEMWAIT_SHIFT   (8)       /* Common memory wait time */
+#define FMC_PMEM_MEMWAIT_MASK    (255 << FMC_PMEM_MEMWAIT_SHIFT)
+#  define FMC_PMEM_MEMWAIT(n)    ((n-1) << FMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */
+#define FMC_PMEM_MEMHOLD_SHIFT   (16)      /* Common memoryhold time */
+#define FMC_PMEM_MEMHOLD_MASK    (255 << FMC_PMEM_MEMHOLD_SHIFT)
+#  define FMC_PMEM_MEMHOLD(n)    ((n) <<  FMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */
+#define FMC_PMEM_MEMHIZ_SHIFT    (24)       /* Common memory databus HiZ time */
+#define FMC_PMEM_MEMHIZ_MASK     (255 << FMC_PMEM_MEMHIZ_SHIFT)
+#  define FMC_PMEM_MEMHIZ(n)     ((n) << FMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */
+
+#define FMC_PATT_ATTSET_SHIFT    (0)       /* Attribute memory setup time */
+#define FMC_PATT_ATTSET_MASK     (255 << FMC_PATT_ATTSET_SHIFT)
+#  define FMC_PATT_ATTSET(n)     ((n-1) << FMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */
+#define FMC_PATT_ATTWAIT_SHIFT   (8)       /* Attribute memory wait time */
+#define FMC_PATT_ATTWAIT_MASK    (255 << FMC_PATT_ATTWAIT_SHIFT)
+#  define FMC_PATT_ATTWAIT(n)    ((n-1) << FMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */
+#define FMC_PATT_ATTHOLD_SHIFT   (16)      /* Attribute memory hold time */
+#define FMC_PATT_ATTHOLD_MASK    (255 << FMC_PATT_ATTHOLD_SHIFT)
+#  define FMC_PATT_ATTHOLD(n)    ((n) <<  FMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */
+#define FMC_PATT_ATTHIZ_SHIFT    (24)       /* Attribute memory databus HiZ time */
+#define FMC_PATT_ATTHIZ_MASK     (255 << FMC_PATT_ATTHIZ_SHIFT)
+#  define FMC_PATT_ATTHIZ(n)     ((n) << FMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */
+
+#define FMC_PIO4_IOSET_SHIFT     (0)       /* IO memory setup time */
+#define FMC_PIO4_IOSET_MASK      (255 << FMC_PIO4_IOSET_SHIFT)
+#  define FMC_PIO4_IOSET(n)      ((n-1) << FMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */
+#define FMC_PIO4_IOWAIT_SHIFT    (8)       /* IO memory wait time */
+#define FMC_PIO4_IOWAIT_MASK     (255 << FMC_PIO4_IOWAIT_SHIFT)
+#  define FMC_PIO4_IOWAIT(n)     ((n-1) << FMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */
+#define FMC_PIO4_IOHOLD_SHIFT    (16)      /* IO memory hold time */
+#define FMC_PIO4_IOHOLD_MASK     (255 << FMC_PIO4_IOHOLD_SHIFT)
+#  define FMC_PIO4_IOHOLD(n)     ((n) <<  FMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */
+#define FMC_PIO4_IOHIZ_SHIFT     (24)      /* IO memory databus HiZ time */
+#define FMC_PIO4_IOHIZ_MASK      (255 << FMC_PIO4_IOHIZ_SHIFT)
+#  define FMC_PIO4_IOHIZ(n)      ((n) << FMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */
+
+#define FMC_SDCR_RESERVED        (0x1ffff << 15)  /* reserved bits */
+#define FMC_SDCR_RPIPE_0         (0 << 13) /* read pipe */
+#define FMC_SDCR_RPIPE_1         (1 << 13)
+#define FMC_SDCR_RPIPE_2         (2 << 13)
+#define FMC_SDCR_READBURST       (1 << 12) /* read burst */
+#define FMC_SDCR_SDCLK_DISABLE   (0 << 10) /* sdram clock */
+#define FMC_SDCR_SDCLK_2X        (2 << 10)
+#define FMC_SDCR_SDCLK_3X        (3 << 10)
+#define FMC_SDCR_WP              (1 << 9) /* write protect */
+#define FMC_SDCR_CAS_LATENCY_1   (1 << 7) /* cas latency */
+#define FMC_SDCR_CAS_LATENCY_2   (2 << 7)
+#define FMC_SDCR_CAS_LATENCY_3   (3 << 7)
+#define FMC_SDCR_NBANKS_2        (0 << 6) /* number of internal banks */
+#define FMC_SDCR_NBANKS_4        (1 << 6)
+#define FMC_SDCR_WIDTH_8         (0 << 4) /* memory width */
+#define FMC_SDCR_WIDTH_16        (1 << 4)
+#define FMC_SDCR_WIDTH_32        (2 << 4)
+#define FMC_SDCR_ROWS_11         (0 << 2) /* number of rows */
+#define FMC_SDCR_ROWS_12         (1 << 2)
+#define FMC_SDCR_ROWS_13         (2 << 2)
+#define FMC_SDCR_COLS_8          (0 << 0) /* number of columns */
+#define FMC_SDCR_COLS_9          (1 << 0)
+#define FMC_SDCR_COLS_10         (2 << 0)
+#define FMC_SDCR_COLS_11         (3 << 0)
+
+#define FMC_SDTR_RESERVED        (15 << 28)  /* reserved bits */
+#define FMC_SDTR_TMRD(n)         (((n & 15) - 1) << 0)
+#define FMC_SDTR_TXSR(n)         (((n & 15) - 1) << 4)
+#define FMC_SDTR_TRAS(n)         (((n & 15) - 1) << 8)
+#define FMC_SDTR_TRC(n)          (((n & 15) - 1) << 12)
+#define FMC_SDTR_TWR(n)          (((n & 15) - 1) << 16)
+#define FMC_SDTR_TRP(n)          (((n & 15) - 1) << 20)
+#define FMC_SDTR_TRCD(n)         (((n & 15) - 1) << 24)
+
+/* Note: The FMC_SDCMR_MDR_x values can be found in the SDRAM datasheet.
+ * They should be standard, but it's probably a good idea to review
+ * the datasheet for your SDRAM device.
+ */
+#define FMC_SDCMR_RESERVED                        (0x3ff << 22)  /* reserved bits */
+#define FMC_SDCMR_MDR_BURST_LENGTH_1              ((0 << 0) << 9)
+#define FMC_SDCMR_MDR_BURST_LENGTH_2              ((1 << 0) << 9)
+#define FMC_SDCMR_MDR_BURST_LENGTH_4              ((2 << 0) << 9)
+#define FMC_SDCMR_MDR_BURST_LENGTH_8              ((3 << 0) << 9)
+#define FMC_SDCMR_MDR_BURST_LENGTH_FULL           ((7 << 0) << 9)
+#define FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL       ((0 << 3) << 9)
+#define FMC_SDCMR_MDR_BURST_TYPE_INTERLEAVE       ((1 << 3) << 9)
+#define FMC_SDCMR_MDR_CAS_LATENCY_1               ((1 << 4) << 9)
+#define FMC_SDCMR_MDR_CAS_LATENCY_2               ((2 << 4) << 9)
+#define FMC_SDCMR_MDR_CAS_LATENCY_3               ((3 << 4) << 9)
+#define FMC_SDCMR_MDR_MODE_NORMAL                 ((0 << 7) << 9)
+#define FMC_SDCMR_MDR_WBL_BURST                   ((0 << 9) << 9)
+#define FMC_SDCMR_MDR_WBL_SINGLE                  ((1 << 9) << 9)
+#define FMC_SDCMR_NRFS(n)                         (((n & 15) - 1) << 5)
+#define FMC_SDCMR_BANK_1                          (1 << 4)
+#define FMC_SDCMR_BANK_2                          (1 << 3)
+#define FMC_SDCMR_CMD_NORMAL                      (0 << 0)
+#define FMC_SDCMR_CMD_CLK_ENABLE                  (1 << 0)
+#define FMC_SDCMR_CMD_PALL                        (2 << 0)
+#define FMC_SDCMR_CMD_AUTO_REFRESH                (3 << 0)
+#define FMC_SDCMR_CMD_LOAD_MODE                   (4 << 0)
+#define FMC_SDCMR_CMD_SELF_REFRESH                (5 << 0)
+#define FMC_SDCMR_CMD_POWER_DOWN                  (6 << 0)
+
+#define FMC_SDSR_RE                       (1 << 0)
+#define FMC_SDSR_BUSY                     (1 << 5)
+#define FMC_SDSR_MODES1_NORMAL            (0 << 1)
+#define FMC_SDSR_MODES1_SELF_REFRESH      (1 << 1)
+#define FMC_SDSR_MODES1_POWER_DOWN        (2 << 1)
+#define FMC_SDSR_MODES2_NORMAL            (0 << 3)
+#define FMC_SDSR_MODES2_SELF_REFRESH      (1 << 3)
+#define FMC_SDSR_MODES2_POWER_DOWN        (2 << 3)
+
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H */
diff --git a/arch/arm/src/stm32/hardware/stm32_fsmc.h b/arch/arm/src/stm32/hardware/stm32_fsmc.h
new file mode 100644
index 00000000000..0ae7d7c3058
--- /dev/null
+++ b/arch/arm/src/stm32/hardware/stm32_fsmc.h
@@ -0,0 +1,292 @@
+/************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32_fsmc.h
+ *
+ *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_FSMC_BCR_OFFSET(n)  (8 * ((n) - 1))
+#define STM32_FSMC_BCR1_OFFSET    0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */
+#define STM32_FSMC_BCR2_OFFSET    0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */
+#define STM32_FSMC_BCR3_OFFSET    0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */
+#define STM32_FSMC_BCR4_OFFSET    0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */
+
+#define STM32_FSMC_BTR_OFFSET(n)  (8 * ((n) - 1) + 0x0004)
+#define STM32_FSMC_BTR1_OFFSET    0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */
+#define STM32_FSMC_BTR2_OFFSET    0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */
+#define STM32_FSMC_BTR3_OFFSET    0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */
+#define STM32_FSMC_BTR4_OFFSET    0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */
+
+#define STM32_FSMC_BWTR_OFFSET(n) (8 * ((n) - 1) + 0x0104)
+#define STM32_FSMC_BWTR1_OFFSET   0x0104 /* SRAM/NOR-Flash write timing registers 1 */
+#define STM32_FSMC_BWTR2_OFFSET   0x010c /* SRAM/NOR-Flash write timing registers 2 */
+#define STM32_FSMC_BWTR3_OFFSET   0x0114 /* SRAM/NOR-Flash write timing registers 3 */
+#define STM32_FSMC_BWTR4_OFFSET   0x011c /* SRAM/NOR-Flash write timing registers 4 */
+
+#define STM32_FSMC_PCR_OFFSET(n)  (0x0020 * ((n) - 1) + 0x0040)
+#define STM32_FSMC_PCR2_OFFSET    0x0060 /* NAND Flash/PC Card controller register 2 */
+#define STM32_FSMC_PCR3_OFFSET    0x0080 /* NAND Flash/PC Card controller register 3 */
+#define STM32_FSMC_PCR4_OFFSET    0x00a0 /* NAND Flash/PC Card controller register 4 */
+
+#define STM32_FSMC_SR_OFFSET(n)   (0x0020 * ((n) - 1) + 0x0044)
+#define STM32_FSMC_SR2_OFFSET     0x0064 /* NAND Flash/PC Card controller register 2 */
+#define STM32_FSMC_SR3_OFFSET     0x0084 /* NAND Flash/PC Card controller register 3 */
+#define STM32_FSMC_SR4_OFFSET     0x00a4 /* NAND Flash/PC Card controller register 4 */
+
+#define STM32_FSMC_PMEM_OFFSET(n) (0x0020 * ((n) - 1) + 0x0048)
+#define STM32_FSMC_PMEM2_OFFSET   0x0068 /* Common memory space timing register 2 */
+#define STM32_FSMC_PMEM3_OFFSET   0x0088 /* Common memory space timing register 3 */
+#define STM32_FSMC_PMEM4_OFFSET   0x00a8 /* Common memory space timing register 4 */
+
+#define STM32_FSMC_PATT_OFFSET(n) (0x0020 * ((n) - 1) + 0x004c)
+#define STM32_FSMC_PATT2_OFFSET   0x006c /* Attribute memory space timing register 2 */
+#define STM32_FSMC_PATT3_OFFSET   0x008c /* Attribute memory space timing register 3 */
+#define STM32_FSMC_PATT4_OFFSET   0x00ac /* Attribute memory space timing register 4 */
+
+#define STM32_FSMC_PIO4_OFFSET    0x00b0  /* I/O space timing register 4 */
+
+#define STM32_FSMC_ECCR_OFFSET(n) (0x0020 * ((n) - 1) + 0x0054)
+#define STM32_FSMC_ECCR2_OFFSET   0x0074 /* ECC result register 2 */
+#define STM32_FSMC_ECCR3_OFFSET   0x0094 /* ECC result register 3 */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_FSMC_BCR(n)         (STM32_FSMC_BASE + STM32_FSMC_BCR_OFFSET(n))
+#define STM32_FSMC_BCR1           (STM32_FSMC_BASE + STM32_FSMC_BCR1_OFFSET)
+#define STM32_FSMC_BCR2           (STM32_FSMC_BASE + STM32_FSMC_BCR2_OFFSET)
+#define STM32_FSMC_BCR3           (STM32_FSMC_BASE + STM32_FSMC_BCR3_OFFSET)
+#define STM32_FSMC_BCR4           (STM32_FSMC_BASE + STM32_FSMC_BCR4_OFFSET)
+
+#define STM32_FSMC_BTR(n)         (STM32_FSMC_BASE + STM32_FSMC_BTR_OFFSET(n))
+#define STM32_FSMC_BTR1           (STM32_FSMC_BASE + STM32_FSMC_BTR1_OFFSET)
+#define STM32_FSMC_BTR2           (STM32_FSMC_BASE + STM32_FSMC_BTR2_OFFSET)
+#define STM32_FSMC_BTR3           (STM32_FSMC_BASE + STM32_FSMC_BTR3_OFFSET)
+#define STM32_FSMC_BTR4           (STM32_FSMC_BASE + STM32_FSMC_BTR4_OFFSET)
+
+#define STM32_FSMC_BWTR(n)        (STM32_FSMC_BASE + STM32_FSMC_BWTR_OFFSET(n))
+#define STM32_FSMC_BWTR1          (STM32_FSMC_BASE + STM32_FSMC_BWTR1_OFFSET)
+#define STM32_FSMC_BWTR2          (STM32_FSMC_BASE + STM32_FSMC_BWTR2_OFFSET)
+#define STM32_FSMC_BWTR3          (STM32_FSMC_BASE + STM32_FSMC_BWTR3_OFFSET)
+#define STM32_FSMC_BWTR4          (STM32_FSMC_BASE + STM32_FSMC_BWTR4_OFFSET)
+
+#define STM32_FSMC_PCR(n)         (STM32_FSMC_BASE + STM32_FSMC_PCR_OFFSET(n))
+#define STM32_FSMC_PCR2           (STM32_FSMC_BASE + STM32_FSMC_PCR2_OFFSET)
+#define STM32_FSMC_PCR3           (STM32_FSMC_BASE + STM32_FSMC_PCR3_OFFSET)
+#define STM32_FSMC_PCR4           (STM32_FSMC_BASE + STM32_FSMC_PCR4_OFFSET)
+
+#define STM32_FSMC_SR(n)          (STM32_FSMC_BASE + STM32_FSMC_SR_OFFSET(n))
+#define STM32_FSMC_SR2            (STM32_FSMC_BASE + STM32_FSMC_SR2_OFFSET)
+#define STM32_FSMC_SR3            (STM32_FSMC_BASE + STM32_FSMC_SR3_OFFSET)
+#define STM32_FSMC_SR4            (STM32_FSMC_BASE + STM32_FSMC_SR4_OFFSET)
+
+#define STM32_FSMC_PMEM(n)        (STM32_FSMC_BASE + STM32_FSMC_PMEM_OFFSET(n))
+#define STM32_FSMC_PMEM2          (STM32_FSMC_BASE + STM32_FSMC_PMEM2_OFFSET)
+#define STM32_FSMC_PMEM3          (STM32_FSMC_BASE + STM32_FSMC_PMEM3_OFFSET)
+#define STM32_FSMC_PMEM4          (STM32_FSMC_BASE + STM32_FSMC_PMEM4_OFFSET)
+
+#define STM32_FSMC_PATT(n)        (STM32_FSMC_BASE + STM32_FSMC_PATT_OFFSET(n))
+#define STM32_FSMC_PATT2          (STM32_FSMC_BASE + STM32_FSMC_PATT2_OFFSET)
+#define STM32_FSMC_PATT3          (STM32_FSMC_BASE + STM32_FSMC_PATT3_OFFSET)
+#define STM32_FSMC_PATT4          (STM32_FSMC_BASE + STM32_FSMC_PATT4_OFFSET)
+
+#define STM32_FSMC_PIO4           (STM32_FSMC_BASE + STM32_FSMC_PIO4_OFFSET)
+
+#define STM32_FSMC_ECCR(n)        (STM32_FSMC_BASE + STM32_FSMC_ECCR_OFFSET(n))
+#define STM32_FSMC_ECCR2          (STM32_FSMC_BASE + STM32_FSMC_ECCR2_OFFSET)
+#define STM32_FSMC_ECCR3          (STM32_FSMC_BASE + STM32_FSMC_ECCR3_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+#define FSMC_BCR_MBKEN            (1 << 0)   /* Memory bank enable bit */
+#define FSMC_BCR_MUXEN            (1 << 1)   /* Address/data multiplexing enable bit */
+#define FSMC_BCR_MTYP_SHIFT       (2)        /* Memory type */
+#define FSMC_BCR_MTYP_MASK        (3 << FSMC_BCR_MTYP_SHIFT)
+#  define FSMC_BCR_SRAM           (0 << FSMC_BCR_MTYP_SHIFT)
+#  define FSMC_BCR_ROM            (0 << FSMC_BCR_MTYP_SHIFT)
+#  define FSMC_BCR_PSRAM          (1 << FSMC_BCR_MTYP_SHIFT)
+#  define FSMC_BCR_CRAM           (1 << FSMC_BCR_MTYP_SHIFT)
+#  define FSMC_BCR_NOR            (2 << FSMC_BCR_MTYP_SHIFT)
+#define FSMC_BCR_MWID_SHIFT       (4)        /* Memory data bus width */
+#define FSMC_BCR_MWID_MASK        (3 <<  FSMC_BCR_MWID_SHIFT)
+#  define FSMC_BCR_MWID8          (0 << FSMC_BCR_MWID_SHIFT)
+#  define FSMC_BCR_MWID16         (1 << FSMC_BCR_MWID_SHIFT)
+#define FSMC_BCR_FACCEN           (1 << 6)   /* Flash access enable */
+#define FSMC_BCR_BURSTEN          (1 << 8)   /* Burst enable bit */
+#define FSMC_BCR_WAITPOL          (1 << 9)   /* Wait signal polarity bit */
+#define FSMC_BCR_WRAPMOD          (1 << 10)  /* Wrapped burst mode support */
+#define FSMC_BCR_WAITCFG          (1 << 11)  /* Wait timing configuration */
+#define FSMC_BCR_WREN             (1 << 12)  /* Write enable bit */
+#define FSMC_BCR_WAITEN           (1 << 13)  /* Wait enable bit */
+#define FSMC_BCR_EXTMOD           (1 << 14)  /* Extended mode enable */
+#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
+#  define FSMC_BCR_ASYNCWAIT      (1 << 15)  /* Wait signal during asynchronous transfers */
+#endif
+#define FSMC_BCR_CBURSTRW         (1 << 19)  /* Write burst enable */
+
+#define FSMC_BCR_RSTVALUE         0x000003d2
+
+#define FSMC_BTR_ADDSET_SHIFT     (0)        /* Address setup phase duration */
+#define FSMC_BTR_ADDSET_MASK      (15 << FSMC_BTR_ADDSET_SHIFT)
+#  define FSMC_BTR_ADDSET(n)      ((n-1) << FSMC_BTR_ADDSET_SHIFT)  /* (n)xHCLK n=1..16 */
+#define FSMC_BTR_ADDHLD_SHIFT     (4)        /* Address-hold phase duration */
+#define FSMC_BTR_ADDHLD_MASK      (15 << FSMC_BTR_ADDHLD_SHIFT)
+#  define FSMC_BTR_ADDHLD(n)      ((n-1) << FSMC_BTR_ADDHLD_SHIFT)  /* (n)xHCLK n=2..16*/
+#define FSMC_BTR_DATAST_SHIFT     (8)        /* Data-phase duration */
+#define FSMC_BTR_DATAST_MASK      (255 << FSMC_BTR_DATAST_SHIFT)
+#  define FSMC_BTR_DATAST(n)      ((n-1) << FSMC_BTR_DATAST_SHIFT)  /* (n)xHCLK n=2..256 */
+#define FSMC_BTR_BUSTURN_SHIFT    (16)       /* Bus turnaround phase duration */
+#define FSMC_BTR_BUSTURN_MASK     (15 << FSMC_BTR1_BUSTURN_SHIFT)
+#  define FSMC_BTR_BUSTURN(n)     ((n-1) << FSMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */
+#define FSMC_BTR_CLKDIV_SHIFT     (20)       /* Clock divide ratio */
+#define FSMC_BTR_CLKDIV_MASK      (15 << FSMC_BTR_CLKDIV_SHIFT)
+#  define FSMC_BTR_CLKDIV(n)      ((n-1) << FSMC_BTR_CLKDIV_SHIFT)  /* (n)xHCLK n=2..16 */
+#define FSMC_BTR_DATLAT_SHIFT     (24)      /* Data latency */
+#define FSMC_BTR_DATLAT_MASK      (15 << FSMC_BTR_DATLAT_SHIFT)
+#  define FSMC_BTR_DATLAT(n)      ((n-2) << FSMC_BTR_DATLAT_SHIFT)  /* (n)xHCLK n=2..17 */
+#define FSMC_BTR_ACCMOD_SHIFT     (28)      /* Access mode */
+#define FSMC_BTR_ACCMOD_MASK      (3 << FSMC_BTR_ACCMOD_SHIFT)
+#  define FSMC_BTR_ACCMODA        (0 << FSMC_BTR_ACCMOD_SHIFT)
+#  define FSMC_BTR_ACCMODB        (1 << FSMC_BTR_ACCMOD_SHIFT)
+#  define FSMC_BTR_ACCMODC        (2 << FSMC_BTR_ACCMOD_SHIFT)
+#  define FSMC_BTR_ACCMODD        (3 << FSMC_BTR_ACCMOD_SHIFT)
+
+#define FSMC_BTR_RSTVALUE         0xffffffff
+
+#define FSMC_BWTR_ADDSET_SHIFT    (0)        /* Address setup phase duration */
+#define FSMC_BWTR_ADDSET_MASK     (15 << FSMC_BWTR_ADDSET_SHIFT)
+#  define FSMC_BWTR_ADDSET(n)     ((n-1) << FSMC_BWTR_ADDSET_SHIFT)  /* (n)xHCLK n=1..16 */
+#define FSMC_BWTR_ADDHLD_SHIFT    (4)        /* Address-hold phase duration */
+#define FSMC_BWTR_ADDHLD_MASK     (15 << FSMC_BWTR_ADDHLD_SHIFT)
+#  define FSMC_BWTR_ADDHLD(n)     ((n-1) << FSMC_BWTR_ADDHLD_SHIFT)  /* (n)xHCLK n=2..16*/
+#define FSMC_BWTR_DATAST_SHIFT    (8)        /* Data-phase duration */
+#define FSMC_BWTR_DATAST_MASK     (255 << FSMC_BWTR_DATAST_SHIFT)
+#  define FSMC_BWTR_DATAST(n)     ((n-1) << FSMC_BWTR_DATAST_SHIFT)  /* (n)xHCLK n=2..256 */
+#define FSMC_BWTR_CLKDIV_SHIFT    (20)       /* Clock divide ratio */
+#define FSMC_BWTR_CLKDIV_MASK     (15 << FSMC_BWTR_CLKDIV_SHIFT)
+#  define FSMC_BWTR_CLKDIV(n)     ((n-1) << FSMC_BWTR_CLKDIV_SHIFT)  /* (n)xHCLK n=2..16 */
+#define FSMC_BWTR_DATLAT_SHIFT    (24)      /* Data latency */
+#define FSMC_BWTR_DATLAT_MASK     (15 << FSMC_BWTR_DATLAT_SHIFT)
+#  define FSMC_BWTR_DATLAT(n)     ((n-2) << FSMC_BWTR_DATLAT_SHIFT)  /* (n)xHCLK n=2..17 */
+#define FSMC_BWTR_ACCMOD_SHIFT    (28)      /* Access mode */
+#define FSMC_BWTR_ACCMOD_MASK     (3 << FSMC_BWTR_ACCMOD_SHIFT)
+#  define FSMC_BWTR_ACCMODA       (0 << FSMC_BWTR_ACCMOD_SHIFT)
+#  define FSMC_BWTR_ACCMODB       (1 << FSMC_BWTR_ACCMOD_SHIFT)
+#  define FSMC_BWTR_ACCMODC       (2 << FSMC_BWTR_ACCMOD_SHIFT)
+#  define FSMC_BWTR_ACCMODD       (3 << FSMC_BTR_ACCMOD_SHIFT)
+
+#define FSMC_PCR_PWAITEN          (1 << 1)  /* Wait feature enable bit */
+#define FSMC_PCR_PBKEN            (1 << 2)  /* PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR_PTYP             (1 << 3)  /* Memory type */
+#define FSMC_PCR_PWID_SHIFT       (4)       /* NAND Flash databus width */
+#define FSMC_PCR_PWID_MASK        (3 <<  FSMC_PCR_PWID_SHIFT)
+#  define FSMC_PCR_PWID8          (0 <<  FSMC_PCR_PWID_SHIFT)
+#  define FSMC_PCR_PWID16         (1 <<  FSMC_PCR_PWID_SHIFT)
+#define FSMC_PCR_ECCEN            (1 << 6)  /* ECC computation logic enable bit */
+#define FSMC_PCR_TCLR_SHIFT       (9)       /* CLE to RE delay */
+#define FSMC_PCR_TCLR_MASK        (15 << FSMC_PCR_TCLR_SHIFT)
+#  define FSMC_PCR_TCLR(n)        ((n-1) << FSMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */
+#define FSMC_PCR_TAR_SHIFT        (13)      /* ALE to RE delay */
+#define FSMC_PCR_TAR_MASK         (15 <<  FSMC_PCR_TAR_MASK)
+#  define FSMC_PCR_TAR(n)         ((n-1) << FSMC_PCR_TAR_SHIFT)  /* (n)xHCLK n=1..16 */
+#define FSMC_PCR_ECCPS_SHIFT      (17)      /* ECC page size */
+#define FSMC_PCR_ECCPS_MASK       (7 << FSMC_PCR_ECCPS_SHIFT)
+#  define FSMC_PCR_ECCPS256       (0 << FSMC_PCR_ECCPS_SHIFT) /* 256 bytes */
+#  define FSMC_PCR_ECCPS512       (1 << FSMC_PCR_ECCPS_SHIFT) /* 512 bytes */
+#  define FSMC_PCR_ECCPS1024      (2 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
+#  define FSMC_PCR_ECCPS2048      (3 << FSMC_PCR_ECCPS_SHIFT) /* 2048 bytes */
+#  define FSMC_PCR_ECCPS4096      (4 << FSMC_PCR_ECCPS_SHIFT) /* 8192 bytes */
+#  define FSMC_PCR_ECCPS8192      (5 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
+
+#define FSMC_SR_IRS               (1 << 0)  /* Interrupt Rising Edge status */
+#define FSMC_SR_ILS               (1 << 1)  /* Interrupt Level status */
+#define FSMC_SR_IFS               (1 << 2)  /* Interrupt Falling Edge status */
+#define FSMC_SR_IREN              (1 << 3)  /* Interrupt Rising Edge detection Enable bit */
+#define FSMC_SR_ILEN              (1 << 4)  /* Interrupt Level detection Enable bit */
+#define FSMC_SR_IFEN              (1 << 5)  /* Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR_FEMPT             (1 << 6)  /* FIFO empty */
+
+#define FSMC_PMEM_MEMSET_SHIFT    (0)       /* Common memory setup time */
+#define FSMC_PMEM_MEMSET_MASK     (255 << FSMC_PMEM_MEMSET_SHIFT)
+#  define FSMC_PMEM_MEMSET(n)     ((n-1) << FSMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */
+#define FSMC_PMEM_MEMWAIT_SHIFT   (8)       /* Common memory wait time */
+#define FSMC_PMEM_MEMWAIT_MASK    (255 << FSMC_PMEM_MEMWAIT_SHIFT)
+#  define FSMC_PMEM_MEMWAIT(n)    ((n-1) << FSMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */
+#define FSMC_PMEM_MEMHOLD_SHIFT   (16)      /* Common memoryhold time */
+#define FSMC_PMEM_MEMHOLD_MASK    (255 << FSMC_PMEM_MEMHOLD_SHIFT)
+#  define FSMC_PMEM_MEMHOLD(n)    ((n) <<  FSMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */
+#define FSMC_PMEM_MEMHIZ_SHIFT    (24)       /* Common memory databus HiZ time */
+#define FSMC_PMEM_MEMHIZ_MASK     (255 << FSMC_PMEM_MEMHIZ_SHIFT)
+#  define FSMC_PMEM_MEMHIZ(n)     ((n) << FSMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */
+
+#define FSMC_PATT_ATTSET_SHIFT    (0)       /* Attribute memory setup time */
+#define FSMC_PATT_ATTSET_MASK     (255 << FSMC_PATT_ATTSET_SHIFT)
+#  define FSMC_PATT_ATTSET(n)     ((n-1) << FSMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */
+#define FSMC_PATT_ATTWAIT_SHIFT   (8)       /* Attribute memory wait time */
+#define FSMC_PATT_ATTWAIT_MASK    (255 << FSMC_PATT_ATTWAIT_SHIFT)
+#  define FSMC_PATT_ATTWAIT(n)    ((n-1) << FSMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */
+#define FSMC_PATT_ATTHOLD_SHIFT   (16)      /* Attribute memory hold time */
+#define FSMC_PATT_ATTHOLD_MASK    (255 << FSMC_PATT_ATTHOLD_SHIFT)
+#  define FSMC_PATT_ATTHOLD(n)    ((n) <<  FSMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */
+#define FSMC_PATT_ATTHIZ_SHIFT    (24)       /* Attribute memory databus HiZ time */
+#define FSMC_PATT_ATTHIZ_MASK     (255 << FSMC_PATT_ATTHIZ_SHIFT)
+#  define FSMC_PATT_ATTHIZ(n)     ((n) << FSMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */
+
+#define FSMC_PIO4_IOSET_SHIFT     (0)       /* IO memory setup time */
+#define FSMC_PIO4_IOSET_MASK      (255 << FSMC_PIO4_IOSET_SHIFT)
+#  define FSMC_PIO4_IOSET(n)      ((n-1) << FSMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */
+#define FSMC_PIO4_IOWAIT_SHIFT    (8)       /* IO memory wait time */
+#define FSMC_PIO4_IOWAIT_MASK     (255 << FSMC_PIO4_IOWAIT_SHIFT)
+#  define FSMC_PIO4_IOWAIT(n)     ((n-1) << FSMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */
+#define FSMC_PIO4_IOHOLD_SHIFT    (16)      /* IO memory hold time */
+#define FSMC_PIO4_IOHOLD_MASK     (255 << FSMC_PIO4_IOHOLD_SHIFT)
+#  define FSMC_PIO4_IOHOLD(n)     ((n) <<  FSMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */
+#define FSMC_PIO4_IOHIZ_SHIFT     (24)       /* IO memory databus HiZ time */
+#define FSMC_PIO4_IOHIZ_MASK      (255 << FSMC_PIO4_IOHIZ_SHIFT)
+#  define FSMC_PIO4_IOHIZ(n)      ((n) << FSMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */
+
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H */
diff --git a/arch/arm/src/stm32/hardware/stm32_i2c.h b/arch/arm/src/stm32/hardware/stm32_i2c.h
new file mode 100644
index 00000000000..75a556ffe37
--- /dev/null
+++ b/arch/arm/src/stm32/hardware/stm32_i2c.h
@@ -0,0 +1,53 @@
+/************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32_i2c.h
+ *
+ *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H
+
+/* There are 2 main types of I2C IP cores among STM32 chips:
+ *   1. STM32 I2C IPv1 - F1, F2, F4 and L1
+ *   2. STM32 I2C IPv2 - G0, L0, F0, F3, F7, H7 and L4
+ */
+
+#if defined(CONFIG_STM32_HAVE_IP_I2C_V1)
+#  include "stm32_i2c_v1.h"
+#elif defined(CONFIG_STM32_HAVE_IP_I2C_V2)
+#  include "stm32_i2c_v2.h"
+#else
+#  error STM32 I2C IP version not specified
+#endif
+
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H */
+
diff --git a/arch/arm/src/stm32/chip/stm32_i2c.h b/arch/arm/src/stm32/hardware/stm32_i2c_v1.h
similarity index 95%
rename from arch/arm/src/stm32/chip/stm32_i2c.h
rename to arch/arm/src/stm32/hardware/stm32_i2c_v1.h
index 682059772c3..de25b0222b9 100644
--- a/arch/arm/src/stm32/chip/stm32_i2c.h
+++ b/arch/arm/src/stm32/hardware/stm32_i2c_v1.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_i2c.h
+ * arch/arm/src/stm32/hardware/stm32_i2c_v1.h
  *
  *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,10 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H
+
+/* This file provide definitions for the STM32 I2C IP core 1 (F1, F2, F4 and L1) */
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -69,7 +71,7 @@
 #  define STM32_I2C1_CCR        (STM32_I2C1_BASE+STM32_I2C_CCR_OFFSET)
 #  define STM32_I2C1_TRISE      (STM32_I2C1_BASE+STM32_I2C_TRISE_OFFSET)
 #  ifdef STM32_I2C_FLTR_OFFSET
-#    define STM32_I2C1_FLTR       (STM32_I2C1_BASE+STM32_I2C_FLTR_OFFSET)
+#    define STM32_I2C1_FLTR     (STM32_I2C1_BASE+STM32_I2C_FLTR_OFFSET)
 #  endif
 #endif
 
@@ -84,7 +86,7 @@
 #  define STM32_I2C2_CCR        (STM32_I2C2_BASE+STM32_I2C_CCR_OFFSET)
 #  define STM32_I2C2_TRISE      (STM32_I2C2_BASE+STM32_I2C_TRISE_OFFSET)
 #  ifdef STM32_I2C_FLTR_OFFSET
-#    define STM32_I2C2_FLTR       (STM32_I2C2_BASE+STM32_I2C_FLTR_OFFSET)
+#    define STM32_I2C2_FLTR     (STM32_I2C2_BASE+STM32_I2C_FLTR_OFFSET)
 #  endif
 #endif
 
@@ -99,7 +101,7 @@
 #  define STM32_I2C3_CCR        (STM32_I2C3_BASE+STM32_I2C_CCR_OFFSET)
 #  define STM32_I2C3_TRISE      (STM32_I2C3_BASE+STM32_I2C_TRISE_OFFSET)
 #  ifdef STM32_I2C_FLTR_OFFSET
-#    define STM32_I2C3_FLTR       (STM32_I2C3_BASE+STM32_I2C_FLTR_OFFSET)
+#    define STM32_I2C3_FLTR     (STM32_I2C3_BASE+STM32_I2C_FLTR_OFFSET)
 #  endif
 #endif
 
@@ -209,5 +211,5 @@
 #  define I2C_FLTR_DNF_MASK     (0xf << I2C_FLTR_DNF_SHIFT)
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_I2C_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_i2c.h b/arch/arm/src/stm32/hardware/stm32_i2c_v2.h
similarity index 97%
rename from arch/arm/src/stm32/chip/stm32f30xxx_i2c.h
rename to arch/arm/src/stm32/hardware/stm32_i2c_v2.h
index 40a0bee37e3..60b8c184e3c 100644
--- a/arch/arm/src/stm32/chip/stm32f30xxx_i2c.h
+++ b/arch/arm/src/stm32/hardware/stm32_i2c_v2.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f30xxx_i2c.h
+ * arch/arm/src/stm32/hardware/stm32_i2c_v2.h
  *
  *   Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,11 +33,11 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_I2C_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_I2C_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H
 
-/* This file provide definitions for the STM32 I2C IP core 2 (F0, F3, F7, H7, and
- * L4).
+/* This file provide definitions for the STM32 I2C IP core 2 (G0, L0, F0, F3, F7,
+ * H7, and L4).
  */
 
 /************************************************************************************
@@ -250,5 +250,5 @@
 
 #define I2C_TXDR_MASK             (0xff)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_I2C_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32_lcd.h b/arch/arm/src/stm32/hardware/stm32_lcd.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32_lcd.h
rename to arch/arm/src/stm32/hardware/stm32_lcd.h
index 70d6be54894..9fa74a94f84 100644
--- a/arch/arm/src/stm32/chip/stm32_lcd.h
+++ b/arch/arm/src/stm32/hardware/stm32_lcd.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_lcd.h
+ * arch/arm/src/stm32/hardware/stm32_lcd.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32_LCD_H
-#define __ARCH_ARM_STC_STM32_CHIP_STM32_LCD_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H
 
 /************************************************************************************
  * Included Files
@@ -210,4 +210,4 @@
 #define LCD_RAMH_S(n)             (1 << ((n)-32))
 
 #endif /* STM32_NLCD */
-#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32_LCD_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H */
diff --git a/arch/arm/src/stm32/chip/stm32_ltdc.h b/arch/arm/src/stm32/hardware/stm32_ltdc.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32_ltdc.h
rename to arch/arm/src/stm32/hardware/stm32_ltdc.h
index 8ae45ddaa4d..d7e9234f5f6 100644
--- a/arch/arm/src/stm32/chip/stm32_ltdc.h
+++ b/arch/arm/src/stm32/hardware/stm32_ltdc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_ltdc.h
+ * arch/arm/src/stm32/hardware/stm32_ltdc.h
  *
  *   Copyright (C) 2013 Ken Pettit. All rights reserved.
  *   Author: Ken Pettit 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_LTDC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_LTDC_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/stm32_memorymap.h"
+#include "hardware/stm32_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -378,4 +378,4 @@
  * Public Types
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_LTDC_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H */
diff --git a/arch/arm/src/stm32/chip/stm32_memorymap.h b/arch/arm/src/stm32/hardware/stm32_memorymap.h
similarity index 81%
rename from arch/arm/src/stm32/chip/stm32_memorymap.h
rename to arch/arm/src/stm32/hardware/stm32_memorymap.h
index e32d5a647aa..68ab4c0c624 100644
--- a/arch/arm/src/stm32/chip/stm32_memorymap.h
+++ b/arch/arm/src/stm32/hardware/stm32_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_memorymap.h
+ * arch/arm/src/stm32/hardware/stm32_memorymap.h
  *
  *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -44,22 +44,22 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32_STM32L15XX)
-#  include "chip/stm32l15xxx_memorymap.h"
+#  include "hardware/stm32l15xxx_memorymap.h"
 #elif defined(CONFIG_STM32_STM32F10XX)
-#  include "chip/stm32f10xxx_memorymap.h"
+#  include "hardware/stm32f10xxx_memorymap.h"
 #elif defined(CONFIG_STM32_STM32F20XX)
-#  include "chip/stm32f20xxx_memorymap.h"
+#  include "hardware/stm32f20xxx_memorymap.h"
 #elif defined(CONFIG_STM32_STM32F30XX)
-#  include "chip/stm32f30xxx_memorymap.h"
+#  include "hardware/stm32f30xxx_memorymap.h"
 #elif defined(CONFIG_STM32_STM32F33XX)
-#  include "chip/stm32f33xxx_memorymap.h"
+#  include "hardware/stm32f33xxx_memorymap.h"
 #elif defined(CONFIG_STM32_STM32F37XX)
-#  include "chip/stm32f37xxx_memorymap.h"
+#  include "hardware/stm32f37xxx_memorymap.h"
 #elif defined(CONFIG_STM32_STM32F4XXX)
-#  include "chip/stm32f40xxx_memorymap.h"
+#  include "hardware/stm32f40xxx_memorymap.h"
 #else
 #  error "Unsupported STM32 memory map"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32_otghs.h b/arch/arm/src/stm32/hardware/stm32_otghs.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32_otghs.h
rename to arch/arm/src/stm32/hardware/stm32_otghs.h
index d3a900f7407..67431405035 100644
--- a/arch/arm/src/stm32/chip/stm32_otghs.h
+++ b/arch/arm/src/stm32/hardware/stm32_otghs.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32_otghs.h
+ * arch/arm/src/stm32/hardware/stm32_otghs.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_OTGHS_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_OTGHS_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H
 
 /****************************************************************************************************
  * Included Files
@@ -1047,4 +1047,4 @@
 #define OTGHS_PCGCCTL_PHYSUSP           (1 << 4)  /* Bit 4: PHY Suspended */
                                                   /* Bits 5-31: Reserved, must be kept at reset value */
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_OTGHS_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H */
diff --git a/arch/arm/src/stm32/hardware/stm32_pinmap.h b/arch/arm/src/stm32/hardware/stm32_pinmap.h
new file mode 100644
index 00000000000..f287c3a4b0c
--- /dev/null
+++ b/arch/arm/src/stm32/hardware/stm32_pinmap.h
@@ -0,0 +1,137 @@
+/************************************************************************************
+ * arch/arm/src/stm32/hardware/stm32_pinmap.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PINMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+/* STM32L EnergyLite Line ***********************************************************/
+
+#if defined(CONFIG_STM32_ENERGYLITE)
+
+/* STM32L15xx family */
+
+#  if defined(CONFIG_STM32_STM32L15XX)
+#    include "hardware/stm32l15xxx_pinmap.h"
+#  else
+#    error "Unsupported EnergyLite chip"
+#  endif
+
+/* STM32 F1 Family ******************************************************************/
+
+#elif defined(CONFIG_STM32_STM32F10XX)
+
+/* STM32F100 Value Line */
+
+#  if defined(CONFIG_STM32_VALUELINE)
+#    include "hardware/stm32f100_pinmap.h"
+
+/* STM32 F102 USB Access Medium Density Family */
+#  elif defined(CONFIG_ARCH_CHIP_STM32F102CB)
+#    include "hardware/stm32f102_pinmap.h"
+
+/* STM32 F103 Low / Medium Density Family */
+#  elif defined(CONFIG_ARCH_CHIP_STM32F103C4) || \
+        defined(CONFIG_ARCH_CHIP_STM32F103C8) || \
+        defined(CONFIG_ARCH_CHIP_STM32F103CB)
+#    include "hardware/stm32f103c_pinmap.h"
+
+/* STM32 F103 High Density Family */
+/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin packages and differ
+ * only in the available FLASH and SRAM.
+ */
+
+#  elif defined(CONFIG_ARCH_CHIP_STM32F103RB) || \
+        defined(CONFIG_ARCH_CHIP_STM32F103RC) || \
+        defined(CONFIG_ARCH_CHIP_STM32F103RD) || \
+        defined(CONFIG_ARCH_CHIP_STM32F103RE) || \
+        defined(CONFIG_ARCH_CHIP_STM32F103RG)
+#    include "hardware/stm32f103r_pinmap.h"
+
+/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin packages and differ
+ * only in the available FLASH and SRAM.
+ */
+
+#  elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE)
+#    include "hardware/stm32f103v_pinmap.h"
+
+/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin packages and differ
+ * only in the available FLASH and SRAM.
+ */
+#  elif defined(CONFIG_ARCH_CHIP_STM32F103ZE)
+#    include "hardware/stm32f103z_pinmap.h"
+
+/* STM32 F105/F107 Connectivity Line */
+
+#  elif defined(CONFIG_ARCH_CHIP_STM32F105VB)
+#    include "hardware/stm32f105v_pinmap.h"
+
+#  elif defined(CONFIG_ARCH_CHIP_STM32F105RB)
+#    include "hardware/stm32f105r_pinmap.h"
+
+#  elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
+#    include "hardware/stm32f107v_pinmap.h"
+#  else
+#    error "Unsupported STM32F10XXX chip"
+#  endif
+
+/* STM32 F2 Family ******************************************************************/
+
+#elif defined(CONFIG_STM32_STM32F20XX)
+#  include "hardware/stm32f20xxx_pinmap.h"
+
+/* STM32 F3 Family ******************************************************************/
+
+#elif defined(CONFIG_STM32_STM32F30XX)
+#  include "hardware/stm32f30xxx_pinmap.h"
+#elif defined(CONFIG_STM32_STM32F33XX)
+#  include "hardware/stm32f33xxx_pinmap.h"
+#elif defined(CONFIG_STM32_STM32F37XX)
+#  include "hardware/stm32f37xxx_pinmap.h"
+
+/* STM32 F4 Family ******************************************************************/
+
+#elif defined(CONFIG_STM32_STM32F4XXX)
+#  include "hardware/stm32f40xxx_pinmap.h"
+#else
+#  error "No pinmap file for this STM32 chip"
+#endif
+
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PINMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32_pwr.h b/arch/arm/src/stm32/hardware/stm32_pwr.h
similarity index 97%
rename from arch/arm/src/stm32/chip/stm32_pwr.h
rename to arch/arm/src/stm32/hardware/stm32_pwr.h
index 6fa55afc6e6..8e309f1df5b 100644
--- a/arch/arm/src/stm32/chip/stm32_pwr.h
+++ b/arch/arm/src/stm32/hardware/stm32_pwr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_pwr.h
+ * arch/arm/src/stm32/hardware/stm32_pwr.h
  *
  *   Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_PWR_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_PWR_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H
 
 /************************************************************************************
  * Included Files
@@ -170,4 +170,4 @@
 #  define PWR_CSR_ODSWRDY      (1 << 17) /* Bit 17: Over Drive Switch ready */
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_PWR_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H */
diff --git a/arch/arm/src/stm32/chip/stm32_rng.h b/arch/arm/src/stm32/hardware/stm32_rng.h
similarity index 94%
rename from arch/arm/src/stm32/chip/stm32_rng.h
rename to arch/arm/src/stm32/hardware/stm32_rng.h
index 5e31d58174f..61bb8e5a59d 100644
--- a/arch/arm/src/stm32/chip/stm32_rng.h
+++ b/arch/arm/src/stm32/hardware/stm32_rng.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_rng.h
+ * arch/arm/src/stm32/hardware/stm32_rng.h
  *
  *   Copyright (C) 2012 Max Holtzberg. All rights reserved.
  *   Author: Max Holtzberg 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32_RNG_H
-#define __ARCH_ARM_STC_STM32_CHIP_STM32_RNG_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H
 
 /************************************************************************************
  * Included Files
@@ -74,4 +74,4 @@
 #define RNG_SR_CEIS               (1 << 5) /* Bit 5: Clock error interrupt status */
 #define RNG_SR_SEIS               (1 << 6) /* Bit 6: Seed error interrupt status */
 
-#endif	/* __ARCH_ARM_STC_STM32_CHIP_STM32_RNG_H */
+#endif	/* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H */
diff --git a/arch/arm/src/stm32/chip/stm32_rtc.h b/arch/arm/src/stm32/hardware/stm32_rtc.h
similarity index 96%
rename from arch/arm/src/stm32/chip/stm32_rtc.h
rename to arch/arm/src/stm32/hardware/stm32_rtc.h
index e5004c5ab8f..820f7a8712b 100644
--- a/arch/arm/src/stm32/chip/stm32_rtc.h
+++ b/arch/arm/src/stm32/hardware/stm32_rtc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_rtc.h
+ * arch/arm/src/stm32/hardware/stm32_rtc.h
  *
  *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_RTC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_RTC_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -93,4 +93,4 @@
 #define RTC_DIVH_RTC_DIV_SHIFT  (0)      /* Bits 3-0: RTC Clock Divider High */
 #define RTC_DIVH_RTC_DIV_MASK   (0x0f << RTC_DIVH_RTC_DIV_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_RTC_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H */
diff --git a/arch/arm/src/stm32/chip/stm32_rtcc.h b/arch/arm/src/stm32/hardware/stm32_rtcc.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32_rtcc.h
rename to arch/arm/src/stm32/hardware/stm32_rtcc.h
index c8712c32e96..fa1700dfe76 100644
--- a/arch/arm/src/stm32/chip/stm32_rtcc.h
+++ b/arch/arm/src/stm32/hardware/stm32_rtcc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_rtcc.h.h
+ * arch/arm/src/stm32/hardware/stm32_rtcc.h.h
  *
  *   Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_RTCC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_RTCC_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -414,4 +414,4 @@
 #define RTC_ALRMSSR_MASKSS_SHIFT  (24)  /* Bits 24-27:  Mask the most-significant bits starting at this bit */
 #define RTC_ALRMSSR_MASKSS_MASK   (0xf << RTC_ALRMSSR_MASKSS_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_RTCC_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H */
diff --git a/arch/arm/src/stm32/chip/stm32_sdio.h b/arch/arm/src/stm32/hardware/stm32_sdio.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32_sdio.h
rename to arch/arm/src/stm32/hardware/stm32_sdio.h
index 7f1a68b485e..0d52cdcd41d 100644
--- a/arch/arm/src/stm32/chip/stm32_sdio.h
+++ b/arch/arm/src/stm32/hardware/stm32_sdio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_sdio.h
+ * arch/arm/src/stm32/hardware/stm32_sdio.h
  *
  *   Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_SDIO_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_SDIO_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -287,5 +287,5 @@
 #define SDIO_FIFOCNT_SHIFT             (0)
 #define SDIO_FIFOCNT_MASK              (0x01ffffff << SDIO_FIFOCNT_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_SDIO_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32_spi.h b/arch/arm/src/stm32/hardware/stm32_spi.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32_spi.h
rename to arch/arm/src/stm32/hardware/stm32_spi.h
index cf9a9e0118e..c78700466fa 100644
--- a/arch/arm/src/stm32/chip/stm32_spi.h
+++ b/arch/arm/src/stm32/hardware/stm32_spi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_spi.h
+ * arch/arm/src/stm32/hardware/stm32_spi.h
  *
  *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32_SPI_H
-#define __ARCH_ARM_STC_STM32_CHIP_STM32_SPI_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H
 
 /************************************************************************************
  * Included Files
@@ -256,4 +256,4 @@
 #    define SPI_I2SPR_MCKOE          (1 << 9)  /* Bit 9: Master clock output enable */
 #endif
 
-#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32_SPI_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H */
diff --git a/arch/arm/src/stm32/chip/stm32_tim.h b/arch/arm/src/stm32/hardware/stm32_tim.h
similarity index 95%
rename from arch/arm/src/stm32/chip/stm32_tim.h
rename to arch/arm/src/stm32/hardware/stm32_tim.h
index 1f91e5c2d37..458357adc78 100644
--- a/arch/arm/src/stm32/chip/stm32_tim.h
+++ b/arch/arm/src/stm32/hardware/stm32_tim.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32_tim.h
+ * arch/arm/src/stm32/hardware/stm32_tim.h
  *
  *   Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_TIM_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_TIM_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -47,17 +47,17 @@
 /* TIM version **************************************************************************************/
 
 /* Chip has extended version of ADV Timers (F3/F7/H7/L4/L4+):
-     - CCMR3, CCR5 and CCR6 registers
-     - OC5 and OC6
-     - 32-bit CCMR register
-     - UIFREMAP bit in CR1 register
-     - TRGO2 configuration in CR2 register
-     - OCCS bit and 4-bit SMS in SMCR register
-
-   Chip has extended version of General Timers 2-5 (F3/F7/H7/L4/L4+):
-     - UIFREMAP bit in CR1 register
-     - 4-bit SMS in SMCR register
-*/
+ *   - CCMR3, CCR5 and CCR6 registers
+ *   - OC5 and OC6
+ *   - 32-bit CCMR register
+ *   - UIFREMAP bit in CR1 register
+ *   - TRGO2 configuration in CR2 register
+ *   - OCCS bit and 4-bit SMS in SMCR register
+ *
+ *  Chip has extended version of General Timers 2-5 (F3/F7/H7/L4/L4+):
+ *   - UIFREMAP bit in CR1 register
+ *   - 4-bit SMS in SMCR register
+ */
 
 #if defined(CONFIG_STM32_HAVE_IP_TIMERS_V2)
 #  define HAVE_IP_TIMERS_V2
@@ -129,13 +129,6 @@
 
 #define STM32_GTIM_OR_OFFSET       0x0050  /* Timer 2/5/11/16 option register */
 
-/* TIM16, and 17 only.
- * Only available in the STM32 F1 Value Line and the STM32 F3 family.
- */
-
-#define STM32_GTIM_RCR_OFFSET      0x0030  /* Repetition counter register (TIM16/TIM17) */
-#define STM32_GTIM_BDTR_OFFSET     0x0044  /* Break and dead-time register (TIM16/TIM17) */
-
 /* Advanced Timers - TIM1 and TIM8 */
 
 #define STM32_ATIM_CR1_OFFSET      0x0000  /* Control register 1 (16-bit) */
@@ -1242,48 +1235,6 @@
 #  define GTIM_CCER_UIFCPY        (1 << 31) /* Bit 31: UIF copy */
 #endif
 
-/* Repitition counter (TIM15-17 only) */
-
-#define GTIM_RCR_REP_SHIFT        (0)       /* Bits 0-7: Repetition Counter Value */
-#define GTIM_RCR_REP_MASK         (0xff << GTIM_RCR_REP_SHIFT)
-
-#define GTIM_RCR_REP_MAX          128
-
-/* Break and dead-time register (TIM15-17 only) */
-
-#define GTIM_BDTR_DTG_SHIFT       (0)       /* Bits 7:0 [7:0]: Dead-Time Generator set-up */
-#define GTIM_BDTR_DTG_MASK        (0xff << GTIM_BDTR_DTG_SHIFT)
-#define GTIM_BDTR_LOCK_SHIFT      (8)       /* Bits 9:8 [1:0]: Lock Configuration */
-#define GTIM_BDTR_LOCK_MASK       (3 << GTIM_BDTR_LOCK_SHIFT)
-#  define GTIM_BDTR_LOCKOFF       (0 << GTIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
-#  define GTIM_BDTR_LOCK1         (1 << GTIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
-#  define GTIM_BDTR_LOCK2         (2 << GTIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
-#  define GTIM_BDTR_LOCK3         (3 << GTIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
-#define GTIM_BDTR_OSSI            (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
-#define GTIM_BDTR_OSSR            (1 << 11) /* Bit 11: Off-State Selection for Run mode */
-#define GTIM_BDTR_BKE             (1 << 12) /* Bit 12: Break enable */
-#define GTIM_BDTR_BKP             (1 << 13) /* Bit 13: Break Polarity */
-#define GTIM_BDTR_AOE             (1 << 14) /* Bit 14: Automatic Output enable */
-#define GTIM_BDTR_MOE             (1 << 15) /* Bit 15: Main Output enable */
-#define GTIM_BDTR_BKF_SHIFT       (16)      /* Bits 16-19: Break filter */
-#define GTIM_BDTR_BKF_MASK        (15 << GTIM_BDTR_BKF_SHIFT)
-#  define GTIM_BDTR_BKF_NOFILT    (0 << GTIM_BDTR_BKF_SHIFT)   /* 0000: No filter, BRK acts asynchronously */
-#  define GTIM_BDTR_BKF_FCKINT2   (1 << GTIM_BDTR_BKF_SHIFT)   /* 0001: fSAMPLING=fCK_INT, N=2 */
-#  define GTIM_BDTR_BKF_FCKINT4   (2 << GTIM_BDTR_BKF_SHIFT)   /* 0010: fSAMPLING=fCK_INT, N=4 */
-#  define GTIM_BDTR_BKF_FCKINT8   (3 << GTIM_BDTR_BKF_SHIFT)   /* 0011: fSAMPLING=fCK_INT, N=8 */
-#  define GTIM_BDTR_BKF_FDTSd26   (4 << GTIM_BDTR_BKF_SHIFT)   /* 0100: fSAMPLING=fDTS/2, N=6 */
-#  define GTIM_BDTR_BKF_FDTSd28   (5 << GTIM_BDTR_BKF_SHIFT)   /* 0101: fSAMPLING=fDTS/2, N=8 */
-#  define GTIM_BDTR_BKF_FDTSd36   (6 << GTIM_BDTR_BKF_SHIFT)   /* 0110: fSAMPLING=fDTS/4, N=6 */
-#  define GTIM_BDTR_BKF_FDTSd38   (7 << GTIM_BDTR_BKF_SHIFT)   /* 0111: fSAMPLING=fDTS/4, N=8 */
-#  define GTIM_BDTR_BKF_FDTSd86   (8 << GTIM_BDTR_BKF_SHIFT)   /* 1000: fSAMPLING=fDTS/8, N=6 */
-#  define GTIM_BDTR_BKF_FDTSd88   (9 << GTIM_BDTR_BKF_SHIFT)   /* 1001: fSAMPLING=fDTS/8, N=8 */
-#  define GTIM_BDTR_BKF_FDTSd165  (10 << GTIM_BDTR_BKF_SHIFT)  /* 1010: fSAMPLING=fDTS/16, N=5 */
-#  define GTIM_BDTR_BKF_FDTSd166  (11 << GTIM_BDTR_BKF_SHIFT)  /* 1011: fSAMPLING=fDTS/16, N=6 */
-#  define GTIM_BDTR_BKF_FDTSd168  (12 << GTIM_BDTR_BKF_SHIFT)  /* 1100: fSAMPLING=fDTS/16, N=8 */
-#  define GTIM_BDTR_BKF_FDTSd325  (13 << GTIM_BDTR_BKF_SHIFT)  /* 1101: fSAMPLING=fDTS/32, N=5 */
-#  define GTIM_BDTR_BKF_FDTSd326  (14 << GTIM_BDTR_BKF_SHIFT)  /* 1110: fSAMPLING=fDTS/32, N=6 */
-#  define GTIM_BDTR_BKF_FDTSd328  (15 << GTIM_BDTR_BKF_SHIFT)  /* 1111: fSAMPLING=fDTS/32, N=8 */
-
 /* DMA control register */
 
 #define GTIM_DCR_DBA_SHIFT        (0)       /* Bits 4-0: DMA Base Address */
@@ -1354,4 +1305,4 @@
 
 #define BTIM_EGR_UG               (1 << 0)  /* Bit 0: Update generation */
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_TIM_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H */
diff --git a/arch/arm/src/stm32/chip/stm32_usbdev.h b/arch/arm/src/stm32/hardware/stm32_usbdev.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32_usbdev.h
rename to arch/arm/src/stm32/hardware/stm32_usbdev.h
index f4013485cad..2583886f63e 100644
--- a/arch/arm/src/stm32/chip/stm32_usbdev.h
+++ b/arch/arm/src/stm32/hardware/stm32_usbdev.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_usbdev.h
+ * arch/arm/src/stm32/hardware/stm32_usbdev.h
  *
  *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_USBDEV_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_USBDEV_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include 
+#include "chip.h"
 
 #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) \
     || defined(CONFIG_STM32_STM32F37XX)
@@ -233,5 +233,5 @@
 #define USB_COUNT_RX_MASK            (0x03ff << USB_COUNT_RX_SHIFT)
 
 #endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F37XX */
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_USBDEV_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32_wdg.h b/arch/arm/src/stm32/hardware/stm32_wdg.h
similarity index 97%
rename from arch/arm/src/stm32/chip/stm32_wdg.h
rename to arch/arm/src/stm32/hardware/stm32_wdg.h
index f0f2916f4b7..9150b841bed 100644
--- a/arch/arm/src/stm32/chip/stm32_wdg.h
+++ b/arch/arm/src/stm32/hardware/stm32_wdg.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_wdg.h
+ * arch/arm/src/stm32/hardware/stm32_wdg.h
  *
  *   Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_WDG_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_WDG_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H
 
 /************************************************************************************
  * Included Files
@@ -159,4 +159,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_WDG_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H */
diff --git a/arch/arm/src/stm32/chip/stm32f100_pinmap.h b/arch/arm/src/stm32/hardware/stm32f100_pinmap.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f100_pinmap.h
rename to arch/arm/src/stm32/hardware/stm32f100_pinmap.h
index 1ab898e9fe5..3d3bcb4c094 100644
--- a/arch/arm/src/stm32/chip/stm32f100_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f100_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f100_pinmap.h
+ * arch/arm/src/stm32/hardware/stm32f100_pinmap.h
  *
  *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2011 Uros Platise. All rights reserved.
@@ -38,8 +38,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F100_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F100_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F100_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F100_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -392,4 +392,4 @@
 #define GPIO_UART5_TX       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
 #define GPIO_UART5_RX       (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F100_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F100_PINMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f102_pinmap.h b/arch/arm/src/stm32/hardware/stm32f102_pinmap.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32f102_pinmap.h
rename to arch/arm/src/stm32/hardware/stm32f102_pinmap.h
index 20cecf5b7cc..1721ad14a75 100644
--- a/arch/arm/src/stm32/chip/stm32f102_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f102_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f102_pinmap.h
+ * arch/arm/src/stm32/hardware/stm32f102_pinmap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F102_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F102_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F102_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F102_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -255,4 +255,4 @@
 #    endif
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F102_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F102_PINMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f103c_pinmap.h b/arch/arm/src/stm32/hardware/stm32f103c_pinmap.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32f103c_pinmap.h
rename to arch/arm/src/stm32/hardware/stm32f103c_pinmap.h
index 35838f70b07..2c58ea3589d 100644
--- a/arch/arm/src/stm32/chip/stm32f103c_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f103c_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f103c_pinmap.h
+ * arch/arm/src/stm32/hardware/stm32f103c_pinmap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  * have the full complement of remapping.
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F103C_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F103C_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F103C_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F103C_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -273,4 +273,4 @@
 #    endif
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F103C_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F103C_PINMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f103r_pinmap.h b/arch/arm/src/stm32/hardware/stm32f103r_pinmap.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f103r_pinmap.h
rename to arch/arm/src/stm32/hardware/stm32f103r_pinmap.h
index 7750f67f1ac..87d563c2fe2 100644
--- a/arch/arm/src/stm32/chip/stm32f103r_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f103r_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f103r_pinmap.h
+ * arch/arm/src/stm32/hardware/stm32f103r_pinmap.h
  *
  *   Copyright (C) 2009, 2014 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2011 Uros Platise. All rights reserved.
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F103R_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F103R_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F103R_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F103R_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -355,4 +355,4 @@
 #define GPIO_SDIO_CK      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
 #define GPIO_SDIO_CMD     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN2)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F103R_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F103R_PINMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f103v_pinmap.h b/arch/arm/src/stm32/hardware/stm32f103v_pinmap.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f103v_pinmap.h
rename to arch/arm/src/stm32/hardware/stm32f103v_pinmap.h
index fb1fe462d41..0a0314f1368 100644
--- a/arch/arm/src/stm32/chip/stm32f103v_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f103v_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f103v_pinmap.h
+ * arch/arm/src/stm32/hardware/stm32f103v_pinmap.h
  *
  *   Copyright (C) 2011, 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F103V_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F103V_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F103V_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F103V_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -429,4 +429,4 @@
 #define GPIO_PB4                (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F103V_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F103V_PINMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f103z_pinmap.h b/arch/arm/src/stm32/hardware/stm32f103z_pinmap.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f103z_pinmap.h
rename to arch/arm/src/stm32/hardware/stm32f103z_pinmap.h
index 1f520fd48d6..f21c41aca66 100644
--- a/arch/arm/src/stm32/chip/stm32f103z_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f103z_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f103z_pinmap.h
+ * arch/arm/src/stm32/hardware/stm32f103z_pinmap.h
  *
  *   Copyright (C) 2009, 2011-2012, 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F103Z_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F103Z_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F103Z_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F103Z_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -586,5 +586,5 @@
 #define GPIO_NAND_NCE2    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN7)
 #define GPIO_NAND_NCE3    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTG|GPIO_PIN9)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F103Z_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F103Z_PINMAP_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f105r_pinmap.h b/arch/arm/src/stm32/hardware/stm32f105r_pinmap.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f105r_pinmap.h
rename to arch/arm/src/stm32/hardware/stm32f105r_pinmap.h
index 8ba082981b9..19351347462 100644
--- a/arch/arm/src/stm32/chip/stm32f105r_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f105r_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f105r_pinmap.h
+ * arch/arm/src/stm32/hardware/stm32f105r_pinmap.h
  *
  *   Copyright (C) 2009, 2011, 2014, 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F105R_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F105R_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F105R_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F105R_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -325,4 +325,4 @@
 #define GPIO_PB4                (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F105R_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F105R_PINMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f105v_pinmap.h b/arch/arm/src/stm32/hardware/stm32f105v_pinmap.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f105v_pinmap.h
rename to arch/arm/src/stm32/hardware/stm32f105v_pinmap.h
index 40716c76f7b..01cf03384b9 100644
--- a/arch/arm/src/stm32/chip/stm32f105v_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f105v_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f105v_pinmap.h
+ * arch/arm/src/stm32/hardware/stm32f105v_pinmap.h
  *
  *   Copyright (C) 2009, 2011, 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F105V_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F105V_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F105V_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F105V_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -373,4 +373,4 @@
 #define GPIO_PB4                (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F105V_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F105V_PINMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f107v_pinmap.h b/arch/arm/src/stm32/hardware/stm32f107v_pinmap.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f107v_pinmap.h
rename to arch/arm/src/stm32/hardware/stm32f107v_pinmap.h
index 6ed9d6a879a..40af7382ebf 100644
--- a/arch/arm/src/stm32/chip/stm32f107v_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f107v_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f107v_pinmap.h
+ * arch/arm/src/stm32/hardware/stm32f107v_pinmap.h
  *
  *   Copyright (C) 2009, 2011, 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F107V_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F107V_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F107V_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F107V_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -417,4 +417,4 @@
 #define GPIO_PB4                (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F107V_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F107V_PINMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h b/arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
rename to arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h
index 11c33343451..7474c36d3f6 100644
--- a/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
+++ b/arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
+ * arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h
  *
  *   Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_GPIO_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_GPIO_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_GPIO_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_GPIO_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -396,5 +396,5 @@
 #  define AFIO_MAPR2_MISC_REMAP          (1 << 13)  /* Bit 13: Miscellaneous features remapping */
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_GPIO_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_GPIO_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h b/arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h
similarity index 96%
rename from arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h
rename to arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h
index 93d241f328f..f67b91923e7 100644
--- a/arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h
+++ b/arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h
+ * arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h
  *
  *   Copyright (C) 2009, 2011, 3013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_MEMORYMAP_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -132,7 +132,8 @@
 #define STM32_RCC_BASE       0x40021000     /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */
                                             /* 0x40021400 - 0x40021fff:  Reserved */
 #define STM32_OTGFS_BASE     0x50000000     /* 0x50000000 - 0x500003ff: USB OTG FS */
-#define STM32_FLASHIF_BASE   0x40022000     /* 0x40022000 - 0x400223ff: Flash memory interface */
+#define STM32_FLASHIF_BASE   0x40022000     /* 0x40022000 - 0x4002203f: Flash memory I/F (Bank 0)*/
+#define STM32_FLASHIF1_BASE  0x40022040     /* 0x40022024 - 0x400223ff: Flash memory I/F (Bank 1)*/
 #define STM32_CRC_BASE       0x40028000     /* 0x40023000 - 0x400233ff: CRC */
                                             /* 0x40023400 - 0x40027fff: Reserved */
 #define STM32_ETHERNET_BASE  0x40028000     /* 0x40028000 - 0x40029fff: Ethernet */
@@ -159,5 +160,5 @@
 #define STM32_SCS_BASE       0xe000e000
 #define STM32_DEBUGMCU_BASE  0xe0042000
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_MEMORYMAP_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h b/arch/arm/src/stm32/hardware/stm32f10xxx_rcc.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
rename to arch/arm/src/stm32/hardware/stm32f10xxx_rcc.h
index 75bd3a9c7cd..ae0d8b4907f 100644
--- a/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
+++ b/arch/arm/src/stm32/hardware/stm32f10xxx_rcc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f10xx_rcc.h
+ * arch/arm/src/stm32/hardware/stm32f10xx_rcc.h
  *
  *   Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_RCC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_RCC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_RCC_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -475,5 +475,5 @@
 
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_RCC_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f10xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f10xxx_uart.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32f10xxx_uart.h
rename to arch/arm/src/stm32/hardware/stm32f10xxx_uart.h
index 414f34c9094..56d5b833378 100644
--- a/arch/arm/src/stm32/chip/stm32f10xxx_uart.h
+++ b/arch/arm/src/stm32/hardware/stm32f10xxx_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f10xxx_uart.h
+ * arch/arm/src/stm32/hardware/stm32f10xxx_uart.h
  *
  *   Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32F10XXX_UART_H
-#define __ARCH_ARM_STC_STM32_CHIP_STM32F10XXX_UART_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H
 
 /************************************************************************************
  * Included Files
@@ -214,4 +214,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32F10XXX_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H */
diff --git a/arch/arm/src/stm32/chip/stm32f20xxx_gpio.h b/arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32f20xxx_gpio.h
rename to arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h
index 9bdb562ef33..4fbc3f9fad8 100644
--- a/arch/arm/src/stm32/chip/stm32f20xxx_gpio.h
+++ b/arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f20xxx_gpio.h
+ * arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_GPIO_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_GPIO_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_GPIO_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_GPIO_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -366,5 +366,5 @@
 #define GPIO_AFRH15_SHIFT          (28)
 #define GPIO_AFRH15_MASK           (15 << GPIO_AFRH15_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_GPIO_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_GPIO_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h b/arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h
rename to arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h
index bfb4e5200f0..d657318ea17 100644
--- a/arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h
+++ b/arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h
+ * arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_MEMORYMAP_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -205,5 +205,5 @@
 #define STM32_SCS_BASE      0xe000e000
 #define STM32_DEBUGMCU_BASE 0xe0042000
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_MEMORYMAP_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h b/arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h
rename to arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h
index 742d7671d51..47e5b38ad66 100644
--- a/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h
+ * arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -59,7 +59,7 @@
  *
  * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
  *
- * The driver will then automatically configre PA11 as the CAN1 RX pin.
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -696,5 +696,5 @@
 #define GPIO_USART6_TX_1      (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
 #define GPIO_USART6_TX_2      (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_PINMAP_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f20xxx_rcc.h b/arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f20xxx_rcc.h
rename to arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h
index c1e09404797..d00191a489a 100644
--- a/arch/arm/src/stm32/chip/stm32f20xxx_rcc.h
+++ b/arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32f20xxx_rcc.h
+ * arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h
  *
  *   Copyright (C) 2012, 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_RCC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_RCC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_RCC_H
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -502,5 +502,5 @@
 #define RCC_PLLI2SCFGR_PLLI2SR_SHIFT (28)      /* Bits 28-30: PLLI2S division factor for I2S clocks */
 #define RCC_PLLI2SCFGR_PLLI2SR_MASK  (7 << RCC_PLLI2SCFGR_PLLI2SR_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_RCC_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f20xxx_syscfg.h b/arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h
similarity index 97%
rename from arch/arm/src/stm32/chip/stm32f20xxx_syscfg.h
rename to arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h
index 7f92a73f4c4..b455f15081f 100644
--- a/arch/arm/src/stm32/chip/stm32f20xxx_syscfg.h
+++ b/arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32f20xxx_syscfg.h
+ * arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h
  *
  *   Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -148,4 +148,4 @@
 #define SYSCFG_CMPCR_READY            (1 << 8)  /* Bit 8: Compensation cell ready flag */
 
 #endif /* CONFIG_STM32_STM32F20XX */
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F20XXX_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_SYSCFG_H */
diff --git a/arch/arm/src/stm32/chip/stm32f20xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f20xxx_uart.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32f20xxx_uart.h
rename to arch/arm/src/stm32/hardware/stm32f20xxx_uart.h
index 4da5c0af2e0..aa3fc0a148b 100644
--- a/arch/arm/src/stm32/chip/stm32f20xxx_uart.h
+++ b/arch/arm/src/stm32/hardware/stm32f20xxx_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f20xxx_uart.h
+ * arch/arm/src/stm32/hardware/stm32f20xxx_uart.h
  *
  *   Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32F20XXX_UART_H
-#define __ARCH_ARM_STC_STM32_CHIP_STM32F20XXX_UART_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H
 
 /************************************************************************************
  * Included Files
@@ -226,4 +226,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32F20XXX_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H */
diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_gpio.h b/arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32f30xxx_gpio.h
rename to arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h
index fef3f2149d8..6b5ec23ef82 100644
--- a/arch/arm/src/stm32/chip/stm32f30xxx_gpio.h
+++ b/arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f30xxx_gpio.h
+ * arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_GPIO_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_GPIO_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_GPIO_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_GPIO_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -328,5 +328,5 @@
 
 #define GPIO_BRR(n)                (1 << (n))
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_GPIO_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_GPIO_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h b/arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h
similarity index 96%
rename from arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
rename to arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h
index be3dbaf590b..be8b1c51e48 100644
--- a/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
+++ b/arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
+ * arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_MEMORYMAP_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -133,7 +133,8 @@
 #define STM32_DMA1_BASE      0x40020000     /* 0x40020000-0x400203ff: DMA1  */
 #define STM32_DMA2_BASE      0x40020400     /* 0x40020400-0x400207ff: DMA2  */
 #define STM32_RCC_BASE       0x40021000     /* 0x40021000-0x400213ff: Reset and Clock control RCC */
-#define STM32_FLASHIF_BASE   0x40022000     /* 0x40022000-0x400223ff: Flash memory interface */
+#define STM32_FLASHIF_BASE   0x40022000     /* 0x40022000-0x4002203f: Flash memory I/F (Bank 0) */
+#define STM32_FLASHIF1_BASE  0x40022040     /* 0x40022000-0x400223ff: Flash memory I/F (Bank 1) */
 #define STM32_CRC_BASE       0x40023000     /* 0x40023000-0x400233ff: CRC */
 #define STM32_TSC_BASE       0x40024000     /* 0x40024000-0x400243ff: TSC */
 
@@ -159,5 +160,5 @@
 #define STM32_SCS_BASE      0xe000e000
 #define STM32_DEBUGMCU_BASE 0xe0042000
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_MEMORYMAP_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h b/arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h
rename to arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h
index 2714c83bcac..3adcfdd49c0 100644
--- a/arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h
+ * arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2015-2016 Omni Hoverboards Inc. All rights reserved.
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -61,7 +61,7 @@
  *
  * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
  *
- * The driver will then automatically configre PA11 as the CAN1 RX pin.
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -666,4 +666,4 @@
 #define GPIO_PF9_EVENT_OUT  (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN9)
 #define GPIO_PF10_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN10)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_PINMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_rcc.h b/arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f30xxx_rcc.h
rename to arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h
index ebcaa76a3b5..6f0f0915e6a 100644
--- a/arch/arm/src/stm32/chip/stm32f30xxx_rcc.h
+++ b/arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f30xx_rcc.h
+ * arch/arm/src/stm32/hardware/stm32f30xx_rcc.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_RCC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_RCC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_RCC_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -394,5 +394,5 @@
 #  define RCC_CFGR3_UART5SW_LSE     (2 << RCC_CFGR3_UART5SW_SHIFT) /* LSE clock */
 #  define RCC_CFGR3_UART5SW_HSI     (0 << RCC_CFGR3_UART5SW_SHIFT) /* HSI clock */
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_RCC_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_syscfg.h b/arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32f30xxx_syscfg.h
rename to arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h
index a4bf5d184ca..eda3ccf2b55 100644
--- a/arch/arm/src/stm32/chip/stm32f30xxx_syscfg.h
+++ b/arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32f30xxx_syscfg.h
+ * arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -174,4 +174,4 @@
 #define SYSCFG_CFGR2_SRAM_PEF         (1 << 8)  /* Bit 8: SRAM parity error */
 
 #endif /* CONFIG_STM32_STM32F30XX */
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_SYSCFG_H */
diff --git a/arch/arm/src/stm32/chip/stm32f30xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f30xxx_uart.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32f30xxx_uart.h
rename to arch/arm/src/stm32/hardware/stm32f30xxx_uart.h
index 5593e6848ff..a60271ceffd 100644
--- a/arch/arm/src/stm32/chip/stm32f30xxx_uart.h
+++ b/arch/arm/src/stm32/hardware/stm32f30xxx_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f30xxx_uart.h
+ * arch/arm/src/stm32/hardware/stm32f30xxx_uart.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32F30XXX_UART_H
-#define __ARCH_ARM_STC_STM32_CHIP_STM32F30XXX_UART_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H
 
 /************************************************************************************
  * Included Files
@@ -347,4 +347,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32F30XXX_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H */
diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_comp.h b/arch/arm/src/stm32/hardware/stm32f33xxx_comp.h
similarity index 97%
rename from arch/arm/src/stm32/chip/stm32f33xxx_comp.h
rename to arch/arm/src/stm32/hardware/stm32f33xxx_comp.h
index cb3ce96a8fc..27449a90a18 100644
--- a/arch/arm/src/stm32/chip/stm32f33xxx_comp.h
+++ b/arch/arm/src/stm32/hardware/stm32f33xxx_comp.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32f33xxx_comp.h
+ * arch/arm/src/stm32/hardware/stm32f33xxx_comp.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_COMP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_COMP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H
 
 /****************************************************************************************************
  * Included Files
@@ -122,4 +122,4 @@
 
 
 
-#endif                          /* __ARCH_ARM_SRC_STM32_CHIP_STM32_COMP_H */
+#endif                          /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h b/arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h
rename to arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h
index 5f1ca17821b..bbbe56b7aea 100644
--- a/arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h
+++ b/arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32f33xxx_hrtim.h
+ * arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_HRTIM_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_HRTIM_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_HRTIM_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_HRTIM_H
 
 /****************************************************************************************************
  * Included Files
@@ -1815,4 +1815,4 @@
 #define HRTIM_BDMADR_SHIFT             0         /* Bits 0-31: Burst DMA Data register */
 #define HRTIM_BDMADR_MASK              (0xffffffff << HRTIM_BDMADR_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_HRTIM_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_HRTIM_H */
diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h b/arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h
similarity index 95%
rename from arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h
rename to arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h
index 8c85ff6af3d..a493c94c1fc 100644
--- a/arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h
+++ b/arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h
+ * arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_MEMORYMAP_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -122,7 +122,8 @@
 
 #define STM32_DMA1_BASE      0x40020000     /* 0x40020000-0x400203ff: DMA1  */
 #define STM32_RCC_BASE       0x40021000     /* 0x40021000-0x400213ff: Reset and Clock control RCC */
-#define STM32_FLASHIF_BASE   0x40022000     /* 0x40022000-0x400223ff: Flash memory interface */
+#define STM32_FLASHIF_BASE   0x40022000     /* 0x40022000-0x4002203f: Flash memory I/F (Bank 0) */
+#define STM32_FLASHIF1_BASE  0x40022040     /* 0x40022000-0x400223ff: Flash memory I/F (Bank 1) */
 #define STM32_CRC_BASE       0x40023000     /* 0x40023000-0x400233ff: CRC */
 #define STM32_TSC_BASE       0x40024000     /* 0x40024000-0x400243ff: TSC */
 
@@ -147,4 +148,4 @@
 #define STM32_SCS_BASE      0xe000e000
 #define STM32_DEBUGMCU_BASE 0xe0042000
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_opamp.h b/arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h
similarity index 97%
rename from arch/arm/src/stm32/chip/stm32f33xxx_opamp.h
rename to arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h
index 3a254af3a80..04220aed39b 100644
--- a/arch/arm/src/stm32/chip/stm32f33xxx_opamp.h
+++ b/arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32f33xxx_opamp.h
+ * arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_OPAMP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32_OPAMP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OPAMP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OPAMP_H
 
 /****************************************************************************************************
  * Included Files
@@ -114,4 +114,4 @@
 #define OPAMP_CSR_OUTCAL            (1 << 30)   /* Bit 30: OPAMP output status flag */
 #define OPAMP_CSR_LOCK              (1 << 31)   /* Bit 31: OPAMP 2 lock */
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_OPAMP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OPAMP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h b/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h
rename to arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h
index d9d3826f033..55cfc6bb5c6 100644
--- a/arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h
+ * arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -60,7 +60,7 @@
  *
  * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
  *
- * The driver will then automatically configre PA11 as the CAN1 RX pin.
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -463,4 +463,4 @@
 
 #define GPIO_PD2_EVENT_OUT  (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN2)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_PINMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_rcc.h b/arch/arm/src/stm32/hardware/stm32f33xxx_rcc.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f33xxx_rcc.h
rename to arch/arm/src/stm32/hardware/stm32f33xxx_rcc.h
index ef65a7d436b..cd25c936492 100644
--- a/arch/arm/src/stm32/chip/stm32f33xxx_rcc.h
+++ b/arch/arm/src/stm32/hardware/stm32f33xxx_rcc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f33xx_rcc.h
+ * arch/arm/src/stm32/hardware/stm32f33xx_rcc.h
  * For STM32F33xx advanced ARM-based 32-bit MCUs
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_RCC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_RCC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_RCC_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -358,4 +358,4 @@
 #  define RCC_CFGR3_USART3SW_LSE    (2 << RCC_CFGR3_USART3SW_SHIFT) /* LSE clock */
 #  define RCC_CFGR3_USART3SW_HSI    (0 << RCC_CFGR3_USART3SW_SHIFT) /* HSI clock */
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_RCC_H */
diff --git a/arch/arm/src/stm32/chip/stm32f33xxx_syscfg.h b/arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32f33xxx_syscfg.h
rename to arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h
index 52309ceccdd..7a154ec83ee 100644
--- a/arch/arm/src/stm32/chip/stm32f33xxx_syscfg.h
+++ b/arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32f33xxx_syscfg.h
+ * arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -207,4 +207,4 @@
 #define SYSCFG_CFGR3_DAC1_TRIG5_RMP          (1 << 17)  /* Bit 17: HRTIM1_DAC1_TRIG2 remap */
 
 #endif /* CONFIG_STM32_STM32F33XX */
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F33XXX_SYSCFG_H */
diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h b/arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h
similarity index 96%
rename from arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h
rename to arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h
index 10daaaae18a..9539af8b4b3 100644
--- a/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h
+++ b/arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h
+ * arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F37XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F37XXX_MEMORYMAP_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -133,7 +133,8 @@
 #define STM32_DMA1_BASE      0x40020000     /* 0x40020000-0x400203ff: DMA1  */
 #define STM32_DMA2_BASE      0x40020400     /* 0x40020400-0x400207ff: DMA2  */
 #define STM32_RCC_BASE       0x40021000     /* 0x40021000-0x400213ff: Reset and Clock control RCC */
-#define STM32_FLASHIF_BASE   0x40022000     /* 0x40022000-0x400223ff: Flash memory interface */
+#define STM32_FLASHIF_BASE   0x40022000     /* 0x40022000-0x4002203f: Flash memory I/F (Bank 0) */
+#define STM32_FLASHIF1_BASE  0x40022040     /* 0x40022000-0x400223ff: Flash memory I/F (Bank 1) */
 #define STM32_CRC_BASE       0x40023000     /* 0x40023000-0x400233ff: CRC */
 #define STM32_TSC_BASE       0x40024000     /* 0x40024000-0x400243ff: TSC */
 
@@ -154,4 +155,4 @@
 #define STM32_SCS_BASE      0xe000e000
 #define STM32_DEBUGMCU_BASE 0xe0042000
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F37XXX_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_pinmap.h b/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f37xxx_pinmap.h
rename to arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h
index a20ae8577f3..7c33d283047 100644
--- a/arch/arm/src/stm32/chip/stm32f37xxx_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f37xxx_pinmap.h
+ * arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F37XXX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F37XXX_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -60,7 +60,7 @@
  *
  * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
  *
- * The driver will then automatically configre PA11 as the CAN1 RX pin.
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -608,5 +608,5 @@
 #define GPIO_PF9_EVENT_OUT  (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN9)
 #define GPIO_PF10_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN10)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F37XXX_PINMAP_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_rcc.h b/arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f37xxx_rcc.h
rename to arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h
index 59d5d0c2695..4b724050ade 100644
--- a/arch/arm/src/stm32/chip/stm32f37xxx_rcc.h
+++ b/arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f37xx_rcc.h
+ * arch/arm/src/stm32/hardware/stm32f37xx_rcc.h
  * For STM32F37xx advanced ARM-based 32-bit MCUs
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_RCC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F37XXX_RCC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F37XXX_RCC_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -387,5 +387,5 @@
 #  define RCC_CFGR3_USART3SW_LSE    (2 << RCC_CFGR3_USART3SW_SHIFT) /* LSE clock */
 #  define RCC_CFGR3_USART3SW_HSI    (0 << RCC_CFGR3_USART3SW_SHIFT) /* HSI clock */
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F37XXX_RCC_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_sdadc.h b/arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32f37xxx_sdadc.h
rename to arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h
index 011ab4d58fd..3a309ad77c2 100644
--- a/arch/arm/src/stm32/chip/stm32f37xxx_sdadc.h
+++ b/arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32f37xxx_sdadc.h
+ * arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h
  *
  *   Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2016 Studelec SA. All rights reserved.
@@ -35,8 +35,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_SDADC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_SDADC_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F37XXX_SDADC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F37XXX_SDADC_H
 
 /****************************************************************************************************
  * Included Files
@@ -301,4 +301,4 @@
  * Public Function Prototypes
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_SDADC_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F37XXX_SDADC_H */
diff --git a/arch/arm/src/stm32/chip/stm32f37xxx_syscfg.h b/arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h
similarity index 97%
rename from arch/arm/src/stm32/chip/stm32f37xxx_syscfg.h
rename to arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h
index 6b4ccd227dd..24c69052b2d 100644
--- a/arch/arm/src/stm32/chip/stm32f37xxx_syscfg.h
+++ b/arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32f37xxx_syscfg.h
+ * arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F37XXX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F37XXX_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -163,4 +163,4 @@
 #define SYSCFG_CFGR2_SRAM_PEF         (1 << 8)  /* Bit 8: SRAM parity error */
 
 #endif /* CONFIG_STM32_STM32F37XX */
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F37XXX_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F37XXX_SYSCFG_H */
diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h b/arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32f40xxx_gpio.h
rename to arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h
index 7d4b33b666a..4191b0c7010 100644
--- a/arch/arm/src/stm32/chip/stm32f40xxx_gpio.h
+++ b/arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f40xxx_gpio.h
+ * arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h
  *
  *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_GPIO_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_GPIO_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_GPIO_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_GPIO_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -392,5 +392,5 @@
 #define GPIO_AFRH15_SHIFT          (28)
 #define GPIO_AFRH15_MASK           (15 << GPIO_AFRH15_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_GPIO_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_GPIO_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h b/arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h
similarity index 92%
rename from arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h
rename to arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h
index 3fad83490bc..6517ec21b47 100644
--- a/arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h
+++ b/arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h
+ * arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h
  *
  *   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_MEMORYMAP_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -45,6 +45,7 @@
 #define STM32_CODE_BASE      0x00000000     /* 0x00000000-0x1fffffff: 512Mb code block */
 #define STM32_SRAM_BASE      0x20000000     /* 0x20000000-0x3fffffff: 512Mb sram block */
 #define STM32_PERIPH_BASE    0x40000000     /* 0x40000000-0x5fffffff: 512Mb peripheral block */
+
 #define STM32_FSMC_BASE12    0x60000000     /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
 #  define STM32_FSMC_BANK1   0x60000000     /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
 #  define STM32_FSMC_BANK2   0x70000000     /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
@@ -52,7 +53,18 @@
 #  define STM32_FSMC_BANK3   0x80000000     /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
 #  define STM32_FSMC_BANK4   0x90000000     /* 0x90000000-0x9fffffff: 256Mb PC CARD*/
 #define STM32_FSMC_BASE      0xa0000000     /* 0xa0000000-0xbfffffff: 512Mb FSMC register block */
-                                            /* 0xc0000000-0xdfffffff: 512Mb (not used) */
+
+#define STM32_FMC_BASE12     0x60000000     /* 0x60000000-0x7fffffff: 512Mb FMC bank1&2 block */
+#  define STM32_FMC_BANK1    0x60000000     /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
+#  define STM32_FMC_BANK2    0x70000000     /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
+#define STM32_FMC_BASE34     0x80000000     /* 0x80000000-0x8fffffff: 512Mb FMC bank3&4 block */
+#  define STM32_FMC_BANK3    0x80000000     /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
+#  define STM32_FMC_BANK4    0x90000000     /* 0x90000000-0x9fffffff: 256Mb PC CARD*/
+#define STM32_FMC_BASE       0xa0000000     /* 0xa0000000-0xbfffffff: 512Mb FMC register block */
+#define STM32_FMC_BASE56     0x80000000     /* 0x80000000-0x8fffffff: 512Mb FMC bank5&6 block */
+#  define STM32_FMC_BANK5    0xc0000000     /* 0xc0000000-0xcfffffff: 256Mb SDRAM */
+#  define STM32_FMC_BANK6    0xd0000000     /* 0xd0000000-0xdfffffff: 256Mb SDRAM */
+
 #define STM32_CORTEX_BASE    0xe0000000     /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
 
 #define STM32_REGION_MASK    0xf0000000
@@ -215,5 +227,5 @@
 #define STM32_SCS_BASE      0xe000e000
 #define STM32_DEBUGMCU_BASE 0xe0042000
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_MEMORYMAP_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h b/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h
similarity index 88%
rename from arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
rename to arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h
index ac069fbb3d8..68f3d34ac37 100644
--- a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
+ * arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h
  *
  *   Copyright (C) 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
@@ -36,8 +36,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -258,6 +258,141 @@
 #  define GPIO_ETH_RMII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
 #endif
 
+/* Flexible Memory Controller (FMC) */
+
+#define GPIO_FMC_A0          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN0)
+#define GPIO_FMC_A1          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN1)
+#define GPIO_FMC_A2          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN2)
+#define GPIO_FMC_A3          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN3)
+#define GPIO_FMC_A4          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN4)
+#define GPIO_FMC_A5          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN5)
+#define GPIO_FMC_A6          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN12)
+#define GPIO_FMC_A7          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN13)
+#define GPIO_FMC_A8          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN14)
+#define GPIO_FMC_A9          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN15)
+#define GPIO_FMC_A10         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN0)
+#define GPIO_FMC_A11         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN1)
+#define GPIO_FMC_A12         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN2)
+#define GPIO_FMC_A13         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN3)
+#define GPIO_FMC_A14         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
+#define GPIO_FMC_A15         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
+#define GPIO_FMC_A16         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
+#define GPIO_FMC_A17         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
+#define GPIO_FMC_A18         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN13)
+#define GPIO_FMC_A19         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN3)
+#define GPIO_FMC_A20         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN4)
+#define GPIO_FMC_A21         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN5)
+#define GPIO_FMC_A22         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN6)
+#define GPIO_FMC_A23         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN2)
+#define GPIO_FMC_A24         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN13)
+#define GPIO_FMC_A25         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN14)
+#define GPIO_FMC_NBL1        (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN1)
+#define GPIO_FMC_CLK         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN3)
+#define GPIO_FMC_D0          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14)
+#define GPIO_FMC_D1          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15)
+#define GPIO_FMC_D2          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0)
+#define GPIO_FMC_D3          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1)
+#define GPIO_FMC_D4          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7)
+#define GPIO_FMC_D5          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8)
+#define GPIO_FMC_D6          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9)
+#define GPIO_FMC_D7          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10)
+#define GPIO_FMC_D8          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11)
+#define GPIO_FMC_D9          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12)
+#define GPIO_FMC_D10         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13)
+#define GPIO_FMC_D11         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14)
+#define GPIO_FMC_D12         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15)
+#define GPIO_FMC_D13         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
+#define GPIO_FMC_D14         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
+#define GPIO_FMC_D15         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10)
+#define GPIO_FMC_NBL0        (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN0)
+#define GPIO_FMC_NE1         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
+#define GPIO_FMC_NE2         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
+#define GPIO_FMC_NE3         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
+#define GPIO_FMC_NE4         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN12)
+#define GPIO_FMC_NL          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_FMC_NOE         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN4)
+#define GPIO_FMC_NWAIT       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6)
+#define GPIO_FMC_NWE         (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5)
+
+#define GPIO_FMC_INT3        (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN7)
+#define GPIO_FMC_NCE3        (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
+
+#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
+#  define GPIO_FMC_CD        (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN9)
+#  define GPIO_FMC_INT2      (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN6)
+#  define GPIO_FMC_INTR      (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN10)
+#  define GPIO_FMC_NCE2      (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
+#  define GPIO_FMC_NCE4_1    (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
+#  define GPIO_FMC_NCE4_2    (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN11)
+#  define GPIO_FMC_NIORD     (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN6)
+#  define GPIO_FMC_NIOWR     (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN8)
+#  define GPIO_FMC_SDCKE0_1  (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
+#  define GPIO_FMC_SDCKE0_2  (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3)
+#  define GPIO_FMC_SDNE0_1   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
+#  define GPIO_FMC_SDNE0_2   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2)
+#  define GPIO_FMC_SDNWE_1   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
+#  define GPIO_FMC_SDNWE_2   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5)
+#  define GPIO_FMC_SDNRAS    (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
+#  define GPIO_FMC_SDCLK     (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
+#  define GPIO_FMC_SDNCAS    (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)
+#  define GPIO_FMC_BA0       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
+#  define GPIO_FMC_BA1       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
+#  define GPIO_FMC_NREG      (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN7)
+#endif
+
+#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
+#  define GPIO_FMC_SDCKE0_1  (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3)
+#  define GPIO_FMC_SDCKE0_2  (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN5)
+#  define GPIO_FMC_SDNE0_1   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2)
+#  define GPIO_FMC_SDNE0_2   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN4)
+#  define GPIO_FMC_SDNWE_1   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN7)
+#  define GPIO_FMC_SDNWE_2   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
+#  define GPIO_FMC_SDNRAS    (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
+#  define GPIO_FMC_SDCLK     (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
+#  define GPIO_FMC_SDNCAS    (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)
+#  define GPIO_FMC_BA0       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
+#  define GPIO_FMC_BA1       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
+#endif
+
+#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
+    defined(CONFIG_STM32_STM32F469)
+#  define GPIO_FMC_D16       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN8)
+#  define GPIO_FMC_D17       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN9)
+#  define GPIO_FMC_D18       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN10)
+#  define GPIO_FMC_D19       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN11)
+#  define GPIO_FMC_D20       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN12)
+#  define GPIO_FMC_D21       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN13)
+#  define GPIO_FMC_D22       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN14)
+#  define GPIO_FMC_D23       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN15)
+#  define GPIO_FMC_D24       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN0)
+#  define GPIO_FMC_D25       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN1)
+#  define GPIO_FMC_D26       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN2)
+#  define GPIO_FMC_D27       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN3)
+#  define GPIO_FMC_D28       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6)
+#  define GPIO_FMC_D29       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7)
+#  define GPIO_FMC_D30       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN9)
+#  define GPIO_FMC_D31       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN10)
+#  define GPIO_FMC_NBL2      (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4)
+#  define GPIO_FMC_NBL3      (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5)
+#  define GPIO_FMC_SDCKE0_3  (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
+#  define GPIO_FMC_SDCKE1_1  (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
+#  define GPIO_FMC_SDCKE1_2  (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN7)
+#  define GPIO_FMC_SDNE0_3   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
+#  define GPIO_FMC_SDNE1_1   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
+#  define GPIO_FMC_SDNE1_2   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN6)
+#  define GPIO_FMC_SDNWE_3   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5)
+#endif
+
+#if defined(CONFIG_STM32_STM32F446)
+#  define GPIO_FMC_SDCKE1    (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
+#  define GPIO_FMC_SDNE1     (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
+#endif
+
+#if defined(CONFIG_STM32_STM32F469)
+#  define GPIO_FMC_CLE       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
+#  define GPIO_FMC_ALE       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
+#endif
+
 /* Flexible Static Memory Controller (FSMC) */
 
 #define GPIO_FSMC_A0          (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN0)
@@ -318,8 +453,7 @@
 #define GPIO_FSMC_NCE3        (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
 
 #if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
-    defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407) || \
-    defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
+    defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407)
 #  define GPIO_FSMC_CD        (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN9)
 #  define GPIO_FSMC_INT2      (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN6)
 #  define GPIO_FSMC_INTR      (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN10)
@@ -342,59 +476,6 @@
 #  define GPIO_FSMC_NREG      (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN7)
 #endif
 
-#if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
-#  define GPIO_FSMC_SDCKE0_1  (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3)
-#  define GPIO_FSMC_SDCKE0_2  (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN5)
-#  define GPIO_FSMC_SDNE0_1   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2)
-#  define GPIO_FSMC_SDNE0_2   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN4)
-#  define GPIO_FSMC_SDNWE_1   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN7)
-#  define GPIO_FSMC_SDNWE_2   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
-#  define GPIO_FSMC_SDNRAS    (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
-#  define GPIO_FSMC_SDCLK     (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
-#  define GPIO_FSMC_SDNCAS    (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)
-#  define GPIO_FSMC_BA0       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
-#  define GPIO_FSMC_BA1       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
-#endif
-
-#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
-    defined(CONFIG_STM32_STM32F469)
-#  define GPIO_FSMC_D16       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN8)
-#  define GPIO_FSMC_D17       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN9)
-#  define GPIO_FSMC_D18       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN10)
-#  define GPIO_FSMC_D19       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN11)
-#  define GPIO_FSMC_D20       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN12)
-#  define GPIO_FSMC_D21       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN13)
-#  define GPIO_FSMC_D22       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN14)
-#  define GPIO_FSMC_D23       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN15)
-#  define GPIO_FSMC_D24       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN0)
-#  define GPIO_FSMC_D25       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN1)
-#  define GPIO_FSMC_D26       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN2)
-#  define GPIO_FSMC_D27       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN3)
-#  define GPIO_FSMC_D28       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6)
-#  define GPIO_FSMC_D29       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7)
-#  define GPIO_FSMC_D30       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN9)
-#  define GPIO_FSMC_D31       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN10)
-#  define GPIO_FSMC_NBL2      (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4)
-#  define GPIO_FSMC_NBL3      (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5)
-#  define GPIO_FSMC_SDCKE0_3  (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
-#  define GPIO_FSMC_SDCKE1_1  (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
-#  define GPIO_FSMC_SDCKE1_2  (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN7)
-#  define GPIO_FSMC_SDNE0_3   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
-#  define GPIO_FSMC_SDNE1_1   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
-#  define GPIO_FSMC_SDNE1_2   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN6)
-#  define GPIO_FSMC_SDNWE_3   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5)
-#endif
-
-#if defined(CONFIG_STM32_STM32F446)
-#  define GPIO_FSMC_SDCKE1    (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
-#  define GPIO_FSMC_SDNE1     (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
-#endif
-
-#if defined(CONFIG_STM32_STM32F469)
-#  define GPIO_FSMC_CLE       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
-#  define GPIO_FSMC_ALE       (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
-#endif
-
 /* I2C */
 
 #define GPIO_I2C1_SCL_1       (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
@@ -1194,4 +1275,4 @@
 #  define GPIO_FMPI2C1_SMBA_2 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN13)
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_PINMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h b/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
rename to arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h
index 3b74b9a6b6b..1701c7b59da 100644
--- a/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
+++ b/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
+ * arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h
  *
  *   Copyright (C) 2009, 2011-2012, 2014-2015 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
@@ -36,8 +36,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_RCC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_RCC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_RCC_H
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -448,6 +448,7 @@
 /* AHB3 Peripheral Clock enable register */
 
 #define RCC_AHB3ENR_FSMCEN          (1 << 0)  /* Bit 0: Flexible static memory controller module clock enable */
+#define RCC_AHB3ENR_FMCEN           (1 << 0)  /* Bit 0: Flexible memory controller module clock enable */
 #if defined(CONFIG_STM32_STM32F446)
 #  define RCC_AHB3ENR_QSPIEN        (1 << 1)  /* Bit 1: QUADSPI memory controller module clock enable */
 #endif
@@ -900,4 +901,4 @@
 #    define RCC_DCKCFGR2_SPDIFRXSEL_PLLI2S (1 << RCC_DCKCFGR2_SPDIFRXSEL_SHIFT) /* PLLI2S clock is selected as SPDIF-Rx clock */
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_RCC_H */
diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_syscfg.h b/arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32f40xxx_syscfg.h
rename to arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h
index 98769f3dd44..af71e16e4bb 100644
--- a/arch/arm/src/stm32/chip/stm32f40xxx_syscfg.h
+++ b/arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32f40xxx_syscfg.h
+ * arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h
  *
  *   Copyright (C) 2011, 2013, 2014-2015 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
@@ -36,8 +36,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -199,4 +199,4 @@
 #endif
 
 #endif /* CONFIG_STM32_STM32F4XXX */
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_SYSCFG_H */
diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f40xxx_uart.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32f40xxx_uart.h
rename to arch/arm/src/stm32/hardware/stm32f40xxx_uart.h
index 9693baa5077..47afb0aba6e 100644
--- a/arch/arm/src/stm32/chip/stm32f40xxx_uart.h
+++ b/arch/arm/src/stm32/hardware/stm32f40xxx_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32f40xxx_uart.h
+ * arch/arm/src/stm32/hardware/stm32f40xxx_uart.h
  *
  *   Copyright (C) 2009, 2011-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32F40XXX_UART_H
-#define __ARCH_ARM_STC_STM32_CHIP_STM32F40XXX_UART_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H
 
 /************************************************************************************
  * Included Files
@@ -244,4 +244,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32F40XXX_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H */
diff --git a/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h b/arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h
rename to arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h
index c2b29f15282..a42ad5a87cf 100644
--- a/arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h
+++ b/arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32fxxxxx_otgfs.h
+ * arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h
  *
  *   Copyright (C) 2012, 2014-2016 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
@@ -36,8 +36,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32FXXXXX_OTGFS_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32FXXXXX_OTGFS_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H
 
 /****************************************************************************************************
  * Included Files
@@ -1043,4 +1043,4 @@
 #define OTGFS_PCGCCTL_PHYSUSP           (1 << 4)  /* Bit 4: PHY Suspended */
                                                   /* Bits 5-31: Reserved, must be kept at reset value */
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32FXXXXX_OTGFS_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H */
diff --git a/arch/arm/src/stm32/chip/stm32l15xxx_aes.h b/arch/arm/src/stm32/hardware/stm32l15xxx_aes.h
similarity index 95%
rename from arch/arm/src/stm32/chip/stm32l15xxx_aes.h
rename to arch/arm/src/stm32/hardware/stm32l15xxx_aes.h
index a692a314405..3c7c03ad1df 100644
--- a/arch/arm/src/stm32/chip/stm32l15xxx_aes.h
+++ b/arch/arm/src/stm32/hardware/stm32l15xxx_aes.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/arm/src/stm32/chip/stm32l15xxx_aes.h
+ * arch/arm/src/stm32/hardware/stm32l15xxx_aes.h
  * AES hardware accelerator for STM32L162xx advanced ARM-based
  * 32-bit MCUs
  *
@@ -35,8 +35,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_AES_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_AES_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_AES_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_AES_H
 
 /********************************************************************************************
  * Included Files
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32l15xxx_memorymap.h"
+#include "hardware/stm32l15xxx_memorymap.h"
 
 /********************************************************************************************
  * Pre-processor Definitions
@@ -114,4 +114,4 @@
 #define AES_SR_RDERR                       (1 << 1)       /* Read Error Flag */
 #define AES_SR_WRERR                       (1 << 2)       /* Write Error Flag */
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_AES_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_AES_H */
diff --git a/arch/arm/src/stm32/chip/stm32l15xxx_gpio.h b/arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32l15xxx_gpio.h
rename to arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h
index 0b339505ab8..b791d0206a1 100644
--- a/arch/arm/src/stm32/chip/stm32l15xxx_gpio.h
+++ b/arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32l15xxx_gpio.h
+ * arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h
  * For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based
  * 32-bit MCUs
  *
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_GPIO_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_GPIO_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_GPIO_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_GPIO_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -355,4 +355,4 @@
 #define GPIO_AFRH15_SHIFT          (28)
 #define GPIO_AFRH15_MASK           (15 << GPIO_AFRH15_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_GPIO_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_GPIO_H */
diff --git a/arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h b/arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h
similarity index 97%
rename from arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h
rename to arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h
index 8f70210f5de..7a5d0325b0b 100644
--- a/arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h
+++ b/arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h
+ * arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h
  * For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based
  * 32-bit MCUs
  *
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_MEMORYMAP_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -143,4 +143,4 @@
 #define STM32_SCS_BASE      0xe000e000
 #define STM32_DEBUGMCU_BASE 0xe0042000
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h b/arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h
rename to arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h
index 879ad4a160c..2bd8f57a731 100644
--- a/arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h
+++ b/arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h
+ * arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -57,7 +57,7 @@
  *
  * #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
  *
- * The driver will then automatically configre PB6 as the I2C1 SCL pin.
+ * The driver will then automatically configure PB6 as the I2C1 SCL pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -613,4 +613,4 @@
 #define GPIO_WKUP2          (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN13)
 #define GPIO_WKUP3          (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN6)
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_PINMAP_H */
diff --git a/arch/arm/src/stm32/chip/stm32l15xxx_rcc.h b/arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h
similarity index 99%
rename from arch/arm/src/stm32/chip/stm32l15xxx_rcc.h
rename to arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h
index ca022500ab3..8df4f0e20a1 100644
--- a/arch/arm/src/stm32/chip/stm32l15xxx_rcc.h
+++ b/arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32l15xx_rcc.h
+ * arch/arm/src/stm32/hardware/stm32l15xx_rcc.h
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_RCC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_RCC_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_RCC_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -461,5 +461,5 @@
 #define RCC_CSR_WWDGRSTF            (1 << 30) /* Bit 30: Window watchdog reset flag */
 #define RCC_CSR_LPWRRSTF            (1 << 31) /* Bit 31: Low-Power reset flag */
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_RCC_H */
 
diff --git a/arch/arm/src/stm32/chip/stm32l15xxx_syscfg.h b/arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h
similarity index 97%
rename from arch/arm/src/stm32/chip/stm32l15xxx_syscfg.h
rename to arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h
index a4558f62502..4e4f0255360 100644
--- a/arch/arm/src/stm32/chip/stm32l15xxx_syscfg.h
+++ b/arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32/chip/stm32l15xxx_syscfg.h
+ * arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h
  * For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based
  * 32-bit MCUs
  *
@@ -35,8 +35,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -156,4 +156,4 @@
 #define SYSCFG_EXTICR4_EXTI15_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
                                                 /* Bits 16-31: Reserved */
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32L15XXX_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_SYSCFG_H */
diff --git a/arch/arm/src/stm32/chip/stm32l15xxx_uart.h b/arch/arm/src/stm32/hardware/stm32l15xxx_uart.h
similarity index 98%
rename from arch/arm/src/stm32/chip/stm32l15xxx_uart.h
rename to arch/arm/src/stm32/hardware/stm32l15xxx_uart.h
index 4b85b837c76..7b942f450bf 100644
--- a/arch/arm/src/stm32/chip/stm32l15xxx_uart.h
+++ b/arch/arm/src/stm32/hardware/stm32l15xxx_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32l15xxx_uart.h
+ * arch/arm/src/stm32/hardware/stm32l15xxx_uart.h
  * For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based
  * 32-bit MCUs
  *
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32L15XXX_UART_H
-#define __ARCH_ARM_STC_STM32_CHIP_STM32L15XXX_UART_H
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H
 
 /************************************************************************************
  * Included Files
@@ -218,4 +218,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32L15XXX_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H */
diff --git a/arch/arm/src/stm32/stm32.h b/arch/arm/src/stm32/stm32.h
index fe61cd4811d..ad70df23b94 100644
--- a/arch/arm/src/stm32/stm32.h
+++ b/arch/arm/src/stm32/stm32.h
@@ -64,6 +64,7 @@
 #include "stm32_dac.h"
 #include "stm32_exti.h"
 #include "stm32_flash.h"
+#include "stm32_fmc.h"
 #include "stm32_fsmc.h"
 #include "stm32_gpio.h"
 #include "stm32_i2c.h"
diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c
index 3de146ae411..0073f3d06e6 100644
--- a/arch/arm/src/stm32/stm32_adc.c
+++ b/arch/arm/src/stm32/stm32_adc.c
@@ -3292,16 +3292,20 @@ static void adc_dumpregs(FAR struct stm32_dev_s *priv)
         adc_getreg(priv, STM32_ADC_CR2_OFFSET));
 #endif
 
-  ainfo("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x SQR4: 0x%08x\n",
+  ainfo("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n",
         adc_getreg(priv, STM32_ADC_SQR1_OFFSET),
         adc_getreg(priv, STM32_ADC_SQR2_OFFSET),
-        adc_getreg(priv, STM32_ADC_SQR3_OFFSET),
-        adc_getreg(priv, STM32_ADC_SQR4_OFFSET));
+        adc_getreg(priv, STM32_ADC_SQR3_OFFSET));
 
   ainfo("SMPR1: 0x%08x SMPR2: 0x%08x\n",
         adc_getreg(priv, STM32_ADC_SMPR1_OFFSET),
         adc_getreg(priv, STM32_ADC_SMPR2_OFFSET));
 
+#if defined(STM32_ADC_SQR4_OFFSET)
+  ainfo("SQR4: 0x%08x\n",
+        adc_getreg(priv, STM32_ADC_SQR5_OFFSET));
+#endif
+
 #if defined(STM32_ADC_SQR5_OFFSET)
   ainfo("SQR5: 0x%08x\n",
         adc_getreg(priv, STM32_ADC_SQR4_OFFSET));
diff --git a/arch/arm/src/stm32/stm32_adc.h b/arch/arm/src/stm32/stm32_adc.h
index 94e6690dc75..dcb59212b07 100644
--- a/arch/arm/src/stm32/stm32_adc.h
+++ b/arch/arm/src/stm32/stm32_adc.h
@@ -46,7 +46,7 @@
 
 #include "chip.h"
 
-#include "chip/stm32_adc.h"
+#include "hardware/stm32_adc.h"
 
 #include 
 
diff --git a/arch/arm/src/stm32/stm32_aes.c b/arch/arm/src/stm32/stm32_aes.c
index d72ab695af7..5c46040e012 100644
--- a/arch/arm/src/stm32/stm32_aes.c
+++ b/arch/arm/src/stm32/stm32_aes.c
@@ -167,8 +167,7 @@ static void stm32aes_encryptblock(FAR void *block_out, FAR const void *block_in)
   in++;
   putreg32(*in, STM32_AES_DINR);
 
-  while (!(getreg32(STM32_AES_SR) & AES_SR_CCF))
-    ;
+  while (!(getreg32(STM32_AES_SR) & AES_SR_CCF));
   stm32aes_ccfc();
 
   *out = getreg32(STM32_AES_DOUTR);
diff --git a/arch/arm/src/stm32/stm32_aes.h b/arch/arm/src/stm32/stm32_aes.h
index 50c0d22eab1..b4ceeea6be0 100644
--- a/arch/arm/src/stm32/stm32_aes.h
+++ b/arch/arm/src/stm32/stm32_aes.h
@@ -51,7 +51,7 @@
  */
 
 #ifdef CONFIG_STM32_STM32L15XX
-#  include "chip/stm32l15xxx_aes.h"
+#  include "hardware/stm32l15xxx_aes.h"
 #else
 #  error "Unknown chip for AES"
 #endif
diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c
index e97f1b97ab3..2ce15acfcfb 100644
--- a/arch/arm/src/stm32/stm32_allocateheap.c
+++ b/arch/arm/src/stm32/stm32_allocateheap.c
@@ -76,24 +76,23 @@
  *
  * CONFIG_STM32_CCMEXCLUDE    : Exclude CCM SRAM from the HEAP
  *
- * In addition to internal SRAM, SRAM may also be available through the FSMC.
- * In order to use FSMC SRAM, the following additional things need to be
- * present in the NuttX configuration file:
+ * In addition to internal SRAM, external RAM may also be available through the
+ * FMC/FSMC. To use external RAM, the following things need to be present in
+ * the NuttX configuration file:
  *
- * CONFIG_STM32_FSMC=y        : Enables the FSMC
- * CONFIG_STM32_FSMC_SRAM=y   : Indicates that SRAM is available via the
- *                              FSMC (as opposed to an LCD or FLASH).
- * CONFIG_HEAP2_BASE          : The base address of the SRAM in the FSMC
- *                              address space
- * CONFIG_HEAP2_SIZE          : The size of the SRAM in the FSMC
- *                              address space
- * CONFIG_MM_REGIONS          : Must be set to a large enough value to
- *                              include the FSMC SRAM (as determined by
- *                              the rules provided below)
+ * CONFIG_STM32_FSMC=y         : Enables the FSMC
+ * CONFIG_STM32_FMC=y          : Enables the FMC
+ * CONFIG_STM32_EXTERNAL_RAM=y : Indicates external RAM is available via the
+ *                               FMC/FSMC (as opposed to an LCD or FLASH).
+ * CONFIG_HEAP2_BASE           : The base address of the external RAM
+ * CONFIG_HEAP2_SIZE           : The size of the external RAM
+ * CONFIG_MM_REGIONS           : Must be set to a large enough value to
+ *                               include the external RAM (as determined by
+ *                               the rules provided below)
  */
 
-#ifndef CONFIG_STM32_FSMC
-#  undef CONFIG_STM32_FSMC_SRAM
+#if !defined(CONFIG_STM32_FSMC) && !defined(CONFIG_STM32_FMC)
+#  undef CONFIG_STM32_EXTERNAL_RAM
 #endif
 
 /* The STM32L15xxx family has only internal SRAM.  The heap is in one contiguous
@@ -108,7 +107,7 @@
 
    /* There is no FSMC (Other EnergyLite STM32's do have an FSMC, but not the STM32L15X */
 
-#  undef CONFIG_STM32_FSMC_SRAM
+#  undef CONFIG_STM32_EXTERNAL_RAM
 
    /* The STM32L EnergyLite family has no CCM SRAM */
 
@@ -134,10 +133,10 @@
 
    /* Check if external FSMC SRAM is provided */
 
-#  ifdef CONFIG_STM32_FSMC_SRAM
+#  ifdef CONFIG_STM32_EXTERNAL_RAM
 #    if CONFIG_MM_REGIONS < 2
 #      warning "FSMC SRAM not included in the heap"
-#      undef CONFIG_STM32_FSMC_SRAM
+#      undef CONFIG_STM32_EXTERNAL_RAM
 #    elif CONFIG_MM_REGIONS > 2
 #      error "CONFIG_MM_REGIONS > 2 but I don't know what some of the region(s) are"
 #      undef CONFIG_MM_REGIONS
@@ -173,7 +172,7 @@
 
    /* There is no FSMC */
 
-#  undef CONFIG_STM32_FSMC_SRAM
+#  undef CONFIG_STM32_EXTERNAL_RAM
 
    /* There are 2 possible SRAM configurations:
     *
@@ -243,7 +242,7 @@
 
    /* There is no FSMC */
 
-#  undef CONFIG_STM32_FSMC_SRAM
+#  undef CONFIG_STM32_EXTERNAL_RAM
 
    /* There are 2 possible SRAM configurations:
     *
@@ -305,7 +304,7 @@
 
    /* There is no FSMC */
 
-#  undef CONFIG_STM32_FSMC_SRAM
+#  undef CONFIG_STM32_EXTERNAL_RAM
 
    /* The STM32 F37xx has no CCM SRAM */
 
@@ -389,26 +388,26 @@
     *
     * Configuration 1. System SRAM (only)
     *                  CONFIG_MM_REGIONS == 1
-    *                  CONFIG_STM32_FSMC_SRAM NOT defined
+    *                  CONFIG_STM32_EXTERNAL_RAM NOT defined
     *                  CONFIG_STM32_CCMEXCLUDE defined
     * Configuration 2. System SRAM and CCM SRAM
     *                  CONFIG_MM_REGIONS == 2
-    *                  CONFIG_STM32_FSMC_SRAM NOT defined
+    *                  CONFIG_STM32_EXTERNAL_RAM NOT defined
     *                  CONFIG_STM32_CCMEXCLUDE NOT defined
     * Configuration 3. System SRAM and FSMC SRAM
     *                  CONFIG_MM_REGIONS == 2
-    *                  CONFIG_STM32_FSMC_SRAM defined
+    *                  CONFIG_STM32_EXTERNAL_RAM defined
     *                  CONFIG_STM32_CCMEXCLUDE defined
     * Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM
     *                  CONFIG_MM_REGIONS == 3
-    *                  CONFIG_STM32_FSMC_SRAM defined
+    *                  CONFIG_STM32_EXTERNAL_RAM defined
     *                  CONFIG_STM32_CCMEXCLUDE NOT defined
     *
     * Let's make sure that all definitions are consistent before doing
     * anything else
     */
 
-#  if defined(CONFIG_STM32_FSMC_SRAM)
+#  if defined(CONFIG_STM32_EXTERNAL_RAM)
 
    /* Configuration 3 or 4. External SRAM is available.  CONFIG_MM_REGIONS
     * should be at least 2.
@@ -419,7 +418,7 @@
        /* Only one memory region.  Force Configuration 1 */
 
 #      warning "FSMC SRAM (and CCM SRAM) excluded from the heap"
-#      undef CONFIG_STM32_FSMC_SRAM
+#      undef CONFIG_STM32_EXTERNAL_RAM
 #      undef CONFIG_STM32_CCMEXCLUDE
 #      define CONFIG_STM32_CCMEXCLUDE 1
 
@@ -497,10 +496,10 @@
  * configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE).
  */
 
-#ifdef CONFIG_STM32_FSMC_SRAM
+#ifdef CONFIG_STM32_EXTERNAL_RAM
 #  if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE)
 #    error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided"
-#    undef CONFIG_STM32_FSMC_SRAM
+#    undef CONFIG_STM32_EXTERNAL_RAM
 #  endif
 #endif
 
@@ -688,7 +687,7 @@ void up_addregion(void)
   kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START);
 #endif
 
-#ifdef CONFIG_STM32_FSMC_SRAM
+#ifdef CONFIG_STM32_EXTERNAL_RAM
 #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
 
   /* Allow user-mode access to the FSMC SRAM user heap memory */
diff --git a/arch/arm/src/stm32/stm32_bbsram.c b/arch/arm/src/stm32/stm32_bbsram.c
index 5cc175a9baa..3bd1626efbd 100644
--- a/arch/arm/src/stm32/stm32_bbsram.c
+++ b/arch/arm/src/stm32/stm32_bbsram.c
@@ -131,10 +131,8 @@ static ssize_t stm32_bbsram_write(FAR struct file *filep,
                  FAR const char *buffer, size_t len);
 static int stm32_bbsram_ioctl(FAR struct file *filep, int cmd,
                  unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int     stm32_bbsram_poll(FAR struct file *filep, FAR struct pollfd *fds,
                  bool setup);
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
 static int     stm32_bbsram_unlink(FAR struct inode *inode);
 #endif
@@ -155,9 +153,7 @@ static const struct file_operations stm32_bbsram_fops =
   .write  = stm32_bbsram_write,
   .seek   = stm32_bbsram_seek,
   .ioctl  = stm32_bbsram_ioctl,
-#ifndef CONFIG_DISABLE_POLL
   .poll   = stm32_bbsram_poll,
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   .unlink = stm32_bbsram_unlink,
 #endif
@@ -545,7 +541,6 @@ static ssize_t stm32_bbsram_write(FAR struct file *filep, FAR const char *buffer
  * Name: stm32_bbsram_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int stm32_bbsram_poll(FAR struct file *filep, FAR struct pollfd *fds,
                              bool setup)
 {
@@ -560,7 +555,6 @@ static int stm32_bbsram_poll(FAR struct file *filep, FAR struct pollfd *fds,
 
   return OK;
 }
-#endif
 
 /****************************************************************************
  * Name: stm32_bbsram_ioctl
diff --git a/arch/arm/src/stm32/stm32_bkp.h b/arch/arm/src/stm32/stm32_bkp.h
index 4478ffd6335..964822a803e 100644
--- a/arch/arm/src/stm32/stm32_bkp.h
+++ b/arch/arm/src/stm32/stm32_bkp.h
@@ -50,9 +50,9 @@
 
 #include "chip.h"
 #ifdef CONFIG_STM32_STM32F10XX
-#  include "chip/stm32_bkp.h"
+#  include "hardware/stm32_bkp.h"
 #else
-#  include "chip/stm32_rtcc.h"
+#  include "hardware/stm32_rtcc.h"
 #endif
 
 /************************************************************************************
diff --git a/arch/arm/src/stm32/stm32_can.h b/arch/arm/src/stm32/stm32_can.h
index 193158462f3..27160f55a58 100644
--- a/arch/arm/src/stm32/stm32_can.h
+++ b/arch/arm/src/stm32/stm32_can.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_can.h"
+#include "hardware/stm32_can.h"
 
 #include 
 
diff --git a/arch/arm/src/stm32/stm32_capture.h b/arch/arm/src/stm32/stm32_capture.h
index 8e54fbb6612..225dbf7df14 100644
--- a/arch/arm/src/stm32/stm32_capture.h
+++ b/arch/arm/src/stm32/stm32_capture.h
@@ -44,7 +44,7 @@
 
 #include "chip.h"
 #include 
-#include "chip/stm32_tim.h"
+#include "hardware/stm32_tim.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32/stm32_ccm.c b/arch/arm/src/stm32/stm32_ccm.c
index cdf7fb8805b..95d5b3a7c30 100644
--- a/arch/arm/src/stm32/stm32_ccm.c
+++ b/arch/arm/src/stm32/stm32_ccm.c
@@ -44,14 +44,6 @@
 
 #ifdef HAVE_CCM_HEAP
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
 /****************************************************************************
  * Public Data
  ****************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_ccm.h b/arch/arm/src/stm32/stm32_ccm.h
index 2f73021cd4c..e5ad55888ea 100644
--- a/arch/arm/src/stm32/stm32_ccm.h
+++ b/arch/arm/src/stm32/stm32_ccm.h
@@ -48,7 +48,9 @@
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
+
 /* Configuration ************************************************************/
+
 /* Assume that we can support the CCM heap */
 
 #define HAVE_CCM_HEAP 1
diff --git a/arch/arm/src/stm32/stm32_comp.h b/arch/arm/src/stm32/stm32_comp.h
index ab28cac186a..17a8e3fcd28 100644
--- a/arch/arm/src/stm32/stm32_comp.h
+++ b/arch/arm/src/stm32/stm32_comp.h
@@ -49,7 +49,7 @@
 #if defined(CONFIG_STM32_STM32F30XX)
 #  error "COMP support for STM32F30XX not implemented yet"
 #elif defined(CONFIG_STM32_STM32F33XX)
-#  include "chip/stm32f33xxx_comp.h"
+#  include "hardware/stm32f33xxx_comp.h"
 #elif defined(CONFIG_STM32_STM32F37XX)
 #  error "COMP support for STM32F37XX ot implemented yet"
 #endif
diff --git a/arch/arm/src/stm32/stm32_dac.h b/arch/arm/src/stm32/stm32_dac.h
index 81c5aa73c3e..0144703de46 100644
--- a/arch/arm/src/stm32/stm32_dac.h
+++ b/arch/arm/src/stm32/stm32_dac.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_dac.h"
+#include "hardware/stm32_dac.h"
 
 #include 
 
diff --git a/arch/arm/src/stm32/stm32_dbgmcu.h b/arch/arm/src/stm32/stm32_dbgmcu.h
index 5fb19218665..d9e1886bb7d 100644
--- a/arch/arm/src/stm32/stm32_dbgmcu.h
+++ b/arch/arm/src/stm32/stm32_dbgmcu.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_dbgmcu.h"
+#include "hardware/stm32_dbgmcu.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32/stm32_dma.h b/arch/arm/src/stm32/stm32_dma.h
index 5d0aae27e21..0817eedd9e9 100644
--- a/arch/arm/src/stm32/stm32_dma.h
+++ b/arch/arm/src/stm32/stm32_dma.h
@@ -45,7 +45,7 @@
 
 #include "chip.h"
 
-#include "chip/stm32_dma.h"
+#include "hardware/stm32_dma.h"
 
 /* These definitions provide the bit encoding of the 'status' parameter passed to the
  * DMA callback function (see dma_callback_t).
diff --git a/arch/arm/src/stm32/stm32_dma2d.c b/arch/arm/src/stm32/stm32_dma2d.c
index 37d6a259560..67c86deb2aa 100644
--- a/arch/arm/src/stm32/stm32_dma2d.c
+++ b/arch/arm/src/stm32/stm32_dma2d.c
@@ -58,9 +58,9 @@
 #include "up_arch.h"
 #include "up_internal.h"
 #include "stm32.h"
-#include "chip/stm32_ltdc.h"
-#include "chip/stm32_dma2d.h"
-#include "chip/stm32_ccm.h"
+#include "hardware/stm32_ltdc.h"
+#include "hardware/stm32_dma2d.h"
+#include "stm32_ccm.h"
 #include "stm32_dma2d.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c
index 406fdfc963c..974ebcf11ba 100644
--- a/arch/arm/src/stm32/stm32_eth.c
+++ b/arch/arm/src/stm32/stm32_eth.c
@@ -206,7 +206,7 @@
 #    error missing logic
 #  elif defined( CONFIG_ETH0_PHY_KSZ8081)
 #    define MII_INT_REG    MII_KSZ8081_INT
-#    define MII_INT_SETEN  MII_KSZ80x1_INT_LDEN | MII_KSZ80x1_INT_LUEN
+#    define MII_INT_SETEN  MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN
 #    define MII_INT_CLREN  0
 #  elif defined( CONFIG_ETH0_PHY_KSZ90x1)
 #    error missing logic
diff --git a/arch/arm/src/stm32/stm32_eth.h b/arch/arm/src/stm32/stm32_eth.h
index 62bc83cbf95..5892e8fc54e 100644
--- a/arch/arm/src/stm32/stm32_eth.h
+++ b/arch/arm/src/stm32/stm32_eth.h
@@ -46,7 +46,7 @@
 
 #if STM32_NETHERNET > 0
 
-#include "chip/stm32_eth.h"
+#include "hardware/stm32_eth.h"
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/src/stm32/stm32_exti.h b/arch/arm/src/stm32/stm32_exti.h
index 4c2bc6264c4..12d469d9cf9 100644
--- a/arch/arm/src/stm32/stm32_exti.h
+++ b/arch/arm/src/stm32/stm32_exti.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_exti.h"
+#include "hardware/stm32_exti.h"
 
 /************************************************************************************
  * Public Data
diff --git a/arch/arm/src/stm32/stm32_flash.h b/arch/arm/src/stm32/stm32_flash.h
index 4d5003b0567..001f52f6993 100644
--- a/arch/arm/src/stm32/stm32_flash.h
+++ b/arch/arm/src/stm32/stm32_flash.h
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_flash.h"
+#include "hardware/stm32_flash.h"
 
 /************************************************************************************
  * Public Function Prototypes
diff --git a/arch/arm/src/stm32/stm32_fmc.c b/arch/arm/src/stm32/stm32_fmc.c
new file mode 100644
index 00000000000..9180bf7ef24
--- /dev/null
+++ b/arch/arm/src/stm32/stm32_fmc.c
@@ -0,0 +1,219 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_fmc.c
+ *
+ *   Copyright (C) 20019 Gregory Nutt. All rights reserved.
+ *   Author: Jason T. Harris 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include "stm32.h"
+
+#if defined(CONFIG_STM32_FMC)
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_fmc_sdram_wait
+ *
+ * Description:
+ *   Wait for the SDRAM controller to be ready.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_sdram_wait(void)
+{
+  int timeout = 0xffff;
+  while (timeout > 0)
+    {
+      if ((getreg32(STM32_FMC_SDSR) & FMC_SDSR_BUSY) == 0)
+        {
+          break;
+        }
+      timeout--;
+    }
+
+  DEBUGASSERT(timeout > 0);
+}
+
+/****************************************************************************
+ * Name: stm32_fmc_enable
+ *
+ * Description:
+ *   Enable clocking to the FMC.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_enable(void)
+{
+  modifyreg32(STM32_RCC_AHB3ENR, 0, RCC_AHB3ENR_FMCEN);
+}
+
+/****************************************************************************
+ * Name: stm32_fmc_disable
+ *
+ * Description:
+ *   Disable clocking to the FMC.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_disable(void)
+{
+  modifyreg32(STM32_RCC_AHB3ENR, RCC_AHB3ENR_FMCEN, 0);
+}
+
+/****************************************************************************
+ * Name: stm32_fmc_sdram_write_protect
+ *
+ * Description:
+ *   Enable/Disable writes to an SDRAM.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_sdram_write_protect(int bank, bool state)
+{
+  uint32_t val, sdcr;
+
+  DEBUGASSERT(bank == 1 || bank == 2);
+  sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
+
+  stm32_fmc_sdram_wait();
+
+  val = getreg32(sdcr);
+  if (state)
+    {
+      val |= FMC_SDCR_WP;       /* wp == 1 */
+    }
+  else
+    {
+      val &= ~FMC_SDCR_WP;      /* wp == 0 */
+    }
+
+  putreg32(val, sdcr);
+}
+
+/****************************************************************************
+ * Name: stm32_fmc_sdram_set_refresh_rate
+ *
+ * Description:
+ *   Set the SDRAM refresh rate.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_sdram_set_refresh_rate(int count)
+{
+  uint32_t val;
+
+  DEBUGASSERT(count <= 0x1fff && count >= 0x29);
+
+  stm32_fmc_sdram_wait();
+
+  val  = getreg32(STM32_FMC_SDRTR);
+  val &= ~(0x1fff << 1);        /* preserve non-count bits */
+  val |= (count << 1);
+  putreg32(val, STM32_FMC_SDRTR);
+}
+
+/****************************************************************************
+ * Name: stm32_fmc_sdram_set_timing
+ *
+ * Description:
+ *   Set the SDRAM timing parameters.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
+{
+  uint32_t val, sdtr;
+
+  DEBUGASSERT((bank == 1) || (bank == 2));
+  DEBUGASSERT((timing & FMC_SDTR_RESERVED) == 0);
+
+  sdtr = (bank == 1) ? STM32_FMC_SDTR1 : STM32_FMC_SDTR2;
+  val  = getreg32(sdtr);
+  val &= FMC_SDTR_RESERVED;     /* preserve reserved bits */
+  val |= timing;
+  putreg32(val, sdtr);
+}
+
+/****************************************************************************
+ * Name: stm32_fmc_sdram_set_control
+ *
+ * Description:
+ *   Set the SDRAM control parameters.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl)
+{
+  uint32_t val, sdcr;
+
+  DEBUGASSERT((bank == 1) || (bank == 2));
+  DEBUGASSERT((ctrl & FMC_SDCR_RESERVED) == 0);
+
+  sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
+  val  = getreg32(sdcr);
+  val &= FMC_SDCR_RESERVED;     /* preserve reserved bits */
+  val |= ctrl;
+  putreg32(val, sdcr);
+}
+
+/****************************************************************************
+ * Name: stm32_fmc_sdram_command
+ *
+ * Description:
+ *   Send a command to the SDRAM.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_sdram_command(uint32_t cmd)
+{
+  uint32_t val;
+
+  DEBUGASSERT((cmd & FMC_SDCMR_RESERVED) == 0);
+
+  /* Wait for the controller to be ready */
+
+  stm32_fmc_sdram_wait();
+
+  val  = getreg32(STM32_FMC_SDCMR);
+  val &= FMC_SDCMR_RESERVED;    /* Preserve reserved bits */
+  val |= cmd;
+  putreg32(val, STM32_FMC_SDCMR);
+}
+
+#endif /* CONFIG_STM32_FMC */
diff --git a/arch/arm/src/stm32/stm32_fmc.h b/arch/arm/src/stm32/stm32_fmc.h
new file mode 100644
index 00000000000..1884500a2ae
--- /dev/null
+++ b/arch/arm/src/stm32/stm32_fmc.h
@@ -0,0 +1,149 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_fmc.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Jason T. Harris 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_STC_STM32_STM32_FMC_H
+#define __ARCH_ARM_STC_STM32_STM32_FMC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include "chip.h"
+#include "hardware/stm32_fmc.h"
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: stm32_fmc_sdram_wait
+ *
+ * Description:
+ *   Wait for the SDRAM controller to be ready.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_sdram_wait(void);
+
+/****************************************************************************
+ * Name: stm32_fmc_enable
+ *
+ * Description:
+ *   Enable clocking to the FMC.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_enable(void);
+
+/****************************************************************************
+ * Name: stm32_fmc_disable
+ *
+ * Description:
+ *   Disable clocking to the FMC.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_disable(void);
+
+/****************************************************************************
+ * Name: stm32_fmc_sdram_write_protect
+ *
+ * Description:
+ *   Enable/Disable writes to an SDRAM.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_sdram_write_protect(int bank, bool state);
+
+/****************************************************************************
+ * Name: stm32_fmc_sdram_set_refresh_rate
+ *
+ * Description:
+ *   Set the SDRAM refresh rate.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_sdram_set_refresh_rate(int count);
+
+/****************************************************************************
+ * Name: stm32_fmc_sdram_set_timing
+ *
+ * Description:
+ *   Set the SDRAM timing parameters.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_sdram_set_timing(int bank, uint32_t timing);
+
+/****************************************************************************
+ * Name: stm32_fmc_sdram_set_control
+ *
+ * Description:
+ *   Set the SDRAM control parameters.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl);
+
+/****************************************************************************
+ * Name: stm32_fmc_sdram_command
+ *
+ * Description:
+ *   Send a command to the SDRAM.
+ *
+ ****************************************************************************/
+
+void stm32_fmc_sdram_command(uint32_t cmd);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_STC_STM32_STM32_FMC_H */
diff --git a/arch/arm/src/stm32/stm32_fsmc.c b/arch/arm/src/stm32/stm32_fsmc.c
new file mode 100644
index 00000000000..a7f57c142da
--- /dev/null
+++ b/arch/arm/src/stm32/stm32_fsmc.c
@@ -0,0 +1,98 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_fsmc.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Jason T. Harris 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include "stm32.h"
+
+#if defined(CONFIG_STM32_FSMC)
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_fsmc_enable
+ *
+ * Description:
+ *   Enable clocking to the FSMC.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX)
+
+void stm32_fsmc_enable(void)
+{
+  modifyreg32(STM32_RCC_AHBENR, 0, RCC_AHBENR_FSMCEN);
+}
+
+#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
+
+void stm32_fsmc_enable(void)
+{
+  modifyreg32(STM32_RCC_AHB3ENR, 0, RCC_AHB3ENR_FSMCEN);
+}
+
+#endif
+
+/****************************************************************************
+ * Name: stm32_fsmc_disable
+ *
+ * Description:
+ *   Disable clocking to the FSMC.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX)
+
+void stm32_fsmc_disable(void)
+{
+  modifyreg32(STM32_RCC_AHBENR, RCC_AHBENR_FSMCEN, 0);
+}
+
+#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
+
+void stm32_fsmc_disable(void)
+{
+  modifyreg32(STM32_RCC_AHB3ENR, RCC_AHB3ENR_FSMCEN, 0);
+}
+
+#endif
+
+#endif /* CONFIG_STM32_FSMC */
diff --git a/arch/arm/src/stm32/stm32_fsmc.h b/arch/arm/src/stm32/stm32_fsmc.h
index 330f47d062e..441f32675cb 100644
--- a/arch/arm/src/stm32/stm32_fsmc.h
+++ b/arch/arm/src/stm32/stm32_fsmc.h
@@ -1,8 +1,8 @@
 /************************************************************************************
  * arch/arm/src/stm32/stm32_fsmc.h
  *
- *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt 
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Jason T. Harris 
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -43,355 +43,47 @@
 #include 
 
 #include "chip.h"
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Register Offsets *****************************************************************/
-
-#define STM32_FSMC_BCR_OFFSET(n)  (8*((n)-1))
-#define STM32_FSMC_BCR1_OFFSET    0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */
-#define STM32_FSMC_BCR2_OFFSET    0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */
-#define STM32_FSMC_BCR3_OFFSET    0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */
-#define STM32_FSMC_BCR4_OFFSET    0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */
-
-#define STM32_FSMC_BTR_OFFSET(n)  (8*((n)-1)+0x0004)
-#define STM32_FSMC_BTR1_OFFSET    0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */
-#define STM32_FSMC_BTR2_OFFSET    0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */
-#define STM32_FSMC_BTR3_OFFSET    0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */
-#define STM32_FSMC_BTR4_OFFSET    0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */
-
-#define STM32_FSMC_BWTR_OFFSET(n) (8*((n)-1)+0x0104)
-#define STM32_FSMC_BWTR1_OFFSET   0x0104 /* SRAM/NOR-Flash write timing registers 1 */
-#define STM32_FSMC_BWTR2_OFFSET   0x010c /* SRAM/NOR-Flash write timing registers 2 */
-#define STM32_FSMC_BWTR3_OFFSET   0x0114 /* SRAM/NOR-Flash write timing registers 3 */
-#define STM32_FSMC_BWTR4_OFFSET   0x011c /* SRAM/NOR-Flash write timing registers 4 */
-
-#define STM32_FSMC_PCR_OFFSET(n)  (0x0020*((n)-1)+0x0040)
-#define STM32_FSMC_PCR2_OFFSET    0x0060 /* NAND Flash/PC Card controller register 2 */
-#define STM32_FSMC_PCR3_OFFSET    0x0080 /* NAND Flash/PC Card controller register 3 */
-#define STM32_FSMC_PCR4_OFFSET    0x00a0 /* NAND Flash/PC Card controller register 4 */
-
-#define STM32_FSMC_SR_OFFSET(n)   (0x0020*((n)-1)+0x0044)
-#define STM32_FSMC_SR2_OFFSET     0x0064 /* NAND Flash/PC Card controller register 2 */
-#define STM32_FSMC_SR3_OFFSET     0x0084 /* NAND Flash/PC Card controller register 3 */
-#define STM32_FSMC_SR4_OFFSET     0x00a4 /* NAND Flash/PC Card controller register 4 */
-
-#define STM32_FSMC_PMEM_OFFSET(n) (0x0020*((n)-1)+0x0048)
-#define STM32_FSMC_PMEM2_OFFSET   0x0068 /* Common memory space timing register 2 */
-#define STM32_FSMC_PMEM3_OFFSET   0x0088 /* Common memory space timing register 3 */
-#define STM32_FSMC_PMEM4_OFFSET   0x00a8 /* Common memory space timing register 4 */
-
-#define STM32_FSMC_PATT_OFFSET(n) (0x0020*((n)-1)+0x004c)
-#define STM32_FSMC_PATT2_OFFSET   0x006c /* Attribute memory space timing register 2 */
-#define STM32_FSMC_PATT3_OFFSET   0x008c /* Attribute memory space timing register 3 */
-#define STM32_FSMC_PATT4_OFFSET   0x00ac /* Attribute memory space timing register 4 */
-
-#define STM32_PIO4_OFFSET         0x00b0  /* I/O space timing register 4 */
-
-#define STM32_FSMC_ECCR_OFFSET(n) (0x0020*((n)-1)+0x003c)
-#define STM32_FSMC_ECCR2_OFFSET   0x0054 /* ECC result register 2 */
-#define STM32_FSMC_ECCR3_OFFSET   0x0074 /* ECC result register 3 */
-
-#if defined(CONFIG_STM32_STM32F429)
-#  define STM32_FSMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 0 */
-#  define STM32_FSMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 1 */
-
-#  define STM32_FSMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register?, Bank 0 */
-#  define STM32_FSMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register?, Bank 1 */
-
-#  define STM32_FSMC_SDCMR_OFFSET 0x0150 /* SDRAM Config register? */
-#  define STM32_FSMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe? */
-#  define STM32_FSMC_SDSR_OFFSET  0x0158 /* SDRAM Status Register */
-#endif
-
-/* Register Addresses ***************************************************************/
-
-#define STM32_FSMC_BCR(n)         (STM32_FSMC_BASE+STM32_FSMC_BCR_OFFSET(n))
-#define STM32_FSMC_BCR1           (STM32_FSMC_BASE+STM32_FSMC_BCR1_OFFSET )
-#define STM32_FSMC_BCR2           (STM32_FSMC_BASE+STM32_FSMC_BCR2_OFFSET )
-#define STM32_FSMC_BCR3           (STM32_FSMC_BASE+STM32_FSMC_BCR3_OFFSET )
-#define STM32_FSMC_BCR4           (STM32_FSMC_BASE+STM32_FSMC_BCR4_OFFSET )
-
-#define STM32_FSMC_BTR(n)         (STM32_FSMC_BASE+STM32_FSMC_BTR_OFFSET(n))
-#define STM32_FSMC_BTR1           (STM32_FSMC_BASE+STM32_FSMC_BTR1_OFFSET )
-#define STM32_FSMC_BTR2           (STM32_FSMC_BASE+STM32_FSMC_BTR2_OFFSET )
-#define STM32_FSMC_BTR3           (STM32_FSMC_BASE+STM32_FSMC_BTR3_OFFSET )
-#define STM32_FSMC_BTR4           (STM32_FSMC_BASE+STM32_FSMC_BTR4_OFFSET )
-
-#define STM32_FSMC_BWTR(n)        (STM32_FSMC_BASE+STM32_FSMC_BWTR_OFFSET(n))
-#define STM32_FSMC_BWTR1          (STM32_FSMC_BASE+STM32_FSMC_BWTR1_OFFSET )
-#define STM32_FSMC_BWTR2          (STM32_FSMC_BASE+STM32_FSMC_BWTR2_OFFSET )
-#define STM32_FSMC_BWTR3          (STM32_FSMC_BASE+STM32_FSMC_BWTR3_OFFSET )
-#define STM32_FSMC_BWTR4          (STM32_FSMC_BASE+STM32_FSMC_BWTR4_OFFSET )
-
-#define STM32_FSMC_PCR(n)         (STM32_FSMC_BASE+STM32_FSMC_PCR_OFFSET(n))
-#define STM32_FSMC_PCR2           (STM32_FSMC_BASE+STM32_FSMC_PCR2_OFFSET )
-#define STM32_FSMC_PCR3           (STM32_FSMC_BASE+STM32_FSMC_PCR3_OFFSET )
-#define STM32_FSMC_PCR4           (STM32_FSMC_BASE+STM32_FSMC_PCR4_OFFSET )
-
-#define STM32_FSMC_SR(n)          (STM32_FSMC_BASE+STM32_FSMC_SR_OFFSET(n))
-#define STM32_FSMC_SR2            (STM32_FSMC_BASE+STM32_FSMC_SR2_OFFSET )
-#define STM32_FSMC_SR3            (STM32_FSMC_BASE+STM32_FSMC_SR3_OFFSET )
-#define STM32_FSMC_SR4            (STM32_FSMC_BASE+STM32_FSMC_SR4_OFFSET )
-
-#define STM32_FSMC_PMEM(n)        (STM32_FSMC_BASE+STM32_FSMC_PMEM_OFFSET(n))
-#define STM32_FSMC_PMEM2          (STM32_FSMC_BASE+STM32_FSMC_PMEM2_OFFSET )
-#define STM32_FSMC_PMEM3          (STM32_FSMC_BASE+STM32_FSMC_PMEM3_OFFSET )
-#define STM32_FSMC_PMEM4          (STM32_FSMC_BASE+STM32_FSMC_PMEM4_OFFSET )
-
-#define STM32_FSMC_PATT(n)        (STM32_FSMC_BASE+STM32_FSMC_PATT_OFFSET(n))
-#define STM32_FSMC_PATT2          (STM32_FSMC_BASE+STM32_FSMC_PATT2_OFFSET )
-#define STM32_FSMC_PATT3          (STM32_FSMC_BASE+STM32_FSMC_PATT3_OFFSET )
-#define STM32_FSMC_PATT4          (STM32_FSMC_BASE+STM32_FSMC_PATT4_OFFSET )
-
-#define STM32_PIO4                (STM32_FSMC_BASE+STM32_FSMC_PIO4_OFFSET )
-
-#define STM32_FSMC_ECCR(n)        (STM32_FSMC_BASE+STM32_FSMC_ECCR_OFFSET(n))
-#define STM32_FSMC_ECCR2          (STM32_FSMC_BASE+STM32_FSMC_ECCR2_OFFSET )
-#define STM32_FSMC_ECCR3          (STM32_FSMC_BASE+STM32_FSMC_ECCR3_OFFSET )
-
-#if defined(CONFIG_STM32_STM32F429)
-#  define STM32_FSMC_SDCR1        (STM32_FSMC_BASE+STM32_FSMC_SDCR1_OFFSET)
-#  define STM32_FSMC_SDCR2        (STM32_FSMC_BASE+STM32_FSMC_SDCR2_OFFSET)
-
-#  define STM32_FSMC_SDTR1        (STM32_FSMC_BASE+STM32_FSMC_SDTR1_OFFSET)
-#  define STM32_FSMC_SDTR2        (STM32_FSMC_BASE+STM32_FSMC_SDTR2_OFFSET)
-
-#  define STM32_FSMC_SDCMR        (STM32_FSMC_BASE+STM32_FSMC_SDCMR_OFFSET)
-#  define STM32_FSMC_SDRTR        (STM32_FSMC_BASE+STM32_FSMC_SDRTR_OFFSET)
-#  define STM32_FSMC_SDSR         (STM32_FSMC_BASE+STM32_FSMC_SDSR_OFFSET)
-#endif
-
-/* Register Bitfield Definitions ****************************************************/
-
-#define FSMC_BCR_MBKEN            (1 << 0)   /* Memory bank enable bit */
-#define FSMC_BCR_MUXEN            (1 << 1)   /* Address/data multiplexing enable bit */
-#define FSMC_BCR_MTYP_SHIFT       (2)        /* Memory type */
-#define FSMC_BCR_MTYP_MASK        (3 << FSMC_BCR_MTYP_SHIFT)
-#  define FSMC_BCR_SRAM           (0 << FSMC_BCR_MTYP_SHIFT)
-#  define FSMC_BCR_ROM            (0 << FSMC_BCR_MTYP_SHIFT)
-#  define FSMC_BCR_PSRAM          (1 << FSMC_BCR_MTYP_SHIFT)
-#  define FSMC_BCR_CRAM           (1 << FSMC_BCR_MTYP_SHIFT)
-#  define FSMC_BCR_NOR            (2 << FSMC_BCR_MTYP_SHIFT)
-#define FSMC_BCR_MWID_SHIFT       (4)        /* Memory data bus width */
-#define FSMC_BCR_MWID_MASK        (3 <<  FSMC_BCR_MWID_SHIFT)
-#  define FSMC_BCR_MWID8          (0 << FSMC_BCR_MWID_SHIFT)
-#  define FSMC_BCR_MWID16         (1 << FSMC_BCR_MWID_SHIFT)
-#define FSMC_BCR_FACCEN           (1 << 6)   /* Flash access enable */
-#define FSMC_BCR_BURSTEN          (1 << 8)   /* Burst enable bit */
-#define FSMC_BCR_WAITPOL          (1 << 9)   /* Wait signal polarity bit */
-#define FSMC_BCR_WRAPMOD          (1 << 10)  /* Wrapped burst mode support */
-#define FSMC_BCR_WAITCFG          (1 << 11)  /* Wait timing configuration */
-#define FSMC_BCR_WREN             (1 << 12)  /* Write enable bit */
-#define FSMC_BCR_WAITEN           (1 << 13)  /* Wait enable bit */
-#define FSMC_BCR_EXTMOD           (1 << 14)  /* Extended mode enable */
-#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
-#  define FSMC_BCR_ASYNCWAIT      (1 << 15)  /* Wait signal during asynchronous transfers */
-#endif
-#define FSMC_BCR_CBURSTRW         (1 << 19)  /* Write burst enable */
-
-#define FSMC_BCR_RSTVALUE         0x000003d2
-
-#define FSMC_BTR_ADDSET_SHIFT     (0)        /* Address setup phase duration */
-#define FSMC_BTR_ADDSET_MASK      (15 << FSMC_BTR_ADDSET_SHIFT)
-#  define FSMC_BTR_ADDSET(n)      ((n-1) << FSMC_BTR_ADDSET_SHIFT)  /* (n)xHCLK n=1..16 */
-#define FSMC_BTR_ADDHLD_SHIFT     (4)        /* Address-hold phase duration */
-#define FSMC_BTR_ADDHLD_MASK      (15 << FSMC_BTR_ADDHLD_SHIFT)
-#  define FSMC_BTR_ADDHLD(n)      ((n-1) << FSMC_BTR_ADDHLD_SHIFT)  /* (n)xHCLK n=2..16*/
-#define FSMC_BTR_DATAST_SHIFT     (8)        /* Data-phase duration */
-#define FSMC_BTR_DATAST_MASK      (255 << FSMC_BTR_DATAST_SHIFT)
-#  define FSMC_BTR_DATAST(n)      ((n-1) << FSMC_BTR_DATAST_SHIFT)  /* (n)xHCLK n=2..256 */
-#define FSMC_BTR_BUSTURN_SHIFT    (16)       /* Bus turnaround phase duration */
-#define FSMC_BTR_BUSTURN_MASK     (15 << FSMC_BTR1_BUSTURN_SHIFT)
-#  define FSMC_BTR_BUSTURN(n)     ((n-1) << FSMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */
-#define FSMC_BTR_CLKDIV_SHIFT     (20)       /* Clock divide ratio */
-#define FSMC_BTR_CLKDIV_MASK      (15 << FSMC_BTR_CLKDIV_SHIFT)
-#  define FSMC_BTR_CLKDIV(n)      ((n-1) << FSMC_BTR_CLKDIV_SHIFT)  /* (n)xHCLK n=2..16 */
-#define FSMC_BTR_DATLAT_SHIFT     (24)      /* Data latency */
-#define FSMC_BTR_DATLAT_MASK      (15 << FSMC_BTR_DATLAT_SHIFT)
-#  define FSMC_BTR_DATLAT(n)      ((n-2) << FSMC_BTR_DATLAT_SHIFT)  /* (n)xHCLK n=2..17 */
-#define FSMC_BTR_ACCMOD_SHIFT     (28)      /* Access mode */
-#define FSMC_BTR_ACCMOD_MASK      (3 << FSMC_BTR_ACCMOD_SHIFT)
-#  define FSMC_BTR_ACCMODA        (0 << FSMC_BTR_ACCMOD_SHIFT)
-#  define FSMC_BTR_ACCMODB        (1 << FSMC_BTR_ACCMOD_SHIFT)
-#  define FSMC_BTR_ACCMODC        (2 << FSMC_BTR_ACCMOD_SHIFT)
-#  define FSMC_BTR_ACCMODD        (3 << FSMC_BTR_ACCMOD_SHIFT)
-
-#define FSMC_BTR_RSTVALUE         0xffffffff
-
-#define FSMC_BWTR_ADDSET_SHIFT    (0)        /* Address setup phase duration */
-#define FSMC_BWTR_ADDSET_MASK     (15 << FSMC_BWTR_ADDSET_SHIFT)
-#  define FSMC_BWTR_ADDSET(n)     ((n-1) << FSMC_BWTR_ADDSET_SHIFT)  /* (n)xHCLK n=1..16 */
-#define FSMC_BWTR_ADDHLD_SHIFT    (4)        /* Address-hold phase duration */
-#define FSMC_BWTR_ADDHLD_MASK     (15 << FSMC_BWTR_ADDHLD_SHIFT)
-#  define FSMC_BWTR_ADDHLD(n)     ((n-1) << FSMC_BWTR_ADDHLD_SHIFT)  /* (n)xHCLK n=2..16*/
-#define FSMC_BWTR_DATAST_SHIFT    (8)        /* Data-phase duration */
-#define FSMC_BWTR_DATAST_MASK     (255 << FSMC_BWTR_DATAST_SHIFT)
-#  define FSMC_BWTR_DATAST(n)     ((n-1) << FSMC_BWTR_DATAST_SHIFT)  /* (n)xHCLK n=2..256 */
-#define FSMC_BWTR_CLKDIV_SHIFT    (20)       /* Clock divide ratio */
-#define FSMC_BWTR_CLKDIV_MASK     (15 << FSMC_BWTR_CLKDIV_SHIFT)
-#  define FSMC_BWTR_CLKDIV(n)     ((n-1) << FSMC_BWTR_CLKDIV_SHIFT)  /* (n)xHCLK n=2..16 */
-#define FSMC_BWTR_DATLAT_SHIFT    (24)      /* Data latency */
-#define FSMC_BWTR_DATLAT_MASK     (15 << FSMC_BWTR_DATLAT_SHIFT)
-#  define FSMC_BWTR_DATLAT(n)     ((n-2) << FSMC_BWTR_DATLAT_SHIFT)  /* (n)xHCLK n=2..17 */
-#define FSMC_BWTR_ACCMOD_SHIFT    (28)      /* Access mode */
-#define FSMC_BWTR_ACCMOD_MASK     (3 << FSMC_BWTR_ACCMOD_SHIFT)
-#  define FSMC_BWTR_ACCMODA       (0 << FSMC_BWTR_ACCMOD_SHIFT)
-#  define FSMC_BWTR_ACCMODB       (1 << FSMC_BWTR_ACCMOD_SHIFT)
-#  define FSMC_BWTR_ACCMODC       (2 << FSMC_BWTR_ACCMOD_SHIFT)
-#  define FSMC_BWTR_ACCMODD       (3 << FSMC_BTR_ACCMOD_SHIFT)
-
-#define FSMC_PCR_PWAITEN          (1 << 1)  /* Wait feature enable bit */
-#define FSMC_PCR_PBKEN            (1 << 2)  /* PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR_PTYP             (1 << 3)  /* Memory type */
-#define FSMC_PCR_PWID_SHIFT       (4)       /* NAND Flash databus width */
-#define FSMC_PCR_PWID_MASK        (3 <<  FSMC_PCR_PWID_SHIFT)
-#  define FSMC_PCR_PWID8          (0 <<  FSMC_PCR_PWID_SHIFT)
-#  define FSMC_PCR_PWID16         (1 <<  FSMC_PCR_PWID_SHIFT)
-#define FSMC_PCR_ECCEN            (1 << 6)  /* ECC computation logic enable bit */
-#define FSMC_PCR_TCLR_SHIFT       (9)       /* CLE to RE delay */
-#define FSMC_PCR_TCLR_MASK        (15 << FSMC_PCR_TCLR_SHIFT)
-#  define FSMC_PCR_TCLR(n)        ((n-1) << FSMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */
-#define FSMC_PCR_TAR_SHIFT        (13)      /* ALE to RE delay */
-#define FSMC_PCR_TAR_MASK         (15 <<  FSMC_PCR_TAR_MASK)
-#  define FSMC_PCR_TAR(n)         ((n-1) << FSMC_PCR_TAR_SHIFT)  /* (n)xHCLK n=1..16 */
-#define FSMC_PCR_ECCPS_SHIFT      (17)      /* ECC page size */
-#define FSMC_PCR_ECCPS_MASK       (7 << FSMC_PCR_ECCPS_SHIFT)
-#  define FSMC_PCR_ECCPS256       (0 << FSMC_PCR_ECCPS_SHIFT) /* 256 bytes */
-#  define FSMC_PCR_ECCPS512       (1 << FSMC_PCR_ECCPS_SHIFT) /* 512 bytes */
-#  define FSMC_PCR_ECCPS1024      (2 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
-#  define FSMC_PCR_ECCPS2048      (3 << FSMC_PCR_ECCPS_SHIFT) /* 2048 bytes */
-#  define FSMC_PCR_ECCPS4096      (4 << FSMC_PCR_ECCPS_SHIFT) /* 8192 bytes */
-#  define FSMC_PCR_ECCPS8192      (5 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
-
-#define FSMC_SR_IRS               (1 << 0)  /* Interrupt Rising Edge status */
-#define FSMC_SR_ILS               (1 << 1)  /* Interrupt Level status */
-#define FSMC_SR_IFS               (1 << 2)  /* Interrupt Falling Edge status */
-#define FSMC_SR_IREN              (1 << 3)  /* Interrupt Rising Edge detection Enable bit */
-#define FSMC_SR_ILEN              (1 << 4)  /* Interrupt Level detection Enable bit */
-#define FSMC_SR_IFEN              (1 << 5)  /* Interrupt Falling Edge detection Enable bit */
-#define FSMC_SR_FEMPT             (1 << 6)  /* FIFO empty */
-
-#define FSMC_PMEM_MEMSET_SHIFT    (0)       /* Common memory setup time */
-#define FSMC_PMEM_MEMSET_MASK     (255 << FSMC_PMEM_MEMSET_SHIFT)
-#  define FSMC_PMEM_MEMSET(n)     ((n-1) << FSMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */
-#define FSMC_PMEM_MEMWAIT_SHIFT   (8)       /* Common memory wait time */
-#define FSMC_PMEM_MEMWAIT_MASK    (255 << FSMC_PMEM_MEMWAIT_SHIFT)
-#  define FSMC_PMEM_MEMWAIT(n)    ((n-1) << FSMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */
-#define FSMC_PMEM_MEMHOLD_SHIFT   (16)      /* Common memoryhold time */
-#define FSMC_PMEM_MEMHOLD_MASK    (255 << FSMC_PMEM_MEMHOLD_SHIFT)
-#  define FSMC_PMEM_MEMHOLD(n)    ((n) <<  FSMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */
-#define FSMC_PMEM_MEMHIZ_SHIFT    (24)       /* Common memory databus HiZ time */
-#define FSMC_PMEM_MEMHIZ_MASK     (255 << FSMC_PMEM_MEMHIZ_SHIFT)
-#  define FSMC_PMEM_MEMHIZ(n)     ((n) << FSMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */
-
-#define FSMC_PATT_ATTSET_SHIFT    (0)       /* Attribute memory setup time */
-#define FSMC_PATT_ATTSET_MASK     (255 << FSMC_PATT_ATTSET_SHIFT)
-#  define FSMC_PATT_ATTSET(n)     ((n-1) << FSMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */
-#define FSMC_PATT_ATTWAIT_SHIFT   (8)       /* Attribute memory wait time */
-#define FSMC_PATT_ATTWAIT_MASK    (255 << FSMC_PATT_ATTWAIT_SHIFT)
-#  define FSMC_PATT_ATTWAIT(n)    ((n-1) << FSMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */
-#define FSMC_PATT_ATTHOLD_SHIFT   (16)      /* Attribute memory hold time */
-#define FSMC_PATT_ATTHOLD_MASK    (255 << FSMC_PATT_ATTHOLD_SHIFT)
-#  define FSMC_PATT_ATTHOLD(n)    ((n) <<  FSMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */
-#define FSMC_PATT_ATTHIZ_SHIFT    (24)       /* Attribute memory databus HiZ time */
-#define FSMC_PATT_ATTHIZ_MASK     (255 << FSMC_PATT_ATTHIZ_SHIFT)
-#  define FSMC_PATT_ATTHIZ(n)     ((n) << FSMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */
-
-#define FSMC_PIO4_IOSET_SHIFT     (0)       /* IOribute memory setup time */
-#define FSMC_PIO4_IOSET_MASK      (255 << FSMC_PIO4_IOSET_SHIFT)
-#  define FSMC_PIO4_IOSET(n)      ((n-1) << FSMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */
-#define FSMC_PIO4_IOWAIT_SHIFT    (8)       /* IOribute memory wait time */
-#define FSMC_PIO4_IOWAIT_MASK     (255 << FSMC_PIO4_IOWAIT_SHIFT)
-#  define FSMC_PIO4_IOWAIT(n)     ((n-1) << FSMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */
-#define FSMC_PIO4_IOHOLD_SHIFT    (16)      /* IOribute memory hold time */
-#define FSMC_PIO4_IOHOLD_MASK     (255 << FSMC_PIO4_IOHOLD_SHIFT)
-#  define FSMC_PIO4_IOHOLD(n)     ((n) <<  FSMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */
-#define FSMC_PIO4_IOHIZ_SHIFT     (24)       /* IOribute memory databus HiZ time */
-#define FSMC_PIO4_IOHIZ_MASK      (255 << FSMC_PIO4_IOHIZ_SHIFT)
-#  define FSMC_PIO4_IOHIZ(n)      ((n) << FSMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */
-
-#if defined(CONFIG_STM32_STM32F429)
-
-#  define FSMC_SDRAM_CR_COLBITS_8                       0x00000000
-#  define FSMC_SDRAM_CR_COLBITS_9                       0x00000001
-#  define FSMC_SDRAM_CR_COLBITS_10                      0x00000002
-#  define FSMC_SDRAM_CR_COLBITS_11                      0x00000003
-
-#  define FSMC_SDRAM_CR_ROWBITS_11                      0x00000000
-#  define FSMC_SDRAM_CR_ROWBITS_12                      0x00000004
-#  define FSMC_SDRAM_CR_ROWBITS_13                      0x00000008
-
-#  define FSMC_SDRAM_CR_WIDTH_8                         0x00000000
-#  define FSMC_SDRAM_CR_WIDTH_16                        0x00000010
-#  define FSMC_SDRAM_CR_WIDTH_32                        0x00000020
-
-#  define FSMC_SDRAM_CR_BANKS_2                         0x00000000
-#  define FSMC_SDRAM_CR_BANKS_4                         0x00000040
-
-#  define FSMC_SDRAM_CR_CASLAT_1                        0x00000080
-#  define FSMC_SDRAM_CR_CASLAT_2                        0x00000100
-#  define FSMC_SDRAM_CR_CASLAT_3                        0x00000180
-
-#  define FSMC_SDRAM_CR_WRITE_PROT                      0x00000200
-
-#  define FSMC_SDRAM_CR_SDCLK_DISABLE                   0x00000000
-#  define FSMC_SDRAM_CR_SDCLK_2X                        0x00000800
-#  define FSMC_SDRAM_CR_SDCLK_3X                        0x00000C00
-
-#  define FSMC_SDRAM_CR_BURST_READ                      0x00001000
-
-#  define FSMC_SDRAM_CR_RPIPE_0                         0x00000000
-#  define FSMC_SDRAM_CR_RPIPE_1                         0x00002000
-#  define FSMC_SDRAM_CR_RPIPE_2                         0x00004000
-
-#  define FSMC_SDRAM_TR_TMRD_SHIFT                      0
-#  define FSMC_SDRAM_TR_TXSR_SHIFT                      4
-#  define FSMC_SDRAM_TR_TRAS_SHIFT                      8
-#  define FSMC_SDRAM_TR_TRC_SHIFT                       12
-#  define FSMC_SDRAM_TR_TWR_SHIFT                       16
-#  define FSMC_SDRAM_TR_TRP_SHIFT                       20
-#  define FSMC_SDRAM_TR_TRCD_SHIFT                      24
-
-#  define FSMC_SDRAM_MODE_CMD_NORMAL                    0
-#  define FSMC_SDRAM_MODE_CMD_CLK_ENABLE                1
-#  define FSMC_SDRAM_MODE_CMD_PALL                      2
-#  define FSMC_SDRAM_MODE_CMD_AUTO_REFRESH              3
-#  define FSMC_SDRAM_MODE_CMD_LOAD_MODE                 4
-#  define FSMC_SDRAM_MODE_CMD_SELF_REFRESH              5
-#  define FSMC_SDRAM_MODE_CMD_POWER_DOWN                6
-
-#  define FSMC_SDRAM_CMD_BANK_1                         0x00000010
-#  define FSMC_SDRAM_CMD_BANK_2                         0x00000008
-
-#  define FSMC_SDRAM_AUTO_REFRESH_SHIFT                 5
-#  define FSMC_SDRAM_MODEREG_SHIFT                      9
-
-#  define FSMC_SDRAM_MODEREG_BURST_LENGTH_1             (0x0000 << FSMC_SDRAM_MODEREG_SHIFT)
-#  define FSMC_SDRAM_MODEREG_BURST_LENGTH_2             (0x0001 << FSMC_SDRAM_MODEREG_SHIFT)
-#  define FSMC_SDRAM_MODEREG_BURST_LENGTH_4             (0x0002 << FSMC_SDRAM_MODEREG_SHIFT)
-#  define FSMC_SDRAM_MODEREG_BURST_LENGTH_8             (0x0004 << FSMC_SDRAM_MODEREG_SHIFT)
-#  define FSMC_SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      (0x0000 << FSMC_SDRAM_MODEREG_SHIFT)
-#  define FSMC_SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     (0x0008 << FSMC_SDRAM_MODEREG_SHIFT)
-#  define FSMC_SDRAM_MODEREG_CAS_LATENCY_2              (0x0020 << FSMC_SDRAM_MODEREG_SHIFT)
-#  define FSMC_SDRAM_MODEREG_CAS_LATENCY_3              (0x0030 << FSMC_SDRAM_MODEREG_SHIFT)
-#  define FSMC_SDRAM_MODEREG_OPERATING_MODE_STANDARD    (0x0000 << FSMC_SDRAM_MODEREG_SHIFT)
-#  define FSMC_SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000 << FSMC_SDRAM_MODEREG_SHIFT)
-#  define FSMC_SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     (0x0200 << FSMC_SDRAM_MODEREG_SHIFT)
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+#include "hardware/stm32_fsmc.h"
 
 /************************************************************************************
  * Public Functions
  ************************************************************************************/
 
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: stm32_fsmc_enable
+ *
+ * Description:
+ *   Enable clocking to the FSMC.
+ *
+ ****************************************************************************/
+
+void stm32_fsmc_enable(void);
+
+/****************************************************************************
+ * Name: stm32_fsmc_disable
+ *
+ * Description:
+ *   Disable clocking to the FSMC.
+ *
+ ****************************************************************************/
+
+void stm32_fsmc_disable(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
 #endif /* __ARCH_ARM_SRC_STM32_STM32_FSMC_H */
diff --git a/arch/arm/src/stm32/stm32_gpio.h b/arch/arm/src/stm32/stm32_gpio.h
index 40b32baf719..8b65c1bd3f0 100644
--- a/arch/arm/src/stm32/stm32_gpio.h
+++ b/arch/arm/src/stm32/stm32_gpio.h
@@ -54,16 +54,16 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32_STM32L15XX)
-#  include "chip/stm32l15xxx_gpio.h"
+#  include "hardware/stm32l15xxx_gpio.h"
 #elif defined(CONFIG_STM32_STM32F10XX)
-#  include "chip/stm32f10xxx_gpio.h"
+#  include "hardware/stm32f10xxx_gpio.h"
 #elif defined(CONFIG_STM32_STM32F20XX)
-#  include "chip/stm32f20xxx_gpio.h"
+#  include "hardware/stm32f20xxx_gpio.h"
 #elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
       defined(CONFIG_STM32_STM32F37XX)
-#  include "chip/stm32f30xxx_gpio.h"
+#  include "hardware/stm32f30xxx_gpio.h"
 #elif defined(CONFIG_STM32_STM32F4XXX)
-#  include "chip/stm32f40xxx_gpio.h"
+#  include "hardware/stm32f40xxx_gpio.h"
 #else
 #  error "Unrecognized STM32 chip"
 #endif
diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/stm32/stm32_hrtim.c
index af1d4c3e3f6..762845344df 100644
--- a/arch/arm/src/stm32/stm32_hrtim.c
+++ b/arch/arm/src/stm32/stm32_hrtim.c
@@ -797,10 +797,8 @@ static const struct file_operations hrtim_fops =
   NULL,               /* read */
   NULL,               /* write */
   NULL,               /* seek */
-  stm32_hrtim_ioctl   /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL              /* poll */
-#endif
+  stm32_hrtim_ioctl,  /* ioctl */
+  NULL                /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL              /* unlink */
 #endif
diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/stm32/stm32_hrtim.h
index e44ca389750..d04df7728e0 100644
--- a/arch/arm/src/stm32/stm32_hrtim.h
+++ b/arch/arm/src/stm32/stm32_hrtim.h
@@ -49,8 +49,8 @@
 #ifdef CONFIG_STM32_HRTIM1
 
 #if defined(CONFIG_STM32_STM32F33XX)
-#  include "chip/stm32f33xxx_hrtim.h"
-#  include "chip/stm32f33xxx_rcc.h"
+#  include "hardware/stm32f33xxx_hrtim.h"
+#  include "hardware/stm32f33xxx_rcc.h"
 #else
 #  error
 #endif
diff --git a/arch/arm/src/stm32/stm32_i2c.h b/arch/arm/src/stm32/stm32_i2c.h
index c61f17332bd..d1004298e18 100644
--- a/arch/arm/src/stm32/stm32_i2c.h
+++ b/arch/arm/src/stm32/stm32_i2c.h
@@ -44,12 +44,7 @@
 #include 
 
 #include "chip.h"
-#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
-    defined(CONFIG_STM32_STM32F33XX)
-#  include "chip/stm32f30xxx_i2c.h"
-#else
-#  include "chip/stm32_i2c.h"
-#endif
+#include "hardware/stm32_i2c.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32/stm32_i2c_v2.c b/arch/arm/src/stm32/stm32_i2c_v2.c
new file mode 100644
index 00000000000..213a8c42d26
--- /dev/null
+++ b/arch/arm/src/stm32/stm32_i2c_v2.c
@@ -0,0 +1,2872 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_i2c.c
+ * STM32 I2C IPv2 Hardware Layer - Device Driver ported from STM32F7
+ *
+ *   Copyright (C) 2011 Uros Platise. All rights reserved.
+ *   Author: Uros Platise 
+ *
+ * With extensions and modifications for the F1, F2, and F4 by:
+ *
+ *   Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *            John Wharington
+ *            David Sidrane 
+ *            Bob Feretich 
+ *
+ * Major rewrite of ISR and supporting methods, including support
+ * for NACK and RELOAD by:
+ *
+ *   Copyright (c) 2016 Doug Vetter.  All rights reserved.
+ *   Author: Doug Vetter 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/* ------------------------------------------------------------------------------
+ *
+ * STM32 I2C IPv2 I2C Driver
+ *
+ * Supports:
+ *  - Master operation:
+ *      Standard-mode (up to 100 kHz)
+ *      Fast-mode (up to 400 kHz)
+ *      Fast-mode Plus (up to 1 MHz)
+ *      fI2CCLK clock source selection is based on STM32_RCC_DCKCFGR2_I2CxSRC
+ *      being set to HSI and the calculations are based on STM32_HSI_FREQUENCY
+ *      of 16mHz
+ *
+ *  - Multiple instances (shared bus)
+ *  - Interrupt based operation
+ *  - RELOAD support
+ *
+ * Unsupported, possible future work:
+ *  - More effective error reporting to higher layers
+ *  - Slave operation
+ *  - Support of fI2CCLK frequencies other than 8Mhz
+ *  - Polled operation (code present but untested)
+ *  - SMBus support
+ *  - Multi-master support
+ *  - IPMI
+ *
+ * Test Environment:
+ *
+ *  - NUCLEO-F303ZE
+ *
+ * Operational Status:
+ *
+ *  All supported features have been tested and found to be operational.
+ *
+ *  Although the RELOAD capability has been tested as it was required to
+ *  implement the I2C_M_NOSTART flag on F3 hardware, the associated
+ *  logic to support the transfer messages with more than 255 byte
+ *  payloads has not been  tested as the author lacked access to a real
+ *  device supporting these types of transfers.
+ *
+ * Performance Benchmarks: TBD
+ *
+ *  Time to transfer two messages, each a byte in length, in addition to the
+ *  START condition, in interrupt mode:
+ *
+ *  DEBUG enabled (development): TBDms
+ *      Excessive delay here is caused by printing to the console and
+ *      is of no concern.
+ *
+ *  DEBUG disabled (production): TBSus
+ *      Between Messages: TBDus
+ *      Between Bytes: TBDus
+ *
+ * Implementation:
+ *
+ *  - Device: structure as defined by the nuttx/i2c/i2c.h
+ *
+ *  - Instance: represents each individual access to the I2C driver, obtained by
+ *      the i2c_init(); it extends the Device structure from the nuttx/i2c/i2c.h;
+ *      Instance points to OPS, to common I2C Hardware private data and contains
+ *      its own private data including frequency, address and mode of operation.
+ *
+ *  - Private: Private data of an I2C Hardware
+ *
+ * High Level Functional Description
+ *
+ * This driver works with I2C "messages" (struct i2c_msg_s), which carry a buffer
+ * intended to transfer data to, or store data read from, the I2C bus.
+ *
+ * As the hardware can only transmit or receive one byte at a time the basic job
+ * of the driver (and the ISR specifically) is to process each message in the
+ * order they are stored in the message list, one byte at a time.  When
+ * no messages are left the ISR exits and returns the result to the caller.
+ *
+ * The order of the list of I2C messages provided to the driver is important and
+ * dependent upon the hardware in use.  A typical I2C transaction between the F3
+ * as an I2C Master and some other IC as a I2C Slave requires two messages that
+ * communicate the:
+ *
+ *    1) Subaddress (register offset on the slave device)
+ *    2) Data sent to or read from the device
+ *
+ * These messages will typically be one byte in length but may be up to 2^31
+ * bytes in length.  Incidentally, the maximum length is limited only because
+ * i2c_msg_s.length is a signed int for some odd reason.
+ *
+ * Interrupt mode relies on the following interrupt events:
+ *
+ *   TXIS  - Transmit interrupt
+ *           (data transmitted to bus and acknowledged)
+ *   NACKF - Not Acknowledge Received
+ *           (data transmitted to bus and NOT acknowledged)
+ *   RXNE  - Receive interrupt
+ *           (data received from bus)
+ *   TC    - Transfer Complete
+ *           (All bytes in message transferred)
+ *   TCR   - Transfer Complete (Reload)
+ *           (Current batch of bytes in message transferred)
+ *
+ * The driver currently supports Single Master mode only.  Slave mode is not
+ * supported.  Additionally, the driver runs in Software End Mode (AUTOEND
+ * disabled) so the driver is responsible for telling the hardware what to
+ * do at the end of a transfer.
+ *
+ * ------------------------------------------------------------------------------
+ *
+ * Configuration:
+ *
+ *  To use this driver, enable the following configuration variable:
+ *
+ *    CONFIG_STM32_I2C1
+ *    CONFIG_STM32_I2C2
+ *    CONFIG_STM32_I2C3
+ *    CONFIG_STM32_I2C4
+ *
+ *  To configure the ISR timeout using fixed values (CONFIG_STM32_I2C_DYNTIMEO=n):
+ *
+ *    CONFIG_STM32_I2CTIMEOSEC   (Timeout in seconds)
+ *    CONFIG_STM32_I2CTIMEOMS    (Timeout in milliseconds)
+ *    CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks)
+ *
+ *  To configure the ISR timeout using dynamic values (CONFIG_STM32_I2C_DYNTIMEO=y):
+ *
+ *    CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE  (Timeout in microseconds per byte)
+ *    CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP    (Timeout for start/stop in milliseconds)
+ *
+ *  Debugging output enabled with:
+ *
+ *    CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_{ERROR|WARN|INFO}
+ *
+ *  ISR Debugging output may be enabled with:
+ *
+ *    CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_INFO
+ *
+ * ------------------------------------------------------------------------------
+ *
+ * References:
+ *
+ *  RM0431:
+ *     ST STM322xxx and STM323xxx Reference Manual
+ *     Document ID: DocID029480 Revision 1, Jan 2017.
+ *
+ *  RM0316:
+ *     ST STM326xxx and STM327xxx Reference Manual
+ *     Document ID: DocID028270 Revision 2, April 2016.
+ *
+ *  DATASHEET:
+ *     ST STM3277xx/STM3278Ax/STM3279x Datasheet
+ *     Document ID: DocID028294, Revision 3, May 2016.
+ *
+ *  ERRATA:
+ *     STM326xxx/STM327xxx Errata sheet Rev A device limitations
+ *     Document ID: DocID028806, Revision 2, April 2016.
+ *
+ *  I2CSPEC:
+ *     I2C Bus Specification and User Manual
+ *     Document ID: UM10204, Revision 6, April 2014.
+ *
+ * ------------------------------------------------------------------------------
+ */
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "up_arch.h"
+
+#include "stm32_rcc.h"
+#include "stm32_i2c.h"
+#include "stm32_gpio.h"
+
+/* At least one I2C peripheral must be enabled */
+
+#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \
+    defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4)
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+#undef INVALID_CLOCK_SOURCE
+
+#warning TODO: check I2C clock source. It must be HSI!
+
+/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used.  Instead,
+ * CPU-intensive polling will be used.
+ */
+
+/* Interrupt wait timeout in seconds and milliseconds */
+
+#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS)
+#  define CONFIG_STM32_I2CTIMEOSEC 0
+#  define CONFIG_STM32_I2CTIMEOMS  500   /* Default is 500 milliseconds */
+#  warning "Using Default 500 Ms Timeout"
+#elif !defined(CONFIG_STM32_I2CTIMEOSEC)
+#  define CONFIG_STM32_I2CTIMEOSEC 0     /* User provided milliseconds */
+#elif !defined(CONFIG_STM32_I2CTIMEOMS)
+#  define CONFIG_STM32_I2CTIMEOMS  0     /* User provided seconds */
+#endif
+
+/* Interrupt wait time timeout in system timer ticks */
+
+#ifndef CONFIG_STM32_I2CTIMEOTICKS
+#  define CONFIG_STM32_I2CTIMEOTICKS \
+    (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS))
+#endif
+
+#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP
+#  define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS)
+#endif
+
+/* Macros to convert a I2C pin to a GPIO output */
+
+#define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\
+                      GPIO_SPEED_50MHz | GPIO_OUTPUT_SET)
+
+#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
+
+#define I2C_CR1_TXRX      (I2C_CR1_RXIE | I2C_CR1_TXIE)
+#define I2C_CR1_ALLINTS   (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE)
+
+/* Unused bit in I2c_ISR used to communicate a bad state has occurred in
+ * the isr processing
+*/
+
+#define I2C_INT_BAD_STATE 0x8000000
+
+/* I2C event tracing
+ *
+ * To enable tracing statements which show the details of the state machine
+ * enable the following configuration variable:
+ *
+ * CONFIG_I2C_TRACE
+ *
+ * Note: This facility uses syslog, which sends output to the console by
+ * default.  No other debug configuration variables are required.
+ */
+
+#ifndef CONFIG_I2C_TRACE
+#  define stm32_i2c_tracereset(p)
+#  define stm32_i2c_tracenew(p,s)
+#  define stm32_i2c_traceevent(p,e,a)
+#  define stm32_i2c_tracedump(p)
+#endif
+
+#ifndef CONFIG_I2C_NTRACE
+#  define CONFIG_I2C_NTRACE 32
+#endif
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+
+/* Interrupt state */
+
+enum stm32_intstate_e
+{
+  INTSTATE_IDLE = 0,      /* No I2C activity */
+  INTSTATE_WAITING,       /* Waiting for completion of interrupt activity */
+  INTSTATE_DONE,          /* Interrupt activity complete */
+};
+
+/* Trace events */
+
+enum stm32_trace_e
+{
+  I2CEVENT_NONE = 0,
+  I2CEVENT_STATE_ERROR,
+  I2CEVENT_ISR_SHUTDOWN,
+  I2CEVENT_ISR_CALL,
+  I2CEVENT_ISR_EMPTY_CALL,
+  I2CEVENT_MSG_HANDLING,
+  I2CEVENT_POLL_NOT_READY,
+  I2CEVENT_EMPTY_MSG,
+  I2CEVENT_START,
+  I2CEVENT_ADDRESS_ACKED,
+  I2CEVENT_ADDRESS_NACKED,
+  I2CEVENT_NACK,
+  I2CEVENT_READ,
+  I2CEVENT_READ_ERROR,
+  I2CEVENT_WRITE_TO_DR,
+  I2CEVENT_WRITE_STOP,
+  I2CEVENT_WRITE_RESTART,
+  I2CEVENT_WRITE_NO_RESTART,
+  I2CEVENT_WRITE_ERROR,
+  I2CEVENT_WRITE_FLAG_ERROR,
+  I2CEVENT_TC_RESTART,
+  I2CEVENT_TC_NO_RESTART
+};
+
+/* Trace data */
+
+struct stm32_trace_s
+{
+  uint32_t status;             /* I2C 32-bit SR2|SR1 status */
+  uint32_t count;              /* Interrupt count when status change */
+  enum stm32_intstate_e event; /* Last event that occurred with this status */
+  uint32_t parm;               /* Parameter associated with the event */
+  clock_t time;                /* First of event or first status */
+};
+
+/* I2C Device hardware configuration */
+
+struct stm32_i2c_config_s
+{
+  uint32_t base;              /* I2C base address */
+  uint32_t clk_bit;           /* Clock enable bit */
+  uint32_t reset_bit;         /* Reset bit */
+  uint32_t scl_pin;           /* GPIO configuration for SCL as SCL */
+  uint32_t sda_pin;           /* GPIO configuration for SDA as SDA */
+#ifndef CONFIG_I2C_POLLED
+  uint32_t ev_irq;            /* Event IRQ */
+  uint32_t er_irq;            /* Error IRQ */
+#endif
+};
+
+/* I2C Device Private Data */
+
+struct stm32_i2c_priv_s
+{
+  const struct stm32_i2c_config_s *config; /* Port configuration */
+  int refs;                    /* Reference count */
+  sem_t sem_excl;              /* Mutual exclusion semaphore */
+#ifndef CONFIG_I2C_POLLED
+  sem_t sem_isr;               /* Interrupt wait semaphore */
+#endif
+  volatile uint8_t intstate;   /* Interrupt handshake (see enum stm32_intstate_e) */
+
+  uint8_t msgc;                /* Message count */
+  struct i2c_msg_s *msgv;      /* Message list */
+  uint8_t *ptr;                /* Current message buffer */
+  uint32_t frequency;          /* Current I2C frequency */
+  int dcnt;                    /* Current message bytes remaining to transfer */
+  uint16_t flags;              /* Current message flags */
+  bool astart;                 /* START sent */
+
+  /* I2C trace support */
+
+#ifdef CONFIG_I2C_TRACE
+  int tndx;                    /* Trace array index */
+  clock_t start_time;          /* Time when the trace was started */
+
+  /* The actual trace data */
+
+  struct stm32_trace_s trace[CONFIG_I2C_NTRACE];
+#endif
+
+  uint32_t status;             /* End of transfer SR2|SR1 status */
+
+#ifdef CONFIG_PM
+  struct pm_callback_s pm_cb;  /* PM callbacks */
+#endif
+};
+
+/* I2C Device, Instance */
+
+struct stm32_i2c_inst_s
+{
+  const struct i2c_ops_s  *ops;  /* Standard I2C operations */
+  struct stm32_i2c_priv_s *priv; /* Common driver private data structure */
+};
+
+/************************************************************************************
+ * Private Function Prototypes
+ ************************************************************************************/
+
+static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv,
+                                        uint8_t offset);
+static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset,
+                                    uint16_t value);
+static inline void stm32_i2c_putreg32(FAR struct stm32_i2c_priv_s *priv, uint8_t offset,
+                                    uint32_t value);
+static inline void stm32_i2c_modifyreg32(FAR struct stm32_i2c_priv_s *priv,
+                                         uint8_t offset, uint32_t clearbits,
+                                         uint32_t setbits);
+static inline void stm32_i2c_sem_wait(FAR struct i2c_master_s *dev);
+#ifdef CONFIG_STM32_I2C_DYNTIMEO
+static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs);
+#endif /* CONFIG_STM32_I2C_DYNTIMEO */
+static inline int  stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv);
+static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv);
+static inline void stm32_i2c_sem_post(FAR struct i2c_master_s *dev);
+static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev);
+static inline void stm32_i2c_sem_destroy(FAR struct i2c_master_s *dev);
+#ifdef CONFIG_I2C_TRACE
+static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv);
+static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t status);
+static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
+                               enum stm32_trace_e event, uint32_t parm);
+static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv);
+#endif /* CONFIG_I2C_TRACE */
+static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv,
+                               uint32_t frequency);
+static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv);
+static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv);
+static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv);
+static int stm32_i2c_isr_process(struct stm32_i2c_priv_s * priv);
+#ifndef CONFIG_I2C_POLLED
+static int stm32_i2c_isr(int irq, void *context, FAR void *arg);
+#endif
+static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv);
+static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv);
+
+static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
+                             int count);
+static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
+                              int count);
+#ifdef CONFIG_I2C_RESET
+static int stm32_i2c_reset(FAR struct i2c_master_s * dev);
+#endif
+#ifdef CONFIG_PM
+static int stm32_i2c_pm_prepare(FAR struct pm_callback_s *cb, int domain,
+                                enum pm_state_e pmstate);
+#endif
+
+/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32_I2C1
+static const struct stm32_i2c_config_s stm32_i2c1_config =
+{
+  .base          = STM32_I2C1_BASE,
+  .clk_bit       = RCC_APB1ENR_I2C1EN,
+  .reset_bit     = RCC_APB1RSTR_I2C1RST,
+  .scl_pin       = GPIO_I2C1_SCL,
+  .sda_pin       = GPIO_I2C1_SDA,
+#ifndef CONFIG_I2C_POLLED
+  .ev_irq        = STM32_IRQ_I2C1EV,
+  .er_irq        = STM32_IRQ_I2C1ER
+#endif
+};
+
+static struct stm32_i2c_priv_s stm32_i2c1_priv =
+{
+  .config        = &stm32_i2c1_config,
+  .refs          = 0,
+  .intstate      = INTSTATE_IDLE,
+  .msgc          = 0,
+  .msgv          = NULL,
+  .ptr           = NULL,
+  .frequency     = 0,
+  .dcnt          = 0,
+  .flags         = 0,
+  .status        = 0,
+#ifdef CONFIG_PM
+  .pm_cb.prepare = stm32_i2c_pm_prepare,
+#endif
+};
+#endif
+
+#ifdef CONFIG_STM32_I2C2
+static const struct stm32_i2c_config_s stm32_i2c2_config =
+{
+  .base          = STM32_I2C2_BASE,
+  .clk_bit       = RCC_APB1ENR_I2C2EN,
+  .reset_bit     = RCC_APB1RSTR_I2C2RST,
+  .scl_pin       = GPIO_I2C2_SCL,
+  .sda_pin       = GPIO_I2C2_SDA,
+#ifndef CONFIG_I2C_POLLED
+  .ev_irq        = STM32_IRQ_I2C2EV,
+  .er_irq        = STM32_IRQ_I2C2ER
+#endif
+};
+
+static struct stm32_i2c_priv_s stm32_i2c2_priv =
+{
+  .config        = &stm32_i2c2_config,
+  .refs          = 0,
+  .intstate      = INTSTATE_IDLE,
+  .msgc          = 0,
+  .msgv          = NULL,
+  .ptr           = NULL,
+  .frequency     = 0,
+  .dcnt          = 0,
+  .flags         = 0,
+  .status        = 0,
+#ifdef CONFIG_PM
+  .pm_cb.prepare = stm32_i2c_pm_prepare,
+#endif
+};
+#endif
+
+#ifdef CONFIG_STM32_I2C3
+static const struct stm32_i2c_config_s stm32_i2c3_config =
+{
+  .base          = STM32_I2C3_BASE,
+  .clk_bit       = RCC_APB1ENR_I2C3EN,
+  .reset_bit     = RCC_APB1RSTR_I2C3RST,
+  .scl_pin       = GPIO_I2C3_SCL,
+  .sda_pin       = GPIO_I2C3_SDA,
+#ifndef CONFIG_I2C_POLLED
+  .ev_irq        = STM32_IRQ_I2C3EV,
+  .er_irq        = STM32_IRQ_I2C3ER
+#endif
+};
+
+static struct stm32_i2c_priv_s stm32_i2c3_priv =
+{
+  .config        = &stm32_i2c3_config,
+  .refs          = 0,
+  .intstate      = INTSTATE_IDLE,
+  .msgc          = 0,
+  .msgv          = NULL,
+  .ptr           = NULL,
+  .frequency     = 0,
+  .dcnt          = 0,
+  .flags         = 0,
+  .status        = 0,
+#ifdef CONFIG_PM
+  .pm_cb.prepare = stm32_i2c_pm_prepare,
+#endif
+};
+#endif
+
+#ifdef CONFIG_STM32_I2C4
+static const struct stm32_i2c_config_s stm32_i2c4_config =
+{
+  .base          = STM32_I2C4_BASE,
+  .clk_bit       = RCC_APB1ENR_I2C4EN,
+  .reset_bit     = RCC_APB1RSTR_I2C4RST,
+  .scl_pin       = GPIO_I2C4_SCL,
+  .sda_pin       = GPIO_I2C4_SDA,
+#ifndef CONFIG_I2C_POLLED
+  .ev_irq        = STM32_IRQ_I2C4EV,
+  .er_irq        = STM32_IRQ_I2C4ER
+#endif
+};
+
+static struct stm32_i2c_priv_s stm32_i2c4_priv =
+{
+  .config        = &stm32_i2c4_config,
+  .refs          = 0,
+  .intstate      = INTSTATE_IDLE,
+  .msgc          = 0,
+  .msgv          = NULL,
+  .ptr           = NULL,
+  .frequency     = 0,
+  .dcnt          = 0,
+  .flags         = 0,
+  .status        = 0,
+#ifdef CONFIG_PM
+  .pm_cb.prepare = stm32_i2c_pm_prepare,
+#endif
+};
+#endif
+
+/* Device Structures, Instantiation */
+
+static const struct i2c_ops_s stm32_i2c_ops =
+{
+  .transfer      = stm32_i2c_transfer,
+#ifdef CONFIG_I2C_RESET
+  .reset         = stm32_i2c_reset,
+#endif
+};
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_i2c_getreg
+ *
+ * Description:
+ *   Get a 16-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv,
+                                        uint8_t offset)
+{
+  return getreg16(priv->config->base + offset);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_getreg32
+ *
+ * Description:
+ *   Get a 32-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline uint32_t stm32_i2c_getreg32(FAR struct stm32_i2c_priv_s *priv,
+                                          uint8_t offset)
+{
+  return getreg32(priv->config->base + offset);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_putreg
+ *
+ * Description:
+ *  Put a 16-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset,
+                                    uint16_t value)
+{
+  putreg16(value, priv->config->base + offset);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_putreg32
+ *
+ * Description:
+ *  Put a 32-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_putreg32(FAR struct stm32_i2c_priv_s *priv,
+                                      uint8_t offset, uint32_t value)
+{
+  putreg32(value, priv->config->base + offset);
+}
+
+
+/************************************************************************************
+ * Name: stm32_i2c_modifyreg32
+ *
+ * Description:
+ *   Modify a 32-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_modifyreg32(FAR struct stm32_i2c_priv_s *priv,
+                                         uint8_t offset, uint32_t clearbits,
+                                         uint32_t setbits)
+{
+  modifyreg32(priv->config->base + offset, clearbits, setbits);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_sem_wait
+ *
+ * Description:
+ *   Take the exclusive access, waiting as necessary
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_sem_wait(FAR struct i2c_master_s *dev)
+{
+  int ret;
+
+  do
+    {
+      /* Take the semaphore (perhaps waiting) */
+
+      ret = nxsem_wait(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl);
+
+      /* The only case that an error should occur here is if the wait was
+       * awakened by a signal.
+       */
+
+      DEBUGASSERT(ret == OK || ret == -EINTR);
+    }
+  while (ret == -EINTR);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_tousecs
+ *
+ * Description:
+ *   Return a micro-second delay based on the number of bytes left to be processed.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32_I2C_DYNTIMEO
+static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
+{
+  size_t bytecount = 0;
+  int i;
+
+  /* Count the number of bytes left to process */
+
+  for (i = 0; i < msgc; i++)
+    {
+      bytecount += msgs[i].length;
+    }
+
+  /* Then return a number of microseconds based on a user provided scaling
+   * factor.
+   */
+
+  return (useconds_t)(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount);
+}
+#endif
+
+/************************************************************************************
+ * Name: stm32_i2c_enableinterrupts
+ *
+ * Description:
+ *   Enable I2C interrupts
+ *
+ ************************************************************************************/
+
+#ifndef CONFIG_I2C_POLLED
+static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv)
+{
+    stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE));
+}
+#endif
+
+/************************************************************************************
+ * Name: stm32_i2c_sem_waitdone
+ *
+ * Description:
+ *   Wait for a transfer to complete
+ *
+ * There are two versions of this function.  The first is included when using
+ * interrupts while the second is used if polling (CONFIG_I2C_POLLED=y).
+ *
+ ************************************************************************************/
+
+#ifndef CONFIG_I2C_POLLED
+static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
+{
+  struct timespec abstime;
+  irqstate_t flags;
+  int ret;
+
+  flags = enter_critical_section();
+
+  /* Enable I2C interrupts */
+
+  /* The TXIE and RXIE interrupts are enabled initially in stm32_i2c_process.
+   * The remainder of the interrupts, including error-related, are enabled here.
+   */
+
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0,
+                        (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX));
+
+  /* Signal the interrupt handler that we are waiting */
+
+  priv->intstate = INTSTATE_WAITING;
+  do
+    {
+      /* Get the current time */
+
+      (void)clock_gettime(CLOCK_REALTIME, &abstime);
+
+      /* Calculate a time in the future */
+
+#if CONFIG_STM32_I2CTIMEOSEC > 0
+      abstime.tv_sec += CONFIG_STM32_I2CTIMEOSEC;
+#endif
+
+      /* Add a value proportional to the number of bytes in the transfer */
+
+#ifdef CONFIG_STM32_I2C_DYNTIMEO
+      abstime.tv_nsec += 1000 * stm32_i2c_tousecs(priv->msgc, priv->msgv);
+      if (abstime.tv_nsec >= 1000 * 1000 * 1000)
+        {
+          abstime.tv_sec++;
+          abstime.tv_nsec -= 1000 * 1000 * 1000;
+        }
+
+#elif CONFIG_STM32_I2CTIMEOMS > 0
+      abstime.tv_nsec += CONFIG_STM32_I2CTIMEOMS * 1000 * 1000;
+      if (abstime.tv_nsec >= 1000 * 1000 * 1000)
+        {
+          abstime.tv_sec++;
+          abstime.tv_nsec -= 1000 * 1000 * 1000;
+        }
+#endif
+      /* Wait until either the transfer is complete or the timeout expires */
+
+      ret = nxsem_timedwait(&priv->sem_isr, &abstime);
+      if (ret < 0 && ret != -EINTR)
+        {
+          /* Break out of the loop on irrecoverable errors.  This would
+           * include timeouts and mystery errors reported by nxsem_timedwait.
+           * NOTE that we try again if we are awakened by a signal (EINTR).
+           */
+
+          break;
+        }
+    }
+
+  /* Loop until the interrupt level transfer is complete. */
+
+  while (priv->intstate != INTSTATE_DONE);
+
+  /* Set the interrupt state back to IDLE */
+
+  priv->intstate = INTSTATE_IDLE;
+
+  /* Disable I2C interrupts */
+
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
+
+  leave_critical_section(flags);
+  return ret;
+}
+#else
+static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
+{
+  clock_t timeout;
+  clock_t start;
+  clock_t elapsed;
+  int ret;
+
+  /* Get the timeout value */
+
+#ifdef CONFIG_STM32_I2C_DYNTIMEO
+  timeout = USEC2TICK(stm32_i2c_tousecs(priv->msgc, priv->msgv));
+#else
+  timeout = CONFIG_STM32_I2CTIMEOTICKS;
+#endif
+
+  /* Signal the interrupt handler that we are waiting.  NOTE:  Interrupts
+   * are currently disabled but will be temporarily re-enabled below when
+   * nxsem_timedwait() sleeps.
+   */
+
+  priv->intstate = INTSTATE_WAITING;
+  start = clock_systimer();
+
+  do
+    {
+      /* Calculate the elapsed time */
+
+      elapsed = clock_systimer() - start;
+
+      /* Poll by simply calling the timer interrupt handler until it
+       * reports that it is done.
+       */
+
+      stm32_i2c_isr_process(priv);
+    }
+
+  /* Loop until the transfer is complete. */
+
+  while (priv->intstate != INTSTATE_DONE && elapsed < timeout);
+
+  i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: 0x%08x\n",
+          priv->intstate, (long)elapsed, (long)timeout, priv->status);
+
+  /* Set the interrupt state back to IDLE */
+
+  ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT;
+  priv->intstate = INTSTATE_IDLE;
+  return ret;
+}
+#endif
+
+/************************************************************************************
+ * Name: stm32_i2c_set_7bit_address
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32_i2c_set_7bit_address(FAR struct stm32_i2c_priv_s *priv)
+{
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK,
+                        ((priv->msgv->addr & 0x7F) << I2C_CR2_SADD7_SHIFT));
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_set_bytes_to_transfer
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32_i2c_set_bytes_to_transfer(FAR struct stm32_i2c_priv_s *priv,
+                               uint8_t n_bytes)
+{
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK,
+                        (n_bytes << I2C_CR2_NBYTES_SHIFT));
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_set_write_transfer_dir
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32_i2c_set_write_transfer_dir(FAR struct stm32_i2c_priv_s *priv)
+{
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_set_read_transfer_dir
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32_i2c_set_read_transfer_dir(FAR struct stm32_i2c_priv_s *priv)
+{
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_enable_reload
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32_i2c_enable_reload(FAR struct stm32_i2c_priv_s *priv)
+{
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_disable_reload
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32_i2c_disable_reload(FAR struct stm32_i2c_priv_s *priv)
+{
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0);
+}
+
+
+/************************************************************************************
+ * Name: stm32_i2c_sem_waitstop
+ *
+ * Description:
+ *   Wait for a STOP to complete
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
+{
+  clock_t start;
+  clock_t elapsed;
+  clock_t timeout;
+  uint32_t cr;
+  uint32_t sr;
+
+  /* Select a timeout */
+
+#ifdef CONFIG_STM32_I2C_DYNTIMEO
+  timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP);
+#else
+  timeout = CONFIG_STM32_I2CTIMEOTICKS;
+#endif
+
+  /* Wait as stop might still be in progress */
+
+  start = clock_systimer();
+  do
+    {
+      /* Calculate the elapsed time */
+
+      elapsed = clock_systimer() - start;
+
+      /* Check for STOP condition */
+
+      cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET);
+      if ((cr & I2C_CR2_STOP) == 0)
+        {
+          return;
+        }
+
+      /* Check for timeout error */
+
+      sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
+      if ((sr & I2C_INT_TIMEOUT) != 0)
+        {
+          return;
+        }
+
+    }
+
+  /* Loop until the stop is complete or a timeout occurs. */
+
+  while (elapsed < timeout);
+
+  /* If we get here then a timeout occurred with the STOP condition
+   * still pending.
+   */
+
+  i2cinfo("Timeout with CR: %04x SR: %04x\n", cr, sr);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_sem_post
+ *
+ * Description:
+ *   Release the mutual exclusion semaphore
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_sem_post(FAR struct i2c_master_s *dev)
+{
+  nxsem_post(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_sem_init
+ *
+ * Description:
+ *   Initialize semaphores
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev)
+{
+  nxsem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl, 0, 1);
+
+#ifndef CONFIG_I2C_POLLED
+  /* This semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  nxsem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0);
+  nxsem_setprotocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE);
+#endif
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_sem_destroy
+ *
+ * Description:
+ *   Destroy semaphores.
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_sem_destroy(FAR struct i2c_master_s *dev)
+{
+  nxsem_destroy(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl);
+#ifndef CONFIG_I2C_POLLED
+  nxsem_destroy(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr);
+#endif
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_trace*
+ *
+ * Description:
+ *   I2C trace instrumentation
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_I2C_TRACE
+static void stm32_i2c_traceclear(FAR struct stm32_i2c_priv_s *priv)
+{
+  struct stm32_trace_s *trace = &priv->trace[priv->tndx];
+
+  trace->status = 0;              /* I2C 32-bit status */
+  trace->count  = 0;              /* Interrupt count when status change */
+  trace->event  = I2CEVENT_NONE;  /* Last event that occurred with this status */
+  trace->parm   = 0;              /* Parameter associated with the event */
+  trace->time   = 0;              /* Time of first status or event */
+}
+
+static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv)
+{
+  /* Reset the trace info for a new data collection */
+
+  priv->tndx       = 0;
+  priv->start_time = clock_systimer();
+  stm32_i2c_traceclear(priv);
+}
+
+static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv,
+                               uint32_t status)
+{
+  struct stm32_trace_s *trace = &priv->trace[priv->tndx];
+
+  /* Is the current entry uninitialized?   Has the status changed? */
+
+  if (trace->count == 0 || status != trace->status)
+    {
+      /* Yes.. Was it the status changed?  */
+
+      if (trace->count != 0)
+        {
+          /* Yes.. bump up the trace index (unless we are out of trace entries) */
+
+          if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
+            {
+              i2cerr("ERROR: Trace table overflow\n");
+              return;
+            }
+
+          priv->tndx++;
+          trace = &priv->trace[priv->tndx];
+        }
+
+      /* Initialize the new trace entry */
+
+      stm32_i2c_traceclear(priv);
+      trace->status = status;
+      trace->count  = 1;
+      trace->time   = clock_systimer();
+    }
+  else
+    {
+      /* Just increment the count of times that we have seen this status */
+
+      trace->count++;
+    }
+}
+
+static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
+                                enum stm32_trace_e event, uint32_t parm)
+{
+  struct stm32_trace_s *trace;
+
+  if (event != I2CEVENT_NONE)
+    {
+      trace = &priv->trace[priv->tndx];
+
+      /* Initialize the new trace entry */
+
+      trace->event  = event;
+      trace->parm   = parm;
+
+      /* Bump up the trace index (unless we are out of trace entries) */
+
+      if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
+        {
+          i2cerr("ERROR: Trace table overflow\n");
+          return;
+        }
+
+      priv->tndx++;
+      stm32_i2c_traceclear(priv);
+    }
+}
+
+static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
+{
+  struct stm32_trace_s *trace;
+  int i;
+
+  syslog(LOG_DEBUG, "Elapsed time: %d\n",
+         (int)(clock_systimer() - priv->start_time));
+
+  for (i = 0; i < priv->tndx; i++)
+    {
+      trace = &priv->trace[i];
+      syslog(LOG_DEBUG,
+             "%2d. STATUS: %08x COUNT: %3d EVENT: %2d PARM: %08x TIME: %d\n",
+             i+1, trace->status, trace->count,  trace->event, trace->parm,
+             (int)(trace->time - priv->start_time));
+    }
+}
+#endif /* CONFIG_I2C_TRACE */
+
+/************************************************************************************
+ * Name: stm32_i2c_setclock
+ *
+ * Description:
+ *
+ *   Sets the I2C bus clock frequency by configuring the I2C_TIMINGR register.
+ *
+ *   This function supports bus clock frequencies of:
+ *
+ *      1000Khz (Fast Mode+)
+ *      400Khz  (Fast Mode)
+ *      100Khz  (Standard Mode)
+ *      10Khz   (Standard Mode)
+ *
+ *   Attempts to set a different frequency will quietly provision the default
+ *   of 10Khz.
+ *
+ *   The only differences between the various modes of operation (std, fast,
+ *   fast+) are the bus clock speed and setup/hold times.  Setup/hold times are
+ *   specified as a MINIMUM time for the given mode, and naturally std mode
+ *   has the longest minimum times.  As a result, by provisioning setup/hold
+ *   times for std mode they are also compatible with fast/fast+, though some
+ *   performance degradation occurs in fast/fast+ as a result of the times
+ *   being somewhat longer than strictly required.  The values remain as they
+ *   are because reliability is favored over performance.
+ *
+ * Clock Selection:
+ *
+ *   The I2C peripheral clock can be provided by either PCLK1, SYSCLK or the HSI.
+ *
+ *    PCLK1 >------|\   I2CCLK
+ *   SYSCLK >------| |--------->
+ *      HSI >------|/
+ *
+ *   HSI is the default and is always 8Mhz.
+ *
+ *   SYSCLK can, in turn, be derived from the HSI, HSE, PPLCLK.
+ *
+ *      HSI >------|\
+ *                 | |  SYSCLK
+ *      PLL >------| |--------->
+ *                 | |
+ *      HSE >------|/
+ *
+ *
+ * References:
+ *
+ *  App Note AN4235 and the associated software STSW-STM32126.
+ *
+ ************************************************************************************/
+
+static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequency)
+{
+  uint8_t presc;
+  uint8_t scl_delay;
+  uint8_t sda_delay;
+  uint8_t scl_h_period;
+  uint8_t scl_l_period;
+
+  /* I2C peripheral must be disabled to update clocking configuration.
+   * This will SW reset the device.
+   */
+
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
+
+  if (frequency != priv->frequency)
+    {
+
+      /*  The Speed and timing calculation are based on the following
+       *  fI2CCLK = HSI and is 16Mhz
+       *  Analog filter is on,
+       *  Digital filter off
+       *  Rise Time is 120 ns and fall is 10ns
+       *  Mode is FastMode
+       */
+
+        if (frequency == 100000)
+          {
+            presc        = 0;
+            scl_delay    = 5;
+            sda_delay    = 0;
+            scl_h_period = 61;
+            scl_l_period = 89;
+
+          }
+        else if (frequency == 400000)
+           {
+             presc        = 0;
+             scl_delay    = 3;
+             sda_delay    = 0;
+             scl_h_period = 6;
+             scl_l_period = 24;
+           }
+         else if (frequency == 1000000)
+            {
+              presc        = 0;
+              scl_delay    = 2;
+              sda_delay    = 0;
+              scl_h_period = 1;
+              scl_l_period = 5;
+            }
+        else
+          {
+            presc        = 7;
+            scl_delay    = 0;
+            sda_delay    = 0;
+            scl_h_period = 35;
+            scl_l_period = 162;
+          }
+
+      uint32_t timingr =
+        (presc << I2C_TIMINGR_PRESC_SHIFT) |
+        (scl_delay << I2C_TIMINGR_SCLDEL_SHIFT) |
+        (sda_delay << I2C_TIMINGR_SDADEL_SHIFT) |
+        (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) |
+        (scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
+
+      stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr);
+      priv->frequency = frequency;
+    }
+
+  /* Enable I2C peripheral */
+
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_sendstart
+ *
+ * Description:
+ *   Send the START condition / force Master mode
+ *
+ *   A START condition in I2C consists of a single byte that contains both the
+ *   7 bit slave address and a read/write bit (0 = WRITE, 1 = READ).  If the
+ *   address is recognized by one of the slave devices that slave device will
+ *   ACK the byte so that data transfers can begin.
+ *
+ *   A RESTART (or repeated START per the I2CSPEC) is simply a START condition
+ *   issued in the middle of a transfer (i.e. after the initial START and before
+ *   a STOP).  A RESTART sends a new address byte and R/W bit to the bus. A
+ *   RESTART is optional in most cases but mandatory in the event the transfer
+ *   direction is changed.
+ *
+ *   Most of the time reading data from an I2C slave requires a WRITE of the
+ *   subaddress followed by a READ (and hence a RESTART in between).  Writing
+ *   to an I2C slave typically requires only WRITE operations and hence no
+ *   RESTARTs.
+ *
+ *   This function is therefore called both at the beginning of a transfer
+ *   (START) and at appropriate times during a transfer (RESTART).
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv)
+{
+  bool next_norestart = false;
+
+  /* Set the private "current message" data used in protocol processing.
+   *
+   * ptr:   A pointer to the start of the current message buffer.  This is
+   *        advanced after each byte in the current message is transferred.
+   *
+   * dcnt:  A running counter of the bytes in the current message waiting to be
+   *        transferred.  This is decremented each time a byte is transferred.
+   *        The hardware normally accepts a maximum of 255 bytes per transfer
+   *        but can support more via the RELOAD mechanism.  If dcnt initially
+   *        exceeds 255, the RELOAD mechanism will be enabled automatically.
+   *
+   * flags: Used to characterize handling of the current message.
+   *
+   *  The default flags value is 0 which specifies:
+   *
+   *   - A transfer direction of WRITE (R/W bit = 0)
+   *   - RESTARTs between all messages
+   *
+   *  The following flags can be used to override this behavior as follows:
+   *
+   *   - I2C_M_READ: Sets the transfer direction to READ (R/W bit = 1)
+   *   - I2C_M_NOSTART: Prevents a RESTART from being issued prior to the
+   *      transfer of the message (where allowed by the protocol).
+   *
+   */
+
+  priv->ptr   = priv->msgv->buffer;
+  priv->dcnt  = priv->msgv->length;
+  priv->flags = priv->msgv->flags;
+
+  if ((priv->flags & I2C_M_NOSTART) == 0)
+    {
+      /* Flag the first byte as an address byte */
+
+      priv->astart = true;
+    }
+
+  /* Enabling RELOAD allows the transfer of:
+   *
+   *  - individual messages with a payload exceeding 255 bytes
+   *  - multiple messages back to back without a RESTART in between
+   *
+   * so we enable it if either of those conditions exist and disable
+   * it otherwise.
+   */
+
+  /* Check if there are multiple messages and the next is a continuation */
+
+  if (priv->msgc > 1)
+    {
+      next_norestart = (((priv->msgv + 1)->flags & I2C_M_NOSTART) != 0);
+    }
+
+  if (next_norestart || priv->dcnt > 255)
+    {
+      i2cinfo("RELOAD enabled: dcnt = %i msgc = %i\n",
+          priv->dcnt, priv->msgc);
+      stm32_i2c_enable_reload(priv);
+    }
+  else
+    {
+      i2cinfo("RELOAD disable: dcnt = %i msgc = %i\n",
+          priv->dcnt, priv->msgc);
+      stm32_i2c_disable_reload(priv);
+    }
+
+  /* Set the number of bytes to transfer (I2C_CR2->NBYTES) to the number of
+   * bytes in the current message or 255, whichever is lower so as to not
+   * exceed the hardware maximum allowed.
+   */
+
+  if (priv->dcnt > 255)
+    {
+      stm32_i2c_set_bytes_to_transfer(priv, 255);
+    }
+  else
+    {
+      stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
+    }
+
+  /* Set the (7 bit) address.
+   * 10 bit addressing is not yet supported.
+   */
+
+  stm32_i2c_set_7bit_address(priv);
+
+  /* The flag of the current message is used to determine the direction of
+   * transfer required for the current message.
+   */
+
+  if (priv->flags & I2C_M_READ)
+    {
+      stm32_i2c_set_read_transfer_dir(priv);
+    }
+  else
+    {
+      stm32_i2c_set_write_transfer_dir(priv);
+    }
+
+  /* Set the I2C_CR2->START bit to 1 to instruct the hardware to send the
+   * START condition using the address and transfer direction data entered.
+   */
+
+  i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n",
+          priv->dcnt, priv->msgc, priv->flags);
+
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_sendstop
+ *
+ * Description:
+ *   Send the STOP conditions
+ *
+ *   A STOP condition can be requested by setting the STOP bit in the I2C_CR2
+ *   register. Setting the STOP bit clears the TC flag and the STOP condition is
+ *   sent on the bus.
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv)
+{
+  i2cinfo("Sending STOP\n");
+  stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0);
+
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_getstatus
+ *
+ * Description:
+ *   Get 32-bit status (SR1 and SR2 combined)
+ *
+ ************************************************************************************/
+
+static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv)
+{
+  return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_clearinterrupts
+ *
+ * Description:
+ *  Clear all interrupts
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv)
+{
+  stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_isr_process
+ *
+ * Description:
+ *  Common interrupt service routine (ISR) that handles I2C protocol logic.
+ *  This is instantiated for each configured I2C interface (I2C1, I2C2, I2C3).
+ *
+ *  This ISR is activated and deactivated by:
+ *
+ *   stm32_i2c_process
+ *    and
+ *   stm32_i2c_waitdone
+ *
+ * Input Parameters:
+ *   priv - The private struct of the I2C driver.
+ *
+ ************************************************************************************/
+
+static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
+{
+  uint32_t status;
+
+  /* Get state of the I2C controller */
+
+  status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
+
+  i2cinfo("ENTER: status = 0x%08x\n", status);
+
+  /* Update private version of the state assuming a good state */
+
+  priv->status = status & ~I2C_INT_BAD_STATE;
+
+  /* If this is a new transmission set up the trace table accordingly */
+
+  stm32_i2c_tracenew(priv, status);
+  stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0);
+
+  /* --------------------- Start of I2C protocol handling -------------------- */
+
+  /* I2C protocol logic follows. It's organized in an if else chain such that
+   * only one mode of operation is executed every time the ISR is called.
+   *
+   * If you need to add additional states to support new features be sure they
+   * continue the chain (i.e. begin with "else if") and are placed before the
+   * empty call / error states at the end of the chain.
+   */
+
+  /* NACK Handling
+   *
+   * This branch is only triggered when the NACK (Not Acknowledge Received)
+   * interrupt occurs.  This interrupt will only fire when the I2C_CR1->NACKIE
+   * bit is 1.
+   *
+   * I2C_ISR->NACKF is set by hardware when a NACK is received after a byte
+   * is transmitted and the slave fails to acknowledge it.  This is the
+   * opposite of, and mutually exclusive to, the I2C_ISR->TXIS event.
+   *
+   * In response to the NACK the hardware automatically triggers generation
+   * of a STOP condition, terminating the transfer.  The only valid response
+   * to this state is to exit the ISR and report the failure.
+   *
+   * To differentiate an "address NACK" from a NACK that might occur during
+   * the transfer of other bytes the "priv->astart" parameter is
+   * used.  This flag is set to TRUE in sendstart() and set to FALSE when
+   * the first TXIS event is received, which would be after the first byte
+   * (the address) is transmitted successfully (acknowledged).
+   */
+
+  if (status & I2C_INT_NACK)
+    {
+
+      if (priv->astart == true)
+        {
+
+          /* NACK received on first (address) byte: address is invalid */
+
+          i2cinfo("NACK: Address invalid: dcnt=%i msgc=%i status=0x%08x\n",
+          priv->dcnt, priv->msgc, status);
+          stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr);
+        }
+      else
+        {
+          /* NACK received on regular byte */
+
+          i2cinfo("NACK: NACK received: dcnt=%i msgc=%i status=0x%08x\n",
+          priv->dcnt, priv->msgc, status);
+          stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr);
+        }
+
+      /* Set flags to terminate message transmission:
+       *
+       *   set message length to -1 to indicate last byte of message sent
+       *   set message count to 0 to indicate no more messages to send
+       *
+       * As we fall through the logic in the ISR the message handling block
+       * will be triggered by these flags and signal the ISR to terminate.
+       */
+
+      priv->dcnt = -1;
+      priv->msgc = 0;
+    }
+
+  /* Transmit Interrupt Status (TXIS) Handler
+   *
+   * This branch is only triggered when the TXIS interrupt occurs.  This
+   * interrupt will only fire when the I2C_CR1->TXIE bit is 1.
+   *
+   * This indicates the transmit data register I2C_TXDR has been emptied
+   * following the successful transmission of a byte and slave acknowledgment.
+   * In this state the I2C_TXDR register is ready to accept another byte for
+   * transmission.  The TXIS bit will be cleared automatically when the next
+   * byte is written to I2C_TXDR.
+   *
+   * The number of TXIS events during the transfer corresponds to NBYTES.
+   *
+   * The TXIS flag is not set when a NACK is received.
+   *
+   * When RELOAD is disabled (RELOAD=0) and NBYTES data have been transferred:
+   *
+   *   - In Automatic End Mode (AUTOEND=1), a STOP is automatically sent.
+   *
+   *     Note:  Automatic End Mode is not currently supported.
+   *
+   *   - In Software End Mode (AUTOEND=0), the TC event occurs and the SCL
+   *     line is stretched low in order to allow software actions (STOP,
+   *     RESTART).
+   *
+   * When RELOAD is enabled (RELOAD=1) and NBYTES bytes have been transferred
+   * a TCR event occurs instead and that handler simply updates NBYTES which
+   * causes TXIS events to continue.  The process repeats until all bytes in
+   * the message have been transferred.
+   */
+
+  else if ((priv->flags & (I2C_M_READ)) == 0 && (status & (I2C_ISR_TXIS)) != 0)
+    {
+
+      /* TXIS interrupt occurred, address valid, ready to transmit */
+
+      stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0);
+      i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08x\n",
+              priv->dcnt, priv->msgc, status);
+
+      /* The first event after the address byte is sent will be either TXIS
+       * or NACKF so it's safe to set the astart flag to false on
+       * the first TXIS event to indicate that it is no longer necessary to
+       * check for address validity.
+       */
+
+      if (priv->astart == true)
+        {
+          i2cinfo("TXIS: Address Valid\n");
+          stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, priv->msgv->addr);
+          priv->astart = false;
+        }
+
+      /* If one or more bytes in the current message are ready to transmit */
+
+      if (priv->dcnt > 0)
+        {
+          /* Prepare to transmit the current byte */
+
+          stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt);
+          i2cinfo("TXIS: Write Data 0x%02x\n", *priv->ptr);
+
+          /* Decrement byte counter */
+
+          priv->dcnt--;
+
+          /* If we are about to transmit the last byte in the current message */
+
+          if (priv->dcnt == 0)
+            {
+              /* If this is also the last message to send, disable RELOAD so
+               * TC fires next and issues STOP condition.  If we don't do this
+               * TCR will fire next, and since there are no bytes to send we
+               * can't write NBYTES to clear TCR so it will fire forever.
+               */
+
+              if (priv->msgc == 1)
+                {
+                  stm32_i2c_disable_reload(priv);
+                }
+            }
+
+          /* Transmit current byte */
+
+          stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr);
+
+          /* Advance to next byte */
+
+          priv->ptr++;
+        }
+      else
+        {
+          /* Unsupported state */
+
+          i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, status 0x%08x\n",
+          priv->dcnt, status);
+          stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0);
+
+          /* Indicate the bad state, so that on termination HW will be reset */
+
+          priv->status |= I2C_INT_BAD_STATE;
+        }
+
+      i2cinfo("TXIS: EXIT  dcnt = %i msgc = %i status 0x%08x\n",
+              priv->dcnt, priv->msgc, status);
+    }
+
+  /* Receive Buffer Not Empty (RXNE) State Handler
+   *
+   * This branch is only triggered when the RXNE interrupt occurs.  This
+   * interrupt will only fire when the I2C_CR1->RXIE bit is 1.
+   *
+   * This indicates data has been received from the bus and is waiting to
+   * be read from the I2C_RXDR register.  When I2C_RXDR is read this bit
+   * is automatically cleared and then an ACK or NACK is sent depending on
+   * whether we have more bytes to receive.
+   *
+   * When RELOAD is disabled and bytes remain to be transferred an acknowledge
+   * is automatically sent on the bus and the RXNE events continue until the
+   * last byte is received.
+   *
+   * When RELOAD is disabled (RELOAD=0) and BYTES have been transferred:
+   *
+   *   - In Automatic End Mode (AUTOEND=1), a NACK and a STOP are automatically
+   *     sent after the last received byte.
+   *
+   *     Note:  Automatic End Mode is not currently supported.
+   *
+   *   - In Software End Mode (AUTOEND=0), a NACK is automatically sent after
+   *     the last received byte, the TC event occurs and the SCL line is
+   *     stretched low in order to allow software actions (STOP, RESTART).
+   *
+   * When RELOAD is enabled (RELOAD=1) and NBYTES bytes have been transferred
+   * a TCR event occurs and that handler simply updates NBYTES which causes
+   * RXNE events to continue until all bytes have been transferred.
+   */
+
+  else if ((priv->flags & (I2C_M_READ)) != 0 && (status & I2C_ISR_RXNE) != 0)
+    {
+      /* When read flag is set and the receive buffer is not empty
+       * (RXNE is set) then the driver can read from the data register.
+       */
+
+      stm32_i2c_traceevent(priv, I2CEVENT_READ, 0);
+      i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08x\n",
+              priv->dcnt, priv->msgc, status);
+
+      /* If more bytes in the current message */
+
+      if (priv->dcnt > 0)
+        {
+          stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt);
+
+          /* No interrupts or context switches may occur in the following
+           * sequence.  Otherwise, additional bytes may be received.
+           */
+
+#ifdef CONFIG_I2C_POLLED
+          irqstate_t state = enter_critical_section();
+#endif
+          /* Receive a byte */
+
+          *priv->ptr = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET);
+
+          i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr);
+
+          /* Advance buffer to the next byte in the message */
+
+          priv->ptr++;
+
+          /* Signal byte received */
+
+          priv->dcnt--;
+
+#ifdef CONFIG_I2C_POLLED
+          leave_critical_section(state);
+#endif
+        }
+      else
+        {
+          /* Unsupported state */
+
+          stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0);
+          status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
+          i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, status 0x%08x\n",
+                 priv->dcnt, status);
+
+          /* Set signals that will terminate ISR and wake waiting thread */
+
+          priv->status |= I2C_INT_BAD_STATE;
+          priv->dcnt = -1;
+          priv->msgc = 0;
+        }
+
+      i2cinfo("RXNE: EXIT  dcnt = %i msgc = %i status 0x%08x\n",
+              priv->dcnt, priv->msgc, status);
+    }
+
+  /* Transfer Complete (TC) State Handler
+   *
+   * This branch is only triggered when the TC interrupt occurs.  This
+   * interrupt will only fire when:
+   *
+   * I2C_CR1->TCIE = 1 (Transfer Complete Interrupts Enabled)
+   * I2C_CR2->RELOAD = 0 (Reload Mode Disabled)
+   * I2C_CR2->AUTOEND = 0 (Autoend Mode Disabled, i.e. Software End Mode)
+   *
+   * This event indicates that the number of bytes initially defined
+   * in NBYTES, meaning, the number of bytes in the current message (priv->dcnt)
+   * has been successfully transmitted or received.
+   *
+   * When the TC interrupt occurs we have two choices to clear it and move
+   * on, regardless of the transfer direction:
+   *
+   *    - if more messages follow, perform a repeated START if required
+   *      and then fall through to transmit or receive the next message.
+   *
+   *    - if no messages follow, perform a STOP and set flags needed to
+   *      exit the ISR.
+   *
+   * The fact that the hardware must either RESTART or STOP when a TC
+   * event occurs explains why, when messages must be sent back to back
+   * (i.e. without a restart by specifying the I2C_M_NOSTART flag),
+   * RELOAD mode must be enabled and TCR event(s) must be generated
+   * instead.  See the TCR handler for more.
+   */
+
+  else if ((status & I2C_ISR_TC) != 0)
+    {
+      i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08x\n",
+              priv->dcnt, priv->msgc, status);
+
+      /* Prior message has been sent successfully. Or there could have
+       * been an error that set msgc to 0; So test for that case as
+       * we do not want to decrement msgc less then zero nor move msgv
+       * past the last message.
+       */
+
+      if (priv->msgc > 0)
+        {
+          priv->msgc--;
+        }
+
+      /* Are there additional messages remain to be transmitted / received? */
+
+      if (priv->msgc > 0)
+        {
+          i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n",
+          priv->dcnt, priv->msgc);
+          stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc);
+
+          /* Issue a START condition.
+           *
+           * Note that the first thing sendstart does is update the
+           * private structure "current message" data (ptr, dcnt, flags)
+           * so they all reflect the next message in the list so we
+           * update msgv before we get there.
+           */
+
+          /* Advance to the next message in the list */
+
+          priv->msgv++;
+
+          stm32_i2c_sendstart(priv);
+
+        }
+      else
+        {
+          /* Issue a STOP conditions.
+           *
+           * No additional messages to transmit / receive, so the
+           * transfer is indeed complete.  Nothing else to do but
+           * issue a STOP and exit.
+           */
+
+          i2cinfo("TC: STOP: dcnt=%i msgc=%i\n",
+          priv->dcnt, priv->msgc);
+          stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt);
+
+          stm32_i2c_sendstop(priv);
+
+          /* Set signals that will terminate ISR and wake waiting thread */
+
+          priv->dcnt = -1;
+          priv->msgc = 0;
+        }
+
+      i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08x\n",
+      priv->dcnt, priv->msgc, status);
+    }
+
+  /* Transfer Complete (Reload) State Handler
+   *
+   * This branch is only triggered when the TCR interrupt occurs.  This
+   * interrupt will only fire when:
+   *
+   *  I2C_CR1->TCIE = 1 (Transfer Complete Interrupts Enabled)
+   *  I2C_CR2->RELOAD = 1 (Reload Mode Active)
+   *  I2C_CR2->AUTOEND = 0 (Autoend Mode Disabled, i.e. Software End Mode)
+   *
+   * This is similar to the TC event except that TCR assumes that additional
+   * bytes are available to transfer.  So despite what its name might imply
+   * the transfer really isn't complete.
+   *
+   * There are two reasons RELOAD would be enabled:
+   *
+   *  1) We're trying to send a message with a payload greater than 255 bytes.
+   *  2) We're trying to send messages back to back, regardless of their
+   *     payload size, to avoid a RESTART (i.e. I2C_M_NOSTART flag is set).
+   *
+   * These conditions may be true simultaneously, as would be the case if
+   * we're sending multiple messages with payloads > 255 bytes.   So we only
+   * advance to the next message if we arrive here and dcnt is 0, meaning,
+   * we're finished with the last message and ready to move to the next.
+   *
+   * This logic supports the transfer of bytes limited only by the size of
+   * the i2c_msg_s length variable.  The SCL line will be stretched low
+   * until NBYTES is written with a non-zero value, allowing the transfer
+   * to continue.
+   *
+   * TODO: RESTARTs are required by the I2CSPEC if the next message transfer
+   * direction changes.  Right now the NORESTART flag overrides this behavior.
+   * May have to introduce logic to issue sendstart, assuming it's legal
+   * with the hardware in the TCR state.
+   */
+
+  else if ((status & I2C_ISR_TCR) != 0)
+    {
+      i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08x\n",
+      priv->dcnt, priv->msgc, status);
+
+      /* If no more bytes in the current message to transfer */
+
+      if (priv->dcnt == 0)
+        {
+          /* Prior message has been sent successfully */
+
+          priv->msgc--;
+
+          /* Advance to the next message in the list */
+
+          priv->msgv++;
+
+          /* Update current message data */
+
+          priv->ptr    = priv->msgv->buffer;
+          priv->dcnt   = priv->msgv->length;
+          priv->flags  = priv->msgv->flags;
+
+          /* if this is the last message, disable reload so the
+           * TC event fires next time */
+
+          if (priv->msgc == 0)
+            {
+              i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n",
+              priv->dcnt, priv->msgc);
+
+              stm32_i2c_disable_reload(priv);
+            }
+
+          /* Update NBYTES with length of current message */
+
+          i2cinfo("TCR: NEXT MSG dcnt = %i msgc = %i\n",
+                  priv->dcnt, priv->msgc);
+
+          stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
+        }
+      else
+        {
+          /* More bytes in the current (greater than 255 byte payload
+           * length) message, so set NBYTES according to the bytes
+           * remaining in the message, up to a maximum each cycle of 255.
+           */
+
+          if (priv->dcnt > 255)
+            {
+              i2cinfo("TCR: ENABLE RELOAD: NBYTES = 255 dcnt = %i msgc = %i\n",
+              priv->dcnt, priv->msgc);
+
+              /* More than 255 bytes to transfer so the RELOAD bit is
+               * set in order to generate a TCR event rather than a TC
+               * event when 255 bytes are successfully transferred.
+               * This forces us to return here to update NBYTES and
+               * continue until NBYTES is set to less than 255 bytes,
+               * at which point RELOAD will be disabled and a TC
+               * event will (eventually) follow to officially terminate
+               * the transfer.
+               */
+
+              stm32_i2c_enable_reload(priv);
+
+              stm32_i2c_set_bytes_to_transfer(priv, 255);
+            }
+          else
+            {
+              /* Less than 255 bytes left to transfer, which means we'll
+               * complete the transfer of all bytes in the current message
+               * the next time around.
+               *
+               * This means we need to disable the RELOAD functionality so
+               * we receive a TC event next time which will allow us to
+               * either RESTART and continue sending the contents of the
+               * next message or send a STOP condition and exit the ISR.
+               */
+
+              i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n",
+                      priv->dcnt, priv->msgc);
+
+              stm32_i2c_disable_reload(priv);
+
+              stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
+            }
+
+          i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08x\n",
+          priv->dcnt, priv->msgc, status);
+        }
+    }
+
+  /* Empty call handler
+   *
+   * Case to handle an empty call to the ISR where it has nothing to
+   * do and should exit immediately.
+   */
+
+  else if (priv->dcnt == -1 && priv->msgc == 0)
+    {
+      status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
+      i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08x\n", status);
+      stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0);
+    }
+
+  /* Error handler
+   *
+   * We get to this branch only if we can't handle the current state.
+   *
+   * This can happen in interrupt based operation on ARLO & BUSY.
+   *
+   * This will happen during polled operation when the device is not
+   * in one of the supported states when polled.
+   */
+
+  else
+    {
+#ifdef CONFIG_I2C_POLLED
+      stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0);
+#else
+      /* Read rest of the state */
+
+      status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
+
+      i2cerr("ERROR: Invalid state detected, status 0x%08x\n", status);
+
+      /* set condition to terminate ISR and wake waiting thread */
+
+      priv->status |= I2C_INT_BAD_STATE;
+      priv->dcnt = -1;
+      priv->msgc = 0;
+      stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0);
+#endif
+    }
+
+  /* --------------------- End of I2C protocol handling -------------------- */
+
+  /* Message Handling
+   *
+   * Transmission of the whole message chain has been completed. We have to
+   * terminate the ISR and wake up stm32_i2c_process() that is waiting for
+   * the ISR cycle to handle the sending/receiving of the messages.
+   */
+
+  if (priv->dcnt == -1 && priv->msgc == 0)
+    {
+      i2cinfo("MSG: Shutting down I2C ISR\n");
+
+      stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0);
+
+      /* clear pointer to message content to reflect we are done
+       * with the current transaction */
+
+      priv->msgv = NULL;
+
+#ifdef CONFIG_I2C_POLLED
+      priv->intstate = INTSTATE_DONE;
+#else
+
+      /* We will update private state to capture NACK which is used in
+       * combination with the astart flag to report the type of NACK received
+       * (address vs data) to the upper layers once we exit the ISR.
+       *
+       * Note: status is captured  prior to clearing interrupts because
+       * the NACKF flag will naturally be cleared by that process.
+       */
+
+      status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
+
+      /* Clear all interrupts */
+
+      stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
+
+      /* Was a bad state detected in the processing? */
+
+      if (priv->status & I2C_INT_BAD_STATE)
+        {
+          /* SW reset device  */
+
+          stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
+        }
+
+      /* Update private status from above sans I2C_INT_BAD_STATE */
+
+      priv->status = status;
+
+      /* If a thread is waiting then inform it transfer is complete */
+
+      if (priv->intstate == INTSTATE_WAITING)
+        {
+          nxsem_post(&priv->sem_isr);
+          priv->intstate = INTSTATE_DONE;
+        }
+#endif
+    }
+
+  status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
+  i2cinfo("EXIT: status = 0x%08x\n", status);
+
+  return OK;
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_isr
+ *
+ * Description:
+ *   Common I2C interrupt service routine
+ *
+ ************************************************************************************/
+
+#ifndef CONFIG_I2C_POLLED
+static int stm32_i2c_isr(int irq, void *context, FAR void *arg)
+{
+  struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg;
+
+  DEBUGASSERT(priv != NULL);
+  return stm32_i2c_isr_process(priv);
+}
+#endif
+
+/************************************************************************************
+ * Name: stm32_i2c_init
+ *
+ * Description:
+ *   Setup the I2C hardware, ready for operation with defaults
+ *
+ ************************************************************************************/
+
+static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
+{
+  /* Power-up and configure GPIOs */
+
+  /* Enable power and reset the peripheral */
+
+  modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit);
+  modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit);
+  modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0);
+
+  /* Configure pins */
+
+  if (stm32_configgpio(priv->config->scl_pin) < 0)
+    {
+      return ERROR;
+    }
+
+  if (stm32_configgpio(priv->config->sda_pin) < 0)
+    {
+      stm32_unconfiggpio(priv->config->scl_pin);
+      return ERROR;
+    }
+
+#ifndef CONFIG_I2C_POLLED
+  /* Attach error and event interrupts to the ISRs */
+
+  irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv);
+  irq_attach(priv->config->er_irq, stm32_i2c_isr, priv);
+  up_enable_irq(priv->config->ev_irq);
+  up_enable_irq(priv->config->er_irq);
+#endif
+
+  /* TODO:
+   * - Provide means to set peripheral clock source via RCC_CFGR3_I2CxSW
+   * - Set to HSI by default, make Kconfig option
+   */
+
+  /* Force a frequency update */
+
+  priv->frequency = 0;
+  stm32_i2c_setclock(priv, 100000);
+
+  return OK;
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_deinit
+ *
+ * Description:
+ *   Shutdown the I2C hardware
+ *
+ ************************************************************************************/
+
+static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv)
+{
+  /* Disable I2C */
+
+  stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0);
+
+  /* Unconfigure GPIO pins */
+
+  stm32_unconfiggpio(priv->config->scl_pin);
+  stm32_unconfiggpio(priv->config->sda_pin);
+
+#ifndef CONFIG_I2C_POLLED
+
+  /* Disable and detach interrupts */
+
+  up_disable_irq(priv->config->ev_irq);
+  up_disable_irq(priv->config->er_irq);
+  irq_detach(priv->config->ev_irq);
+  irq_detach(priv->config->er_irq);
+#endif
+
+  /* Disable clocking */
+
+  modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0);
+
+  return OK;
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_process
+ *
+ * Description:
+ *   Common I2C transfer logic
+ *
+ *   Initiates a master mode transaction on the I2C bus to transfer the provided
+ *   messages to and from the slave devices.
+ *
+ ************************************************************************************/
+
+static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count)
+{
+  struct stm32_i2c_inst_s     *inst = (struct stm32_i2c_inst_s *)dev;
+  FAR struct stm32_i2c_priv_s *priv = inst->priv;
+  uint32_t    status = 0;
+  uint32_t    cr1;
+  uint32_t    cr2;
+  int         errval = 0;
+  int         waitrc = 0;
+
+  DEBUGASSERT(count > 0);
+
+  /* Wait for any STOP in progress */
+
+  stm32_i2c_sem_waitstop(priv);
+
+  /* Clear any pending error interrupts */
+
+  stm32_i2c_clearinterrupts(priv);
+
+  /* Old transfers are done */
+
+  priv->msgv = msgs;
+  priv->msgc = count;
+
+  /* Reset I2C trace logic */
+
+  stm32_i2c_tracereset(priv);
+
+  /* Set I2C clock frequency toggles I2C_CR1_PE performing a SW reset! */
+
+  stm32_i2c_setclock(priv, msgs->frequency);
+
+  /* Trigger start condition, then the process moves into the ISR.  I2C
+   * interrupts will be enabled within stm32_i2c_waitdone().
+   */
+
+  priv->status = 0;
+
+#ifndef CONFIG_I2C_POLLED
+  /* Enable transmit and receive interrupts here so when we send the start
+   * condition below the ISR will fire if the data was sent and some
+   * response from the slave received.  All other interrupts relevant to
+   * our needs are enabled in stm32_i2c_sem_waitdone() below.
+   */
+
+  stm32_i2c_enableinterrupts(priv);
+#endif
+
+  /* Trigger START condition generation, which also sends the slave address
+   * with read/write flag and the data in the first message
+   */
+
+  stm32_i2c_sendstart(priv);
+
+  /* Wait for the ISR to tell us that the transfer is complete by attempting
+   * to grab the semaphore that is initially locked by the ISR.  If the ISR
+   * does not release the lock so we can obtain it here prior to the end of
+   * the timeout period waitdone returns error and we report a timeout.
+   */
+
+  waitrc = stm32_i2c_sem_waitdone(priv);
+
+  cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET);
+  cr2 = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET);
+#if !defined(CONFIG_DEBUG_I2C)
+  UNUSED(cr1);
+  UNUSED(cr2);
+#endif
+
+  /* Status after a normal / good exit is usually 0x00000001, meaning the TXE
+   * bit is set.  That occurs as a result of the I2C_TXDR register being
+   * empty, and it naturally will be after the last byte is transmitted.
+   * This bit is cleared when we attempt communications again and re-enable
+   * the peripheral.  The priv->status field can hold additional information
+   * like a NACK, so we reset the status field to include that information.
+   */
+
+  status = stm32_i2c_getstatus(priv);
+
+  /* The priv->status field can hold additional information like a NACK
+   * event so we include that information.
+   */
+
+  status = priv->status & 0xffffffff;
+
+  if (waitrc < 0)
+    {
+      /* Connection timed out */
+
+      errval = ETIMEDOUT;
+      i2cerr("ERROR: Waitdone timed out CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n",
+             cr1, cr2,status);
+    }
+  else
+    {
+      i2cinfo("Waitdone success: CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n",
+             cr1, cr2,status );
+    }
+
+  UNUSED(cr1);
+  UNUSED(cr2);
+
+  i2cinfo("priv->status: 0x%08x\n", priv->status);
+
+  /* Check for error status conditions */
+
+  if ((status & (I2C_INT_BERR |
+                 I2C_INT_ARLO |
+                 I2C_INT_OVR |
+                 I2C_INT_PECERR |
+                 I2C_INT_TIMEOUT |
+                 I2C_INT_NACK)) != 0)
+
+    {
+      /* one or more errors in the mask are present */
+
+      if (status & I2C_INT_BERR)
+        {
+          /* Bus Error, ignore it because of errata (revision A,Z) */
+
+          i2cerr("ERROR: I2C Bus Error\n");
+
+          /* errval = EIO; */
+        }
+      else if (status & I2C_INT_ARLO)
+        {
+          /* Arbitration Lost (master mode) */
+
+          i2cerr("ERROR: I2C Arbitration Lost\n");
+          errval = EAGAIN;
+        }
+
+      else if (status & I2C_INT_OVR)
+        {
+          /* Overrun/Underrun */
+
+          i2cerr("ERROR: I2C Overrun/Underrun\n");
+          errval = EIO;
+        }
+      else if (status & I2C_INT_PECERR)
+        {
+      /* PEC Error in reception (SMBus Only) */
+
+          i2cerr("ERROR: I2C PEC Error\n");
+          errval = EPROTO;
+        }
+      else if (status & I2C_INT_TIMEOUT)
+        {
+          /* Timeout or Tlow Error (SMBus Only) */
+
+          i2cerr("ERROR: I2C Timeout / Tlow Error\n");
+          errval = ETIME;
+        }
+      else if (status & I2C_INT_NACK)
+        {
+          /* NACK Received, flag as "communication error on send" */
+
+          if (priv->astart == TRUE)
+            {
+              i2cwarn("WARNING: I2C Address NACK\n");
+              errval = EADDRNOTAVAIL;
+            }
+          else
+            {
+              i2cwarn("WARNING: I2C Data NACK\n");
+              errval = ECOMM;
+            }
+        }
+      else
+        {
+          /* Unrecognized error */
+
+          i2cerr("ERROR: I2C Unrecognized Error");
+          errval = EINTR;
+        }
+    }
+
+  /* This is not an error, but should not happen.  The BUSY signal can be
+   * present if devices on the bus are in an odd state and need to be reset.
+   * NOTE:  We will only see this busy indication if stm32_i2c_sem_waitdone()
+   * fails above;  Otherwise it is cleared.
+   */
+
+  else if ((status & I2C_ISR_BUSY) != 0)
+    {
+      /* I2C Bus Busy
+       *
+       * This is a status condition rather than an error.
+       *
+       * We will only see this busy indication if stm32_i2c_sem_waitdone()
+       * fails above;  Otherwise it is cleared by the hardware when the ISR
+       * wraps up the transfer with a STOP condition.
+       */
+
+      clock_t start = clock_systimer();
+      clock_t timeout = USEC2TICK(USEC_PER_SEC/priv->frequency) + 1;
+
+      status = stm32_i2c_getstatus(priv);
+
+      while (status & I2C_ISR_BUSY)
+        {
+          if ((clock_systimer() - start) > timeout)
+            {
+              i2cerr("ERROR: I2C Bus busy");
+              errval = EBUSY;
+              break;
+            }
+
+          status = stm32_i2c_getstatus(priv);
+        }
+    }
+
+  /* Dump the trace result */
+
+  stm32_i2c_tracedump(priv);
+  stm32_i2c_sem_post(dev);
+
+  return -errval;
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_transfer
+ *
+ * Description:
+ *   Generic I2C transfer function
+ *
+ ************************************************************************************/
+
+static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
+                              int count)
+{
+  stm32_i2c_sem_wait(dev);   /* ensure that address or flags don't change meanwhile */
+  return stm32_i2c_process(dev, msgs, count);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_reset
+ *
+ * Description:
+ *   Reset an I2C bus
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_I2C_RESET
+static int stm32_i2c_reset(FAR struct i2c_master_s * dev)
+{
+  struct stm32_i2c_priv_s * priv;
+  unsigned int clock_count;
+  unsigned int stretch_count;
+  uint32_t scl_gpio;
+  uint32_t sda_gpio;
+  uint32_t frequency;
+  int ret = ERROR;
+
+  DEBUGASSERT(dev);
+
+  /* Get I2C private structure */
+
+  priv = ((struct stm32_i2c_inst_s *)dev)->priv;
+
+  /* Our caller must own a ref */
+
+  DEBUGASSERT(priv->refs > 0);
+
+  /* Lock out other clients */
+
+  stm32_i2c_sem_wait(dev);
+
+  /* Save the current frequency */
+
+  frequency = priv->frequency;
+
+  /* De-init the port */
+
+  stm32_i2c_deinit(priv);
+
+  /* Use GPIO configuration to un-wedge the bus */
+
+  scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin);
+  sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin);
+
+  stm32_configgpio(sda_gpio);
+  stm32_configgpio(scl_gpio);
+
+  /* Let SDA go high */
+
+  stm32_gpiowrite(sda_gpio, 1);
+
+  /* Clock the bus until any slaves currently driving it let it go. */
+
+  clock_count = 0;
+  while (!stm32_gpioread(sda_gpio))
+    {
+      /* Give up if we have tried too hard */
+
+      if (clock_count++ > 10)
+        {
+          goto out;
+        }
+
+      /* Sniff to make sure that clock stretching has finished.
+       *
+       * If the bus never relaxes, the reset has failed.
+       */
+
+      stretch_count = 0;
+      while (!stm32_gpioread(scl_gpio))
+        {
+          /* Give up if we have tried too hard */
+
+          if (stretch_count++ > 10)
+            {
+              goto out;
+            }
+
+          up_udelay(10);
+        }
+
+      /* Drive SCL low */
+
+      stm32_gpiowrite(scl_gpio, 0);
+      up_udelay(10);
+
+      /* Drive SCL high again */
+
+      stm32_gpiowrite(scl_gpio, 1);
+      up_udelay(10);
+    }
+
+  /* Generate a start followed by a stop to reset slave
+   * state machines.
+   */
+
+  stm32_gpiowrite(sda_gpio, 0);
+  up_udelay(10);
+  stm32_gpiowrite(scl_gpio, 0);
+  up_udelay(10);
+  stm32_gpiowrite(scl_gpio, 1);
+  up_udelay(10);
+  stm32_gpiowrite(sda_gpio, 1);
+  up_udelay(10);
+
+  /* Revert the GPIO configuration. */
+
+  stm32_unconfiggpio(sda_gpio);
+  stm32_unconfiggpio(scl_gpio);
+
+  /* Re-init the port */
+
+  stm32_i2c_init(priv);
+
+  /* Restore the frequency */
+
+  stm32_i2c_setclock(priv, frequency);
+  ret = OK;
+
+out:
+
+  /* Release the port for re-use by other clients */
+
+  stm32_i2c_sem_post(dev);
+  return ret;
+}
+#endif /* CONFIG_I2C_RESET */
+
+/************************************************************************************
+ * Name: stm32_i2c_pm_prepare
+ *
+ * Description:
+ *   Request the driver to prepare for a new power state. This is a
+ *   warning that the system is about to enter into a new power state.  The
+ *   driver should begin whatever operations that may be required to enter
+ *   power state.  The driver may abort the state change mode by returning
+ *   a non-zero value from the callback function.
+ *
+ * Input Parameters:
+ *   cb      - Returned to the driver.  The driver version of the callback
+ *             structure may include additional, driver-specific state
+ *             data at the end of the structure.
+ *   domain  - Identifies the activity domain of the state change
+ *   pmstate - Identifies the new PM state
+ *
+ * Returned Value:
+ *   0 (OK) means the event was successfully processed and that the driver
+ *   is prepared for the PM state change.  Non-zero means that the driver
+ *   is not prepared to perform the tasks needed achieve this power setting
+ *   and will cause the state change to be aborted.  NOTE:  The prepare
+ *   method will also be recalled when reverting from lower back to higher
+ *   power consumption modes (say because another driver refused a lower
+ *   power state change).  Drivers are not permitted to return non-zero
+ *   values when reverting back to higher power consumption modes!
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_PM
+static int stm32_i2c_pm_prepare(FAR struct pm_callback_s *cb, int domain,
+                                enum pm_state_e pmstate)
+{
+  struct stm32_i2c_priv_s *priv =
+      (struct stm32_i2c_priv_s *)((char *)cb -
+                                    offsetof(struct stm32_i2c_priv_s, pm_cb));
+  int sval;
+
+  /* Logic to prepare for a reduced power state goes here. */
+
+  switch (pmstate)
+    {
+    case PM_NORMAL:
+    case PM_IDLE:
+      break;
+
+    case PM_STANDBY:
+    case PM_SLEEP:
+      /* Check if exclusive lock for I2C bus is held. */
+
+      if (nxsem_getvalue(&priv->sem_excl, &sval) < 0)
+        {
+          DEBUGASSERT(false);
+          return -EINVAL;
+        }
+
+      if (sval <= 0)
+        {
+          /* Exclusive lock is held, do not allow entry to deeper PM states. */
+
+          return -EBUSY;
+        }
+
+      break;
+
+    default:
+      /* Should not get here */
+
+      break;
+    }
+
+  return OK;
+}
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_i2cbus_initialize
+ *
+ * Description:
+ *   Initialize one I2C bus
+ *
+ ************************************************************************************/
+
+FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
+{
+  struct stm32_i2c_priv_s * priv = NULL;  /* private data of device with multiple instances */
+  struct stm32_i2c_inst_s * inst = NULL;  /* device, single instance */
+  irqstate_t irqs;
+#ifdef CONFIG_PM
+  int ret;
+#endif
+
+#if STM32_HSI_FREQUENCY != 8000000 || defined(INVALID_CLOCK_SOURCE)
+#   warning STM32_I2C_INIT: Peripheral clock is HSI and it must be 16mHz or the speed/timing calculations need to be redone.
+    return NULL;
+#endif
+
+  /* Get I2C private structure */
+
+  switch (port)
+    {
+#ifdef CONFIG_STM32_I2C1
+      case 1:
+        priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv;
+        break;
+#endif
+#ifdef CONFIG_STM32_I2C2
+      case 2:
+        priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv;
+        break;
+#endif
+#ifdef CONFIG_STM32_I2C3
+      case 3:
+        priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv;
+        break;
+#endif
+#ifdef CONFIG_STM32_I2C4
+      case 4:
+        priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv;
+        break;
+#endif
+      default:
+        return NULL;
+    }
+
+  /* Allocate instance */
+
+  if (!(inst = kmm_malloc(sizeof(struct stm32_i2c_inst_s))))
+    {
+      return NULL;
+    }
+
+  /* Initialize instance */
+
+  inst->ops       = &stm32_i2c_ops;
+  inst->priv      = priv;
+
+  /* Init private data for the first time, increment refs count,
+   * power-up hardware and configure GPIOs.
+   */
+
+  irqs = enter_critical_section();
+
+  if ((volatile int)priv->refs++ == 0)
+    {
+      stm32_i2c_sem_init((struct i2c_master_s *)inst);
+      stm32_i2c_init(priv);
+
+#ifdef CONFIG_PM
+      /* Register to receive power management callbacks */
+
+      ret = pm_register(&priv->pm_cb);
+      DEBUGASSERT(ret == OK);
+      UNUSED(ret);
+#endif
+    }
+
+  leave_critical_section(irqs);
+  return (struct i2c_master_s *)inst;
+}
+
+/************************************************************************************
+ * Name: stm32_i2cbus_uninitialize
+ *
+ * Description:
+ *   Uninitialize an I2C bus
+ *
+ ************************************************************************************/
+
+int stm32_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
+{
+  irqstate_t irqs;
+
+  DEBUGASSERT(dev);
+
+  /* Decrement refs and check for underflow */
+
+  if (((struct stm32_i2c_inst_s *)dev)->priv->refs == 0)
+    {
+      return ERROR;
+    }
+
+  irqs = enter_critical_section();
+
+  if (--((struct stm32_i2c_inst_s *)dev)->priv->refs)
+    {
+      leave_critical_section(irqs);
+      kmm_free(dev);
+      return OK;
+    }
+
+  leave_critical_section(irqs);
+
+#ifdef CONFIG_PM
+  /* Unregister power management callbacks */
+
+  pm_unregister(&((struct stm32_i2c_inst_s *)dev)->priv->pm_cb);
+#endif
+
+  /* Disable power and other HW resource (GPIO's) */
+
+  stm32_i2c_deinit(((struct stm32_i2c_inst_s *)dev)->priv);
+
+  /* Release unused resources */
+
+  stm32_i2c_sem_destroy((struct i2c_master_s *)dev);
+
+  kmm_free(dev);
+  return OK;
+}
+
+#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \
+          CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */
diff --git a/arch/arm/src/stm32/stm32_i2s.c b/arch/arm/src/stm32/stm32_i2s.c
index 1b26a5545a2..a99b8927a34 100644
--- a/arch/arm/src/stm32/stm32_i2s.c
+++ b/arch/arm/src/stm32/stm32_i2s.c
@@ -1785,7 +1785,7 @@ static uint32_t stm32_i2s_rxsamplerate(struct i2s_dev_s *dev, uint32_t rate)
 {
 #if defined(I2S_HAVE_RX) && defined(I2S_HAVE_MCK)
   struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev;
-  DEBUGASSERT(priv && priv->samplerate > 0 && rate > 0);
+  DEBUGASSERT(priv && priv->samplerate >= 0 && rate > 0);
 
   /* Check if the receiver is driven by the MCK */
 
@@ -1985,7 +1985,7 @@ static uint32_t stm32_i2s_txsamplerate(struct i2s_dev_s *dev, uint32_t rate)
 #if defined(I2S_HAVE_TX) && defined(I2S_HAVE_MCK)
   struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev;
 
-  DEBUGASSERT(priv && priv->samplerate > 0 && rate > 0);
+  DEBUGASSERT(priv && priv->samplerate >= 0 && rate > 0);
 
   /* Check if the receiver is driven by the MCK/2 */
 
@@ -2182,7 +2182,7 @@ static uint32_t i2s_mckdivider(struct stm32_i2s_s *priv)
 
   uint16_t pllr = 5, plln = 256, div = 12, odd = 1;
 
-  DEBUGASSERT(priv && priv->samplerate > 0 && priv->datalen > 0);
+  DEBUGASSERT(priv && priv->samplerate >= 0 && priv->datalen > 0);
 
   /* A zero sample rate means to disable the MCK/2 clock */
 
diff --git a/arch/arm/src/stm32/stm32_i2s.h b/arch/arm/src/stm32/stm32_i2s.h
index 734e4af5af3..cdc346848cb 100644
--- a/arch/arm/src/stm32/stm32_i2s.h
+++ b/arch/arm/src/stm32/stm32_i2s.h
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_i2s.h"
+#include "hardware/stm32_i2s.h"
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/src/stm32/stm32_iwdg.c b/arch/arm/src/stm32/stm32_iwdg.c
index 2ceaf9bd4bb..903c0372d0c 100644
--- a/arch/arm/src/stm32/stm32_iwdg.c
+++ b/arch/arm/src/stm32/stm32_iwdg.c
@@ -51,7 +51,7 @@
 
 #include "up_arch.h"
 #include "stm32_rcc.h"
-#include "chip/stm32_dbgmcu.h"
+#include "hardware/stm32_dbgmcu.h"
 #include "stm32_wdg.h"
 
 #if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG)
diff --git a/arch/arm/src/stm32/stm32_ltdc.c b/arch/arm/src/stm32/stm32_ltdc.c
index bc710753cef..280f5a0e0ea 100644
--- a/arch/arm/src/stm32/stm32_ltdc.c
+++ b/arch/arm/src/stm32/stm32_ltdc.c
@@ -58,8 +58,8 @@
 #include "up_arch.h"
 #include "up_internal.h"
 #include "stm32.h"
-#include "chip/stm32_ltdc.h"
-#include "chip/stm32_dma2d.h"
+#include "hardware/stm32_ltdc.h"
+#include "hardware/stm32_dma2d.h"
 #include "stm32_ltdc.h"
 #include "stm32_dma2d.h"
 
diff --git a/arch/arm/src/stm32/stm32_opamp.h b/arch/arm/src/stm32/stm32_opamp.h
index 94af6990f9c..907ddbd5999 100644
--- a/arch/arm/src/stm32/stm32_opamp.h
+++ b/arch/arm/src/stm32/stm32_opamp.h
@@ -49,7 +49,7 @@
 #if defined(CONFIG_STM32_STM32F30XX)
 #  error "OPAMP support for STM32F30XX not implemented yet"
 #elif defined(CONFIG_STM32_STM32F33XX)
-#  include "chip/stm32f33xxx_opamp.h"
+#  include "hardware/stm32f33xxx_opamp.h"
 #endif
 
 #include 
diff --git a/arch/arm/src/stm32/stm32_otgfs.h b/arch/arm/src/stm32/stm32_otgfs.h
index 4860e7d004a..69f35ba370f 100644
--- a/arch/arm/src/stm32/stm32_otgfs.h
+++ b/arch/arm/src/stm32/stm32_otgfs.h
@@ -46,7 +46,7 @@
 
 #include "stm32.h"
 
-#include "chip/stm32fxxxxx_otgfs.h"
+#include "hardware/stm32fxxxxx_otgfs.h"
 
 #if defined(CONFIG_STM32_OTGFS)
 
diff --git a/arch/arm/src/stm32/stm32_otghs.h b/arch/arm/src/stm32/stm32_otghs.h
index d077bc25795..e6c4dd47441 100644
--- a/arch/arm/src/stm32/stm32_otghs.h
+++ b/arch/arm/src/stm32/stm32_otghs.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "stm32.h"
-#include "chip/stm32_otghs.h"
+#include "hardware/stm32_otghs.h"
 
 #if defined(CONFIG_STM32_OTGHS)
 
diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c
index 9761653c6d6..9d9a1abbe67 100644
--- a/arch/arm/src/stm32/stm32_pwm.c
+++ b/arch/arm/src/stm32/stm32_pwm.c
@@ -111,9 +111,9 @@
 #define TIMTYPE_TIM12      TIMTYPE_COUNTUP16
 #define TIMTYPE_TIM13      TIMTYPE_COUNTUP16
 #define TIMTYPE_TIM14      TIMTYPE_COUNTUP16
-#define TIMTYPE_TIM15      TIMTYPE_COUNTUP16_N
-#define TIMTYPE_TIM16      TIMTYPE_COUNTUP16_N
-#define TIMTYPE_TIM17      TIMTYPE_COUNTUP16_N
+#define TIMTYPE_TIM15      TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */
+#define TIMTYPE_TIM16      TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */
+#define TIMTYPE_TIM17      TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */
 
 /* Timer clock source, RCC EN offset, enable bit,
  * RCC RST offset, reset bit to use
@@ -369,7 +369,7 @@ struct stm32_pwm_break_s
 struct stm32_pwmchan_s
 {
   uint8_t                  channel:4;   /* Timer output channel: {1,..4} */
-  uint8_t                  mode:4;      /* PWM channel mode (see stm32_chan_mode_e) */
+  uint8_t                  mode:4;      /* PWM channel mode (see stm32_pwm_chanmode_e) */
   struct stm32_pwm_out_s   out1;        /* PWM output configuration */
 #ifdef HAVE_BREAK
   struct stm32_pwm_break_s brk;         /* PWM break configuration */
@@ -442,7 +442,7 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg);
 
 static int pwm_frequency_update(FAR struct pwm_lowerhalf_s *dev,
                                 uint32_t frequency);
-static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv,
+static int pwm_mode_configure(FAR struct pwm_lowerhalf_s *dev,
                               uint8_t channel, uint32_t mode);
 static int pwm_timer_configure(FAR struct stm32_pwmtimer_s *priv);
 static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
@@ -537,6 +537,7 @@ static const struct stm32_pwm_ops_s g_llpwmops =
   .configure       = pwm_configure,
   .soft_break      = pwm_soft_break,
   .ccr_update      = pwm_ccr_update,
+  .mode_update     = pwm_mode_configure,
   .ccr_get         = pwm_ccr_get,
   .arr_update      = pwm_arr_update,
   .arr_get         = pwm_arr_get,
@@ -673,7 +674,7 @@ static struct stm32_pwmchan_s g_pwm1channels[] =
       .pincfg  = 0,    /* No available externaly */
     }
 #endif
-  }
+  },
 #endif
 #ifdef CONFIG_STM32_TIM1_CHANNEL6
   {
@@ -1233,7 +1234,7 @@ static struct stm32_pwmchan_s g_pwm8channels[] =
       .pincfg  = 0,    /* No available externaly */
     }
 #endif
-  }
+  },
 #endif
 #ifdef CONFIG_STM32_TIM8_CHANNEL6
   {
@@ -2119,38 +2120,38 @@ static int pwm_ccr_update(FAR struct pwm_lowerhalf_s *dev, uint8_t index,
 
   switch (index)
     {
-      case 1:
+      case STM32_PWM_CHAN1:
         {
           offset = STM32_GTIM_CCR1_OFFSET;
           break;
         }
 
-      case 2:
+      case STM32_PWM_CHAN2:
         {
           offset = STM32_GTIM_CCR2_OFFSET;
           break;
         }
 
-      case 3:
+      case STM32_PWM_CHAN3:
         {
           offset = STM32_GTIM_CCR3_OFFSET;
           break;
         }
 
-      case 4:
+      case STM32_PWM_CHAN4:
         {
           offset = STM32_GTIM_CCR4_OFFSET;
           break;
         }
 
 #ifdef HAVE_IP_TIMERS_V2
-      case 5:
+      case STM32_PWM_CHAN5:
         {
           offset = STM32_ATIM_CCR5_OFFSET;
           break;
         }
 
-      case 6:
+      case STM32_PWM_CHAN6:
         {
           offset = STM32_ATIM_CCR6_OFFSET;
           break;
@@ -2183,38 +2184,38 @@ static uint32_t pwm_ccr_get(FAR struct pwm_lowerhalf_s *dev, uint8_t index)
 
   switch (index)
     {
-      case 1:
+      case STM32_PWM_CHAN1:
         {
           offset = STM32_GTIM_CCR1_OFFSET;
           break;
         }
 
-      case 2:
+      case STM32_PWM_CHAN2:
         {
           offset = STM32_GTIM_CCR2_OFFSET;
           break;
         }
 
-      case 3:
+      case STM32_PWM_CHAN3:
         {
           offset = STM32_GTIM_CCR3_OFFSET;
           break;
         }
 
-      case 4:
+      case STM32_PWM_CHAN4:
         {
           offset = STM32_GTIM_CCR4_OFFSET;
           break;
         }
 
 #ifdef HAVE_IP_TIMERS_V2
-      case 5:
+      case STM32_PWM_CHAN5:
         {
           offset = STM32_ATIM_CCR5_OFFSET;
           break;
         }
 
-      case 6:
+      case STM32_PWM_CHAN6:
         {
           offset = STM32_ATIM_CCR6_OFFSET;
           break;
@@ -2533,18 +2534,16 @@ errout:
  *
  ****************************************************************************/
 
-static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv,
+static int pwm_mode_configure(FAR struct pwm_lowerhalf_s *dev,
                               uint8_t channel, uint32_t mode)
 {
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
   uint32_t chanmode = 0;
-  uint32_t ocmode1  = 0;
-  uint32_t ocmode2  = 0;
-  uint32_t ccmr1    = 0;
-  uint32_t ccmr2    = 0;
+  uint32_t ocmode   = 0;
+  uint32_t ccmr     = 0;
+  uint32_t offset   = 0;
   int      ret      = OK;
 #ifdef HAVE_IP_TIMERS_V2
-  uint32_t ccmr3    = 0;
-  uint32_t ocmode3  = 0;
   bool     ocmbit   = false;
 #endif
 
@@ -2565,6 +2564,42 @@ static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv,
 
   switch (mode)
     {
+      case STM32_CHANMODE_FRZN:
+        {
+          chanmode = GTIM_CCMR_MODE_FRZN;
+          break;
+        }
+
+      case STM32_CHANMODE_CHACT:
+        {
+          chanmode = GTIM_CCMR_MODE_CHACT;
+          break;
+        }
+
+      case STM32_CHANMODE_CHINACT:
+        {
+          chanmode = GTIM_CCMR_MODE_CHINACT;
+          break;
+        }
+
+      case STM32_CHANMODE_OCREFTOG:
+        {
+          chanmode = GTIM_CCMR_MODE_OCREFTOG;
+          break;
+        }
+
+      case STM32_CHANMODE_OCREFLO:
+        {
+          chanmode = GTIM_CCMR_MODE_OCREFLO;
+          break;
+        }
+
+      case STM32_CHANMODE_OCREFHI:
+        {
+          chanmode = GTIM_CCMR_MODE_OCREFHI;
+          break;
+        }
+
       case STM32_CHANMODE_PWM1:
         {
           chanmode = ATIM_CCMR_MODE_PWM1;
@@ -2615,207 +2650,29 @@ static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv,
         }
     }
 
-  /* Get current registers */
-
-  ccmr1 = pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET);
-  ccmr2 = pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET);
-#ifdef HAVE_IP_TIMERS_V2
-  if (priv->timtype == TIMTYPE_ADVANCED)
-    {
-      ccmr3 = pwm_getreg(priv, STM32_ATIM_CCMR3_OFFSET);
-    }
-#endif
+  /* Get CCMR offset */
 
   switch (channel)
     {
-      case 1: /* PWM Mode configuration: Channel 1 */
+      case STM32_PWM_CHAN1:
+      case STM32_PWM_CHAN2:
         {
-          /* Reset current channel 1 mode configuration */
-
-          ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK |
-                     ATIM_CCMR1_OC1PE);
-
-          /* Configure CC1 as output */
-
-          ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT);
-
-          /* Configure Compare 1 mode */
-
-          ocmode1 |= (chanmode << ATIM_CCMR1_OC1M_SHIFT);
-
-          /* Enable CCR2 preload */
-
-          ocmode1 |= ATIM_CCMR1_OC1PE;
-
-#ifdef HAVE_IP_TIMERS_V2
-          /* Reset current OC bit */
-
-          ccmr1 &= ~(ATIM_CCMR1_OC1M);
-
-          /* Set an additional OC1M bit */
-
-          if (ocmbit)
-            {
-              ocmode1 |= ATIM_CCMR1_OC1M;
-            }
-#endif
+          offset = STM32_GTIM_CCMR1_OFFSET;
           break;
         }
 
-      case 2: /* PWM Mode configuration: Channel 2 */
+      case STM32_PWM_CHAN3:
+      case STM32_PWM_CHAN4:
         {
-          /* Reset current channel 2 mode configuration */
-
-          ccmr1 &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK |
-                     ATIM_CCMR1_OC2PE);
-
-          /* Configure CC2 as output */
-
-          ocmode1 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT);
-
-          /* Configure Compare 2 mode */
-
-          ocmode1 |= (chanmode << ATIM_CCMR1_OC2M_SHIFT);
-
-          /* Enable CCR2 preload */
-
-          ocmode1 |= ATIM_CCMR1_OC2PE;
-
-#ifdef HAVE_IP_TIMERS_V2
-          /* Reset current OC bit */
-
-          ccmr1 &= ~(ATIM_CCMR1_OC2M);
-
-          /* Set an additional OC2M bit */
-
-          if (ocmbit)
-            {
-              ocmode1 |= ATIM_CCMR1_OC2M;
-            }
-#endif
-          break;
-        }
-
-      case 3: /* PWM Mode configuration: Channel 3 */
-        {
-          /* Reset current channel 3 mode configuration */
-
-          ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK |
-                     ATIM_CCMR2_OC3PE);
-
-          /* Configure CC3 as output */
-
-          ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT);
-
-          /* Configure Compare 3 mode */
-
-          ocmode2 |= (chanmode << ATIM_CCMR2_OC3M_SHIFT);
-
-          /* Enable CCR3 preload */
-
-          ocmode2 |= ATIM_CCMR2_OC3PE;
-
-#ifdef HAVE_IP_TIMERS_V2
-          /* Reset current OC bit */
-
-          ccmr2 &= ~(ATIM_CCMR2_OC3M);
-
-          /* Set an additional OC3M bit */
-
-          if (ocmbit)
-            {
-              ocmode2 |= ATIM_CCMR2_OC3M;
-            }
-#endif
-          break;
-        }
-
-      case 4: /* PWM Mode configuration: Channel 4 */
-        {
-          /* Reset current channel 4 mode configuration */
-
-          ccmr2 &= ~(ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK |
-                     ATIM_CCMR2_OC4PE);
-
-          /* Configure Compare 4 mode */
-
-          ocmode2 |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT);
-
-          /* Enable CCR4 preload */
-
-          ocmode2 |= (chanmode << ATIM_CCMR2_OC4M_SHIFT);
-
-          /* Enable CCR4 preload */
-
-          ocmode2 |= ATIM_CCMR2_OC4PE;
-
-#ifdef HAVE_IP_TIMERS_V2
-          /* Reset current OC bit */
-
-          ccmr2 &= ~(ATIM_CCMR2_OC4M);
-
-          /* Set an additional OC4M bit */
-
-          if (ocmbit)
-            {
-              ocmode2 |= ATIM_CCMR2_OC4M;
-            }
-#endif
+          offset = STM32_GTIM_CCMR2_OFFSET;
           break;
         }
 
 #ifdef HAVE_IP_TIMERS_V2
-      case 5: /* PWM Mode configuration: Channel 5 */
+      case STM32_PWM_CHAN5:
+      case STM32_PWM_CHAN6:
         {
-          /* Reset current channel 5 mode configuration */
-
-          ccmr3 &= ~(ATIM_CCMR3_OC5M_MASK | ATIM_CCMR3_OC5PE);
-
-          /* Enable CCR5 preload */
-
-          ocmode3 |= (chanmode << ATIM_CCMR3_OC5M_SHIFT);
-
-          /* Enable CCR5 preload */
-
-          ocmode3 |= ATIM_CCMR3_OC5PE;
-
-          /* Reset current OC bit */
-
-          ccmr3 &= ~(ATIM_CCMR3_OC5M);
-
-          /* Set an additional OC5M bit */
-
-          if (ocmbit)
-            {
-              ocmode3 |= ATIM_CCMR3_OC5M;
-            }
-          break;
-        }
-
-      case 6: /* PWM Mode configuration: Channel 6 */
-        {
-          /* Reset current channel 6 mode configuration */
-
-          ccmr3 &= ~(ATIM_CCMR3_OC6M_MASK | ATIM_CCMR3_OC6PE);
-
-          /* Enable CCR6 preload */
-
-          ocmode3 |= (chanmode << ATIM_CCMR3_OC6M_SHIFT);
-
-          /* Enable CCR6 preload */
-
-          ocmode3 |= ATIM_CCMR3_OC6PE;
-
-          /* Reset current OC bit */
-
-          ccmr3 &= ~(ATIM_CCMR3_OC6M);
-
-          /* Set an additional OC6M bit */
-
-          if (ocmbit)
-            {
-              ocmode3 |= ATIM_CCMR3_OC6M;
-            }
+          offset = STM32_ATIM_CCMR3_OFFSET;
           break;
         }
 #endif
@@ -2828,22 +2685,104 @@ static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv,
         }
     }
 
+  /* Get current registers */
+
+  ccmr = pwm_getreg(priv, offset);
+
+  /* PWM mode configuration.
+   * NOTE: The CCMRx registers are identical if the channels are outputs.
+   */
+
+  switch (channel)
+    {
+      /* Configure channel 1/3/5 */
+
+      case STM32_PWM_CHAN1:
+      case STM32_PWM_CHAN3:
+#ifdef HAVE_IP_TIMERS_V2
+      case STM32_PWM_CHAN5:
+#endif
+        {
+          /* Reset current channel 1/3/5 mode configuration */
+
+          ccmr &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK |
+                     ATIM_CCMR1_OC1PE);
+
+          /* Configure CC1/3/5 as output */
+
+          ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT);
+
+          /* Configure Compare 1/3/5 mode */
+
+          ocmode |= (chanmode << ATIM_CCMR1_OC1M_SHIFT);
+
+          /* Enable CCR1/3/5 preload */
+
+          ocmode |= ATIM_CCMR1_OC1PE;
+
+#ifdef HAVE_IP_TIMERS_V2
+          /* Reset current OC bit */
+
+          ccmr &= ~(ATIM_CCMR1_OC1M);
+
+          /* Set an additional OC1/3/5M bit */
+
+          if (ocmbit)
+            {
+              ocmode |= ATIM_CCMR1_OC1M;
+            }
+#endif
+          break;
+        }
+
+      /* Configure channel 2/4/6 */
+
+      case STM32_PWM_CHAN2:
+      case STM32_PWM_CHAN4:
+#ifdef HAVE_IP_TIMERS_V2
+      case STM32_PWM_CHAN6:
+#endif
+        {
+          /* Reset current channel 2/4/6 mode configuration */
+
+          ccmr &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK |
+                     ATIM_CCMR1_OC2PE);
+
+          /* Configure CC2/4/6 as output */
+
+          ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT);
+
+          /* Configure Compare 2/4/6 mode */
+
+          ocmode |= (chanmode << ATIM_CCMR1_OC2M_SHIFT);
+
+          /* Enable CCR2/4/6 preload */
+
+          ocmode |= ATIM_CCMR1_OC2PE;
+
+#ifdef HAVE_IP_TIMERS_V2
+          /* Reset current OC bit */
+
+          ccmr &= ~(ATIM_CCMR1_OC2M);
+
+          /* Set an additioneal OC2/4/6M bit */
+
+          if (ocmbit)
+            {
+              ocmode |= ATIM_CCMR1_OC2M;
+            }
+#endif
+          break;
+        }
+    }
+
   /* Set the selected output compare mode */
 
-  ccmr1 |= ocmode1;
-  ccmr2 |= ocmode2;
+  ccmr |= ocmode;
 
   /* Write CCMRx registers */
 
-  pwm_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1);
-  pwm_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2);
-#ifdef HAVE_IP_TIMERS_V2
-  if (priv->timtype == TIMTYPE_ADVANCED)
-    {
-      ccmr3 |= ocmode3;
-      pwm_putreg(priv, STM32_ATIM_CCMR3_OFFSET, ccmr3);
-    }
-#endif
+  pwm_putreg(priv, offset, ccmr);
 
 errout:
   return ret;
@@ -2985,19 +2924,19 @@ static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev,
 
   /* Get outputs configuration */
 
-  regval |= ((outputs & STM32_CHAN1)  ? ATIM_CCER_CC1E  : 0);
-  regval |= ((outputs & STM32_CHAN1N) ? ATIM_CCER_CC1NE : 0);
-  regval |= ((outputs & STM32_CHAN2)  ? ATIM_CCER_CC2E  : 0);
-  regval |= ((outputs & STM32_CHAN2N) ? ATIM_CCER_CC2NE : 0);
-  regval |= ((outputs & STM32_CHAN3)  ? ATIM_CCER_CC3E  : 0);
-  regval |= ((outputs & STM32_CHAN3N) ? ATIM_CCER_CC3NE : 0);
-  regval |= ((outputs & STM32_CHAN4)  ? ATIM_CCER_CC4E  : 0);
+  regval |= ((outputs & STM32_PWM_OUT1)  ? ATIM_CCER_CC1E  : 0);
+  regval |= ((outputs & STM32_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0);
+  regval |= ((outputs & STM32_PWM_OUT2)  ? ATIM_CCER_CC2E  : 0);
+  regval |= ((outputs & STM32_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0);
+  regval |= ((outputs & STM32_PWM_OUT3)  ? ATIM_CCER_CC3E  : 0);
+  regval |= ((outputs & STM32_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0);
+  regval |= ((outputs & STM32_PWM_OUT4)  ? ATIM_CCER_CC4E  : 0);
 
   /* NOTE: CC4N does not exist, but some docs show configuration bits for it */
 
 #ifdef HAVE_IP_TIMERS_V2
-  regval |= ((outputs & STM32_CHAN5)  ? ATIM_CCER_CC5E  : 0);
-  regval |= ((outputs & STM32_CHAN6)  ? ATIM_CCER_CC6E  : 0);
+  regval |= ((outputs & STM32_PWM_OUT5)  ? ATIM_CCER_CC5E  : 0);
+  regval |= ((outputs & STM32_PWM_OUT6)  ? ATIM_CCER_CC6E  : 0);
 #endif
 
   if (state == true)
@@ -3170,7 +3109,7 @@ static uint16_t pwm_outputs_from_channels(FAR struct stm32_pwmtimer_s *priv)
 
           if (priv->channels[i].out1.in_use == 1)
             {
-              outputs |= (STM32_CHAN1 << ((channel-1)*2));
+              outputs |= (STM32_PWM_OUT1 << ((channel-1)*2));
             }
 
 #ifdef HAVE_PWM_COMPLEMENTARY
@@ -3178,7 +3117,7 @@ static uint16_t pwm_outputs_from_channels(FAR struct stm32_pwmtimer_s *priv)
 
           if (priv->channels[i].out2.in_use == 1)
             {
-              outputs |= (STM32_CHAN1N << ((channel-1)*2));
+              outputs |= (STM32_PWM_OUT1N << ((channel-1)*2));
             }
 #endif
         }
@@ -3261,7 +3200,7 @@ static int pwm_break_dt_configure(FAR struct stm32_pwmtimer_s *priv)
 
   /* Configure lock */
 
-  bdtr |= priv->lock << GTIM_BDTR_LOCK_SHIFT;
+  bdtr |= priv->lock << ATIM_BDTR_LOCK_SHIFT;
 
   /* Write BDTR register at once */
 
@@ -3352,7 +3291,7 @@ static int pwm_pulsecount_configure(FAR struct pwm_lowerhalf_s *dev)
         {
           /* Update PWM mode */
 
-          pwm_mode_configure(priv, priv->channels[j].channel,
+          pwm_mode_configure(dev, priv->channels[j].channel,
                              priv->channels[j].mode);
 
           /* PWM outputs configuration */
@@ -3597,7 +3536,7 @@ static int pwm_configure(FAR struct pwm_lowerhalf_s *dev)
         {
           /* Update PWM mode */
 
-          ret = pwm_mode_configure(priv, priv->channels[j].channel,
+          ret = pwm_mode_configure(dev, priv->channels[j].channel,
                                    priv->channels[j].mode);
           if (ret < 0)
             {
@@ -3946,7 +3885,7 @@ static uint8_t pwm_pulsecount(uint32_t count)
    * just return the count.
    */
 
-  if (count <= GTIM_RCR_REP_MAX)
+  if (count <= ATIM_RCR_REP_MAX)
     {
       return (uint8_t)count;
     }
@@ -3958,16 +3897,16 @@ static uint8_t pwm_pulsecount(uint32_t count)
    * and 128.
    */
 
-  else if (count < (3 * GTIM_RCR_REP_MAX / 2))
+  else if (count < (3 * ATIM_RCR_REP_MAX / 2))
     {
-      return (uint8_t)((GTIM_RCR_REP_MAX + 1) >> 1);
+      return (uint8_t)((ATIM_RCR_REP_MAX + 1) >> 1);
     }
 
   /* Otherwise, return the maximum.  The final count will be 64 or more */
 
   else
     {
-      return (uint8_t)GTIM_RCR_REP_MAX;
+      return (uint8_t)ATIM_RCR_REP_MAX;
     }
 }
 #endif  /* HAVE_PWM_INTERRUPT */
diff --git a/arch/arm/src/stm32/stm32_pwm.h b/arch/arm/src/stm32/stm32_pwm.h
index 30add559613..c12e95f1385 100644
--- a/arch/arm/src/stm32/stm32_pwm.h
+++ b/arch/arm/src/stm32/stm32_pwm.h
@@ -121,13 +121,11 @@
 #ifdef CONFIG_STM32_PWM
 
 #include 
-#include "chip/stm32_tim.h"
+#include "hardware/stm32_tim.h"
 
-/* Configuration needed by upper-half PWM driver */
+/* PWM driver channels configuration */
 
-#ifdef CONFIG_PWM
-
-#ifdef CONFIG_PWM_MULTICHAN
+#ifdef CONFIG_STM32_PWM_MULTICHAN
 
 #ifdef CONFIG_STM32_TIM1_CHANNEL1
 #  define PWM_TIM1_CHANNEL1 1
@@ -149,8 +147,19 @@
 #else
 #  define PWM_TIM1_CHANNEL4 0
 #endif
+#ifdef CONFIG_STM32_TIM1_CHANNEL5
+#  define PWM_TIM1_CHANNEL5 1
+#else
+#  define PWM_TIM1_CHANNEL5 0
+#endif
+#ifdef CONFIG_STM32_TIM1_CHANNEL6
+#  define PWM_TIM1_CHANNEL6 1
+#else
+#  define PWM_TIM1_CHANNEL6 0
+#endif
 #define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \
-                            PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4)
+                            PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \
+                            PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6)
 
 #ifdef CONFIG_STM32_TIM2_CHANNEL1
 #  define PWM_TIM2_CHANNEL1 1
@@ -264,8 +273,19 @@
 #else
 #  define PWM_TIM8_CHANNEL4 0
 #endif
+#ifdef CONFIG_STM32_TIM8_CHANNEL5
+#  define PWM_TIM8_CHANNEL5 1
+#else
+#  define PWM_TIM8_CHANNEL5 0
+#endif
+#ifdef CONFIG_STM32_TIM8_CHANNEL6
+#  define PWM_TIM8_CHANNEL6 1
+#else
+#  define PWM_TIM8_CHANNEL6 0
+#endif
 #define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \
-                            PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4)
+                            PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \
+                            PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6)
 
 #ifdef CONFIG_STM32_TIM9_CHANNEL1
 #  define PWM_TIM9_CHANNEL1 1
@@ -603,9 +623,7 @@
 #  define PWM_TIM17_NCHANNELS 1
 #endif
 
-#endif /* CONFIG_PWM_MULTICHAN */
-
-#endif /* CONFIG_PWM */
+#endif /* CONFIG_STM32_PWM_MULTICHAN */
 
 #ifdef CONFIG_STM32_TIM1_CH1OUT
 #  define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
@@ -876,6 +894,8 @@
 
 /* Low-level ops helpers ************************************************************/
 
+#ifdef CONFIG_STM32_PWM_LL_OPS
+
 /* NOTE: low-level ops accept pwm_lowerhalf_s as first argument, but llops access
  *       can be found in stm32_pwm_dev_s
  */
@@ -886,6 +906,8 @@
         (dev)->ops->shutdown((FAR struct pwm_lowerhalf_s *)dev)
 #define PWM_CCR_UPDATE(dev, index, ccr)                                            \
         (dev)->llops->ccr_update((FAR struct pwm_lowerhalf_s *)dev, index, ccr)
+#define PWM_MODE_UPDATE(dev, index, mode)                                          \
+        (dev)->llops->mode_update((FAR struct pwm_lowerhalf_s *)dev, index, mode)
 #define PWM_CCR_GET(dev, index)                                                    \
         (dev)->llops->ccr_get((FAR struct pwm_lowerhalf_s *)dev, index)
 #define PWM_ARR_UPDATE(dev, arr)                                                   \
@@ -913,6 +935,8 @@
 #define PWM_DT_UPDATE(dev, dt)                                                     \
         (dev)->llops->dt_update((FAR struct pwm_lowerhalf_s *)dev, dt)
 
+#endif
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/
@@ -946,37 +970,57 @@ enum stm32_pwm_idle_e
 
 /* PWM channel mode */
 
-enum stm32_chan_mode_e
+enum stm32_pwm_chanmode_e
 {
-  STM32_CHANMODE_PWM1        = 0,
-  STM32_CHANMODE_PWM2        = 1,
+  STM32_CHANMODE_FRZN        = 0,  /* CCRx matches has no effects on outputs */
+  STM32_CHANMODE_CHACT       = 1,  /* OCxREF active on match */
+  STM32_CHANMODE_CHINACT     = 2,  /* OCxREF inactive on match */
+  STM32_CHANMODE_OCREFTOG    = 3,  /* OCxREF toggles when TIMy_CNT=TIMyCCRx */
+  STM32_CHANMODE_OCREFLO     = 4,  /* OCxREF is forced low */
+  STM32_CHANMODE_OCREFHI     = 5,  /* OCxREF is forced high */
+  STM32_CHANMODE_PWM1        = 6,  /* PWM mode 1 */
+  STM32_CHANMODE_PWM2        = 7,  /* PWM mode 2 */
 #ifdef HAVE_IP_TIMERS_V2
-  STM32_CHANMODE_COMBINED1   = 2,
-  STM32_CHANMODE_COMBINED2   = 3,
-  STM32_CHANMODE_ASYMMETRIC1 = 4,
-  STM32_CHANMODE_ASYMMETRIC2 = 5
+  STM32_CHANMODE_COMBINED1   = 8,  /* Combined PWM mode 1 */
+  STM32_CHANMODE_COMBINED2   = 9,  /* Combined PWM mode 2 */
+  STM32_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */
+  STM32_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */
 #endif
 };
 
-/* Timer channel */
+/* PWM timer channel */
 
-enum stm32_chan_e
+enum stm32_pwm_chan_e
 {
-  STM32_CHAN1  = (1 << 0),
-  STM32_CHAN1N = (1 << 1),
-  STM32_CHAN2  = (1 << 2),
-  STM32_CHAN2N = (1 << 3),
-  STM32_CHAN3  = (1 << 4),
-  STM32_CHAN3N = (1 << 5),
-  STM32_CHAN4  = (1 << 6),
-  /* No complementary output for CH4 */
+  STM32_PWM_CHAN1  = 1,
+  STM32_PWM_CHAN2  = 2,
+  STM32_PWM_CHAN3  = 3,
+  STM32_PWM_CHAN4  = 4,
+#ifdef HAVE_IP_TIMERS_V2
+  STM32_PWM_CHAN5  = 5,
+  STM32_PWM_CHAN6  = 6,
+#endif
+};
+
+/* PWM timer channel output */
+
+enum stm32_pwm_output_e
+{
+  STM32_PWM_OUT1  = (1 << 0),
+  STM32_PWM_OUT1N = (1 << 1),
+  STM32_PWM_OUT2  = (1 << 2),
+  STM32_PWM_OUT2N = (1 << 3),
+  STM32_PWM_OUT3  = (1 << 4),
+  STM32_PWM_OUT3N = (1 << 5),
+  STM32_PWM_OUT4  = (1 << 6),
+  /* 1 << 7 reserved - no complementary output for CH4 */
 #ifdef HAVE_IP_TIMERS_V2
   /* Only available inside micro */
 
-  STM32_CHAN5  = (1 << 7),
-  /* 1<<8 reserved */
-  STM32_CHAN6  = (1 << 9),
-  /* 1<<10 reserved */
+  STM32_PWM_OUT5  = (1 << 8),
+  /* 1 << 9 reserved - no complementary output for CH5 */
+  STM32_PWM_OUT6  = (1 << 10),
+  /* 1 << 11 reserved - no complementary output for CH6 */
 #endif
 };
 
@@ -1010,6 +1054,10 @@ struct stm32_pwm_ops_s
 
   int (*ccr_update)(FAR struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t ccr);
 
+  /* Update PWM mode */
+
+  int (*mode_update)(FAR struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t mode);
+
   /* Get CCR register */
 
   uint32_t (*ccr_get)(FAR struct pwm_lowerhalf_s *dev, uint8_t index);
diff --git a/arch/arm/src/stm32/stm32_pwr.h b/arch/arm/src/stm32/stm32_pwr.h
index ee56a40d18e..58a9c544a10 100644
--- a/arch/arm/src/stm32/stm32_pwr.h
+++ b/arch/arm/src/stm32/stm32_pwr.h
@@ -46,7 +46,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_pwr.h"
+#include "hardware/stm32_pwr.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32/stm32_rcc.h b/arch/arm/src/stm32/stm32_rcc.h
index c31461650c6..1237f30f276 100644
--- a/arch/arm/src/stm32/stm32_rcc.h
+++ b/arch/arm/src/stm32/stm32_rcc.h
@@ -46,19 +46,19 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32_STM32L15XX)
-#  include "chip/stm32l15xxx_rcc.h"
+#  include "hardware/stm32l15xxx_rcc.h"
 #elif defined(CONFIG_STM32_STM32F10XX)
-#  include "chip/stm32f10xxx_rcc.h"
+#  include "hardware/stm32f10xxx_rcc.h"
 #elif defined(CONFIG_STM32_STM32F20XX)
-#  include "chip/stm32f20xxx_rcc.h"
+#  include "hardware/stm32f20xxx_rcc.h"
 #elif defined(CONFIG_STM32_STM32F30XX)
-#  include "chip/stm32f30xxx_rcc.h"
+#  include "hardware/stm32f30xxx_rcc.h"
 #elif defined(CONFIG_STM32_STM32F33XX)
-#  include "chip/stm32f33xxx_rcc.h"
+#  include "hardware/stm32f33xxx_rcc.h"
 #elif defined(CONFIG_STM32_STM32F37XX)
-#  include "chip/stm32f37xxx_rcc.h"
+#  include "hardware/stm32f37xxx_rcc.h"
 #elif defined(CONFIG_STM32_STM32F4XXX)
-#  include "chip/stm32f40xxx_rcc.h"
+#  include "hardware/stm32f40xxx_rcc.h"
 #endif
 
 /************************************************************************************
diff --git a/arch/arm/src/stm32/stm32_rng.c b/arch/arm/src/stm32/stm32_rng.c
index 15925563e8d..b3e1647c118 100644
--- a/arch/arm/src/stm32/stm32_rng.c
+++ b/arch/arm/src/stm32/stm32_rng.c
@@ -51,7 +51,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/stm32_rng.h"
+#include "hardware/stm32_rng.h"
 #include "up_internal.h"
 
 #if defined(CONFIG_STM32_RNG)
@@ -62,10 +62,10 @@
  ****************************************************************************/
 
 static int stm32_rng_initialize(void);
-static int stm32_interrupt(int irq, void *context, FAR void *arg);
-static void stm32_enable(void);
-static void stm32_disable(void);
-static ssize_t stm32_read(struct file *filep, char *buffer, size_t);
+static int stm32_rng_interrupt(int irq, void *context, FAR void *arg);
+static void stm32_rng_enable(void);
+static void stm32_rng_disable(void);
+static ssize_t stm32_rng_read(struct file *filep, char *buffer, size_t);
 
 /****************************************************************************
  * Private Types
@@ -89,17 +89,15 @@ static struct rng_dev_s g_rngdev;
 
 static const struct file_operations g_rngops =
 {
-  0,               /* open */
-  0,               /* close */
-  stm32_read,      /* read */
-  0,               /* write */
-  0,               /* seek */
-  0                /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0              /* poll */
-#endif
+  NULL,            /* open */
+  NULL,            /* close */
+  stm32_rng_read,  /* read */
+  NULL,            /* write */
+  NULL,            /* seek */
+  NULL,            /* ioctl */
+  NULL             /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
-  , 0              /* unlink */
+  , NULL           /* unlink */
 #endif
 };
 
@@ -121,7 +119,7 @@ static int stm32_rng_initialize(void)
 
   nxsem_init(&g_rngdev.rd_devsem, 0, 1);
 
-  if (irq_attach(STM32_IRQ_RNG, stm32_interrupt, NULL))
+  if (irq_attach(STM32_IRQ_RNG, stm32_rng_interrupt, NULL))
     {
       /* We could not attach the ISR to the interrupt */
 
@@ -142,10 +140,10 @@ static int stm32_rng_initialize(void)
 }
 
 /****************************************************************************
- * Name: stm32_enable
+ * Name: stm32_rng_enable
  ****************************************************************************/
 
-static void stm32_enable(void)
+static void stm32_rng_enable(void)
 {
   uint32_t regval;
 
@@ -157,10 +155,10 @@ static void stm32_enable(void)
 }
 
 /****************************************************************************
- * Name: stm32_disable
+ * Name: stm32_rng_disable
  ****************************************************************************/
 
-static void stm32_disable(void)
+static void stm32_rng_disable(void)
 {
   uint32_t regval;
   regval = getreg32(STM32_RNG_CR);
@@ -169,10 +167,10 @@ static void stm32_disable(void)
 }
 
 /****************************************************************************
- * Name: stm32_interrupt
+ * Name: stm32_rng_interrupt
  ****************************************************************************/
 
-static int stm32_interrupt(int irq, void *context, FAR void *arg)
+static int stm32_rng_interrupt(int irq, void *context, FAR void *arg)
 {
   uint32_t rngsr;
   uint32_t data;
@@ -233,7 +231,7 @@ static int stm32_interrupt(int irq, void *context, FAR void *arg)
     {
       /* Buffer filled, stop further interrupts. */
 
-      stm32_disable();
+      stm32_rng_disable();
       nxsem_post(&g_rngdev.rd_readsem);
     }
 
@@ -241,10 +239,10 @@ static int stm32_interrupt(int irq, void *context, FAR void *arg)
 }
 
 /****************************************************************************
- * Name: stm32_read
+ * Name: stm32_rng_read
  ****************************************************************************/
 
-static ssize_t stm32_read(struct file *filep, char *buffer, size_t buflen)
+static ssize_t stm32_rng_read(struct file *filep, char *buffer, size_t buflen)
 {
   int ret;
 
@@ -270,7 +268,7 @@ static ssize_t stm32_read(struct file *filep, char *buffer, size_t buflen)
 
   /* Enable RNG with interrupts */
 
-  stm32_enable();
+  stm32_rng_enable();
 
   /* Wait until the buffer is filled */
 
diff --git a/arch/arm/src/stm32/stm32_rtc.h b/arch/arm/src/stm32/stm32_rtc.h
index b1ad332258e..2a7b848f40e 100644
--- a/arch/arm/src/stm32/stm32_rtc.h
+++ b/arch/arm/src/stm32/stm32_rtc.h
@@ -51,8 +51,8 @@
  */
 
 #if defined(CONFIG_STM32_STM32F10XX)
-#  include "chip/stm32_rtc.h"
-#  include "chip/stm32_bkp.h"
+#  include "hardware/stm32_rtc.h"
+#  include "hardware/stm32_bkp.h"
 
 /* The other families use a more traditional Realtime Clock/Calendar (RTCC) with
  * broken-out data/time in BCD format.  The backup registers are integrated into
@@ -61,7 +61,7 @@
 
 #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
       defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F4XXX)
-#  include "chip/stm32_rtcc.h"
+#  include "hardware/stm32_rtcc.h"
 #endif
 
 /* Alarm function differs from part to part */
diff --git a/arch/arm/src/stm32/stm32_sdadc.h b/arch/arm/src/stm32/stm32_sdadc.h
index 24b89dbf9e8..2cdbba4d0d4 100644
--- a/arch/arm/src/stm32/stm32_sdadc.h
+++ b/arch/arm/src/stm32/stm32_sdadc.h
@@ -47,7 +47,7 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32_STM32F37XX)
-#  include "chip/stm32f37xxx_sdadc.h"
+#  include "hardware/stm32f37xxx_sdadc.h"
 #else
 /* No generic chip/stm32_sdadc.h yet */
 
diff --git a/arch/arm/src/stm32/stm32_sdio.h b/arch/arm/src/stm32/stm32_sdio.h
index f9d7487a381..88b1f5d777b 100644
--- a/arch/arm/src/stm32/stm32_sdio.h
+++ b/arch/arm/src/stm32/stm32_sdio.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_sdio.h"
+#include "hardware/stm32_sdio.h"
 
 /************************************************************************************
  * Public Functions
diff --git a/arch/arm/src/stm32/stm32_spi.h b/arch/arm/src/stm32/stm32_spi.h
index bcc2f0e14bb..0d22992ba57 100644
--- a/arch/arm/src/stm32/stm32_spi.h
+++ b/arch/arm/src/stm32/stm32_spi.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_spi.h"
+#include "hardware/stm32_spi.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32/stm32_start.c b/arch/arm/src/stm32/stm32_start.c
index 2d7a03ecb8d..05a23c7f280 100644
--- a/arch/arm/src/stm32/stm32_start.c
+++ b/arch/arm/src/stm32/stm32_start.c
@@ -47,15 +47,11 @@
 
 #include "up_arch.h"
 #include "up_internal.h"
+#include "nvic.h"
 
 #include "stm32.h"
 #include "stm32_gpio.h"
 #include "stm32_userspace.h"
-
-#ifdef CONFIG_ARCH_FPU
-#  include "nvic.h"
-#endif
-
 #include "stm32_start.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/stm32/stm32_syscfg.h b/arch/arm/src/stm32/stm32_syscfg.h
index 917de13031c..83005fd9568 100644
--- a/arch/arm/src/stm32/stm32_syscfg.h
+++ b/arch/arm/src/stm32/stm32_syscfg.h
@@ -44,17 +44,17 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32_STM32L15XX)
-#  include "chip/stm32l15xxx_syscfg.h"
+#  include "hardware/stm32l15xxx_syscfg.h"
 #elif defined(CONFIG_STM32_STM32F20XX)
-#  include "chip/stm32f20xxx_syscfg.h"
+#  include "hardware/stm32f20xxx_syscfg.h"
 #elif defined(CONFIG_STM32_STM32F30XX)
-#  include "chip/stm32f30xxx_syscfg.h"
+#  include "hardware/stm32f30xxx_syscfg.h"
 #elif defined(CONFIG_STM32_STM32F33XX)
-#  include "chip/stm32f33xxx_syscfg.h"
+#  include "hardware/stm32f33xxx_syscfg.h"
 #elif defined(CONFIG_STM32_STM32F37XX)
-#  include "chip/stm32f37xxx_syscfg.h"
+#  include "hardware/stm32f37xxx_syscfg.h"
 #elif defined(CONFIG_STM32_STM32F4XXX)
-#  include "chip/stm32f40xxx_syscfg.h"
+#  include "hardware/stm32f40xxx_syscfg.h"
 #endif
 
 /****************************************************************************************************
diff --git a/arch/arm/src/stm32/stm32_tim.h b/arch/arm/src/stm32/stm32_tim.h
index 2e0828fafa2..7c1b3d01e56 100644
--- a/arch/arm/src/stm32/stm32_tim.h
+++ b/arch/arm/src/stm32/stm32_tim.h
@@ -48,7 +48,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_tim.h"
+#include "hardware/stm32_tim.h"
 
 #include 
 
diff --git a/arch/arm/src/stm32/stm32_uart.h b/arch/arm/src/stm32/stm32_uart.h
index 02a0528fda2..df479384933 100644
--- a/arch/arm/src/stm32/stm32_uart.h
+++ b/arch/arm/src/stm32/stm32_uart.h
@@ -46,16 +46,16 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32_STM32L15XX)
-#  include "chip/stm32l15xxx_uart.h"
+#  include "hardware/stm32l15xxx_uart.h"
 #elif defined(CONFIG_STM32_STM32F10XX)
-#  include "chip/stm32f10xxx_uart.h"
+#  include "hardware/stm32f10xxx_uart.h"
 #elif defined(CONFIG_STM32_STM32F20XX)
-#  include "chip/stm32f20xxx_uart.h"
+#  include "hardware/stm32f20xxx_uart.h"
 #elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
     defined(CONFIG_STM32_STM32F37XX)
-#  include "chip/stm32f30xxx_uart.h"
+#  include "hardware/stm32f30xxx_uart.h"
 #elif defined(CONFIG_STM32_STM32F4XXX)
-#  include "chip/stm32f40xxx_uart.h"
+#  include "hardware/stm32f40xxx_uart.h"
 #else
 #  error "Unsupported STM32 UART"
 #endif
diff --git a/arch/arm/src/stm32/stm32_uid.c b/arch/arm/src/stm32/stm32_uid.c
index 5456b2027d6..48fd5503020 100644
--- a/arch/arm/src/stm32/stm32_uid.c
+++ b/arch/arm/src/stm32/stm32_uid.c
@@ -39,8 +39,7 @@
 
 #include 
 
-#include 
-
+#include "hardware/stm32_memorymap.h"
 #include "stm32_uid.h"
 
 #ifdef STM32_SYSMEM_UID /* Not defined for the STM32L */
diff --git a/arch/arm/src/stm32/stm32_usbdev.h b/arch/arm/src/stm32/stm32_usbdev.h
index 3ed55d01fdf..cbf511e0903 100644
--- a/arch/arm/src/stm32/stm32_usbdev.h
+++ b/arch/arm/src/stm32/stm32_usbdev.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_usbdev.h"
+#include "hardware/stm32_usbdev.h"
 
 /************************************************************************************
  * Public Functions
diff --git a/arch/arm/src/stm32/stm32_usbhost.h b/arch/arm/src/stm32/stm32_usbhost.h
index e4aab465f8c..22b113914ff 100644
--- a/arch/arm/src/stm32/stm32_usbhost.h
+++ b/arch/arm/src/stm32/stm32_usbhost.h
@@ -46,8 +46,8 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32fxxxxx_otgfs.h"
-#include "chip/stm32_otghs.h"
+#include "hardware/stm32fxxxxx_otgfs.h"
+#include "hardware/stm32_otghs.h"
 
 #if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS)) && defined(CONFIG_USBHOST)
 
@@ -280,7 +280,7 @@ extern "C"
  *
  ***********************************************************************************/
 
-#ifdef CONFIG_STM32_OTGFS_VBUS_CONTROL
+#if defined(CONFIG_STM32_OTGFS_VBUS_CONTROL) || defined(CONFIG_STM32_OTGHS_VBUS_CONTROL)
 void stm32_usbhost_vbusdrive(int iface, bool enable);
 #endif
 
diff --git a/arch/arm/src/stm32/stm32_wdg.h b/arch/arm/src/stm32/stm32_wdg.h
index 264734b9f53..8b2e25005a4 100644
--- a/arch/arm/src/stm32/stm32_wdg.h
+++ b/arch/arm/src/stm32/stm32_wdg.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_wdg.h"
+#include "hardware/stm32_wdg.h"
 
 #ifdef CONFIG_WATCHDOG
 
diff --git a/arch/arm/src/stm32/stm32_wwdg.c b/arch/arm/src/stm32/stm32_wwdg.c
index ba2b994fa40..6b6618b6817 100644
--- a/arch/arm/src/stm32/stm32_wwdg.c
+++ b/arch/arm/src/stm32/stm32_wwdg.c
@@ -49,7 +49,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/stm32_dbgmcu.h"
+#include "hardware/stm32_dbgmcu.h"
 #include "stm32_wdg.h"
 
 #if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_WWDG)
diff --git a/arch/arm/src/stm32/stm32f10xxf30xx_flash.c b/arch/arm/src/stm32/stm32f10xxf30xx_flash.c
index a7c85b24002..261d05ca499 100644
--- a/arch/arm/src/stm32/stm32f10xxf30xx_flash.c
+++ b/arch/arm/src/stm32/stm32f10xxf30xx_flash.c
@@ -73,9 +73,15 @@
 #define FLASH_OPTKEY2              0x4c5d6e7f
 #define FLASH_ERASEDVALUE          0xff
 
-#if !defined(STM32_FLASH_DUAL_BANK)
+#if defined(STM32_FLASH_DUAL_BANK)
+/* Bank 0 is 512Kb; Bank 1 is up to 512Kb */
+
+#  define STM32_FLASH_BANK0_NPAGES (512 * 1024 / STM32_FLASH_PAGESIZE)
+#  define STM32_FLASH_BANK1_NPAGES (STM32_FLASH_NPAGES - STM32_FLASH_BANK0_NPAGES)
+#else
+/* Bank 0 is up to 512Kb; Bank 1 is not present */
+
 #  define STM32_FLASH_BANK0_NPAGES STM32_FLASH_NPAGES
-#  define STM32_FLASH_BANK0_BASE   STM32_FLASH_BASE
 #endif
 
 /************************************************************************************
@@ -140,9 +146,9 @@ static void flash_lock(uintptr_t base)
 void stm32_flash_unlock(void)
 {
   sem_lock();
-  flash_unlock(STM32_FLASH_BANK0_BASE);
+  flash_unlock(STM32_FLASHIF_BASE);
 #if defined(STM32_FLASH_DUAL_BANK)
-  flash_unlock(STM32_FLASH_BANK1_BASE);
+  flash_unlock(STM32_FLASHIF1_BASE);
 #endif
   sem_unlock();
 }
@@ -150,9 +156,9 @@ void stm32_flash_unlock(void)
 void stm32_flash_lock(void)
 {
   sem_lock();
-  flash_lock(STM32_FLASH_BANK0_BASE);
+  flash_lock(STM32_FLASHIF_BASE);
 #if defined(STM32_FLASH_DUAL_BANK)
-  flash_lock(STM32_FLASH_BANK1_BASE);
+  flash_lock(STM32_FLASHIF1_BASE);
 #endif
   sem_unlock();
 }
@@ -246,17 +252,17 @@ ssize_t up_progmem_eraseblock(size_t block)
 
   if (block >= STM32_FLASH_BANK0_NPAGES)
     {
-      base = STM32_FLASH_BANK1_BASE;
+      base = STM32_FLASHIF1_BASE;
     }
   else
 #endif
     {
-      base = STM32_FLASH_BANK0_BASE;
+      base = STM32_FLASHIF_BASE;
     }
 
   sem_lock();
 
-  if ((getreg32(base + STM32_RCC_CR_OFFSET) & RCC_CR_HSION) == 0)
+  if ((getreg32(STM32_RCC_CR) & RCC_CR_HSION) == 0)
     {
       sem_unlock();
       return -EPERM;
@@ -306,12 +312,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
 
   if (page >= STM32_FLASH_BANK0_NPAGES)
     {
-      base = STM32_FLASH_BANK1_BASE;
+      base = STM32_FLASHIF1_BASE;
     }
   else
 #endif
     {
-      base = STM32_FLASH_BANK0_BASE;
+      base = STM32_FLASHIF_BASE;
     }
 
   /* STM32 requires half-word access */
@@ -335,7 +341,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
 
   sem_lock();
 
-  if ((getreg32(base + STM32_RCC_CR_OFFSET) & RCC_CR_HSION) == 0)
+  if ((getreg32(STM32_RCC_CR) & RCC_CR_HSION) == 0)
     {
       sem_unlock();
       return -EPERM;
diff --git a/arch/arm/src/stm32/stm32f30xxx_i2c.c b/arch/arm/src/stm32/stm32f30xxx_i2c.c
deleted file mode 100644
index 29f084590b1..00000000000
--- a/arch/arm/src/stm32/stm32f30xxx_i2c.c
+++ /dev/null
@@ -1,2019 +0,0 @@
-/************************************************************************************
- * arch/arm/src/stm32/stm32f3xx_i2c.c
- * STM32 F3 I2C Hardware Layer - Device Driver
- *
- *   Copyright (C) 2011 Uros Platise. All rights reserved.
- *   Author: Uros Platise 
- *
- * With extensions and modifications for the F1, F2, and F4 by:
- *
- *   Copyright (C) 2011-2013, 2016-2017 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt 
- *
- * And this version for the STM32 F3 by
- *
- *   Author: John Wharington
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-/* Supports:
- *  - Master operation, 100 kHz (standard) and 400 kHz (full speed)
- *  - Multiple instances (shared bus)
- *  - Interrupt based operation
- *
- * Structure naming:
- *  - Device: structure as defined by the nuttx/i2c/i2c.h
- *  - Instance: represents each individual access to the I2C driver, obtained by
- *      the i2c_init(); it extends the Device structure from the nuttx/i2c/i2c.h;
- *      Instance points to OPS, to common I2C Hardware private data and contains
- *      its own private data, as frequency, address, mode of operation (in the future)
- *  - Private: Private data of an I2C Hardware
- *
- * TODO
- *  - Check for all possible deadlocks (as BUSY='1' I2C needs to be reset in HW using the I2C_CR1_SWRST)
- *  - SMBus support (hardware layer timings are already supported) and add SMBA gpio pin
- *  - Slave support with multiple addresses (on multiple instances):
- *      - 2 x 7-bit address or
- *      - 1 x 10 bit adresses + 1 x 7 bit address (?)
- *      - plus the broadcast address (general call)
- *  - Multi-master support
- *  - DMA (to get rid of too many CPU wake-ups and interventions)
- *  - Be ready for IPMI
- */
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include 
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include 
-
-#include "up_arch.h"
-
-#include "stm32_rcc.h"
-#include "stm32_i2c.h"
-#include "stm32_waste.h"
-
-/* At least one I2C peripheral must be enabled */
-
-#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || defined(CONFIG_STM32_I2C3)
-/* This implementation is for the STM32 F1, F2, and F4 only */
-
-#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-/* Configuration ********************************************************************/
-/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used.  Instead,
- * CPU-intensive polling will be used.
- */
-
-/* Interrupt wait timeout in seconds and milliseconds */
-
-#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS)
-#  define CONFIG_STM32_I2CTIMEOSEC 0
-#  define CONFIG_STM32_I2CTIMEOMS  500   /* Default is 500 milliseconds */
-#elif !defined(CONFIG_STM32_I2CTIMEOSEC)
-#  define CONFIG_STM32_I2CTIMEOSEC 0     /* User provided milliseconds */
-#elif !defined(CONFIG_STM32_I2CTIMEOMS)
-#  define CONFIG_STM32_I2CTIMEOMS  0     /* User provided seconds */
-#endif
-
-/* Interrupt wait time timeout in system timer ticks */
-
-#ifndef CONFIG_STM32_I2CTIMEOTICKS
-#  define CONFIG_STM32_I2CTIMEOTICKS \
-    (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS))
-#endif
-
-#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP
-#  define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS)
-#endif
-
-#define I2C_OUTPUT \
-  (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_OPENDRAIN | GPIO_SPEED_50MHz)
-#define MKI2C_OUTPUT(p) \
-  (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
-
-/* Register setting unique to the STM32F30xx */
-
-#define I2C_CR1_TXRX \
-  (I2C_CR1_RXIE | I2C_CR1_TXIE)
-#define I2C_CR1_ALLINTS \
-  (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ADDRIE | I2C_CR1_ERRIE)
-
-#define STATUS_NACK(status)    (status & I2C_INT_NACK)
-#define STATUS_ADDR(status)    (status & I2C_INT_ADDR)
-#define STATUS_ADDR_TX(status) (status & (I2C_INT_ADDR | I2C_ISR_TXIS))
-#define STATUS_ADD10(status)   (0)
-#define STATUS_RXNE(status)    (status & I2C_ISR_RXNE)
-#define STATUS_TC(status)      (status & I2C_ISR_TC)
-#define STATUS_BUSY(status)    (status & I2C_ISR_BUSY)
-
-/* Debug ****************************************************************************/
-
-/* I2C event trace logic.  NOTE:  trace uses the internal, non-standard, low-level
- * debug interface syslog() but does not require that any other debug
- * is enabled.
- */
-
-#ifndef CONFIG_I2C_TRACE
-#  define stm32_i2c_tracereset(p)
-#  define stm32_i2c_tracenew(p,s)
-#  define stm32_i2c_traceevent(p,e,a)
-#  define stm32_i2c_tracedump(p)
-#endif
-
-#ifndef CONFIG_I2C_NTRACE
-#  define CONFIG_I2C_NTRACE 32
-#endif
-
-/************************************************************************************
- * Private Types
- ************************************************************************************/
-/* Interrupt state */
-
-enum stm32_intstate_e
-{
-  INTSTATE_IDLE = 0,      /* No I2C activity */
-  INTSTATE_WAITING,       /* Waiting for completion of interrupt activity */
-  INTSTATE_DONE,          /* Interrupt activity complete */
-};
-
-/* Trace events */
-
-enum stm32_trace_e
-{
-  I2CEVENT_NONE = 0,      /* No events have occurred with this status */
-  I2CEVENT_SENDADDR,      /* Start/Master bit set and address sent, param = msgc */
-  I2CEVENT_SENDBYTE,      /* Send byte, param = dcnt */
-  I2CEVENT_ITBUFEN,       /* Enable buffer interrupts, param = 0 */
-  I2CEVENT_RCVBYTE,       /* Read more dta, param = dcnt */
-  I2CEVENT_REITBUFEN,     /* Re-enable buffer interrupts, param = 0 */
-  I2CEVENT_DISITBUFEN,    /* Disable buffer interrupts, param = 0 */
-  I2CEVENT_BTFNOSTART,    /* BTF on last byte with no restart, param = msgc */
-  I2CEVENT_BTFRESTART,    /* Last byte sent, re-starting, param = msgc */
-  I2CEVENT_BTFSTOP,       /* Last byte sten, send stop, param = 0 */
-  I2CEVENT_ERROR          /* Error occurred, param = 0 */
-};
-
-/* Trace data */
-
-struct stm32_trace_s
-{
-  uint32_t status;             /* I2C 32-bit SR2|SR1 status */
-  uint32_t count;              /* Interrupt count when status change */
-  enum stm32_intstate_e event; /* Last event that occurred with this status */
-  uint32_t parm;               /* Parameter associated with the event */
-  clock_t time;                /* First of event or first status */
-};
-
-/* I2C Device hardware configuration */
-
-struct stm32_i2c_config_s
-{
-  uint32_t base;              /* I2C base address */
-  uint32_t clk_bit;           /* Clock enable bit */
-  uint32_t reset_bit;         /* Reset bit */
-  uint32_t scl_pin;           /* GPIO configuration for SCL as SCL */
-  uint32_t sda_pin;           /* GPIO configuration for SDA as SDA */
-#ifndef CONFIG_I2C_POLLED
-  uint32_t ev_irq;            /* Event IRQ */
-  uint32_t er_irq;            /* Error IRQ */
-#endif
-};
-
-/* I2C Device Private Data */
-
-struct stm32_i2c_priv_s
-{
-  const struct i2c_ops_s *ops; /* Standard I2C operations */
-  const struct stm32_i2c_config_s *config; /* Port configuration */
-  int refs;                    /* Referernce count */
-  sem_t sem_excl;              /* Mutual exclusion semaphore */
-#ifndef CONFIG_I2C_POLLED
-  sem_t sem_isr;               /* Interrupt wait semaphore */
-#endif
-  volatile uint8_t intstate;   /* Interrupt handshake (see enum stm32_intstate_e) */
-
-  uint8_t msgc;                /* Message count */
-  struct i2c_msg_s *msgv;      /* Message list */
-  uint8_t *ptr;                /* Current message buffer */
-  uint32_t frequency;          /* Current I2C frequency */
-  int dcnt;                    /* Current message length */
-  uint16_t flags;              /* Current message flags */
-  bool astart;                 /* START sent */
-
-  /* I2C trace support */
-
-#ifdef CONFIG_I2C_TRACE
-  int tndx;                    /* Trace array index */
-  clock_t start_time;          /* Time when the trace was started */
-
-  /* The actual trace data */
-
-  struct stm32_trace_s trace[CONFIG_I2C_NTRACE];
-#endif
-
-  uint32_t status;             /* End of transfer SR2|SR1 status */
-};
-
-/************************************************************************************
- * Private Function Prototypes
- ************************************************************************************/
-
-static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv,
-                                        uint8_t offset);
-static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset,
-                                    uint16_t value);
-static inline void stm32_i2c_putreg32(FAR struct stm32_i2c_priv_s *priv, uint8_t offset,
-                                    uint32_t value);
-static inline void stm32_i2c_modifyreg(FAR struct stm32_i2c_priv_s *priv,
-                                       uint8_t offset, uint16_t clearbits,
-                                       uint16_t setbits);
-static inline void stm32_i2c_modifyreg32(FAR struct stm32_i2c_priv_s *priv,
-                                         uint8_t offset, uint32_t clearbits,
-                                         uint32_t setbits);
-static inline void stm32_i2c_sem_wait(FAR struct stm32_i2c_priv_s *priv);
-#ifdef CONFIG_STM32_I2C_DYNTIMEO
-static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs);
-#endif /* CONFIG_STM32_I2C_DYNTIMEO */
-static inline int  stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv);
-static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv);
-static inline void stm32_i2c_sem_post(FAR struct stm32_i2c_priv_s *priv);
-static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv);
-static inline void stm32_i2c_sem_destroy(FAR struct stm32_i2c_priv_s *priv);
-#ifdef CONFIG_I2C_TRACE
-static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv);
-static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t status);
-static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
-                               enum stm32_trace_e event, uint32_t parm);
-static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv);
-#endif /* CONFIG_I2C_TRACE */
-static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv,
-                               uint32_t frequency);
-static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv);
-static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv);
-static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv);
-static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv);
-static int stm32_i2c_isr_process(struct stm32_i2c_priv_s * priv);
-#ifndef CONFIG_I2C_POLLED
-static int stm32_i2c_isr(int irq, void *context, FAR void *arg);
-#endif
-static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv);
-static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv);
-static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
-                              int count);
-#ifdef CONFIG_I2C_RESET
-static int stm32_i2c_reset(FAR struct i2c_master_s *dev);
-#endif
-
-/************************************************************************************
- * Private Data
- ************************************************************************************/
-
-/* Device Structures, Instantiation */
-
-static const struct i2c_ops_s stm32_i2c_ops =
-{
- .transfer = stm32_i2c_transfer
-#ifdef CONFIG_I2C_RESET
-  , .reset  = stm32_i2c_reset
-#endif
-};
-
-#ifdef CONFIG_STM32_I2C1
-static const struct stm32_i2c_config_s stm32_i2c1_config =
-{
-  .base       = STM32_I2C1_BASE,
-  .clk_bit    = RCC_APB1ENR_I2C1EN,
-  .reset_bit  = RCC_APB1RSTR_I2C1RST,
-  .scl_pin    = GPIO_I2C1_SCL,
-  .sda_pin    = GPIO_I2C1_SDA,
-#ifndef CONFIG_I2C_POLLED
-  .ev_irq     = STM32_IRQ_I2C1EV,
-  .er_irq     = STM32_IRQ_I2C1ER
-#endif
-};
-
-static struct stm32_i2c_priv_s stm32_i2c1_priv =
-{
-  .ops        = &stm32_i2c_ops,
-  .config     = &stm32_i2c1_config,
-  .refs       = 0,
-  .intstate   = INTSTATE_IDLE,
-  .msgc       = 0,
-  .msgv       = NULL,
-  .ptr        = NULL,
-  .dcnt       = 0,
-  .flags      = 0,
-  .status     = 0
-};
-#endif
-
-#ifdef CONFIG_STM32_I2C2
-static const struct stm32_i2c_config_s stm32_i2c2_config =
-{
-  .base       = STM32_I2C2_BASE,
-  .clk_bit    = RCC_APB1ENR_I2C2EN,
-  .reset_bit  = RCC_APB1RSTR_I2C2RST,
-  .scl_pin    = GPIO_I2C2_SCL,
-  .sda_pin    = GPIO_I2C2_SDA,
-#ifndef CONFIG_I2C_POLLED
-  .ev_irq     = STM32_IRQ_I2C2EV,
-  .er_irq     = STM32_IRQ_I2C2ER
-#endif
-};
-
-static struct stm32_i2c_priv_s stm32_i2c2_priv =
-{
-  .ops        = &stm32_i2c_ops,
-  .config     = &stm32_i2c2_config,
-  .refs       = 0,
-  .intstate   = INTSTATE_IDLE,
-  .msgc       = 0,
-  .msgv       = NULL,
-  .ptr        = NULL,
-  .dcnt       = 0,
-  .flags      = 0,
-  .status     = 0
-};
-#endif
-
-#ifdef CONFIG_STM32_I2C3
-static const struct stm32_i2c_config_s stm32_i2c3_config =
-{
-  .base       = STM32_I2C3_BASE,
-  .clk_bit    = RCC_APB1ENR_I2C3EN,
-  .reset_bit  = RCC_APB1RSTR_I2C3RST,
-  .scl_pin    = GPIO_I2C3_SCL,
-  .sda_pin    = GPIO_I2C3_SDA,
-#ifndef CONFIG_I2C_POLLED
-  .ev_irq     = STM32_IRQ_I2C3EV,
-  .er_irq     = STM32_IRQ_I2C3ER
-#endif
-};
-
-static struct stm32_i2c_priv_s stm32_i2c3_priv =
-{
-  .ops        = &stm32_i2c_ops,
-  .config     = &stm32_i2c3_config,
-  .refs       = 0,
-  .intstate   = INTSTATE_IDLE,
-  .msgc       = 0,
-  .msgv       = NULL,
-  .ptr        = NULL,
-  .dcnt       = 0,
-  .flags      = 0,
-  .status     = 0
-};
-#endif
-
-/************************************************************************************
- * Private Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Name: stm32_i2c_getreg
- *
- * Description:
- *   Get a 16-bit register value by offset
- *
- ************************************************************************************/
-
-static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv,
-                                        uint8_t offset)
-{
-  return getreg16(priv->config->base + offset);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_getreg32
- *
- * Description:
- *   Get a 32-bit register value by offset
- *
- ************************************************************************************/
-
-static inline uint32_t stm32_i2c_getreg32(FAR struct stm32_i2c_priv_s *priv,
-                                          uint8_t offset)
-{
-  return getreg32(priv->config->base + offset);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_putreg
- *
- * Description:
- *  Put a 16-bit register value by offset
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset,
-                                    uint16_t value)
-{
-  putreg16(value, priv->config->base + offset);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_putreg32
- *
- * Description:
- *  Put a 32-bit register value by offset
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_putreg32(FAR struct stm32_i2c_priv_s *priv,
-                                      uint8_t offset, uint32_t value)
-{
-  putreg32(value, priv->config->base + offset);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_modifyreg
- *
- * Description:
- *   Modify a 16-bit register value by offset
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_modifyreg(FAR struct stm32_i2c_priv_s *priv,
-                                       uint8_t offset, uint16_t clearbits,
-                                       uint16_t setbits)
-{
-  modifyreg16(priv->config->base + offset, clearbits, setbits);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_modifyreg32
- *
- * Description:
- *   Modify a 32-bit register value by offset
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_modifyreg32(FAR struct stm32_i2c_priv_s *priv,
-                                         uint8_t offset, uint32_t clearbits,
-                                         uint32_t setbits)
-{
-  modifyreg32(priv->config->base + offset, clearbits, setbits);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_sem_wait
- *
- * Description:
- *   Take the exclusive access, waiting as necessary
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_sem_wait(FAR struct stm32_i2c_priv_s *priv)
-{
-  int ret;
-
-  do
-    {
-      /* Take the semaphore (perhaps waiting) */
-
-      ret = nxsem_wait(&priv->sem_excl);
-
-      /* The only case that an error should occur here is if the wait was
-       * awakened by a signal.
-       */
-
-      DEBUGASSERT(ret == OK || ret == -EINTR);
-    }
-  while (ret == -EINTR);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_tousecs
- *
- * Description:
- *   Return a micro-second delay based on the number of bytes left to be processed.
- *
- ************************************************************************************/
-
-#ifdef CONFIG_STM32_I2C_DYNTIMEO
-static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
-{
-  size_t bytecount = 0;
-  int i;
-
-  /* Count the number of bytes left to process */
-
-  for (i = 0; i < msgc; i++)
-    {
-      bytecount += msgs[i].length;
-    }
-
-  /* Then return a number of microseconds based on a user provided scaling
-   * factor.
-   */
-
-  return (useconds_t)(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount);
-}
-#endif
-
-/************************************************************************************
- * Name: stm32_i2c_enableinterrupts
- *
- * Description:
- *   Enable I2C interrupts
- *
- ************************************************************************************/
-
-#ifndef CONFIG_I2C_POLLED
-static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_TXRX);
-}
-#endif
-
-/************************************************************************************
- * Name: stm32_i2c_disableinterrupts
- *
- * Description:
- *   Enable I2C interrupts
- *
- ************************************************************************************/
-
-#ifndef CONFIG_I2C_POLLED
-static inline void stm32_i2c_disableinterrupts(struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_TXRX, 0);
-}
-#endif
-
-/************************************************************************************
- * Name: stm32_i2c_sem_waitdone
- *
- * Description:
- *   Wait for a transfer to complete
- *
- ************************************************************************************/
-
-#ifndef CONFIG_I2C_POLLED
-static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
-{
-  struct timespec abstime;
-  irqstate_t flags;
-  int ret;
-
-  flags = enter_critical_section();
-
-  /* Enable I2C interrupts */
-
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0,
-                        (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX));
-
-  /* Signal the interrupt handler that we are waiting.  NOTE:  Interrupts
-   * are currently disabled but will be temporarily re-enabled below when
-   * nxsem_timedwait() sleeps.
-   */
-
-   priv->intstate = INTSTATE_WAITING;
-   do
-    {
-      /* Get the current time */
-
-      (void)clock_gettime(CLOCK_REALTIME, &abstime);
-
-      /* Calculate a time in the future */
-
-#if CONFIG_STM32_I2CTIMEOSEC > 0
-      abstime.tv_sec += CONFIG_STM32_I2CTIMEOSEC;
-#endif
-
-      /* Add a value proportional to the number of bytes in the transfer */
-
-#ifdef CONFIG_STM32_I2C_DYNTIMEO
-      abstime.tv_nsec += 1000 * stm32_i2c_tousecs(priv->msgc, priv->msgv);
-      if (abstime.tv_nsec >= 1000 * 1000 * 1000)
-        {
-          abstime.tv_sec++;
-          abstime.tv_nsec -= 1000 * 1000 * 1000;
-        }
-
-#elif CONFIG_STM32_I2CTIMEOMS > 0
-      abstime.tv_nsec += CONFIG_STM32_I2CTIMEOMS * 1000 * 1000;
-      if (abstime.tv_nsec >= 1000 * 1000 * 1000)
-        {
-          abstime.tv_sec++;
-          abstime.tv_nsec -= 1000 * 1000 * 1000;
-        }
-#endif
-      /* Wait until either the transfer is complete or the timeout expires */
-
-      ret = nxsem_timedwait(&priv->sem_isr, &abstime);
-      if (ret < 0 && ret != -EINTR)
-        {
-          /* Break out of the loop on irrecoverable errors.  This would
-           * include timeouts and mystery errors reported by nxsem_timedwait.
-           * NOTE that we try again if we are awakened by a signal (EINTR).
-           */
-
-          break;
-        }
-    }
-
-  /* Loop until the interrupt level transfer is complete. */
-
-  while (priv->intstate != INTSTATE_DONE);
-
-  /* Set the interrupt state back to IDLE */
-
-  priv->intstate = INTSTATE_IDLE;
-
-  /* Disable I2C interrupts */
-
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
-
-  leave_critical_section(flags);
-  return ret;
-}
-#else
-static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
-{
-  clock_t timeout;
-  clock_t start;
-  clock_t elapsed;
-  int ret;
-
-  /* Get the timeout value */
-
-#ifdef CONFIG_STM32_I2C_DYNTIMEO
-  timeout = USEC2TICK(stm32_i2c_tousecs(priv->msgc, priv->msgv));
-#else
-  timeout = CONFIG_STM32_I2CTIMEOTICKS;
-#endif
-
-  /* Signal the interrupt handler that we are waiting.  NOTE:  Interrupts
-   * are currently disabled but will be temporarily re-enabled below when
-   * nxsem_timedwait() sleeps.
-   */
-
-  priv->intstate = INTSTATE_WAITING;
-  start = clock_systimer();
-
-  do
-    {
-      /* Calculate the elapsed time */
-
-      elapsed = clock_systimer() - start;
-
-      /* Poll by simply calling the timer interrupt handler until it
-       * reports that it is done.
-       */
-
-      stm32_i2c_isr_process(priv);
-    }
-
-  /* Loop until the transfer is complete. */
-
-  while (priv->intstate != INTSTATE_DONE && elapsed < timeout);
-
-  i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08x\n",
-          priv->intstate, (long)elapsed, (long)timeout, priv->status);
-
-  /* Set the interrupt state back to IDLE */
-
-  ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT;
-  priv->intstate = INTSTATE_IDLE;
-  return ret;
-}
-#endif
-
-/************************************************************************************
- * Name: stm32_i2c_set_7bit_address
- *
- * Description:
- *
- ************************************************************************************/
-
-static inline void
-stm32_i2c_set_7bit_address(FAR struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK,
-                        ((priv->msgv->addr & 0x7F) << I2C_CR2_SADD7_SHIFT));
-}
-
-/************************************************************************************
- * Name: stm32_i2c_set_bytes_to_transfer
- *
- * Description:
- *
- ************************************************************************************/
-
-static inline void
-stm32_i2c_set_bytes_to_transfer(FAR struct stm32_i2c_priv_s *priv,
-                               uint8_t n_bytes)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK,
-                        (n_bytes << I2C_CR2_NBYTES_SHIFT));
-}
-
-/************************************************************************************
- * Name: stm32_i2c_set_write_transfer_dir
- *
- * Description:
- *
- ************************************************************************************/
-
-static inline void
-stm32_i2c_set_write_transfer_dir(FAR struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_set_read_transfer_dir
- *
- * Description:
- *
- ************************************************************************************/
-
-static inline void
-stm32_i2c_set_read_transfer_dir(FAR struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_enable_autoend
- *
- * Description:
- *
- ************************************************************************************/
-
-static inline void
-stm32_i2c_enable_autoend(FAR struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_AUTOEND);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_disable_autoend
- *
- * Description:
- *
- ************************************************************************************/
-
-static inline void
-stm32_i2c_disable_autoend(FAR struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_AUTOEND, 0);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_sem_waitstop
- *
- * Description:
- *   Wait for a STOP to complete
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
-{
-  clock_t start;
-  clock_t elapsed;
-  clock_t timeout;
-  uint32_t cr;
-  uint32_t sr;
-
-  /* Select a timeout */
-
-#ifdef CONFIG_STM32_I2C_DYNTIMEO
-  timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP);
-#else
-  timeout = CONFIG_STM32_I2CTIMEOTICKS;
-#endif
-
-  /* Wait as stop might still be in progress; but stop might also
-   * be set because of a timeout error: "The [STOP] bit is set and
-   * cleared by software, cleared by hardware when a Stop condition is
-   * detected, set by hardware when a timeout error is detected."
-   */
-
-  start = clock_systimer();
-  do
-    {
-      /* Calculate the elapsed time */
-
-      elapsed = clock_systimer() - start;
-
-      /* Check for STOP condition */
-
-      cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET);
-      if ((cr & I2C_CR2_STOP) == 0)
-        {
-          return;
-        }
-
-      /* Check for timeout error */
-
-      sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
-      if ((sr & I2C_INT_TIMEOUT) != 0)
-        {
-          return;
-        }
-
-    }
-
-  /* Loop until the stop is complete or a timeout occurs. */
-
-  while (elapsed < timeout);
-
-  /* If we get here then a timeout occurred with the STOP condition
-   * still pending.
-   */
-
-  i2cinfo("Timeout with CR: %04x SR: %04x\n", cr, sr);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_sem_post
- *
- * Description:
- *   Release the mutual exclusion semaphore
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_sem_post(FAR struct stm32_i2c_priv_s *priv)
-{
-  nxsem_post(&priv->sem_excl);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_sem_init
- *
- * Description:
- *   Initialize semaphores
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv)
-{
-  nxsem_init(&priv->sem_excl, 0, 1);
-
-#ifndef CONFIG_I2C_POLLED
-  /* This semaphore is used for signaling and, hence, should not have
-   * priority inheritance enabled.
-   */
-
-  nxsem_init(&priv->sem_isr, 0, 0);
-  nxsem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
-#endif
-}
-
-/************************************************************************************
- * Name: stm32_i2c_sem_destroy
- *
- * Description:
- *   Destroy semaphores.
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_sem_destroy(FAR struct stm32_i2c_priv_s *priv)
-{
-  nxsem_destroy(&priv->sem_excl);
-#ifndef CONFIG_I2C_POLLED
-  nxsem_destroy(&priv->sem_isr);
-#endif
-}
-
-/************************************************************************************
- * Name: stm32_i2c_trace*
- *
- * Description:
- *   I2C trace instrumentation
- *
- ************************************************************************************/
-
-#ifdef CONFIG_I2C_TRACE
-static void stm32_i2c_traceclear(FAR struct stm32_i2c_priv_s *priv)
-{
-  struct stm32_trace_s *trace = &priv->trace[priv->tndx];
-
-  trace->status = 0;              /* I2C 32-bit SR2|SR1 status */
-  trace->count  = 0;              /* Interrupt count when status change */
-  trace->event  = I2CEVENT_NONE;  /* Last event that occurred with this status */
-  trace->parm   = 0;              /* Parameter associated with the event */
-  trace->time   = 0;              /* Time of first status or event */
-}
-
-static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv)
-{
-  /* Reset the trace info for a new data collection */
-
-  priv->tndx       = 0;
-  priv->start_time = clock_systimer();
-  stm32_i2c_traceclear(priv);
-}
-
-static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv,
-                               uint32_t status)
-{
-  struct stm32_trace_s *trace = &priv->trace[priv->tndx];
-
-  /* Is the current entry uninitialized?   Has the status changed? */
-
-  if (trace->count == 0 || status != trace->status)
-    {
-      /* Yes.. Was it the status changed?  */
-
-      if (trace->count != 0)
-        {
-          /* Yes.. bump up the trace index (unless we are out of trace entries) */
-
-          if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
-            {
-              i2cerr("ERROR: Trace table overflow\n");
-              return;
-            }
-
-          priv->tndx++;
-          trace = &priv->trace[priv->tndx];
-        }
-
-      /* Initialize the new trace entry */
-
-      stm32_i2c_traceclear(priv);
-      trace->status = status;
-      trace->count  = 1;
-      trace->time   = clock_systimer();
-    }
-  else
-    {
-      /* Just increment the count of times that we have seen this status */
-
-      trace->count++;
-    }
-}
-
-static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
-                                enum stm32_trace_e event, uint32_t parm)
-{
-  struct stm32_trace_s *trace;
-
-  if (event != I2CEVENT_NONE)
-    {
-      trace = &priv->trace[priv->tndx];
-
-      /* Initialize the new trace entry */
-
-      trace->event  = event;
-      trace->parm   = parm;
-
-      /* Bump up the trace index (unless we are out of trace entries) */
-
-      if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
-        {
-          i2cerr("ERROR: Trace table overflow\n");
-          return;
-        }
-
-      priv->tndx++;
-      stm32_i2c_traceclear(priv);
-    }
-}
-
-static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
-{
-  struct stm32_trace_s *trace;
-  int i;
-
-  syslog(LOG_DEBUG, "Elapsed time: %ld\n",
-         (long)(clock_systimer() - priv->start_time));
-
-  for (i = 0; i < priv->tndx; i++)
-    {
-      trace = &priv->trace[i];
-      syslog(LOG_DEBUG,
-             "%2d. STATUS: %08x COUNT: %3d EVENT: %2d PARM: %08x TIME: %d\n",
-             i+1, trace->status, trace->count,  trace->event, trace->parm,
-             trace->time - priv->start_time);
-    }
-}
-#endif /* CONFIG_I2C_TRACE */
-
-/************************************************************************************
- * Name: stm32_i2c_setclock
- *
- * Description:
- *   Set the I2C clock
- *
- ************************************************************************************/
-
-static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequency)
-{
-  uint32_t pe;
-  uint8_t presc;
-  uint8_t s_time;
-  uint8_t h_time;
-  uint8_t scl_h_period;
-  uint8_t scl_l_period;
-
-  /* Has the I2C bus frequency changed? */
-
-  if (frequency != priv->frequency)
-    {
-      /* Disable the selected I2C peripheral to configure TRISE */
-
-      pe = (stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE);
-      if (pe)
-        {
-          stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
-        }
-
-      /* Update timing and control registers */
-
-      /* TODO: speed/timing calcs */
-#warning "check set filters before timing, see RM0316"
-
-      /* values from 100khz at 8mhz i2c clock */
-
-      /* prescaler */
-      /* t_presc= (presc+1)*t_i2cclk */
-      /* RM0316 */
-
-      if (frequency == 10000)
-        {
-          presc        = 0x01;
-          scl_l_period = 0xc7;
-          scl_h_period = 0xc3;
-          h_time       = 0x02;
-          s_time       = 0x04;
-        }
-     else if (frequency == 100000)
-        {
-          /* values from datasheet with clock 8mhz */
-
-          presc        = 0x01;
-          scl_l_period = 0x13;
-          scl_h_period = 0x0f;
-          h_time       = 0x02;
-          s_time       = 0x04;
-        }
-      else
-        {
-          presc        = 0x00;
-          scl_l_period = 0x09;
-          scl_h_period = 0x03;
-          h_time       = 0x01;
-          s_time       = 0x03;
-        }
-
-      uint32_t timingr =
-        (presc << I2C_TIMINGR_PRESC_SHIFT) |
-        (s_time << I2C_TIMINGR_SCLDEL_SHIFT) |
-        (h_time << I2C_TIMINGR_SDADEL_SHIFT) |
-        (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) |
-        (scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
-
-      stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr);
-
-      /* Bit 14 of OAR1 must be configured and kept at 1 */
-
-      stm32_i2c_putreg(priv, STM32_I2C_OAR1_OFFSET, I2C_OAR1_ONE);
-
-      /* Re-enable the peripheral (or not) */
-
-      if (pe)
-        {
-          stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
-        }
-
-      /* Save the new I2C frequency */
-
-      priv->frequency = frequency;
-    }
-}
-
-/************************************************************************************
- * Name: stm32_i2c_sendstart
- *
- * Description:
- *   Send the START conditions/force Master mode
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv)
-{
-  /* Get run-time data */
-
-  priv->astart = true;
-  priv->ptr   = priv->msgv->buffer;
-  priv->dcnt  = priv->msgv->length;
-  priv->flags = priv->msgv->flags;
-
-  /* Disable ACK on receive by default and generate START */
-
-  stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
-  stm32_i2c_set_7bit_address(priv);
-  if (priv->flags & I2C_M_READ)
-    {
-      stm32_i2c_set_read_transfer_dir(priv);
-    }
-  else
-    {
-      stm32_i2c_set_write_transfer_dir(priv);
-    }
-
-  if (priv->msgc == 1)
-    {
-      /* stm32_i2c_enable_autoend(priv); */
-    }
-  else
-    {
-      /* stm32_i2c_disable_autoend(priv); */
-    }
-
-  /* TODO check NACK */
-  /* TODO handle NACKR? */
-
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_clrstart
- *
- * Description:
- *   Clear the STOP, START or PEC condition on certain error recovery steps.
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv)
-{
-  /* "Note: When the STOP, START or PEC bit is set, the software must
-   *  not perform any write access to I2C_CR1 before this bit is
-   *  cleared by hardware. Otherwise there is a risk of setting a
-   *  second STOP, START or PEC request."
-   *
-   * "The [STOP] bit is set and cleared by software, cleared by hardware
-   *  when a Stop condition is detected, set by hardware when a timeout
-   *  error is detected.
-   *
-   * "This [START] bit is set and cleared by software and cleared by hardware
-   *  when start is sent or PE=0."  The bit must be cleared by software if the
-   *  START is never sent.
-   *
-   * "This [PEC] bit is set and cleared by software, and cleared by hardware
-   *  when PEC is transferred or by a START or Stop condition or when PE=0."
-   */
-
-  /* TODO check PEC (32 bit separate reg) */
-
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET,
-                        I2C_CR2_START | I2C_CR2_STOP, 0);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_sendstop
- *
- * Description:
- *   Send the STOP conditions
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv)
-{
-  /* TODO check NACK */
-
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_getstatus
- *
- * Description:
- *   Get 32-bit status (SR1 and SR2 combined)
- *
- ************************************************************************************/
-
-static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv)
-{
-  return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_isr_startmessage
- *
- * Description:
- *   Common logic when a message is started.  Just adds the even to the trace buffer
- *   if enabled and adjusts the message pointer and count.
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_isr_startmessage(struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_traceevent(priv, I2CEVENT_SENDADDR, priv->msgc);
-
-  /* Increment to next pointer and decrement message count */
-
-  priv->msgv++;
-  priv->msgc--;
-}
-
-/************************************************************************************
- * Name: stm32_i2c_clearinterrupts
- *
- * Description:
- *  Clear all interrupts
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv)
-{
-#warning "check this clears interrupts?"
-    stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_isr_process
- *
- * Description:
- *  Common Interrupt Service Routine
- *
- ************************************************************************************/
-
-static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
-{
-  uint32_t status = stm32_i2c_getstatus(priv);
-
-  /* Check for new trace setup */
-
-  stm32_i2c_tracenew(priv, status);
-
-#warning "TODO: check clear interrupts after all actions"
-
-  if (STATUS_NACK(status))
-    {
-      /* wait, reset this? */
-    }
-  else if (priv->astart)
-    {
-      stm32_i2c_isr_startmessage(priv);
-      priv->astart = false;
-    }
-
-  /* Was address sent, continue with either sending or reading data */
-
-  if ((priv->flags & I2C_M_READ) == 0 && STATUS_ADDR_TX(status))
-    {
-#warning "TODO: ADDRCF clear address interrupt flag"
-      if (priv->dcnt > 0)
-        {
-          /* Send a byte */
-
-          stm32_i2c_traceevent(priv, I2CEVENT_SENDBYTE, priv->dcnt);
-          stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr++);
-          priv->dcnt--;
-        }
-    }
-
-  else if ((priv->flags & I2C_M_READ) != 0 && STATUS_ADDR(status))
-    {
-      /* Enable RxNE and TxE buffers in order to receive one or multiple bytes */
-
-#warning "TODO: ADDRCF clear address interrupt flag"
-
-#ifndef CONFIG_I2C_POLLED
-      stm32_i2c_traceevent(priv, I2CEVENT_ITBUFEN, 0);
-      stm32_i2c_enableinterrupts(priv);
-#endif
-    }
-
-  /* More bytes to read */
-  else if (STATUS_RXNE(status))
-    {
-      /* Read a byte, if dcnt goes < 0, then read dummy bytes to ack ISRs */
-
-      if (priv->dcnt > 0)
-        {
-          stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt);
-
-          /* No interrupts or context switches may occur in the following
-           * sequence.  Otherwise, additional bytes may be sent by the
-           * device.
-           */
-
-#ifdef CONFIG_I2C_POLLED
-          irqstate_t flags = enter_critical_section();
-#endif
-          /* Receive a byte */
-
-          *priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET);
-
-          /* Disable acknowledge when last byte is to be received */
-
-          priv->dcnt--;
-          if (priv->dcnt == 1)
-            {
-              /* autoend? */
-            }
-
-#ifdef CONFIG_I2C_POLLED
-          leave_critical_section(flags);
-#endif
-        }
-    }
-
-  /* Do we have more bytes to send, enable/disable buffer interrupts
-   * (these ISRs could be replaced by DMAs)
-   */
-
-#ifndef CONFIG_I2C_POLLED
-  if (priv->dcnt > 0)
-    {
-      stm32_i2c_traceevent(priv, I2CEVENT_REITBUFEN, 0);
-      stm32_i2c_enableinterrupts(priv);
-    }
-  else if ((priv->dcnt == 0) && (priv->msgc == 0))
-    {
-      stm32_i2c_traceevent(priv, I2CEVENT_DISITBUFEN, 0);
-      stm32_i2c_disableinterrupts(priv);
-    }
-#endif
-
-  /* Was last byte received or sent?  Hmmm... the F2 and F4 seems to differ from
-   * the F1 in that BTF is not set after data is received (only RXNE).
-   */
-
-  if (priv->dcnt <= 0 && STATUS_TC(status))
-    {
-      /* ??? */
-
-      /* Do we need to terminate or restart after this byte?
-       * If there are more messages to send, then we may:
-       *
-       *  - continue with repeated start
-       *  - or just continue sending writeable part
-       *  - or we close down by sending the stop bit
-       */
-
-      if (priv->msgc > 0)
-        {
-          if (priv->msgv->flags & I2C_M_NOSTART)
-            {
-              stm32_i2c_traceevent(priv, I2CEVENT_BTFNOSTART, priv->msgc);
-              priv->ptr   = priv->msgv->buffer;
-              priv->dcnt  = priv->msgv->length;
-              priv->flags = priv->msgv->flags;
-              priv->msgv++;
-              priv->msgc--;
-
-              /* Restart this ISR! */
-
-#ifndef CONFIG_I2C_POLLED
-              stm32_i2c_enableinterrupts(priv);
-#endif
-            }
-          else
-            {
-              stm32_i2c_traceevent(priv, I2CEVENT_BTFRESTART, priv->msgc);
-              /* ??? */
-              stm32_i2c_sendstart(priv);
-            }
-        }
-      else if (priv->msgv)
-        {
-          stm32_i2c_traceevent(priv, I2CEVENT_BTFSTOP, 0);
-
-          stm32_i2c_sendstop(priv);
-
-          /* Is there a thread waiting for this event (there should be) */
-
-#ifndef CONFIG_I2C_POLLED
-          if (priv->intstate == INTSTATE_WAITING)
-            {
-              /* Yes.. inform the thread that the transfer is complete
-               * and wake it up.
-               */
-
-              nxsem_post(&priv->sem_isr);
-              priv->intstate = INTSTATE_DONE;
-            }
-#else
-          priv->intstate = INTSTATE_DONE;
-#endif
-
-          /* Mark that we have stopped with this transaction */
-
-          priv->msgv = NULL;
-        }
-    }
-
-  /* Check for errors, in which case, stop the transfer and return
-   * Note that in master reception mode AF becomes set on last byte
-   * since ACK is not returned. We should ignore this error.
-   */
-
-  if ((status & I2C_ISR_ERRORMASK) != 0)
-    {
-      stm32_i2c_traceevent(priv, I2CEVENT_ERROR, 0);
-
-      /* Clear interrupt flags */
-
-      stm32_i2c_clearinterrupts(priv);
-
-      /* Is there a thread waiting for this event (there should be) */
-
-#ifndef CONFIG_I2C_POLLED
-      if (priv->intstate == INTSTATE_WAITING)
-        {
-          /* Yes.. inform the thread that the transfer is complete
-           * and wake it up.
-           */
-
-          nxsem_post(&priv->sem_isr);
-          priv->intstate = INTSTATE_DONE;
-        }
-#else
-      priv->intstate = INTSTATE_DONE;
-#endif
-    }
-
-  priv->status = status;
-  return OK;
-}
-
-/************************************************************************************
- * Name: stm32_i2c_isr
- *
- * Description:
- *   Common I2C interrupt service routine
- *
- ************************************************************************************/
-
-#ifndef CONFIG_I2C_POLLED
-static int stm32_i2c_isr(int irq, void *context, FAR void *arg)
-{
-  struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg;
-
-  DEBUGASSERT(priv != NULL);
-  return stm32_i2c_isr_process(priv);
-}
-#endif
-
-/************************************************************************************
- * Name: stm32_i2c_init
- *
- * Description:
- *   Setup the I2C hardware, ready for operation with defaults
- *
- ************************************************************************************/
-
-static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
-{
-  /* Power-up and configure GPIOs */
-
-  /* Enable power and reset the peripheral */
-
-  modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit);
-  modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit);
-  modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0);
-
-  /* Configure pins */
-
-  if (stm32_configgpio(priv->config->scl_pin) < 0)
-    {
-      return ERROR;
-    }
-
-  if (stm32_configgpio(priv->config->sda_pin) < 0)
-    {
-      stm32_unconfiggpio(priv->config->scl_pin);
-      return ERROR;
-    }
-
-  /* Attach ISRs */
-
-#ifndef CONFIG_I2C_POLLED
-  irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv);
-  irq_attach(priv->config->er_irq, stm32_i2c_isr, priv);
-  up_enable_irq(priv->config->ev_irq);
-  up_enable_irq(priv->config->er_irq);
-#endif
-
-  /* Set peripheral frequency, where it must be at least 2 MHz  for 100 kHz
-   * or 4 MHz for 400 kHz.  This also disables all I2C interrupts.
-   */
-
-  /* Force a frequency update */
-
-  priv->frequency = 0;
-
-  /* TODO: f303 i2c clock source RCC_CFGR3 */
-  /* RCC_CFGR3_I2C1SW (default is HSI clock) */
-
-  stm32_i2c_setclock(priv, 100000);
-
-  /* Enable I2C */
-
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
-  return OK;
-}
-
-/************************************************************************************
- * Name: stm32_i2c_deinit
- *
- * Description:
- *   Shutdown the I2C hardware
- *
- ************************************************************************************/
-
-static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv)
-{
-  /* Disable I2C */
-
-  stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0);
-
-  /* Unconfigure GPIO pins */
-
-  stm32_unconfiggpio(priv->config->scl_pin);
-  stm32_unconfiggpio(priv->config->sda_pin);
-
-  /* Disable and detach interrupts */
-
-#ifndef CONFIG_I2C_POLLED
-  up_disable_irq(priv->config->ev_irq);
-  up_disable_irq(priv->config->er_irq);
-  irq_detach(priv->config->ev_irq);
-  irq_detach(priv->config->er_irq);
-#endif
-
-  /* Disable clocking */
-
-  modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0);
-  return OK;
-}
-
-/************************************************************************************
- * Device Driver Operations
- ************************************************************************************/
-
-/************************************************************************************
- * Name: stm32_i2c_transfer
- *
- * Description:
- *   Generic I2C transfer function
- *
- ************************************************************************************/
-
-static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
-                              int count)
-{
-  FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev;
-  uint32_t status = 0;
-  int ret = OK;
-
-  DEBUGASSERT(dev != NULL && msgs != NULL && count > 0);
-
-  /* Ensure that address or flags don't change meanwhile */
-
-  stm32_i2c_sem_wait(priv);
-
-  /* Wait for any STOP in progress. */
-
-  stm32_i2c_sem_waitstop(priv);
-
-  /* Clear any pending error interrupts */
-
-  stm32_i2c_clearinterrupts(priv);
-
-  /* "Note: When the STOP, START or PEC bit is set, the software must
-   *  not perform any write access to I2C_CR1 before this bit is
-   *  cleared by hardware. Otherwise there is a risk of setting a
-   *  second STOP, START or PEC request."  However, if the bits are
-   *  not cleared by hardware, then we will have to do that from hardware.
-   */
-
-  stm32_i2c_clrstart(priv);
-
-  /* Old transfers are done */
-
-  priv->msgv = msgs;
-  priv->msgc = count;
-
-  /* Reset I2C trace logic */
-
-  stm32_i2c_tracereset(priv);
-
-  /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !)
-   * REVISIT: Note that the frequency is set only on the first message.
-   * This could be extended to support different transfer frequencies for
-   * each message segment.
-   */
-
-  stm32_i2c_setclock(priv, msgs->frequency);
-
-  /* Trigger start condition, then the process moves into the ISR.  I2C
-   * interrupts will be enabled within stm32_i2c_waitdone().
-   */
-
-  priv->status = 0;
-
-#ifndef CONFIG_I2C_POLLED
-  stm32_i2c_enableinterrupts(priv);
-#endif
-
-  stm32_i2c_sendstart(priv);
-
-  /* Wait for an ISR, if there was a timeout, fetch latest status to get
-   * the BUSY flag.
-   */
-
-  if (stm32_i2c_sem_waitdone(priv) < 0)
-    {
-      status = stm32_i2c_getstatus(priv);
-      ret = -ETIMEDOUT;
-
-      i2cerr("ERROR: Timed out: CR1: %04x status: %08x\n",
-             stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status);
-
-      /* "Note: When the STOP, START or PEC bit is set, the software must
-       *  not perform any write access to I2C_CR1 before this bit is
-       *  cleared by hardware. Otherwise there is a risk of setting a
-       *  second STOP, START or PEC request."
-       */
-
-      stm32_i2c_clrstart(priv);
-
-      /* Clear busy flag in case of timeout */
-
-      status = priv->status & 0xffff;
-    }
-  else
-    {
-      /* clear SR2 (BUSY flag) as we've done successfully */
-
-      status = priv->status & 0xffff;
-    }
-
-  status &= ~I2C_ISR_BUSY;
-#if 0
-  /* Refresh status */
-  do
-    {
-      status = stm32_i2c_getstatus(priv);
-    }
-  while (STATUS_BUSY(status));
-#endif
-
-  /* Check for error status conditions */
-
-  if ((status & I2C_ISR_ERRORMASK) != 0)
-    {
-      /* I2C_SR1_ERRORMASK is the 'OR' of the following individual bits: */
-
-      if (status & I2C_INT_BERR)
-        {
-          /* Bus Error */
-
-          ret = -EIO;
-        }
-      else if (status & I2C_INT_ARLO)
-        {
-          /* Arbitration Lost (master mode) */
-
-          ret = -EAGAIN;
-        }
-
-      /* TODO Acknowledge failure */
-
-      else if (status & I2C_INT_OVR)
-        {
-          /* Overrun/Underrun */
-
-          ret = -EIO;
-        }
-      else if (status & I2C_INT_PECERR)
-        {
-          /* PEC Error in reception */
-
-          ret = -EPROTO;
-        }
-      else if (status & I2C_INT_TIMEOUT)
-        {
-          /* Timeout or Tlow Error */
-
-          ret = -ETIME;
-        }
-
-      /* This is not an error and should never happen since SMBus is not
-       * enabled
-       */
-
-      else /* if (status & I2C_INT_ALERT) */
-        {
-          /* SMBus alert is an optional signal with an interrupt line for devices
-           * that want to trade their ability to master for a pin.
-           */
-
-          ret = -EINTR;
-        }
-    }
-
-  /* This is not an error, but should not happen.  The BUSY signal can hang,
-   * however, if there are unhealthy devices on the bus that need to be reset.
-   * NOTE:  We will only see this buy indication if stm32_i2c_sem_waitdone()
-   * fails above;  Otherwise it is cleared.
-   */
-
-  else if ((status & I2C_ISR_BUSY) != 0)
-    {
-      /* I2C Bus is for some reason busy */
-
-      ret = -EBUSY;
-    }
-
-  /* Dump the trace result */
-
-  stm32_i2c_tracedump(priv);
-  stm32_i2c_sem_post(priv);
-  return ret;
-}
-
-/************************************************************************************
- * Name: stm32_i2c_reset
- *
- * Description:
- *   Perform an I2C bus reset in an attempt to break loose stuck I2C devices.
- *
- * Input Parameters:
- *   dev   - Device-specific state data
- *
- * Returned Value:
- *   Zero (OK) on success; a negated errno value on failure.
- *
- ************************************************************************************/
-
-#ifdef CONFIG_I2C_RESET
-static int stm32_i2c_reset(FAR struct i2c_master_s * dev)
-{
-  FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev;
-  unsigned int clock_count;
-  unsigned int stretch_count;
-  uint32_t scl_gpio;
-  uint32_t sda_gpio;
-  uint32_t frequency;
-  int ret = ERROR;
-
-  DEBUGASSERT(dev);
-
-  /* Our caller must own a ref */
-
-  DEBUGASSERT(priv->refs > 0);
-
-  /* Lock out other clients */
-
-  stm32_i2c_sem_wait(priv);
-
-  /* Save the current frequency */
-
-  frequency = priv->frequency;
-
-  /* De-init the port */
-
-  stm32_i2c_deinit(priv);
-
-  /* Use GPIO configuration to un-wedge the bus */
-
-  scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin);
-  sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin);
-
-  /* Let SDA go high */
-
-  stm32_gpiowrite(sda_gpio, 1);
-
-  /* Clock the bus until any slaves currently driving it let it go. */
-
-  clock_count = 0;
-  while (!stm32_gpioread(sda_gpio))
-    {
-      /* Give up if we have tried too hard */
-
-      if (clock_count++ > 10)
-        {
-          goto out;
-        }
-
-      /* Sniff to make sure that clock stretching has finished.
-       *
-       * If the bus never relaxes, the reset has failed.
-       */
-
-      stretch_count = 0;
-      while (!stm32_gpioread(scl_gpio))
-        {
-          /* Give up if we have tried too hard */
-
-          if (stretch_count++ > 10)
-            {
-              goto out;
-            }
-
-          up_udelay(10);
-        }
-
-      /* Drive SCL low */
-
-      stm32_gpiowrite(scl_gpio, 0);
-      up_udelay(10);
-
-      /* Drive SCL high again */
-
-      stm32_gpiowrite(scl_gpio, 1);
-      up_udelay(10);
-    }
-
-  /* Generate a start followed by a stop to reset slave
-   * state machines.
-   */
-
-  stm32_gpiowrite(sda_gpio, 0);
-  up_udelay(10);
-  stm32_gpiowrite(scl_gpio, 0);
-  up_udelay(10);
-  stm32_gpiowrite(scl_gpio, 1);
-  up_udelay(10);
-  stm32_gpiowrite(sda_gpio, 1);
-  up_udelay(10);
-
-  /* Revert the GPIO configuration. */
-
-  stm32_unconfiggpio(sda_gpio);
-  stm32_unconfiggpio(scl_gpio);
-
-  /* Re-init the port */
-
-  stm32_i2c_init(priv);
-
-  /* Restore the frequency */
-
-  stm32_i2c_setclock(priv, frequency);
-  ret = OK;
-
-out:
-
-  /* Release the port for re-use by other clients */
-
-  stm32_i2c_sem_post(priv);
-  return ret;
-}
-#endif /* CONFIG_I2C_RESET */
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Name: stm32_i2cbus_initialize
- *
- * Description:
- *   Initialize one I2C bus
- *
- ************************************************************************************/
-
-FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
-{
-  struct stm32_i2c_priv_s * priv = NULL;  /* private data of device with multiple instances */
-  irqstate_t flags;
-
-#if STM32_PCLK1_FREQUENCY < 4000000
-#   warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation.
-#endif
-
-#if STM32_PCLK1_FREQUENCY < 2000000
-#   warning STM32_I2C_INIT: Peripheral clock must be at least 2 MHz to support 100 kHz operation.
-  return NULL;
-#endif
-
-  /* Get I2C private structure */
-
-  switch (port)
-    {
-#ifdef CONFIG_STM32_I2C1
-      case 1:
-        priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv;
-        break;
-#endif
-#ifdef CONFIG_STM32_I2C2
-      case 2:
-        priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv;
-        break;
-#endif
-#ifdef CONFIG_STM32_I2C3
-      case 3:
-        priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv;
-        break;
-#endif
-      default:
-        return NULL;
-    }
-
-  /* Init private data for the first time, increment refs count,
-   * power-up hardware and configure GPIOs.
-   */
-
-  flags = enter_critical_section();
-
-  if ((volatile int)priv->refs++ == 0)
-    {
-      stm32_i2c_sem_init(priv);
-      stm32_i2c_init(priv);
-    }
-
-  leave_critical_section(flags);
-  return (struct i2c_master_s *)priv;
-}
-
-/************************************************************************************
- * Name: stm32_i2cbus_uninitialize
- *
- * Description:
- *   Uninitialize an I2C bus
- *
- ************************************************************************************/
-
-int stm32_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
-{
-  FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev;
-  irqstate_t flags;
-
-  DEBUGASSERT(dev);
-
-  /* Decrement refs and check for underflow */
-
-  if (priv->refs == 0)
-    {
-      return ERROR;
-    }
-
-  flags = enter_critical_section();
-
-  if (--priv->refs)
-    {
-      leave_critical_section(flags);
-      return OK;
-    }
-
-  leave_critical_section(flags);
-
-  /* Disable power and other HW resource (GPIO's) */
-
-  stm32_i2c_deinit(priv);
-
-  /* Release unused resources */
-
-  stm32_i2c_sem_destroy(priv);
-  return OK;
-}
-
-#endif /* CONFIG_STM32_STM32F30XX */
-#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */
diff --git a/arch/arm/src/stm32f0l0/Kconfig b/arch/arm/src/stm32f0l0/Kconfig
deleted file mode 100644
index 7343e272781..00000000000
--- a/arch/arm/src/stm32f0l0/Kconfig
+++ /dev/null
@@ -1,1680 +0,0 @@
-#
-# For a description of the syntax of this configuration file,
-# see the file kconfig-language.txt in the NuttX tools repository.
-#
-
-comment "STM32F0/L0 Configuration Options"
-
-choice
-	prompt "ST STM32F0/L0 Chip Selection"
-	default ARCH_CHIP_STM32F051R8 if ARCH_CHIP_STM32F0
-	default ARCH_CHIP_STM32L073RZ if !ARCH_CHIP_STM32F0 && ARCH_CHIP_STM32L0
-	depends on ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32F030C6
-	bool "STM32F030C6"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_VALUELINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F030C8
-	bool "STM32F030C8"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_VALUELINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F030CC
-	bool "STM32F030CC"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_VALUELINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F030F4
-	bool "STM32F030F4"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_VALUELINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F030K6
-	bool "STM32F030K6"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_VALUELINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F030R8
-	bool "STM32F030R8"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_VALUELINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F030RC
-	bool "STM32F030RC"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_VALUELINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F031C4
-	bool "STM32F031C4"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F031C6
-	bool "STM32F031C6"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F031E6
-	bool "STM32F031E6"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F031F4
-	bool "STM32F031F4"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F031F6
-	bool "STM32F031F6"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F031G4
-	bool "STM32F031G4"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F031G6
-	bool "STM32F031G6"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F031K4
-	bool "STM32F031K4"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F031K6
-	bool "STM32F031K6"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F038C6
-	bool "STM32F038C6"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F038E6
-	bool "STM32F038E6"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F038F6
-	bool "STM32F038F6"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F038G6
-	bool "STM32F038G6"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F038K6
-	bool "STM32F038K6"
-	select STM32F0L0_STM32F03X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F042C4
-	bool "STM32F042C4"
-	select STM32F0L0_STM32F04X
-	select STM32F0L0_USBLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F042C6
-	bool "STM32F042C6"
-	select STM32F0L0_STM32F04X
-	select STM32F0L0_USBLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F042F4
-	bool "STM32F042F4"
-	select STM32F0L0_STM32F04X
-	select STM32F0L0_USBLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F042F6
-	bool "STM32F042F6"
-	select STM32F0L0_STM32F04X
-	select STM32F0L0_USBLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F042G4
-	bool "STM32F042G4"
-	select STM32F0L0_STM32F04X
-	select STM32F0L0_USBLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F042G6
-	bool "STM32F042G6"
-	select STM32F0L0_STM32F04X
-	select STM32F0L0_USBLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F042K4
-	bool "STM32F042K4"
-	select STM32F0L0_STM32F04X
-	select STM32F0L0_USBLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F042K6
-	bool "STM32F042K6"
-	select STM32F0L0_STM32F04X
-	select STM32F0L0_USBLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F042T6
-	bool "STM32F042T6"
-	select STM32F0L0_STM32F04X
-	select STM32F0L0_USBLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F048C6
-	bool "STM32F048C6"
-	select STM32F0L0_STM32F04X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F048G6
-	bool "STM32F048G6"
-	select STM32F0L0_STM32F04X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F048T6
-	bool "STM32F048T6"
-	select STM32F0L0_STM32F04X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F051C4
-	bool "STM32F051C4"
-	select STM32F0L0_STM32F05X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F051C6
-	bool "STM32F051C6"
-	select STM32F0L0_STM32F05X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F051C8
-	bool "STM32F051C8"
-	select STM32F0L0_STM32F05X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F051K4
-	bool "STM32F051K4"
-	select STM32F0L0_STM32F05X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F051K6
-	bool "STM32F051K6"
-	select STM32F0L0_STM32F05X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F051K8
-	bool "STM32F051K8"
-	select STM32F0L0_STM32F05X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F051R4
-	bool "STM32F051R4"
-	select STM32F0L0_STM32F05X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F051R6
-	bool "STM32F051R6"
-	select STM32F0L0_STM32F05X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F051R8
-	bool "STM32F051R8"
-	select STM32F0L0_STM32F05X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F051T8
-	bool "STM32F051T8"
-	select STM32F0L0_STM32F05X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F058C8
-	bool "STM32F058C8"
-	select STM32F0L0_STM32F05X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F058R8
-	bool "STM32F058R8"
-	select STM32F0L0_STM32F05X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F058T8
-	bool "STM32F058T8"
-	select STM32F0L0_STM32F05X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F070C6
-	bool "STM32F070C6"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_VALUELINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F070CB
-	bool "STM32F070CB"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_VALUELINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F070F6
-	bool "STM32F070F6"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_VALUELINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F070RB
-	bool "STM32F070RB"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_VALUELINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F071C8
-	bool "STM32F071C8"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F071CB
-	bool "STM32F071CB"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F071RB
-	bool "STM32F071RB"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F071V8
-	bool "STM32F071V8"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F071VB
-	bool "STM32F071VB"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F072C8
-	bool "STM32F072C8"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_USBLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F072CB
-	bool "STM32F072CB"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_USBLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F072R8
-	bool "STM32F072R8"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_USBLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F072RB
-	bool "STM32F072RB"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_USBLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F072V8
-	bool "STM32F072V8"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_USBLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F072VB
-	bool "STM32F072VB"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_USBLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F078CB
-	bool "STM32F078CB"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F078RB
-	bool "STM32F078RB"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F078VB
-	bool "STM32F078VB"
-	select STM32F0L0_STM32F07X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F091CB
-	bool "STM32F091CB"
-	select STM32F0L0_STM32F09X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F091CC
-	bool "STM32F091CC"
-	select STM32F0L0_STM32F09X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F091RB
-	bool "STM32F091RB"
-	select STM32F0L0_STM32F09X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F091RC
-	bool "STM32F091RC"
-	select STM32F0L0_STM32F09X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F091VB
-	bool "STM32F091VB"
-	select STM32F0L0_STM32F09X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F091VC
-	bool "STM32F091VC"
-	select STM32F0L0_STM32F09X
-	select STM32F0L0_ACCESSLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F098CC
-	bool "STM32F098CC"
-	select STM32F0L0_STM32F09X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F098RC
-	bool "STM32F098RC"
-	select STM32F0L0_STM32F09X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32F098VC
-	bool "STM32F098VC"
-	select STM32F0L0_STM32F09X
-	select STM32F0L0_LOWVOLTLINE
-	depends on ARCH_CHIP_STM32F0
-
-config ARCH_CHIP_STM32L072V8
-	bool "STM32L072V8"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32L072VB
-	bool "STM32L072VB"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32L072VZ
-	bool "STM32L072VZ"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32L072KB
-	bool "STM32L072KB"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32L072KZ
-	bool "STM32L072KZ"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32L072CB
-	bool "STM32L072CB"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32L072CZ
-	bool "STM32L072CZ"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32L072RB
-	bool "STM32L072RB"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32L072RZ
-	bool "STM32L072RZ"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32L073V8
-	bool "STM32L073V8"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32L073VB
-	bool "STM32L073VB"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32L073VZ
-	bool "STM32L073VZ"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32L073CB
-	bool "STM32L073CB"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32L073CZ
-	bool "STM32L073CZ"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32L073RB
-	bool "STM32L073RB"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-config ARCH_CHIP_STM32L073RZ
-	bool "STM32L073RZ"
-	select STM32F0L0_STM32L0
-	depends on ARCH_CHIP_STM32L0
-
-endchoice # ST STM32F0/L0 Chip Selection
-
-config ARCH_FAMILY_STM32F0XX
-	bool
-
-choice
-	prompt "Override Flash Size Designator"
-	default STM32F0L0_FLASH_CONFIG_DEFAULT
-	depends on ARCH_CHIP_STM32
-	---help---
-		STM32F series parts numbering (sans the package type) ends with a number or letter
-		that designates the FLASH size.
-
-			Designator  Size in KiB
-				4    16
-				6    32
-				8    64
-				B    128
-				C    256
-				D    384
-				E    512
-				F    768
-				G    1024
-				I    2048
-
-		This configuration option defaults to using the configuration based on that designator
-		or the default smaller size if there is no last character designator is present in the
-		STM32 Chip Selection.
-
-		Examples:
-			If the STM32F407VE is chosen, the Flash configuration would be 'E', if a variant of
-			the part with a  2048 KiB Flash is released in the future one could simply select
-			the 'I' designator here.
-
-			If an STM32F42xxx or  Series parts is chosen the default Flash configuration will be 'G'
-			and can be set herein to 'I' to choose the larger FLASH part.
-
-config STM32F0L0_FLASH_CONFIG_DEFAULT
-	bool "Default"
-
-config STM32F0L0_FLASH_CONFIG_4
-	bool "4 16KiB"
-
-config STM32F0L0_FLASH_CONFIG_6
-	bool "6 32KiB"
-
-config STM32F0L0_FLASH_CONFIG_8
-	bool "8 64KiB"
-
-config STM32F0L0_FLASH_CONFIG_B
-	bool "B 128KiB"
-
-config STM32F0L0_FLASH_CONFIG_C
-	bool "C 256KiB"
-
-config STM32F0L0_FLASH_CONFIG_D
-	bool "D 384KiB"
-
-config STM32F0L0_FLASH_CONFIG_E
-	bool "E 512KiB"
-
-config STM32F0L0_FLASH_CONFIG_F
-	bool "F 768KiB"
-
-config STM32F0L0_FLASH_CONFIG_G
-	bool "G 1024KiB"
-
-config STM32F0L0_FLASH_CONFIG_I
-	bool "I 2048KiB"
-
-endchoice
-
-config STM32F0L0_STM32F0
-	bool
-	default n
-
-config STM32F0L0_STM32L0
-	bool
-	select STM32F0L0_ENERGYLITE
-	default n
-
-config STM32F0L0_STM32F03X
-	bool
-	default n
-	select STM32F0L0_STM32F0
-
-config STM32F0L0_STM32F04X
-	bool
-	default n
-	select STM32F0L0_STM32F0
-
-config STM32F0L0_STM32F05X
-	bool
-	default n
-	select STM32F0L0_STM32F0
-
-config STM32F0L0_STM32F07X
-	bool
-	default n
-	select STM32F0L0_STM32F0
-
-config STM32F0L0_STM32F09X
-	bool
-	default n
-	select STM32F0L0_STM32F0
-	select STM32F0L0_HAVE_HSI48
-
-config STM32F0L0_VALUELINE
-	bool
-	default n
-	select STM32F0L0_HAVE_USART3
-	select STM32F0L0_HAVE_USART4
-	select STM32F0L0_HAVE_USART5
-	select STM32F0L0_HAVE_TIM1
-	select STM32F0L0_HAVE_TIM2
-	select STM32F0L0_HAVE_TIM3
-	select STM32F0L0_HAVE_TIM6
-	select STM32F0L0_HAVE_TIM7
-	select STM32F0L0_HAVE_TIM14
-	select STM32F0L0_HAVE_TIM15
-	select STM32F0L0_HAVE_TIM16
-	select STM32F0L0_HAVE_TIM17
-	select STM32F0L0_HAVE_SPI2 if STM32F0L0_HIGHDENSITY
-	select STM32F0L0_HAVE_SPI3 if STM32F0L0_HIGHDENSITY
-
-config STM32F0L0_ACCESSLINE
-	bool
-	default n
-	select STM32F0L0_HAVE_USART3
-	select STM32F0L0_HAVE_USART4
-	select STM32F0L0_HAVE_USART5
-	select STM32F0L0_HAVE_TIM1
-	select STM32F0L0_HAVE_TIM2
-	select STM32F0L0_HAVE_TIM3
-	select STM32F0L0_HAVE_TIM6
-	select STM32F0L0_HAVE_TIM7
-	select STM32F0L0_HAVE_TIM14
-	select STM32F0L0_HAVE_TIM15
-	select STM32F0L0_HAVE_TIM16
-	select STM32F0L0_HAVE_TIM17
-	select STM32F0L0_HAVE_ADC2
-	select STM32F0L0_HAVE_CAN1
-	select STM32F0L0_HAVE_SPI2
-	select STM32F0L0_HAVE_SPI3
-
-config STM32F0L0_LOWVOLTLINE
-	bool
-	default n
-	select STM32F0L0_HAVE_USART3
-	select STM32F0L0_HAVE_USART4
-	select STM32F0L0_HAVE_USART5
-	select STM32F0L0_HAVE_TIM1
-	select STM32F0L0_HAVE_TIM2
-	select STM32F0L0_HAVE_TIM3
-	select STM32F0L0_HAVE_TIM6
-	select STM32F0L0_HAVE_TIM7
-	select STM32F0L0_HAVE_TIM14
-	select STM32F0L0_HAVE_TIM15
-	select STM32F0L0_HAVE_TIM16
-	select STM32F0L0_HAVE_TIM17
-	select STM32F0L0_HAVE_ADC2
-	select STM32F0L0_HAVE_CAN1
-	select STM32F0L0_HAVE_SPI2
-	select STM32F0L0_HAVE_SPI3
-
-config STM32F0L0_USBLINE
-	bool
-	default n
-	select STM32F0L0_HAVE_HSI48
-	select STM32F0L0_HAVE_USART3
-	select STM32F0L0_HAVE_USART4
-	select STM32F0L0_HAVE_TIM1
-	select STM32F0L0_HAVE_TIM2
-	select STM32F0L0_HAVE_TIM3
-	select STM32F0L0_HAVE_TIM6
-	select STM32F0L0_HAVE_TIM7
-	select STM32F0L0_HAVE_TIM14
-	select STM32F0L0_HAVE_TIM15
-	select STM32F0L0_HAVE_TIM16
-	select STM32F0L0_HAVE_TIM17
-	select STM32F0L0_HAVE_ADC2
-	select STM32F0L0_HAVE_CAN1
-	select STM32F0L0_HAVE_SPI2
-	select STM32F0L0_HAVE_SPI3
-	select STM32F0L0_HAVE_USBDEV
-
-config STM32F0L0_ENERGYLITE
-	bool
-	default n
-
-config STM32F0L0_DFU
-	bool "DFU bootloader"
-	default n
-	depends on !STM32F0L0_VALUELINE
-	---help---
-		Configure and position code for use with the STMicro DFU bootloader.  Do
-		not select this option if you will load code using JTAG/SWM.
-
-choice
-	prompt "SysTick clock source"
-	default STM32F0L0_SYSTICK_CORECLK
-
-config STM32F0L0_SYSTICK_CORECLK
-	bool "Cortex-M0 core clock"
-
-config STM32F0L0_SYSTICK_CORECLK_DIV16
-	bool "Cortex-M0 core clock divided by 16"
-
-endchoice
-
-
-menu "STM32 Peripheral Support"
-
-# These "hidden" settings determine is a peripheral option is available for the
-# selection MCU
-
-config STM32F0L0_HAVE_CCM
-	bool
-	default n
-
-config STM32F0L0_HAVE_HSI48
-	bool
-	default n
-
-config STM32F0L0_HAVE_USBDEV
-	bool
-	default n
-
-config STM32F0L0_HAVE_FSMC
-	bool
-	default n
-
-config STM32F0L0_HAVE_USART3
-	bool
-	default n
-
-config STM32F0L0_HAVE_USART4
-	bool
-	default n
-
-config STM32F0L0_HAVE_USART5
-	bool
-	default n
-
-config STM32F0L0_HAVE_USART6
-	bool
-	default n
-
-config STM32F0L0_HAVE_USART7
-	bool
-	default n
-
-config STM32F0L0_HAVE_USART8
-	bool
-	default n
-
-config STM32F0L0_HAVE_TIM1
-	bool
-	default n
-
-config STM32F0L0_HAVE_TIM2
-	bool
-	default n
-
-config STM32F0L0_HAVE_TIM3
-	bool
-	default n
-
-config STM32F0L0_HAVE_TIM6
-	bool
-	default n
-
-config STM32F0L0_HAVE_TIM7
-	bool
-	default n
-
-config STM32F0L0_HAVE_TIM14
-	bool
-	default n
-
-config STM32F0L0_HAVE_TIM15
-	bool
-	default n
-
-config STM32F0L0_HAVE_TIM16
-	bool
-	default n
-
-config STM32F0L0_HAVE_TIM17
-	bool
-	default n
-
-config STM32F0L0_HAVE_TSC
-	bool
-	default n
-
-config STM32F0L0_HAVE_ADC2
-	bool
-	default n
-
-config STM32F0L0_HAVE_ADC3
-	bool
-	default n
-
-config STM32F0L0_HAVE_ADC4
-	bool
-	default n
-
-config STM32F0L0_HAVE_ADC1_DMA
-	bool
-	default n
-
-config STM32F0L0_HAVE_ADC2_DMA
-	bool
-	default n
-
-config STM32F0L0_HAVE_ADC3_DMA
-	bool
-	default n
-
-config STM32F0L0_HAVE_ADC4_DMA
-	bool
-	default n
-
-config STM32F0L0_HAVE_SDADC1
-	bool
-	default n
-
-config STM32F0L0_HAVE_SDADC2
-	bool
-	default n
-
-config STM32F0L0_HAVE_SDADC3
-	bool
-	default n
-
-config STM32F0L0_HAVE_SDADC1_DMA
-	bool
-	default n
-
-config STM32F0L0_HAVE_SDADC2_DMA
-	bool
-	default n
-
-config STM32F0L0_HAVE_SDADC3_DMA
-	bool
-	default n
-
-config STM32F0L0_HAVE_CAN1
-	bool
-	default n
-
-config STM32F0L0_HAVE_COMP1
-       bool
-       default n
-
-config STM32F0L0_HAVE_COMP2
-       bool
-       default n
-
-config STM32F0L0_HAVE_COMP3
-       bool
-       default n
-
-config STM32F0L0_HAVE_COMP4
-       bool
-       default n
-
-config STM32F0L0_HAVE_COMP5
-       bool
-       default n
-
-config STM32F0L0_HAVE_COMP6
-       bool
-       default n
-
-config STM32F0L0_HAVE_COMP7
-       bool
-       default n
-
-config STM32F0L0_HAVE_DAC1
-	bool
-	default n
-
-config STM32F0L0_HAVE_DAC2
-	bool
-	default n
-
-config STM32F0L0_HAVE_RNG
-	bool
-	default n
-
-config STM32F0L0_HAVE_I2C2
-	bool
-	default n
-
-config STM32F0L0_HAVE_I2C3
-	bool
-	default n
-
-config STM32F0L0_HAVE_SPI2
-	bool
-	default n
-
-config STM32F0L0_HAVE_SPI3
-	bool
-	default n
-
-config STM32F0L0_HAVE_SPI4
-	bool
-	default n
-
-config STM32F0L0_HAVE_SPI5
-	bool
-	default n
-
-config STM32F0L0_HAVE_SPI6
-	bool
-	default n
-
-config STM32F0L0_HAVE_SAIPLL
-	bool
-	default n
-
-config STM32F0L0_HAVE_I2SPLL
-	bool
-	default n
-
-config STM32F0L0_HAVE_OPAMP1
-       bool
-       default n
-
-config STM32F0L0_HAVE_OPAMP2
-       bool
-       default n
-
-config STM32F0L0_HAVE_OPAMP3
-       bool
-       default n
-
-config STM32F0L0_HAVE_OPAMP4
-       bool
-       default n
-
-# These are the peripheral selections proper
-
-config STM32F0L0_ADC1
-	bool "ADC1"
-	default n
-	select STM32F0L0_ADC
-
-config STM32F0L0_ADC2
-	bool "ADC2"
-	default n
-	select STM32F0L0_ADC
-	depends on STM32F0L0_HAVE_ADC2
-
-config STM32F0L0_ADC3
-	bool "ADC3"
-	default n
-	select STM32F0L0_ADC
-	depends on STM32F0L0_HAVE_ADC3
-
-config STM32F0L0_ADC4
-	bool "ADC4"
-	default n
-	select STM32F0L0_ADC
-	depends on STM32F0L0_HAVE_ADC4
-
-config STM32F0L0_SDADC1
-	bool "SDADC1"
-	default n
-	select STM32F0L0_SDADC
-	depends on STM32F0L0_HAVE_SDADC1
-
-config STM32F0L0_SDADC2
-	bool "SDADC2"
-	default n
-	select STM32F0L0_SDADC
-	depends on STM32F0L0_HAVE_SDADC2
-
-config STM32F0L0_SDADC3
-	bool "SDADC3"
-	default n
-	select STM32F0L0_SDADC
-	depends on STM32F0L0_HAVE_SDADC3
-
-config STM32F0L0_COMP
-	bool "COMP"
-	default n
-
-config STM32F0L0_COMP1
-	bool "COMP1"
-	default n
-	depends on STM32F0L0_HAVE_COMP1
-
-config STM32F0L0_COMP2
-	bool "COMP2"
-	default n
-	depends on STM32F0L0_HAVE_COMP2
-
-config STM32F0L0_COMP3
-	bool "COMP3"
-	default n
-	depends on STM32F0L0_HAVE_COMP3
-
-config STM32F0L0_COMP4
-	bool "COMP4"
-	default n
-	depends on STM32F0L0_HAVE_COMP4
-
-config STM32F0L0_COMP5
-	bool "COMP5"
-	default n
-	depends on STM32F0L0_HAVE_COMP5
-
-config STM32F0L0_COMP6
-	bool "COMP6"
-	default n
-	depends on STM32F0L0_HAVE_COMP6
-
-config STM32F0L0_COMP7
-	bool "COMP7"
-	default n
-	depends on STM32F0L0_HAVE_COMP6
-
-config STM32F0L0_BKP
-	bool "BKP"
-	default n
-
-config STM32F0L0_BKPSRAM
-	bool "Enable BKP RAM Domain"
-	default n
-
-config STM32F0L0_CAN1
-	bool "CAN1"
-	default n
-	select CAN
-	select STM32F0L0_CAN
-	depends on STM32F0L0_HAVE_CAN1
-
-config STM32F0L0_CEC
-	bool "CEC"
-	default n
-	depends on STM32F0L0_VALUELINE
-
-config STM32F0L0_CRC
-	bool "CRC"
-	default n
-
-config STM32F0L0_CRYP
-	bool "CRYP"
-	default n
-	depends on STM32F0L0_STM32F207 || STM32F0L0_STM32F40XX
-
-config STM32F0L0_DMA1
-	bool "DMA1"
-	default n
-	select ARCH_DMA
-
-config STM32F0L0_DMA2
-	bool "DMA2"
-	default n
-	select ARCH_DMA
-	depends on !STM32F0L0_VALUELINE || (STM32F0L0_VALUELINE && STM32F0L0_HIGHDENSITY)
-
-config STM32F0L0_DAC1
-	bool "DAC1"
-	default n
-	depends on STM32F0L0_HAVE_DAC1
-	select STM32F0L0_DAC
-
-config STM32F0L0_DAC2
-	bool "DAC2"
-	default n
-	depends on STM32F0L0_HAVE_DAC2
-	select STM32F0L0_DAC
-
-config STM32F0L0_FSMC
-	bool "FSMC"
-	default n
-	depends on STM32F0L0_HAVE_FSMC
-
-config STM32F0L0_HASH
-	bool "HASH"
-	default n
-	depends on STM32F0L0_STM32F207 || STM32F0L0_STM32F40XX
-
-config STM32F0L0_I2C1
-	bool "I2C1"
-	default n
-	select STM32F0L0_I2C
-
-config STM32F0L0_I2C2
-	bool "I2C2"
-	default n
-	depends on STM32F0L0_HAVE_I2C2
-	select STM32F0L0_I2C
-
-config STM32F0L0_I2C3
-	bool "I2C3"
-	default n
-	depends on STM32F0L0_HAVE_I2C3
-	select STM32F0L0_I2C
-
-config STM32F0L0_PWR
-	bool "PWR"
-	default n
-
-config STM32F0L0_RNG
-	bool "RNG"
-	default n
-	depends on STM32F0L0_HAVE_RNG
-	select ARCH_HAVE_RNG
-
-config STM32F0L0_SDIO
-	bool "SDIO"
-	default n
-	depends on !STM32F0L0_CONNECTIVITYLINE && !STM32F0L0_VALUELINE
-	select ARCH_HAVE_SDIO
-	select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
-	select ARCH_HAVE_SDIO_PREFLIGHT
-
-config STM32F0L0_SPI1
-	bool "SPI1"
-	default n
-	select SPI
-	select STM32F0L0_SPI
-
-config STM32F0L0_SPI2
-	bool "SPI2"
-	default n
-	depends on STM32F0L0_HAVE_SPI2
-	select SPI
-	select STM32F0L0_SPI
-
-config STM32F0L0_SPI3
-	bool "SPI3"
-	default n
-	depends on STM32F0L0_HAVE_SPI3
-	select SPI
-	select STM32F0L0_SPI
-
-config STM32F0L0_SPI4
-	bool "SPI4"
-	default n
-	depends on STM32F0L0_HAVE_SPI4
-	select SPI
-	select STM32F0L0_SPI
-
-config STM32F0L0_SPI5
-	bool "SPI5"
-	default n
-	depends on STM32F0L0_HAVE_SPI5
-	select SPI
-	select STM32F0L0_SPI
-
-config STM32F0L0_SPI6
-	bool "SPI6"
-	default n
-	depends on STM32F0L0_HAVE_SPI6
-	select SPI
-	select STM32F0L0_SPI
-
-config STM32F0L0_SYSCFG
-	bool "SYSCFG"
-	default y
-
-config STM32F0L0_TIM1
-	bool "TIM1"
-	default n
-	depends on STM32F0L0_HAVE_TIM1
-
-config STM32F0L0_TIM2
-	bool "TIM2"
-	default n
-
-config STM32F0L0_TIM3
-	bool "TIM3"
-	default n
-	depends on STM32F0L0_HAVE_TIM3
-
-config STM32F0L0_TIM6
-	bool "TIM6"
-	default n
-	depends on STM32F0L0_HAVE_TIM6
-
-config STM32F0L0_TIM7
-	bool "TIM7"
-	default n
-	depends on STM32F0L0_HAVE_TIM7
-
-config STM32F0L0_TIM14
-	bool "TIM14"
-	default n
-	depends on STM32F0L0_HAVE_TIM14
-
-config STM32F0L0_TIM15
-	bool "TIM15"
-	default n
-	depends on STM32F0L0_HAVE_TIM15
-
-config STM32F0L0_TIM16
-	bool "TIM16"
-	default n
-	depends on STM32F0L0_HAVE_TIM16
-
-config STM32F0L0_TIM17
-	bool "TIM17"
-	default n
-	depends on STM32F0L0_HAVE_TIM17
-
-config STM32F0L0_TSC
-	bool "TSC"
-	default n
-	depends on STM32F0L0_HAVE_TSC
-
-config STM32F0L0_USART1
-	bool "USART1"
-	default n
-	select STM32F0L0_USART
-
-config STM32F0L0_USART2
-	bool "USART2"
-	default n
-	select STM32F0L0_USART
-
-config STM32F0L0_USART3
-	bool "USART3"
-	default n
-	depends on STM32F0L0_HAVE_USART3
-	select STM32F0L0_USART
-
-config STM32F0L0_USART4
-	bool "USART4"
-	default n
-	depends on STM32F0L0_HAVE_USART4
-	select STM32F0L0_USART
-
-config STM32F0L0_USART5
-	bool "USART5"
-	default n
-	depends on STM32F0L0_HAVE_USART5
-	select STM32F0L0_USART
-
-config STM32F0L0_USART6
-	bool "USART6"
-	default n
-	depends on STM32F0L0_HAVE_USART6
-	select STM32F0L0_USART
-
-config STM32F0L0_USART7
-	bool "USART7"
-	default n
-	depends on STM32F0L0_HAVE_USART7
-	select STM32F0L0_USART
-
-config STM32F0L0_USART8
-	bool "USART8"
-	default n
-	depends on STM32F0L0_HAVE_USART8
-	select STM32F0L0_USART
-
-config STM32F0L0_USB
-	bool "USB Device"
-	default n
-	depends on STM32F0L0_HAVE_USBDEV
-	select USBDEV
-
-config STM32F0L0_IWDG
-	bool "IWDG"
-	default n
-	select WATCHDOG
-
-config STM32F0L0_WWDG
-	bool "WWDG"
-	default n
-	select WATCHDOG
-
-endmenu
-
-config STM32F0L0_ADC
-	bool
-
-config STM32F0L0_SDADC
-	bool
-
-config STM32F0L0_DAC
-	bool
-
-config STM32F0L0_SPI
-	bool
-
-config STM32F0L0_I2C
-	bool
-
-config STM32F0L0_CAN
-	bool
-
-config STM32F0L0_USART
-	bool
-
-config STM32F0L0_SERIALDRIVER
-	bool
-
-config STM32F0L0_1WIREDRIVER
-	bool
-
-menu "U[S]ART Configuration"
-	depends on STM32F0L0_USART
-
-comment "U[S]ART Device Configuration"
-
-choice
-	prompt "USART1 Driver Configuration"
-	default STM32F0L0_USART1_SERIALDRIVER
-	depends on STM32F0L0_USART1
-
-config STM32F0L0_USART1_SERIALDRIVER
-	bool "Standard serial driver"
-	select USART1_SERIALDRIVER
-	select ARCH_HAVE_SERIAL_TERMIOS
-	select STM32F0L0_SERIALDRIVER
-
-config STM32F0L0_USART1_1WIREDRIVER
-	bool "1-Wire driver"
-	select STM32F0L0_1WIREDRIVER
-
-endchoice # USART1 Driver Configuration
-
-if STM32F0L0_USART1_SERIALDRIVER
-
-config USART1_RS485
-	bool "RS-485 on USART1"
-	default n
-	---help---
-		Enable RS-485 interface on USART1. Your board config will have to
-		provide GPIO_USART1_RS485_DIR pin definition.
-
-config USART1_RS485_DIR_POLARITY
-	int "USART1 RS-485 DIR pin polarity"
-	default 1
-	range 0 1
-	depends on USART1_RS485
-	---help---
-		Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which
-		enables TX (0 - low / nTXEN, 1 - high / TXEN).
-
-endif # STM32F0L0_USART1_SERIALDRIVER
-
-choice
-	prompt "USART2 Driver Configuration"
-	default STM32F0L0_USART2_SERIALDRIVER
-	depends on STM32F0L0_USART2
-
-config STM32F0L0_USART2_SERIALDRIVER
-	bool "Standard serial driver"
-	select USART2_SERIALDRIVER
-	select ARCH_HAVE_SERIAL_TERMIOS
-	select STM32F0L0_SERIALDRIVER
-
-config STM32F0L0_USART2_1WIREDRIVER
-	bool "1-Wire driver"
-	select STM32F0L0_1WIREDRIVER
-
-endchoice # USART2 Driver Configuration
-
-if STM32F0L0_USART2_SERIALDRIVER
-
-config USART2_RS485
-	bool "RS-485 on USART2"
-	default n
-	---help---
-		Enable RS-485 interface on USART2. Your board config will have to
-		provide GPIO_USART2_RS485_DIR pin definition.
-
-config USART2_RS485_DIR_POLARITY
-	int "USART2 RS-485 DIR pin polarity"
-	default 1
-	range 0 1
-	depends on USART2_RS485
-	---help---
-		Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which
-		enables TX (0 - low / nTXEN, 1 - high / TXEN).
-
-endif # STM32F0L0_USART2_SERIALDRIVER
-
-choice
-	prompt "USART3 Driver Configuration"
-	default STM32F0L0_USART3_SERIALDRIVER
-	depends on STM32F0L0_USART3
-
-config STM32F0L0_USART3_SERIALDRIVER
-	bool "Standard serial driver"
-	select USART3_SERIALDRIVER
-	select ARCH_HAVE_SERIAL_TERMIOS
-	select STM32F0L0_SERIALDRIVER
-
-config STM32F0L0_USART3_1WIREDRIVER
-	bool "1-Wire driver"
-	select STM32F0L0_1WIREDRIVER
-
-endchoice # USART3 Driver Configuration
-
-if STM32F0L0_USART3_SERIALDRIVER
-
-config USART3_RS485
-	bool "RS-485 on USART3"
-	default n
-	---help---
-		Enable RS-485 interface on USART3. Your board config will have to
-		provide GPIO_USART3_RS485_DIR pin definition.
-
-config USART3_RS485_DIR_POLARITY
-	int "USART3 RS-485 DIR pin polarity"
-	default 1
-	range 0 1
-	depends on USART3_RS485
-	---help---
-		Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which
-		enables TX (0 - low / nTXEN, 1 - high / TXEN).
-
-endif # STM32F0L0_USART3_SERIALDRIVER
-
-
-choice
-	prompt "USART4 Driver Configuration"
-	default STM32F0L0_USART4_SERIALDRIVER
-	depends on STM32F0L0_USART4
-
-config STM32F0L0_USART4_SERIALDRIVER
-	bool "Standard serial driver"
-	select USART4_SERIALDRIVER
-	select ARCH_HAVE_SERIAL_TERMIOS
-	select STM32F0L0_SERIALDRIVER
-
-config STM32F0L0_USART4_1WIREDRIVER
-	bool "1-Wire driver"
-	select STM32F0L0_1WIREDRIVER
-
-endchoice # USART4 Driver Configuration
-
-if STM32F0L0_USART4_SERIALDRIVER
-
-config USART4_RS485
-	bool "RS-485 on USART4"
-	default n
-	---help---
-		Enable RS-485 interface on USART4. Your board config will have to
-		provide GPIO_USART4_RS485_DIR pin definition.
-
-config USART4_RS485_DIR_POLARITY
-	int "USART4 RS-485 DIR pin polarity"
-	default 1
-	range 0 1
-	depends on USART4_RS485
-	---help---
-		Polarity of DIR pin for RS-485 on USART4. Set to state on DIR pin which
-		enables TX (0 - low / nTXEN, 1 - high / TXEN).
-
-endif # STM32F0L0_USART4_SERIALDRIVER
-
-choice
-	prompt "USART5 Driver Configuration"
-	default STM32F0L0_USART5_SERIALDRIVER
-	depends on STM32F0L0_USART5
-
-config STM32F0L0_USART5_SERIALDRIVER
-	bool "Standard serial driver"
-	select USART5_SERIALDRIVER
-	select ARCH_HAVE_SERIAL_TERMIOS
-	select STM32F0L0_SERIALDRIVER
-
-config STM32F0L0_USART5_1WIREDRIVER
-	bool "1-Wire driver"
-	select STM32F0L0_1WIREDRIVER
-
-endchoice # USART5 Driver Configuration
-
-if STM32F0L0_USART5_SERIALDRIVER
-
-config USART5_RS485
-	bool "RS-485 on USART5"
-	default n
-	---help---
-		Enable RS-485 interface on USART5. Your board config will have to
-		provide GPIO_USART5_RS485_DIR pin definition.
-
-config USART5_RS485_DIR_POLARITY
-	int "USART5 RS-485 DIR pin polarity"
-	default 1
-	range 0 1
-	depends on USART5_RS485
-	---help---
-		Polarity of DIR pin for RS-485 on USART5. Set to state on DIR pin which
-		enables TX (0 - low / nTXEN, 1 - high / TXEN).
-
-endif # STM32F0L0_USART5_SERIALDRIVER
-
-
-choice
-	prompt "USART6 Driver Configuration"
-	default STM32F0L0_USART6_SERIALDRIVER
-	depends on STM32F0L0_USART6
-
-config STM32F0L0_USART6_SERIALDRIVER
-	bool "Standard serial driver"
-	select USART6_SERIALDRIVER
-	select ARCH_HAVE_SERIAL_TERMIOS
-	select STM32F0L0_SERIALDRIVER
-
-config STM32F0L0_USART6_1WIREDRIVER
-	bool "1-Wire driver"
-	select STM32F0L0_1WIREDRIVER
-
-endchoice # USART6 Driver Configuration
-
-if STM32F0L0_USART6_SERIALDRIVER
-
-config USART6_RS485
-	bool "RS-485 on USART6"
-	default n
-	---help---
-		Enable RS-485 interface on USART6. Your board config will have to
-		provide GPIO_USART6_RS485_DIR pin definition.
-
-config USART6_RS485_DIR_POLARITY
-	int "USART6 RS-485 DIR pin polarity"
-	default 1
-	range 0 1
-	depends on USART6_RS485
-	---help---
-		Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which
-		enables TX (0 - low / nTXEN, 1 - high / TXEN).
-
-endif # STM32F0L0_USART6_SERIALDRIVER
-
-choice
-	prompt "USART7 Driver Configuration"
-	default STM32F0L0_USART7_SERIALDRIVER
-	depends on STM32F0L0_USART7
-
-config STM32F0L0_USART7_SERIALDRIVER
-	bool "Standard serial driver"
-	select USART7_SERIALDRIVER
-	select ARCH_HAVE_SERIAL_TERMIOS
-	select STM32F0L0_SERIALDRIVER
-
-config STM32F0L0_USART7_1WIREDRIVER
-	bool "1-Wire driver"
-	select STM32F0L0_1WIREDRIVER
-
-endchoice # USART7 Driver Configuration
-
-if STM32F0L0_USART7_SERIALDRIVER
-
-config USART7_RS485
-	bool "RS-485 on USART7"
-	default n
-	---help---
-		Enable RS-485 interface on USART7. Your board config will have to
-		provide GPIO_USART7_RS485_DIR pin definition.
-
-config USART7_RS485_DIR_POLARITY
-	int "USART7 RS-485 DIR pin polarity"
-	default 1
-	range 0 1
-	depends on USART7_RS485
-	---help---
-		Polarity of DIR pin for RS-485 on USART7. Set to state on DIR pin which
-		enables TX (0 - low / nTXEN, 1 - high / TXEN).
-
-endif # STM32F0L0_USART7_SERIALDRIVER
-
-choice
-	prompt "USART8 Driver Configuration"
-	default STM32F0L0_USART8_SERIALDRIVER
-	depends on STM32F0L0_USART8
-
-config STM32F0L0_USART8_SERIALDRIVER
-	bool "Standard serial driver"
-	select USART8_SERIALDRIVER
-	select ARCH_HAVE_SERIAL_TERMIOS
-	select STM32F0L0_SERIALDRIVER
-
-config STM32F0L0_USART8_1WIREDRIVER
-	bool "1-Wire driver"
-	select STM32F0L0_1WIREDRIVER
-
-endchoice # USART8 Driver Configuration
-
-if STM32F0L0_USART8_SERIALDRIVER
-
-config USART8_RS485
-	bool "RS-485 on USART8"
-	default n
-	---help---
-		Enable RS-485 interface on USART8. Your board config will have to
-		provide GPIO_USART8_RS485_DIR pin definition.
-
-config USART8_RS485_DIR_POLARITY
-	int "USART8 RS-485 DIR pin polarity"
-	default 1
-	range 0 1
-	depends on USART8_RS485
-	---help---
-		Polarity of DIR pin for RS-485 on USART8. Set to state on DIR pin which
-		enables TX (0 - low / nTXEN, 1 - high / TXEN).
-
-endif # STM32F0L0_USART8_SERIALDRIVER
-
-menu "Serial Driver Configuration"
-	depends on STM32F0L0_SERIALDRIVER
-
-config STM32F0L0_SERIAL_DISABLE_REORDERING
-	bool "Disable reordering of ttySx devices."
-	default n
-	---help---
-		NuttX per default reorders the serial ports (/dev/ttySx) so that the
-		console is always on /dev/ttyS0. If more than one UART is in use this
-		can, however, have the side-effect that all port mappings
-		(hardware USART1 -> /dev/ttyS0) change if the console is moved to another
-		UART. This is in particular relevant if a project uses the USB console
-		in some configs and a serial console in other configs, but does not
-		want the side effect of having all serial port names change when just
-		the console is moved from serial to USB.
-
-config STM32F0L0_USART_SINGLEWIRE
-	bool "Single Wire Support"
-	default n
-	depends on STM32F0L0_USART
-	---help---
-		Enable single wire UART support.  The option enables support for the
-		TIOCSSINGLEWIRE ioctl in the STM32F0 serial driver.
-
-endmenu # Serial Driver Configuration
-
-if PM
-
-config STM32F0L0_PM_SERIAL_ACTIVITY
-	int "PM serial activity"
-	default 10
-	---help---
-		PM activity reported to power management logic on every serial
-		interrupt.
-
-endif
-
-endmenu
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f0_gpio.h b/arch/arm/src/stm32f0l0/hardware/stm32f0_gpio.h
deleted file mode 100644
index ffb0bc3c0a9..00000000000
--- a/arch/arm/src/stm32f0l0/hardware/stm32f0_gpio.h
+++ /dev/null
@@ -1,336 +0,0 @@
-/************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32f0_gpio.h
- *
- *   Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt 
- *           Alan Carvalho de Assis 
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_GPIO_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_GPIO_H
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-#undef STM32_GPIO_VERY_LOW_SPEED          /* No very low speed operation */
-#define STM32_HAVE_PORTF           1      /* If STM32_NPORTS > 5, then have GPIOF */
-
-/* Register Offsets *****************************************************************/
-
-#define STM32_GPIO_MODER_OFFSET    0x0000 /* GPIO port mode register */
-#define STM32_GPIO_OTYPER_OFFSET   0x0004 /* GPIO port output type register */
-#define STM32_GPIO_OSPEED_OFFSET   0x0008 /* GPIO port output speed register */
-#define STM32_GPIO_PUPDR_OFFSET    0x000c /* GPIO port pull-up/pull-down register */
-#define STM32_GPIO_IDR_OFFSET      0x0010 /* GPIO port input data register */
-#define STM32_GPIO_ODR_OFFSET      0x0014 /* GPIO port output data register */
-#define STM32_GPIO_BSRR_OFFSET     0x0018 /* GPIO port bit set/reset register */
-#define STM32_GPIO_LCKR_OFFSET     0x001c /* GPIO port configuration lock register */
-#define STM32_GPIO_AFRL_OFFSET     0x0020 /* GPIO alternate function low register */
-#define STM32_GPIO_AFRH_OFFSET     0x0024 /* GPIO alternate function high register */
-#define STM32_GPIO_BRR_OFFSET      0x0028 /* GPIO port bit reset register */
-
-/* Register Addresses ***************************************************************/
-
-#if STM32_NPORTS > 0
-#  define STM32_GPIOA_MODER        (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET)
-#  define STM32_GPIOA_OTYPER       (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET)
-#  define STM32_GPIOA_OSPEED       (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET)
-#  define STM32_GPIOA_PUPDR        (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET)
-#  define STM32_GPIOA_IDR          (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET)
-#  define STM32_GPIOA_ODR          (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET)
-#  define STM32_GPIOA_BSRR         (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET)
-#  define STM32_GPIOA_LCKR         (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET)
-#  define STM32_GPIOA_AFRL         (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET)
-#  define STM32_GPIOA_AFRH         (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET)
-#endif
-
-#if STM32_NPORTS > 1
-#  define STM32_GPIOB_MODER        (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET)
-#  define STM32_GPIOB_OTYPER       (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET)
-#  define STM32_GPIOB_OSPEED       (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET)
-#  define STM32_GPIOB_PUPDR        (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET)
-#  define STM32_GPIOB_IDR          (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET)
-#  define STM32_GPIOB_ODR          (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET)
-#  define STM32_GPIOB_BSRR         (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET)
-#  define STM32_GPIOB_LCKR         (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET)
-#  define STM32_GPIOB_AFRL         (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET)
-#  define STM32_GPIOB_AFRH         (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET)
-#endif
-
-#if STM32_NPORTS > 2
-#  define STM32_GPIOC_MODER        (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET)
-#  define STM32_GPIOC_OTYPER       (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET)
-#  define STM32_GPIOC_OSPEED       (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET)
-#  define STM32_GPIOC_PUPDR        (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET)
-#  define STM32_GPIOC_IDR          (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET)
-#  define STM32_GPIOC_ODR          (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET)
-#  define STM32_GPIOC_BSRR         (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET)
-#  define STM32_GPIOC_LCKR         (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET)
-#  define STM32_GPIOC_AFRL         (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET)
-#  define STM32_GPIOC_AFRH         (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET)
-#endif
-
-#if STM32_NPORTS > 3
-#  define STM32_GPIOD_MODER        (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET)
-#  define STM32_GPIOD_OTYPER       (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET)
-#  define STM32_GPIOD_OSPEED       (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET)
-#  define STM32_GPIOD_PUPDR        (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET)
-#  define STM32_GPIOD_IDR          (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET)
-#  define STM32_GPIOD_ODR          (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET)
-#  define STM32_GPIOD_BSRR         (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET)
-#  define STM32_GPIOD_LCKR         (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET)
-#  define STM32_GPIOD_AFRL         (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET)
-#  define STM32_GPIOD_AFRH         (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET)
-#endif
-
-#if STM32_NPORTS > 4
-#  define STM32_GPIOE_MODER        (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET)
-#  define STM32_GPIOE_OTYPER       (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET)
-#  define STM32_GPIOE_OSPEED       (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET)
-#  define STM32_GPIOE_PUPDR        (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET)
-#  define STM32_GPIOE_IDR          (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET)
-#  define STM32_GPIOE_ODR          (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET)
-#  define STM32_GPIOE_BSRR         (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET)
-#  define STM32_GPIOE_LCKR         (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET)
-#  define STM32_GPIOE_AFRL         (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET)
-#  define STM32_GPIOE_AFRH         (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET)
-#endif
-
-#if STM32_NPORTS > 5
-#  define STM32_GPIOF_MODER        (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET)
-#  define STM32_GPIOF_OTYPER       (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET)
-#  define STM32_GPIOF_OSPEED       (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET)
-#  define STM32_GPIOF_PUPDR        (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET)
-#  define STM32_GPIOF_IDR          (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET)
-#  define STM32_GPIOF_ODR          (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET)
-#  define STM32_GPIOF_BSRR         (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET)
-#  define STM32_GPIOF_LCKR         (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET)
-#  define STM32_GPIOF_AFRL         (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET)
-#  define STM32_GPIOF_AFRH         (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET)
-#endif
-
-/* Register Bitfield Definitions ****************************************************/
-
-/* GPIO port mode register */
-
-#define GPIO_MODER_INPUT           (0) /* Input */
-#define GPIO_MODER_OUTPUT          (1) /* General purpose output mode */
-#define GPIO_MODER_ALT             (2) /* Alternate mode */
-#define GPIO_MODER_ANALOG          (3) /* Analog mode */
-
-#define GPIO_MODER_SHIFT(n)        ((n) << 1)
-#define GPIO_MODER_MASK(n)         (3 << GPIO_MODER_SHIFT(n))
-
-#define GPIO_MODER0_SHIFT          (0)
-#define GPIO_MODER0_MASK           (3 << GPIO_MODER0_SHIFT)
-#define GPIO_MODER1_SHIFT          (2)
-#define GPIO_MODER1_MASK           (3 << GPIO_MODER1_SHIFT)
-#define GPIO_MODER2_SHIFT          (4)
-#define GPIO_MODER2_MASK           (3 << GPIO_MODER2_SHIFT)
-#define GPIO_MODER3_SHIFT          (6)
-#define GPIO_MODER3_MASK           (3 << GPIO_MODER3_SHIFT)
-#define GPIO_MODER4_SHIFT          (8)
-#define GPIO_MODER4_MASK           (3 << GPIO_MODER4_SHIFT)
-#define GPIO_MODER5_SHIFT          (10)
-#define GPIO_MODER5_MASK           (3 << GPIO_MODER5_SHIFT)
-#define GPIO_MODER6_SHIFT          (12)
-#define GPIO_MODER6_MASK           (3 << GPIO_MODER6_SHIFT)
-#define GPIO_MODER7_SHIFT          (14)
-#define GPIO_MODER7_MASK           (3 << GPIO_MODER7_SHIFT)
-#define GPIO_MODER8_SHIFT          (16)
-#define GPIO_MODER8_MASK           (3 << GPIO_MODER8_SHIFT)
-#define GPIO_MODER9_SHIFT          (18)
-#define GPIO_MODER9_MASK           (3 << GPIO_MODER9_SHIFT)
-#define GPIO_MODER10_SHIFT         (20)
-#define GPIO_MODER10_MASK          (3 << GPIO_MODER10_SHIFT)
-#define GPIO_MODER11_SHIFT         (22)
-#define GPIO_MODER11_MASK          (3 << GPIO_MODER11_SHIFT)
-#define GPIO_MODER12_SHIFT         (24)
-#define GPIO_MODER12_MASK          (3 << GPIO_MODER12_SHIFT)
-#define GPIO_MODER13_SHIFT         (26)
-#define GPIO_MODER13_MASK          (3 << GPIO_MODER13_SHIFT)
-#define GPIO_MODER14_SHIFT         (28)
-#define GPIO_MODER14_MASK          (3 << GPIO_MODER14_SHIFT)
-#define GPIO_MODER15_SHIFT         (30)
-#define GPIO_MODER15_MASK          (3 << GPIO_MODER15_SHIFT)
-
-/* GPIO port output type register */
-
-#define GPIO_OTYPER_OD(n)          (1 << (n)) /* 1=Output open-drain */
-#define GPIO_OTYPER_PP(n)          (0)        /* 0=Ouput push-pull */
-
-/* GPIO port output speed register */
-
-#define GPIO_OSPEED_2MHz           (0) /* x0: 2 MHz Low speed */
-#define GPIO_OSPEED_10MHz          (1) /* 01: 10 MHz Medium speed */
-#define GPIO_OSPEED_50MHz          (3) /* 11: 50 MHz High speed */
-
-#define GPIO_OSPEED_SHIFT(n)       ((n) << 1)
-#define GPIO_OSPEED_MASK(n)        (3 << GPIO_OSPEED_SHIFT(n))
-
-#define GPIO_OSPEED0_SHIFT         (0)
-#define GPIO_OSPEED0_MASK          (3 << GPIO_OSPEED0_SHIFT)
-#define GPIO_OSPEED1_SHIFT         (2)
-#define GPIO_OSPEED1_MASK          (3 << GPIO_OSPEED1_SHIFT)
-#define GPIO_OSPEED2_SHIFT         (4)
-#define GPIO_OSPEED2_MASK          (3 << GPIO_OSPEED2_SHIFT)
-#define GPIO_OSPEED3_SHIFT         (6)
-#define GPIO_OSPEED3_MASK          (3 << GPIO_OSPEED3_SHIFT)
-#define GPIO_OSPEED4_SHIFT         (8)
-#define GPIO_OSPEED4_MASK          (3 << GPIO_OSPEED4_SHIFT)
-#define GPIO_OSPEED5_SHIFT         (10)
-#define GPIO_OSPEED5_MASK          (3 << GPIO_OSPEED5_SHIFT)
-#define GPIO_OSPEED6_SHIFT         (12)
-#define GPIO_OSPEED6_MASK          (3 << GPIO_OSPEED6_SHIFT)
-#define GPIO_OSPEED7_SHIFT         (14)
-#define GPIO_OSPEED7_MASK          (3 << GPIO_OSPEED7_SHIFT)
-#define GPIO_OSPEED8_SHIFT         (16)
-#define GPIO_OSPEED8_MASK          (3 << GPIO_OSPEED8_SHIFT)
-#define GPIO_OSPEED9_SHIFT         (18)
-#define GPIO_OSPEED9_MASK          (3 << GPIO_OSPEED9_SHIFT)
-#define GPIO_OSPEED10_SHIFT        (20)
-#define GPIO_OSPEED10_MASK         (3 << GPIO_OSPEED10_SHIFT)
-#define GPIO_OSPEED11_SHIFT        (22)
-#define GPIO_OSPEED11_MASK         (3 << GPIO_OSPEED11_SHIFT)
-#define GPIO_OSPEED12_SHIFT        (24)
-#define GPIO_OSPEED12_MASK         (3 << GPIO_OSPEED12_SHIFT)
-#define GPIO_OSPEED13_SHIFT        (26)
-#define GPIO_OSPEED13_MASK         (3 << GPIO_OSPEED13_SHIFT)
-#define GPIO_OSPEED14_SHIFT        (28)
-#define GPIO_OSPEED14_MASK         (3 << GPIO_OSPEED14_SHIFT)
-#define GPIO_OSPEED15_SHIFT        (30)
-#define GPIO_OSPEED15_MASK         (3 << GPIO_OSPEED15_SHIFT)
-
-/* GPIO port pull-up/pull-down register */
-
-#define GPIO_PUPDR_NONE            (0) /* No pull-up, pull-down */
-#define GPIO_PUPDR_PULLUP          (1) /* Pull-up */
-#define GPIO_PUPDR_PULLDOWN        (2) /* Pull-down */
-
-#define GPIO_PUPDR_SHIFT(n)        ((n) << 1)
-#define GPIO_PUPDR_MASK(n)         (3 << GPIO_PUPDR_SHIFT(n))
-
-#define GPIO_PUPDR0_SHIFT          (0)
-#define GPIO_PUPDR0_MASK           (3 << GPIO_PUPDR0_SHIFT)
-#define GPIO_PUPDR1_SHIFT          (2)
-#define GPIO_PUPDR1_MASK           (3 << GPIO_PUPDR1_SHIFT)
-#define GPIO_PUPDR2_SHIFT          (4)
-#define GPIO_PUPDR2_MASK           (3 << GPIO_PUPDR2_SHIFT)
-#define GPIO_PUPDR3_SHIFT          (6)
-#define GPIO_PUPDR3_MASK           (3 << GPIO_PUPDR3_SHIFT)
-#define GPIO_PUPDR4_SHIFT          (8)
-#define GPIO_PUPDR4_MASK           (3 << GPIO_PUPDR4_SHIFT)
-#define GPIO_PUPDR5_SHIFT          (10)
-#define GPIO_PUPDR5_MASK           (3 << GPIO_PUPDR5_SHIFT)
-#define GPIO_PUPDR6_SHIFT          (12)
-#define GPIO_PUPDR6_MASK           (3 << GPIO_PUPDR6_SHIFT)
-#define GPIO_PUPDR7_SHIFT          (14)
-#define GPIO_PUPDR7_MASK           (3 << GPIO_PUPDR7_SHIFT)
-#define GPIO_PUPDR8_SHIFT          (16)
-#define GPIO_PUPDR8_MASK           (3 << GPIO_PUPDR8_SHIFT)
-#define GPIO_PUPDR9_SHIFT          (18)
-#define GPIO_PUPDR9_MASK           (3 << GPIO_PUPDR9_SHIFT)
-#define GPIO_PUPDR10_SHIFT         (20)
-#define GPIO_PUPDR10_MASK          (3 << GPIO_PUPDR10_SHIFT)
-#define GPIO_PUPDR11_SHIFT         (22)
-#define GPIO_PUPDR11_MASK          (3 << GPIO_PUPDR11_SHIFT)
-#define GPIO_PUPDR12_SHIFT         (24)
-#define GPIO_PUPDR12_MASK          (3 << GPIO_PUPDR12_SHIFT)
-#define GPIO_PUPDR13_SHIFT         (26)
-#define GPIO_PUPDR13_MASK          (3 << GPIO_PUPDR13_SHIFT)
-#define GPIO_PUPDR14_SHIFT         (28)
-#define GPIO_PUPDR14_MASK          (3 << GPIO_PUPDR14_SHIFT)
-#define GPIO_PUPDR15_SHIFT         (30)
-#define GPIO_PUPDR15_MASK          (3 << GPIO_PUPDR15_SHIFT)
-
-/* GPIO port input data register */
-
-#define GPIO_IDR(n)                (1 << (n))
-
-/* GPIO port output data register */
-
-#define GPIO_ODR(n)                (1 << (n))
-
-/* GPIO port bit set/reset register */
-
-#define GPIO_BSRR_SET(n)           (1 << (n))
-#define GPIO_BSRR_RESET(n)         (1 << ((n) + 16))
-
-/* GPIO port configuration lock register */
-
-#define GPIO_LCKR(n)               (1 << (n))
-#define GPIO_LCKK                  (1 << 16)   /* Lock key */
-
-/* GPIO alternate function low/high register */
-
-#define GPIO_AFR_SHIFT(n)          ((n) << 2)
-#define GPIO_AFR_MASK(n)           (15 << GPIO_AFR_SHIFT(n))
-
-#define GPIO_AFRL0_SHIFT           (0)
-#define GPIO_AFRL0_MASK            (15 << GPIO_AFRL0_SHIFT)
-#define GPIO_AFRL1_SHIFT           (4)
-#define GPIO_AFRL1_MASK            (15 << GPIO_AFRL1_SHIFT)
-#define GPIO_AFRL2_SHIFT           (8)
-#define GPIO_AFRL2_MASK            (15 << GPIO_AFRL2_SHIFT)
-#define GPIO_AFRL3_SHIFT           (12)
-#define GPIO_AFRL3_MASK            (15 << GPIO_AFRL3_SHIFT)
-#define GPIO_AFRL4_SHIFT           (16)
-#define GPIO_AFRL4_MASK            (15 << GPIO_AFRL4_SHIFT)
-#define GPIO_AFRL5_SHIFT           (20)
-#define GPIO_AFRL5_MASK            (15 << GPIO_AFRL5_SHIFT)
-#define GPIO_AFRL6_SHIFT           (24)
-#define GPIO_AFRL6_MASK            (15 << GPIO_AFRL6_SHIFT)
-#define GPIO_AFRL7_SHIFT           (28)
-#define GPIO_AFRL7_MASK            (15 << GPIO_AFRL7_SHIFT)
-
-#define GPIO_AFRH8_SHIFT           (0)
-#define GPIO_AFRH8_MASK            (15 << GPIO_AFRH8_SHIFT)
-#define GPIO_AFRH9_SHIFT           (4)
-#define GPIO_AFRH9_MASK            (15 << GPIO_AFRH9_SHIFT)
-#define GPIO_AFRH10_SHIFT          (8)
-#define GPIO_AFRH10_MASK           (15 << GPIO_AFRH10_SHIFT)
-#define GPIO_AFRH11_SHIFT          (12)
-#define GPIO_AFRH11_MASK           (15 << GPIO_AFRH11_SHIFT)
-#define GPIO_AFRH12_SHIFT          (16)
-#define GPIO_AFRH12_MASK           (15 << GPIO_AFRH12_SHIFT)
-#define GPIO_AFRH13_SHIFT          (20)
-#define GPIO_AFRH13_MASK           (15 << GPIO_AFRH13_SHIFT)
-#define GPIO_AFRH14_SHIFT          (24)
-#define GPIO_AFRH14_MASK           (15 << GPIO_AFRH14_SHIFT)
-#define GPIO_AFRH15_SHIFT          (28)
-#define GPIO_AFRH15_MASK           (15 << GPIO_AFRH15_SHIFT)
-
-/* GPIO port bit reset register */
-
-#define GPIO_BRR(n)                (1 << (n))
-
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_GPIO_H */
diff --git a/arch/arm/src/stm32f0l0/stm32_i2c.c b/arch/arm/src/stm32f0l0/stm32_i2c.c
deleted file mode 100644
index d3f4a705c0b..00000000000
--- a/arch/arm/src/stm32f0l0/stm32_i2c.c
+++ /dev/null
@@ -1,2001 +0,0 @@
-/************************************************************************************
- * arch/arm/src/stm32f0l0/stm32_i2c.c
- * STM32L4 I2C driver - based on STM32F3 I2C Hardware Layer - Device Driver
- *
- *   Copyright (C) 2011 Uros Platise. All rights reserved.
- *   Author: Uros Platise 
- *   Copyright (C) 2011-2013, 2016-2017 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt 
- *   Author: John Wharington
- *   Author: Sebastien Lorquet
- *   Author: dev@ziggurat29.com
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-/* Supports:
- *  - Master operation, 100 kHz (standard) and 400 kHz (full speed)
- *  - Multiple instances (shared bus)
- *  - Interrupt based operation
- *
- * Structure naming:
- *  - Device: structure as defined by the nuttx/i2c/i2c.h
- *  - Instance: represents each individual access to the I2C driver, obtained by
- *      the i2c_init(); it extends the Device structure from the nuttx/i2c/i2c.h;
- *      Instance points to OPS, to common I2C Hardware private data and contains
- *      its own private data, as frequency, address, mode of operation (in the future)
- *  - Private: Private data of an I2C Hardware
- *
- * TODO
- *  - Check for all possible deadlocks (as BUSY='1' I2C needs to be reset in HW using
- *     the I2C_CR1_SWRST)
- *  - SMBus support (hardware layer timings are already supported) and add SMBA gpio
- *    pin
- *  - Slave support with multiple addresses (on multiple instances):
- *      - 2 x 7-bit address or
- *      - 1 x 10 bit adresses + 1 x 7 bit address (?)
- *      - plus the broadcast address (general call)
- *  - Multi-master support
- *  - DMA (to get rid of too many CPU wake-ups and interventions)
- *  - Be ready for IPMI
- */
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include 
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include 
-
-#include "up_arch.h"
-
-#include "stm32_gpio.h"
-#include "stm32_rcc.h"
-#include "stm32_i2c.h"
-
-/* At least one I2C peripheral must be enabled */
-
-#if defined(CONFIG_STM32F0L0_I2C1) || defined(CONFIG_STM32F0L0_I2C2) || defined(CONFIG_STM32F0L0_I2C3)
-
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/* Configuration ********************************************************************/
-/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used.  Instead,
- * CPU-intensive polling will be used.
- */
-
-/* Interrupt wait timeout in seconds and milliseconds */
-
-#if !defined(CONFIG_STM32F0L0_I2CTIMEOSEC) && !defined(CONFIG_STM32F0L0_I2CTIMEOMS)
-#  define CONFIG_STM32F0L0_I2CTIMEOSEC 0
-#  define CONFIG_STM32F0L0_I2CTIMEOMS  500   /* Default is 500 milliseconds */
-#elif !defined(CONFIG_STM32F0L0_I2CTIMEOSEC)
-#  define CONFIG_STM32F0L0_I2CTIMEOSEC 0     /* User provided milliseconds */
-#elif !defined(CONFIG_STM32F0L0_I2CTIMEOMS)
-#  define CONFIG_STM32F0L0_I2CTIMEOMS  0     /* User provided seconds */
-#endif
-
-/* Interrupt wait time timeout in system timer ticks */
-
-#ifndef CONFIG_STM32F0L0_I2CTIMEOTICKS
-#  define CONFIG_STM32F0L0_I2CTIMEOTICKS \
-    (SEC2TICK(CONFIG_STM32F0L0_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F0L0_I2CTIMEOMS))
-#endif
-
-#ifndef CONFIG_STM32F0L0_I2C_DYNTIMEO_STARTSTOP
-#  define CONFIG_STM32F0L0_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F0L0_I2CTIMEOTICKS)
-#endif
-
-#define I2C_OUTPUT \
-  (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_OPENDRAIN | GPIO_SPEED_50MHz)
-#define MKI2C_OUTPUT(p) \
-  (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
-
-#define I2C_CR1_TXRX \
-  (I2C_CR1_RXIE | I2C_CR1_TXIE)
-#define I2C_CR1_ALLINTS \
-  (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ADDRIE | I2C_CR1_ERRIE)
-
-#define STATUS_NACK(status)    (status & I2C_INT_NACK)
-#define STATUS_ADDR(status)    (status & I2C_INT_ADDR)
-#define STATUS_ADDR_TX(status) (status & (I2C_INT_ADDR | I2C_ISR_TXIS))
-#define STATUS_ADD10(status)   (0)
-#define STATUS_RXNE(status)    (status & I2C_ISR_RXNE)
-#define STATUS_TC(status)      (status & I2C_ISR_TC)
-#define STATUS_BUSY(status)    (status & I2C_ISR_BUSY)
-
-/* Debug ****************************************************************************/
-
-/* I2C event trace logic.  NOTE:  trace uses the internal, non-standard, low-level
- * debug interface syslog() but does not require that any other debug
- * is enabled.
- */
-
-#ifndef CONFIG_I2C_TRACE
-#  define stm32_i2c_tracereset(p)
-#  define stm32_i2c_tracenew(p,s)
-#  define stm32_i2c_traceevent(p,e,a)
-#  define stm32_i2c_tracedump(p)
-#endif
-
-#ifndef CONFIG_I2C_NTRACE
-#  define CONFIG_I2C_NTRACE 32
-#endif
-
-/************************************************************************************
- * Private Types
- ************************************************************************************/
-/* Interrupt state */
-
-enum stm32_intstate_e
-{
-  INTSTATE_IDLE = 0,      /* No I2C activity */
-  INTSTATE_WAITING,       /* Waiting for completion of interrupt activity */
-  INTSTATE_DONE,          /* Interrupt activity complete */
-};
-
-/* Trace events */
-
-enum stm32_trace_e
-{
-  I2CEVENT_NONE = 0,      /* No events have occurred with this status */
-  I2CEVENT_SENDADDR,      /* Start/Master bit set and address sent, param = msgc */
-  I2CEVENT_SENDBYTE,      /* Send byte, param = dcnt */
-  I2CEVENT_ITBUFEN,       /* Enable buffer interrupts, param = 0 */
-  I2CEVENT_RCVBYTE,       /* Read more dta, param = dcnt */
-  I2CEVENT_REITBUFEN,     /* Re-enable buffer interrupts, param = 0 */
-  I2CEVENT_DISITBUFEN,    /* Disable buffer interrupts, param = 0 */
-  I2CEVENT_BTFNOSTART,    /* BTF on last byte with no restart, param = msgc */
-  I2CEVENT_BTFRESTART,    /* Last byte sent, re-starting, param = msgc */
-  I2CEVENT_BTFSTOP,       /* Last byte sten, send stop, param = 0 */
-  I2CEVENT_ERROR          /* Error occurred, param = 0 */
-};
-
-/* Trace data */
-
-struct stm32_trace_s
-{
-  uint32_t status;               /* I2C 32-bit SR2|SR1 status */
-  uint32_t count;                /* Interrupt count when status change */
-  enum stm32_intstate_e event;   /* Last event that occurred with this status */
-  uint32_t parm;                 /* Parameter associated with the event */
-  clock_t time;                  /* First of event or first status */
-};
-
-/* I2C Device hardware configuration */
-
-struct stm32_i2c_config_s
-{
-  uint32_t base;              /* I2C base address */
-  uint32_t clk_bit;           /* Clock enable bit */
-  uint32_t reset_bit;         /* Reset bit */
-  uint32_t scl_pin;           /* GPIO configuration for SCL as SCL */
-  uint32_t sda_pin;           /* GPIO configuration for SDA as SDA */
-#ifndef CONFIG_I2C_POLLED
-  uint32_t irq;               /* IRQ */
-#endif
-};
-
-/* I2C Device Private Data */
-
-struct stm32_i2c_priv_s
-{
-  const struct i2c_ops_s *ops; /* Standard I2C operations */
-  const struct stm32_i2c_config_s *config; /* Port configuration */
-  int refs;                    /* Reference count */
-  sem_t sem_excl;              /* Mutual exclusion semaphore */
-#ifndef CONFIG_I2C_POLLED
-  sem_t sem_isr;               /* Interrupt wait semaphore */
-#endif
-  volatile uint8_t intstate;   /* Interrupt handshake (see enum stm32_intstate_e) */
-
-  uint8_t msgc;                /* Message count */
-  struct i2c_msg_s *msgv;      /* Message list */
-  uint8_t *ptr;                /* Current message buffer */
-  uint32_t frequency;          /* Current I2C frequency */
-  int dcnt;                    /* Current message length */
-  uint16_t flags;              /* Current message flags */
-  bool astart;                 /* START sent */
-
-  /* I2C trace support */
-
-#ifdef CONFIG_I2C_TRACE
-  int tndx;                    /* Trace array index */
-  clock_t start_time;          /* Time when the trace was started */
-
-  /* The actual trace data */
-
-  struct stm32_trace_s trace[CONFIG_I2C_NTRACE];
-#endif
-
-  uint32_t status;             /* End of transfer SR2|SR1 status */
-};
-
-/************************************************************************************
- * Private Function Prototypes
- ************************************************************************************/
-
-static inline uint32_t stm32_i2c_getreg32(FAR struct stm32_i2c_priv_s *priv,
-                                          uint8_t offset);
-static inline void stm32_i2c_putreg32(FAR struct stm32_i2c_priv_s *priv,
-                                      uint8_t offset, uint32_t value);
-static inline void stm32_i2c_modifyreg32(FAR struct stm32_i2c_priv_s *priv,
-                                         uint8_t offset, uint32_t clearbits,
-                                         uint32_t setbits);
-static inline void stm32_i2c_sem_wait(FAR struct stm32_i2c_priv_s *priv);
-#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO
-static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs);
-#endif /* CONFIG_STM32F0L0_I2C_DYNTIMEO */
-static inline int  stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv);
-static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv);
-static inline void stm32_i2c_sem_post(FAR struct stm32_i2c_priv_s *priv);
-static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv);
-static inline void stm32_i2c_sem_destroy(FAR struct stm32_i2c_priv_s *priv);
-#ifdef CONFIG_I2C_TRACE
-static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv);
-static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv,
-                               uint32_t status);
-static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
-                                 enum stm32_trace_e event, uint32_t parm);
-static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv);
-#endif /* CONFIG_I2C_TRACE */
-static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv,
-                               uint32_t frequency);
-static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv);
-static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv);
-static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv);
-static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv);
-static int stm32_i2c_isr_process(struct stm32_i2c_priv_s * priv);
-#ifndef CONFIG_I2C_POLLED
-static int stm32_i2c_isr(int irq, void *context, FAR void *arg);
-#endif
-static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv);
-static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv);
-static int stm32_i2c_transfer(FAR struct i2c_master_s *dev,
-                              FAR struct i2c_msg_s *msgs, int count);
-#ifdef CONFIG_I2C_RESET
-static int stm32_i2c_reset(FAR struct i2c_master_s *dev);
-#endif
-
-/************************************************************************************
- * Private Data
- ************************************************************************************/
-
-/* Device Structures, Instantiation */
-
-static const struct i2c_ops_s stm32_i2c_ops =
-{
- .transfer = stm32_i2c_transfer
-#ifdef CONFIG_I2C_RESET
-  , .reset  = stm32_i2c_reset
-#endif
-};
-
-#ifdef CONFIG_STM32F0L0_I2C1
-static const struct stm32_i2c_config_s stm32_i2c1_config =
-{
-  .base       = STM32_I2C1_BASE,
-  .clk_bit    = RCC_APB1ENR_I2C1EN,
-  .reset_bit  = RCC_APB1RSTR_I2C1RST,
-  .scl_pin    = GPIO_I2C1_SCL,
-  .sda_pin    = GPIO_I2C1_SDA,
-#ifndef CONFIG_I2C_POLLED
-  .irq        = STM32_IRQ_I2C1
-#endif
-};
-
-static struct stm32_i2c_priv_s stm32_i2c1_priv =
-{
-  .ops        = &stm32_i2c_ops,
-  .config     = &stm32_i2c1_config,
-  .refs       = 0,
-  .intstate   = INTSTATE_IDLE,
-  .msgc       = 0,
-  .msgv       = NULL,
-  .ptr        = NULL,
-  .dcnt       = 0,
-  .flags      = 0,
-  .status     = 0
-};
-#endif
-
-#ifdef CONFIG_STM32F0L0_I2C2
-static const struct stm32_i2c_config_s stm32_i2c2_config =
-{
-  .base       = STM32_I2C2_BASE,
-  .clk_bit    = RCC_APB1ENR1_I2C2EN,
-  .reset_bit  = RCC_APB1RSTR1_I2C2RST,
-  .scl_pin    = GPIO_I2C2_SCL,
-  .sda_pin    = GPIO_I2C2_SDA,
-#ifndef CONFIG_I2C_POLLED
-  .irq        = STM32_IRQ_I2C2
-#endif
-};
-
-static struct stm32_i2c_priv_s stm32_i2c2_priv =
-{
-  .ops        = &stm32_i2c_ops,
-  .config     = &stm32_i2c2_config,
-  .refs       = 0,
-  .intstate   = INTSTATE_IDLE,
-  .msgc       = 0,
-  .msgv       = NULL,
-  .ptr        = NULL,
-  .dcnt       = 0,
-  .flags      = 0,
-  .status     = 0
-};
-#endif
-
-#ifdef CONFIG_STM32F0L0_I2C3
-static const struct stm32_i2c_config_s stm32_i2c3_config =
-{
-  .base       = STM32_I2C3_BASE,
-  .clk_bit    = RCC_APB1ENR1_I2C3EN,
-  .reset_bit  = RCC_APB1RSTR1_I2C3RST,
-  .scl_pin    = GPIO_I2C3_SCL,
-  .sda_pin    = GPIO_I2C3_SDA,
-#ifndef CONFIG_I2C_POLLED
-  .irq        = STM32_IRQ_I2C3
-#endif
-};
-
-static struct stm32_i2c_priv_s stm32_i2c3_priv =
-{
-  .ops        = &stm32_i2c_ops,
-  .config     = &stm32_i2c3_config,
-  .refs       = 0,
-  .intstate   = INTSTATE_IDLE,
-  .msgc       = 0,
-  .msgv       = NULL,
-  .ptr        = NULL,
-  .dcnt       = 0,
-  .flags      = 0,
-  .status     = 0
-};
-#endif
-
-/************************************************************************************
- * Private Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Name: stm32_i2c_getreg32
- *
- * Description:
- *   Get a 32-bit register value by offset
- *
- ************************************************************************************/
-
-static inline uint32_t stm32_i2c_getreg32(FAR struct stm32_i2c_priv_s *priv,
-                                          uint8_t offset)
-{
-  return getreg32(priv->config->base + offset);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_putreg32
- *
- * Description:
- *  Put a 32-bit register value by offset
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_putreg32(FAR struct stm32_i2c_priv_s *priv,
-                                      uint8_t offset, uint32_t value)
-{
-  putreg32(value, priv->config->base + offset);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_modifyreg32
- *
- * Description:
- *   Modify a 32-bit register value by offset
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_modifyreg32(FAR struct stm32_i2c_priv_s *priv,
-                                         uint8_t offset, uint32_t clearbits,
-                                         uint32_t setbits)
-{
-  modifyreg32(priv->config->base + offset, clearbits, setbits);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_sem_wait
- *
- * Description:
- *   Take the exclusive access, waiting as necessary
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_sem_wait(FAR struct stm32_i2c_priv_s *priv)
-{
-  int ret;
-
-  do
-    {
-      /* Take the semaphore (perhaps waiting) */
-
-      ret = nxsem_wait(&priv->sem_excl);
-
-      /* The only case that an error should occur here is if the wait was
-       * awakened by a signal.
-       */
-
-      DEBUGASSERT(ret == OK || ret == -EINTR);
-    }
-  while (ret == -EINTR);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_tousecs
- *
- * Description:
- *   Return a micro-second delay based on the number of bytes left to be processed.
- *
- ************************************************************************************/
-
-#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO
-static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
-{
-  size_t bytecount = 0;
-  int i;
-
-  /* Count the number of bytes left to process */
-
-  for (i = 0; i < msgc; i++)
-    {
-      bytecount += msgs[i].length;
-    }
-
-  /* Then return a number of microseconds based on a user provided scaling
-   * factor.
-   */
-
-  return (useconds_t)(CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE * bytecount);
-}
-#endif
-
-/************************************************************************************
- * Name: stm32_i2c_enableinterrupts
- *
- * Description:
- *   Enable I2C interrupts
- *
- ************************************************************************************/
-
-#ifndef CONFIG_I2C_POLLED
-static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_TXRX);
-}
-#endif
-
-/************************************************************************************
- * Name: stm32_i2c_disableinterrupts
- *
- * Description:
- *   Enable I2C interrupts
- *
- ************************************************************************************/
-
-#ifndef CONFIG_I2C_POLLED
-static inline void stm32_i2c_disableinterrupts(struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_TXRX, 0);
-}
-#endif
-
-/************************************************************************************
- * Name: stm32_i2c_sem_waitdone
- *
- * Description:
- *   Wait for a transfer to complete
- *
- ************************************************************************************/
-
-#ifndef CONFIG_I2C_POLLED
-static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
-{
-  struct timespec abstime;
-  irqstate_t flags;
-  int ret;
-
-  flags = enter_critical_section();
-
-  /* Enable I2C interrupts */
-
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0,
-                        (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX));
-
-  /* Signal the interrupt handler that we are waiting.  NOTE:  Interrupts
-   * are currently disabled but will be temporarily re-enabled below when
-   * nxsem_timedwait() sleeps.
-   */
-
-   priv->intstate = INTSTATE_WAITING;
-   do
-    {
-      /* Get the current time */
-
-      (void)clock_gettime(CLOCK_REALTIME, &abstime);
-
-      /* Calculate a time in the future */
-
-#if CONFIG_STM32F0L0_I2CTIMEOSEC > 0
-      abstime.tv_sec += CONFIG_STM32F0L0_I2CTIMEOSEC;
-#endif
-
-      /* Add a value proportional to the number of bytes in the transfer */
-
-#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO
-      abstime.tv_nsec += 1000 * stm32_i2c_tousecs(priv->msgc, priv->msgv);
-      if (abstime.tv_nsec >= 1000 * 1000 * 1000)
-        {
-          abstime.tv_sec++;
-          abstime.tv_nsec -= 1000 * 1000 * 1000;
-        }
-
-#elif CONFIG_STM32F0L0_I2CTIMEOMS > 0
-      abstime.tv_nsec += CONFIG_STM32F0L0_I2CTIMEOMS * 1000 * 1000;
-      if (abstime.tv_nsec >= 1000 * 1000 * 1000)
-        {
-          abstime.tv_sec++;
-          abstime.tv_nsec -= 1000 * 1000 * 1000;
-        }
-#endif
-      /* Wait until either the transfer is complete or the timeout expires */
-
-      ret = nxsem_timedwait(&priv->sem_isr, &abstime);
-      if (ret < 0 && ret != -EINTR)
-        {
-          /* Break out of the loop on irrecoverable errors.  This would
-           * include timeouts and mystery errors reported by nxsem_timedwait.
-           * NOTE that we try again if we are awakened by a signal (EINTR).
-           */
-
-          break;
-        }
-    }
-
-  /* Loop until the interrupt level transfer is complete. */
-
-  while (priv->intstate != INTSTATE_DONE);
-
-  /* Set the interrupt state back to IDLE */
-
-  priv->intstate = INTSTATE_IDLE;
-
-  /* Disable I2C interrupts */
-
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
-
-  leave_critical_section(flags);
-  return ret;
-}
-#else
-static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
-{
-  clock_t timeout;
-  clock_t start;
-  clock_t elapsed;
-  int ret;
-
-  /* Get the timeout value */
-
-#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO
-  timeout = USEC2TICK(stm32_i2c_tousecs(priv->msgc, priv->msgv));
-#else
-  timeout = CONFIG_STM32F0L0_I2CTIMEOTICKS;
-#endif
-
-  /* Signal the interrupt handler that we are waiting.  NOTE:  Interrupts
-   * are currently disabled but will be temporarily re-enabled below when
-   * nxsem_timedwait() sleeps.
-   */
-
-  priv->intstate = INTSTATE_WAITING;
-  start = clock_systimer();
-
-  do
-    {
-      /* Calculate the elapsed time */
-
-      elapsed = clock_systimer() - start;
-
-      /* Poll by simply calling the timer interrupt handler until it
-       * reports that it is done.
-       */
-
-      stm32_i2c_isr_process(priv);
-    }
-
-  /* Loop until the transfer is complete. */
-
-  while (priv->intstate != INTSTATE_DONE && elapsed < timeout);
-
-  i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08x\n",
-          priv->intstate, (long)elapsed, (long)timeout, priv->status);
-
-  /* Set the interrupt state back to IDLE */
-
-  ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT;
-  priv->intstate = INTSTATE_IDLE;
-  return ret;
-}
-#endif
-
-/************************************************************************************
- * Name: stm32_i2c_set_7bit_address
- *
- * Description:
- *
- ************************************************************************************/
-
-static inline void
-stm32_i2c_set_7bit_address(FAR struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK,
-                        ((priv->msgv->addr & 0x7F) << I2C_CR2_SADD7_SHIFT));
-}
-
-/************************************************************************************
- * Name: stm32_i2c_set_bytes_to_transfer
- *
- * Description:
- *
- ************************************************************************************/
-
-static inline void
-stm32_i2c_set_bytes_to_transfer(FAR struct stm32_i2c_priv_s *priv,
-                                uint8_t n_bytes)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK,
-                        (n_bytes << I2C_CR2_NBYTES_SHIFT));
-}
-
-/************************************************************************************
- * Name: stm32_i2c_set_write_transfer_dir
- *
- * Description:
- *
- ************************************************************************************/
-
-static inline void
-stm32_i2c_set_write_transfer_dir(FAR struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_set_read_transfer_dir
- *
- * Description:
- *
- ************************************************************************************/
-
-static inline void
-stm32_i2c_set_read_transfer_dir(FAR struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_enable_autoend
- *
- * Description:
- *
- ************************************************************************************/
-
-static inline void
-stm32_i2c_enable_autoend(FAR struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_AUTOEND);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_disable_autoend
- *
- * Description:
- *
- ************************************************************************************/
-
-static inline void
-stm32_i2c_disable_autoend(FAR struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_AUTOEND, 0);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_sem_waitstop
- *
- * Description:
- *   Wait for a STOP to complete
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
-{
-  clock_t start;
-  clock_t elapsed;
-  clock_t timeout;
-  uint32_t cr;
-  uint32_t sr;
-
-  /* Select a timeout */
-
-#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO
-  timeout = USEC2TICK(CONFIG_STM32F0L0_I2C_DYNTIMEO_STARTSTOP);
-#else
-  timeout = CONFIG_STM32F0L0_I2CTIMEOTICKS;
-#endif
-
-  /* Wait as stop might still be in progress; but stop might also
-   * be set because of a timeout error: "The [STOP] bit is set and
-   * cleared by software, cleared by hardware when a Stop condition is
-   * detected, set by hardware when a timeout error is detected."
-   */
-
-  start = clock_systimer();
-  do
-    {
-      /* Calculate the elapsed time */
-
-      elapsed = clock_systimer() - start;
-
-      /* Check for STOP condition */
-
-      cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET);
-      if ((cr & I2C_CR2_STOP) == 0)
-        {
-          return;
-        }
-
-      /* Check for timeout error */
-
-      sr = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
-      if ((sr & I2C_INT_TIMEOUT) != 0)
-        {
-          return;
-        }
-    }
-
-  /* Loop until the stop is complete or a timeout occurs. */
-
-  while (elapsed < timeout);
-
-  /* If we get here then a timeout occurred with the STOP condition
-   * still pending.
-   */
-
-  i2cinfo("Timeout with CR: %04x SR: %04x\n", cr, sr);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_sem_post
- *
- * Description:
- *   Release the mutual exclusion semaphore
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_sem_post(FAR struct stm32_i2c_priv_s *priv)
-{
-  nxsem_post(&priv->sem_excl);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_sem_init
- *
- * Description:
- *   Initialize semaphores
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_sem_init(FAR struct stm32_i2c_priv_s *priv)
-{
-  nxsem_init(&priv->sem_excl, 0, 1);
-
-#ifndef CONFIG_I2C_POLLED
-  /* This semaphore is used for signaling and, hence, should not have
-   * priority inheritance enabled.
-   */
-
-  nxsem_init(&priv->sem_isr, 0, 0);
-  nxsem_setprotocol(&priv->sem_isr, SEM_PRIO_NONE);
-#endif
-}
-
-/************************************************************************************
- * Name: stm32_i2c_sem_destroy
- *
- * Description:
- *   Destroy semaphores.
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_sem_destroy(FAR struct stm32_i2c_priv_s *priv)
-{
-  nxsem_destroy(&priv->sem_excl);
-#ifndef CONFIG_I2C_POLLED
-  nxsem_destroy(&priv->sem_isr);
-#endif
-}
-
-/************************************************************************************
- * Name: stm32_i2c_trace*
- *
- * Description:
- *   I2C trace instrumentation
- *
- ************************************************************************************/
-
-#ifdef CONFIG_I2C_TRACE
-static void stm32_i2c_traceclear(FAR struct stm32_i2c_priv_s *priv)
-{
-  struct stm32_trace_s *trace = &priv->trace[priv->tndx];
-
-  trace->status = 0;              /* I2C 32-bit SR2|SR1 status */
-  trace->count  = 0;              /* Interrupt count when status change */
-  trace->event  = I2CEVENT_NONE;  /* Last event that occurred with this status */
-  trace->parm   = 0;              /* Parameter associated with the event */
-  trace->time   = 0;              /* Time of first status or event */
-}
-
-static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv)
-{
-  /* Reset the trace info for a new data collection */
-
-  priv->tndx       = 0;
-  priv->start_time = clock_systimer();
-  stm32_i2c_traceclear(priv);
-}
-
-static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv,
-                               uint32_t status)
-{
-  struct stm32_trace_s *trace = &priv->trace[priv->tndx];
-
-  /* Is the current entry uninitialized?   Has the status changed? */
-
-  if (trace->count == 0 || status != trace->status)
-    {
-      /* Yes.. Was it the status changed?  */
-
-      if (trace->count != 0)
-        {
-          /* Yes.. bump up the trace index (unless we are out of trace entries) */
-
-          if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
-            {
-              i2cerr("ERROR: Trace table overflow\n");
-              return;
-            }
-
-          priv->tndx++;
-          trace = &priv->trace[priv->tndx];
-        }
-
-      /* Initialize the new trace entry */
-
-      stm32_i2c_traceclear(priv);
-      trace->status = status;
-      trace->count  = 1;
-      trace->time   = clock_systimer();
-    }
-  else
-    {
-      /* Just increment the count of times that we have seen this status */
-
-      trace->count++;
-    }
-}
-
-static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
-                                enum stm32_trace_e event, uint32_t parm)
-{
-  struct stm32_trace_s *trace;
-
-  if (event != I2CEVENT_NONE)
-    {
-      trace = &priv->trace[priv->tndx];
-
-      /* Initialize the new trace entry */
-
-      trace->event  = event;
-      trace->parm   = parm;
-
-      /* Bump up the trace index (unless we are out of trace entries) */
-
-      if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
-        {
-          i2cerr("ERROR: Trace table overflow\n");
-          return;
-        }
-
-      priv->tndx++;
-      stm32_i2c_traceclear(priv);
-    }
-}
-
-static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
-{
-  struct stm32_trace_s *trace;
-  int i;
-
-  syslog(LOG_DEBUG, "Elapsed time: %ld\n",
-         (long)(clock_systimer() - priv->start_time));
-
-  for (i = 0; i < priv->tndx; i++)
-    {
-      trace = &priv->trace[i];
-      syslog(LOG_DEBUG,
-             "%2d. STATUS: %08x COUNT: %3d EVENT: %2d PARM: %08x TIME: %d\n",
-             i+1, trace->status, trace->count,  trace->event, trace->parm,
-             trace->time - priv->start_time);
-    }
-}
-#endif /* CONFIG_I2C_TRACE */
-
-/************************************************************************************
- * Name: stm32_i2c_setclock
- *
- * Description:
- *   Set the I2C clock
- *
- ************************************************************************************/
-
-static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequency)
-{
-  uint32_t pe;
-  uint8_t presc;
-  uint8_t s_time;
-  uint8_t h_time;
-  uint8_t scl_h_period;
-  uint8_t scl_l_period;
-
-  /* XXX haque; these are the only freqs we support at the moment, until we can
-   * compute the values ourself.  Pick the highest supported frequency that does
-   * not exceed the requested frequency.
-   */
-
-  if (frequency < 100000)
-    {
-      frequency = 10000;  /* 0Hz <= frequency < 100KHz: Use 10Khz */
-    }
-  else if (frequency < 400000)
-    {
-      frequency = 100000; /* 100KHz <= frequency < 400KHz: Use 100KHz */
-    }
-  else if (frequency < 1000000)
-    {
-      frequency = 400000; /* 400KHz <= frequency < 1MHz: Use 400Khz */
-    }
-  else
-    {
-      frequency = 1000000; /* 1MHz <= frequency:  Use 1Mhz */
-    }
-
-  /* Has the I2C bus frequency changed? */
-
-  if (frequency != priv->frequency)
-    {
-      /* Disable the selected I2C peripheral to configure TRISE */
-
-      pe = (stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE);
-      if (pe)
-        {
-          stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
-        }
-
-      /* Update timing and control registers */
-
-      /* TODO: speed/timing calcs, taking into consideration
-       * STM32_PCLK1_FREQUENCY, or SYSCLK, or HSI16
-       * clock source, RCC_CCIPR, I2CxSEL, 0 = PCKL, 1 = SCLK, 2 = HSI16, 3 = reserved
-#warning "check set filters before timing, see RM0351 35.4.4 p 1112"
-       * analog filter; suppress spikes up to 50 ns in fast-mode and fast-mode plus
-       * ANFOFF cr1
-       * DNF cr1; 1-15 I2CCLK periods
-       */
-      /* RM0351 35.4.9 p 1140 */
-
-      if (frequency == 10000)
-        {
-          /* 10 KHz values from I2C timing tool with clock 8mhz */
-
-          presc        = 0x01;    /* PRESC - (+1) prescale I2CCLK */
-          scl_l_period = 0xc7;    /* SCLL - SCL low period in master mode */
-          scl_h_period = 0xc3;    /* SCLH - SCL high period in master mode */
-          h_time       = 0x02;    /* SDADEL - (+1) data hold time after SCL falling edge */
-          s_time       = 0x04;    /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
-        }
-     else if (frequency == 100000)
-        {
-          /* 100 KHz values from I2C timing tool with clock 8mhz */
-
-          presc        = 0x01;    /* PRESC - (+1) prescale I2CCLK */
-          scl_l_period = 0x13;    /* SCLL - SCL low period in master mode */
-          scl_h_period = 0x0f;    /* SCLH - SCL high period in master mode */
-          h_time       = 0x02;    /* SDADEL - (+1) data hold time after SCL falling edge */
-          s_time       = 0x04;    /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
-        }
-      else if (frequency == 400000)
-        {
-          /* 400 KHz values from I2C timing tool for clock of 8mhz */
-
-          presc        = 0x00;    /* PRESC - (+1) prescale I2CCLK */
-          scl_l_period = 0x09;    /* SCLL - SCL low period in master mode */
-          scl_h_period = 0x03;    /* SCLH - SCL high period in master mode */
-          h_time       = 0x01;    /* SDADEL - (+1) data hold time after SCL falling edge */
-          s_time       = 0x03;    /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
-        }
-      else
-        {
-          /* 1000 KHhz values from I2C timing tool for clock of 8mhz */
-
-          presc        = 0x00;    /* PRESC - (+1) prescale I2CCLK */
-          scl_l_period = 0x06;    /* SCLL - SCL low period in master mode */
-          scl_h_period = 0x03;    /* SCLH - SCL high period in master mode */
-          h_time       = 0x00;    /* SDADEL - (+1) data hold time after SCL falling edge */
-          s_time       = 0x01;    /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
-        }
-
-      uint32_t timingr =
-        (presc << I2C_TIMINGR_PRESC_SHIFT) |
-        (s_time << I2C_TIMINGR_SCLDEL_SHIFT) |
-        (h_time << I2C_TIMINGR_SDADEL_SHIFT) |
-        (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) |
-        (scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
-
-      stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr);
-
-      /* Re-enable the peripheral (or not) */
-
-      if (pe)
-        {
-          stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
-        }
-
-      /* Save the new I2C frequency */
-
-      priv->frequency = frequency;
-    }
-}
-
-/************************************************************************************
- * Name: stm32_i2c_sendstart
- *
- * Description:
- *   Send the START conditions/force Master mode
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv)
-{
-  /* Get run-time data */
-
-  priv->astart = true;
-  priv->ptr   = priv->msgv->buffer;
-  priv->dcnt  = priv->msgv->length;
-  priv->flags = priv->msgv->flags;
-
-  /* Disable ACK on receive by default and generate START */
-
-  stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
-  stm32_i2c_set_7bit_address(priv);
-  if (priv->flags & I2C_M_READ)
-    {
-      stm32_i2c_set_read_transfer_dir(priv);
-    }
-  else
-    {
-      stm32_i2c_set_write_transfer_dir(priv);
-    }
-
-  if (priv->msgc == 1)
-    {
-      /* stm32_i2c_enable_autoend(priv); */
-    }
-  else
-    {
-      /* stm32_i2c_disable_autoend(priv); */
-    }
-
-  /* TODO check NACK */
-  /* TODO handle NACKR? */
-
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_clrstart
- *
- * Description:
- *   Clear the STOP, START or PEC condition on certain error recovery steps.
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv)
-{
-  /* "Note: When the STOP, START or PEC bit is set, the software must
-   *  not perform any write access to I2C_CR1 before this bit is
-   *  cleared by hardware. Otherwise there is a risk of setting a
-   *  second STOP, START or PEC request."
-   *
-   * "The [STOP] bit is set and cleared by software, cleared by hardware
-   *  when a Stop condition is detected, set by hardware when a timeout
-   *  error is detected.
-   *
-   * "This [START] bit is set and cleared by software and cleared by hardware
-   *  when start is sent or PE=0."  The bit must be cleared by software if the
-   *  START is never sent.
-   *
-   * "This [PEC] bit is set and cleared by software, and cleared by hardware
-   *  when PEC is transferred or by a START or Stop condition or when PE=0."
-   */
-
-  /* TODO check PEC (32 bit separate reg) */
-
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET,
-                        I2C_CR2_START | I2C_CR2_STOP, 0);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_sendstop
- *
- * Description:
- *   Send the STOP conditions
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv)
-{
-  /* TODO check NACK */
-
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_getstatus
- *
- * Description:
- *   Get 32-bit status (SR1 and SR2 combined)
- *
- ************************************************************************************/
-
-static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv)
-{
-  return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_isr_startmessage
- *
- * Description:
- *   Common logic when a message is started.  Just adds the even to the trace buffer
- *   if enabled and adjusts the message pointer and count.
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_isr_startmessage(struct stm32_i2c_priv_s *priv)
-{
-  stm32_i2c_traceevent(priv, I2CEVENT_SENDADDR, priv->msgc);
-
-  /* Increment to next pointer and decrement message count */
-
-  priv->msgv++;
-  priv->msgc--;
-}
-
-/************************************************************************************
- * Name: stm32_i2c_clearinterrupts
- *
- * Description:
- *  Clear all interrupts
- *
- ************************************************************************************/
-
-static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv)
-{
-#warning "check this clears interrupts?"
-    stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
-}
-
-/************************************************************************************
- * Name: stm32_i2c_isr_process
- *
- * Description:
- *  Common Interrupt Service Routine
- *
- ************************************************************************************/
-
-static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
-{
-  uint32_t status = stm32_i2c_getstatus(priv);
-
-  /* Check for new trace setup */
-
-  stm32_i2c_tracenew(priv, status);
-
-#warning "TODO: check clear interrupts after all actions"
-
-  if (STATUS_NACK(status))
-    {
-      /* wait, reset this? */
-    }
-  else if (priv->astart)
-    {
-      stm32_i2c_isr_startmessage(priv);
-      priv->astart = false;
-    }
-
-  /* Was address sent, continue with either sending or reading data */
-
-  if ((priv->flags & I2C_M_READ) == 0 && STATUS_ADDR_TX(status))
-    {
-#warning "TODO: ADDRCF clear address interrupt flag"
-      if (priv->dcnt > 0)
-        {
-          /* Send a byte */
-
-          stm32_i2c_traceevent(priv, I2CEVENT_SENDBYTE, priv->dcnt);
-          stm32_i2c_putreg32(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr++);
-          priv->dcnt--;
-        }
-    }
-  else if ((priv->flags & I2C_M_READ) != 0 && STATUS_ADDR(status))
-    {
-      /* Enable RxNE and TxE buffers in order to receive one or multiple bytes */
-
-#warning "TODO: ADDRCF clear address interrupt flag"
-
-#ifndef CONFIG_I2C_POLLED
-      stm32_i2c_traceevent(priv, I2CEVENT_ITBUFEN, 0);
-      stm32_i2c_enableinterrupts(priv);
-#endif
-    }
-
-  /* More bytes to read */
-
-  else if (STATUS_RXNE(status))
-    {
-      /* Read a byte, if dcnt goes < 0, then read dummy bytes to ack ISRs */
-
-      if (priv->dcnt > 0)
-        {
-          stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt);
-
-          /* No interrupts or context switches may occur in the following
-           * sequence.  Otherwise, additional bytes may be sent by the
-           * device.
-           */
-
-#ifdef CONFIG_I2C_POLLED
-          irqstate_t flags = enter_critical_section();
-#endif
-          /* Receive a byte */
-
-          *priv->ptr++ = (uint8_t) stm32_i2c_getreg32(priv, STM32_I2C_RXDR_OFFSET);
-
-          /* Disable acknowledge when last byte is to be received */
-
-          priv->dcnt--;
-          if (priv->dcnt == 1)
-            {
-              /* autoend? */
-            }
-
-#ifdef CONFIG_I2C_POLLED
-          leave_critical_section(flags);
-#endif
-        }
-    }
-
-  /* Do we have more bytes to send, enable/disable buffer interrupts
-   * (these ISRs could be replaced by DMAs)
-   */
-
-#ifndef CONFIG_I2C_POLLED
-  if (priv->dcnt > 0)
-    {
-      stm32_i2c_traceevent(priv, I2CEVENT_REITBUFEN, 0);
-      stm32_i2c_enableinterrupts(priv);
-    }
-  else if ((priv->dcnt == 0) && (priv->msgc == 0))
-    {
-      stm32_i2c_traceevent(priv, I2CEVENT_DISITBUFEN, 0);
-      stm32_i2c_disableinterrupts(priv);
-    }
-#endif
-
-  /* Was last byte received or sent?  Hmmm... the F2 and F4 seems to differ from
-   * the F1 in that BTF is not set after data is received (only RXNE).
-   */
-
-  if (priv->dcnt <= 0 && STATUS_TC(status))
-    {
-      /* Do we need to terminate or restart after this byte?
-       * If there are more messages to send, then we may:
-       *
-       *  - continue with repeated start
-       *  - or just continue sending writeable part
-       *  - or we close down by sending the stop bit
-       */
-
-      if (priv->msgc > 0)
-        {
-          if (priv->msgv->flags & I2C_M_NOSTART)
-            {
-              stm32_i2c_traceevent(priv, I2CEVENT_BTFNOSTART, priv->msgc);
-              priv->ptr   = priv->msgv->buffer;
-              priv->dcnt  = priv->msgv->length;
-              priv->flags = priv->msgv->flags;
-              priv->msgv++;
-              priv->msgc--;
-
-              /* Restart this ISR! */
-
-#ifndef CONFIG_I2C_POLLED
-              stm32_i2c_enableinterrupts(priv);
-#endif
-            }
-          else
-            {
-              stm32_i2c_traceevent(priv, I2CEVENT_BTFRESTART, priv->msgc);
-              stm32_i2c_sendstart(priv);
-            }
-        }
-      else if (priv->msgv)
-        {
-          stm32_i2c_traceevent(priv, I2CEVENT_BTFSTOP, 0);
-
-          stm32_i2c_sendstop(priv);
-
-          /* Is there a thread waiting for this event (there should be) */
-
-#ifndef CONFIG_I2C_POLLED
-          if (priv->intstate == INTSTATE_WAITING)
-            {
-              /* Yes.. inform the thread that the transfer is complete
-               * and wake it up.
-               */
-
-              nxsem_post(&priv->sem_isr);
-              priv->intstate = INTSTATE_DONE;
-            }
-#else
-          priv->intstate = INTSTATE_DONE;
-#endif
-
-          /* Mark that we have stopped with this transaction */
-
-          priv->msgv = NULL;
-        }
-    }
-
-  /* Check for errors, in which case, stop the transfer and return
-   * Note that in master reception mode AF becomes set on last byte
-   * since ACK is not returned. We should ignore this error.
-   */
-
-  if ((status & I2C_ISR_ERRORMASK) != 0)
-    {
-      stm32_i2c_traceevent(priv, I2CEVENT_ERROR, 0);
-
-      /* Clear interrupt flags */
-
-      stm32_i2c_clearinterrupts(priv);
-
-      /* Is there a thread waiting for this event (there should be) */
-
-#ifndef CONFIG_I2C_POLLED
-      if (priv->intstate == INTSTATE_WAITING)
-        {
-          /* Yes.. inform the thread that the transfer is complete
-           * and wake it up.
-           */
-
-          nxsem_post(&priv->sem_isr);
-          priv->intstate = INTSTATE_DONE;
-        }
-#else
-      priv->intstate = INTSTATE_DONE;
-#endif
-    }
-
-  priv->status = status;
-  return OK;
-}
-
-/************************************************************************************
- * Name: stm32_i2c_isr_process
- *
- * Description:
- *   Common I2C interrupt service routine
- *
- ************************************************************************************/
-
-#ifndef CONFIG_I2C_POLLED
-static int stm32_i2c_isr(int irq, void *context, FAR void *arg)
-{
-  struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg;
-
-  DEBUGASSERT(priv != NULL);
-  return stm32_i2c_isr_process(priv);
-}
-#endif
-
-/************************************************************************************
- * Private Initialization and Deinitialization
- ************************************************************************************/
-
-/************************************************************************************
- * Name: stm32_i2c_init
- *
- * Description:
- *   Setup the I2C hardware, ready for operation with defaults
- *
- ************************************************************************************/
-
-static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
-{
-  int ret;
-
-  /* Power-up and configure GPIOs */
-  /* Enable power and reset the peripheral */
-
-  modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit);
-  modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit);
-  modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0);
-
-  /* Configure pins */
-
-  ret = stm32_configgpio(priv->config->scl_pin);
-  if (ret < 0)
-    {
-      return ret;
-    }
-
-  ret = stm32_configgpio(priv->config->sda_pin);
-  if (ret < 0)
-    {
-      stm32_unconfiggpio(priv->config->scl_pin);
-      return ret;
-    }
-
-#ifndef CONFIG_I2C_POLLED
-  /* Attach and enable the I2C interrupt */
-
-  irq_attach(priv->config->irq, stm32_i2c_isr, priv);
-  up_enable_irq(priv->config->irq);
-#endif
-
-  /* Set peripheral frequency, where it must be at least 2 MHz  for 100 kHz
-   * or 4 MHz for 400 kHz.  This also disables all I2C interrupts.
-   */
-
-  /* Force a frequency update */
-
-  priv->frequency = 0;
-
-  /* TODO: i2c clock source RCC_CCIPR */
-  /* RCC_CCIPR I2CxSEL (default is PCLK clock) */
-
-  stm32_i2c_setclock(priv, 100000);
-
-  /* Enable I2C */
-
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
-  return OK;
-}
-
-/************************************************************************************
- * Name: stm32_i2c_deinit
- *
- * Description:
- *   Shutdown the I2C hardware
- *
- ************************************************************************************/
-
-static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv)
-{
-  /* Disable I2C */
-
-  stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0);
-
-  /* Unconfigure GPIO pins */
-
-  stm32_unconfiggpio(priv->config->scl_pin);
-  stm32_unconfiggpio(priv->config->sda_pin);
-
-  /* Disable and detach interrupts */
-
-#ifndef CONFIG_I2C_POLLED
-  up_disable_irq(priv->config->irq);
-  irq_detach(priv->config->irq);
-#endif
-
-  /* Disable clocking */
-
-  modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0);
-  return OK;
-}
-
-/************************************************************************************
- * Device Driver Operations
- ************************************************************************************/
-
-/************************************************************************************
- * Name: stm32_i2c_transfer
- *
- * Description:
- *   Generic I2C transfer function
- *
- ************************************************************************************/
-
-static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
-                              int count)
-{
-  FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev;
-  uint32_t status = 0;
-  int ret = OK;
-
-  DEBUGASSERT(dev != NULL && msgs != NULL && count > 0);
-
-  /* Ensure that address or flags don't change meanwhile */
-
-  stm32_i2c_sem_wait(priv);
-
-  /* Wait for any STOP in progress. */
-
-  stm32_i2c_sem_waitstop(priv);
-
-  /* Clear any pending error interrupts */
-
-  stm32_i2c_clearinterrupts(priv);
-
-  /* "Note: When the STOP, START or PEC bit is set, the software must
-   *  not perform any write access to I2C_CR1 before this bit is
-   *  cleared by hardware. Otherwise there is a risk of setting a
-   *  second STOP, START or PEC request."  However, if the bits are
-   *  not cleared by hardware, then we will have to do that from hardware.
-   */
-
-  stm32_i2c_clrstart(priv);
-
-  /* Old transfers are done */
-
-  priv->msgv = msgs;
-  priv->msgc = count;
-
-  /* Reset I2C trace logic */
-
-  stm32_i2c_tracereset(priv);
-
-  /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !)
-   * REVISIT: Note that the frequency is set only on the first message.
-   * This could be extended to support different transfer frequencies for
-   * each message segment.
-   */
-
-  stm32_i2c_setclock(priv, msgs->frequency);
-
-  /* Trigger start condition, then the process moves into the ISR.  I2C
-   * interrupts will be enabled within stm32_i2c_waitdone().
-   */
-
-  priv->status = 0;
-
-#ifndef CONFIG_I2C_POLLED
-  stm32_i2c_enableinterrupts(priv);
-#endif
-
-  stm32_i2c_sendstart(priv);
-
-  /* Wait for an ISR, if there was a timeout, fetch latest status to get
-   * the BUSY flag.
-   */
-
-  if (stm32_i2c_sem_waitdone(priv) < 0)
-    {
-      status = stm32_i2c_getstatus(priv);
-      ret = -ETIMEDOUT;
-
-      i2cerr("ERROR: Timed out: CR1: %08x status: %08x\n",
-             stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET), status);
-
-      /* "Note: When the STOP, START or PEC bit is set, the software must
-       *  not perform any write access to I2C_CR1 before this bit is
-       *  cleared by hardware. Otherwise there is a risk of setting a
-       *  second STOP, START or PEC request."
-       */
-
-      stm32_i2c_clrstart(priv);
-
-      /* Clear busy flag in case of timeout */
-
-      status = priv->status & 0xffff;
-    }
-  else
-    {
-      /* clear SR2 (BUSY flag) as we've done successfully */
-
-      status = priv->status & 0xffff;
-    }
-
-  status &= ~I2C_ISR_BUSY;
-#if 0
-  /* Refresh status */
-  do
-    {
-      status = stm32_i2c_getstatus(priv);
-    }
-  while (STATUS_BUSY(status));
-#endif
-
-  /* Check for error status conditions */
-
-  if ((status & I2C_ISR_ERRORMASK) != 0)
-    {
-      /* I2C_SR1_ERRORMASK is the 'OR' of the following individual bits: */
-
-      if (status & I2C_INT_BERR)
-        {
-          /* Bus Error */
-
-          ret = -EIO;
-        }
-      else if (status & I2C_INT_ARLO)
-        {
-          /* Arbitration Lost (master mode) */
-
-          ret = -EAGAIN;
-        }
-
-      /* TODO Acknowledge failure */
-
-      else if (status & I2C_INT_OVR)
-        {
-          /* Overrun/Underrun */
-
-          ret = -EIO;
-        }
-      else if (status & I2C_INT_PECERR)
-        {
-          /* PEC Error in reception */
-
-          ret = -EPROTO;
-        }
-      else if (status & I2C_INT_TIMEOUT)
-        {
-          /* Timeout or Tlow Error */
-
-          ret = -ETIME;
-        }
-
-      /* This is not an error and should never happen since SMBus is not
-       * enabled
-       */
-
-      else /* if (status & I2C_INT_ALERT) */
-        {
-          /* SMBus alert is an optional signal with an interrupt line for devices
-           * that want to trade their ability to master for a pin.
-           */
-
-          ret = -EINTR;
-        }
-    }
-
-  /* This is not an error, but should not happen.  The BUSY signal can hang,
-   * however, if there are unhealthy devices on the bus that need to be reset.
-   * NOTE:  We will only see this buy indication if stm32_i2c_sem_waitdone()
-   * fails above;  Otherwise it is cleared.
-   */
-
-  else if ((status & I2C_ISR_BUSY) != 0)
-    {
-      /* I2C Bus is for some reason busy */
-
-      ret = -EBUSY;
-    }
-
-  /* Dump the trace result */
-
-  stm32_i2c_tracedump(priv);
-  stm32_i2c_sem_post(priv);
-  return ret;
-}
-
-/************************************************************************************
- * Name: stm32_i2c_reset
- *
- * Description:
- *   Perform an I2C bus reset in an attempt to break loose stuck I2C devices.
- *
- * Input Parameters:
- *   dev   - Device-specific state data
- *
- * Returned Value:
- *   Zero (OK) on success; a negated errno value on failure.
- *
- ************************************************************************************/
-
-#ifdef CONFIG_I2C_RESET
-static int stm32_i2c_reset(FAR struct i2c_master_s * dev)
-{
-  FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev;
-  unsigned int clock_count;
-  unsigned int stretch_count;
-  uint32_t scl_gpio;
-  uint32_t sda_gpio;
-  uint32_t frequency;
-  int ret = -EIO;
-
-  DEBUGASSERT(dev);
-
-  /* Our caller must own a ref */
-
-  DEBUGASSERT(priv->refs > 0);
-
-  /* Lock out other clients */
-
-  stm32_i2c_sem_wait(priv);
-
-  /* Save the current frequency */
-
-  frequency = priv->frequency;
-
-  /* De-init the port */
-
-  stm32_i2c_deinit(priv);
-
-  /* Use GPIO configuration to un-wedge the bus */
-
-  scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin);
-  sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin);
-
-  /* Let SDA go high */
-
-  stm32_gpiowrite(sda_gpio, 1);
-
-  /* Clock the bus until any slaves currently driving it let it go. */
-
-  clock_count = 0;
-  while (!stm32_gpioread(sda_gpio))
-    {
-      /* Give up if we have tried too hard */
-
-      if (clock_count++ > 10)
-        {
-          goto out;
-        }
-
-      /* Sniff to make sure that clock stretching has finished.
-       *
-       * If the bus never relaxes, the reset has failed.
-       */
-
-      stretch_count = 0;
-      while (!stm32_gpioread(scl_gpio))
-        {
-          /* Give up if we have tried too hard */
-
-          if (stretch_count++ > 10)
-            {
-              goto out;
-            }
-
-          up_udelay(10);
-        }
-
-      /* Drive SCL low */
-
-      stm32_gpiowrite(scl_gpio, 0);
-      up_udelay(10);
-
-      /* Drive SCL high again */
-
-      stm32_gpiowrite(scl_gpio, 1);
-      up_udelay(10);
-    }
-
-  /* Generate a start followed by a stop to reset slave
-   * state machines.
-   */
-
-  stm32_gpiowrite(sda_gpio, 0);
-  up_udelay(10);
-  stm32_gpiowrite(scl_gpio, 0);
-  up_udelay(10);
-  stm32_gpiowrite(scl_gpio, 1);
-  up_udelay(10);
-  stm32_gpiowrite(sda_gpio, 1);
-  up_udelay(10);
-
-  /* Revert the GPIO configuration. */
-
-  stm32_unconfiggpio(sda_gpio);
-  stm32_unconfiggpio(scl_gpio);
-
-  /* Re-init the port */
-
-  ret = stm32_i2c_init(priv);
-  if (ret < 0)
-    {
-      i2cerr("ERROR: stm32_i2c_init failed: %d\n", ret);
-    }
-
-  /* Restore the frequency */
-
-  stm32_i2c_setclock(priv, frequency);
-
-out:
-
-  /* Release the port for re-use by other clients */
-
-  stm32_i2c_sem_post(priv);
-  return ret;
-}
-#endif /* CONFIG_I2C_RESET */
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Name: stm32_i2cbus_initialize
- *
- * Description:
- *   Initialize one I2C bus
- *
- ************************************************************************************/
-
-FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
-{
-  struct stm32_i2c_priv_s *priv = NULL;
-  irqstate_t flags;
-  int ret;
-
-#if STM32_PCLK1_FREQUENCY < 4000000
-#   warning STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 400 kHz operation.
-#endif
-
-#if STM32_PCLK1_FREQUENCY < 2000000
-#   warning STM32_I2C_INIT: Peripheral clock must be at least 2 MHz to support 100 kHz operation.
-  return NULL;
-#endif
-
-  /* Get I2C private structure. */
-
-  switch (port)
-    {
-#ifdef CONFIG_STM32F0L0_I2C1
-      case 1:
-        priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv;
-        break;
-#endif
-#ifdef CONFIG_STM32F0L0_I2C2
-      case 2:
-        priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv;
-        break;
-#endif
-#ifdef CONFIG_STM32F0L0_I2C3
-      case 3:
-        priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv;
-        break;
-#endif
-      default:
-        return NULL;
-    }
-
-  /* Init private data for the first time, increment refs count,
-   * power-up hardware and configure GPIOs.
-   */
-
-  flags = enter_critical_section();
-
-  if ((volatile int)priv->refs++ == 0)
-    {
-      stm32_i2c_sem_init(priv);
-      ret = stm32_i2c_init(priv);
-      if (ret < 0)
-        {
-          i2cerr("ERROR: stm32_i2c_init failed: %d\n", ret);
-        }
-    }
-
-  leave_critical_section(flags);
-  return (struct i2c_master_s *)priv;
-}
-
-/************************************************************************************
- * Name: stm32_i2cbus_uninitialize
- *
- * Description:
- *   Uninitialize an I2C bus
- *
- ************************************************************************************/
-
-int stm32_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
-{
-  FAR struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)dev;
-  irqstate_t flags;
-
-  DEBUGASSERT(dev);
-
-  /* Decrement refs and check for underflow */
-
-  if (priv->refs == 0)
-    {
-      return -ENODEV;
-    }
-
-  flags = enter_critical_section();
-
-  if (--priv->refs)
-    {
-      leave_critical_section(flags);
-      return OK;
-    }
-
-  leave_critical_section(flags);
-
-  /* Disable power and other HW resource (GPIO's) */
-
-  stm32_i2c_deinit(priv);
-
-  /* Release unused resources */
-
-  stm32_i2c_sem_destroy(priv);
-  return OK;
-}
-
-#endif /* CONFIG_STM32F0L0_I2C1 || CONFIG_STM32F0L0_I2C2 || CONFIG_STM32F0L0_I2C3 */
diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig
new file mode 100644
index 00000000000..47e19558f4d
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/Kconfig
@@ -0,0 +1,1930 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+comment "STM32F0/L0/G0 Configuration Options"
+
+choice
+	prompt "ST STM32F0/L0/G0 Chip Selection"
+	default ARCH_CHIP_STM32F051R8 if ARCH_CHIP_STM32F0
+	default ARCH_CHIP_STM32L073RZ if ARCH_CHIP_STM32L0
+	default ARCH_CHIP_STM32G071RB if ARCH_CHIP_STM32G0
+	depends on ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0
+
+config ARCH_CHIP_STM32F030C6
+	bool "STM32F030C6"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_VALUELINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F030C8
+	bool "STM32F030C8"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_VALUELINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F030CC
+	bool "STM32F030CC"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_VALUELINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F030F4
+	bool "STM32F030F4"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_VALUELINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F030K6
+	bool "STM32F030K6"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_VALUELINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F030R8
+	bool "STM32F030R8"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_VALUELINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F030RC
+	bool "STM32F030RC"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_VALUELINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F031C4
+	bool "STM32F031C4"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F031C6
+	bool "STM32F031C6"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F031E6
+	bool "STM32F031E6"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F031F4
+	bool "STM32F031F4"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F031F6
+	bool "STM32F031F6"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F031G4
+	bool "STM32F031G4"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F031G6
+	bool "STM32F031G6"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F031K4
+	bool "STM32F031K4"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F031K6
+	bool "STM32F031K6"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F038C6
+	bool "STM32F038C6"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F038E6
+	bool "STM32F038E6"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F038F6
+	bool "STM32F038F6"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F038G6
+	bool "STM32F038G6"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F038K6
+	bool "STM32F038K6"
+	select STM32F0L0G0_STM32F03X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F042C4
+	bool "STM32F042C4"
+	select STM32F0L0G0_STM32F04X
+	select STM32F0L0G0_USBLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F042C6
+	bool "STM32F042C6"
+	select STM32F0L0G0_STM32F04X
+	select STM32F0L0G0_USBLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F042F4
+	bool "STM32F042F4"
+	select STM32F0L0G0_STM32F04X
+	select STM32F0L0G0_USBLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F042F6
+	bool "STM32F042F6"
+	select STM32F0L0G0_STM32F04X
+	select STM32F0L0G0_USBLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F042G4
+	bool "STM32F042G4"
+	select STM32F0L0G0_STM32F04X
+	select STM32F0L0G0_USBLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F042G6
+	bool "STM32F042G6"
+	select STM32F0L0G0_STM32F04X
+	select STM32F0L0G0_USBLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F042K4
+	bool "STM32F042K4"
+	select STM32F0L0G0_STM32F04X
+	select STM32F0L0G0_USBLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F042K6
+	bool "STM32F042K6"
+	select STM32F0L0G0_STM32F04X
+	select STM32F0L0G0_USBLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F042T6
+	bool "STM32F042T6"
+	select STM32F0L0G0_STM32F04X
+	select STM32F0L0G0_USBLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F048C6
+	bool "STM32F048C6"
+	select STM32F0L0G0_STM32F04X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F048G6
+	bool "STM32F048G6"
+	select STM32F0L0G0_STM32F04X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F048T6
+	bool "STM32F048T6"
+	select STM32F0L0G0_STM32F04X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F051C4
+	bool "STM32F051C4"
+	select STM32F0L0G0_STM32F05X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F051C6
+	bool "STM32F051C6"
+	select STM32F0L0G0_STM32F05X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F051C8
+	bool "STM32F051C8"
+	select STM32F0L0G0_STM32F05X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F051K4
+	bool "STM32F051K4"
+	select STM32F0L0G0_STM32F05X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F051K6
+	bool "STM32F051K6"
+	select STM32F0L0G0_STM32F05X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F051K8
+	bool "STM32F051K8"
+	select STM32F0L0G0_STM32F05X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F051R4
+	bool "STM32F051R4"
+	select STM32F0L0G0_STM32F05X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F051R6
+	bool "STM32F051R6"
+	select STM32F0L0G0_STM32F05X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F051R8
+	bool "STM32F051R8"
+	select STM32F0L0G0_STM32F05X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F051T8
+	bool "STM32F051T8"
+	select STM32F0L0G0_STM32F05X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F058C8
+	bool "STM32F058C8"
+	select STM32F0L0G0_STM32F05X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F058R8
+	bool "STM32F058R8"
+	select STM32F0L0G0_STM32F05X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F058T8
+	bool "STM32F058T8"
+	select STM32F0L0G0_STM32F05X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F070C6
+	bool "STM32F070C6"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_VALUELINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F070CB
+	bool "STM32F070CB"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_VALUELINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F070F6
+	bool "STM32F070F6"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_VALUELINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F070RB
+	bool "STM32F070RB"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_VALUELINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F071C8
+	bool "STM32F071C8"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F071CB
+	bool "STM32F071CB"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F071RB
+	bool "STM32F071RB"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F071V8
+	bool "STM32F071V8"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F071VB
+	bool "STM32F071VB"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F072C8
+	bool "STM32F072C8"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_USBLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F072CB
+	bool "STM32F072CB"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_USBLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F072R8
+	bool "STM32F072R8"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_USBLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F072RB
+	bool "STM32F072RB"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_USBLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F072V8
+	bool "STM32F072V8"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_USBLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F072VB
+	bool "STM32F072VB"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_USBLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F078CB
+	bool "STM32F078CB"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F078RB
+	bool "STM32F078RB"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F078VB
+	bool "STM32F078VB"
+	select STM32F0L0G0_STM32F07X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F091CB
+	bool "STM32F091CB"
+	select STM32F0L0G0_STM32F09X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F091CC
+	bool "STM32F091CC"
+	select STM32F0L0G0_STM32F09X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F091RB
+	bool "STM32F091RB"
+	select STM32F0L0G0_STM32F09X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F091RC
+	bool "STM32F091RC"
+	select STM32F0L0G0_STM32F09X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F091VB
+	bool "STM32F091VB"
+	select STM32F0L0G0_STM32F09X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F091VC
+	bool "STM32F091VC"
+	select STM32F0L0G0_STM32F09X
+	select STM32F0L0G0_ACCESSLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F098CC
+	bool "STM32F098CC"
+	select STM32F0L0G0_STM32F09X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F098RC
+	bool "STM32F098RC"
+	select STM32F0L0G0_STM32F09X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32F098VC
+	bool "STM32F098VC"
+	select STM32F0L0G0_STM32F09X
+	select STM32F0L0G0_LOWVOLTLINE
+	depends on ARCH_CHIP_STM32F0
+
+config ARCH_CHIP_STM32G071EB
+	bool "STM32G071EB"
+	select STM32F0L0G0_STM32G0
+	depends on ARCH_CHIP_STM32G0
+
+config ARCH_CHIP_STM32G071G8
+	bool "STM32G071G8"
+	select STM32F0L0G0_STM32G0
+	depends on ARCH_CHIP_STM32G0
+
+config ARCH_CHIP_STM32G071GB
+	bool "STM32G071GB"
+	select STM32F0L0G0_STM32G0
+	depends on ARCH_CHIP_STM32G0
+
+config ARCH_CHIP_STM32G071G8XN
+	bool "STM32G071G8XN"
+	select STM32F0L0G0_STM32G0
+	depends on ARCH_CHIP_STM32G0
+
+config ARCH_CHIP_STM32G071GBXN
+	bool "STM32G071GBXN"
+	select STM32F0L0G0_STM32G0
+	depends on ARCH_CHIP_STM32G0
+
+config ARCH_CHIP_STM32G071K8
+	bool "STM32G071K8"
+	select STM32F0L0G0_STM32G0
+	depends on ARCH_CHIP_STM32G0
+
+config ARCH_CHIP_STM32G071KB
+	bool "STM32G071KB"
+	select STM32F0L0G0_STM32G0
+	depends on ARCH_CHIP_STM32G0
+
+config ARCH_CHIP_STM32G071K8XN
+	bool "STM32G071K8XN"
+	select STM32F0L0G0_STM32G0
+	depends on ARCH_CHIP_STM32G0
+
+config ARCH_CHIP_STM32G071KBXN
+	bool "STM32G071KBXN"
+	select STM32F0L0G0_STM32G0
+	depends on ARCH_CHIP_STM32G0
+
+config ARCH_CHIP_STM32G071C8
+	bool "STM32G071C8"
+	select STM32F0L0G0_STM32G0
+	depends on ARCH_CHIP_STM32G0
+
+config ARCH_CHIP_STM32G071CB
+	bool "STM32G071CB"
+	select STM32F0L0G0_STM32G0
+	depends on ARCH_CHIP_STM32G0
+
+config ARCH_CHIP_STM32G071R8
+	bool "STM32G071R8"
+	select STM32F0L0G0_STM32G0
+	depends on ARCH_CHIP_STM32G0
+
+config ARCH_CHIP_STM32G071RB
+	bool "STM32G071RB"
+	select STM32F0L0G0_STM32G0
+	depends on ARCH_CHIP_STM32G0
+
+config ARCH_CHIP_STM32L071K8
+	bool "STM32L071K8"
+	select ARCH_CHIP_STM32L071XX
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L071KB
+	bool "STM32L071KB"
+	select ARCH_CHIP_STM32L071XX
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L071KZ
+	bool "STM32L071KZ"
+	select ARCH_CHIP_STM32L071XX
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L071C8
+	bool "STM32L071C8"
+	select ARCH_CHIP_STM32L071XX
+	select STM32F0L0G0_HAVE_USART5
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C3
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L071CB
+	bool "STM32L071CB"
+	select ARCH_CHIP_STM32L071XX
+	select STM32F0L0G0_HAVE_USART5
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C3
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L071CZ
+	bool "STM32L071CZ"
+	select ARCH_CHIP_STM32L071XX
+	select STM32F0L0G0_HAVE_USART5
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C3
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L071V8
+	bool "STM32L071V8"
+	select ARCH_CHIP_STM32L071XX
+	select STM32F0L0G0_HAVE_USART5
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C3
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L071VB
+	bool "STM32L071VB"
+	select ARCH_CHIP_STM32L071XX
+	select STM32F0L0G0_HAVE_USART5
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C3
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L071VZ
+	bool "STM32L071VZ"
+	select ARCH_CHIP_STM32L071XX
+	select STM32F0L0G0_HAVE_USART5
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C3
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L071RB
+	bool "STM32L071RB"
+	select ARCH_CHIP_STM32L071XX
+	select STM32F0L0G0_HAVE_USART5
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C3
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L071RZ
+	bool "STM32L071RZ"
+	select ARCH_CHIP_STM32L071XX
+	select STM32F0L0G0_HAVE_USART5
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C3
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L072V8
+	bool "STM32L072V8"
+	select ARCH_CHIP_STM32L072XX
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C3
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L072VB
+	bool "STM32L072VB"
+	select ARCH_CHIP_STM32L072XX
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C3
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L072VZ
+	bool "STM32L072VZ"
+	select ARCH_CHIP_STM32L072XX
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C3
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L072KB
+	bool "STM32L072KB"
+	select ARCH_CHIP_STM32L072XX
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L072KZ
+	bool "STM32L072KZ"
+	select ARCH_CHIP_STM32L072XX
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L072CB
+	bool "STM32L072CB"
+	select ARCH_CHIP_STM32L072XX
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C3
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L072CZ
+	bool "STM32L072CZ"
+	select ARCH_CHIP_STM32L072XX
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C3
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L072RB
+	bool "STM32L072RB"
+	select ARCH_CHIP_STM32L072XX
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C3
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L072RZ
+	bool "STM32L072RZ"
+	select ARCH_CHIP_STM32L072XX
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C3
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L073V8
+	bool "STM32L073V8"
+	select ARCH_CHIP_STM32L073XX
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L073VB
+	bool "STM32L073VB"
+	select ARCH_CHIP_STM32L073XX
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L073VZ
+	bool "STM32L073VZ"
+	select ARCH_CHIP_STM32L073XX
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L073CB
+	bool "STM32L073CB"
+	select ARCH_CHIP_STM32L073XX
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L073CZ
+	bool "STM32L073CZ"
+	select ARCH_CHIP_STM32L073XX
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L073RB
+	bool "STM32L073RB"
+	select ARCH_CHIP_STM32L073XX
+	depends on ARCH_CHIP_STM32L0
+
+config ARCH_CHIP_STM32L073RZ
+	bool "STM32L073RZ"
+	select ARCH_CHIP_STM32L073XX
+	depends on ARCH_CHIP_STM32L0
+
+endchoice # ST STM32F0/L0 Chip Selection
+
+choice
+	prompt "Override Flash Size Designator"
+	default STM32F0L0G0_FLASH_CONFIG_DEFAULT
+	depends on ARCH_CHIP_STM32
+	---help---
+		STM32F series parts numbering (sans the package type) ends with a number or letter
+		that designates the FLASH size.
+
+			Designator  Size in KiB
+				4    16
+				6    32
+				8    64
+				B    128
+				C    256
+				D    384
+				E    512
+				F    768
+				G    1024
+				I    2048
+
+		This configuration option defaults to using the configuration based on that designator
+		or the default smaller size if there is no last character designator is present in the
+		STM32 Chip Selection.
+
+		Examples:
+			If the STM32F407VE is chosen, the Flash configuration would be 'E', if a variant of
+			the part with a  2048 KiB Flash is released in the future one could simply select
+			the 'I' designator here.
+
+			If an STM32F42xxx or  Series parts is chosen the default Flash configuration will be 'G'
+			and can be set herein to 'I' to choose the larger FLASH part.
+
+config STM32F0L0G0_FLASH_CONFIG_DEFAULT
+	bool "Default"
+
+config STM32F0L0G0_FLASH_CONFIG_4
+	bool "4 16KiB"
+
+config STM32F0L0G0_FLASH_CONFIG_6
+	bool "6 32KiB"
+
+config STM32F0L0G0_FLASH_CONFIG_8
+	bool "8 64KiB"
+
+config STM32F0L0G0_FLASH_CONFIG_B
+	bool "B 128KiB"
+
+config STM32F0L0G0_FLASH_CONFIG_C
+	bool "C 256KiB"
+
+config STM32F0L0G0_FLASH_CONFIG_D
+	bool "D 384KiB"
+
+config STM32F0L0G0_FLASH_CONFIG_E
+	bool "E 512KiB"
+
+config STM32F0L0G0_FLASH_CONFIG_F
+	bool "F 768KiB"
+
+config STM32F0L0G0_FLASH_CONFIG_G
+	bool "G 1024KiB"
+
+config STM32F0L0G0_FLASH_CONFIG_I
+	bool "I 2048KiB"
+
+endchoice
+
+config STM32F0L0G0_STM32F0
+	bool
+	default n
+	select STM32F0L0G0_HAVE_USART3
+	select STM32F0L0G0_HAVE_USART4
+	select STM32F0L0G0_HAVE_TIM1
+	select STM32F0L0G0_HAVE_TIM2
+	select STM32F0L0G0_HAVE_TIM3
+	select STM32F0L0G0_HAVE_TIM6
+	select STM32F0L0G0_HAVE_TIM7
+	select STM32F0L0G0_HAVE_TIM14
+	select STM32F0L0G0_HAVE_TIM15
+	select STM32F0L0G0_HAVE_TIM16
+	select STM32F0L0G0_HAVE_TIM17
+	select STM32F0L0G0_HAVE_ADC1_DMA
+	select STM32F0L0G0_HAVE_IP_USART_V1
+	select STM32F0L0G0_HAVE_IP_EXTI_V1
+
+config STM32F0L0G0_STM32G0
+	bool
+	default n
+	select STM32F0L0G0_HAVE_DMAMUX
+	select STM32F0L0G0_HAVE_IP_USART_V2
+	select STM32F0L0G0_HAVE_IP_EXTI_V2
+
+config STM32F0L0G0_STM32L0
+	bool
+	default n
+	select STM32F0L0G0_ENERGYLITE
+	select STM32F0L0G0_HAVE_VREFINT
+	select STM32F0L0G0_HAVE_ADC1_DMA
+	select STM32F0L0G0_HAVE_IP_USART_V1
+	select STM32F0L0G0_HAVE_IP_EXTI_V1
+
+config STM32F0L0G0_STM32F03X
+	bool
+	default n
+	select STM32F0L0G0_STM32F0
+
+config STM32F0L0G0_STM32F04X
+	bool
+	default n
+	select STM32F0L0G0_STM32F0
+
+config STM32F0L0G0_STM32F05X
+	bool
+	default n
+	select STM32F0L0G0_STM32F0
+
+config STM32F0L0G0_STM32F07X
+	bool
+	default n
+	select STM32F0L0G0_STM32F0
+
+config STM32F0L0G0_STM32F09X
+	bool
+	default n
+	select STM32F0L0G0_STM32F0
+	select STM32F0L0G0_HAVE_HSI48
+	select STM32F0L0G0_HAVE_DMA2
+
+config STM32F0L0G0_VALUELINE
+	bool
+	default n
+	select STM32F0L0G0_HAVE_USART5
+	select STM32F0L0G0_HAVE_SPI2 if STM32F0L0G0_HIGHDENSITY
+	select STM32F0L0G0_HAVE_SPI3 if STM32F0L0G0_HIGHDENSITY
+
+config STM32F0L0G0_ACCESSLINE
+	bool
+	default n
+	select STM32F0L0G0_HAVE_USART5
+	select STM32F0L0G0_HAVE_CAN1
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_SPI3
+
+config STM32F0L0G0_LOWVOLTLINE
+	bool
+	default n
+	select STM32F0L0G0_HAVE_USART5
+	select STM32F0L0G0_HAVE_CAN1
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_SPI3
+
+config STM32F0L0G0_USBLINE
+	bool
+	default n
+	select STM32F0L0G0_HAVE_HSI48
+	select STM32F0L0G0_HAVE_CAN1
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_SPI3
+	select STM32F0L0G0_HAVE_USBDEV
+
+config STM32F0L0G0_ENERGYLITE
+	bool
+	default n
+
+config ARCH_CHIP_STM32L071XX
+	bool
+	select STM32F0L0G0_STM32L0
+	select STM32F0L0G0_HAVE_RNG
+	select STM32F0L0G0_HAVE_HSI48
+	select STM32F0L0G0_HAVE_USART4
+
+config ARCH_CHIP_STM32L072XX
+	bool
+	select STM32F0L0G0_STM32L0
+	select STM32F0L0G0_HAVE_RNG
+	select STM32F0L0G0_HAVE_HSI48
+	select STM32F0L0G0_HAVE_USART4
+	select STM32F0L0G0_HAVE_USART5
+	select STM32F0L0G0_HAVE_I2C2
+	select STM32F0L0G0_HAVE_USBDEV
+
+config ARCH_CHIP_STM32L073XX
+	bool
+	select STM32F0L0G0_STM32L0
+	select STM32F0L0G0_HAVE_RNG
+	select STM32F0L0G0_HAVE_HSI48
+	select STM32F0L0G0_HAVE_USART4
+	select STM32F0L0G0_HAVE_USART5
+	select STM32F0L0G0_HAVE_SPI2
+	select STM32F0L0G0_HAVE_I2C2
+	select STM32F0L0G0_HAVE_I2C3
+	select STM32F0L0G0_HAVE_USBDEV
+
+config STM32F0L0G0_DFU
+	bool "DFU bootloader"
+	default n
+	depends on !STM32F0L0G0_VALUELINE
+	---help---
+		Configure and position code for use with the STMicro DFU bootloader.  Do
+		not select this option if you will load code using JTAG/SWM.
+
+choice
+	prompt "SysTick clock source"
+	default STM32F0L0G0_SYSTICK_CORECLK
+
+config STM32F0L0G0_SYSTICK_CORECLK
+	bool "Cortex-M0 core clock"
+
+config STM32F0L0G0_SYSTICK_CORECLK_DIV16
+	bool "Cortex-M0 core clock divided by 16"
+
+endchoice
+
+menu "STM32 Peripheral Support"
+
+# These "hidden" settings determine is a peripheral option is available for the
+# selection MCU
+
+config STM32F0L0G0_HAVE_AES
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_VREFINT
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_CCM
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_HSI48
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_LCD
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_USBDEV
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_FSMC
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_USART3
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_USART4
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_USART5
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_USART6
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_USART7
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_USART8
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_TIM1
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_TIM2
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_TIM3
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_TIM6
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_TIM7
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_TIM14
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_TIM15
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_TIM16
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_TIM17
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_TSC
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_ADC1_DMA
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_CEC
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_CAN1
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_COMP1
+       bool
+       default n
+
+config STM32F0L0G0_HAVE_COMP2
+       bool
+       default n
+
+config STM32F0L0G0_HAVE_DAC1
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_DMAMUX
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_DMA2
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_RNG
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_I2C2
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_I2C3
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_SPI2
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_SPI3
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_SPI4
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_SPI5
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_SPI6
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_SAIPLL
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_SDIO
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_I2SPLL
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_OPAMP1
+       bool
+       default n
+
+config STM32F0L0G0_HAVE_OPAMP2
+       bool
+       default n
+
+config STM32F0L0G0_HAVE_OPAMP3
+       bool
+       default n
+
+config STM32F0L0G0_HAVE_OPAMP4
+       bool
+       default n
+
+# These are STM32 peripherals IP blocks
+
+config STM32F0L0G0_HAVE_IP_USART_V1
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_IP_USART_V2
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_IP_EXTI_V1
+	bool
+	default n
+
+config STM32F0L0G0_HAVE_IP_EXTI_V2
+	bool
+	default n
+
+# These are the peripheral selections proper
+
+config STM32F0L0G0_ADC1
+	bool "ADC1"
+	default n
+	depends on EXPERIMENTAL
+	select STM32F0L0G0_ADC
+
+config STM32F0L0G0_COMP1
+	bool "COMP1"
+	default n
+	depends on STM32F0L0G0_HAVE_COMP1
+
+config STM32F0L0G0_COMP2
+	bool "COMP2"
+	default n
+	depends on STM32F0L0G0_HAVE_COMP2
+
+config STM32F0L0G0_BKP
+	bool "BKP"
+	default n
+
+config STM32F0L0G0_BKPSRAM
+	bool "Enable BKP RAM Domain"
+	default n
+
+config STM32F0L0G0_CAN1
+	bool "CAN1"
+	default n
+	select CAN
+	select STM32F0L0G0_CAN
+	depends on STM32F0L0G0_HAVE_CAN1
+
+config STM32F0L0G0_AES
+	bool "128-bit AES"
+	default n
+	depends on STM32F0L0G0_HAVE_AES
+	select CRYPTO_AES192_DISABLE if CRYPTO_ALGTEST
+	select CRYPTO_AES256_DISABLE if CRYPTO_ALGTEST
+
+config STM32F0L0G0_VREFINT
+	bool "Enable VREFINT"
+	default n
+	depends on STM32F0L0G0_HAVE_VREFINT
+
+config STM32F0L0G0_CEC
+	bool "CEC"
+	default n
+	depends on STM32F0L0G0_HAVE_CEC
+
+config STM32F0L0G0_CRC
+	bool "CRC"
+	default n
+
+config STM32F0L0G0_CRYP
+	bool "CRYP"
+	default n
+	depends on STM32F0L0G0_HAVE_HASH
+
+config STM32F0L0G0_DMA1
+	bool "DMA1"
+	default n
+	select ARCH_DMA
+	select STM32F0L0G0_DMA
+
+config STM32F0L0G0_DMA2
+	bool "DMA2"
+	default n
+	depends on STM32F0L0G0_HAVE_DMA2
+	select ARCH_DMA
+	select STM32F0L0G0_DMA
+
+config STM32F0L0G0_DAC1
+	bool "DAC1"
+	default n
+	depends on STM32F0L0G0_HAVE_DAC1
+	select STM32F0L0G0_DAC
+
+config STM32F0L0G0_FSMC
+	bool "FSMC"
+	default n
+	depends on STM32F0L0G0_HAVE_FSMC
+
+config STM32F0L0G0_HASH
+	bool "HASH"
+	default n
+	depends on STM32F0L0G0_HAVE_HASH
+
+config STM32F0L0G0_I2C1
+	bool "I2C1"
+	default n
+	select STM32F0L0G0_I2C
+
+config STM32F0L0G0_I2C2
+	bool "I2C2"
+	default n
+	depends on STM32F0L0G0_HAVE_I2C2
+	select STM32F0L0G0_I2C
+
+config STM32F0L0G0_I2C3
+	bool "I2C3"
+	default n
+	depends on STM32F0L0G0_HAVE_I2C3
+	select STM32F0L0G0_I2C
+
+config STM32F0L0G0_PWR
+	bool "PWR"
+	default n
+
+config STM32F0L0G0_RNG
+	bool "RNG"
+	default n
+	depends on STM32F0L0G0_HAVE_RNG
+	select ARCH_HAVE_RNG
+
+config STM32F0L0G0_SDIO
+	bool "SDIO"
+	default n
+	depends on STM32F0L0G0_HAVE_SDIO
+	select ARCH_HAVE_SDIO
+	select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
+	select ARCH_HAVE_SDIO_PREFLIGHT
+
+config STM32F0L0G0_SPI1
+	bool "SPI1"
+	default n
+	select SPI
+	select STM32F0L0G0_SPI
+
+config STM32F0L0G0_SPI2
+	bool "SPI2"
+	default n
+	depends on STM32F0L0G0_HAVE_SPI2
+	select SPI
+	select STM32F0L0G0_SPI
+
+config STM32F0L0G0_SPI3
+	bool "SPI3"
+	default n
+	depends on STM32F0L0G0_HAVE_SPI3
+	select SPI
+	select STM32F0L0G0_SPI
+
+config STM32F0L0G0_SPI4
+	bool "SPI4"
+	default n
+	depends on STM32F0L0G0_HAVE_SPI4
+	select SPI
+	select STM32F0L0G0_SPI
+
+config STM32F0L0G0_SPI5
+	bool "SPI5"
+	default n
+	depends on STM32F0L0G0_HAVE_SPI5
+	select SPI
+	select STM32F0L0G0_SPI
+
+config STM32F0L0G0_SPI6
+	bool "SPI6"
+	default n
+	depends on STM32F0L0G0_HAVE_SPI6
+	select SPI
+	select STM32F0L0G0_SPI
+
+config STM32F0L0G0_SYSCFG
+	bool "SYSCFG"
+	default y
+
+config STM32F0L0G0_TIM1
+	bool "TIM1"
+	default n
+	depends on STM32F0L0G0_HAVE_TIM1
+
+config STM32F0L0G0_TIM2
+	bool "TIM2"
+	default n
+
+config STM32F0L0G0_TIM3
+	bool "TIM3"
+	default n
+	depends on STM32F0L0G0_HAVE_TIM3
+
+config STM32F0L0G0_TIM6
+	bool "TIM6"
+	default n
+	depends on STM32F0L0G0_HAVE_TIM6
+
+config STM32F0L0G0_TIM7
+	bool "TIM7"
+	default n
+	depends on STM32F0L0G0_HAVE_TIM7
+
+config STM32F0L0G0_TIM14
+	bool "TIM14"
+	default n
+	depends on STM32F0L0G0_HAVE_TIM14
+
+config STM32F0L0G0_TIM15
+	bool "TIM15"
+	default n
+	depends on STM32F0L0G0_HAVE_TIM15
+
+config STM32F0L0G0_TIM16
+	bool "TIM16"
+	default n
+	depends on STM32F0L0G0_HAVE_TIM16
+
+config STM32F0L0G0_TIM17
+	bool "TIM17"
+	default n
+	depends on STM32F0L0G0_HAVE_TIM17
+
+config STM32F0L0G0_TSC
+	bool "TSC"
+	default n
+	depends on STM32F0L0G0_HAVE_TSC
+
+config STM32F0L0G0_USART1
+	bool "USART1"
+	default n
+	select STM32F0L0G0_USART
+
+config STM32F0L0G0_USART2
+	bool "USART2"
+	default n
+	select STM32F0L0G0_USART
+
+config STM32F0L0G0_USART3
+	bool "USART3"
+	default n
+	depends on STM32F0L0G0_HAVE_USART3
+	select STM32F0L0G0_USART
+
+config STM32F0L0G0_USART4
+	bool "USART4"
+	default n
+	depends on STM32F0L0G0_HAVE_USART4
+	select STM32F0L0G0_USART
+
+config STM32F0L0G0_USART5
+	bool "USART5"
+	default n
+	depends on STM32F0L0G0_HAVE_USART5
+	select STM32F0L0G0_USART
+
+config STM32F0L0G0_USART6
+	bool "USART6"
+	default n
+	depends on STM32F0L0G0_HAVE_USART6
+	select STM32F0L0G0_USART
+
+config STM32F0L0G0_USART7
+	bool "USART7"
+	default n
+	depends on STM32F0L0G0_HAVE_USART7
+	select STM32F0L0G0_USART
+
+config STM32F0L0G0_USART8
+	bool "USART8"
+	default n
+	depends on STM32F0L0G0_HAVE_USART8
+	select STM32F0L0G0_USART
+
+config STM32F0L0G0_USB
+	bool "USB Device"
+	default n
+	depends on STM32F0L0G0_HAVE_USBDEV
+	select USBDEV
+
+config STM32F0L0G0_LCD
+	bool "Segment LCD"
+	default n
+	depends on STM32F0L0G0_HAVE_LCD
+	select USBDEV
+
+config STM32F0L0G0_IWDG
+	bool "IWDG"
+	default n
+	select WATCHDOG
+
+config STM32F0L0G0_WWDG
+	bool "WWDG"
+	default n
+	select WATCHDOG
+
+endmenu
+
+config STM32F0L0G0_COMP
+	bool
+
+config STM32F0L0G0_ADC
+	bool
+
+config STM32F0L0G0_DAC
+	bool
+
+config STM32F0L0G0_DMA
+	bool
+
+config STM32F0L0G0_SPI
+	bool
+
+config STM32F0L0G0_I2C
+	bool
+
+config STM32F0L0G0_CAN
+	bool
+
+config STM32F0L0G0_USART
+	bool
+
+config STM32F0L0G0_SERIALDRIVER
+	bool
+
+config STM32F0L0G0_1WIREDRIVER
+	bool
+
+menu "U[S]ART Configuration"
+	depends on STM32F0L0G0_USART
+
+comment "U[S]ART Device Configuration"
+
+choice
+	prompt "USART1 Driver Configuration"
+	default STM32F0L0G0_USART1_SERIALDRIVER
+	depends on STM32F0L0G0_USART1
+
+config STM32F0L0G0_USART1_SERIALDRIVER
+	bool "Standard serial driver"
+	select USART1_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select STM32F0L0G0_SERIALDRIVER
+
+config STM32F0L0G0_USART1_1WIREDRIVER
+	bool "1-Wire driver"
+	select STM32F0L0G0_1WIREDRIVER
+
+endchoice # USART1 Driver Configuration
+
+if STM32F0L0G0_USART1_SERIALDRIVER
+
+config USART1_RXFIFO_THRES
+	int "USART1 Rx FIFO Threshold"
+	default 3
+	range 0 5
+	depends on STM32F0L0G0_HAVE_IP_USART_V2
+	---help---
+		Select the Rx FIFO threshold:
+
+		  0 -> 1/8 full
+		  1 -> 1/4 full
+		  2 -> 1/2 full
+		  3 -> 3/4 full
+		  4 -> 7/8 full
+		  5 -> Full
+
+		Higher values mean lower interrupt rates and better CPU performance.
+		Lower values may be needed at high BAUD rates to prevent Rx data
+		overrun errors.
+
+config USART1_RS485
+	bool "RS-485 on USART1"
+	default n
+	---help---
+		Enable RS-485 interface on USART1. Your board config will have to
+		provide GPIO_USART1_RS485_DIR pin definition.
+
+config USART1_RS485_DIR_POLARITY
+	int "USART1 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART1_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+endif # STM32F0L0G0_USART1_SERIALDRIVER
+
+choice
+	prompt "USART2 Driver Configuration"
+	default STM32F0L0G0_USART2_SERIALDRIVER
+	depends on STM32F0L0G0_USART2
+
+config STM32F0L0G0_USART2_SERIALDRIVER
+	bool "Standard serial driver"
+	select USART2_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select STM32F0L0G0_SERIALDRIVER
+
+config STM32F0L0G0_USART2_1WIREDRIVER
+	bool "1-Wire driver"
+	select STM32F0L0G0_1WIREDRIVER
+
+endchoice # USART2 Driver Configuration
+
+if STM32F0L0G0_USART2_SERIALDRIVER
+
+config USART2_RXFIFO_THRES
+	int "USART2 Rx FIFO Threshold"
+	default 3
+	range 0 5
+	depends on STM32F0L0G0_HAVE_IP_USART_V2
+	---help---
+		Select the Rx FIFO threshold:
+
+		  0 -> 1/8 full
+		  1 -> 1/4 full
+		  2 -> 1/2 full
+		  3 -> 3/4 full
+		  4 -> 7/8 full
+		  5 -> Full
+
+		Higher values mean lower interrupt rates and better CPU performance.
+		Lower values may be needed at high BAUD rates to prevent Rx data
+		overrun errors.
+
+config USART2_RS485
+	bool "RS-485 on USART2"
+	default n
+	---help---
+		Enable RS-485 interface on USART2. Your board config will have to
+		provide GPIO_USART2_RS485_DIR pin definition.
+
+config USART2_RS485_DIR_POLARITY
+	int "USART2 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART2_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+endif # STM32F0L0G0_USART2_SERIALDRIVER
+
+choice
+	prompt "USART3 Driver Configuration"
+	default STM32F0L0G0_USART3_SERIALDRIVER
+	depends on STM32F0L0G0_USART3
+
+config STM32F0L0G0_USART3_SERIALDRIVER
+	bool "Standard serial driver"
+	select USART3_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select STM32F0L0G0_SERIALDRIVER
+
+config STM32F0L0G0_USART3_1WIREDRIVER
+	bool "1-Wire driver"
+	select STM32F0L0G0_1WIREDRIVER
+
+endchoice # USART3 Driver Configuration
+
+if STM32F0L0G0_USART3_SERIALDRIVER
+
+config USART3_RS485
+	bool "RS-485 on USART3"
+	default n
+	---help---
+		Enable RS-485 interface on USART3. Your board config will have to
+		provide GPIO_USART3_RS485_DIR pin definition.
+
+config USART3_RS485_DIR_POLARITY
+	int "USART3 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART3_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+endif # STM32F0L0G0_USART3_SERIALDRIVER
+
+choice
+	prompt "USART4 Driver Configuration"
+	default STM32F0L0G0_USART4_SERIALDRIVER
+	depends on STM32F0L0G0_USART4
+
+config STM32F0L0G0_USART4_SERIALDRIVER
+	bool "Standard serial driver"
+	select USART4_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select STM32F0L0G0_SERIALDRIVER
+
+config STM32F0L0G0_USART4_1WIREDRIVER
+	bool "1-Wire driver"
+	select STM32F0L0G0_1WIREDRIVER
+
+endchoice # USART4 Driver Configuration
+
+if STM32F0L0G0_USART4_SERIALDRIVER
+
+config USART4_RS485
+	bool "RS-485 on USART4"
+	default n
+	---help---
+		Enable RS-485 interface on USART4. Your board config will have to
+		provide GPIO_USART4_RS485_DIR pin definition.
+
+config USART4_RS485_DIR_POLARITY
+	int "USART4 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART4_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART4. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+endif # STM32F0L0G0_USART4_SERIALDRIVER
+
+choice
+	prompt "USART5 Driver Configuration"
+	default STM32F0L0G0_USART5_SERIALDRIVER
+	depends on STM32F0L0G0_USART5
+
+config STM32F0L0G0_USART5_SERIALDRIVER
+	bool "Standard serial driver"
+	select USART5_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select STM32F0L0G0_SERIALDRIVER
+
+config STM32F0L0G0_USART5_1WIREDRIVER
+	bool "1-Wire driver"
+	select STM32F0L0G0_1WIREDRIVER
+
+endchoice # USART5 Driver Configuration
+
+if STM32F0L0G0_USART5_SERIALDRIVER
+
+config USART5_RS485
+	bool "RS-485 on USART5"
+	default n
+	---help---
+		Enable RS-485 interface on USART5. Your board config will have to
+		provide GPIO_USART5_RS485_DIR pin definition.
+
+config USART5_RS485_DIR_POLARITY
+	int "USART5 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART5_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART5. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+endif # STM32F0L0G0_USART5_SERIALDRIVER
+
+
+choice
+	prompt "USART6 Driver Configuration"
+	default STM32F0L0G0_USART6_SERIALDRIVER
+	depends on STM32F0L0G0_USART6
+
+config STM32F0L0G0_USART6_SERIALDRIVER
+	bool "Standard serial driver"
+	select USART6_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select STM32F0L0G0_SERIALDRIVER
+
+config STM32F0L0G0_USART6_1WIREDRIVER
+	bool "1-Wire driver"
+	select STM32F0L0G0_1WIREDRIVER
+
+endchoice # USART6 Driver Configuration
+
+if STM32F0L0G0_USART6_SERIALDRIVER
+
+config USART6_RS485
+	bool "RS-485 on USART6"
+	default n
+	---help---
+		Enable RS-485 interface on USART6. Your board config will have to
+		provide GPIO_USART6_RS485_DIR pin definition.
+
+config USART6_RS485_DIR_POLARITY
+	int "USART6 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART6_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+endif # STM32F0L0G0_USART6_SERIALDRIVER
+
+choice
+	prompt "USART7 Driver Configuration"
+	default STM32F0L0G0_USART7_SERIALDRIVER
+	depends on STM32F0L0G0_USART7
+
+config STM32F0L0G0_USART7_SERIALDRIVER
+	bool "Standard serial driver"
+	select USART7_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select STM32F0L0G0_SERIALDRIVER
+
+config STM32F0L0G0_USART7_1WIREDRIVER
+	bool "1-Wire driver"
+	select STM32F0L0G0_1WIREDRIVER
+
+endchoice # USART7 Driver Configuration
+
+if STM32F0L0G0_USART7_SERIALDRIVER
+
+config USART7_RS485
+	bool "RS-485 on USART7"
+	default n
+	---help---
+		Enable RS-485 interface on USART7. Your board config will have to
+		provide GPIO_USART7_RS485_DIR pin definition.
+
+config USART7_RS485_DIR_POLARITY
+	int "USART7 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART7_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART7. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+endif # STM32F0L0G0_USART7_SERIALDRIVER
+
+choice
+	prompt "USART8 Driver Configuration"
+	default STM32F0L0G0_USART8_SERIALDRIVER
+	depends on STM32F0L0G0_USART8
+
+config STM32F0L0G0_USART8_SERIALDRIVER
+	bool "Standard serial driver"
+	select USART8_SERIALDRIVER
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select STM32F0L0G0_SERIALDRIVER
+
+config STM32F0L0G0_USART8_1WIREDRIVER
+	bool "1-Wire driver"
+	select STM32F0L0G0_1WIREDRIVER
+
+endchoice # USART8 Driver Configuration
+
+if STM32F0L0G0_USART8_SERIALDRIVER
+
+config USART8_RS485
+	bool "RS-485 on USART8"
+	default n
+	---help---
+		Enable RS-485 interface on USART8. Your board config will have to
+		provide GPIO_USART8_RS485_DIR pin definition.
+
+config USART8_RS485_DIR_POLARITY
+	int "USART8 RS-485 DIR pin polarity"
+	default 1
+	range 0 1
+	depends on USART8_RS485
+	---help---
+		Polarity of DIR pin for RS-485 on USART8. Set to state on DIR pin which
+		enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+endif # STM32F0L0G0_USART8_SERIALDRIVER
+
+menu "Serial Driver Configuration"
+	depends on STM32F0L0G0_SERIALDRIVER
+
+config STM32F0L0G0_SERIAL_DISABLE_REORDERING
+	bool "Disable reordering of ttySx devices."
+	default n
+	---help---
+		NuttX per default reorders the serial ports (/dev/ttySx) so that the
+		console is always on /dev/ttyS0. If more than one UART is in use this
+		can, however, have the side-effect that all port mappings
+		(hardware USART1 -> /dev/ttyS0) change if the console is moved to another
+		UART. This is in particular relevant if a project uses the USB console
+		in some configs and a serial console in other configs, but does not
+		want the side effect of having all serial port names change when just
+		the console is moved from serial to USB.
+
+config STM32F0L0G0_USART_SINGLEWIRE
+	bool "Single Wire Support"
+	default n
+	depends on STM32F0L0G0_USART
+	---help---
+		Enable single wire UART support.  The option enables support for the
+		TIOCSSINGLEWIRE ioctl in the STM32F0 serial driver.
+
+endmenu # Serial Driver Configuration
+
+if PM
+
+config STM32F0L0G0_PM_SERIAL_ACTIVITY
+	int "PM serial activity"
+	default 10
+	---help---
+		PM activity reported to power management logic on every serial
+		interrupt.
+
+endif
+
+endmenu
+
+menu "ADC Configuration"
+	depends on STM32F0L0G0_ADC
+
+config STM32F0L0G0_ADC1_RESOLUTION
+	int "ADC1 resolution"
+	depends on STM32F0L0G0_ADC1
+	default 0
+	range 0 3
+	---help---
+		ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit
+
+config STM32F0L0G0_ADC_NO_STARTUP_CONV
+	bool "Do not start conversion when opening ADC device"
+	default n
+	---help---
+		Do not start conversion when opening ADC device.
+
+config STM32F0L0G0_ADC_NOIRQ
+	bool "Do not use default ADC interrupts"
+	default n
+	---help---
+		Do not use default ADC interrupts handlers.
+
+config STM32F0L0G0_ADC_LL_OPS
+	bool "ADC low-level operations"
+	default n
+	---help---
+		Enable low-level ADC ops.
+
+config STM32F0L0G0_ADC_CHANGE_SAMPLETIME
+	bool "ADC sample time configuration"
+	default n
+	depends on STM32F0L0G0_ADC_LL_OPS
+	---help---
+		Enable ADC sample time configuration (SMPRx registers).
+
+config STM32F0L0G0_ADC1_DMA
+	bool "ADC1 DMA"
+	depends on STM32F0L0G0_ADC1 && STM32F0L0G0_HAVE_ADC1_DMA
+	default n
+	---help---
+		If DMA is selected, then the ADC may be configured to support
+		DMA transfer, which is necessary if multiple channels are read
+		or if very high trigger frequencies are used.
+
+config STM32F0L0G0_ADC1_DMA_CFG
+	int "ADC1 DMA configuration"
+	depends on STM32F0L0G0_ADC1_DMA && !STM32F0L0G0_HAVE_IP_ADC_V1_BASIC
+	range 0 1
+	default 0
+	---help---
+		0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode
+
+endmenu
+
+menu "SPI Configuration"
+	depends on STM32F0L0G0_SPI
+
+config STM32F0L0G0_SPI_INTERRUPTS
+	bool "Interrupt driver SPI"
+	default n
+	---help---
+		Select to enable interrupt driven SPI support. Non-interrupt-driven,
+		poll-waiting is recommended if the interrupt rate would be to high in
+		the interrupt driven case.
+
+config STM32F0L0G0_SPI_DMA
+	bool "SPI DMA"
+	default n
+	---help---
+		Use DMA to improve SPI transfer performance.  Cannot be used with STM32F0L0G0_SPI_INTERRUPT.
+
+config STM32F0L0G0_SPI1_DMA
+	bool "SPI1 DMA"
+	default n
+	depends on STM32F0L0G0_SPI1 && STM32F0L0G0_SPI_DMA
+	---help---
+		Use DMA to improve SPI1 transfer performance.
+
+config STM32F0L0G0_SPI2_DMA
+	bool "SPI2 DMA"
+	default n
+	depends on STM32F0L0G0_SPI2 && STM32F0L0G0_SPI_DMA
+	---help---
+		Use DMA to improve SPI2 transfer performance.
+
+endmenu # SPI Configuration
+
+menu "I2C Configuration"
+	depends on STM32F0L0G0_I2C
+
+config STM32F0L0G0_I2C_DYNTIMEO
+	bool "Use dynamic timeouts"
+	default n
+	depends on STM32F0L0G0_I2C
+
+config STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE
+	int "Timeout Microseconds per Byte"
+	default 500
+	depends on STM32F0L0G0_I2C_DYNTIMEO
+
+config STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP
+	int "Timeout for Start/Stop (Milliseconds)"
+	default 1000
+	depends on STM32F0L0G0_I2C_DYNTIMEO
+
+config STM32F0L0G0_I2CTIMEOSEC
+	int "Timeout seconds"
+	default 0
+	depends on STM32F0L0G0_I2C
+
+config STM32F0L0G0_I2CTIMEOMS
+	int "Timeout Milliseconds"
+	default 500
+	depends on STM32F0L0G0_I2C && !STM32F0L0G0_I2C_DYNTIMEO
+
+config STM32F0L0G0_I2CTIMEOTICKS
+	int "Timeout for Done and Stop (ticks)"
+	default 500
+	depends on STM32F0L0G0_I2C && !STM32F0L0G0_I2C_DYNTIMEO
+
+endmenu #I2C Configuration
diff --git a/arch/arm/src/stm32f0l0/Make.defs b/arch/arm/src/stm32f0l0g0/Make.defs
similarity index 85%
rename from arch/arm/src/stm32f0l0/Make.defs
rename to arch/arm/src/stm32f0l0g0/Make.defs
index e3ef2f8b8f5..7047383c622 100644
--- a/arch/arm/src/stm32f0l0/Make.defs
+++ b/arch/arm/src/stm32f0l0g0/Make.defs
@@ -1,5 +1,5 @@
 ############################################################################
-# arch/arm/src/stm32f0l0/Make.defs
+# arch/arm/src/stm32f0l0g0/Make.defs
 #
 #   Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt 
@@ -50,11 +50,9 @@ CMN_CSRCS += up_hardfault.c up_svcall.c up_vectors.c up_vfork.c
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
@@ -65,10 +63,14 @@ CMN_CSRCS += up_dumpnvic.c
 endif
 
 CHIP_ASRCS  =
-CHIP_CSRCS  = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c # stm32_dma_v1.c
+CHIP_CSRCS  = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c
 CHIP_CSRCS += stm32_lse.c stm32_lowputc.c stm32_serial.c stm32_rcc.c
 
-ifeq ($(CONFIG_STM32F0L0_PWR),y)
+ifeq ($(CONFIG_STM32F0L0G0_DMA),y)
+CHIP_CSRCS += stm32_dma_v1.c
+endif
+
+ifeq ($(CONFIG_STM32F0L0G0_PWR),y)
 CHIP_CSRCS += stm32_pwr.c
 endif
 
@@ -84,7 +86,7 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CHIP_CSRCS += stm32_userspace.c
 endif
 
-ifeq ($(CONFIG_STM32F0L0_GPIOIRQ),y)
+ifeq ($(CONFIG_STM32F0L0G0_GPIOIRQ),y)
 CHIP_CSRCS += stm32_gpioint.c
 endif
 
@@ -92,22 +94,34 @@ ifeq ($(CONFIG_ARCH_IRQPRIO),y)
 CHIP_CSRCS += stm32_irqprio.c
 endif
 
-ifeq ($(CONFIG_STM32F0L0_HAVE_HSI48),y)
+ifeq ($(CONFIG_STM32F0L0G0_HAVE_HSI48),y)
 CHIP_CSRCS += stm32_hsi48.c
 endif
 
-ifeq ($(CONFIG_STM32F0L0_USB),y)
+ifeq ($(CONFIG_STM32F0L0G0_USB),y)
 CHIP_CSRCS += stm32_usbdev.c
 endif
 
-ifeq ($(CONFIG_STM32F0L0_I2C),y)
+ifeq ($(CONFIG_STM32F0L0G0_I2C),y)
 CHIP_CSRCS += stm32_i2c.c
 endif
 
-ifeq ($(CONFIG_STM32F0L0_SPI),y)
+ifeq ($(CONFIG_STM32F0L0G0_SPI),y)
 CHIP_CSRCS += stm32_spi.c
 endif
 
-ifeq ($(CONFIG_PWM),y)
+ifeq ($(CONFIG_STM32F0L0G0_PWM),y)
 CHIP_CSRCS += stm32_pwm.c
 endif
+
+ifeq ($(CONFIG_STM32F0L0G0_ADC),y)
+CHIP_CSRCS += stm32_adc.c
+endif
+
+ifeq ($(CONFIG_STM32F0L0G0_AES),y)
+CHIP_CSRCS += stm32_aes.c
+endif
+
+ifeq ($(CONFIG_STM32F0L0G0_RNG),y)
+CHIP_CSRCS += stm32_rng.c
+endif
diff --git a/arch/arm/src/stm32f0l0/chip.h b/arch/arm/src/stm32f0l0g0/chip.h
similarity index 92%
rename from arch/arm/src/stm32f0l0/chip.h
rename to arch/arm/src/stm32f0l0g0/chip.h
index dae04640ce9..a8382541a77 100644
--- a/arch/arm/src/stm32f0l0/chip.h
+++ b/arch/arm/src/stm32f0l0g0/chip.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/chip.h
+ * arch/arm/src/stm32f0l0g0/chip.h
  *
  *   Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H
 
 /************************************************************************************
  * Included Files
@@ -46,7 +46,7 @@
 
 /* Include the chip capabilities file */
 
-#include 
+#include 
 
 #define ARMV6M_PERIPHERAL_INTERRUPTS 32
 
@@ -56,4 +56,4 @@
 
 #include "hardware/stm32_memorymap.h"
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_adc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h
similarity index 64%
rename from arch/arm/src/stm32f0l0/hardware/stm32_adc.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h
index 75dd3ddcd4a..240fc528ad2 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_adc.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h
@@ -1,5 +1,5 @@
 /********************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_adc.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ********************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_ADC_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_ADC_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H
 
 /********************************************************************************
  * Included Files
@@ -45,10 +45,64 @@
 
 #include "chip.h"
 
+/* STM32 M0 ADC driver:
+ * - no injected channels
+ * - no offset registers
+ * - the F0/L0 family support one sampling time configuration for all channels
+ * - the G0 family support two sampling time configurations
+ */
+
+/* Support for battery voltage */
+
+#if 0
+#  define HAVE_ADC_VBAT
+#else
+#  undef HAVE_ADC_VBAT
+#endif
+
+/* Support for ADC clock prescaler */
+
+#if defined(CONFIG_STM32F0L0G0_STM32L0) || defined(CONFIG_STM32F0L0G0_STM32G0)
+#  define HAVE_ADC_PRE
+#else
+#  undef HAVE_ADC_PRE
+#endif
+
+/* Support for LCD voltage */
+
+#ifdef CONFIG_STM32F0L0G0_HAVE_LCD
+#  define  HAVE_ADC_VLCD
+#else
+#  undef  HAVE_ADC_VLCD
+#endif
+
+/* Supprot for Low frequency mode */
+
+#ifdef CONFIG_STM32F0L0G0_ENERGYLITE
+#  define  HAVE_ADC_LFM
+#else
+#  undef  HAVE_ADC_LFM
+#endif
+
+#undef ADC_HAVE_INJECTED
+
 /********************************************************************************
  * Pre-processor Definitions
  ********************************************************************************/
 
+#define STM32_ADC1_OFFSET            0x0000
+#define STM32_ADC2_OFFSET            0x0100
+#define STM32_ADC3_OFFSET            0x0000
+#define STM32_ADC4_OFFSET            0x0100
+#define STM32_ADCCMN_OFFSET          0x0300
+
+#define STM32_ADC1_BASE              (STM32_ADC1_OFFSET+STM32_ADC12_BASE) /* ADC1 Master ADC */
+#define STM32_ADC2_BASE              (STM32_ADC2_OFFSET+STM32_ADC12_BASE) /* ADC2 Slave ADC */
+#define STM32_ADC3_BASE              (STM32_ADC3_OFFSET+STM32_ADC34_BASE) /* ADC3 Master ADC */
+#define STM32_ADC4_BASE              (STM32_ADC4_OFFSET+STM32_ADC34_BASE) /* ADC4 Slave ADC */
+#define STM32_ADC12CMN_BASE          (STM32_ADCCMN_OFFSET+STM32_ADC12_BASE) /* ADC1, ADC2 common */
+#define STM32_ADC34CMN_BASE          (STM32_ADCCMN_OFFSET+STM32_ADC34_BASE) /* ADC3, ADC4 common */
+
 /* Register Offsets *********************************************************************************/
 
 #define STM32_ADC_ISR_OFFSET        0x0000  /* ADC interrupt and status register */
@@ -60,20 +114,23 @@
 #define STM32_ADC_TR_OFFSET         0x0020  /* ADC watchdog threshold register */
 #define STM32_ADC_CHSELR_OFFSET     0x0028  /* ADC channel selection register */
 #define STM32_ADC_DR_OFFSET         0x0040  /* ADC regular data register */
-#define STM32_ADC_CCR_OFFSET        0x0308  /* ADC common configuration register */
+
+/* Master and Slave ADC Common Registers */
+
+#define STM32_ADC_CCR_OFFSET         0x0008  /* Common control register */
 
 /* Register Addresses *******************************************************************************/
 
-#define STM32_ADC_ISR              (STM32_ADC_BASE + STM32_ADC_ISR_OFFSET)
-#define STM32_ADC_IER              (STM32_ADC_BASE + STM32_ADC_IER_OFFSET)
-#define STM32_ADC_CR               (STM32_ADC_BASE + STM32_ADC_CR_OFFSET)
-#define STM32_ADC_CFGR1            (STM32_ADC_BASE + STM32_ADC_CFGR1_OFFSET)
-#define STM32_ADC_CFGR2            (STM32_ADC_BASE + STM32_ADC_CFGR2_OFFSET)
-#define STM32_ADC_SMPR             (STM32_ADC_BASE + STM32_ADC_SMPR_OFFSET)
-#define STM32_ADC_TR               (STM32_ADC_BASE + STM32_ADC_TR_OFFSET)
-#define STM32_ADC_CHSELR           (STM32_ADC_BASE + STM32_ADC_CHSELR_OFFSET)
-#define STM32_ADC_DR               (STM32_ADC_BASE + STM32_ADC_DR_OFFSET)
-#define STM32_ADC_CCR              (STM32_ADC_BASE + STM32_ADC_CCR_OFFSET)
+#define STM32_ADC1_ISR              (STM32_ADC1_BASE + STM32_ADC_ISR_OFFSET)
+#define STM32_ADC1_IER              (STM32_ADC1_BASE + STM32_ADC_IER_OFFSET)
+#define STM32_ADC1_CR               (STM32_ADC1_BASE + STM32_ADC_CR_OFFSET)
+#define STM32_ADC1_CFGR1            (STM32_ADC1_BASE + STM32_ADC_CFGR1_OFFSET)
+#define STM32_ADC1_CFGR2            (STM32_ADC1_BASE + STM32_ADC_CFGR2_OFFSET)
+#define STM32_ADC1_SMPR             (STM32_ADC1_BASE + STM32_ADC_SMPR_OFFSET)
+#define STM32_ADC1_TR               (STM32_ADC1_BASE + STM32_ADC_TR_OFFSET)
+#define STM32_ADC1_CHSELR           (STM32_ADC1_BASE + STM32_ADC_CHSELR_OFFSET)
+#define STM32_ADC1_DR               (STM32_ADC1_BASE + STM32_ADC_DR_OFFSET)
+#define STM32_ADC1_CCR              (STM32_ADC1_BASE + STM32_ADC_CCR_OFFSET)
 
 /* Register Bitfield Definitions ************************************************/
 
@@ -92,6 +149,7 @@
 #define ADC_CR_ADDIS                (1 << 1)  /* Bit 1: ADC disable command */
 #define ADC_CR_ADSTART              (1 << 2)  /* Bit 2: ADC start of regular conversion */
 #define ADC_CR_ADSTP                (1 << 4)  /* Bit 4: ADC stop of regular conversion command */
+#define ADC_CR_ADVREGEN             (1 << 28) /* Bit 28: ADC Voltage Regulator Enable */
 #define ADC_CR_ADCAL                (1 << 31) /* Bit 31: ADC calibration */
 
 /* ADC configuration register 1 */
@@ -143,16 +201,21 @@
 
 /* ADC sample time register */
 
-#define ADC_SMPR_SMP_SHIFT          (0)       /* Bits 0-2: Sampling time selection */
-#define ADC_SMPR_SMP_MASK           (7 << ADC_SMPR_SMP_SHIFT)
-#define ADC_SMPR_SMP_1p5            (0 << ADC_SMPR_SMP_SHIFT)  /* 000: 1.5 cycles */
-#define ADC_SMPR_SMP_7p5            (1 << ADC_SMPR_SMP_SHIFT)  /* 001: 7.5 cycles */
-#define ADC_SMPR_SMP_13p5           (2 << ADC_SMPR_SMP_SHIFT)  /* 010: 13.5 cycles */
-#define ADC_SMPR_SMP_28p5           (3 << ADC_SMPR_SMP_SHIFT)  /* 011: 28.5 cycles */
-#define ADC_SMPR_SMP_41p5           (4 << ADC_SMPR_SMP_SHIFT)  /* 100: 41.5 cycles */
-#define ADC_SMPR_SMP_55p5           (5 << ADC_SMPR_SMP_SHIFT)  /* 101: 55.5 cycles */
-#define ADC_SMPR_SMP_71p5           (6 << ADC_SMPR_SMP_SHIFT)  /* 110: 71.5 cycles */
-#define ADC_SMPR_SMP_239p5          (7 << ADC_SMPR_SMP_SHIFT)  /* 111: 239.5 cycles */
+#define ADC_SMPR_1p5                (0)       /* 000: 1.5 cycles */
+#define ADC_SMPR_7p5                (1)       /* 001: 7.5 cycles */
+#define ADC_SMPR_13p5               (2)       /* 010: 13.5 cycles */
+#define ADC_SMPR_28p5               (3)       /* 011: 28.5 cycles */
+#define ADC_SMPR_41p5               (4)       /* 100: 41.5 cycles */
+#define ADC_SMPR_55p5               (5)       /* 101: 55.5 cycles */
+#define ADC_SMPR_71p5               (6)       /* 110: 71.5 cycles */
+#define ADC_SMPR_239p5              (7)       /* 111: 239.5 cycles */
+
+#define ADC_SMPR_SMP1_SHIFT         (0)       /* Bits 0-2: Sampling time selection 1 */
+#define ADC_SMPR_SMP1_MASK          (7 << ADC_SMPR_SMP_SHIFT)
+#define ADC_SMPR_SMP2_SHIFT         (4)       /* Bits 4-6: Sampling time selection 2 */
+#define ADC_SMPR_SMP2_MASK          (7 << ADC_SMPR_SMP_SHIFT)
+#define ADC_SMPR_SMPSEL_SHIFT       (8)       /* Bits 8-26: channel-x sampling time selection */
+#define ADC_SMPR_SMPSEL(ch, smp)    (smp << ADC_SMPR_SMPSEL_SHIFT)
 
 /* ADC watchdog threshold register */
 
@@ -173,23 +236,36 @@
 #define ADC_CHSELR_CHSEL7           (1 << 7)    /* Select channel 7 */
 #define ADC_CHSELR_CHSEL8           (1 << 8)    /* Select channel 8 */
 #define ADC_CHSELR_CHSEL9           (1 << 9)    /* Select channel 9 */
-#define ADC_CHSELR_CHSEL10          (1 << 10)    /* Select channel 10 */
-#define ADC_CHSELR_CHSEL11          (1 << 11)    /* Select channel 11 */
-#define ADC_CHSELR_CHSEL12          (1 << 12)    /* Select channel 12 */
-#define ADC_CHSELR_CHSEL13          (1 << 13)    /* Select channel 13 */
-#define ADC_CHSELR_CHSEL14          (1 << 14)    /* Select channel 14 */
-#define ADC_CHSELR_CHSEL15          (1 << 15)    /* Select channel 15 */
-#define ADC_CHSELR_CHSEL16          (1 << 16)    /* Select channel 16 */
-#define ADC_CHSELR_CHSEL17          (1 << 17)    /* Select channel 17 */
-#define ADC_CHSELR_CHSEL18          (1 << 18)    /* Select channel 18 */
+#define ADC_CHSELR_CHSEL10          (1 << 10)   /* Select channel 10 */
+#define ADC_CHSELR_CHSEL11          (1 << 11)   /* Select channel 11 */
+#define ADC_CHSELR_CHSEL12          (1 << 12)   /* Select channel 12 */
+#define ADC_CHSELR_CHSEL13          (1 << 13)   /* Select channel 13 */
+#define ADC_CHSELR_CHSEL14          (1 << 14)   /* Select channel 14 */
+#define ADC_CHSELR_CHSEL15          (1 << 15)   /* Select channel 15 */
+#define ADC_CHSELR_CHSEL16          (1 << 16)   /* Select channel 16 */
+#define ADC_CHSELR_CHSEL17          (1 << 17)   /* Select channel 17 */
+#define ADC_CHSELR_CHSEL18          (1 << 18)   /* Select channel 18 */
+#define ADC_CHSELR_CHSEL(ch)        (1 << ch)
 
 #define ADC_DR_RDATA_SHIFT          (0)
 #define ADC_DR_RDATA_MASK           (0xffff << ADC_DR_RDATA_SHIFT)
 
 /* Common configuration register */
 
+#ifdef HAVE_ADC_VLCD
+#  define ADC_CCR_PRESC_SHIFT       (18)       /* ADC Prescaler */
+#  define ADC_CCR_PRESC_MASK        (0xf << ADC_CCR_PRESC_SHIFT)
+#endif
 #define ADC_CCR_VREFEN              (1 << 22)  /* Bit 22: VREFINT enable */
 #define ADC_CCR_TSEN                (1 << 23)  /* Bit 23: Temperature sensor enable */
-#define ADC_CCR_VBATEN              (1 << 24)  /* Bit 22: VBAT enable */
+#ifdef HAVE_ADC_VBAT
+#  define ADC_CCR_VBATEN            (1 << 24)  /* Bit 24: VBAT enable */
+#endif
+#ifdef HAVE_ADC_VLCD
+#  define ADC_CCR_VLCDEN            (1 << 24)  /* Bit 24: VLCD enable */
+#endif
+#ifdef HAVE_ADC_LFM
+#  define ADC_CCR_LFMEN             (1 << 25)  /* Bit 25: Low Frequency Mode enable */
+#endif
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_ADC_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h
new file mode 100644
index 00000000000..fa60d0bd293
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h
@@ -0,0 +1,114 @@
+/********************************************************************************************
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h
+ *
+ *   Copyright (C) 2015 Haltian Ltd. All rights reserved.
+ *   Author: Juha Niskanen 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H
+
+/********************************************************************************************
+ * Included Files
+ ********************************************************************************************/
+
+#include 
+
+#include "chip.h"
+
+/********************************************************************************************
+ * Pre-processor Definitions
+ ********************************************************************************************/
+
+/* AES register offsets *********************************************************************/
+
+#define STM32_AES_CR_OFFSET                0x0000 /* Control Register */
+#define STM32_AES_SR_OFFSET                0x0004 /* Status Register */
+#define STM32_AES_DINR_OFFSET              0x0008 /* Data Input Register */
+#define STM32_AES_DOUTR_OFFSET             0x000C /* Data Output Register */
+#define STM32_AES_KEYR0_OFFSET             0x0010 /* AES Key Register 0 */
+#define STM32_AES_KEYR1_OFFSET             0x0014 /* AES Key Register 1 */
+#define STM32_AES_KEYR2_OFFSET             0x0018 /* AES Key Register 2 */
+#define STM32_AES_KEYR3_OFFSET             0x001C /* AES Key Register 3 */
+#define STM32_AES_IVR0_OFFSET              0x0020 /* AES Initialization Vector Register 0 */
+#define STM32_AES_IVR1_OFFSET              0x0024 /* AES Initialization Vector Register 1 */
+#define STM32_AES_IVR2_OFFSET              0x0028 /* AES Initialization Vector Register 2 */
+#define STM32_AES_IVR3_OFFSET              0x002C /* AES Initialization Vector Register 3 */
+
+/* AES register addresses *******************************************************************/
+
+#define STM32_AES_CR                       (STM32_AES_BASE + STM32_AES_CR_OFFSET)
+#define STM32_AES_SR                       (STM32_AES_BASE + STM32_AES_SR_OFFSET)
+#define STM32_AES_DINR                     (STM32_AES_BASE + STM32_AES_DINR_OFFSET)
+#define STM32_AES_DOUTR                    (STM32_AES_BASE + STM32_AES_DOUTR_OFFSET)
+#define STM32_AES_KEYR0                    (STM32_AES_BASE + STM32_AES_KEYR0_OFFSET)
+#define STM32_AES_KEYR1                    (STM32_AES_BASE + STM32_AES_KEYR1_OFFSET)
+#define STM32_AES_KEYR2                    (STM32_AES_BASE + STM32_AES_KEYR2_OFFSET)
+#define STM32_AES_KEYR3                    (STM32_AES_BASE + STM32_AES_KEYR3_OFFSET)
+#define STM32_AES_IVR0                     (STM32_AES_BASE + STM32_AES_IVR0_OFFSET)
+#define STM32_AES_IVR1                     (STM32_AES_BASE + STM32_AES_IVR1_OFFSET)
+#define STM32_AES_IVR2                     (STM32_AES_BASE + STM32_AES_IVR2_OFFSET)
+#define STM32_AES_IVR3                     (STM32_AES_BASE + STM32_AES_IVR3_OFFSET)
+
+/* AES register bit definitions *************************************************************/
+
+/* AES_CR register */
+
+#define AES_CR_EN                          (1 << 0)       /* AES Enable */
+#define AES_CR_DATATYPE                    (1 << 1)       /* Data type selection */
+#  define AES_CR_DATATYPE_LE               (0x0 << 1)
+#  define AES_CR_DATATYPE_BE               (0x2 << 1)
+
+#define AES_CR_MODE                        (1 << 3)       /* AES Mode of operation */
+#  define AES_CR_MODE_ENCRYPT              (0x0 << 3)
+#  define AES_CR_MODE_KEYDERIV             (0x1 << 3)
+#  define AES_CR_MODE_DECRYPT              (0x2 << 3)
+#  define AES_CR_MODE_DECRYPT_KEYDERIV     (0x3 << 3)
+
+#define AES_CR_CHMOD                       (1 << 5)       /* AES Chaining Mode */
+#  define AES_CR_CHMOD_ECB                 (0x0 << 5)
+#  define AES_CR_CHMOD_CBC                 (0x1 << 5)
+#  define AES_CR_CHMOD_CTR                 (0x2 << 5)
+
+#define AES_CR_CCFC                        (1 << 7)       /* Computation Complete Flag Clear */
+#define AES_CR_ERRC                        (1 << 8)       /* Error Clear */
+#define AES_CR_CCIE                        (1 << 9)       /* Computation Complete Interrupt Enable */
+#define AES_CR_ERRIE                       (1 << 10)      /* Error Interrupt Enable */
+#define AES_CR_DMAINEN                     (1 << 11)      /* DMA Enable Input */
+#define AES_CR_DMAOUTEN                    (1 << 12)      /* DMA Enable Output */
+
+/* AES_SR register */
+
+#define AES_SR_CCF                         (1 << 0)       /* Computation Complete Flag */
+#define AES_SR_RDERR                       (1 << 1)       /* Read Error Flag */
+#define AES_SR_WRERR                       (1 << 2)       /* Write Error Flag */
+
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_can.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h
similarity index 99%
rename from arch/arm/src/stm32f0l0/hardware/stm32_can.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_can.h
index a3dc2ba6e04..92cec1782fd 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_can.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_can.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_can.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CAN_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CAN_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H
 
 /************************************************************************************
  * Included Files
@@ -466,4 +466,4 @@
 #define CAN_FA1R_FACT_SHIFT       (0)      /* Bits 13:0: Filter Active */
 #define CAN_FA1R_FACT_MASK        (0x3fff << CAN_FA1R_FACT_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CAN_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_comp.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h
similarity index 97%
rename from arch/arm/src/stm32f0l0/hardware/stm32_comp.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h
index c8dca2f4e82..380f0cde55b 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_comp.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_comp.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_COMP_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_COMP_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H
 
 /************************************************************************************
  * Included Files
@@ -135,4 +135,4 @@
 #define COMP_CSR_COMP2OUT             (1 << 14)   /* Bit 14: Comparator 1 output */
 #define COMP_CSR_COMP2LOCK            (1 << 15)   /* Bit 15: Comparator 1 lock */
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_COMP_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_crc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h
similarity index 95%
rename from arch/arm/src/stm32f0l0/hardware/stm32_crc.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h
index d368142eb9c..4e360dc707f 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_crc.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_crc.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRC_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRC_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H
 
 /************************************************************************************
  * Included Files
@@ -87,4 +87,4 @@
 #  define CRC_CR_REVIN_WORD     (3 << CRC_CR_REVIN_SHIFT) /* 11: reversal done by word */
 #define CRC_CR_REVOUT           (1 << 7)  /* This bit controls the reversal of the bit order of the output data */
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRC_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_crs.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h
similarity index 92%
rename from arch/arm/src/stm32f0l0/hardware/stm32_crs.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h
index b0c79e1b80f..1699d6b5cb9 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_crs.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_crs.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRS_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRS_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -78,19 +78,19 @@
 #define CRS_CFGR_SYNCDIV_SHIFT     24        /* Bits 24-26: SYNC divider */
 #define CRS_CFGR_SYNCDIV_MASK      (7 << CRS_CFGR_SYNCDIV_SHIFT)
 #  define CRS_CFGR_SYNCDIV_d1      (0 << CRS_CFGR_SYNCDIV_SHIFT) /* Not divided */
-#  define CRS_CFGR_SYNCDIV_d2      (1 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 2) */
-#  define CRS_CFGR_SYNCDIV_d4      (2 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 4) */
-#  define CRS_CFGR_SYNCDIV_d8      (3 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 8) */
-#  define CRS_CFGR_SYNCDIV_d16     (4 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 16) */
-#  define CRS_CFGR_SYNCDIV_d32     (5 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 32) */
-#  define CRS_CFGR_SYNCDIV_d64     (6 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 64) */
-#  define CRS_CFGR_SYNCDIV_d128    (6 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 128) */
+#  define CRS_CFGR_SYNCDIV_d2      (1 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 2 */
+#  define CRS_CFGR_SYNCDIV_d4      (2 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 4 */
+#  define CRS_CFGR_SYNCDIV_d8      (3 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 8 */
+#  define CRS_CFGR_SYNCDIV_d16     (4 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 16 */
+#  define CRS_CFGR_SYNCDIV_d32     (5 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 32 */
+#  define CRS_CFGR_SYNCDIV_d64     (6 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 64 */
+#  define CRS_CFGR_SYNCDIV_d128    (7 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 128 */
 #define CRS_CFGR_SYNCSRC_SHIFT     28        /* Bits 28-29: SYNC signal source selection */
 #define CRS_CFGR_SYNCSRC_MASK      (3 << CRS_CFGR_SYNCSRC_SHIFT)
 #  define CRS_CFGR_SYNCSRC_GPIO    (0 << CRS_CFGR_SYNCSRC_SHIFT) /* GPIO as SYNC signal source */
 #  define CRS_CFGR_SYNCSRC_LSE     (1 << CRS_CFGR_SYNCSRC_SHIFT) /* LSE as SYNC signal source */
 #  define CRS_CFGR_SYNCSRC_USBSOF  (2 << CRS_CFGR_SYNCSRC_SHIFT) /* USB SOF as SYNC signal source */
-#define CRS_CFGR_SYNCPOL           (1 << 30) /* SYNC polarity selection */
+#define CRS_CFGR_SYNCPOL           (1 << 31) /* SYNC polarity selection */
 
 /* CRS interrupt and status register */
 
@@ -112,4 +112,4 @@
 #define CRS_ICR_ERRC               (1 << 2)  /* Bit 2: Error clear flag */
 #define CRS_ICR_ESYNCC             (1 << 3)  /* Bit 3: Expected SYNC clear flag */
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_CRS_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_dac.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h
similarity index 98%
rename from arch/arm/src/stm32f0l0/hardware/stm32_dac.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h
index a61111ec0e5..74e1bbfc728 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_dac.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_dac.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DAC_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DAC_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H
 
 /************************************************************************************
  * Included Files
@@ -215,4 +215,4 @@
 #define DAC_SR_DMAUDR1            (1 << 13)  /* Bit 13: DAC channel 1 DMA underrun flag */
 #define DAC_SR_DMAUDR2            (1 << 29)  /* Bit 29: DAC channel 2 DMA underrun flag */
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_DAC_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h
similarity index 99%
rename from arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h
index e31964ab805..46a921637d1 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_dma_v1.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_HEARDWARE_STM32_DMA_V1_H
-#define __ARCH_ARM_SRC_STM32F0L0_HEARDWARE_STM32_DMA_V1_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -550,4 +550,4 @@
 #  error "Unknown DMA channel assignments"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_HEARDWARE_STM32_DMA_V1_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h
new file mode 100644
index 00000000000..1294463efec
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h
@@ -0,0 +1,162 @@
+/************************************************************************************
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+#define DMAMUX1 0
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_DMAMUX_CXCR_OFFSET(x)  (0x0000+0x0004*(x)) /* DMAMUX12 request line multiplexer channel x configuration register */
+#define STM32_DMAMUX_C0CR_OFFSET     STM32_DMAMUX_CXCR_OFFSET(0)
+#define STM32_DMAMUX_C1CR_OFFSET     STM32_DMAMUX_CXCR_OFFSET(1)
+#define STM32_DMAMUX_C2CR_OFFSET     STM32_DMAMUX_CXCR_OFFSET(2)
+#define STM32_DMAMUX_C3CR_OFFSET     STM32_DMAMUX_CXCR_OFFSET(3)
+#define STM32_DMAMUX_C4CR_OFFSET     STM32_DMAMUX_CXCR_OFFSET(4)
+#define STM32_DMAMUX_C5CR_OFFSET     STM32_DMAMUX_CXCR_OFFSET(5)
+#define STM32_DMAMUX_C6CR_OFFSET     STM32_DMAMUX_CXCR_OFFSET(6)
+                                            /* 0x01C-0x07C: Reserved */
+#define STM32_DMAMUX_CSR_OFFSET      0x0080 /* DMAMUX12 request line multiplexer interrupt channel status register */
+#define STM32_DMAMUX_CFR_OFFSET      0x0084 /* DMAMUX12 request line multiplexer interrupt clear flag register */
+                                            /* 0x088-0x0FC: Reserved */
+#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX12 request generator channel x configuration register */
+#define STM32_DMAMUX_RG0CR_OFFSET    STM32_DMAMUX_RGXCR_OFFSET(0)
+#define STM32_DMAMUX_RG1CR_OFFSET    STM32_DMAMUX_RGXCR_OFFSET(1)
+#define STM32_DMAMUX_RG2CR_OFFSET    STM32_DMAMUX_RGXCR_OFFSET(2)
+#define STM32_DMAMUX_RG3CR_OFFSET    STM32_DMAMUX_RGXCR_OFFSET(3)
+#define STM32_DMAMUX_RGSR_OFFSET     0x0140 /* DMAMUX12 request generator interrupt status register */
+#define STM32_DMAMUX_RGCFR_OFFSET    0x0144 /* DMAMUX12 request generator interrupt clear flag register */
+                                            /* 0x148-0x3FC: Reserved */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_DMAMUX1_CXCR(x)  (STM32_DMAMUX1_BASE+STM32_DMAMUX_CXCR_OFFSET(x))
+#define STM32_DMAMUX1_C0CR     (STM32_DMAMUX1_BASE+STM32_DMAMUX_C0CR_OFFSET)
+#define STM32_DMAMUX1_C1CR     (STM32_DMAMUX1_BASE+STM32_DMAMUX_C1CR_OFFSET)
+#define STM32_DMAMUX1_C2CR     (STM32_DMAMUX1_BASE+STM32_DMAMUX_C2CR_OFFSET)
+#define STM32_DMAMUX1_C3CR     (STM32_DMAMUX1_BASE+STM32_DMAMUX_C3CR_OFFSET)
+#define STM32_DMAMUX1_C4CR     (STM32_DMAMUX1_BASE+STM32_DMAMUX_C4CR_OFFSET)
+#define STM32_DMAMUX1_C5CR     (STM32_DMAMUX1_BASE+STM32_DMAMUX_C5CR_OFFSET)
+#define STM32_DMAMUX1_C6CR     (STM32_DMAMUX1_BASE+STM32_DMAMUX_C6CR_OFFSET)
+
+#define STM32_DMAMUX1_CSR      (STM32_DMAMUX1_BASE+STM32_DMAMUX_CSR_OFFSET)
+#define STM32_DMAMUX1_CFR      (STM32_DMAMUX1_BASE+STM32_DMAMUX_CFR_OFFSET)
+
+#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGXCR_OFFSET(x))
+#define STM32_DMAMUX1_RG0CR    (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG0CR_OFFSET)
+#define STM32_DMAMUX1_RG1CR    (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG1CR_OFFSET)
+#define STM32_DMAMUX1_RG2CR    (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG2CR_OFFSET)
+#define STM32_DMAMUX1_RG3CR    (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG3CR_OFFSET)
+
+#define STM32_DMAMUX1_RGSR     (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGSR_OFFSET)
+#define STM32_DMAMUX1_RGCFR    (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGCFR_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* DMAMUX12 request line multiplexer channel x configuration register */
+
+#define DMAMUX_CCR_DMAREQID_SHIFT (0)  /* Bits 0-6: DMA request identification */
+#define DMAMUX_CCR_DMAREQID_MASK  (0x7f << DMAMUX_CCR_DMAREQID_SHIFT)
+#define DMAMUX_CCR_SOIE           (8)  /* Bit 8: Synchronization overrun interrupt enable */
+#define DMAMUX_CCR_EGE            (9)  /* Bit 9: Event generation enable */
+#define DMAMUX_CCR_SE             (16) /* Bit 16: Synchronization enable */
+#define DMAMUX_CCR_SPOL_SHIFT     (17) /* Bits 17-18: Synchronization polarity */
+#define DMAMUX_CCR_SPOL_MASK      (3 << DMAMUX_CCR_SPOL_SHIFT)
+#define DMAMUX_CCR_NBREQ_SHIFT    (19) /* Bits 19-23: Number of DMA request - 1 to forward */
+#define DMAMUX_CCR_NBREQ_MASK     (0x1f << DMAMUX_CCR_NBREQ_SHIFT)
+#define DMAMUX_CCR_SYNCID_SHIFT   (24) /* Bits 24-26: Synchronization identification */
+#define DMAMUX_CCR_SYNCID_MASK    (7 << DMAMUX_CCR_SYNCID_SHIFT)
+
+/* DMAMUX12 request line multiplexer interrupt channel status register */
+
+#define DMAMUX1_CSR_SOF(x)         (1 << x) /* Synchronization overrun event flag */
+
+/* DMAMUX12 request line multiplexer interrupt clear flag register */
+
+#define DMAMUX1_CFR_SOF(x)         (1 << x) /* Clear synchronization overrun event flag */
+
+/* DMAMUX12 request generator channel x configuration register */
+
+#define DMAMUX_RGCR_SIGID_SHIFT    (0)  /* Bits 0-4: Signal identifiaction */
+                                        /* WARNING: different length for DMAMUX1 and DMAMUX2 !*/
+#define DMAMUX_RGCR_SIGID_MASK     (0x1f << DMAMUX_RGCR_SIGID_SHIFT)
+#define DMAMUX_RGCR_OIE            (8)  /* Bit 8: Trigger overrun interrupt enable */
+#define DMAMUX_RGCR_GE             (16) /* Bit 16: DMA request generator channel X enable*/
+#define DMAMUX_RGCR_GPOL_SHIFT     (17) /* Bits 17-18: DMA request generator trigger polarity */
+#define DMAMUX_RGCR_GPOL_MASK      (7 << DMAMUX_RGCR_GPOL_SHIFT)
+#define DMAMUX_RGCR_GNBREQ_SHIFT   (17) /* Bits 19-23: Number of DMA requests to be generated -1 */
+#define DMAMUX_RGCR_GNBREQL_MASK   (7 << DMAMUX_RGCR_GNBREQ_SHIFT)
+
+/* DMAMUX12 request generator interrupt status register */
+
+#define DMAMUX1_RGSR_SOF(x)        (1 << x) /* Trigger overrun event flag */
+
+/* DMAMUX12 request generator interrupt clear flag register */
+
+#define DMAMUX1_RGCFR_SOF(x)       (1 << x) /* Clear trigger overrun event flag */
+
+/* DMA channel mapping
+ *
+ * XXXXX.DDD.CCCCCCCC
+ * C - DMAMUX request
+ * D - DMA controller
+ * X - free bits
+ */
+
+#define DMAMAP_MAP(d,c)           ((d) << 8 | c)
+#define DMAMAP_CONTROLLER(m)      ((m) >> 8 & 0x07)
+#define DMAMAP_REQUEST(m)         ((m) >> 0 & 0xff)
+
+/* Import DMAMUX map */
+
+#if defined(CONFIG_STM32F0L0G0_STM32G0)
+#  include "chip/stm32g0_dmamux.h"
+#else
+#  error "Unsupported STM32 M0 sub family"
+#endif
+
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_exti.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h
similarity index 86%
rename from arch/arm/src/stm32f0l0/hardware/stm32_exti.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h
index 924aca2ccd2..2baf8cec348 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_exti.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_exti.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h
  *
  *   Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_EXTI_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_EXTI_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H
 
 /************************************************************************************
  * Included Files
@@ -48,8 +48,10 @@
 #  include "hardware/stm32f0_exti.h"
 #elif defined(CONFIG_ARCH_CHIP_STM32L0)
 #  include "hardware/stm32l0_exti.h"
+#elif defined(CONFIG_ARCH_CHIP_STM32G0)
+#  include "hardware/stm32g0_exti.h"
 #else
-#  error "Unrecognized STM32F0/L0 EXTI"
+#  error "Unrecognized STM32 M0 EXTI"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_EXTI_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_flash.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h
similarity index 86%
rename from arch/arm/src/stm32f0l0/hardware/stm32_flash.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h
index a017ab0089d..652308369a2 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_flash.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_flash.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h
  *
  *   Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_FLASH_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_FLASH_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H
 
 /************************************************************************************
  * Included Files
@@ -47,8 +47,10 @@
 #  include "hardware/stm32f0_flash.h"
 #elif defined(CONFIG_ARCH_CHIP_STM32L0)
 #  include "hardware/stm32l0_flash.h"
+#elif defined(CONFIG_ARCH_CHIP_STM32G0)
+#  include "hardware/stm32g0_flash.h"
 #else
-#  error "Unsupported STM32 FLASH"
+#  error "Unsupported STM32 M0 FLASH"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_FLASH_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_gpio.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h
similarity index 93%
rename from arch/arm/src/stm32f0l0/hardware/stm32l0_gpio.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h
index 371e0cb0623..a5906407e45 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32l0_gpio.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h
@@ -1,9 +1,9 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32l0_gpio.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
- *   Author: Mateusz Szafoni 
-
+ *   Author: Gregory Nutt 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -33,15 +33,22 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_GPIO_H
-#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_GPIO_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H
 
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
 
-#define STM32_GPIO_VERY_LOW_SPEED  1      /* Have very low speed operation (400KHz) */
-#undef STM32_HAVE_PORTF                   /* If STM32_NPORTS > 5, then have GPIOH */
+#if defined(CONFIG_ARCH_CHIP_STM32F0)
+#  undef STM32_GPIO_VERY_LOW_SPEED          /* No very low speed operation */
+#elif defined(CONFIG_ARCH_CHIP_STM32L0)
+#  define STM32_GPIO_VERY_LOW_SPEED  1      /* Have very low speed operation (400KHz) */
+#elif defined(CONFIG_ARCH_CHIP_STM32G0)
+#  define STM32_GPIO_VERY_LOW_SPEED  1      /* Have very low speed operation */
+#else
+#  error "Unsupported STM32 M0 family"
+#endif
 
 /* Register Offsets *****************************************************************/
 
@@ -215,10 +222,16 @@
 
 /* GPIO port output speed register */
 
-#define GPIO_OSPEED_400KHz         (0) /* 400 kHz Very low speed */
-#define GPIO_OSPEED_2MHz           (1) /* 2 MHz Low speed */
-#define GPIO_OSPEED_10MHz          (2) /* 10 MHz Medium speed */
-#define GPIO_OSPEED_40MHz          (3) /* 40 MHz High speed */
+#if defined(STM32_GPIO_VERY_LOW_SPEED)
+#  define GPIO_OSPEED_VERYLOW        (0) /* Very low speed */
+#  define GPIO_OSPEED_LOW            (1) /* Low speed */
+#  define GPIO_OSPEED_MEDIUM         (2) /* Medium speed */
+#  define GPIO_OSPEED_HIGH           (3) /* High speed */
+#else
+#  define GPIO_OSPEED_LOW            (0) /* Low speed */
+#  define GPIO_OSPEED_MEDIUM         (1) /* Medium speed */
+#  define GPIO_OSPEED_HIGH           (3) /* High speed */
+#endif
 
 #define GPIO_OSPEED_SHIFT(n)       ((n) << 1)
 #define GPIO_OSPEED_MASK(n)        (3 << GPIO_OSPEED_SHIFT(n))
@@ -342,4 +355,4 @@
 
 #define GPIO_BRR(n)                (1 << (n))
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_GPIO_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_i2c.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h
similarity index 98%
rename from arch/arm/src/stm32f0l0/hardware/stm32_i2c.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h
index 3ad47e6c583..1f0bf66e273 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_i2c.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_i2c.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_I2C_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_I2C_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -235,4 +235,4 @@
 
 #define I2C_TXDR_MASK             (0xff)
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_I2C_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h
similarity index 81%
rename from arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h
index f44c5b222c5..ca15936ce27 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_memorymap.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h
  *
  *   Copyright (C) 2017, 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -44,13 +44,15 @@
 #include 
 #include "chip.h"
 
-#if defined(CONFIG_STM32F0L0_STM32F05X) || defined(CONFIG_STM32F0L0_STM32F07X) || \
-    defined(CONFIG_STM32F0L0_STM32F09X)
+#if defined(CONFIG_STM32F0L0G0_STM32F05X) || defined(CONFIG_STM32F0L0G0_STM32F07X) || \
+    defined(CONFIG_STM32F0L0G0_STM32F09X)
 #  include "hardware/stm32f05xf07xf09x_memorymap.h"
 #elif defined(CONFIG_ARCH_CHIP_STM32L0)
 #  include "hardware/stm32l0_memorymap.h"
+#elif defined(CONFIG_ARCH_CHIP_STM32G0)
+#  include "hardware/stm32g0_memorymap.h"
 #else
-#  error "Unsupported STM32F0/L0 memory map"
+#  error "Unsupported STM32 M0 memory map"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h
similarity index 82%
rename from arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h
index ea10b8f8c33..63270d7cbbe 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_pinmap.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H
-#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -43,16 +43,18 @@
 #include 
 #include "chip.h"
 
-#if defined(CONFIG_STM32F0L0_STM32F05X)
+#if defined(CONFIG_STM32F0L0G0_STM32F05X)
 #  include "hardware/stm32f05x_pinmap.h"
-#elif defined(CONFIG_STM32F0L0_STM32F07X)
+#elif defined(CONFIG_STM32F0L0G0_STM32F07X)
 #  include "hardware/stm32f07x_pinmap.h"
-#elif defined(CONFIG_STM32F0L0_STM32F09X)
+#elif defined(CONFIG_STM32F0L0G0_STM32F09X)
 #  include "hardware/stm32f09x_pinmap.h"
 #elif defined(CONFIG_ARCH_CHIP_STM32L0)
 #  include "hardware/stm32l0_pinmap.h"
+#elif defined(CONFIG_ARCH_CHIP_STM32G0)
+#  include "hardware/stm32g0_pinmap.h"
 #else
-#  error "Unsupported STM32F0/L0 pin map"
+#  error "Unsupported STM32 M0 pin map"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_pwr.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h
similarity index 87%
rename from arch/arm/src/stm32f0l0/hardware/stm32_pwr.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h
index 1ba0decf1d6..3cd05ce0579 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_pwr.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_pwr.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h
  *
  *   Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H
-#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H
 
 /************************************************************************************
  * Included Files
@@ -48,9 +48,11 @@
 #  include "hardware/stm32f0_pwr.h"
 #elif defined(CONFIG_ARCH_CHIP_STM32L0)
 #  include "hardware/stm32l0_pwr.h"
+#elif defined(CONFIG_ARCH_CHIP_STM32G0)
+#  include "hardware/stm32g0_pwr.h"
 #else
-#  error "Unsupported STM32F0/L0 PWR"
+#  error "Unsupported STM32 M0 PWR"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32_PWR_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H */
 
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_rcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h
similarity index 87%
rename from arch/arm/src/stm32f0l0/hardware/stm32_rcc.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h
index 6cabfcf8e51..df37deec4d6 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_rcc.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_rcc.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h
  *
  *   Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RCC_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H
 
 /************************************************************************************
  * Included Files
@@ -48,8 +48,10 @@
 #  include "hardware/stm32f0_rcc.h"
 #elif defined(CONFIG_ARCH_CHIP_STM32L0)
 #  include "hardware/stm32l0_rcc.h"
+#elif defined(CONFIG_ARCH_CHIP_STM32G0)
+#  include "hardware/stm32g0_rcc.h"
 #else
-#  error "Unsupported STM32 RCC"
+#  error "Unsupported STM32 M0 RCC"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h
new file mode 100644
index 00000000000..c2caa80bf4a
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h
@@ -0,0 +1,78 @@
+/************************************************************************************
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h
+ *
+ *   Copyright (C) 2012 Max Holtzberg. All rights reserved.
+ *   Author: Max Holtzberg 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_RNG_CR_OFFSET       0x0000  /* RNG Control Register */
+#define STM32_RNG_SR_OFFSET       0x0004  /* RNG Status Register */
+#define STM32_RNG_DR_OFFSET       0x0008  /* RNG Data Register */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_RNG_CR              (STM32_RNG_BASE+STM32_RNG_CR_OFFSET)
+#define STM32_RNG_SR              (STM32_RNG_BASE+STM32_RNG_SR_OFFSET)
+#define STM32_RNG_DR              (STM32_RNG_BASE+STM32_RNG_DR_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* RNG Control Register */
+
+#define RNG_CR_RNGEN              (1 << 2)  /* Bit 2: RNG enable */
+#define RNG_CR_IE                 (1 << 3)  /* Bit 3: Interrupt enable */
+#define RNG_CR_CE                 (1 << 5)  /* Bit 5: Clock error detection */
+
+/* RNG Status Register */
+
+#define RNG_SR_DRDY               (1 << 0) /* Bit 0: Data ready */
+#define RNG_SR_CECS               (1 << 1) /* Bit 1: Clock error current status */
+#define RNG_SR_SECS               (1 << 2) /* Bit 2: Seed error current status */
+#define RNG_SR_CEIS               (1 << 5) /* Bit 5: Clock error interrupt status */
+#define RNG_SR_SEIS               (1 << 6) /* Bit 6: Seed error interrupt status */
+
+#endif	/* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h
similarity index 98%
rename from arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h
index d40da9470fb..014da6be5e5 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_rtcc.h.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RTCC_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RTCC_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -321,4 +321,4 @@
 #define RTC_ALRMSSR_MASKSS_SHIFT  (24)  /* Bits 24-27:  Mask the most-significant bits starting at this bit */
 #define RTC_ALRMSSR_MASKSS_MASK   (0xf << RTC_ALRMSSR_MASKSS_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_RTCC_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_spi.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h
similarity index 98%
rename from arch/arm/src/stm32f0l0/hardware/stm32_spi.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h
index 7d8efa1e03d..3328bd6e9de 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_spi.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_spi.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SPI_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SPI_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H
 
 /************************************************************************************
  * Included Files
@@ -45,9 +45,9 @@
 
 /* Select STM32 SPI IP core */
 
-#if defined(CONFIG_STM32F0L0_STM32F0)
+#if defined(CONFIG_STM32F0L0G0_STM32F0)
 #  define HAVE_IP_SPI_V2
-#elif defined(CONFIG_STM32F0L0_STM32L0)
+#elif defined(CONFIG_STM32F0L0G0_STM32L0)
 #  define HAVE_IP_SPI_V1
 #else
 #  error Unsupported family
@@ -269,4 +269,4 @@
 #define SPI_I2SPR_ODD             (1 << 8)  /* Bit 8: Odd factor for the prescaler */
 #define SPI_I2SPR_MCKOE           (1 << 9)  /* Bit 9: Master clock output enable */
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SPI_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h
similarity index 86%
rename from arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h
index a048caadf50..8fded4c1951 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_syscfg.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h
  *
  *   Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -48,8 +48,10 @@
 #  include "hardware/stm32f0_syscfg.h"
 #elif defined(CONFIG_ARCH_CHIP_STM32L0)
 #  include "hardware/stm32l0_syscfg.h"
+#elif defined(CONFIG_ARCH_CHIP_STM32G0)
+#  include "hardware/stm32g0_syscfg.h"
 #else
-#  error "Unsupported STM32F0/L0 SYSCFG"
+#  error "Unsupported STM32 M0 SYSCFG"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_tim.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h
similarity index 91%
rename from arch/arm/src/stm32f0l0/hardware/stm32_tim.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h
index 793e5fb68da..11e684630af 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_tim.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_tim.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_TIM_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_TIM_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -49,4 +49,4 @@
 
 /* Register Bitfield Definitions ********************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_TIM_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_uart.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h
similarity index 82%
rename from arch/arm/src/stm32f0l0/hardware/stm32_uart.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h
index 21545517bd0..390f0adcbe5 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_uart.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_uart.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h
  *
  *   Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_UART_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_UART_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H
 
 /************************************************************************************
  * Included Files
@@ -44,12 +44,12 @@
 #include 
 #include "chip.h"
 
-#if defined(CONFIG_ARCH_CHIP_STM32F0)
-#  include "hardware/stm32f0_uart.h"
-#elif defined(CONFIG_ARCH_CHIP_STM32L0)
-#  include "hardware/stm32l0_uart.h"
+#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1)
+#  include "hardware/stm32_uart_v1.h"
+#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2)
+#  include "hardware/stm32_uart_v2.h"
 #else
-#  error "Unsupported STM32F0/L0 UART"
+#  error "Unsupported STM32 M0 USART"
 #endif
 
-#endif /* __ARCH_ARM_STC_STM32F0L0_CHIP_STM32_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f0_uart.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h
similarity index 98%
rename from arch/arm/src/stm32f0l0/hardware/stm32f0_uart.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h
index 5c71dd0bacc..839a3f1c151 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32f0_uart.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32f0_uart.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h
  *
  *   Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_UART_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_UART_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V1_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V1_H
 
 /************************************************************************************
  * Included Files
@@ -313,4 +313,4 @@
 #define USART_TDR_SHIFT           (0)       /* Bits 8:0: Data value */
 #define USART_TDR_MASK            (0xff << USART_TDR_SHIFT)
 
-#endif /* __ARCH_ARM_STC_STM32F0L0_CHIP_STM32_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_uart.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h
similarity index 54%
rename from arch/arm/src/stm32f0l0/hardware/stm32l0_uart.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h
index 0f6fc436efa..9529afcec7d 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32l0_uart.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h
@@ -1,8 +1,8 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32l0_uart.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
- *   Author: Mateusz Szafoni 
+ *   Authors: Gregory Nutt 
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -33,21 +33,21 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_STC_STM32F0L0_HARDWARE_STM32L0_UART_H
-#define __ARCH_ARM_STC_STM32F0L0_HARDWARE_STM32L0_UART_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V2_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_UART_V2_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-
 #include "chip.h"
 
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
 
+
 /* Register Offsets *****************************************************************/
 
 #define STM32_USART_CR1_OFFSET    0x0000  /* Control register 1 */
@@ -61,88 +61,80 @@
 #define STM32_USART_ICR_OFFSET    0x0020  /* Interrupt flag clear register */
 #define STM32_USART_RDR_OFFSET    0x0024  /* Receive data register */
 #define STM32_USART_TDR_OFFSET    0x0028  /* Transmit data register */
+#define STM32_USART_PRESC_OFFSET  0x002c  /* Prescaler register */
 
 /* Register Addresses ***************************************************************/
 
 #if STM32_NUSART > 0
-#  define STM32_USART1_CR1        (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
-#  define STM32_USART1_CR2        (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
-#  define STM32_USART1_CR3        (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
-#  define STM32_USART1_BRR        (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
-#  define STM32_USART1_GTPR       (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
-#  define STM32_USART1_RTOR       (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET)
-#  define STM32_USART1_RQR        (STM32_USART1_BASE+STM32_USART_RQR_OFFSET)
-#  define STM32_USART1_GTPR       (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
-#  define STM32_USART1_ISR        (STM32_USART1_BASE+STM32_USART_ISR_OFFSET)
-#  define STM32_USART1_ICR        (STM32_USART1_BASE+STM32_USART_ICR_OFFSET)
-#  define STM32_USART1_RDR        (STM32_USART1_BASE+STM32_USART_RDR_OFFSET)
-#  define STM32_USART1_TDR        (STM32_USART1_BASE+STM32_USART_TDR_OFFSET)
+#  define STM32_USART1_CR1        (STM32_USART1_BASE + STM32_USART_CR1_OFFSET)
+#  define STM32_USART1_CR2        (STM32_USART1_BASE + STM32_USART_CR2_OFFSET)
+#  define STM32_USART1_CR3        (STM32_USART1_BASE + STM32_USART_CR3_OFFSET)
+#  define STM32_USART1_BRR        (STM32_USART1_BASE + STM32_USART_BRR_OFFSET)
+#  define STM32_USART1_GTPR       (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET)
+#  define STM32_USART1_RTOR       (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET)
+#  define STM32_USART1_RQR        (STM32_USART1_BASE + STM32_USART_RQR_OFFSET)
+#  define STM32_USART1_GTPR       (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET)
+#  define STM32_USART1_ISR        (STM32_USART1_BASE + STM32_USART_ISR_OFFSET)
+#  define STM32_USART1_ICR        (STM32_USART1_BASE + STM32_USART_ICR_OFFSET)
+#  define STM32_USART1_RDR        (STM32_USART1_BASE + STM32_USART_RDR_OFFSET)
+#  define STM32_USART1_TDR        (STM32_USART1_BASE + STM32_USART_TDR_OFFSET)
+#  define STM32_USART1_PRESC      (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET)
 #endif
 
 #if STM32_NUSART > 1
-#  define STM32_USART2_CR1        (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
-#  define STM32_USART2_CR2        (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
-#  define STM32_USART2_CR3        (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
-#  define STM32_USART2_BRR        (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
-#  define STM32_USART2_GTPR       (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
-#  define STM32_USART2_RTOR       (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET)
-#  define STM32_USART2_RQR        (STM32_USART2_BASE+STM32_USART_RQR_OFFSET)
-#  define STM32_USART2_GTPR       (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
-#  define STM32_USART2_ISR        (STM32_USART2_BASE+STM32_USART_ISR_OFFSET)
-#  define STM32_USART2_ICR        (STM32_USART2_BASE+STM32_USART_ICR_OFFSET)
-#  define STM32_USART2_RDR        (STM32_USART2_BASE+STM32_USART_RDR_OFFSET)
-#  define STM32_USART2_TDR        (STM32_USART2_BASE+STM32_USART_TDR_OFFSET)
+#  define STM32_USART2_CR1        (STM32_USART2_BASE + STM32_USART_CR1_OFFSET)
+#  define STM32_USART2_CR2        (STM32_USART2_BASE + STM32_USART_CR2_OFFSET)
+#  define STM32_USART2_CR3        (STM32_USART2_BASE + STM32_USART_CR3_OFFSET)
+#  define STM32_USART2_BRR        (STM32_USART2_BASE + STM32_USART_BRR_OFFSET)
+#  define STM32_USART2_GTPR       (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET)
+#  define STM32_USART2_RTOR       (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET)
+#  define STM32_USART2_RQR        (STM32_USART2_BASE + STM32_USART_RQR_OFFSET)
+#  define STM32_USART2_GTPR       (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET)
+#  define STM32_USART2_ISR        (STM32_USART2_BASE + STM32_USART_ISR_OFFSET)
+#  define STM32_USART2_ICR        (STM32_USART2_BASE + STM32_USART_ICR_OFFSET)
+#  define STM32_USART2_RDR        (STM32_USART2_BASE + STM32_USART_RDR_OFFSET)
+#  define STM32_USART2_TDR        (STM32_USART2_BASE + STM32_USART_TDR_OFFSET)
+#  define STM32_USART2_PRESC      (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET)
 #endif
 
 #if STM32_NUSART > 2
-#  define STM32_USART3_CR1        (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
-#  define STM32_USART3_CR2        (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
-#  define STM32_USART3_CR3        (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
-#  define STM32_USART3_BRR        (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
-#  define STM32_USART3_GTPR       (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
-#  define STM32_USART3_RTOR       (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET)
-#  define STM32_USART3_RQR        (STM32_USART3_BASE+STM32_USART_RQR_OFFSET)
-#  define STM32_USART3_GTPR       (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
-#  define STM32_USART3_ISR        (STM32_USART3_BASE+STM32_USART_ISR_OFFSET)
-#  define STM32_USART3_ICR        (STM32_USART3_BASE+STM32_USART_ICR_OFFSET)
-#  define STM32_USART3_RDR        (STM32_USART3_BASE+STM32_USART_RDR_OFFSET)
-#  define STM32_USART3_TDR        (STM32_USART3_BASE+STM32_USART_TDR_OFFSET)
+#  define STM32_USART3_CR1        (STM32_USART3_BASE + STM32_USART_CR1_OFFSET)
+#  define STM32_USART3_CR2        (STM32_USART3_BASE + STM32_USART_CR2_OFFSET)
+#  define STM32_USART3_CR3        (STM32_USART3_BASE + STM32_USART_CR3_OFFSET)
+#  define STM32_USART3_BRR        (STM32_USART3_BASE + STM32_USART_BRR_OFFSET)
+#  define STM32_USART3_GTPR       (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET)
+#  define STM32_USART3_RTOR       (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET)
+#  define STM32_USART3_RQR        (STM32_USART3_BASE + STM32_USART_RQR_OFFSET)
+#  define STM32_USART3_GTPR       (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET)
+#  define STM32_USART3_ISR        (STM32_USART3_BASE + STM32_USART_ISR_OFFSET)
+#  define STM32_USART3_ICR        (STM32_USART3_BASE + STM32_USART_ICR_OFFSET)
+#  define STM32_USART3_RDR        (STM32_USART3_BASE + STM32_USART_RDR_OFFSET)
+#  define STM32_USART3_TDR        (STM32_USART3_BASE + STM32_USART_TDR_OFFSET)
+#  define STM32_USART3_PRESC      (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET)
 #endif
 
 #if STM32_NUSART > 3
-#  define STM32_UART4_CR1        (STM32_UART4_BASE+STM32_USART_CR1_OFFSET)
-#  define STM32_UART4_CR2        (STM32_UART4_BASE+STM32_USART_CR2_OFFSET)
-#  define STM32_UART4_CR3        (STM32_UART4_BASE+STM32_USART_CR3_OFFSET)
-#  define STM32_UART4_BRR        (STM32_UART4_BASE+STM32_USART_BRR_OFFSET)
-#  define STM32_UART4_GTPR       (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET)
-#  define STM32_UART4_RTOR       (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET)
-#  define STM32_UART4_RQR        (STM32_UART4_BASE+STM32_USART_RQR_OFFSET)
-#  define STM32_UART4_GTPR       (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET)
-#  define STM32_UART4_ISR        (STM32_UART4_BASE+STM32_USART_ISR_OFFSET)
-#  define STM32_UART4_ICR        (STM32_UART4_BASE+STM32_USART_ICR_OFFSET)
-#  define STM32_UART4_RDR        (STM32_UART4_BASE+STM32_USART_RDR_OFFSET)
-#  define STM32_UART4_TDR        (STM32_UART4_BASE+STM32_USART_TDR_OFFSET)
-#endif
-
-#if STM32_NUSART > 4
-#  define STM32_UART5_CR1        (STM32_UART5_BASE+STM32_USART_CR1_OFFSET)
-#  define STM32_UART5_CR2        (STM32_UART5_BASE+STM32_USART_CR2_OFFSET)
-#  define STM32_UART5_CR3        (STM32_UART5_BASE+STM32_USART_CR3_OFFSET)
-#  define STM32_UART5_BRR        (STM32_UART5_BASE+STM32_USART_BRR_OFFSET)
-#  define STM32_UART5_GTPR       (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET)
-#  define STM32_UART5_RTOR       (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET)
-#  define STM32_UART5_RQR        (STM32_UART5_BASE+STM32_USART_RQR_OFFSET)
-#  define STM32_UART5_GTPR       (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET)
-#  define STM32_UART5_ISR        (STM32_UART5_BASE+STM32_USART_ISR_OFFSET)
-#  define STM32_UART5_ICR        (STM32_UART5_BASE+STM32_USART_ICR_OFFSET)
-#  define STM32_UART5_RDR        (STM32_UART5_BASE+STM32_USART_RDR_OFFSET)
-#  define STM32_UART5_TDR        (STM32_UART5_BASE+STM32_USART_TDR_OFFSET)
+#  define STM32_USART4_CR1        (STM32_USART4_BASE + STM32_USART_CR1_OFFSET)
+#  define STM32_USART4_CR2        (STM32_USART4_BASE + STM32_USART_CR2_OFFSET)
+#  define STM32_USART4_CR3        (STM32_USART4_BASE + STM32_USART_CR3_OFFSET)
+#  define STM32_USART4_BRR        (STM32_USART4_BASE + STM32_USART_BRR_OFFSET)
+#  define STM32_USART4_GTPR       (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET)
+#  define STM32_USART4_RTOR       (STM32_USART4_BASE + STM32_USART_RTOR_OFFSET)
+#  define STM32_USART4_RQR        (STM32_USART4_BASE + STM32_USART_RQR_OFFSET)
+#  define STM32_USART4_GTPR       (STM32_USART4_BASE + STM32_USART_GTPR_OFFSET)
+#  define STM32_USART4_ISR        (STM32_USART4_BASE + STM32_USART_ISR_OFFSET)
+#  define STM32_USART4_ICR        (STM32_USART4_BASE + STM32_USART_ICR_OFFSET)
+#  define STM32_USART4_RDR        (STM32_USART4_BASE + STM32_USART_RDR_OFFSET)
+#  define STM32_USART4_TDR        (STM32_USART4_BASE + STM32_USART_TDR_OFFSET)
+#  define STM32_USART4_PRESC      (STM32_USART4_BASE + STM32_USART_PRESC_OFFSET)
 #endif
 
 /* Register Bitfield Definitions ****************************************************/
 
+/* Control register 1 */
+
 #define USART_CR1_UE              (1 << 0)  /* Bit 0:  USART enable */
-#define USART_CR1_UESM            (1 << 1)  /* Bit 1:  USART enable in Stop mode */
+#define USART_CR1_UESM            (1 << 1)  /* Bit 1:  USART enable in low-power mode */
 #define USART_CR1_RE              (1 << 2)  /* Bit 2:  Receiver Enable */
 #define USART_CR1_TE              (1 << 3)  /* Bit 3:  Transmitter Enable */
 #define USART_CR1_IDLEIE          (1 << 4)  /* Bit 4:  IDLE Interrupt Enable */
@@ -153,33 +145,37 @@
 #define USART_CR1_PS              (1 << 9)  /* Bit 9:  Parity Selection */
 #define USART_CR1_PCE             (1 << 10) /* Bit 10: Parity Control Enable */
 #define USART_CR1_WAKE            (1 << 11) /* Bit 11: Receiver wakeup method */
-#define USART_CR1_M               (1 << 12) /* Bit 12: Word length */
+#define USART_CR1_M0              (1 << 12) /* Bit 12: Word length, bit 0 */
 #define USART_CR1_MME             (1 << 13) /* Bit 13: Mute mode enable */
 #define USART_CR1_CMIE            (1 << 14) /* Bit 14: Character match interrupt enable */
 #define USART_CR1_OVER8           (1 << 15) /* Bit 15: Oversampling mode */
 #define USART_CR1_DEDT_SHIFT      (16)      /* Bits 16-20: Driver Enable deassertion time */
 #define USART_CR1_DEDT_MASK       (31 << USART_CR1_DEDT_SHIFT)
+#  define USART_CR1_DEDT(n)       ((uint32_t)(n) << USART_CR1_DEDT_SHIFT)
 #define USART_CR1_DEAT_SHIFT      (21)      /* Bits 21-25: Driver Enable assertion time */
 #define USART_CR1_DEAT_MASK       (31 << USART_CR1_DEAT_SHIFT)
+#  define USART_CR1_DEAT(n)       ((uint32_t)(n) << USART_CR1_DEAT_SHIFT)
 #define USART_CR1_RTOIE           (1 << 26) /* Bit 26: Receiver timeout interrupt enable */
 #define USART_CR1_EOBIE           (1 << 27) /* Bit 27: End of Block interrupt enable */
+#define USART_CR1_M1              (1 << 28) /* Bit 28: Word length, bit 1 */
+#define USART_CR1_FIFOEN          (1 << 29) /* Bit 29: FIFO mode enable */
+#define USART_CR1_TXFEIE          (1 << 30) /* Bit 30: TXFIFO empty interrupt enable */
+#define USART_CR1_RXFFIE          (1 << 31) /* Bit 31: RXFIFO Full interrupt enable */
 
 #define USART_CR1_ALLINTS \
   (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\
-   USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE)
-
-/* F0 Compatibility definitions */
-
-#define USART_CR1_M0              USART_CR1_M
-#define USART_CR1_M1              0
+   USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE |\
+   USART_CR1_TXFEIE | USART_CR1_RXFFIE)
 
 /* Control register 2 */
 
-#define USART_CR2_ADDM7           (1 << 4)  /* Bit 4: :7-/4-bit Address Detection */
-#define USART_CR2_LBDL            (1 << 5)  /* Bit 5: LIN Break Detection Length */
-#define USART_CR2_LBDIE           (1 << 6)  /* Bit 6: LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL            (1 << 8)  /* Bit 8: Last Bit Clock pulse */
-#define USART_CR2_CPHA            (1 << 9)  /* Bit 9: Clock Phase */
+#define USART_CR2_SLVEN           (1 << 0)  /* Bit 0:  Synchronous Slave mode enable */
+#define USART_CR2_DISNSS          (1 << 3)  /* Bit 3:  Ignore NSS pin input */
+#define USART_CR2_ADDM7           (1 << 4)  /* Bit 4:  7-/4-bit Address Detection */
+#define USART_CR2_LBDL            (1 << 5)  /* Bit 5:  LIN Break Detection Length */
+#define USART_CR2_LBDIE           (1 << 6)  /* Bit 6:  LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL            (1 << 8)  /* Bit 8:  Last Bit Clock pulse */
+#define USART_CR2_CPHA            (1 << 9)  /* Bit 9:  Clock Phase */
 #define USART_CR2_CPOL            (1 << 10) /* Bit 10: Clock Polarity */
 #define USART_CR2_CLKEN           (1 << 11) /* Bit 11: Clock Enable */
 #define USART_CR2_STOP_SHIFT      (12)      /* Bits 13-12: STOP bits */
@@ -188,6 +184,7 @@
 #  define USART_CR2_STOP2         (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
 #  define USART_CR2_STOP1p5       (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
 #define USART_CR2_LINEN           (1 << 14) /* Bit 14: LIN mode enable */
+#define USART_CR2_SWAP            (1 << 15) /* Bit 15: Swap TX/RX pins */
 #define USART_CR2_RXINV           (1 << 16) /* Bit 16: RX pin active level inversion */
 #define USART_CR2_TXINV           (1 << 17) /* Bit 17: TX pin active level inversion */
 #define USART_CR2_DATAINV         (1 << 18) /* Bit 18: Binary data inversion */
@@ -200,17 +197,15 @@
 #  define USART_CR2_ABRMOD_7F     (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */
 #  define USART_CR2_ABRMOD_55     (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */
 #define USART_CR2_RTOEN           (1 << 23) /* Bit 23: Receiver timeout enable */
-#define USART_CR2_ADD4L_SHIFT     (24)      /* Bits 24-17: Address[3:0]:of the USART node */
-#define USART_CR2_ADD4L_MASK      (15 << USART_CR2_ADD4_SHIFT)
+#define USART_CR2_ADD4L_SHIFT     (24)      /* Bits 24-27: Address[3:0]:of the USART node */
+#define USART_CR2_ADD4L_MASK      (15 << USART_CR2_ADD4L_SHIFT)
+#  define USART_CR2_ADD4L(n)      ((uint32_t)(n) << USART_CR2_ADD4L_SHIFT)
 #define USART_CR2_ADD4H_SHIFT     (28)      /* Bits 28-31: Address[4:0] of the USART node */
-#define USART_CR2_ADD4H_MASK      (15 << USART_CR2_ADD4_SHIFT)
+#define USART_CR2_ADD4H_MASK      (15 << USART_CR2_ADD4H_SHIFT)
+#  define USART_CR2_ADD4H(n)      ((uint32_t)(n) << USART_CR2_ADD4H_SHIFT)
 #define USART_CR2_ADD8_SHIFT      (24)      /* Bits 24-31: Address[7:0] of the USART node */
 #define USART_CR2_ADD8_MASK       (255 << USART_CR2_ADD8_SHIFT)
-
-/* F0 Compatibility definitions */
-
-#define USART_CR2_SWAP            0
-#define USART_CR2_ADD_MASK        USART_CR2_ADD8_MASK
+#  define USART_CR2_ADD8(n)       ((uint32_t)(n) << USART_CR2_ADD8_SHIFT)
 
 /* Control register 3 */
 
@@ -232,35 +227,50 @@
 #define USART_CR3_DEP             (1 << 15) /* Bit 15: Driver enable polarity selection */
 #define USART_CR3_SCARCNT_SHIFT   (17)      /* Bit 17-19: Smartcard auto-retry count */
 #define USART_CR3_SCARCNT_MASK    (7 << USART_CR3_SCARCNT_SHIFT)
-#define USART_CR3_WUS_SHIFT       (20)      /* Bit 20-21: Wakeup from Stop mode interrupt */
-#define USART_CR3_WUS_MASK        (3 << USART_CR3_WUS_SHIFT)
-#  define USART_CR3_WUS_ADDRMAT   (0 << USART_CR3_WUS_SHIFT) /* Active on address match */
-#  define USART_CR3_WUS_STARTBIT  (2 << USART_CR3_WUS_SHIFT) /* Active on Start bit */
-#  define USART_CR3_WUS_RXNE      (3 << USART_CR3_WUS_SHIFT) /* Active on RXNE */
-#define USART_CR3_WUFIE           (1 << 22) /* Bit 22:  Wakeup from Stop mode interrupt enable */
+#  define USART_CR3_SCARCNT(n)    ((uint32_t)(n) << USART_CR3_SCARCNT_SHIFT)
+#define USART_CR3_RXFTCFG_SHIFT   (25)      /* Bit 25-27: Receive FIFO threshold configuration */
+#define USART_CR3_RXFTCFG_MASK    (7 << USART_CR3_RXFTCFG_SHIFT)
+#  define USART_CR3_RXFTCFG(n)    ((uint32_t)(n) << USART_CR3_RXFTCFG_SHIFT)
+#  define USART_CR3_RXFTCFG_12PCT (0 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/8 full */
+#  define USART_CR3_RXFTCFG_25PCT (1 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/4 full */
+#  define USART_CR3_RXFTCFG_50PCT (2 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 1/2 full */
+#  define USART_CR3_RXFTCFG_75PCT (3 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 3/4 full */
+#  define USART_CR3_RXFTCFG_88PCT (4 << USART_CR3_RXFTCFG_SHIFT) /* RXFIFO 7/8 full */
+#  define USART_CR3_RXFTCFG_FULL  (5 << USART_CR3_RXFTCFG_SHIFT) /* RXIFO full */
+#define USART_CR3_RXFTIE          (1 << 28) /* Bit 28: RXFIFO threshold interrupt enable */
+#define USART_CR3_TXFTCFG_SHIFT   (29)      /* Bits 29-31: TXFIFO threshold configuration */
+#define USART_CR3_TXFTCFG_MASK    (7 << USART_CR3_TXFTCFG_SHIFT)
+#  define USART_CR3_TXFTCFG(n)    ((uint32_t)(n) << USART_CR3_TXFTCFG_SHIFT)
+#  define USART_CR3_TXFTCFG_12PCT (0 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/8 full */
+#  define USART_CR3_TXFTCFG_24PCT (1 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/4 full */
+#  define USART_CR3_TXFTCFG_50PCT (2 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 1/2 full */
+#  define USART_CR3_TXFTCFG_75PCT (3 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 3/4 full */
+#  define USART_CR3_TXFTCFG_88PCT (4 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO 7/8 full */
+#  define USART_CR3_TXFTCFG_EMPY  (5 << USART_CR3_TXFTCFG_SHIFT) /* TXFIFO empty */
 
 /* Baud Rate Register */
 
 #define USART_BRR_SHIFT           (0)       /* Bits 0-15: USARTDIV[15:0] OVER8=0*/
 #define USART_BRR_MASK            (0xffff << USART_BRR_SHIFT)
-#define USART_BRR_0_3_SHIFT       (0)       /* Bits 0-2: USARTDIV[3:0] OVER8=1 */
-#define USART_BRR_0_3_MASK        (0x0fff << USART_BRR_0_3_SHIFT)
-#define USART_BRR_4_7_SHIFT       (0)       /* Bits 4-15: USARTDIV[15:4] OVER8=1*/
-#define USART_BRR_4_7_MASK        (0xffff << USART_BRR_4_7_SHIFT)
+#  define USART_BRR(n)            ((uint32_t)(n) << USART_BRR_SHIFT)
 
 /* Guard time and prescaler register */
 
 #define USART_GTPR_PSC_SHIFT      (0)       /* Bits 0-7: Prescaler value */
 #define USART_GTPR_PSC_MASK       (0xff << USART_GTPR_PSC_SHIFT)
+#  define USART_GTPR_PSC(n)       ((uint32_t)(n) << USART_GTPR_PSC_SHIFT)
 #define USART_GTPR_GT_SHIFT       (8)       /* Bits 8-15: Guard time value */
 #define USART_GTPR_GT_MASK        (0xff <<  USART_GTPR_GT_SHIFT)
+#  define USART_GTPR_GT(n)        ((uint32_t)(n) <<  USART_GTPR_GT_SHIFT)
 
 /* Receiver timeout register */
 
 #define USART_RTOR_RTO_SHIFT      (0)       /* Bits 0-23: Receiver timeout value */
 #define USART_RTOR_RTO_MASK       (0xffffff << USART_RTOR_RTO_SHIFT)
+#  define USART_RTOR_RTO(n)       ((uint32_t)(n) << USART_RTOR_RTO_SHIFT)
 #define USART_RTOR_BLEN_SHIFT     (24)      /* Bits 24-31: Block Length */
 #define USART_RTOR_BLEN_MASK      (0xff << USART_RTOR_BLEN_SHIFT)
+#  define USART_RTOR_BLEN(n)      ((uint32_t)(n) << USART_RTOR_BLEN_SHIFT)
 
 /* Request register */
 
@@ -274,7 +284,7 @@
 
 #define USART_ISR_PE              (1 << 0)  /* Bit 0:  Parity error */
 #define USART_ISR_FE              (1 << 1)  /* Bit 1:  Framing error */
-#define USART_ISR_NF              (1 << 2)  /* Bit 2:  Noise detected flag */
+#define USART_ISR_NE              (1 << 2)  /* Bit 2:  Noise detected flag */
 #define USART_ISR_ORE             (1 << 3)  /* Bit 3:  Overrun error */
 #define USART_ISR_IDLE            (1 << 4)  /* Bit 4:  Idle line detected */
 #define USART_ISR_RXNE            (1 << 5)  /* Bit 5:  Read data register not empty */
@@ -285,17 +295,23 @@
 #define USART_ISR_CTS             (1 << 10) /* Bit 10: CTS flag */
 #define USART_ISR_RTOF            (1 << 11) /* Bit 11: Receiver timeout */
 #define USART_ISR_EOBF            (1 << 12) /* Bit 12: End of block flag */
+#define USART_ISR_UDR             (1 << 13) /* Bit 13: SPI slave underrun error flag */
 #define USART_ISR_ABRE            (1 << 14) /* Bit 14: Auto baud rate error */
 #define USART_ISR_ABRF            (1 << 15) /* Bit 15: Auto baud rate flag */
 #define USART_ISR_BUSY            (1 << 16) /* Bit 16: Busy flag */
 #define USART_ISR_CMF             (1 << 17) /* Bit 17: Character match flag */
 #define USART_ISR_SBKF            (1 << 18) /* Bit 18: Send break flag */
-#define USART_ISR_ISRRWU          (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */
-#define USART_ISR_WUF             (1 << 20) /* Bit 20: Wakeup from Stop mode flag */
+#define USART_ISR_RWU             (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */
+#define USART_ISR_WUF             (1 << 20) /* Bit 20: Wakeup from low-power mode flag */
 #define USART_ISR_TEACK           (1 << 21) /* Bit 21: Transmit enable acknowledge flag */
 #define USART_ISR_REACK           (1 << 22) /* Bit 22: Receive enable acknowledge flag */
+#define USART_ISR_TXFE            (1 << 23) /* Bit 23: TXFIFO Empty */
+#define USART_ISR_RXFF            (1 << 24) /* Bit 24: RXFIFO Full */
+#define USART_ISR_TCBGT           (1 << 25) /* Bit 25: Transmission complete before guard time flag */
+#define USART_ISR_RXFT            (1 << 26) /* Bit 26: RXFIFO threshold flag */
+#define USART_ISR_TXFT            (1 << 27) /* Bit 27: TXFIFO threshold flag */
 
-#define USART_ISR_ALLBITS         (0x007fdfff)
+#define USART_ISR_ALLBITS         (0x0fffffff)
 
 /* Interrupt flag clear register */
 
@@ -304,42 +320,44 @@
 #define USART_ICR_NCF             (1 << 2)  /* Bit 2:  Noise detected flag *clear flag */
 #define USART_ICR_ORECF           (1 << 3)  /* Bit 3:  Overrun error clear flag */
 #define USART_ICR_IDLECF          (1 << 4)  /* Bit 4:  Idle line detected clear flag */
+#define USART_ICR_TXFECF          (1 << 5)  /* Bit 5:  TXFIFO empty clear flag */
 #define USART_ICR_TCCF            (1 << 6)  /* Bit 6:  Transmission complete */
+#define USART_ICR_TCBGTCF         (1 << 7)  /* Bit 7:  Transmission complete before Guard time clear flag */
 #define USART_ICR_LBDCF           (1 << 8)  /* Bit 8:  LIN break detection clear flag */
 #define USART_ICR_CTSCF           (1 << 9)  /* Bit 9:  CTS interrupt clear flag */
 #define USART_ICR_RTOCF           (1 << 11) /* Bit 11: Receiver timeout clear flag */
 #define USART_ICR_EOBCF           (1 << 12) /* Bit 12: End of block clear flag */
+#define USART_ICR_UDRCF           (1 << 13) /* Bit 13:SPI slave underrun clear flag */
 #define USART_ICR_CMCF            (1 << 17) /* Bit 17: Character match clear flag */
-#define USART_ICR_WUCF            (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */
+#define USART_ICR_WUCF            (1 << 20) /* Bit 20: Wakeup from low-power mode clear flag */
 
-#define USART_ICR_ALLBITS         (0x00121b5f)
+#define USART_ICR_ALLBITS         (0x00123b7f)
 
 /* Receive data register */
 
-#define USART_RDR_SHIFT           (0)       /* Bits 8:0: Receive data value */
+#define USART_RDR_SHIFT           (0)       /* Bits 0-8: Receive data value */
 #define USART_RDR_MASK            (0x1ff << USART_RDR_SHIFT)
 
 /* Transmit data register */
 
-#define USART_TDR_SHIFT           (0)       /* Bits 8:0: Transmit data value */
+#define USART_TDR_SHIFT           (0)       /* Bits 0-8: Transmit data value */
 #define USART_TDR_MASK            (0x1ff << USART_TDR_SHIFT)
 
-/* Compatibility definitions ********************************************************/
-/* F1/F2/F4 Status register */
+/* Prescaler register */
 
-#define STM32_USART_SR_OFFSET     STM32_USART_ISR_OFFSET
+#define USART_PRESC_SHIFT         (0)       /* Bits 0-3: Clock prescaler */
+#define USART_PRESC_MASK          (15 << USART_PRESC_SHIFT)
+# define USART_PRESC_NODIV        (0 << USART_PRESC_SHIFT)  /* Input clock not divided */
+# define USART_PRESC_DIV1         (1 << USART_PRESC_SHIFT)  /* Input clock divided by 2 */
+# define USART_PRESC_DIV4         (2 << USART_PRESC_SHIFT)  /* Input clock divided by 4 */
+# define USART_PRESC_DIV6         (3 << USART_PRESC_SHIFT)  /* Input clock divided by 6 */
+# define USART_PRESC_DIV8         (4 << USART_PRESC_SHIFT)  /* Input clock divided by 8 */
+# define USART_PRESC_DIV10        (5 << USART_PRESC_SHIFT)  /* Input clock divided by 10 */
+# define USART_PRESC_DIV12        (6 << USART_PRESC_SHIFT)  /* Input clock divided by 12 */
+# define USART_PRESC_DIV16        (7 << USART_PRESC_SHIFT)  /* Input clock divided by 16 */
+# define USART_PRESC_DIV32        (8 << USART_PRESC_SHIFT)  /* Input clock divided by 32 */
+# define USART_PRESC_DIV64        (9 << USART_PRESC_SHIFT)  /* Input clock divided by 64 */
+# define USART_PRESC_DIV128       (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */
+# define USART_PRESC_DIV256       (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */
 
-#define USART_SR_PE               USART_ISR_PE   /* Parity Error */
-#define USART_SR_FE               USART_ISR_FE   /* Framing error */
-#define USART_SR_NE               USART_ISR_NF   /* Noise detected flag */
-#define USART_SR_ORE              USART_ISR_ORE  /* Overrun error */
-#define USART_SR_IDLE             USART_ISR_IDLE /* IDLE line detected */
-#define USART_SR_RXNE             USART_ISR_RXNE /* Read Data Register Not Empty */
-#define USART_SR_TC               USART_ISR_TC   /* Transmission Complete */
-#define USART_SR_TXE              USART_ISR_TXE  /* Transmit Data Register Empty */
-#define USART_SR_LBD              USART_ISR_LBDF /* LIN Break Detection Flag */
-#define USART_SR_CTS              USART_ISR_CTS  /* Bit 9: CTS Flag */
-
-#define USART_SR_ALLBITS          USART_ISR_ALLBITS
-
-#endif /* __ARCH_ARM_STC_STM32F0L0_HARDWARE_STM32L0_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h
similarity index 98%
rename from arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h
index a93160654e7..55bc7cc4a97 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_usbdev.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_USBDEV_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_USBDEV_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#ifdef CONFIG_STM32F0L0_HAVE_USBDEV
+#ifdef CONFIG_STM32F0L0G0_HAVE_USBDEV
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -260,5 +260,5 @@
 #define USB_COUNT_RX_SHIFT             (0)       /* Bits 9-0: Reception Byte Count */
 #define USB_COUNT_RX_MASK              (0x03ff << USB_COUNT_RX_SHIFT)
 
-#endif /* CONFIG_STM32F0L0_HAVE_USBDEV */
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_USBDEV_H */
+#endif /* CONFIG_STM32F0L0G0_HAVE_USBDEV */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_wdt.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h
similarity index 96%
rename from arch/arm/src/stm32f0l0/hardware/stm32_wdt.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h
index e545b818af6..0f122ad2236 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_wdt.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_wdt.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_WDG_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_WDG_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H
 
 /************************************************************************************
  * Included Files
@@ -139,4 +139,4 @@
 
 #define WWDG_SR_EWIF           (1 << 0)  /* Bit 0: Early Wakeup Interrupt Flag */
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_WDG_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h
similarity index 95%
rename from arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h
index 153a4c1a388..1c5b64030d2 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F05X_PINMAP_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F05X_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -59,7 +59,7 @@
  *
  * #define GPIO_USART1_TX GPIO_USART1_TX_1
  *
- * The driver will then automatically configre PD0 as the CAN1 RX pin.
+ * The driver will then automatically configure PD0 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -133,4 +133,4 @@
 #define GPIO_I2C2_SCL       (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN10)
 #define GPIO_I2C2_SDA       (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_SPEED_HIGH | GPIO_PORTB | GPIO_PIN11)
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F05X_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h
similarity index 96%
rename from arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h
index 7aed68d2dd9..26b0f8e7501 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -119,7 +119,7 @@
 #define STM32_USART6_BASE    0x40011400     /* 0x40011400-0x400117ff USART6 */
 #define STM32_USART7_BASE    0x40011800     /* 0x40011800-0x40011bff USART7 */
 #define STM32_USART8_BASE    0x40011c00     /* 0x40011c00-0x40011fff USART8 */
-#define STM32_ADC1_BASE      0x40012400     /* 0x40012400-0x400127ff ADC 1 */
+#define STM32_ADC12_BASE     0x40012400     /* 0x40012400-0x400127ff ADC 12 */
 #define STM32_TIM1_BASE      0x40012c00     /* 0x40012c00-0x40012fff TIM1 */
 #define STM32_SPI1_BASE      0x40013000     /* 0x40013000-0x400133ff SPI1 */
 #define STM32_USART1_BASE    0x40013800     /* 0x40013800-0x40013bff USART1 */
@@ -154,4 +154,4 @@
 #define STM32_SCS_BASE       0xe000e000
 #define STM32_DEBUGMCU_BASE  0xe0042000
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_ST32F05XF07XF09X_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32F05XF07XF09X_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h
similarity index 98%
rename from arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h
index 18cf426856f..eb40ae357c7 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F07X_PINMAP_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F07X_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -58,7 +58,7 @@
  *
  * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
  *
- * The driver will then automatically configre PD0 as the CAN1 RX pin.
+ * The driver will then automatically configure PD0 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -397,4 +397,4 @@
 
 #define GPIO_USB_NOE             (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN13)
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F07X_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h
similarity index 98%
rename from arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h
index 5c55782f865..cab3346f008 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F09X_PINMAP_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F09X_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -58,7 +58,7 @@
  *
  * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
  *
- * The driver will then automatically configre PD0 as the CAN1 RX pin.
+ * The driver will then automatically configure PD0 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -427,4 +427,4 @@
 #define GPIO_USART8_RX_3         (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN13)
 #define GPIO_USART8_CK_RST       (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN14)
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F09X_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f0_exti.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h
similarity index 96%
rename from arch/arm/src/stm32f0l0/hardware/stm32f0_exti.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h
index cee311b6dcc..cbd8dd85930 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32f0_exti.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_exti.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h
  *
  *   Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_EXTI_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_EXTI_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H
 
 /************************************************************************************
  * Included Files
@@ -128,4 +128,4 @@
 #define EXTI_PR_SHIFT            (0)                /* Bits 0-X: Pending bit for all lines */
 #define EXTI_PR_MASK             STM32_EXTI_MASK
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_EXTI_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f0_flash.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h
similarity index 95%
rename from arch/arm/src/stm32f0l0/hardware/stm32f0_flash.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h
index d46e2c6117a..6e3534693ab 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32f0_flash.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32f0_flash.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_FLASH_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_FLASH_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H
 
 /************************************************************************************
  * Included Files
@@ -105,4 +105,4 @@
 
 #define FLASH_OBR_                            /* To be provided */
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_FLASH_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f0_pwr.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h
similarity index 95%
rename from arch/arm/src/stm32f0l0/hardware/stm32f0_pwr.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h
index d28979805a5..17eda3ccbdf 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32f0_pwr.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32f0_pwr.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h
  *
  *   Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_PWR_H
-#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_PWR_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H
 
 /************************************************************************************
  * Included Files
@@ -97,4 +97,4 @@
 #define PWR_CSR_EWUP7        (1 << 14) /* Bit 14: Enable WKUP7 pin */
 #define PWR_CSR_EWUP8        (1 << 15) /* Bit 15: Enable WKUP8 pin */
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32F0_PWR_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h
similarity index 98%
rename from arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h
index b21f2977df7..35df2a34c1c 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_RCC_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -363,6 +363,8 @@
 #  define RCC_CFGR3_USART1SW_HSI    (3 << RCC_CFGR3_USART1SW_SHIFT) /* HSI is USART1 clock */
 #define RCC_CFGR3_CECSW             (1 << 6)  /* Bit 6: HDMI CEC clock source selection */
 #define RCC_CFGR3_USBSW             (1 << 7)  /* Bit 7: USB clock source selection */
+#define RCC_CFGR3_CLK48_HSI48       0
+#define RCC_CFGR3_CLK48_PLL         (1 << 7)
 #define RCC_CFGR3_ADCSW             (1 << 8)  /* Bit 8: ADC clock source selection */
 #define RCC_CFGR3_USART2SW_SHIFT    (16)      /* Bits 16-17: USART2 clock source selection */
 #define RCC_CFGR3_USART2SW_MASK     (3 << RCC_CFGR3_USART2SW_SHIFT)
@@ -391,4 +393,4 @@
 #define RCC_CR2_HSI48CAL_SHIFT      (24)      /* Bits 24-31: HSI48 factory clock calibration */
 #define RCC_CR2_HSI48CAL_MASK       (0xff << RCC_CR2_HSI48CAL_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f0_syscfg.h b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h
similarity index 99%
rename from arch/arm/src/stm32f0l0/hardware/stm32f0_syscfg.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h
index 4954abd928e..a3314f6d121 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32f0_syscfg.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32f0_syscfg.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h
  *
  *   Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -388,4 +388,4 @@
 #define SYSCFG_ITLINE30_CEC            (1 << 0)  /* Bit 0: CEC interrupt request pending, combined with EXTI line 27 */
 #define SYSCFG_ITLINE30_CAN            (1 << 1)  /* Bit 1: CAN interrupt request pending */
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32F0_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h
new file mode 100644
index 00000000000..60d1019c811
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h
@@ -0,0 +1,74 @@
+/************************************************************************************
+ * arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* DMAMUX1 mapping ****************************************************/
+
+/* NOTE: DMAMUX1 channels 0 to 7 are connected to DMA1 channels 0 to 7 */
+
+#define DMAMUX1_REQ_GEN0       (1)
+#define DMAMUX1_REQ_GEN1       (2)
+#define DMAMUX1_REQ_GEN2       (3)
+#define DMAMUX1_REQ_GEN3       (4)
+#define DMAMUX1_ADC1           (5)
+#define DMAMUX1_AES_IN         (6)
+#define DMAMUX1_AES_OUT        (7)
+
+/* TODO: ... */
+
+/* DMAP for DMA1 */
+
+#define DMAMAP_DMA1_REGGEN0     DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN0)
+#define DMAMAP_DMA1_REGGEN1     DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN1)
+#define DMAMAP_DMA1_REGGEN2     DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN2)
+#define DMAMAP_DMA1_REGGEN3     DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN3)
+#define DMAMAP_DMA1_ADC1        DMAMAP_MAP(DMA1, DMAMUX1_ADC1)
+
+/* TODO: ... */
+
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h
new file mode 100644
index 00000000000..7031badc2ce
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h
@@ -0,0 +1,103 @@
+/************************************************************************************
+ * arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+#define STM32_NEXTI              18
+#define STM32_EXTI_MASK          0xffffffff
+
+#define STM32_EXTI_BIT(n)        (1 << (n))
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_EXTI_RTSR1_OFFSET     0x0000  /* Rising Trigger selection register 1 */
+#define STM32_EXTI_FTSR1_OFFSET     0x0004  /* Falling Trigger selection register 1 */
+#define STM32_EXTI_SWIER1_OFFSET    0x0008  /* Software interrupt event register 1 */
+#define STM32_EXTI_RPR1_OFFSET      0x000c  /* Rising edge pending register 1 */
+#define STM32_EXTI_FPR1_OFFSET      0x0010  /* Falling edge pending register 1 */
+
+#define STM32_EXTI_EXTICR_OFFSET(p) (0x0060 + ((p) & 0x000c)) /* Registers are displaced by 4! */
+#define STM32_EXTI_EXTICR1_OFFSET   0x0060  /* External interrupt selection register 1 */
+#define STM32_EXTI_EXTICR2_OFFSET   0x0064  /* External interrupt selection register 2 */
+#define STM32_EXTI_EXTICR3_OFFSET   0x0068  /* External interrupt selection register 3 */
+#define STM32_EXTI_EXTICR4_OFFSET   0x006c  /* External interrupt selection register 4 */
+#define STM32_EXTI_IMR1_OFFSET      0x0080  /* CPU wakeup with interrupt mask register 1 */
+#define STM32_EXTI_EMR1_OFFSET      0x0084  /* CPU wakeup with event mask register 1 */
+#define STM32_EXTI_IMR2_OFFSET      0x0090  /* CPU wakeup with interrupt mask register 2 */
+#define STM32_EXTI_EMR2_OFFSET      0x0094  /* CPU wakeup with event mask register 2 */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_EXTI_RTSR1            (STM32_EXTI_BASE + STM32_EXTI_RTSR1_OFFSET)
+#define STM32_EXTI_FTSR1            (STM32_EXTI_BASE + STM32_EXTI_FTSR1_OFFSET)
+#define STM32_EXTI_SWIER1           (STM32_EXTI_BASE + STM32_EXTI_SWIER1_OFFSET)
+#define STM32_EXTI_RPR1             (STM32_EXTI_BASE + STM32_EXTI_RPR1_OFFSET)
+#define STM32_EXTI_FPR1             (STM32_EXTI_BASE + STM32_EXTI_FPR1_OFFSET)
+#define STM32_EXTI_EXTICR(p)        (STM32_EXTI_BASE + STM32_EXTI_EXTICR_OFFSET(p))
+#define STM32_EXTI_IMR1             (STM32_EXTI_BASE + STM32_EXTI_IMR1_OFFSET)
+#define STM32_EXTI_EMR1             (STM32_EXTI_BASE + STM32_EXTI_EMR1_OFFSET)
+#define STM32_EXTI_IMR2             (STM32_EXTI_BASE + STM32_EXTI_IMR2_OFFSET)
+#define STM32_EXTI_EMR2             (STM32_EXTI_BASE + STM32_EXTI_EMR2_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* EXTI external interrupt configuration register 1-4 */
+
+#define EXTI_EXTICR_PORTA           (0)       /* 0000: PA[x] pin */
+#define EXTI_EXTICR_PORTB           (1)       /* 0001: PB[x] pin */
+#define EXTI_EXTICR_PORTC           (2)       /* 0010: PC[x] pin */
+#define EXTI_EXTICR_PORTD           (3)       /* 0011: PD[x] pin */
+                                                /* 0100: Reserved */
+#define EXTI_EXTICR_PORTF           (5)       /* 0100: PF[x] pin */
+
+#define EXTI_EXTICR_PORT_MASK       (0xff)
+#define EXTI_EXTICR_EXTI_SHIFT(g)   (((g) & 3) << 3)
+#define EXTI_EXTICR_EXTI_MASK(g)    (EXTI_EXTICR_PORT_MASK << (EXTI_EXTICR_EXTI_SHIFT(g)))
+
+/* TODO */
+
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h
new file mode 100644
index 00000000000..c01bab4149d
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h
@@ -0,0 +1,107 @@
+/************************************************************************************
+ * arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_FLASH_ACR_OFFSET       0x0000
+#define STM32_FLASH_KEYR_OFFSET      0x0008
+#define STM32_FLASH_OPTKEYR_OFFSET   0x000c
+#define STM32_FLASH_SR_OFFSET        0x0010
+#define STM32_FLASH_CR_OFFSET        0x0014
+#define STM32_FLASH_ECCR_OFFSET      0x0018
+#define STM32_FLASH_OPTR_OFFSET      0x0020
+#define STM32_FLASH_PCROP1ASE_OFFSET 0x0024
+#define STM32_FLASH_PCROP1AER_OFFSET 0x0028
+#define STM32_FLASH_WPR1AR_OFFSET    0x002c
+#define STM32_FLASH_WPR1BR_OFFSET    0x0030
+#define STM32_FLASH_WPR1BSR_OFFSET   0x0034
+#define STM32_FLASH_PCROP1BER_OFFSET 0x0038
+#define STM32_FLASH_SECR_OFFSET      0x0080
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_FLASH_ACR              (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET)
+#define STM32_FLASH_KEYR             (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET)
+#define STM32_FLASH_OPTKEYR          (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
+#define STM32_FLASH_SR               (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
+#define STM32_FLASH_CR               (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
+#define STM32_FLASH_ECCR             (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET)
+#define STM32_FLASH_OPTR             (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET)
+#define STM32_FLASH_PCROP1ASE        (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ASE_OFFSET)
+#define STM32_FLASH_PCROP1AER        (STM32_FLASHIF_BAER+STM32_FLASH_PCROP1AER_OFFSET)
+#define STM32_FLASH_WPR1AR           (STM32_FLASHIF_BASE+STM32_FLASH_WPR1AR_OFFSET)
+#define STM32_FLASH_WPR1BR           (STM32_FLASHIF_BASE+STM32_FLASH_WPR1BR_OFFSET)
+#define STM32_FLASH_WPR1BSR          (STM32_FLASHIF_BASE+STM32_FLASH_WPR1BSR_OFFSET)
+#define STM32_FLASH_PCROP1BER        (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1BER_OFFSET)
+#define STM32_FLASH_SECR             (STM32_FLASHIF_BASE+STM32_FLASH_SECR_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+/* Flash Access Control Register (ACR) */
+
+#define FLASH_ACR_LATENCY_SHIFT     (0)       /* Bits 0-2: Flash memory access latency*/
+#define FLASH_ACR_LATENCY_MASK      (7 << FLASH_ACR_LATENCY_SHIFT)
+#  define FLASH_ACR_LATENCY(n)      ((n) << FLASH_ACR_LATENCY_SHIFT)
+#  define FLASH_ACR_LATENCY_0       (0 << FLASH_ACR_LATENCY_SHIFT)    /* 000: Zero wait states  */
+#  define FLASH_ACR_LATENCY_1       (1 << FLASH_ACR_LATENCY_SHIFT)    /* 001: One wait state    */
+#  define FLASH_ACR_LATENCY_2       (2 << FLASH_ACR_LATENCY_SHIFT)    /* 010: Two wait states   */
+                                              /* Bits 3-7: Reserved */
+#define FLASH_ACR_PRFTEN            (1 << 8)  /* Bit 8: Prefetch enable */
+#define FLASH_ACR_ICEN              (1 << 9)  /* Bit 9: Instruction cache enable */
+                                              /* Bit 10:Reserved */
+#define FLASH_ACR_ICRST             (1 << 11) /* Bit 11:Instruction cache reset */
+                                              /* Bits 12-15: Reserved */
+#define FLASH_ACR_EMPTY             (1 << 16) /* Bit 16: Main Flash memory area empty */
+                                              /* Bit 17: Reserved */
+#define FLASH_ACR_DBGSWEN           (1 << 18) /* Bit 18: Debug access software enable */
+                                              /* Bits 19-31: Reserved */
+
+/* TODO */
+
+
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h
new file mode 100644
index 00000000000..889df8dfa0e
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h
@@ -0,0 +1,140 @@
+/************************************************************************************
+ * arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32G0_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32G0_MEMORYMAP_H
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* ST32F05XF07X Address Blocks ******************************************************/
+
+#define STM32_CODE_BASE      0x00000000     /* 0x00000000-0x1fffffff: 512Mb code block */
+#define STM32_SRAM_BASE      0x20000000     /* 0x20000000-0x3fffffff: 512Mb sram block */
+#define STM32_PERIPH_BASE    0x40000000     /* 0x40000000-0x5fffffff: 512Mb peripheral block */
+                                            /* 0x60000000-0xdfffffff: Reserved */
+#define STM32_CORTEX_BASE    0xe0000000     /* 0xe0000000-0xffffffff: 512Mb Cortex-M0 block */
+
+#define STM32_REGION_MASK    0xf0000000
+#define STM32_IS_SRAM(a)     ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
+
+/* Code Base Addresses **************************************************************/
+
+#define STM32_BOOT_BASE      0x00000000     /* 0x00000000-0x0001ffff: Aliased boot memory */
+                                            /* 0x00020000-0x07ffffff: Reserved */
+#define STM32_FLASH_BASE     0x08000000     /* 0x08000000-0x0801ffff: FLASH memory */
+                                            /* 0x08020000-0x1fffd7ff: Reserved */
+#define STM32_SYSMEM_BASE    0x1fff0000     /* 0x1fff0000-0x1fff77ff: System memory */
+#define STM32_OPTION_BASE    0x1fff7800     /* 0x1fff7800-0x1fff7fff: Option bytes */
+
+/* Peripheral Base Addresses ********************************************************/
+
+#define STM32_APB1_BASE      0x40000000     /* 0x40000000-0x4000b3ff: APB1 */
+                                            /* 0x4000b400-0x4000ffff: Reserved */
+#define STM32_APB2_BASE      0x40010000     /* 0x40010000-0x40015800: APB2 */
+                                            /* 0x40015c00-0x4001ffff: Reserved */
+#define STM32_AHB_BASE       0x40020000     /* 0x40020000-0x400263ff: AHB */
+                                            /* 0x40026400-0x4fffffff: Reserved */
+#define STM32_IOPORT_BASE    0x50000000     /* 0x50000000-0x50001fff: IOPORT */
+
+/* APB1 Base Addresses **************************************************************/
+
+#define STM32_TIM2_BASE      0x40000000     /* 0x40000000-0x400003ff TIM2 */
+#define STM32_TIM3_BASE      0x40000400     /* 0x40000400-0x400007ff TIM3 */
+#define STM32_TIM6_BASE      0x40001000     /* 0x40001000-0x400013ff TIM6 */
+#define STM32_TIM7_BASE      0x40001400     /* 0x40001400-0x400017ff TIM7 */
+#define STM32_TIM14_BASE     0x40002000     /* 0x40002000-0x400023ff TIM14 */
+#define STM32_RTC_BASE       0x40002800     /* 0x40002800-0x40002bff RTC */
+#define STM32_WWDG_BASE      0x40002c00     /* 0x40002c00-0x40002fff WWDG */
+#define STM32_IWDG_BASE      0x40003000     /* 0x40003000-0x400033ff IWDG */
+#define STM32_SPI2_BASE      0x40003800     /* 0x40003800-0x40003bff SPI2, or */
+#define STM32_I2S2_BASE      0x40003800     /* 0x40003800-0x40003bff I2S2 */
+#define STM32_USART2_BASE    0x40004400     /* 0x40004400-0x400047ff USART2 */
+#define STM32_USART3_BASE    0x40004800     /* 0x40004800-0x40004bff USART3 */
+#define STM32_USART4_BASE    0x40004c00     /* 0x40004c00-0x40004fff USART4 */
+#define STM32_I2C1_BASE      0x40005400     /* 0x40005400-0x400057ff I2C1 */
+#define STM32_I2C2_BASE      0x40005800     /* 0x40005800-0x40005bff I2C2 */
+#define STM32_PWR_BASE       0x40007000     /* 0x40007000-0x400073ff PWR */
+#define STM32_DAC1_BASE      0x40007400     /* 0x40007400-0x400077ff DAC 1 */
+#define STM32_CEC_BASE       0x40007800     /* 0x40007800-0x40007bff HDMI CEC */
+#define STM32_LPTIM1_BASE    0x40007C00     /* 0x40007c00-0x40007fff LPTIM1 */
+#define STM32_LPUART1_BASE   0x40008000     /* 0x40008000-0x400083ff LPUART1 */
+#define STM32_LPTIM2_BASE    0x40009400     /* 0x40009400-0x400097ff LPTIM2 */
+#define STM32_UCPD1_BASE     0x4000a000     /* 0x4000a000-0x4000a3ff UCPD1 */
+#define STM32_UCPD2_BASE     0x4000a400     /* 0x4000a400-0x4000a7ff UCPD2 */
+#define STM32_TAMP_BASE      0x4000b000     /* 0x4000b000-0x4000b3ff TAMP */
+
+/* APB2 Base Addresses **************************************************************/
+
+#define STM32_SYSCFG_BASE    0x40010000     /* 0x40010000-0x400103ff SYSCFG */
+/* EXTI ??? */
+#define STM32_ADC1_BASE      0x40012400     /* 0x40012400-0x400127ff ADC 1 */
+#define STM32_TIM1_BASE      0x40012c00     /* 0x40012c00-0x40012fff TIM1 */
+#define STM32_SPI1_BASE      0x40013000     /* 0x40013000-0x400133ff SPI1 */
+#define STM32_USART1_BASE    0x40013800     /* 0x40013800-0x40013bff USART1 */
+#define STM32_TIM15_BASE     0x40014000     /* 0x40014000-0x400143ff TIM15 */
+#define STM32_TIM16_BASE     0x40014400     /* 0x40014400-0x400147ff TIM16 */
+#define STM32_TIM17_BASE     0x40014800     /* 0x40014800-0x40014bff TIM17 */
+#define STM32_DBGMCU_BASE    0x40015800     /* 0x40015800-0x40015bff DBGMCU */
+
+/* AHB1 Base Addresses **************************************************************/
+
+#define STM32_DMA1_BASE      0x40020000     /* 0x40020000-0x400203ff: DMA1  */
+#define STM32_DMAMUX_BASE    0x40020800     /* 0x40020800-0x40020bff: DMAMUX  */
+#define STM32_RCC_BASE       0x40021000     /* 0x40021000-0x400213ff: Reset and Clock control RCC */
+#define STM32_EXTI_BASE      0x40021800     /* 0x40021800-0x40021bff: EXTI */
+#define STM32_FLASHIF_BASE   0x40022000     /* 0x40022000-0x400223ff: Flash memory interface */
+#define STM32_CRC_BASE       0x40023000     /* 0x40023000-0x400233ff: CRC */
+#define STM32_RNG_BASE       0x40025000     /* 0x40025000-0x400253ff: RNG */
+#define STM32_AES_BASE       0x40026000     /* 0x40026000-0x400263ff: AES */
+
+/* AHB2 Base Addresses **************************************************************/
+
+#define STM32_GPIOA_BASE     0x50000000     /* 0x50000000-0x500003ff: GPIO Port A */
+#define STM32_GPIOB_BASE     0x50000400     /* 0x50000400-0x500007ff: GPIO Port B */
+#define STM32_GPIOC_BASE     0x50000800     /* 0x50000800-0x50000bff: GPIO Port C */
+#define STM32_GPIOD_BASE     0X50000C00     /* 0x50000c00-0x50000fff: GPIO Port D */
+#define STM32_GPIOF_BASE     0x50001400     /* 0x50001400-0x500017ff: GPIO Port F */
+
+/* Cortex-M4 Base Addresses *********************************************************/
+/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this
+ * address range
+ */
+
+#define STM32_SCS_BASE       0xe000e000
+#define STM32_DEBUGMCU_BASE  0xe0042000
+
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_ST32G0_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h
new file mode 100644
index 00000000000..d479d863bb4
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h
@@ -0,0 +1,122 @@
+/************************************************************************************
+ * arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include "stm32_gpio.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Alternate Pin Functions.
+ *
+ * Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
+ * Drivers, however, will use the pin selection without the numeric suffix.
+ * Additional definitions are required in the board.h file.  For example, if
+ * CAN1_RX connects vis PA11 on some board, then the following definitions should
+ * appear in the board.h header file for that board:
+ *
+ * #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
+ *
+ * The driver will then automatically configure PB6 as the I2C1 SCL pin.
+ */
+
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as frequency,
+ * open-drain/push-pull, and pull-up/down!  Just the basics are defined for most
+ * pins in this file.
+ */
+
+/* TODO: ADC */
+
+/* TODO: DAC */
+
+/* TODO: I2C */
+
+/* TODO: Clocking */
+
+/* TODO: RTC */
+
+/* TODO: SPI */
+
+/* TODO: Timers */
+
+/* TODO: USART */
+
+#define GPIO_USART1_CTS_1    (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN11)
+#define GPIO_USART1_CTS_2    (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN4)
+#define GPIO_USART1_RTS_1    (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN12)
+#define GPIO_USART1_RTS_2    (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN3)
+#define GPIO_USART1_RX_1     (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN10)
+#define GPIO_USART1_RX_2     (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7)
+#define GPIO_USART1_RX_3     (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN5)
+#define GPIO_USART1_TX_1     (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN9)
+#define GPIO_USART1_TX_2     (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_USART1_TX_3     (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN4)
+
+#define GPIO_USART2_CTS_1   (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_USART2_CTS_2   (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN3)
+#define GPIO_USART2_RTS_1   (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN1)
+#define GPIO_USART2_RTS_2   (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN4)
+#define GPIO_USART2_RX_1    (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_USART2_RX_2    (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN15)
+#define GPIO_USART2_RX_3    (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN6)
+#define GPIO_USART2_TX_1    (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN2)
+#define GPIO_USART2_TX_2    (GPIO_ALT | GPIO_PULLUP | GPIO_AF1 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN14)
+#define GPIO_USART2_TX_3    (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN6)
+
+/* TODO: USART3 */
+
+/* TODO: USART4 */
+
+/* TODO: LPTIM */
+
+/* TODO: LPUART */
+
+/* TODO: COMP */
+
+/* TODO: UCPD */
+
+/* TODO: CEC */
+
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h
new file mode 100644
index 00000000000..ad8acfce5a1
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h
@@ -0,0 +1,186 @@
+/************************************************************************************
+ * arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_PWR_CR1_OFFSET   0x0000  /* Power control register 1 */
+#define STM32_PWR_CR2_OFFSET   0x0004  /* Power control register 2 */
+#define STM32_PWR_CR3_OFFSET   0x0008  /* Power control register 3 */
+#define STM32_PWR_CR4_OFFSET   0x000C  /* Power control register 4 */
+#define STM32_PWR_SR1_OFFSET   0x0010  /* Power status register 1 */
+#define STM32_PWR_SR2_OFFSET   0x0014  /* Power status register 2 */
+#define STM32_PWR_SCR_OFFSET   0x0018  /* Power status clear register */
+#define STM32_PWR_PUCRA_OFFSET 0x0020  /* Power Port A pull-up control register */
+#define STM32_PWR_PDCRA_OFFSET 0x0024  /* Power Port A pull-down control register */
+#define STM32_PWR_PUCRB_OFFSET 0x0028  /* Power Port B pull-up control register */
+#define STM32_PWR_PDCRB_OFFSET 0x002C  /* Power Port B pull-down control register */
+#define STM32_PWR_PUCRC_OFFSET 0x0030  /* Power Port C pull-up control register */
+#define STM32_PWR_PDCRC_OFFSET 0x0034  /* Power Port C pull-down control register */
+#define STM32_PWR_PUCRD_OFFSET 0x0038  /* Power Port D pull-up control register */
+#define STM32_PWR_PDCRD_OFFSET 0x003C  /* Power Port D pull-down control register */
+#define STM32_PWR_PUCRF_OFFSET 0x0048  /* Power Port F pull-up control register */
+#define STM32_PWR_PDCRF_OFFSET 0x004C  /* Power Port F pull-down control register */
+#define STM32_PWR_PUCRG_OFFSET 0x0050  /* Power Port G pull-up control register */
+#define STM32_PWR_PDCRG_OFFSET 0x0054  /* Power Port G pull-down control register */
+#define STM32_PWR_PUCRH_OFFSET 0x0058  /* Power Port H pull-up control register */
+#define STM32_PWR_PDCRH_OFFSET 0x005C  /* Power Port H pull-down control register */
+#define STM32_PWR_PUCRI_OFFSET 0x0060  /* Power Port I pull-up control register */
+#define STM32_PWR_PDCRI_OFFSET 0x0064  /* Power Port I pull-down control register */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_PWR_CR1          (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET)
+#define STM32_PWR_CR2          (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET)
+#define STM32_PWR_CR3          (STM32_PWR_BASE+STM32_PWR_CR3_OFFSET)
+#define STM32_PWR_CR4          (STM32_PWR_BASE+STM32_PWR_CR4_OFFSET)
+#define STM32_PWR_SR1          (STM32_PWR_BASE+STM32_PWR_SR1_OFFSET)
+#define STM32_PWR_SR2          (STM32_PWR_BASE+STM32_PWR_SR2_OFFSET)
+#define STM32_PWR_SCR          (STM32_PWR_BASE+STM32_PWR_SCR_OFFSET)
+#define STM32_PWR_PUCRA        (STM32_PWR_BASE+STM32_PWR_PUCRA_OFFSET)
+#define STM32_PWR_PDCRA        (STM32_PWR_BASE+STM32_PWR_PDCRA_OFFSET)
+#define STM32_PWR_PUCRB        (STM32_PWR_BASE+STM32_PWR_PUCRB_OFFSET)
+#define STM32_PWR_PDCRB        (STM32_PWR_BASE+STM32_PWR_PDCRB_OFFSET)
+#define STM32_PWR_PUCRC        (STM32_PWR_BASE+STM32_PWR_PUCRC_OFFSET)
+#define STM32_PWR_PDCRC        (STM32_PWR_BASE+STM32_PWR_PDCRC_OFFSET)
+#define STM32_PWR_PUCRD        (STM32_PWR_BASE+STM32_PWR_PUCRD_OFFSET)
+#define STM32_PWR_PDCRD        (STM32_PWR_BASE+STM32_PWR_PDCRD_OFFSET)
+#define STM32_PWR_PUCRE        (STM32_PWR_BASE+STM32_PWR_PUCRE_OFFSET)
+#define STM32_PWR_PDCRE        (STM32_PWR_BASE+STM32_PWR_PDCRE_OFFSET)
+#define STM32_PWR_PUCRF        (STM32_PWR_BASE+STM32_PWR_PUCRF_OFFSET)
+#define STM32_PWR_PDCRF        (STM32_PWR_BASE+STM32_PWR_PDCRF_OFFSET)
+#define STM32_PWR_PUCRG        (STM32_PWR_BASE+STM32_PWR_PUCRG_OFFSET)
+#define STM32_PWR_PDCRG        (STM32_PWR_BASE+STM32_PWR_PDCRG_OFFSET)
+#define STM32_PWR_PUCRH        (STM32_PWR_BASE+STM32_PWR_PUCRH_OFFSET)
+#define STM32_PWR_PDCRH        (STM32_PWR_BASE+STM32_PWR_PDCRH_OFFSET)
+#define STM32_PWR_PUCRI        (STM32_PWR_BASE+STM32_PWR_PUCRI_OFFSET)
+#define STM32_PWR_PDCRI        (STM32_PWR_BASE+STM32_PWR_PDCRI_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Power control register 1 */
+
+#define PWR_CR1_LPMS_SHIFT       (0)      /* Bits 0-2: Low-power mode selection */
+#define PWR_CR1_LPMS_MASK        (7 << PWR_CR1_LPMS_SHIFT)
+#  define PWR_CR1_LPMS_STOP1MR   (0 << PWR_CR1_LPMS_SHIFT) /* Stop 1 mode with main regulator (MR) */
+#  define PWR_CR1_LPMS_STOP1LPR  (1 << PWR_CR1_LPMS_SHIFT) /* Stop 1 mode with low-power regulator (LPR) */
+#  define PWR_CR1_LPMS_STOP2     (2 << PWR_CR1_LPMS_SHIFT) /* 010: Stop 2 mode */
+#  define PWR_CR1_LPMS_STANDBY   (3 << PWR_CR1_LPMS_SHIFT) /* 011: Standby mode */
+#  define PWR_CR1_LPMS_SHUTDOWN  (4 << PWR_CR1_LPMS_SHIFT) /* 1xx: Shutdown mode */
+#define PWR_CR1_FPDSTOP          (1 << 3) /* Bit 3: Flash memory powered down during Stop mode */
+#define PWR_CR1_FPDLPRUN         (1 << 4) /* Bit 4: Flash memory powered down during Low-power run mode */
+#define PWR_CR1_FPDLPSLP         (1 << 5) /* Bit 5: Flash memory powered down during Low-power sleep mode */
+#define PWR_CR1_DBP              (1 << 8) /* Bit 8: Disable Backup domain write protection */
+#define PWR_CR1_VOS_SHIFT        (9)      /* Bits 9-10: Voltage scaling range selection */
+#define PWR_CR1_VOS_MASK         (3 << PWR_CR1_VOS_SHIFT)
+#  define PWR_CR1_VOS_RANGE1     (1 << PWR_CR1_VOS_SHIFT) /* 01: Range 1 */
+#  define PWR_CR1_VOS_RANGE2     (2 << PWR_CR1_VOS_SHIFT) /* 10: Range 2 */
+#define PWR_CR1_LPR              (1 << 14) /* Bit 14: Low-power run */
+
+/* Power control register 2 */
+
+#define PWR_CR2_PVDE             (1 << 0) /* Bit 0: Power voltage detector enable */
+#define PWR_CR2_PVDFT_SHIFT      (1)      /* Bits 1-3: Power voltage detector falling threshold selection */
+#define PWR_CR2_PVDFT_MASK       (7 << PWR_CR2_PLS_SHIFT)
+#define PWR_CR2_PVDRT_SHIFT      (4)      /* Bits 4-6: Power voltage detector rising threshold selection */
+#define PWR_CR2_PVDRT_MASK       (7 << PWR_CR2_PLS_SHIFT)
+
+/* Power control register 3 */
+
+#define PWR_CR3_EWUP1            (1 << 0)  /* Bit 0: Enable Wakeup pin WKUP1 */
+#define PWR_CR3_EWUP2            (1 << 1)  /* Bit 1: Enable Wakeup pin WKUP2 */
+#define PWR_CR3_EWUP3            (1 << 2)  /* Bit 2: Enable Wakeup pin WKUP3 */
+#define PWR_CR3_EWUP4            (1 << 3)  /* Bit 3: Enable Wakeup pin WKUP4 */
+#define PWR_CR3_EWUP5            (1 << 4)  /* Bit 4: Enable Wakeup pin WKUP5 */
+#define PWR_CR3_EWUP6            (1 << 5)  /* Bit 5: Enable Wakeup pin WKUP6 */
+#define PWR_CR3_RRS              (1 << 8)  /* Bit 8: SRAM2 retention in Standby mode */
+#define PWR_CR3_ULPEN            (1 << 9)  /* Bit 9: Ultra-low-power enable */
+#define PWR_CR3_APC              (1 << 10) /* Bit 10: Apply pull-up and pull-down configuration */
+#define PWR_CR3_EIWUL            (1 << 15) /* Bit 15: Enable internal wakeup line */
+
+/* Power control register 4 */
+
+#define PWR_CR4_WP1              (1 << 0) /* Bit 0: Wakeup pin WKUP1 polarity */
+#define PWR_CR4_WP2              (1 << 1) /* Bit 1: Wakeup pin WKUP2 polarity */
+#define PWR_CR4_WP3              (1 << 2) /* Bit 2: Wakeup pin WKUP3 polarity */
+#define PWR_CR4_WP4              (1 << 3) /* Bit 3: Wakeup pin WKUP4 polarity */
+#define PWR_CR4_WP5              (1 << 4) /* Bit 4: Wakeup pin WKUP5 polarity */
+#define PWR_CR4_VBE              (1 << 8) /* Bit 8: Vbat battery charging enable */
+#define PWR_CR4_VBRS             (1 << 9) /* Bit 9: Vbat battery charging resistor selection */
+#  define PWR_CR4_VBRS_5k        0            /* 0: 5k  resistor */
+#  define PWR_CR4_VBRS_1k5       PWR_CR4_VBRS /* 1: 1k5 resistor */
+
+/* Power status register 1 */
+
+#define PWR_SR1_WUF1             (1 << 0)  /* Bit 0: Wakeup flag 1 */
+#define PWR_SR1_WUF2             (1 << 1)  /* Bit 1: Wakeup flag 2 */
+#define PWR_SR1_WUF3             (1 << 2)  /* Bit 2: Wakeup flag 3 */
+#define PWR_SR1_WUF4             (1 << 3)  /* Bit 3: Wakeup flag 4 */
+#define PWR_SR1_WUF5             (1 << 4)  /* Bit 4: Wakeup flag 5 */
+#define PWR_SR1_WUF6             (1 << 5)  /* Bit 5: Wakeup flag 6 */
+#define PWR_SR1_SBF              (1 << 8)  /* Bit 8: Standby flag */
+#define PWR_SR1_WUFI             (1 << 15) /* Bit 15: Wakeup internal flag */
+
+/* Power status register 2 */
+
+#define PWR_SR2_FLASHRDY         (1 << 7)  /* Bit 7: Flash ready flag */
+#define PWR_SR2_REGLPS           (1 << 8)  /* Bit 8: Low power regulator started */
+#define PWR_SR2_REGLPF           (1 << 9)  /* Bit 9: Low power regulator flag */
+#define PWR_SR2_VOSF             (1 << 10) /* Bit 10: Voltage scaling flag */
+#define PWR_SR2_PVDO             (1 << 11) /* Bit 11: Power voltage detector output */
+
+/* Power status clear register */
+
+#define PWR_SCR_CWUF1            (1 << 0) /* Bit 0: Clear wakeup flag 1 */
+#define PWR_SCR_CWUF2            (1 << 1) /* Bit 1: Clear wakeup flag 2 */
+#define PWR_SCR_CWUF3            (1 << 2) /* Bit 2: Clear wakeup flag 3 */
+#define PWR_SCR_CWUF4            (1 << 3) /* Bit 3: Clear wakeup flag 4 */
+#define PWR_SCR_CWUF5            (1 << 4) /* Bit 4: Clear wakeup flag 5 */
+#define PWR_SCR_CSBF             (1 << 8) /* Bit 8: Clear standby flag */
+
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h
new file mode 100644
index 00000000000..56c9efd95bd
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h
@@ -0,0 +1,368 @@
+/************************************************************************************
+ * arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_RCC_CR_OFFSET             0x0000  /* Clock control register */
+#define STM32_RCC_ICSCR_OFFSET          0x0004  /* Internal clock sources calibration register */
+#define STM32_RCC_CFGR_OFFSET           0x0008  /* Clock configuration register */
+#define STM32_RCC_PLLCFG_OFFSET         0x000C  /* PLL clock configuration register */
+#define STM32_RCC_CIER_OFFSET           0x0018  /* Clock Source Interrupt enable register */
+#define STM32_RCC_CIFR_OFFSET           0x001c  /* Clock Source Interrupt Flag register */
+#define STM32_RCC_CICR_OFFSET           0x0020  /* Clock Source Interrupt Clear register */
+#define STM32_RCC_IOPRSTR_OFFSET        0x0024  /* GPIO reset register */
+#define STM32_RCC_AHBRSTR_OFFSET        0x0028  /* AHB peripheral reset register */
+#define STM32_RCC_APB1RSTR_OFFSET       0x002C  /* APB1 Peripheral reset register */
+#define STM32_RCC_APB2RSTR_OFFSET       0x0030  /* APB2 Peripheral reset register */
+#define STM32_RCC_IOPENR_OFFSET         0x0034  /* GPIO clock enable register */
+#define STM32_RCC_AHBENR_OFFSET         0x0038  /* AHB Peripheral Clock enable register */
+#define STM32_RCC_APB1ENR_OFFSET        0x003C  /* APB1 Peripheral Clock enable register */
+#define STM32_RCC_APB2ENR_OFFSET        0x0040  /* APB2 Peripheral Clock enable register */
+#define STM32_RCC_IOPSMEN_OFFSET        0x0044  /* GPIO clock enable in Sleep mode register */
+#define STM32_RCC_AHBSMENR_OFFSET       0x0048  /* AHB peripheral clock enable in Sleep mode register */
+#define STM32_RCC_APB1SMENR_OFFSET      0x004C  /* APB1 peripheral clock enable in Sleep mode register */
+#define STM32_RCC_APB2SMENR_OFFSET      0x0050  /* APB2 peripheral clock enable in Sleep mode register */
+#define STM32_RCC_CCIPR_OFFSET          0x0054  /* Clock configuration register */
+#define STM32_RCC_BDCR_OFFSET           0x005c  /* RTC domain control register */
+#define STM32_RCC_CSR_OFFSET            0x0060  /* Control/status register */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_RCC_CR                (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
+#define STM32_RCC_ICSCR             (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET)
+#define STM32_RCC_CFGR              (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
+#define STM32_RCC_PLLCFG            (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET)
+#define STM32_RCC_CIER              (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET)
+#define STM32_RCC_CIFR              (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET)
+#define STM32_RCC_CICR              (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET)
+#define STM32_RCC_IOPRSTR           (STM32_RCC_BASE+STM32_RCC_IOPRSTR_OFFSET)
+#define STM32_RCC_AHBRSTR           (STM32_RCC_BASE+STM32_RCC_AHBRSTR_OFFSET)
+#define STM32_RCC_APB1RSTR          (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET)
+#define STM32_RCC_APB2RSTR          (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
+#define STM32_RCC_IOPENR            (STM32_RCC_BASE+STM32_RCC_IOPENR_OFFSET)
+#define STM32_RCC_AHBENR            (STM32_RCC_BASE+STM32_RCC_AHBENR_OFFSET)
+#define STM32_RCC_APB1ENR           (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
+#define STM32_RCC_APB2ENR           (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
+#define STM32_RCC_IOPSMEN           (STM32_RCC_BASE+STM32_RCC_IOPSMEN_OFFSET)
+#define STM32_RCC_AHBSMENR          (STM32_RCC_BASE+STM32_RCC_AHBSMENR_OFFSET)
+#define STM32_RCC_APB1SMENR         (STM32_RCC_BASE+STM32_RCC_APB1SMENR_OFFSET)
+#define STM32_RCC_APB2SMENR         (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET)
+#define STM32_RCC_CCIPR             (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET)
+#define STM32_RCC_BDCR              (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
+#define STM32_RCC_CSR               (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Clock control register */
+
+                                              /* Bits 0-7: Reserved */
+#define RCC_CR_HSION                (1 << 8)  /* Bit 8: Internal high speed clock enable */
+#define RCC_CR_HSIKERON             (1 << 9)  /* Bit 9: Internal high speed clock enable for some IP kernels */
+#define RCC_CR_HSIRDY               (1 << 10) /* Bit 10: Internal high speed clock ready flag */
+#define RCC_CR_HSIDIV_SHIFT         (11)      /* Bit 11: Internal high speed clock divider */
+#define RCC_CR_HSIDIV_MASK          (7 << RCC_CR_HSIDIV_SHIFT)
+                                              /* Bits 14-15: Reserved */
+#define RCC_CR_HSEON                (1 << 16) /* Bit 16: External high speed clock enable */
+#define RCC_CR_HSERDY               (1 << 17) /* Bit 17: External high speed clock ready flag */
+#define RCC_CR_HSEBYP               (1 << 18) /* Bit 18: External high speed clock bypass */
+
+#define RCC_CR_CSSON                (1 << 19) /* Bit 19: Clock security system enable */
+                                              /* Bits 20-23: Reserved */
+#define RCC_CR_PLLON                (1 << 24) /* Bit 24: PLL enable */
+#define RCC_CR_PLLRDY               (1 << 25) /* Bit 25: PLL clock ready flag */
+                                              /* Bits 26-27: Reserved */
+
+#define RCC_CR_RESET                 0x00000500
+
+/* Internal clock sources calibration register */
+
+#define RCC_ICSCR_HSICAL_SHIFT      (0)       /* Bits 0-7:  Internal high speed clock calibration */
+#define RCC_ICSCR_HSICAL_MASK       (0xff << RCC_ICSCR_HSICAL_SHIFT)
+#define RCC_ICSCR_HSITRIM_SHIFT     (8)       /* Bits 8-14:  High speed internal clock trimming */
+#define RCC_ICSCR_HSITRIM_MASK      (0x7f << RCC_ICSCR_HSITRIM_SHIFT)
+
+/* Clock configuration register */
+
+#define RCC_CFGR_SW_SHIFT           (0)       /* Bits 0-2: System clock Switch */
+#define RCC_CFGR_SW_MASK            (7 << RCC_CFGR_SW_SHIFT)
+#  define RCC_CFGR_SW_HSI           (0 << RCC_CFGR_SW_SHIFT) /* 000: HSI selected as system clock */
+#  define RCC_CFGR_SW_HSE           (1 << RCC_CFGR_SW_SHIFT) /* 001: HSE selected as system clock */
+#  define RCC_CFGR_SW_PLL           (2 << RCC_CFGR_SW_SHIFT) /* 010: PLL selected as system clock */
+#  define RCC_CFGR_SW_LSI           (3 << RCC_CFGR_SW_SHIFT) /* 011: LSI selected as system clock */
+#  define RCC_CFGR_SW_LSE           (4 << RCC_CFGR_SW_SHIFT) /* 100: LSE selected as system clock */
+#define RCC_CFGR_SWS_SHIFT          (3)       /* Bits 3-5: System Clock Switch Status */
+#define RCC_CFGR_SWS_MASK           (3 << RCC_CFGR_SWS_SHIFT)
+#  define RCC_CFGR_SWS_HSI          (0 << RCC_CFGR_SWS_SHIFT) /* 000: HSI oscillator used as system clock */
+#  define RCC_CFGR_SWS_HSE          (1 << RCC_CFGR_SWS_SHIFT) /* 001: HSE oscillator used as system clock */
+#  define RCC_CFGR_SWS_PLL          (2 << RCC_CFGR_SWS_SHIFT) /* 010: PLL oscillator used as system clock */
+#  define RCC_CFGR_SWS_LSI          (3 << RCC_CFGR_SWS_SHIFT) /* 011: LSI used as system clock */
+#  define RCC_CFGR_SWS_LSE          (4 << RCC_CFGR_SWS_SHIFT) /* 100: LSE used as system clock */
+#define RCC_CFGR_HPRE_SHIFT         (8)       /* Bits 8-11: AHB prescaler */
+#define RCC_CFGR_HPRE_MASK          (0x0f << RCC_CFGR_HPRE_SHIFT)
+#  define RCC_CFGR_HPRE_SYSCLK      (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */
+#  define RCC_CFGR_HPRE_SYSCLKd2    (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
+#  define RCC_CFGR_HPRE_SYSCLKd4    (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
+#  define RCC_CFGR_HPRE_SYSCLKd8    (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
+#  define RCC_CFGR_HPRE_SYSCLKd16   (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
+#  define RCC_CFGR_HPRE_SYSCLKd64   (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
+#  define RCC_CFGR_HPRE_SYSCLKd128  (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
+#  define RCC_CFGR_HPRE_SYSCLKd256  (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
+#  define RCC_CFGR_HPRE_SYSCLKd512  (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
+#define RCC_CFGR_PPRE1_SHIFT        (12)       /* Bits 12-14: APB Low speed prescaler (APB1) */
+#define RCC_CFGR_PPRE1_MASK         (7 << RCC_CFGR_PPRE1_SHIFT)
+#  define RCC_CFGR_PPRE1_HCLK       (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */
+#  define RCC_CFGR_PPRE1_HCLKd2     (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */
+#  define RCC_CFGR_PPRE1_HCLKd4     (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */
+#  define RCC_CFGR_PPRE1_HCLKd8     (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */
+#  define RCC_CFGR_PPRE1_HCLKd16    (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */
+                                              /* Bits 15-23: Reserved */
+#define RCC_CFGR_MCOSEL_SHIFT       (24)      /* Bits 24-26: Microcontroller clock output selection */
+#define RCC_CFGR_MCOSEL_MASK        (7 << RCC_CFGR_MCOSEL_SHIFT)
+                                              /* Bit 27: Reserved */
+#define RCC_CFGR_MCOPRE_SHIFT       (28)      /* Bits 28-30: Microcontroller clock output selection */
+#define RCC_CFGR_MCOPRE_MASK        (7 << RCC_CFGR_MCOPRE_SHIFT)
+
+#define RCC_CFGR_RESET              0x00000000
+
+/* PLL clock configuration register */
+
+#define RCC_PLLCFG_PLLSRC_SHIFT    (0)      /* Bits 0-1: PLL entry clock source */
+#define RCC_PLLCFG_PLLSRC_MASK     (3 << RCC_PLLCFG_PLLSRC_SHIFT)
+#  define RCC_PLLCFG_PLLSRC_NOCLK  (0 << RCC_PLLCFG_PLLSRC_SHIFT)
+#  define RCC_PLLCFG_PLLSRC_HSI    (2 << RCC_PLLCFG_PLLSRC_SHIFT)
+#  define RCC_PLLCFG_PLLSRC_HSE    (3 << RCC_PLLCFG_PLLSRC_SHIFT)
+                                            /* Bits 2-3: Reserved */
+#define RCC_PLLCFG_PLLM_SHIFT      (4)      /* Bits 4-6: Division factor M of the PLL input clock divider */
+#define RCC_PLLCFG_PLLM_MASK       (7 << RCC_PLLCFG_PLLM_SHIFT)
+#define RCC_PLLCFG_PLLM(n)         ((n-1) << RCC_PLLCFG_PLLM_SHIFT)
+                                             /* Bit 7: Reserved */
+#define RCC_PLLCFG_PLLN_SHIFT      (8)       /* Bits 8-14: PLL frequency multiplication factor N */
+#define RCC_PLLCFG_PLLN_MASK       (0x7f << RCC_PLLCFG_PLLN_SHIFT)
+#define RCC_PLLCFG_PLLN(n)         ((n) << RCC_PLLCFG_PLLN_SHIFT)
+                                             /* Bit 15: Reserved */
+#define RCC_PLLCFG_PLLPEN          (1 << 16) /* Bit 16: PLLPCLK clock output enable */
+#define RCC_PLLCFG_PLLP_SHIFT      (17)      /* Bits 17-21: PLL VCO division factor P for PLLPCLK clock output */
+#define RCC_PLLCFG_PLLP_MASK       (0x1f << RCC_PLLCFG_PLLP_SHIFT)
+#define RCC_PLLCFG_PLLP(n)         ((n-1) << RCC_PLLCFG_PLLP_SHIFT) /* n=2,...,32 */
+                                             /* Bits 22-23: Reserved */
+#define RCC_PLLCFG_PLLQEN          (1 << 24) /* Bit 24: PLLQCLK clock output enable */
+#define RCC_PLLCFG_PLLQ_SHIFT      (25)      /* Bits 25-27: Division factor Q of the PLL input clock divider */
+#define RCC_PLLCFG_PLLQ_MASK       (7 << RCC_PLLCFG_PLLQ_SHIFT)
+#define RCC_PLLCFG_PLLQ(n)         ((n-1) << RCC_PLLCFG_PLLQ_SHIFT)
+#define RCC_PLLCFG_PLLREN          (1 << 28) /* Bit 28: PLLRCLK clock output enable */
+#define RCC_PLLCFG_PLLR_SHIFT      (29)      /* Bits 29-31: Division factor R of the PLL input clock divider */
+#define RCC_PLLCFG_PLLR_MASK       (7 << RCC_PLLCFG_PLLR_SHIFT)
+#define RCC_PLLCFG_PLLR(n)         ((n-1) << RCC_PLLCFG_PLLR_SHIFT)
+
+#define RCC_PLLCFGR_RESET           0x00001000
+
+/* TODO: Clock Source Interrupt enable register */
+
+/* TODO: Clock Source Interrupt Flag register */
+
+/* TODO: Clock Source Interrupt Clear register */
+
+/* GPIO reset register */
+
+#define RCC_IOPRSTR_IOPARST         (1 << 0)  /* Bit 0: IO port A reset */
+#define RCC_IOPRSTR_IOPBRST         (1 << 1)  /* Bit 1: IO port B reset */
+#define RCC_IOPRSTR_IOPCRST         (1 << 2)  /* Bit 2: IO port C reset */
+#define RCC_IOPRSTR_IOPDRST         (1 << 3)  /* Bit 3: IO port D reset */
+                                              /* Bits 4: Reserved */
+#define RCC_IOPRSTR_IOPFRST         (1 << 5)  /* Bit 5: IO port F reset */
+
+/* AHB peripheral reset register */
+
+#define RCC_AHBRSTR_DMA1RST         (1 << 0)  /* Bit 0: DMA 1 reset */
+                                              /* Bits 1-7: Reserved */
+#define RCC_AHBRSTR_MIFRST          (1 << 8)  /* Bit 8: Memory interface reset */
+                                              /* Bits 9-11: Reserved */
+#define RCC_AHBRSTR_CRCRST          (1 << 12) /* Bit 12: Memory interface reset */
+                                              /* Bits 13-15: Reserved */
+#define RCC_AHBRSTR_AESRST          (1 << 16) /* Bit 16: Touch sensing reset */
+                                              /* Bit 17: Reserved */
+#define RCC_AHBRSTR_RNGRST          (1 << 18) /* Bit 18: Random number generator module reset */
+                                              /* Bits 19-31: Reserved */
+
+/* APB1 Peripheral reset register */
+
+#define RCC_APB1RSTR_TIM2RST        (1 << 0)  /* Bit 0:  Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST        (1 << 1)  /* Bit 1:  Timer 3 reset */
+                                              /* Bits 2-3: Reserved */
+#define RCC_APB1RSTR_TIM6RST        (1 << 4)  /* Bit 4:  Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST        (1 << 5)  /* Bit 5:  Timer 7 reset */
+                                              /* Bits 6-13: Reserved */
+#define RCC_APB1RSTR_SPI2RST        (1 << 14) /* Bit 14: SPI 2 reset */
+                                              /* Bits 15-16: Reserved */
+#define RCC_APB1RSTR_USART2RST      (1 << 17) /* Bit 17: USART 2 reset */
+#define RCC_APB1RSTR_USART3RST      (1 << 18) /* Bit 18: USART 3 reset */
+#define RCC_APB1RSTR_USART4RST      (1 << 19) /* Bit 19: USART 4 reset */
+#define RCC_APB1RSTR_LPUSART1RST    (1 << 20) /* Bit 20: Low-power USART 1 reset */
+#define RCC_APB1RSTR_I2C1RST        (1 << 21) /* Bit 21: I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST        (1 << 22) /* Bit 22: I2C 2 reset */
+                                              /* Bit 23: Reserved */
+#define RCC_APB1RSTR_CECRST         (1 << 24) /* Bit 24: HDMI CEC reset */
+#define RCC_APB1RSTR_UCPD1RST       (1 << 25) /* Bit 25: UCPD1 reset */
+#define RCC_APB1RSTR_UCPD2RST       (1 << 26) /* Bit 26: UCPD2 reset */
+#define RCC_APB1RSTR_DBGRST         (1 << 27) /* Bit 27: DBG reset */
+#define RCC_APB1RSTR_PWRRST         (1 << 28) /* Bit 28: PWR reset */
+#define RCC_APB1RSTR_DAC1RST        (1 << 29) /* Bit 29: DAC1 reset */
+#define RCC_APB1RSTR_LPTIM2RST      (1 << 30) /* Bit 30: LPTIM2 reset */
+#define RCC_APB1RSTR_LPTIM1RST      (1 << 31) /* Bit 31: LPTIM1 reset */
+
+/* APB2 Peripheral reset register */
+
+#define RCC_APB2RSTR_SYSCFGRST      (1 << 0)  /* Bit 0:  System configuration controller reset */
+                                              /* Bits 1-10: Reserved */
+#define RCC_APB2RSTR_TIM1RST        (1 << 11) /* Bit 11: TIM1 timer reset */
+#define RCC_APB2RSTR_SPI1RST        (1 << 12) /* Bit 12: SPI 1 reset */
+                                              /* Bit 13: Reserved */
+#define RCC_APB2RSTR_USART1RST      (1 << 14) /* Bit 14: USART1 reset */
+#define RCC_APB2RSTR_TIM14RST       (1 << 15) /* Bit 15: TIM14 timer reset */
+#define RCC_APB2RSTR_TIM15RST       (1 << 16) /* Bit 16: TIM15 timer reset */
+#define RCC_APB2RSTR_TIM16RST       (1 << 17) /* Bit 17: TIM16 timer reset */
+#define RCC_APB2RSTR_TIM17RST       (1 << 18) /* Bit 18: TIM17 timer reset */
+                                              /* Bit 19: Reserved */
+#define RCC_APB2RSTR_ADC1RST        (1 << 20) /* Bit 20: ADC1 timer reset */
+
+/* GPIO clock enable register */
+
+#define RCC_IOPENR_IOPAEN           (1 << 0)  /* Bit 0: IO port A enable */
+#define RCC_IOPENR_IOPBEN           (1 << 1)  /* Bit 1: IO port B enable */
+#define RCC_IOPENR_IOPCEN           (1 << 2)  /* Bit 2: IO port C enable */
+#define RCC_IOPENR_IOPDEN           (1 << 3)  /* Bit 3: IO port D enable */
+                                              /* Bits 4: Reserved */
+#define RCC_IOPENR_IOPFEN           (1 << 5)  /* Bit 5: IO port F enable */
+
+/* AHB Peripheral Clock enable register */
+
+#define RCC_AHBENR_DMA1EN           (1 << 0)  /* Bit 0: DMA 1 enable */
+                                              /* Bits 1-7: Reserved */
+#define RCC_AHBENR_MIFEN            (1 << 8)  /* Bit 8: Memory interface enable */
+                                              /* Bits 9-11: Reserved */
+#define RCC_AHBENR_CRCEN            (1 << 12) /* Bit 12: Memory interface enable */
+                                              /* Bits 13-15: Reserved */
+#define RCC_AHBENR_AESEN            (1 << 16) /* Bit 16: Touch sensing enable */
+                                              /* Bit 17: Reserved */
+#define RCC_AHBENR_RNGEN            (1 << 18) /* Bit 18: Random number generator module enable */
+                                              /* Bits 19-31: Reserved */
+
+/* APB1 Peripheral Clock enable register */
+
+#define RCC_APB1ENR_TIM2EN          (1 << 0)  /* Bit 0:  Timer 2 enable */
+#define RCC_APB1ENR_TIM3EN          (1 << 1)  /* Bit 1:  Timer 3 enable */
+                                              /* Bits 2-3: Reserved */
+#define RCC_APB1ENR_TIM6EN          (1 << 4)  /* Bit 4:  Timer 6 enable */
+#define RCC_APB1ENR_TIM7EN          (1 << 5)  /* Bit 5:  Timer 7 enable */
+                                              /* Bits 6-13: Reserved */
+#define RCC_APB1ENR_SPI2EN          (1 << 14) /* Bit 14: SPI 2 enable */
+                                              /* Bits 15-16: Reserved */
+#define RCC_APB1ENR_USART2EN        (1 << 17) /* Bit 17: USART 2 enable */
+#define RCC_APB1ENR_USART3EN        (1 << 18) /* Bit 18: USART 3 enable */
+#define RCC_APB1ENR_USART4EN        (1 << 19) /* Bit 19: USART 4 enable */
+#define RCC_APB1ENR_LPUSART1EN      (1 << 20) /* Bit 20: Low-power USART 1 enable */
+#define RCC_APB1ENR_I2C1EN          (1 << 21) /* Bit 21: I2C 1 enable */
+#define RCC_APB1ENR_I2C2EN          (1 << 22) /* Bit 22: I2C 2 enable */
+                                              /* Bit 23: Reserved */
+#define RCC_APB1ENR_CECEN           (1 << 24) /* Bit 24: HDMI CEC enable */
+#define RCC_APB1ENR_UCPD1EN         (1 << 25) /* Bit 25: UCPD1 enable */
+#define RCC_APB1ENR_UCPD2EN         (1 << 26) /* Bit 26: UCPD2 enable */
+#define RCC_APB1ENR_DBGEN           (1 << 27) /* Bit 27: DBG enable */
+#define RCC_APB1ENR_PWREN           (1 << 28) /* Bit 28: PWR enable */
+#define RCC_APB1ENR_DAC1EN          (1 << 29) /* Bit 29: DAC1 enable */
+#define RCC_APB1ENR_LPTIM2EN        (1 << 30) /* Bit 30: LPTIM2 enable */
+#define RCC_APB1ENR_LPTIM1EN        (1 << 31) /* Bit 31: LPTIM1 enable */
+
+/* APB2 Peripheral Clock enable register */
+
+#define RCC_APB2ENR_SYSCFGEN        (1 << 0)  /* Bit 0:  System configuration controller enable */
+                                              /* Bits 1-10: Reserved */
+#define RCC_APB2ENR_TIM1EN          (1 << 11) /* Bit 11: TIM1 timer enable */
+#define RCC_APB2ENR_SPI1EN          (1 << 12) /* Bit 12: SPI 1 enable */
+                                              /* Bit 13: Reserved */
+#define RCC_APB2ENR_USART1EN        (1 << 14) /* Bit 14: USART1 enable */
+#define RCC_APB2ENR_TIM14EN         (1 << 15) /* Bit 15: TIM14 timer enable */
+#define RCC_APB2ENR_TIM15EN         (1 << 16) /* Bit 16: TIM15 timer enable */
+#define RCC_APB2ENR_TIM16EN         (1 << 17) /* Bit 17: TIM16 timer enable */
+#define RCC_APB2ENR_TIM17EN         (1 << 18) /* Bit 18: TIM17 timer enable */
+                                              /* Bit 19: Reserved */
+#define RCC_APB2ENR_ADC1EN          (1 << 20) /* Bit 20: ADC1 timer enable */
+
+/* GPIO clock enable in Sleep mode register */
+
+/* AHB peripheral clock enable in Sleep mode register */
+
+#define RCC_AHBSMENR_DMA1SMEN       (1 << 0)  /* Bit 0: DMA 1 enable in Sleep mode */
+                                              /* Bits 1-7: Reserved */
+#define RCC_AHBSMENR_MIFSMEN        (1 << 8)  /* Bit 8: Memory interface enable in Sleep mode */
+                                              /* Bits 9-11: Reserved */
+#define RCC_AHBSMENR_CRCSMEN        (1 << 12) /* Bit 12: Memory interface enable in Sleep mode */
+                                              /* Bits 13-15: Reserved */
+#define RCC_AHBSMENR_AESSMEN        (1 << 16) /* Bit 16: Touch sensing enable in Sleep mode */
+                                              /* Bit 17: Reserved */
+#define RCC_AHBSMENR_RNGSMEN        (1 << 18) /* Bit 18: Random number generator module enable in Sleep mode */
+                                              /* Bits 19-31: Reserved */
+
+/* TODO: APB1 peripheral clock enable in Sleep mode register */
+
+/* TODO: APB2 peripheral clock enable in Sleep mode register */
+
+/* TODO: Clock configuration register */
+
+/* TODO: RTC domain control register */
+
+/* Control/status register */
+
+#define RCC_CSR_LSION                   (1 << 0)  /* Bit 0: LSI enable */
+#define RCC_CSR_LSIRDY                  (1 << 1)  /* Bit 1: ready */
+                                                  /* Bits 2-22: Reserved */
+#define RCC_CSR_RMVF                    (1 << 23) /* Bit 23: Remove reset flag */
+                                                  /* Bit 24: Reserved */
+#define RCC_CSR_OBLRSTF                 (1 << 25) /* Bit 25: Options bytes loading reset flag */
+#define RCC_CSR_PINRSTF                 (1 << 26) /* Bit 26: PIN reset flag */
+#define RCC_CSR_PORRSTF                 (1 << 27) /* Bit 27: POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF                 (1 << 28) /* Bit 28: software reset flag */
+#define RCC_CSR_IWDGRSTF                (1 << 29) /* Bit 29: IWDG reset flag */
+#define RCC_CSR_WWDGRSTF                (1 << 30) /* Bit 30: WWDG reset flag */
+#define RCC_CSR_LPWRRSTF                (1 << 31) /* Bit 31: Low-power reset flag */
+
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H */
diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h
new file mode 100644
index 00000000000..a78bd7d3034
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h
@@ -0,0 +1,316 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include 
+#include "chip.h"
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Register Offsets *********************************************************************************/
+
+#define STM32_SYSCFG_CFGR1_OFFSET      0x0000 /* SYSCFG configuration register 1 */
+#define STM32_SYSCFG_CFGR2_OFFSET      0x0018 /* SYSCFG configuration register 2 */
+#define STM32_SYSCFG_ITLINE0_OFFSET    0x0080 /* SYSCFG interrupt line 0 status register */
+#define STM32_SYSCFG_ITLINE1_OFFSET    0x0084 /* SYSCFG interrupt line 1 status register */
+#define STM32_SYSCFG_ITLINE2_OFFSET    0x0088 /* SYSCFG interrupt line 2 status register */
+#define STM32_SYSCFG_ITLINE3_OFFSET    0x008c /* SYSCFG interrupt line 3 status register */
+#define STM32_SYSCFG_ITLINE4_OFFSET    0x0090 /* SYSCFG interrupt line 4 status register */
+#define STM32_SYSCFG_ITLINE5_OFFSET    0x0094 /* SYSCFG interrupt line 5 status register */
+#define STM32_SYSCFG_ITLINE6_OFFSET    0x0098 /* SYSCFG interrupt line 6 status register */
+#define STM32_SYSCFG_ITLINE7_OFFSET    0x009c /* SYSCFG interrupt line 7 status register */
+#define STM32_SYSCFG_ITLINE8_OFFSET    0x00a0 /* SYSCFG interrupt line 8 status register */
+#define STM32_SYSCFG_ITLINE9_OFFSET    0x00a4 /* SYSCFG interrupt line 9 status register */
+#define STM32_SYSCFG_ITLINE10_OFFSET   0x00a8 /* SYSCFG interrupt line 10 status register */
+#define STM32_SYSCFG_ITLINE11_OFFSET   0x00ac /* SYSCFG interrupt line 11 status register */
+#define STM32_SYSCFG_ITLINE12_OFFSET   0x00b0 /* SYSCFG interrupt line 12 status register */
+#define STM32_SYSCFG_ITLINE13_OFFSET   0x00b4 /* SYSCFG interrupt line 13 status register */
+#define STM32_SYSCFG_ITLINE14_OFFSET   0x00b8 /* SYSCFG interrupt line 14 status register */
+#define STM32_SYSCFG_ITLINE15_OFFSET   0x00bc /* SYSCFG interrupt line 15 status register */
+#define STM32_SYSCFG_ITLINE16_OFFSET   0x00c0 /* SYSCFG interrupt line 16 status register */
+#define STM32_SYSCFG_ITLINE17_OFFSET   0x00c4 /* SYSCFG interrupt line 17 status register */
+#define STM32_SYSCFG_ITLINE18_OFFSET   0x00c8 /* SYSCFG interrupt line 18 status register */
+#define STM32_SYSCFG_ITLINE19_OFFSET   0x00cc /* SYSCFG interrupt line 19 status register */
+#define STM32_SYSCFG_ITLINE20_OFFSET   0x00d0 /* SYSCFG interrupt line 20 status register */
+#define STM32_SYSCFG_ITLINE21_OFFSET   0x00d4 /* SYSCFG interrupt line 21 status register */
+#define STM32_SYSCFG_ITLINE22_OFFSET   0x00d8 /* SYSCFG interrupt line 22 status register */
+#define STM32_SYSCFG_ITLINE23_OFFSET   0x00dc /* SYSCFG interrupt line 23 status register */
+#define STM32_SYSCFG_ITLINE24_OFFSET   0x00e0 /* SYSCFG interrupt line 24 status register */
+#define STM32_SYSCFG_ITLINE25_OFFSET   0x00e4 /* SYSCFG interrupt line 25 status register */
+#define STM32_SYSCFG_ITLINE26_OFFSET   0x00e8 /* SYSCFG interrupt line 26 status register */
+#define STM32_SYSCFG_ITLINE27_OFFSET   0x00ec /* SYSCFG interrupt line 27 status register */
+#define STM32_SYSCFG_ITLINE28_OFFSET   0x00f0 /* SYSCFG interrupt line 28 status register */
+#define STM32_SYSCFG_ITLINE29_OFFSET   0x00f4 /* SYSCFG interrupt line 29 status register */
+#define STM32_SYSCFG_ITLINE30_OFFSET   0x00f8 /* SYSCFG interrupt line 30 status register */
+#define STM32_SYSCFG_ITLINE31_OFFSET   0x00fc /* SYSCFG interrupt line 31 status register */
+
+/* Register Addresses *******************************************************************************/
+
+#define STM32_SYSCFG_CFGR1             (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET)
+
+#define STM32_SYSCFG_ITLINE0           (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE0_OFFSET)
+#define STM32_SYSCFG_ITLINE1           (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE1_OFFSET)
+#define STM32_SYSCFG_ITLINE2           (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE2_OFFSET)
+#define STM32_SYSCFG_ITLINE3           (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE3_OFFSET)
+#define STM32_SYSCFG_ITLINE4           (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE4_OFFSET)
+#define STM32_SYSCFG_ITLINE5           (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE5_OFFSET)
+#define STM32_SYSCFG_ITLINE6           (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE6_OFFSET)
+#define STM32_SYSCFG_ITLINE7           (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE7_OFFSET)
+#define STM32_SYSCFG_ITLINE8           (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE8_OFFSET)
+#define STM32_SYSCFG_ITLINE9           (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE9_OFFSET)
+#define STM32_SYSCFG_ITLINE10          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE10_OFFSET)
+#define STM32_SYSCFG_ITLINE11          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE11_OFFSET)
+#define STM32_SYSCFG_ITLINE12          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE12_OFFSET)
+#define STM32_SYSCFG_ITLINE13          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE13_OFFSET)
+#define STM32_SYSCFG_ITLINE14          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE14_OFFSET)
+#define STM32_SYSCFG_ITLINE15          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE15_OFFSET)
+#define STM32_SYSCFG_ITLINE16          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE16_OFFSET)
+#define STM32_SYSCFG_ITLINE17          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE17_OFFSET)
+#define STM32_SYSCFG_ITLINE18          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE18_OFFSET)
+#define STM32_SYSCFG_ITLINE19          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE19_OFFSET)
+#define STM32_SYSCFG_ITLINE20          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE20_OFFSET)
+#define STM32_SYSCFG_ITLINE21          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE21_OFFSET)
+#define STM32_SYSCFG_ITLINE22          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE22_OFFSET)
+#define STM32_SYSCFG_ITLINE23          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE23_OFFSET)
+#define STM32_SYSCFG_ITLINE24          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE24_OFFSET)
+#define STM32_SYSCFG_ITLINE25          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE25_OFFSET)
+#define STM32_SYSCFG_ITLINE26          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE26_OFFSET)
+#define STM32_SYSCFG_ITLINE27          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE27_OFFSET)
+#define STM32_SYSCFG_ITLINE28          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE28_OFFSET)
+#define STM32_SYSCFG_ITLINE29          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE29_OFFSET)
+#define STM32_SYSCFG_ITLINE30          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE30_OFFSET)
+#define STM32_SYSCFG_ITLINE31          (STM32_SYSCFG_BASE + STM32_SYSCFG_ITLINE31_OFFSET)
+
+/* Register Bitfield Definitions ********************************************************************/
+
+/* SYSCFG memory remap register */
+
+#define SYSCFG_CFGR1_MEMMODE_SHIFT     (0)       /* Bits 1:0 MEM_MODE: Memory mapping selection */
+#define SYSCFG_CFGR1_MEMMODE_MASK      (3 << SYSCFG_CFGR1_MEMMODE_SHIFT)
+#  define SYSCFG_CFGR1_MEMMODE_FLASH   (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */
+#  define SYSCFG_CFGR1_MEMMODE_SYSTEM  (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */
+#  define SYSCFG_CFGR1_MEMMODE_SRAM    (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */
+                                                 /* Bit 2: Reserved */
+#define SYSCFG_CFGR1_PA11_RMP          (1 << 3)  /* Bit 3: PA11 remapping bit */
+#define SYSCFG_CFGR1_PA12_RMP          (1 << 4)  /* Bit 4: PA12 remapping bit */
+#define SYSCFG_CFGR1_IRPOL             (1 << 5)  /* Bit 5: IR output polarity selection */
+#define SYSCFG_CFGR1_IRMOD_SHIFT       (6)       /* Bits 6-7: IR Modulation Envelope signal selection */
+#define SYSCFG_CFGR1_IRMOD_MASK        (3 << SYSCFG_CFGR1_IRMOD_SHIFT)
+#  define SYSCFG_CFGR1_IRMOD_TIM16     (0 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 00: TIM16 selected */
+#  define SYSCFG_CFGR1_IRMOD_USART1    (1 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 01: USART1 selected */
+#  define SYSCFG_CFGR1_IRMOD_USART4    (2 << SYSCFG_CFGR1_IRMOD_SHIFT) /* 10: USART1 selected */
+#define SYSCFG_CFGR1_BOOSTEN           (1 << 8)  /* Bit 8: IO analog switch voltage booster enable */
+#define SYSCFG_CFGR1_UCPD1STROBE       (1 << 9)  /* Bit 9: UCPD1 pull-down configuration strobe */
+#define SYSCFG_CFGR1_UCPD2STROBE       (1 << 10) /* Bit 10: UCPD2 pull-down configuration strobe */
+                                                 /* Bits 11-15: Reserved */
+#define SYSCFG_CFGR1_I2CPB6FMP         (1 << 16) /* Bit 16: */
+#define SYSCFG_CFGR1_I2CPB7FMP         (1 << 17) /* Bit 17: */
+#define SYSCFG_CFGR1_I2CPB8FMP         (1 << 18) /* Bit 18: */
+#define SYSCFG_CFGR1_I2CPB9FMP         (1 << 19) /* Bit 19: */
+#define SYSCFG_CFGR1_I2C1FMP           (1 << 20) /* Bit 20: */
+#define SYSCFG_CFGR1_I2C2FMP           (1 << 21) /* Bit 21: */
+#define SYSCFG_CFGR1_I2CPA9FMP         (1 << 22) /* Bit 22: */
+#define SYSCFG_CFGR1_I2CPA10FMP        (1 << 23) /* Bit 23: */
+                                                 /* Bits 24-31: Reserved */
+
+/* SYSCFG interrupt line 0 status register */
+
+#define SYSCFG_ITLINE0_WWDG            (1 << 0)  /* Bit 0: Window Watchdog interrupt pending flag */
+
+/* SYSCFG interrupt line 1 status register */
+
+#define SYSCFG_ITLINE1_PVDOUT          (1 << 0)  /* Bit 0: PVD supply monitoring interrupt request pending (EXTI line 16) */
+
+/* SYSCFG interrupt line 2 status register */
+
+#define SYSCFG_ITLINE2_RTC_WAKEUP      (1 << 0)  /* Bit 0: RTC Wake Up interrupt request pending (EXTI line 20) */
+#define SYSCFG_ITLINE2_RTC_TSTAMP      (1 << 1)  /* Bit 1: RTC Tamper and TimeStamp interrupt request pending (EXTI line 19) */
+
+/* SYSCFG interrupt line 3 status register */
+
+#define SYSCFG_ITLINE3_FLASH_ITF       (1 << 0)  /* Bit 0: Flash interface interrupt request pending */
+#define SYSCFG_ITLINE3_FLASH_ECC       (1 << 1)  /* Bit 1: Flash interface ECC interrupt request pending */
+
+/* SYSCFG interrupt line 4 status register */
+
+#define SYSCFG_ITLINE4_RCC             (1 << 0)  /* Bit 0: Reset and clock control interrupt request pending */
+
+/* SYSCFG interrupt line 5 status register */
+
+#define SYSCFG_ITLINE5_EXTI0           (1 << 0)  /* Bit 0: EXTI line 0 interrupt request pending */
+#define SYSCFG_ITLINE5_EXTI1           (1 << 1)  /* Bit 1: EXTI line 1 interrupt request pending */
+
+/* SYSCFG interrupt line 6 status register */
+
+#define SYSCFG_ITLINE6_EXTI2           (1 << 0)  /* Bit 0: EXTI line 2 interrupt request pending */
+#define SYSCFG_ITLINE6_EXTI3           (1 << 1)  /* Bit 1: EXTI line 3 interrupt request pending */
+
+/* SYSCFG interrupt line 7 status register */
+
+#define SYSCFG_ITLINE7_EXTI4           (1 << 0)  /* Bit 0: EXTI line 4 interrupt request pending */
+#define SYSCFG_ITLINE7_EXTI5           (1 << 1)  /* Bit 1: EXTI line 5 interrupt request pending */
+#define SYSCFG_ITLINE7_EXTI6           (1 << 2)  /* Bit 2: EXTI line 6 interrupt request pending */
+#define SYSCFG_ITLINE7_EXTI7           (1 << 3)  /* Bit 3: EXTI line 7 interrupt request pending */
+#define SYSCFG_ITLINE7_EXTI8           (1 << 4)  /* Bit 4: EXTI line 8 interrupt request pending */
+#define SYSCFG_ITLINE7_EXTI9           (1 << 5)  /* Bit 5: EXTI line 9 interrupt request pending */
+#define SYSCFG_ITLINE7_EXTI10          (1 << 6)  /* Bit 6: EXTI line 10 interrupt request pending */
+#define SYSCFG_ITLINE7_EXTI11          (1 << 7)  /* Bit 7: EXTI line 11 interrupt request pending */
+#define SYSCFG_ITLINE7_EXTI12          (1 << 8)  /* Bit 8: EXTI line 12 interrupt request pending */
+#define SYSCFG_ITLINE7_EXTI13          (1 << 9)  /* Bit 9: EXTI line 13 interrupt request pending */
+#define SYSCFG_ITLINE7_EXTI14          (1 << 10) /* Bit 10: EXTI line 14 interrupt request pending */
+#define SYSCFG_ITLINE7_EXTI15          (1 << 11) /* Bit 11: EXTI line 15 interrupt request pending */
+
+/* SYSCFG interrupt line 8 status register */
+
+#define SYSCFG_ITLINE8_UCPD1           (1 << 0)  /* Bit 0: UCPD1 interrupt request pending */
+#define SYSCFG_ITLINE8_UCPD2           (1 << 1)  /* Bit 1: UCPD2 interrupt request pending */
+
+/* SYSCFG interrupt line 9 status register */
+
+#define SYSCFG_ITLINE9_DMA1_CH1        (1 << 0)  /* Bit 0: DMA1 channel 1 interrupt request pending */
+
+/* SYSCFG interrupt line 10 status register */
+
+#define SYSCFG_ITLINE10_DMA1_CH2       (1 << 0)  /* Bit 0: DMA1 channel 2 interrupt request pending */
+#define SYSCFG_ITLINE10_DMA1_CH3       (1 << 1)  /* Bit 1: DMA1 channel 3 interrupt request pending */
+
+/* SYSCFG interrupt line 11 status register */
+
+#define SYSCFG_ITLINE11_DMAMUX         (1 << 0)  /* Bit 0: DMAMUX interrupt request pending */
+#define SYSCFG_ITLINE11_DMA1_CH4       (1 << 1)  /* Bit 1: DMA1 channel 4 interrupt request pending */
+#define SYSCFG_ITLINE11_DMA1_CH5       (1 << 2)  /* Bit 2: DMA1 channel 5 interrupt request pending */
+#define SYSCFG_ITLINE11_DMA1_CH6       (1 << 3)  /* Bit 3: DMA1 channel 6 interrupt request pending */
+#define SYSCFG_ITLINE11_DMA1_CH7       (1 << 4)  /* Bit 4: DMA1 channel 7 interrupt request pending */
+
+/* SYSCFG interrupt line 12 status register */
+
+#define SYSCFG_ITLINE12_ADC            (1 << 0)  /* Bit 0: ADC interrupt request pending */
+#define SYSCFG_ITLINE12_COMP1          (1 << 1)  /* Bit 1: Comparator 1 interrupt request pending */
+#define SYSCFG_ITLINE12_COMP2          (1 << 2)  /* Bit 2: Comparator 2 interrupt request pending */
+
+/* SYSCFG interrupt line 13 status register */
+
+#define SYSCFG_ITLINE13_TIM1_CCU       (1 << 0)  /* Bit 0: TIM1 commutation interrupt request pending */
+#define SYSCFG_ITLINE13_TIM1_TRG       (1 << 1)  /* Bit 1: TIM1 triggerinterrupt request pending */
+#define SYSCFG_ITLINE13_TIM1_UPD       (1 << 2)  /* Bit 2: TIM1 update interrupt request pending */
+#define SYSCFG_ITLINE13_TIM1_BRK       (1 << 3)  /* Bit 3: TIM1 break interrupt request pending */
+
+/* SYSCFG interrupt line 14 status register */
+
+#define SYSCFG_ITLINE14_TIM1_CC        (1 << 0)  /* Bit 0: TIM1 capture compare interrupt request pending */
+
+/* SYSCFG interrupt line 15 status register */
+
+#define SYSCFG_ITLINE15_TIM2           (1 << 0)  /* Bit 0: Timer 2 interrupt request pending */
+
+/* SYSCFG interrupt line 16 status register */
+
+#define SYSCFG_ITLINE16_TIM3           (1 << 0)  /* Bit 0: Timer 3 interrupt request pending */
+
+/* SYSCFG interrupt line 17 status register */
+
+#define SYSCFG_ITLINE17_TIM6           (1 << 0)  /* Bit 0: Timer 6 interrupt request pending */
+#define SYSCFG_ITLINE17_DAC            (1 << 1)  /* Bit 1: DAC underrun interrupt request pending */
+#define SYSCFG_ITLINE17_LPTIM1         (1 << 2)  /* Bit 2: Low-power timer 1 interrupt request pending */
+
+/* SYSCFG interrupt line 18 status register */
+
+#define SYSCFG_ITLINE18_TIM7           (1 << 0)  /* Bit 0: Timer 7 interrupt request pending */
+#define SYSCFG_ITLINE18_LPTIM2         (1 << 1)  /* Bit 1: Low-power timer 2 interrupt request pending */
+
+/* SYSCFG interrupt line 19 status register */
+
+#define SYSCFG_ITLINE19_TIM14          (1 << 0)  /* Bit 0: Timer 14 interrupt request pending */
+
+/* SYSCFG interrupt line 20 status register */
+
+#define SYSCFG_ITLINE20_TIM15          (1 << 0)  /* Bit 0: Timer 15 interrupt request pending */
+
+/* SYSCFG interrupt line 21 status register */
+
+#define SYSCFG_ITLINE21_TIM16          (1 << 0)  /* Bit 0: Timer 16 interrupt request pending */
+
+/* SYSCFG interrupt line 22 status register */
+
+#define SYSCFG_ITLINE22_TIM17          (1 << 0)  /* Bit 0: Timer 17 interrupt request pending */
+
+/* SYSCFG interrupt line 23 status register */
+
+#define SYSCFG_ITLINE23_I2C1           (1 << 0)  /* Bit 0: I2C1 interrupt request pending, combined with EXTI line 23 */
+
+/* SYSCFG interrupt line 24 status register */
+
+#define SYSCFG_ITLINE24_I2C2           (1 << 0)  /* Bit 0: I2C2 interrupt request pending */
+
+/* SYSCFG interrupt line 25 status register */
+
+#define SYSCFG_ITLINE25_SPI1           (1 << 0)  /* Bit 0: SPI1 interrupt request pending */
+
+/* SYSCFG interrupt line 26 status register */
+
+#define SYSCFG_ITLINE26_SPI2           (1 << 0)  /* Bit 0: SPI2 interrupt request pending */
+
+/* SYSCFG interrupt line 27 status register */
+
+#define SYSCFG_ITLINE27_USART1         (1 << 0)  /* Bit 0: USART1 interrupt request pending */
+
+/* SYSCFG interrupt line 28 status register */
+
+#define SYSCFG_ITLINE28_USART2         (1 << 0)  /* Bit 0: USART2 interrupt request pending */
+
+/* SYSCFG interrupt line 29 status register */
+
+#define SYSCFG_ITLINE29_USART3         (1 << 0)  /* Bit 0: USART3 interrupt request pending */
+#define SYSCFG_ITLINE29_USART4         (1 << 1)  /* Bit 1: USART4 interrupt request pending */
+#define SYSCFG_ITLINE29_LPUART1        (1 << 2)  /* Bit 2: LPUART1 interrupt request pending */
+
+/* SYSCFG interrupt line 30 status register */
+
+#define SYSCFG_ITLINE30_CEC            (1 << 0)  /* Bit 0: CEC interrupt request pending, combined with EXTI line 27 */
+
+/* SYSCFG interrupt line 31 status register */
+
+#define SYSCFG_ITLINE30_RNG            (1 << 0)  /* Bit 0: RNG interrupt request pending */
+#define SYSCFG_ITLINE30_AES            (1 << 1)  /* Bit 1: AES interrupt request pending */
+
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_exti.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h
similarity index 95%
rename from arch/arm/src/stm32f0l0/hardware/stm32l0_exti.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h
index f62df1100a4..c810affae18 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32l0_exti.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_exti.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32L0_EXTI_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32L0_EXTI_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H
 
 /************************************************************************************
  * Included Files
@@ -47,7 +47,7 @@
  * Pre-processor Definitions
  ************************************************************************************/
 
-#define STM32_NEXTI              31      /* REVISIT: Taken from the F0, probably incorrect */
+#define STM32_NEXTI              29
 #define STM32_EXTI_MASK          0xffffffff
 
 #define STM32_EXTI_BIT(n)        (1 << (n))
@@ -126,4 +126,4 @@
 #define EXTI_PR_SHIFT            (0)                /* Bits 0-X: Pending bit for all lines */
 #define EXTI_PR_MASK             STM32_EXTI_MASK
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32L0_EXTI_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_flash.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h
similarity index 96%
rename from arch/arm/src/stm32f0l0/hardware/stm32l0_flash.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h
index bbff059cb08..0ce7b63c00c 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32l0_flash.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/hardware/stm32l0_flash.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_FLASH_H
-#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_FLASH_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H
 
 /************************************************************************************
  * Included Files
@@ -114,4 +114,4 @@
 #define FLASH_SR_OPTVERRUSR         (1 << 12) /* Bit 12: Option UserValidity Error */
 #define FLASH_SR_RDERR              (1 << 13) /* Bit 13: Read protected error */
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_FLASH_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h
similarity index 93%
rename from arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h
index f6ac7a385c7..c38609e0c18 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -84,8 +84,8 @@
 #define STM32_SPI2_BASE      0x40003800     /* 0x40003800-0x40003bff SPI2 */
 #define STM32_USART2_BASE    0x40004400     /* 0x40004400-0x400047ff USART2 */
 #define STM32_LPUART1_BASE   0x40004800     /* 0x40004800-0x40004bff LPUART1 */
-#define STM32_UART4_BASE     0x40004c00     /* 0x40004c00-0x40004fff UART4 */
-#define STM32_UART5_BASE     0x40005000     /* 0x40005000-0x400053ff UART5 */
+#define STM32_USART4_BASE    0x40004c00     /* 0x40004c00-0x40004fff USART4 */
+#define STM32_USART5_BASE    0x40005000     /* 0x40005000-0x400053ff USART5 */
 #define STM32_I2C1_BASE      0x40005400     /* 0x40005400-0x400057ff I2C1 */
 #define STM32_I2C2_BASE      0x40005800     /* 0x40005800-0x40005bff I2C2 */
 #define STM32_USB_BASE       0x40005c00     /* 0x40005c00-0x40005fff USB device FS */
@@ -103,7 +103,7 @@
 #define STM32_TIM21_BASE     0x40010800     /* 0x40010800-0x40010bff TIM21 */
 #define STM32_TIM22_BASE     0x40014000     /* 0x40014000-0x400117ff TIM22 */
 #define STM32_FIREWALL_BASE  0x4001c000     /* 0x4001c000-0x400113ff Firewall */
-#define STM32_ADC1_BASE      0x40012400     /* 0x40012400-0x400127ff ADC1 */
+#define STM32_ADC12_BASE     0x40012400     /* 0x40012400-0x400127ff ADC12 */
 #define STM32_SPI1_BASE      0x40013000     /* 0x40013000-0x400133ff SPI1 */
 #define STM32_USART1_BASE    0x40013800     /* 0x40013800-0x40013bff USART1 */
 #define STM32_DBGMCU_BASE    0x40015800     /* 0x40015800-0x40015bff DBGMCU */
@@ -127,4 +127,4 @@
 #define STM32_GPIOE_BASE     0x50001000     /* 0x50001000-0x500013ff GPIO Port E */
 #define STM32_GPIOH_BASE     0x50001c00     /* 0x50001c00-0x50001fff GPIO Port H */
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h
similarity index 95%
rename from arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h
index fc2a6e31116..6d799c1288c 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PINMAP_H
-#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -58,7 +58,7 @@
  *
  * #define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
  *
- * The driver will then automatically configre PB6 as the I2C1 SCL pin.
+ * The driver will then automatically configure PB6 as the I2C1 SCL pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -294,7 +294,6 @@
 #define GPIO_USART1_CTS_2   (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN4)
 #define GPIO_USART1_RTS_1   (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN12)
 #define GPIO_USART1_RTS_2   (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN3)
-#define GPIO_USART1_RTS     (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN12)
 #define GPIO_USART1_RX_1    (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN10)
 #define GPIO_USART1_RX_2    (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7)
 #define GPIO_USART1_TX_1    (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN9)
@@ -308,16 +307,20 @@
 #define GPIO_USART2_RTS_2   (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN4)
 #define GPIO_USART2_RX_1    (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN3)
 #define GPIO_USART2_RX_2    (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN6)
+#define GPIO_USART2_RX_3    (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN15)
 #define GPIO_USART2_TX_1    (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN2)
 #define GPIO_USART2_TX_2    (GPIO_ALT | GPIO_PULLUP | GPIO_AF0 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN5)
+#define GPIO_USART2_TX_3    (GPIO_ALT | GPIO_PULLUP | GPIO_AF4 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN14)
 
-#define GPIO_USART2_CK      (GPIO_ALT | GPIO_AF6 | GPIO_PORTC | GPIO_PIN12)
-#define GPIO_USART2_RTS     (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN15)
-#define GPIO_USART2_CTS     (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN7)
+#define GPIO_USART4_CK      (GPIO_ALT | GPIO_AF6 | GPIO_PORTC | GPIO_PIN12)
+#define GPIO_USART4_RTS     (GPIO_ALT | GPIO_AF6 | GPIO_PORTA | GPIO_PIN15)
+#define GPIO_USART4_CTS     (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN7)
 #define GPIO_USART4_RX_1    (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN11)
 #define GPIO_USART4_RX_2    (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN9)
+#define GPIO_USART4_RX_3    (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN1)
 #define GPIO_USART4_TX_1    (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN10)
 #define GPIO_USART4_TX_2    (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN8)
+#define GPIO_USART4_TX_3    (GPIO_ALT | GPIO_PULLUP | GPIO_AF6 | GPIO_SPEED_HIGH | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN0)
 
 #define GPIO_USART5_CK_1    (GPIO_ALT | GPIO_AF6 | GPIO_PORTB | GPIO_PIN5)
 #define GPIO_USART5_CK_2    (GPIO_ALT | GPIO_AF6 | GPIO_PORTE | GPIO_PIN7)
@@ -336,6 +339,4 @@
 
 /* TODO: LPUART */
 
-/* TODO: LCD */
-
-#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h
similarity index 95%
rename from arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h
index ece00a1ecfd..b15936c3151 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32l0_pwr.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PWR_H
-#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PWR_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H
 
 /************************************************************************************
  * Included Files
@@ -102,4 +102,4 @@
 #define PWR_CSR_EWUP2          (1 << 9)  /* Bit 9:  Enable WKUP2 pin */
 #define PWR_CSR_EWUP3          (1 << 10) /* Bit 10: Enable WKUP3 pin */
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_PWR_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h
similarity index 82%
rename from arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h
index 0b2736d1835..706a09756c7 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_RCC_H
-#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -139,9 +139,9 @@
 
 /* Clock recovery RC register */
 
-#define RCC_CRRCR_HSI48ON           (0)       /* Bits 0: 48MHz HSI clock enable */
-#define RCC_CRRCR_HSI48RDY          (1)       /* Bits 1: 48MHz HSI clock ready */
-#define RCC_CRRCR_HSI48DIV6EN       (2)       /* Bits 2: 48MHz HSI clock divided by 6 output enable */
+#define RCC_CRRCR_HSI48ON           (1 << 0)  /* Bits 0: 48MHz HSI clock enable */
+#define RCC_CRRCR_HSI48RDY          (1 << 1)  /* Bits 1: 48MHz HSI clock ready */
+#define RCC_CRRCR_HSI48DIV6EN       (1 << 2)  /* Bits 2: 48MHz HSI clock divided by 6 output enable */
                                               /* Bits 3-7: Reserved */
 #define RCC_CRRCR_HSI48CAL_SHIFT    (8)       /* Bits 8: 48 MHz HSI reset calibration */
 #define RCC_CRRCR_HSI48CAL_MASK     (0xff << RCC_CRRCR_HSI48CAL_SHIFT)
@@ -263,27 +263,27 @@
 /* GPIO reset register */
 
 #define RCC_IOPRSTR_IOPARST         (1 << 0)  /* Bit 0: IO port A reset */
-#define RCC_IOPRSTR_IOPBRST         (1 << 1)  /* Bit 0: IO port B reset */
-#define RCC_IOPRSTR_IOPCRST         (1 << 2)  /* Bit 0: IO port C reset */
-#define RCC_IOPRSTR_IOPDRST         (1 << 3)  /* Bit 0: IO port D reset */
-#define RCC_IOPRSTR_IOPERST         (1 << 4)  /* Bit 0: IO port E reset */
+#define RCC_IOPRSTR_IOPBRST         (1 << 1)  /* Bit 1: IO port B reset */
+#define RCC_IOPRSTR_IOPCRST         (1 << 2)  /* Bit 3: IO port C reset */
+#define RCC_IOPRSTR_IOPDRST         (1 << 3)  /* Bit 4: IO port D reset */
+#define RCC_IOPRSTR_IOPERST         (1 << 4)  /* Bit 4: IO port E reset */
                                               /* Bits 5-6: Reserved */
-#define RCC_IOPRSTR_IOPHRST         (1 << 7)  /* Bit 0: IO port H reset */
+#define RCC_IOPRSTR_IOPHRST         (1 << 7)  /* Bit 5: IO port H reset */
 
 /* AHB peripheral reset register */
 
-#define RCC_AHBRSTR_DMA1RST         (0)  /* Bit 0: DMA 1 reset */
-                                         /* Bits 1-7: Reserved */
-#define RCC_AHBRSTR_MIFRST          (8)  /* Bit 8: Memory interface reset */
-                                         /* Bits 9-11: Reserved */
-#define RCC_AHBRSTR_CRCRST          (12) /* Bit 12: Memory interface reset */
-                                         /* Bits 13-15: Reserved */
-#define RCC_AHBRSTR_TSCRST          (12) /* Bit 12: Touch sensing reset */
-                                         /* Bits 17-19: Reserved */
-#define RCC_AHBRSTR_RNGRST          (20) /* Bit 20: Random number generator module reset */
-                                         /* Bits 21-23: Reserved */
-#define RCC_AHBRSTR_CRYPRST         (24) /* Bit 24: Crypto module reset */
-                                         /* Bits 25-31: Reserved */
+#define RCC_AHBRSTR_DMA1RST         (1 << 0)  /* Bit 0: DMA 1 reset */
+                                              /* Bits 1-7: Reserved */
+#define RCC_AHBRSTR_MIFRST          (1 << 8)  /* Bit 8: Memory interface reset */
+                                              /* Bits 9-11: Reserved */
+#define RCC_AHBRSTR_CRCRST          (1 << 12) /* Bit 12: Memory interface reset */
+                                              /* Bits 13-15: Reserved */
+#define RCC_AHBRSTR_TSCRST          (1 << 16) /* Bit 16: Touch sensing reset */
+                                              /* Bits 17-19: Reserved */
+#define RCC_AHBRSTR_RNGRST          (1 << 20) /* Bit 20: Random number generator module reset */
+                                              /* Bits 21-23: Reserved */
+#define RCC_AHBRSTR_AESRST          (1 << 24) /* Bit 24: Crypto module (AES) reset */
+                                              /* Bits 25-31: Reserved */
 
 /* APB2 Peripheral reset register */
 
@@ -318,8 +318,8 @@
                                               /* Bits 15-16: Reserved */
 #define RCC_APB1RSTR_USART2RST      (1 << 17) /* Bit 17: USART 2 reset */
 #define RCC_APB1RSTR_USART3RST      (1 << 18) /* Bit 18: USART 3 reset */
-#define RCC_APB1RSTR_UART4RST       (1 << 19) /* Bit 19: UART 4 reset */
-#define RCC_APB1RSTR_UART5RST       (1 << 20) /* Bit 20: UART 5 reset */
+#define RCC_APB1RSTR_USART4RST      (1 << 19) /* Bit 19: USART 4 reset */
+#define RCC_APB1RSTR_USART5RST      (1 << 20) /* Bit 20: USART 5 reset */
 #define RCC_APB1RSTR_I2C1RST        (1 << 21) /* Bit 21: I2C 1 reset */
 #define RCC_APB1RSTR_I2C2RST        (1 << 22) /* Bit 22: I2C 2 reset */
 #define RCC_APB1RSTR_USBRST         (1 << 23) /* Bit 23: USB reset */
@@ -333,27 +333,27 @@
 /* GPIO clock enable register */
 
 #define RCC_IOPENR_IOPAEN           (1 << 0)  /* Bit 0: IO port A clock enable */
-#define RCC_IOPENR_IOPBEN           (1 << 1)  /* Bit 0: IO port B clock enable */
-#define RCC_IOPENR_IOPCEN           (1 << 2)  /* Bit 0: IO port C clock enable */
-#define RCC_IOPENR_IOPDEN           (1 << 3)  /* Bit 0: IO port D clock enable */
-#define RCC_IOPENR_IOPEEN           (1 << 4)  /* Bit 0: IO port E clock enable */
+#define RCC_IOPENR_IOPBEN           (1 << 1)  /* Bit 1: IO port B clock enable */
+#define RCC_IOPENR_IOPCEN           (1 << 2)  /* Bit 2: IO port C clock enable */
+#define RCC_IOPENR_IOPDEN           (1 << 3)  /* Bit 3: IO port D clock enable */
+#define RCC_IOPENR_IOPEEN           (1 << 4)  /* Bit 4: IO port E clock enable */
                                               /* Bits 5-6: Reserved */
-#define RCC_IOPENR_IOPHEN           (1 << 7)  /* Bit 0: IO port H clock enable */
+#define RCC_IOPENR_IOPHEN           (1 << 7)  /* Bit 5: IO port H clock enable */
 
 /* AHB Peripheral Clock enable register */
 
-#define RCC_AHBENR_DMA1EN           (0)  /* Bit 0: DMA 1 clock enable */
-                                         /* Bits 1-7: Reserved */
-#define RCC_AHBENR_MIFEN            (8)  /* Bit 8: Memory interface clock enable */
-                                         /* Bits 9-11: Reserved */
-#define RCC_AHBENR_CRCEN            (12) /* Bit 12: Memory interface clock enable */
-                                         /* Bits 13-15: Reserved */
-#define RCC_AHBENR_TSCEN            (12) /* Bit 12: Touch sensing clock enable */
-                                         /* Bits 17-19: Reserved */
-#define RCC_AHBENR_RNGEN            (20) /* Bit 20: Random number generator module clock enable */
-                                         /* Bits 21-23: Reserved */
-#define RCC_AHBENR_CRYPEN           (24) /* Bit 24: Crypto module clock enable */
-                                         /* Bits 25-31: Reserved */
+#define RCC_AHBENR_DMA1EN           (1 << 0)  /* Bit 0: DMA 1 clock enable */
+                                              /* Bits 1-7: Reserved */
+#define RCC_AHBENR_MIFEN            (1 << 8)  /* Bit 8: Memory interface clock enable */
+                                              /* Bits 9-11: Reserved */
+#define RCC_AHBENR_CRCEN            (1 << 12) /* Bit 12: Memory interface clock enable */
+                                              /* Bits 13-15: Reserved */
+#define RCC_AHBENR_TSCEN            (1 << 12) /* Bit 12: Touch sensing clock enable */
+                                              /* Bits 17-19: Reserved */
+#define RCC_AHBENR_RNGEN            (1 << 20) /* Bit 20: Random number generator module clock enable */
+                                              /* Bits 21-23: Reserved */
+#define RCC_AHBENR_AESEN            (1 << 24) /* Bit 24: Crypto module (AES) clock enable */
+                                               /* Bits 25-31: Reserved */
 
 /* APB2 Peripheral Clock enable register */
 
@@ -388,8 +388,8 @@
                                                 /* Bits 15-16: Reserved */
 #define RCC_APB1ENR_USART2EN          (1 << 17) /* Bit 17: USART 2 clock enable */
 #define RCC_APB1ENR_USART3EN          (1 << 18) /* Bit 18: USART 3 clock enable */
-#define RCC_APB1ENR_UART4EN           (1 << 19) /* Bit 19: UART 4 clock enable */
-#define RCC_APB1ENR_UART5EN           (1 << 20) /* Bit 20: UART 5 clock enable */
+#define RCC_APB1ENR_USART4EN          (1 << 19) /* Bit 19: USART 4 clock enable */
+#define RCC_APB1ENR_USART5EN          (1 << 20) /* Bit 20: USART 5 clock enable */
 #define RCC_APB1ENR_I2C1EN            (1 << 21) /* Bit 21: I2C 1 clock enable */
 #define RCC_APB1ENR_I2C2EN            (1 << 22) /* Bit 22: I2C 2 clock enable */
 #define RCC_APB1ENR_USBEN             (1 << 23) /* Bit 23: USB clock enable */
@@ -403,27 +403,27 @@
 /* GPIO clock enable in Sleep mode register */
 
 #define RCC_IOPSMENR_IOPASMEN          (1 << 0)  /* Bit 0: IO port A clock enable during Sleep mode */
-#define RCC_IOPSMENR_IOPBSMEN          (1 << 1)  /* Bit 0: IO port B clock enable during Sleep mode */
-#define RCC_IOPSMENR_IOPCSMEN          (1 << 2)  /* Bit 0: IO port C clock enable during Sleep mode */
-#define RCC_IOPSMENR_IOPDSMEN          (1 << 3)  /* Bit 0: IO port D clock enable during Sleep mode */
-#define RCC_IOPSMENR_IOPESMEN          (1 << 4)  /* Bit 0: IO port E clock enable during Sleep mode */
+#define RCC_IOPSMENR_IOPBSMEN          (1 << 1)  /* Bit 1: IO port B clock enable during Sleep mode */
+#define RCC_IOPSMENR_IOPCSMEN          (1 << 2)  /* Bit 2: IO port C clock enable during Sleep mode */
+#define RCC_IOPSMENR_IOPDSMEN          (1 << 3)  /* Bit 3: IO port D clock enable during Sleep mode */
+#define RCC_IOPSMENR_IOPESMEN          (1 << 4)  /* Bit 4: IO port E clock enable during Sleep mode */
                                                  /* Bits 5-6: Reserved */
-#define RCC_IOPSMENR_IOPHSMEN          (1 << 7)  /* Bit 0: IO port H clock enable during Sleep mode */
+#define RCC_IOPSMENR_IOPHSMEN          (1 << 7)  /* Bit 7: IO port H clock enable during Sleep mode */
 
 /* AHB peripheral clock enable in Sleep mode register */
 
-#define RCC_AHBSMENR_DMA1SMEN           (0)  /* Bit 0: DMA 1 clock enable in Sleep mode */
-                                             /* Bits 1-7: Reserved */
-#define RCC_AHBSMENR_MIFSMEN            (8)  /* Bit 8: Memory interface clock enable in Sleep mode */
-                                             /* Bits 9-11: Reserved */
-#define RCC_AHBSMENR_CRCSMEN            (12) /* Bit 12: Memory interface clock enable in Sleep mode */
-                                             /* Bits 13-15: Reserved */
-#define RCC_AHBSMENR_TSCSMEN            (12) /* Bit 12: Touch sensing clock enable in Sleep mode */
-                                             /* Bits 17-19: Reserved */
-#define RCC_AHBSMENR_RNGSMEN            (20) /* Bit 20: Random number generator module clock enable in Sleep mode */
-                                             /* Bits 21-23: Reserved */
-#define RCC_AHBSMENR_CRYPSMEN           (24) /* Bit 24: Crypto module clock enable in Sleep mode */
-                                             /* Bits 25-31: Reserved */
+#define RCC_AHBSMENR_DMA1SMEN           (1 << 0)  /* Bit 0: DMA 1 clock enable in Sleep mode */
+                                                  /* Bits 1-7: Reserved */
+#define RCC_AHBSMENR_MIFSMEN            (1 << 8)  /* Bit 8: Memory interface clock enable in Sleep mode */
+                                                  /* Bits 9-11: Reserved */
+#define RCC_AHBSMENR_CRCSMEN            (1 << 12) /* Bit 12: Memory interface clock enable in Sleep mode */
+                                                  /* Bits 13-15: Reserved */
+#define RCC_AHBSMENR_TSCSMEN            (1 << 12) /* Bit 12: Touch sensing clock enable in Sleep mode */
+                                                  /* Bits 17-19: Reserved */
+#define RCC_AHBSMENR_RNGSMEN            (1 << 20) /* Bit 20: Random number generator module clock enable in Sleep mode */
+                                                  /* Bits 21-23: Reserved */
+#define RCC_AHBSMENR_AESSMEN            (1 << 24) /* Bit 24: Crypto module (AES) clock enable in Sleep mode */
+                                                  /* Bits 25-31: Reserved */
 
 /* APB2 peripheral clock enable in Sleep mode register */
 
@@ -458,8 +458,8 @@
                                                   /* Bits 15-16: Reserved */
 #define RCC_APB1SMENR_USART2SMEN        (1 << 17) /* Bit 17: USART 2 clock enable in Sleep mode */
 #define RCC_APB1SMENR_USART3SMEN        (1 << 18) /* Bit 18: USART 3 clock enable in Sleep mode */
-#define RCC_APB1SMENR_UART4SMEN         (1 << 19) /* Bit 19: UART 4 clock enable in Sleep mode */
-#define RCC_APB1SMENR_UART5SMEN         (1 << 20) /* Bit 20: UART 5 clock enable in Sleep mode */
+#define RCC_APB1SMENR_USART4SMEN        (1 << 19) /* Bit 19: USART 4 clock enable in Sleep mode */
+#define RCC_APB1SMENR_USART5SMEN        (1 << 20) /* Bit 20: USART 5 clock enable in Sleep mode */
 #define RCC_APB1SMENR_I2C1SMEN          (1 << 21) /* Bit 21: I2C 1 clock enable in Sleep mode */
 #define RCC_APB1SMENR_I2C2SMEN          (1 << 22) /* Bit 22: I2C 2 clock enable in Sleep mode */
 #define RCC_APB1SMENR_USBSMEN           (1 << 23) /* Bit 23: USB clock enable in Sleep mode */
@@ -484,7 +484,7 @@
 #  define RCC_CCIPR_USART2SEL_SYSCLK    (1 << RCC_CCIPR_USART2SEL_SHIFT)
 #  define RCC_CCIPR_USART2SEL_HSI16     (2 << RCC_CCIPR_USART2SEL_SHIFT)
 #  define RCC_CCIPR_USART2SEL_LSE       (3 << RCC_CCIPR_USART2SEL_SHIFT)
-                                             /* Bits 4-9: Reserved */
+                                              /* Bits 4-9: Reserved */
 #define RCC_CCIPR_LPUART1SEL_SHIFT      (10)  /* Bits 10-11: LPUART1 clock source selection */
 #define RCC_CCIPR_LPUART1SEL_MASK       (3 << RCC_CCIPR_LPUART1SEL_SHIFT)
 #  define RCC_CCIPR_LPUART1SEL_APB      (0 << RCC_CCIPR_LPUART1SEL_SHIFT)
@@ -509,46 +509,46 @@
 #  define RCC_CCIPR_LPTIM1SEL_HSI16     (2 << RCC_CCIPR_LPTIM1SEL_SHIFT)
 #  define RCC_CCIPR_LPTIM1SEL_LSE       (3 << RCC_CCIPR_LPTIM1SEL_SHIFT)
                                               /* Bits 20-25: Reserved */
-#define RCC_CCIPR_HSI48SEL_SHIFT        (26)  /* Bit 26: HSI48 clock source selection */
-#define RCC_CCIPR_HSI48SEL_MASK         (1 << RCC_CCIPR_HSI48SEL_SHIFT)
-#  define RCC_CCIPR_HSI48SEL_PLL        (0 << RCC_CCIPR_HSI48SEL_SHIFT)
-#  define RCC_CCIPR_HSI48SEL_RC48       (1 << RCC_CCIPR_HSI48SEL_SHIFT)
+#define RCC_CCIPR_CLK48SEL_SHIFT        (26)  /* Bit 26: HSI48 clock source selection */
+#define RCC_CCIPR_CLK48SEL_MASK         (1 << RCC_CCIPR_CLK48SEL_SHIFT)
+#  define RCC_CCIPR_CLK48SEL_PLL        (0 << RCC_CCIPR_CLK48SEL_SHIFT)
+#  define RCC_CCIPR_CLK48SEL_HSI48      (1 << RCC_CCIPR_CLK48SEL_SHIFT)
                                               /* Bits 27-31: Reserved */
 
 /* Control/status register */
 
-#define RCC_CSR_LSION                   (0)  /* Bit 0: LSI enable */
-#define RCC_CSR_LSIRDY                  (1)  /* Bit 1: ready */
-                                             /* Bits 3-7: Reserved */
-#define RCC_CSR_LSEON                   (8)  /* Bit 8: LSE enable */
-#define RCC_CSR_LSERDY                  (9)  /* Bit 9: LSE ready */
-#define RCC_CSR_LSEBPY                  (10) /* Bit 10: LSE bypass */
-#define RCC_CSR_LSEDRV_SHIFT            (11) /* Bits 11-12: LSE driving capability */
+#define RCC_CSR_LSION                   (1 << 0)  /* Bit 0: LSI enable */
+#define RCC_CSR_LSIRDY                  (1 << 1)  /* Bit 1: ready */
+                                                  /* Bits 2-7: Reserved */
+#define RCC_CSR_LSEON                   (1 << 8)  /* Bit 8: LSE enable */
+#define RCC_CSR_LSERDY                  (1 << 9)  /* Bit 9: LSE ready */
+#define RCC_CSR_LSEBPY                  (1 << 10) /* Bit 10: LSE bypass */
+#define RCC_CSR_LSEDRV_SHIFT            (11)      /* Bits 11-12: LSE driving capability */
 #define RCC_CSR_LSEDRV_MASK             (3 << RCC_CSR_LSEDRV_SHIFT)
 #  define RCC_CSR_LSEDRV_LOW            (0 << RCC_CSR_LSEDRV_SHIFT)
 #  define RCC_CSR_LSEDRV_MEDLOW         (1 << RCC_CSR_LSEDRV_SHIFT)
 #  define RCC_CSR_LSEDRV_MEDHGIH        (2 << RCC_CSR_LSEDRV_SHIFT)
 #  define RCC_CSR_LSEDRV_HIGH           (3 << RCC_CSR_LSEDRV_SHIFT)
-#define RCC_CSR_CSSLSEON                (13) /* Bit 13: CSS on LSE enable */
-#define RCC_CSR_CSSLSED                 (14) /* Bit 14: CSS on LSE failure detection flag */
-                                             /* Bit 15: Reserved */
-#define RCC_CSR_RTCSEL_SHIFT            (16) /* Bits 16-17: RTC clock source selection */
+#define RCC_CSR_CSSLSEON                (1 << 13) /* Bit 13: CSS on LSE enable */
+#define RCC_CSR_CSSLSED                 (1 << 14) /* Bit 14: CSS on LSE failure detection flag */
+                                                 /* Bit 15: Reserved */
+#define RCC_CSR_RTCSEL_SHIFT            (16)     /* Bits 16-17: RTC clock source selection */
 #define RCC_CSR_RTCSEL_MASK             (3 << RCC_CSR_RTCSEL_SHIFT)
 #  define RCC_CSR_RTCSEL_NOCLK          (0 << RCC_CSR_RTCSEL_SHIFT)
 #  define RCC_CSR_RTCSEL_LSE            (1 << RCC_CSR_RTCSEL_SHIFT)
 #  define RCC_CSR_RTCSEL_LSI            (2 << RCC_CSR_RTCSEL_SHIFT)
 #  define RCC_CSR_RTCSEL_HSE            (3 << RCC_CSR_RTCSEL_SHIFT)
-#define RCC_CSR_RTCEN                   (18) /* Bit 18: RTC clock enable */
-#define RCC_CSR_RTCRST                  (19) /* Bit 19: RTC software reset */
-                                             /* Bits 20-22: Reserved */
-#define RCC_CSR_RMVF                    (23) /* Bit 23: Remove reset flag */
-#define RCC_CSR_FWRSTF                  (24) /* Bit 24: Firewall reset flag */
-#define RCC_CSR_OBLRSTF                 (25) /* Bit 25: Options bytes loading reset flag */
-#define RCC_CSR_PINRSTF                 (26) /* Bit 26: PIN reset flag */
-#define RCC_CSR_PORRSTF                 (27) /* Bit 27: POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF                 (28) /* Bit 28: software reset flag */
-#define RCC_CSR_IWDGRSTF                (29) /* Bit 29: IWDG reset flag */
-#define RCC_CSR_WWDGRSTF                (30) /* Bit 30: WWDG reset flag */
-#define RCC_CSR_LPWRRSTF                (31) /* Bit 31: Low-power reset flag */
+#define RCC_CSR_RTCEN                   (1 << 18) /* Bit 18: RTC clock enable */
+#define RCC_CSR_RTCRST                  (1 << 19) /* Bit 19: RTC software reset */
+                                                  /* Bits 20-22: Reserved */
+#define RCC_CSR_RMVF                    (1 << 23) /* Bit 23: Remove reset flag */
+#define RCC_CSR_FWRSTF                  (1 << 24) /* Bit 24: Firewall reset flag */
+#define RCC_CSR_OBLRSTF                 (1 << 25) /* Bit 25: Options bytes loading reset flag */
+#define RCC_CSR_PINRSTF                 (1 << 26) /* Bit 26: PIN reset flag */
+#define RCC_CSR_PORRSTF                 (1 << 27) /* Bit 27: POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF                 (1 << 28) /* Bit 28: software reset flag */
+#define RCC_CSR_IWDGRSTF                (1 << 29) /* Bit 29: IWDG reset flag */
+#define RCC_CSR_WWDGRSTF                (1 << 30) /* Bit 30: WWDG reset flag */
+#define RCC_CSR_LPWRRSTF                (1 << 31) /* Bit 31: Low-power reset flag */
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H */
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_syscfg.h b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h
similarity index 83%
rename from arch/arm/src/stm32f0l0/hardware/stm32l0_syscfg.h
rename to arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h
index f2680abaeb7..31898e76f99 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32l0_syscfg.h
+++ b/arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32l0_syscfg.h
+ * arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -51,6 +51,7 @@
 
 #define STM32_SYSCFG_CFGR1_OFFSET      0x0000 /* SYSCFG configuration register 1 */
 #define STM32_SYSCFG_CFGR2_OFFSET      0x0004 /* SYSCFG configuration register 2 */
+#define STM32_SYSCFG_CFGR3_OFFSET      0x0020 /* SYSCFG configuration register 3 */
 
 #define STM32_SYSCFG_EXTICR_OFFSET(p)  (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
 #define STM32_SYSCFG_EXTICR1_OFFSET    0x0008 /* SYSCFG external interrupt configuration register 1 */
@@ -64,6 +65,7 @@
 
 #define STM32_SYSCFG_CFGR1             (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET)
 #define STM32_SYSCFG_CFGR2             (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET)
+#define STM32_SYSCFG_CFGR3             (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR3_OFFSET)
 
 #define STM32_SYSCFG_EXTICR(p)         (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
 #define STM32_SYSCFG_EXTICR1           (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
@@ -81,6 +83,20 @@
 
 /* TODO: SYSCFG configuration register 3 */
 
+#define SYSCFG_CFGR3_ENVREFINT        (1 << 0)   /* Bit 0: VREFINT enable and scaler control for COMP2 enable */
+                                                 /* Bits 1-3: Reserved */
+#define SYSCFG_CFGR3_SELVREFOUT_SHIFT (4)        /* Bits 4-5: VREFINT_ADC connection */
+#define SYSCFG_CFGR3_SELVREFOUT_MASK  (3 << SYSCFG_CFGR3_SELVREFOUT_SHIFT)
+                                                 /* Bits 6-7: Reserved */
+#define SYSCFG_CFGR3_ENBUFVREFADC     (1 << 8)   /* Bit 8: VREFINT reference for ADC enable */
+#define SYSCFG_CFGR3_ENBUFSENSORADC   (1 << 9)   /* Bit 9: Temperature sensor reference for ADC enable */
+                                                 /* Bits 10-11: Reserved */
+#define SYSCFG_CFGR3_ENBUFVREFINTCOMP2 (1 << 12) /* Bit 12: VREFINT reference for COMP2 scaler enable */
+#define SYSCFG_CFGR3_ENBUFVREFINTHSI48 (1 << 13) /* Bit 13: VREFINT reference for HSI48 scaler enable */
+                                                 /* Bits 14-29: Reserved */
+#define SYSCFG_CFGR3_VREFINTRDYF       (1 << 30) /* Bit 30: VREFINT ready flag */
+#define SYSCFG_CFGR3_REFLOCK           (1 << 31) /* Bit 31: SYSCFG_CFG3 lock bit */
+
 /* SYSCFG external interrupt configuration register 1-4 */
 
 #define SYSCFG_EXTICR_PORTA           (0)       /* 0000: PA[x] pin */
@@ -129,4 +145,4 @@
 #define SYSCFG_EXTICR4_EXTI15_SHIFT   (12)      /* Bits 12-15: EXTI 15 configuration */
 #define SYSCFG_EXTICR4_EXTI15_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_HARDWARE_STM32L0_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H */
diff --git a/arch/arm/src/stm32f0l0/stm32.h b/arch/arm/src/stm32f0l0g0/stm32.h
similarity index 93%
rename from arch/arm/src/stm32f0l0/stm32.h
rename to arch/arm/src/stm32f0l0g0/stm32.h
index 20bac988fd2..13a0a2d666f 100644
--- a/arch/arm/src/stm32f0l0/stm32.h
+++ b/arch/arm/src/stm32f0l0g0/stm32.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/stm32.h
+ * arch/arm/src/stm32f0l0g0/stm32.h
  *
  *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_H
-#define __ARCH_ARM_SRC_STM32F0L0_STM32_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_H
 
 /************************************************************************************
  * Included Files
@@ -62,5 +62,6 @@
 #include "stm32_spi.h"
 #include "stm32_uart.h"
 #include "stm32_lowputc.h"
+#include "stm32_adc.h"
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_H */
diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.c b/arch/arm/src/stm32f0l0g0/stm32_adc.c
new file mode 100644
index 00000000000..2bcbe7bc51b
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/stm32_adc.c
@@ -0,0 +1,2400 @@
+/****************************************************************************
+ * arch/arm/src/stm32/stm32_adc.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "stm32.h"
+#include "stm32_dma.h"
+#include "stm32_adc.h"
+
+/* STM32 ADC "lower-half" support must be enabled */
+
+#ifdef CONFIG_STM32F0L0G0_ADC
+
+/* Some ADC peripheral must be enabled */
+
+#if defined(CONFIG_STM32F0L0G0_ADC1)
+
+#if !defined(CONFIG_STM32F0L0G0_STM32L0)
+#  error Only L0 supported for now
+#endif
+
+/* At the moment there is no proper implementation for timers external
+ * trigger.
+ */
+
+#if defined(ADC_HAVE_TIMER)
+#  error not supported yet
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* RCC reset ****************************************************************/
+
+#define STM32_RCC_RSTR      STM32_RCC_APB2RSTR
+#define RCC_RSTR_ADC1RST    RCC_APB2RSTR_ADC1RST
+
+/* ADC Channels/DMA ********************************************************/
+/* The maximum number of channels that can be sampled.  If DMA support is
+ * not enabled, then only a single channel can be sampled.  Otherwise,
+ * data overruns would occur.
+ */
+
+#define ADC_MAX_CHANNELS_DMA   16
+#define ADC_MAX_CHANNELS_NODMA 1
+
+#ifdef ADC_HAVE_DMA
+#  define ADC_MAX_SAMPLES ADC_MAX_CHANNELS_DMA
+#else
+#  define ADC_MAX_SAMPLES ADC_MAX_CHANNELS_NODMA
+#endif
+
+/* DMA channels and interface values differs according to STM32 DMA IP core version */
+
+#if  defined(HAVE_IP_DMA_V1)
+#  define ADC_DMA_CONTROL_WORD (DMA_CCR_MSIZE_16BITS | \
+                                DMA_CCR_PSIZE_16BITS | \
+                                DMA_CCR_MINC | \
+                                DMA_CCR_CIRC)
+#else
+#  error Not supported
+#endif
+
+/* Sample time default configuration */
+
+/* G0 support additional sample time selection 2 */
+
+#if defined(CONFIG_STM32F0L0G0_STM32G0)
+#  define ADC_HAVE_SMPR_SMP2
+#endif
+
+#if defined(ADC_HAVE_DMA) || (ADC_MAX_SAMPLES == 1)
+#  define ADC_SMP1_DEFAULT    ADC_SMPR_13p5
+#  define ADC_SMP2_DEFAULT    ADC_SMPR_13p5
+#else /* Slow down sampling frequency */
+#  define ADC_SMP1_DEFAULT    ADC_SMPR_239p5
+#  define ADC_SMP2_DEFAULT    ADC_SMPR_239p5
+#endif
+
+#ifdef ADC_HAVE_SMPR_SMP2
+#  define ADC_SMPSEL_DEFAULT  0 /* For now we use only SMP1 */
+#endif
+
+/* Number of channels per ADC:
+ *   - F0, L0, G0 - 19, but singe SMP for all channels
+ *
+ * NOTE: this value can be obtained from SMPRx register description (ST manual)
+ */
+
+#if defined(CONFIG_STM32F0L0G0_STM32F0) || defined(CONFIG_STM32F0L0G0_STM32L0)
+#  define ADC_CHANNELS_NUMBER 19
+#else
+#  error "Not supported"
+#endif
+
+/* ADC resolution */
+
+#define HAVE_ADC_RESOLUTION
+
+/* ADC have common registers but only single ADC */
+
+#define HAVE_ADC_CMN_REGS 1
+
+/* ADCx_EXTSEL_VALUE */
+
+#ifdef ADC1_EXTSEL_VALUE
+#  define ADC1_HAVE_EXTCFG  1
+#  define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT)
+#else
+#  undef ADC1_HAVE_EXTCFG
+#endif
+
+#if defined(ADC1_HAVE_EXTCFG)
+#  define ADC_HAVE_EXTCFG
+#endif
+
+/* ADC DMA configuration bit support */
+
+#define ADC_HAVE_DMACFG 1
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* Data common to all ADC instances */
+
+#ifdef HAVE_ADC_CMN_DATA
+struct adccmn_data_s
+{
+  uint8_t initialized; /* How many ADC instances are currently in use */
+  sem_t   lock;        /* Exclusive access to common ADC data */
+};
+#endif
+
+/* This structure describes the state of one ADC block
+ * REVISIT: save some space with bit fields.
+ */
+
+struct stm32_dev_s
+{
+#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
+  FAR const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */
+#endif
+#if !defined(CONFIG_STM32F0L0G0_ADC_NOIRQ) | defined(ADC_HAVE_DMA)
+  FAR const struct adc_callback_s *cb;
+  uint8_t irq;               /* Interrupt generated by this ADC block */
+#endif
+#ifdef HAVE_ADC_CMN_DATA
+  struct adccmn_data_s *cmn; /* Common ADC data */
+#endif
+  uint8_t rnchannels;        /* Number of regular channels */
+  uint8_t cr_channels;       /* Number of configured regular channels */
+  uint8_t intf;              /* ADC interface number */
+  uint8_t current;           /* Current ADC channel being converted */
+#ifdef HAVE_ADC_RESOLUTION
+  uint8_t resolution;        /* ADC resolution (0-3) */
+#endif
+#ifdef ADC_HAVE_DMA
+  uint8_t dmachan;           /* DMA channel needed by this ADC */
+#  ifdef ADC_HAVE_DMACFG
+  uint8_t dmacfg;            /* DMA channel configuration, only for ADC IPv2 */
+#  endif
+  bool    hasdma;            /* True: This channel supports DMA */
+#endif
+#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
+  /* Sample time selection. These bits must be written only when ADON=0.
+   * REVISIT: this takes too much space. We need only 3 bits per channel.
+   */
+
+  uint8_t sample_rate[ADC_CHANNELS_NUMBER];
+  uint8_t adc_channels;      /* ADC channels number */
+#endif
+#ifdef ADC_HAVE_TIMER
+  uint8_t trigger;           /* Timer trigger channel: 0=CC1, 1=CC2, 2=CC3,
+                              * 3=CC4, 4=TRGO */
+#endif
+  xcpt_t   isr;              /* Interrupt handler for this ADC block */
+  uint32_t base;             /* Base address of registers unique to this ADC
+                              * block */
+#ifdef ADC_HAVE_EXTCFG
+  uint32_t extcfg;           /* External event configuration for regular group */
+#endif
+#ifdef ADC_HAVE_TIMER
+  uint32_t tbase;            /* Base address of timer used by this ADC block */
+  uint32_t pclck;            /* The PCLK frequency that drives this timer */
+  uint32_t freq;             /* The desired frequency of conversions */
+#endif
+#ifdef ADC_HAVE_DMA
+  DMA_HANDLE dma;            /* Allocated DMA channel */
+
+  /* DMA transfer buffer */
+
+  uint16_t r_dmabuffer[ADC_MAX_SAMPLES];
+#endif
+
+  /* List of selected ADC channels to sample */
+
+  uint8_t  r_chanlist[ADC_MAX_SAMPLES];
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* ADC Register access */
+
+static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
+                              uint32_t setbits);
+static uint32_t adc_getreg(FAR struct stm32_dev_s *priv, int offset);
+static void adc_putreg(FAR struct stm32_dev_s *priv, int offset,
+                       uint32_t value);
+static void adc_modifyreg(FAR struct stm32_dev_s *priv, int offset,
+                          uint32_t clrbits, uint32_t setbits);
+#ifdef HAVE_ADC_CMN_REGS
+static uint32_t adccmn_base_get(FAR struct stm32_dev_s *priv);
+static void adccmn_modifyreg(FAR struct stm32_dev_s *priv, uint32_t offset,
+                              uint32_t clrbits, uint32_t setbits);
+#  ifdef CONFIG_DEBUG_ANALOG_INFO
+static uint32_t adccmn_getreg(FAR struct stm32_dev_s *priv, uint32_t offset);
+#  endif
+#endif
+#ifdef ADC_HAVE_TIMER
+static uint16_t tim_getreg(FAR struct stm32_dev_s *priv, int offset);
+static void tim_putreg(FAR struct stm32_dev_s *priv, int offset,
+                       uint16_t value);
+static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset,
+                          uint16_t clrbits, uint16_t setbits);
+static void tim_dumpregs(FAR struct stm32_dev_s *priv,
+                             FAR const char *msg);
+#endif
+
+#ifdef HAVE_ADC_CMN_DATA
+static int  adccmn_lock(FAR struct stm32_dev_s *priv, bool lock);
+#endif
+
+static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset);
+
+/* ADC Interrupt Handler */
+
+#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
+static int  adc_interrupt(FAR struct adc_dev_s *dev);
+static int  adc1_interrupt(int irq, FAR void *context, FAR void *arg);
+#endif  /* CONFIG_STM32F0L0G0_ADC_NOIRQ */
+
+/* ADC Driver Methods */
+
+static int  adc_bind(FAR struct adc_dev_s *dev,
+                     FAR const struct adc_callback_s *callback);
+static void adc_reset(FAR struct adc_dev_s *dev);
+static int  adc_setup(FAR struct adc_dev_s *dev);
+static void adc_shutdown(FAR struct adc_dev_s *dev);
+static void adc_rxint(FAR struct adc_dev_s *dev, bool enable);
+static int  adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg);
+static void adc_enable(FAR struct stm32_dev_s *priv, bool enable);
+
+static int  adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch);
+
+static int  adc_ioc_change_ints(FAR struct adc_dev_s *dev, int cmd,
+                                bool arg);
+
+#ifdef HAVE_ADC_RESOLUTION
+static int  adc_resolution_set(FAR struct adc_dev_s *dev, uint8_t res);
+#endif
+#ifdef HAVE_ADC_VBAT
+static void adc_enable_vbat_channel(FAR struct adc_dev_s *dev, bool enable);
+#endif
+#ifdef HAVE_ADC_POWERDOWN
+static int  adc_ioc_change_sleep_between_opers(FAR struct adc_dev_s *dev,
+                                               int cmd, bool arg);
+static void adc_power_down_idle(FAR struct stm32_dev_s *priv,
+                                bool pdi_high);
+static void adc_power_down_delay(FAR struct stm32_dev_s *priv,
+                                 bool pdd_high);
+#endif
+
+#ifdef ADC_HAVE_TIMER
+static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable);
+static int  adc_timinit(FAR struct stm32_dev_s *priv);
+#endif
+
+#if defined(ADC_HAVE_DMA)
+static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr,
+                                FAR void *arg);
+#endif
+
+static void adc_reg_startconv(FAR struct stm32_dev_s *priv, bool enable);
+
+#ifdef ADC_HAVE_EXTCFG
+static int adc_extcfg_set(FAR struct adc_dev_s *dev, uint32_t extcfg);
+#endif
+
+static void adc_dumpregs(FAR struct stm32_dev_s *priv);
+
+#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
+static void adc_llops_intack(FAR struct stm32_adc_dev_s *dev, uint32_t source);
+static void adc_llops_inten(FAR struct stm32_adc_dev_s *dev, uint32_t source);
+static void adc_llops_intdis(FAR struct stm32_adc_dev_s *dev, uint32_t source);
+static uint32_t adc_llops_intget(FAR struct stm32_adc_dev_s *dev);
+static uint32_t adc_llops_regget(FAR struct stm32_adc_dev_s *dev);
+static void adc_llops_reg_startconv(FAR struct stm32_adc_dev_s *dev, bool enable);
+#  ifdef ADC_HAVE_DMA
+static int adc_llops_regbufregister(FAR struct stm32_adc_dev_s *dev,
+                                    uint16_t *buffer, uint8_t len);
+#  endif
+#  ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
+static void adc_sampletime_set(FAR struct stm32_adc_dev_s *dev,
+                               FAR struct adc_sample_time_s *time_samples);
+static void adc_sampletime_write(FAR struct stm32_adc_dev_s *dev);
+#  endif
+static void adc_llops_dumpregs(FAR struct stm32_adc_dev_s *dev);
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* ADC interface operations */
+
+static const struct adc_ops_s g_adcops =
+{
+  .ao_bind        = adc_bind,
+  .ao_reset       = adc_reset,
+  .ao_setup       = adc_setup,
+  .ao_shutdown    = adc_shutdown,
+  .ao_rxint       = adc_rxint,
+  .ao_ioctl       = adc_ioctl,
+};
+
+/* Publicly visible ADC lower-half operations */
+
+#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
+static const struct stm32_adc_ops_s g_adc_llops =
+{
+  .int_ack       = adc_llops_intack,
+  .int_get       = adc_llops_intget,
+  .int_en        = adc_llops_inten,
+  .int_dis       = adc_llops_intdis,
+  .val_get       = adc_llops_regget,
+  .reg_startconv = adc_llops_reg_startconv,
+#  ifdef ADC_HAVE_DMA
+  .regbuf_reg    = adc_llops_regbufregister,
+#  endif
+#  ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
+  .stime_set     = adc_sampletime_set,
+  .stime_write   = adc_sampletime_write,
+#  endif
+  .dump_regs     = adc_llops_dumpregs
+};
+#endif
+
+/* ADC1 state */
+
+#ifdef CONFIG_STM32F0L0G0_ADC1
+static struct stm32_dev_s g_adcpriv1 =
+{
+#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
+  .llops       = &g_adc_llops,
+#endif
+#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
+  .irq         = STM32_IRQ_ADC,
+  .isr         = adc1_interrupt,
+#endif  /* CONFIG_STM32F0L0G0_ADC_NOIRQ */
+#ifdef HAVE_ADC_CMN_DATA
+  .cmn         = &ADC1CMN_DATA,
+#endif
+  .intf        = 1,
+#ifdef HAVE_ADC_RESOLUTION
+  .resolution  = CONFIG_STM32F0L0G0_ADC1_RESOLUTION,
+#endif
+  .base        = STM32_ADC1_BASE,
+#ifdef ADC1_HAVE_EXTCFG
+  .extcfg      = ADC1_EXTCFG_VALUE,
+#endif
+#ifdef ADC1_HAVE_TIMER
+  .trigger     = CONFIG_STM32F0L0G0_ADC1_TIMTRIG,
+  .tbase       = ADC1_TIMER_BASE,
+  .pclck       = ADC1_TIMER_PCLK_FREQUENCY,
+  .freq        = CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY,
+#endif
+#ifdef ADC1_HAVE_DMA
+  .dmachan     = ADC1_DMA_CHAN,
+#  ifdef ADC_HAVE_DMACFG
+  .dmacfg      = CONFIG_STM32F0L0G0_ADC1_DMA_CFG,
+#  endif
+  .hasdma      = true,
+#endif
+};
+
+static struct adc_dev_s g_adcdev1 =
+{
+  .ad_ops      = &g_adcops,
+  .ad_priv     = &g_adcpriv1,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_modifyreg32
+ *
+ * Description:
+ *   Modify the value of a 32-bit register (not atomic).
+ *
+ * Input Parameters:
+ *   addr    - The address of the register
+ *   clrbits - The bits to clear
+ *   setbits - The bits to set
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
+                              uint32_t setbits)
+{
+  putreg32((getreg32(addr) & ~clrbits) | setbits, addr);
+}
+
+/****************************************************************************
+ * Name: adc_getreg
+ *
+ * Description:
+ *   Read the value of an ADC register.
+ *
+ * Input Parameters:
+ *   priv   - A reference to the ADC block status
+ *   offset - The offset to the register to read
+ *
+ * Returned Value:
+ *   The current contents of the specified register
+ *
+ ****************************************************************************/
+
+static uint32_t adc_getreg(FAR struct stm32_dev_s *priv, int offset)
+{
+  return getreg32(priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: adc_putreg
+ *
+ * Description:
+ *   Write a value to an ADC register.
+ *
+ * Input Parameters:
+ *   priv   - A reference to the ADC block status
+ *   offset - The offset to the register to write to
+ *   value  - The value to write to the register
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void adc_putreg(FAR struct stm32_dev_s *priv, int offset,
+                       uint32_t value)
+{
+  putreg32(value, priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: adc_modifyreg
+ *
+ * Description:
+ *   Modify the value of an ADC register (not atomic).
+ *
+ * Input Parameters:
+ *   priv    - A reference to the ADC block status
+ *   offset  - The offset to the register to modify
+ *   clrbits - The bits to clear
+ *   setbits - The bits to set
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void adc_modifyreg(FAR struct stm32_dev_s *priv, int offset,
+                          uint32_t clrbits, uint32_t setbits)
+{
+  adc_putreg(priv, offset, (adc_getreg(priv, offset) & ~clrbits) | setbits);
+}
+
+#ifdef HAVE_ADC_CMN_REGS
+
+/****************************************************************************
+ * Name: adccmn_base_get
+ ****************************************************************************/
+
+static uint32_t adccmn_base_get(FAR struct stm32_dev_s *priv)
+{
+  uint32_t base = 0;
+
+  if (priv->base == STM32_ADC1_BASE)
+    {
+      base = STM32_ADC12CMN_BASE;
+    }
+
+  return base;
+}
+
+/****************************************************************************
+ * Name: adccmn_modifyreg
+ ****************************************************************************/
+
+static void adccmn_modifyreg(FAR struct stm32_dev_s *priv, uint32_t offset,
+                              uint32_t clrbits, uint32_t setbits)
+{
+  uint32_t base = 0;
+
+  /* Get base address for ADC common register */
+
+  base = adccmn_base_get(priv);
+
+  /* Modify register */
+
+  stm32_modifyreg32(offset + base, clrbits, setbits);
+}
+
+/****************************************************************************
+ * Name: adccmn_getreg
+ ****************************************************************************/
+
+#  ifdef CONFIG_DEBUG_ANALOG_INFO
+static uint32_t adccmn_getreg(FAR struct stm32_dev_s *priv, uint32_t offset)
+{
+  uint32_t base = 0;
+
+  /* Get base address for ADC common register */
+
+  base = adccmn_base_get(priv);
+
+  /* Return register value */
+
+  return getreg32(base+offset);
+}
+#  endif
+#endif  /* HAVE_ADC_CMN_REGS */
+
+/****************************************************************************
+ * Name: tim_getreg
+ *
+ * Description:
+ *   Read the value of an ADC timer register.
+ *
+ * Input Parameters:
+ *   priv   - A reference to the ADC block status
+ *   offset - The offset to the register to read
+ *
+ * Returned Value:
+ *   The current contents of the specified register
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static uint16_t tim_getreg(FAR struct stm32_dev_s *priv, int offset)
+{
+  return getreg16(priv->tbase + offset);
+}
+#endif
+
+/****************************************************************************
+ * Name: tim_putreg
+ *
+ * Description:
+ *   Write a value to an ADC timer register.
+ *
+ * Input Parameters:
+ *   priv   - A reference to the ADC block status
+ *   offset - The offset to the register to write to
+ *   value  - The value to write to the register
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static void tim_putreg(FAR struct stm32_dev_s *priv, int offset,
+                       uint16_t value)
+{
+  putreg16(value, priv->tbase + offset);
+}
+#endif
+
+/****************************************************************************
+ * Name: tim_modifyreg
+ *
+ * Description:
+ *   Modify the value of an ADC timer register (not atomic).
+ *
+ * Input Parameters:
+ *   priv    - A reference to the ADC block status
+ *   offset  - The offset to the register to modify
+ *   clrbits - The bits to clear
+ *   setbits - The bits to set
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static void tim_modifyreg(FAR struct stm32_dev_s *priv, int offset,
+                          uint16_t clrbits, uint16_t setbits)
+{
+  tim_putreg(priv, offset, (tim_getreg(priv, offset) & ~clrbits) | setbits);
+}
+#endif
+
+/****************************************************************************
+ * Name: tim_dumpregs
+ *
+ * Description:
+ *   Dump all timer registers.
+ *
+ * Input Parameters:
+ *   priv - A reference to the ADC block status
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static void tim_dumpregs(FAR struct stm32_dev_s *priv, FAR const char *msg)
+{
+  ainfo("%s:\n", msg);
+  ainfo("  CR1: %04x CR2:  %04x SMCR:  %04x DIER:  %04x\n",
+        tim_getreg(priv, STM32_GTIM_CR1_OFFSET),
+        tim_getreg(priv, STM32_GTIM_CR2_OFFSET),
+        tim_getreg(priv, STM32_GTIM_SMCR_OFFSET),
+        tim_getreg(priv, STM32_GTIM_DIER_OFFSET));
+  ainfo("   SR: %04x EGR:  0000 CCMR1: %04x CCMR2: %04x\n",
+        tim_getreg(priv, STM32_GTIM_SR_OFFSET),
+        tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
+        tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
+  ainfo(" CCER: %04x CNT:  %04x PSC:   %04x ARR:   %04x\n",
+        tim_getreg(priv, STM32_GTIM_CCER_OFFSET),
+        tim_getreg(priv, STM32_GTIM_CNT_OFFSET),
+        tim_getreg(priv, STM32_GTIM_PSC_OFFSET),
+        tim_getreg(priv, STM32_GTIM_ARR_OFFSET));
+  ainfo(" CCR1: %04x CCR2: %04x CCR3:  %04x CCR4:  %04x\n",
+        tim_getreg(priv, STM32_GTIM_CCR1_OFFSET),
+        tim_getreg(priv, STM32_GTIM_CCR2_OFFSET),
+        tim_getreg(priv, STM32_GTIM_CCR3_OFFSET),
+        tim_getreg(priv, STM32_GTIM_CCR4_OFFSET));
+#if STM32_NATIM > 0
+  if (priv->tbase == STM32_TIM1_BASE)
+    {
+      ainfo("  RCR: %04x BDTR: %04x DCR:   %04x DMAR:  %04x\n",
+            tim_getreg(priv, STM32_ATIM_RCR_OFFSET),
+            tim_getreg(priv, STM32_ATIM_BDTR_OFFSET),
+            tim_getreg(priv, STM32_ATIM_DCR_OFFSET),
+            tim_getreg(priv, STM32_ATIM_DMAR_OFFSET));
+    }
+  else
+#endif
+    {
+      ainfo("  DCR: %04x DMAR: %04x\n",
+            tim_getreg(priv, STM32_GTIM_DCR_OFFSET),
+            tim_getreg(priv, STM32_GTIM_DMAR_OFFSET));
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_timstart
+ *
+ * Description:
+ *   Start (or stop) the timer counter
+ *
+ * Input Parameters:
+ *   priv - A reference to the ADC block status
+ *   enable - True: Start conversion
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable)
+{
+  ainfo("enable: %d\n", enable ? 1 : 0);
+
+  if (enable)
+    {
+      /* Start the counter */
+
+      tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN);
+    }
+  else
+    {
+      /* Disable the counter */
+
+      tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0);
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_timinit
+ *
+ * Description:
+ *   Initialize the timer that drivers the ADC sampling for this channel
+ *   using the pre-calculated timer divider definitions.
+ *
+ * Input Parameters:
+ *   priv - A reference to the ADC block status
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_TIMER
+static int adc_timinit(FAR struct stm32_dev_s *priv)
+{
+#warning TODO: adc_timinit
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_reg_startconv
+ *
+ * Description:
+ *   Start (or stop) the ADC regular conversion process
+ *
+ * Input Parameters:
+ *   priv - A reference to the ADC block status
+ *   enable - True: Start conversion
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static void adc_reg_startconv(FAR struct stm32_dev_s *priv, bool enable)
+{
+  uint32_t regval;
+
+  ainfo("reg enable: %d\n", enable ? 1 : 0);
+
+  if (enable)
+    {
+      /* Start the conversion of regular channels */
+
+      adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_ADSTART);
+    }
+  else
+    {
+      regval = adc_getreg(priv, STM32_ADC_CR_OFFSET);
+
+      /* Is a conversion ongoing? */
+
+      if ((regval & ADC_CR_ADSTART) != 0)
+        {
+          /* Stop the conversion */
+
+          adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADSTP);
+
+          /* Wait for the conversion to stop */
+
+          while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADSTP) != 0);
+        }
+    }
+}
+
+/****************************************************************************
+ * Name: adccmn_lock
+ ****************************************************************************/
+
+#ifdef HAVE_ADC_CMN_DATA
+static int adccmn_lock(FAR struct stm32_dev_s *priv, bool lock)
+{
+  int ret;
+
+  if (lock)
+    {
+      /* Take the semaphore (perhaps waiting) */
+
+      do
+        {
+          ret = nxsem_wait(&priv->cmn->lock);
+
+          /* The only case that an error should occur here is if the wait
+           * was awakened by a signal.
+           */
+
+          DEBUGASSERT(ret == OK || ret == -EINTR);
+        }
+      while (ret == -EINTR);
+    }
+  else
+    {
+      (void)nxsem_post(&priv->cmn->lock);
+      ret = OK;
+    }
+
+  return ret;
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_rccreset
+ *
+ * Description:
+ *   Deinitializes the ADCx peripheral registers to their default
+ *   reset values. It could set all the ADCs configured.
+ *
+ * Input Parameters:
+ *   regaddr - The register to read
+ *   reset - Condition, set or reset
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static void adc_rccreset(FAR struct stm32_dev_s *priv, bool reset)
+{
+  uint32_t adcbit;
+
+  /* Pick the appropriate bit in the RCC reset register.
+   * For the STM32 ADC IPv2, there is an individual bit to reset each ADC block.
+   */
+
+  switch (priv->intf)
+    {
+#if defined(CONFIG_STM32F0L0G0_ADC1)
+      case 1:
+        {
+          adcbit = RCC_RSTR_ADC1RST;
+          break;
+        }
+#endif
+      default:
+        {
+          return;
+        }
+    }
+
+  /* Set or clear the selected bit in the RCC reset register */
+
+  if (reset)
+    {
+      /* Enable ADC reset state */
+
+      modifyreg32(STM32_RCC_RSTR, 0, adcbit);
+    }
+  else
+    {
+      /* Release ADC from reset state */
+
+      modifyreg32(STM32_RCC_RSTR, adcbit, 0);
+    }
+}
+
+/****************************************************************************
+ * Name: adc_enable
+ *
+ * Description:
+ *   Enables or disables the specified ADC peripheral.  Also, starts a
+ *   conversion when the ADC is not triggered by timers
+ *
+ * Input Parameters:
+ *
+ *   enable - true:  enable ADC conversion
+ *            false: disable ADC conversion
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static void adc_enable(FAR struct stm32_dev_s *priv, bool enable)
+{
+  uint32_t regval;
+
+  ainfo("enable: %d\n", enable ? 1 : 0);
+
+  regval = adc_getreg(priv, STM32_ADC_CR_OFFSET);
+
+  if (enable)
+    {
+      /* Enable the ADC */
+
+      adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADEN);
+
+      /* Wait for the ADC to be ready */
+
+      while ((adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_ARDY) == 0);
+    }
+  else if ((regval & ADC_CR_ADEN) != 0 && (regval & ADC_CR_ADDIS) == 0)
+    {
+      /* Stop ongoing regular conversions */
+
+      adc_reg_startconv(priv, false);
+
+      /* Disable the ADC */
+
+      adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_ADDIS);
+
+      /* Wait for the ADC to be disabled */
+
+      while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADEN) != 0);
+    }
+}
+
+/****************************************************************************
+ * Name: adc_dmaconvcallback
+ *
+ * Description:
+ *   Callback for DMA.  Called from the DMA transfer complete interrupt after
+ *   all channels have been converted and transferred with DMA.
+ *
+ * Input Parameters:
+ *
+ *   handle - handle to DMA
+ *   isr -
+ *   arg - adc device
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+#if defined(ADC_HAVE_DMA)
+static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
+{
+  FAR struct adc_dev_s   *dev  = (FAR struct adc_dev_s *)arg;
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+  int i;
+
+  /* Verify that the upper-half driver has bound its callback functions */
+
+  if (priv->cb != NULL)
+    {
+      DEBUGASSERT(priv->cb->au_receive != NULL);
+
+      for (i = 0; i < priv->rnchannels; i++)
+        {
+          priv->cb->au_receive(dev, priv->r_chanlist[priv->current],
+                               priv->r_dmabuffer[priv->current]);
+          priv->current++;
+          if (priv->current >= priv->rnchannels)
+            {
+              /* Restart the conversion sequence from the beginning */
+
+              priv->current = 0;
+            }
+        }
+    }
+
+  /* Restart DMA for the next conversion series */
+
+  adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, ADC_DMAREG_DMA, 0);
+  adc_modifyreg(priv, STM32_ADC_DMAREG_OFFSET, 0, ADC_DMAREG_DMA);
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_bind
+ *
+ * Description:
+ *   Bind the upper-half driver callbacks to the lower-half implementation.
+ *   This must be called early in order to receive ADC event notifications.
+ *
+ ****************************************************************************/
+
+static int adc_bind(FAR struct adc_dev_s *dev,
+                    FAR const struct adc_callback_s *callback)
+{
+#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+
+  DEBUGASSERT(priv != NULL);
+  priv->cb = callback;
+#endif
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: adc_watchdog_cfg
+ ****************************************************************************/
+
+static void adc_watchdog_cfg(FAR struct stm32_dev_s *priv)
+{
+  uint32_t clrbits = 0;
+  uint32_t setbits = 0;
+
+  uint32_t th = 0;
+
+  /* Initialize the watchdog high threshold register */
+
+  th |= 0x0fff << ADC_TR_HT_SHIFT;
+
+  /* Initialize the watchdog low threshold register */
+
+  th |= 0x0000 << ADC_TR_LT_SHIFT;
+
+  /* Write threshold register */
+
+  adc_putreg(priv, STM32_ADC_TR_OFFSET, th);
+
+  clrbits = ADC_CFGR1_AWDCH_MASK;
+  setbits = ADC_CFGR1_AWDEN | (priv->r_chanlist[0] << ADC_CFGR1_AWDCH_SHIFT);
+
+  /* Modify CFGR1 configuration */
+
+  adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits);
+}
+
+/****************************************************************************
+ * Name: adc_calibrate
+ ****************************************************************************/
+
+static void adc_calibrate(FAR struct stm32_dev_s *priv)
+{
+#if 0 /* Doesn't work */
+  /* Calibrate the ADC */
+
+  adc_modifyreg(priv, STM32_ADC_CR_OFFSET, ADC_CR_ADCALDIF, AD_CR_ADCAL);
+
+  /* Wait for the calibration to complete */
+
+  while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADCAL) != 0);
+
+#else
+  UNUSED(priv);
+#endif
+}
+
+/****************************************************************************
+ * Name: adc_mode_cfg
+ ****************************************************************************/
+
+static void adc_mode_cfg(FAR struct stm32_dev_s *priv)
+{
+  uint32_t clrbits = 0;
+  uint32_t setbits = 0;
+
+  /* Disable continuous mode and set align to right */
+
+  clrbits = ADC_CFGR1_CONT | ADC_CFGR1_ALIGN;
+
+  /* Disable external trigger for regular channels */
+
+  clrbits |= ADC_CFGR1_EXTEN_MASK;
+  setbits |= ADC_CFGR1_EXTEN_NONE;
+
+  /* Set CFGR configuration */
+
+  adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits);
+}
+
+/****************************************************************************
+ * Name: adc_voltreg_cfg
+ ****************************************************************************/
+
+static void adc_voltreg_cfg(FAR struct stm32_dev_s *priv)
+{
+  UNUSED(priv);
+}
+
+/****************************************************************************
+ * Name: adc_sampletime_cfg
+ ****************************************************************************/
+
+static void adc_sampletime_cfg(FAR struct adc_dev_s *dev)
+{
+  /* Initialize the same sample time for each ADC.
+   * During sample cycles channel selection bits must remain unchanged.
+   */
+
+#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
+  adc_sampletime_write((FAR struct stm32_adc_dev_s *)dev);
+#else
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+  uint32_t setbits = 0;
+
+  /* Configure sample time 1 */
+
+  setbits |= ADC_SMP1_DEFAULT << ADC_SMPR_SMP1_SHIFT;
+
+#  ifdef ADC_HAVE_SMPR_SMP2
+  /* Configure sample time 2 */
+
+  setbits |= ADC_SMP2_DEFAULT << ADC_SMPR_SMP2_SHIFT;
+
+  /* Configure sample time selection */
+
+  setbits |= ADC_SMPSEL_DEFAULT << ADC_SMPR_SMPSEL_SHIFT;
+#  endif
+
+  /* Write SMPR register */
+
+  adc_putreg(priv, STM32_ADC_SMPR_OFFSET, setbits);
+
+#endif
+}
+
+/****************************************************************************
+ * Name: adc_common_cfg
+ ****************************************************************************/
+
+static void adc_common_cfg(FAR struct stm32_dev_s *priv)
+{
+  uint32_t clrbits = 0;
+  uint32_t setbits = 0;
+
+  /* REVISIT: for now we reset all CCR bits */
+
+  clrbits |= ADC_CCR_VREFEN;
+  clrbits |= ADC_CCR_TSEN;
+
+#ifdef HAVE_ADC_VLCD
+  clrbits |= ADC_CCR_PRESC_MASK;
+#endif
+
+#ifdef HAVE_ADC_VLCD
+  clrbits |= ADC_CCR_VLCDEN;
+#endif
+
+#ifdef HAVE_ADC_LFM
+  clrbits |= ADC_CCR_LFMEN;
+#endif
+
+  setbits = 0;
+
+  adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, clrbits, setbits);
+}
+
+#ifdef ADC_HAVE_DMA
+/****************************************************************************
+ * Name: adc_dma_cfg
+ ****************************************************************************/
+
+static void adc_dma_cfg(FAR struct stm32_dev_s *priv)
+{
+  uint32_t clrbits = 0;
+  uint32_t setbits = 0;
+
+  /* Set DMA mode */
+
+  if (priv->dmacfg == 0)
+    {
+      /* One Shot Mode */
+
+      clrbits |= ADC_CFGR1_DMACFG;
+    }
+  else
+    {
+      /* Circular Mode */
+
+      setbits |= ADC_CFGR1_DMACFG;
+    }
+
+  /* Enable DMA */
+
+  setbits |= ADC_CFGR1_DMAEN;
+
+  /* Modify CFGR configuration */
+
+  adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, clrbits, setbits);
+}
+
+/****************************************************************************
+ * Name: adc_dma_start
+ ****************************************************************************/
+
+static void adc_dma_start(FAR struct adc_dev_s *dev)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+
+  /* Stop and free DMA if it was started before */
+
+  if (priv->dma != NULL)
+    {
+      stm32_dmastop(priv->dma);
+      stm32_dmafree(priv->dma);
+    }
+
+  priv->dma = stm32_dmachannel(priv->dmachan);
+
+  stm32_dmasetup(priv->dma,
+                 priv->base + STM32_ADC_DR_OFFSET,
+                 (uint32_t)priv->r_dmabuffer,
+                 priv->rnchannels,
+                 ADC_DMA_CONTROL_WORD);
+
+  stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false);
+}
+#endif  /* ADC_HAVE_DMA */
+
+/****************************************************************************
+ * Name: adc_configure
+ ****************************************************************************/
+
+static void adc_configure(FAR struct adc_dev_s *dev)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+
+  /* Turn off the ADC before configuration */
+
+  adc_enable(priv, false);
+
+  /* Configure voltage regulator if present */
+
+  adc_voltreg_cfg(priv);
+
+  /* Calibrate ADC - doesnt work for now */
+
+  adc_calibrate(priv);
+
+  /* Initialize the ADC watchdog */
+
+  adc_watchdog_cfg(priv);
+
+  /* Initialize the ADC sample time */
+
+  adc_sampletime_cfg(dev);
+
+  /* Set ADC working mode */
+
+  adc_mode_cfg(priv);
+
+  /* Configuration of the channel conversions */
+
+  if (priv->cr_channels > 0)
+    {
+      adc_set_ch(dev, 0);
+    }
+
+  /* ADC common register configuration */
+
+  adc_common_cfg(priv);
+
+#ifdef ADC_HAVE_DMA
+  /* Configure ADC DMA if enabled */
+
+  if (priv->hasdma)
+    {
+      /* Configure ADC DMA */
+
+      adc_dma_cfg(priv);
+
+      /* Start ADC DMA */
+
+      adc_dma_start(dev);
+    }
+#endif
+
+#ifdef HAVE_ADC_RESOLUTION
+  /* Configure ADC resolution */
+
+  (void)adc_resolution_set(dev, priv->resolution);
+#endif
+
+#ifdef ADC_HAVE_EXTCFG
+  /* Configure external event for regular group */
+
+  adc_extcfg_set(dev, priv->extcfg);
+#endif
+
+  /* Enable ADC */
+
+  adc_enable(priv, true);
+
+  /* Dump regs */
+
+  adc_dumpregs(priv);
+}
+
+/****************************************************************************
+ * Name: adc_reset
+ *
+ * Description:
+ *   Reset the ADC device.  Called early to initialize the hardware.
+ *   This is called, before adc_setup() and on error conditions.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static void adc_reset(FAR struct adc_dev_s *dev)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+  irqstate_t flags;
+
+  ainfo("intf: %d\n", priv->intf);
+  flags = enter_critical_section();
+
+#if defined(HAVE_IP_ADC_V2)
+  /* Turn off the ADC so we can write the RCC bits */
+
+  adc_enable(priv, false);
+#endif
+
+  /* Only if this is the first initialzied ADC instance in the ADC block */
+
+#ifdef HAVE_ADC_CMN_DATA
+  adccmn_lock(priv, true);
+
+  if (priv->cmn->initialized == 0)
+#endif
+    {
+      /* Enable ADC reset state */
+
+      adc_rccreset(priv, true);
+
+      /* Release ADC from reset state */
+
+      adc_rccreset(priv, false);
+    }
+
+#ifdef HAVE_ADC_CMN_DATA
+  adccmn_lock(priv, false);
+#endif
+
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: adc_setup
+ *
+ * Description:
+ *   Configure the ADC. This method is called the first time that the ADC
+ *   device is opened.  This will occur when the port is first opened.
+ *   This setup includes configuring and attaching ADC interrupts.
+ *   Interrupts are all disabled upon return.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static int adc_setup(FAR struct adc_dev_s *dev)
+{
+#if !defined(CONFIG_STM32F0L0G0_ADC_NOIRQ) || defined(HAVE_ADC_CMN_DATA) ||   \
+     defined(ADC_HAVE_TIMER) || !defined(CONFIG_STM32F0L0G0_ADC_NO_STARTUP_CONV)
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+#endif
+  int ret = OK;
+
+  /* Attach the ADC interrupt */
+
+#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
+  ret = irq_attach(priv->irq, priv->isr, NULL);
+  if (ret < 0)
+    {
+      ainfo("irq_attach failed: %d\n", ret);
+      return ret;
+    }
+#endif
+
+  /* Make sure that the ADC device is in the powered up, reset state */
+
+  adc_reset(dev);
+
+  /* Configure ADC device */
+
+  adc_configure(dev);
+
+#ifdef ADC_HAVE_TIMER
+  /* Configure timer */
+
+  if (priv->tbase != 0)
+    {
+      ret = adc_timinit(priv);
+      if (ret < 0)
+        {
+          aerr("ERROR: adc_timinit failed: %d\n", ret);
+        }
+    }
+#endif
+
+  /* As default conversion is started here.
+   *
+   * NOTE: for ADC IPv2 (J)ADSTART bit must be set to start ADC conversion
+   *       even if hardware trigger is selected.
+   *       This can be done here during the opening of the ADC device
+   *       or later with ANIOC_TRIGGER ioctl call.
+   */
+
+#ifndef CONFIG_STM32F0L0G0_ADC_NO_STARTUP_CONV
+  /* Start regular conversion */
+
+  adc_reg_startconv(priv, true);
+
+#endif
+
+  /* Enable the ADC interrupt */
+
+#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
+  ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq);
+  up_enable_irq(priv->irq);
+#endif
+
+#ifdef HAVE_ADC_CMN_DATA
+  /* Increase instances counter */
+
+  adccmn_lock(priv, true);
+  priv->cmn->initialized += 1;
+  adccmn_lock(priv, false);
+#endif
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: adc_shutdown
+ *
+ * Description:
+ *   Disable the ADC.  This method is called when the ADC device is closed.
+ *   This method reverses the operation the setup method.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static void adc_shutdown(FAR struct adc_dev_s *dev)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+
+  /* Disable ADC */
+
+  adc_enable(priv, false);
+
+#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
+  /* Disable ADC interrupts and detach the ADC interrupt handler */
+
+  up_disable_irq(priv->irq);
+  irq_detach(priv->irq);
+#endif
+
+#ifdef HAVE_ADC_CMN_DATA
+  adccmn_lock(priv, true);
+
+  if (priv->cmn->initialized <= 1)
+#endif
+    {
+      /* Disable and reset the ADC module.
+       *
+       * NOTE: The ADC block will be reset to its reset state only if all
+       *       ADC block instances are closed. This means that the closed ADC
+       *       may not be reset which in turn may affect low-power applications.
+       *       (But ADC is turned off here, is not that enough?)
+       */
+
+      adc_rccreset(priv, true);
+    }
+
+#ifdef ADC_HAVE_TIMER
+  /* Disable timer */
+
+  if (priv->tbase != 0)
+    {
+      adc_timstart(priv, false);
+    }
+#endif
+
+#ifdef HAVE_ADC_CMN_DATA
+  /* Decrease instances counter */
+
+  priv->cmn->initialized -= 1;
+
+  adccmn_lock(priv, false);
+#endif
+}
+
+/****************************************************************************
+ * Name: adc_rxint
+ *
+ * Description:
+ *   Call to enable or disable RX interrupts.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+  uint32_t regval;
+
+  ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0);
+
+  if (enable)
+    {
+      /* Enable the analog watchdog / overrun interrupts, and if no DMA,
+       * end-of-conversion ADC.
+       */
+
+      regval = ADC_IER_ALLINTS;
+#ifdef ADC_HAVE_DMA
+      if (priv->hasdma)
+        {
+          regval &= ~(ADC_IER_EOC);
+        }
+#endif
+
+      adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, regval);
+    }
+  else
+    {
+      /* Disable all ADC interrupts */
+
+      adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_ALLINTS, 0);
+    }
+}
+
+/****************************************************************************
+ * Name: adc_resolution_set
+ ****************************************************************************/
+
+#ifdef HAVE_ADC_RESOLUTION
+static int adc_resolution_set(FAR struct adc_dev_s *dev, uint8_t res)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+  int ret = OK;
+
+  /* Check input */
+
+  if (res > 3)
+    {
+      ret = -EINVAL;
+      goto errout;
+    }
+
+  /* Modify appropriate register */
+
+  adc_modifyreg(priv, STM32_ADC_CFGR1_OFFSET, ADC_CFGR1_RES_MASK,
+                res << ADC_CFGR1_RES_SHIFT);
+
+errout:
+  return ret;
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_extsel_set
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_EXTCFG
+static int adc_extcfg_set(FAR struct adc_dev_s *dev, uint32_t extcfg)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+  uint32_t exten  = 0;
+  uint32_t extsel = 0;
+  uint32_t setbits = 0;
+  uint32_t clrbits = 0;
+
+  /* Get EXTEN and EXTSEL from input */
+
+  exten = (extcfg & ADC_EXTREG_EXTEN_MASK);
+  extsel = (extcfg & ADC_EXTREG_EXTSEL_MASK);
+
+  /* EXTSEL selection: These bits select the external event used
+   * to trigger the start of conversion of a regular group.  NOTE:
+   *
+   * - The position with of the EXTSEL field varies from one STM32 MCU
+   *   to another.
+   * - The width of the EXTSEL field varies from one STM32 MCU to another.
+   */
+
+  if (exten > 0)
+    {
+      setbits = (extsel | exten);
+      clrbits = (ADC_EXTREG_EXTEN_MASK | ADC_EXTREG_EXTSEL_MASK);
+
+      ainfo("Initializing extsel = 0x%08x\n", extsel);
+
+      /* Write register */
+
+      adc_modifyreg(priv, STM32_ADC_EXTREG_OFFSET, clrbits, setbits);
+    }
+
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_dumpregs
+ ****************************************************************************/
+
+static void adc_dumpregs(FAR struct stm32_dev_s *priv)
+{
+  UNUSED(priv);
+
+  ainfo("ISR:  0x%08x IER:  0x%08x CR:   0x%08x CFGR1: 0x%08x\n",
+        adc_getreg(priv, STM32_ADC_ISR_OFFSET),
+        adc_getreg(priv, STM32_ADC_IER_OFFSET),
+        adc_getreg(priv, STM32_ADC_CR_OFFSET),
+        adc_getreg(priv, STM32_ADC_CFGR1_OFFSET));
+
+  ainfo("SMPR: 0x%08x CHSELR: 0x%08x\n",
+        adc_getreg(priv, STM32_ADC_SMPR_OFFSET),
+        adc_getreg(priv, STM32_ADC_CHSELR_OFFSET));
+
+  ainfo("CCR:  0x%08x\n", adccmn_getreg(priv, STM32_ADC_CCR_OFFSET));
+}
+
+/****************************************************************************
+ * Name: adc_enable_vbat_channel
+ *
+ * Description:
+ *   Enable/disable the Vbat voltage measurement channel.
+ *
+ * Input Parameters:
+ *   dev - pointer to device structure used by the driver
+ *   enable - true:  Vbat input channel enabled (ch 18)
+ *            false: Vbat input channel disabled (ch 18)
+ *
+ * Returned Value:
+ *   None.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_ADC_VBAT
+static void adc_enable_vbat_channel(FAR struct adc_dev_s *dev, bool enable)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+
+  if (enable)
+    {
+      adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, 0, ADC_CCR_VBATEN);
+    }
+  else
+    {
+      adccmn_modifyreg(priv, STM32_ADC_CCR_OFFSET, ADC_CCR_VBATEN, 0);
+    }
+
+  ainfo("STM32_ADC_CCR value: 0x%08x\n", adccmn_getreg(priv, STM32_ADC_CCR_OFFSET));
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_ioc_change_sleep_between_opers
+ *
+ * Description:
+ *   Changes PDI and PDD bits to save battery.
+ *
+ * Input Parameters:
+ *   dev - pointer to device structure used by the driver
+ *   cmd - command
+ *   arg - arguments passed with command
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_ADC_POWERDOWN
+static int adc_ioc_change_sleep_between_opers(FAR struct adc_dev_s *dev,
+                                              int cmd, bool arg)
+{
+  int ret = OK;
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+
+  adc_enable(priv, false);
+
+  switch (cmd)
+    {
+      case IO_ENABLE_DISABLE_PDI:
+        adc_power_down_idle(priv, arg);
+        break;
+
+      case IO_ENABLE_DISABLE_PDD:
+        adc_power_down_delay(priv, arg);
+        break;
+
+      case IO_ENABLE_DISABLE_PDD_PDI:
+        adc_power_down_idle(priv, arg);
+        adc_power_down_delay(priv, arg);
+        break;
+
+      default:
+        ainfo("unknown cmd: %d\n", cmd);
+        break;
+    }
+
+  adc_enable(priv, true);
+
+  return ret;
+}
+#endif
+
+/****************************************************************************
+ * Name: adc_ioc_enable_awd_int
+ *
+ * Description:
+ *   Turns ON/OFF ADC analog watchdog interrupt.
+ *
+ * Input Parameters:
+ *   dev - pointer to device structure used by the driver
+ *   arg - true:  Turn ON interrupt
+ *         false: Turn OFF interrupt
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static void adc_ioc_enable_awd_int(FAR struct stm32_dev_s *priv, bool enable)
+{
+  if (enable)
+    {
+      adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_AWD);
+    }
+  else
+    {
+      adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_AWD, 0);
+    }
+}
+
+/****************************************************************************
+ * Name: adc_ioc_enable_eoc_int
+ *
+ * Description:
+ *   Turns ON/OFF ADC EOC interrupt.
+ *
+ * Input Parameters:
+ *   dev - pointer to device structure used by the driver
+ *   arg - true:  Turn ON interrupt
+ *         false: Turn OFF interrupt
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static void adc_ioc_enable_eoc_int(FAR struct stm32_dev_s *priv, bool enable)
+{
+  if (enable)
+    {
+      adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_EOC);
+    }
+  else
+    {
+      adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_EOC, 0);
+    }
+}
+
+/****************************************************************************
+ * Name: adc_ioc_enable_ovr_int
+ *
+ * Description:
+ *   Turns ON/OFF ADC overrun interrupt.
+ *
+ * Input Parameters:
+ *   dev - pointer to device structure used by the driver
+ *   arg - true:  Turn ON interrupt
+ *         false: Turn OFF interrupt
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static void adc_ioc_enable_ovr_int(FAR struct stm32_dev_s *priv, bool enable)
+{
+  if (enable)
+    {
+      adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, ADC_IER_OVR);
+    }
+  else
+    {
+      adc_modifyreg(priv, STM32_ADC_IER_OFFSET, ADC_IER_OVR, 0);
+    }
+}
+
+/****************************************************************************
+ * Name: adc_ioc_change_ints
+ *
+ * Description:
+ *   Turns ON/OFF ADC interrupts.
+ *
+ * Input Parameters:
+ *   dev - pointer to device structure used by the driver
+ *   cmd - command
+ *   arg - arguments passed with command
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static int adc_ioc_change_ints(FAR struct adc_dev_s *dev, int cmd, bool arg)
+{
+  int ret = OK;
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+
+  switch (cmd)
+    {
+      case IO_ENABLE_DISABLE_AWDIE:
+        adc_ioc_enable_awd_int(priv, arg);
+        break;
+
+      case IO_ENABLE_DISABLE_EOCIE:
+        adc_ioc_enable_eoc_int(priv, arg);
+        break;
+
+      case IO_ENABLE_DISABLE_OVRIE:
+        adc_ioc_enable_ovr_int(priv, arg);
+        break;
+
+      case IO_ENABLE_DISABLE_ALL_INTS:
+        adc_ioc_enable_awd_int(priv, arg);
+        adc_ioc_enable_eoc_int(priv, arg);
+        adc_ioc_enable_ovr_int(priv, arg);
+        break;
+
+      default:
+        ainfo("unknown cmd: %d\n", cmd);
+        break;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: adc_set_ch
+ *
+ * Description:
+ *   Sets the ADC channel.
+ *
+ * Input Parameters:
+ *   dev - pointer to device structure used by the driver
+ *   ch  - ADC channel number + 1. 0 reserved for all configured channels
+ *
+ * Returned Value:
+ *   int - errno
+ *
+ ****************************************************************************/
+
+static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+  uint32_t bits = 0;
+  int      i    = 0;
+
+  if (ch == 0)
+    {
+      priv->current    = 0;
+      priv->rnchannels = priv->cr_channels;
+    }
+  else
+    {
+      for (i = 0; i < priv->cr_channels && priv->r_chanlist[i] != ch - 1; i++);
+
+      if (i >= priv->cr_channels)
+        {
+          return -ENODEV;
+        }
+
+      priv->current    = i;
+      priv->rnchannels = 1;
+    }
+
+
+  for (i = 0; i < priv->rnchannels; i+=1)
+    {
+      bits |= ADC_CHSELR_CHSEL(priv->r_chanlist[i]);
+    }
+
+  /* Write register */
+
+  adc_modifyreg(priv, STM32_ADC_CHSELR_OFFSET, 0, bits);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: adc_ioctl
+ *
+ * Description:
+ *   All ioctl calls will be routed through this method.
+ *
+ * Input Parameters:
+ *   dev - pointer to device structure used by the driver
+ *   cmd - command
+ *   arg - arguments passed with command
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+  int ret                      = OK;
+
+  switch (cmd)
+    {
+      case ANIOC_TRIGGER:
+        {
+          /* Start regular conversion if regular channels configured */
+
+          if (priv->cr_channels > 0)
+            {
+              adc_reg_startconv(priv, true);
+            }
+
+          break;
+        }
+
+      case IO_TRIGGER_REG:
+        {
+          /* Start regular conversion if regular channels configured */
+
+          if (priv->cr_channels > 0)
+            {
+              adc_reg_startconv(priv, true);
+            }
+
+          break;
+        }
+
+      case IO_ENABLE_DISABLE_AWDIE:
+      case IO_ENABLE_DISABLE_EOCIE:
+      case IO_ENABLE_DISABLE_OVRIE:
+      case IO_ENABLE_DISABLE_ALL_INTS:
+        {
+          adc_ioc_change_ints(dev, cmd, *(bool *)arg);
+          break;
+        }
+
+#ifdef HAVE_ADC_VBAT
+      case IO_ENABLE_DISABLE_VBAT_CH:
+        {
+          adc_enable_vbat_channel(dev, *(bool *)arg);
+          break;
+        }
+#endif
+
+#ifdef HAVE_ADC_POWERDOWN
+      case IO_ENABLE_DISABLE_PDI:
+      case IO_ENABLE_DISABLE_PDD:
+      case IO_ENABLE_DISABLE_PDD_PDI:
+        {
+          adc_ioc_change_sleep_between_opers(dev, cmd, *(bool *)arg);
+          break;
+        }
+#endif
+
+      case IO_STOP_ADC:
+        {
+          adc_enable(priv, false);
+          break;
+        }
+
+      case IO_START_ADC:
+        {
+          adc_enable(priv, true);
+          break;
+        }
+
+      case IO_START_CONV:
+        {
+          uint8_t ch = ((uint8_t)arg);
+
+          ret = adc_set_ch(dev, ch);
+          if (ret < 0)
+            {
+              return ret;
+            }
+
+#ifdef CONFIG_ADC
+          if (ch)
+            {
+              /* Clear fifo if upper-half driver enabled */
+
+              dev->ad_recv.af_head = 0;
+              dev->ad_recv.af_tail = 0;
+            }
+#endif
+
+          adc_reg_startconv(priv, true);
+          break;
+        }
+
+      default:
+        {
+          aerr("ERROR: Unknown cmd: %d\n", cmd);
+          ret = -ENOTTY;
+          break;
+        }
+    }
+
+  return ret;
+}
+
+#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ
+
+/****************************************************************************
+ * Name: adc_interrupt
+ *
+ * Description:
+ *   Common ADC interrupt handler.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static int adc_interrupt(FAR struct adc_dev_s *dev)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+  uint32_t regval;
+  uint32_t pending;
+  int32_t  data;
+
+  regval  = adc_getreg(priv, STM32_ADC_ISR_OFFSET);
+  pending = regval & ADC_ISR_ALLINTS;
+  if (pending == 0)
+    {
+      return OK;
+    }
+
+  /* Identifies the interruption AWD, OVR or EOC */
+
+  if ((regval & ADC_ISR_AWD) != 0)
+    {
+      awarn("WARNING: Analog Watchdog, Value converted out of range!\n");
+    }
+
+  if ((regval & ADC_ISR_OVR) != 0)
+    {
+      awarn("WARNING: Overrun has occurred!\n");
+    }
+
+  /* EOC: End of conversion */
+
+  if ((regval & ADC_ISR_EOC) != 0)
+    {
+      /* Read the converted value and clear EOC bit
+       * (It is cleared by reading the ADC_DR)
+       */
+
+      data = adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_RDATA_MASK;
+
+      /* Verify that the upper-half driver has bound its callback functions */
+
+      if (priv->cb != NULL)
+        {
+          /* Give the ADC data to the ADC driver.  The ADC receive() method
+           * accepts 3 parameters:
+           *
+           * 1) The first is the ADC device instance for this ADC block.
+           * 2) The second is the channel number for the data, and
+           * 3) The third is the converted data for the channel.
+           */
+
+          DEBUGASSERT(priv->cb->au_receive != NULL);
+          priv->cb->au_receive(dev, priv->r_chanlist[priv->current], data);
+        }
+
+      /* Set the channel number of the next channel that will complete
+       * conversion.
+       */
+
+      priv->current++;
+
+      if (priv->current >= priv->rnchannels)
+        {
+          /* Restart the conversion sequence from the beginning */
+
+          priv->current = 0;
+        }
+    }
+
+  /* Clear pending interrupts */
+
+  adc_putreg(priv, STM32_ADC_ISR_OFFSET, pending);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: adc1_interrupt
+ *
+ * Description:
+ *   ADC interrupt handler for the STM32 L15XX family.
+ *
+ * Input Parameters:
+ *   irq     - The IRQ number that generated the interrupt.
+ *   context - Architecture specific register save information.
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static int adc1_interrupt(int irq, FAR void *context, FAR void *arg)
+{
+  adc_interrupt(&g_adcdev1);
+
+  return OK;
+}
+#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */
+
+#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
+
+/****************************************************************************
+ * Name: adc_llops_intack
+ ****************************************************************************/
+
+static void adc_llops_intack(FAR struct stm32_adc_dev_s *dev, uint32_t source)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
+
+  /* Clear pending interrupts */
+
+#ifdef HAVE_IP_ADC_V2
+  /* Cleared by writing 1 to it */
+
+  adc_putreg(priv, STM32_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS));
+#else
+  /* Cleared by writing 0 to it */
+
+  adc_modifyreg(priv, STM32_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS), 0);
+#endif
+}
+
+/****************************************************************************
+ * Name: adc_llops_inten
+ ****************************************************************************/
+
+static void adc_llops_inten(FAR struct stm32_adc_dev_s *dev, uint32_t source)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
+
+  /* Enable interrupts */
+
+  adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, (source & ADC_IER_ALLINTS));
+}
+
+/****************************************************************************
+ * Name: adc_llops_intdis
+ ****************************************************************************/
+
+static void adc_llops_intdis(FAR struct stm32_adc_dev_s *dev, uint32_t source)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
+
+  /* Disable interrupts */
+
+  adc_modifyreg(priv, STM32_ADC_IER_OFFSET, (source & ADC_IER_ALLINTS), 0);
+}
+
+/****************************************************************************
+ * Name: adc_ackget
+ ****************************************************************************/
+
+static uint32_t adc_llops_intget(FAR struct stm32_adc_dev_s *dev)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
+  uint32_t regval;
+  uint32_t pending;
+
+  regval  = adc_getreg(priv, STM32_ADC_ISR_OFFSET);
+  pending = regval & ADC_ISR_ALLINTS;
+
+  return pending;
+}
+
+/****************************************************************************
+ * Name: adc_llops_regget
+ ****************************************************************************/
+
+static uint32_t adc_llops_regget(FAR struct stm32_adc_dev_s *dev)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
+
+  return adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_RDATA_MASK;
+}
+
+/****************************************************************************
+ * Name: adc_llops_reg_startconv
+ ****************************************************************************/
+
+static void adc_llops_reg_startconv(FAR struct stm32_adc_dev_s *dev, bool enable)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
+
+  adc_reg_startconv(priv, enable);
+}
+
+/****************************************************************************
+ * Name: adc_llops_regbufregister
+ ****************************************************************************/
+
+#ifdef ADC_HAVE_DMA
+static int adc_llops_regbufregister(FAR struct stm32_adc_dev_s *dev,
+                                    uint16_t *buffer, uint8_t len)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
+
+  stm32_dmasetup(priv->dma,
+                 priv->base + STM32_ADC_DR_OFFSET,
+                 (uint32_t)buffer,
+                 len,
+                 ADC_DMA_CONTROL_WORD);
+
+  /* No DMA callback */
+
+  stm32_dmastart(priv->dma, NULL, dev, false);
+
+  return OK;
+}
+#endif  /* ADC_HAVE_DMA */
+
+/****************************************************************************
+ * Name: adc_sampletime_write
+ *
+ * Description:
+ *   Writes previously defined values into ADC_SMPRx registers.
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
+static void adc_sampletime_write(FAR struct stm32_adc_dev_s *dev)
+{
+  #error TODO adc_sampletime_write
+}
+
+/****************************************************************************
+ * Name: adc_change_sample_time
+ *
+ * Description:
+ *   Changes sample times for specified channels. This method
+ *   doesn't make any register writing. So, it's only stores the information.
+ *   Values provided by user will be written in registers only on the next
+ *   ADC peripheral start, as it was told to do in manual. However, before
+ *   very first start, user can call this method and override default values
+ *   either for every channels or for only some predefined by user channel(s)
+ *
+ * Input Parameters:
+ *   priv     - pointer to the adc device structure
+ *   pdi_high - true:  The ADC is powered down when waiting for a start event
+ *              false: The ADC is powered up when waiting for a start event
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void adc_sampletime_set(FAR struct stm32_adc_dev_s *dev,
+                        FAR struct adc_sample_time_s *time_samples)
+{
+  #error TODO adc_sampletime_write
+}
+#endif  /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */
+
+/****************************************************************************
+ * Name: adc_llops_dumpregs
+ ****************************************************************************/
+
+static void adc_llops_dumpregs(FAR struct stm32_adc_dev_s *dev)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
+
+  adc_dumpregs(priv);
+}
+
+#endif  /* CONFIG_STM32F0L0G0_ADC_LL_OPS */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_adc_initialize
+ *
+ * Description:
+ *   Initialize the ADC.
+ *
+ * Input Parameters:
+ *   intf      - Could be {1} for ADC1
+ *   chanlist  - The list of channels
+ *   channels - Number of channels
+ *
+ * Returned Value:
+ *   Valid ADC device structure reference on success; a NULL on failure
+ *
+ ****************************************************************************/
+
+struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
+                                      int channels)
+{
+  FAR struct adc_dev_s   *dev;
+  FAR struct stm32_dev_s *priv;
+
+  ainfo("intf: %d cchannels: %d\n", intf, channels);
+
+  switch (intf)
+    {
+#ifdef CONFIG_STM32F0L0G0_ADC1
+      case 1:
+        {
+          ainfo("ADC1 selected\n");
+          dev = &g_adcdev1;
+          break;
+        }
+#endif
+      default:
+        {
+          aerr("ERROR: No ADC interface defined\n");
+          return NULL;
+        }
+    }
+
+  /* Configure the selected ADC */
+
+  priv = (FAR struct stm32_dev_s *)dev->ad_priv;
+  priv->cb = NULL;
+
+  DEBUGASSERT(channels <= ADC_MAX_SAMPLES);
+
+  priv->cr_channels = channels;
+  memcpy(priv->r_chanlist, chanlist, channels);
+
+#ifdef CONFIG_PM
+  if (pm_register(&priv->pm_callback) != OK)
+    {
+      aerr("Power management registration failed\n");
+      return NULL;
+    }
+#endif
+
+  return dev;
+}
+
+#endif /* CONFIG_STM32F0L0G0_ADC1 */
+#endif /* CONFIG_STM32F0L0G0_ADC */
diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.h b/arch/arm/src/stm32f0l0g0/stm32_adc.h
new file mode 100644
index 00000000000..b18d4900e39
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/stm32_adc.h
@@ -0,0 +1,344 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_adc.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include "chip.h"
+
+#include 
+#include 
+
+#include "hardware/stm32_adc.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Configuration ********************************************************************/
+
+/* Timer ADC trigger not supported yet */
+
+#undef  ADC1_HAVE_TIMER
+
+/* Up to 1 ADC interfaces are supported */
+
+#if STM32_NADC < 1
+#  undef CONFIG_STM32F0L0G0_ADC1
+#endif
+
+#if defined(CONFIG_STM32F0L0G0_ADC1)
+
+/* DMA support */
+
+#undef ADC_HAVE_DMA
+#if defined(CONFIG_STM32F0L0G0_ADC1_DMA)
+#  define ADC_HAVE_DMA  1
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_ADC1_DMA
+#  define ADC1_HAVE_DMA 1
+#else
+#  undef  ADC1_HAVE_DMA
+#endif
+
+/* EXTSEL */
+
+#if defined(CONFIG_STM32F0L0G0_STM32F0)
+#  define ADC1_EXTSEL_T1TRGO  ADC12_CFGR1_EXTSEL_TRG0
+#  define ADC1_EXTSEL_T1CC4   ADC12_CFGR1_EXTSEL_TRG1
+#  define ADC1_EXTSEL_T2TRGO  ADC12_CFGR1_EXTSEL_TRG2
+#  define ADC1_EXTSEL_T3TRGO  ADC12_CFGR1_EXTSEL_TRG3
+#  define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_TRG4
+                              /* TRG5 reserved */
+                              /* TRG6 reserved */
+                              /* TRG7 reserved */
+#elif defined(CONFIG_STM32F0L0G0_STM32L0)
+                              /* TRG0 reserved */
+#  define ADC1_EXTSEL_T21CC2  ADC12_CFGR1_EXTSEL_TRG1
+#  define ADC1_EXTSEL_T2TRGO  ADC12_CFGR1_EXTSEL_TRG2
+#  define ADC1_EXTSEL_T2CC4   ADC12_CFGR1_EXTSEL_TRG3
+#  define ADC1_EXTSEL_T21TRGO ADC12_CFGR1_EXTSEL_TRG4
+#  define ADC1_EXTSEL_T2CC3   ADC12_CFGR1_EXTSEL_TRG5
+                              /* TRG6 reserved */
+#  define ADC1_EXTSEL_EXTI11  ADC12_CFGR1_EXTSEL_TRG7
+#elif defined(CONFIG_STM32F0L0G0_STM32G0)
+#  define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_TRG0
+#  define ADC1_EXTSEL_T1CC4   ADC12_CFGR1_EXTSEL_TRG1
+#  define ADC1_EXTSEL_T2TRGO  ADC12_CFGR1_EXTSEL_TRG2
+#  define ADC1_EXTSEL_T3TRGO  ADC12_CFGR1_EXTSEL_TRG3
+#  define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_TRG4
+#  define ADC1_EXTSEL_T6TRGO  ADC12_CFGR1_EXTSEL_TRG5
+                              /* TRG6 reserved */
+#  define ADC1_EXTSEL_EXTI11  ADC12_CFGR1_EXTSEL_TRG7
+#else
+#  error
+#endif
+
+/* EXTSEL configuration *****************************************************/
+/* TODO */
+
+/* ADC interrupts ***********************************************************/
+
+#define ADC_ISR_EOC                  ADC_INT_EOC
+#define ADC_IER_EOC                  ADC_INT_EOC
+#define ADC_ISR_AWD                  ADC_INT_AWD
+#define ADC_IER_AWD                  ADC_INT_AWD
+#define ADC_ISR_OVR                  ADC_INT_OVR
+#define ADC_IER_OVR                  ADC_INT_OVR
+
+#define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_AWD | ADC_ISR_OVR)
+#define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_AWD | ADC_IER_OVR)
+
+/* ADC registers ***********************************************************/
+
+#define STM32_ADC_DMAREG_OFFSET      STM32_ADC_CFGR1_OFFSET
+#define ADC_DMAREG_DMA               ADC_CFGR1_DMAEN
+#define STM32_ADC_EXTREG_OFFSET      STM32_ADC_CFGR1_OFFSET
+#define ADC_EXTREG_EXTSEL_MASK       ADC_CFGR1_EXTSEL_MASK
+#define ADC_EXTREG_EXTEN_MASK        ADC_CFGR1_EXTEN_MASK
+#define ADC_EXTREG_EXTEN_DEFAULT     ADC_CFGR1_EXTEN_RISING
+
+/* Low-level ops helpers ****************************************************/
+
+#define ADC_INT_ACK(adc, source)                     \
+        (adc)->llops->int_ack(adc, source)
+#define ADC_INT_GET(adc)                             \
+        (adc)->llops->int_get(adc)
+#define ADC_INT_ENABLE(adc, source)                  \
+        (adc)->llops->int_en(adc, source)
+#define ADC_INT_DISABLE(adc, source)                 \
+        (adc)->llops->int_dis(adc, source)
+#define ADC_REGDATA_GET(adc)                         \
+        (adc)->llops->val_get(adc)
+#define ADC_REGBUF_REGISTER(adc, buffer, len)        \
+        (adc)->llops->regbuf_reg(adc, buffer, len)
+#define ADC_REG_STARTCONV(adc, state)                \
+        (adc)->llops->reg_startconv(adc, state)
+#define ADC_SAMPLETIME_SET(adc, time_samples)        \
+        (adc)->llops->stime_set(adc, time_samples)
+#define ADC_SAMPLETIME_WRITE(adc)                    \
+        (adc)->llops->stime_write(adc)
+#define ADC_DUMP_REGS(adc)                           \
+        (adc)->llops->dump_regs(adc)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/* On STM32F42xx and STM32F43xx devices,VBAT and temperature sensor are connected
+ * to the same ADC internal channel (ADC1_IN18). Only one conversion, either
+ * temperature sensor or VBAT, must be selected at a time. When both conversion are
+ * enabled simultaneously, only the VBAT conversion is performed.
+ */
+
+enum adc_io_cmds_e
+{
+#ifdef HAVE_ADC_VBAT
+  IO_ENABLE_DISABLE_VBAT_CH,
+#endif
+  IO_ENABLE_DISABLE_AWDIE,
+  IO_ENABLE_DISABLE_EOCIE,
+  IO_ENABLE_DISABLE_JEOCIE,
+  IO_ENABLE_DISABLE_OVRIE,
+  IO_ENABLE_DISABLE_ALL_INTS,
+  IO_STOP_ADC,
+  IO_START_ADC,
+  IO_START_CONV,
+  IO_TRIGGER_REG,
+#ifdef ADC_HAVE_INJECTED
+  IO_TRIGGER_INJ,
+#endif
+#ifdef HAVE_ADC_POWERDOWN
+  IO_ENABLE_DISABLE_PDI,
+  IO_ENABLE_DISABLE_PDD,
+  IO_ENABLE_DISABLE_PDD_PDI
+#endif
+};
+
+/* ADC resolution can be reduced in order to perform faster conversion */
+
+enum stm32_adc_resoluton_e
+{
+  ADC_RESOLUTION_12BIT = 0,     /* 12 bit */
+  ADC_RESOLUTION_10BIT = 1,     /* 10 bit */
+  ADC_RESOLUTION_8BIT  = 2,     /* 8 bit */
+  ADC_RESOLUTION_6BIT  = 3      /* 6 bit */
+};
+
+#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
+
+#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
+
+/* Channel and sample time pair */
+
+typedef struct adc_channel_s
+{
+  uint8_t channel:5;
+
+  /* Sampling time individually for each channel. It differs between families */
+
+  uint8_t sample_time:3;
+} adc_channel_t;
+
+/* This structure will be used while setting channels to specified by the
+ * "channel-sample time" pairs' values
+ */
+
+struct adc_sample_time_s
+{
+  adc_channel_t *channel;                /* Array of channels */
+  uint8_t        channels_nbr:5;         /* Number of channels in array */
+  bool           all_same:1;             /* All channels will get the
+                                          * same value of the sample time */
+  uint8_t        all_ch_sample_time:3;   /* Sample time for all channels */
+};
+#endif  /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */
+
+/* This structure provides the publicly visable representation of the
+ * "lower-half" ADC driver structure.
+ */
+
+struct stm32_adc_dev_s
+{
+  /* Publicly visible portion of the "lower-half" ADC driver structure */
+
+  FAR const struct stm32_adc_ops_s *llops;
+
+  /* Require cast-compatibility with private "lower-half" ADC strucutre */
+};
+
+/* Low-level operations for ADC */
+
+struct stm32_adc_ops_s
+{
+  /* Acknowledge interrupts */
+
+  void (*int_ack)(FAR struct stm32_adc_dev_s *dev, uint32_t source);
+
+  /* Get pending interrupts */
+
+  uint32_t (*int_get)(FAR struct stm32_adc_dev_s *dev);
+
+  /* Enable interrupts */
+
+  void (*int_en)(FAR struct stm32_adc_dev_s *dev, uint32_t source);
+
+  /* Disable interrupts */
+
+  void (*int_dis)(FAR struct stm32_adc_dev_s *dev, uint32_t source);
+
+  /* Get current ADC data register */
+
+  uint32_t (*val_get)(FAR struct stm32_adc_dev_s *dev);
+
+  /* Register buffer for ADC DMA transfer */
+
+  int (*regbuf_reg)(FAR struct stm32_adc_dev_s *dev, uint16_t *buffer, uint8_t len);
+
+  /* Start/stop regular conversion */
+
+  void (*reg_startconv)(FAR struct stm32_adc_dev_s *dev, bool state);
+
+#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME
+  /* Set ADC sample time */
+
+  void (*stime_set)(FAR struct stm32_adc_dev_s *dev,
+                    FAR struct adc_sample_time_s *time_samples);
+
+  /* Write ADC sample time */
+
+  void (*stime_write)(FAR struct stm32_adc_dev_s *dev);
+#endif
+
+  void (*dump_regs)(FAR struct stm32_adc_dev_s *dev);
+};
+
+#endif  /* CONFIG_STM32F0L0G0_ADC_LL_OPS */
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: stm32_adcinitialize
+ *
+ * Description:
+ *   Initialize the ADC. See stm32_adc.c for more details.
+ *
+ * Input Parameters:
+ *   intf      - Could be {1,2,3,4} for ADC1, ADC2, ADC3 or ADC4
+ *   chanlist  - The list of channels (regular + injected)
+ *   nchannels - Number of channels (regular + injected)
+ *
+ * Returned Value:
+ *   Valid can device structure reference on succcess; a NULL on failure
+ *
+ ****************************************************************************/
+
+struct adc_dev_s;
+struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
+                                      int channels);
+
+/************************************************************************************
+ * Name: stm32_adc_llops_get
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS
+FAR const struct stm32_adc_ops_s *stm32_adc_llops_get(FAR struct adc_dev_s *dev);
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_STM32F0L0G0_ADC1 */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H */
diff --git a/arch/arm/src/stm32f0l0g0/stm32_aes.c b/arch/arm/src/stm32f0l0g0/stm32_aes.c
new file mode 100644
index 00000000000..2a5281f01e7
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/stm32_aes.c
@@ -0,0 +1,342 @@
+/****************************************************************************
+ * arch/arm/src/stm32f0l0g0/stm32_aes.c
+ *
+ *   Copyright (C) 2015 Haltian Ltd. All rights reserved.
+ *   Author:  Juha Niskanen 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "stm32_rcc.h"
+#include "stm32_aes.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define AES_BLOCK_SIZE 16
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static void stm32aes_enable(bool on);
+static void stm32aes_ccfc(void);
+static void stm32aes_setkey(FAR const void *key, size_t key_len);
+static void stm32aes_setiv(FAR const void *iv);
+static void stm32aes_encryptblock(FAR void *block_out,
+                                  FAR const void *block_in);
+static int  stm32aes_setup_cr(int mode, int encrypt);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static sem_t g_stm32aes_lock;
+static bool  g_stm32aes_initdone = false;
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static void stm32aes_enable(bool on)
+{
+  uint32_t regval;
+
+  regval = getreg32(STM32_AES_CR);
+  if (on)
+    {
+      regval |= AES_CR_EN;
+    }
+  else
+    {
+      regval &= ~AES_CR_EN;
+    }
+
+  putreg32(regval, STM32_AES_CR);
+}
+
+/* Clear AES_SR_CCF status register bit */
+
+static void stm32aes_ccfc(void)
+{
+  uint32_t regval;
+
+  regval  = getreg32(STM32_AES_CR);
+  regval |= AES_CR_CCFC;
+  putreg32(regval, STM32_AES_CR);
+}
+
+/* TODO: Handle other AES key lengths or fail if length is not valid */
+
+static void stm32aes_setkey(FAR const void *key, size_t key_len)
+{
+  FAR uint32_t *in = (FAR uint32_t *)key;
+
+  (void)key_len;
+
+  putreg32(__builtin_bswap32(*in), STM32_AES_KEYR3);
+  in++;
+  putreg32(__builtin_bswap32(*in), STM32_AES_KEYR2);
+  in++;
+  putreg32(__builtin_bswap32(*in), STM32_AES_KEYR1);
+  in++;
+  putreg32(__builtin_bswap32(*in), STM32_AES_KEYR0);
+}
+
+static void stm32aes_setiv(FAR const void *iv)
+{
+  FAR uint32_t *in = (FAR uint32_t *)iv;
+
+  putreg32(__builtin_bswap32(*in), STM32_AES_IVR3);
+  in++;
+  putreg32(__builtin_bswap32(*in), STM32_AES_IVR2);
+  in++;
+  putreg32(__builtin_bswap32(*in), STM32_AES_IVR1);
+  in++;
+  putreg32(__builtin_bswap32(*in), STM32_AES_IVR0);
+}
+
+static void stm32aes_encryptblock(FAR void *block_out, FAR const void *block_in)
+{
+  FAR uint32_t *in  = (FAR uint32_t *)block_in;
+  FAR uint32_t *out = (FAR uint32_t *)block_out;
+
+  putreg32(*in, STM32_AES_DINR);
+  in++;
+  putreg32(*in, STM32_AES_DINR);
+  in++;
+  putreg32(*in, STM32_AES_DINR);
+  in++;
+  putreg32(*in, STM32_AES_DINR);
+
+  while (!(getreg32(STM32_AES_SR) & AES_SR_CCF));
+  stm32aes_ccfc();
+
+  *out = getreg32(STM32_AES_DOUTR);
+  out++;
+  *out = getreg32(STM32_AES_DOUTR);
+  out++;
+  *out = getreg32(STM32_AES_DOUTR);
+  out++;
+  *out = getreg32(STM32_AES_DOUTR);
+}
+
+static int stm32aes_setup_cr(int mode, int encrypt)
+{
+  uint32_t regval = 0;
+
+  regval |= AES_CR_DATATYPE_BE;
+
+  switch (mode)
+  {
+  case AES_MODE_ECB:
+    regval |= AES_CR_CHMOD_ECB;
+    break;
+
+  case AES_MODE_CBC:
+    regval |= AES_CR_CHMOD_CBC;
+    break;
+
+  case AES_MODE_CTR:
+    regval |= AES_CR_CHMOD_CTR;
+    break;
+
+  default:
+    return -EINVAL;
+  }
+
+  if (encrypt)
+    {
+      regval |= AES_CR_MODE_ENCRYPT;
+    }
+  else
+    {
+      if (mode == AES_MODE_CTR)
+        {
+          regval |= AES_CR_MODE_DECRYPT;
+        }
+      else
+        {
+          regval |= AES_CR_MODE_DECRYPT_KEYDERIV;
+        }
+    }
+
+  putreg32(regval, STM32_AES_CR);
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+int stm32_aesreset(void)
+{
+  irqstate_t flags;
+  uint32_t regval;
+
+  flags = enter_critical_section();
+
+  regval  = getreg32(STM32_RCC_AHBRSTR);
+  regval |= RCC_AHBRSTR_AESRST;
+  putreg32(regval, STM32_RCC_AHBRSTR);
+  regval &= ~RCC_AHBRSTR_AESRST;
+  putreg32(regval, STM32_RCC_AHBRSTR);
+
+  leave_critical_section(flags);
+
+  return OK;
+}
+
+int stm32_aesinitialize(void)
+{
+  uint32_t regval;
+
+  nxsem_init(&g_stm32aes_lock, 0, 1);
+
+  regval  = getreg32(STM32_RCC_AHBENR);
+  regval |= RCC_AHBENR_AESEN;
+  putreg32(regval, STM32_RCC_AHBENR);
+
+  stm32aes_enable(false);
+
+  return OK;
+}
+
+int stm32_aesuninitialize(void)
+{
+  uint32_t regval;
+
+  stm32aes_enable(false);
+
+  regval  = getreg32(STM32_RCC_AHBENR);
+  regval &= ~RCC_AHBENR_AESEN;
+  putreg32(regval, STM32_RCC_AHBENR);
+
+  nxsem_destroy(&g_stm32aes_lock);
+
+  return OK;
+}
+
+int aes_cypher(FAR void *out, FAR const void *in, uint32_t size,
+               FAR const void *iv, FAR const void *key, uint32_t keysize,
+               int mode, int encrypt)
+{
+  int ret = OK;
+
+  /* Ensure initialization was done */
+
+  if (!g_stm32aes_initdone)
+    {
+      ret = stm32_aesinitialize();
+      if (ret < 0)
+        {
+          return ret; /* AES init failed */
+        }
+
+      g_stm32aes_initdone = true;
+    }
+
+  if ((size & (AES_BLOCK_SIZE-1)) != 0)
+    {
+      return -EINVAL;
+    }
+
+  if (keysize != 16)
+    {
+      return -EINVAL;
+    }
+
+  ret = nxsem_wait(&g_stm32aes_lock);
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+  /* AES must be disabled before changing mode, key or IV. */
+
+  stm32aes_enable(false);
+  ret = stm32aes_setup_cr(mode, encrypt);
+  if (ret < 0)
+    {
+      goto out;
+    }
+
+  stm32aes_setkey(key, keysize);
+  if (iv != NULL)
+    {
+      stm32aes_setiv(iv);
+    }
+
+  stm32aes_enable(true);
+  while (size)
+    {
+      stm32aes_encryptblock(out, in);
+      out   = (FAR uint8_t *)out + AES_BLOCK_SIZE;
+      in    = (FAR uint8_t *)in  + AES_BLOCK_SIZE;
+      size -= AES_BLOCK_SIZE;
+    }
+
+  stm32aes_enable(false);
+
+out:
+  nxsem_post(&g_stm32aes_lock);
+  return ret;
+}
diff --git a/arch/arm/src/stm32f0l0g0/stm32_aes.h b/arch/arm/src/stm32f0l0g0/stm32_aes.h
new file mode 100644
index 00000000000..64b6e841a56
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/stm32_aes.h
@@ -0,0 +1,63 @@
+/************************************************************************************
+ * arch/arm/src/stm32f0l0g0/stm32_aes.h
+ *
+ *   Copyright (C) 2014 Haltian Ltd. All rights reserved.
+ *   Author:  Juha Niskanen 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include 
+
+#include "chip.h"
+
+#include "hardware/stm32_aes.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H */
diff --git a/arch/arm/src/stm32f0l0/stm32_dma.h b/arch/arm/src/stm32f0l0g0/stm32_dma.h
similarity index 98%
rename from arch/arm/src/stm32f0l0/stm32_dma.h
rename to arch/arm/src/stm32f0l0g0/stm32_dma.h
index 2d5b0137cd6..2744931924d 100644
--- a/arch/arm/src/stm32f0l0/stm32_dma.h
+++ b/arch/arm/src/stm32f0l0g0/stm32_dma.h
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_DMA_H
-#define __ARCH_ARM_SRC_STM32F0L0_STM32_DMA_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H
 
 /************************************************************************************
  * Included Files
@@ -245,7 +245,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle);
  *
  ****************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_DMACAPABLE
+#ifdef CONFIG_STM32F0L0G0_DMACAPABLE
 bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr);
 #else
 #  define stm32_dmacapable(maddr, count, ccr) (true)
@@ -331,4 +331,4 @@ uint8_t  stm32_dma_intget(unsigned int controller, uint8_t stream);
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_DMA_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H */
diff --git a/arch/arm/src/stm32f0l0/stm32_dma_v1.c b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c
similarity index 98%
rename from arch/arm/src/stm32f0l0/stm32_dma_v1.c
rename to arch/arm/src/stm32f0l0g0/stm32_dma_v1.c
index 495762c3ab9..6740509c0c6 100644
--- a/arch/arm/src/stm32f0l0/stm32_dma_v1.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c
@@ -49,6 +49,8 @@
 #include 
 #include 
 
+#include 
+
 #include "up_arch.h"
 #include "up_internal.h"
 #include "sched/sched.h"
@@ -62,6 +64,10 @@
  * the DMA requests for each channel.
  */
 
+#ifdef CONFIG_STM32F0L0G0_HAVE_DMAMUX
+#  error DMAMUX not supported yet
+#endif
+
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
@@ -159,12 +165,12 @@ static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
   },
   {
     .chan     = 3,
-    .irq      = STM32_IRQ_DMA2CH45,
+    .irq      = STM32_IRQ_DMA2CH4,
     .base     = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3),
   },
   {
     .chan     = 4,
-    .irq      = STM32_IRQ_DMA2CH45,
+    .irq      = STM32_IRQ_DMA2CH5,
     .base     = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4),
   },
 #endif
@@ -292,7 +298,7 @@ static int stm32_dmainterrupt(int irq, void *context, FAR void *arg)
     }
   else
 #if STM32_NDMA > 1
-  if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH45)
+  if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5)
     {
       chndx = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS;
     }
@@ -649,7 +655,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_DMACAPABLE
+#ifdef CONFIG_STM32F0L0G0_DMACAPABLE
 bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
 {
   uint32_t transfer_size;
diff --git a/arch/arm/src/stm32f0l0/stm32_exti.h b/arch/arm/src/stm32f0l0g0/stm32_exti.h
similarity index 96%
rename from arch/arm/src/stm32f0l0/stm32_exti.h
rename to arch/arm/src/stm32f0l0g0/stm32_exti.h
index d83e4c725d0..d708333febb 100644
--- a/arch/arm/src/stm32f0l0/stm32_exti.h
+++ b/arch/arm/src/stm32f0l0g0/stm32_exti.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/stm32_exti.h
+ * arch/arm/src/stm32f0l0g0/stm32_exti.h
  *
  *   Copyright (C) 2009, 2012, 2015, 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_EXTI_H
-#define __ARCH_ARM_SRC_STM32F0L0_STM32_EXTI_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H
 
 /************************************************************************************
  * Included Files
@@ -140,4 +140,4 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event,
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_EXTI_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H */
diff --git a/arch/arm/src/stm32f0l0/stm32_exti_gpio.c b/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c
similarity index 80%
rename from arch/arm/src/stm32f0l0/stm32_exti_gpio.c
rename to arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c
index b40e0ae9591..e841faef4c2 100644
--- a/arch/arm/src/stm32f0l0/stm32_exti_gpio.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f0l0/stm32_exti_gpio.c
+ * arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c
  *
  *   Copyright (C) 2009, 2011-2012, 2015, 2017 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2011 Uros Platise. All rights reserved.
@@ -55,6 +55,17 @@
 #include "stm32_gpio.h"
 #include "stm32_exti.h"
 
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2)
+#  define STM32_EXTI_FTSR             STM32_EXTI_FTSR1
+#  define STM32_EXTI_RTSR             STM32_EXTI_RTSR1
+#  define STM32_EXTI_IMR              STM32_EXTI_IMR1
+#  define STM32_EXTI_EMR              STM32_EXTI_EMR1
+#endif
+
 /****************************************************************************
  * Private Types
  ****************************************************************************/
@@ -81,6 +92,7 @@ static struct gpio_callback_s g_gpio_callbacks[16];
  * Interrupt Service Routines - Dispatchers
  ****************************************************************************/
 
+#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1)
 static int stm32_exti_multiisr(int irq, void *context, void *arg,
                                int first, int last)
 {
@@ -124,6 +136,56 @@ static int stm32_exti_multiisr(int irq, void *context, void *arg,
 
   return ret;
 }
+#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2)
+static int stm32_exti_multiisr(int irq, void *context, void *arg,
+                               int first, int last)
+{
+  uint32_t rpr;
+  uint32_t fpr;
+  int pin;
+  int ret = OK;
+
+  /* Examine the state of each pin in the group.
+   * NOTE: We don't distinguish rising/falling edge!
+   */
+
+  rpr = getreg32(STM32_EXTI_RPR1);
+  fpr = getreg32(STM32_EXTI_FPR1);
+
+  /* And dispatch the interrupt to the handler */
+
+  for (pin = first; pin <= last; pin++)
+    {
+      /* Is an interrupt pending on this pin? */
+
+      uint32_t mask = (1 << pin);
+      if (((rpr & mask) != 0) || ((fpr & mask) != 0))
+        {
+          /* Clear the pending interrupt */
+
+          putreg32(mask, STM32_EXTI_RPR1);
+          putreg32(mask, STM32_EXTI_FPR1);
+
+          /* And dispatch the interrupt to the handler */
+
+          if (g_gpio_callbacks[pin].callback != NULL)
+            {
+              xcpt_t callback = g_gpio_callbacks[pin].callback;
+              void  *cbarg    = g_gpio_callbacks[pin].arg;
+              int tmp;
+
+              tmp = callback(irq, context, cbarg);
+              if (tmp < 0)
+                {
+                  ret = tmp;
+                }
+            }
+        }
+    }
+
+  return ret;
+}
+#endif
 
 static int stm32_exti01_isr(int irq, void *context, void *arg)
 {
@@ -241,6 +303,7 @@ int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
 
   stm32_configgpio(pinset);
 
+
   /* Configure rising/falling edges */
 
   modifyreg32(STM32_EXTI_RTSR,
diff --git a/arch/arm/src/stm32f0l0/stm32_gpio.c b/arch/arm/src/stm32f0l0g0/stm32_gpio.c
similarity index 86%
rename from arch/arm/src/stm32f0l0/stm32_gpio.c
rename to arch/arm/src/stm32f0l0g0/stm32_gpio.c
index b2caf126acf..35d8d3cafa1 100644
--- a/arch/arm/src/stm32f0l0/stm32_gpio.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_gpio.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f0l0/stm32_gpio.c
+ * arch/arm/src/stm32f0l0g0/stm32_gpio.c
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -47,14 +47,18 @@
 #include 
 
 #include 
-#include 
+#include 
 
 #include "up_arch.h"
 
 #include "chip.h"
 #include "stm32_gpio.h"
 
-#include "hardware/stm32_syscfg.h"
+#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1)
+#  include "hardware/stm32_syscfg.h"
+#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2)
+#  include "hardware/stm32_exti.h"
+#endif
 
 /****************************************************************************
  * Public Data
@@ -70,18 +74,19 @@ const uint32_t g_gpiobase[STM32_NPORTS] =
   STM32_GPIOB_BASE,   /* Two GPIO ports, GPIOA-B */
 #endif
 #if STM32_NPORTS > 2
-  STM32_GPIOC_BASE,   /* Three GPIO ports, GPIOA-D*/
+  STM32_GPIOC_BASE,   /* Three GPIO ports, GPIOA-C*/
 #endif
 #if STM32_NPORTS > 3
   STM32_GPIOD_BASE,   /* Four GPIO ports, GPIOA-D */
 #endif
-#if STM32_NPORTS > 4
-  STM32_GPIOE_BASE,   /* Five GPIO ports, GPIOA-E */
+#if defined(STM32_GPIOE_BASE)
+  STM32_GPIOE_BASE,   /* GPIOE */
 #endif
-#if STM32_NPORTS > 5 && defined(STM32_HAVE_PORTF)
-  STM32_GPIOF_BASE,   /* Six GPIO ports, GPIOA-F */
-#elif STM32_NPORTS > 5 && !defined(STM32_HAVE_PORTF)
-  STM32_GPIOH_BASE,   /* Six GPIO ports, GPIOA-E, H */
+#if defined(STM32_GPIOF_BASE)
+  STM32_GPIOF_BASE,   /* GPIOF */
+#endif
+#if defined(STM32_GPIOH_BASE)
+  STM32_GPIOH_BASE,   /* GPIOH */
 #endif
 };
 
@@ -252,32 +257,32 @@ int stm32_configgpio(uint32_t cfgset)
         {
           default:
 #if defined(STM32_GPIO_VERY_LOW_SPEED)
-          case GPIO_SPPED_VERYLOW: /* 400KHz Very Low speed output */
-            setting = GPIO_OSPEED_2MHz;
+          case GPIO_SPPED_VERYLOW: /* Very Low speed output */
+            setting = GPIO_OSPEED_VERYLOW;
             break;
 
-          case GPIO_SPEED_LOW:     /* 2 MHz Low speed output */
-            setting = GPIO_OSPEED_2MHz;
+          case GPIO_SPEED_LOW:     /* Low speed output */
+            setting = GPIO_OSPEED_LOW;
             break;
 
-          case GPIO_SPEED_MEDIUM:  /* 10 MHz Medium speed output */
-            setting = GPIO_OSPEED_10MHz;
+          case GPIO_SPEED_MEDIUM:  /* Medium speed output */
+            setting = GPIO_OSPEED_MEDIUM;
             break;
 
-          case GPIO_SPEED_HIGH:    /* 40 MHz High speed output  */
-            setting = GPIO_OSPEED_40MHz;
+          case GPIO_SPEED_HIGH:    /* High speed output  */
+            setting = GPIO_OSPEED_HIGH;
             break;
 #else
-          case GPIO_SPEED_LOW:     /* 2 MHz Low speed output */
-            setting = GPIO_OSPEED_2MHz;
+          case GPIO_SPEED_LOW:     /* Low speed output */
+            setting = GPIO_OSPEED_LOW;
             break;
 
-          case GPIO_SPEED_MEDIUM:  /* 10 MHz Medium speed output */
-            setting = GPIO_OSPEED_10MHz;
+          case GPIO_SPEED_MEDIUM:  /* Medium speed output */
+            setting = GPIO_OSPEED_MEDIUM;
             break;
 
-          case GPIO_SPEED_HIGH:    /* 50 MHz High speed output  */
-            setting = GPIO_OSPEED_50MHz;
+          case GPIO_SPEED_HIGH:    /* High speed output  */
+            setting = GPIO_OSPEED_HIGH;
             break;
 #endif
         }
@@ -313,19 +318,10 @@ int stm32_configgpio(uint32_t cfgset)
 
   if ((cfgset & GPIO_EXTI) != 0)
     {
-      /* "In STM32 F1 the selection of the EXTI line source is performed through
-       *  the EXTIx bits in the AFIO_EXTICRx registers, while in F2 series this
-       *  selection is done through the EXTIx bits in the SYSCFG_EXTICRx registers.
-       *
-       * "Only the mapping of the EXTICRx registers has been changed, without any
-       *  changes to the meaning of the EXTIx bits. However, the range of EXTI
-       *  bits values has been extended to 0b1000 to support the two ports added
-       *  in F2, port H and I (in F1 series the maximum value is 0b0110)."
-       */
-
       uint32_t regaddr;
       int shift;
 
+#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1)
       /* Set the bits in the SYSCFG EXTICR register */
 
       regaddr = STM32_SYSCFG_EXTICR(pin);
@@ -335,6 +331,19 @@ int stm32_configgpio(uint32_t cfgset)
       regval |= (((uint32_t)port) << shift);
 
       putreg32(regval, regaddr);
+#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2)
+      /* Set the bits in the EXTI EXTICR register */
+
+      regaddr = STM32_EXTI_EXTICR(pin);
+      regval  = getreg32(regaddr);
+      shift   = EXTI_EXTICR_EXTI_SHIFT(pin);
+      regval &= ~(EXTI_EXTICR_PORT_MASK << shift);
+      regval |= (((uint32_t)port) << shift);
+
+      putreg32(regval, regaddr);
+#else
+#  error unknown EXTI IP core
+#endif
     }
 
   leave_critical_section(flags);
diff --git a/arch/arm/src/stm32f0l0/stm32_gpio.h b/arch/arm/src/stm32f0l0g0/stm32_gpio.h
similarity index 98%
rename from arch/arm/src/stm32f0l0/stm32_gpio.h
rename to arch/arm/src/stm32f0l0g0/stm32_gpio.h
index 563709f71fc..d4c0969d0f6 100644
--- a/arch/arm/src/stm32f0l0/stm32_gpio.h
+++ b/arch/arm/src/stm32f0l0g0/stm32_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/stm32_gpio.h
+ * arch/arm/src/stm32f0l0g0/stm32_gpio.h
  *
  *   Copyright (C) 2009, 2011-2012, 2015 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2015-2016 Sebastien Lorquet. All rights reserved.
@@ -36,8 +36,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_GPIO_H
-#define __ARCH_ARM_SRC_STM32F0L0_STM32_GPIO_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -51,7 +51,7 @@
 #endif
 
 #include 
-#include 
+#include 
 
 #include "chip.h"
 #include "hardware/stm32_gpio.h"
@@ -370,4 +370,4 @@ void stm32_gpioinit(void);
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_GPIO_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H */
diff --git a/arch/arm/src/stm32f0l0/stm32_hsi48.c b/arch/arm/src/stm32f0l0g0/stm32_hsi48.c
similarity index 85%
rename from arch/arm/src/stm32f0l0/stm32_hsi48.c
rename to arch/arm/src/stm32f0l0g0/stm32_hsi48.c
index 9dfd1a3e848..6f1fc8929d5 100644
--- a/arch/arm/src/stm32f0l0/stm32_hsi48.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_hsi48.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- *  arch/arm/src/stm32f0l0/stm32_hsi48.c
+ *  arch/arm/src/stm32f0l0g0/stm32_hsi48.c
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -46,6 +46,22 @@
 
 #include "stm32_hsi48.h"
 
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if defined(CONFIG_ARCH_CHIP_STM32F0)
+#  define STM32_HSI48_REG STM32_RCC_CR2
+#  define STM32_HSI48ON   RCC_CR2_HSI48ON
+#  define STM32_HSI48RDY  RCC_CR2_HSI48RDY
+#elif defined(CONFIG_ARCH_CHIP_STM32L0)
+#  define STM32_HSI48_REG STM32_RCC_CRRCR
+#  define STM32_HSI48ON   RCC_CRRCR_HSI48ON
+#  define STM32_HSI48RDY  RCC_CRRCR_HSI48RDY
+#else
+#  error "Unsupported STM32F0/L0 HSI48"
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -93,23 +109,20 @@ void stm32_enable_hsi48(enum syncsrc_e syncsrc)
    * enabled.
    */
 
-  regval  = getreg32(STM32_RCC_CR2);
-  regval |= RCC_CR2_HSI48ON;
-  putreg32(regval, STM32_RCC_CR2);
-
-  if (syncsrc == SYNCSRC_USB)
-    {
-      /* Select the HSI48 as the USB clock source */
-
-      regval  = getreg32(STM32_RCC_CFGR3);
-      regval &= ~RCC_CFGR3_USBSW;
-      putreg32(regval, STM32_RCC_CFGR3);
-    }
+  regval  = getreg32(STM32_HSI48_REG);
+  regval |= STM32_HSI48ON;
+  putreg32(regval, STM32_HSI48_REG);
 
   /* Wait for the HSI48 clock to stabilize */
 
-  while ((getreg32(STM32_RCC_CR2) & RCC_CR2_HSI48RDY) == 0);
+  while ((getreg32(STM32_HSI48_REG) & STM32_HSI48RDY) == 0);
 
+  /* Return if no synchronization */
+
+  if (syncsrc == SYNCSRC_NONE)
+    {
+      return;
+    }
 
   /* The CRS synchronization (SYNC) source, selectable through the CRS_CFGR
    * register, can be the signal from the external CRS_SYNC pin, the LSE
@@ -167,9 +180,9 @@ void stm32_disable_hsi48(void)
 
   /* Disable the HSI48 clock */
 
-  regval  = getreg32(STM32_RCC_CR2);
-  regval &= ~RCC_CR2_HSI48ON;
-  putreg32(regval, STM32_RCC_CR2);
+  regval  = getreg32(STM32_HSI48_REG);
+  regval &= ~STM32_HSI48ON;
+  putreg32(regval, STM32_HSI48_REG);
 
   /* Set other registers to the default settings. */
 
diff --git a/arch/arm/src/stm32f0l0/stm32_hsi48.h b/arch/arm/src/stm32f0l0g0/stm32_hsi48.h
similarity index 91%
rename from arch/arm/src/stm32f0l0/stm32_hsi48.h
rename to arch/arm/src/stm32f0l0g0/stm32_hsi48.h
index a8772b6197a..e638ca7f526 100644
--- a/arch/arm/src/stm32f0l0/stm32_hsi48.h
+++ b/arch/arm/src/stm32f0l0g0/stm32_hsi48.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/stm32_rcc.h
+ * arch/arm/src/stm32f0l0g0/stm32_hsi48.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_HSI48_H
-#define __ARCH_ARM_SRC_STM32F0L0_STM32_HSI48_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 
 #include 
 
-#ifdef CONFIG_STM32F0L0_HAVE_HSI48
+#ifdef CONFIG_STM32F0L0G0_HAVE_HSI48
 
 /************************************************************************************
  * Public Types
@@ -51,7 +51,8 @@
 
 enum syncsrc_e
 {
-  SYNCSRC_GPIO = 0, /* GPIO selected as SYNC signal source */
+  SYNCSRC_NONE = 0, /* No SYNC signal */
+  SYNCSRC_GPIO,     /* GPIO selected as SYNC signal source */
   SYNCSRC_LSE,      /* LSE selected as SYNC signal source */
   SYNCSRC_USB,      /* USB SOF selected as SYNC signal source */
 };
@@ -105,5 +106,5 @@ void stm32_enable_hsi48(enum syncsrc_e syncsrc);
 
 void stm32_disable_hsi48(void);
 
-#endif /* CONFIG_STM32F0L0_HAVE_HSI48 */
-#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_HSI48_H */
+#endif /* CONFIG_STM32F0L0G0_HAVE_HSI48 */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H */
diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.c b/arch/arm/src/stm32f0l0g0/stm32_i2c.c
new file mode 100644
index 00000000000..1c725c8fdd8
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/stm32_i2c.c
@@ -0,0 +1,2865 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_i2c.c
+ * STM32 I2C IPv2 Hardware Layer - Device Driver ported from STM32F7
+ *
+ *   Copyright (C) 2011 Uros Platise. All rights reserved.
+ *   Author: Uros Platise 
+ *
+ * With extensions and modifications for the F1, F2, and F4 by:
+ *
+ *   Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *            John Wharington
+ *            David Sidrane 
+ *            Bob Feretich 
+ *
+ * Major rewrite of ISR and supporting methods, including support
+ * for NACK and RELOAD by:
+ *
+ *   Copyright (c) 2016 Doug Vetter.  All rights reserved.
+ *   Author: Doug Vetter 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/* ------------------------------------------------------------------------------
+ *
+ * STM32 I2C IPv2 I2C Driver
+ *
+ * Supports:
+ *  - Master operation:
+ *      Standard-mode (up to 100 kHz)
+ *      Fast-mode (up to 400 kHz)
+ *      Fast-mode Plus (up to 1 MHz)
+ *      fI2CCLK clock source selection is based on STM32_RCC_DCKCFGR2_I2CxSRC
+ *      being set to HSI and the calculations are based on STM32_HSI_FREQUENCY
+ *      of 16mHz
+ *
+ *  - Multiple instances (shared bus)
+ *  - Interrupt based operation
+ *  - RELOAD support
+ *
+ * Unsupported, possible future work:
+ *  - More effective error reporting to higher layers
+ *  - Slave operation
+ *  - Support of fI2CCLK frequencies other than 16Mhz
+ *  - Polled operation (code present but untested)
+ *  - SMBus support
+ *  - Multi-master support
+ *  - IPMI
+ *
+ * Test Environment:
+ *
+ *  - B-L072Z-LRWAN1
+ *
+ * Operational Status:
+ *
+ *  All supported features have been tested and found to be operational.
+ *
+ *  Although the RELOAD capability has been tested as it was required to
+ *  implement the I2C_M_NOSTART flag on F3 hardware, the associated
+ *  logic to support the transfer messages with more than 255 byte
+ *  payloads has not been  tested as the author lacked access to a real
+ *  device supporting these types of transfers.
+ *
+ * Performance Benchmarks: TBD
+ *
+ *  Time to transfer two messages, each a byte in length, in addition to the
+ *  START condition, in interrupt mode:
+ *
+ *  DEBUG enabled (development): TBDms
+ *      Excessive delay here is caused by printing to the console and
+ *      is of no concern.
+ *
+ *  DEBUG disabled (production): TBSus
+ *      Between Messages: TBDus
+ *      Between Bytes: TBDus
+ *
+ * Implementation:
+ *
+ *  - Device: structure as defined by the nuttx/i2c/i2c.h
+ *
+ *  - Instance: represents each individual access to the I2C driver, obtained by
+ *      the i2c_init(); it extends the Device structure from the nuttx/i2c/i2c.h;
+ *      Instance points to OPS, to common I2C Hardware private data and contains
+ *      its own private data including frequency, address and mode of operation.
+ *
+ *  - Private: Private data of an I2C Hardware
+ *
+ * High Level Functional Description
+ *
+ * This driver works with I2C "messages" (struct i2c_msg_s), which carry a buffer
+ * intended to transfer data to, or store data read from, the I2C bus.
+ *
+ * As the hardware can only transmit or receive one byte at a time the basic job
+ * of the driver (and the ISR specifically) is to process each message in the
+ * order they are stored in the message list, one byte at a time.  When
+ * no messages are left the ISR exits and returns the result to the caller.
+ *
+ * The order of the list of I2C messages provided to the driver is important and
+ * dependent upon the hardware in use.  A typical I2C transaction between the F3
+ * as an I2C Master and some other IC as a I2C Slave requires two messages that
+ * communicate the:
+ *
+ *    1) Subaddress (register offset on the slave device)
+ *    2) Data sent to or read from the device
+ *
+ * These messages will typically be one byte in length but may be up to 2^31
+ * bytes in length.  Incidentally, the maximum length is limited only because
+ * i2c_msg_s.length is a signed int for some odd reason.
+ *
+ * Interrupt mode relies on the following interrupt events:
+ *
+ *   TXIS  - Transmit interrupt
+ *           (data transmitted to bus and acknowledged)
+ *   NACKF - Not Acknowledge Received
+ *           (data transmitted to bus and NOT acknowledged)
+ *   RXNE  - Receive interrupt
+ *           (data received from bus)
+ *   TC    - Transfer Complete
+ *           (All bytes in message transferred)
+ *   TCR   - Transfer Complete (Reload)
+ *           (Current batch of bytes in message transferred)
+ *
+ * The driver currently supports Single Master mode only.  Slave mode is not
+ * supported.  Additionally, the driver runs in Software End Mode (AUTOEND
+ * disabled) so the driver is responsible for telling the hardware what to
+ * do at the end of a transfer.
+ *
+ * ------------------------------------------------------------------------------
+ *
+ * Configuration:
+ *
+ *  To use this driver, enable the following configuration variable:
+ *
+ *    CONFIG_STM32F0L0G0_I2C1
+ *    CONFIG_STM32F0L0G0_I2C2
+ *    CONFIG_STM32F0L0G0_I2C3
+ *    CONFIG_STM32F0L0G0_I2C4
+ *
+ *  To configure the ISR timeout using fixed values (CONFIG_STM32F0L0G0_I2C_DYNTIMEO=n):
+ *
+ *    CONFIG_STM32F0L0G0_I2CTIMEOSEC   (Timeout in seconds)
+ *    CONFIG_STM32F0L0G0_I2CTIMEOMS    (Timeout in milliseconds)
+ *    CONFIG_STM32F0L0G0_I2CTIMEOTICKS (Timeout in ticks)
+ *
+ *  To configure the ISR timeout using dynamic values (CONFIG_STM32F0L0G0_I2C_DYNTIMEO=y):
+ *
+ *    CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE  (Timeout in microseconds per byte)
+ *    CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP    (Timeout for start/stop in milliseconds)
+ *
+ *  Debugging output enabled with:
+ *
+ *    CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_{ERROR|WARN|INFO}
+ *
+ *  ISR Debugging output may be enabled with:
+ *
+ *    CONFIG_DEBUG_FEATURES and CONFIG_DEBUG_I2C_INFO
+ *
+ * ------------------------------------------------------------------------------
+ *
+ * References:
+ *
+ *  RM0431:
+ *     ST STM322xxx and STM323xxx Reference Manual
+ *     Document ID: DocID029480 Revision 1, Jan 2017.
+ *
+ *  RM0316:
+ *     ST STM326xxx and STM327xxx Reference Manual
+ *     Document ID: DocID028270 Revision 2, April 2016.
+ *
+ *  DATASHEET:
+ *     ST STM3277xx/STM3278Ax/STM3279x Datasheet
+ *     Document ID: DocID028294, Revision 3, May 2016.
+ *
+ *  ERRATA:
+ *     STM326xxx/STM327xxx Errata sheet Rev A device limitations
+ *     Document ID: DocID028806, Revision 2, April 2016.
+ *
+ *  I2CSPEC:
+ *     I2C Bus Specification and User Manual
+ *     Document ID: UM10204, Revision 6, April 2014.
+ *
+ * ------------------------------------------------------------------------------
+ */
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "up_arch.h"
+
+#include "stm32_rcc.h"
+#include "stm32_i2c.h"
+#include "stm32_gpio.h"
+
+/* At least one I2C peripheral must be enabled */
+
+#if defined(CONFIG_STM32F0L0G0_I2C1) || defined(CONFIG_STM32F0L0G0_I2C2) || \
+    defined(CONFIG_STM32F0L0G0_I2C3) || defined(CONFIG_STM32F0L0G0_I2C4)
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+#undef INVALID_CLOCK_SOURCE
+
+#warning TODO: check I2C clock source. It must be HSI!
+
+/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used.  Instead,
+ * CPU-intensive polling will be used.
+ */
+
+/* Interrupt wait timeout in seconds and milliseconds */
+
+#if !defined(CONFIG_STM32F0L0G0_I2CTIMEOSEC) && !defined(CONFIG_STM32F0L0G0_I2CTIMEOMS)
+#  define CONFIG_STM32F0L0G0_I2CTIMEOSEC 0
+#  define CONFIG_STM32F0L0G0_I2CTIMEOMS  500   /* Default is 500 milliseconds */
+#  warning "Using Default 500 Ms Timeout"
+#elif !defined(CONFIG_STM32F0L0G0_I2CTIMEOSEC)
+#  define CONFIG_STM32F0L0G0_I2CTIMEOSEC 0     /* User provided milliseconds */
+#elif !defined(CONFIG_STM32F0L0G0_I2CTIMEOMS)
+#  define CONFIG_STM32F0L0G0_I2CTIMEOMS  0     /* User provided seconds */
+#endif
+
+/* Interrupt wait time timeout in system timer ticks */
+
+#ifndef CONFIG_STM32F0L0G0_I2CTIMEOTICKS
+#  define CONFIG_STM32F0L0G0_I2CTIMEOTICKS \
+    (SEC2TICK(CONFIG_STM32F0L0G0_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F0L0G0_I2CTIMEOMS))
+#endif
+
+#ifndef CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP
+#  define CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F0L0G0_I2CTIMEOTICKS)
+#endif
+
+/* Macros to convert a I2C pin to a GPIO output */
+
+#define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\
+                      GPIO_SPEED_50MHz | GPIO_OUTPUT_SET)
+
+#define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
+
+#define I2C_CR1_TXRX      (I2C_CR1_RXIE | I2C_CR1_TXIE)
+#define I2C_CR1_ALLINTS   (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE)
+
+/* Unused bit in I2c_ISR used to communicate a bad state has occurred in
+ * the isr processing
+*/
+
+#define I2C_INT_BAD_STATE 0x8000000
+
+/* I2C event tracing
+ *
+ * To enable tracing statements which show the details of the state machine
+ * enable the following configuration variable:
+ *
+ * CONFIG_I2C_TRACE
+ *
+ * Note: This facility uses syslog, which sends output to the console by
+ * default.  No other debug configuration variables are required.
+ */
+
+#ifndef CONFIG_I2C_TRACE
+#  define stm32_i2c_tracereset(p)
+#  define stm32_i2c_tracenew(p,s)
+#  define stm32_i2c_traceevent(p,e,a)
+#  define stm32_i2c_tracedump(p)
+#endif
+
+#ifndef CONFIG_I2C_NTRACE
+#  define CONFIG_I2C_NTRACE 32
+#endif
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+
+/* Interrupt state */
+
+enum stm32_intstate_e
+{
+  INTSTATE_IDLE = 0,      /* No I2C activity */
+  INTSTATE_WAITING,       /* Waiting for completion of interrupt activity */
+  INTSTATE_DONE,          /* Interrupt activity complete */
+};
+
+/* Trace events */
+
+enum stm32_trace_e
+{
+  I2CEVENT_NONE = 0,
+  I2CEVENT_STATE_ERROR,
+  I2CEVENT_ISR_SHUTDOWN,
+  I2CEVENT_ISR_CALL,
+  I2CEVENT_ISR_EMPTY_CALL,
+  I2CEVENT_MSG_HANDLING,
+  I2CEVENT_POLL_NOT_READY,
+  I2CEVENT_EMPTY_MSG,
+  I2CEVENT_START,
+  I2CEVENT_ADDRESS_ACKED,
+  I2CEVENT_ADDRESS_NACKED,
+  I2CEVENT_NACK,
+  I2CEVENT_READ,
+  I2CEVENT_READ_ERROR,
+  I2CEVENT_WRITE_TO_DR,
+  I2CEVENT_WRITE_STOP,
+  I2CEVENT_WRITE_RESTART,
+  I2CEVENT_WRITE_NO_RESTART,
+  I2CEVENT_WRITE_ERROR,
+  I2CEVENT_WRITE_FLAG_ERROR,
+  I2CEVENT_TC_RESTART,
+  I2CEVENT_TC_NO_RESTART
+};
+
+/* Trace data */
+
+struct stm32_trace_s
+{
+  uint32_t status;             /* I2C 32-bit SR2|SR1 status */
+  uint32_t count;              /* Interrupt count when status change */
+  enum stm32_intstate_e event; /* Last event that occurred with this status */
+  uint32_t parm;               /* Parameter associated with the event */
+  clock_t time;                /* First of event or first status */
+};
+
+/* I2C Device hardware configuration */
+
+struct stm32_i2c_config_s
+{
+  uint32_t base;              /* I2C base address */
+  uint32_t clk_bit;           /* Clock enable bit */
+  uint32_t reset_bit;         /* Reset bit */
+  uint32_t scl_pin;           /* GPIO configuration for SCL as SCL */
+  uint32_t sda_pin;           /* GPIO configuration for SDA as SDA */
+#ifndef CONFIG_I2C_POLLED
+  uint32_t irq;               /* IRQ */
+#endif
+};
+
+/* I2C Device Private Data */
+
+struct stm32_i2c_priv_s
+{
+  const struct stm32_i2c_config_s *config; /* Port configuration */
+  int refs;                    /* Reference count */
+  sem_t sem_excl;              /* Mutual exclusion semaphore */
+#ifndef CONFIG_I2C_POLLED
+  sem_t sem_isr;               /* Interrupt wait semaphore */
+#endif
+  volatile uint8_t intstate;   /* Interrupt handshake (see enum stm32_intstate_e) */
+
+  uint8_t msgc;                /* Message count */
+  struct i2c_msg_s *msgv;      /* Message list */
+  uint8_t *ptr;                /* Current message buffer */
+  uint32_t frequency;          /* Current I2C frequency */
+  int dcnt;                    /* Current message bytes remaining to transfer */
+  uint16_t flags;              /* Current message flags */
+  bool astart;                 /* START sent */
+
+  /* I2C trace support */
+
+#ifdef CONFIG_I2C_TRACE
+  int tndx;                    /* Trace array index */
+  clock_t start_time;          /* Time when the trace was started */
+
+  /* The actual trace data */
+
+  struct stm32_trace_s trace[CONFIG_I2C_NTRACE];
+#endif
+
+  uint32_t status;             /* End of transfer SR2|SR1 status */
+
+#ifdef CONFIG_PM
+  struct pm_callback_s pm_cb;  /* PM callbacks */
+#endif
+};
+
+/* I2C Device, Instance */
+
+struct stm32_i2c_inst_s
+{
+  const struct i2c_ops_s  *ops;  /* Standard I2C operations */
+  struct stm32_i2c_priv_s *priv; /* Common driver private data structure */
+};
+
+/************************************************************************************
+ * Private Function Prototypes
+ ************************************************************************************/
+
+static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv,
+                                        uint8_t offset);
+static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset,
+                                    uint16_t value);
+static inline void stm32_i2c_putreg32(FAR struct stm32_i2c_priv_s *priv, uint8_t offset,
+                                    uint32_t value);
+static inline void stm32_i2c_modifyreg32(FAR struct stm32_i2c_priv_s *priv,
+                                         uint8_t offset, uint32_t clearbits,
+                                         uint32_t setbits);
+static inline void stm32_i2c_sem_wait(FAR struct i2c_master_s *dev);
+#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
+static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs);
+#endif /* CONFIG_STM32F0L0G0_I2C_DYNTIMEO */
+static inline int  stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv);
+static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv);
+static inline void stm32_i2c_sem_post(FAR struct i2c_master_s *dev);
+static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev);
+static inline void stm32_i2c_sem_destroy(FAR struct i2c_master_s *dev);
+#ifdef CONFIG_I2C_TRACE
+static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv);
+static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t status);
+static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
+                               enum stm32_trace_e event, uint32_t parm);
+static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv);
+#endif /* CONFIG_I2C_TRACE */
+static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv,
+                               uint32_t frequency);
+static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv);
+static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv);
+static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv);
+static int stm32_i2c_isr_process(struct stm32_i2c_priv_s * priv);
+#ifndef CONFIG_I2C_POLLED
+static int stm32_i2c_isr(int irq, void *context, FAR void *arg);
+#endif
+static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv);
+static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv);
+
+static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
+                             int count);
+static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
+                              int count);
+#ifdef CONFIG_I2C_RESET
+static int stm32_i2c_reset(FAR struct i2c_master_s * dev);
+#endif
+#ifdef CONFIG_PM
+static int stm32_i2c_pm_prepare(FAR struct pm_callback_s *cb, int domain,
+                                enum pm_state_e pmstate);
+#endif
+
+/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F0L0G0_I2C1
+static const struct stm32_i2c_config_s stm32_i2c1_config =
+{
+  .base          = STM32_I2C1_BASE,
+  .clk_bit       = RCC_APB1ENR_I2C1EN,
+  .reset_bit     = RCC_APB1RSTR_I2C1RST,
+  .scl_pin       = GPIO_I2C1_SCL,
+  .sda_pin       = GPIO_I2C1_SDA,
+#ifndef CONFIG_I2C_POLLED
+  .irq        = STM32_IRQ_I2C1
+#endif
+};
+
+static struct stm32_i2c_priv_s stm32_i2c1_priv =
+{
+  .config        = &stm32_i2c1_config,
+  .refs          = 0,
+  .intstate      = INTSTATE_IDLE,
+  .msgc          = 0,
+  .msgv          = NULL,
+  .ptr           = NULL,
+  .frequency     = 0,
+  .dcnt          = 0,
+  .flags         = 0,
+  .status        = 0,
+#ifdef CONFIG_PM
+  .pm_cb.prepare = stm32_i2c_pm_prepare,
+#endif
+};
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_I2C2
+static const struct stm32_i2c_config_s stm32_i2c2_config =
+{
+  .base          = STM32_I2C2_BASE,
+  .clk_bit       = RCC_APB1ENR_I2C2EN,
+  .reset_bit     = RCC_APB1RSTR_I2C2RST,
+  .scl_pin       = GPIO_I2C2_SCL,
+  .sda_pin       = GPIO_I2C2_SDA,
+#ifndef CONFIG_I2C_POLLED
+  .irq        = STM32_IRQ_I2C1
+#endif
+};
+
+static struct stm32_i2c_priv_s stm32_i2c2_priv =
+{
+  .config        = &stm32_i2c2_config,
+  .refs          = 0,
+  .intstate      = INTSTATE_IDLE,
+  .msgc          = 0,
+  .msgv          = NULL,
+  .ptr           = NULL,
+  .frequency     = 0,
+  .dcnt          = 0,
+  .flags         = 0,
+  .status        = 0,
+#ifdef CONFIG_PM
+  .pm_cb.prepare = stm32_i2c_pm_prepare,
+#endif
+};
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_I2C3
+static const struct stm32_i2c_config_s stm32_i2c3_config =
+{
+  .base          = STM32_I2C3_BASE,
+  .clk_bit       = RCC_APB1ENR_I2C3EN,
+  .reset_bit     = RCC_APB1RSTR_I2C3RST,
+  .scl_pin       = GPIO_I2C3_SCL,
+  .sda_pin       = GPIO_I2C3_SDA,
+#ifndef CONFIG_I2C_POLLED
+  .irq        = STM32_IRQ_I2C1
+#endif
+};
+
+static struct stm32_i2c_priv_s stm32_i2c3_priv =
+{
+  .config        = &stm32_i2c3_config,
+  .refs          = 0,
+  .intstate      = INTSTATE_IDLE,
+  .msgc          = 0,
+  .msgv          = NULL,
+  .ptr           = NULL,
+  .frequency     = 0,
+  .dcnt          = 0,
+  .flags         = 0,
+  .status        = 0,
+#ifdef CONFIG_PM
+  .pm_cb.prepare = stm32_i2c_pm_prepare,
+#endif
+};
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_I2C4
+static const struct stm32_i2c_config_s stm32_i2c4_config =
+{
+  .base          = STM32_I2C4_BASE,
+  .clk_bit       = RCC_APB1ENR_I2C4EN,
+  .reset_bit     = RCC_APB1RSTR_I2C4RST,
+  .scl_pin       = GPIO_I2C4_SCL,
+  .sda_pin       = GPIO_I2C4_SDA,
+#ifndef CONFIG_I2C_POLLED
+  .irq        = STM32_IRQ_I2C1
+#endif
+};
+
+static struct stm32_i2c_priv_s stm32_i2c4_priv =
+{
+  .config        = &stm32_i2c4_config,
+  .refs          = 0,
+  .intstate      = INTSTATE_IDLE,
+  .msgc          = 0,
+  .msgv          = NULL,
+  .ptr           = NULL,
+  .frequency     = 0,
+  .dcnt          = 0,
+  .flags         = 0,
+  .status        = 0,
+#ifdef CONFIG_PM
+  .pm_cb.prepare = stm32_i2c_pm_prepare,
+#endif
+};
+#endif
+
+/* Device Structures, Instantiation */
+
+static const struct i2c_ops_s stm32_i2c_ops =
+{
+  .transfer      = stm32_i2c_transfer,
+#ifdef CONFIG_I2C_RESET
+  .reset         = stm32_i2c_reset,
+#endif
+};
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_i2c_getreg
+ *
+ * Description:
+ *   Get a 16-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline uint16_t stm32_i2c_getreg(FAR struct stm32_i2c_priv_s *priv,
+                                        uint8_t offset)
+{
+  return getreg16(priv->config->base + offset);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_getreg32
+ *
+ * Description:
+ *   Get a 32-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline uint32_t stm32_i2c_getreg32(FAR struct stm32_i2c_priv_s *priv,
+                                          uint8_t offset)
+{
+  return getreg32(priv->config->base + offset);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_putreg
+ *
+ * Description:
+ *  Put a 16-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t offset,
+                                    uint16_t value)
+{
+  putreg16(value, priv->config->base + offset);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_putreg32
+ *
+ * Description:
+ *  Put a 32-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_putreg32(FAR struct stm32_i2c_priv_s *priv,
+                                      uint8_t offset, uint32_t value)
+{
+  putreg32(value, priv->config->base + offset);
+}
+
+
+/************************************************************************************
+ * Name: stm32_i2c_modifyreg32
+ *
+ * Description:
+ *   Modify a 32-bit register value by offset
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_modifyreg32(FAR struct stm32_i2c_priv_s *priv,
+                                         uint8_t offset, uint32_t clearbits,
+                                         uint32_t setbits)
+{
+  modifyreg32(priv->config->base + offset, clearbits, setbits);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_sem_wait
+ *
+ * Description:
+ *   Take the exclusive access, waiting as necessary
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_sem_wait(FAR struct i2c_master_s *dev)
+{
+  int ret;
+
+  do
+    {
+      /* Take the semaphore (perhaps waiting) */
+
+      ret = nxsem_wait(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl);
+
+      /* The only case that an error should occur here is if the wait was
+       * awakened by a signal.
+       */
+
+      DEBUGASSERT(ret == OK || ret == -EINTR);
+    }
+  while (ret == -EINTR);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_tousecs
+ *
+ * Description:
+ *   Return a micro-second delay based on the number of bytes left to be processed.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
+static useconds_t stm32_i2c_tousecs(int msgc, FAR struct i2c_msg_s *msgs)
+{
+  size_t bytecount = 0;
+  int i;
+
+  /* Count the number of bytes left to process */
+
+  for (i = 0; i < msgc; i++)
+    {
+      bytecount += msgs[i].length;
+    }
+
+  /* Then return a number of microseconds based on a user provided scaling
+   * factor.
+   */
+
+  return (useconds_t)(CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE * bytecount);
+}
+#endif
+
+/************************************************************************************
+ * Name: stm32_i2c_enableinterrupts
+ *
+ * Description:
+ *   Enable I2C interrupts
+ *
+ ************************************************************************************/
+
+#ifndef CONFIG_I2C_POLLED
+static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv)
+{
+    stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE));
+}
+#endif
+
+/************************************************************************************
+ * Name: stm32_i2c_sem_waitdone
+ *
+ * Description:
+ *   Wait for a transfer to complete
+ *
+ * There are two versions of this function.  The first is included when using
+ * interrupts while the second is used if polling (CONFIG_I2C_POLLED=y).
+ *
+ ************************************************************************************/
+
+#ifndef CONFIG_I2C_POLLED
+static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
+{
+  struct timespec abstime;
+  irqstate_t flags;
+  int ret;
+
+  flags = enter_critical_section();
+
+  /* Enable I2C interrupts */
+
+  /* The TXIE and RXIE interrupts are enabled initially in stm32_i2c_process.
+   * The remainder of the interrupts, including error-related, are enabled here.
+   */
+
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0,
+                        (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX));
+
+  /* Signal the interrupt handler that we are waiting */
+
+  priv->intstate = INTSTATE_WAITING;
+  do
+    {
+      /* Get the current time */
+
+      (void)clock_gettime(CLOCK_REALTIME, &abstime);
+
+      /* Calculate a time in the future */
+
+#if CONFIG_STM32F0L0G0_I2CTIMEOSEC > 0
+      abstime.tv_sec += CONFIG_STM32F0L0G0_I2CTIMEOSEC;
+#endif
+
+      /* Add a value proportional to the number of bytes in the transfer */
+
+#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
+      abstime.tv_nsec += 1000 * stm32_i2c_tousecs(priv->msgc, priv->msgv);
+      if (abstime.tv_nsec >= 1000 * 1000 * 1000)
+        {
+          abstime.tv_sec++;
+          abstime.tv_nsec -= 1000 * 1000 * 1000;
+        }
+
+#elif CONFIG_STM32F0L0G0_I2CTIMEOMS > 0
+      abstime.tv_nsec += CONFIG_STM32F0L0G0_I2CTIMEOMS * 1000 * 1000;
+      if (abstime.tv_nsec >= 1000 * 1000 * 1000)
+        {
+          abstime.tv_sec++;
+          abstime.tv_nsec -= 1000 * 1000 * 1000;
+        }
+#endif
+      /* Wait until either the transfer is complete or the timeout expires */
+
+      ret = nxsem_timedwait(&priv->sem_isr, &abstime);
+      if (ret < 0 && ret != -EINTR)
+        {
+          /* Break out of the loop on irrecoverable errors.  This would
+           * include timeouts and mystery errors reported by nxsem_timedwait.
+           * NOTE that we try again if we are awakened by a signal (EINTR).
+           */
+
+          break;
+        }
+    }
+
+  /* Loop until the interrupt level transfer is complete. */
+
+  while (priv->intstate != INTSTATE_DONE);
+
+  /* Set the interrupt state back to IDLE */
+
+  priv->intstate = INTSTATE_IDLE;
+
+  /* Disable I2C interrupts */
+
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0);
+
+  leave_critical_section(flags);
+  return ret;
+}
+#else
+static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
+{
+  clock_t timeout;
+  clock_t start;
+  clock_t elapsed;
+  int ret;
+
+  /* Get the timeout value */
+
+#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
+  timeout = USEC2TICK(stm32_i2c_tousecs(priv->msgc, priv->msgv));
+#else
+  timeout = CONFIG_STM32F0L0G0_I2CTIMEOTICKS;
+#endif
+
+  /* Signal the interrupt handler that we are waiting.  NOTE:  Interrupts
+   * are currently disabled but will be temporarily re-enabled below when
+   * nxsem_timedwait() sleeps.
+   */
+
+  priv->intstate = INTSTATE_WAITING;
+  start = clock_systimer();
+
+  do
+    {
+      /* Calculate the elapsed time */
+
+      elapsed = clock_systimer() - start;
+
+      /* Poll by simply calling the timer interrupt handler until it
+       * reports that it is done.
+       */
+
+      stm32_i2c_isr_process(priv);
+    }
+
+  /* Loop until the transfer is complete. */
+
+  while (priv->intstate != INTSTATE_DONE && elapsed < timeout);
+
+  i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: 0x%08x\n",
+          priv->intstate, (long)elapsed, (long)timeout, priv->status);
+
+  /* Set the interrupt state back to IDLE */
+
+  ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT;
+  priv->intstate = INTSTATE_IDLE;
+  return ret;
+}
+#endif
+
+/************************************************************************************
+ * Name: stm32_i2c_set_7bit_address
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32_i2c_set_7bit_address(FAR struct stm32_i2c_priv_s *priv)
+{
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK,
+                        ((priv->msgv->addr & 0x7F) << I2C_CR2_SADD7_SHIFT));
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_set_bytes_to_transfer
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32_i2c_set_bytes_to_transfer(FAR struct stm32_i2c_priv_s *priv,
+                               uint8_t n_bytes)
+{
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK,
+                        (n_bytes << I2C_CR2_NBYTES_SHIFT));
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_set_write_transfer_dir
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32_i2c_set_write_transfer_dir(FAR struct stm32_i2c_priv_s *priv)
+{
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_set_read_transfer_dir
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32_i2c_set_read_transfer_dir(FAR struct stm32_i2c_priv_s *priv)
+{
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_enable_reload
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32_i2c_enable_reload(FAR struct stm32_i2c_priv_s *priv)
+{
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_disable_reload
+ *
+ * Description:
+ *
+ ************************************************************************************/
+
+static inline void
+stm32_i2c_disable_reload(FAR struct stm32_i2c_priv_s *priv)
+{
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0);
+}
+
+
+/************************************************************************************
+ * Name: stm32_i2c_sem_waitstop
+ *
+ * Description:
+ *   Wait for a STOP to complete
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
+{
+  clock_t start;
+  clock_t elapsed;
+  clock_t timeout;
+  uint32_t cr;
+  uint32_t sr;
+
+  /* Select a timeout */
+
+#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
+  timeout = USEC2TICK(CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP);
+#else
+  timeout = CONFIG_STM32F0L0G0_I2CTIMEOTICKS;
+#endif
+
+  /* Wait as stop might still be in progress */
+
+  start = clock_systimer();
+  do
+    {
+      /* Calculate the elapsed time */
+
+      elapsed = clock_systimer() - start;
+
+      /* Check for STOP condition */
+
+      cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET);
+      if ((cr & I2C_CR2_STOP) == 0)
+        {
+          return;
+        }
+
+      /* Check for timeout error */
+
+      sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
+      if ((sr & I2C_INT_TIMEOUT) != 0)
+        {
+          return;
+        }
+
+    }
+
+  /* Loop until the stop is complete or a timeout occurs. */
+
+  while (elapsed < timeout);
+
+  /* If we get here then a timeout occurred with the STOP condition
+   * still pending.
+   */
+
+  i2cinfo("Timeout with CR: %04x SR: %04x\n", cr, sr);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_sem_post
+ *
+ * Description:
+ *   Release the mutual exclusion semaphore
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_sem_post(FAR struct i2c_master_s *dev)
+{
+  nxsem_post(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_sem_init
+ *
+ * Description:
+ *   Initialize semaphores
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_sem_init(FAR struct i2c_master_s *dev)
+{
+  nxsem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl, 0, 1);
+
+#ifndef CONFIG_I2C_POLLED
+  /* This semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  nxsem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, 0, 0);
+  nxsem_setprotocol(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr, SEM_PRIO_NONE);
+#endif
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_sem_destroy
+ *
+ * Description:
+ *   Destroy semaphores.
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_sem_destroy(FAR struct i2c_master_s *dev)
+{
+  nxsem_destroy(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl);
+#ifndef CONFIG_I2C_POLLED
+  nxsem_destroy(&((struct stm32_i2c_inst_s *)dev)->priv->sem_isr);
+#endif
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_trace*
+ *
+ * Description:
+ *   I2C trace instrumentation
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_I2C_TRACE
+static void stm32_i2c_traceclear(FAR struct stm32_i2c_priv_s *priv)
+{
+  struct stm32_trace_s *trace = &priv->trace[priv->tndx];
+
+  trace->status = 0;              /* I2C 32-bit status */
+  trace->count  = 0;              /* Interrupt count when status change */
+  trace->event  = I2CEVENT_NONE;  /* Last event that occurred with this status */
+  trace->parm   = 0;              /* Parameter associated with the event */
+  trace->time   = 0;              /* Time of first status or event */
+}
+
+static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv)
+{
+  /* Reset the trace info for a new data collection */
+
+  priv->tndx       = 0;
+  priv->start_time = clock_systimer();
+  stm32_i2c_traceclear(priv);
+}
+
+static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv,
+                               uint32_t status)
+{
+  struct stm32_trace_s *trace = &priv->trace[priv->tndx];
+
+  /* Is the current entry uninitialized?   Has the status changed? */
+
+  if (trace->count == 0 || status != trace->status)
+    {
+      /* Yes.. Was it the status changed?  */
+
+      if (trace->count != 0)
+        {
+          /* Yes.. bump up the trace index (unless we are out of trace entries) */
+
+          if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
+            {
+              i2cerr("ERROR: Trace table overflow\n");
+              return;
+            }
+
+          priv->tndx++;
+          trace = &priv->trace[priv->tndx];
+        }
+
+      /* Initialize the new trace entry */
+
+      stm32_i2c_traceclear(priv);
+      trace->status = status;
+      trace->count  = 1;
+      trace->time   = clock_systimer();
+    }
+  else
+    {
+      /* Just increment the count of times that we have seen this status */
+
+      trace->count++;
+    }
+}
+
+static void stm32_i2c_traceevent(FAR struct stm32_i2c_priv_s *priv,
+                                enum stm32_trace_e event, uint32_t parm)
+{
+  struct stm32_trace_s *trace;
+
+  if (event != I2CEVENT_NONE)
+    {
+      trace = &priv->trace[priv->tndx];
+
+      /* Initialize the new trace entry */
+
+      trace->event  = event;
+      trace->parm   = parm;
+
+      /* Bump up the trace index (unless we are out of trace entries) */
+
+      if (priv->tndx >= (CONFIG_I2C_NTRACE-1))
+        {
+          i2cerr("ERROR: Trace table overflow\n");
+          return;
+        }
+
+      priv->tndx++;
+      stm32_i2c_traceclear(priv);
+    }
+}
+
+static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
+{
+  struct stm32_trace_s *trace;
+  int i;
+
+  syslog(LOG_DEBUG, "Elapsed time: %d\n",
+         (int)(clock_systimer() - priv->start_time));
+
+  for (i = 0; i < priv->tndx; i++)
+    {
+      trace = &priv->trace[i];
+      syslog(LOG_DEBUG,
+             "%2d. STATUS: %08x COUNT: %3d EVENT: %2d PARM: %08x TIME: %d\n",
+             i+1, trace->status, trace->count,  trace->event, trace->parm,
+             (int)(trace->time - priv->start_time));
+    }
+}
+#endif /* CONFIG_I2C_TRACE */
+
+/************************************************************************************
+ * Name: stm32_i2c_setclock
+ *
+ * Description:
+ *
+ *   Sets the I2C bus clock frequency by configuring the I2C_TIMINGR register.
+ *
+ *   This function supports bus clock frequencies of:
+ *
+ *      1000Khz (Fast Mode+)
+ *      400Khz  (Fast Mode)
+ *      100Khz  (Standard Mode)
+ *      10Khz   (Standard Mode)
+ *
+ *   Attempts to set a different frequency will quietly provision the default
+ *   of 10Khz.
+ *
+ *   The only differences between the various modes of operation (std, fast,
+ *   fast+) are the bus clock speed and setup/hold times.  Setup/hold times are
+ *   specified as a MINIMUM time for the given mode, and naturally std mode
+ *   has the longest minimum times.  As a result, by provisioning setup/hold
+ *   times for std mode they are also compatible with fast/fast+, though some
+ *   performance degradation occurs in fast/fast+ as a result of the times
+ *   being somewhat longer than strictly required.  The values remain as they
+ *   are because reliability is favored over performance.
+ *
+ * Clock Selection:
+ *
+ *   The I2C peripheral clock can be provided by either PCLK1, SYSCLK or the HSI.
+ *
+ *    PCLK1 >------|\   I2CCLK
+ *   SYSCLK >------| |--------->
+ *      HSI >------|/
+ *
+ *   HSI is the default and is always 16Mhz.
+ *
+ *   SYSCLK can, in turn, be derived from the HSI, HSE, PPLCLK.
+ *
+ *      HSI >------|\
+ *                 | |  SYSCLK
+ *      PLL >------| |--------->
+ *                 | |
+ *      HSE >------|/
+ *
+ *
+ * References:
+ *
+ *  App Note AN4235 and the associated software STSW-STM32126.
+ *
+ ************************************************************************************/
+
+static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequency)
+{
+  uint8_t presc;
+  uint8_t scl_delay;
+  uint8_t sda_delay;
+  uint8_t scl_h_period;
+  uint8_t scl_l_period;
+
+  /* I2C peripheral must be disabled to update clocking configuration.
+   * This will SW reset the device.
+   */
+
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
+
+  if (frequency != priv->frequency)
+    {
+
+      /*  The Speed and timing calculation are based on the following
+       *  fI2CCLK = HSI and is 16Mhz
+       *  Analog filter is on,
+       *  Digital filter off
+       *  Rise Time is 120 ns and fall is 10ns
+       *  Mode is FastMode
+       */
+
+        if (frequency == 100000)
+          {
+            presc        = 0;
+            scl_delay    = 5;
+            sda_delay    = 0;
+            scl_h_period = 61;
+            scl_l_period = 89;
+
+          }
+        else if (frequency == 400000)
+           {
+             presc        = 0;
+             scl_delay    = 3;
+             sda_delay    = 0;
+             scl_h_period = 6;
+             scl_l_period = 24;
+           }
+         else if (frequency == 1000000)
+            {
+              presc        = 0;
+              scl_delay    = 2;
+              sda_delay    = 0;
+              scl_h_period = 1;
+              scl_l_period = 5;
+            }
+        else
+          {
+            presc        = 7;
+            scl_delay    = 0;
+            sda_delay    = 0;
+            scl_h_period = 35;
+            scl_l_period = 162;
+          }
+
+      uint32_t timingr =
+        (presc << I2C_TIMINGR_PRESC_SHIFT) |
+        (scl_delay << I2C_TIMINGR_SCLDEL_SHIFT) |
+        (sda_delay << I2C_TIMINGR_SDADEL_SHIFT) |
+        (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) |
+        (scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
+
+      stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr);
+      priv->frequency = frequency;
+    }
+
+  /* Enable I2C peripheral */
+
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_sendstart
+ *
+ * Description:
+ *   Send the START condition / force Master mode
+ *
+ *   A START condition in I2C consists of a single byte that contains both the
+ *   7 bit slave address and a read/write bit (0 = WRITE, 1 = READ).  If the
+ *   address is recognized by one of the slave devices that slave device will
+ *   ACK the byte so that data transfers can begin.
+ *
+ *   A RESTART (or repeated START per the I2CSPEC) is simply a START condition
+ *   issued in the middle of a transfer (i.e. after the initial START and before
+ *   a STOP).  A RESTART sends a new address byte and R/W bit to the bus. A
+ *   RESTART is optional in most cases but mandatory in the event the transfer
+ *   direction is changed.
+ *
+ *   Most of the time reading data from an I2C slave requires a WRITE of the
+ *   subaddress followed by a READ (and hence a RESTART in between).  Writing
+ *   to an I2C slave typically requires only WRITE operations and hence no
+ *   RESTARTs.
+ *
+ *   This function is therefore called both at the beginning of a transfer
+ *   (START) and at appropriate times during a transfer (RESTART).
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv)
+{
+  bool next_norestart = false;
+
+  /* Set the private "current message" data used in protocol processing.
+   *
+   * ptr:   A pointer to the start of the current message buffer.  This is
+   *        advanced after each byte in the current message is transferred.
+   *
+   * dcnt:  A running counter of the bytes in the current message waiting to be
+   *        transferred.  This is decremented each time a byte is transferred.
+   *        The hardware normally accepts a maximum of 255 bytes per transfer
+   *        but can support more via the RELOAD mechanism.  If dcnt initially
+   *        exceeds 255, the RELOAD mechanism will be enabled automatically.
+   *
+   * flags: Used to characterize handling of the current message.
+   *
+   *  The default flags value is 0 which specifies:
+   *
+   *   - A transfer direction of WRITE (R/W bit = 0)
+   *   - RESTARTs between all messages
+   *
+   *  The following flags can be used to override this behavior as follows:
+   *
+   *   - I2C_M_READ: Sets the transfer direction to READ (R/W bit = 1)
+   *   - I2C_M_NOSTART: Prevents a RESTART from being issued prior to the
+   *      transfer of the message (where allowed by the protocol).
+   *
+   */
+
+  priv->ptr   = priv->msgv->buffer;
+  priv->dcnt  = priv->msgv->length;
+  priv->flags = priv->msgv->flags;
+
+  if ((priv->flags & I2C_M_NOSTART) == 0)
+    {
+      /* Flag the first byte as an address byte */
+
+      priv->astart = true;
+    }
+
+  /* Enabling RELOAD allows the transfer of:
+   *
+   *  - individual messages with a payload exceeding 255 bytes
+   *  - multiple messages back to back without a RESTART in between
+   *
+   * so we enable it if either of those conditions exist and disable
+   * it otherwise.
+   */
+
+  /* Check if there are multiple messages and the next is a continuation */
+
+  if (priv->msgc > 1)
+    {
+      next_norestart = (((priv->msgv + 1)->flags & I2C_M_NOSTART) != 0);
+    }
+
+  if (next_norestart || priv->dcnt > 255)
+    {
+      i2cinfo("RELOAD enabled: dcnt = %i msgc = %i\n",
+          priv->dcnt, priv->msgc);
+      stm32_i2c_enable_reload(priv);
+    }
+  else
+    {
+      i2cinfo("RELOAD disable: dcnt = %i msgc = %i\n",
+          priv->dcnt, priv->msgc);
+      stm32_i2c_disable_reload(priv);
+    }
+
+  /* Set the number of bytes to transfer (I2C_CR2->NBYTES) to the number of
+   * bytes in the current message or 255, whichever is lower so as to not
+   * exceed the hardware maximum allowed.
+   */
+
+  if (priv->dcnt > 255)
+    {
+      stm32_i2c_set_bytes_to_transfer(priv, 255);
+    }
+  else
+    {
+      stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
+    }
+
+  /* Set the (7 bit) address.
+   * 10 bit addressing is not yet supported.
+   */
+
+  stm32_i2c_set_7bit_address(priv);
+
+  /* The flag of the current message is used to determine the direction of
+   * transfer required for the current message.
+   */
+
+  if (priv->flags & I2C_M_READ)
+    {
+      stm32_i2c_set_read_transfer_dir(priv);
+    }
+  else
+    {
+      stm32_i2c_set_write_transfer_dir(priv);
+    }
+
+  /* Set the I2C_CR2->START bit to 1 to instruct the hardware to send the
+   * START condition using the address and transfer direction data entered.
+   */
+
+  i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n",
+          priv->dcnt, priv->msgc, priv->flags);
+
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_sendstop
+ *
+ * Description:
+ *   Send the STOP conditions
+ *
+ *   A STOP condition can be requested by setting the STOP bit in the I2C_CR2
+ *   register. Setting the STOP bit clears the TC flag and the STOP condition is
+ *   sent on the bus.
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_sendstop(FAR struct stm32_i2c_priv_s *priv)
+{
+  i2cinfo("Sending STOP\n");
+  stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0);
+
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_getstatus
+ *
+ * Description:
+ *   Get 32-bit status (SR1 and SR2 combined)
+ *
+ ************************************************************************************/
+
+static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv)
+{
+  return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_clearinterrupts
+ *
+ * Description:
+ *  Clear all interrupts
+ *
+ ************************************************************************************/
+
+static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv)
+{
+  stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_isr_process
+ *
+ * Description:
+ *  Common interrupt service routine (ISR) that handles I2C protocol logic.
+ *  This is instantiated for each configured I2C interface (I2C1, I2C2, I2C3).
+ *
+ *  This ISR is activated and deactivated by:
+ *
+ *   stm32_i2c_process
+ *    and
+ *   stm32_i2c_waitdone
+ *
+ * Input Parameters:
+ *   priv - The private struct of the I2C driver.
+ *
+ ************************************************************************************/
+
+static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
+{
+  uint32_t status;
+
+  /* Get state of the I2C controller */
+
+  status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
+
+  i2cinfo("ENTER: status = 0x%08x\n", status);
+
+  /* Update private version of the state assuming a good state */
+
+  priv->status = status & ~I2C_INT_BAD_STATE;
+
+  /* If this is a new transmission set up the trace table accordingly */
+
+  stm32_i2c_tracenew(priv, status);
+  stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0);
+
+  /* --------------------- Start of I2C protocol handling -------------------- */
+
+  /* I2C protocol logic follows. It's organized in an if else chain such that
+   * only one mode of operation is executed every time the ISR is called.
+   *
+   * If you need to add additional states to support new features be sure they
+   * continue the chain (i.e. begin with "else if") and are placed before the
+   * empty call / error states at the end of the chain.
+   */
+
+  /* NACK Handling
+   *
+   * This branch is only triggered when the NACK (Not Acknowledge Received)
+   * interrupt occurs.  This interrupt will only fire when the I2C_CR1->NACKIE
+   * bit is 1.
+   *
+   * I2C_ISR->NACKF is set by hardware when a NACK is received after a byte
+   * is transmitted and the slave fails to acknowledge it.  This is the
+   * opposite of, and mutually exclusive to, the I2C_ISR->TXIS event.
+   *
+   * In response to the NACK the hardware automatically triggers generation
+   * of a STOP condition, terminating the transfer.  The only valid response
+   * to this state is to exit the ISR and report the failure.
+   *
+   * To differentiate an "address NACK" from a NACK that might occur during
+   * the transfer of other bytes the "priv->astart" parameter is
+   * used.  This flag is set to TRUE in sendstart() and set to FALSE when
+   * the first TXIS event is received, which would be after the first byte
+   * (the address) is transmitted successfully (acknowledged).
+   */
+
+  if (status & I2C_INT_NACK)
+    {
+
+      if (priv->astart == true)
+        {
+
+          /* NACK received on first (address) byte: address is invalid */
+
+          i2cinfo("NACK: Address invalid: dcnt=%i msgc=%i status=0x%08x\n",
+          priv->dcnt, priv->msgc, status);
+          stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr);
+        }
+      else
+        {
+          /* NACK received on regular byte */
+
+          i2cinfo("NACK: NACK received: dcnt=%i msgc=%i status=0x%08x\n",
+          priv->dcnt, priv->msgc, status);
+          stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr);
+        }
+
+      /* Set flags to terminate message transmission:
+       *
+       *   set message length to -1 to indicate last byte of message sent
+       *   set message count to 0 to indicate no more messages to send
+       *
+       * As we fall through the logic in the ISR the message handling block
+       * will be triggered by these flags and signal the ISR to terminate.
+       */
+
+      priv->dcnt = -1;
+      priv->msgc = 0;
+    }
+
+  /* Transmit Interrupt Status (TXIS) Handler
+   *
+   * This branch is only triggered when the TXIS interrupt occurs.  This
+   * interrupt will only fire when the I2C_CR1->TXIE bit is 1.
+   *
+   * This indicates the transmit data register I2C_TXDR has been emptied
+   * following the successful transmission of a byte and slave acknowledgment.
+   * In this state the I2C_TXDR register is ready to accept another byte for
+   * transmission.  The TXIS bit will be cleared automatically when the next
+   * byte is written to I2C_TXDR.
+   *
+   * The number of TXIS events during the transfer corresponds to NBYTES.
+   *
+   * The TXIS flag is not set when a NACK is received.
+   *
+   * When RELOAD is disabled (RELOAD=0) and NBYTES data have been transferred:
+   *
+   *   - In Automatic End Mode (AUTOEND=1), a STOP is automatically sent.
+   *
+   *     Note:  Automatic End Mode is not currently supported.
+   *
+   *   - In Software End Mode (AUTOEND=0), the TC event occurs and the SCL
+   *     line is stretched low in order to allow software actions (STOP,
+   *     RESTART).
+   *
+   * When RELOAD is enabled (RELOAD=1) and NBYTES bytes have been transferred
+   * a TCR event occurs instead and that handler simply updates NBYTES which
+   * causes TXIS events to continue.  The process repeats until all bytes in
+   * the message have been transferred.
+   */
+
+  else if ((priv->flags & (I2C_M_READ)) == 0 && (status & (I2C_ISR_TXIS)) != 0)
+    {
+
+      /* TXIS interrupt occurred, address valid, ready to transmit */
+
+      stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0);
+      i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08x\n",
+              priv->dcnt, priv->msgc, status);
+
+      /* The first event after the address byte is sent will be either TXIS
+       * or NACKF so it's safe to set the astart flag to false on
+       * the first TXIS event to indicate that it is no longer necessary to
+       * check for address validity.
+       */
+
+      if (priv->astart == true)
+        {
+          i2cinfo("TXIS: Address Valid\n");
+          stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, priv->msgv->addr);
+          priv->astart = false;
+        }
+
+      /* If one or more bytes in the current message are ready to transmit */
+
+      if (priv->dcnt > 0)
+        {
+          /* Prepare to transmit the current byte */
+
+          stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt);
+          i2cinfo("TXIS: Write Data 0x%02x\n", *priv->ptr);
+
+          /* Decrement byte counter */
+
+          priv->dcnt--;
+
+          /* If we are about to transmit the last byte in the current message */
+
+          if (priv->dcnt == 0)
+            {
+              /* If this is also the last message to send, disable RELOAD so
+               * TC fires next and issues STOP condition.  If we don't do this
+               * TCR will fire next, and since there are no bytes to send we
+               * can't write NBYTES to clear TCR so it will fire forever.
+               */
+
+              if (priv->msgc == 1)
+                {
+                  stm32_i2c_disable_reload(priv);
+                }
+            }
+
+          /* Transmit current byte */
+
+          stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr);
+
+          /* Advance to next byte */
+
+          priv->ptr++;
+        }
+      else
+        {
+          /* Unsupported state */
+
+          i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, status 0x%08x\n",
+          priv->dcnt, status);
+          stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0);
+
+          /* Indicate the bad state, so that on termination HW will be reset */
+
+          priv->status |= I2C_INT_BAD_STATE;
+        }
+
+      i2cinfo("TXIS: EXIT  dcnt = %i msgc = %i status 0x%08x\n",
+              priv->dcnt, priv->msgc, status);
+    }
+
+  /* Receive Buffer Not Empty (RXNE) State Handler
+   *
+   * This branch is only triggered when the RXNE interrupt occurs.  This
+   * interrupt will only fire when the I2C_CR1->RXIE bit is 1.
+   *
+   * This indicates data has been received from the bus and is waiting to
+   * be read from the I2C_RXDR register.  When I2C_RXDR is read this bit
+   * is automatically cleared and then an ACK or NACK is sent depending on
+   * whether we have more bytes to receive.
+   *
+   * When RELOAD is disabled and bytes remain to be transferred an acknowledge
+   * is automatically sent on the bus and the RXNE events continue until the
+   * last byte is received.
+   *
+   * When RELOAD is disabled (RELOAD=0) and BYTES have been transferred:
+   *
+   *   - In Automatic End Mode (AUTOEND=1), a NACK and a STOP are automatically
+   *     sent after the last received byte.
+   *
+   *     Note:  Automatic End Mode is not currently supported.
+   *
+   *   - In Software End Mode (AUTOEND=0), a NACK is automatically sent after
+   *     the last received byte, the TC event occurs and the SCL line is
+   *     stretched low in order to allow software actions (STOP, RESTART).
+   *
+   * When RELOAD is enabled (RELOAD=1) and NBYTES bytes have been transferred
+   * a TCR event occurs and that handler simply updates NBYTES which causes
+   * RXNE events to continue until all bytes have been transferred.
+   */
+
+  else if ((priv->flags & (I2C_M_READ)) != 0 && (status & I2C_ISR_RXNE) != 0)
+    {
+      /* When read flag is set and the receive buffer is not empty
+       * (RXNE is set) then the driver can read from the data register.
+       */
+
+      stm32_i2c_traceevent(priv, I2CEVENT_READ, 0);
+      i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08x\n",
+              priv->dcnt, priv->msgc, status);
+
+      /* If more bytes in the current message */
+
+      if (priv->dcnt > 0)
+        {
+          stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt);
+
+          /* No interrupts or context switches may occur in the following
+           * sequence.  Otherwise, additional bytes may be received.
+           */
+
+#ifdef CONFIG_I2C_POLLED
+          irqstate_t state = enter_critical_section();
+#endif
+          /* Receive a byte */
+
+          *priv->ptr = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET);
+
+          i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr);
+
+          /* Advance buffer to the next byte in the message */
+
+          priv->ptr++;
+
+          /* Signal byte received */
+
+          priv->dcnt--;
+
+#ifdef CONFIG_I2C_POLLED
+          leave_critical_section(state);
+#endif
+        }
+      else
+        {
+          /* Unsupported state */
+
+          stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0);
+          status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
+          i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, status 0x%08x\n",
+                 priv->dcnt, status);
+
+          /* Set signals that will terminate ISR and wake waiting thread */
+
+          priv->status |= I2C_INT_BAD_STATE;
+          priv->dcnt = -1;
+          priv->msgc = 0;
+        }
+
+      i2cinfo("RXNE: EXIT  dcnt = %i msgc = %i status 0x%08x\n",
+              priv->dcnt, priv->msgc, status);
+    }
+
+  /* Transfer Complete (TC) State Handler
+   *
+   * This branch is only triggered when the TC interrupt occurs.  This
+   * interrupt will only fire when:
+   *
+   * I2C_CR1->TCIE = 1 (Transfer Complete Interrupts Enabled)
+   * I2C_CR2->RELOAD = 0 (Reload Mode Disabled)
+   * I2C_CR2->AUTOEND = 0 (Autoend Mode Disabled, i.e. Software End Mode)
+   *
+   * This event indicates that the number of bytes initially defined
+   * in NBYTES, meaning, the number of bytes in the current message (priv->dcnt)
+   * has been successfully transmitted or received.
+   *
+   * When the TC interrupt occurs we have two choices to clear it and move
+   * on, regardless of the transfer direction:
+   *
+   *    - if more messages follow, perform a repeated START if required
+   *      and then fall through to transmit or receive the next message.
+   *
+   *    - if no messages follow, perform a STOP and set flags needed to
+   *      exit the ISR.
+   *
+   * The fact that the hardware must either RESTART or STOP when a TC
+   * event occurs explains why, when messages must be sent back to back
+   * (i.e. without a restart by specifying the I2C_M_NOSTART flag),
+   * RELOAD mode must be enabled and TCR event(s) must be generated
+   * instead.  See the TCR handler for more.
+   */
+
+  else if ((status & I2C_ISR_TC) != 0)
+    {
+      i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08x\n",
+              priv->dcnt, priv->msgc, status);
+
+      /* Prior message has been sent successfully. Or there could have
+       * been an error that set msgc to 0; So test for that case as
+       * we do not want to decrement msgc less then zero nor move msgv
+       * past the last message.
+       */
+
+      if (priv->msgc > 0)
+        {
+          priv->msgc--;
+        }
+
+      /* Are there additional messages remain to be transmitted / received? */
+
+      if (priv->msgc > 0)
+        {
+          i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n",
+          priv->dcnt, priv->msgc);
+          stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc);
+
+          /* Issue a START condition.
+           *
+           * Note that the first thing sendstart does is update the
+           * private structure "current message" data (ptr, dcnt, flags)
+           * so they all reflect the next message in the list so we
+           * update msgv before we get there.
+           */
+
+          /* Advance to the next message in the list */
+
+          priv->msgv++;
+
+          stm32_i2c_sendstart(priv);
+
+        }
+      else
+        {
+          /* Issue a STOP conditions.
+           *
+           * No additional messages to transmit / receive, so the
+           * transfer is indeed complete.  Nothing else to do but
+           * issue a STOP and exit.
+           */
+
+          i2cinfo("TC: STOP: dcnt=%i msgc=%i\n",
+          priv->dcnt, priv->msgc);
+          stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt);
+
+          stm32_i2c_sendstop(priv);
+
+          /* Set signals that will terminate ISR and wake waiting thread */
+
+          priv->dcnt = -1;
+          priv->msgc = 0;
+        }
+
+      i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08x\n",
+      priv->dcnt, priv->msgc, status);
+    }
+
+  /* Transfer Complete (Reload) State Handler
+   *
+   * This branch is only triggered when the TCR interrupt occurs.  This
+   * interrupt will only fire when:
+   *
+   *  I2C_CR1->TCIE = 1 (Transfer Complete Interrupts Enabled)
+   *  I2C_CR2->RELOAD = 1 (Reload Mode Active)
+   *  I2C_CR2->AUTOEND = 0 (Autoend Mode Disabled, i.e. Software End Mode)
+   *
+   * This is similar to the TC event except that TCR assumes that additional
+   * bytes are available to transfer.  So despite what its name might imply
+   * the transfer really isn't complete.
+   *
+   * There are two reasons RELOAD would be enabled:
+   *
+   *  1) We're trying to send a message with a payload greater than 255 bytes.
+   *  2) We're trying to send messages back to back, regardless of their
+   *     payload size, to avoid a RESTART (i.e. I2C_M_NOSTART flag is set).
+   *
+   * These conditions may be true simultaneously, as would be the case if
+   * we're sending multiple messages with payloads > 255 bytes.   So we only
+   * advance to the next message if we arrive here and dcnt is 0, meaning,
+   * we're finished with the last message and ready to move to the next.
+   *
+   * This logic supports the transfer of bytes limited only by the size of
+   * the i2c_msg_s length variable.  The SCL line will be stretched low
+   * until NBYTES is written with a non-zero value, allowing the transfer
+   * to continue.
+   *
+   * TODO: RESTARTs are required by the I2CSPEC if the next message transfer
+   * direction changes.  Right now the NORESTART flag overrides this behavior.
+   * May have to introduce logic to issue sendstart, assuming it's legal
+   * with the hardware in the TCR state.
+   */
+
+  else if ((status & I2C_ISR_TCR) != 0)
+    {
+      i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08x\n",
+      priv->dcnt, priv->msgc, status);
+
+      /* If no more bytes in the current message to transfer */
+
+      if (priv->dcnt == 0)
+        {
+          /* Prior message has been sent successfully */
+
+          priv->msgc--;
+
+          /* Advance to the next message in the list */
+
+          priv->msgv++;
+
+          /* Update current message data */
+
+          priv->ptr    = priv->msgv->buffer;
+          priv->dcnt   = priv->msgv->length;
+          priv->flags  = priv->msgv->flags;
+
+          /* if this is the last message, disable reload so the
+           * TC event fires next time */
+
+          if (priv->msgc == 0)
+            {
+              i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n",
+              priv->dcnt, priv->msgc);
+
+              stm32_i2c_disable_reload(priv);
+            }
+
+          /* Update NBYTES with length of current message */
+
+          i2cinfo("TCR: NEXT MSG dcnt = %i msgc = %i\n",
+                  priv->dcnt, priv->msgc);
+
+          stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
+        }
+      else
+        {
+          /* More bytes in the current (greater than 255 byte payload
+           * length) message, so set NBYTES according to the bytes
+           * remaining in the message, up to a maximum each cycle of 255.
+           */
+
+          if (priv->dcnt > 255)
+            {
+              i2cinfo("TCR: ENABLE RELOAD: NBYTES = 255 dcnt = %i msgc = %i\n",
+              priv->dcnt, priv->msgc);
+
+              /* More than 255 bytes to transfer so the RELOAD bit is
+               * set in order to generate a TCR event rather than a TC
+               * event when 255 bytes are successfully transferred.
+               * This forces us to return here to update NBYTES and
+               * continue until NBYTES is set to less than 255 bytes,
+               * at which point RELOAD will be disabled and a TC
+               * event will (eventually) follow to officially terminate
+               * the transfer.
+               */
+
+              stm32_i2c_enable_reload(priv);
+
+              stm32_i2c_set_bytes_to_transfer(priv, 255);
+            }
+          else
+            {
+              /* Less than 255 bytes left to transfer, which means we'll
+               * complete the transfer of all bytes in the current message
+               * the next time around.
+               *
+               * This means we need to disable the RELOAD functionality so
+               * we receive a TC event next time which will allow us to
+               * either RESTART and continue sending the contents of the
+               * next message or send a STOP condition and exit the ISR.
+               */
+
+              i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n",
+                      priv->dcnt, priv->msgc);
+
+              stm32_i2c_disable_reload(priv);
+
+              stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
+            }
+
+          i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08x\n",
+          priv->dcnt, priv->msgc, status);
+        }
+    }
+
+  /* Empty call handler
+   *
+   * Case to handle an empty call to the ISR where it has nothing to
+   * do and should exit immediately.
+   */
+
+  else if (priv->dcnt == -1 && priv->msgc == 0)
+    {
+      status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
+      i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08x\n", status);
+      stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0);
+    }
+
+  /* Error handler
+   *
+   * We get to this branch only if we can't handle the current state.
+   *
+   * This can happen in interrupt based operation on ARLO & BUSY.
+   *
+   * This will happen during polled operation when the device is not
+   * in one of the supported states when polled.
+   */
+
+  else
+    {
+#ifdef CONFIG_I2C_POLLED
+      stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0);
+#else
+      /* Read rest of the state */
+
+      status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
+
+      i2cerr("ERROR: Invalid state detected, status 0x%08x\n", status);
+
+      /* set condition to terminate ISR and wake waiting thread */
+
+      priv->status |= I2C_INT_BAD_STATE;
+      priv->dcnt = -1;
+      priv->msgc = 0;
+      stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0);
+#endif
+    }
+
+  /* --------------------- End of I2C protocol handling -------------------- */
+
+  /* Message Handling
+   *
+   * Transmission of the whole message chain has been completed. We have to
+   * terminate the ISR and wake up stm32_i2c_process() that is waiting for
+   * the ISR cycle to handle the sending/receiving of the messages.
+   */
+
+  if (priv->dcnt == -1 && priv->msgc == 0)
+    {
+      i2cinfo("MSG: Shutting down I2C ISR\n");
+
+      stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0);
+
+      /* clear pointer to message content to reflect we are done
+       * with the current transaction */
+
+      priv->msgv = NULL;
+
+#ifdef CONFIG_I2C_POLLED
+      priv->intstate = INTSTATE_DONE;
+#else
+
+      /* We will update private state to capture NACK which is used in
+       * combination with the astart flag to report the type of NACK received
+       * (address vs data) to the upper layers once we exit the ISR.
+       *
+       * Note: status is captured  prior to clearing interrupts because
+       * the NACKF flag will naturally be cleared by that process.
+       */
+
+      status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
+
+      /* Clear all interrupts */
+
+      stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
+
+      /* Was a bad state detected in the processing? */
+
+      if (priv->status & I2C_INT_BAD_STATE)
+        {
+          /* SW reset device  */
+
+          stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
+        }
+
+      /* Update private status from above sans I2C_INT_BAD_STATE */
+
+      priv->status = status;
+
+      /* If a thread is waiting then inform it transfer is complete */
+
+      if (priv->intstate == INTSTATE_WAITING)
+        {
+          nxsem_post(&priv->sem_isr);
+          priv->intstate = INTSTATE_DONE;
+        }
+#endif
+    }
+
+  status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
+  i2cinfo("EXIT: status = 0x%08x\n", status);
+
+  return OK;
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_isr
+ *
+ * Description:
+ *   Common I2C interrupt service routine
+ *
+ ************************************************************************************/
+
+#ifndef CONFIG_I2C_POLLED
+static int stm32_i2c_isr(int irq, void *context, FAR void *arg)
+{
+  struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg;
+
+  DEBUGASSERT(priv != NULL);
+  return stm32_i2c_isr_process(priv);
+}
+#endif
+
+/************************************************************************************
+ * Name: stm32_i2c_init
+ *
+ * Description:
+ *   Setup the I2C hardware, ready for operation with defaults
+ *
+ ************************************************************************************/
+
+static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
+{
+  /* Power-up and configure GPIOs */
+
+  /* Enable power and reset the peripheral */
+
+  modifyreg32(STM32_RCC_APB1ENR, 0, priv->config->clk_bit);
+  modifyreg32(STM32_RCC_APB1RSTR, 0, priv->config->reset_bit);
+  modifyreg32(STM32_RCC_APB1RSTR, priv->config->reset_bit, 0);
+
+  /* Configure pins */
+
+  if (stm32_configgpio(priv->config->scl_pin) < 0)
+    {
+      return ERROR;
+    }
+
+  if (stm32_configgpio(priv->config->sda_pin) < 0)
+    {
+      stm32_unconfiggpio(priv->config->scl_pin);
+      return ERROR;
+    }
+
+#ifndef CONFIG_I2C_POLLED
+  /* Attach error and event interrupts to the ISRs */
+
+  irq_attach(priv->config->irq, stm32_i2c_isr, priv);
+  up_enable_irq(priv->config->irq);
+#endif
+
+  /* TODO:
+   * - Provide means to set peripheral clock source via RCC_CFGR3_I2CxSW
+   * - Set to HSI by default, make Kconfig option
+   */
+
+  /* Force a frequency update */
+
+  priv->frequency = 0;
+  stm32_i2c_setclock(priv, 100000);
+
+  return OK;
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_deinit
+ *
+ * Description:
+ *   Shutdown the I2C hardware
+ *
+ ************************************************************************************/
+
+static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv)
+{
+  /* Disable I2C */
+
+  stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0);
+
+  /* Unconfigure GPIO pins */
+
+  stm32_unconfiggpio(priv->config->scl_pin);
+  stm32_unconfiggpio(priv->config->sda_pin);
+
+#ifndef CONFIG_I2C_POLLED
+
+  /* Disable and detach interrupts */
+
+  up_disable_irq(priv->config->irq);
+  irq_detach(priv->config->irq);
+#endif
+
+  /* Disable clocking */
+
+  modifyreg32(STM32_RCC_APB1ENR, priv->config->clk_bit, 0);
+
+  return OK;
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_process
+ *
+ * Description:
+ *   Common I2C transfer logic
+ *
+ *   Initiates a master mode transaction on the I2C bus to transfer the provided
+ *   messages to and from the slave devices.
+ *
+ ************************************************************************************/
+
+static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs, int count)
+{
+  struct stm32_i2c_inst_s     *inst = (struct stm32_i2c_inst_s *)dev;
+  FAR struct stm32_i2c_priv_s *priv = inst->priv;
+  uint32_t    status = 0;
+  uint32_t    cr1;
+  uint32_t    cr2;
+  int         errval = 0;
+  int         waitrc = 0;
+
+  DEBUGASSERT(count > 0);
+
+  /* Wait for any STOP in progress */
+
+  stm32_i2c_sem_waitstop(priv);
+
+  /* Clear any pending error interrupts */
+
+  stm32_i2c_clearinterrupts(priv);
+
+  /* Old transfers are done */
+
+  priv->msgv = msgs;
+  priv->msgc = count;
+
+  /* Reset I2C trace logic */
+
+  stm32_i2c_tracereset(priv);
+
+  /* Set I2C clock frequency toggles I2C_CR1_PE performing a SW reset! */
+
+  stm32_i2c_setclock(priv, msgs->frequency);
+
+  /* Trigger start condition, then the process moves into the ISR.  I2C
+   * interrupts will be enabled within stm32_i2c_waitdone().
+   */
+
+  priv->status = 0;
+
+#ifndef CONFIG_I2C_POLLED
+  /* Enable transmit and receive interrupts here so when we send the start
+   * condition below the ISR will fire if the data was sent and some
+   * response from the slave received.  All other interrupts relevant to
+   * our needs are enabled in stm32_i2c_sem_waitdone() below.
+   */
+
+  stm32_i2c_enableinterrupts(priv);
+#endif
+
+  /* Trigger START condition generation, which also sends the slave address
+   * with read/write flag and the data in the first message
+   */
+
+  stm32_i2c_sendstart(priv);
+
+  /* Wait for the ISR to tell us that the transfer is complete by attempting
+   * to grab the semaphore that is initially locked by the ISR.  If the ISR
+   * does not release the lock so we can obtain it here prior to the end of
+   * the timeout period waitdone returns error and we report a timeout.
+   */
+
+  waitrc = stm32_i2c_sem_waitdone(priv);
+
+  cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET);
+  cr2 = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET);
+#if !defined(CONFIG_DEBUG_I2C)
+  UNUSED(cr1);
+  UNUSED(cr2);
+#endif
+
+  /* Status after a normal / good exit is usually 0x00000001, meaning the TXE
+   * bit is set.  That occurs as a result of the I2C_TXDR register being
+   * empty, and it naturally will be after the last byte is transmitted.
+   * This bit is cleared when we attempt communications again and re-enable
+   * the peripheral.  The priv->status field can hold additional information
+   * like a NACK, so we reset the status field to include that information.
+   */
+
+  status = stm32_i2c_getstatus(priv);
+
+  /* The priv->status field can hold additional information like a NACK
+   * event so we include that information.
+   */
+
+  status = priv->status & 0xffffffff;
+
+  if (waitrc < 0)
+    {
+      /* Connection timed out */
+
+      errval = ETIMEDOUT;
+      i2cerr("ERROR: Waitdone timed out CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n",
+             cr1, cr2,status);
+    }
+  else
+    {
+      i2cinfo("Waitdone success: CR1: 0x%08x CR2: 0x%08x status: 0x%08x\n",
+             cr1, cr2,status );
+    }
+
+  UNUSED(cr1);
+  UNUSED(cr2);
+
+  i2cinfo("priv->status: 0x%08x\n", priv->status);
+
+  /* Check for error status conditions */
+
+  if ((status & (I2C_INT_BERR |
+                 I2C_INT_ARLO |
+                 I2C_INT_OVR |
+                 I2C_INT_PECERR |
+                 I2C_INT_TIMEOUT |
+                 I2C_INT_NACK)) != 0)
+
+    {
+      /* one or more errors in the mask are present */
+
+      if (status & I2C_INT_BERR)
+        {
+          /* Bus Error, ignore it because of errata (revision A,Z) */
+
+          i2cerr("ERROR: I2C Bus Error\n");
+
+          /* errval = EIO; */
+        }
+      else if (status & I2C_INT_ARLO)
+        {
+          /* Arbitration Lost (master mode) */
+
+          i2cerr("ERROR: I2C Arbitration Lost\n");
+          errval = EAGAIN;
+        }
+
+      else if (status & I2C_INT_OVR)
+        {
+          /* Overrun/Underrun */
+
+          i2cerr("ERROR: I2C Overrun/Underrun\n");
+          errval = EIO;
+        }
+      else if (status & I2C_INT_PECERR)
+        {
+      /* PEC Error in reception (SMBus Only) */
+
+          i2cerr("ERROR: I2C PEC Error\n");
+          errval = EPROTO;
+        }
+      else if (status & I2C_INT_TIMEOUT)
+        {
+          /* Timeout or Tlow Error (SMBus Only) */
+
+          i2cerr("ERROR: I2C Timeout / Tlow Error\n");
+          errval = ETIME;
+        }
+      else if (status & I2C_INT_NACK)
+        {
+          /* NACK Received, flag as "communication error on send" */
+
+          if (priv->astart == TRUE)
+            {
+              i2cwarn("WARNING: I2C Address NACK\n");
+              errval = EADDRNOTAVAIL;
+            }
+          else
+            {
+              i2cwarn("WARNING: I2C Data NACK\n");
+              errval = ECOMM;
+            }
+        }
+      else
+        {
+          /* Unrecognized error */
+
+          i2cerr("ERROR: I2C Unrecognized Error");
+          errval = EINTR;
+        }
+    }
+
+  /* This is not an error, but should not happen.  The BUSY signal can be
+   * present if devices on the bus are in an odd state and need to be reset.
+   * NOTE:  We will only see this busy indication if stm32_i2c_sem_waitdone()
+   * fails above;  Otherwise it is cleared.
+   */
+
+  else if ((status & I2C_ISR_BUSY) != 0)
+    {
+      /* I2C Bus Busy
+       *
+       * This is a status condition rather than an error.
+       *
+       * We will only see this busy indication if stm32_i2c_sem_waitdone()
+       * fails above;  Otherwise it is cleared by the hardware when the ISR
+       * wraps up the transfer with a STOP condition.
+       */
+
+      clock_t start = clock_systimer();
+      clock_t timeout = USEC2TICK(USEC_PER_SEC/priv->frequency) + 1;
+
+      status = stm32_i2c_getstatus(priv);
+
+      while (status & I2C_ISR_BUSY)
+        {
+          if ((clock_systimer() - start) > timeout)
+            {
+              i2cerr("ERROR: I2C Bus busy");
+              errval = EBUSY;
+              break;
+            }
+
+          status = stm32_i2c_getstatus(priv);
+        }
+    }
+
+  /* Dump the trace result */
+
+  stm32_i2c_tracedump(priv);
+  stm32_i2c_sem_post(dev);
+
+  return -errval;
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_transfer
+ *
+ * Description:
+ *   Generic I2C transfer function
+ *
+ ************************************************************************************/
+
+static int stm32_i2c_transfer(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s *msgs,
+                              int count)
+{
+  stm32_i2c_sem_wait(dev);   /* ensure that address or flags don't change meanwhile */
+  return stm32_i2c_process(dev, msgs, count);
+}
+
+/************************************************************************************
+ * Name: stm32_i2c_reset
+ *
+ * Description:
+ *   Reset an I2C bus
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_I2C_RESET
+static int stm32_i2c_reset(FAR struct i2c_master_s * dev)
+{
+  struct stm32_i2c_priv_s * priv;
+  unsigned int clock_count;
+  unsigned int stretch_count;
+  uint32_t scl_gpio;
+  uint32_t sda_gpio;
+  uint32_t frequency;
+  int ret = ERROR;
+
+  DEBUGASSERT(dev);
+
+  /* Get I2C private structure */
+
+  priv = ((struct stm32_i2c_inst_s *)dev)->priv;
+
+  /* Our caller must own a ref */
+
+  DEBUGASSERT(priv->refs > 0);
+
+  /* Lock out other clients */
+
+  stm32_i2c_sem_wait(dev);
+
+  /* Save the current frequency */
+
+  frequency = priv->frequency;
+
+  /* De-init the port */
+
+  stm32_i2c_deinit(priv);
+
+  /* Use GPIO configuration to un-wedge the bus */
+
+  scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin);
+  sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin);
+
+  stm32_configgpio(sda_gpio);
+  stm32_configgpio(scl_gpio);
+
+  /* Let SDA go high */
+
+  stm32_gpiowrite(sda_gpio, 1);
+
+  /* Clock the bus until any slaves currently driving it let it go. */
+
+  clock_count = 0;
+  while (!stm32_gpioread(sda_gpio))
+    {
+      /* Give up if we have tried too hard */
+
+      if (clock_count++ > 10)
+        {
+          goto out;
+        }
+
+      /* Sniff to make sure that clock stretching has finished.
+       *
+       * If the bus never relaxes, the reset has failed.
+       */
+
+      stretch_count = 0;
+      while (!stm32_gpioread(scl_gpio))
+        {
+          /* Give up if we have tried too hard */
+
+          if (stretch_count++ > 10)
+            {
+              goto out;
+            }
+
+          up_udelay(10);
+        }
+
+      /* Drive SCL low */
+
+      stm32_gpiowrite(scl_gpio, 0);
+      up_udelay(10);
+
+      /* Drive SCL high again */
+
+      stm32_gpiowrite(scl_gpio, 1);
+      up_udelay(10);
+    }
+
+  /* Generate a start followed by a stop to reset slave
+   * state machines.
+   */
+
+  stm32_gpiowrite(sda_gpio, 0);
+  up_udelay(10);
+  stm32_gpiowrite(scl_gpio, 0);
+  up_udelay(10);
+  stm32_gpiowrite(scl_gpio, 1);
+  up_udelay(10);
+  stm32_gpiowrite(sda_gpio, 1);
+  up_udelay(10);
+
+  /* Revert the GPIO configuration. */
+
+  stm32_unconfiggpio(sda_gpio);
+  stm32_unconfiggpio(scl_gpio);
+
+  /* Re-init the port */
+
+  stm32_i2c_init(priv);
+
+  /* Restore the frequency */
+
+  stm32_i2c_setclock(priv, frequency);
+  ret = OK;
+
+out:
+
+  /* Release the port for re-use by other clients */
+
+  stm32_i2c_sem_post(dev);
+  return ret;
+}
+#endif /* CONFIG_I2C_RESET */
+
+/************************************************************************************
+ * Name: stm32_i2c_pm_prepare
+ *
+ * Description:
+ *   Request the driver to prepare for a new power state. This is a
+ *   warning that the system is about to enter into a new power state.  The
+ *   driver should begin whatever operations that may be required to enter
+ *   power state.  The driver may abort the state change mode by returning
+ *   a non-zero value from the callback function.
+ *
+ * Input Parameters:
+ *   cb      - Returned to the driver.  The driver version of the callback
+ *             structure may include additional, driver-specific state
+ *             data at the end of the structure.
+ *   domain  - Identifies the activity domain of the state change
+ *   pmstate - Identifies the new PM state
+ *
+ * Returned Value:
+ *   0 (OK) means the event was successfully processed and that the driver
+ *   is prepared for the PM state change.  Non-zero means that the driver
+ *   is not prepared to perform the tasks needed achieve this power setting
+ *   and will cause the state change to be aborted.  NOTE:  The prepare
+ *   method will also be recalled when reverting from lower back to higher
+ *   power consumption modes (say because another driver refused a lower
+ *   power state change).  Drivers are not permitted to return non-zero
+ *   values when reverting back to higher power consumption modes!
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_PM
+static int stm32_i2c_pm_prepare(FAR struct pm_callback_s *cb, int domain,
+                                enum pm_state_e pmstate)
+{
+  struct stm32_i2c_priv_s *priv =
+      (struct stm32_i2c_priv_s *)((char *)cb -
+                                    offsetof(struct stm32_i2c_priv_s, pm_cb));
+  int sval;
+
+  /* Logic to prepare for a reduced power state goes here. */
+
+  switch (pmstate)
+    {
+    case PM_NORMAL:
+    case PM_IDLE:
+      break;
+
+    case PM_STANDBY:
+    case PM_SLEEP:
+      /* Check if exclusive lock for I2C bus is held. */
+
+      if (nxsem_getvalue(&priv->sem_excl, &sval) < 0)
+        {
+          DEBUGASSERT(false);
+          return -EINVAL;
+        }
+
+      if (sval <= 0)
+        {
+          /* Exclusive lock is held, do not allow entry to deeper PM states. */
+
+          return -EBUSY;
+        }
+
+      break;
+
+    default:
+      /* Should not get here */
+
+      break;
+    }
+
+  return OK;
+}
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_i2cbus_initialize
+ *
+ * Description:
+ *   Initialize one I2C bus
+ *
+ ************************************************************************************/
+
+FAR struct i2c_master_s *stm32_i2cbus_initialize(int port)
+{
+  struct stm32_i2c_priv_s * priv = NULL;  /* private data of device with multiple instances */
+  struct stm32_i2c_inst_s * inst = NULL;  /* device, single instance */
+  irqstate_t irqs;
+#ifdef CONFIG_PM
+  int ret;
+#endif
+
+#if 0                           /* REVISIT: this is not true for all STM32 M0 */
+#if STM32_HSI_FREQUENCY != 8000000 || defined(INVALID_CLOCK_SOURCE)
+#   warning STM32_I2C_INIT: Peripheral clock is HSI and it must be 16mHz or the speed/timing calculations need to be redone.
+    return NULL;
+#endif
+#endif
+
+  /* Get I2C private structure */
+
+  switch (port)
+    {
+#ifdef CONFIG_STM32F0L0G0_I2C1
+      case 1:
+        priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv;
+        break;
+#endif
+#ifdef CONFIG_STM32F0L0G0_I2C2
+      case 2:
+        priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv;
+        break;
+#endif
+#ifdef CONFIG_STM32F0L0G0_I2C3
+      case 3:
+        priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv;
+        break;
+#endif
+#ifdef CONFIG_STM32F0L0G0_I2C4
+      case 4:
+        priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv;
+        break;
+#endif
+      default:
+        return NULL;
+    }
+
+  /* Allocate instance */
+
+  if (!(inst = kmm_malloc(sizeof(struct stm32_i2c_inst_s))))
+    {
+      return NULL;
+    }
+
+  /* Initialize instance */
+
+  inst->ops       = &stm32_i2c_ops;
+  inst->priv      = priv;
+
+  /* Init private data for the first time, increment refs count,
+   * power-up hardware and configure GPIOs.
+   */
+
+  irqs = enter_critical_section();
+
+  if ((volatile int)priv->refs++ == 0)
+    {
+      stm32_i2c_sem_init((struct i2c_master_s *)inst);
+      stm32_i2c_init(priv);
+
+#ifdef CONFIG_PM
+      /* Register to receive power management callbacks */
+
+      ret = pm_register(&priv->pm_cb);
+      DEBUGASSERT(ret == OK);
+      UNUSED(ret);
+#endif
+    }
+
+  leave_critical_section(irqs);
+  return (struct i2c_master_s *)inst;
+}
+
+/************************************************************************************
+ * Name: stm32_i2cbus_uninitialize
+ *
+ * Description:
+ *   Uninitialize an I2C bus
+ *
+ ************************************************************************************/
+
+int stm32_i2cbus_uninitialize(FAR struct i2c_master_s * dev)
+{
+  irqstate_t irqs;
+
+  DEBUGASSERT(dev);
+
+  /* Decrement refs and check for underflow */
+
+  if (((struct stm32_i2c_inst_s *)dev)->priv->refs == 0)
+    {
+      return ERROR;
+    }
+
+  irqs = enter_critical_section();
+
+  if (--((struct stm32_i2c_inst_s *)dev)->priv->refs)
+    {
+      leave_critical_section(irqs);
+      kmm_free(dev);
+      return OK;
+    }
+
+  leave_critical_section(irqs);
+
+#ifdef CONFIG_PM
+  /* Unregister power management callbacks */
+
+  pm_unregister(&((struct stm32_i2c_inst_s *)dev)->priv->pm_cb);
+#endif
+
+  /* Disable power and other HW resource (GPIO's) */
+
+  stm32_i2c_deinit(((struct stm32_i2c_inst_s *)dev)->priv);
+
+  /* Release unused resources */
+
+  stm32_i2c_sem_destroy((struct i2c_master_s *)dev);
+
+  kmm_free(dev);
+  return OK;
+}
+
+#endif /* CONFIG_STM32F0L0G0_I2C1 || CONFIG_STM32F0L0G0_I2C2 || \
+          CONFIG_STM32F0L0G0_I2C3 || CONFIG_STM32F0L0G0_I2C4 */
diff --git a/arch/arm/src/stm32f0l0/stm32_i2c.h b/arch/arm/src/stm32f0l0g0/stm32_i2c.h
similarity index 89%
rename from arch/arm/src/stm32f0l0/stm32_i2c.h
rename to arch/arm/src/stm32f0l0g0/stm32_i2c.h
index 9a9d881dce8..1d791335450 100644
--- a/arch/arm/src/stm32f0l0/stm32_i2c.h
+++ b/arch/arm/src/stm32f0l0g0/stm32_i2c.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f0l0/stm32_i2c.h
+ * arch/arm/src/stm32f0l0g0/stm32_i2c.h
  *
  *   Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_I2C_H
-#define __ARCH_ARM_SRC_STM32F0L0_STM32_I2C_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H
 
 /****************************************************************************
  * Included Files
@@ -54,10 +54,10 @@
  * seconds per byte value must be provided as well.
  */
 
-#ifdef CONFIG_STM32F0L0_I2C_DYNTIMEO
-#  if CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE < 1
-#    warning "Ignoring CONFIG_STM32F0L0_I2C_DYNTIMEO because of CONFIG_STM32F0L0_I2C_DYNTIMEO_USECPERBYTE"
-#    undef CONFIG_STM32F0L0_I2C_DYNTIMEO
+#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
+#  if CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE < 1
+#    warning "Ignoring CONFIG_STM32F0L0G0_I2C_DYNTIMEO because of CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE"
+#    undef CONFIG_STM32F0L0G0_I2C_DYNTIMEO
 #  endif
 #endif
 
@@ -101,4 +101,4 @@ FAR struct i2c_master_s *stm32_i2cbus_initialize(int port);
 
 int stm32_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_I2C_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H */
diff --git a/arch/arm/src/stm32f0l0/stm32_idle.c b/arch/arm/src/stm32f0l0g0/stm32_idle.c
similarity index 98%
rename from arch/arm/src/stm32f0l0/stm32_idle.c
rename to arch/arm/src/stm32f0l0g0/stm32_idle.c
index 982bd0579ce..c56ad593ad5 100644
--- a/arch/arm/src/stm32f0l0/stm32_idle.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_idle.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- *  arch/arm/src/stm32f0l0/stm32_idle.c
+ *  arch/arm/src/stm32f0l0g0/stm32_idle.c
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -97,7 +97,7 @@ void up_idle(void)
  * disabled in order to save power."
  */
 
-#ifdef CONFIG_STM32F0L0_GPDMA
+#ifdef CONFIG_STM32F0L0G0_GPDMA
   if (g_dma_inprogress == 0)
 #endif
     {
diff --git a/arch/arm/src/stm32f0l0/stm32_irq.c b/arch/arm/src/stm32f0l0g0/stm32_irq.c
similarity index 99%
rename from arch/arm/src/stm32f0l0/stm32_irq.c
rename to arch/arm/src/stm32f0l0g0/stm32_irq.c
index 3161352812e..d2d70eb7fd6 100644
--- a/arch/arm/src/stm32f0l0/stm32_irq.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_irq.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f0l0/stm32_irq.c
+ * arch/arm/src/stm32f0l0g0/stm32_irq.c
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -245,7 +245,7 @@ void up_irqinitialize(void)
    * configured pin interrupts.
    */
 
-#ifdef CONFIG_STM32F0L0_GPIOIRQ
+#ifdef CONFIG_STM32F0L0G0_GPIOIRQ
   stm32_gpioirqinitialize();
 #endif
 
diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc.c b/arch/arm/src/stm32f0l0g0/stm32_lowputc.c
new file mode 100644
index 00000000000..71ab893d4fe
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/stm32_lowputc.c
@@ -0,0 +1,53 @@
+/****************************************************************************
+ * arch/arm/src/stm32f0l0g0/stm32_lowputc.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include "chip.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1)
+#  include "stm32_lowputc_v1.c"
+#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2)
+#  include "stm32_lowputc_v2.c"
+#else
+#  error "Unsupported STM32 M0 serial"
+#endif
diff --git a/arch/arm/src/stm32f0l0/stm32_lowputc.h b/arch/arm/src/stm32f0l0g0/stm32_lowputc.h
similarity index 93%
rename from arch/arm/src/stm32f0l0/stm32_lowputc.h
rename to arch/arm/src/stm32f0l0g0/stm32_lowputc.h
index ee6a1723eca..25ba89c7b4d 100644
--- a/arch/arm/src/stm32f0l0/stm32_lowputc.h
+++ b/arch/arm/src/stm32f0l0g0/stm32_lowputc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/stm32_lowputc.h
+ * arch/arm/src/stm32f0l0g0/stm32_lowputc.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_LOWPUTC_H
-#define __ARCH_ARM_SRC_STM32F0L0_STM32_LOWPUTC_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H
 
 /************************************************************************************
  * Included Files
@@ -77,4 +77,4 @@ void stm32_lowsetup(void);
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_LOWPUTC_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H */
diff --git a/arch/arm/src/stm32f0l0/stm32_lowputc.c b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c
similarity index 98%
rename from arch/arm/src/stm32f0l0/stm32_lowputc.c
rename to arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c
index a3e1c920898..8dd8daa25a8 100644
--- a/arch/arm/src/stm32f0l0/stm32_lowputc.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f0l0/stm32_lowputc.c
+ * arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c
  *
  *   Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -62,7 +62,7 @@
 #ifdef HAVE_CONSOLE
 #  if defined(CONFIG_USART1_SERIAL_CONSOLE)
 #    define STM32_CONSOLE_BASE     STM32_USART1_BASE
-#    define STM32_APBCLOCK         STM32_PCLK2_FREQUENCY
+#    define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY
 #    define STM32_CONSOLE_BAUD     CONFIG_USART1_BAUD
 #    define STM32_CONSOLE_BITS     CONFIG_USART1_BITS
 #    define STM32_CONSOLE_PARITY   CONFIG_USART1_PARITY
@@ -280,7 +280,7 @@ void stm32_lowsetup(void)
 
   /* Setup clocking and GPIO pins for all configured USARTs */
 
-#ifdef CONFIG_STM32F0L0_USART1
+#ifdef CONFIG_STM32F0L0G0_USART1
   /* Enable USART APB2 clock */
 
   modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN);
@@ -296,7 +296,7 @@ void stm32_lowsetup(void)
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART2
+#ifdef CONFIG_STM32F0L0G0_USART2
   /* Enable USART APB1 clock */
 
   modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART2EN);
@@ -312,7 +312,7 @@ void stm32_lowsetup(void)
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART3
+#ifdef CONFIG_STM32F0L0G0_USART3
   /* Enable USART APB1 clock */
 
   modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART3EN);
@@ -328,7 +328,7 @@ void stm32_lowsetup(void)
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART4
+#ifdef CONFIG_STM32F0L0G0_USART4
   /* Enable USART APB1 clock */
 
   modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART4EN);
@@ -344,7 +344,7 @@ void stm32_lowsetup(void)
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART5
+#ifdef CONFIG_STM32F0L0G0_USART5
   /* Enable USART APB1 clock */
 
   modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART5EN);
diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c
new file mode 100644
index 00000000000..0841e50abd4
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c
@@ -0,0 +1,364 @@
+/****************************************************************************
+ * arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+
+#include "hardware/stm32_pinmap.h"
+#include "stm32_rcc.h"
+#include "stm32_gpio.h"
+#include "stm32_uart.h"
+
+#include 
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Select USART parameters for the selected console */
+
+#ifdef HAVE_CONSOLE
+#  if defined(CONFIG_USART1_SERIAL_CONSOLE)
+#    define STM32_CONSOLE_BASE     STM32_USART1_BASE
+#    define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY
+#    define STM32_CONSOLE_APBREG   STM32_RCC_APB2ENR
+#    define STM32_CONSOLE_APBEN    RCC_APB2ENR_USART1EN
+#    define STM32_CONSOLE_BAUD     CONFIG_USART1_BAUD
+#    define STM32_CONSOLE_BITS     CONFIG_USART1_BITS
+#    define STM32_CONSOLE_PARITY   CONFIG_USART1_PARITY
+#    define STM32_CONSOLE_2STOP    CONFIG_USART1_2STOP
+#    define STM32_CONSOLE_TX       GPIO_USART1_TX
+#    define STM32_CONSOLE_RX       GPIO_USART1_RX
+#    ifdef CONFIG_USART1_RS485
+#      define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
+#      if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
+#        define STM32_CONSOLE_RS485_DIR_POLARITY false
+#      else
+#        define STM32_CONSOLE_RS485_DIR_POLARITY true
+#      endif
+#    endif
+#  elif defined(CONFIG_USART2_SERIAL_CONSOLE)
+#    define STM32_CONSOLE_BASE     STM32_USART2_BASE
+#    define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY
+#    define STM32_CONSOLE_APBREG   STM32_RCC_APB1ENR
+#    define STM32_CONSOLE_APBEN    RCC_APB1ENR_USART2EN
+#    define STM32_CONSOLE_BAUD     CONFIG_USART2_BAUD
+#    define STM32_CONSOLE_BITS     CONFIG_USART2_BITS
+#    define STM32_CONSOLE_PARITY   CONFIG_USART2_PARITY
+#    define STM32_CONSOLE_2STOP    CONFIG_USART2_2STOP
+#    define STM32_CONSOLE_TX       GPIO_USART2_TX
+#    define STM32_CONSOLE_RX       GPIO_USART2_RX
+#    ifdef CONFIG_USART2_RS485
+#      define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
+#      if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
+#        define STM32_CONSOLE_RS485_DIR_POLARITY false
+#      else
+#        define STM32_CONSOLE_RS485_DIR_POLARITY true
+#      endif
+#    endif
+#  elif defined(CONFIG_USART3_SERIAL_CONSOLE)
+#    define STM32_CONSOLE_BASE     STM32_USART3_BASE
+#    define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY
+#    define STM32_CONSOLE_APBREG   STM32_RCC_APB1ENR
+#    define STM32_CONSOLE_APBEN    RCC_APB1ENR_USART3EN
+#    define STM32_CONSOLE_BAUD     CONFIG_USART3_BAUD
+#    define STM32_CONSOLE_BITS     CONFIG_USART3_BITS
+#    define STM32_CONSOLE_PARITY   CONFIG_USART3_PARITY
+#    define STM32_CONSOLE_2STOP    CONFIG_USART3_2STOP
+#    define STM32_CONSOLE_TX       GPIO_USART3_TX
+#    define STM32_CONSOLE_RX       GPIO_USART3_RX
+#    ifdef CONFIG_USART3_RS485
+#      define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
+#      if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
+#        define STM32_CONSOLE_RS485_DIR_POLARITY false
+#      else
+#        define STM32_CONSOLE_RS485_DIR_POLARITY true
+#      endif
+#    endif
+#  elif defined(CONFIG_USART4_SERIAL_CONSOLE)
+#    define STM32_CONSOLE_BASE     STM32_USART4_BASE
+#    define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY
+#    define STM32_CONSOLE_APBREG   STM32_RCC_APB1ENR
+#    define STM32_CONSOLE_APBEN    RCC_APB1ENR_USART4EN
+#    define STM32_CONSOLE_BAUD     CONFIG_USART4_BAUD
+#    define STM32_CONSOLE_BITS     CONFIG_USART4_BITS
+#    define STM32_CONSOLE_PARITY   CONFIG_USART4_PARITY
+#    define STM32_CONSOLE_2STOP    CONFIG_USART4_2STOP
+#    define STM32_CONSOLE_TX       GPIO_USART4_TX
+#    define STM32_CONSOLE_RX       GPIO_USART4_RX
+#    ifdef CONFIG_USART4_RS485
+#      define STM32_CONSOLE_RS485_DIR GPIO_USART4_RS485_DIR
+#      if (CONFIG_USART4_RS485_DIR_POLARITY == 0)
+#        define STM32_CONSOLE_RS485_DIR_POLARITY false
+#      else
+#        define STM32_CONSOLE_RS485_DIR_POLARITY true
+#      endif
+#    endif
+#  endif
+
+  /* CR1 settings */
+
+#  if STM32_CONSOLE_BITS == 7
+#    define USART_CR_M01_VALUE USART_CR1_M1
+#  elif STM32_CONSOLE_BITS == 9
+#    define USART_CR_M01_VALUE USART_CR1_M0
+#  else /*  STM32_CONSOLE_BITS == 8 */
+#    define USART_CR_M01_VALUE 0
+#  endif
+
+#  if STM32_CONSOLE_PARITY == 1
+#    define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
+#  elif STM32_CONSOLE_PARITY == 2
+#    define USART_CR1_PARITY_VALUE USART_CR1_PCE
+#  else
+#    define USART_CR1_PARITY_VALUE 0
+#  endif
+
+#  define USART_CR1_CLRBITS \
+    (USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | USART_CR1_PCE | \
+     USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_MME | USART_CR1_OVER8 | \
+     USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK | USART_CR1_ALLINTS)
+
+#  define USART_CR1_SETBITS (USART_CR_M01_VALUE | USART_CR1_PARITY_VALUE)
+
+  /* CR2 settings */
+
+#  if STM32_CONSOLE_2STOP != 0
+#    define USART_CR2_STOP2_VALUE USART_CR2_STOP2
+#  else
+#    define USART_CR2_STOP2_VALUE 0
+#  endif
+
+#  define USART_CR2_CLRBITS \
+    (USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
+     USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \
+     USART_CR2_LINEN | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV | \
+     USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMOD_MASK | \
+     USART_CR2_RTOEN | USART_CR2_ADD8_MASK)
+
+#  define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
+
+  /* CR3 settings */
+
+#  define USART_CR3_CLRBITS \
+    (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \
+     USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \
+     USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \
+     USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \
+     USART_CR3_SCARCNT_MASK)
+
+#  define USART_CR3_SETBITS 0
+
+  /* Only the STM32 F3 supports oversampling by 8 */
+
+#  undef USE_OVER8
+
+  /* Calculate USART BAUD rate divider */
+  /* Baud rate for standard USART (SPI mode included):
+   *
+   * In case of oversampling by 16, the equation is:
+   *   baud    = fCK / UARTDIV
+   *   UARTDIV = fCK / baud
+   *
+   * In case of oversampling by 8, the equation is:
+   *
+   *   baud    = 2 * fCK / UARTDIV
+   *   UARTDIV = 2 * fCK / baud
+   */
+
+#  define STM32_USARTDIV8 \
+    (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
+#  define STM32_USARTDIV16 \
+    ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
+
+   /* Use oversampling by 8 only if the divisor is small.  But what is small? */
+
+#  if STM32_USARTDIV8 > 100
+#    define STM32_BRR_VALUE STM32_USARTDIV16
+#  else
+#    define USE_OVER8 1
+#    define STM32_BRR_VALUE \
+      ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1))
+#  endif
+#endif /* HAVE_CONSOLE */
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_lowputc
+ *
+ * Description:
+ *   Output one byte on the serial console
+ *
+ ****************************************************************************/
+
+void up_lowputc(char ch)
+{
+#ifdef HAVE_CONSOLE
+  /* Wait until the TX data register is empty */
+
+  while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0);
+#ifdef STM32_CONSOLE_RS485_DIR
+  stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY);
+#endif
+
+  /* Then send the character */
+
+  putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
+
+#ifdef STM32_CONSOLE_RS485_DIR
+  while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0);
+  stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
+#endif
+
+#endif /* HAVE_CONSOLE */
+}
+
+/****************************************************************************
+ * Name: stm32_lowsetup
+ *
+ * Description:
+ *   This performs basic initialization of the USART used for the serial
+ *   console.  Its purpose is to get the console output availabe as soon
+ *   as possible.
+ *
+ ****************************************************************************/
+
+void stm32_lowsetup(void)
+{
+#if defined(HAVE_USART)
+#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
+  uint32_t cr;
+#endif
+
+#if defined(HAVE_CONSOLE)
+  /* Enable USART APB1/2 clock */
+
+  modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN);
+#endif
+
+  /* Enable the console USART and configure GPIO pins needed for rx/tx.
+   *
+   * NOTE: Clocking for selected U[S]ARTs was already provided in stm32_rcc.c
+   */
+
+#ifdef STM32_CONSOLE_TX
+  stm32_configgpio(STM32_CONSOLE_TX);
+#endif
+#ifdef STM32_CONSOLE_RX
+  stm32_configgpio(STM32_CONSOLE_RX);
+#endif
+
+#ifdef STM32_CONSOLE_RS485_DIR
+  stm32_configgpio(STM32_CONSOLE_RS485_DIR);
+  stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
+#endif
+
+  /* Enable and configure the selected console device */
+
+#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
+  /* Configure CR2 */
+
+  cr  = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
+  cr &= ~USART_CR2_CLRBITS;
+  cr |= USART_CR2_SETBITS;
+  putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
+
+  /* Configure CR1 */
+
+  cr  = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
+  cr &= ~USART_CR1_CLRBITS;
+  cr |= USART_CR1_SETBITS;
+  putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
+
+  /* Configure CR3 */
+
+  cr  = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
+  cr &= ~USART_CR3_CLRBITS;
+  cr |= USART_CR3_SETBITS;
+  putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
+
+  /* Configure the USART Baud Rate */
+
+  putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
+
+  /* Select oversampling by 8 */
+
+  cr  = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
+#ifdef USE_OVER8
+  cr |= USART_CR1_OVER8;
+  putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
+#endif
+
+  /* Enable Rx, Tx and the USART */
+
+  cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
+  putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
+
+#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
+#endif /* HAVE_USART */
+}
diff --git a/arch/arm/src/stm32f0l0/stm32_lse.c b/arch/arm/src/stm32f0l0g0/stm32_lse.c
similarity index 100%
rename from arch/arm/src/stm32f0l0/stm32_lse.c
rename to arch/arm/src/stm32f0l0g0/stm32_lse.c
diff --git a/arch/arm/src/stm32f0l0/stm32_pwr.c b/arch/arm/src/stm32f0l0g0/stm32_pwr.c
similarity index 98%
rename from arch/arm/src/stm32f0l0/stm32_pwr.c
rename to arch/arm/src/stm32f0l0g0/stm32_pwr.c
index fd7c8dfd843..18907f98e54 100644
--- a/arch/arm/src/stm32f0l0/stm32_pwr.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_pwr.c
@@ -49,7 +49,7 @@
 #include "up_arch.h"
 #include "stm32_pwr.h"
 
-#if defined(CONFIG_STM32F0L0_PWR)
+#if defined(CONFIG_STM32F0L0G0_PWR)
 
 /************************************************************************************
  * Private Data
@@ -310,7 +310,7 @@ bool stm32_pwr_getwuf(void)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_ENERGYLITE
+#ifdef CONFIG_STM32F0L0G0_ENERGYLITE
 void stm32_pwr_setvos(uint16_t vos)
 {
   uint16_t regval;
@@ -401,6 +401,6 @@ void stm32_pwr_disablepvd(void)
   stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, PWR_CR_PVDE, 0);
 }
 
-#endif /* CONFIG_STM32F0L0_ENERGYLITE */
+#endif /* CONFIG_STM32F0L0G0_ENERGYLITE */
 
-#endif /* CONFIG_STM32F0L0_PWR */
+#endif /* CONFIG_STM32F0L0G0_PWR */
diff --git a/arch/arm/src/stm32f0l0/stm32_pwr.h b/arch/arm/src/stm32f0l0g0/stm32_pwr.h
similarity index 96%
rename from arch/arm/src/stm32f0l0/stm32_pwr.h
rename to arch/arm/src/stm32f0l0g0/stm32_pwr.h
index b137bc7a915..563ba4b37a0 100644
--- a/arch/arm/src/stm32f0l0/stm32_pwr.h
+++ b/arch/arm/src/stm32f0l0g0/stm32_pwr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/stm32_pwr.h
+ * arch/arm/src/stm32f0l0g0/stm32_pwr.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_PWR_H
-#define __ARCH_ARM_SRC_STM32F0L0_STM32_PWR_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H
 
 /************************************************************************************
  * Included Files
@@ -181,7 +181,7 @@ bool stm32_pwr_getwuf(void);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_ENERGYLITE
+#ifdef CONFIG_STM32F0L0G0_ENERGYLITE
 void stm32_pwr_setvos(uint16_t vos);
 
 /************************************************************************************
@@ -223,7 +223,7 @@ void stm32_pwr_enablepvd(void);
 
 void stm32_pwr_disablepvd(void);
 
-#endif /* CONFIG_STM32F0L0_ENERGYLITE */
+#endif /* CONFIG_STM32F0L0G0_ENERGYLITE */
 
 #undef EXTERN
 #if defined(__cplusplus)
@@ -231,4 +231,4 @@ void stm32_pwr_disablepvd(void);
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_PWR_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H */
diff --git a/arch/arm/src/stm32f0l0/stm32_rcc.c b/arch/arm/src/stm32f0l0g0/stm32_rcc.c
similarity index 93%
rename from arch/arm/src/stm32f0l0/stm32_rcc.c
rename to arch/arm/src/stm32f0l0g0/stm32_rcc.c
index 65a1e5c7241..353ab5fb9ff 100644
--- a/arch/arm/src/stm32f0l0/stm32_rcc.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_rcc.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f0l0/stm32_rcc.c
+ * arch/arm/src/stm32f0l0g0/stm32_rcc.c
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -52,11 +52,23 @@
 #include "hardware/stm32_flash.h"
 #include "stm32_gpio.h"
 #include "stm32_rcc.h"
+#include "stm32_hsi48.h"
 
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
 
+#ifdef CONFIG_STM32F0L0G0_RNG
+#  ifndef STM32_USE_CLK48
+#    error RNG requires CLK48 enabled
+#  endif
+#endif
+#ifdef CONFIG_STM32F0L0G0_USB
+#  ifndef STM32_USE_CLK48
+#    error USB requires CLK48 enabled
+#  endif
+#endif
+
 /* Allow up to 100 milliseconds for the high speed clock to become ready.
  * that is a very long delay, but if the clock does not become ready we are
  * hosed anyway.
@@ -74,6 +86,8 @@
 #  include "stm32f0_rcc.c"
 #elif defined(CONFIG_ARCH_CHIP_STM32L0)
 #  include "stm32l0_rcc.c"
+#elif defined(CONFIG_ARCH_CHIP_STM32G0)
+#  include "stm32g0_rcc.c"
 #else
 #  error "Unsupported STM32F0/L0 RCC"
 #endif
@@ -99,7 +113,7 @@
  *
  ****************************************************************************/
 
-#if defined(CONFIG_STM32F0L0_RTC) && defined(CONFIG_STM32F0L0_PWR)
+#if defined(CONFIG_STM32F0L0G0_RTC) && defined(CONFIG_STM32F0L0G0_PWR)
 static inline void rcc_resetbkp(void)
 {
   uint32_t regval;
@@ -174,7 +188,7 @@ void stm32_clockconfig(void)
 
 #endif
 
-#ifdef CONFIG_STM32F0L0_SYSCFG_IOCOMPENSATION
+#ifdef CONFIG_STM32F0L0G0_SYSCFG_IOCOMPENSATION
   /* Enable I/O Compensation */
 
   stm32_iocompensation();
diff --git a/arch/arm/src/stm32f0l0/stm32_rcc.h b/arch/arm/src/stm32f0l0g0/stm32_rcc.h
similarity index 94%
rename from arch/arm/src/stm32f0l0/stm32_rcc.h
rename to arch/arm/src/stm32f0l0g0/stm32_rcc.h
index d157305efb7..5c5444040e3 100644
--- a/arch/arm/src/stm32f0l0/stm32_rcc.h
+++ b/arch/arm/src/stm32f0l0g0/stm32_rcc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/stm32_rcc.h
+ * arch/arm/src/stm32f0l0g0/stm32_rcc.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H
-#define __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H
 
 /************************************************************************************
  * Included Files
@@ -80,4 +80,4 @@ void stm32_clockconfig(void);
 
 void stm32_rcc_enablelse(void);
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H */
diff --git a/arch/arm/src/stm32f0l0g0/stm32_rng.c b/arch/arm/src/stm32f0l0g0/stm32_rng.c
new file mode 100644
index 00000000000..001c5805e93
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/stm32_rng.c
@@ -0,0 +1,335 @@
+/****************************************************************************
+ * arch/arm/src/stm32f0l0g0/stm32_rng.c
+ *
+ *   Copyright (C) 2012 Max Holtzberg. All rights reserved.
+ *   Author: Max Holtzberg 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "up_arch.h"
+#include "hardware/stm32_rng.h"
+#include "up_internal.h"
+
+#if defined(CONFIG_STM32F0L0G0_RNG)
+#if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH)
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int stm32_rng_initialize(void);
+static int stm32_rng_interrupt(int irq, void *context, FAR void *arg);
+static void stm32_rng_enable(void);
+static void stm32_rng_disable(void);
+static ssize_t stm32_rng_read(struct file *filep, char *buffer, size_t);
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct rng_dev_s
+{
+  sem_t rd_devsem;      /* Threads can only exclusively access the RNG */
+  sem_t rd_readsem;     /* To block until the buffer is filled  */
+  char *rd_buf;
+  size_t rd_buflen;
+  uint32_t rd_lastval;
+  bool rd_first;
+};
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static struct rng_dev_s g_rngdev;
+
+static const struct file_operations g_rngops =
+{
+  NULL,            /* open */
+  NULL,            /* close */
+  stm32_rng_read,  /* read */
+  NULL,            /* write */
+  NULL,            /* seek */
+  NULL,            /* ioctl */
+  NULL             /* poll */
+#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
+  , NULL           /* unlink */
+#endif
+};
+
+/****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_rng_initialize
+ ****************************************************************************/
+
+static int stm32_rng_initialize(void)
+{
+  uint32_t regval;
+
+  _info("Initializing RNG\n");
+
+  memset(&g_rngdev, 0, sizeof(struct rng_dev_s));
+
+  nxsem_init(&g_rngdev.rd_devsem, 0, 1);
+
+  if (irq_attach(STM32_IRQ_RNG, stm32_rng_interrupt, NULL))
+    {
+      /* We could not attach the ISR to the interrupt */
+
+      _info("Could not attach IRQ.\n");
+
+      return -EAGAIN;
+    }
+
+  /* Enable interrupts */
+
+  regval = getreg32(STM32_RNG_CR);
+  regval |=  RNG_CR_IE;
+  putreg32(regval, STM32_RNG_CR);
+
+  up_enable_irq(STM32_IRQ_RNG);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32_rng_enable
+ ****************************************************************************/
+
+static void stm32_rng_enable(void)
+{
+  uint32_t regval;
+
+  g_rngdev.rd_first = true;
+
+  regval = getreg32(STM32_RNG_CR);
+  regval |= RNG_CR_RNGEN;
+  putreg32(regval, STM32_RNG_CR);
+}
+
+/****************************************************************************
+ * Name: stm32_rng_disable
+ ****************************************************************************/
+
+static void stm32_rng_disable(void)
+{
+  uint32_t regval;
+  regval = getreg32(STM32_RNG_CR);
+  regval &= ~RNG_CR_RNGEN;
+  putreg32(regval, STM32_RNG_CR);
+}
+
+/****************************************************************************
+ * Name: stm32_rng_interrupt
+ ****************************************************************************/
+
+static int stm32_rng_interrupt(int irq, void *context, FAR void *arg)
+{
+  uint32_t rngsr;
+  uint32_t data;
+
+  rngsr = getreg32(STM32_RNG_SR);
+
+  if ((rngsr & (RNG_SR_SEIS | RNG_SR_CEIS)) /* Check for error bits */
+      || !(rngsr & RNG_SR_DRDY)) /* Data ready must be set */
+    {
+      /* This random value is not valid, we will try again. */
+
+      return OK;
+    }
+
+  data = getreg32(STM32_RNG_DR);
+
+  /* As required by the FIPS PUB (Federal Information Processing Standard
+   * Publication) 140-2, the first random number generated after setting the
+   * RNGEN bit should not be used, but saved for comparison with the next
+   * generated random number. Each subsequent generated random number has to be
+   * compared with the previously generated number. The test fails if any two
+   * compared numbers are equal (continuous random number generator test).
+   */
+
+  if (g_rngdev.rd_first)
+    {
+      g_rngdev.rd_first = false;
+      g_rngdev.rd_lastval = data;
+      return OK;
+    }
+
+  if (g_rngdev.rd_lastval == data)
+    {
+      /* Two subsequent same numbers, we will try again. */
+
+      return OK;
+    }
+
+  /* If we get here, the random number is valid. */
+
+  g_rngdev.rd_lastval = data;
+
+  if (g_rngdev.rd_buflen >= 4)
+    {
+      g_rngdev.rd_buflen -= 4;
+      *(uint32_t *)&g_rngdev.rd_buf[g_rngdev.rd_buflen] = data;
+    }
+  else
+    {
+      while (g_rngdev.rd_buflen > 0)
+        {
+          g_rngdev.rd_buf[--g_rngdev.rd_buflen] = (char)data;
+          data >>= 8;
+        }
+    }
+
+  if (g_rngdev.rd_buflen == 0)
+    {
+      /* Buffer filled, stop further interrupts. */
+
+      stm32_rng_disable();
+      nxsem_post(&g_rngdev.rd_readsem);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32_rng_read
+ ****************************************************************************/
+
+static ssize_t stm32_rng_read(struct file *filep, char *buffer, size_t buflen)
+{
+  int ret;
+
+  ret = nxsem_wait(&g_rngdev.rd_devsem);
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+  /* We've got the semaphore. */
+
+  /* Initialize the operation semaphore with 0 for blocking until the
+   * buffer is filled from interrupts.  The readsem semaphore is used
+   * for signaling and, hence, should not have priority inheritance
+   * enabled.
+   */
+
+  nxsem_init(&g_rngdev.rd_readsem, 0, 0);
+  nxsem_setprotocol(&g_rngdev.rd_readsem, SEM_PRIO_NONE);
+
+  g_rngdev.rd_buflen = buflen;
+  g_rngdev.rd_buf = buffer;
+
+  /* Enable RNG with interrupts */
+
+  stm32_rng_enable();
+
+  /* Wait until the buffer is filled */
+
+  ret = nxsem_wait(&g_rngdev.rd_readsem);
+
+  /* Free RNG for next use */
+
+  nxsem_post(&g_rngdev.rd_devsem);
+  return ret < 0 ? ret : buflen;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: devrandom_register
+ *
+ * Description:
+ *   Initialize the RNG hardware and register the /dev/random driver.
+ *   Must be called BEFORE devurandom_register.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_RANDOM
+void devrandom_register(void)
+{
+  stm32_rng_initialize();
+  (void)register_driver("/dev/random", &g_rngops, 0444, NULL);
+}
+#endif
+
+/****************************************************************************
+ * Name: devurandom_register
+ *
+ * Description:
+ *   Register /dev/urandom
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEV_URANDOM_ARCH
+void devurandom_register(void)
+{
+#ifndef CONFIG_DEV_RANDOM
+  stm32_rng_initialize();
+#endif
+  (void)register_driver("/dev/urandom", &g_rngops, 0444, NULL);
+}
+#endif
+
+#endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */
+#endif /* CONFIG_STM32F0L0G0_RNG */
diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial.c b/arch/arm/src/stm32f0l0g0/stm32_serial.c
new file mode 100644
index 00000000000..6ff7d582915
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/stm32_serial.c
@@ -0,0 +1,60 @@
+/****************************************************************************
+ * arch/arm/src/stm32f0l0g0/stm32_serial.c
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *           Alan Carvalho de Assis 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include "chip.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/* This file is only a thin shell that includes the correct serial
+ * implementation for the selected STM32 IP core:
+ *   - STM32 UART IP version 1 - F0, L0
+ *   - STM32 UART IP version 2 - G0
+ */
+
+#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1)
+#  include "stm32_serial_v1.c"
+#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2)
+#  include "stm32_serial_v2.c"
+#else
+#  error "Unsupported STM32 M0 serial"
+#endif
diff --git a/arch/arm/src/stm32f0l0/stm32_serial.h b/arch/arm/src/stm32f0l0g0/stm32_serial.h
similarity index 91%
rename from arch/arm/src/stm32f0l0/stm32_serial.h
rename to arch/arm/src/stm32f0l0g0/stm32_serial.h
index b51ef343fee..8fe1f9cb2b9 100644
--- a/arch/arm/src/stm32f0l0/stm32_serial.h
+++ b/arch/arm/src/stm32f0l0g0/stm32_serial.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/stm32_serial.h
+ * arch/arm/src/stm32f0l0g0/stm32_serial.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_SERIAL_H
-#define __ARCH_ARM_SRC_STM32F0L0_STM32_SERIAL_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H
 
 /************************************************************************************
  * Included Files
@@ -47,4 +47,4 @@
  * Pre-processor Definitions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_SERIAL_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H */
diff --git a/arch/arm/src/stm32f0l0/stm32_serial.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c
similarity index 97%
rename from arch/arm/src/stm32f0l0/stm32_serial.c
rename to arch/arm/src/stm32f0l0g0/stm32_serial_v1.c
index d38a9b21b27..97bf3fbe2d4 100644
--- a/arch/arm/src/stm32f0l0/stm32_serial.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f0l0/stm32_serial.c
+ * arch/arm/src/stm32f0l0g0/stm32_serial_v1.c
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -97,14 +97,14 @@
  */
 
 #  if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA)
-#    ifndef CONFIG_STM32F0L0_DMA1
-#      error STM32F0 USART2/3 receive DMA requires CONFIG_STM32F0L0_DMA1
+#    ifndef CONFIG_STM32F0L0G0_DMA1
+#      error STM32F0 USART2/3 receive DMA requires CONFIG_STM32F0L0G0_DMA1
 #    endif
 #  endif
 
 #  if defined(CONFIG_USART4_RXDMA) || defined(CONFIG_USART5_RXDMA)
-#    ifndef CONFIG_STM32F0L0_DMA2
-#      error STM32F0 USART4/5 receive DMA requires CONFIG_STM32F0L0_DMA2
+#    ifndef CONFIG_STM32F0L0G0_DMA2
+#      error STM32F0 USART4/5 receive DMA requires CONFIG_STM32F0L0G0_DMA2
 #    endif
 #  endif
 
@@ -173,8 +173,8 @@
 
 /* Power management definitions */
 
-#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY)
-#  define CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY 10
+#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY)
+#  define CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY 10
 #endif
 #if defined(CONFIG_PM)
 #  define PM_IDLE_DOMAIN             0 /* Revisit */
@@ -191,7 +191,7 @@
  * See stm32serial_restoreusartint where the masking is done.
  */
 
-#ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT
+#ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
 #  define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
 #  define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
 #endif
@@ -363,7 +363,7 @@ static const struct uart_ops_s g_uart_dma_ops =
 
 /* I/O buffers */
 
-#ifdef CONFIG_STM32F0L0_USART1
+#ifdef CONFIG_STM32F0L0G0_USART1
 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
 static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
 # ifdef CONFIG_USART1_RXDMA
@@ -371,7 +371,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE];
 # endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART2
+#ifdef CONFIG_STM32F0L0G0_USART2
 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
 static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
 # ifdef CONFIG_USART2_RXDMA
@@ -379,7 +379,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE];
 # endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART3
+#ifdef CONFIG_STM32F0L0G0_USART3
 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE];
 static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE];
 # ifdef CONFIG_USART3_RXDMA
@@ -387,7 +387,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE];
 # endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART4
+#ifdef CONFIG_STM32F0L0G0_USART4
 static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE];
 static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE];
 # ifdef CONFIG_USART4_RXDMA
@@ -395,7 +395,7 @@ static char g_usart4rxfifo[RXDMA_BUFFER_SIZE];
 # endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART5
+#ifdef CONFIG_STM32F0L0G0_USART5
 static char g_usart5rxbuffer[CONFIG_USART5_RXBUFSIZE];
 static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE];
 # ifdef CONFIG_USART5_RXDMA
@@ -405,7 +405,7 @@ static char g_usart5rxfifo[RXDMA_BUFFER_SIZE];
 
 /* This describes the state of the STM32 USART1 ports. */
 
-#ifdef CONFIG_STM32F0L0_USART1
+#ifdef CONFIG_STM32F0L0G0_USART1
 static struct stm32_serial_s g_usart1priv =
 {
   .dev =
@@ -466,7 +466,7 @@ static struct stm32_serial_s g_usart1priv =
 
 /* This describes the state of the STM32 USART2 port. */
 
-#ifdef CONFIG_STM32F0L0_USART2
+#ifdef CONFIG_STM32F0L0G0_USART2
 static struct stm32_serial_s g_usart2priv =
 {
   .dev =
@@ -527,7 +527,7 @@ static struct stm32_serial_s g_usart2priv =
 
 /* This describes the state of the STM32 USART3 port. */
 
-#ifdef CONFIG_STM32F0L0_USART3
+#ifdef CONFIG_STM32F0L0G0_USART3
 static struct stm32_serial_s g_usart3priv =
 {
   .dev =
@@ -553,7 +553,7 @@ static struct stm32_serial_s g_usart3priv =
       .priv      = &g_usart3priv,
     },
 
-  .irq           = STM32_IRQ_USART345678,
+  .irq           = STM32_IRQ_USART3,
   .parity        = CONFIG_USART3_PARITY,
   .bits          = CONFIG_USART3_BITS,
   .stopbits2     = CONFIG_USART3_2STOP,
@@ -588,7 +588,7 @@ static struct stm32_serial_s g_usart3priv =
 
 /* This describes the state of the STM32 USART4 port. */
 
-#ifdef CONFIG_STM32F0L0_USART4
+#ifdef CONFIG_STM32F0L0G0_USART4
 static struct stm32_serial_s g_usart4priv =
 {
   .dev =
@@ -614,7 +614,7 @@ static struct stm32_serial_s g_usart4priv =
       .priv      = &g_usart4priv,
     },
 
-  .irq           = STM32_IRQ_USART345678,
+  .irq           = STM32_IRQ_USART4,
   .parity        = CONFIG_USART4_PARITY,
   .bits          = CONFIG_USART4_BITS,
   .stopbits2     = CONFIG_USART4_2STOP,
@@ -653,7 +653,7 @@ static struct stm32_serial_s g_usart4priv =
 
 /* This describes the state of the STM32 USART5 port. */
 
-#ifdef CONFIG_STM32F0L0_USART5
+#ifdef CONFIG_STM32F0L0G0_USART5
 static struct stm32_serial_s g_usart5priv =
 {
   .dev =
@@ -679,7 +679,7 @@ static struct stm32_serial_s g_usart5priv =
       .priv     = &g_usart5priv,
     },
 
-  .irq            = STM32_IRQ_USART345678,
+  .irq            = STM32_IRQ_USART5,
   .parity         = CONFIG_USART5_PARITY,
   .bits           = CONFIG_USART5_BITS,
   .stopbits2      = CONFIG_USART5_2STOP,
@@ -720,19 +720,19 @@ static struct stm32_serial_s g_usart5priv =
 
 FAR static struct stm32_serial_s * const g_uart_devs[STM32_NUSART] =
 {
-#ifdef CONFIG_STM32F0L0_USART1
+#ifdef CONFIG_STM32F0L0G0_USART1
   [0] = &g_usart1priv,
 #endif
-#ifdef CONFIG_STM32F0L0_USART2
+#ifdef CONFIG_STM32F0L0G0_USART2
   [1] = &g_usart2priv,
 #endif
-#ifdef CONFIG_STM32F0L0_USART3
+#ifdef CONFIG_STM32F0L0G0_USART3
   [2] = &g_usart3priv,
 #endif
-#ifdef CONFIG_STM32F0L0_USART4
+#ifdef CONFIG_STM32F0L0G0_USART4
   [3] = &g_usart4priv,
 #endif
-#ifdef CONFIG_STM32F0L0_USART5
+#ifdef CONFIG_STM32F0L0G0_USART5
   [4] = &g_usart5priv,
 #endif
 };
@@ -1008,7 +1008,7 @@ static void stm32serial_setformat(FAR struct uart_dev_s *dev)
   regval  = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET);
   regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE);
 
-#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32F0L0_FLOWCONTROL_BROKEN)
+#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN)
   if (priv->iflow && (priv->rts_gpio != 0))
     {
       regval |= USART_CR3_RTSE;
@@ -1050,31 +1050,31 @@ static void stm32serial_setapbclock(FAR struct uart_dev_s *dev, bool on)
     {
     default:
       return;
-#ifdef CONFIG_STM32F0L0_USART1
+#ifdef CONFIG_STM32F0L0G0_USART1
     case STM32_USART1_BASE:
       rcc_en  = RCC_APB2ENR_USART1EN;
       regaddr = STM32_RCC_APB2ENR;
       break;
 #endif
-#ifdef CONFIG_STM32F0L0_USART2
+#ifdef CONFIG_STM32F0L0G0_USART2
     case STM32_USART2_BASE:
       rcc_en  = RCC_APB1ENR_USART2EN;
       regaddr = STM32_RCC_APB1ENR;
       break;
 #endif
-#ifdef CONFIG_STM32F0L0_USART3
+#ifdef CONFIG_STM32F0L0G0_USART3
     case STM32_USART3_BASE:
       rcc_en  = RCC_APB1ENR_USART3EN;
       regaddr = STM32_RCC_APB1ENR;
       break;
 #endif
-#ifdef CONFIG_STM32F0L0_USART4
+#ifdef CONFIG_STM32F0L0G0_USART4
     case STM32_USART4_BASE:
       rcc_en  = RCC_APB1ENR_USART4EN;
       regaddr = STM32_RCC_APB1ENR;
       break;
 #endif
-#ifdef CONFIG_STM32F0L0_USART5
+#ifdef CONFIG_STM32F0L0G0_USART5
     case STM32_USART5_BASE:
       rcc_en  = RCC_APB1ENR_USART5EN;
       regaddr = STM32_RCC_APB1ENR;
@@ -1135,7 +1135,7 @@ static int stm32serial_setup(FAR struct uart_dev_s *dev)
     {
       uint32_t config = priv->rts_gpio;
 
-#ifdef CONFIG_STM32F0L0_FLOWCONTROL_BROKEN
+#ifdef CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN
       /* Instead of letting hw manage this pin, we will bitbang */
 
       config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT;
@@ -1460,8 +1460,8 @@ static int up_interrupt(int irq, FAR void *context, FAR void *arg)
 
   /* Report serial activity to the power management logic */
 
-#if defined(CONFIG_PM) && CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY > 0
-  pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0_PM_SERIAL_ACTIVITY);
+#if defined(CONFIG_PM) && CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY > 0
+  pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY);
 #endif
 
   /* Loop until there are no characters to be transferred or,
@@ -1592,7 +1592,7 @@ static int stm32serial_ioctl(FAR struct file *filep, int cmd,
       break;
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART_SINGLEWIRE
+#ifdef CONFIG_STM32F0L0G0_USART_SINGLEWIRE
 #warning please review the potential use of ALTERNATE_FUNCTION_OPENDRAIN
     case TIOCSSINGLEWIRE:
       {
@@ -1713,8 +1713,8 @@ static int stm32serial_ioctl(FAR struct file *filep, int cmd,
       break;
 #endif /* CONFIG_SERIAL_TERMIOS */
 
-#ifdef CONFIG_STM32F0L0_USART_BREAKS
-#  ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT
+#ifdef CONFIG_STM32F0L0G0_USART_BREAKS
+#  ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
     case TIOCSBRK:  /* BSD compatibility: Turn break on, unconditionally */
       {
         irqstate_t flags;
@@ -1927,7 +1927,7 @@ static bool stm32serial_rxflowcontrol(FAR struct uart_dev_s *dev,
   FAR struct stm32_serial_s *priv = (FAR struct stm32_serial_s *)dev->priv;
 
 #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \
-    defined(CONFIG_STM32F0L0_FLOWCONTROL_BROKEN)
+    defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN)
   if (priv->iflow && (priv->rts_gpio != 0))
     {
       /* Assert/de-assert nRTS set it high resume/stop sending */
@@ -2173,7 +2173,7 @@ static void stm32serial_txint(FAR struct uart_dev_s *dev, bool enable)
         }
 #  endif
 
-#  ifdef CONFIG_STM32F0L0_SERIALBRK_BSDCOMPAT
+#  ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
       if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
         {
           return;
@@ -2426,7 +2426,7 @@ void up_serialinit(void)
 #if CONSOLE_USART > 0
   (void)uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev);
 
-#ifndef CONFIG_STM32F0L0_SERIAL_DISABLE_REORDERING
+#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING
   /* If not disabled, register the console USART to ttyS0 and exclude
    * it from initializing it further down
    */
@@ -2455,7 +2455,7 @@ void up_serialinit(void)
           continue;
         }
 
-#ifndef CONFIG_STM32F0L0_SERIAL_DISABLE_REORDERING
+#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING
       /* Don't create a device for the console - we did that above */
 
       if (g_uart_devs[i]->dev.isconsole)
diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c
new file mode 100644
index 00000000000..3463093471f
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c
@@ -0,0 +1,1959 @@
+/****************************************************************************
+ * arch/arm/src/stm32f0l0g0/stm32_serial.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *            David Sidrane 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_SERIAL_TERMIOS
+#  include 
+#endif
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "chip.h"
+#include "stm32_gpio.h"
+#include "hardware/stm32_pinmap.h"
+#include "stm32_rcc.h"
+#include "stm32_uart.h"
+
+#include 
+
+#ifdef CONFIG_STM32F0L0G0_USART3
+#  error not supported yet
+#endif
+#ifdef CONFIG_STM32F0L0G0_USART4
+#  error not supported yet
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+/* Some sanity checks *******************************************************/
+/* Total number of possible serial devices */
+
+#define STM32_NSERIAL (STM32_NUSART)
+#define HAVE_UART
+
+/* Power management definitions */
+
+#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY)
+#  define CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY 10
+#endif
+#if defined(CONFIG_PM)
+#  define PM_IDLE_DOMAIN             0 /* Revisit */
+#endif
+
+/* Keep track if a Break was set
+ *
+ * Note:
+ *
+ * 1) This value is set in the priv->ie but never written to the control
+ *    register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE
+ * 2) USART_CR3_EIE is also carried in the up_dev_s ie member.
+ *
+ * See up_restoreusartint where the masking is done.
+ */
+
+#ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
+#  define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
+#  define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
+#endif
+
+#ifdef USE_SERIALDRIVER
+#ifdef HAVE_UART
+
+/* Warnings for potentially unsafe configuration combinations. */
+
+#if defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) && \
+    !defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS)
+#  error "CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN requires \
+          CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled."
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct up_dev_s
+{
+  struct uart_dev_s dev;       /* Generic UART device */
+  uint16_t          ie;        /* Saved interrupt mask bits value */
+  uint16_t          sr;        /* Saved status bits */
+
+  /* Has been initialized and HW is setup. */
+
+  bool              initialized;
+
+  /* If termios are supported, then the following fields may vary at
+   * runtime.
+   */
+
+#ifdef CONFIG_SERIAL_TERMIOS
+  uint8_t           parity;    /* 0=none, 1=odd, 2=even */
+  uint8_t           bits;      /* Number of bits (7 or 8) */
+  bool              stopbits2; /* True: Configure with 2 stop bits instead of 1 */
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+  bool              iflow;     /* input flow control (RTS) enabled */
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+  bool              oflow;     /* output flow control (CTS) enabled */
+#endif
+  uint32_t          baud;      /* Configured baud */
+#else
+  const uint8_t     rxftcfg;   /* Rx FIFO threshold level */
+  const uint8_t     parity;    /* 0=none, 1=odd, 2=even */
+  const uint8_t     bits;      /* Number of bits (7 or 8) */
+  const bool        stopbits2; /* True: Configure with 2 stop bits instead of 1 */
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+  const bool        iflow;     /* input flow control (RTS) enabled */
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+  const bool        oflow;     /* output flow control (CTS) enabled */
+#endif
+  const uint32_t    baud;      /* Configured baud */
+#endif
+
+  const uint8_t     irq;       /* IRQ associated with this USART */
+  const uint32_t    apbclock;  /* PCLK 1 or 2 frequency */
+  const uint32_t    usartbase; /* Base address of USART registers */
+  const uint32_t    tx_gpio;   /* U[S]ART TX GPIO pin configuration */
+  const uint32_t    rx_gpio;   /* U[S]ART RX GPIO pin configuration */
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+  const uint32_t    rts_gpio;  /* U[S]ART RTS GPIO pin configuration */
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+  const uint32_t    cts_gpio;  /* U[S]ART CTS GPIO pin configuration */
+#endif
+
+#ifdef HAVE_RS485
+  const uint32_t    rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */
+  const bool        rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */
+#endif
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static void up_set_format(struct uart_dev_s *dev);
+static int  up_setup(struct uart_dev_s *dev);
+static void up_shutdown(struct uart_dev_s *dev);
+static int  up_attach(struct uart_dev_s *dev);
+static void up_detach(struct uart_dev_s *dev);
+static int  up_interrupt(int irq, void *context, FAR void *arg);
+static int  up_ioctl(struct file *filep, int cmd, unsigned long arg);
+static int  up_receive(struct uart_dev_s *dev, unsigned int *status);
+static void up_rxint(struct uart_dev_s *dev, bool enable);
+static bool up_rxavailable(struct uart_dev_s *dev);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool up_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered,
+                             bool upper);
+#endif
+static void up_send(struct uart_dev_s *dev, int ch);
+static void up_txint(struct uart_dev_s *dev, bool enable);
+static bool up_txready(struct uart_dev_s *dev);
+
+#ifdef CONFIG_PM
+static void up_pm_notify(struct pm_callback_s *cb, int domain,
+                         enum pm_state_e pmstate);
+static int  up_pm_prepare(struct pm_callback_s *cb, int domain,
+                          enum pm_state_e pmstate);
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct uart_ops_s g_uart_ops =
+{
+  .setup          = up_setup,
+  .shutdown       = up_shutdown,
+  .attach         = up_attach,
+  .detach         = up_detach,
+  .ioctl          = up_ioctl,
+  .receive        = up_receive,
+  .rxint          = up_rxint,
+  .rxavailable    = up_rxavailable,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+  .rxflowcontrol  = up_rxflowcontrol,
+#endif
+  .send           = up_send,
+  .txint          = up_txint,
+  .txready        = up_txready,
+  .txempty        = up_txready,
+};
+
+/* Receive/Transmit buffers */
+
+#ifdef CONFIG_STM32F0L0G0_USART1
+static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
+static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_USART2
+static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
+static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_USART3
+static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE];
+static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE];
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_USART4
+static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE];
+static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE];
+#endif
+
+/* This describes the state of the STM32 USART1 ports. */
+
+#ifdef CONFIG_STM32F0L0G0_USART1
+static struct up_dev_s g_usart1priv =
+{
+  .dev =
+    {
+#if CONSOLE_USART == 1
+      .isconsole = true,
+#endif
+      .recv      =
+      {
+        .size    = CONFIG_USART1_RXBUFSIZE,
+        .buffer  = g_usart1rxbuffer,
+      },
+      .xmit      =
+      {
+        .size    = CONFIG_USART1_TXBUFSIZE,
+        .buffer  = g_usart1txbuffer,
+      },
+      .ops       = &g_uart_ops,
+      .priv      = &g_usart1priv,
+    },
+
+  .irq           = STM32_IRQ_USART1,
+  .rxftcfg       = CONFIG_USART1_RXFIFO_THRES,
+  .parity        = CONFIG_USART1_PARITY,
+  .bits          = CONFIG_USART1_BITS,
+  .stopbits2     = CONFIG_USART1_2STOP,
+  .baud          = CONFIG_USART1_BAUD,
+  .apbclock      = STM32_PCLK1_FREQUENCY,
+  .usartbase     = STM32_USART1_BASE,
+  .tx_gpio       = GPIO_USART1_TX,
+  .rx_gpio       = GPIO_USART1_RX,
+#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
+  .oflow         = true,
+  .cts_gpio      = GPIO_USART1_CTS,
+#endif
+#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL)
+  .iflow         = true,
+  .rts_gpio      = GPIO_USART1_RTS,
+#endif
+
+#ifdef CONFIG_USART1_RS485
+  .rs485_dir_gpio = GPIO_USART1_RS485_DIR,
+#  if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
+  .rs485_dir_polarity = false,
+#  else
+  .rs485_dir_polarity = true,
+#  endif
+#endif
+};
+#endif
+
+/* This describes the state of the STM32 USART2 port. */
+
+#ifdef CONFIG_STM32F0L0G0_USART2
+static struct up_dev_s g_usart2priv =
+{
+  .dev =
+    {
+#if CONSOLE_USART == 2
+      .isconsole = true,
+#endif
+      .recv      =
+      {
+        .size    = CONFIG_USART2_RXBUFSIZE,
+        .buffer  = g_usart2rxbuffer,
+      },
+      .xmit      =
+      {
+        .size    = CONFIG_USART2_TXBUFSIZE,
+        .buffer  = g_usart2txbuffer,
+      },
+      .ops       = &g_uart_ops,
+      .priv      = &g_usart2priv,
+    },
+
+  .irq           = STM32_IRQ_USART2,
+  .rxftcfg       = CONFIG_USART2_RXFIFO_THRES,
+  .parity        = CONFIG_USART2_PARITY,
+  .bits          = CONFIG_USART2_BITS,
+  .stopbits2     = CONFIG_USART2_2STOP,
+  .baud          = CONFIG_USART2_BAUD,
+  .apbclock      = STM32_PCLK1_FREQUENCY,
+  .usartbase     = STM32_USART2_BASE,
+  .tx_gpio       = GPIO_USART2_TX,
+  .rx_gpio       = GPIO_USART2_RX,
+#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL)
+  .oflow         = true,
+  .cts_gpio      = GPIO_USART2_CTS,
+#endif
+#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL)
+  .iflow         = true,
+  .rts_gpio      = GPIO_USART2_RTS,
+#endif
+
+#ifdef CONFIG_USART2_RS485
+  .rs485_dir_gpio = GPIO_USART2_RS485_DIR,
+#  if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
+  .rs485_dir_polarity = false,
+#  else
+  .rs485_dir_polarity = true,
+#  endif
+#endif
+};
+#endif
+
+/* TODO: USART3 */
+
+/* TODO: USART4 */
+
+/* This table lets us iterate over the configured USARTs */
+
+static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] =
+{
+#ifdef CONFIG_STM32F0L0G0_USART1
+  [0] = &g_usart1priv,
+#endif
+#ifdef CONFIG_STM32F0L0G0_USART2
+  [1] = &g_usart2priv,
+#endif
+#ifdef CONFIG_STM32F0L0G0_USART3
+  [2] = &g_usart3priv,
+#endif
+#ifdef CONFIG_STM32F0L0G0_USART4
+  [3] = &g_usart4priv
+#endif
+};
+
+#ifdef CONFIG_PM
+static  struct pm_callback_s g_serialcb =
+{
+  .notify  = up_pm_notify,
+  .prepare = up_pm_prepare,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_serialin
+ ****************************************************************************/
+
+static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
+{
+  return getreg32(priv->usartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_serialout
+ ****************************************************************************/
+
+static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
+{
+  putreg32(value, priv->usartbase + offset);
+}
+
+/****************************************************************************
+ * Name: up_serialmod
+ ****************************************************************************/
+
+static inline void up_serialmod(struct up_dev_s *priv, int offset,
+                                uint32_t clrbits, uint32_t setbits)
+{
+  uint32_t addr = priv->usartbase + offset;
+  uint32_t regval = (getreg32(addr) & ~clrbits) | setbits;
+  putreg32(regval, addr);
+}
+
+/****************************************************************************
+ * Name: up_setusartint
+ ****************************************************************************/
+
+static inline void up_setusartint(struct up_dev_s *priv, uint16_t ie)
+{
+  uint32_t cr;
+
+  /* Save the interrupt mask */
+
+  priv->ie = ie;
+
+  /* And restore the interrupt state (see the interrupt enable/usage table above) */
+
+  cr = up_serialin(priv, STM32_USART_CR1_OFFSET);
+  cr &= ~(USART_CR1_USED_INTS);
+  cr |= (ie & (USART_CR1_USED_INTS));
+  up_serialout(priv, STM32_USART_CR1_OFFSET, cr);
+
+  cr = up_serialin(priv, STM32_USART_CR3_OFFSET);
+  cr &= ~USART_CR3_EIE;
+  cr |= (ie & USART_CR3_EIE);
+  up_serialout(priv, STM32_USART_CR3_OFFSET, cr);
+}
+
+/****************************************************************************
+ * Name: up_restoreusartint
+ ****************************************************************************/
+
+static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie)
+{
+  irqstate_t flags;
+
+  flags = enter_critical_section();
+
+  up_setusartint(priv, ie);
+
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: up_disableusartint
+ ****************************************************************************/
+
+static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
+{
+  irqstate_t flags;
+
+  flags = enter_critical_section();
+
+  if (ie)
+    {
+      uint32_t cr1;
+      uint32_t cr3;
+
+      /* USART interrupts:
+       *
+       * Enable             Status          Meaning                        Usage
+       * ------------------ --------------- ------------------------------ ----------
+       * USART_CR1_IDLEIE   USART_ISR_IDLE  Idle Line Detected             (not used)
+       * USART_CR1_RXNEIE   USART_ISR_RXNE  Received Data Ready to be Read
+       * "              "   USART_ISR_ORE   Overrun Error Detected
+       * USART_CR1_TCIE     USART_ISR_TC    Transmission Complete          (used only for RS-485)
+       * USART_CR1_TXEIE    USART_ISR_TXE   Transmit Data Register Empty
+       * USART_CR1_PEIE     USART_ISR_PE    Parity Error
+       *
+       * USART_CR2_LBDIE    USART_ISR_LBD   Break Flag                     (not used)
+       * USART_CR3_EIE      USART_ISR_FE    Framing Error
+       * "           "      USART_ISR_NF    Noise Error
+       * "           "      USART_ISR_ORE   Overrun Error Detected
+       * USART_CR3_CTSIE    USART_ISR_CTS   CTS flag                       (not used)
+       */
+
+      cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET);
+      cr3 = up_serialin(priv, STM32_USART_CR3_OFFSET);
+
+      /* Return the current interrupt mask value for the used interrupts.  Notice
+       * that this depends on the fact that none of the used interrupt enable bits
+       * overlap.  This logic would fail if we needed the break interrupt!
+       */
+
+      *ie = (cr1 & (USART_CR1_USED_INTS)) | (cr3 & USART_CR3_EIE);
+    }
+
+  /* Disable all interrupts */
+
+  up_setusartint(priv, 0);
+
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: up_set_format
+ *
+ * Description:
+ *   Set the serial line format and speed.
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SUPPRESS_UART_CONFIG
+static void up_set_format(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+  uint32_t regval;
+  uint32_t usartdiv8;
+  uint32_t cr1;
+  uint32_t cr1_ue;
+  uint32_t brr;
+  irqstate_t flags;
+
+  flags = enter_critical_section();
+
+  /* Get the original state of UE */
+
+  cr1  = up_serialin(priv, STM32_USART_CR1_OFFSET);
+  cr1_ue = cr1 & USART_CR1_UE;
+  cr1 &= ~USART_CR1_UE;
+
+  /* Disable UE as the format bits and baud rate registers can not be
+   * updated while UE = 1 */
+
+  up_serialout(priv, STM32_USART_CR1_OFFSET, cr1);
+
+  /* In case of oversampling by 8, the equation is:
+   *
+   *   baud      = 2 * fCK / usartdiv8
+   *   usartdiv8 = 2 * fCK / baud
+   */
+
+  usartdiv8 = ((priv->apbclock << 1) + (priv->baud >> 1)) / priv->baud;
+
+  /* Baud rate for standard USART (SPI mode included):
+   *
+   * In case of oversampling by 16, the equation is:
+   *   baud       = fCK / usartdiv16
+   *   usartdiv16 = fCK / baud
+   *              = 2 * usartdiv8
+   */
+
+  /* Use oversamply by 8 only if the divisor is small.  But what is small? */
+
+  if (usartdiv8 > 100)
+    {
+      /* Use usartdiv16 */
+
+      brr  = (usartdiv8 + 1) >> 1;
+
+      /* Clear oversampling by 8 to enable oversampling by 16 */
+
+      cr1 &= ~USART_CR1_OVER8;
+    }
+  else
+    {
+      DEBUGASSERT(usartdiv8 >= 8);
+
+      /* Perform mysterious operations on bits 0-3 */
+
+      brr  = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1));
+
+      /* Set oversampling by 8 */
+
+      cr1 |= USART_CR1_OVER8;
+    }
+
+  up_serialout(priv, STM32_USART_CR1_OFFSET, cr1);
+  up_serialout(priv, STM32_USART_BRR_OFFSET, brr);
+
+  /* Configure parity mode */
+
+  cr1 &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1);
+
+  if (priv->parity == 1)       /* Odd parity */
+    {
+      cr1 |= (USART_CR1_PCE | USART_CR1_PS);
+    }
+  else if (priv->parity == 2)  /* Even parity */
+    {
+      cr1 |= USART_CR1_PCE;
+    }
+
+  /* Configure word length (parity uses one of configured bits)
+   *
+   * Default: 1 start, 8 data (no parity), n stop, OR
+   *          1 start, 7 data + parity, n stop
+   */
+
+  if (priv->bits == 9 || (priv->bits == 8 && priv->parity != 0))
+    {
+      /* Select: 1 start, 8 data + parity, n stop, OR
+       *         1 start, 9 data (no parity), n stop.
+       */
+
+      cr1 |= USART_CR1_M0;
+    }
+  else if (priv->bits == 7 && priv->parity == 0)
+    {
+      /* Select: 1 start, 7 data (no parity), n stop, OR
+       */
+
+      cr1 |= USART_CR1_M1;
+    }
+
+  /* Else Select: 1 start, 7 data + parity, n stop, OR
+   *              1 start, 8 data (no parity), n stop.
+   */
+
+  up_serialout(priv, STM32_USART_CR1_OFFSET, cr1);
+
+  /* Configure STOP bits */
+
+  regval = up_serialin(priv, STM32_USART_CR2_OFFSET);
+  regval &= ~(USART_CR2_STOP_MASK);
+
+  if (priv->stopbits2)
+    {
+      regval |= USART_CR2_STOP2;
+    }
+
+  up_serialout(priv, STM32_USART_CR2_OFFSET, regval);
+
+  /* Configure hardware flow control */
+
+  regval  = up_serialin(priv, STM32_USART_CR3_OFFSET);
+  regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE);
+
+#if defined(CONFIG_SERIAL_IFLOWCONTROL) && \
+   !defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN)
+  if (priv->iflow && (priv->rts_gpio != 0))
+    {
+      regval |= USART_CR3_RTSE;
+    }
+#endif
+
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+  if (priv->oflow && (priv->cts_gpio != 0))
+    {
+      regval |= USART_CR3_CTSE;
+    }
+#endif
+
+  up_serialout(priv, STM32_USART_CR3_OFFSET, regval);
+  up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue);
+  leave_critical_section(flags);
+}
+#endif /* CONFIG_SUPPRESS_UART_CONFIG */
+
+/****************************************************************************
+ * Name: up_set_apb_clock
+ *
+ * Description:
+ *   Enable or disable APB clock for the USART peripheral
+ *
+ * Input Parameters:
+ *   dev - A reference to the UART driver state structure
+ *   on  - Enable clock if 'on' is 'true' and disable if 'false'
+ *
+ ****************************************************************************/
+
+static void up_set_apb_clock(struct uart_dev_s *dev, bool on)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+  uint32_t rcc_en;
+  uint32_t regaddr;
+
+  /* Determine which USART to configure */
+
+  switch (priv->usartbase)
+    {
+    default:
+      return;
+#ifdef CONFIG_STM32F0L0G0_USART1
+    case STM32_USART1_BASE:
+      rcc_en = RCC_APB2ENR_USART1EN;
+      regaddr = STM32_RCC_APB2ENR;
+      break;
+#endif
+#ifdef CONFIG_STM32F0L0G0_USART2
+    case STM32_USART2_BASE:
+      rcc_en = RCC_APB1ENR_USART2EN;
+      regaddr = STM32_RCC_APB1ENR;
+      break;
+#endif
+#ifdef CONFIG_STM32F0L0G0_USART3
+    case STM32_USART3_BASE:
+      rcc_en = RCC_APB1ENR_USART3EN;
+      regaddr = STM32_RCC_APB1ENR;
+      break;
+#endif
+#ifdef CONFIG_STM32F0L0G0_USART4
+    case STM32_USART4_BASE:
+      rcc_en = RCC_APB1ENR_USART4EN;
+      regaddr = STM32_RCC_APB1ENR;
+      break;
+#endif
+    }
+
+  /* Enable/disable APB 1/2 clock for USART */
+
+  if (on)
+    {
+      modifyreg32(regaddr, 0, rcc_en);
+    }
+  else
+    {
+      modifyreg32(regaddr, rcc_en, 0);
+    }
+}
+
+/****************************************************************************
+ * Name: up_setup
+ *
+ * Description:
+ *   Configure the USART baud, bits, parity, etc. This method is called the
+ *   first time that the serial port is opened.
+ *
+ ****************************************************************************/
+
+static int up_setup(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+  /* Make sure that USART is disabled */
+
+  up_serialout(priv, STM32_USART_CR1_OFFSET, 0);
+
+#ifndef CONFIG_SUPPRESS_UART_CONFIG
+  uint32_t regval;
+
+  /* Note: The logic here depends on the fact that that the USART module
+   * was enabled in stm32_lowsetup().
+   */
+
+  /* Enable USART APB1/2 clock */
+
+  up_set_apb_clock(dev, true);
+
+  /* Configure pins for USART use */
+
+  stm32_configgpio(priv->tx_gpio);
+  stm32_configgpio(priv->rx_gpio);
+
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+  if (priv->cts_gpio != 0)
+    {
+      stm32_configgpio(priv->cts_gpio);
+    }
+#endif
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+  if (priv->rts_gpio != 0)
+    {
+      uint32_t config = priv->rts_gpio;
+
+#ifdef CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN
+      /* Instead of letting hw manage this pin, we will bitbang */
+
+      config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT;
+#endif
+      stm32_configgpio(config);
+    }
+#endif
+
+#ifdef HAVE_RS485
+  if (priv->rs485_dir_gpio != 0)
+    {
+      stm32_configgpio(priv->rs485_dir_gpio);
+      stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity);
+    }
+#endif
+
+  /* Configure CR2 */
+  /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */
+
+  regval  = up_serialin(priv, STM32_USART_CR2_OFFSET);
+  regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL |
+              USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE);
+
+  /* Configure STOP bits */
+
+  if (priv->stopbits2)
+    {
+      regval |= USART_CR2_STOP2;
+    }
+
+  up_serialout(priv, STM32_USART_CR2_OFFSET, regval);
+
+  /* Configure CR1 */
+  /* Clear TE, REm and all interrupt enable bits */
+
+  regval  = up_serialin(priv, STM32_USART_CR1_OFFSET);
+  regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS);
+
+  up_serialout(priv, STM32_USART_CR1_OFFSET, regval);
+
+  /* Configure CR3 */
+  /* Clear CTSE, RTSE, and all interrupt enable bits */
+
+  regval  = up_serialin(priv, STM32_USART_CR3_OFFSET);
+  regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE);
+
+  /* Set Rx FIFO threshold to the configured level */
+
+  regval |= USART_CR3_RXFTCFG(priv->rxftcfg);
+
+  up_serialout(priv, STM32_USART_CR3_OFFSET, regval);
+
+  /* Configure the USART line format and speed. */
+
+  up_set_format(dev);
+
+  /* Enable Rx, Tx, and the USART */
+  /* Enable FIFO */
+
+  regval  = up_serialin(priv, STM32_USART_CR1_OFFSET);
+  regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
+  regval |= USART_CR1_FIFOEN;
+
+  up_serialout(priv, STM32_USART_CR1_OFFSET, regval);
+
+#endif /* CONFIG_SUPPRESS_UART_CONFIG */
+
+  /* Set up the cached interrupt enables value */
+
+  priv->ie = 0;
+
+  /* Mark device as initialized. */
+
+  priv->initialized = true;
+
+  return OK;
+}
+
+
+/****************************************************************************
+ * Name: up_shutdown
+ *
+ * Description:
+ *   Disable the USART.  This method is called when the serial
+ *   port is closed
+ *
+ ****************************************************************************/
+
+static void up_shutdown(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+  uint32_t regval;
+
+  /* Mark device as uninitialized. */
+
+  priv->initialized = false;
+
+  /* Disable all interrupts */
+
+  up_disableusartint(priv, NULL);
+
+  /* Disable USART APB1/2 clock */
+
+  up_set_apb_clock(dev, false);
+
+  /* Disable Rx, Tx, and the UART */
+
+  regval  = up_serialin(priv, STM32_USART_CR1_OFFSET);
+  regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
+  up_serialout(priv, STM32_USART_CR1_OFFSET, regval);
+
+  /* Release pins. "If the serial-attached device is powered down, the TX
+   * pin causes back-powering, potentially confusing the device to the point
+   * of complete lock-up."
+   *
+   * REVISIT:  Is unconfiguring the pins appropriate for all device?  If not,
+   * then this may need to be a configuration option.
+   */
+
+  stm32_unconfiggpio(priv->tx_gpio);
+  stm32_unconfiggpio(priv->rx_gpio);
+
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+  if (priv->cts_gpio != 0)
+    {
+      stm32_unconfiggpio(priv->cts_gpio);
+    }
+#endif
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+  if (priv->rts_gpio != 0)
+    {
+      stm32_unconfiggpio(priv->rts_gpio);
+    }
+#endif
+
+#ifdef HAVE_RS485
+  if (priv->rs485_dir_gpio != 0)
+    {
+      stm32_unconfiggpio(priv->rs485_dir_gpio);
+    }
+#endif
+}
+
+
+/****************************************************************************
+ * Name: up_attach
+ *
+ * Description:
+ *   Configure the USART to operation in interrupt driven mode.  This method is
+ *   called when the serial port is opened.  Normally, this is just after the
+ *   the setup() method is called, however, the serial console may operate in
+ *   a non-interrupt driven mode during the boot phase.
+ *
+ *   RX and TX interrupts are not enabled when by the attach method (unless the
+ *   hardware supports multiple levels of interrupt enabling).  The RX and TX
+ *   interrupts are not enabled until the txint() and rxint() methods are called.
+ *
+ ****************************************************************************/
+
+static int up_attach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+  int ret;
+
+  /* Attach and enable the IRQ */
+
+  ret = irq_attach(priv->irq, up_interrupt, priv);
+  if (ret == OK)
+    {
+      /* Enable the interrupt (RX and TX interrupts are still disabled
+       * in the USART
+       */
+
+       up_enable_irq(priv->irq);
+    }
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_detach
+ *
+ * Description:
+ *   Detach USART interrupts.  This method is called when the serial port is
+ *   closed normally just before the shutdown method is called.  The exception
+ *   is the serial console which is never shutdown.
+ *
+ ****************************************************************************/
+
+static void up_detach(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+  up_disable_irq(priv->irq);
+  irq_detach(priv->irq);
+}
+
+/****************************************************************************
+ * Name: up_interrupt
+ *
+ * Description:
+ *   This is the USART interrupt handler.  It will be invoked when an
+ *   interrupt received on the 'irq'  It should call uart_transmitchars or
+ *   uart_receivechar to perform the appropriate data transfers.  The
+ *   interrupt handling logic must be able to map the 'irq' number into the
+ *   appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int up_interrupt(int irq, void *context, FAR void *arg)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)arg;
+  int  passes;
+  bool handled;
+
+  DEBUGASSERT(priv != NULL);
+
+  /* Report serial activity to the power management logic */
+
+#if defined(CONFIG_PM) && CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY > 0
+  pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY);
+#endif
+
+  /* Loop until there are no characters to be transferred or,
+   * until we have been looping for a long time.
+   */
+
+  handled = true;
+  for (passes = 0; passes < 256 && handled; passes++)
+    {
+      handled = false;
+
+      /* Get the masked USART status word. */
+
+      priv->sr = up_serialin(priv, STM32_USART_ISR_OFFSET);
+
+      /* USART interrupts:
+       *
+       * Enable             Status          Meaning                         Usage
+       * ------------------ --------------- ------------------------------- ----------
+       * USART_CR1_IDLEIE   USART_ISR_IDLE  Idle Line Detected              (not used)
+       * USART_CR1_RXNEIE   USART_ISR_RXNE  Received Data Ready to be Read
+       * "              "   USART_ISR_ORE   Overrun Error Detected
+       * USART_CR1_TCIE     USART_ISR_TC    Transmission Complete           (used only for RS-485)
+       * USART_CR1_TXEIE    USART_ISR_TXE   Transmit Data Register Empty
+       * USART_CR1_PEIE     USART_ISR_PE    Parity Error
+       *
+       * USART_CR2_LBDIE    USART_ISR_LBD   Break Flag                      (not used)
+       * USART_CR3_EIE      USART_ISR_FE    Framing Error
+       * "           "      USART_ISR_NF    Noise Error
+       * "           "      USART_ISR_ORE   Overrun Error Detected
+       * USART_CR3_CTSIE    USART_ISR_CTS   CTS flag                        (not used)
+       *
+       * NOTE: Some of these status bits must be cleared by explicitly writing zero
+       * to the SR register: USART_ISR_CTS, USART_ISR_LBD. Note of those are currently
+       * being used.
+       */
+
+#ifdef HAVE_RS485
+      /* Transmission of whole buffer is over - TC is set, TXEIE is cleared.
+       * Note - this should be first, to have the most recent TC bit value from
+       * SR register - sending data affects TC, but without refresh we will not
+       * know that...
+       */
+
+      if ((priv->sr & USART_ISR_TC) != 0 && (priv->ie & USART_CR1_TCIE) != 0 &&
+          (priv->ie & USART_CR1_TXEIE) == 0)
+        {
+          stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity);
+          up_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE);
+        }
+#endif
+
+      /* Handle incoming, receive bytes. */
+
+      if ((priv->sr & USART_ISR_RXNE) != 0 && (priv->ie & USART_CR1_RXNEIE) != 0)
+        {
+          /* Received data ready... process incoming bytes.  NOTE the check for
+           * RXNEIE:  We cannot call uart_recvchards of RX interrupts are disabled.
+           */
+
+          uart_recvchars(&priv->dev);
+          handled = true;
+        }
+
+      /* We may still have to read from the DR register to clear any pending
+       * error conditions.
+       */
+
+      else if ((priv->sr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE)) != 0)
+        {
+          /* These errors are cleared by writing the corresponding bit to the
+           * interrupt clear register (ICR).
+           */
+
+          up_serialout(priv, STM32_USART_ICR_OFFSET,
+                      (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF));
+        }
+
+      /* Handle outgoing, transmit bytes */
+
+      if ((priv->sr & USART_ISR_TXE) != 0 && (priv->ie & USART_CR1_TXEIE) != 0)
+        {
+          /* Transmit data register empty ... process outgoing bytes */
+
+          uart_xmitchars(&priv->dev);
+          handled = true;
+        }
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_ioctl
+ *
+ * Description:
+ *   All ioctl calls will be routed through this method
+ *
+ ****************************************************************************/
+
+static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \
+    || defined(CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT)
+  struct inode      *inode = filep->f_inode;
+  struct uart_dev_s *dev   = inode->i_private;
+#endif
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT)
+  struct up_dev_s   *priv  = (struct up_dev_s *)dev->priv;
+#endif
+  int                ret    = OK;
+
+  switch (cmd)
+    {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+    case TIOCSERGSTRUCT:
+      {
+        struct up_dev_s *user = (struct up_dev_s *)arg;
+        if (!user)
+          {
+            ret = -EINVAL;
+          }
+        else
+          {
+            memcpy(user, dev, sizeof(struct up_dev_s));
+          }
+      }
+      break;
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_USART_SINGLEWIRE
+    case TIOCSSINGLEWIRE:
+      {
+        uint32_t cr1;
+        uint32_t cr1_ue;
+        irqstate_t flags;
+
+        flags = enter_critical_section();
+
+        /* Get the original state of UE */
+
+        cr1  = up_serialin(priv, STM32_USART_CR1_OFFSET);
+        cr1_ue = cr1 & USART_CR1_UE;
+        cr1 &= ~USART_CR1_UE;
+
+        /* Disable UE, HDSEL can only be written when UE=0 */
+
+        up_serialout(priv, STM32_USART_CR1_OFFSET, cr1);
+
+        /* Change the TX port to be open-drain/push-pull and enable/disable
+         * half-duplex mode.
+         */
+
+        uint32_t cr = up_serialin(priv, STM32_USART_CR3_OFFSET);
+
+        if (arg == SER_SINGLEWIRE_ENABLED)
+          {
+            stm32_configgpio(priv->tx_gpio | GPIO_OPENDRAIN);
+            cr |= USART_CR3_HDSEL;
+          }
+        else
+          {
+            stm32_configgpio(priv->tx_gpio | GPIO_PUSHPULL);
+            cr &= ~USART_CR3_HDSEL;
+          }
+
+        up_serialout(priv, STM32_USART_CR3_OFFSET, cr);
+
+        /* Re-enable UE if appropriate */
+
+        up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue);
+        leave_critical_section(flags);
+      }
+     break;
+#endif
+
+#ifdef CONFIG_SERIAL_TERMIOS
+    case TCGETS:
+      {
+        struct termios *termiosp = (struct termios *)arg;
+
+        if (!termiosp)
+          {
+            ret = -EINVAL;
+            break;
+          }
+
+        cfsetispeed(termiosp, priv->baud);
+
+        /* Note that since we only support 8/9 bit modes and
+         * there is no way to report 9-bit mode, we always claim 8.
+         */
+
+        termiosp->c_cflag =
+          ((priv->parity != 0) ? PARENB : 0) |
+          ((priv->parity == 1) ? PARODD : 0) |
+          ((priv->stopbits2) ? CSTOPB : 0) |
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+          ((priv->oflow) ? CCTS_OFLOW : 0) |
+#endif
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+          ((priv->iflow) ? CRTS_IFLOW : 0) |
+#endif
+          CS8;
+
+        /* TODO: CCTS_IFLOW, CCTS_OFLOW */
+      }
+      break;
+
+    case TCSETS:
+      {
+        struct termios *termiosp = (struct termios *)arg;
+
+        if (!termiosp)
+          {
+            ret = -EINVAL;
+            break;
+          }
+
+        /* Perform some sanity checks before accepting any changes */
+
+        if (((termiosp->c_cflag & CSIZE) != CS8)
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+            || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0))
+#endif
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+            || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0))
+#endif
+           )
+          {
+            ret = -EINVAL;
+            break;
+          }
+
+        if (termiosp->c_cflag & PARENB)
+          {
+            priv->parity = (termiosp->c_cflag & PARODD) ? 1 : 2;
+          }
+        else
+          {
+            priv->parity = 0;
+          }
+
+        priv->stopbits2 = (termiosp->c_cflag & CSTOPB) != 0;
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+        priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0;
+#endif
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+        priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0;
+#endif
+
+        /* Note that since there is no way to request 9-bit mode
+         * and no way to support 5/6/7-bit modes, we ignore them
+         * all here.
+         */
+
+        /* Note that only cfgetispeed is used because we have knowledge
+         * that only one speed is supported.
+         */
+
+        priv->baud = cfgetispeed(termiosp);
+
+        /* Effect the changes immediately - note that we do not implement
+         * TCSADRAIN / TCSAFLUSH
+         */
+
+        up_set_format(dev);
+      }
+      break;
+#endif /* CONFIG_SERIAL_TERMIOS */
+
+#ifdef CONFIG_STM32F0L0G0_USART_BREAKS
+#  ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT
+    case TIOCSBRK:  /* BSD compatibility: Turn break on, unconditionally */
+      {
+        irqstate_t flags;
+        uint32_t tx_break;
+
+        flags = enter_critical_section();
+
+        /* Disable any further tx activity */
+
+        priv->ie |= USART_CR1_IE_BREAK_INPROGRESS;
+
+        up_txint(dev, false);
+
+        /* Configure TX as a GPIO output pin and Send a break signal*/
+
+        tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK|GPIO_OUTPUT_SET) & priv->tx_gpio);
+        stm32_configgpio(tx_break);
+
+        leave_critical_section(flags);
+      }
+      break;
+
+    case TIOCCBRK:  /* BSD compatibility: Turn break off, unconditionally */
+      {
+        irqstate_t flags;
+
+        flags = enter_critical_section();
+
+        /* Configure TX back to U(S)ART */
+
+        stm32_configgpio(priv->tx_gpio);
+
+        priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS;
+
+        /* Enable further tx activity */
+
+        up_txint(dev, true);
+
+        leave_critical_section(flags);
+      }
+      break;
+#  else
+    case TIOCSBRK:  /* No BSD compatibility: Turn break on for M bit times */
+      {
+        uint32_t cr1;
+        irqstate_t flags;
+
+        flags = enter_critical_section();
+        cr1   = up_serialin(priv, STM32_USART_CR1_OFFSET);
+        up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK);
+        leave_critical_section(flags);
+      }
+      break;
+
+    case TIOCCBRK:  /* No BSD compatibility: May turn off break too soon */
+      {
+        uint32_t cr1;
+        irqstate_t flags;
+
+        flags = enter_critical_section();
+        cr1   = up_serialin(priv, STM32_USART_CR1_OFFSET);
+        up_serialout(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK);
+        leave_critical_section(flags);
+      }
+      break;
+#  endif
+#endif
+
+    default:
+      ret = -ENOTTY;
+      break;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: up_receive
+ *
+ * Description:
+ *   Called (usually) from the interrupt level to receive one
+ *   character from the USART.  Error bits associated with the
+ *   receipt are provided in the return 'status'.
+ *
+ ****************************************************************************/
+
+static int up_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+  uint32_t rdr;
+
+  /* Get the Rx byte */
+
+  rdr      = up_serialin(priv, STM32_USART_RDR_OFFSET);
+
+  /* Get the Rx byte plux error information.  Return those in status */
+
+  *status  = priv->sr << 16 | rdr;
+  priv->sr = 0;
+
+  /* Then return the actual received byte */
+
+  return rdr & 0xff;
+}
+
+/****************************************************************************
+ * Name: up_rxint
+ *
+ * Description:
+ *   Call to enable or disable RX interrupts
+ *
+ ****************************************************************************/
+
+static void up_rxint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+  irqstate_t flags;
+  uint16_t ie;
+
+  /* USART receive interrupts:
+   *
+   * Enable             Status          Meaning                         Usage
+   * ------------------ --------------- ------------------------------- ----------
+   * USART_CR1_IDLEIE   USART_ISR_IDLE  Idle Line Detected              (not used)
+   * USART_CR1_RXNEIE   USART_ISR_RXNE  Received Data Ready to be Read
+   * "              "   USART_ISR_ORE   Overrun Error Detected
+   * USART_CR1_PEIE     USART_ISR_PE    Parity Error
+   *
+   * USART_CR2_LBDIE    USART_ISR_LBD   Break Flag                      (not used)
+   * USART_CR3_EIE      USART_ISR_FE    Framing Error
+   * "           "      USART_ISR_NF    Noise Error
+   * "           "      USART_ISR_ORE   Overrun Error Detected
+   */
+
+  flags = enter_critical_section();
+  ie = priv->ie;
+  if (enable)
+    {
+      /* Receive an interrupt when their is anything in the Rx data register (or an Rx
+       * timeout occurs).
+       */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+#ifdef CONFIG_USART_ERRINTS
+      ie |= (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE);
+#else
+      ie |= USART_CR1_RXNEIE;
+#endif
+#endif
+    }
+  else
+    {
+      ie &= ~(USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR3_EIE);
+    }
+
+  /* Then set the new interrupt state */
+
+  up_restoreusartint(priv, ie);
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: up_rxavailable
+ *
+ * Description:
+ *   Return true if the receive register is not empty
+ *
+ ****************************************************************************/
+
+static bool up_rxavailable(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+  return ((up_serialin(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0);
+}
+
+/****************************************************************************
+ * Name: up_rxflowcontrol
+ *
+ * Description:
+ *   Called when Rx buffer is full (or exceeds configured watermark levels
+ *   if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined).
+ *   Return true if UART activated RX flow control to block more incoming
+ *   data
+ *
+ * Input Parameters:
+ *   dev       - UART device instance
+ *   nbuffered - the number of characters currently buffered
+ *               (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is
+ *               not defined the value will be 0 for an empty buffer or the
+ *               defined buffer size for a full buffer)
+ *   upper     - true indicates the upper watermark was crossed where
+ *               false indicates the lower watermark has been crossed
+ *
+ * Returned Value:
+ *   true if RX flow control activated.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool up_rxflowcontrol(struct uart_dev_s *dev,
+                             unsigned int nbuffered, bool upper)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \
+    defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN)
+  if (priv->iflow && (priv->rts_gpio != 0))
+    {
+      /* Assert/de-assert nRTS set it high resume/stop sending */
+
+      stm32_gpiowrite(priv->rts_gpio, upper);
+
+      if (upper)
+        {
+          /* With heavy Rx traffic, RXNE might be set and data pending.
+           * Returning 'true' in such case would cause RXNE left unhandled
+           * and causing interrupt storm. Sending end might be also be slow
+           * to react on nRTS, and returning 'true' here would prevent
+           * processing that data.
+           *
+           * Therefore, return 'false' so input data is still being processed
+           * until sending end reacts on nRTS signal and stops sending more.
+           */
+
+          return false;
+        }
+
+      return upper;
+    }
+
+#else
+  if (priv->iflow)
+    {
+      /* Is the RX buffer full? */
+
+      if (upper)
+        {
+          /* Disable Rx interrupt to prevent more data being from
+           * peripheral.  When hardware RTS is enabled, this will
+           * prevent more data from coming in.
+           *
+           * This function is only called when UART recv buffer is full,
+           * that is: "dev->recv.head + 1 == dev->recv.tail".
+           *
+           * Logic in "uart_read" will automatically toggle Rx interrupts
+           * when buffer is read empty and thus we do not have to re-
+           * enable Rx interrupts.
+           */
+
+          uart_disablerxint(dev);
+          return true;
+        }
+
+      /* No.. The RX buffer is empty */
+
+      else
+        {
+          /* We might leave Rx interrupt disabled if full recv buffer was
+           * read empty.  Enable Rx interrupt to make sure that more input is
+           * received.
+           */
+
+          uart_enablerxint(dev);
+        }
+    }
+#endif
+
+  return false;
+}
+#endif
+
+/****************************************************************************
+ * Name: up_send
+ *
+ * Description:
+ *   This method will send one byte on the USART
+ *
+ ****************************************************************************/
+
+static void up_send(struct uart_dev_s *dev, int ch)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+#ifdef HAVE_RS485
+  if (priv->rs485_dir_gpio != 0)
+    {
+      stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity);
+    }
+#endif
+
+  up_serialout(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch);
+}
+
+/****************************************************************************
+ * Name: up_txint
+ *
+ * Description:
+ *   Call to enable or disable TX interrupts
+ *
+ ****************************************************************************/
+
+static void up_txint(struct uart_dev_s *dev, bool enable)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+  irqstate_t flags;
+
+  /* USART transmit interrupts:
+   *
+   * Enable             Status          Meaning                      Usage
+   * ------------------ --------------- ---------------------------- ----------
+   * USART_CR1_TCIE     USART_ISR_TC    Transmission Complete        (used only for RS-485)
+   * USART_CR1_TXEIE    USART_ISR_TXE   Transmit Data Register Empty
+   * USART_CR3_CTSIE    USART_ISR_CTS   CTS flag                     (not used)
+   */
+
+  flags = enter_critical_section();
+  if (enable)
+    {
+      /* Set to receive an interrupt when the TX data register is empty */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+      uint16_t ie = priv->ie | USART_CR1_TXEIE;
+
+      /* If RS-485 is supported on this U[S]ART, then also enable the
+       * transmission complete interrupt.
+       */
+
+#  ifdef HAVE_RS485
+      if (priv->rs485_dir_gpio != 0)
+        {
+          ie |= USART_CR1_TCIE;
+        }
+#  endif
+
+#  ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT
+      if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS)
+        {
+          return;
+        }
+#  endif
+
+      up_restoreusartint(priv, ie);
+
+      /* Fake a TX interrupt here by just calling uart_xmitchars() with
+       * interrupts disabled (note this may recurse).
+       */
+
+      uart_xmitchars(dev);
+#endif
+    }
+  else
+    {
+      /* Disable the TX interrupt */
+
+      up_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE);
+    }
+
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: up_txready
+ *
+ * Description:
+ *   Return true if the transmit data register is empty
+ *
+ ****************************************************************************/
+
+static bool up_txready(struct uart_dev_s *dev)
+{
+  struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+  return ((up_serialin(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0);
+}
+
+/****************************************************************************
+ * Name: up_pm_notify
+ *
+ * Description:
+ *   Notify the driver of new power state. This callback is  called after
+ *   all drivers have had the opportunity to prepare for the new power state.
+ *
+ * Input Parameters:
+ *
+ *    cb - Returned to the driver. The driver version of the callback
+ *         structure may include additional, driver-specific state data at
+ *         the end of the structure.
+ *
+ *    pmstate - Identifies the new PM state
+ *
+ * Returned Value:
+ *   None - The driver already agreed to transition to the low power
+ *   consumption state when when it returned OK to the prepare() call.
+ *
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+static void up_pm_notify(struct pm_callback_s *cb, int domain,
+                         enum pm_state_e pmstate)
+{
+  switch (pmstate)
+    {
+      case(PM_NORMAL):
+        {
+          /* Logic for PM_NORMAL goes here */
+
+        }
+        break;
+
+      case(PM_IDLE):
+        {
+          /* Logic for PM_IDLE goes here */
+
+        }
+        break;
+
+      case(PM_STANDBY):
+        {
+          /* Logic for PM_STANDBY goes here */
+
+        }
+        break;
+
+      case(PM_SLEEP):
+        {
+          /* Logic for PM_SLEEP goes here */
+
+        }
+        break;
+
+      default:
+        /* Should not get here */
+        break;
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: up_pm_prepare
+ *
+ * Description:
+ *   Request the driver to prepare for a new power state. This is a warning
+ *   that the system is about to enter into a new power state. The driver
+ *   should begin whatever operations that may be required to enter power
+ *   state. The driver may abort the state change mode by returning a
+ *   non-zero value from the callback function.
+ *
+ * Input Parameters:
+ *
+ *    cb - Returned to the driver. The driver version of the callback
+ *         structure may include additional, driver-specific state data at
+ *         the end of the structure.
+ *
+ *    pmstate - Identifies the new PM state
+ *
+ * Returned Value:
+ *   Zero - (OK) means the event was successfully processed and that the
+ *          driver is prepared for the PM state change.
+ *
+ *   Non-zero - means that the driver is not prepared to perform the tasks
+ *              needed achieve this power setting and will cause the state
+ *              change to be aborted. NOTE: The prepare() method will also
+ *              be called when reverting from lower back to higher power
+ *              consumption modes (say because another driver refused a
+ *              lower power state change). Drivers are not permitted to
+ *              return non-zero values when reverting back to higher power
+ *              consumption modes!
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+static int up_pm_prepare(struct pm_callback_s *cb, int domain,
+                         enum pm_state_e pmstate)
+{
+  /* Logic to prepare for a reduced power state goes here. */
+
+  return OK;
+}
+#endif
+#endif /* HAVE_UART */
+#endif /* USE_SERIALDRIVER */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef USE_SERIALDRIVER
+
+/****************************************************************************
+ * Name: stm32_serial_get_uart
+ *
+ * Description:
+ *   Get serial driver structure for STM32 USART
+ *
+ ****************************************************************************/
+
+FAR uart_dev_t *stm32_serial_get_uart(int uart_num)
+{
+  int uart_idx = uart_num - 1;
+
+  if (uart_idx < 0 || uart_idx >= STM32_NSERIAL || !g_uart_devs[uart_idx])
+    {
+      return NULL;
+    }
+
+  if (!g_uart_devs[uart_idx]->initialized)
+    {
+      return NULL;
+    }
+
+  return &g_uart_devs[uart_idx]->dev;
+}
+
+/****************************************************************************
+ * Name: up_earlyserialinit
+ *
+ * Description:
+ *   Performs the low level USART initialization early in debug so that the
+ *   serial console will be available during bootup.  This must be called
+ *   before up_serialinit.
+ *
+ ****************************************************************************/
+
+#ifdef USE_EARLYSERIALINIT
+void up_earlyserialinit(void)
+{
+#ifdef HAVE_UART
+  unsigned i;
+
+  /* Disable all USART interrupts */
+
+  for (i = 0; i < STM32_NSERIAL; i++)
+    {
+      if (g_uart_devs[i])
+        {
+          up_disableusartint(g_uart_devs[i], NULL);
+        }
+    }
+
+  /* Configure whichever one is the console */
+
+#if CONSOLE_USART > 0
+  up_setup(&g_uart_devs[CONSOLE_USART - 1]->dev);
+#endif
+#endif /* HAVE UART */
+}
+#endif
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ *   Register serial console and serial ports.  This assumes
+ *   that up_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+void up_serialinit(void)
+{
+#ifdef HAVE_UART
+  char devname[16];
+  unsigned i;
+  unsigned minor = 0;
+#ifdef CONFIG_PM
+  int ret;
+#endif
+
+  /* Register to receive power management callbacks */
+
+#ifdef CONFIG_PM
+  ret = pm_register(&g_serialcb);
+  DEBUGASSERT(ret == OK);
+  UNUSED(ret);
+#endif
+
+  /* Register the console */
+
+#if CONSOLE_USART > 0
+  (void)uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev);
+
+#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING
+  /* If not disabled, register the console UART to ttyS0 and exclude
+   * it from initializing it further down
+   */
+
+  (void)uart_register("/dev/ttyS0", &g_uart_devs[CONSOLE_USART - 1]->dev);
+  minor = 1;
+#endif
+
+#endif /* CONSOLE_USART > 0 */
+
+  /* Register all remaining USARTs */
+
+  strcpy(devname, "/dev/ttySx");
+
+  for (i = 0; i < STM32_NSERIAL; i++)
+    {
+      /* Don't create a device for non-configured ports. */
+
+      if (g_uart_devs[i] == 0)
+        {
+          continue;
+        }
+
+#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING
+      /* Don't create a device for the console - we did that above */
+
+      if (g_uart_devs[i]->dev.isconsole)
+        {
+          continue;
+        }
+#endif
+
+      /* Register USARTs as devices in increasing order */
+
+      devname[9] = '0' + minor++;
+      (void)uart_register(devname, &g_uart_devs[i]->dev);
+    }
+#endif /* HAVE UART */
+}
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug  writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#if CONSOLE_USART > 0
+  struct up_dev_s *priv = g_uart_devs[CONSOLE_USART - 1];
+  uint16_t ie;
+
+  up_disableusartint(priv, &ie);
+
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_lowputc('\r');
+    }
+
+  up_lowputc(ch);
+  up_restoreusartint(priv, ie);
+
+#endif
+  return ch;
+}
+
+#else /* USE_SERIALDRIVER */
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ *   Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#if CONSOLE_USART > 0
+  /* Check for LF */
+
+  if (ch == '\n')
+    {
+      /* Add CR */
+
+      up_lowputc('\r');
+    }
+
+  up_lowputc(ch);
+#endif
+  return ch;
+}
+
+#endif /* USE_SERIALDRIVER */
diff --git a/arch/arm/src/stm32f0l0/stm32_spi.c b/arch/arm/src/stm32f0l0g0/stm32_spi.c
similarity index 97%
rename from arch/arm/src/stm32f0l0/stm32_spi.c
rename to arch/arm/src/stm32f0l0g0/stm32_spi.c
index 779ec0f62aa..bd62655e19a 100644
--- a/arch/arm/src/stm32f0l0/stm32_spi.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_spi.c
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/stm32_spi.c
+ * arch/arm/src/stm32f0l0g0/stm32_spi.c
  * copied from arch/arm/src/stm32
  *
  *   Copyright (C) 2009-2013, 2016 Gregory Nutt. All rights reserved.
@@ -93,7 +93,7 @@
 
 #include 
 
-#ifdef CONFIG_STM32F0L0_SPI
+#ifdef CONFIG_STM32F0L0G0_SPI
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -102,19 +102,19 @@
 /* Configuration ********************************************************************/
 /* SPI interrupts */
 
-#ifdef CONFIG_STM32F0L0_SPI_INTERRUPTS
+#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
 #  error "Interrupt driven SPI not yet supported"
 #endif
 
 /* Can't have both interrupt driven SPI and SPI DMA */
 
-#if defined(CONFIG_STM32F0L0_SPI_INTERRUPTS) && defined(CONFIG_STM32F0L0_SPI_DMA)
+#if defined(CONFIG_STM32F0L0G0_SPI_INTERRUPTS) && defined(CONFIG_STM32F0L0G0_SPI_DMA)
 #  error "Cannot enable both interrupt mode and DMA mode for SPI"
 #endif
 
 /* SPI DMA priority */
 
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
 
 #  if defined(CONFIG_SPI_DMAPRIO)
 #    define SPI_DMA_PRIO  CONFIG_SPI_DMAPRIO
@@ -148,10 +148,10 @@ struct stm32_spidev_s
   struct spi_dev_s spidev;       /* Externally visible part of the SPI interface */
   uint32_t         spibase;      /* SPIn base address */
   uint32_t         spiclock;     /* Clocking for the SPI module */
-#ifdef CONFIG_STM32F0L0_SPI_INTERRUPTS
+#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
   uint8_t          spiirq;       /* SPI IRQ number */
 #endif
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
   volatile uint8_t rxresult;     /* Result of the RX DMA */
   volatile uint8_t txresult;     /* Result of the RX DMA */
 #ifdef CONFIG_SPI_TRIGGER
@@ -193,7 +193,7 @@ static inline bool spi_16bitmode(FAR struct stm32_spidev_s *priv);
 
 /* DMA support */
 
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
 static void        spi_dmarxwait(FAR struct stm32_spidev_s *priv);
 static void        spi_dmatxwait(FAR struct stm32_spidev_s *priv);
 static inline void spi_dmarxwakeup(FAR struct stm32_spidev_s *priv);
@@ -246,7 +246,7 @@ static int         spi_pm_prepare(FAR struct pm_callback_s *cb, int domain,
  * Private Data
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI1
+#ifdef CONFIG_STM32F0L0G0_SPI1
 static const struct spi_ops_s g_spi1ops =
 {
   .lock              = spi_lock,
@@ -283,10 +283,10 @@ static struct stm32_spidev_s g_spi1dev =
   .spidev   = { &g_spi1ops },
   .spibase  = STM32_SPI1_BASE,
   .spiclock = STM32_PCLK2_FREQUENCY,
-#ifdef CONFIG_STM32F0L0_SPI_INTERRUPTS
+#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
   .spiirq   = STM32_IRQ_SPI1,
 #endif
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
   /* lines must be configured in board.h */
   .rxch     = DMACHAN_SPI1_RX,
   .txch     = DMACHAN_SPI1_TX,
@@ -297,7 +297,7 @@ static struct stm32_spidev_s g_spi1dev =
 };
 #endif
 
-#ifdef CONFIG_STM32F0L0_SPI2
+#ifdef CONFIG_STM32F0L0G0_SPI2
 static const struct spi_ops_s g_spi2ops =
 {
   .lock              = spi_lock,
@@ -334,10 +334,10 @@ static struct stm32_spidev_s g_spi2dev =
   .spidev   = { &g_spi2ops },
   .spibase  = STM32_SPI2_BASE,
   .spiclock = STM32_PCLK1_FREQUENCY,
-#ifdef CONFIG_STM32F0L0_SPI_INTERRUPTS
+#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS
   .spiirq   = STM32_IRQ_SPI2,
 #endif
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
   .rxch     = DMACHAN_SPI2_RX,
   .txch     = DMACHAN_SPI2_TX,
 #endif
@@ -567,7 +567,7 @@ static inline bool spi_16bitmode(FAR struct stm32_spidev_s *priv)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
 static void spi_dmarxwait(FAR struct stm32_spidev_s *priv)
 {
   int ret;
@@ -598,7 +598,7 @@ static void spi_dmarxwait(FAR struct stm32_spidev_s *priv)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
 static void spi_dmatxwait(FAR struct stm32_spidev_s *priv)
 {
   int ret;
@@ -629,7 +629,7 @@ static void spi_dmatxwait(FAR struct stm32_spidev_s *priv)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
 static inline void spi_dmarxwakeup(FAR struct stm32_spidev_s *priv)
 {
   (void)nxsem_post(&priv->rxsem);
@@ -644,7 +644,7 @@ static inline void spi_dmarxwakeup(FAR struct stm32_spidev_s *priv)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
 static inline void spi_dmatxwakeup(FAR struct stm32_spidev_s *priv)
 {
   (void)nxsem_post(&priv->txsem);
@@ -659,7 +659,7 @@ static inline void spi_dmatxwakeup(FAR struct stm32_spidev_s *priv)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
 static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
 {
   FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)arg;
@@ -679,7 +679,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
 static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
 {
   FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)arg;
@@ -699,7 +699,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
 static void spi_dmarxsetup(FAR struct stm32_spidev_s *priv, FAR void *rxbuffer,
                            FAR void *rxdummy, size_t nwords)
 {
@@ -749,7 +749,7 @@ static void spi_dmarxsetup(FAR struct stm32_spidev_s *priv, FAR void *rxbuffer,
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
 static void spi_dmatxsetup(FAR struct stm32_spidev_s *priv, FAR const void *txbuffer,
                            FAR const void *txdummy, size_t nwords)
 {
@@ -799,7 +799,7 @@ static void spi_dmatxsetup(FAR struct stm32_spidev_s *priv, FAR const void *txbu
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
 static inline void spi_dmarxstart(FAR struct stm32_spidev_s *priv)
 {
   priv->rxresult = 0;
@@ -815,7 +815,7 @@ static inline void spi_dmarxstart(FAR struct stm32_spidev_s *priv)
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
 static inline void spi_dmatxstart(FAR struct stm32_spidev_s *priv)
 {
   priv->txresult = 0;
@@ -1285,8 +1285,8 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
  *
  ************************************************************************************/
 
-#if !defined(CONFIG_STM32F0L0_SPI_DMA) || defined(CONFIG_STM32F0L0_DMACAPABLE)
-#if !defined(CONFIG_STM32F0L0_SPI_DMA)
+#if !defined(CONFIG_STM32F0L0G0_SPI_DMA) || defined(CONFIG_STM32F0L0G0_DMACAPABLE)
+#if !defined(CONFIG_STM32F0L0G0_SPI_DMA)
 static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
                          FAR void *rxbuffer, size_t nwords)
 #else
@@ -1368,7 +1368,7 @@ static void spi_exchange_nodma(FAR struct spi_dev_s *dev, FAR const void *txbuff
         }
     }
 }
-#endif /* !CONFIG_STM32F0L0_SPI_DMA || CONFIG_STM32F0L0_DMACAPABLE */
+#endif /* !CONFIG_STM32F0L0G0_SPI_DMA || CONFIG_STM32F0L0G0_DMACAPABLE */
 
 /****************************************************************************
  * Name: spi_exchange (with DMA capability)
@@ -1390,13 +1390,13 @@ static void spi_exchange_nodma(FAR struct spi_dev_s *dev, FAR const void *txbuff
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
 static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
                          FAR void *rxbuffer, size_t nwords)
 {
   FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev;
 
-#ifdef CONFIG_STM32F0L0_DMACAPABLE
+#ifdef CONFIG_STM32F0L0G0_DMACAPABLE
   if ((txbuffer && !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) ||
       (rxbuffer && !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr)))
     {
@@ -1451,7 +1451,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
 #endif
     }
 }
-#endif /* CONFIG_STM32F0L0_SPI_DMA */
+#endif /* CONFIG_STM32F0L0G0_SPI_DMA */
 
 /****************************************************************************
  * Name: spi_trigger
@@ -1472,7 +1472,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
 #ifdef CONFIG_SPI_TRIGGER
 static int spi_trigger(FAR struct spi_dev_s *dev)
 {
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
   FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)dev;
 
   if (!priv->trigarmed)
@@ -1691,7 +1691,7 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv)
 
   nxsem_init(&priv->exclsem, 0, 1);
 
-#ifdef CONFIG_STM32F0L0_SPI_DMA
+#ifdef CONFIG_STM32F0L0G0_SPI_DMA
   /* Initialize the SPI semaphores that is used to wait for DMA completion */
 
   nxsem_init(&priv->rxsem, 0, 0);
@@ -1756,7 +1756,7 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus)
 
   irqstate_t flags = enter_critical_section();
 
-#ifdef CONFIG_STM32F0L0_SPI1
+#ifdef CONFIG_STM32F0L0G0_SPI1
   if (bus == 1)
     {
       /* Select SPI1 */
@@ -1781,7 +1781,7 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus)
     }
   else
 #endif
-#ifdef CONFIG_STM32F0L0_SPI2
+#ifdef CONFIG_STM32F0L0G0_SPI2
   if (bus == 2)
     {
       /* Select SPI2 */
@@ -1815,4 +1815,4 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus)
   return (FAR struct spi_dev_s *)priv;
 }
 
-#endif /* CONFIG_STM32F0L0_SPI */
+#endif /* CONFIG_STM32F0L0G0_SPI */
diff --git a/arch/arm/src/stm32f0l0/stm32_spi.h b/arch/arm/src/stm32f0l0g0/stm32_spi.h
similarity index 97%
rename from arch/arm/src/stm32f0l0/stm32_spi.h
rename to arch/arm/src/stm32f0l0g0/stm32_spi.h
index b9d84b82a34..5e0f5100a1a 100644
--- a/arch/arm/src/stm32f0l0/stm32_spi.h
+++ b/arch/arm/src/stm32f0l0g0/stm32_spi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/stm32_spi.h
+ * arch/arm/src/stm32f0l0g0/stm32_spi.h
  *
  *   Copyright (C) 2009, 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -115,13 +115,13 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI1
+#ifdef CONFIG_STM32F0L0G0_SPI1
 void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
 uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid);
 int stm32_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
 #endif
 
-#ifdef CONFIG_STM32F0L0_SPI2
+#ifdef CONFIG_STM32F0L0G0_SPI2
 void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
 uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid);
 int stm32_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
@@ -148,12 +148,12 @@ int stm32_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
  ****************************************************************************/
 
 #ifdef CONFIG_SPI_CALLBACK
-#ifdef CONFIG_STM32F0L0_SPI1
+#ifdef CONFIG_STM32F0L0G0_SPI1
 int stm32_spi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
                        FAR void *arg);
 #endif
 
-#ifdef CONFIG_STM32F0L0_SPI2
+#ifdef CONFIG_STM32F0L0G0_SPI2
 int stm32_spi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
                        FAR void *arg);
 #endif
diff --git a/arch/arm/src/stm32f0l0/stm32_start.c b/arch/arm/src/stm32f0l0g0/stm32_start.c
similarity index 99%
rename from arch/arm/src/stm32f0l0/stm32_start.c
rename to arch/arm/src/stm32f0l0g0/stm32_start.c
index b2176ef1875..457defaa5a0 100644
--- a/arch/arm/src/stm32f0l0/stm32_start.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_start.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f0l0/stm32_start.c
+ * arch/arm/src/stm32f0l0g0/stm32_start.c
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
diff --git a/arch/arm/src/stm32f0l0/stm32_start.h b/arch/arm/src/stm32f0l0g0/stm32_start.h
similarity index 93%
rename from arch/arm/src/stm32f0l0/stm32_start.h
rename to arch/arm/src/stm32f0l0g0/stm32_start.h
index 73087cbe3f7..e3692311224 100644
--- a/arch/arm/src/stm32f0l0/stm32_start.h
+++ b/arch/arm/src/stm32f0l0g0/stm32_start.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/stm32_start.h
+ * arch/arm/src/stm32f0l0g0/stm32_start.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_START_H
-#define __ARCH_ARM_SRC_STM32F0L0_STM32_START_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H
 
 /************************************************************************************
  * Included Files
@@ -73,4 +73,4 @@ void stm32_boardinitialize(void);
 #endif
 #endif /* __ASSEMBLY__ */
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_START_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H */
diff --git a/arch/arm/src/stm32f0l0/stm32_timerisr.c b/arch/arm/src/stm32f0l0g0/stm32_timerisr.c
similarity index 96%
rename from arch/arm/src/stm32f0l0/stm32_timerisr.c
rename to arch/arm/src/stm32f0l0g0/stm32_timerisr.c
index 0007fb48340..f4bddc4ef11 100644
--- a/arch/arm/src/stm32f0l0/stm32_timerisr.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_timerisr.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f0l0/stm32_timerisr.c
+ * arch/arm/src/stm32f0l0g0/stm32_timerisr.c
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -62,9 +62,9 @@
  * (when CLKSOURCE = 0). ..."
  */
 
-#if defined(CONFIG_STM32F0L0_SYSTICK_CORECLK)
+#if defined(CONFIG_STM32F0L0G0_SYSTICK_CORECLK)
 #  define SYSTICK_CLOCK STM32_SYSCLK_FREQUENCY        /* Core clock */
-#elif defined(CONFIG_STM32F0L0_SYSTICK_CORECLK_DIV16)
+#elif defined(CONFIG_STM32F0L0G0_SYSTICK_CORECLK_DIV16)
 #  define SYSTICK_CLOCK (STM32_SYSCLK_FREQUENCY / 16) /* Core clock divided by 16 */
 #endif
 
@@ -152,7 +152,7 @@ void arm_timer_initialize(void)
    * a divide-by-16 of the core clock (when CLKSOURCE = 0). ..."
    */
 
-#ifdef CONFIG_STM32F0L0_SYSTICK_CORECLK
+#ifdef CONFIG_STM32F0L0G0_SYSTICK_CORECLK
   putreg32((SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE),
            ARMV6M_SYSTICK_CSR);
 #else
diff --git a/arch/arm/src/stm32f0l0/stm32_uart.h b/arch/arm/src/stm32f0l0g0/stm32_uart.h
similarity index 60%
rename from arch/arm/src/stm32f0l0/stm32_uart.h
rename to arch/arm/src/stm32f0l0g0/stm32_uart.h
index 823b2cdc468..ea83905a417 100644
--- a/arch/arm/src/stm32f0l0/stm32_uart.h
+++ b/arch/arm/src/stm32f0l0g0/stm32_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/stm32_uart.h
+ * arch/arm/src/stm32f0l0g0/stm32_uart.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_UART_H
-#define __ARCH_ARM_SRC_STM32F0L0_STM32_UART_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H
 
 /************************************************************************************
  * Included Files
@@ -54,29 +54,29 @@
  * device.
  */
 
-#if STM32_NUSART < 8 || !defined(CONFIG_STM32F0L0_HAVE_USART8)
-#  undef CONFIG_STM32F0L0_USART8
+#if STM32_NUSART < 8 || !defined(CONFIG_STM32F0L0G0_HAVE_USART8)
+#  undef CONFIG_STM32F0L0G0_USART8
 #endif
-#if STM32_NUSART < 7 || !defined(CONFIG_STM32F0L0_HAVE_USART7)
-#  undef CONFIG_STM32F0L0_USART7
+#if STM32_NUSART < 7 || !defined(CONFIG_STM32F0L0G0_HAVE_USART7)
+#  undef CONFIG_STM32F0L0G0_USART7
 #endif
-#if STM32_NUSART < 6 || !defined(CONFIG_STM32F0L0_HAVE_USART6)
-#  undef CONFIG_STM32F0L0_USART6
+#if STM32_NUSART < 6 || !defined(CONFIG_STM32F0L0G0_HAVE_USART6)
+#  undef CONFIG_STM32F0L0G0_USART6
 #endif
-#if STM32_NUSART < 5 || !defined(CONFIG_STM32F0L0_HAVE_USART5)
-#  undef CONFIG_STM32F0L0_USART5
+#if STM32_NUSART < 5 || !defined(CONFIG_STM32F0L0G0_HAVE_USART5)
+#  undef CONFIG_STM32F0L0G0_USART5
 #endif
-#if STM32_NUSART < 4 || !defined(CONFIG_STM32F0L0_HAVE_USART4)
-#  undef CONFIG_STM32F0L0_USART4
+#if STM32_NUSART < 4 || !defined(CONFIG_STM32F0L0G0_HAVE_USART4)
+#  undef CONFIG_STM32F0L0G0_USART4
 #endif
-#if STM32_NUSART < 3 || !defined(CONFIG_STM32F0L0_HAVE_USART3)
-#  undef CONFIG_STM32F0L0_USART3
+#if STM32_NUSART < 3 || !defined(CONFIG_STM32F0L0G0_HAVE_USART3)
+#  undef CONFIG_STM32F0L0G0_USART3
 #endif
 #if STM32_NUSART < 2
-#  undef CONFIG_STM32F0L0_USART2
+#  undef CONFIG_STM32F0L0G0_USART2
 #endif
 #if STM32_NUSART < 1
-#  undef CONFIG_STM32F0L0_USART1
+#  undef CONFIG_STM32F0L0G0_USART1
 #endif
 
 /* USART 3-8 are multiplexed to the same interrupt.  Current interrupt
@@ -85,128 +85,128 @@
  * issue in the future.
  */
 
-#if defined(CONFIG_STM32F0L0_USART3)
-#  undef CONFIG_STM32F0L0_USART4
-#  undef CONFIG_STM32F0L0_USART5
-#  undef CONFIG_STM32F0L0_USART6
-#  undef CONFIG_STM32F0L0_USART7
-#  undef CONFIG_STM32F0L0_USART8
-#elif defined(CONFIG_STM32F0L0_USART4)
-#  undef CONFIG_STM32F0L0_USART5
-#  undef CONFIG_STM32F0L0_USART6
-#  undef CONFIG_STM32F0L0_USART7
-#  undef CONFIG_STM32F0L0_USART8
-#elif defined(CONFIG_STM32F0L0_USART5)
-#  undef CONFIG_STM32F0L0_USART6
-#  undef CONFIG_STM32F0L0_USART7
-#  undef CONFIG_STM32F0L0_USART8
-#elif defined(CONFIG_STM32F0L0_USART6)
-#  undef CONFIG_STM32F0L0_USART7
-#  undef CONFIG_STM32F0L0_USART8
-#elif defined(CONFIG_STM32F0L0_USART7)
-#  undef CONFIG_STM32F0L0_USART8
+#if defined(CONFIG_STM32F0L0G0_USART3)
+#  undef CONFIG_STM32F0L0G0_USART4
+#  undef CONFIG_STM32F0L0G0_USART5
+#  undef CONFIG_STM32F0L0G0_USART6
+#  undef CONFIG_STM32F0L0G0_USART7
+#  undef CONFIG_STM32F0L0G0_USART8
+#elif defined(CONFIG_STM32F0L0G0_USART4)
+#  undef CONFIG_STM32F0L0G0_USART5
+#  undef CONFIG_STM32F0L0G0_USART6
+#  undef CONFIG_STM32F0L0G0_USART7
+#  undef CONFIG_STM32F0L0G0_USART8
+#elif defined(CONFIG_STM32F0L0G0_USART5)
+#  undef CONFIG_STM32F0L0G0_USART6
+#  undef CONFIG_STM32F0L0G0_USART7
+#  undef CONFIG_STM32F0L0G0_USART8
+#elif defined(CONFIG_STM32F0L0G0_USART6)
+#  undef CONFIG_STM32F0L0G0_USART7
+#  undef CONFIG_STM32F0L0G0_USART8
+#elif defined(CONFIG_STM32F0L0G0_USART7)
+#  undef CONFIG_STM32F0L0G0_USART8
 #endif
 
 /* Is there a USART enabled? */
 
-#if defined(CONFIG_STM32F0L0_USART1) || defined(CONFIG_STM32F0L0_USART2) || \
-    defined(CONFIG_STM32F0L0_USART3) || defined(CONFIG_STM32F0L0_USART4) || \
-    defined(CONFIG_STM32F0L0_USART5) || defined(CONFIG_STM32F0L0_USART6) || \
-    defined(CONFIG_STM32F0L0_USART7) || defined(CONFIG_STM32F0L0_USART8)
+#if defined(CONFIG_STM32F0L0G0_USART1) || defined(CONFIG_STM32F0L0G0_USART2) || \
+    defined(CONFIG_STM32F0L0G0_USART3) || defined(CONFIG_STM32F0L0G0_USART4) || \
+    defined(CONFIG_STM32F0L0G0_USART5) || defined(CONFIG_STM32F0L0G0_USART6) || \
+    defined(CONFIG_STM32F0L0G0_USART7) || defined(CONFIG_STM32F0L0G0_USART8)
 #  define HAVE_USART 1
 #endif
 
 /* Sanity checks */
 
-#if !defined(CONFIG_STM32F0L0_USART1)
-#  undef CONFIG_STM32F0L0_USART1_SERIALDRIVER
-#  undef CONFIG_STM32F0L0_USART1_1WIREDRIVER
+#if !defined(CONFIG_STM32F0L0G0_USART1)
+#  undef CONFIG_STM32F0L0G0_USART1_SERIALDRIVER
+#  undef CONFIG_STM32F0L0G0_USART1_1WIREDRIVER
 #endif
-#if !defined(CONFIG_STM32F0L0_USART2)
-#  undef CONFIG_STM32F0L0_USART2_SERIALDRIVER
-#  undef CONFIG_STM32F0L0_USART2_1WIREDRIVER
+#if !defined(CONFIG_STM32F0L0G0_USART2)
+#  undef CONFIG_STM32F0L0G0_USART2_SERIALDRIVER
+#  undef CONFIG_STM32F0L0G0_USART2_1WIREDRIVER
 #endif
-#if !defined(CONFIG_STM32F0L0_USART3)
-#  undef CONFIG_STM32F0L0_USART3_SERIALDRIVER
-#  undef CONFIG_STM32F0L0_USART3_1WIREDRIVER
+#if !defined(CONFIG_STM32F0L0G0_USART3)
+#  undef CONFIG_STM32F0L0G0_USART3_SERIALDRIVER
+#  undef CONFIG_STM32F0L0G0_USART3_1WIREDRIVER
 #endif
-#if !defined(CONFIG_STM32F0L0_USART4)
-#  undef CONFIG_STM32F0L0_USART4_SERIALDRIVER
-#  undef CONFIG_STM32F0L0_USART4_1WIREDRIVER
+#if !defined(CONFIG_STM32F0L0G0_USART4)
+#  undef CONFIG_STM32F0L0G0_USART4_SERIALDRIVER
+#  undef CONFIG_STM32F0L0G0_USART4_1WIREDRIVER
 #endif
-#if !defined(CONFIG_STM32F0L0_USART5)
-#  undef CONFIG_STM32F0L0_USART5_SERIALDRIVER
-#  undef CONFIG_STM32F0L0_USART5_1WIREDRIVER
+#if !defined(CONFIG_STM32F0L0G0_USART5)
+#  undef CONFIG_STM32F0L0G0_USART5_SERIALDRIVER
+#  undef CONFIG_STM32F0L0G0_USART5_1WIREDRIVER
 #endif
-#if !defined(CONFIG_STM32F0L0_USART6)
-#  undef CONFIG_STM32F0L0_USART6_SERIALDRIVER
-#  undef CONFIG_STM32F0L0_USART6_1WIREDRIVER
+#if !defined(CONFIG_STM32F0L0G0_USART6)
+#  undef CONFIG_STM32F0L0G0_USART6_SERIALDRIVER
+#  undef CONFIG_STM32F0L0G0_USART6_1WIREDRIVER
 #endif
-#if !defined(CONFIG_STM32F0L0_USART7)
-#  undef CONFIG_STM32F0L0_USART7_SERIALDRIVER
-#  undef CONFIG_STM32F0L0_USART7_1WIREDRIVER
+#if !defined(CONFIG_STM32F0L0G0_USART7)
+#  undef CONFIG_STM32F0L0G0_USART7_SERIALDRIVER
+#  undef CONFIG_STM32F0L0G0_USART7_1WIREDRIVER
 #endif
-#if !defined(CONFIG_STM32F0L0_USART8)
-#  undef CONFIG_STM32F0L0_USART8_SERIALDRIVER
-#  undef CONFIG_STM32F0L0_USART8_1WIREDRIVER
+#if !defined(CONFIG_STM32F0L0G0_USART8)
+#  undef CONFIG_STM32F0L0G0_USART8_SERIALDRIVER
+#  undef CONFIG_STM32F0L0G0_USART8_1WIREDRIVER
 #endif
 
 /* Check 1-Wire and U(S)ART conflicts */
 
-#if defined(CONFIG_STM32F0L0_USART1_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER)
-#  error Both CONFIG_STM32F0L0_USART1_1WIREDRIVER and CONFIG_STM32F0L0_USART1_SERIALDRIVER defined
-#  undef CONFIG_STM32F0L0_USART1_1WIREDRIVER
+#if defined(CONFIG_STM32F0L0G0_USART1_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER)
+#  error Both CONFIG_STM32F0L0G0_USART1_1WIREDRIVER and CONFIG_STM32F0L0G0_USART1_SERIALDRIVER defined
+#  undef CONFIG_STM32F0L0G0_USART1_1WIREDRIVER
 #endif
-#if defined(CONFIG_STM32F0L0_USART2_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER)
-#  error Both CONFIG_STM32F0L0_USART2_1WIREDRIVER and CONFIG_STM32F0L0_USART2_SERIALDRIVER defined
-#  undef CONFIG_STM32F0L0_USART2_1WIREDRIVER
+#if defined(CONFIG_STM32F0L0G0_USART2_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER)
+#  error Both CONFIG_STM32F0L0G0_USART2_1WIREDRIVER and CONFIG_STM32F0L0G0_USART2_SERIALDRIVER defined
+#  undef CONFIG_STM32F0L0G0_USART2_1WIREDRIVER
 #endif
-#if defined(CONFIG_STM32F0L0_USART3_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER)
-#  error Both CONFIG_STM32F0L0_USART3_1WIREDRIVER and CONFIG_STM32F0L0_USART3_SERIALDRIVER defined
-#  undef CONFIG_STM32F0L0_USART3_1WIREDRIVER
+#if defined(CONFIG_STM32F0L0G0_USART3_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER)
+#  error Both CONFIG_STM32F0L0G0_USART3_1WIREDRIVER and CONFIG_STM32F0L0G0_USART3_SERIALDRIVER defined
+#  undef CONFIG_STM32F0L0G0_USART3_1WIREDRIVER
 #endif
-#if defined(CONFIG_STM32F0L0_USART4_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER)
-#  error Both CONFIG_STM32F0L0_USART4_1WIREDRIVER and CONFIG_STM32F0L0_USART4_SERIALDRIVER defined
-#  undef CONFIG_STM32F0L0_USART4_1WIREDRIVER
+#if defined(CONFIG_STM32F0L0G0_USART4_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER)
+#  error Both CONFIG_STM32F0L0G0_USART4_1WIREDRIVER and CONFIG_STM32F0L0G0_USART4_SERIALDRIVER defined
+#  undef CONFIG_STM32F0L0G0_USART4_1WIREDRIVER
 #endif
-#if defined(CONFIG_STM32F0L0_USART5_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER)
-#  error Both CONFIG_STM32F0L0_USART5_1WIREDRIVER and CONFIG_STM32F0L0_USART5_SERIALDRIVER defined
-#  undef CONFIG_STM32F0L0_USART5_1WIREDRIVER
+#if defined(CONFIG_STM32F0L0G0_USART5_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER)
+#  error Both CONFIG_STM32F0L0G0_USART5_1WIREDRIVER and CONFIG_STM32F0L0G0_USART5_SERIALDRIVER defined
+#  undef CONFIG_STM32F0L0G0_USART5_1WIREDRIVER
 #endif
-#if defined(CONFIG_STM32F0L0_USART6_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER)
-#  error Both CONFIG_STM32F0L0_USART6_1WIREDRIVER and CONFIG_STM32F0L0_USART6_SERIALDRIVER defined
-#  undef CONFIG_STM32F0L0_USART6_1WIREDRIVER
+#if defined(CONFIG_STM32F0L0G0_USART6_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER)
+#  error Both CONFIG_STM32F0L0G0_USART6_1WIREDRIVER and CONFIG_STM32F0L0G0_USART6_SERIALDRIVER defined
+#  undef CONFIG_STM32F0L0G0_USART6_1WIREDRIVER
 #endif
-#if defined(CONFIG_STM32F0L0_USART7_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER)
-#  error Both CONFIG_STM32F0L0_USART7_1WIREDRIVER and CONFIG_STM32F0L0_USART7_SERIALDRIVER defined
-#  undef CONFIG_STM32F0L0_USART7_1WIREDRIVER
+#if defined(CONFIG_STM32F0L0G0_USART7_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER)
+#  error Both CONFIG_STM32F0L0G0_USART7_1WIREDRIVER and CONFIG_STM32F0L0G0_USART7_SERIALDRIVER defined
+#  undef CONFIG_STM32F0L0G0_USART7_1WIREDRIVER
 #endif
-#if defined(CONFIG_STM32F0L0_USART8_1WIREDRIVER) && defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER)
-#  error Both CONFIG_STM32F0L0_USART8_1WIREDRIVER and CONFIG_STM32F0L0_USART8_SERIALDRIVER defined
-#  undef CONFIG_STM32F0L0_USART8_1WIREDRIVER
+#if defined(CONFIG_STM32F0L0G0_USART8_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER)
+#  error Both CONFIG_STM32F0L0G0_USART8_1WIREDRIVER and CONFIG_STM32F0L0G0_USART8_SERIALDRIVER defined
+#  undef CONFIG_STM32F0L0G0_USART8_1WIREDRIVER
 #endif
 
 /* Is the serial driver enabled? */
 
-#if defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER) || \
-    defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER) || defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER)  || \
-    defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER)  || defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER) || \
-    defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER)  || defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER)
+#if defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) || \
+    defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER)  || \
+    defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER)  || defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) || \
+    defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER)  || defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER)
 #  define HAVE_SERIALDRIVER 1
 #endif
 
 /* Is the 1-Wire driver? */
 
-#if defined(CONFIG_STM32F0L0_USART1_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART2_1WIREDRIVER) || \
-    defined(CONFIG_STM32F0L0_USART3_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART4_1WIREDRIVER) || \
-    defined(CONFIG_STM32F0L0_USART5_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART6_1WIREDRIVER) || \
-    defined(CONFIG_STM32F0L0_USART7_1WIREDRIVER) || defined(CONFIG_STM32F0L0_USART8_1WIREDRIVER)
+#if defined(CONFIG_STM32F0L0G0_USART1_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART2_1WIREDRIVER) || \
+    defined(CONFIG_STM32F0L0G0_USART3_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART4_1WIREDRIVER) || \
+    defined(CONFIG_STM32F0L0G0_USART5_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART6_1WIREDRIVER) || \
+    defined(CONFIG_STM32F0L0G0_USART7_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART8_1WIREDRIVER)
 #  define HAVE_1WIREDRIVER 1
 #endif
 
 /* Is there a serial console? */
 
-#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER)
+#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER)
 #  undef CONFIG_USART2_SERIAL_CONSOLE
 #  undef CONFIG_USART3_SERIAL_CONSOLE
 #  undef CONFIG_USART4_SERIAL_CONSOLE
@@ -216,7 +216,7 @@
 #  undef CONFIG_USART8_SERIAL_CONSOLE
 #  define CONSOLE_USART 1
 #  define HAVE_CONSOLE 1
-#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER)
+#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER)
 #  undef CONFIG_USART1_SERIAL_CONSOLE
 #  undef CONFIG_USART3_SERIAL_CONSOLE
 #  undef CONFIG_USART4_SERIAL_CONSOLE
@@ -226,7 +226,7 @@
 #  undef CONFIG_USART8_SERIAL_CONSOLE
 #  define CONSOLE_USART 2
 #  define HAVE_CONSOLE 1
-#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER)
+#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER)
 #  undef CONFIG_USART1_SERIAL_CONSOLE
 #  undef CONFIG_USART2_SERIAL_CONSOLE
 #  undef CONFIG_USART4_SERIAL_CONSOLE
@@ -236,7 +236,7 @@
 #  undef CONFIG_USART8_SERIAL_CONSOLE
 #  define CONSOLE_USART 3
 #  define HAVE_CONSOLE 1
-#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER)
+#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER)
 #  undef CONFIG_USART1_SERIAL_CONSOLE
 #  undef CONFIG_USART2_SERIAL_CONSOLE
 #  undef CONFIG_USART3_SERIAL_CONSOLE
@@ -246,7 +246,7 @@
 #  undef CONFIG_USART8_SERIAL_CONSOLE
 #  define CONSOLE_USART 4
 #  define HAVE_CONSOLE 1
-#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER)
+#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER)
 #  undef CONFIG_USART1_SERIAL_CONSOLE
 #  undef CONFIG_USART2_SERIAL_CONSOLE
 #  undef CONFIG_USART3_SERIAL_CONSOLE
@@ -256,7 +256,7 @@
 #  undef CONFIG_USART8_SERIAL_CONSOLE
 #  define CONSOLE_USART 5
 #  define HAVE_CONSOLE 1
-#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER)
+#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER)
 #  undef CONFIG_USART1_SERIAL_CONSOLE
 #  undef CONFIG_USART2_SERIAL_CONSOLE
 #  undef CONFIG_USART3_SERIAL_CONSOLE
@@ -266,7 +266,7 @@
 #  undef CONFIG_USART8_SERIAL_CONSOLE
 #  define CONSOLE_USART 6
 #  define HAVE_CONSOLE 1
-#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER)
+#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER)
 #  undef CONFIG_USART1_SERIAL_CONSOLE
 #  undef CONFIG_USART2_SERIAL_CONSOLE
 #  undef CONFIG_USART3_SERIAL_CONSOLE
@@ -277,7 +277,7 @@
 #  undef CONFIG_USART8_SERIAL_CONSOLE
 #  define CONSOLE_USART 7
 #  define HAVE_CONSOLE 1
-#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER)
+#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER)
 #  undef CONFIG_USART1_SERIAL_CONSOLE
 #  undef CONFIG_USART2_SERIAL_CONSOLE
 #  undef CONFIG_USART3_SERIAL_CONSOLE
@@ -315,35 +315,35 @@
 
 /* Disable the DMA configuration on all unused USARTs */
 
-#ifndef CONFIG_STM32F0L0_USART1_SERIALDRIVER
+#ifndef CONFIG_STM32F0L0G0_USART1_SERIALDRIVER
 #  undef CONFIG_USART1_RXDMA
 #endif
 
-#ifndef CONFIG_STM32F0L0_USART2_SERIALDRIVER
+#ifndef CONFIG_STM32F0L0G0_USART2_SERIALDRIVER
 #  undef CONFIG_USART2_RXDMA
 #endif
 
-#ifndef CONFIG_STM32F0L0_USART3_SERIALDRIVER
+#ifndef CONFIG_STM32F0L0G0_USART3_SERIALDRIVER
 #  undef CONFIG_USART3_RXDMA
 #endif
 
-#ifndef CONFIG_STM32F0L0_USART4_SERIALDRIVER
+#ifndef CONFIG_STM32F0L0G0_USART4_SERIALDRIVER
 #  undef CONFIG_USART4_RXDMA
 #endif
 
-#ifndef CONFIG_STM32F0L0_USART5_SERIALDRIVER
+#ifndef CONFIG_STM32F0L0G0_USART5_SERIALDRIVER
 #  undef CONFIG_USART5_RXDMA
 #endif
 
-#ifndef CONFIG_STM32F0L0_USART6_SERIALDRIVER
+#ifndef CONFIG_STM32F0L0G0_USART6_SERIALDRIVER
 #  undef CONFIG_USART6_RXDMA
 #endif
 
-#ifndef CONFIG_STM32F0L0_USART7_SERIALDRIVER
+#ifndef CONFIG_STM32F0L0G0_USART7_SERIALDRIVER
 #  undef CONFIG_USART7_RXDMA
 #endif
 
-#ifndef CONFIG_STM32F0L0_USART8_SERIALDRIVER
+#ifndef CONFIG_STM32F0L0G0_USART8_SERIALDRIVER
 #  undef CONFIG_USART8_RXDMA
 #endif
 
@@ -381,21 +381,21 @@
 /* Is DMA used on all (enabled) USARTs */
 
 #define SERIAL_HAVE_ONLY_DMA 1
-#if defined(CONFIG_STM32F0L0_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
+#if defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
 #  undef SERIAL_HAVE_ONLY_DMA
-#elif defined(CONFIG_STM32F0L0_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
+#elif defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
 #  undef SERIAL_HAVE_ONLY_DMA
-#elif defined(CONFIG_STM32F0L0_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
+#elif defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
 #  undef SERIAL_HAVE_ONLY_DMA
-#elif defined(CONFIG_STM32F0L0_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA)
+#elif defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA)
 #  undef SERIAL_HAVE_ONLY_DMA
-#elif defined(CONFIG_STM32F0L0_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA)
+#elif defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA)
 #  undef SERIAL_HAVE_ONLY_DMA
-#elif defined(CONFIG_STM32F0L0_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA)
+#elif defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA)
 #  undef SERIAL_HAVE_ONLY_DMA
-#elif defined(CONFIG_STM32F0L0_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA)
+#elif defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA)
 #  undef SERIAL_HAVE_ONLY_DMA
-#elif defined(CONFIG_STM32F0L0_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA)
+#elif defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA)
 #  undef SERIAL_HAVE_ONLY_DMA
 #endif
 
@@ -460,4 +460,4 @@ void stm32_serial_dma_poll(void);
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H */
diff --git a/arch/arm/src/stm32f0l0/stm32_usbdev.c b/arch/arm/src/stm32f0l0g0/stm32_usbdev.c
similarity index 99%
rename from arch/arm/src/stm32f0l0/stm32_usbdev.c
rename to arch/arm/src/stm32f0l0g0/stm32_usbdev.c
index 2cca8a24b55..be4eea7ff73 100644
--- a/arch/arm/src/stm32f0l0/stm32_usbdev.c
+++ b/arch/arm/src/stm32f0l0g0/stm32_usbdev.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f0l0/stm32_usbdev.c
+ * arch/arm/src/stm32f0l0g0/stm32_usbdev.c
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -63,11 +63,10 @@
 #include "up_internal.h"
 #include "hardware/stm32_rcc.h"
 #include "hardware/stm32_usbdev.h"
-#include "stm32_hsi48.h"
 #include "stm32_gpio.h"
 #include "stm32_usbdev.h"
 
-#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32F0L0_USB)
+#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32F0L0G0_USB)
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -88,7 +87,7 @@
  */
 
 #ifndef CONFIG_DEBUG_USB_INFO
-#  undef CONFIG_STM32F0L0_USBDEV_REGDEBUG
+#  undef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG
 #endif
 
 /* Initial interrupt mask: Reset + Suspend + Correct Transfer */
@@ -371,7 +370,7 @@ struct stm32_usbdev_s
 
 /* Register operations ******************************************************/
 
-#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG
+#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG
 static uint16_t stm32_getreg(uint32_t addr);
 static void stm32_putreg(uint16_t val, uint32_t addr);
 static void stm32_dumpep(int epno);
@@ -632,7 +631,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] =
  * Name: stm32_getreg
  ****************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG
+#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG
 static uint16_t stm32_getreg(uint32_t addr)
 {
   static uint32_t prevaddr = 0;
@@ -690,7 +689,7 @@ static uint16_t stm32_getreg(uint32_t addr)
  * Name: stm32_putreg
  ****************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG
+#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG
 static void stm32_putreg(uint16_t val, uint32_t addr)
 {
   /* Show the register value being written */
@@ -707,7 +706,7 @@ static void stm32_putreg(uint16_t val, uint32_t addr)
  * Name: stm32_dumpep
  ****************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_USBDEV_REGDEBUG
+#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG
 static void stm32_dumpep(int epno)
 {
   uint32_t addr;
@@ -3659,10 +3658,8 @@ void up_usbinitialize(void)
 
   /* Configure USB GPIO alternate function pins */
 
-#ifdef CONFIG_STM32F0L0_STM32F30XX
   (void)stm32_configgpio(GPIO_USB_DM);
   (void)stm32_configgpio(GPIO_USB_DP);
-#endif
 
   /* Enable clocking to the USB peripheral */
 
@@ -3670,10 +3667,6 @@ void up_usbinitialize(void)
   regval &= ~RCC_APB1ENR_USBEN;
   putreg32(regval, STM32_RCC_APB1RSTR);
 
-  /* Enable HSI48 clocking to to support USB transfers */
-
-  stm32_enable_hsi48(SYNCSRC_USB);
-
   /* Power up the USB controller, but leave it in the reset state */
 
   stm32_hwsetup(priv);
@@ -3868,4 +3861,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
   return OK;
 }
 
-#endif /* CONFIG_USBDEV && CONFIG_STM32F0L0_USB */
+#endif /* CONFIG_USBDEV && CONFIG_STM32F0L0G0_USB */
diff --git a/arch/arm/src/stm32f0l0/stm32_usbdev.h b/arch/arm/src/stm32f0l0g0/stm32_usbdev.h
similarity index 94%
rename from arch/arm/src/stm32f0l0/stm32_usbdev.h
rename to arch/arm/src/stm32f0l0g0/stm32_usbdev.h
index fb3a48f44fc..b034d5eb1b0 100644
--- a/arch/arm/src/stm32f0l0/stm32_usbdev.h
+++ b/arch/arm/src/stm32f0l0g0/stm32_usbdev.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/stm32_usbdev.h
+ * arch/arm/src/stm32f0l0g0/stm32_usbdev.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_USBDEV_H
-#define __ARCH_ARM_SRC_STM32F0L0_STM32_USBDEV_H
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H
 
 /************************************************************************************
  * Included Files
@@ -93,4 +93,4 @@ void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume);
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_USBDEV_H */
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H */
diff --git a/arch/arm/src/stm32f0l0/stm32f0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c
similarity index 79%
rename from arch/arm/src/stm32f0l0/stm32f0_rcc.c
rename to arch/arm/src/stm32f0l0g0/stm32f0_rcc.c
index 2d292962283..477fb6ad2d8 100644
--- a/arch/arm/src/stm32f0l0/stm32f0_rcc.c
+++ b/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f0l0/stm32f0_rcc.c
+ * arch/arm/src/stm32f0l0g0/stm32f0_rcc.c
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -53,6 +53,18 @@
 #include "hardware/stm32_flash.h"
 #include "hardware/stm32_gpio.h"
 
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Determine if board wants to use HSI48 as 48 MHz oscillator. */
+
+#if defined(CONFIG_STM32F0L0G0_HAVE_HSI48) && defined(STM32_USE_CLK48)
+#  if STM32_CLK48_SEL == RCC_CFGR3_CLK48_HSI48
+#    define STM32_USE_HSI48
+#  endif
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -109,25 +121,25 @@ static inline void rcc_enableahb(void)
 
   regval  = getreg32(STM32_RCC_AHBENR);
 
-#ifdef CONFIG_STM32F0L0_DMA1
+#ifdef CONFIG_STM32F0L0G0_DMA1
   /* DMA 1 clock enable */
 
   regval |= RCC_AHBENR_DMA1EN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_DMA2
+#ifdef CONFIG_STM32F0L0G0_DMA2
   /* DMA 2 clock enable */
 
   regval |= RCC_AHBENR_DMA2EN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_CRC
+#ifdef CONFIG_STM32F0L0G0_CRC
   /* CRC clock enable */
 
   regval |= RCC_AHBENR_CRCEN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_TSC
+#ifdef CONFIG_STM32F0L0G0_TSC
   /* TSC clock enable */
 
   regval |= RCC_AHBENR_TSCEN;
@@ -154,145 +166,145 @@ static inline void rcc_enableapb1(void)
 
   regval  = getreg32(STM32_RCC_APB1ENR);
 
-#ifdef CONFIG_STM32F0L0_TIM2
+#ifdef CONFIG_STM32F0L0G0_TIM2
   /* Timer 2 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_TIM2EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_TIM3
+#ifdef CONFIG_STM32F0L0G0_TIM3
   /* Timer 3 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_TIM3EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_TIM4
+#ifdef CONFIG_STM32F0L0G0_TIM4
   /* Timer 4 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_TIM4EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_TIM6
+#ifdef CONFIG_STM32F0L0G0_TIM6
   /* Timer 6 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_TIM6EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_TIM7
+#ifdef CONFIG_STM32F0L0G0_TIM7
   /* Timer 7 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_TIM7EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_TIM14
+#ifdef CONFIG_STM32F0L0G0_TIM14
   /* Timer 14 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_TIM14EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_WWDG
+#ifdef CONFIG_STM32F0L0G0_WWDG
   /* Window Watchdog clock enable */
 
   regval |= RCC_APB1ENR_WWDGEN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_SPI2
+#ifdef CONFIG_STM32F0L0G0_SPI2
   /* SPI 2 clock enable */
 
   regval |= RCC_APB1ENR_SPI2EN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART2
+#ifdef CONFIG_STM32F0L0G0_USART2
   /* USART 2 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_USART2EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART3
+#ifdef CONFIG_STM32F0L0G0_USART3
   /* USART 3 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_USART3EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART4
+#ifdef CONFIG_STM32F0L0G0_USART4
   /* USART 4 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_USART4EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART5
+#ifdef CONFIG_STM32F0L0G0_USART5
   /* USART 5 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_USART5EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_I2C1
+#ifdef CONFIG_STM32F0L0G0_I2C1
   /* I2C 1 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_I2C1EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_I2C2
+#ifdef CONFIG_STM32F0L0G0_I2C2
   /* I2C 2 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_I2C2EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USB
+#ifdef CONFIG_STM32F0L0G0_USB
   /* USB clock enable */
 
   regval |= RCC_APB1ENR_USBEN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_CAN1
+#ifdef CONFIG_STM32F0L0G0_CAN1
   /* CAN1 clock enable */
 
   regval |= RCC_APB1ENR_CAN1EN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_CRS
+#ifdef CONFIG_STM32F0L0G0_CRS
   /*  Clock recovery system clock enable */
 
   regval |= RCC_APB1ENR_CRSEN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_PWR
+#ifdef CONFIG_STM32F0L0G0_PWR
   /*  Power interface clock enable */
 
   regval |= RCC_APB1ENR_PWREN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_DAC1
+#ifdef CONFIG_STM32F0L0G0_DAC1
   /* DAC 1 interface clock enable */
 
   regval |= RCC_APB1ENR_DAC1EN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_CEC
+#ifdef CONFIG_STM32F0L0G0_CEC
   /* CEC interface clock enable */
 
   regval |= RCC_APB1ENR_CECEN;
@@ -319,84 +331,84 @@ static inline void rcc_enableapb2(void)
 
   regval = getreg32(STM32_RCC_APB2ENR);
 
-#ifdef CONFIG_STM32F0L0_SYSCFG
+#ifdef CONFIG_STM32F0L0G0_SYSCFG
   /* SYSCFG clock */
 
   regval |= RCC_APB2ENR_SYSCFGCOMPEN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART6
+#ifdef CONFIG_STM32F0L0G0_USART6
   /* USART 6 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB2ENR_USART6EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART7
+#ifdef CONFIG_STM32F0L0G0_USART7
   /* USART 7 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB2ENR_USART7EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART8
+#ifdef CONFIG_STM32F0L0G0_USART8
   /* USART 8 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB2ENR_USART8EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_ADC1
+#ifdef CONFIG_STM32F0L0G0_ADC1
   /* ADC 1 clock enable */
 
   regval |= RCC_APB2ENR_ADC1EN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_TIM1
+#ifdef CONFIG_STM32F0L0G0_TIM1
   /* Timer 1 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB2ENR_TIM1EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_SPI1
+#ifdef CONFIG_STM32F0L0G0_SPI1
   /* SPI 1 clock enable */
 
   regval |= RCC_APB2ENR_SPI1EN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART1
+#ifdef CONFIG_STM32F0L0G0_USART1
   /* USART1 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB2ENR_USART1EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_TIM15
+#ifdef CONFIG_STM32F0L0G0_TIM15
   /* Timer 15 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB2ENR_TIM15EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_TIM16
+#ifdef CONFIG_STM32F0L0G0_TIM16
   /* Timer 16 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB2ENR_TIM16EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_TIM17
+#ifdef CONFIG_STM32F0L0G0_TIM17
   /* Timer 17 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB2ENR_TIM17EN;
 #endif
 #endif
@@ -490,6 +502,14 @@ static void stm32_stdclockconfig(void)
   regval |= RCC_CFGR_SW_PLL;
   putreg32(regval, STM32_RCC_CFGR);
   while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL);
+
+#ifdef STM32_USE_CLK48
+  /* Select the HSI48 clock source (USB clock source) */
+
+  regval  = getreg32(STM32_RCC_CFGR3);
+  regval |= STM32_CLK48_SEL;
+  putreg32(regval, STM32_RCC_CFGR3);
+#endif
 }
 #endif
 
@@ -503,4 +523,10 @@ static inline void rcc_enableperipherals(void)
   rcc_enableahb();
   rcc_enableapb2();
   rcc_enableapb1();
+
+#ifdef STM32_USE_HSI48
+  /* Enable HSI48 clocking to support USB transfers or RNG */
+
+  stm32_enable_hsi48(STM32_HSI48_SYNCSRC);
+#endif
 }
diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c
new file mode 100644
index 00000000000..b4c1c83bbce
--- /dev/null
+++ b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c
@@ -0,0 +1,635 @@
+/****************************************************************************
+ * arch/arm/src/stm32f0l0g0/stm32g0_rcc.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "stm32_pwr.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Allow up to 100 milliseconds for the high speed clock to become ready.
+ * that is a very long delay, but if the clock does not become ready we are
+ * hosed anyway.  Normally this is very fast, but I have seen at least one
+ * board that required this long, long timeout for the HSE to be ready.
+ */
+
+#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
+
+/* HSE divisor to yield ~1MHz RTC clock (valid for HSE = 8MHz) */
+
+#define HSE_DIVISOR RCC_CR_RTCPRE_HSEd8
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: rcc_reset
+ *
+ * Description:
+ *   Put all RCC registers in reset state
+ *
+ ****************************************************************************/
+
+static inline void rcc_reset(void)
+{
+  uint32_t regval;
+
+  /* Reset CFGR register */
+
+  putreg32(RCC_CFGR_RESET, STM32_RCC_CFGR);
+
+  /* Reset CR register */
+
+  putreg32(RCC_CR_RESET, STM32_RCC_CR);
+
+  /* Reset PLLCFGR register */
+
+  putreg32(RCC_PLLCFGR_RESET, STM32_RCC_PLLCFG);
+
+  /* DBG clock enable */
+
+  regval = RCC_APB1ENR_DBGEN;
+  putreg32(regval, STM32_RCC_APB1ENR);
+}
+
+/****************************************************************************
+ * Name: rcc_enableio
+ *
+ * Description:
+ *   Enable selected GPIO
+ *
+ ****************************************************************************/
+
+static inline void rcc_enableio(void)
+{
+  uint32_t regval = 0;
+
+  /* REVISIT: */
+
+  regval |= (RCC_IOPENR_IOPAEN | RCC_IOPENR_IOPBEN | RCC_IOPENR_IOPCEN | \
+             RCC_IOPENR_IOPDEN | RCC_IOPENR_IOPFEN);
+
+  putreg32(regval, STM32_RCC_IOPENR);   /* Enable GPIO */
+}
+
+/****************************************************************************
+ * Name: rcc_enableahb
+ *
+ * Description:
+ *   Enable selected AHB peripherals
+ *
+ ****************************************************************************/
+
+static inline void rcc_enableahb(void)
+{
+  uint32_t regval = 0;
+
+  /* Set the appropriate bits in the AHBENR register to enabled the
+   * selected AHBENR peripherals.
+   */
+
+  regval  = getreg32(STM32_RCC_AHBENR);
+
+#ifdef CONFIG_STM32F0L0G0_DMA1
+  /* DMA 1 clock enable */
+
+  regval |= RCC_AHBENR_DMA1EN;
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_MIF
+  /* Memory interface clock enable */
+
+  regval |= RCC_AHBENR_MIFEN;
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_CRC
+  /* CRC clock enable */
+
+  regval |= RCC_AHBENR_CRCEN;
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_RNG
+  /* Random number generator clock enable */
+
+  regval |= RCC_AHBENR_RNGEN;
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_AES
+  /* AES modules clock enable */
+
+  regval |= RCC_AHBENR_AESEN;
+#endif
+
+  putreg32(regval, STM32_RCC_AHBENR);   /* Enable peripherals */
+}
+
+/****************************************************************************
+ * Name: rcc_enableapb1
+ *
+ * Description:
+ *   Enable selected APB1 peripherals
+ *
+ ****************************************************************************/
+
+static inline void rcc_enableapb1(void)
+{
+  uint32_t regval;
+
+  /* Set the appropriate bits in the APB1ENR register to enabled the
+   * selected APB1 peripherals.
+   */
+
+  regval  = getreg32(STM32_RCC_APB1ENR);
+
+#ifdef CONFIG_STM32F0L0G0_TIM2
+  /* Timer 2 clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM2EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_TIM3
+  /* Timer 3 clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM3EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_TIM6
+  /* Timer 6 clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM6EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_TIM7
+  /* Timer 7 clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM7EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_SPI2
+  /* SPI 2 clock enable */
+
+  regval |= RCC_APB1ENR_SPI2EN;
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_USART2
+  /* USART 2 clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB1ENR_USART2EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_USART3
+  /* USART 3 clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB1ENR_USART3EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_USART4
+  /* USART 4 clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB1ENR_USART4EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_LPUSART1
+  /* USART 5 clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB1ENR_LPUSART1EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_I2C1
+  /* I2C 1 clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB1ENR_I2C1EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_I2C2
+  /* I2C 2 clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB1ENR_I2C2EN;
+#endif
+#endif
+#ifdef CONFIG_STM32F0L0G0_PWR
+  /*  Power interface clock enable */
+
+  regval |= RCC_APB1ENR_PWREN;
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_DAC1
+  /* DAC 1 interface clock enable */
+
+  regval |= RCC_APB1ENR_DAC1EN;
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_LPTIM1
+  /* LPTIM1 clock enable */
+
+  regval |= RCC_APB1ENR_LPTIM1EN;
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_LPTIM2
+  /* LPTIM2 clock enable */
+
+  regval |= RCC_APB1ENR_LPTIM2EN;
+#endif
+
+  putreg32(regval, STM32_RCC_APB1ENR);
+}
+
+/****************************************************************************
+ * Name: rcc_enableapb2
+ *
+ * Description:
+ *   Enable selected APB2 peripherals
+ *
+ ****************************************************************************/
+
+static inline void rcc_enableapb2(void)
+{
+  uint32_t regval;
+
+  /* Set the appropriate bits in the APB2ENR register to enabled the
+   * selected APB2 peripherals.
+   */
+
+  regval = getreg32(STM32_RCC_APB2ENR);
+
+#ifdef CONFIG_STM32F0L0G0_SYSCFG
+  /* SYSCFG clock */
+
+  regval |= RCC_APB2ENR_SYSCFGEN;
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_TIM1
+  /* TIM1 Timer clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM1EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_SPI1
+  /* SPI 1 clock enable */
+
+  regval |= RCC_APB2ENR_SPI1EN;
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_USART1
+  /* USART1 clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB2ENR_USART1EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_TIM14
+  /* TIM14 Timer clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM14EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_TIM15
+  /* TIM5 Timer clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM15EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_TIM16
+  /* TIM16 Timer clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM16EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_TIM17
+  /* TIM17 Timer clock enable */
+
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM17EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_ADC1
+  /* ADC 1 clock enable */
+
+  regval |= RCC_APB2ENR_ADC1EN;
+#endif
+
+  putreg32(regval, STM32_RCC_APB2ENR);
+}
+
+/****************************************************************************
+ * Name: stm32_rcc_enablehse
+ *
+ * Description:
+ *   Enable the External High-Speed (HSE) Oscillator.
+ *
+ ****************************************************************************/
+
+#if (STM32_PLLCFG_PLLSRC == RCC_PLLCFG_PLLSRC_HSE) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
+static inline bool stm32_rcc_enablehse(void)
+{
+  uint32_t regval;
+  volatile int32_t timeout;
+
+  /* Enable External High-Speed Clock (HSE) */
+
+  regval  = getreg32(STM32_RCC_CR);
+#ifdef STM32_HSEBYP_ENABLE          /* May be defined in board.h header file */
+  regval |= RCC_CR_HSEBYP;          /* Enable HSE clock bypass */
+#else
+  regval &= ~RCC_CR_HSEBYP;         /* Disable HSE clock bypass */
+#endif
+  regval |= RCC_CR_HSEON;           /* Enable HSE */
+  putreg32(regval, STM32_RCC_CR);
+
+  /* Wait until the HSE is ready (or until a timeout elapsed) */
+
+  for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
+    {
+      /* Check if the HSERDY flag is set in the CR */
+
+      if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
+        {
+          /* If so, then return TRUE */
+
+          return true;
+        }
+    }
+
+  /* In the case of a timeout starting the HSE, we really don't have a
+   * strategy.  This is almost always a hardware failure or misconfiguration.
+   */
+
+  return false;
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_stdclockconfig
+ *
+ * Description:
+ *   Called to change to new clock based on settings in board.h.
+ *
+ *   NOTE:  This logic would need to be extended if you need to select low-
+ *   power clocking modes or any clocking other than PLL driven by the HSE.
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
+static void stm32_stdclockconfig(void)
+{
+  uint32_t regval;
+#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
+  uint16_t pwrcr;
+#endif
+  uint32_t pwr_vos;
+  bool flash_1ws;
+
+  /* Enable PWR clock from APB1 to give access to PWR_CR register */
+
+  regval  = getreg32(STM32_RCC_APB1ENR);
+  regval |= RCC_APB1ENR_PWREN;
+  putreg32(regval, STM32_RCC_APB1ENR);
+
+#warning TODO: configure VOS range
+  UNUSED(pwr_vos);
+
+#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
+  /* If RTC / LCD selects HSE as clock source, the RTC prescaler
+   * needs to be set before HSEON bit is set.
+   */
+
+  /* The RTC domain has write access denied after reset,
+   * you have to enable write access using DBP bit in the PWR CR
+   * register before to selecting the clock source ( and the PWR
+   * peripheral must be enabled)
+   */
+
+  regval  = getreg32(STM32_RCC_APB1ENR);
+  regval |= RCC_APB1ENR_PWREN;
+  putreg32(regval, STM32_RCC_APB1ENR);
+
+  pwrcr = getreg16(STM32_PWR_CR);
+  putreg16(pwrcr | PWR_CR_DBP, STM32_PWR_CR);
+
+  /* Set the RTC clock divisor */
+
+  regval = getreg32(STM32_RCC_CSR);
+  regval &= ~RCC_CSR_RTCSEL_MASK;
+  regval |= RCC_CSR_RTCSEL_HSE;
+  putreg32(regval, STM32_RCC_CSR);
+
+  regval = getreg32(STM32_RCC_CR);
+  regval &= ~RCC_CR_RTCPRE_MASK;
+  regval |= HSE_DIVISOR;
+  putreg32(regval, STM32_RCC_CR);
+
+  /* Restore the previous state of the DBP bit */
+
+  putreg32(regval, STM32_PWR_CR);
+
+#endif
+
+  /* Enable the source clock for the PLL (via HSE or HSI), HSE, and HSI. */
+
+#if (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE) || \
+    ((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && (STM32_PLLCFG_PLLSRC == RCC_PLLCFG_PLLSRC_HSE))
+
+  /* The PLL is using the HSE, or the HSE is the system clock.  In either
+   * case, we need to enable HSE clocking.
+   */
+
+  if (!stm32_rcc_enablehse())
+    {
+      /* In the case of a timeout starting the HSE, we really don't have a
+       * strategy.  This is almost always a hardware failure or
+       * misconfiguration (for example, if no crystal is fitted on the board.
+       */
+
+      return;
+    }
+
+#elif (STM32_SYSCLK_SW == RCC_CFGR_SW_HSI) || \
+      ((STM32_SYSCLK_SW == RCC_CFGR_SW_PLL) && STM32_PLLCFG_PLLSRC == RCC_PLLCFG_PLLSRC_HSI)
+
+  /* The PLL is using the HSI, or the HSI is the system clock.  In either
+   * case, we need to enable HSI clocking.
+   */
+
+  regval  = getreg32(STM32_RCC_CR);   /* Enable the HSI */
+  regval |= RCC_CR_HSION;
+  putreg32(regval, STM32_RCC_CR);
+
+  /* Wait until the HSI clock is ready.  Since this is an internal clock, no
+   * timeout is expected
+   */
+
+  while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0);
+
+#endif
+
+#warning TODO: configure flash latency
+  UNUSED(flash_1ws);
+
+  /* Set the HCLK source/divider */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_HPRE_MASK;
+  regval |= STM32_RCC_CFGR_HPRE;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Set the PCLK1 divider */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_PPRE1_MASK;
+  regval |= STM32_RCC_CFGR_PPRE1;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* If we are using the PLL, configure and start it */
+
+#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
+
+  /* Configure PLLs */
+
+  regval = STM32_PLLCFG_PLLSRC | STM32_PLLCFG_PLLCFG;
+
+  /* Configure PLL clock input */
+
+  regval |= STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN;
+
+  /* Configure PLL clock outputs division */
+
+  regval |= STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR;
+
+  /* Write PLLCFG register */
+
+  putreg32(regval, STM32_RCC_PLLCFG);
+
+  /* Enable PLL */
+
+  regval = getreg32(STM32_RCC_CR);
+  regval |= RCC_CR_PLLON;
+  putreg32(regval, STM32_RCC_CR);
+#endif
+
+  /* Select the system clock source (probably the PLL) */
+
+  regval  = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_SW_MASK;
+  regval |= STM32_SYSCLK_SW;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Wait until the selected source is used as the system clock source */
+
+  while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
+
+#if defined(CONFIG_STM32F0L0G0_IWDG)   || \
+    defined(CONFIG_STM32F0L0G0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK)
+  /* Low speed internal clock source LSI
+   *
+   * TODO: There is another case where the LSI needs to
+   * be enabled: if the MCO pin selects LSI as source.
+   */
+
+  stm32_rcc_enablelsi();
+
+#endif
+
+#if defined(CONFIG_STM32F0L0G0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK)
+  /* Low speed external clock source LSE
+   *
+   * TODO: There is another case where the LSE needs to
+   * be enabled: if the MCO pin selects LSE as source.
+   *
+   * TODO: There is another case where the LSE needs to
+   * be enabled: if TIM9-10 Channel 1 selects LSE as input.
+   *
+   * TODO: There is another case where the LSE needs to
+   * be enabled: if TIM10-11 selects LSE as ETR Input.
+   *
+   */
+
+  stm32_rcc_enablelse();
+#endif
+}
+#endif
+
+/****************************************************************************
+ * Name: rcc_enableperiphals
+ ****************************************************************************/
+
+static inline void rcc_enableperipherals(void)
+{
+  rcc_enableio();
+  rcc_enableahb();
+  rcc_enableapb2();
+  rcc_enableapb1();
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
diff --git a/arch/arm/src/stm32f0l0/stm32l0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c
similarity index 81%
rename from arch/arm/src/stm32f0l0/stm32l0_rcc.c
rename to arch/arm/src/stm32f0l0g0/stm32l0_rcc.c
index fc83e0c1349..1d15e6f241f 100644
--- a/arch/arm/src/stm32f0l0/stm32l0_rcc.c
+++ b/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f0l0/stm32l0_rcc.c
+ * arch/arm/src/stm32f0l0g0/stm32l0_rcc.c
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -39,6 +39,8 @@
 
 #include "stm32_pwr.h"
 
+#include "hardware/stm32_syscfg.h"
+
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
@@ -55,6 +57,17 @@
 
 #define HSE_DIVISOR RCC_CR_RTCPRE_HSEd8
 
+/* Determine if board wants to use HSI48 as 48 MHz oscillator. */
+
+#if defined(CONFIG_STM32F0L0G0_HAVE_HSI48) && defined(STM32_USE_CLK48)
+#  if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48
+#    define STM32_USE_HSI48
+#    ifndef CONFIG_STM32F0L0G0_VREFINT
+#      error VREFINT must be enabled if HSI48 used
+#    endif
+#  endif
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -128,42 +141,36 @@ static inline void rcc_enableahb(void)
 
   regval  = getreg32(STM32_RCC_AHBENR);
 
-#ifdef CONFIG_STM32F0L0_DMA1
+#ifdef CONFIG_STM32F0L0G0_DMA1
   /* DMA 1 clock enable */
 
   regval |= RCC_AHBENR_DMA1EN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_MIF
+#ifdef CONFIG_STM32F0L0G0_MIF
   /* Memory interface clock enable */
 
   regval |= RCC_AHBENR_MIFEN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_CRC
+#ifdef CONFIG_STM32F0L0G0_CRC
   /* CRC clock enable */
 
   regval |= RCC_AHBENR_CRCEN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_TSC
+#ifdef CONFIG_STM32F0L0G0_TSC
   /* TSC clock enable */
 
   regval |= RCC_AHBENR_TSCEN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_RNG
+#ifdef CONFIG_STM32F0L0G0_RNG
   /* Random number generator clock enable */
 
   regval |= RCC_AHBENR_RNGEN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_CRYP
-  /* Cryptographic modules clock enable */
-
-  regval |= RCC_AHBENR_CRYPEN;
-#endif
-
   putreg32(regval, STM32_RCC_AHBENR);   /* Enable peripherals */
 }
 
@@ -185,137 +192,137 @@ static inline void rcc_enableapb1(void)
 
   regval  = getreg32(STM32_RCC_APB1ENR);
 
-#ifdef CONFIG_STM32F0L0_TIM2
+#ifdef CONFIG_STM32F0L0G0_TIM2
   /* Timer 2 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_TIM2EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_TIM3
+#ifdef CONFIG_STM32F0L0G0_TIM3
   /* Timer 3 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_TIM3EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_TIM6
+#ifdef CONFIG_STM32F0L0G0_TIM6
   /* Timer 6 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_TIM6EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_TIM7
+#ifdef CONFIG_STM32F0L0G0_TIM7
   /* Timer 7 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_TIM7EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_LCD
+#ifdef CONFIG_STM32F0L0G0_LCD
   /* LCD clock enable */
 
   regval |= RCC_APB1ENR_LCDEN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_WWDG
+#ifdef CONFIG_STM32F0L0G0_WWDG
   /* Window Watchdog clock enable */
 
   regval |= RCC_APB1ENR_WWDGEN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_SPI2
+#ifdef CONFIG_STM32F0L0G0_SPI2
   /* SPI 2 clock enable */
 
   regval |= RCC_APB1ENR_SPI2EN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART2
+#ifdef CONFIG_STM32F0L0G0_USART2
   /* USART 2 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_USART2EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART3
+#ifdef CONFIG_STM32F0L0G0_USART3
   /* USART 3 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_USART3EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_UART4
+#ifdef CONFIG_STM32F0L0G0_USART4
   /* USART 4 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
-  regval |= RCC_APB1ENR_UART4EN;
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB1ENR_USART4EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_UART5
+#ifdef CONFIG_STM32F0L0G0_USART5
   /* USART 5 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
-  regval |= RCC_APB1ENR_UART5EN;
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
+  regval |= RCC_APB1ENR_USART5EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_I2C1
+#ifdef CONFIG_STM32F0L0G0_I2C1
   /* I2C 1 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_I2C1EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_I2C2
+#ifdef CONFIG_STM32F0L0G0_I2C2
   /* I2C 2 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_I2C2EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_USB
+#ifdef CONFIG_STM32F0L0G0_USB
   /* USB clock enable */
 
   regval |= RCC_APB1ENR_USBEN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_CRS
+#ifdef CONFIG_STM32F0L0G0_CRS
   /*  Clock recovery system clock enable */
 
   regval |= RCC_APB1ENR_CRSEN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_PWR
+#ifdef CONFIG_STM32F0L0G0_PWR
   /*  Power interface clock enable */
 
   regval |= RCC_APB1ENR_PWREN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_DAC1
+#ifdef CONFIG_STM32F0L0G0_DAC1
   /* DAC 1 interface clock enable */
 
   regval |= RCC_APB1ENR_DAC1EN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_I2C3
+#ifdef CONFIG_STM32F0L0G0_I2C3
   /* I2C 3 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB1ENR_I2C4EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_LPTIM1
+#ifdef CONFIG_STM32F0L0G0_LPTIM1
   /* LPTIM1 clock enable */
 
   regval |= RCC_APB1ENR_LPTIM1EN;
@@ -342,44 +349,44 @@ static inline void rcc_enableapb2(void)
 
   regval = getreg32(STM32_RCC_APB2ENR);
 
-#ifdef CONFIG_STM32F0L0_SYSCFG
+#ifdef CONFIG_STM32F0L0G0_SYSCFG
   /* SYSCFG clock */
 
   regval |= RCC_APB2ENR_SYSCFGEN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_TIM21
+#ifdef CONFIG_STM32F0L0G0_TIM21
   /* TIM21 Timer clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB2ENR_TIM21EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_TIM22
+#ifdef CONFIG_STM32F0L0G0_TIM22
   /* TIM22 Timer clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB2ENR_TIM10EN;
 #endif
 #endif
 
-#ifdef CONFIG_STM32F0L0_ADC1
+#ifdef CONFIG_STM32F0L0G0_ADC1
   /* ADC 1 clock enable */
 
   regval |= RCC_APB2ENR_ADC1EN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_SPI1
+#ifdef CONFIG_STM32F0L0G0_SPI1
   /* SPI 1 clock enable */
 
   regval |= RCC_APB2ENR_SPI1EN;
 #endif
 
-#ifdef CONFIG_STM32F0L0_USART1
+#ifdef CONFIG_STM32F0L0G0_USART1
   /* USART1 clock enable */
 
-#ifdef CONFIG_STM32F0L0_FORCEPOWER
+#ifdef CONFIG_STM32F0L0G0_FORCEPOWER
   regval |= RCC_APB2ENR_USART1EN;
 #endif
 #endif
@@ -393,6 +400,32 @@ static inline void rcc_enableapb2(void)
   putreg32(regval, STM32_RCC_APB2ENR);
 }
 
+/****************************************************************************
+ * Name: rcc_enableccip
+ *
+ * Description:
+ *   Set peripherals independent clock configuration.
+ *
+ ****************************************************************************/
+
+static inline void rcc_enableccip(void)
+{
+  uint32_t regval;
+
+  /* Certain peripherals have no clock selected even when their enable bit is
+   * set. Set some defaults in the CCIPR register so those peripherals
+   * will at least have a clock.
+   */
+
+  regval = getreg32(STM32_RCC_CCIPR);
+
+#if defined(STM32_USE_CLK48)
+  regval |= STM32_CLK48_SEL;
+#endif
+
+  putreg32(regval, STM32_RCC_CCIPR);
+}
+
 /****************************************************************************
  * Name: stm32_rcc_enablehse
  *
@@ -455,7 +488,7 @@ static inline bool stm32_rcc_enablehse(void)
 static void stm32_stdclockconfig(void)
 {
   uint32_t regval;
-#if defined(CONFIG_STM32F0L0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
+#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
   uint16_t pwrcr;
 #endif
   uint32_t pwr_vos;
@@ -506,7 +539,7 @@ static void stm32_stdclockconfig(void)
 
   stm32_pwr_setvos(pwr_vos);
 
-#if defined(CONFIG_STM32F0L0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
+#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK)
   /* If RTC / LCD selects HSE as clock source, the RTC prescaler
    * needs to be set before HSEON bit is set.
    */
@@ -684,8 +717,8 @@ static void stm32_stdclockconfig(void)
 
   while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
 
-#if defined(CONFIG_STM32F0L0_IWDG)   || \
-    defined(CONFIG_STM32F0L0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK)
+#if defined(CONFIG_STM32F0L0G0_IWDG)   || \
+    defined(CONFIG_STM32F0L0G0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK)
   /* Low speed internal clock source LSI
    *
    * TODO: There is another case where the LSI needs to
@@ -696,7 +729,7 @@ static void stm32_stdclockconfig(void)
 
 #endif
 
-#if defined(CONFIG_STM32F0L0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK)
+#if defined(CONFIG_STM32F0L0G0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK)
   /* Low speed external clock source LSE
    *
    * TODO: There is another case where the LSE needs to
@@ -712,6 +745,41 @@ static void stm32_stdclockconfig(void)
 
   stm32_rcc_enablelse();
 #endif
+
+}
+#endif
+
+/****************************************************************************
+ * Name: vrefint_enable
+ *
+ * Description:
+ *   Enable and configure internal voltage reference (VREFINT)
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32F0L0G0_VREFINT
+static void vrefint_enable(void)
+{
+  uint32_t regval = 0;
+
+  /* The HSI48 requires VREFINT and its reference to HSI48  */
+
+  regval = getreg32(STM32_SYSCFG_CFGR3);
+
+  /* Enable VREFINT */
+
+  regval |= SYSCFG_CFGR3_ENVREFINT;
+  putreg32(regval, STM32_SYSCFG_CFGR3);
+
+#ifdef STM32_USE_HSI48
+  /* Enable VREFINT reference to HSI48 */
+
+  regval |= SYSCFG_CFGR3_ENBUFVREFINTHSI48;
+#endif
+
+  /* Wait for VREFINT ready */
+
+  while ((getreg32(STM32_SYSCFG_CFGR3) & SYSCFG_CFGR3_VREFINTRDYF) == 0);
 }
 #endif
 
@@ -721,10 +789,20 @@ static void stm32_stdclockconfig(void)
 
 static inline void rcc_enableperipherals(void)
 {
+  rcc_enableccip();
   rcc_enableio();
   rcc_enableahb();
   rcc_enableapb2();
   rcc_enableapb1();
+#ifdef CONFIG_STM32F0L0G0_VREFINT
+  vrefint_enable();
+#endif
+
+#ifdef STM32_USE_HSI48
+  /* Enable HSI48 clocking to support USB transfers or RNG */
+
+  stm32_enable_hsi48(STM32_HSI48_SYNCSRC);
+#endif
 }
 
 /****************************************************************************
diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig
index fd0dc4a3041..d5f19303da5 100644
--- a/arch/arm/src/stm32f7/Kconfig
+++ b/arch/arm/src/stm32f7/Kconfig
@@ -95,6 +95,7 @@ config ARCH_CHIP_STM32F723RE
 config ARCH_CHIP_STM32F723VC
 	bool "STM32F723VC"
 	select STM32F7_STM32F723XX
+	select STM32F7_HAVE_INTERNAL_ULPI
 	select STM32F7_FLASH_CONFIG_C
 	select STM32F7_IO_CONFIG_V
 	---help---
@@ -103,6 +104,7 @@ config ARCH_CHIP_STM32F723VC
 config ARCH_CHIP_STM32F723VE
 	bool "STM32F723VE"
 	select STM32F7_STM32F723XX
+	select STM32F7_HAVE_INTERNAL_ULPI
 	select STM32F7_FLASH_CONFIG_E
 	select STM32F7_IO_CONFIG_V
 	---help---
@@ -111,6 +113,7 @@ config ARCH_CHIP_STM32F723VE
 config ARCH_CHIP_STM32F723ZC
 	bool "STM32F723ZC"
 	select STM32F7_STM32F723XX
+	select STM32F7_HAVE_INTERNAL_ULPI
 	select STM32F7_FLASH_CONFIG_C
 	select STM32F7_IO_CONFIG_Z
 	---help---
@@ -119,6 +122,7 @@ config ARCH_CHIP_STM32F723ZC
 config ARCH_CHIP_STM32F723ZE
 	bool "STM32F723ZE"
 	select STM32F7_STM32F723XX
+	select STM32F7_HAVE_INTERNAL_ULPI
 	select STM32F7_FLASH_CONFIG_E
 	select STM32F7_IO_CONFIG_Z
 	---help---
@@ -127,6 +131,7 @@ config ARCH_CHIP_STM32F723ZE
 config ARCH_CHIP_STM32F723IC
 	bool "STM32F723IC"
 	select STM32F7_STM32F723XX
+	select STM32F7_HAVE_INTERNAL_ULPI
 	select STM32F7_FLASH_CONFIG_C
 	select STM32F7_IO_CONFIG_I
 	---help---
@@ -135,6 +140,7 @@ config ARCH_CHIP_STM32F723IC
 config ARCH_CHIP_STM32F723IE
 	bool "STM32F723IE"
 	select STM32F7_STM32F723XX
+	select STM32F7_HAVE_INTERNAL_ULPI
 	select STM32F7_FLASH_CONFIG_E
 	select STM32F7_IO_CONFIG_I
 	---help---
@@ -666,6 +672,7 @@ config STM32F7_STM32F722XX
 	select STM32F7_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V)
 	select STM32F7_HAVE_CRYP
 	select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R
+	select STM32F7_HAVE_EXTERNAL_ULPI
 
 config STM32F7_STM32F723XX
 	bool
@@ -724,6 +731,7 @@ config STM32F7_STM32F746XX
 	select STM32F7_HAVE_DMA2D
 	select STM32F7_HAVE_CAN2
 	select STM32F7_HAVE_SPI4
+	select STM32F7_HAVE_EXTERNAL_ULPI
 
 config STM32F7_STM32F756XX
 	bool
@@ -1110,6 +1118,27 @@ config STM32F7_FLASH_ART_ACCELERATOR
 		Enable if code and/or read-only data is accessed through ITCM bus instead of
 		AXIM bus.
 
+config STM32F7_PROGMEM
+	bool "Flash progmem support"
+	default n
+	---help---
+		Add progmem support, start block and end block options are provided to 
+		obtain an uniform flash memory mapping.
+
+if STM32F7_PROGMEM
+
+config STM32F7_PROGMEM_STARTBLOCK
+	int "First mapped progmem block"
+	default 0
+	range 0 64
+
+config STM32F7_PROGMEM_LASTBLOCK
+	int "Last mapped progmem block"
+	default -1
+	range -1 64
+
+endif # STM32F7_PROGMEM
+
 menu "STM32 Peripheral Support"
 
 # These "hidden" settings determine is a peripheral option is available for the
@@ -1199,6 +1228,14 @@ config STM32F7_HAVE_DFSDM1
 	bool
 	default n
 
+config STM32F7_HAVE_INTERNAL_ULPI
+	bool
+	default n
+
+config STM32F7_HAVE_EXTERNAL_ULPI
+	bool
+	default n
+
 # These "hidden" settings are the OR of individual peripheral selections
 # indicating that the general capability is required.
 
@@ -1427,8 +1464,8 @@ config STM32F7_OTGFS
 	default n
 	select USBHOST_HAVE_ASYNCH if USBHOST
 
-config STM32F7_OTGHS
-	bool "OTG HS"
+config STM32F7_OTGFSHS
+	bool "OTG FS/HS"
 	default n
 	select USBHOST_HAVE_ASYNCH if USBHOST
 
@@ -1953,6 +1990,33 @@ endif
 
 endmenu # U[S]ART Configuration
 
+menu "STM32F7_OTG_HS Configuration"
+	depends on STM32F7_OTGFSHS
+
+choice
+	prompt "ULPI Selection"
+	default STM32F7_NO_ULPI
+
+config STM32F7_NO_ULPI
+	bool "No External ULPI"
+	---help---
+	Select to enable the presence of an external ULPI PHY
+
+config STM32F7_EXTERNAL_ULPI
+	 bool "External ULPI"
+	depends on STM32F7_HAVE_EXTERNAL_ULPI
+	---help---
+		Select to enable the presence of an external ULPI PHY
+
+config STM32F7_INTERNAL_ULPI
+	bool "Internal ULPI PHY"
+	depends on STM32F7_HAVE_INTERNAL_ULPI
+	---help---
+		Select to enable the internal ULPI for USB HS
+endchoice #"ULPI Selection"
+
+endmenu # OTG_HS Config
+
 menu "QuadSPI Configuration"
 	depends on STM32F7_QUADSPI
 
@@ -2103,7 +2167,7 @@ config STM32F7_SPI_DMA
 	default n
 	---help---
 		Use DMA to improve SPI transfer performance.  Cannot be used with STM32F7_SPI_INTERRUPT.
-		
+
 config STM32F7_SPI1_DMA
 	bool "SPI1 DMA"
 	default n
@@ -2406,6 +2470,27 @@ config STM32F7_DMACAPABLE
 
 menu "Timer Configuration"
 
+if SCHED_TICKLESS
+
+config STM32F7_TICKLESS_TIMER
+	int "Tickless hardware timer"
+	default 2
+	range 1 14
+	---help---
+		If the Tickless OS feature is enabled, then one clock must be
+		assigned to provided the timer needed by the OS.
+
+config STM32F7_TICKLESS_CHANNEL
+	int "Tickless timer channel"
+	default 1
+	range 1 4
+	---help---
+		If the Tickless OS feature is enabled, the one clock must be
+		assigned to provided the free-running timer needed by the OS
+		and one channel on that clock is needed to handle intervals.
+
+endif # SCHED_TICKLESS
+
 config STM32F7_TIM1_PWM
 	bool "TIM1 PWM"
 	default n
diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs
index 1c9dd1a0364..387dcda7d19 100644
--- a/arch/arm/src/stm32f7/Make.defs
+++ b/arch/arm/src/stm32f7/Make.defs
@@ -89,11 +89,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
@@ -104,10 +102,16 @@ endif
 CHIP_ASRCS  =
 CHIP_CSRCS  = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c
 CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_serial.c
-CHIP_CSRCS += stm32_start.c stm32_capture.c stm32_flash.c
+CHIP_CSRCS += stm32_start.c stm32_capture.c stm32_uid.c
 
 ifneq ($(CONFIG_SCHED_TICKLESS),y)
 CHIP_CSRCS += stm32_timerisr.c
+else
+CHIP_CSRCS += stm32_tickless.c
+endif
+
+ifeq ($(CONFIG_STM32F7_PROGMEM),y)
+CHIP_CSRCS += stm32_flash.c
 endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
@@ -226,3 +230,8 @@ endif
 ifeq ($(CONFIG_STM32F7_CAN),y)
 CHIP_CSRCS += stm32_can.c
 endif
+
+ifeq ($(CONFIG_PWM),y)
+CHIP_CSRCS += stm32_pwm.c
+endif
+
diff --git a/arch/arm/src/stm32f7/chip.h b/arch/arm/src/stm32f7/chip.h
index 4893f4a6447..192f9d70be6 100644
--- a/arch/arm/src/stm32f7/chip.h
+++ b/arch/arm/src/stm32f7/chip.h
@@ -48,8 +48,8 @@
 
 #include 
 #include 
-#include "chip/stm32_pinmap.h"
-#include "chip/stm32_memorymap.h"
+#include "hardware/stm32_pinmap.h"
+#include "hardware/stm32_memorymap.h"
 
 /* If the common ARMv7-M vector handling logic is used, then it expects the
  * following definition in this file that provides the number of supported external
diff --git a/arch/arm/src/stm32f7/chip/stm32_adc.h b/arch/arm/src/stm32f7/hardware/stm32_adc.h
similarity index 89%
rename from arch/arm/src/stm32f7/chip/stm32_adc.h
rename to arch/arm/src/stm32f7/hardware/stm32_adc.h
index 9bf8e1940f1..68e7982501c 100644
--- a/arch/arm/src/stm32f7/chip/stm32_adc.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_adc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_adc.h
+ * arch/arm/src/stm32f7/hardware/stm32_adc.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ADC_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ADC_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_ADC_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_ADC_H
 
 /****************************************************************************************************
  * Included Files
@@ -45,12 +45,12 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
-#  include "chip/stm32f72xx73xx_adc.h"
+#  include "hardware/stm32f72xx73xx_adc.h"
 #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
     defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
-#  include "chip/stm32f74xx77xx_adc.h"
+#  include "hardware/stm32f74xx77xx_adc.h"
 #else
 #  error "Unsupported STM32 F7 sub family"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ADC_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_ADC_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_can.h b/arch/arm/src/stm32f7/hardware/stm32_can.h
similarity index 94%
rename from arch/arm/src/stm32f7/chip/stm32_can.h
rename to arch/arm/src/stm32f7/hardware/stm32_can.h
index 8de35e9f19c..6cd945d04bb 100644
--- a/arch/arm/src/stm32f7/chip/stm32_can.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_can.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32_can.h
+ * arch/arm/src/stm32f7/hardware/stm32_can.h
  *
  *   Copyright (C) 2009, 2011, 2013, 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F7_CAN_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F7_CAN_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F7_CAN_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F7_CAN_H
 
 /************************************************************************************
  * Included Files
@@ -59,14 +59,7 @@
 #define CAN_RXMBOX1 0
 #define CAN_RXMBOX2 1
 
-/* Number of filters depends on silicon */
-
-#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || \
-    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F4XXX)
 #  define CAN_NFILTERS 28
-#else
-#  define CAN_NFILTERS 14
-#endif
 
 /* Register Offsets *****************************************************************/
 
@@ -503,50 +496,28 @@
 /* CAN filter master register */
 
 #define CAN_FMR_FINIT             (1 << 0)  /* Bit 0: Filter Init Mode */
-#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
 #  define CAN_FMR_CAN2SB_SHIFT    (8)       /* Bits 13-8: CAN2 start bank */
 #  define CAN_FMR_CAN2SB_MASK     (0x3f << CAN_FMR_CAN2SB_SHIFT)
-#endif
 
 /* CAN filter mode register */
 
-#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
 #  define CAN_FM1R_FBM_SHIFT      (0)      /* Bits 13:0: Filter Mode */
 #  define CAN_FM1R_FBM_MASK       (0x3fff << CAN_FM1R_FBM_SHIFT)
-#else
-#  define CAN_FM1R_FBM_SHIFT      (0)      /* Bits 27:0: Filter Mode */
-#  define CAN_FM1R_FBM_MASK       (0x0fffffff << CAN_FM1R_FBM_SHIFT)
-#endif
 
 /* CAN filter scale register */
 
-#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
 #  define CAN_FS1R_FSC_SHIFT      (0)      /* Bits 13:0: Filter Scale Configuration */
 #  define CAN_FS1R_FSC_MASK       (0x3fff << CAN_FS1R_FSC_SHIFT)
-#else
-#  define CAN_FS1R_FSC_SHIFT      (0)      /* Bits 27:0: Filter Scale Configuration */
-#  define CAN_FS1R_FSC_MASK       (0x0fffffff << CAN_FS1R_FSC_SHIFT)
-#endif
 
 /* CAN filter FIFO assignment register */
 
-#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
 #  define CAN_FFA1R_FFA_SHIFT     (0)      /* Bits 13:0: Filter FIFO Assignment */
 #  define CAN_FFA1R_FFA_MASK      (0x3fff << CAN_FFA1R_FFA_SHIFT)
-#else
-#  define CAN_FFA1R_FFA_SHIFT     (0)      /* Bits 27:0: Filter FIFO Assignment */
-#  define CAN_FFA1R_FFA_MASK      (0x0fffffff << CAN_FFA1R_FFA_SHIFT)
-#endif
 
 /* CAN filter activation register */
 
-#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
 #  define CAN_FA1R_FACT_SHIFT     (0)      /* Bits 13:0: Filter Active */
 #  define CAN_FA1R_FACT_MASK      (0x3fff << CAN_FA1R_FACT_SHIFT)
-#else
-#  define CAN_FA1R_FACT_SHIFT     (0)      /* Bits 27:0: Filter Active */
-#  define CAN_FA1R_FACT_MASK      (0x0fffffff << CAN_FA1R_FACT_SHIFT)
-#endif
 
 /************************************************************************************
  * Public Types
@@ -560,4 +531,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_CAN_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_CAN_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_dbgmcu.h b/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h
similarity index 86%
rename from arch/arm/src/stm32f7/chip/stm32_dbgmcu.h
rename to arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h
index 4f4d348baf7..4c2720b7ad9 100644
--- a/arch/arm/src/stm32f7/chip/stm32_dbgmcu.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_dbgmcu.h
+ * arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h
  *
  *   Copyright (C) 2016, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DBGMCU_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DBGMCU_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_DBGMCU_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_DBGMCU_H
 
 /****************************************************************************
  * Included Files
@@ -45,13 +45,13 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
-#  include "chip/stm32f72xx73xx_dbgmcu.h"
+#  include "hardware/stm32f72xx73xx_dbgmcu.h"
 #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
-#  include "chip/stm32f74xx75xx_dbgmcu.h"
+#  include "hardware/stm32f74xx75xx_dbgmcu.h"
 #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
-#  include "chip/stm32f76xx77xx_dbgmcu.h"
+#  include "hardware/stm32f76xx77xx_dbgmcu.h"
 #else
 #  error "Unsupported STM32 F7 part"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DBGMCU_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_DBGMCU_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_dma.h b/arch/arm/src/stm32f7/hardware/stm32_dma.h
similarity index 87%
rename from arch/arm/src/stm32f7/chip/stm32_dma.h
rename to arch/arm/src/stm32f7/hardware/stm32_dma.h
index 2b9bcfeffd7..a2f54cdbe67 100644
--- a/arch/arm/src/stm32f7/chip/stm32_dma.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_dma.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_dma.h
+ * arch/arm/src/stm32f7/hardware/stm32_dma.h
  *
  *   Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DMA_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DMA_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_DMA_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_DMA_H
 
 /************************************************************************************
  * Included Files
@@ -45,13 +45,13 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
-#  include "chip/stm32f72xx73xx_dma.h"
+#  include "hardware/stm32f72xx73xx_dma.h"
 #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
-#  include "chip/stm32f74xx75xx_dma.h"
+#  include "hardware/stm32f74xx75xx_dma.h"
 #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
-#  include "chip/stm32f76xx77xx_dma.h"
+#  include "hardware/stm32f76xx77xx_dma.h"
 #else
 #  error "Unsupported STM32 F7 part"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DMA_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_DMA_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_dma2d.h b/arch/arm/src/stm32f7/hardware/stm32_dma2d.h
similarity index 98%
rename from arch/arm/src/stm32f7/chip/stm32_dma2d.h
rename to arch/arm/src/stm32f7/hardware/stm32_dma2d.h
index 69d3a86d94a..b7244ca6084 100644
--- a/arch/arm/src/stm32f7/chip/stm32_dma2d.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_dma2d.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_dma2d.h
+ * arch/arm/src/stm32f7/hardware/stm32_dma2d.h
  *
  *   Copyright (C) 2014-2015 Marco Krahl. All rights reserved.
  *   Author: Marco Krahl 
@@ -33,15 +33,15 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DMA2D_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DMA2D_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_DMA2D_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_DMA2D_H
 
 /****************************************************************************
  * Included Files
  ****************************************************************************/
 
 #include 
-#include "chip/stm32_memorymap.h"
+#include "hardware/stm32_memorymap.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -247,4 +247,4 @@
  * Public Types
  ****************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DMA2D_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_DMA2D_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_ethernet.h b/arch/arm/src/stm32f7/hardware/stm32_ethernet.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32_ethernet.h
rename to arch/arm/src/stm32f7/hardware/stm32_ethernet.h
index dfb3a34745c..f8133be7bce 100644
--- a/arch/arm/src/stm32f7/chip/stm32_ethernet.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_ethernet.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_ethernet.h
+ * arch/arm/src/stm32f7/hardware/stm32_ethernet.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ETHERNET_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ETHERNET_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_ETHERNET_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_ETHERNET_H
 
 /****************************************************************************************************
  * Included Files
@@ -808,5 +808,5 @@ struct eth_rxdesc_s
 
 #endif /* __ASSEMBLY__ */
 #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_ETHERNET_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_ETHERNET_H */
 
diff --git a/arch/arm/src/stm32f7/chip/stm32_exti.h b/arch/arm/src/stm32f7/hardware/stm32_exti.h
similarity index 96%
rename from arch/arm/src/stm32f7/chip/stm32_exti.h
rename to arch/arm/src/stm32f7/hardware/stm32_exti.h
index e7de6b6953e..6b184228eb4 100644
--- a/arch/arm/src/stm32f7/chip/stm32_exti.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_exti.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_exti.h
+ * arch/arm/src/stm32f7/hardware/stm32_exti.h
  *
  *   Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_EXTI_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_EXTI_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_EXTI_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_EXTI_H
 
 /************************************************************************************
  * Included Files
@@ -132,4 +132,4 @@
 #define EXTI_PR_MASK             STM32_EXTI_MASK
 
 #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_EXTI_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_EXTI_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_flash.h b/arch/arm/src/stm32f7/hardware/stm32_flash.h
similarity index 87%
rename from arch/arm/src/stm32f7/chip/stm32_flash.h
rename to arch/arm/src/stm32f7/hardware/stm32_flash.h
index 91554fe44b3..0081c43773a 100644
--- a/arch/arm/src/stm32f7/chip/stm32_flash.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_flash.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_flash.h
+ * arch/arm/src/stm32f7/hardware/stm32_flash.h
  *
  *   Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_FLASH_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_FLASH_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_FLASH_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_FLASH_H
 
 /************************************************************************************
  * Included Files
@@ -45,13 +45,13 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
-#  include "chip/stm32f72xx73xx_flash.h"
+#  include "hardware/stm32f72xx73xx_flash.h"
 #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
-#  include "chip/stm32f74xx75xx_flash.h"
+#  include "hardware/stm32f74xx75xx_flash.h"
 #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
-#  include "chip/stm32f76xx77xx_flash.h"
+#  include "hardware/stm32f76xx77xx_flash.h"
 #else
 #  error "Unsupported STM32 F7 part"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_FLASH_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_FLASH_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_gpio.h b/arch/arm/src/stm32f7/hardware/stm32_gpio.h
similarity index 87%
rename from arch/arm/src/stm32f7/chip/stm32_gpio.h
rename to arch/arm/src/stm32f7/hardware/stm32_gpio.h
index 1d6478e59e4..db3a5926863 100644
--- a/arch/arm/src/stm32f7/chip/stm32_gpio.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_gpio.h
+ * arch/arm/src/stm32f7/hardware/stm32_gpio.h
  *
  *   Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_GPIO_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_GPIO_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_GPIO_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -45,13 +45,13 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
-#  include "chip/stm32f72xx73xx_gpio.h"
+#  include "hardware/stm32f72xx73xx_gpio.h"
 #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
-#  include "chip/stm32f74xx75xx_gpio.h"
+#  include "hardware/stm32f74xx75xx_gpio.h"
 #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
-#  include "chip/stm32f76xx77xx_gpio.h"
+#  include "hardware/stm32f76xx77xx_gpio.h"
 #else
 #  error "Unsupported STM32 F7 part"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_GPIO_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_GPIO_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_i2c.h b/arch/arm/src/stm32f7/hardware/stm32_i2c.h
similarity index 90%
rename from arch/arm/src/stm32f7/chip/stm32_i2c.h
rename to arch/arm/src/stm32f7/hardware/stm32_i2c.h
index b1c295c196a..52eb1d2550f 100644
--- a/arch/arm/src/stm32f7/chip/stm32_i2c.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_i2c.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_i2c.h
+ * arch/arm/src/stm32f7/hardware/stm32_i2c.h
  *
  *   Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_I2C_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_I2C_H
 
 /************************************************************************************
  * Included Files
@@ -48,9 +48,9 @@
 #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \
     defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
     defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
-#  include "chip/stm32f74xx77xx_i2c.h"
+#  include "hardware/stm32f74xx77xx_i2c.h"
 #else
 #  error "Unsupported STM32 F7 sub family"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_I2C_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_I2C_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_ltdc.h b/arch/arm/src/stm32f7/hardware/stm32_ltdc.h
similarity index 98%
rename from arch/arm/src/stm32f7/chip/stm32_ltdc.h
rename to arch/arm/src/stm32f7/hardware/stm32_ltdc.h
index 1bac6074874..c26cf68103c 100644
--- a/arch/arm/src/stm32f7/chip/stm32_ltdc.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_ltdc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_ltdc.h
+ * arch/arm/src/stm32f7/hardware/stm32_ltdc.h
  *
  *   Copyright (C) 2013 Ken Pettit. All rights reserved.
  *   Author: Ken Pettit 
@@ -33,15 +33,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_LTDC_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_LTDC_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_LTDC_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_LTDC_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/stm32_memorymap.h"
+#include "hardware/stm32_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -378,4 +378,4 @@
  * Public Types
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_LTDC_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_LTDC_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32_memorymap.h
similarity index 86%
rename from arch/arm/src/stm32f7/chip/stm32_memorymap.h
rename to arch/arm/src/stm32f7/hardware/stm32_memorymap.h
index 591c482a5dd..6c8a138884f 100644
--- a/arch/arm/src/stm32f7/chip/stm32_memorymap.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_memorymap.h
+ * arch/arm/src/stm32f7/hardware/stm32_memorymap.h
  *
  *   Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -45,13 +45,13 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
-#  include "chip/stm32f72xx73xx_memorymap.h"
+#  include "hardware/stm32f72xx73xx_memorymap.h"
 #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
-#  include "chip/stm32f74xx75xx_memorymap.h"
+#  include "hardware/stm32f74xx75xx_memorymap.h"
 #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
-#  include "chip/stm32f76xx77xx_memorymap.h"
+#  include "hardware/stm32f76xx77xx_memorymap.h"
 #else
 #  error "Unsupported STM32 F7 memory map"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_otg.h b/arch/arm/src/stm32f7/hardware/stm32_otg.h
similarity index 80%
rename from arch/arm/src/stm32f7/chip/stm32_otg.h
rename to arch/arm/src/stm32f7/hardware/stm32_otg.h
index b69ef1a9ddc..c7a077dba59 100644
--- a/arch/arm/src/stm32f7/chip/stm32_otg.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_otg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f_otg.h
+ * arch/arm/src/stm32f7/hardware/stm32f_otg.h
  *
  *   Copyright (C) 2012, 2014-2016 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
@@ -35,8 +35,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_OTG_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_OTG_H
 
 /****************************************************************************************************
  * Included Files
@@ -149,6 +149,11 @@
 #define STM32_OTG_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
 #define STM32_OTG_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
 
+/* USB PHY OFFSET */
+
+#define STM32_USBPHYC_PLL1_OFFSET     0x0000 /* USBPHYC PLL1 control register */
+#define STM32_USBPHYC_TUNE_OFFSET     0x000c /* USBPHYC tuning control register */
+#define STM32_USBPHYC_LDO_OFFSET      0x0018 /* USBPHYC LDO control and status register */
 
 /* Register Addresses *******************************************************************************/
 
@@ -231,6 +236,11 @@
 #define STM32_OTG_DFIFO_DEP(n)        (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP_OFFSET(n))
 #define STM32_OTG_DFIFO_HCH(n)        (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH_OFFSET(n))
 
+/* USB PHY Registers */
+
+#define STM32_USBPHYC_PLL1            (STM32_USBPHYC_BASE+STM32_USBPHYC_PLL1_OFFSET)
+#define STM32_USBPHYC_TUNE            (STM32_USBPHYC_BASE+STM32_USBPHYC_TUNE_OFFSET)
+#define STM32_USBPHYC_LDO             (STM32_USBPHYC_BASE+STM32_USBPHYC_LDO_OFFSET)
 
 /* Register Bitfield Definitions ********************************************************************/
 /* Core global control and status registers */
@@ -250,56 +260,68 @@
 #define OTG_GOTGCTL_HSHNPEN           (1 << 10) /* Bit 10: host set HNP enable */
 #define OTG_GOTGCTL_DHNPEN            (1 << 11) /* Bit 11: Device HNP enabled */
 #define OTG_GOTGCTL_EHEN              (1 << 12) /* Bit 12: Embedded host enable */
-                                                  /* Bits 13-15: Reserved, must be kept at reset value */
+                                                /* Bits 13-15: Reserved, must be kept at reset value */
 #define OTG_GOTGCTL_CIDSTS            (1 << 16) /* Bit 16: Connector ID status */
 #define OTG_GOTGCTL_DBCT              (1 << 17) /* Bit 17: Long/short debounce time */
 #define OTG_GOTGCTL_ASVLD             (1 << 18) /* Bit 18: A-session valid */
 #define OTG_GOTGCTL_BSVLD             (1 << 19) /* Bit 19: B-session valid */
 #define OTG_GOTGCTL_OTGVER            (1 << 20) /* Bit 20: OTG version */
-                                                  /* Bits 21-31: Reserved, must be kept at reset value */
+                                                /* Bits 21-31: Reserved, must be kept at reset value */
 /* Interrupt register */
-                                                  /* Bits 1:0 Reserved, must be kept at reset value */
+                                                /* Bits 1:0 Reserved, must be kept at reset value */
 #define OTG_GOTGINT_SEDET             (1 << 2)  /* Bit 2: Session end detected */
-                                                  /* Bits 3-7: Reserved, must be kept at reset value */
+                                                /* Bits 3-7: Reserved, must be kept at reset value */
 #define OTG_GOTGINT_SRSSCHG           (1 << 8)  /* Bit 8: Session request success status change */
 #define OTG_GOTGINT_HNSSCHG           (1 << 9)  /* Bit 9: Host negotiation success status change */
-                                                  /* Bits 16:10 Reserved, must be kept at reset value */
+                                                /* Bits 16:10 Reserved, must be kept at reset value */
 #define OTG_GOTGINT_HNGDET            (1 << 17) /* Bit 17: Host negotiation detected */
 #define OTG_GOTGINT_ADTOCHG           (1 << 18) /* Bit 18: A-device timeout change */
 #define OTG_GOTGINT_DBCDNE            (1 << 19) /* Bit 19: Debounce done */
 #define OTG_GOTGINT_IDCHNG            (1 << 20) /* Bit 20: Change in ID pin input value */
-                                                  /* Bits 21-31: Reserved, must be kept at reset value */
+                                                /* Bits 21-31: Reserved, must be kept at reset value */
 
 /* AHB configuration register */
 
 #define OTG_GAHBCFG_GINTMSK           (1 << 0)  /* Bit 0: Global interrupt mask */
-                                                  /* Bits 1-6: Reserved, must be kept at reset value */
+                                                /* Bits 1-6: Reserved, must be kept at reset value */
 #define OTG_GAHBCFG_TXFELVL           (1 << 7)  /* Bit 7: TxFIFO empty level */
 #define OTG_GAHBCFG_PTXFELVL          (1 << 8)  /* Bit 8: Periodic TxFIFO empty level */
-                                                  /* Bits 20-31: Reserved, must be kept at reset value */
+                                                /* Bits 20-31: Reserved, must be kept at reset value */
 /* USB configuration register */
 
 #define OTG_GUSBCFG_TOCAL_SHIFT       (0)       /* Bits 0-2: FS timeout calibration */
 #define OTG_GUSBCFG_TOCAL_MASK        (7 << OTG_GUSBCFG_TOCAL_SHIFT)
-                                                  /* Bits 3-5: Reserved, must be kept at reset value */
+                                                /* Bits 3-5: Reserved, must be kept at reset value */
+#define OTG_GUSBCFG_ULPISEL           (1 << 4)  /* Bit 4: Select which high speed interface is to be used STM32F7x3 only*/
 #define OTG_GUSBCFG_PHYSEL            (1 << 6)  /* Bit 6: Full Speed serial transceiver select */
-                                                  /* Bit 7: Reserved, must be kept at reset value */
+                                                /* Bit 7: Reserved, must be kept at reset value */
 #define OTG_GUSBCFG_SRPCAP            (1 << 8)  /* Bit 8: SRP-capable */
 #define OTG_GUSBCFG_HNPCAP            (1 << 9)  /* Bit 9: HNP-capable */
 #define OTG_GUSBCFG_TRDT_SHIFT        (10)      /* Bits 10-13: USB turnaround time */
 #define OTG_GUSBCFG_TRDT_MASK         (15 << OTG_GUSBCFG_TRDT_SHIFT)
 #  define OTG_GUSBCFG_TRDT(n)         ((n) << OTG_GUSBCFG_TRDT_SHIFT)
-                                                  /* Bits 14-28: Reserved, must be kept at reset value */
+                                                /* Bit 14: Reserved, must be kept at reset value */
+#define OTG_GUSBCFG_PHYLPC            (1 << 15) /* Bit 15: PHY Low-power clock select for USB OTG HS */
+                                                /* Bit 16: Reserved, must be kept at reset value */
+#define OTG_GUSBCFG_ULPIFSLS          (1 << 17) /* Bit 17: ULPI FS/LS select for USB OTG HS */
+#define OTG_GUSBCFG_ULPIAR            (1 << 18) /* Bit 18: ULPI Auto-resume for USB OTG HS */
+#define OTG_GUSBCFG_ULPICSM           (1 << 19) /* Bit 19: ULPI clock SuspendM for USB OTG HS */
+#define OTG_GUSBCFG_ULPIEVBUSD        (1 << 20) /* Bit 20: ULPI External VBUS Drive for USB OTG HS */
+#define OTG_GUSBCFG_ULPIEVBUSI        (1 << 21) /* Bit 21: ULPI external VBUS indicator for USB OTG HS */
+#define OTG_GUSBCFG_TSDPS             (1 << 22) /* Bit 22: TermSel DLine pulsing selection for USB OTG HS */
+#define OTG_GUSBCFG_PCCI              (1 << 23) /* Bit 23: Indicator complement for USB OTG HS */
+#define OTG_GUSBCFG_PTCI              (1 << 24) /* Bit 24: Indicator pass through for USB OTG HS */
+#define OTG_GUSBCFG_ULPIIPD           (1 << 25) /* Bit 24: ULPI interface protect disable for USB OTG HS */
+                                                /* Bit 26-28: Reserved, must be kept at reset value */
 #define OTG_GUSBCFG_FHMOD             (1 << 29) /* Bit 29: Force host mode */
 #define OTG_GUSBCFG_FDMOD             (1 << 30) /* Bit 30: Force device mode */
-#define OTG_GUSBCFG_CTXPKT            (1 << 31) /* Bit 31: Corrupt Tx packet */
-                                                  /* Bits 20-31: Reserved, must be kept at reset value */
+                                                /* Bits 20-31: Reserved, must be kept at reset value */
 /* Reset register */
 
 #define OTG_GRSTCTL_CSRST             (1 << 0)  /* Bit 0: Core soft reset */
 #define OTG_GRSTCTL_HSRST             (1 << 1)  /* Bit 1: HCLK soft reset */
 #define OTG_GRSTCTL_FCRST             (1 << 2)  /* Bit 2: Host frame counter reset */
-                                                  /* Bit 3 Reserved, must be kept at reset value */
+                                                /* Bit 3 Reserved, must be kept at reset value */
 #define OTG_GRSTCTL_RXFFLSH           (1 << 4)  /* Bit 4: RxFIFO flush */
 #define OTG_GRSTCTL_TXFFLSH           (1 << 5)  /* Bit 5: TxFIFO flush */
 #define OTG_GRSTCTL_TXFNUM_SHIFT      (6)       /* Bits 6-10: TxFIFO number */
@@ -337,12 +359,15 @@
 #define OTG_GINT_IISOIXFR             (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */
 #define OTG_GINT_IISOOXFR             (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */
 #define OTG_GINT_IPXFR                (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */
-#define OTG_GINT_RES22                (1 << 22) /* Bits 22: Reserved, must be kept at reset value */
+#define OTG_GINT_RES22                (1 << 22) /* Bit 22: Reserved, must be kept at reset value */
+#define OTG_GINT_DATAFSUSP            (1 << 22) /* Bit 22: Data fetch suspended for USB OTG HS */
+#define OTG_GINT_RES23                (1 << 23) /* Bit 23: Reserved, must be kept at reset value */
 #define OTG_GINT_RSTDET               (1 << 23) /* Bit 23: Reset detected interrupt */
 #define OTG_GINT_HPRT                 (1 << 24) /* Bit 24: Host port interrupt */
 #define OTG_GINT_HC                   (1 << 25) /* Bit 25: Host channels interrupt */
 #define OTG_GINT_PTXFE                (1 << 26) /* Bit 26: Periodic TxFIFO empty */
 #define OTG_GINT_LPMINT               (1 << 27) /* Bit 27: LPM interrupt */
+#define OTG_GINT_RES27                (1 << 27) /* Bit 27: Reserved, must be kept at reset value */
 #define OTG_GINT_CIDSCHG              (1 << 28) /* Bit 28: Connector ID status change */
 #define OTG_GINT_DISC                 (1 << 29) /* Bit 29: Disconnect detected interrupt */
 #define OTG_GINT_SRQ                  (1 << 30) /* Bit 30: Session request/new session detected interrupt */
@@ -388,7 +413,7 @@
 #  define OTG_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTG_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */
 #define OTG_GRXSTSD_FRMNUM_SHIFT      (21)      /* Bits 21-24: Frame number */
 #define OTG_GRXSTSD_FRMNUM_MASK       (15 << OTG_GRXSTSD_FRMNUM_SHIFT)
-                                                  /* Bits 25-31: Reserved, must be kept at reset value */
+                                                /* Bits 25-31: Reserved, must be kept at reset value */
 /* Receive FIFO size register */
 
 #define OTG_GRXFSIZ_MASK              (0xffff)
@@ -431,13 +456,14 @@
 #  define OTG_HNPTXSTS_CHNUM_MASK     (15 << OTG_HNPTXSTS_CHNUM_SHIFT)
 #  define OTG_HNPTXSTS_EPNUM_SHIFT    (27)      /* Bits 27-30: Endpoint number */
 #  define OTG_HNPTXSTS_EPNUM_MASK     (15 << OTG_HNPTXSTS_EPNUM_SHIFT)
-                                                  /* Bit 31 Reserved, must be kept at reset value */
+                                                /* Bit 31 Reserved, must be kept at reset value */
 /* General core configuration register */
-                                                  /* Bits 0-15: Reserved, must be kept at reset value */
+                                                /* Bits 0-15: Reserved, must be kept at reset value */
 #define OTG_GCCFG_PWRDWN              (1 << 16) /* Bit 16: Power down */
-                                                  /* Bit 17 Reserved, must be kept at reset value */
+                                                /* Bit 17 Reserved, must be kept at reset value */
 #define OTG_GCCFG_VBDEN               (1 << 21) /* Bit 21: USB VBUS detection enable */
-                                                  /* Bits 22-31: Reserved, must be kept at reset value */
+#define OTG_GCCFG_PHYHSEN             (1 << 23) /* Bit 21: NOT In datasheet but in STMCube.. */
+                                                /* Bits 22-31: Reserved, must be kept at reset value */
 /* Core ID register  (32-bit product ID) */
 
 /* Host periodic transmit FIFO size register */
@@ -465,7 +491,7 @@
 #  define OTG_HCFG_FSLSPCS_LS48MHz    (1 << OTG_HCFG_FSLSPCS_SHIFT) /* LS host mode,  Select 48 MHz PHY clock frequency */
 #  define OTG_HCFG_FSLSPCS_LS6MHz     (2 << OTG_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */
 #define OTG_HCFG_FSLSS                (1 << 2)  /* Bit 2: FS- and LS-only support */
-                                                  /* Bits 31:3 Reserved, must be kept at reset value */
+                                                /* Bits 31:3 Reserved, must be kept at reset value */
 /* Host frame interval register */
 
 #define OTG_HFIR_MASK                 (0xffff)
@@ -514,7 +540,7 @@
 #define OTG_HPRT_PRES                 (1 << 6)  /* Bit 6:  Port resume */
 #define OTG_HPRT_PSUSP                (1 << 7)  /* Bit 7:  Port suspend */
 #define OTG_HPRT_PRST                 (1 << 8)  /* Bit 8:  Port reset */
-                                                  /* Bit 9:  Reserved, must be kept at reset value */
+                                                /* Bit 9:  Reserved, must be kept at reset value */
 #define OTG_HPRT_PLSTS_SHIFT          (10)      /* Bits 10-11: Port line status */
 #define OTG_HPRT_PLSTS_MASK           (3 << OTG_HPRT_PLSTS_SHIFT)
 #  define OTG_HPRT_PLSTS_DP           (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */
@@ -532,7 +558,7 @@
 #define OTG_HPRT_PSPD_MASK            (3 << OTG_HPRT_PSPD_SHIFT)
 #  define OTG_HPRT_PSPD_FS            (1 << OTG_HPRT_PSPD_SHIFT) /* Full speed */
 #  define OTG_HPRT_PSPD_LS            (2 << OTG_HPRT_PSPD_SHIFT) /* Low speed */
-                                                  /* Bits 19-31: Reserved, must be kept at reset value */
+                                                /* Bits 19-31: Reserved, must be kept at reset value */
 
 /* Host channel-n characteristics register */
 
@@ -543,7 +569,7 @@
 #define OTG_HCCHAR_EPDIR              (1 << 15) /* Bit 15: Endpoint direction */
 #  define OTG_HCCHAR_EPDIR_OUT        (0)
 #  define OTG_HCCHAR_EPDIR_IN         OTG_HCCHAR_EPDIR
-                                                  /* Bit 16 Reserved, must be kept at reset value */
+                                                /* Bit 16 Reserved, must be kept at reset value */
 #define OTG_HCCHAR_LSDEV              (1 << 17) /* Bit 17: Low-speed device */
 #define OTG_HCCHAR_EPTYP_SHIFT        (18)      /* Bits 18-19: Endpoint type */
 #define OTG_HCCHAR_EPTYP_MASK         (3 << OTG_HCCHAR_EPTYP_SHIFT)
@@ -563,7 +589,7 @@
 
 #define OTG_HCINT_XFRC                (1 << 0)  /* Bit 0:  Transfer completed */
 #define OTG_HCINT_CHH                 (1 << 1)  /* Bit 1:  Channel halted */
-                                                  /* Bit 2:  Reserved, must be kept at reset value */
+                                                /* Bit 2:  Reserved, must be kept at reset value */
 #define OTG_HCINT_STALL               (1 << 3)  /* Bit 3:  STALL response received interrupt */
 #define OTG_HCINT_NAK                 (1 << 4)  /* Bit 4:  NAK response received interrupt */
 #define OTG_HCINT_ACK                 (1 << 5)  /* Bit 5:  ACK response received/transmitted interrupt */
@@ -572,7 +598,7 @@
 #define OTG_HCINT_BBERR               (1 << 8)  /* Bit 8:  Babble error */
 #define OTG_HCINT_FRMOR               (1 << 9)  /* Bit 9:  Frame overrun */
 #define OTG_HCINT_DTERR               (1 << 10) /* Bit 10: Data toggle error */
-                                                  /* Bits 11-31 Reserved, must be kept at reset value */
+                                                /* Bits 11-31 Reserved, must be kept at reset value */
 /* Host channel-n interrupt register */
 
 #define OTG_HCTSIZ_XFRSIZ_SHIFT       (0)       /* Bits 0-18: Transfer size */
@@ -586,16 +612,18 @@
 #  define OTG_HCTSIZ_DPID_DATA1       (2 << OTG_HCTSIZ_DPID_SHIFT)
 #  define OTG_HCTSIZ_DPID_MDATA       (3 << OTG_HCTSIZ_DPID_SHIFT) /* Non-control */
 #  define OTG_HCTSIZ_PID_SETUP        (3 << OTG_HCTSIZ_DPID_SHIFT) /* Control */
-                                                  /* Bit 31 Reserved, must be kept at reset value */
+                                                /* Bit 31 Reserved, must be kept at reset value */
 /* Device-mode control and status registers */
 
 /* Device configuration register */
 
 #define OTG_DCFG_DSPD_SHIFT           (0)       /* Bits 0-1: Device speed */
 #define OTG_DCFG_DSPD_MASK            (3 << OTG_DCFG_DSPD_SHIFT)
+#  define OTG_DCFG_DSPD_HS            (0 << OTG_DCFG_DSPD_SHIFT) /* High Speed */
+#  define OTG_DCFG_DSPD_FS_USING_HS   (1 << OTG_DCFG_DSPD_SHIFT) /* Full speed using High Speed*/
 #  define OTG_DCFG_DSPD_FS            (3 << OTG_DCFG_DSPD_SHIFT) /* Full speed */
 #define OTG_DCFG_NZLSOHSK             (1 << 2)  /* Bit 2:  Non-zero-length status OUT handshake */
-                                                  /* Bit 3:  Reserved, must be kept at reset value */
+                                                /* Bit 3:  Reserved, must be kept at reset value */
 #define OTG_DCFG_DAD_SHIFT            (4)       /* Bits 4-10: Device address */
 #define OTG_DCFG_DAD_MASK             (0x7f << OTG_DCFG_DAD_SHIFT)
 #define OTG_DCFG_PFIVL_SHIFT          (11)      /* Bits 11-12: Periodic frame interval */
@@ -604,7 +632,7 @@
 #  define OTG_DCFG_PFIVL_85PCT        (1 << OTG_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */
 #  define OTG_DCFG_PFIVL_90PCT        (2 << OTG_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */
 #  define OTG_DCFG_PFIVL_95PCT        (3 << OTG_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */
-                                                  /* Bits 13-31 Reserved, must be kept at reset value */
+                                                /* Bits 13-31 Reserved, must be kept at reset value */
 /* Device control register */
 
 #define OTG_TESTMODE_DISABLED         (0) /* Test mode disabled */
@@ -631,42 +659,47 @@
 #define OTG_DCTL_SGONAK               (1 << 9)  /* Bit 9:  Set global OUT NAK */
 #define OTG_DCTL_CGONAK               (1 << 10) /* Bit 10: Clear global OUT NAK */
 #define OTG_DCTL_POPRGDNE             (1 << 11) /* Bit 11: Power-on programming done */
-                                                  /* Bits 12-31: Reserved, must be kept at reset value */
+                                                /* Bits 12-31: Reserved, must be kept at reset value */
 /* Device status register */
 
 #define OTG_DSTS_SUSPSTS              (1 << 0)  /* Bit 0: Suspend status */
 #define OTG_DSTS_ENUMSPD_SHIFT        (1)       /* Bits 1-2: Enumerated speed */
 #define OTG_DSTS_ENUMSPD_MASK         (3 << OTG_DSTS_ENUMSPD_SHIFT)
 #  define OTG_DSTS_ENUMSPD_FS         (3 << OTG_DSTS_ENUMSPD_MASK) /* Full speed */
-                                                  /* Bits 4-7: Reserved, must be kept at reset value */
+                                                /* Bits 4-7: Reserved, must be kept at reset value */
 #define OTG_DSTS_EERR                 (1 << 3)  /* Bit 3: Erratic error */
 #define OTG_DSTS_SOFFN_SHIFT          (8)       /* Bits 8-21: Frame number of the received SOF */
 #define OTG_DSTS_SOFFN_MASK           (0x3fff << OTG_DSTS_SOFFN_SHIFT)
 #define OTG_DSTS_SOFFN0               (1 << 8)  /* Bits 8: Frame number even/odd bit */
 #define OTG_DSTS_SOFFN_EVEN           0
 #define OTG_DSTS_SOFFN_ODD            OTG_DSTS_SOFFN0
-                                                  /* Bits 22-31: Reserved, must be kept at reset value */
+                                                /* Bits 22-31: Reserved, must be kept at reset value */
 /* Device IN endpoint common interrupt mask register */
 
 #define OTG_DIEPMSK_XFRCM             (1 << 0)  /* Bit 0: Transfer completed interrupt mask */
 #define OTG_DIEPMSK_EPDM              (1 << 1)  /* Bit 1: Endpoint disabled interrupt mask */
-                                                  /* Bit 2:  Reserved, must be kept at reset value */
+#define OTG_DIEPMSK_AHBERRM           (1 << 2)  /* Bit 2: AHB error mask for USB OTG HS */
 #define OTG_DIEPMSK_TOM               (1 << 3)  /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */
 #define OTG_DIEPMSK_ITTXFEMSK         (1 << 4)  /* Bit 4: IN token received when TxFIFO empty mask */
 #define OTG_DIEPMSK_INEPNMM           (1 << 5)  /* Bit 5: IN token received with EP mismatch mask */
 #define OTG_DIEPMSK_INEPNEM           (1 << 6)  /* Bit 6: IN endpoint NAK effective mask */
-                                                  /* Bits 7-31: Reserved, must be kept at reset value */
+                                                /* Bit 7: Reserved, must be kept at reset value */
+#define OTG_DIEPMSK_TXFURM            (1 << 8)  /* Bit 8: FIFO underrun mask */
+                                                /* Bits 9-12: Reserved, must be kept at reset value */
+#define OTG_DIEPMSK_NAKM              (1 << 13) /* Bit 13: NAK interrupt mask */
+                                                /* Bits 14-31: Reserved, must be kept at reset value */
+
 /* Device OUT endpoint common interrupt mask register */
 
 #define OTG_DOEPMSK_XFRCM             (1 << 0)  /* Bit 0: Transfer completed interrupt mask */
 #define OTG_DOEPMSK_EPDM              (1 << 1)  /* Bit 1: Endpoint disabled interrupt mask */
-                                                  /* Bit 2:  Reserved, must be kept at reset value */
+                                                /* Bit 2:  Reserved, must be kept at reset value */
 #define OTG_DOEPMSK_STUPM             (1 << 3)  /* Bit 3: SETUP phase done mask */
 #define OTG_DOEPMSK_OTEPDM            (1 << 4)  /* Bit 4: OUT token received when endpoint disabled mask */
-                                                  /* Bits 5-31: Reserved, must be kept at reset value */
+                                                /* Bits 5-31: Reserved, must be kept at reset value */
 /* Device all endpoints interrupt and All endpoints interrupt mask registers */
 
-#define OTG_DAINT_IEP_SHIFT           (0)      /* Bits 0-15: IN endpoint interrupt bits */
+#define OTG_DAINT_IEP_SHIFT           (0)       /* Bits 0-15: IN endpoint interrupt bits */
 #define OTG_DAINT_IEP_MASK            (0xffff << OTG_DAINT_IEP_SHIFT)
 #  define OTG_DAINT_IEP(n)            (1 << (n))
 #define OTG_DAINT_OEP_SHIFT           (16)      /* Bits 16-31: OUT endpoint interrupt bits */
@@ -693,20 +726,20 @@
 #  define OTG_DIEPCTL0_MPSIZ_32       (1 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 32 bytes */
 #  define OTG_DIEPCTL0_MPSIZ_16       (2 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 16 bytes */
 #  define OTG_DIEPCTL0_MPSIZ_8        (3 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 8 bytes */
-                                                  /* Bits 2-14: Reserved, must be kept at reset value */
+                                                /* Bits 2-14: Reserved, must be kept at reset value */
 #define OTG_DIEPCTL0_USBAEP           (1 << 15) /* Bit 15: USB active endpoint */
-                                                  /* Bit 16: Reserved, must be kept at reset value */
+                                                /* Bit 16: Reserved, must be kept at reset value */
 #define OTG_DIEPCTL0_NAKSTS           (1 << 17) /* Bit 17: NAK status */
 #define OTG_DIEPCTL0_EPTYP_SHIFT      (18)      /* Bits 18-19: Endpoint type */
 #define OTG_DIEPCTL0_EPTYP_MASK       (3 << OTG_DIEPCTL0_EPTYP_SHIFT)
 #  define OTG_DIEPCTL0_EPTYP_CTRL     (0 << OTG_DIEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */
-                                                  /* Bit 20: Reserved, must be kept at reset value */
+                                                /* Bit 20: Reserved, must be kept at reset value */
 #define OTG_DIEPCTL0_STALL            (1 << 21) /* Bit 21: STALL handshake */
 #define OTG_DIEPCTL0_TXFNUM_SHIFT     (22)      /* Bits 22-25: TxFIFO number */
 #define OTG_DIEPCTL0_TXFNUM_MASK      (15 << OTG_DIEPCTL0_TXFNUM_SHIFT)
 #define OTG_DIEPCTL0_CNAK             (1 << 26) /* Bit 26: Clear NAK */
 #define OTG_DIEPCTL0_SNAK             (1 << 27) /* Bit 27: Set NAK */
-                                                  /* Bits 28-29: Reserved, must be kept at reset value */
+                                                /* Bits 28-29: Reserved, must be kept at reset value */
 #define OTG_DIEPCTL0_EPDIS            (1 << 30) /* Bit 30: Endpoint disable */
 #define OTG_DIEPCTL0_EPENA            (1 << 31) /* Bit 31: Endpoint enable */
 
@@ -714,7 +747,7 @@
 
 #define OTG_DIEPCTL_MPSIZ_SHIFT       (0)       /* Bits 0-10: Maximum packet size */
 #define OTG_DIEPCTL_MPSIZ_MASK        (0x7ff << OTG_DIEPCTL_MPSIZ_SHIFT)
-                                                  /* Bits 11-14: Reserved, must be kept at reset value */
+                                                /* Bits 11-14: Reserved, must be kept at reset value */
 #define OTG_DIEPCTL_USBAEP            (1 << 15) /* Bit 15: USB active endpoint */
 #define OTG_DIEPCTL_EONUM             (1 << 16) /* Bit 16: Even/odd frame */
 #  define OTG_DIEPCTL_EVEN            (0)
@@ -728,7 +761,7 @@
 #  define OTG_DIEPCTL_EPTYP_ISOC      (1 << OTG_DIEPCTL_EPTYP_SHIFT) /* Isochronous */
 #  define OTG_DIEPCTL_EPTYP_BULK      (2 << OTG_DIEPCTL_EPTYP_SHIFT) /* Bulk */
 #  define OTG_DIEPCTL_EPTYP_INTR      (3 << OTG_DIEPCTL_EPTYP_SHIFT) /* Interrupt */
-                                                  /* Bit 20: Reserved, must be kept at reset value */
+                                                /* Bit 20: Reserved, must be kept at reset value */
 #define OTG_DIEPCTL_STALL             (1 << 21) /* Bit 21: STALL handshake */
 #define OTG_DIEPCTL_TXFNUM_SHIFT      (22)      /* Bits 22-25: TxFIFO number */
 #define OTG_DIEPCTL_TXFNUM_MASK       (15 << OTG_DIEPCTL_TXFNUM_SHIFT)
@@ -744,21 +777,21 @@
 
 #define OTG_DIEPINT_XFRC              (1 << 0)  /* Bit 0:  Transfer completed interrupt */
 #define OTG_DIEPINT_EPDISD            (1 << 1)  /* Bit 1:  Endpoint disabled interrupt */
-                                                  /* Bit 2:  Reserved, must be kept at reset value */
+                                                /* Bit 2:  Reserved, must be kept at reset value */
 #define OTG_DIEPINT_TOC               (1 << 3)  /* Bit 3:  Timeout condition */
 #define OTG_DIEPINT_ITTXFE            (1 << 4)  /* Bit 4:  IN token received when TxFIFO is empty */
-                                                  /* Bit 5:  Reserved, must be kept at reset value */
+                                                /* Bit 5:  Reserved, must be kept at reset value */
 #define OTG_DIEPINT_INEPNE            (1 << 6)  /* Bit 6:  IN endpoint NAK effective */
 #define OTG_DIEPINT_TXFE              (1 << 7)  /* Bit 7:  Transmit FIFO empty */
-                                                  /* Bits 8-31: Reserved, must be kept at reset value */
+                                                /* Bits 8-31: Reserved, must be kept at reset value */
 /* Device IN endpoint 0 transfer size register */
 
 #define OTG_DIEPTSIZ0_XFRSIZ_SHIFT    (0)       /* Bits 0-6: Transfer size */
 #define OTG_DIEPTSIZ0_XFRSIZ_MASK     (0x7f << OTG_DIEPTSIZ0_XFRSIZ_SHIFT)
-                                                  /* Bits 7-18: Reserved, must be kept at reset value */
+                                                /* Bits 7-18: Reserved, must be kept at reset value */
 #define OTG_DIEPTSIZ0_PKTCNT_SHIFT    (19)      /* Bits 19-20: Packet count */
 #define OTG_DIEPTSIZ0_PKTCNT_MASK     (3 << OTG_DIEPTSIZ0_PKTCNT_SHIFT)
-                                                  /* Bits 21-31: Reserved, must be kept at reset value */
+                                                /* Bits 21-31: Reserved, must be kept at reset value */
 /* Device IN endpoint n transfer size register */
 
 #define OTG_DIEPTSIZ_XFRSIZ_SHIFT     (0)       /* Bits 0-18: Transfer size */
@@ -767,7 +800,7 @@
 #define OTG_DIEPTSIZ_PKTCNT_MASK      (0x3ff << OTG_DIEPTSIZ_PKTCNT_SHIFT)
 #define OTG_DIEPTSIZ_MCNT_SHIFT       (29)      /* Bits 29-30: Multi count */
 #define OTG_DIEPTSIZ_MCNT_MASK        (3 << OTG_DIEPTSIZ_MCNT_SHIFT)
-                                                  /* Bit 31: Reserved, must be kept at reset value */
+                                                /* Bit 31: Reserved, must be kept at reset value */
 /* Device OUT endpoint TxFIFO status register */
 
 #define OTG_DTXFSTS_MASK              (0xffff)
@@ -780,19 +813,19 @@
 #  define OTG_DOEPCTL0_MPSIZ_32       (1 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */
 #  define OTG_DOEPCTL0_MPSIZ_16       (2 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */
 #  define OTG_DOEPCTL0_MPSIZ_8        (3 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */
-                                                  /* Bits 2-14: Reserved, must be kept at reset value */
+                                                /* Bits 2-14: Reserved, must be kept at reset value */
 #define OTG_DOEPCTL0_USBAEP           (1 << 15) /* Bit 15: USB active endpoint */
-                                                  /* Bit 16: Reserved, must be kept at reset value */
+                                                /* Bit 16: Reserved, must be kept at reset value */
 #define OTG_DOEPCTL0_NAKSTS           (1 << 17) /* Bit 17: NAK status */
 #define OTG_DOEPCTL0_EPTYP_SHIFT      (18)      /* Bits 18-19: Endpoint type */
 #define OTG_DOEPCTL0_EPTYP_MASK       (3 << OTG_DOEPCTL0_EPTYP_SHIFT)
 #  define OTG_DOEPCTL0_EPTYP_CTRL     (0 << OTG_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */
 #define OTG_DOEPCTL0_SNPM             (1 << 20) /* Bit 20: Snoop mode */
 #define OTG_DOEPCTL0_STALL            (1 << 21) /* Bit 21: STALL handshake */
-                                                  /* Bits 22-25: Reserved, must be kept at reset value */
+                                                /* Bits 22-25: Reserved, must be kept at reset value */
 #define OTG_DOEPCTL0_CNAK             (1 << 26) /* Bit 26: Clear NAK */
 #define OTG_DOEPCTL0_SNAK             (1 << 27) /* Bit 27: Set NAK */
-                                                  /* Bits 28-29: Reserved, must be kept at reset value */
+                                                /* Bits 28-29: Reserved, must be kept at reset value */
 #define OTG_DOEPCTL0_EPDIS            (1 << 30) /* Bit 30: Endpoint disable */
 #define OTG_DOEPCTL0_EPENA            (1 << 31) /* Bit 31: Endpoint enable */
 
@@ -800,7 +833,7 @@
 
 #define OTG_DOEPCTL_MPSIZ_SHIFT       (0)       /* Bits 0-10: Maximum packet size */
 #define OTG_DOEPCTL_MPSIZ_MASK        (0x7ff << OTG_DOEPCTL_MPSIZ_SHIFT)
-                                                  /* Bits 11-14: Reserved, must be kept at reset value */
+                                                /* Bits 11-14: Reserved, must be kept at reset value */
 #define OTG_DOEPCTL_USBAEP            (1 << 15) /* Bit 15: USB active endpoint */
 #define OTG_DOEPCTL_DPID              (1 << 16) /* Bit 16: Endpoint data PID (interrupt/buld) */
 #  define OTG_DOEPCTL_DATA0           (0)
@@ -817,7 +850,7 @@
 #  define OTG_DOEPCTL_EPTYP_INTR      (3 << OTG_DOEPCTL_EPTYP_SHIFT) /* Interrupt */
 #define OTG_DOEPCTL_SNPM              (1 << 20) /* Bit 20: Snoop mode */
 #define OTG_DOEPCTL_STALL             (1 << 21) /* Bit 21: STALL handshake */
-                                                  /* Bits 22-25: Reserved, must be kept at reset value */
+                                                /* Bits 22-25: Reserved, must be kept at reset value */
 #define OTG_DOEPCTL_CNAK              (1 << 26) /* Bit 26: Clear NAK */
 #define OTG_DOEPCTL_SNAK              (1 << 27) /* Bit 27: Set NAK */
 #define OTG_DOEPCTL_SD0PID            (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */
@@ -831,22 +864,22 @@
 
 #define OTG_DOEPINT_XFRC              (1 << 0)  /* Bit 0: Transfer completed interrupt */
 #define OTG_DOEPINT_EPDISD            (1 << 1)  /* Bit 1: Endpoint disabled interrupt */
-                                                  /* Bit 2: Reserved, must be kept at reset value */
+                                                /* Bit 2: Reserved, must be kept at reset value */
 #define OTG_DOEPINT_SETUP             (1 << 3)  /* Bit 3: SETUP phase done */
 #define OTG_DOEPINT_OTEPDIS           (1 << 4)  /* Bit 4: OUT token received when endpoint disabled */
-                                                  /* Bit 5: Reserved, must be kept at reset value */
+                                                /* Bit 5: Reserved, must be kept at reset value */
 #define OTG_DOEPINT_B2BSTUP           (1 << 6)  /* Bit 6: Back-to-back SETUP packets received */
-                                                  /* Bits 7-31: Reserved, must be kept at reset value */
+                                                /* Bits 7-31: Reserved, must be kept at reset value */
 /* Device OUT endpoint-0 transfer size register */
 
 #define OTG_DOEPTSIZ0_XFRSIZ_SHIFT    (0)       /* Bits 0-6: Transfer size */
 #define OTG_DOEPTSIZ0_XFRSIZ_MASK     (0x7f << OTG_DOEPTSIZ0_XFRSIZ_SHIFT)
-                                                  /* Bits 7-18: Reserved, must be kept at reset value */
+                                                /* Bits 7-18: Reserved, must be kept at reset value */
 #define OTG_DOEPTSIZ0_PKTCNT          (1 << 19) /* Bit 19 PKTCNT: Packet count */
-                                                  /* Bits 20-28: Reserved, must be kept at reset value */
+                                                /* Bits 20-28: Reserved, must be kept at reset value */
 #define OTG_DOEPTSIZ0_STUPCNT_SHIFT   (29)      /* Bits 29-30: SETUP packet count */
 #define OTG_DOEPTSIZ0_STUPCNT_MASK    (3 << OTG_DOEPTSIZ0_STUPCNT_SHIFT)
-                                                  /* Bit 31: Reserved, must be kept at reset value */
+                                                /* Bit 31: Reserved, must be kept at reset value */
 /* Device OUT endpoint-n transfer size register */
 
 #define OTG_DOEPTSIZ_XFRSIZ_SHIFT     (0)       /* Bits 0-18: Transfer size */
@@ -866,8 +899,57 @@
 
 #define OTG_PCGCCTL_STPPCLK           (1 << 0)  /* Bit 0: Stop PHY clock */
 #define OTG_PCGCCTL_GATEHCLK          (1 << 1)  /* Bit 1: Gate HCLK */
-                                                  /* Bits 2-3: Reserved, must be kept at reset value */
+                                                /* Bits 2-3: Reserved, must be kept at reset value */
 #define OTG_PCGCCTL_PHYSUSP           (1 << 4)  /* Bit 4: PHY Suspended */
-                                                  /* Bits 5-31: Reserved, must be kept at reset value */
+                                                /* Bits 5-31: Reserved, must be kept at reset value */
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H */
+/* USB PHYC Registers */
+/* USBPHYC PLL1 control register */
+
+#define USBPHYC_PLL1_EN                 (1 << 0)  /* Bit 0: Enable the PLL1 inside PHY */
+#define USBPHYC_PLL1_SEL_SHIFT          (1)       /* Bits 1-3: Controls the PHY PLL1 input clock frequency selection */
+#define USBPHYC_PLL1_SEL_MASK           (7 << USBPHYC_PLL1SEL_SHIFT)
+#  define USBPHYC_PLL1_SEL_12MHz        (0 << USBPHYC_PLL1_SEL_SHIFT)  /* 12 MHz */
+#  define USBPHYC_PLL1_SEL_12_5MHz      (1 << USBPHYC_PLL1_SEL_SHIFT)  /* 12.5 MHz */
+#  define USBPHYC_PLL1_SEL_12_5bMHz     (2 << USBPHYC_PLL1_SEL_SHIFT)  /* 12.5 MHz */
+#  define USBPHYC_PLL1_SEL_16MHz        (3 << USBPHYC_PLL1_SEL_SHIFT)  /* 16 MHz */
+#  define USBPHYC_PLL1_SEL_24MHz        (4 << USBPHYC_PLL1_SEL_SHIFT)  /* 24 MHz */
+#  define USBPHYC_PLL1_SEL_25MHz        (5 << USBPHYC_PLL1_SEL_SHIFT)  /* 25 MHz */
+#  define USBPHYC_PLL1_SEL_25bMHz       (6 << USBPHYC_PLL1_SEL_SHIFT)  /* 25 MHz */
+
+/* USBPHYC tuning control register */
+
+#define USBPHYC_TUNE_INCURREN           (1 << 0)  /* Bit 0: Controls the current boosting function */
+#define USBPHYC_TUNE_INCURRINT          (1 << 1)  /* Bit 1: Controls PHY current boosting */
+#define USBPHYC_TUNE_LFSCAPEN           (1 << 2)  /* Bit 2: Enables the Low Full Speed feedback capacitor */
+#define USBPHYC_TUNE_HSDRVSLEW          (1 << 3)  /* Bit 3: Controls the HS driver slew rate */
+#define USBPHYC_TUNE_HSDRVDCLEV         (1 << 4)  /* Bit 4: Decreases the HS driver DC level */
+#define USBPHYC_TUNE_HSDRVDCCUR         (1 << 5)  /* Bit 5: Increases the HS Driver DC level. Not applicable
+                                                   *        during the HS Test J and Test K data transfer */
+#define USBPHYC_TUNE_HSDRVCURINCR       (1 << 6)  /* Bit 6: Enable the HS driver current increase feature */
+#define USBPHYC_TUNE_FSDRVRFADJ         (1 << 7)  /* Bit 7: Tuning pin to adjust the full speed rise/fall time */
+#define USBPHYC_TUNE_HSDRVRFRED         (1 << 8)  /* Bit 8: High Speed rise-fall reduction enable */
+#define USBPHYC_TUNE_HSDRVCHKITRM_SHIFT (9)       /* Bits 9-12 : HS Driver current trimming pins for choke compensation */
+#define USBPHYC_TUNE_HSDRVCHKITRM_MASK  (0xF << USBPHYC_TUNE_HSDRVCHKITRM_SHIFT)
+#define USBPHYC_TUNE_HSDRVCHKZTRM_SHIFT (13)       /* Bits 13-14 : Controls the PHY bus HS driver impedance tuning for choke  */
+#define USBPHYC_TUNE_HSDRVCHKZTRM_MASK  (3 << USBPHYC_TUNE_HSDRVCHKZTRM_SHIFT)
+#define USBPHYC_TUNE_SQLCHCTL_SHIFT     (15)       /* Bits 15-16 :  Adjust the squelch DC threshold value */
+#define USBPHYC_TUNE_SQLCHCTL_MASK      (3 << USBPHYC_TUNE_SQLCHCTL_SHIFT)
+#define USBPHYC_TUNE_HDRXGNEQEN         (1 << 17)  /* Bit 17: Enables the HS Rx Gain Equalizer */
+#define USBPHYC_TUNE_STAGSEL            (1 << 18)  /* Bit 18: HS Tx staggering enable */
+#define USBPHYC_TUNE_HSFALLPREEM        (1 << 19)  /* Bit 19: HS Fall time control of single ended signals during pre-emphasis */
+#define USBPHYC_TUNE_HSRXOFF_SHIFT      (20)       /* Bits 20-21 : HS Receiver Offset adjustment  */
+#define USBPHYC_TUNE_HSRXOFF_MASK       (3 << USBPHYC_TUNE_HSRXOFF_SHIFT)
+#define USBPHYC_TUNE_SHTCCTCTLPROT      (1 << 22)  /* Bit 22: Enables the short circuit protection circuitry in LS/FS driver */
+#define USBPHYC_TUNE_SQLBYP             (1 << 23)  /* Bit 23: This pin is used to bypass the squelch inter-locking circuitry */
+
+/* USBPHYC LDO control and status register */
+
+#define USBPHYC_LDO_USED                (1 << 0)  /* Bit 0: Indicates the presence of the LDO in the chip. */
+#define USBPHYC_LDO_STATUS              (1 << 1)  /* Bit 1: Monitors the status of the PHY's LDO. */
+
+/* It looks like they made a mistake, is it ENABLE or DISABLE? */
+
+#define USBPHYC_LDO_ENABLE             (1 << 2)  /* Bit 2: Controls disable of the High Speed PHY's LDO. */
+
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_OTG_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32_pinmap.h
similarity index 86%
rename from arch/arm/src/stm32f7/chip/stm32_pinmap.h
rename to arch/arm/src/stm32f7/hardware/stm32_pinmap.h
index a6d106b1f67..1fe28114ea3 100644
--- a/arch/arm/src/stm32f7/chip/stm32_pinmap.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_pinmap.h
+ * arch/arm/src/stm32f7/hardware/stm32_pinmap.h
  *
  *   Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PINMAP_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_PINMAP_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -45,14 +45,14 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
-#  include "chip/stm32f72xx73xx_pinmap.h"
+#  include "hardware/stm32f72xx73xx_pinmap.h"
 #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
-#  include "chip/stm32f74xx75xx_pinmap.h"
+#  include "hardware/stm32f74xx75xx_pinmap.h"
 #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
-#  include "chip/stm32f76xx77xx_pinmap.h"
+#  include "hardware/stm32f76xx77xx_pinmap.h"
 #else
 #  error "Unsupported STM32 F7 Pin map"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_PINMAP_H */
 
diff --git a/arch/arm/src/stm32f7/chip/stm32_pwr.h b/arch/arm/src/stm32f7/hardware/stm32_pwr.h
similarity index 87%
rename from arch/arm/src/stm32f7/chip/stm32_pwr.h
rename to arch/arm/src/stm32f7/hardware/stm32_pwr.h
index 080fd754961..91d325c2458 100644
--- a/arch/arm/src/stm32f7/chip/stm32_pwr.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_pwr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_pwr.h
+ * arch/arm/src/stm32f7/hardware/stm32_pwr.h
  *
  *   Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PWR_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PWR_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_PWR_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_PWR_H
 
 /************************************************************************************
  * Included Files
@@ -45,13 +45,13 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
-#  include "chip/stm32f72xx73xx_pwr.h"
+#  include "hardware/stm32f72xx73xx_pwr.h"
 #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
-#  include "chip/stm32f74xx75xx_pwr.h"
+#  include "hardware/stm32f74xx75xx_pwr.h"
 #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
-#  include "chip/stm32f76xx77xx_pwr.h"
+#  include "hardware/stm32f76xx77xx_pwr.h"
 #else
 #  error "Unsupported STM32 F7 part"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_PWR_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_PWR_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_qspi.h b/arch/arm/src/stm32f7/hardware/stm32_qspi.h
similarity index 98%
rename from arch/arm/src/stm32f7/chip/stm32_qspi.h
rename to arch/arm/src/stm32f7/hardware/stm32_qspi.h
index 652298fe0fa..61c84d2ea2f 100644
--- a/arch/arm/src/stm32f7/chip/stm32_qspi.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_qspi.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_qspi.h
+ * arch/arm/src/stm32f7/hardware/stm32_qspi.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: dev@ziggurat29.com
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F7_QSPI_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F7_QSPI_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F7_QSPI_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F7_QSPI_H
 
 /****************************************************************************************
  * Included Files
@@ -236,6 +236,6 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32L4_QSPI_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32L4_QSPI_H */
 
 
diff --git a/arch/arm/src/stm32f7/chip/stm32_rcc.h b/arch/arm/src/stm32f7/hardware/stm32_rcc.h
similarity index 87%
rename from arch/arm/src/stm32f7/chip/stm32_rcc.h
rename to arch/arm/src/stm32f7/hardware/stm32_rcc.h
index c4fa94a9337..4b360252b3c 100644
--- a/arch/arm/src/stm32f7/chip/stm32_rcc.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_rcc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_rcc.h
+ * arch/arm/src/stm32f7/hardware/stm32_rcc.h
  *
  *   Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_RCC_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_RCC_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_RCC_H
 
 /************************************************************************************
  * Included Files
@@ -45,13 +45,13 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
-#  include "chip/stm32f72xx73xx_rcc.h"
+#  include "hardware/stm32f72xx73xx_rcc.h"
 #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
-#  include "chip/stm32f74xx75xx_rcc.h"
+#  include "hardware/stm32f74xx75xx_rcc.h"
 #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
-#  include "chip/stm32f76xx77xx_rcc.h"
+#  include "hardware/stm32f76xx77xx_rcc.h"
 #else
 #  error "Unsupported STM32 F7 part"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_RCC_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_rng.h b/arch/arm/src/stm32f7/hardware/stm32_rng.h
similarity index 94%
rename from arch/arm/src/stm32f7/chip/stm32_rng.h
rename to arch/arm/src/stm32f7/hardware/stm32_rng.h
index 3f5351a074b..8278cab13b3 100644
--- a/arch/arm/src/stm32f7/chip/stm32_rng.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_rng.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_rng.h
+ * arch/arm/src/stm32f7/hardware/stm32_rng.h
  *
  *   Copyright (C) 2012 Max Holtzberg. All rights reserved.
  *   Author: Max Holtzberg 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32_RNG_H
-#define __ARCH_ARM_STC_STM32F7_CHIP_STM32_RNG_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_RNG_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_RNG_H
 
 /************************************************************************************
  * Included Files
@@ -74,4 +74,4 @@
 #define RNG_SR_CEIS               (1 << 5) /* Bit 5: Clock error interrupt status */
 #define RNG_SR_SEIS               (1 << 6) /* Bit 6: Seed error interrupt status */
 
-#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32_RNG_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_RNG_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_rtcc.h b/arch/arm/src/stm32f7/hardware/stm32_rtcc.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32_rtcc.h
rename to arch/arm/src/stm32f7/hardware/stm32_rtcc.h
index efc1428a565..08d8361ff74 100644
--- a/arch/arm/src/stm32f7/chip/stm32_rtcc.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_rtcc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_rtcc.h
+ * arch/arm/src/stm32f7/hardware/stm32_rtcc.h
  *
  *   Copyright (C) 2011-2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_RTCC_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_RTCC_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_RTCC_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_RTCC_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -402,4 +402,4 @@
 #define RTC_OR_RTC_ALARM_TYPE     (1 << 3) /* RTC_ALARM on PC13 output type */
 
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_RTCC_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_RTCC_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_sdmmc.h b/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h
similarity index 92%
rename from arch/arm/src/stm32f7/chip/stm32_sdmmc.h
rename to arch/arm/src/stm32f7/hardware/stm32_sdmmc.h
index cd890d29273..d59f452dd7f 100644
--- a/arch/arm/src/stm32f7/chip/stm32_sdmmc.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_sdmmc.h
+ * arch/arm/src/stm32f7/hardware/stm32_sdmmc.h
  *
  *   Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SDMMC_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SDMMC_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_SDMMC_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_SDMMC_H
 
 /************************************************************************************
  * Included Files
@@ -54,4 +54,4 @@
 #  error "Unsupported STM32 F7 part"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SDMMC_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_SDMMC_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_spi.h b/arch/arm/src/stm32f7/hardware/stm32_spi.h
similarity index 89%
rename from arch/arm/src/stm32f7/chip/stm32_spi.h
rename to arch/arm/src/stm32f7/hardware/stm32_spi.h
index 64db932c32e..45379fb6ce5 100644
--- a/arch/arm/src/stm32f7/chip/stm32_spi.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_spi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_spi.h
+ * arch/arm/src/stm32f7/hardware/stm32_spi.h
  *
  *   Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_SPI_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_SPI_H
 
 /************************************************************************************
  * Included Files
@@ -46,11 +46,11 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
-#  include "chip/stm32f72xx73xx_spi.h"
+#  include "hardware/stm32f72xx73xx_spi.h"
 #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
     defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
-#  include "chip/stm32f74xx77xx_spi.h"
+#  include "hardware/stm32f74xx77xx_spi.h"
 #else
 #  error "Unsupported STM32 F7 sub family"
 #endif
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_SPI_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32_syscfg.h
similarity index 86%
rename from arch/arm/src/stm32f7/chip/stm32_syscfg.h
rename to arch/arm/src/stm32f7/hardware/stm32_syscfg.h
index 8d0a6340c70..91e8054c1cb 100644
--- a/arch/arm/src/stm32f7/chip/stm32_syscfg.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_syscfg.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_syscfg.h
+ * arch/arm/src/stm32f7/hardware/stm32_syscfg.h
  *
  *   Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_SYSCFG_H
 
 /************************************************************************************
  * Included Files
@@ -45,13 +45,13 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
-#  include "chip/stm32f72xx73xx_syscfg.h"
+#  include "hardware/stm32f72xx73xx_syscfg.h"
 #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
-#  include "chip/stm32f74xx75xx_syscfg.h"
+#  include "hardware/stm32f74xx75xx_syscfg.h"
 #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
-#  include "chip/stm32f76xx77xx_syscfg.h"
+#  include "hardware/stm32f76xx77xx_syscfg.h"
 #else
 #  error "Unsupported STM32 F7 part"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_SYSCFG_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_tim.h b/arch/arm/src/stm32f7/hardware/stm32_tim.h
similarity index 87%
rename from arch/arm/src/stm32f7/chip/stm32_tim.h
rename to arch/arm/src/stm32f7/hardware/stm32_tim.h
index 672f97667a3..4a01d32033e 100644
--- a/arch/arm/src/stm32f7/chip/stm32_tim.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_tim.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_tim.h
+ * arch/arm/src/stm32f7/hardware/stm32_tim.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_TIM_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_TIM_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_TIM_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_TIM_H
 
 /************************************************************************************
  * Included Files
@@ -45,13 +45,13 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
-#  include "chip/stm32f72xx73xx_tim.h"
+#  include "hardware/stm32f72xx73xx_tim.h"
 #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
-#  include "chip/stm32f74xx75xx_tim.h"
+#  include "hardware/stm32f74xx75xx_tim.h"
 #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
-#  include "chip/stm32f76xx77xx_tim.h"
+#  include "hardware/stm32f76xx77xx_tim.h"
 #else
 #  error "Unsupported STM32 F7 sub family"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_TIM_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_TIM_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32_uart.h b/arch/arm/src/stm32f7/hardware/stm32_uart.h
similarity index 88%
rename from arch/arm/src/stm32f7/chip/stm32_uart.h
rename to arch/arm/src/stm32f7/hardware/stm32_uart.h
index c86940e0fc2..76f377544f5 100644
--- a/arch/arm/src/stm32f7/chip/stm32_uart.h
+++ b/arch/arm/src/stm32f7/hardware/stm32_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32_uart.h
+ * arch/arm/src/stm32f7/hardware/stm32_uart.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_UART_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_UART_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_UART_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_UART_H
 
 /************************************************************************************
  * Included Files
@@ -45,12 +45,12 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
-#  include "chip/stm32f72xx73xx_uart.h"
+#  include "hardware/stm32f72xx73xx_uart.h"
 #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
     defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
-#  include "chip/stm32f74xx77xx_uart.h"
+#  include "hardware/stm32f74xx77xx_uart.h"
 #else
 #  error "Unsupported STM32 F7 part"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_UART_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_adc.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f72xx73xx_adc.h
rename to arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h
index 55e12efb6b2..1ac70548431 100644
--- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_adc.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f72xx73xx_adc.h
+ * arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h
  *
  *   Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_ADC_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_ADC_H
 
 /****************************************************************************************************
  * Included Files
@@ -482,4 +482,4 @@
  * Public Function Prototypes
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_ADC_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_dbgmcu.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dbgmcu.h
similarity index 95%
rename from arch/arm/src/stm32f7/chip/stm32f72xx73xx_dbgmcu.h
rename to arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dbgmcu.h
index 5d6bda71b58..3a2036ae7d9 100644
--- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_dbgmcu.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dbgmcu.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f72xx73xx_dbgmcu.h
+ * arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dbgmcu.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XXDBGMCU_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XXDBGMCU_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XXDBGMCU_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XXDBGMCU_H
 
 /****************************************************************************
  * Included Files
@@ -105,4 +105,4 @@
 #define DBGMCU_APB2_TIM10STOP     (1 << 17)  /* Bit 17: TIM10 stopped when core is halted */
 #define DBGMCU_APB2_TIM11STOP     (1 << 18)  /* Bit 18: TIM11 stopped when core is halted */
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX74XXDBGMCU_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX74XXDBGMCU_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f72xx73xx_dma.h
rename to arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h
index 71e72fae7c9..fbe4af97331 100644
--- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_dma.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f72xx73xx_dma.h
+ * arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XXX73XX_DMA_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XXX73XX_DMA_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XXX73XX_DMA_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XXX73XX_DMA_H
 
 /************************************************************************************
  * Included Files
@@ -543,4 +543,4 @@
 #define DMAMAP_SDMMC2_2            STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11)
 
 #endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XXX73XX_DMA_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XXX73XX_DMA_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f72xx73xx_flash.h
rename to arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h
index 9de274e0ed5..f8805a839e7 100644
--- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_flash.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f72xx73xx_flash.h
+ * arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h
  *
  *   Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h
similarity index 98%
rename from arch/arm/src/stm32f7/chip/stm32f72xx73xx_gpio.h
rename to arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h
index 33d66d9b4c5..95c1eeb0711 100644
--- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_gpio.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f72xxx73xx_gpio.h
+ * arch/arm/src/stm32f7/hardware/stm32f72xxx73xx_gpio.h
  *
  *   Copyright (C) 2005 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_GPIO_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_GPIO_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_GPIO_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -401,4 +401,4 @@
 #define GPIO_AFRH15_MASK           (15 << GPIO_AFRH15_SHIFT)
 
 #endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_GPIO_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_GPIO_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h
similarity index 97%
rename from arch/arm/src/stm32f7/chip/stm32f72xx73xx_memorymap.h
rename to arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h
index 3d462cee858..a97916c69e6 100644
--- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_memorymap.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/chip/stm32f72xx73xx_memorymap.h
+ * arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h
  *
  *   Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XXX73XXX_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XXX73XXX_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XXX73XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XXX73XXX_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -202,4 +202,4 @@
 #define STM32_DEBUGMCU_BASE 0xe0042000
 
 #endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h
similarity index 98%
rename from arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h
rename to arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h
index c421d72e8e7..0bc2853378e 100644
--- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h
+ * arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h
  *
  *   Copyright (C) 2014-2015, 2017-2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F72XX73XX_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F72XX73XX_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -63,7 +63,7 @@
  *
  * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
  *
- * The driver will then automatically configre PA11 as the CAN1 RX pin.
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -485,10 +485,10 @@
 #define GPIO_OTGFS_ID         (GPIO_ALT|GPIO_PULLUP|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN10)
 #define GPIO_OTGFS_SOF        (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
 
-#define GPIO_OTGHS_DM         (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
-#define GPIO_OTGHS_DP         (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
-#define GPIO_OTGHS_ID         (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
-#define GPIO_OTGHS_SOF        (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_OTGHSFS_DM       (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_OTGHSFS_DP       (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_OTGHSFS_ID       (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_OTGHSFS_SOF      (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4)
 
 #define GPIO_OTGHS_ULPI_CK    (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN5)
 #define GPIO_OTGHS_ULPI_D0    (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3)
@@ -900,8 +900,11 @@
 #define GPIO_UART4_RTS        (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN15)
 #define GPIO_UART4_RX_1       (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
 #define GPIO_UART4_RX_2       (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
+#define GPIO_UART4_RX_3       (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN14)
+#define GPIO_UART4_RX_4       (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9)
 #define GPIO_UART4_TX_1       (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
 #define GPIO_UART4_TX_2       (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
+#define GPIO_UART4_TX_3       (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13)
 
 #define GPIO_UART5_CTS        (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN9)
 #define GPIO_UART5_RTS        (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN8)
@@ -934,4 +937,4 @@
 #define GPIO_UART8_TX         (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
 
 #endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F72XX73XX_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PINMAP_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h
similarity index 97%
rename from arch/arm/src/stm32f7/chip/stm32f72xx73xx_pwr.h
rename to arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h
index 6591d0feede..690b8af2873 100644
--- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_pwr.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f72xx73xx_pwr.h
+ * arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h
  *
  *   Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_PWR_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_PWR_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PWR_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PWR_H
 
 /************************************************************************************
  * Included Files
@@ -158,4 +158,4 @@
 #define PWR_CSR2_EWUP6           (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */
 
 #endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_PWR_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PWR_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f72xx73xx_rcc.h
rename to arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h
index 9b1607f7ace..1c3bab77cb0 100644
--- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_rcc.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f72xx73xx_rcc.h
+ * arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h
  *
  *   Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F72XX73XX_RCC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F72XX73XX_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_RCC_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_RCC_H
 
 /****************************************************************************************************
  * Included Files
@@ -666,4 +666,4 @@
 #  define RCC_DCKCFGR2_SDMMC2SEL_SYSCLK  (1 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT)  /* System clock is selected as SDMMC clock */
 
 #endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F74XX75XX_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_sdmmc.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_sdmmc.h
similarity index 98%
rename from arch/arm/src/stm32f7/chip/stm32f72xx73xx_sdmmc.h
rename to arch/arm/src/stm32f7/hardware/stm32f72xx73xx_sdmmc.h
index d6f3ad750a9..743ecea05cd 100644
--- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_sdmmc.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_sdmmc.h
@@ -1,4 +1,4 @@
- /* arch/arm/src/stm32f7/chip/stm32f72xx73xx_sdmmc.h
+ /* arch/arm/src/stm32f7/hardware/stm32f72xx73xx_sdmmc.h
  *
  *   Copyright (C) 2009, 2011-2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SDMMC_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SDMMC_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SDMMC_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SDMMC_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -221,4 +221,4 @@
 #define STM32_SDMMC_FIFOCNT_SHIFT             (0)
 #define STM32_SDMMC_FIFOCNT_MASK              (0x0ffffff << STM32_SDMMC_FIFOCNT_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SDMMC_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SDMMC_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_spi.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h
similarity index 98%
rename from arch/arm/src/stm32f7/chip/stm32f72xx73xx_spi.h
rename to arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h
index fb42f44bc0b..38fbe13d4ef 100644
--- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_spi.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f72xx73xx_spi.h
+ * arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SPI_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SPI_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SPI_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SPI_H
 
 /************************************************************************************
  * Included Files
@@ -252,4 +252,4 @@
 #define SPI_I2SPR_ODD             (1 << 8)  /* Bit 8: Odd factor for the prescaler */
 #define SPI_I2SPR_MCKOE           (1 << 9)  /* Bit 9: Master clock output enable */
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SPI_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SPI_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h
similarity index 97%
rename from arch/arm/src/stm32f7/chip/stm32f72xx73xx_syscfg.h
rename to arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h
index 4a341e1a917..d3e9bfacb5b 100644
--- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_syscfg.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f72xx74xx_syscfg.h
+ * arch/arm/src/stm32f7/hardware/stm32f72xx74xx_syscfg.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -159,4 +159,4 @@
 #define SYSCFG_CMPCR_READY            (1 << 8)  /* Bit 8: Compensation cell ready flag */
 
 #endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SYSCFG_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f72xx73xx_tim.h
rename to arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h
index 3e91342ea74..08dd4362668 100644
--- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_tim.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f72xx73xx_tim.h
+ * arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h
  *
  *   Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_TIM_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_TIM_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_TIM_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_TIM_H
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -1127,4 +1127,4 @@
 
 #define BTIM_EGR_UG               (1 << 0)  /* Bit 0: Update generation */
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_TIM_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_TIM_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h
similarity index 98%
rename from arch/arm/src/stm32f7/chip/stm32f72xx73xx_uart.h
rename to arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h
index 64d55996766..01c755a30ae 100644
--- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_uart.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xxf77xx_uart.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xxf77xx_uart.h
  *
  *   Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_UART_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_UART_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_UART_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_UART_H
 
 /************************************************************************************
  * Included Files
@@ -368,4 +368,4 @@
 #define USART_TDR_MASK            (0x1ff << USART_TDR_SHIFT)
 
 #endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_UART_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_dbgmcu.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dbgmcu.h
similarity index 96%
rename from arch/arm/src/stm32f7/chip/stm32f74xx75xx_dbgmcu.h
rename to arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dbgmcu.h
index 33842b73410..d88cef1fa09 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_dbgmcu.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dbgmcu.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xx75xx_dbgmcu.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dbgmcu.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XXDBGMCU_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XXDBGMCU_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XXDBGMCU_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XXDBGMCU_H
 
 /****************************************************************************
  * Included Files
@@ -109,4 +109,4 @@
 #define DBGMCU_APB2_TIM10STOP     (1 << 17)  /* Bit 17: TIM10 stopped when core is halted */
 #define DBGMCU_APB2_TIM11STOP     (1 << 18)  /* Bit 18: TIM11 stopped when core is halted */
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XXDBGMCU_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XXDBGMCU_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f74xx75xx_dma.h
rename to arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h
index 6b7fed23c16..ad8525a8e68 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_dma.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xx75xx_dma.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XX_DMA_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XX_DMA_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XXX75XX_DMA_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XXX75XX_DMA_H
 
 /************************************************************************************
  * Included Files
@@ -548,4 +548,4 @@
 #define DMAMAP_TIM8_COM            STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7)
 
 #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XX_DMA_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XXX75XX_DMA_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h
rename to arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h
index 08b62e191a4..2fdce0492b6 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h
similarity index 98%
rename from arch/arm/src/stm32f7/chip/stm32f74xx75xx_gpio.h
rename to arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h
index b8818f6e49b..3b28d3c3e72 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_gpio.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xxx75xx_gpio.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xxx75xx_gpio.h
  *
  *   Copyright (C) 2005 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_GPIO_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_GPIO_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_GPIO_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -400,4 +400,4 @@
 #define GPIO_AFRH15_MASK           (15 << GPIO_AFRH15_SHIFT)
 
 #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_GPIO_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_GPIO_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h
similarity index 98%
rename from arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h
rename to arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h
index eb98f260f97..86ce9d08f47 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm3fr2/chip/stm32f74xxx75xxx_memorymap.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xxx75xxx_memorymap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XXX_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XXX_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XXX75XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XXX75XXX_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -213,4 +213,4 @@
 #define STM32_DEBUGMCU_BASE 0xe0042000
 
 #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XXX_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XXX75XXX_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h
similarity index 97%
rename from arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h
rename to arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h
index c5cbbaee4a2..3836c399772 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F74XX75XX_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F74XX75XX_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -62,7 +62,7 @@
  *
  * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
  *
- * The driver will then automatically configre PA11 as the CAN1 RX pin.
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -726,26 +726,26 @@
 #define GPIO_OTGFS_ID         (GPIO_ALT|GPIO_PULLUP|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN10)
 #define GPIO_OTGFS_SOF        (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
 
-#define GPIO_OTGHS_DM         (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
-#define GPIO_OTGHS_DP         (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
-#define GPIO_OTGHS_ID         (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_OTGHSFS_DM       (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_OTGHSFS_DP       (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_OTGHSFS_ID       (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
 
 #define GPIO_OTGHS_SOF        (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4)
 
-#define GPIO_OTGHS_ULPI_CK    (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN5)
-#define GPIO_OTGHS_ULPI_D0    (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3)
-#define GPIO_OTGHS_ULPI_D1    (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
-#define GPIO_OTGHS_ULPI_D2    (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1)
-#define GPIO_OTGHS_ULPI_D3    (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10)
-#define GPIO_OTGHS_ULPI_D4    (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11)
-#define GPIO_OTGHS_ULPI_D5    (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN12)
-#define GPIO_OTGHS_ULPI_D6    (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN13)
-#define GPIO_OTGHS_ULPI_D7    (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN5)
-#define GPIO_OTGHS_ULPI_DIR_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2)
-#define GPIO_OTGHS_ULPI_DIR_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN11)
-#define GPIO_OTGHS_ULPI_NXT_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3)
-#define GPIO_OTGHS_ULPI_NXT_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN4)
-#define GPIO_OTGHS_ULPI_STP   (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_OTGHS_ULPI_CK    (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_OTGHS_ULPI_D0    (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_OTGHS_ULPI_D1    (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_OTGHS_ULPI_D2    (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_OTGHS_ULPI_D3    (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_OTGHS_ULPI_D4    (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_OTGHS_ULPI_D5    (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_OTGHS_ULPI_D6    (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_OTGHS_ULPI_D7    (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_OTGHS_ULPI_DIR_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_OTGHS_ULPI_DIR_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN11)
+#define GPIO_OTGHS_ULPI_NXT_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_OTGHS_ULPI_NXT_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN4)
+#define GPIO_OTGHS_ULPI_STP   (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN0)
 
 /* QuadSPI */
 
@@ -1184,4 +1184,4 @@
 #define GPIO_UART8_TX         (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
 
 #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F74XX75XX_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PINMAP_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h
similarity index 97%
rename from arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h
rename to arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h
index 547b555a92b..3b41c0cf918 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xx75xx_pwr.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_PWR_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_PWR_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PWR_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PWR_H
 
 /************************************************************************************
  * Included Files
@@ -157,4 +157,4 @@
 #define PWR_CSR2_EWUP6           (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */
 
 #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_PWR_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PWR_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h
rename to arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h
index 0a4ff1e5eeb..5494002b2ca 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h
  *
  *   Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F74XX75XX_RCC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F74XX75XX_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H
 
 /****************************************************************************************************
  * Included Files
@@ -709,4 +709,4 @@
 #  define RCC_DCKCFGR2_SDMMCSEL_SYSCLK  (1 << RCC_DCKCFGR2_SDMMCSEL_SHIFT)  /* System clock is selected as SDMMC clock */
 
 #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F74XX75XX_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h
similarity index 97%
rename from arch/arm/src/stm32f7/chip/stm32f74xx75xx_syscfg.h
rename to arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h
index 55f90c56276..8e30f19dc7a 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_syscfg.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xx75xx_syscfg.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -156,4 +156,4 @@
 #define SYSCFG_CMPCR_READY            (1 << 8)  /* Bit 8: Compensation cell ready flag */
 
 #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_SYSCFG_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h
rename to arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h
index 5fad1f5a781..c46d57ac5a5 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xx75xx_tim.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_TIM_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_TIM_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_TIM_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_TIM_H
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -1126,4 +1126,4 @@
 
 #define BTIM_EGR_UG               (1 << 0)  /* Bit 0: Update generation */
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_TIM_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_TIM_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h
rename to arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h
index 14685022a4e..da7338acf78 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xx77xx_adc.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_ADC_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_ADC_H
 
 /****************************************************************************************************
  * Included Files
@@ -481,4 +481,4 @@
  * Public Function Prototypes
  ****************************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_ADC_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_ADC_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h
rename to arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h
index 7e2d801dc90..f6a5d848c6a 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xx77xx_i2c.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -260,5 +260,5 @@
 
 #define I2C_TXDR_MASK             (0xff)
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_I2C_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_I2C_H */
 
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_sdmmc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_sdmmc.h
similarity index 98%
rename from arch/arm/src/stm32f7/chip/stm32f74xx77xx_sdmmc.h
rename to arch/arm/src/stm32f7/hardware/stm32f74xx77xx_sdmmc.h
index e0d52edc4ef..8999a12be84 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_sdmmc.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_sdmmc.h
@@ -1,4 +1,4 @@
- /* arch/arm/src/stm32f7/chip/stm32f74xx77xx_sdmmc.h
+ /* arch/arm/src/stm32f7/hardware/stm32f74xx77xx_sdmmc.h
  *
  *   Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SDMMC_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SDMMC_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_SDMMC_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_SDMMC_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -220,5 +220,5 @@
 #define STM32_SDMMC_FIFOCNT_SHIFT             (0)
 #define STM32_SDMMC_FIFOCNT_MASK              (0x0ffffff << STM32_SDMMC_FIFOCNT_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SDMMC_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_SDMMC_H */
 
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h
similarity index 98%
rename from arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h
rename to arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h
index fe8c899c564..98d1f84f4c8 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xx77xx_spi.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h
  *stm32f74xx77xx
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SPI_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SPI_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_SPI_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_SPI_H
 
 /************************************************************************************
  * Included Files
@@ -255,4 +255,4 @@
 #define SPI_I2SPR_ODD             (1 << 8)  /* Bit 8: Odd factor for the prescaler */
 #define SPI_I2SPR_MCKOE           (1 << 9)  /* Bit 9: Master clock output enable */
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SPI_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_SPI_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h
similarity index 98%
rename from arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h
rename to arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h
index 4d109bead0d..7e92d008260 100644
--- a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_uart.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xxf77xx_uart.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xxf77xx_uart.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_UART_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_UART_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_UART_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_UART_H
 
 /************************************************************************************
  * Included Files
@@ -368,4 +368,4 @@
 #define USART_TDR_MASK            (0x1ff << USART_TDR_SHIFT)
 
 #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_UART_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dbgmcu.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dbgmcu.h
similarity index 96%
rename from arch/arm/src/stm32f7/chip/stm32f76xx77xx_dbgmcu.h
rename to arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dbgmcu.h
index 6804dc25748..9c8c3375428 100644
--- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dbgmcu.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dbgmcu.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f76xx77xx_dbgmcu.h
+ * arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dbgmcu.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XXDBGMCU_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XXDBGMCU_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XXDBGMCU_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XXDBGMCU_H
 
 /****************************************************************************
  * Included Files
@@ -110,4 +110,4 @@
 #define DBGMCU_APB2_TIM10STOP     (1 << 17)  /* Bit 17: TIM10 stopped when core is halted */
 #define DBGMCU_APB2_TIM11STOP     (1 << 18)  /* Bit 18: TIM11 stopped when core is halted */
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XXDBGMCU_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XXDBGMCU_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h
rename to arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h
index d4d4eb0f893..f26469ccfeb 100644
--- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f76xx77xx_dma.h
+ * arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XX_DMA_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XX_DMA_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XXX77XX_DMA_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XXX77XX_DMA_H
 
 /************************************************************************************
  * Included Files
@@ -590,4 +590,4 @@
 #define DMAMAP_SDMMC2_2            STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11)
 
 #endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XX_DMA_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XXX77XX_DMA_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f76xx77xx_flash.h
rename to arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h
index 1e102040861..1a2065ae37e 100644
--- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_flash.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xx75xx_flash.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h
  *
  *   Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h
similarity index 98%
rename from arch/arm/src/stm32f7/chip/stm32f76xx77xx_gpio.h
rename to arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h
index 711dc0e1247..8bc226918d0 100644
--- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_gpio.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f76xxx77xx_gpio.h
+ * arch/arm/src/stm32f7/hardware/stm32f76xxx77xx_gpio.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_GPIO_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_GPIO_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_GPIO_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -401,4 +401,4 @@
 #define GPIO_AFRH15_MASK           (15 << GPIO_AFRH15_SHIFT)
 
 #endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_GPIO_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_GPIO_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h
similarity index 98%
rename from arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h
rename to arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h
index 0c3285dfd89..e7e609dec48 100644
--- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm3fr2/chip/stm32f76xxx77xxx_memorymap.h
+ * arch/arm/src/stm32f7/hardware/stm32f76xxx77xxx_memorymap.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XXX_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XXX77XXX_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XXX77XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XXX77XXX_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -220,4 +220,4 @@
 #define STM32_DEBUGMCU_BASE 0xe0042000
 
 #endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XXX75XXX_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XXX75XXX_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h
rename to arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h
index 38864dca6fd..2fbd4414e4c 100644
--- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h
+ * arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h
  *
  *   Copyright (C) 2016, 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -62,7 +62,7 @@
  *
  * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
  *
- * The driver will then automatically configre PA11 as the CAN1 RX pin.
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -834,9 +834,9 @@
 #define GPIO_OTGFS_ID         (GPIO_ALT|GPIO_PULLUP|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN10)
 #define GPIO_OTGFS_SOF        (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
 
-#define GPIO_OTGHS_DM         (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
-#define GPIO_OTGHS_DP         (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
-#define GPIO_OTGHS_ID         (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_OTGHSFS_DM       (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_OTGHSFS_DP       (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_OTGHSFS_ID       (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN12)
 
 #define GPIO_OTGHS_SOF        (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4)
 
@@ -993,6 +993,7 @@
 #define GPIO_SPI2_MOSI_1      (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15)
 #define GPIO_SPI2_MOSI_2      (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN3)
 #define GPIO_SPI2_MOSI_3      (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN3)
+#define GPIO_SPI2_MOSI_4      (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN1)
 #define GPIO_SPI2_NSS_1       (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN12)
 #define GPIO_SPI2_NSS_2       (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9)
 #define GPIO_SPI2_NSS_3       (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTI|GPIO_PIN0)
@@ -1346,4 +1347,4 @@
 #define GPIO_UART8_TX         (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
 
 #endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PINMAP_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h
similarity index 97%
rename from arch/arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h
rename to arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h
index c2f9f8a981a..ceb46ba8281 100644
--- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f76xx77xx_pwr.h
+ * arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_PWR_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_PWR_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PWR_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PWR_H
 
 /************************************************************************************
  * Included Files
@@ -156,4 +156,4 @@
 #define PWR_CSR2_EWUP6           (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */
 
 #endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_PWR_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PWR_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h
rename to arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h
index b7f73c27b5e..d33b448ed03 100644
--- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h
+ * arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_RCC_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_RCC_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_RCC_H
 
 /****************************************************************************************************
  * Included Files
@@ -740,4 +740,4 @@
 #  define RCC_DCKCFGR2_DSISEL_SYSCLK    (1 << RCC_DCKCFGR2_DSISEL_SHIFT)  /* System clock is selected as DSI clock */
 
 #endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F76XX77XX_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_RCC_H */
diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h
similarity index 97%
rename from arch/arm/src/stm32f7/chip/stm32f76xx77xx_syscfg.h
rename to arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h
index d3a469fe8a6..58dd0110075 100644
--- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_syscfg.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f76xx77xx_syscfg.h
+ * arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -177,4 +177,5 @@
 #define SYSCFG_CMPCR_READY            (1 << 8)  /* Bit 8: Compensation cell ready flag */
 
 #endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_SYSCFG_H */
+
diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h
similarity index 99%
rename from arch/arm/src/stm32f7/chip/stm32f76xx77xx_tim.h
rename to arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h
index bb6a657aa84..f2b14287098 100644
--- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_tim.h
+++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32f7/chip/stm32f76xx77xx_tim.h
+ * arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_TIM_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_TIM_H
+#ifndef __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_TIM_H
+#define __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_TIM_H
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -1144,4 +1144,4 @@
 
 #define BTIM_EGR_UG               (1 << 0)  /* Bit 0: Update generation */
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XX_TIM_H */
+#endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_TIM_H */
diff --git a/arch/arm/src/stm32f7/stm32_adc.h b/arch/arm/src/stm32f7/stm32_adc.h
index fa1c0bb2ec3..0a0794c18a5 100644
--- a/arch/arm/src/stm32f7/stm32_adc.h
+++ b/arch/arm/src/stm32f7/stm32_adc.h
@@ -46,7 +46,7 @@
 #include 
 #include 
 #include "chip.h"
-#include "chip/stm32_adc.h"
+#include "hardware/stm32_adc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c
index afc23bbe0d0..92749a054c0 100644
--- a/arch/arm/src/stm32f7/stm32_allocateheap.c
+++ b/arch/arm/src/stm32f7/stm32_allocateheap.c
@@ -57,7 +57,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/stm32_memorymap.h"
+#include "hardware/stm32_memorymap.h"
 #include "stm32_mpuinit.h"
 #include "stm32_dtcm.h"
 
diff --git a/arch/arm/src/stm32f7/stm32_bbsram.c b/arch/arm/src/stm32f7/stm32_bbsram.c
index ec62e9e3b67..091a3492184 100644
--- a/arch/arm/src/stm32f7/stm32_bbsram.c
+++ b/arch/arm/src/stm32f7/stm32_bbsram.c
@@ -131,10 +131,8 @@ static ssize_t stm32_bbsram_write(FAR struct file *filep,
                  FAR const char *buffer, size_t len);
 static int stm32_bbsram_ioctl(FAR struct file *filep, int cmd,
                  unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int     stm32_bbsram_poll(FAR struct file *filep, FAR struct pollfd *fds,
                  bool setup);
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
 static int     stm32_bbsram_unlink(FAR struct inode *inode);
 #endif
@@ -155,9 +153,7 @@ static const struct file_operations stm32_bbsram_fops =
   .write  = stm32_bbsram_write,
   .seek   = stm32_bbsram_seek,
   .ioctl  = stm32_bbsram_ioctl,
-#ifndef CONFIG_DISABLE_POLL
   .poll   = stm32_bbsram_poll,
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   .unlink = stm32_bbsram_unlink,
 #endif
@@ -546,7 +542,6 @@ static ssize_t stm32_bbsram_write(FAR struct file *filep,
  * Name: stm32_bbsram_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int stm32_bbsram_poll(FAR struct file *filep, FAR struct pollfd *fds,
                              bool setup)
 {
@@ -561,7 +556,6 @@ static int stm32_bbsram_poll(FAR struct file *filep, FAR struct pollfd *fds,
 
   return OK;
 }
-#endif
 
 /****************************************************************************
  * Name: stm32_bbsram_ioctl
diff --git a/arch/arm/src/stm32f7/stm32_can.c b/arch/arm/src/stm32f7/stm32_can.c
index af3d768c011..3a8dfdf137e 100644
--- a/arch/arm/src/stm32f7/stm32_can.c
+++ b/arch/arm/src/stm32f7/stm32_can.c
@@ -1987,14 +1987,10 @@ static int stm32can_filterinit(FAR struct stm32_can_s *priv)
 
   /* Assign half the filters to CAN1, half to CAN2 */
 
-#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \
-    defined(CONFIG_STM32_STM32F20XX) || \
-    defined(CONFIG_STM32_STM32F4XXX)
   regval  = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET);
   regval &= CAN_FMR_CAN2SB_MASK;
   regval |= (CAN_NFILTERS / 2) << CAN_FMR_CAN2SB_SHIFT;
   stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval);
-#endif
 
   /* Disable the filter */
 
diff --git a/arch/arm/src/stm32f7/stm32_can.h b/arch/arm/src/stm32f7/stm32_can.h
index 1667b022df0..52237109db2 100644
--- a/arch/arm/src/stm32f7/stm32_can.h
+++ b/arch/arm/src/stm32f7/stm32_can.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_can.h"
+#include "hardware/stm32_can.h"
 
 #include 
 
diff --git a/arch/arm/src/stm32f7/stm32_capture.h b/arch/arm/src/stm32f7/stm32_capture.h
index 4bc386e68bf..ab8db0ca040 100644
--- a/arch/arm/src/stm32f7/stm32_capture.h
+++ b/arch/arm/src/stm32f7/stm32_capture.h
@@ -44,7 +44,7 @@
 
 #include "chip.h"
 #include 
-#include "chip/stm32_tim.h"
+#include "hardware/stm32_tim.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32f7/stm32_dbgmcu.h b/arch/arm/src/stm32f7/stm32_dbgmcu.h
index 0aef4d5f0a0..f6d976b2b85 100644
--- a/arch/arm/src/stm32f7/stm32_dbgmcu.h
+++ b/arch/arm/src/stm32f7/stm32_dbgmcu.h
@@ -43,6 +43,6 @@
 
 #include 
 
-#include "chip/stm32_dbgmcu.h"
+#include "hardware/stm32_dbgmcu.h"
 
 #endif /* __ARCH_ARM_SRC_STM32F7_STM32_DBGMCU_H */
diff --git a/arch/arm/src/stm32f7/stm32_dma.h b/arch/arm/src/stm32f7/stm32_dma.h
index 567e2330647..20e52db04ef 100644
--- a/arch/arm/src/stm32f7/stm32_dma.h
+++ b/arch/arm/src/stm32f7/stm32_dma.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/stm32_dma.h"
+#include "hardware/stm32_dma.h"
 
 /* These definitions provide the bit encoding of the 'status' parameter passed to the
  * DMA callback function (see dma_callback_t).
diff --git a/arch/arm/src/stm32f7/stm32_dma2d.c b/arch/arm/src/stm32f7/stm32_dma2d.c
index 81dfbedbfbb..dfe587cc0bf 100644
--- a/arch/arm/src/stm32f7/stm32_dma2d.c
+++ b/arch/arm/src/stm32f7/stm32_dma2d.c
@@ -57,9 +57,9 @@
 
 #include "up_arch.h"
 #include "up_internal.h"
-#include "chip/stm32_ltdc.h"
-#include "chip/stm32_dma2d.h"
-#include "chip/stm32_dtcm.h"
+#include "hardware/stm32_ltdc.h"
+#include "hardware/stm32_dma2d.h"
+#include "hardware/stm32_dtcm.h"
 #include "stm32_dma2d.h"
 #include "stm32_ltdc.h"
 #include "stm32_gpio.h"
diff --git a/arch/arm/src/stm32f7/stm32_dtcm.h b/arch/arm/src/stm32f7/stm32_dtcm.h
index 905a5c2b42c..e7532add151 100644
--- a/arch/arm/src/stm32f7/stm32_dtcm.h
+++ b/arch/arm/src/stm32f7/stm32_dtcm.h
@@ -133,6 +133,18 @@ EXTERN struct mm_heap_s g_dtcm_heap;
 }
 #endif
 
+/****************************************************************************
+ * Name: dtcm_procfs_register
+ *
+ * Description:
+ *   Register the DTCM procfs file system entry
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32F7_DTCM_PROCFS
+int dtcm_procfs_register(void);
+#endif
+
 #endif /* __ASSEMBLY__ */
 #endif /* HAVE_DTCM_HEAP */
 #endif /* __ARCH_ARM_SRC_STM32F7_STM32_DTCM_H */
diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c
index 01e0e6ca447..e80ae02af2f 100644
--- a/arch/arm/src/stm32f7/stm32_ethernet.c
+++ b/arch/arm/src/stm32f7/stm32_ethernet.c
@@ -56,6 +56,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #if defined(CONFIG_NET_PKT)
 #  include 
@@ -64,11 +65,12 @@
 #include "up_internal.h"
 #include "barriers.h"
 
-#include "chip/stm32_syscfg.h"
-#include "chip/stm32_pinmap.h"
+#include "hardware/stm32_syscfg.h"
+#include "hardware/stm32_pinmap.h"
 #include "stm32_gpio.h"
 #include "stm32_rcc.h"
 #include "stm32_ethernet.h"
+#include "stm32_uid.h"
 
 #include 
 
@@ -4081,6 +4083,8 @@ static inline
 int stm32_ethinitialize(int intf)
 {
   struct stm32_ethmac_s *priv;
+  uint8_t uid[12];
+  uint64_t crc;
 
   ninfo("intf: %d\n", intf);
 
@@ -4110,6 +4114,20 @@ int stm32_ethinitialize(int intf)
   priv->txpoll       = wd_create();     /* Create periodic poll timer */
   priv->txtimeout    = wd_create();     /* Create TX timeout timer */
 
+  stm32_get_uniqueid(uid);
+  crc = crc64(uid, 12);
+
+  /* Specify as localy administrated address */
+
+  priv->dev.d_mac.ether.ether_addr_octet[0]  = (crc >> 0) | 0x02;
+  priv->dev.d_mac.ether.ether_addr_octet[0] &= ~0x1;
+
+  priv->dev.d_mac.ether.ether_addr_octet[1]  = crc >> 8;
+  priv->dev.d_mac.ether.ether_addr_octet[2]  = crc >> 16;
+  priv->dev.d_mac.ether.ether_addr_octet[3]  = crc >> 24;
+  priv->dev.d_mac.ether.ether_addr_octet[4]  = crc >> 32;
+  priv->dev.d_mac.ether.ether_addr_octet[5]  = crc >> 40;
+
   /* Configure GPIO pins to support Ethernet */
 
   stm32_ethgpioconfig(priv);
diff --git a/arch/arm/src/stm32f7/stm32_ethernet.h b/arch/arm/src/stm32f7/stm32_ethernet.h
index 2916232e26b..6c872545140 100644
--- a/arch/arm/src/stm32f7/stm32_ethernet.h
+++ b/arch/arm/src/stm32f7/stm32_ethernet.h
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/stm32_ethernet.h"
+#include "hardware/stm32_ethernet.h"
 
 #if STM32F7_NETHERNET > 0
 #ifndef __ASSEMBLY__
diff --git a/arch/arm/src/stm32f7/stm32_exti.h b/arch/arm/src/stm32f7/stm32_exti.h
index e6e4786d954..3e546d161e9 100644
--- a/arch/arm/src/stm32f7/stm32_exti.h
+++ b/arch/arm/src/stm32f7/stm32_exti.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_exti.h"
+#include "hardware/stm32_exti.h"
 
 /****************************************************************************
  * Public Data
diff --git a/arch/arm/src/stm32f7/stm32_flash.c b/arch/arm/src/stm32f7/stm32_flash.c
index 26619bb65dd..bff212e4410 100644
--- a/arch/arm/src/stm32f7/stm32_flash.c
+++ b/arch/arm/src/stm32f7/stm32_flash.c
@@ -60,7 +60,7 @@
 
 #include "barriers.h"
 
-#include "chip/stm32_flash.h"
+#include "hardware/stm32_flash.h"
 #include "up_arch.h"
 
 /****************************************************************************
@@ -73,20 +73,33 @@
 #define FLASH_OPTKEY2      0x4c5d6e7f
 #define FLASH_ERASEDVALUE  0xff
 
+#if CONFIG_STM32F7_PROGMEM_STARTBLOCK < 0 || \
+    CONFIG_STM32F7_PROGMEM_STARTBLOCK >= STM32_FLASH_NPAGES
+#  error "Invalid CONFIG_STM32F7_PROGMEM_STARTBLOCK"
+#endif
+
+#if CONFIG_STM32F7_PROGMEM_LASTBLOCK < 0
+#  undef CONFIG_STM32F7_PROGMEM_LASTBLOCK
+#  define CONFIG_STM32F7_PROGMEM_LASTBLOCK (STM32_FLASH_NPAGES-1)
+#endif
+
+#define PROGMEM_NBLOCKS \
+  (CONFIG_STM32F7_PROGMEM_LASTBLOCK - CONFIG_STM32F7_PROGMEM_STARTBLOCK + 1)
+
+#define PAGESIZE 256
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
 
 static sem_t g_sem = SEM_INITIALIZER(1);
 
+static const size_t page_sizes[STM32_FLASH_NPAGES] = STM32_FLASH_SIZES;
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
 
-static void up_waste(void)
-{
-}
-
 static void sem_lock(void)
 {
   int ret;
@@ -115,7 +128,6 @@ static void flash_unlock(void)
 {
   while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
     {
-      up_waste();
     }
 
   if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK)
@@ -132,6 +144,39 @@ static void flash_lock(void)
   modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK);
 }
 
+static uint32_t flash_size(void)
+{
+  static uint32_t size;
+  int i;
+
+  if (size == 0)
+    {
+      for (i = 0; i < PROGMEM_NBLOCKS; i++)
+        {
+          size += page_sizes[CONFIG_STM32F7_PROGMEM_STARTBLOCK + i];
+        }
+    }
+
+  return size;
+}
+
+static uint32_t flash_base(void)
+{
+  static uint32_t base;
+  int i;
+
+  if (base == 0)
+    {
+      base = STM32_FLASH_BASE;
+      for (i = 0; i < CONFIG_STM32F7_PROGMEM_STARTBLOCK; i++)
+        {
+          base += page_sizes[i];
+        }
+    }
+
+  return base;
+}
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -158,27 +203,29 @@ void stm32_flash_lock(void)
  *
  ****************************************************************************/
 
-int stm32_flash_writeprotect(size_t page, bool enabled)
+int stm32_flash_writeprotect(size_t block, bool enabled)
 {
   uint32_t reg;
   uint32_t val;
 
-  if (page >= STM32_FLASH_NPAGES)
+  if (block >= PROGMEM_NBLOCKS)
     {
       return -EFAULT;
     }
 
+  block = block + CONFIG_STM32F7_PROGMEM_STARTBLOCK;
+
   /* Select the register that contains the bit to be changed */
 
-  if (page < 12)
+  if (block < 12)
     {
       reg = STM32_FLASH_OPTCR;
     }
-#if defined(CONFIG_STM32_FLASH_CONFIG_I)
+#if defined(CONFIG_STM32F7_FLASH_CONFIG_I)
   else
     {
       reg = STM32_FLASH_OPTCR1;
-      page -= 12;
+      block -= 12;
     }
 #else
   else
@@ -195,11 +242,11 @@ int stm32_flash_writeprotect(size_t page, bool enabled)
 
   if (enabled)
     {
-      val &= ~(1 << (16 + page));
+      val &= ~(1 << (16 + block));
     }
   else
     {
-      val |=  (1 << (16 + page));
+      val |=  (1 << (16 + block));
     }
 
   /* Unlock options */
@@ -219,7 +266,6 @@ int stm32_flash_writeprotect(size_t page, bool enabled)
 
   while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
     {
-      up_waste();
     }
 
   /* Re-lock options */
@@ -230,75 +276,57 @@ int stm32_flash_writeprotect(size_t page, bool enabled)
 
 size_t up_progmem_pagesize(size_t page)
 {
-  static const size_t page_sizes[STM32_FLASH_NPAGES] = STM32_FLASH_SIZES;
-
-  if (page >= sizeof(page_sizes) / sizeof(*page_sizes))
-    {
-      return 0;
-    }
-  else
-    {
-      return page_sizes[page];
-    }
+  return PAGESIZE;
 }
 
 ssize_t up_progmem_getpage(size_t addr)
 {
-  size_t page_end = 0;
-  size_t i;
-
-  if (addr >= STM32_FLASH_BASE)
+  if (addr >= flash_base())
     {
-      addr -= STM32_FLASH_BASE;
+      addr -= flash_base();
     }
 
-  if (addr >= STM32_FLASH_SIZE)
+  if (addr >= flash_size())
     {
       return -EFAULT;
     }
 
-  for (i = 0; i < STM32_FLASH_NPAGES; ++i)
-    {
-      page_end += up_progmem_pagesize(i);
-      if (page_end > addr)
-        {
-          return i;
-        }
-    }
-
-  return -EFAULT;
+  return addr / PAGESIZE;
 }
 
 size_t up_progmem_getaddress(size_t page)
 {
-  size_t base_address = STM32_FLASH_BASE;
-  size_t i;
+  size_t base_address = flash_base();
 
-  if (page >= STM32_FLASH_NPAGES)
+  if (page >= flash_size() / PAGESIZE)
     {
       return SIZE_MAX;
     }
 
-  for (i = 0; i < page; ++i)
-    {
-      base_address += up_progmem_pagesize(i);
-    }
+  base_address += PAGESIZE * page;
 
   return base_address;
 }
 
 size_t up_progmem_neraseblocks(void)
 {
-  return STM32_FLASH_NPAGES;
+  return PROGMEM_NBLOCKS;
 }
 
 bool up_progmem_isuniform(void)
 {
-#ifdef STM32_FLASH_PAGESIZE
+  size_t size = up_progmem_pagesize(0);
+  int i;
+
+  for (i = 1; i < PROGMEM_NBLOCKS; i++)
+    {
+      if (up_progmem_pagesize(i) != size)
+        {
+          return false;
+        }
+    }
+
   return true;
-#else
-  return false;
-#endif
 }
 
 ssize_t up_progmem_ispageerased(size_t page)
@@ -307,7 +335,7 @@ ssize_t up_progmem_ispageerased(size_t page)
   size_t count;
   size_t bwritten = 0;
 
-  if (page >= STM32_FLASH_NPAGES)
+  if (page >= flash_size() / PAGESIZE)
     {
       return -EFAULT;
     }
@@ -328,7 +356,7 @@ ssize_t up_progmem_ispageerased(size_t page)
 
 ssize_t up_progmem_eraseblock(size_t block)
 {
-  if (block >= STM32_FLASH_NPAGES)
+  if (block >= PROGMEM_NBLOCKS)
     {
       return -EFAULT;
     }
@@ -340,10 +368,13 @@ ssize_t up_progmem_eraseblock(size_t block)
   flash_unlock();
 
   modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_SER);
-  modifyreg32(STM32_FLASH_CR, FLASH_CR_SNB_MASK, FLASH_CR_SNB(block));
+  modifyreg32(STM32_FLASH_CR, FLASH_CR_SNB_MASK,
+      FLASH_CR_SNB((block + CONFIG_STM32F7_PROGMEM_STARTBLOCK)));
   modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT);
 
-  while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
+  while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
+    {
+    }
 
   modifyreg32(STM32_FLASH_CR, FLASH_CR_SER, 0);
   sem_unlock();
@@ -360,6 +391,20 @@ ssize_t up_progmem_eraseblock(size_t block)
     }
 }
 
+size_t up_progmem_erasesize(size_t block)
+{
+  block = block + CONFIG_STM32F7_PROGMEM_STARTBLOCK;
+
+  if (block >= sizeof(page_sizes) / sizeof(*page_sizes))
+    {
+      return 0;
+    }
+  else
+    {
+      return page_sizes[block];
+    }
+}
+
 ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
 {
   uint8_t *byte = (uint8_t *)buf;
@@ -371,7 +416,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
   if (addr >= STM32_FLASH_BASE &&
       addr + count <= STM32_FLASH_BASE + STM32_FLASH_SIZE)
     {
-      flash_base = STM32_FLASH_BASE;
+      flash_base = up_progmem_getaddress(0);
     }
   else if (addr >= STM32_OPT_BASE &&
            addr + count <= STM32_OPT_BASE + STM32_OPT_SIZE)
@@ -410,7 +455,9 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
 
       ARM_DSB();
 
-      while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
+      while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
+        {
+        }
 
       /* Verify */
 
diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c
index af861578cfd..9d3d7660eb2 100644
--- a/arch/arm/src/stm32f7/stm32_gpio.c
+++ b/arch/arm/src/stm32f7/stm32_gpio.c
@@ -50,7 +50,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/stm32_syscfg.h"
+#include "hardware/stm32_syscfg.h"
 #include "stm32_gpio.h"
 
 /* Content of this file requires verification before it is used with other
diff --git a/arch/arm/src/stm32f7/stm32_gpio.h b/arch/arm/src/stm32f7/stm32_gpio.h
index e3b49e81303..eb7fd3d29eb 100644
--- a/arch/arm/src/stm32f7/stm32_gpio.h
+++ b/arch/arm/src/stm32f7/stm32_gpio.h
@@ -50,7 +50,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_gpio.h"
+#include "hardware/stm32_gpio.h"
 
 /************************************************************************************
  * Pre-Processor Declarations
diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c
index faf082a4112..eac2435e003 100644
--- a/arch/arm/src/stm32f7/stm32_i2c.c
+++ b/arch/arm/src/stm32f7/stm32_i2c.c
@@ -112,7 +112,7 @@
  *
  *  - Private: Private data of an I2C Hardware
  *
- * High Level Functional Desecription
+ * High Level Functional Description
  *
  * This driver works with I2C "messages" (struct i2c_msg_s), which carry a buffer
  * intended to transfer data to, or store data read from, the I2C bus.
@@ -137,7 +137,7 @@
  * Interrupt mode relies on the following interrupt events:
  *
  *   TXIS  - Transmit interrupt
- *           (data transmitted to bus and acknowedged)
+ *           (data transmitted to bus and acknowledged)
  *   NACKF - Not Acknowledge Received
  *           (data transmitted to bus and NOT acknowledged)
  *   RXNE  - Receive interrupt
@@ -252,7 +252,7 @@
 #include "stm32_rcc.h"
 #include "stm32_i2c.h"
 #include "stm32_gpio.h"
-#include "chip/stm32_pinmap.h"
+#include "hardware/stm32_pinmap.h"
 
 /* At least one I2C peripheral must be enabled */
 
@@ -271,7 +271,7 @@
 #    define INVALID_CLOCK_SOURCE
 #  endif
 #endif
-#ifdef CONFIG_STM32F7_I2C1
+#ifdef CONFIG_STM32F7_I2C2
 #  if STM32_RCC_DCKCFGR2_I2C2SRC != RCC_DCKCFGR2_I2C2SEL_HSI
 #    warning "Clock Source STM32_RCC_DCKCFGR2_I2C2SRC must be HSI"
 #    define INVALID_CLOCK_SOURCE
@@ -324,8 +324,14 @@
 
 #define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT)
 
-#define I2C_CR1_TXRX (I2C_CR1_RXIE | I2C_CR1_TXIE)
-#define I2C_CR1_ALLINTS (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE)
+#define I2C_CR1_TXRX      (I2C_CR1_RXIE | I2C_CR1_TXIE)
+#define I2C_CR1_ALLINTS   (I2C_CR1_TXRX | I2C_CR1_TCIE | I2C_CR1_ERRIE)
+
+/* Unused bit in I2c_ISR used to communicate a bad state has occurred in
+ * the isr processing
+*/
+
+#define I2C_INT_BAD_STATE 0x8000000
 
 /* I2C event tracing
  *
@@ -421,7 +427,7 @@ struct stm32_i2c_config_s
 struct stm32_i2c_priv_s
 {
   const struct stm32_i2c_config_s *config; /* Port configuration */
-  int refs;                    /* Referernce count */
+  int refs;                    /* Reference count */
   sem_t sem_excl;              /* Mutual exclusion semaphore */
 #ifndef CONFIG_I2C_POLLED
   sem_t sem_isr;               /* Interrupt wait semaphore */
@@ -1310,24 +1316,22 @@ static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
 
 static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequency)
 {
-  uint32_t pe;
   uint8_t presc;
   uint8_t scl_delay;
   uint8_t sda_delay;
   uint8_t scl_h_period;
   uint8_t scl_l_period;
 
+  /* I2C peripheral must be disabled to update clocking configuration.
+   * This will SW reset the device.
+   */
+
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
+
   if (frequency != priv->frequency)
     {
-      /* I2C peripheral must be disabled to update clocking configuration */
 
-      pe = (stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE);
-      if (pe)
-        {
-          stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
-        }
-
-      /*  The Sppeed and timing calculation are based on the following
+      /*  The Speed and timing calculation are based on the following
        *  fI2CCLK = HSI and is 16Mhz
        *  Analog filter is on,
        *  Digital filter off
@@ -1377,14 +1381,12 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
         (scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
 
       stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr);
-
-      if (pe)
-        {
-          stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
-        }
-
       priv->frequency = frequency;
     }
+
+  /* Enable I2C peripheral */
+
+  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
 }
 
 /************************************************************************************
@@ -1601,9 +1603,9 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
 
   i2cinfo("ENTER: status = 0x%08x\n", status);
 
-  /* Update private version of the state */
+  /* Update private version of the state assuming a good state */
 
-  priv->status = status;
+  priv->status = status & ~I2C_INT_BAD_STATE;
 
   /* If this is a new transmission set up the trace table accordingly */
 
@@ -1681,7 +1683,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
    * interrupt will only fire when the I2C_CR1->TXIE bit is 1.
    *
    * This indicates the transmit data register I2C_TXDR has been emptied
-   * following the successful transmission of a byte and slave acknowledgement.
+   * following the successful transmission of a byte and slave acknowledgment.
    * In this state the I2C_TXDR register is ready to accept another byte for
    * transmission.  The TXIS bit will be cleared automatically when the next
    * byte is written to I2C_TXDR.
@@ -1772,6 +1774,10 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
           i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, status 0x%08x\n",
           priv->dcnt, status);
           stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0);
+
+          /* Indicate the bad state, so that on termination HW will be reset */
+
+          priv->status |= I2C_INT_BAD_STATE;
         }
 
       i2cinfo("TXIS: EXIT  dcnt = %i msgc = %i status 0x%08x\n",
@@ -1860,6 +1866,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
 
           /* Set signals that will terminate ISR and wake waiting thread */
 
+          priv->status |= I2C_INT_BAD_STATE;
           priv->dcnt = -1;
           priv->msgc = 0;
         }
@@ -2105,7 +2112,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
    *
    * We get to this branch only if we can't handle the current state.
    *
-   * This should not happen in interrupt based operation.
+   * This can happen in interrupt based operation on ARLO & BUSY.
    *
    * This will happen during polled operation when the device is not
    * in one of the supported states when polled.
@@ -2124,6 +2131,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
 
       /* set condition to terminate ISR and wake waiting thread */
 
+      priv->status |= I2C_INT_BAD_STATE;
       priv->dcnt = -1;
       priv->msgc = 0;
       stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0);
@@ -2154,22 +2162,33 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv)
       priv->intstate = INTSTATE_DONE;
 #else
 
-      status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
-
-      /* Update private state to capture NACK which is used in combination
-       * with the astart flag to report the type of NACK received (address
-       * vs data) to the upper layers once we exit the ISR.
+      /* We will update private state to capture NACK which is used in
+       * combination with the astart flag to report the type of NACK received
+       * (address vs data) to the upper layers once we exit the ISR.
        *
-       * Note: We do this prior to clearing interrupts because the NACKF
-       * flag will naturally be cleared by that process.
+       * Note: status is captured  prior to clearing interrupts because
+       * the NACKF flag will naturally be cleared by that process.
        */
 
-      priv->status = status;
+      status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET);
 
       /* Clear all interrupts */
 
       stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
 
+      /* Was a bad state detected in the processing? */
+
+      if (priv->status & I2C_INT_BAD_STATE)
+        {
+          /* SW reset device  */
+
+          stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
+        }
+
+      /* Update private status from above sans I2C_INT_BAD_STATE */
+
+      priv->status = status;
+
       /* If a thread is waiting then inform it transfer is complete */
 
       if (priv->intstate == INTSTATE_WAITING)
@@ -2254,10 +2273,6 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
   priv->frequency = 0;
   stm32_i2c_setclock(priv, 100000);
 
-  /* Enable I2C peripheral */
-
-  stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
-
   return OK;
 }
 
@@ -2337,7 +2352,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
 
   stm32_i2c_tracereset(priv);
 
-  /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) */
+  /* Set I2C clock frequency toggles I2C_CR1_PE performing a SW reset! */
 
   stm32_i2c_setclock(priv, msgs->frequency);
 
diff --git a/arch/arm/src/stm32f7/stm32_i2c.h b/arch/arm/src/stm32f7/stm32_i2c.h
index e2223f53c8f..6a1ac38884e 100644
--- a/arch/arm/src/stm32f7/stm32_i2c.h
+++ b/arch/arm/src/stm32f7/stm32_i2c.h
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_i2c.h"
+#include "hardware/stm32_i2c.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32f7/stm32_lowputc.c b/arch/arm/src/stm32f7/stm32_lowputc.c
index d642c862a69..9aefb4295cf 100644
--- a/arch/arm/src/stm32f7/stm32_lowputc.c
+++ b/arch/arm/src/stm32f7/stm32_lowputc.c
@@ -46,7 +46,7 @@
 
 #include "chip.h"
 
-#include "chip/stm32_pinmap.h"
+#include "hardware/stm32_pinmap.h"
 #include "stm32_rcc.h"
 #include "stm32_gpio.h"
 #include "stm32_uart.h"
diff --git a/arch/arm/src/stm32f7/stm32_ltdc.c b/arch/arm/src/stm32f7/stm32_ltdc.c
index 22f1c3c6c20..ec83b816166 100644
--- a/arch/arm/src/stm32f7/stm32_ltdc.c
+++ b/arch/arm/src/stm32f7/stm32_ltdc.c
@@ -57,8 +57,8 @@
 
 #include "up_arch.h"
 #include "up_internal.h"
-#include "chip/stm32_ltdc.h"
-#include "chip/stm32_dma2d.h"
+#include "hardware/stm32_ltdc.h"
+#include "hardware/stm32_dma2d.h"
 #include "stm32_rcc.h"
 #include "stm32_gpio.h"
 #include "stm32_ltdc.h"
diff --git a/arch/arm/src/stm32f7/stm32_otg.h b/arch/arm/src/stm32f7/stm32_otg.h
index 26ed5f824b0..90672ae24a9 100644
--- a/arch/arm/src/stm32f7/stm32_otg.h
+++ b/arch/arm/src/stm32f7/stm32_otg.h
@@ -45,15 +45,20 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_otg.h"
+#include "hardware/stm32_otg.h"
 
-#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGHS)
+#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS)
 
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
+
 /* Configuration ********************************************************************/
 
+#ifndef CONFIG_OTG_PRI
+#  define CONFIG_OTG_PRI NVIC_SYSH_PRIORITY_DEFAULT
+#endif
+
 #if defined(CONFIG_STM32F7_OTGFS)
 #  define STM32_IRQ_OTG         STM32_IRQ_OTGFS
 #  define STM32_OTG_BASE        STM32_USBOTGFS_BASE
@@ -62,17 +67,19 @@
 #  define GPIO_OTG_DP           GPIO_OTGFS_DP
 #  define GPIO_OTG_ID           GPIO_OTGFS_ID
 #  define GPIO_OTG_SOF          GPIO_OTGFS_SOF
+#  define GPIO_OTG_VBUS         GPIO_OTGFS_VBUS
 #  define STM32_OTG_FIFO_SIZE   1280
 #endif
 
-#if defined(CONFIG_STM32F7_OTGHS)
+#if defined(CONFIG_STM32F7_OTGFSHS)
 #  define STM32_IRQ_OTG         STM32_IRQ_OTGHS
 #  define STM32_OTG_BASE        STM32_USBOTGHS_BASE
 #  define STM32_NENDPOINTS      (7)          /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */
-#  define GPIO_OTG_DM           GPIO_OTGHS_DM
-#  define GPIO_OTG_DP           GPIO_OTGHS_DP
-#  define GPIO_OTG_ID           GPIO_OTGHS_ID
-#  define GPIO_OTG_SOF          GPIO_OTGHS_SOF
+#  define GPIO_OTG_DM           GPIO_OTGHSFS_DM
+#  define GPIO_OTG_DP           GPIO_OTGHSFS_DP
+#  define GPIO_OTG_ID           GPIO_OTGHSFS_ID
+#  define GPIO_OTG_SOF          GPIO_OTGHSFS_SOF
+#  define GPIO_OTG_VBUS         GPIO_OTGHSFS_VBUS
 #  define STM32_OTG_FIFO_SIZE   4096
 #endif
 
diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c
index 65dea7403fd..ba465e28233 100644
--- a/arch/arm/src/stm32f7/stm32_otgdev.c
+++ b/arch/arm/src/stm32f7/stm32_otgdev.c
@@ -63,9 +63,8 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-
 #if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32F7_OTGFS) || \
-    defined(CONFIG_STM32F7_OTGHS))
+    defined(CONFIG_STM32F7_OTGFSHS))
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -73,17 +72,17 @@
 
 /* Configuration ************************************************************/
 
-#ifndef CONFIG_USBDEV_EP0_MAXSIZE
-#  define CONFIG_USBDEV_EP0_MAXSIZE 64
-#endif
+#  ifndef CONFIG_USBDEV_EP0_MAXSIZE
+#    define CONFIG_USBDEV_EP0_MAXSIZE 64
+#  endif
 
-#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE
-#  define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE
-#endif
+#  ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE
+#    define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE
+#  endif
 
-#ifndef CONFIG_USBDEV_MAXPOWER
-#  define CONFIG_USBDEV_MAXPOWER 100  /* mA */
-#endif
+#  ifndef CONFIG_USBDEV_MAXPOWER
+#    define CONFIG_USBDEV_MAXPOWER 100  /* mA */
+#  endif
 
 /* There is 1.25Kb of FIFO memory.  The default partitions this memory
  * so that there is a TxFIFO allocated for each endpoint and with more
@@ -91,271 +90,322 @@
  * configuration would not allocate any TxFIFO space to OUT endpoints.
  */
 
-#ifndef CONFIG_USBDEV_RXFIFO_SIZE
-#  define CONFIG_USBDEV_RXFIFO_SIZE (STM32_OTG_FIFO_SIZE - STM32_OTG_FIFO_SIZE/4/2/STM32_NENDPOINTS*4*STM32_NENDPOINTS)
-#endif
-
-#if STM32_NENDPOINTS > 0
-#  ifndef CONFIG_USBDEV_EP0_TXFIFO_SIZE
-#    define CONFIG_USBDEV_EP0_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
+#  ifndef CONFIG_USBDEV_RXFIFO_SIZE
+#    define CONFIG_USBDEV_RXFIFO_SIZE \
+       (STM32_OTG_FIFO_SIZE - \
+        STM32_OTG_FIFO_SIZE / 4/ 2 / STM32_NENDPOINTS * 4 * STM32_NENDPOINTS)
 #  endif
-#else
-#  define CONFIG_USBDEV_EP0_TXFIFO_SIZE 0
-#endif
 
-#if STM32_NENDPOINTS > 1
-#  ifndef CONFIG_USBDEV_EP1_TXFIFO_SIZE
-#    define CONFIG_USBDEV_EP1_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
+#  if STM32_NENDPOINTS > 0
+#    ifndef CONFIG_USBDEV_EP0_TXFIFO_SIZE
+#      define CONFIG_USBDEV_EP0_TXFIFO_SIZE \
+          ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE) / STM32_NENDPOINTS)
+#    endif
+#  else
+#    define CONFIG_USBDEV_EP0_TXFIFO_SIZE 0
 #  endif
-#else
-#  define CONFIG_USBDEV_EP1_TXFIFO_SIZE 0
-#endif
 
-#if STM32_NENDPOINTS > 2
-#  ifndef CONFIG_USBDEV_EP2_TXFIFO_SIZE
-#    define CONFIG_USBDEV_EP2_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
+#  if STM32_NENDPOINTS > 1
+#    ifndef CONFIG_USBDEV_EP1_TXFIFO_SIZE
+#      define CONFIG_USBDEV_EP1_TXFIFO_SIZE \
+         ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE) / STM32_NENDPOINTS)
+#    endif
+#  else
+#    define CONFIG_USBDEV_EP1_TXFIFO_SIZE 0
 #  endif
-#else
-#  define CONFIG_USBDEV_EP2_TXFIFO_SIZE 0
-#endif
 
-#if STM32_NENDPOINTS > 3
-#  ifndef CONFIG_USBDEV_EP3_TXFIFO_SIZE
-#    define CONFIG_USBDEV_EP3_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
+#  if STM32_NENDPOINTS > 2
+#    ifndef CONFIG_USBDEV_EP2_TXFIFO_SIZE
+#      define CONFIG_USBDEV_EP2_TXFIFO_SIZE \
+         ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE) / STM32_NENDPOINTS)
+#    endif
+#  else
+#    define CONFIG_USBDEV_EP2_TXFIFO_SIZE 0
 #  endif
-#else
-#  define CONFIG_USBDEV_EP3_TXFIFO_SIZE 0
-#endif
 
-#if STM32_NENDPOINTS > 4
-#  ifndef CONFIG_USBDEV_EP4_TXFIFO_SIZE
-#    define CONFIG_USBDEV_EP4_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
+#  if STM32_NENDPOINTS > 3
+#    ifndef CONFIG_USBDEV_EP3_TXFIFO_SIZE
+#      define CONFIG_USBDEV_EP3_TXFIFO_SIZE \
+         ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE) / STM32_NENDPOINTS)
+#    endif
+#  else
+#    define CONFIG_USBDEV_EP3_TXFIFO_SIZE 0
 #  endif
-#else
-#  define CONFIG_USBDEV_EP4_TXFIFO_SIZE 0
-#endif
 
-#if STM32_NENDPOINTS > 5
-#  ifndef CONFIG_USBDEV_EP5_TXFIFO_SIZE
-#    define CONFIG_USBDEV_EP5_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
+#  if STM32_NENDPOINTS > 4
+#    ifndef CONFIG_USBDEV_EP4_TXFIFO_SIZE
+#      define CONFIG_USBDEV_EP4_TXFIFO_SIZE \
+         ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE) / STM32_NENDPOINTS)
+#    endif
+#  else
+#    define CONFIG_USBDEV_EP4_TXFIFO_SIZE 0
 #  endif
-#else
-#  define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0
-#endif
 
-#if STM32_NENDPOINTS > 6
-#  ifndef CONFIG_USBDEV_EP6_TXFIFO_SIZE
-#    define CONFIG_USBDEV_EP6_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
+#  if STM32_NENDPOINTS > 5
+#    ifndef CONFIG_USBDEV_EP5_TXFIFO_SIZE
+#      define CONFIG_USBDEV_EP5_TXFIFO_SIZE \
+         ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE) / STM32_NENDPOINTS)
+#    endif
+#  else
+#    define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0
 #  endif
-#else
-#  define CONFIG_USBDEV_EP6_TXFIFO_SIZE 0
-#endif
 
-#if STM32_NENDPOINTS > 7
-#  ifndef CONFIG_USBDEV_EP7_TXFIFO_SIZE
-#    define CONFIG_USBDEV_EP7_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
+#  if STM32_NENDPOINTS > 6
+#    ifndef CONFIG_USBDEV_EP6_TXFIFO_SIZE
+#      define CONFIG_USBDEV_EP6_TXFIFO_SIZE (\
+         (STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE) / STM32_NENDPOINTS)
+#    endif
+#  else
+#    define CONFIG_USBDEV_EP6_TXFIFO_SIZE 0
 #  endif
-#else
-#  define CONFIG_USBDEV_EP7_TXFIFO_SIZE 0
-#endif
 
-#if STM32_NENDPOINTS > 8
-#  ifndef CONFIG_USBDEV_EP8_TXFIFO_SIZE
-#    define CONFIG_USBDEV_EP8_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
+#  if STM32_NENDPOINTS > 7
+#    ifndef CONFIG_USBDEV_EP7_TXFIFO_SIZE
+#      define CONFIG_USBDEV_EP7_TXFIFO_SIZE \
+         ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE) / STM32_NENDPOINTS)
+#    endif
+#  else
+#    define CONFIG_USBDEV_EP7_TXFIFO_SIZE 0
+#  endif
+
+#  if STM32_NENDPOINTS > 8
+#    ifndef CONFIG_USBDEV_EP8_TXFIFO_SIZE
+#      define CONFIG_USBDEV_EP8_TXFIFO_SIZE \
+         ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE) / STM32_NENDPOINTS)
+#    endif
+#  else
+#    define CONFIG_USBDEV_EP8_TXFIFO_SIZE 0
 #  endif
-#else
-#  define CONFIG_USBDEV_EP8_TXFIFO_SIZE 0
-#endif
 
 /* The actual FIFO addresses that we use must be aligned to 4-byte boundaries;
  * FIFO sizes must be provided in units of 32-bit words.
  */
 
-#define STM32_RXFIFO_BYTES     ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3)
-#define STM32_RXFIFO_WORDS     ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2)
+#  define STM32_RXFIFO_BYTES     ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3)
+#  define STM32_RXFIFO_WORDS     ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2)
 
-#define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3)
-#define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2)
+#  define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3)
+#  define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2)
 
-#define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3)
-#define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2)
+#  define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3)
+#  define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2)
 
-#define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3)
-#define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2)
+#  define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3)
+#  define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2)
 
-#define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3)
-#define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2)
+#  define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3)
+#  define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2)
 
-#define STM32_EP4_TXFIFO_BYTES ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) & ~3)
-#define STM32_EP4_TXFIFO_WORDS ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) >> 2)
+#  define STM32_EP4_TXFIFO_BYTES ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) & ~3)
+#  define STM32_EP4_TXFIFO_WORDS ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) >> 2)
 
-#define STM32_EP5_TXFIFO_BYTES ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) & ~3)
-#define STM32_EP5_TXFIFO_WORDS ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) >> 2)
+#  define STM32_EP5_TXFIFO_BYTES ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) & ~3)
+#  define STM32_EP5_TXFIFO_WORDS ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) >> 2)
 
-#define STM32_EP6_TXFIFO_BYTES ((CONFIG_USBDEV_EP6_TXFIFO_SIZE + 3) & ~3)
-#define STM32_EP6_TXFIFO_WORDS ((CONFIG_USBDEV_EP6_TXFIFO_SIZE + 3) >> 2)
+#  define STM32_EP6_TXFIFO_BYTES ((CONFIG_USBDEV_EP6_TXFIFO_SIZE + 3) & ~3)
+#  define STM32_EP6_TXFIFO_WORDS ((CONFIG_USBDEV_EP6_TXFIFO_SIZE + 3) >> 2)
 
-#define STM32_EP7_TXFIFO_BYTES ((CONFIG_USBDEV_EP7_TXFIFO_SIZE + 3) & ~3)
-#define STM32_EP7_TXFIFO_WORDS ((CONFIG_USBDEV_EP7_TXFIFO_SIZE + 3) >> 2)
+#  define STM32_EP7_TXFIFO_BYTES ((CONFIG_USBDEV_EP7_TXFIFO_SIZE + 3) & ~3)
+#  define STM32_EP7_TXFIFO_WORDS ((CONFIG_USBDEV_EP7_TXFIFO_SIZE + 3) >> 2)
 
-#define STM32_EP8_TXFIFO_BYTES ((CONFIG_USBDEV_EP8_TXFIFO_SIZE + 3) & ~3)
-#define STM32_EP8_TXFIFO_WORDS ((CONFIG_USBDEV_EP8_TXFIFO_SIZE + 3) >> 2)
+#  define STM32_EP8_TXFIFO_BYTES ((CONFIG_USBDEV_EP8_TXFIFO_SIZE + 3) & ~3)
+#  define STM32_EP8_TXFIFO_WORDS ((CONFIG_USBDEV_EP8_TXFIFO_SIZE + 3) >> 2)
 
-
-#if (STM32_RXFIFO_BYTES + \
+#  if (STM32_RXFIFO_BYTES + \
      STM32_EP0_TXFIFO_BYTES + STM32_EP1_TXFIFO_BYTES + STM32_EP2_TXFIFO_BYTES + STM32_EP3_TXFIFO_BYTES + \
      STM32_EP4_TXFIFO_BYTES + STM32_EP5_TXFIFO_BYTES + STM32_EP6_TXFIFO_BYTES + STM32_EP7_TXFIFO_BYTES + CONFIG_USBDEV_EP8_TXFIFO_SIZE   \
     ) > STM32_OTG_FIFO_SIZE
-#  error "FIFO allocations exceed FIFO memory size"
-#endif
+#    error "FIFO allocations exceed FIFO memory size"
+#  endif
 
-#define OTG_GINT_RESERVED   (OTG_GINT_RES89   | \
-                            OTG_GINT_RES1617  | \
-                            OTG_GINT_RES22)
+#  define OTG_GINT_RESERVED_FS   (OTG_GINT_RES89    | \
+                                OTG_GINT_RES1617  | \
+                                OTG_GINT_RES22)
 
+#  define OTG_GINT_RESERVED_HS   (OTG_GINT_RES89    | \
+                                OTG_GINT_RES1617  | \
+                                OTG_GINT_RES23    | \
+                                OTG_GINT_RES27)
 
-#define OTG_GINT_RC_W1   (OTG_GINT_MMIS     | \
-                          OTG_GINT_SOF      | \
-                          OTG_GINT_ESUSP    | \
-                          OTG_GINT_USBSUSP  | \
-                          OTG_GINT_USBRST   | \
-                          OTG_GINT_ENUMDNE  | \
-                          OTG_GINT_ISOODRP  | \
-                          OTG_GINT_EOPF     | \
-                          OTG_GINT_IISOIXFR | \
-                          OTG_GINT_IISOOXFR | \
-                          OTG_GINT_RSTDET   | \
-                          OTG_GINT_LPMINT   | \
-                          OTG_GINT_CIDSCHG  | \
-                          OTG_GINT_DISC     | \
-                          OTG_GINT_SRQ      | \
-                          OTG_GINT_WKUP)
+#  define OTG_GINT_RC_W1_FS      (OTG_GINT_MMIS     | \
+                                OTG_GINT_SOF      | \
+                                OTG_GINT_ESUSP    | \
+                                OTG_GINT_USBSUSP  | \
+                                OTG_GINT_USBRST   | \
+                                OTG_GINT_ENUMDNE  | \
+                                OTG_GINT_ISOODRP  | \
+                                OTG_GINT_EOPF     | \
+                                OTG_GINT_IISOIXFR | \
+                                OTG_GINT_IISOOXFR | \
+                                OTG_GINT_RSTDET   | \
+                                OTG_GINT_LPMINT   | \
+                                OTG_GINT_CIDSCHG  | \
+                                OTG_GINT_DISC     | \
+                                OTG_GINT_SRQ      | \
+                                OTG_GINT_WKUP)
 
+#  define OTG_GINT_RC_W1_HS      (OTG_GINT_MMIS     | \
+                                OTG_GINT_SOF      | \
+                                OTG_GINT_ESUSP    | \
+                                OTG_GINT_USBSUSP  | \
+                                OTG_GINT_USBRST   | \
+                                OTG_GINT_ENUMDNE  | \
+                                OTG_GINT_ISOODRP  | \
+                                OTG_GINT_EOPF     | \
+                                OTG_GINT_IISOIXFR | \
+                                OTG_GINT_IISOOXFR | \
+                                OTG_GINT_DATAFSUSP| \
+                                OTG_GINT_CIDSCHG  | \
+                                OTG_GINT_DISC     | \
+                                OTG_GINT_SRQ      | \
+                                OTG_GINT_WKUP)
+
+/* Only stm32F723 has internal ULPI. We consider in HS only if a ULPI is present */
+
+#  ifdef CONFIG_STM32F7_OTGFSHS
+#    define OTG_GINT_RESERVED     OTG_GINT_RESERVED_HS
+#    define OTG_GINT_RC_W1        OTG_GINT_RC_W1_HS
+#  else
+#    define OTG_GINT_RESERVED     OTG_GINT_RESERVED_FS
+#    define OTG_GINT_RC_W1        OTG_GINT_RC_W1_FS
+#  endif
 
 /* Debug ***********************************************************************/
+
 /* Trace error codes */
 
-#define STM32_TRACEERR_ALLOCFAIL            0x01
-#define STM32_TRACEERR_BADCLEARFEATURE      0x02
-#define STM32_TRACEERR_BADDEVGETSTATUS      0x03
-#define STM32_TRACEERR_BADEPNO              0x04
-#define STM32_TRACEERR_BADEPGETSTATUS       0x05
-#define STM32_TRACEERR_BADGETCONFIG         0x06
-#define STM32_TRACEERR_BADGETSETDESC        0x07
-#define STM32_TRACEERR_BADGETSTATUS         0x08
-#define STM32_TRACEERR_BADSETADDRESS        0x09
-#define STM32_TRACEERR_BADSETCONFIG         0x0a
-#define STM32_TRACEERR_BADSETFEATURE        0x0b
-#define STM32_TRACEERR_BADTESTMODE          0x0c
-#define STM32_TRACEERR_BINDFAILED           0x0d
-#define STM32_TRACEERR_DISPATCHSTALL        0x0e
-#define STM32_TRACEERR_DRIVER               0x0f
-#define STM32_TRACEERR_DRIVERREGISTERED     0x10
-#define STM32_TRACEERR_EP0NOSETUP           0x11
-#define STM32_TRACEERR_EP0SETUPSTALLED      0x12
-#define STM32_TRACEERR_EPINNULLPACKET       0x13
-#define STM32_TRACEERR_EPINUNEXPECTED       0x14
-#define STM32_TRACEERR_EPOUTNULLPACKET      0x15
-#define STM32_TRACEERR_EPOUTUNEXPECTED      0x16
-#define STM32_TRACEERR_INVALIDCTRLREQ       0x17
-#define STM32_TRACEERR_INVALIDPARMS         0x18
-#define STM32_TRACEERR_IRQREGISTRATION      0x19
-#define STM32_TRACEERR_NOEP                 0x1a
-#define STM32_TRACEERR_NOTCONFIGURED        0x1b
-#define STM32_TRACEERR_EPOUTQEMPTY          0x1c
-#define STM32_TRACEERR_EPINREQEMPTY         0x1d
-#define STM32_TRACEERR_NOOUTSETUP           0x1e
-#define STM32_TRACEERR_POLLTIMEOUT          0x1f
+#  define STM32_TRACEERR_ALLOCFAIL            0x01
+#  define STM32_TRACEERR_BADCLEARFEATURE      0x02
+#  define STM32_TRACEERR_BADDEVGETSTATUS      0x03
+#  define STM32_TRACEERR_BADEPNO              0x04
+#  define STM32_TRACEERR_BADEPGETSTATUS       0x05
+#  define STM32_TRACEERR_BADGETCONFIG         0x06
+#  define STM32_TRACEERR_BADGETSETDESC        0x07
+#  define STM32_TRACEERR_BADGETSTATUS         0x08
+#  define STM32_TRACEERR_BADSETADDRESS        0x09
+#  define STM32_TRACEERR_BADSETCONFIG         0x0a
+#  define STM32_TRACEERR_BADSETFEATURE        0x0b
+#  define STM32_TRACEERR_BADTESTMODE          0x0c
+#  define STM32_TRACEERR_BINDFAILED           0x0d
+#  define STM32_TRACEERR_DISPATCHSTALL        0x0e
+#  define STM32_TRACEERR_DRIVER               0x0f
+#  define STM32_TRACEERR_DRIVERREGISTERED     0x10
+#  define STM32_TRACEERR_EP0NOSETUP           0x11
+#  define STM32_TRACEERR_EP0SETUPSTALLED      0x12
+#  define STM32_TRACEERR_EPINNULLPACKET       0x13
+#  define STM32_TRACEERR_EPINUNEXPECTED       0x14
+#  define STM32_TRACEERR_EPOUTNULLPACKET      0x15
+#  define STM32_TRACEERR_EPOUTUNEXPECTED      0x16
+#  define STM32_TRACEERR_INVALIDCTRLREQ       0x17
+#  define STM32_TRACEERR_INVALIDPARMS         0x18
+#  define STM32_TRACEERR_IRQREGISTRATION      0x19
+#  define STM32_TRACEERR_NOEP                 0x1a
+#  define STM32_TRACEERR_NOTCONFIGURED        0x1b
+#  define STM32_TRACEERR_EPOUTQEMPTY          0x1c
+#  define STM32_TRACEERR_EPINREQEMPTY         0x1d
+#  define STM32_TRACEERR_NOOUTSETUP           0x1e
+#  define STM32_TRACEERR_POLLTIMEOUT          0x1f
 
 /* Trace interrupt codes */
 
-#define STM32_TRACEINTID_USB                1       /* USB Interrupt entry/exit */
-#define STM32_TRACEINTID_INTPENDING         2       /* On each pass through the loop */
+#  define STM32_TRACEINTID_USB                1 /* USB Interrupt entry/exit */
+#  define STM32_TRACEINTID_INTPENDING         2 /* On each pass through the
+                                                 * loop */
 
-#define STM32_TRACEINTID_EPOUT              (10 + 0) /* First level interrupt decode */
-#define STM32_TRACEINTID_EPIN               (10 + 1)
-#define STM32_TRACEINTID_MISMATCH           (10 + 2)
-#define STM32_TRACEINTID_WAKEUP             (10 + 3)
-#define STM32_TRACEINTID_SUSPEND            (10 + 4)
-#define STM32_TRACEINTID_SOF                (10 + 5)
-#define STM32_TRACEINTID_RXFIFO             (10 + 6)
-#define STM32_TRACEINTID_DEVRESET           (10 + 7)
-#define STM32_TRACEINTID_ENUMDNE            (10 + 8)
-#define STM32_TRACEINTID_IISOIXFR           (10 + 9)
-#define STM32_TRACEINTID_IISOOXFR           (10 + 10)
-#define STM32_TRACEINTID_SRQ                (10 + 11)
-#define STM32_TRACEINTID_OTG                (10 + 12)
+#  define STM32_TRACEINTID_EPOUT              (10 + 0)  /* First level
+                                                         * interrupt decode */
+#  define STM32_TRACEINTID_EPIN               (10 + 1)
+#  define STM32_TRACEINTID_MISMATCH           (10 + 2)
+#  define STM32_TRACEINTID_WAKEUP             (10 + 3)
+#  define STM32_TRACEINTID_SUSPEND            (10 + 4)
+#  define STM32_TRACEINTID_SOF                (10 + 5)
+#  define STM32_TRACEINTID_RXFIFO             (10 + 6)
+#  define STM32_TRACEINTID_DEVRESET           (10 + 7)
+#  define STM32_TRACEINTID_ENUMDNE            (10 + 8)
+#  define STM32_TRACEINTID_IISOIXFR           (10 + 9)
+#  define STM32_TRACEINTID_IISOOXFR           (10 + 10)
+#  define STM32_TRACEINTID_SRQ                (10 + 11)
+#  define STM32_TRACEINTID_OTG                (10 + 12)
 
-#define STM32_TRACEINTID_EPOUT_XFRC         (40 + 0) /* EPOUT second level decode */
-#define STM32_TRACEINTID_EPOUT_EPDISD       (40 + 1)
-#define STM32_TRACEINTID_EPOUT_SETUP        (40 + 2)
-#define STM32_TRACEINTID_DISPATCH           (40 + 3)
+#  define STM32_TRACEINTID_EPOUT_XFRC         (40 + 0)  /* EPOUT second level
+                                                         * decode */
+#  define STM32_TRACEINTID_EPOUT_EPDISD       (40 + 1)
+#  define STM32_TRACEINTID_EPOUT_SETUP        (40 + 2)
+#  define STM32_TRACEINTID_DISPATCH           (40 + 3)
 
-#define STM32_TRACEINTID_GETSTATUS          (50 + 0) /* EPOUT third level decode */
-#define STM32_TRACEINTID_EPGETSTATUS        (50 + 1)
-#define STM32_TRACEINTID_DEVGETSTATUS       (50 + 2)
-#define STM32_TRACEINTID_IFGETSTATUS        (50 + 3)
-#define STM32_TRACEINTID_CLEARFEATURE       (50 + 4)
-#define STM32_TRACEINTID_SETFEATURE         (50 + 5)
-#define STM32_TRACEINTID_SETADDRESS         (50 + 6)
-#define STM32_TRACEINTID_GETSETDESC         (50 + 7)
-#define STM32_TRACEINTID_GETCONFIG          (50 + 8)
-#define STM32_TRACEINTID_SETCONFIG          (50 + 9)
-#define STM32_TRACEINTID_GETSETIF           (50 + 10)
-#define STM32_TRACEINTID_SYNCHFRAME         (50 + 11)
+#  define STM32_TRACEINTID_GETSTATUS          (50 + 0)  /* EPOUT third level
+                                                         * decode */
+#  define STM32_TRACEINTID_EPGETSTATUS        (50 + 1)
+#  define STM32_TRACEINTID_DEVGETSTATUS       (50 + 2)
+#  define STM32_TRACEINTID_IFGETSTATUS        (50 + 3)
+#  define STM32_TRACEINTID_CLEARFEATURE       (50 + 4)
+#  define STM32_TRACEINTID_SETFEATURE         (50 + 5)
+#  define STM32_TRACEINTID_SETADDRESS         (50 + 6)
+#  define STM32_TRACEINTID_GETSETDESC         (50 + 7)
+#  define STM32_TRACEINTID_GETCONFIG          (50 + 8)
+#  define STM32_TRACEINTID_SETCONFIG          (50 + 9)
+#  define STM32_TRACEINTID_GETSETIF           (50 + 10)
+#  define STM32_TRACEINTID_SYNCHFRAME         (50 + 11)
 
-#define STM32_TRACEINTID_EPIN_XFRC          (70 + 0) /* EPIN second level decode */
-#define STM32_TRACEINTID_EPIN_TOC           (70 + 1)
-#define STM32_TRACEINTID_EPIN_ITTXFE        (70 + 2)
-#define STM32_TRACEINTID_EPIN_EPDISD        (70 + 3)
-#define STM32_TRACEINTID_EPIN_TXFE          (70 + 4)
+#  define STM32_TRACEINTID_EPIN_XFRC          (70 + 0)  /* EPIN second level
+                                                         * decode */
+#  define STM32_TRACEINTID_EPIN_TOC           (70 + 1)
+#  define STM32_TRACEINTID_EPIN_ITTXFE        (70 + 2)
+#  define STM32_TRACEINTID_EPIN_EPDISD        (70 + 3)
+#  define STM32_TRACEINTID_EPIN_TXFE          (70 + 4)
 
-#define STM32_TRACEINTID_EPIN_EMPWAIT       (80 + 0) /* EPIN second level decode */
+#  define STM32_TRACEINTID_EPIN_EMPWAIT       (80 + 0)  /* EPIN second level
+                                                         * decode */
 
-#define STM32_TRACEINTID_OUTNAK             (90 + 0) /* RXFLVL second level decode */
-#define STM32_TRACEINTID_OUTRECVD           (90 + 1)
-#define STM32_TRACEINTID_OUTDONE            (90 + 2)
-#define STM32_TRACEINTID_SETUPDONE          (90 + 3)
-#define STM32_TRACEINTID_SETUPRECVD         (90 + 4)
+#  define STM32_TRACEINTID_OUTNAK             (90 + 0)  /* RXFLVL second level
+                                                         * decode */
+#  define STM32_TRACEINTID_OUTRECVD           (90 + 1)
+#  define STM32_TRACEINTID_OUTDONE            (90 + 2)
+#  define STM32_TRACEINTID_SETUPDONE          (90 + 3)
+#  define STM32_TRACEINTID_SETUPRECVD         (90 + 4)
 
 /* Endpoints ******************************************************************/
 
 /* Odd physical endpoint numbers are IN; even are OUT */
 
-#define STM32_EPPHYIN2LOG(epphy)     ((uint8_t)(epphy)|USB_DIR_IN)
-#define STM32_EPPHYOUT2LOG(epphy)    ((uint8_t)(epphy)|USB_DIR_OUT)
+#  define STM32_EPPHYIN2LOG(epphy)     ((uint8_t)(epphy)|USB_DIR_IN)
+#  define STM32_EPPHYOUT2LOG(epphy)    ((uint8_t)(epphy)|USB_DIR_OUT)
 
 /* Endpoint 0 */
 
-#define EP0                          (0)
+#  define EP0                          (0)
 
 /* The set of all enpoints available to the class implementation (1-3) */
 
-#define STM32_EP_AVAILABLE           (0x0e)       /* All available endpoints */
+#  define STM32_EP_AVAILABLE           (0xfe)   /* All available endpoints */
 
 /* Maximum packet sizes for full speed endpoints */
 
-#define STM32_MAXPACKET              (64)         /* Max packet size (1-64) */
+#  ifdef CONFIG_STM32F7_OTGFSHS
+#    define STM32_MAXPACKET              (512)  /* Max packet size (1-512) */
+#  else
+#    define STM32_MAXPACKET              (64)   /* Max packet size (1-64) */
+#  endif
 
 /* Delays **********************************************************************/
 
-#define STM32_READY_DELAY            200000
-#define STM32_FLUSH_DELAY            200000
+#  define STM32_READY_DELAY            200000
+#  define STM32_FLUSH_DELAY            200000
 
 /* Request queue operations ****************************************************/
 
-#define stm32_rqempty(ep)            ((ep)->head == NULL)
-#define stm32_rqpeek(ep)             ((ep)->head)
+#  define stm32_rqempty(ep)            ((ep)->head == NULL)
+#  define stm32_rqpeek(ep)             ((ep)->head)
 
 /* Standard stuff **************************************************************/
 
-#ifndef MIN
-#  define MIN(a,b) ((a) < (b) ? (a) : (b))
-#endif
+#  ifndef MIN
+#    define MIN(a,b) ((a) < (b) ? (a) : (b))
+#  endif
 
-#ifndef MAX
-#  define MAX(a,b) ((a) > (b) ? (a) : (b))
-#endif
+#  ifndef MAX
+#    define MAX(a,b) ((a) > (b) ? (a) : (b))
+#  endif
 
 /****************************************************************************
  * Private Types
@@ -365,91 +415,78 @@
 
 enum stm32_devstate_e
 {
-  DEVSTATE_DEFAULT = 0,    /* Power-up, unconfigured state.  This state simply
-                            * means that the device is not yet been given an
-                            * address.
-                            *   SET:    At initialization, uninitialization,
-                            *           reset, and whenever the device address
-                            *           is set to zero
-                            *   TESTED: Never
-                            */
-  DEVSTATE_ADDRESSED,      /* Device address has been assigned, not no
-                            * configuration has yet been selected.
-                            *   SET:    When either a non-zero device address
-                            *           is first assigned or when the device
-                            *           is unconfigured (with configuration == 0)
-                            *   TESTED: never
-                            */
-  DEVSTATE_CONFIGURED,     /* Address assigned and configured:
-                            *   SET:    When the device has been addressed and
-                            *           an non-zero configuration has been selected.
-                            *   TESTED: In many places to assure that the USB device
-                            *           has been properly configured by the host.
-                            */
+  DEVSTATE_DEFAULT = 0,       /* Power-up, unconfigured state.  This state
+                               * simply means that the device is not yet been
+                               * given an address.  SET: At initialization,
+                               * uninitialization, reset, and whenever the
+                               * device address is set to zero TESTED: Never */
+  DEVSTATE_ADDRESSED,         /* Device address has been assigned, not no
+                               * configuration has yet been selected.  SET:
+                               * When either a non-zero device address is
+                               * first assigned or when the device is
+                               * unconfigured (with configuration == 0)
+                               * TESTED: never */
+  DEVSTATE_CONFIGURED,        /* Address assigned and configured: SET: When
+                               * the device has been addressed and an
+                               * non-zero configuration has been selected.
+                               * TESTED: In many places to assure that the
+                               * USB device has been properly configured by
+                               * the host. */
 };
 
 /* Endpoint 0 states */
 
 enum stm32_ep0state_e
 {
-  EP0STATE_IDLE = 0,       /* Idle State, leave on receiving a SETUP packet or
-                            * epsubmit:
-                            *   SET:    In stm32_epin() and stm32_epout() when
-                            *           we revert from request processing to
-                            *           SETUP processing.
-                            *   TESTED: Never
-                            */
-  EP0STATE_SETUP_OUT,      /* OUT SETUP packet received.  Waiting for the DATA
-                            * OUT phase of SETUP Packet to complete before
-                            * processing a SETUP command (without a USB request):
-                            *   SET:    Set in stm32_rxinterrupt() when SETUP OUT
-                            *           packet is received.
-                            *   TESTED: In stm32_ep0out_receive()
-                            */
-  EP0STATE_SETUP_READY,    /* IN SETUP packet received -OR- OUT SETUP packet and
-                            * accompanying data have been received.  Processing
-                            * of SETUP command will happen soon.
-                            *   SET:    (1) stm32_ep0out_receive() when the OUT
-                            *           SETUP data phase completes, or (2)
-                            *           stm32_rxinterrupt() when an IN SETUP is
-                            *           packet received.
-                            *   TESTED: Tested in stm32_epout_interrupt() when
-                            *           SETUP phase is done to see if the SETUP
-                            *           command is ready to be processed.  Also
-                            *           tested in stm32_ep0out_setup() just to
-                            *           double-check that we have a SETUP request
-                            *           and any accompanying data.
-                            */
-  EP0STATE_SETUP_PROCESS,  /* SETUP Packet is being processed by stm32_ep0out_setup():
-                            *   SET:    When SETUP packet received in EP0 OUT
-                            *   TESTED: Never
-                            */
-  EP0STATE_SETUPRESPONSE,  /* Short SETUP response write (without a USB request):
-                            *   SET:    When SETUP response is sent by
-                            *           stm32_ep0in_setupresponse()
-                            *   TESTED: Never
-                            */
-  EP0STATE_DATA_IN,        /* Waiting for data out stage (with a USB request):
-                            *   SET:    In stm32_epin_request() when a write
-                            *           request is processed on EP0.
-                            *   TESTED: In stm32_epin() to see if we should
-                            *           revert to SETUP processing.
-                            */
-  EP0STATE_DATA_OUT        /* Waiting for data in phase to complete ( with a
-                            * USB request)
-                            *   SET:    In stm32_epout_request() when a read
-                            *           request is processed on EP0.
-                            *   TESTED: In stm32_epout() to see if we should
-                            *           revert to SETUP processing
-                            */
+  EP0STATE_IDLE = 0,          /* Idle State, leave on receiving a SETUP
+                               * packet or epsubmit: SET: In stm32_epin() and
+                               * stm32_epout() when we revert from request
+                               * processing to SETUP processing.  TESTED:
+                               * Never */
+  EP0STATE_SETUP_OUT,         /* OUT SETUP packet received.  Waiting for the
+                               * DATA OUT phase of SETUP Packet to complete
+                               * before processing a SETUP command (without a
+                               * USB request): SET: Set in
+                               * stm32_rxinterrupt() when SETUP OUT packet is
+                               * received.  TESTED: In stm32_ep0out_receive() */
+  EP0STATE_SETUP_READY,       /* IN SETUP packet received -OR- OUT SETUP
+                               * packet and accompanying data have been
+                               * received.  Processing of SETUP command will
+                               * happen soon.  SET: (1)
+                               * stm32_ep0out_receive() when the OUT SETUP
+                               * data phase completes, or (2)
+                               * stm32_rxinterrupt() when an IN SETUP is
+                               * packet received.  TESTED: Tested in
+                               * stm32_epout_interrupt() when SETUP phase is
+                               * done to see if the SETUP command is ready to
+                               * be processed.  Also tested in
+                               * stm32_ep0out_setup() just to double-check
+                               * that we have a SETUP request and any
+                               * accompanying data. */
+  EP0STATE_SETUP_PROCESS,     /* SETUP Packet is being processed by
+                               * stm32_ep0out_setup(): SET: When SETUP packet
+                               * received in EP0 OUT TESTED: Never */
+  EP0STATE_SETUPRESPONSE,     /* Short SETUP response write (without a USB
+                               * request): SET: When SETUP response is sent
+                               * by stm32_ep0in_setupresponse() TESTED: Never */
+  EP0STATE_DATA_IN,           /* Waiting for data out stage (with a USB
+                               * request): SET: In stm32_epin_request() when
+                               * a write request is processed on EP0.
+                               * TESTED: In stm32_epin() to see if we should
+                               * revert to SETUP processing. */
+  EP0STATE_DATA_OUT           /* Waiting for data in phase to complete ( with
+                               * a USB request) SET: In stm32_epout_request()
+                               * when a read request is processed on EP0.
+                               * TESTED: In stm32_epout() to see if we should
+                               * revert to SETUP processing */
 };
 
 /* Parsed control request */
 
 struct stm32_ctrlreq_s
 {
-  uint8_t  type;
-  uint8_t  req;
+  uint8_t type;
+  uint8_t req;
   uint16_t value;
   uint16_t index;
   uint16_t len;
@@ -459,8 +496,8 @@ struct stm32_ctrlreq_s
 
 struct stm32_req_s
 {
-  struct usbdev_req_s  req;           /* Standard USB request */
-  struct stm32_req_s  *flink;         /* Supports a singly linked list */
+  struct usbdev_req_s req;    /* Standard USB request */
+  struct stm32_req_s *flink;  /* Supports a singly linked list */
 };
 
 /* This is the internal representation of an endpoint */
@@ -472,20 +509,21 @@ struct stm32_ep_s
    * to struct stm32_ep_s.
    */
 
-  struct usbdev_ep_s      ep;          /* Standard endpoint structure */
+  struct usbdev_ep_s ep;      /* Standard endpoint structure */
 
   /* STM32-specific fields */
 
-  struct stm32_usbdev_s *dev;          /* Reference to private driver data */
-  struct stm32_req_s    *head;         /* Request list for this endpoint */
-  struct stm32_req_s    *tail;
-  uint8_t                epphy;        /* Physical EP address */
-  uint8_t                eptype:2;     /* Endpoint type */
-  uint8_t                active:1;     /* 1: A request is being processed */
-  uint8_t                stalled:1;    /* 1: Endpoint is stalled */
-  uint8_t                isin:1;       /* 1: IN Endpoint */
-  uint8_t                odd:1;        /* 1: Odd frame */
-  uint8_t                zlp:1;        /* 1: Transmit a zero-length-packet (IN EPs only) */
+  struct stm32_usbdev_s *dev; /* Reference to private driver data */
+  struct stm32_req_s *head;   /* Request list for this endpoint */
+  struct stm32_req_s *tail;
+  uint8_t epphy;              /* Physical EP address */
+  uint8_t eptype:2;           /* Endpoint type */
+  uint8_t active:1;           /* 1: A request is being processed */
+  uint8_t stalled:1;          /* 1: Endpoint is stalled */
+  uint8_t isin:1;             /* 1: IN Endpoint */
+  uint8_t odd:1;              /* 1: Odd frame */
+  uint8_t zlp:1;              /* 1: Transmit a zero-length-packet (IN EPs
+                               * only) */
 };
 
 /* This structure retains the state of the USB device controller */
@@ -493,11 +531,11 @@ struct stm32_ep_s
 struct stm32_usbdev_s
 {
   /* Common device fields.  This must be the first thing defined in the
-   * structure so that it is possible to simply cast from struct usbdev_s
-   * to struct stm32_usbdev_s.
+   * structure so that it is possible to simply cast from struct usbdev_s to
+   * struct stm32_usbdev_s.
    */
 
-  struct usbdev_s         usbdev;
+  struct usbdev_s usbdev;
 
   /* The bound device class driver */
 
@@ -505,17 +543,17 @@ struct stm32_usbdev_s
 
   /* STM32-specific fields */
 
-  uint8_t                 stalled:1;     /* 1: Protocol stalled */
-  uint8_t                 selfpowered:1; /* 1: Device is self powered */
-  uint8_t                 addressed:1;   /* 1: Peripheral address has been set */
-  uint8_t                 configured:1;  /* 1: Class driver has been configured */
-  uint8_t                 wakeup:1;      /* 1: Device remote wake-up */
-  uint8_t                 dotest:1;      /* 1: Test mode selected */
+  uint8_t stalled:1;          /* 1: Protocol stalled */
+  uint8_t selfpowered:1;      /* 1: Device is self powered */
+  uint8_t addressed:1;        /* 1: Peripheral address has been set */
+  uint8_t configured:1;       /* 1: Class driver has been configured */
+  uint8_t wakeup:1;           /* 1: Device remote wake-up */
+  uint8_t dotest:1;           /* 1: Test mode selected */
 
-  uint8_t                 devstate:4;    /* See enum stm32_devstate_e */
-  uint8_t                 ep0state:4;    /* See enum stm32_ep0state_e */
-  uint8_t                 testmode:4;    /* Selected test mode */
-  uint8_t                 epavail[2];    /* Bitset of available OUT/IN endpoints */
+  uint8_t devstate:4;         /* See enum stm32_devstate_e */
+  uint8_t ep0state:4;         /* See enum stm32_ep0state_e */
+  uint8_t testmode:4;         /* Selected test mode */
+  uint8_t epavail[2];         /* Bitset of available OUT/IN endpoints */
 
   /* E0 SETUP data buffering.
    *
@@ -523,28 +561,28 @@ struct stm32_usbdev_s
    *   The 8-byte SETUP request is received on the EP0 OUT endpoint and is
    *   saved.
    *
-   * ep0data
-   *   For OUT SETUP requests, the SETUP data phase must also complete before
-   *   the SETUP command can be processed.  The pack receipt logic will save
-   *   the accompanying EP0 IN data in ep0data[] before the SETUP command is
-   *   processed.
+   * ep0data:
+   *   For OUT SETUP requests, the SETUP data phase must also complete
+   *   before the SETUP command can be processed.  The pack receipt logic
+   *   will save the accompanying EP0 IN data in ep0data[] before the
+   *   SETUP command is processed.
    *
    *   For IN SETUP requests, the DATA phase will occur AFTER the SETUP
-   *   control request is processed.  In that case, ep0data[] may be used as
-   *   the response buffer.
+   *   control request is processed.  In that case, ep0data[] may be used
+   *   as the response buffer.
    *
-   * ep0datlen
+   * ep0datlen:
    *   Length of OUT DATA received in ep0data[] (Not used with OUT data)
    */
 
-  struct usb_ctrlreq_s    ctrlreq;
-  uint8_t                 ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE];
-  uint16_t                ep0datlen;
+  struct usb_ctrlreq_s ctrlreq;
+  uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE];
+  uint16_t ep0datlen;
 
   /* The endpoint lists */
 
-  struct stm32_ep_s       epin[STM32_NENDPOINTS];
-  struct stm32_ep_s       epout[STM32_NENDPOINTS];
+  struct stm32_ep_s epin[STM32_NENDPOINTS];
+  struct stm32_ep_s epout[STM32_NENDPOINTS];
 };
 
 /****************************************************************************
@@ -553,76 +591,76 @@ struct stm32_usbdev_s
 
 /* Register operations ******************************************************/
 
-#if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
-static uint32_t    stm32_getreg(uint32_t addr);
-static void        stm32_putreg(uint32_t val, uint32_t addr);
-#else
-# define stm32_getreg(addr)     getreg32(addr)
-# define stm32_putreg(val,addr) putreg32(val,addr)
-#endif
+#  if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+static uint32_t stm32_getreg(uint32_t addr);
+static void stm32_putreg(uint32_t val, uint32_t addr);
+#  else
+#    define stm32_getreg(addr)     getreg32(addr)
+#    define stm32_putreg(val,addr) putreg32(val,addr)
+#  endif
 
 /* Request queue operations **************************************************/
 
-static FAR struct stm32_req_s *stm32_req_remfirst(FAR struct stm32_ep_s *privep);
-static bool       stm32_req_addlast(FAR struct stm32_ep_s *privep,
-                    FAR struct stm32_req_s *req);
+static FAR struct stm32_req_s *stm32_req_remfirst(FAR struct stm32_ep_s
+                                                  *privep);
+static bool stm32_req_addlast(FAR struct stm32_ep_s *privep,
+                              FAR struct stm32_req_s *req);
 
 /* Low level data transfers and request operations ***************************/
+
 /* Special endpoint 0 data transfer logic */
 
-static void        stm32_ep0in_setupresponse(FAR struct stm32_usbdev_s *priv,
-                     FAR uint8_t *data, uint32_t nbytes);
+static void stm32_ep0in_setupresponse(FAR struct stm32_usbdev_s *priv,
+                                      FAR uint8_t * data, uint32_t nbytes);
 static inline void stm32_ep0in_transmitzlp(FAR struct stm32_usbdev_s *priv);
-static void        stm32_ep0in_activate(void);
+static void stm32_ep0in_activate(void);
 
-static void        stm32_ep0out_ctrlsetup(FAR struct stm32_usbdev_s *priv);
+static void stm32_ep0out_ctrlsetup(FAR struct stm32_usbdev_s *priv);
 
 /* IN request and TxFIFO handling */
 
-static void        stm32_txfifo_write(FAR struct stm32_ep_s *privep,
-                     FAR uint8_t *buf, int nbytes);
-static void        stm32_epin_transfer(FAR struct stm32_ep_s *privep,
-                     FAR uint8_t *buf, int nbytes);
-static void        stm32_epin_request(FAR struct stm32_usbdev_s *priv,
-                     FAR struct stm32_ep_s *privep);
+static void stm32_txfifo_write(FAR struct stm32_ep_s *privep,
+                               FAR uint8_t * buf, int nbytes);
+static void stm32_epin_transfer(FAR struct stm32_ep_s *privep,
+                                FAR uint8_t * buf, int nbytes);
+static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
+                               FAR struct stm32_ep_s *privep);
 
 /* OUT request and RxFIFO handling */
 
-static void        stm32_rxfifo_read(FAR struct stm32_ep_s *privep,
-                     FAR uint8_t *dest, uint16_t len);
-static void        stm32_rxfifo_discard(FAR struct stm32_ep_s *privep, int len);
-static void        stm32_epout_complete(FAR struct stm32_usbdev_s *priv,
-                     FAR struct stm32_ep_s *privep);
-static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt);
+static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep,
+                              FAR uint8_t * dest, uint16_t len);
+static void stm32_rxfifo_discard(FAR struct stm32_ep_s *privep, int len);
+static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv,
+                                 FAR struct stm32_ep_s *privep);
+static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep,
+                                        int bcnt);
 static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt);
-static void        stm32_epout_request(FAR struct stm32_usbdev_s *priv,
-                     FAR struct stm32_ep_s *privep);
+static void stm32_epout_request(FAR struct stm32_usbdev_s *priv,
+                                FAR struct stm32_ep_s *privep);
 
 /* General request handling */
 
-static void        stm32_ep_flush(FAR struct stm32_ep_s *privep);
-static void        stm32_req_complete(FAR struct stm32_ep_s *privep,
-                     int16_t result);
-static void        stm32_req_cancel(FAR struct stm32_ep_s *privep,
-                     int16_t status);
+static void stm32_ep_flush(FAR struct stm32_ep_s *privep);
+static void stm32_req_complete(FAR struct stm32_ep_s *privep, int16_t result);
+static void stm32_req_cancel(FAR struct stm32_ep_s *privep, int16_t status);
 
 /* Interrupt handling ********************************************************/
 
-static struct      stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv,
-                     uint16_t eplog);
-static int         stm32_req_dispatch(FAR struct stm32_usbdev_s *priv,
-                     FAR const struct usb_ctrlreq_s *ctrl);
-static void        stm32_usbreset(FAR struct stm32_usbdev_s *priv);
+static struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv,
+                                              uint16_t eplog);
+static int stm32_req_dispatch(FAR struct stm32_usbdev_s *priv,
+                              FAR const struct usb_ctrlreq_s *ctrl);
+static void stm32_usbreset(FAR struct stm32_usbdev_s *priv);
 
 /* Second level OUT endpoint interrupt processing */
 
 static inline void stm32_ep0out_testmode(FAR struct stm32_usbdev_s *priv,
-                     uint16_t index);
+                                         uint16_t index);
 static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv,
-                     FAR struct stm32_ctrlreq_s *ctrlreq);
+                                           FAR struct stm32_ctrlreq_s *ctrlreq);
 static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv);
-static inline void stm32_epout(FAR struct stm32_usbdev_s *priv,
-                     uint8_t epno);
+static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno);
 static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv);
 
 /* Second level IN endpoint interrupt processing */
@@ -630,7 +668,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv);
 static inline void stm32_epin_runtestmode(FAR struct stm32_usbdev_s *priv);
 static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno);
 static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv,
-                     int epno);
+                                          int epno);
 static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv);
 
 /* Other second level interrupt processing */
@@ -639,97 +677,95 @@ static inline void stm32_resumeinterrupt(FAR struct stm32_usbdev_s *priv);
 static inline void stm32_suspendinterrupt(FAR struct stm32_usbdev_s *priv);
 static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv);
 static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv);
-#ifdef CONFIG_USBDEV_ISOCHRONOUS
+#  ifdef CONFIG_USBDEV_ISOCHRONOUS
 static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv);
 static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv);
-#endif
-#ifdef CONFIG_USBDEV_VBUSSENSING
+#  endif
+#  ifdef CONFIG_USBDEV_VBUSSENSING
 static inline void stm32_sessioninterrupt(FAR struct stm32_usbdev_s *priv);
 static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv);
-#endif
+#  endif
 
 /* First level interrupt processing */
 
-static int         stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg);
+static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg);
 
 /* Endpoint operations *********************************************************/
+
 /* Global OUT NAK controls */
 
-static void        stm32_enablegonak(FAR struct stm32_ep_s *privep);
-static void        stm32_disablegonak(FAR struct stm32_ep_s *privep);
+static void stm32_enablegonak(FAR struct stm32_ep_s *privep);
+static void stm32_disablegonak(FAR struct stm32_ep_s *privep);
 
 /* Endpoint configuration */
 
-static int         stm32_epout_configure(FAR struct stm32_ep_s *privep,
-                     uint8_t eptype, uint16_t maxpacket);
-static int         stm32_epin_configure(FAR struct stm32_ep_s *privep,
-                     uint8_t eptype, uint16_t maxpacket);
-static int         stm32_ep_configure(FAR struct usbdev_ep_s *ep,
-                     FAR const struct usb_epdesc_s *desc, bool last);
-static void        stm32_ep0_configure(FAR struct stm32_usbdev_s *priv);
+static int stm32_epout_configure(FAR struct stm32_ep_s *privep,
+                                 uint8_t eptype, uint16_t maxpacket);
+static int stm32_epin_configure(FAR struct stm32_ep_s *privep,
+                                uint8_t eptype, uint16_t maxpacket);
+static int stm32_ep_configure(FAR struct usbdev_ep_s *ep,
+                              FAR const struct usb_epdesc_s *desc, bool last);
+static void stm32_ep0_configure(FAR struct stm32_usbdev_s *priv);
 
 /* Endpoint disable */
 
-static void        stm32_epout_disable(FAR struct stm32_ep_s *privep);
-static void        stm32_epin_disable(FAR struct stm32_ep_s *privep);
-static int         stm32_ep_disable(FAR struct usbdev_ep_s *ep);
+static void stm32_epout_disable(FAR struct stm32_ep_s *privep);
+static void stm32_epin_disable(FAR struct stm32_ep_s *privep);
+static int stm32_ep_disable(FAR struct usbdev_ep_s *ep);
 
 /* Endpoint request management */
 
 static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep);
-static void        stm32_ep_freereq(FAR struct usbdev_ep_s *ep,
-                     FAR struct usbdev_req_s *);
+static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep,
+                             FAR struct usbdev_req_s *);
 
 /* Endpoint buffer management */
 
-#ifdef CONFIG_USBDEV_DMA
-static void       *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep,
-                     uint16_t bytes);
-static void        stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep,
-                     FAR void *buf);
-#endif
+#  ifdef CONFIG_USBDEV_DMA
+static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, uint16_t bytes);
+static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf);
+#  endif
 
 /* Endpoint request submission */
 
-static int         stm32_ep_submit(FAR struct usbdev_ep_s *ep,
-                     struct usbdev_req_s *req);
+static int stm32_ep_submit(FAR struct usbdev_ep_s *ep,
+                           struct usbdev_req_s *req);
 
 /* Endpoint request cancellation */
 
-static int         stm32_ep_cancel(FAR struct usbdev_ep_s *ep,
-                     struct usbdev_req_s *req);
+static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep,
+                           struct usbdev_req_s *req);
 
 /* Stall handling */
 
-static int         stm32_epout_setstall(FAR struct stm32_ep_s *privep);
-static int         stm32_epin_setstall(FAR struct stm32_ep_s *privep);
-static int         stm32_ep_setstall(FAR struct stm32_ep_s *privep);
-static int         stm32_ep_clrstall(FAR struct stm32_ep_s *privep);
-static int         stm32_ep_stall(FAR struct usbdev_ep_s *ep, bool resume);
-static void        stm32_ep0_stall(FAR struct stm32_usbdev_s *priv);
+static int stm32_epout_setstall(FAR struct stm32_ep_s *privep);
+static int stm32_epin_setstall(FAR struct stm32_ep_s *privep);
+static int stm32_ep_setstall(FAR struct stm32_ep_s *privep);
+static int stm32_ep_clrstall(FAR struct stm32_ep_s *privep);
+static int stm32_ep_stall(FAR struct usbdev_ep_s *ep, bool resume);
+static void stm32_ep0_stall(FAR struct stm32_usbdev_s *priv);
 
 /* Endpoint allocation */
 
 static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev,
-                     uint8_t epno, bool in, uint8_t eptype);
-static void        stm32_ep_free(FAR struct usbdev_s *dev,
-                     FAR struct usbdev_ep_s *ep);
+                                              uint8_t epno, bool in,
+                                              uint8_t eptype);
+static void stm32_ep_free(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep);
 
 /* USB device controller operations ********************************************/
 
-static int         stm32_getframe(struct usbdev_s *dev);
-static int         stm32_wakeup(struct usbdev_s *dev);
-static int         stm32_selfpowered(struct usbdev_s *dev, bool selfpowered);
-static int         stm32_pullup(struct usbdev_s *dev, bool enable);
-static void        stm32_setaddress(struct stm32_usbdev_s *priv,
-                     uint16_t address);
-static int         stm32_txfifo_flush(uint32_t txfnum);
-static int         stm32_rxfifo_flush(void);
+static int stm32_getframe(struct usbdev_s *dev);
+static int stm32_wakeup(struct usbdev_s *dev);
+static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered);
+static int stm32_pullup(struct usbdev_s *dev, bool enable);
+static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address);
+static int stm32_txfifo_flush(uint32_t txfnum);
+static int stm32_rxfifo_flush(void);
 
 /* Initialization **************************************************************/
 
-static void        stm32_swinitialize(FAR struct stm32_usbdev_s *priv);
-static void        stm32_hwinitialize(FAR struct stm32_usbdev_s *priv);
+static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv);
+static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv);
 
 /****************************************************************************
  * Private Data
@@ -743,123 +779,123 @@ static struct stm32_usbdev_s g_otghsdev;
 
 static const struct usbdev_epops_s g_epops =
 {
-  .configure   = stm32_ep_configure,
-  .disable     = stm32_ep_disable,
-  .allocreq    = stm32_ep_allocreq,
-  .freereq     = stm32_ep_freereq,
-#ifdef CONFIG_USBDEV_DMA
+  .configure = stm32_ep_configure,
+  .disable = stm32_ep_disable,
+  .allocreq = stm32_ep_allocreq,
+  .freereq = stm32_ep_freereq,
+#  ifdef CONFIG_USBDEV_DMA
   .allocbuffer = stm32_ep_allocbuffer,
-  .freebuffer  = stm32_ep_freebuffer,
-#endif
-  .submit      = stm32_ep_submit,
-  .cancel      = stm32_ep_cancel,
-  .stall       = stm32_ep_stall,
+  .freebuffer = stm32_ep_freebuffer,
+#  endif
+  .submit = stm32_ep_submit,
+  .cancel = stm32_ep_cancel,
+  .stall = stm32_ep_stall,
 };
 
 static const struct usbdev_ops_s g_devops =
 {
-  .allocep     = stm32_ep_alloc,
-  .freeep      = stm32_ep_free,
-  .getframe    = stm32_getframe,
-  .wakeup      = stm32_wakeup,
+  .allocep = stm32_ep_alloc,
+  .freeep = stm32_ep_free,
+  .getframe = stm32_getframe,
+  .wakeup = stm32_wakeup,
   .selfpowered = stm32_selfpowered,
-  .pullup      = stm32_pullup,
+  .pullup = stm32_pullup,
 };
 
 /* Device error strings that may be enabled for more descriptive USB trace
  * output.
  */
 
-#ifdef CONFIG_USBDEV_TRACE_STRINGS
+#  ifdef CONFIG_USBDEV_TRACE_STRINGS
 const struct trace_msg_t g_usb_trace_strings_deverror[] =
 {
-  TRACE_STR(STM32_TRACEERR_ALLOCFAIL       ),
-  TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE ),
-  TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS ),
-  TRACE_STR(STM32_TRACEERR_BADEPNO         ),
-  TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS  ),
-  TRACE_STR(STM32_TRACEERR_BADGETCONFIG    ),
-  TRACE_STR(STM32_TRACEERR_BADGETSETDESC   ),
-  TRACE_STR(STM32_TRACEERR_BADGETSTATUS    ),
-  TRACE_STR(STM32_TRACEERR_BADSETADDRESS   ),
-  TRACE_STR(STM32_TRACEERR_BADSETCONFIG    ),
-  TRACE_STR(STM32_TRACEERR_BADSETFEATURE   ),
-  TRACE_STR(STM32_TRACEERR_BADTESTMODE     ),
-  TRACE_STR(STM32_TRACEERR_BINDFAILED      ),
-  TRACE_STR(STM32_TRACEERR_DISPATCHSTALL   ),
-  TRACE_STR(STM32_TRACEERR_DRIVER          ),
+  TRACE_STR(STM32_TRACEERR_ALLOCFAIL),
+  TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE),
+  TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS),
+  TRACE_STR(STM32_TRACEERR_BADEPNO),
+  TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS),
+  TRACE_STR(STM32_TRACEERR_BADGETCONFIG),
+  TRACE_STR(STM32_TRACEERR_BADGETSETDESC),
+  TRACE_STR(STM32_TRACEERR_BADGETSTATUS),
+  TRACE_STR(STM32_TRACEERR_BADSETADDRESS),
+  TRACE_STR(STM32_TRACEERR_BADSETCONFIG),
+  TRACE_STR(STM32_TRACEERR_BADSETFEATURE),
+  TRACE_STR(STM32_TRACEERR_BADTESTMODE),
+  TRACE_STR(STM32_TRACEERR_BINDFAILED),
+  TRACE_STR(STM32_TRACEERR_DISPATCHSTALL),
+  TRACE_STR(STM32_TRACEERR_DRIVER),
   TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED),
-  TRACE_STR(STM32_TRACEERR_EP0NOSETUP      ),
-  TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED ),
-  TRACE_STR(STM32_TRACEERR_EPINNULLPACKET  ),
-  TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED  ),
-  TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET ),
-  TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED ),
-  TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ  ),
-  TRACE_STR(STM32_TRACEERR_INVALIDPARMS    ),
-  TRACE_STR(STM32_TRACEERR_IRQREGISTRATION ),
-  TRACE_STR(STM32_TRACEERR_NOEP            ),
-  TRACE_STR(STM32_TRACEERR_NOTCONFIGURED   ),
-  TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY     ),
-  TRACE_STR(STM32_TRACEERR_EPINREQEMPTY    ),
-  TRACE_STR(STM32_TRACEERR_NOOUTSETUP      ),
-  TRACE_STR(STM32_TRACEERR_POLLTIMEOUT     ),
+  TRACE_STR(STM32_TRACEERR_EP0NOSETUP),
+  TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED),
+  TRACE_STR(STM32_TRACEERR_EPINNULLPACKET),
+  TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED),
+  TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET),
+  TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED),
+  TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ),
+  TRACE_STR(STM32_TRACEERR_INVALIDPARMS),
+  TRACE_STR(STM32_TRACEERR_IRQREGISTRATION),
+  TRACE_STR(STM32_TRACEERR_NOEP),
+  TRACE_STR(STM32_TRACEERR_NOTCONFIGURED),
+  TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY),
+  TRACE_STR(STM32_TRACEERR_EPINREQEMPTY),
+  TRACE_STR(STM32_TRACEERR_NOOUTSETUP),
+  TRACE_STR(STM32_TRACEERR_POLLTIMEOUT),
   TRACE_STR_END
 };
-#endif
+#  endif
 
 /* Interrupt event strings that may be enabled for more descriptive USB trace
  * output.
  */
 
-#ifdef CONFIG_USBDEV_TRACE_STRINGS
+#  ifdef CONFIG_USBDEV_TRACE_STRINGS
 const struct trace_msg_t g_usb_trace_strings_intdecode[] =
 {
-  TRACE_STR(STM32_TRACEINTID_USB         ),
-  TRACE_STR(STM32_TRACEINTID_INTPENDING  ),
-  TRACE_STR(STM32_TRACEINTID_EPOUT       ),
-  TRACE_STR(STM32_TRACEINTID_EPIN        ),
-  TRACE_STR(STM32_TRACEINTID_MISMATCH    ),
-  TRACE_STR(STM32_TRACEINTID_WAKEUP      ),
-  TRACE_STR(STM32_TRACEINTID_SUSPEND     ),
-  TRACE_STR(STM32_TRACEINTID_SOF         ),
-  TRACE_STR(STM32_TRACEINTID_RXFIFO      ),
-  TRACE_STR(STM32_TRACEINTID_DEVRESET    ),
-  TRACE_STR(STM32_TRACEINTID_ENUMDNE     ),
-  TRACE_STR(STM32_TRACEINTID_IISOIXFR    ),
-  TRACE_STR(STM32_TRACEINTID_IISOOXFR    ),
-  TRACE_STR(STM32_TRACEINTID_SRQ         ),
-  TRACE_STR(STM32_TRACEINTID_OTG         ),
-  TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC  ),
+  TRACE_STR(STM32_TRACEINTID_USB),
+  TRACE_STR(STM32_TRACEINTID_INTPENDING),
+  TRACE_STR(STM32_TRACEINTID_EPOUT),
+  TRACE_STR(STM32_TRACEINTID_EPIN),
+  TRACE_STR(STM32_TRACEINTID_MISMATCH),
+  TRACE_STR(STM32_TRACEINTID_WAKEUP),
+  TRACE_STR(STM32_TRACEINTID_SUSPEND),
+  TRACE_STR(STM32_TRACEINTID_SOF),
+  TRACE_STR(STM32_TRACEINTID_RXFIFO),
+  TRACE_STR(STM32_TRACEINTID_DEVRESET),
+  TRACE_STR(STM32_TRACEINTID_ENUMDNE),
+  TRACE_STR(STM32_TRACEINTID_IISOIXFR),
+  TRACE_STR(STM32_TRACEINTID_IISOOXFR),
+  TRACE_STR(STM32_TRACEINTID_SRQ),
+  TRACE_STR(STM32_TRACEINTID_OTG),
+  TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC),
   TRACE_STR(STM32_TRACEINTID_EPOUT_EPDISD),
-  TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP ),
-  TRACE_STR(STM32_TRACEINTID_DISPATCH    ),
-  TRACE_STR(STM32_TRACEINTID_GETSTATUS   ),
-  TRACE_STR(STM32_TRACEINTID_EPGETSTATUS ),
+  TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP),
+  TRACE_STR(STM32_TRACEINTID_DISPATCH),
+  TRACE_STR(STM32_TRACEINTID_GETSTATUS),
+  TRACE_STR(STM32_TRACEINTID_EPGETSTATUS),
   TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS),
-  TRACE_STR(STM32_TRACEINTID_IFGETSTATUS ),
+  TRACE_STR(STM32_TRACEINTID_IFGETSTATUS),
   TRACE_STR(STM32_TRACEINTID_CLEARFEATURE),
-  TRACE_STR(STM32_TRACEINTID_SETFEATURE  ),
-  TRACE_STR(STM32_TRACEINTID_SETADDRESS  ),
-  TRACE_STR(STM32_TRACEINTID_GETSETDESC  ),
-  TRACE_STR(STM32_TRACEINTID_GETCONFIG   ),
-  TRACE_STR(STM32_TRACEINTID_SETCONFIG   ),
-  TRACE_STR(STM32_TRACEINTID_GETSETIF    ),
-  TRACE_STR(STM32_TRACEINTID_SYNCHFRAME  ),
-  TRACE_STR(STM32_TRACEINTID_EPIN_XFRC   ),
-  TRACE_STR(STM32_TRACEINTID_EPIN_TOC    ),
-  TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE ),
-  TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD ),
-  TRACE_STR(STM32_TRACEINTID_EPIN_TXFE   ),
+  TRACE_STR(STM32_TRACEINTID_SETFEATURE),
+  TRACE_STR(STM32_TRACEINTID_SETADDRESS),
+  TRACE_STR(STM32_TRACEINTID_GETSETDESC),
+  TRACE_STR(STM32_TRACEINTID_GETCONFIG),
+  TRACE_STR(STM32_TRACEINTID_SETCONFIG),
+  TRACE_STR(STM32_TRACEINTID_GETSETIF),
+  TRACE_STR(STM32_TRACEINTID_SYNCHFRAME),
+  TRACE_STR(STM32_TRACEINTID_EPIN_XFRC),
+  TRACE_STR(STM32_TRACEINTID_EPIN_TOC),
+  TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE),
+  TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD),
+  TRACE_STR(STM32_TRACEINTID_EPIN_TXFE),
   TRACE_STR(STM32_TRACEINTID_EPIN_EMPWAIT),
-  TRACE_STR(STM32_TRACEINTID_OUTNAK      ),
-  TRACE_STR(STM32_TRACEINTID_OUTRECVD    ),
-  TRACE_STR(STM32_TRACEINTID_OUTDONE     ),
-  TRACE_STR(STM32_TRACEINTID_SETUPDONE   ),
-  TRACE_STR(STM32_TRACEINTID_SETUPRECVD  ),
+  TRACE_STR(STM32_TRACEINTID_OUTNAK),
+  TRACE_STR(STM32_TRACEINTID_OUTRECVD),
+  TRACE_STR(STM32_TRACEINTID_OUTDONE),
+  TRACE_STR(STM32_TRACEINTID_SETUPDONE),
+  TRACE_STR(STM32_TRACEINTID_SETUPRECVD),
   TRACE_STR_END
 };
-#endif
+#  endif
 
 /****************************************************************************
  * Private Functions
@@ -873,7 +909,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] =
  *
  ****************************************************************************/
 
-#if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#  if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
 static uint32_t stm32_getreg(uint32_t addr)
 {
   static uint32_t prevaddr = 0;
@@ -884,8 +920,8 @@ static uint32_t stm32_getreg(uint32_t addr)
 
   uint32_t val = getreg32(addr);
 
-  /* Is this the same value that we read from the same register last time?  Are
-   * we polling the register?  If so, suppress some of the output.
+  /* Is this the same value that we read from the same register last time? Are
+   * we polling the register? If so, suppress some of the output.
    */
 
   if (addr == prevaddr && val == preval)
@@ -911,14 +947,14 @@ static uint32_t stm32_getreg(uint32_t addr)
         {
           /* Yes.. then show how many times the value repeated */
 
-          uinfo("[repeats %d more times]\n", count-3);
+          uinfo("[repeats %d more times]\n", count - 3);
         }
 
       /* Save the new address, value, and count */
 
       prevaddr = addr;
-      preval   = val;
-      count    = 1;
+      preval = val;
+      count = 1;
     }
 
   /* Show the register value read */
@@ -926,7 +962,7 @@ static uint32_t stm32_getreg(uint32_t addr)
   uinfo("%08x->%08x\n", addr, val);
   return val;
 }
-#endif
+#  endif
 
 /****************************************************************************
  * Name: stm32_putreg
@@ -936,7 +972,7 @@ static uint32_t stm32_getreg(uint32_t addr)
  *
  ****************************************************************************/
 
-#if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
+#  if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES)
 static void stm32_putreg(uint32_t val, uint32_t addr)
 {
   /* Show the register value being written */
@@ -947,7 +983,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr)
 
   putreg32(val, addr);
 }
-#endif
+#  endif
 
 /****************************************************************************
  * Name: stm32_req_remfirst
@@ -997,7 +1033,7 @@ static bool stm32_req_addlast(FAR struct stm32_ep_s *privep,
   else
     {
       privep->tail->flink = req;
-      privep->tail        = req;
+      privep->tail = req;
     }
 
   return is_empty;
@@ -1012,7 +1048,7 @@ static bool stm32_req_addlast(FAR struct stm32_ep_s *privep,
  ****************************************************************************/
 
 static void stm32_ep0in_setupresponse(FAR struct stm32_usbdev_s *priv,
-                                      FAR uint8_t *buf, uint32_t nbytes)
+                                      FAR uint8_t * buf, uint32_t nbytes)
 {
   stm32_epin_transfer(&priv->epin[EP0], buf, nbytes);
   priv->ep0state = EP0STATE_SETUPRESPONSE;
@@ -1044,28 +1080,28 @@ static void stm32_ep0in_activate(void)
 {
   uint32_t regval;
 
-  /* Set the max packet size  of the IN EP. */
+  /* Set the max packet size of the IN EP. */
 
-  regval  = stm32_getreg(STM32_OTG_DIEPCTL(0));
+  regval = stm32_getreg(STM32_OTG_DIEPCTL(0));
   regval &= ~OTG_DIEPCTL0_MPSIZ_MASK;
 
-#if CONFIG_USBDEV_EP0_MAXSIZE == 8
+#  if CONFIG_USBDEV_EP0_MAXSIZE == 8
   regval |= OTG_DIEPCTL0_MPSIZ_8;
-#elif CONFIG_USBDEV_EP0_MAXSIZE == 16
+#  elif CONFIG_USBDEV_EP0_MAXSIZE == 16
   regval |= OTG_DIEPCTL0_MPSIZ_16;
-#elif CONFIG_USBDEV_EP0_MAXSIZE == 32
+#  elif CONFIG_USBDEV_EP0_MAXSIZE == 32
   regval |= OTG_DIEPCTL0_MPSIZ_32;
-#elif CONFIG_USBDEV_EP0_MAXSIZE == 64
+#  elif CONFIG_USBDEV_EP0_MAXSIZE == 64
   regval |= OTG_DIEPCTL0_MPSIZ_64;
-#else
-#  error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE"
-#endif
+#  else
+#    error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE"
+#  endif
 
   stm32_putreg(regval, STM32_OTG_DIEPCTL(0));
 
   /* Clear global IN NAK */
 
-  regval  = stm32_getreg(STM32_OTG_DCTL);
+  regval = stm32_getreg(STM32_OTG_DCTL);
   regval |= OTG_DCTL_CGINAK;
   stm32_putreg(regval, STM32_OTG_DCTL);
 }
@@ -1085,13 +1121,12 @@ static void stm32_ep0out_ctrlsetup(FAR struct stm32_usbdev_s *priv)
   /* Setup the hardware to perform the SETUP transfer */
 
   regval = (USB_SIZEOF_CTRLREQ * 3 << OTG_DOEPTSIZ0_XFRSIZ_SHIFT) |
-           (OTG_DOEPTSIZ0_PKTCNT) |
-           (3 << OTG_DOEPTSIZ0_STUPCNT_SHIFT);
+    (OTG_DOEPTSIZ0_PKTCNT) | (3 << OTG_DOEPTSIZ0_STUPCNT_SHIFT);
   stm32_putreg(regval, STM32_OTG_DOEPTSIZ(0));
 
   /* Then clear NAKing and enable the transfer */
 
-  regval  = stm32_getreg(STM32_OTG_DOEPCTL(0));
+  regval = stm32_getreg(STM32_OTG_DOEPCTL(0));
   regval |= (OTG_DOEPCTL0_CNAK | OTG_DOEPCTL0_EPENA);
   stm32_putreg(regval, STM32_OTG_DOEPCTL(0));
 }
@@ -1105,7 +1140,7 @@ static void stm32_ep0out_ctrlsetup(FAR struct stm32_usbdev_s *priv)
  ****************************************************************************/
 
 static void stm32_txfifo_write(FAR struct stm32_ep_s *privep,
-                               FAR uint8_t *buf, int nbytes)
+                               FAR uint8_t * buf, int nbytes)
 {
   uint32_t regaddr;
   uint32_t regval;
@@ -1128,10 +1163,10 @@ static void stm32_txfifo_write(FAR struct stm32_ep_s *privep,
        * and pack these into one 32-bit word (little endian).
        */
 
-      regval  = (uint32_t)*buf++;
-      regval |= ((uint32_t)*buf++) << 8;
-      regval |= ((uint32_t)*buf++) << 16;
-      regval |= ((uint32_t)*buf++) << 24;
+      regval = (uint32_t) * buf++;
+      regval |= ((uint32_t) * buf++) << 8;
+      regval |= ((uint32_t) * buf++) << 16;
+      regval |= ((uint32_t) * buf++) << 24;
 
       /* Then write the packet data to the TxFIFO */
 
@@ -1148,7 +1183,7 @@ static void stm32_txfifo_write(FAR struct stm32_ep_s *privep,
  ****************************************************************************/
 
 static void stm32_epin_transfer(FAR struct stm32_ep_s *privep,
-                                FAR uint8_t *buf, int nbytes)
+                                FAR uint8_t * buf, int nbytes)
 {
   uint32_t pktcnt;
   uint32_t regval;
@@ -1173,22 +1208,21 @@ static void stm32_epin_transfer(FAR struct stm32_ep_s *privep,
   else
     {
       /* No.. Program the transfer size and packet count .  First calculate:
-       *
-       * xfrsize = The total number of bytes to be sent.
-       * pktcnt  = the number of packets (of maxpacket bytes) required to
-       *   perform the transfer.
+       * xfrsize = The total number of bytes to be sent. pktcnt = the number of
+       * packets (of maxpacket bytes) required to perform the transfer.
        */
 
-      pktcnt  = ((uint32_t)nbytes + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket;
+      pktcnt =
+        ((uint32_t) nbytes + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket;
     }
 
   /* Set the XFRSIZ and PKTCNT */
 
   regval |= (pktcnt << OTG_DIEPTSIZ_PKTCNT_SHIFT);
-  regval |= ((uint32_t)nbytes << OTG_DIEPTSIZ_XFRSIZ_SHIFT);
+  regval |= ((uint32_t) nbytes << OTG_DIEPTSIZ_XFRSIZ_SHIFT);
 
-  /* If this is an isochronous endpoint, then set the multi-count field to
-   * the PKTCNT as well.
+  /* If this is an isochronous endpoint, then set the multi-count field to the
+   * PKTCNT as well.
    */
 
   if (privep->eptype == USB_EP_ATTR_XFER_ISOC)
@@ -1204,8 +1238,8 @@ static void stm32_epin_transfer(FAR struct stm32_ep_s *privep,
 
   regval = stm32_getreg(STM32_OTG_DIEPCTL(privep->epphy));
 
-  /* If this is an isochronous endpoint, then set the even/odd frame bit
-   * the DIEPCTLx register.
+  /* If this is an isochronous endpoint, then set the even/odd frame bit the
+   * DIEPCTLx register.
    */
 
   if (privep->eptype == USB_EP_ATTR_XFER_ISOC)
@@ -1261,19 +1295,22 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
   /* We get here in one of four possible ways.  From three interrupting
    * events:
    *
-   * 1. From stm32_epin as part of the transfer complete interrupt processing
-   *    This interrupt indicates that the last transfer has completed.
-   * 2. As part of the ITTXFE interrupt processing.  That interrupt indicates
-   *    that an IN token was received when the associated TxFIFO was empty.
-   * 3. From stm32_epin_txfifoempty as part of the TXFE interrupt processing.
-   *    The TXFE interrupt is only enabled when the TxFIFO is full and the
-   *    software must wait for space to become available in the TxFIFO.
+   * 1. From stm32_epin as part of the transfer complete interrupt
+   *    processing This interrupt indicates that the last transfer has
+   *    completed.
+   * 2. As part of the ITTXFE interrupt processing.  That interrupt
+   *    indicates that an IN token was received when the associated
+   *    TxFIFO was empty.
+   * 3. From stm32_epin_txfifoempty as part of the TXFE interrupt
+   *    processing.  The TXFEinterrupt is only enabled when the TxFIFO
+   *    is full and the software must wait for space to become available
+   *    in the TxFIFO.
    *
-   * And this function may be called immediately when the write request is
-   * queue to start up the next transaction.
+   * And this function may be called immediately when the write request
+   * is queued to start up the next transaction.
    *
-   * 4. From stm32_ep_submit when a new write request is received WHILE the
-   *    endpoint is not active (privep->active == false).
+   * 4. From stm32_ep_submit when a new write request is received WHILE
+   *    the endpoint is not active (privep->active == false).
    */
 
   /* Check the request from the head of the endpoint request queue */
@@ -1283,14 +1320,14 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
     {
       usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy);
 
-      /* There is no TX transfer in progress and no new pending TX
-       * requests to send.  To stop transmitting any data on a particular
-       * IN endpoint, the application must set the IN NAK bit. To set this
-       * bit, the following field must be programmed.
+      /* There is no TX transfer in progress and no new pending TX requests to
+       * send.  To stop transmitting any data on a particular IN endpoint, the
+       * application must set the IN NAK bit. To set this bit, the following
+       * field must be programmed.
        */
 
       regaddr = STM32_OTG_DIEPCTL(privep->epphy);
-      regval  = stm32_getreg(regaddr);
+      regval = stm32_getreg(regaddr);
       regval |= OTG_DIEPCTL_SNAK;
       stm32_putreg(regval, regaddr);
 
@@ -1301,43 +1338,41 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
     }
 
   uinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
-          privep->epphy, privreq, privreq->req.len,
-          privreq->req.xfrd, privep->zlp);
+        privep->epphy, privreq, privreq->req.len,
+        privreq->req.xfrd, privep->zlp);
 
-  /* Check for a special case:  If we are just starting a request (xfrd==0) and
-   * the class driver is trying to send a zero-length packet (len==0).  Then set
-   * the ZLP flag so that the packet will be sent.
+  /* Check for a special case: If we are just starting a request (xfrd==0) and
+   * the class driver is trying to send a zero-length packet (len==0).  Then
+   * set the ZLP flag so that the packet will be sent.
    */
 
   if (privreq->req.len == 0)
     {
-      /* The ZLP flag is set TRUE whenever we want to force the driver to
-       * send a zero-length-packet on the next pass through the loop (below).
-       * The flag is cleared whenever a packet is sent in the loop below.
+      /* The ZLP flag is set TRUE whenever we want to force the driver to send
+       * a zero-length-packet on the next pass through the loop (below). The
+       * flag is cleared whenever a packet is sent in the loop below.
        */
 
-       privep->zlp = true;
+      privep->zlp = true;
     }
 
-  /* Add one more packet to the TxFIFO.  We will wait for the transfer
-   * complete event before we add the next packet (or part of a packet
-   * to the TxFIFO).
-   *
-   * The documentation says that we can can multiple packets to the TxFIFO,
-   * but it seems that we need to get the transfer complete event before
-   * we can add the next (or maybe I have got something wrong?)
+  /* Add one more packet to the TxFIFO.  We will wait for the transfer complete
+   * event before we add the next packet (or part of a packet to the TxFIFO).
+   * The documentation says that we can can multiple packets to the TxFIFO, but
+   * it seems that we need to get the transfer complete event before we can add
+   * the next (or maybe I have got something wrong?)
    */
 
-#if 0
+#  if 0
   while (privreq->req.xfrd < privreq->req.len || privep->zlp)
-#else
+#  else
   if (privreq->req.xfrd < privreq->req.len || privep->zlp)
-#endif
+#  endif
     {
       /* Get the number of bytes left to be sent in the request */
 
       bytesleft = privreq->req.len - privreq->req.xfrd;
-      nbytes    = bytesleft;
+      nbytes = bytesleft;
 
       /* Assume no zero-length-packet on the next pass through this loop */
 
@@ -1349,28 +1384,27 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
 
       if (nbytes > 0)
         {
-          /* Either send the maxpacketsize or all of the remaining data in
-           * the request.
+          /* Either send the maxpacketsize or all of the remaining data in the
+           * request.
            */
 
           if (nbytes >= privep->ep.maxpacket)
             {
-              nbytes =  privep->ep.maxpacket;
+              nbytes = privep->ep.maxpacket;
 
               /* Handle the case where this packet is exactly the
-               * maxpacketsize.  Do we need to send a zero-length packet
-               * in this case?
+               * maxpacketsize.  Do we need to send a zero-length packet in
+               * this case?
                */
 
-              if (bytesleft ==  privep->ep.maxpacket &&
-                 (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0)
+              if (bytesleft == privep->ep.maxpacket &&
+                  (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0)
                 {
-                  /* The ZLP flag is set TRUE whenever we want to force
-                   * the driver to send a zero-length-packet on the next
-                   * pass through this loop. The flag is cleared (above)
-                   * whenever we are committed to sending any packet and
-                   * set here when we want to force one more pass through
-                   * the loop.
+                  /* The ZLP flag is set TRUE whenever we want to force the
+                   * driver to send a zero-length-packet on the next pass
+                   * through this loop. The flag is cleared (above) whenever we
+                   * are committed to sending any packet and set here when we
+                   * want to force one more pass through the loop.
                    */
 
                   privep->zlp = true;
@@ -1382,9 +1416,9 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
 
       nwords = (nbytes + 3) >> 2;
 
-      /* Get the number of 32-bit words available in the TxFIFO. The
-       * DXTFSTS indicates the amount of free space available in the
-       * endpoint TxFIFO. Values are in terms of 32-bit words:
+      /* Get the number of 32-bit words available in the TxFIFO. The DXTFSTS
+       * indicates the amount of free space available in the endpoint TxFIFO.
+       * Values are in terms of 32-bit words:
        *
        *   0: Endpoint TxFIFO is full
        *   1: 1 word available
@@ -1395,14 +1429,15 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
       regaddr = STM32_OTG_DTXFSTS(privep->epphy);
 
       /* Check for space in the TxFIFO.  If space in the TxFIFO is not
-       * available, then set up an interrupt to resume the transfer when
-       * the TxFIFO is empty.
+       * available, then set up an interrupt to resume the transfer when the
+       * TxFIFO is empty.
        */
 
       regval = stm32_getreg(regaddr);
       if ((int)(regval & OTG_DTXFSTS_MASK) < nwords)
         {
-          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), (uint16_t)regval);
+          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT),
+                   (uint16_t) regval);
 
           /* There is insufficient space in the TxFIFO.  Wait for a TxFIFO
            * empty interrupt and try again.
@@ -1451,8 +1486,8 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
     {
       usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd);
 
-      /* We are finished with the request (although the transfer has not
-       * yet completed).
+      /* We are finished with the request (although the transfer has not yet
+       * completed).
        */
 
       stm32_req_complete(privep, OK);
@@ -1468,13 +1503,13 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
  ****************************************************************************/
 
 static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep,
-                              FAR uint8_t *dest, uint16_t len)
+                              FAR uint8_t * dest, uint16_t len)
 {
   uint32_t regaddr;
   int i;
 
-  /* Get the address of the RxFIFO.  Note:  there is only one RxFIFO so
-   * we might as well use the address associated with EP0.
+  /* Get the address of the RxFIFO.  Note: there is only one RxFIFO so we might
+   * as well use the address associated with EP0.
    */
 
   regaddr = STM32_OTG_DFIFO_DEP(EP0);
@@ -1484,10 +1519,10 @@ static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep,
   for (i = 0; i < len; i += 4)
     {
       union
-      {
-        uint32_t w;
-        uint8_t  b[4];
-      } data;
+        {
+          uint32_t w;
+          uint8_t b[4];
+        } data;
 
       /* Read 1 x 32-bits of EP0 packet data */
 
@@ -1517,8 +1552,8 @@ static void stm32_rxfifo_discard(FAR struct stm32_ep_s *privep, int len)
       uint32_t regaddr;
       int i;
 
-      /* Get the address of the RxFIFO  Note:  there is only one RxFIFO so
-       * we might as well use the address associated with EP0.
+      /* Get the address of the RxFIFO Note: there is only one RxFIFO so we
+       * might as well use the address associated with EP0.
        */
 
       regaddr = STM32_OTG_DFIFO_DEP(EP0);
@@ -1548,8 +1583,8 @@ static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv,
 {
   struct stm32_req_s *privreq;
 
-  /* Since a transfer just completed, there must be a read request at the head of
-   * the endpoint request queue.
+  /* Since a transfer just completed, there must be a read request at the head
+   * of the endpoint request queue.
    */
 
   privreq = stm32_rqpeek(privep);
@@ -1567,7 +1602,7 @@ static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv,
     }
 
   uinfo("EP%d: len=%d xfrd=%d\n",
-          privep->epphy, privreq->req.len, privreq->req.xfrd);
+        privep->epphy, privreq->req.len, privreq->req.xfrd);
 
   /* Return the completed read request to the class driver and mark the state
    * IDLE.
@@ -1604,8 +1639,8 @@ static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt)
   uinfo("EP0: bcnt=%d\n", bcnt);
   usbtrace(TRACE_READ(EP0), bcnt);
 
-  /* Verify that an OUT SETUP request as received before this data was
-   * received in the RxFIFO.
+  /* Verify that an OUT SETUP request as received before this data was received
+   * in the RxFIFO.
    */
 
   if (priv->ep0state == EP0STATE_SETUP_OUT)
@@ -1617,21 +1652,21 @@ static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt)
 
       /* Do we have to discard any excess bytes? */
 
-      stm32_rxfifo_discard(privep,  bcnt - readlen);
+      stm32_rxfifo_discard(privep, bcnt - readlen);
 
       /* Now we can process the setup command */
 
-      privep->active  = false;
-      priv->ep0state  = EP0STATE_SETUP_READY;
+      privep->active = false;
+      priv->ep0state = EP0STATE_SETUP_READY;
       priv->ep0datlen = readlen;
 
       stm32_ep0out_setup(priv);
     }
   else
     {
-      /* This is an error.  We don't have any idea what to do with the EP0
-       * data in this case.  Just read and discard it so that the RxFIFO
-       * does not become constipated.
+      /* This is an error.  We don't have any idea what to do with the EP0 data
+       * in this case.  Just read and discard it so that the RxFIFO does not
+       * become constipated.
        */
 
       usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOOUTSETUP), priv->ep0state);
@@ -1666,11 +1701,12 @@ static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt)
     {
       /* Incoming data is available in the RxFIFO, but there is no read setup
        * to receive the receive the data.  This should not happen for data
-       * endpoints; those endpoints should have been NAKing any OUT data tokens.
+       * endpoints; those endpoints should have been NAKing any OUT data
+       * tokens.
        *
        * We should get here normally on OUT data phase following an OUT
-       * SETUP command.  EP0 data will still receive data in this case and it
-       * should not be NAKing.
+       * SETUP command.  EP0 data will still receive data in this case and
+       * it should not be NAKing.
        */
 
       if (privep->epphy == 0)
@@ -1694,12 +1730,13 @@ static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt)
       return;
     }
 
-  uinfo("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len, privreq->req.xfrd);
+  uinfo("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len,
+        privreq->req.xfrd);
   usbtrace(TRACE_READ(privep->epphy), bcnt);
 
   /* Get the number of bytes to transfer from the RxFIFO */
 
-  buflen  = privreq->req.len - privreq->req.xfrd;
+  buflen = privreq->req.len - privreq->req.xfrd;
   DEBUGASSERT(buflen > 0 && buflen >= bcnt);
   readlen = MIN(buflen, bcnt);
 
@@ -1741,8 +1778,8 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv,
   uint32_t xfrsize;
   uint32_t pktcnt;
 
-  /* Make sure that there is not already a pending request request.  If there is,
-   * just return, leaving the newly received request in the request queue.
+  /* Make sure that there is not already a pending request request.  If there
+   * is, just return, leaving the newly received request in the request queue.
    */
 
   if (!privep->active)
@@ -1754,21 +1791,24 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv,
 
       for (; ; )
         {
-          /* Get a reference to the request at the head of the endpoint's request queue */
+          /* Get a reference to the request at the head of the endpoint's
+           * request queue
+           */
 
           privreq = stm32_rqpeek(privep);
           if (!privreq)
             {
-              usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy);
+              usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY),
+                       privep->epphy);
 
-              /* There are no read requests to be setup.  Configure the hardware to
-               * NAK any incoming packets.  (This should already be the case.  I
-               * think that the hardware will automatically NAK after a transfer is
-               * completed until SNAK is cleared).
+              /* There are no read requests to be setup.  Configure the
+               * hardware to NAK any incoming packets.  (This should already be
+               * the case.  I think that the hardware will automatically NAK
+               * after a transfer is completed until SNAK is cleared).
                */
 
               regaddr = STM32_OTG_DOEPCTL(privep->epphy);
-              regval  = stm32_getreg(regaddr);
+              regval = stm32_getreg(regaddr);
               regval |= OTG_DOEPCTL_SNAK;
               stm32_putreg(regval, regaddr);
 
@@ -1799,35 +1839,36 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv,
         }
 
       /* Setup the pending read into the request buffer.  First calculate:
-       *
-       * pktcnt  = the number of packets (of maxpacket bytes) required to
+      *
+       * pktcnt = the number of packets (of maxpacket bytes) required to
        *   perform the transfer.
-       * xfrsize = The total number of bytes required (in units of
-       *   maxpacket bytes).
+       * xfrsize = The total number of bytes required (in units of maxpacket
+       *   bytes).
        */
 
-      pktcnt  = (privreq->req.len + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket;
+      pktcnt =
+        (privreq->req.len + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket;
       xfrsize = pktcnt * privep->ep.maxpacket;
 
       /* Then setup the hardware to perform this transfer */
 
       regaddr = STM32_OTG_DOEPTSIZ(privep->epphy);
-      regval  = stm32_getreg(regaddr);
+      regval = stm32_getreg(regaddr);
       regval &= ~(OTG_DOEPTSIZ_XFRSIZ_MASK | OTG_DOEPTSIZ_PKTCNT_MASK);
       regval |= (xfrsize << OTG_DOEPTSIZ_XFRSIZ_SHIFT);
-      regval |= (pktcnt  << OTG_DOEPTSIZ_PKTCNT_SHIFT);
+      regval |= (pktcnt << OTG_DOEPTSIZ_PKTCNT_SHIFT);
       stm32_putreg(regval, regaddr);
 
       /* Then enable the transfer */
 
       regaddr = STM32_OTG_DOEPCTL(privep->epphy);
-      regval  = stm32_getreg(regaddr);
+      regval = stm32_getreg(regaddr);
 
       /* When an isochronous transfer is enabled the Even/Odd frame bit must
        * also be set appropriately.
        */
 
-#ifdef CONFIG_USBDEV_ISOCHRONOUS
+#  ifdef CONFIG_USBDEV_ISOCHRONOUS
       if (privep->eptype == USB_EP_ATTR_XFER_ISOC)
         {
           if (privep->odd)
@@ -1839,7 +1880,7 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv,
               regval |= OTG_DOEPCTL_SEVNFRM;
             }
         }
-#endif
+#  endif
 
       /* Clearing NAKing and enable the transfer. */
 
@@ -1850,8 +1891,8 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv,
 
       privep->active = true;
 
-      /* EP0 is a special case.  We need to know when to switch back to
-       * normal SETUP processing.
+      /* EP0 is a special case.  We need to know when to switch back to normal
+       * SETUP processing.
        */
 
       if (privep->epphy == EP0)
@@ -1898,8 +1939,8 @@ static void stm32_req_complete(struct stm32_ep_s *privep, int16_t result)
   privreq = stm32_req_remfirst(privep);
   DEBUGASSERT(privreq != NULL);
 
-  /* If endpoint 0, temporarily reflect the state of protocol stalled
-   * in the callback.
+  /* If endpoint 0, temporarily reflect the state of protocol stalled in the
+   * callback.
    */
 
   bool stalled = privep->stalled;
@@ -1938,8 +1979,7 @@ static void stm32_req_cancel(struct stm32_ep_s *privep, int16_t status)
 
   while (!stm32_rqempty(privep))
     {
-      usbtrace(TRACE_COMPLETE(privep->epphy),
-               (stm32_rqpeek(privep))->req.xfrd);
+      usbtrace(TRACE_COMPLETE(privep->epphy), (stm32_rqpeek(privep))->req.xfrd);
       stm32_req_complete(privep, status);
     }
 }
@@ -2039,8 +2079,8 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv)
 
   stm32_txfifo_flush(OTG_GRSTCTL_TXFNUM_D(EP0));
 
-  /* Tell the class driver that we are disconnected. The class
-   * driver should then accept any new configurations.
+  /* Tell the class driver that we are disconnected. The class driver should
+   * then accept any new configurations.
    */
 
   if (priv->driver)
@@ -2055,7 +2095,7 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv)
 
   /* Disable all end point interrupts */
 
-  for (i = 0; i < STM32_NENDPOINTS ; i++)
+  for (i = 0; i < STM32_NENDPOINTS; i++)
     {
       /* Disable endpoint interrupts */
 
@@ -2102,7 +2142,11 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv)
 
   stm32_setaddress(priv, 0);
   priv->devstate = DEVSTATE_DEFAULT;
+#  if defined(CONFIG_STM32F7_INTERNAL_ULPI) ||  defined(CONFIG_STM32F7_EXTERNAL_ULPI)
+  priv->usbdev.speed = USB_SPEED_HIGH;
+#  else
   priv->usbdev.speed = USB_SPEED_FULL;
+#  endif
 
   /* Re-configure EP0 */
 
@@ -2151,9 +2195,9 @@ static inline void stm32_ep0out_testmode(FAR struct stm32_usbdev_s *priv,
 
     default:
       usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADTESTMODE), testmode);
-      priv->dotest   = false;
+      priv->dotest = false;
       priv->testmode = OTG_TESTMODE_DISABLED;
-      priv->stalled  = true;
+      priv->stalled = true;
     }
 
   priv->dotest = true;
@@ -2188,9 +2232,8 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv,
 
         usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), 0);
         if (!priv->addressed ||
-             ctrlreq->len != 2 ||
-            USB_REQ_ISOUT(ctrlreq->type) ||
-            ctrlreq->value != 0)
+            ctrlreq->len != 2 ||
+            USB_REQ_ISOUT(ctrlreq->type) || ctrlreq->value != 0)
           {
             priv->stalled = true;
           }
@@ -2204,7 +2247,8 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv,
                   privep = stm32_ep_findbyaddr(priv, ctrlreq->index);
                   if (!privep)
                     {
-                      usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0);
+                      usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS),
+                               0);
                       priv->stalled = true;
                     }
                   else
@@ -2228,19 +2272,23 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv,
                 {
                   if (ctrlreq->index == 0)
                     {
-                      usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVGETSTATUS), 0);
+                      usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVGETSTATUS),
+                               0);
 
-                      /* Features:  Remote Wakeup and self-powered */
+                      /* Features: Remote Wakeup and self-powered */
 
-                      priv->ep0data[0]  = (priv->selfpowered << USB_FEATURE_SELFPOWERED);
-                      priv->ep0data[0] |= (priv->wakeup      << USB_FEATURE_REMOTEWAKEUP);
-                      priv->ep0data[1]  = 0;
+                      priv->ep0data[0] =
+                        (priv->selfpowered << USB_FEATURE_SELFPOWERED);
+                      priv->ep0data[0] |=
+                        (priv->wakeup << USB_FEATURE_REMOTEWAKEUP);
+                      priv->ep0data[1] = 0;
 
                       stm32_ep0in_setupresponse(priv, priv->ep0data, 2);
                     }
                   else
                     {
-                      usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADDEVGETSTATUS), 0);
+                      usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADDEVGETSTATUS),
+                               0);
                       priv->stalled = true;
                     }
                 }
@@ -2336,7 +2384,7 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv,
                      ctrlreq->value == USB_FEATURE_TESTMODE &&
                      ((ctrlreq->index & 0xff) == 0))
               {
-                 stm32_ep0out_testmode(priv, ctrlreq->index);
+                stm32_ep0out_testmode(priv, ctrlreq->index);
               }
             else if (priv->configured)
               {
@@ -2367,17 +2415,15 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv,
          */
 
         usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), ctrlreq->value);
-        if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE &&
-            ctrlreq->index  == 0 &&
-            ctrlreq->len == 0 &&
-            ctrlreq->value < 128 &&
-            priv->devstate != DEVSTATE_CONFIGURED)
+        if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE
+            && ctrlreq->index == 0 && ctrlreq->len == 0 && ctrlreq->value < 128
+            && priv->devstate != DEVSTATE_CONFIGURED)
           {
-            /* Save the address.  We cannot actually change to the next address until
-             * the completion of the status phase.
+            /* Save the address.  We cannot actually change to the next address
+             * until the completion of the status phase.
              */
 
-            stm32_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]);
+            stm32_setaddress(priv, (uint16_t) priv->ctrlreq.value[0]);
             stm32_ep0in_transmitzlp(priv);
           }
         else
@@ -2389,7 +2435,7 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv,
       break;
 
     case USB_REQ_GETDESCRIPTOR:
-      /* type:  device-to-host; recipient = device
+      /* type:  device-to-host; recipient = device, interface
        * value: descriptor type and index
        * index: 0 or language ID;
        * len:   descriptor len; data = descriptor
@@ -2404,7 +2450,10 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv,
 
       {
         usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), 0);
-        if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE)
+        if (((ctrlreq->type & USB_REQ_RECIPIENT_MASK) ==
+             USB_REQ_RECIPIENT_DEVICE) ||
+            ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) ==
+             USB_REQ_RECIPIENT_INTERFACE))
           {
             (void)stm32_req_dispatch(priv, &priv->ctrlreq);
           }
@@ -2426,10 +2475,8 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv,
       {
         usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), 0);
         if (priv->addressed &&
-           (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE &&
-            ctrlreq->value == 0 &&
-            ctrlreq->index == 0 &&
-            ctrlreq->len == 1)
+            (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE
+            && ctrlreq->value == 0 && ctrlreq->index == 0 && ctrlreq->len == 1)
           {
             (void)stm32_req_dispatch(priv, &priv->ctrlreq);
           }
@@ -2451,9 +2498,8 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv,
       {
         usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), 0);
         if (priv->addressed &&
-            (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE &&
-            ctrlreq->index == 0 &&
-            ctrlreq->len == 0)
+            (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE
+            && ctrlreq->index == 0 && ctrlreq->len == 0)
           {
             /* Give the configuration to the class driver */
 
@@ -2466,15 +2512,15 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv,
 
             if (ret == OK)
               {
-                uint8_t cfg = (uint8_t)ctrlreq->value;
+                uint8_t cfg = (uint8_t) ctrlreq->value;
                 if (cfg != 0)
                   {
-                    priv->devstate   = DEVSTATE_CONFIGURED;
+                    priv->devstate = DEVSTATE_CONFIGURED;
                     priv->configured = true;
                   }
                 else
                   {
-                    priv->devstate   = DEVSTATE_ADDRESSED;
+                    priv->devstate = DEVSTATE_ADDRESSED;
                     priv->configured = false;
                   }
               }
@@ -2552,7 +2598,7 @@ static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv)
   /* Terminate any pending requests */
 
   stm32_req_cancel(&priv->epout[EP0], -EPROTO);
-  stm32_req_cancel(&priv->epin[EP0],  -EPROTO);
+  stm32_req_cancel(&priv->epin[EP0], -EPROTO);
 
   /* Assume NOT stalled */
 
@@ -2566,14 +2612,14 @@ static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv)
 
   /* And extract the little-endian 16-bit values to host order */
 
-  ctrlreq.type  = priv->ctrlreq.type;
-  ctrlreq.req   = priv->ctrlreq.req;
+  ctrlreq.type = priv->ctrlreq.type;
+  ctrlreq.req = priv->ctrlreq.req;
   ctrlreq.value = GETUINT16(priv->ctrlreq.value);
   ctrlreq.index = GETUINT16(priv->ctrlreq.index);
-  ctrlreq.len   = GETUINT16(priv->ctrlreq.len);
+  ctrlreq.len = GETUINT16(priv->ctrlreq.len);
 
   uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n",
-          ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
+        ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len);
 
   /* Check for a standard request */
 
@@ -2600,7 +2646,7 @@ static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv)
 
   /* Reset state/data associated with thie SETUP request */
 
-   priv->ep0datlen = 0;
+  priv->ep0datlen = 0;
 }
 
 /****************************************************************************
@@ -2622,9 +2668,8 @@ static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno)
     {
       privep = &priv->epout[EP0];
 
-      /* In the EP0STATE_DATA_OUT state, we are receiving data into the
-       * request buffer.  In that case, we must continue the request
-       * processing.
+      /* In the EP0STATE_DATA_OUT state, we are receiving data into the request
+       * buffer.  In that case, we must continue the request processing.
        */
 
       if (priv->ep0state == EP0STATE_DATA_OUT)
@@ -2633,8 +2678,8 @@ static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno)
 
           stm32_epout_complete(priv, privep);
 
-          /* If we are not actively processing an OUT request, then we
-           * need to setup to receive the next control request.
+          /* If we are not actively processing an OUT request, then we need to
+           * setup to receive the next control request.
            */
 
           if (!privep->active)
@@ -2645,8 +2690,8 @@ static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno)
         }
     }
 
-  /* For other endpoints, the only possibility is that we are continuing
-   * or finishing an OUT request.
+  /* For other endpoints, the only possibility is that we are continuing or
+   * finishing an OUT request.
    */
 
   else if (priv->devstate == DEVSTATE_CONFIGURED)
@@ -2679,27 +2724,27 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv)
    * interrupt status register.
    */
 
-  regval  = stm32_getreg(STM32_OTG_DAINT);
+  regval = stm32_getreg(STM32_OTG_DAINT);
   regval &= stm32_getreg(STM32_OTG_DAINTMSK);
-  daint   = (regval & OTG_DAINT_OEP_MASK) >> OTG_DAINT_OEP_SHIFT;
+  daint = (regval & OTG_DAINT_OEP_MASK) >> OTG_DAINT_OEP_SHIFT;
 
   if (daint == 0)
     {
       /* We got an interrupt, but there is no unmasked endpoint that caused
-       * it ?!  When this happens, the interrupt flag never gets cleared and
+       * it?! When this happens, the interrupt flag never gets cleared and
        * we are stuck in infinite interrupt loop.
        *
        * This shouldn't happen if we are diligent about handling timing
        * issues when masking endpoint interrupts. However, this workaround
-       * avoids infinite loop and allows operation to continue normally.  It
-       * works by clearing each endpoint flags, masked or not.
+       * avoids infinite loop and allows operation to continue normally.
+       * It works by clearing each endpoint flags, masked or not.
        */
 
-      regval  = stm32_getreg(STM32_OTG_DAINT);
-      daint   = (regval & OTG_DAINT_OEP_MASK) >> OTG_DAINT_OEP_SHIFT;
+      regval = stm32_getreg(STM32_OTG_DAINT);
+      daint = (regval & OTG_DAINT_OEP_MASK) >> OTG_DAINT_OEP_SHIFT;
 
       usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTUNEXPECTED),
-               (uint16_t)regval);
+               (uint16_t) regval);
 
       epno = 0;
       while (daint)
@@ -2708,7 +2753,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv)
             {
               regval = stm32_getreg(STM32_OTG_DOEPINT(epno));
               uerr("DOEPINT(%d) = %08x\n", epno, regval);
-              stm32_putreg(0xFF, STM32_OTG_DOEPINT(epno));
+              stm32_putreg(0xff, STM32_OTG_DOEPINT(epno));
             }
 
           epno++;
@@ -2729,18 +2774,19 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv)
         {
           /* Yes.. get the OUT endpoint interrupt status */
 
-          doepint  = stm32_getreg(STM32_OTG_DOEPINT(epno));
+          doepint = stm32_getreg(STM32_OTG_DOEPINT(epno));
           doepint &= stm32_getreg(STM32_OTG_DOEPMSK);
 
           /* Transfer completed interrupt.  This interrupt is trigged when
            * stm32_rxinterrupt() removes the last packet data from the RxFIFO.
-           * In this case, core internally sets the NAK bit for this endpoint to
-           * prevent it from receiving any more packets.
+           * In this case, core internally sets the NAK bit for this endpoint
+           * to prevent it from receiving any more packets.
            */
 
           if ((doepint & OTG_DOEPINT_XFRC) != 0)
             {
-              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC), (uint16_t)doepint);
+              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC),
+                       (uint16_t) doepint);
 
               /* Clear the bit in DOEPINTn for this interrupt */
 
@@ -2754,26 +2800,29 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv)
           /* Endpoint disabled interrupt (ignored because this interrupt is
            * used in polled mode by the endpoint disable logic).
            */
-#if 1
+#  if 1
           /* REVISIT: */
+
           if ((doepint & OTG_DOEPINT_EPDISD) != 0)
             {
-              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), (uint16_t)doepint);
+              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD),
+                       (uint16_t) doepint);
 
               /* Clear the bit in DOEPINTn for this interrupt */
 
               stm32_putreg(OTG_DOEPINT_EPDISD, STM32_OTG_DOEPINT(epno));
             }
-#endif
+#  endif
           /* Setup Phase Done (control EPs) */
 
           if ((doepint & OTG_DOEPINT_SETUP) != 0)
             {
-              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP), priv->ep0state);
+              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP),
+                       priv->ep0state);
 
               /* Handle the receipt of the IN SETUP packets now (OUT setup
-               * packet processing may be delayed until the accompanying
-               * OUT DATA is received)
+               * packet processing may be delayed until the accompanying OUT
+               * DATA is received)
                */
 
               if (priv->ep0state == EP0STATE_SETUP_READY)
@@ -2801,8 +2850,8 @@ static inline void stm32_epin_runtestmode(FAR struct stm32_usbdev_s *priv)
 {
   uint32_t regval = stm32_getreg(STM32_OTG_DCTL);
   regval &= OTG_DCTL_TCTL_MASK;
-  regval |= (uint32_t)priv->testmode << OTG_DCTL_TCTL_SHIFT;
-  stm32_putreg(regval , STM32_OTG_DCTL);
+  regval |= (uint32_t) priv->testmode << OTG_DCTL_TCTL_SHIFT;
+  stm32_putreg(regval, STM32_OTG_DCTL);
 
   priv->dotest = 0;
   priv->testmode = OTG_TESTMODE_DISABLED;
@@ -2826,7 +2875,7 @@ static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno)
   if (epno == 0)
     {
       /* In the EP0STATE_DATA_IN state, we are sending data from request
-       * buffer.  In that case, we must continue the request processing.
+       * buffer.  In that case, we must continue the request processing
        */
 
       if (priv->ep0state == EP0STATE_DATA_IN)
@@ -2835,8 +2884,8 @@ static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno)
 
           stm32_epin_request(priv, privep);
 
-          /* If we are not actively processing an OUT request, then we
-           * need to setup to receive the next control request.
+          /* If we are not actively processing an OUT request, then we need to
+           * setup to receive the next control request.
            */
 
           if (!privep->active)
@@ -2854,8 +2903,8 @@ static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno)
         }
     }
 
-  /* For other endpoints, the only possibility is that we are continuing
-   * or finishing an IN request.
+  /* For other endpoints, the only possibility is that we are continuing or
+   * finishing an IN request.
    */
 
   else if (priv->devstate == DEVSTATE_CONFIGURED)
@@ -2874,13 +2923,14 @@ static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno)
  *
  ****************************************************************************/
 
-static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, int epno)
+static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv,
+                                          int epno)
 {
   FAR struct stm32_ep_s *privep = &priv->epin[epno];
 
-  /* Continue processing the write request queue.  This may mean sending
-   * more data from the existing request or terminating the current requests
-   * and (perhaps) starting the IN transfer from the next write request.
+  /* Continue processing the write request queue.  This may mean sending more
+   * data from the existing request or terminating the current requests and
+   * (perhaps) starting the IN transfer from the next write request.
    */
 
   stm32_epin_request(priv, privep);
@@ -2910,25 +2960,24 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv)
    * interrupt status register.
    */
 
-  daint  = stm32_getreg(STM32_OTG_DAINT);
+  daint = stm32_getreg(STM32_OTG_DAINT);
   daint &= stm32_getreg(STM32_OTG_DAINTMSK);
   daint &= OTG_DAINT_IEP_MASK;
 
   if (daint == 0)
     {
       /* We got an interrupt, but there is no unmasked endpoint that caused
-       * it ?!  When this happens, the interrupt flag never gets cleared and
+       * it?! When this happens, the interrupt flag never gets cleared and
        * we are stuck in infinite interrupt loop.
        *
        * This shouldn't happen if we are diligent about handling timing
        * issues when masking endpoint interrupts. However, this workaround
-       * avoids infinite loop and allows operation to continue normally.  It
-       * works by clearing each endpoint flags, masked or not.
+       * avoids infinite loop and allows operation to continue normally.
+       * It works by clearing each endpoint flags, masked or not.
        */
 
-      daint  = stm32_getreg(STM32_OTG_DAINT);
-      usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED),
-               (uint16_t)daint);
+      daint = stm32_getreg(STM32_OTG_DAINT);
+      usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), (uint16_t) daint);
 
       daint &= OTG_DAINT_IEP_MASK;
       epno = 0;
@@ -2938,8 +2987,8 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv)
           if ((daint & 1) != 0)
             {
               uerr("DIEPINT(%d) = %08x\n",
-                     epno, stm32_getreg(STM32_OTG_DIEPINT(epno)));
-              stm32_putreg(0xFF, STM32_OTG_DIEPINT(epno));
+                   epno, stm32_getreg(STM32_OTG_DIEPINT(epno)));
+              stm32_putreg(0xff, STM32_OTG_DIEPINT(epno));
             }
 
           epno++;
@@ -2966,10 +3015,10 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv)
           mask = stm32_getreg(STM32_OTG_DIEPMSK);
 
           /* Check if the TxFIFO not empty interrupt is enabled for this
-           * endpoint in the DIEPMSK register.  Bits n corresponds to
-           * endpoint n in the register. That condition corresponds to
-           * bit 7 of the DIEPINT interrupt status register.  There is
-           * no TXFE bit in the mask register, so we fake one here.
+           * endpoint in the DIEPMSK register.  Bits n corresponds to endpoint
+           * n in the register. That condition corresponds to bit 7 of the
+           * DIEPINT interrupt status register.  There is no TXFE bit in the
+           * mask register, so we fake one here.
            */
 
           empty = stm32_getreg(STM32_OTG_DIEPEMPMSK);
@@ -2990,12 +3039,12 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv)
           if ((diepint & OTG_DIEPINT_XFRC) != 0)
             {
               usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_XFRC),
-                       (uint16_t)diepint);
+                       (uint16_t) diepint);
 
-              /* It is possible that logic may be waiting for a the
-               * TxFIFO to become empty.  We disable the TxFIFO empty
-               * interrupt here; it will be re-enabled if there is still
-               * insufficient space in the TxFIFO.
+              /* It is possible that logic may be waiting for a the TxFIFO to
+               * become empty.  We disable the TxFIFO empty interrupt here; it
+               * will be re-enabled if there is still insufficient space in the
+               * TxFIFO.
                */
 
               empty &= ~OTG_DIEPEMPMSK(epno);
@@ -3011,20 +3060,22 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv)
 
           if ((diepint & OTG_DIEPINT_TOC) != 0)
             {
-              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), (uint16_t)diepint);
+              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC),
+                       (uint16_t) diepint);
               stm32_putreg(OTG_DIEPINT_TOC, STM32_OTG_DIEPINT(epno));
             }
 
-          /* IN token received when TxFIFO is empty.  Applies to non-periodic IN
-           * endpoints only.  This interrupt indicates that an IN token was received
-           * when the associated TxFIFO (periodic/non-periodic) was empty. This
-           * interrupt is asserted on the endpoint for which the IN token was
-           * received.
+          /* IN token received when TxFIFO is empty.  Applies to non-periodic
+           * IN endpoints only.  This interrupt indicates that an IN token was
+           * received when the associated TxFIFO (periodic/non-periodic) was
+           * empty. This interrupt is asserted on the endpoint for which the IN
+           * token was received.
            */
 
           if ((diepint & OTG_DIEPINT_ITTXFE) != 0)
             {
-              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), (uint16_t)diepint);
+              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE),
+                       (uint16_t) diepint);
               stm32_epin_request(priv, &priv->epin[epno]);
               stm32_putreg(OTG_DIEPINT_ITTXFE, STM32_OTG_DIEPINT(epno));
             }
@@ -3032,38 +3083,42 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv)
           /* IN endpoint NAK effective (ignored as this used only in polled
            * mode)
            */
-#if 0
+#  if 0
           if ((diepint & OTG_DIEPINT_INEPNE) != 0)
             {
-              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), (uint16_t)diepint);
+              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE),
+                       (uint16_t) diepint);
               stm32_putreg(OTG_DIEPINT_INEPNE, STM32_OTG_DIEPINT(epno));
             }
-#endif
+#  endif
           /* Endpoint disabled interrupt (ignored as this used only in polled
            * mode)
            */
-#if 0
+#  if 0
           if ((diepint & OTG_DIEPINT_EPDISD) != 0)
             {
-              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), (uint16_t)diepint);
+              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD),
+                       (uint16_t) diepint);
               stm32_putreg(OTG_DIEPINT_EPDISD, STM32_OTG_DIEPINT(epno));
             }
-#endif
+#  endif
           /* Transmit FIFO empty */
 
           if ((diepint & OTG_DIEPINT_TXFE) != 0)
             {
-              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), (uint16_t)diepint);
+              usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE),
+                       (uint16_t) diepint);
 
-              /* If we were waiting for TxFIFO to become empty, the we might have both
-               * XFRC and TXFE interrupts pending.  Since we do the same thing for both
-               * cases, ignore the TXFE if we have already processed the XFRC.
+              /* If we were waiting for TxFIFO to become empty, the we might
+               * have both XFRC and TXFE interrupts pending.  Since we do the
+               * same thing for both cases, ignore the TXFE if we have already
+               * processed the XFRC.
                */
 
               if ((diepint & OTG_DIEPINT_XFRC) == 0)
                 {
-                  /* Mask further FIFO empty interrupts.  This will be re-enabled
-                   * whenever we need to wait for a FIFO event.
+                  /* Mask further FIFO empty interrupts.  This will be
+                   * re-enabled whenever we need to wait for a FIFO event.
                    */
 
                   empty &= ~OTG_DIEPEMPMSK(epno);
@@ -3099,15 +3154,15 @@ static inline void stm32_resumeinterrupt(FAR struct stm32_usbdev_s *priv)
 
   /* Restart the PHY clock and un-gate USB core clock (HCLK) */
 
-#ifdef CONFIG_USBDEV_LOWPOWER
+#  ifdef CONFIG_USBDEV_LOWPOWER
   regval = stm32_getreg(STM32_OTG_PCGCCTL);
   regval &= ~(OTG_PCGCCTL_STPPCLK | OTG_PCGCCTL_GATEHCLK);
   stm32_putreg(regval, STM32_OTG_PCGCCTL);
-#endif
+#  endif
 
   /* Clear remote wake-up signaling */
 
-  regval  = stm32_getreg(STM32_OTG_DCTL);
+  regval = stm32_getreg(STM32_OTG_DCTL);
   regval &= ~OTG_DCTL_RWUSIG;
   stm32_putreg(regval, STM32_OTG_DCTL);
 
@@ -3133,9 +3188,9 @@ static inline void stm32_resumeinterrupt(FAR struct stm32_usbdev_s *priv)
 
 static inline void stm32_suspendinterrupt(FAR struct stm32_usbdev_s *priv)
 {
-#ifdef CONFIG_USBDEV_LOWPOWER
+#  ifdef CONFIG_USBDEV_LOWPOWER
   uint32_t regval;
-#endif
+#  endif
 
   /* Notify the class driver of the suspend event */
 
@@ -3144,9 +3199,9 @@ static inline void stm32_suspendinterrupt(FAR struct stm32_usbdev_s *priv)
       CLASS_SUSPEND(priv->driver, &priv->usbdev);
     }
 
-#ifdef CONFIG_USBDEV_LOWPOWER
-  /* OTG_DSTS_SUSPSTS is set as long as the suspend condition is detected
-   * on USB.  Check if we are still have the suspend condition, that we are
+#  ifdef CONFIG_USBDEV_LOWPOWER
+  /* OTG_DSTS_SUSPSTS is set as long as the suspend condition is detected on
+   * USB.  Check if we are still have the suspend condition, that we are
    * connected to the host, and that we have been configured.
    */
 
@@ -3154,26 +3209,24 @@ static inline void stm32_suspendinterrupt(FAR struct stm32_usbdev_s *priv)
 
   if ((regval & OTG_DSTS_SUSPSTS) != 0 && devstate == DEVSTATE_CONFIGURED)
     {
-      /* Switch off OTG clocking.  Setting OTG_PCGCCTL_STPPCLK stops the
-       * PHY clock.
+      /* Switch off OTG clocking.  Setting OTG_PCGCCTL_STPPCLK stops the PHY
+       * clock.
        */
 
       regval = stm32_getreg(STM32_OTG_PCGCCTL);
       regval |= OTG_PCGCCTL_STPPCLK;
       stm32_putreg(regval, STM32_OTG_PCGCCTL);
 
-      /* Setting OTG_PCGCCTL_GATEHCLK gate HCLK to modules other than
-       * the AHB Slave and Master and wakeup logic.
+      /* Setting OTG_PCGCCTL_GATEHCLK gate HCLK to modules other than the AHB
+       * Slave and Master and wakeup logic.
        */
 
       regval |= OTG_PCGCCTL_GATEHCLK;
       stm32_putreg(regval, STM32_OTG_PCGCCTL);
     }
-#endif
+#  endif
 
-  /* Let the board-specific logic know that we have entered the suspend
-   * state
-   */
+  /* Let the board-specific logic know that we have entered the suspend state */
 
   stm32_usbsuspend((FAR struct usbdev_s *)priv, false);
 }
@@ -3200,7 +3253,7 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
 
   /* Decode status fields */
 
-  epphy  = (regval & OTG_GRXSTSD_EPNUM_MASK) >> OTG_GRXSTSD_EPNUM_SHIFT;
+  epphy = (regval & OTG_GRXSTSD_EPNUM_MASK) >> OTG_GRXSTSD_EPNUM_SHIFT;
 
   if (epphy < STM32_NENDPOINTS)
     {
@@ -3210,12 +3263,12 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
 
       switch (regval & OTG_GRXSTSD_PKTSTS_MASK)
         {
-        /* Global OUT NAK.  This indicate that the global OUT NAK bit has taken
-         * effect.
-         *
-         * PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't
-         * Care.
-         */
+          /* Global OUT NAK.  This indicate that the global OUT NAK bit has
+           * taken effect.
+           *
+           * PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID =
+           * Don't Care.
+           */
 
         case OTG_GRXSTSD_PKTSTS_OUTNAK:
           {
@@ -3223,11 +3276,10 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
           }
           break;
 
-        /* OUT data packet received.
-         *
-         * PKTSTS = DataOUT, BCNT = size of the received data OUT packet,
-         * EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID.
-         */
+          /* OUT data packet received. PKTSTS = DataOUT, BCNT = size of the
+           * received data OUT packet, EPNUM = EPNUM on which the packet was
+           * received, DPID = Actual Data PID.
+           */
 
         case OTG_GRXSTSD_PKTSTS_OUTRECVD:
           {
@@ -3240,14 +3292,14 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
           }
           break;
 
-        /* OUT transfer completed.  This indicates that an OUT data transfer for
-         * the specified OUT endpoint has completed. After this entry is popped
-         * from the receive FIFO, the core asserts a Transfer Completed interrupt
-         * on the specified OUT endpoint.
-         *
-         * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on
-         * which the data transfer is complete, DPID = Don't Care.
-         */
+          /* OUT transfer completed.  This indicates that an OUT data transfer
+           * for the specified OUT endpoint has completed. After this entry is
+           * popped from the receive FIFO, the core asserts a Transfer
+           * Completed interrupt on the specified OUT endpoint.
+           *
+           * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on
+           * which the data transfer is complete, DPID = Don't Care.
+           */
 
         case OTG_GRXSTSD_PKTSTS_OUTDONE:
           {
@@ -3255,43 +3307,42 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
           }
           break;
 
-        /* SETUP transaction completed. This indicates that the Setup stage for
-         * the specified endpoint has completed and the Data stage has started.
-         * After this entry is popped from the receive FIFO, the core asserts a
-         * Setup interrupt on the specified control OUT endpoint (triggers an
-         * interrupt).
-         *
-         * PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num,
-         * DPID = Don't Care.
-         */
+          /* SETUP transaction completed. This indicates that the Setup stage
+           * for the specified endpoint has completed and the Data stage has
+           * started. After this entry is popped from the receive FIFO, the
+           * core asserts a Setup interrupt on the specified control OUT
+           * endpoint (triggers an interrupt).
+           *
+           * PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num,
+           * DPID = Don't Care.
+           */
 
         case OTG_GRXSTSD_PKTSTS_SETUPDONE:
           {
             usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy);
 
-            /* Now that the Setup Phase is complete if it was an OUT enable
-             * the endpoint
-             * (Doing this here prevents the loss of the first FIFO word)
+            /* Now that the Setup Phase is complete if it was an OUT enable the
+             * endpoint (Doing this here prevents the loss of the first FIFO
+             * word)
              */
 
             if (priv->ep0state == EP0STATE_SETUP_OUT)
               {
-
                 /* Clear NAKSTS so that we can receive the data */
 
-                regval  = stm32_getreg(STM32_OTG_DOEPCTL(0));
+                regval = stm32_getreg(STM32_OTG_DOEPCTL(0));
                 regval |= OTG_DOEPCTL0_CNAK;
                 stm32_putreg(regval, STM32_OTG_DOEPCTL(0));
-
-            }
+              }
           }
           break;
 
-        /* SETUP data packet received.  This indicates that a SETUP packet for the
-         * specified endpoint is now available for reading from the receive FIFO.
-         *
-         * PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0.
-         */
+          /* SETUP data packet received.  This indicates that a SETUP packet
+           * for the specified endpoint is now available for reading from the
+           * receive FIFO.
+           *
+           * PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0.
+           */
 
         case OTG_GRXSTSD_PKTSTS_SETUPRECVD:
           {
@@ -3299,18 +3350,19 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
 
             usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy);
 
-            /* Read EP0 setup data.  NOTE:  If multiple SETUP packets are received,
-             * the last one overwrites the previous setup packets and only that
-             * last SETUP packet will be processed.
+            /* Read EP0 setup data.  NOTE: If multiple SETUP packets are
+             * received, the last one overwrites the previous setup packets and
+             * only that last SETUP packet will be processed.
              */
 
-            stm32_rxfifo_read(&priv->epout[EP0], (FAR uint8_t *)&priv->ctrlreq,
-                             USB_SIZEOF_CTRLREQ);
+            stm32_rxfifo_read(&priv->epout[EP0],
+                              (FAR uint8_t *) & priv->ctrlreq,
+                              USB_SIZEOF_CTRLREQ);
 
             /* Was this an IN or an OUT SETUP packet.  If it is an OUT SETUP,
              * then we need to wait for the completion of the data phase to
-             * process the setup command.  If it is an IN SETUP packet, then
-             * we must processing the command BEFORE we enter the DATA phase.
+             * process the setup command.  If it is an IN SETUP packet, then we
+             * must processing the command BEFORE we enter the DATA phase.
              *
              * If the data associated with the OUT SETUP packet is zero length,
              * then, of course, we don't need to wait.
@@ -3335,12 +3387,12 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
         default:
           {
             usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS),
-                     (regval & OTG_GRXSTSD_PKTSTS_MASK) >> OTG_GRXSTSD_PKTSTS_SHIFT);
+                     (regval & OTG_GRXSTSD_PKTSTS_MASK) >>
+                     OTG_GRXSTSD_PKTSTS_SHIFT);
           }
           break;
         }
     }
-
 }
 
 /****************************************************************************
@@ -3359,11 +3411,17 @@ static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv)
 
   stm32_ep0in_activate();
 
-  /* Set USB turn-around time for the full speed device with internal PHY interface. */
+  /* Set USB turn-around time for the full speed device with internal PHY
+   * interface.
+   */
 
-  regval  = stm32_getreg(STM32_OTG_GUSBCFG);
+  regval = stm32_getreg(STM32_OTG_GUSBCFG);
   regval &= ~OTG_GUSBCFG_TRDT_MASK;
-  regval |=  OTG_GUSBCFG_TRDT(6);
+#  ifdef CONFIG_STM32F7_OTGFSHS
+  regval |= OTG_GUSBCFG_TRDT(9);
+#  else
+  regval |= OTG_GUSBCFG_TRDT(6);
+#  endif
   stm32_putreg(regval, STM32_OTG_GUSBCFG);
 }
 
@@ -3377,13 +3435,14 @@ static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_USBDEV_ISOCHRONOUS
+#  ifdef CONFIG_USBDEV_ISOCHRONOUS
 static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv)
 {
   int i;
 
-  /* The application must read the endpoint control register for all isochronous
-   * IN endpoints to detect endpoints with incomplete IN data transfers.
+  /* The application must read the endpoint control register for all
+   * isochronous IN endpoints to detect endpoints with incomplete IN data
+   * transfers.
    */
 
   for (i = 0; i < STM32_NENDPOINTS; i++)
@@ -3411,10 +3470,10 @@ static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv)
 
       regaddr = STM32_OTG_DIEPCTL(privep->epphy);
       doepctl = stm32_getreg(regaddr);
-      dsts    = stm32_getreg(STM32_OTG_DSTS);
+      dsts = stm32_getreg(STM32_OTG_DSTS);
 
-      /* EONUM = 0:even frame, 1:odd frame
-       * SOFFN = Frame number of the received SOF
+      /* EONUM = 0:even frame, 1:odd frame SOFFN = Frame number of the received
+       * SOF
        */
 
       eonum = ((doepctl & OTG_DIEPCTL_EONUM) != 0);
@@ -3427,18 +3486,18 @@ static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv)
           continue;
         }
 
-      /* For isochronous IN endpoints with incomplete transfers,
-       * the application must discard the data in the memory and
-       * disable the endpoint.
+      /* For isochronous IN endpoints with incomplete transfers, the
+       * application must discard the data in the memory and disable the
+       * endpoint.
        */
 
       stm32_req_complete(privep, -EIO);
-#warning "Will clear OTG_DIEPCTL_USBAEP too"
+#    warning "Will clear OTG_DIEPCTL_USBAEP too"
       stm32_epin_disable(privep);
       break;
     }
 }
-#endif
+#  endif
 
 /****************************************************************************
  * Name: stm32_isocoutinterrupt
@@ -3448,7 +3507,7 @@ static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_USBDEV_ISOCHRONOUS
+#  ifdef CONFIG_USBDEV_ISOCHRONOUS
 static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv)
 {
   FAR struct stm32_ep_s *privep;
@@ -3462,10 +3521,11 @@ static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv)
   /* When it receives an IISOOXFR interrupt, the application must read the
    * control registers of all isochronous OUT endpoints to determine which
    * endpoints had an incomplete transfer in the current microframe. An
-   * endpoint transfer is incomplete if both the following conditions are true:
+   * endpoint transfer is incomplete if both the following conditions are
+   * true:
    *
-   *   DOEPCTLx:EONUM = DSTS:SOFFN[0], and
-   *   DOEPCTLx:EPENA = 1
+   * DOEPCTLx:EONUM = DSTS:SOFFN[0], and
+   * DOEPCTLx:EPENA = 1
    */
 
   for (i = 0; i < STM32_NENDPOINTS; i++)
@@ -3493,7 +3553,7 @@ static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv)
 
       regaddr = STM32_OTG_DOEPCTL(privep->epphy);
       doepctl = stm32_getreg(regaddr);
-      dsts    = stm32_getreg(STM32_OTG_DSTS);
+      dsts = stm32_getreg(STM32_OTG_DSTS);
 
       /* EONUM = 0:even frame, 1:odd frame
        * SOFFN = Frame number of the received SOF
@@ -3509,18 +3569,18 @@ static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv)
           continue;
         }
 
-      /* For isochronous OUT endpoints with incomplete transfers,
-       * the application must discard the data in the memory and
-       * disable the endpoint.
+      /* For isochronous OUT endpoints with incomplete transfers, the
+       * application must discard the data in the memory and disable the
+       * endpoint.
        */
 
       stm32_req_complete(privep, -EIO);
-#warning "Will clear OTG_DOEPCTL_USBAEP too"
+#    warning "Will clear OTG_DOEPCTL_USBAEP too"
       stm32_epout_disable(privep);
       break;
     }
 }
-#endif
+#  endif
 
 /****************************************************************************
  * Name: stm32_sessioninterrupt
@@ -3530,12 +3590,12 @@ static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_USBDEV_VBUSSENSING
+#  ifdef CONFIG_USBDEV_VBUSSENSING
 static inline void stm32_sessioninterrupt(FAR struct stm32_usbdev_s *priv)
 {
-#warning "Missing logic"
+#    warning "Missing logic"
 }
-#endif
+#  endif
 
 /****************************************************************************
  * Name: stm32_otginterrupt
@@ -3545,7 +3605,7 @@ static inline void stm32_sessioninterrupt(FAR struct stm32_usbdev_s *priv)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_USBDEV_VBUSSENSING
+#  ifdef CONFIG_USBDEV_VBUSSENSING
 static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv)
 {
   uint32_t regval;
@@ -3555,14 +3615,14 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv)
   regval = stm32_getreg(STM32_OTG_GOTGINT);
   if ((regval & OTG_GOTGINT_SEDET) != 0)
     {
-#warning "Missing logic"
+#    warning "Missing logic"
     }
 
   /* Clear OTG interrupt */
 
   stm32_putreg(regval, STM32_OTG_GOTGINT);
 }
-#endif
+#  endif
 
 /****************************************************************************
  * Name: stm32_usbinterrupt
@@ -3574,7 +3634,7 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv)
 
 static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg)
 {
-  /* At present, there is only a single OTG  device support. Hence it is
+  /* At present, there is only a single OTG device support. Hence it is
    * pre-allocated as g_otghsdev.  However, in most code, the private data
    * structure will be referenced using the 'priv' pointer (rather than the
    * global data) in order to simplify any future support for multiple devices.
@@ -3588,36 +3648,36 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg)
 
   /* Assure that we are in device mode */
 
-  DEBUGASSERT((stm32_getreg(STM32_OTG_GINTSTS) & OTG_GINTSTS_CMOD) == OTG_GINTSTS_DEVMODE);
+  DEBUGASSERT((stm32_getreg(STM32_OTG_GINTSTS) & OTG_GINTSTS_CMOD) ==
+              OTG_GINTSTS_DEVMODE);
 
-  /* Get the state of all enabled interrupts.  We will do this repeatedly
-   * some interrupts (like RXFLVL) will generate additional interrupting
-   * events.
+  /* Get the state of all enabled interrupts.  We will do this repeatedly some
+   * interrupts (like RXFLVL) will generate additional interrupting events.
    */
 
   for (; ; )
     {
       /* Get the set of pending, un-masked interrupts */
 
-      regval  = stm32_getreg(STM32_OTG_GINTSTS);
+      regval = stm32_getreg(STM32_OTG_GINTSTS);
       reserved = (regval & OTG_GINT_RESERVED);
       regval &= stm32_getreg(STM32_OTG_GINTMSK);
 
-      /* With out modifying the reserved bits, acknowledge all
-       * **Writable** pending irqs we will service below
+      /* With out modifying the reserved bits, acknowledge all **Writable**
+       * pending irqs we will service below.
        */
 
       stm32_putreg(((regval | reserved) & OTG_GINT_RC_W1), STM32_OTG_GINTSTS);
 
-      /* Break out of the loop when there are no further pending (and
-       * unmasked) interrupts to be processes.
+      /* Break out of the loop when there are no further pending (and unmasked)
+       * interrupts to be processes.
        */
 
       if (regval == 0)
         {
           break;
         }
-      usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), (uint16_t)regval);
+      usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), (uint16_t) regval);
 
       /* OUT endpoint interrupt. The core sets this bit to indicate that an
        * interrupt is pending on one of the OUT endpoints of the core.
@@ -3625,34 +3685,35 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg)
 
       if ((regval & OTG_GINT_OEP) != 0)
         {
-          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t)regval);
+          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t) regval);
           stm32_epout_interrupt(priv);
         }
 
-      /* IN endpoint interrupt.  The core sets this bit to indicate that
-       * an interrupt is pending on one of the IN endpoints of the core.
+      /* IN endpoint interrupt.  The core sets this bit to indicate that an
+       * interrupt is pending on one of the IN endpoints of the core.
        */
 
       if ((regval & OTG_GINT_IEP) != 0)
         {
-          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval);
+          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t) regval);
           stm32_epin_interrupt(priv);
         }
 
       /* Host/device mode mismatch error interrupt */
 
-#ifdef CONFIG_DEBUG_USB
+#  ifdef CONFIG_DEBUG_USB
       if ((regval & OTG_GINT_MMIS) != 0)
         {
-          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), (uint16_t)regval);
+          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH),
+                   (uint16_t) regval);
         }
-#endif
+#  endif
 
       /* Resume/remote wakeup detected interrupt */
 
       if ((regval & OTG_GINT_WKUP) != 0)
         {
-          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t)regval);
+          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t) regval);
           stm32_resumeinterrupt(priv);
         }
 
@@ -3660,18 +3721,19 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg)
 
       if ((regval & OTG_GINT_USBSUSP) != 0)
         {
-          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), (uint16_t)regval);
+          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND),
+                   (uint16_t) regval);
           stm32_suspendinterrupt(priv);
         }
 
       /* Start of frame interrupt */
 
-#ifdef CONFIG_USBDEV_SOFINTERRUPT
+#  ifdef CONFIG_USBDEV_SOFINTERRUPT
       if ((regval & OTG_GINT_SOF) != 0)
         {
-          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval);
+          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t) regval);
         }
-#endif
+#  endif
 
       /* RxFIFO non-empty interrupt.  Indicates that there is at least one
        * packet pending to be read from the RxFIFO.
@@ -3679,7 +3741,7 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg)
 
       if ((regval & OTG_GINT_RXFLVL) != 0)
         {
-          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t)regval);
+          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t) regval);
           stm32_rxinterrupt(priv);
         }
 
@@ -3687,7 +3749,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg)
 
       if ((regval & (OTG_GINT_USBRST | OTG_GINT_RSTDET)) != 0)
         {
-          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), (uint16_t)regval);
+          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET),
+                   (uint16_t) regval);
 
           /* Perform the device reset */
 
@@ -3700,46 +3763,48 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg)
 
       if ((regval & OTG_GINT_ENUMDNE) != 0)
         {
-          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), (uint16_t)regval);
+          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE),
+                   (uint16_t) regval);
           stm32_enuminterrupt(priv);
         }
 
       /* Incomplete isochronous IN transfer interrupt.  When the core finds
-       * non-empty any of the isochronous IN endpoint FIFOs scheduled for
-       * the current frame non-empty, the core generates an IISOIXFR
-       * interrupt.
+       * non-empty any of the isochronous IN endpoint FIFOs scheduled for the
+       * current frame non-empty, the core generates an IISOIXFR interrupt.
        */
 
-#ifdef CONFIG_USBDEV_ISOCHRONOUS
+#  ifdef CONFIG_USBDEV_ISOCHRONOUS
       if ((regval & OTG_GINT_IISOIXFR) != 0)
         {
-          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), (uint16_t)regval);
+          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR),
+                   (uint16_t) regval);
           stm32_isocininterrupt(priv);
         }
 
-      /* Incomplete isochronous OUT transfer.  For isochronous OUT
-       * endpoints, the XFRC interrupt may not always be asserted. If the
-       * core drops isochronous OUT data packets, the application could fail
-       * to detect the XFRC interrupt.  The incomplete Isochronous OUT data
-       * interrupt indicates that an XFRC interrupt was not asserted on at
-       * least one of the isochronous OUT endpoints. At this point, the
-       * endpoint with the incomplete transfer remains enabled, but no active
-       * transfers remain in progress on this endpoint on the USB.
+      /* Incomplete isochronous OUT transfer.  For isochronous OUT endpoints,
+       * the XFRC interrupt may not always be asserted. If the core drops
+       * isochronous OUT data packets, the application could fail to detect the
+       * XFRC interrupt.  The incomplete Isochronous OUT data interrupt
+       * indicates that an XFRC interrupt was not asserted on at least one of
+       * the isochronous OUT endpoints. At this point, the endpoint with the
+       * incomplete transfer remains enabled, but no active transfers remain in
+       * progress on this endpoint on the USB.
        */
 
       if ((regval & OTG_GINT_IISOOXFR) != 0)
         {
-          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), (uint16_t)regval);
+          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR),
+                   (uint16_t) regval);
           stm32_isocoutinterrupt(priv);
         }
-#endif
+#  endif
 
       /* Session request/new session detected interrupt */
 
-#ifdef CONFIG_USBDEV_VBUSSENSING
+#  ifdef CONFIG_USBDEV_VBUSSENSING
       if ((regval & OTG_GINT_SRQ) != 0)
         {
-          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval);
+          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t) regval);
           stm32_sessioninterrupt(priv);
         }
 
@@ -3747,10 +3812,10 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg)
 
       if ((regval & OTG_GINT_OTG) != 0)
         {
-          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval);
+          usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t) regval);
           stm32_otginterrupt(priv);
         }
-#endif
+#  endif
     }
 
   usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0);
@@ -3775,9 +3840,9 @@ static void stm32_enablegonak(FAR struct stm32_ep_s *privep)
 
   /* First, make sure that there is no GNOAKEFF interrupt pending. */
 
-#if 0
+#  if 0
   stm32_putreg(OTG_GINT_GONAKEFF, STM32_OTG_GINTSTS);
-#endif
+#  endif
 
   /* Enable Global OUT NAK mode in the core. */
 
@@ -3785,16 +3850,16 @@ static void stm32_enablegonak(FAR struct stm32_ep_s *privep)
   regval |= OTG_DCTL_SGONAK;
   stm32_putreg(regval, STM32_OTG_DCTL);
 
-#if 0
-  /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK
-   * mode is in effect.  When the interrupt handler pops the OUTNAK word
-   * from the RxFIFO, the core sets the GONAKEFF interrupt.
+#  if 0
+  /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK mode is in
+   * effect.  When the interrupt handler pops the OUTNAK word from the RxFIFO,
+   * the core sets the GONAKEFF interrupt.
    */
 
   while ((stm32_getreg(STM32_OTG_GINTSTS) & OTG_GINT_GONAKEFF) == 0);
   stm32_putreg(OTG_GINT_GONAKEFF, STM32_OTG_GINTSTS);
 
-#else
+#  else
   /* Since we are in the interrupt handler, we cannot wait inline for the
    * GONAKEFF because it cannot occur until service the RXFLVL global interrupt
    * and pop the OUTNAK word from the RxFIFO.
@@ -3804,7 +3869,7 @@ static void stm32_enablegonak(FAR struct stm32_ep_s *privep)
    */
 
   while ((stm32_getreg(STM32_OTG_DCTL) & OTG_DCTL_GONSTS) == 0);
-#endif
+#  endif
 }
 
 /****************************************************************************
@@ -3821,7 +3886,7 @@ static void stm32_disablegonak(FAR struct stm32_ep_s *privep)
 
   /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */
 
-  regval  = stm32_getreg(STM32_OTG_DCTL);
+  regval = stm32_getreg(STM32_OTG_DCTL);
   regval |= OTG_DCTL_CGONAK;
   stm32_putreg(regval, STM32_OTG_DCTL);
 }
@@ -3858,25 +3923,25 @@ static int stm32_epout_configure(FAR struct stm32_ep_s *privep,
 
       switch (maxpacket)
         {
-          case 8:
-            mpsiz = OTG_DOEPCTL0_MPSIZ_8;
-            break;
+        case 8:
+          mpsiz = OTG_DOEPCTL0_MPSIZ_8;
+          break;
 
-          case 16:
-            mpsiz = OTG_DOEPCTL0_MPSIZ_16;
-            break;
+        case 16:
+          mpsiz = OTG_DOEPCTL0_MPSIZ_16;
+          break;
 
-          case 32:
-            mpsiz = OTG_DOEPCTL0_MPSIZ_32;
-            break;
+        case 32:
+          mpsiz = OTG_DOEPCTL0_MPSIZ_32;
+          break;
 
-          case 64:
-            mpsiz = OTG_DOEPCTL0_MPSIZ_64;
-            break;
+        case 64:
+          mpsiz = OTG_DOEPCTL0_MPSIZ_64;
+          break;
 
-          default:
-            uerr("Unsupported maxpacket: %d\n", maxpacket);
-            return -EINVAL;
+        default:
+          uerr("Unsupported maxpacket: %d\n", maxpacket);
+          return -EINVAL;
         }
     }
 
@@ -3892,7 +3957,7 @@ static int stm32_epout_configure(FAR struct stm32_ep_s *privep,
    */
 
   regaddr = STM32_OTG_DOEPCTL(privep->epphy);
-  regval  = stm32_getreg(regaddr);
+  regval = stm32_getreg(regaddr);
   if ((regval & OTG_DOEPCTL_USBAEP) == 0)
     {
       if (regval & OTG_DOEPCTL_NAKSTS)
@@ -3909,8 +3974,8 @@ static int stm32_epout_configure(FAR struct stm32_ep_s *privep,
       /* Save the endpoint configuration */
 
       privep->ep.maxpacket = maxpacket;
-      privep->eptype       = eptype;
-      privep->stalled      = false;
+      privep->eptype = eptype;
+      privep->stalled = false;
     }
 
   /* Enable the interrupt for this endpoint */
@@ -3953,25 +4018,25 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep,
 
       switch (maxpacket)
         {
-          case 8:
-            mpsiz = OTG_DIEPCTL0_MPSIZ_8;
-            break;
+        case 8:
+          mpsiz = OTG_DIEPCTL0_MPSIZ_8;
+          break;
 
-          case 16:
-            mpsiz = OTG_DIEPCTL0_MPSIZ_16;
-            break;
+        case 16:
+          mpsiz = OTG_DIEPCTL0_MPSIZ_16;
+          break;
 
-          case 32:
-            mpsiz = OTG_DIEPCTL0_MPSIZ_32;
-            break;
+        case 32:
+          mpsiz = OTG_DIEPCTL0_MPSIZ_32;
+          break;
 
-          case 64:
-            mpsiz = OTG_DIEPCTL0_MPSIZ_64;
-            break;
+        case 64:
+          mpsiz = OTG_DIEPCTL0_MPSIZ_64;
+          break;
 
-          default:
-            uerr("Unsupported maxpacket: %d\n", maxpacket);
-            return -EINVAL;
+        default:
+          uerr("Unsupported maxpacket: %d\n", maxpacket);
+          return -EINVAL;
         }
     }
 
@@ -3982,13 +4047,12 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep,
       mpsiz = (maxpacket << OTG_DIEPCTL_MPSIZ_SHIFT);
     }
 
-
   /* If the endpoint is already active don't change the endpoint control
    * register.
    */
 
   regaddr = STM32_OTG_DIEPCTL(privep->epphy);
-  regval  = stm32_getreg(regaddr);
+  regval = stm32_getreg(regaddr);
   if ((regval & OTG_DIEPCTL_USBAEP) == 0)
     {
       if (regval & OTG_DIEPCTL_NAKSTS)
@@ -4007,8 +4071,8 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep,
       /* Save the endpoint configuration */
 
       privep->ep.maxpacket = maxpacket;
-      privep->eptype       = eptype;
-      privep->stalled      = false;
+      privep->eptype = eptype;
+      privep->stalled = false;
     }
 
   /* Enable the interrupt for this endpoint */
@@ -4036,12 +4100,11 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep,
  ****************************************************************************/
 
 static int stm32_ep_configure(FAR struct usbdev_ep_s *ep,
-                              FAR const struct usb_epdesc_s *desc,
-                              bool last)
+                              FAR const struct usb_epdesc_s *desc, bool last)
 {
   FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep;
   uint16_t maxpacket;
-  uint8_t  eptype;
+  uint8_t eptype;
   int ret;
 
   usbtrace(TRACE_EPCONFIGURE, privep->epphy);
@@ -4050,7 +4113,7 @@ static int stm32_ep_configure(FAR struct usbdev_ep_s *ep,
   /* Initialize EP capabilities */
 
   maxpacket = GETUINT16(desc->mxpacketsize);
-  eptype    = desc->attr & USB_EP_ATTR_XFERTYPE_MASK;
+  eptype = desc->attr & USB_EP_ATTR_XFERTYPE_MASK;
 
   /* Setup Endpoint Control Register */
 
@@ -4102,48 +4165,49 @@ static void stm32_epout_disable(FAR struct stm32_ep_s *privep)
 
   /* Is this an IN or an OUT endpoint */
 
-  /* Before disabling any OUT endpoint, the application must enable
-   * Global OUT NAK mode in the core.
+  /* Before disabling any OUT endpoint, the application must enable Global OUT
+   * NAK mode in the core.
    */
 
   flags = enter_critical_section();
   stm32_enablegonak(privep);
 
-  /* Disable the required OUT endpoint by setting the EPDIS and SNAK bits
-   * int DOECPTL register.
+  /* Disable the required OUT endpoint by setting the EPDIS and SNAK bits int
+   * DOECPTL register.
    */
 
   regaddr = STM32_OTG_DOEPCTL(privep->epphy);
-  regval  = stm32_getreg(regaddr);
+  regval = stm32_getreg(regaddr);
   regval &= ~OTG_DOEPCTL_USBAEP;
   regval |= (OTG_DOEPCTL_EPDIS | OTG_DOEPCTL_SNAK);
   stm32_putreg(regval, regaddr);
 
-  /* Wait for the EPDISD interrupt which indicates that the OUT
-   * endpoint is completely disabled.
+  /* Wait for the EPDISD interrupt which indicates that the OUT endpoint is
+   * completely disabled.
    */
 
-#if 0 /* Doesn't happen */
+#  if 0    /* Doesn't happen */
   regaddr = STM32_OTG_DOEPINT(privep->epphy);
   while ((stm32_getreg(regaddr) & OTG_DOEPINT_EPDISD) == 0);
-#else
+#  else
   /* REVISIT: */
+
   up_udelay(10);
-#endif
+#  endif
 
   /* Clear the EPDISD interrupt indication */
 
   stm32_putreg(OTG_DOEPINT_EPDISD, STM32_OTG_DOEPINT(privep->epphy));
 
-  /* Then disable the Global OUT NAK mode to continue receiving data
-   * from other non-disabled OUT endpoints.
+  /* Then disable the Global OUT NAK mode to continue receiving data from other
+   * non-disabled OUT endpoints.
    */
 
   stm32_disablegonak(privep);
 
   /* Disable endpoint interrupts */
 
-  regval  = stm32_getreg(STM32_OTG_DAINTMSK);
+  regval = stm32_getreg(STM32_OTG_DAINTMSK);
   regval &= ~OTG_DAINT_OEP(privep->epphy);
   stm32_putreg(regval, STM32_OTG_DAINTMSK);
 
@@ -4170,24 +4234,24 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep)
 
   usbtrace(TRACE_EPDISABLE, privep->epphy);
 
-  /* After USB reset, the endpoint will already be deactivated by the
-   * hardware. Trying to disable again will just hang in the wait.
+  /* After USB reset, the endpoint will already be deactivated by the hardware.
+   * Trying to disable again will just hang in the wait.
    */
 
   regaddr = STM32_OTG_DIEPCTL(privep->epphy);
-  regval  = stm32_getreg(regaddr);
+  regval = stm32_getreg(regaddr);
   if ((regval & OTG_DIEPCTL_USBAEP) == 0)
     {
       return;
     }
 
-  /* This INEPNE wait logic is suggested by reference manual, but seems
-   * to get stuck to infinite loop.
+  /* This INEPNE wait logic is suggested by reference manual, but seems to get
+   * stuck to infinite loop.
    */
 
-#if 0
-  /* Make sure that there is no pending IPEPNE interrupt (because we are
-   * to poll this bit below).
+#  if 0
+  /* Make sure that there is no pending IPEPNE interrupt (because we are to
+   * poll this bit below).
    */
 
   stm32_putreg(OTG_DIEPINT_INEPNE, STM32_OTG_DIEPINT(privep->epphy));
@@ -4195,7 +4259,7 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep)
   /* Set the endpoint in NAK mode */
 
   regaddr = STM32_OTG_DIEPCTL(privep->epphy);
-  regval  = stm32_getreg(regaddr);
+  regval = stm32_getreg(regaddr);
   regval &= ~OTG_DIEPCTL_USBAEP;
   regval |= (OTG_DIEPCTL_EPDIS | OTG_DIEPCTL_SNAK);
   stm32_putreg(regval, regaddr);
@@ -4208,21 +4272,21 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep)
   /* Clear the INEPNE interrupt indication */
 
   stm32_putreg(OTG_DIEPINT_INEPNE, regaddr);
-#endif
+#  endif
 
-  /* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits
-   * the DIEPCTLx register.
+  /* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits the
+   * DIEPCTLx register.
    */
 
   flags = enter_critical_section();
   regaddr = STM32_OTG_DIEPCTL(privep->epphy);
-  regval  = stm32_getreg(regaddr);
+  regval = stm32_getreg(regaddr);
   regval &= ~OTG_DIEPCTL_USBAEP;
   regval |= (OTG_DIEPCTL_EPDIS | OTG_DIEPCTL_SNAK);
   stm32_putreg(regval, regaddr);
 
-  /* Wait for the EPDISD interrupt which indicates that the IN
-   * endpoint is completely disabled.
+  /* Wait for the EPDISD interrupt which indicates that the IN endpoint is
+   * completely disabled.
    */
 
   regaddr = STM32_OTG_DIEPINT(privep->epphy);
@@ -4240,7 +4304,7 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep)
 
   /* Disable endpoint interrupts */
 
-  regval  = stm32_getreg(STM32_OTG_DAINTMSK);
+  regval = stm32_getreg(STM32_OTG_DAINTMSK);
   regval &= ~OTG_DAINT_IEP(privep->epphy);
   stm32_putreg(regval, STM32_OTG_DAINTMSK);
 
@@ -4262,13 +4326,13 @@ static int stm32_ep_disable(FAR struct usbdev_ep_s *ep)
 {
   FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep;
 
-#ifdef CONFIG_DEBUG_FEATURES
+#  ifdef CONFIG_DEBUG_FEATURES
   if (!ep)
     {
       usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
       return -EINVAL;
     }
-#endif
+#  endif
 
   usbtrace(TRACE_EPDISABLE, privep->epphy);
 
@@ -4302,13 +4366,13 @@ static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep)
 {
   FAR struct stm32_req_s *privreq;
 
-#ifdef CONFIG_DEBUG_FEATURES
+#  ifdef CONFIG_DEBUG_FEATURES
   if (!ep)
     {
       usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
       return NULL;
     }
-#endif
+#  endif
 
   usbtrace(TRACE_EPALLOCREQ, ((FAR struct stm32_ep_s *)ep)->epphy);
 
@@ -4331,17 +4395,18 @@ static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep)
  *
  ****************************************************************************/
 
-static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req)
+static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep,
+                             FAR struct usbdev_req_s *req)
 {
   FAR struct stm32_req_s *privreq = (FAR struct stm32_req_s *)req;
 
-#ifdef CONFIG_DEBUG_FEATURES
+#  ifdef CONFIG_DEBUG_FEATURES
   if (!ep || !req)
     {
       usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
       return;
     }
-#endif
+#  endif
 
   usbtrace(TRACE_EPFREEREQ, ((FAR struct stm32_ep_s *)ep)->epphy);
   kmm_free(privreq);
@@ -4355,18 +4420,18 @@ static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s
  *
  ****************************************************************************/
 
-#ifdef CONFIG_USBDEV_DMA
+#  ifdef CONFIG_USBDEV_DMA
 static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, uint16_t bytes)
 {
   usbtrace(TRACE_EPALLOCBUFFER, ((FAR struct stm32_ep_s *)ep)->epphy);
 
-#ifdef CONFIG_USBDEV_DMAMEMORY
+#    ifdef CONFIG_USBDEV_DMAMEMORY
   return usbdev_dma_alloc(bytes);
-#else
+#    else
   return kmm_malloc(bytes);
-#endif
+#    endif
 }
-#endif
+#  endif
 
 /****************************************************************************
  * Name: stm32_ep_freebuffer
@@ -4376,18 +4441,18 @@ static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, uint16_t bytes)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_USBDEV_DMA
+#  ifdef CONFIG_USBDEV_DMA
 static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf)
 {
   usbtrace(TRACE_EPALLOCBUFFER, ((FAR struct stm32_ep_s *)ep)->epphy);
 
-#ifdef CONFIG_USBDEV_DMAMEMORY
+#    ifdef CONFIG_USBDEV_DMAMEMORY
   usbdev_dma_free(buf);
-#else
+#    else
   kmm_free(buf);
-#endif
+#    endif
 }
-#endif
+#  endif
 
 /****************************************************************************
  * Name: stm32_ep_submit
@@ -4397,7 +4462,8 @@ static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf)
  *
  ****************************************************************************/
 
-static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req)
+static int stm32_ep_submit(FAR struct usbdev_ep_s *ep,
+                           FAR struct usbdev_req_s *req)
 {
   FAR struct stm32_req_s *privreq = (FAR struct stm32_req_s *)req;
   FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep;
@@ -4407,30 +4473,32 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
 
   /* Some sanity checking */
 
-#ifdef CONFIG_DEBUG_FEATURES
+#  ifdef CONFIG_DEBUG_FEATURES
   if (!req || !req->callback || !req->buf || !ep)
     {
       usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
-      uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep);
+      uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf,
+            ep);
       return -EINVAL;
     }
-#endif
+#  endif
 
   usbtrace(TRACE_EPSUBMIT, privep->epphy);
   priv = privep->dev;
 
-#ifdef CONFIG_DEBUG_FEATURES
+#  ifdef CONFIG_DEBUG_FEATURES
   if (!priv->driver)
     {
-      usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed);
+      usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED),
+               priv->usbdev.speed);
       return -ESHUTDOWN;
     }
-#endif
+#  endif
 
   /* Handle the request from the class driver */
 
   req->result = -EINPROGRESS;
-  req->xfrd   = 0;
+  req->xfrd = 0;
 
   /* Disable Interrupts */
 
@@ -4448,16 +4516,16 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
 
       if (stm32_req_addlast(privep, privreq) && !privep->active)
         {
-          /* If a request was added to an IN endpoint, then attempt to send
-           * the request data buffer now.
+          /* If a request was added to an IN endpoint, then attempt to send the
+           * request data buffer now.
            */
 
           if (privep->isin)
             {
               usbtrace(TRACE_INREQQUEUED(privep->epphy), privreq->req.len);
 
-              /* If the endpoint is not busy with another write request,
-               * then process the newly received write request now.
+              /* If the endpoint is not busy with another write request, then
+               * process the newly received write request now.
                */
 
               if (!privep->active)
@@ -4466,9 +4534,9 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
                 }
             }
 
-          /* If the request was added to an OUT endpoint, then attempt to
-           * setup a read into the request data buffer now (this will, of
-           * course, fail if there is already a read in place).
+          /* If the request was added to an OUT endpoint, then attempt to setup
+           * a read into the request data buffer now (this will, of course,
+           * fail if there is already a read in place).
            */
 
           else
@@ -4491,27 +4559,27 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
  *
  ****************************************************************************/
 
-static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req)
+static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep,
+                           FAR struct usbdev_req_s *req)
 {
   FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep;
   irqstate_t flags;
 
-#ifdef CONFIG_DEBUG_FEATURES
+#  ifdef CONFIG_DEBUG_FEATURES
   if (!ep || !req)
     {
       usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
       return -EINVAL;
     }
-#endif
+#  endif
 
   usbtrace(TRACE_EPCANCEL, privep->epphy);
 
   flags = enter_critical_section();
 
-  /* FIXME: if the request is the first, then we need to flush the EP
-   *         otherwise just remove it from the list
-   *
-   *  but ... all other implementations cancel all requests ...
+  /* FIXME: if the request is the first, then we need to flush the EP otherwise
+   * just remove it from the list but ... all other implementations cancel all
+   * requests ...
    */
 
   stm32_req_cancel(privep, -ESHUTDOWN);
@@ -4529,7 +4597,7 @@ static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *
 
 static int stm32_epout_setstall(FAR struct stm32_ep_s *privep)
 {
-#if 1
+#  if 1
   /* This implementation follows the requirements from the STM32 F4 reference
    * manual.
    */
@@ -4541,26 +4609,27 @@ static int stm32_epout_setstall(FAR struct stm32_ep_s *privep)
 
   stm32_enablegonak(privep);
 
-  /* Disable and STALL the OUT endpoint by setting the EPDIS and STALL bits
-   * in the DOECPTL register.
+  /* Disable and STALL the OUT endpoint by setting the EPDIS and STALL bits in
+   * the DOECPTL register.
    */
 
   regaddr = STM32_OTG_DOEPCTL(privep->epphy);
-  regval  = stm32_getreg(regaddr);
+  regval = stm32_getreg(regaddr);
   regval |= (OTG_DOEPCTL_EPDIS | OTG_DOEPCTL_STALL);
   stm32_putreg(regval, regaddr);
 
-  /* Wait for the EPDISD interrupt which indicates that the OUT
-   * endpoint is completely disabled.
+  /* Wait for the EPDISD interrupt which indicates that the OUT endpoint is
+   * completely disabled.
    */
 
-#if 0 /* Doesn't happen */
+#    if 0    /* Doesn't happen */
   regaddr = STM32_OTG_DOEPINT(privep->epphy);
   while ((stm32_getreg(regaddr) & OTG_DOEPINT_EPDISD) == 0);
-#else
+#    else
   /* REVISIT: */
+
   up_udelay(10);
-#endif
+#    endif
 
   /* Disable Global OUT NAK mode */
 
@@ -4570,7 +4639,7 @@ static int stm32_epout_setstall(FAR struct stm32_ep_s *privep)
 
   privep->stalled = true;
   return OK;
-#else
+#  else
   /* This implementation follows the STMicro code example. */
   /* REVISIT: */
 
@@ -4580,7 +4649,7 @@ static int stm32_epout_setstall(FAR struct stm32_ep_s *privep)
   /* Stall the OUT endpoint by setting the STALL bit in the DOECPTL register. */
 
   regaddr = STM32_OTG_DOEPCTL(privep->epphy);
-  regval  = stm32_getreg(regaddr);
+  regval = stm32_getreg(regaddr);
   regval |= OTG_DOEPCTL_STALL;
   stm32_putreg(regval, regaddr);
 
@@ -4588,7 +4657,7 @@ static int stm32_epout_setstall(FAR struct stm32_ep_s *privep)
 
   privep->stalled = true;
   return OK;
-#endif
+#  endif
 }
 
 /****************************************************************************
@@ -4607,7 +4676,7 @@ static int stm32_epin_setstall(FAR struct stm32_ep_s *privep)
   /* Get the IN endpoint device control register */
 
   regaddr = STM32_OTG_DIEPCTL(privep->epphy);
-  regval  = stm32_getreg(regaddr);
+  regval = stm32_getreg(regaddr);
 
   /* Then stall the endpoint */
 
@@ -4667,7 +4736,7 @@ static int stm32_ep_clrstall(FAR struct stm32_ep_s *privep)
     {
       /* Clear the stall bit in the IN endpoint device control register */
 
-      regaddr  = STM32_OTG_DIEPCTL(privep->epphy);
+      regaddr = STM32_OTG_DIEPCTL(privep->epphy);
       stallbit = OTG_DIEPCTL_STALL;
       data0bit = OTG_DIEPCTL_SD0PID;
     }
@@ -4675,14 +4744,14 @@ static int stm32_ep_clrstall(FAR struct stm32_ep_s *privep)
     {
       /* Clear the stall bit in the IN endpoint device control register */
 
-      regaddr  = STM32_OTG_DOEPCTL(privep->epphy);
+      regaddr = STM32_OTG_DOEPCTL(privep->epphy);
       stallbit = OTG_DOEPCTL_STALL;
       data0bit = OTG_DOEPCTL_SD0PID;
     }
 
   /* Clear the stall bit */
 
-  regval  = stm32_getreg(regaddr);
+  regval = stm32_getreg(regaddr);
   regval &= ~stallbit;
 
   /* Set the DATA0 pid for interrupt and bulk endpoints */
@@ -4779,7 +4848,7 @@ static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev,
   int epphy;
   int epno = 0;
 
-  usbtrace(TRACE_DEVALLOCEP, (uint16_t)eplog);
+  usbtrace(TRACE_DEVALLOCEP, (uint16_t) eplog);
 
   /* Ignore any direction bits in the logical address */
 
@@ -4794,16 +4863,17 @@ static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev,
 
   if (epphy > 0)
     {
-      /* Otherwise, we will return the endpoint structure only for the requested
-       * 'logical' endpoint.  All of the other checks will still be performed.
+      /* Otherwise, we will return the endpoint structure only for the
+       * requested 'logical' endpoint.  All of the other checks will still be
+       * performed.
        *
        * First, verify that the logical endpoint is in the range supported by
-       * by the hardware.
+       * the hardware.
        */
 
       if (epphy >= STM32_NENDPOINTS)
         {
-          usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epphy);
+          usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t) epphy);
           return NULL;
         }
 
@@ -4841,7 +4911,7 @@ static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev,
       /* We should not get here */
     }
 
-  usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOEP), (uint16_t)eplog);
+  usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOEP), (uint16_t) eplog);
   leave_critical_section(flags);
   return NULL;
 }
@@ -4860,7 +4930,7 @@ static void stm32_ep_free(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep)
   FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep;
   irqstate_t flags;
 
-  usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy);
+  usbtrace(TRACE_DEVFREEEP, (uint16_t) privep->epphy);
 
   if (priv && privep)
     {
@@ -4920,14 +4990,14 @@ static int stm32_wakeup(struct usbdev_s *dev)
         {
           /* Re-start the PHY clock and un-gate USB core clock (HCLK) */
 
-#ifdef CONFIG_USBDEV_LOWPOWER
+#  ifdef CONFIG_USBDEV_LOWPOWER
           regval = stm32_getreg(STM32_OTG_PCGCCTL);
           regval &= ~(OTG_PCGCCTL_STPPCLK | OTG_PCGCCTL_GATEHCLK);
           stm32_putreg(regval, STM32_OTG_PCGCCTL);
-#endif
+#  endif
           /* Activate Remote wakeup signaling */
 
-          regval  = stm32_getreg(STM32_OTG_DCTL);
+          regval = stm32_getreg(STM32_OTG_DCTL);
           regval |= OTG_DCTL_RWUSIG;
           stm32_putreg(regval, STM32_OTG_DCTL);
           up_mdelay(5);
@@ -4952,15 +5022,15 @@ static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered)
 {
   FAR struct stm32_usbdev_s *priv = (FAR struct stm32_usbdev_s *)dev;
 
-  usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
+  usbtrace(TRACE_DEVSELFPOWERED, (uint16_t) selfpowered);
 
-#ifdef CONFIG_DEBUG_FEATURES
+#  ifdef CONFIG_DEBUG_FEATURES
   if (!dev)
     {
       usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
       return -ENODEV;
     }
-#endif
+#  endif
 
   priv->selfpowered = selfpowered;
   return OK;
@@ -4978,22 +5048,22 @@ static int stm32_pullup(struct usbdev_s *dev, bool enable)
 {
   uint32_t regval;
 
-  usbtrace(TRACE_DEVPULLUP, (uint16_t)enable);
+  usbtrace(TRACE_DEVPULLUP, (uint16_t) enable);
 
   irqstate_t flags = enter_critical_section();
   regval = stm32_getreg(STM32_OTG_DCTL);
   if (enable)
     {
       /* Connect the device by clearing the soft disconnect bit in the DCTL
-       * register
+       * register.
        */
 
       regval &= ~OTG_DCTL_SDIS;
     }
   else
     {
-      /* Connect the device by setting the soft disconnect bit in the DCTL
-       * register
+      /* Disconnect the device by setting the soft disconnect bit in the DCTL
+       * register.
        */
 
       regval |= OTG_DCTL_SDIS;
@@ -5020,21 +5090,19 @@ static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address)
 
   regval = stm32_getreg(STM32_OTG_DCFG);
   regval &= ~OTG_DCFG_DAD_MASK;
-  regval |= ((uint32_t)address << OTG_DCFG_DAD_SHIFT);
+  regval |= ((uint32_t) address << OTG_DCFG_DAD_SHIFT);
   stm32_putreg(regval, STM32_OTG_DCFG);
 
-  /* Are we now addressed?  (i.e., do we have a non-NULL device
-   * address?)
-   */
+  /* Are we now addressed? (i.e., do we have a non-NULL device address?) */
 
   if (address != 0)
     {
-      priv->devstate  = DEVSTATE_ADDRESSED;
+      priv->devstate = DEVSTATE_ADDRESSED;
       priv->addressed = true;
     }
   else
     {
-      priv->devstate  = DEVSTATE_DEFAULT;
+      priv->devstate = DEVSTATE_DEFAULT;
       priv->addressed = false;
     }
 }
@@ -5131,34 +5199,33 @@ static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv)
   priv->epavail[0] = STM32_EP_AVAILABLE;
   priv->epavail[1] = STM32_EP_AVAILABLE;
 
-  priv->epin[EP0].ep.priv  = priv;
+  priv->epin[EP0].ep.priv = priv;
   priv->epout[EP0].ep.priv = priv;
 
   /* Initialize the endpoint lists */
 
   for (i = 0; i < STM32_NENDPOINTS; i++)
     {
-      /* Set endpoint operations, reference to driver structure (not
-       * really necessary because there is only one controller), and
-       * the physical endpoint number (which is just the index to the
-       * endpoint).
+      /* Set endpoint operations, reference to driver structure (not really
+       * necessary because there is only one controller), and the physical
+       * endpoint number (which is just the index to the endpoint).
        */
 
-      privep           = &priv->epin[i];
-      privep->ep.ops   = &g_epops;
-      privep->dev      = priv;
-      privep->isin     = 1;
+      privep = &priv->epin[i];
+      privep->ep.ops = &g_epops;
+      privep->dev = priv;
+      privep->isin = 1;
 
-      /* The index, i, is the physical endpoint address;  Map this
-       * to a logical endpoint address usable by the class driver.
+      /* The index, i, is the physical endpoint address; Map this to a logical
+       * endpoint address usable by the class driver.
        */
 
-      privep->epphy    = i;
+      privep->epphy = i;
       privep->ep.eplog = STM32_EPPHYIN2LOG(i);
 
       /* Control until endpoint is activated */
 
-      privep->eptype       = USB_EP_ATTR_XFER_CONTROL;
+      privep->eptype = USB_EP_ATTR_XFER_CONTROL;
       privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE;
     }
 
@@ -5166,26 +5233,25 @@ static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv)
 
   for (i = 0; i < STM32_NENDPOINTS; i++)
     {
-      /* Set endpoint operations, reference to driver structure (not
-       * really necessary because there is only one controller), and
-       * the physical endpoint number (which is just the index to the
-       * endpoint).
+      /* Set endpoint operations, reference to driver structure (not really
+       * necessary because there is only one controller), and the physical
+       * endpoint number (which is just the index to the endpoint).
        */
 
-      privep           = &priv->epout[i];
-      privep->ep.ops   = &g_epops;
-      privep->dev      = priv;
+      privep = &priv->epout[i];
+      privep->ep.ops = &g_epops;
+      privep->dev = priv;
 
-      /* The index, i, is the physical endpoint address;  Map this
-       * to a logical endpoint address usable by the class driver.
+      /* The index, i, is the physical endpoint address; Map this to a logical
+       * endpoint address usable by the class driver.
        */
 
-      privep->epphy    = i;
+      privep->epphy = i;
       privep->ep.eplog = STM32_EPPHYOUT2LOG(i);
 
       /* Control until endpoint is activated */
 
-      privep->eptype       = USB_EP_ATTR_XFER_CONTROL;
+      privep->eptype = USB_EP_ATTR_XFER_CONTROL;
       privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE;
     }
 }
@@ -5214,15 +5280,86 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
 
   stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG);
 
-#if defined(CONFIG_STM32F7_OTGHS)
-  /* Set the PHYSEL bit in the GUSBCFG register to select the OTG HS serial
-   * transceiver: "This bit is always 1 with write-only access"
+#  ifdef CONFIG_STM32F7_OTGFSHS
+
+#    ifndef CONFIG_STM32F7_NO_ULPI
+
+  /* Switch off FS tranceiver */
+
+  regval = stm32_getreg(STM32_OTG_GCCFG);
+  regval &= ~(OTG_GCCFG_PWRDWN);
+  stm32_putreg(regval, STM32_OTG_GCCFG);
+
+  /* Init The ULPI Interface: Set the PHYSEL bit in the GUSBCFG register to
+   * select the OTG HS serial 0: USB 2.0 external ULPI high-speed PHY or
+   * internal UTMI high-speed PHY" 1: USB 1.1 full-speed serial transceiver
    */
 
-  regval  = stm32_getreg(STM32_OTG_GUSBCFG);
+  regval = stm32_getreg(STM32_OTG_GUSBCFG);
+  regval &= ~(OTG_GUSBCFG_TSDPS | OTG_GUSBCFG_ULPIFSLS | OTG_GUSBCFG_PHYSEL);
+  stm32_putreg(regval, STM32_OTG_GUSBCFG);
+
+  /* Select vbus source */
+
+  regval = stm32_getreg(STM32_OTG_GUSBCFG);
+  regval &= ~(OTG_GUSBCFG_ULPIEVBUSD | OTG_GUSBCFG_ULPIEVBUSI);
+  stm32_putreg(regval, STM32_OTG_GUSBCFG);
+
+#      ifdef CONFIG_STM32F7_INTERNAL_ULPI
+
+  /* Select UTMI/ULPI Interace */
+
+  regval = stm32_getreg(STM32_OTG_GUSBCFG);
+  regval &= ~OTG_GUSBCFG_ULPISEL;
+  stm32_putreg(regval, STM32_OTG_GUSBCFG);
+
+  /* Not in datasheet but in stmcube ? */
+
+  regval = stm32_getreg(STM32_OTG_GCCFG);
+  regval |= OTG_GCCFG_PHYHSEN;
+  stm32_putreg(regval, STM32_OTG_GCCFG);
+
+  /* Enable LDO */
+
+  stm32_putreg(USBPHYC_LDO_ENABLE, STM32_USBPHYC_LDO);
+
+  /* wait for LDO Ready */
+
+  while (!(stm32_getreg(STM32_USBPHYC_LDO) & USBPHYC_LDO_STATUS));
+
+  /* Controls PHY frequency operation selection */
+
+  stm32_putreg(USBPHYC_PLL1_SEL_25MHz, STM32_USBPHYC_PLL1);
+
+  /* Control the tuning interface of the High Speed PHY */
+
+  regval = stm32_getreg(STM32_USBPHYC_TUNE);
+
+  /* TODO set right value */
+
+  regval |= 0x00000f13;
+  stm32_putreg(regval, STM32_USBPHYC_TUNE);
+
+  /* Enable PLL internal PHY */
+
+  regval = stm32_getreg(STM32_USBPHYC_PLL1);
+  regval |= USBPHYC_PLL1_EN;
+  stm32_putreg(regval, STM32_USBPHYC_PLL1);
+
+  /* 2ms delay required for clk to be stable */
+
+  up_udelay(2000);
+
+#      endif  /* CONFIG_STM32F7_INTERNAL_ULPI */
+#    endif    /* ifndef CONFIG_STM32F7_NO_ULPI */
+
+#  else       /* CONFIG_STM32F7_OTGFSHS */
+
+  regval = stm32_getreg(STM32_OTG_GUSBCFG);
   regval |= OTG_GUSBCFG_PHYSEL;
   stm32_putreg(regval, STM32_OTG_GUSBCFG);
-#endif
+
+#  endif      /* CONFIG_STM32F7_OTGFSHS */
 
   /* Common USB OTG core initialization */
   /* Reset after a PHY select and set Host mode.  First, wait for AHB master
@@ -5241,7 +5378,9 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
 
   /* Then perform the core soft reset. */
 
-  stm32_putreg(OTG_GRSTCTL_CSRST, STM32_OTG_GRSTCTL);
+  regval = stm32_getreg(STM32_OTG_GRSTCTL);
+  regval |= OTG_GRSTCTL_CSRST;
+  stm32_putreg(regval, STM32_OTG_GRSTCTL);
   for (timeout = 0; timeout < STM32_READY_DELAY; timeout++)
     {
       regval = stm32_getreg(STM32_OTG_GRSTCTL);
@@ -5257,35 +5396,32 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
 
   /* Deactivate the power down */
 
+  /* Detection Enable when set */
 
-  /* Detection Enable when set
-   */
+  regval = stm32_getreg(STM32_OTG_GCCFG);
 
-  regval  = OTG_GCCFG_PWRDWN;
+#  if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_NO_ULPI))
+  regval |= OTG_GCCFG_PWRDWN;
+#  endif
 
-# ifdef CONFIG_USBDEV_VBUSSENSING
+#  ifdef CONFIG_USBDEV_VBUSSENSING
   regval |= OTG_GCCFG_VBDEN;
-# endif
-
+#  endif
 
   stm32_putreg(regval, STM32_OTG_GCCFG);
   up_mdelay(20);
 
-  /* When VBUS sensing is not used we
-   * need to force the B session valid
-   */
+  /* When VBUS sensing is not used we need to force the B session valid */
 
-
-# ifndef CONFIG_USBDEV_VBUSSENSING
-  regval  =  stm32_getreg(STM32_OTG_GOTGCTL);
+#  ifndef CONFIG_USBDEV_VBUSSENSING
+  regval = stm32_getreg(STM32_OTG_GOTGCTL);
   regval |= (OTG_GOTGCTL_BVALOEN | OTG_GOTGCTL_BVALOVAL);
   stm32_putreg(regval, STM32_OTG_GOTGCTL);
-# endif
-
+#  endif
 
   /* Force Device Mode */
 
-  regval  = stm32_getreg(STM32_OTG_GUSBCFG);
+  regval = stm32_getreg(STM32_OTG_GUSBCFG);
   regval &= ~OTG_GUSBCFG_FHMOD;
   regval |= OTG_GUSBCFG_FDMOD;
   stm32_putreg(regval, STM32_OTG_GUSBCFG);
@@ -5303,79 +5439,83 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
   regval |= OTG_DCFG_PFIVL_80PCT;
   stm32_putreg(regval, STM32_OTG_DCFG);
 
-  /* Set full speed PHY */
+  /* Set PHY speed */
 
   regval = stm32_getreg(STM32_OTG_DCFG);
   regval &= ~OTG_DCFG_DSPD_MASK;
+#  ifdef CONFIG_STM32F7_OTGFSHS
+  regval |= OTG_DCFG_DSPD_HS;
+#  else
   regval |= OTG_DCFG_DSPD_FS;
+#  endif
   stm32_putreg(regval, STM32_OTG_DCFG);
 
   /* Set Rx FIFO size */
 
   stm32_putreg(STM32_RXFIFO_WORDS, STM32_OTG_GRXFSIZ);
 
-#if STM32_NENDPOINTS > 0
+#  if STM32_NENDPOINTS > 0
   address = STM32_RXFIFO_WORDS;
-  regval  = (address << OTG_DIEPTXF0_TX0FD_SHIFT) |
-            (STM32_EP0_TXFIFO_WORDS << OTG_DIEPTXF0_TX0FSA_SHIFT);
+  regval = (address << OTG_DIEPTXF0_TX0FD_SHIFT) |
+    (STM32_EP0_TXFIFO_WORDS << OTG_DIEPTXF0_TX0FSA_SHIFT);
   stm32_putreg(regval, STM32_OTG_DIEPTXF0);
-#endif
+#  endif
 
-#if STM32_NENDPOINTS > 1
+#  if STM32_NENDPOINTS > 1
   address += STM32_EP0_TXFIFO_WORDS;
-  regval   = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
-             (STM32_EP1_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
+  regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
+    (STM32_EP1_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
   stm32_putreg(regval, STM32_OTG_DIEPTXF(1));
-#endif
+#  endif
 
-#if STM32_NENDPOINTS > 2
+#  if STM32_NENDPOINTS > 2
   address += STM32_EP1_TXFIFO_WORDS;
-  regval   = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
-             (STM32_EP2_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
+  regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
+    (STM32_EP2_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
   stm32_putreg(regval, STM32_OTG_DIEPTXF(2));
-#endif
+#  endif
 
-#if STM32_NENDPOINTS > 3
+#  if STM32_NENDPOINTS > 3
   address += STM32_EP2_TXFIFO_WORDS;
-  regval   = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
-             (STM32_EP3_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
+  regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
+    (STM32_EP3_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
   stm32_putreg(regval, STM32_OTG_DIEPTXF(3));
-#endif
+#  endif
 
-#if STM32_NENDPOINTS > 4
+#  if STM32_NENDPOINTS > 4
   address += STM32_EP3_TXFIFO_WORDS;
-  regval   = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
-             (STM32_EP4_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
+  regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
+    (STM32_EP4_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
   stm32_putreg(regval, STM32_OTG_DIEPTXF(4));
-#endif
+#  endif
 
-#if STM32_NENDPOINTS > 5
+#  if STM32_NENDPOINTS > 5
   address += STM32_EP4_TXFIFO_WORDS;
-  regval   = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
-             (STM32_EP5_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
+  regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
+    (STM32_EP5_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
   stm32_putreg(regval, STM32_OTG_DIEPTXF(5));
-#endif
+#  endif
 
-#if STM32_NENDPOINTS > 6
+#  if STM32_NENDPOINTS > 6
   address += STM32_EP5_TXFIFO_WORDS;
-  regval   = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
-             (STM32_EP6_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
+  regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
+    (STM32_EP6_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
   stm32_putreg(regval, STM32_OTG_DIEPTXF(6));
-#endif
+#  endif
 
-#if STM32_NENDPOINTS > 7
+#  if STM32_NENDPOINTS > 7
   address += STM32_EP6_TXFIFO_WORDS;
-  regval   = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
-             (STM32_EP7_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
+  regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
+    (STM32_EP7_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
   stm32_putreg(regval, STM32_OTG_DIEPTXF(7));
-#endif
+#  endif
 
-#if STM32_NENDPOINTS > 8
+#  if STM32_NENDPOINTS > 8
   address += STM32_EP7_TXFIFO_WORDS;
-  regval   = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
-             (STM32_EP8_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
+  regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
+    (STM32_EP8_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
   stm32_putreg(regval, STM32_OTG_DIEPTXF(8));
-#endif
+#  endif
 
   /* Flush the FIFOs */
 
@@ -5399,7 +5539,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
         {
           /* The endpoint is already enabled */
 
-          regval = OTG_DIEPCTL_EPENA | OTG_DIEPCTL_SNAK;
+          regval = OTG_DIEPCTL_EPDIS | OTG_DIEPCTL_SNAK;
         }
       else
         {
@@ -5420,7 +5560,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
         {
           /* The endpoint is already enabled */
 
-          regval = OTG_DOEPCTL_EPENA | OTG_DOEPCTL_SNAK;
+          regval = OTG_DOEPCTL_EPDIS | OTG_DOEPCTL_SNAK;
         }
       else
         {
@@ -5443,52 +5583,51 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
   /* Clear any pending interrupts */
 
   regval = stm32_getreg(STM32_OTG_GINTSTS);
-  regval &=  OTG_GINT_RESERVED;
+  regval &= OTG_GINT_RESERVED;
   stm32_putreg(regval | OTG_GINT_RC_W1, STM32_OTG_GINTSTS);
 
-#if defined(CONFIG_STM32F7_OTGHS) && !defined(BOARD_ENABLE_USBOTG_HSULPI)
-  /* Disable the ULPI Clock enable in RCC AHB1 Register.  This must
-   * be done because if both the ULPI and the FS PHY clock enable bits
-   * are set at the same time, the ARM never awakens from WFI due to
-   * some bug / errata in the chip.
+#  if defined(CONFIG_STM32F7_OTGFSHS) && defined(CONFIG_STM32F7_NO_ULPI)
+  /* Disable the ULPI Clock enable in RCC AHB1 Register.  This must be done
+   * because if both the ULPI and the FS PHY clock enable bits are set at the
+   * same time, the ARM never awakens from WFI due to some bug / errata in the
+   * chip.
    */
 
   regval = stm32_getreg(STM32_RCC_AHB1LPENR);
   regval &= ~RCC_AHB1ENR_OTGHSULPIEN;
   stm32_putreg(regval, STM32_RCC_AHB1LPENR);
-#endif
+#  endif
 
   /* Enable the interrupts in the INTMSK */
 
   regval = (OTG_GINT_RXFLVL | OTG_GINT_USBSUSP | OTG_GINT_ENUMDNE |
             OTG_GINT_IEP | OTG_GINT_OEP | OTG_GINT_USBRST);
 
-#ifdef CONFIG_USBDEV_ISOCHRONOUS
+#  ifdef CONFIG_USBDEV_ISOCHRONOUS
   regval |= (OTG_GINT_IISOIXFR | OTG_GINT_IISOOXFR);
-#endif
+#  endif
 
-#ifdef CONFIG_USBDEV_SOFINTERRUPT
+#  ifdef CONFIG_USBDEV_SOFINTERRUPT
   regval |= OTG_GINT_SOF;
-#endif
+#  endif
 
-#ifdef CONFIG_USBDEV_VBUSSENSING
+#  ifdef CONFIG_USBDEV_VBUSSENSING
   regval |= (OTG_GINT_OTG | OTG_GINT_SRQ);
-#endif
+#  endif
 
-#ifdef CONFIG_DEBUG_USB
+#  ifdef CONFIG_DEBUG_USB
   regval |= OTG_GINT_MMIS;
-#endif
+#  endif
 
   stm32_putreg(regval, STM32_OTG_GINTMSK);
 
-  /* Enable the USB global interrupt by setting GINTMSK in the global OTG
-   * AHB configuration register; Set the TXFELVL bit in the GAHBCFG
-   * register so that TxFIFO interrupts will occur when the TxFIFO is truly
-   * empty (not just half full).
+  /* Enable the USB global interrupt by setting GINTMSK in the global OTG AHB
+   * configuration register; Set the TXFELVL bit in the GAHBCFG register so
+   * that TxFIFO interrupts will occur when the TxFIFO is truly empty (not just
+   * half full).
    */
 
-  stm32_putreg(OTG_GAHBCFG_GINTMSK | OTG_GAHBCFG_TXFELVL,
-               STM32_OTG_GAHBCFG);
+  stm32_putreg(OTG_GAHBCFG_GINTMSK | OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG);
 }
 
 /****************************************************************************
@@ -5515,8 +5654,7 @@ void up_usbinitialize(void)
   /* At present, there is only a single OTG device support. Hence it is
    * pre-allocated as g_otghsdev.  However, in most code, the private data
    * structure will be referenced using the 'priv' pointer (rather than the
-   * global data) in order to simplify any future support for multiple
-   * devices.
+   * global data) in order to simplify any future support for multiple devices.
    */
 
   FAR struct stm32_usbdev_s *priv = &g_otghsdev;
@@ -5524,30 +5662,27 @@ void up_usbinitialize(void)
 
   usbtrace(TRACE_DEVINIT, 0);
 
-  /* Here we assume that:
-   *
-   * 1. GPIOA and OTG  peripheral clocking has already been enabled as part
-   *    of the boot sequence.
-   * 2. Board-specific logic has already enabled other board specific GPIOs
-   *    for things like soft pull-up, VBUS sensing, power controls, and over-
-   *    current detection.
+  /* Here we assume that: 1. GPIOA and OTG peripheral clocking has already
+   * been enabled as part of the boot sequence. 2. Board-specific logic has
+   * already enabled other board specific GPIOs for things like soft pull-up,
+   * VBUS sensing, power controls, and over- current detection.
    */
 
-  /* Configure OTG alternate function pins
-   */
+  /* Configure OTG alternate function pins */
 
   stm32_configgpio(GPIO_OTG_DM);
   stm32_configgpio(GPIO_OTG_DP);
-  stm32_configgpio(GPIO_OTG_ID);    /* Only needed for OTG */
+  stm32_configgpio(GPIO_OTG_ID);        /* Only needed for OTG */
 
   /* SOF output pin configuration is configurable. */
 
-#ifdef CONFIG_STM32F7_OTG_SOFOUTPUT
+#  ifdef CONFIG_STM32F7_OTG_SOFOUTPUT
   stm32_configgpio(GPIO_OTG_SOF);
-#endif
+#  endif
 
   /* Uninitialize the hardware so that we know that we are starting from a
-   * known state. */
+   * known state.
+   */
 
   up_usbuninitialize();
 
@@ -5579,6 +5714,7 @@ void up_usbinitialize(void)
   /* Enable USB controller interrupts at the NVIC */
 
   up_enable_irq(STM32_IRQ_OTG);
+
   return;
 
 errout:
@@ -5591,7 +5727,7 @@ errout:
 
 void up_usbuninitialize(void)
 {
-  /* At present, there is only a single OTG  device support. Hence it is
+  /* At present, there is only a single OTG device support. Hence it is
    * pre-allocated as g_otghsdev.  However, in most code, the private data
    * structure will be referenced using the 'priv' pointer (rather than the
    * global data) in order to simplify any future support for multiple devices.
@@ -5656,7 +5792,7 @@ void up_usbuninitialize(void)
 
 int usbdev_register(struct usbdevclass_driver_s *driver)
 {
-  /* At present, there is only a single OTG  device support. Hence it is
+  /* At present, there is only a single OTG device support. Hence it is
    * pre-allocated as g_otghsdev.  However, in most code, the private data
    * structure will be referenced using the 'priv' pointer (rather than the
    * global data) in order to simplify any future support for multiple devices.
@@ -5667,7 +5803,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
 
   usbtrace(TRACE_DEVREGISTER, 0);
 
-#ifdef CONFIG_DEBUG_FEATURES
+#  ifdef CONFIG_DEBUG_FEATURES
   if (!driver || !driver->ops->bind || !driver->ops->unbind ||
       !driver->ops->disconnect || !driver->ops->setup)
     {
@@ -5680,7 +5816,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
       usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0);
       return -EBUSY;
     }
-#endif
+#  endif
 
   /* First hook up the driver */
 
@@ -5691,7 +5827,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
   ret = CLASS_BIND(driver, &priv->usbdev);
   if (ret)
     {
-      usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret);
+      usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t) - ret);
       priv->driver = NULL;
     }
   else
@@ -5700,16 +5836,21 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
 
       up_enable_irq(STM32_IRQ_OTG);
 
-      /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set
-       *        the RS bit to enable the controller.  It kind of makes sense
-       *        to do this after the class has bound to us...
+      /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set the
+       *        RS bit to enable the controller.  It kind of makes sense to
+       *        do this after the class has bound to us...
        * GEN:   This bug is really in the class driver.  It should make the
-       *        soft connect when it is ready to be enumerated.  I have added
-       *        that logic to the class drivers but left this logic here.
+       *        soft connect when it is ready to be enumerated.  I have
+       *        added that logic to the class drivers but left this logic
+       *        here.
        */
 
       stm32_pullup(&priv->usbdev, true);
+#  if defined(CONFIG_STM32F7_INTERNAL_ULPI) ||  defined(CONFIG_STM32F7_EXTERNAL_ULPI)
+      priv->usbdev.speed = USB_SPEED_HIGH;
+#  else
       priv->usbdev.speed = USB_SPEED_FULL;
+#  endif
     }
 
   return ret;
@@ -5738,16 +5879,16 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
 
   usbtrace(TRACE_DEVUNREGISTER, 0);
 
-#ifdef CONFIG_DEBUG_FEATURES
+#  ifdef CONFIG_DEBUG_FEATURES
   if (driver != priv->driver)
     {
       usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0);
       return -EINVAL;
     }
-#endif
+#  endif
 
-  /* Reset the hardware and cancel all requests.  All requests must be
-   * canceled while the class driver is still bound.
+  /* Reset the hardware and cancel all requests.  All requests must be canceled
+   * while the class driver is still bound.
    */
 
   flags = enter_critical_section();
@@ -5775,4 +5916,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
   return OK;
 }
 
-#endif /* CONFIG_USBDEV && CONFIG_STM32F7_OTGDEV */
+#endif    /* CONFIG_USBDEV && CONFIG_STM32F7_OTGDEV */
diff --git a/arch/arm/src/stm32f7/stm32_procfs_dtcm.c b/arch/arm/src/stm32f7/stm32_procfs_dtcm.c
index 30c54f2387d..9abcd6371e1 100644
--- a/arch/arm/src/stm32f7/stm32_procfs_dtcm.c
+++ b/arch/arm/src/stm32f7/stm32_procfs_dtcm.c
@@ -69,7 +69,8 @@
 
 #include "stm32_dtcm.h"
 
-#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_FS_PROCFS)
+#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_FS_PROCFS) && \
+     defined(CONFIG_FS_PROCFS_REGISTER) && defined(CONFIG_STM32F7_DTCM_PROCFS)
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -120,7 +121,7 @@ static int     dtcm_stat(FAR const char *relpath, FAR struct stat *buf);
  * with any compiler.
  */
 
-const struct procfs_operations dtcm_procfsoperations =
+static const struct procfs_operations dtcm_procfsoperations =
 {
   dtcm_open,       /* open */
   dtcm_close,      /* close */
@@ -134,6 +135,12 @@ const struct procfs_operations dtcm_procfsoperations =
   dtcm_stat        /* stat */
 };
 
+static const struct procfs_entry_s g_procfs_dtcm =
+{
+  "dtcm",
+  &dtcm_procfsoperations
+};
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -320,4 +327,22 @@ static int dtcm_stat(const char *relpath, struct stat *buf)
   return OK;
 }
 
-#endif /* !CONFIG_DISABLE_MOUNTPOINT && CONFIG_FS_PROCFS */
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: dtcm_procfs_register
+ *
+ * Description:
+ *   Register the DTCM procfs file system entry
+ *
+ ****************************************************************************/
+
+int dtcm_procfs_register(void)
+{
+  return procfs_register(&g_procfs_dtcm);
+}
+
+#endif /* !CONFIG_DISABLE_MOUNTPOINT && CONFIG_FS_PROCFS &&
+        * CONFIG_FS_PROCFS_REGISTER && CONFIG_STM32F7_DTCM_PROCFS */
diff --git a/arch/arm/src/stm32f7/stm32_pwm.c b/arch/arm/src/stm32f7/stm32_pwm.c
new file mode 100644
index 00000000000..0ac1070af21
--- /dev/null
+++ b/arch/arm/src/stm32f7/stm32_pwm.c
@@ -0,0 +1,2527 @@
+/****************************************************************************
+ * arch/arm/src/stm32f7/stm32_pwm.c
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *            Paul Alexander Patience 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "stm32_pwm.h"
+#include "stm32_gpio.h"
+
+/* This module then only compiles if there is at least one enabled timer
+ * intended for use with the PWM upper half driver.
+ */
+
+#if defined(CONFIG_STM32F7_TIM1_PWM)  || defined(CONFIG_STM32F7_TIM2_PWM)  || \
+    defined(CONFIG_STM32F7_TIM3_PWM)  || defined(CONFIG_STM32F7_TIM4_PWM)  || \
+    defined(CONFIG_STM32F7_TIM5_PWM)  || defined(CONFIG_STM32F7_TIM8_PWM)  || \
+    defined(CONFIG_STM32F7_TIM9_PWM)  || defined(CONFIG_STM32F7_TIM10_PWM) || \
+    defined(CONFIG_STM32F7_TIM11_PWM) || defined(CONFIG_STM32F7_TIM12_PWM) || \
+    defined(CONFIG_STM32F7_TIM13_PWM) || defined(CONFIG_STM32F7_TIM14_PWM) || \
+    defined(CONFIG_STM32F7_TIM15_PWM) || defined(CONFIG_STM32F7_TIM16_PWM) || \
+    defined(CONFIG_STM32F7_TIM17_PWM)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* PWM/Timer Definitions ****************************************************/
+
+/* The following definitions are used to identify the various time types */
+
+#define TIMTYPE_BASIC      0  /* Basic timers: TIM6-7 */
+#define TIMTYPE_GENERAL16  1  /* General 16-bit timers: TIM3-4 */
+#define TIMTYPE_COUNTUP16  2  /* General 16-bit count-up timers: TIM9-14 */
+#define TIMTYPE_GENERAL32  3  /* General 32-bit timers: TIM2-5 */
+#define TIMTYPE_ADVANCED   4  /* Advanced timers:  TIM1-8 */
+
+#define TIMTYPE_TIM1       TIMTYPE_ADVANCED
+#define TIMTYPE_TIM2       TIMTYPE_GENERAL32
+#define TIMTYPE_TIM3       TIMTYPE_GENERAL16
+#define TIMTYPE_TIM4       TIMTYPE_GENERAL16
+#define TIMTYPE_TIM5       TIMTYPE_GENERAL32
+#define TIMTYPE_TIM6       TIMTYPE_BASIC
+#define TIMTYPE_TIM7       TIMTYPE_BASIC
+#define TIMTYPE_TIM8       TIMTYPE_ADVANCED
+#define TIMTYPE_TIM9       TIMTYPE_COUNTUP16
+#define TIMTYPE_TIM10      TIMTYPE_COUNTUP16
+#define TIMTYPE_TIM11      TIMTYPE_COUNTUP16
+#define TIMTYPE_TIM12      TIMTYPE_COUNTUP16
+#define TIMTYPE_TIM13      TIMTYPE_COUNTUP16
+#define TIMTYPE_TIM14      TIMTYPE_COUNTUP16
+
+/* Timer clock source, RCC EN offset, enable bit,
+ * RCC RST offset, reset bit to use
+ */
+
+#define TIMCLK_TIM1      STM32_APB2_TIM1_CLKIN
+#define TIMRCCEN_TIM1    STM32_RCC_APB2ENR
+#define TIMEN_TIM1       RCC_APB2ENR_TIM1EN
+#define TIMRCCRST_TIM1   STM32_RCC_APB2RSTR
+#define TIMRST_TIM1      RCC_APB2RSTR_TIM1RST
+#define TIMCLK_TIM2      STM32_APB1_TIM2_CLKIN
+#define TIMRCCEN_TIM2    STM32_RCC_APB1ENR
+#define TIMEN_TIM2       RCC_APB1ENR_TIM2EN
+#define TIMRCCRST_TIM2   STM32_RCC_APB1RSTR
+#define TIMRST_TIM2      RCC_APB1RSTR_TIM2RST
+#define TIMCLK_TIM3      STM32_APB1_TIM3_CLKIN
+#define TIMRCCEN_TIM3    STM32_RCC_APB1ENR
+#define TIMEN_TIM3       RCC_APB1ENR_TIM3EN
+#define TIMRCCRST_TIM3   STM32_RCC_APB1RSTR
+#define TIMRST_TIM3      RCC_APB1RSTR_TIM3RST
+#define TIMCLK_TIM4      STM32_APB1_TIM4_CLKIN
+#define TIMRCCEN_TIM4    STM32_RCC_APB1ENR
+#define TIMEN_TIM4       RCC_APB1ENR_TIM4EN
+#define TIMRCCRST_TIM4   STM32_RCC_APB1RSTR
+#define TIMRST_TIM4      RCC_APB1RSTR_TIM4RST
+#define TIMCLK_TIM5      STM32_APB1_TIM5_CLKIN
+#define TIMRCCEN_TIM5    STM32_RCC_APB1ENR
+#define TIMEN_TIM5       RCC_APB1ENR_TIM5EN
+#define TIMRCCRST_TIM5   STM32_RCC_APB1RSTR
+#define TIMRST_TIM5      RCC_APB1RSTR_TIM5RST
+#define TIMCLK_TIM8      STM32_APB2_TIM8_CLKIN
+#define TIMRCCEN_TIM8    STM32_RCC_APB2ENR
+#define TIMEN_TIM8       RCC_APB2ENR_TIM8EN
+#define TIMRCCRST_TIM8   STM32_RCC_APB2RSTR
+#define TIMRST_TIM8      RCC_APB2RSTR_TIM8RST
+#define TIMCLK_TIM9      STM32_APB2_TIM9_CLKIN
+#define TIMRCCEN_TIM9    STM32_RCC_APB2ENR
+#define TIMEN_TIM9       RCC_APB2ENR_TIM9EN
+#define TIMRCCRST_TIM9   STM32_RCC_APB2RSTR
+#define TIMRST_TIM9      RCC_APB2RSTR_TIM9RST
+#define TIMCLK_TIM10     STM32_APB2_TIM10_CLKIN
+#define TIMRCCEN_TIM10   STM32_RCC_APB2ENR
+#define TIMEN_TIM10      RCC_APB2ENR_TIM10EN
+#define TIMRCCRST_TIM10  STM32_RCC_APB2RSTR
+#define TIMRST_TIM10     RCC_APB2RSTR_TIM10RST
+#define TIMCLK_TIM11     STM32_APB2_TIM11_CLKIN
+#define TIMRCCEN_TIM11   STM32_RCC_APB2ENR
+#define TIMEN_TIM11      RCC_APB2ENR_TIM11EN
+#define TIMRCCRST_TIM11  STM32_RCC_APB2RSTR
+#define TIMRST_TIM11     RCC_APB2RSTR_TIM11RST
+#define TIMCLK_TIM12     STM32_APB1_TIM12_CLKIN
+#define TIMRCCEN_TIM12   STM32_RCC_APB1ENR
+#define TIMEN_TIM12      RCC_APB1ENR_TIM12EN
+#define TIMRCCRST_TIM12  STM32_RCC_APB1RSTR
+#define TIMRST_TIM12     RCC_APB1RSTR_TIM12RST
+#define TIMCLK_TIM13     STM32_APB1_TIM13_CLKIN
+#define TIMRCCEN_TIM13   STM32_RCC_APB1ENR
+#define TIMEN_TIM13      RCC_APB1ENR_TIM13EN
+#define TIMRCCRST_TIM13  STM32_RCC_APB1RSTR
+#define TIMRST_TIM13     RCC_APB1RSTR_TIM13RST
+#define TIMCLK_TIM14     STM32_APB1_TIM14_CLKIN
+#define TIMRCCEN_TIM14   STM32_RCC_APB1ENR
+#define TIMEN_TIM14      RCC_APB1ENR_TIM14EN
+#define TIMRCCRST_TIM14  STM32_RCC_APB1RSTR
+#define TIMRST_TIM14     RCC_APB1RSTR_TIM14RST
+
+/* Debug ********************************************************************/
+
+#ifdef CONFIG_DEBUG_PWM_INFO
+#  define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
+#else
+#  define pwm_dumpgpio(p,m)
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+enum stm32_timmode_e
+{
+  STM32_TIMMODE_COUNTUP   = 0,
+  STM32_TIMMODE_COUNTDOWN = 1,
+  STM32_TIMMODE_CENTER1   = 2,
+  STM32_TIMMODE_CENTER2   = 3,
+  STM32_TIMMODE_CENTER3   = 4,
+};
+
+enum stm32_chanmode_e
+{
+  STM32_CHANMODE_PWM1        = 0,
+  STM32_CHANMODE_PWM2        = 1,
+  STM32_CHANMODE_COMBINED1   = 2,
+  STM32_CHANMODE_COMBINED2   = 3,
+  STM32_CHANMODE_ASYMMETRIC1 = 4,
+  STM32_CHANMODE_ASYMMETRIC2 = 5,
+};
+
+struct stm32_pwmchan_s
+{
+  uint8_t channel;                     /* Timer output channel: {1,..4} */
+  uint32_t pincfg;                     /* Output pin configuration */
+  enum stm32_chanmode_e mode;
+};
+
+/* This structure represents the state of one PWM timer */
+
+struct stm32_pwmtimer_s
+{
+  FAR const struct pwm_ops_s *ops;     /* PWM operations */
+  uint8_t timid;                       /* Timer ID {1,...,17} */
+  struct stm32_pwmchan_s channels[PWM_NCHANNELS];
+  uint8_t timtype;                     /* See the TIMTYPE_* definitions */
+  enum stm32_timmode_e mode;
+#ifdef CONFIG_PWM_PULSECOUNT
+  uint8_t irq;                         /* Timer update IRQ */
+  uint8_t prev;                        /* The previous value of the RCR (pre-loaded) */
+  uint8_t curr;                        /* The current value of the RCR (pre-loaded) */
+  uint32_t count;                      /* Remaining pluse count */
+#else
+  uint32_t frequency;                  /* Current frequency setting */
+#endif
+  uint32_t base;                       /* The base address of the timer */
+  uint32_t pclk;                       /* The frequency of the peripheral clock
+                                        * that drives the timer module. */
+#ifdef CONFIG_PWM_PULSECOUNT
+  FAR void *handle;                    /* Handle used for upper-half callback */
+#endif
+};
+
+/****************************************************************************
+ * Static Function Prototypes
+ ****************************************************************************/
+/* Register access */
+
+static uint16_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset);
+static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, uint16_t value);
+
+#ifdef CONFIG_DEBUG_PWM_INFO
+static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg);
+#else
+#  define pwm_dumpregs(priv,msg)
+#endif
+
+/* Timer management */
+
+static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
+                     FAR const struct pwm_info_s *info);
+
+#if defined(CONFIG_PWM_PULSECOUNT) && (defined(CONFIG_STM32F7_TIM1_PWM) || defined(CONFIG_STM32F7_TIM8_PWM))
+static int pwm_interrupt(struct stm32_pwmtimer_s *priv);
+#if defined(CONFIG_STM32F7_TIM1_PWM)
+static int pwm_tim1interrupt(int irq, void *context, FAR void *arg);
+#endif
+#if defined(CONFIG_STM32F7_TIM8_PWM)
+static int pwm_tim8interrupt(int irq, void *context, FAR void *arg);
+#endif
+static uint8_t pwm_pulsecount(uint32_t count);
+#endif
+
+/* PWM driver methods */
+
+static int pwm_setup(FAR struct pwm_lowerhalf_s *dev);
+static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev);
+
+#ifdef CONFIG_PWM_PULSECOUNT
+static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
+                     FAR const struct pwm_info_s *info,
+                     FAR void *handle);
+#else
+static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
+                     FAR const struct pwm_info_s *info);
+#endif
+
+static int pwm_stop(FAR struct pwm_lowerhalf_s *dev);
+static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev,
+                     int cmd, unsigned long arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This is the list of lower half PWM driver methods used by the upper half
+ * driver
+ */
+
+static const struct pwm_ops_s g_pwmops =
+{
+  .setup       = pwm_setup,
+  .shutdown    = pwm_shutdown,
+  .start       = pwm_start,
+  .stop        = pwm_stop,
+  .ioctl       = pwm_ioctl,
+};
+
+#ifdef CONFIG_STM32F7_TIM1_PWM
+static struct stm32_pwmtimer_s g_pwm1dev =
+{
+  .ops         = &g_pwmops,
+  .timid       = 1,
+  .channels    =
+  {
+#ifdef CONFIG_STM32F7_TIM1_CHANNEL1
+    {
+      .channel = 1,
+      .pincfg  = PWM_TIM1_CH1CFG,
+      .mode    = CONFIG_STM32F7_TIM1_CH1MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM1_CHANNEL2
+    {
+      .channel = 2,
+      .pincfg  = PWM_TIM1_CH2CFG,
+      .mode    = CONFIG_STM32F7_TIM1_CH2MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM1_CHANNEL3
+    {
+      .channel = 3,
+      .pincfg  = PWM_TIM1_CH3CFG,
+      .mode    = CONFIG_STM32F7_TIM1_CH3MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM1_CHANNEL4
+    {
+      .channel = 4,
+      .pincfg  = PWM_TIM1_CH4CFG,
+      .mode    = CONFIG_STM32F7_TIM1_CH4MODE,
+    },
+#endif
+  },
+  .timtype     = TIMTYPE_TIM1,
+  .mode        = CONFIG_STM32F7_TIM1_MODE,
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM1UP,
+#endif
+  .base        = STM32_TIM1_BASE,
+  .pclk        = TIMCLK_TIM1,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM2_PWM
+static struct stm32_pwmtimer_s g_pwm2dev =
+{
+  .ops         = &g_pwmops,
+  .timid       = 2,
+  .channels    =
+  {
+#ifdef CONFIG_STM32F7_TIM2_CHANNEL1
+    {
+      .channel = 1,
+      .pincfg  = PWM_TIM2_CH1CFG,
+      .mode    = CONFIG_STM32F7_TIM2_CH1MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM2_CHANNEL2
+    {
+      .channel = 2,
+      .pincfg  = PWM_TIM2_CH2CFG,
+      .mode    = CONFIG_STM32F7_TIM2_CH2MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM2_CHANNEL3
+    {
+      .channel = 3,
+      .pincfg  = PWM_TIM2_CH3CFG,
+      .mode    = CONFIG_STM32F7_TIM2_CH3MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM2_CHANNEL4
+    {
+      .channel = 4,
+      .pincfg  = PWM_TIM2_CH4CFG,
+      .mode    = CONFIG_STM32F7_TIM2_CH4MODE,
+    },
+#endif
+  },
+  .timtype     = TIMTYPE_TIM2,
+  .mode        = CONFIG_STM32F7_TIM2_MODE,
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM2,
+#endif
+  .base        = STM32_TIM2_BASE,
+  .pclk        = TIMCLK_TIM2,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM3_PWM
+static struct stm32_pwmtimer_s g_pwm3dev =
+{
+  .ops         = &g_pwmops,
+  .timid       = 3,
+  .channels    =
+  {
+#ifdef CONFIG_STM32F7_TIM3_CHANNEL1
+    {
+      .channel = 1,
+      .pincfg  = PWM_TIM3_CH1CFG,
+      .mode    = CONFIG_STM32F7_TIM3_CH1MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM3_CHANNEL2
+    {
+      .channel = 2,
+      .pincfg  = PWM_TIM3_CH2CFG,
+      .mode    = CONFIG_STM32F7_TIM3_CH2MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM3_CHANNEL3
+    {
+      .channel = 3,
+      .pincfg  = PWM_TIM3_CH3CFG,
+      .mode    = CONFIG_STM32F7_TIM3_CH3MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM3_CHANNEL4
+    {
+      .channel = 4,
+      .pincfg  = PWM_TIM3_CH4CFG,
+      .mode    = CONFIG_STM32F7_TIM3_CH4MODE,
+    },
+#endif
+  },
+  .timtype     = TIMTYPE_TIM3,
+  .mode        = CONFIG_STM32F7_TIM3_MODE,
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM3,
+#endif
+  .base        = STM32_TIM3_BASE,
+  .pclk        = TIMCLK_TIM3,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM4_PWM
+static struct stm32_pwmtimer_s g_pwm4dev =
+{
+  .ops         = &g_pwmops,
+  .timid       = 4,
+  .channels    =
+  {
+#ifdef CONFIG_STM32F7_TIM4_CHANNEL1
+    {
+      .channel = 1,
+      .pincfg  = PWM_TIM4_CH1CFG,
+      .mode    = CONFIG_STM32F7_TIM4_CH1MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM4_CHANNEL2
+    {
+      .channel = 2,
+      .pincfg  = PWM_TIM4_CH2CFG,
+      .mode    = CONFIG_STM32F7_TIM4_CH2MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM4_CHANNEL3
+    {
+      .channel = 3,
+      .pincfg  = PWM_TIM4_CH3CFG,
+      .mode    = CONFIG_STM32F7_TIM4_CH3MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM4_CHANNEL4
+    {
+      .channel = 4,
+      .pincfg  = PWM_TIM4_CH4CFG,
+      .mode    = CONFIG_STM32F7_TIM4_CH4MODE,
+    },
+#endif
+  },
+  .timtype     = TIMTYPE_TIM4,
+  .mode        = CONFIG_STM32F7_TIM4_MODE,
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM4,
+#endif
+  .base        = STM32_TIM4_BASE,
+  .pclk        = TIMCLK_TIM4,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM5_PWM
+static struct stm32_pwmtimer_s g_pwm5dev =
+{
+  .ops         = &g_pwmops,
+  .timid       = 5,
+  .channels    =
+  {
+#ifdef CONFIG_STM32F7_TIM5_CHANNEL1
+    {
+      .channel = 1,
+      .pincfg  = PWM_TIM5_CH1CFG,
+      .mode    = CONFIG_STM32F7_TIM5_CH1MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM5_CHANNEL2
+    {
+      .channel = 2,
+      .pincfg  = PWM_TIM5_CH2CFG,
+      .mode    = CONFIG_STM32F7_TIM5_CH2MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM5_CHANNEL3
+    {
+      .channel = 3,
+      .pincfg  = PWM_TIM5_CH3CFG,
+      .mode    = CONFIG_STM32F7_TIM5_CH3MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM5_CHANNEL4
+    {
+      .channel = 4,
+      .pincfg  = PWM_TIM5_CH4CFG,
+      .mode    = CONFIG_STM32F7_TIM5_CH4MODE,
+    },
+#endif
+  },
+  .timtype     = TIMTYPE_TIM5,
+  .mode        = CONFIG_STM32F7_TIM5_MODE,
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM5,
+#endif
+  .base        = STM32_TIM5_BASE,
+  .pclk        = TIMCLK_TIM5,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM8_PWM
+static struct stm32_pwmtimer_s g_pwm8dev =
+{
+  .ops         = &g_pwmops,
+  .timid       = 8,
+  .channels    =
+  {
+#ifdef CONFIG_STM32F7_TIM8_CHANNEL1
+    {
+      .channel = 1,
+      .pincfg  = PWM_TIM8_CH1CFG,
+      .mode    = CONFIG_STM32F7_TIM8_CH1MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM8_CHANNEL2
+    {
+      .channel = 2,
+      .pincfg  = PWM_TIM8_CH2CFG,
+      .mode    = CONFIG_STM32F7_TIM8_CH2MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM8_CHANNEL3
+    {
+      .channel = 3,
+      .pincfg  = PWM_TIM8_CH3CFG,
+      .mode    = CONFIG_STM32F7_TIM8_CH3MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM8_CHANNEL4
+    {
+      .channel = 4,
+      .pincfg  = PWM_TIM8_CH4CFG,
+      .mode    = CONFIG_STM32F7_TIM8_CH4MODE,
+    },
+#endif
+  },
+  .timtype     = TIMTYPE_TIM8,
+  .mode        = CONFIG_STM32F7_TIM8_MODE,
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM8UP,
+#endif
+  .base        = STM32_TIM8_BASE,
+  .pclk        = TIMCLK_TIM8,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM9_PWM
+static struct stm32_pwmtimer_s g_pwm9dev =
+{
+  .ops         = &g_pwmops,
+  .timid       = 9,
+  .channels    =
+  {
+#ifdef CONFIG_STM32F7_TIM9_CHANNEL1
+    {
+      .channel = 1,
+      .pincfg  = PWM_TIM9_CH1CFG,
+      .mode    = CONFIG_STM32F7_TIM9_CH1MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM9_CHANNEL2
+    {
+      .channel = 2,
+      .pincfg  = PWM_TIM9_CH2CFG,
+      .mode    = CONFIG_STM32F7_TIM9_CH2MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM9_CHANNEL3
+    {
+      .channel = 3,
+      .pincfg  = PWM_TIM9_CH3CFG,
+      .mode    = CONFIG_STM32F7_TIM9_CH3MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM9_CHANNEL4
+    {
+      .channel = 4,
+      .pincfg  = PWM_TIM9_CH4CFG,
+      .mode    = CONFIG_STM32F7_TIM9_CH4MODE,
+    },
+#endif
+  },
+  .timtype     = TIMTYPE_TIM9,
+  .mode        = STM32_TIMMODE_COUNTUP,
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM9,
+#endif
+  .base        = STM32_TIM9_BASE,
+  .pclk        = TIMCLK_TIM9,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM10_PWM
+static struct stm32_pwmtimer_s g_pwm10dev =
+{
+  .ops         = &g_pwmops,
+  .timid       = 10,
+  .channels    =
+  {
+#ifdef CONFIG_STM32F7_TIM10_CHANNEL1
+    {
+      .channel = 1,
+      .pincfg  = PWM_TIM10_CH1CFG,
+      .mode    = CONFIG_STM32F7_TIM10_CH1MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM10_CHANNEL2
+    {
+      .channel = 2,
+      .pincfg  = PWM_TIM10_CH2CFG,
+      .mode    = CONFIG_STM32F7_TIM10_CH2MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM10_CHANNEL3
+    {
+      .channel = 3,
+      .pincfg  = PWM_TIM10_CH3CFG,
+      .mode    = CONFIG_STM32F7_TIM10_CH3MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM10_CHANNEL4
+    {
+      .channel = 4,
+      .pincfg  = PWM_TIM10_CH4CFG,
+      .mode    = CONFIG_STM32F7_TIM10_CH4MODE,
+    },
+#endif
+  },
+  .timtype     = TIMTYPE_TIM10,
+  .mode        = STM32_TIMMODE_COUNTUP,
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM10,
+#endif
+  .base        = STM32_TIM10_BASE,
+  .pclk        = TIMCLK_TIM10,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM11_PWM
+static struct stm32_pwmtimer_s g_pwm11dev =
+{
+  .ops         = &g_pwmops,
+  .timid       = 11,
+  .channels    =
+  {
+#ifdef CONFIG_STM32F7_TIM11_CHANNEL1
+    {
+      .channel = 1,
+      .pincfg  = PWM_TIM11_CH1CFG,
+      .mode    = CONFIG_STM32F7_TIM11_CH1MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM11_CHANNEL2
+    {
+      .channel = 2,
+      .pincfg  = PWM_TIM11_CH2CFG,
+      .mode    = CONFIG_STM32F7_TIM11_CH2MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM11_CHANNEL3
+    {
+      .channel = 3,
+      .pincfg  = PWM_TIM11_CH3CFG,
+      .mode    = CONFIG_STM32F7_TIM11_CH3MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM11_CHANNEL4
+    {
+      .channel = 4,
+      .pincfg  = PWM_TIM11_CH4CFG,
+      .mode    = CONFIG_STM32F7_TIM11_CH4MODE,
+    },
+#endif
+  },
+  .timtype     = TIMTYPE_TIM11,
+  .mode        = STM32_TIMMODE_COUNTUP,
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM11,
+#endif
+  .base        = STM32_TIM11_BASE,
+  .pclk        = TIMCLK_TIM11,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM12_PWM
+static struct stm32_pwmtimer_s g_pwm12dev =
+{
+  .ops         = &g_pwmops,
+  .timid       = 12,
+  .channels    =
+  {
+#ifdef CONFIG_STM32F7_TIM12_CHANNEL1
+    {
+      .channel = 1,
+      .pincfg  = PWM_TIM12_CH1CFG,
+      .mode    = CONFIG_STM32F7_TIM12_CH1MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM12_CHANNEL2
+    {
+      .channel = 2,
+      .pincfg  = PWM_TIM12_CH2CFG,
+      .mode    = CONFIG_STM32F7_TIM12_CH2MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM12_CHANNEL3
+    {
+      .channel = 3,
+      .pincfg  = PWM_TIM12_CH3CFG,
+      .mode    = CONFIG_STM32F7_TIM12_CH3MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM12_CHANNEL4
+    {
+      .channel = 4,
+      .pincfg  = PWM_TIM12_CH4CFG,
+      .mode    = CONFIG_STM32F7_TIM12_CH4MODE,
+    },
+#endif
+  },
+  .timtype     = TIMTYPE_TIM12,
+  .mode        = STM32_TIMMODE_COUNTUP,
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM12,
+#endif
+  .base        = STM32_TIM12_BASE,
+  .pclk        = TIMCLK_TIM12,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM13_PWM
+static struct stm32_pwmtimer_s g_pwm13dev =
+{
+  .ops         = &g_pwmops,
+  .timid       = 13,
+  .channels    =
+  {
+#ifdef CONFIG_STM32F7_TIM13_CHANNEL1
+    {
+      .channel = 1,
+      .pincfg  = PWM_TIM13_CH1CFG,
+      .mode    = CONFIG_STM32F7_TIM13_CH1MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM13_CHANNEL2
+    {
+      .channel = 2,
+      .pincfg  = PWM_TIM13_CH2CFG,
+      .mode    = CONFIG_STM32F7_TIM13_CH2MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM13_CHANNEL3
+    {
+      .channel = 3,
+      .pincfg  = PWM_TIM13_CH3CFG,
+      .mode    = CONFIG_STM32F7_TIM13_CH3MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM13_CHANNEL4
+    {
+      .channel = 4,
+      .pincfg  = PWM_TIM13_CH4CFG,
+      .mode    = CONFIG_STM32F7_TIM13_CH4MODE,
+    },
+#endif
+  },
+  .timtype     = TIMTYPE_TIM13,
+  .mode        = STM32_TIMMODE_COUNTUP,
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM13,
+#endif
+  .base        = STM32_TIM13_BASE,
+  .pclk        = TIMCLK_TIM13,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM14_PWM
+static struct stm32_pwmtimer_s g_pwm14dev =
+{
+  .ops         = &g_pwmops,
+  .timid       = 14,
+  .channels    =
+  {
+#ifdef CONFIG_STM32F7_TIM14_CHANNEL1
+    {
+      .channel = 1,
+      .pincfg  = PWM_TIM14_CH1CFG,
+      .mode    = CONFIG_STM32F7_TIM14_CH1MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM14_CHANNEL2
+    {
+      .channel = 2,
+      .pincfg  = PWM_TIM14_CH2CFG,
+      .mode    = CONFIG_STM32F7_TIM14_CH2MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM14_CHANNEL3
+    {
+      .channel = 3,
+      .pincfg  = PWM_TIM14_CH3CFG,
+      .mode    = CONFIG_STM32F7_TIM14_CH3MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM14_CHANNEL4
+    {
+      .channel = 4,
+      .pincfg  = PWM_TIM14_CH4CFG,
+      .mode    = CONFIG_STM32F7_TIM14_CH4MODE,
+    },
+#endif
+  },
+  .timtype     = TIMTYPE_TIM14,
+  .mode        = STM32_TIMMODE_COUNTUP,
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM14,
+#endif
+  .base        = STM32_TIM14_BASE,
+  .pclk        = TIMCLK_TIM14,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM15_PWM
+static struct stm32_pwmtimer_s g_pwm15dev =
+{
+  .ops         = &g_pwmops,
+  .timid       = 15,
+  .channels    =
+  {
+#ifdef CONFIG_STM32F7_TIM15_CHANNEL1
+    {
+      .channel = 1,
+      .pincfg  = PWM_TIM15_CH1CFG,
+      .mode    = CONFIG_STM32F7_TIM15_CH1MODE,
+    },
+#endif
+#ifdef CONFIG_STM32F7_TIM15_CHANNEL2
+    {
+      .channel = 2,
+      .pincfg  = PWM_TIM15_CH2CFG,
+      .mode    = CONFIG_STM32F7_TIM15_CH2MODE,
+    },
+#endif
+  },
+  .timtype     = TIMTYPE_TIM15,
+  .mode        = STM32_TIMMODE_COUNTUP,
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM15,
+#endif
+  .base        = STM32_TIM15_BASE,
+  .pclk        = TIMCLK_TIM15,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM16_PWM
+static struct stm32_pwmtimer_s g_pwm16dev =
+{
+  .ops         = &g_pwmops,
+  .timid       = 16,
+  .channels    =
+  {
+#ifdef CONFIG_STM32F7_TIM16_CHANNEL1
+    {
+      .channel = 1,
+      .pincfg  = PWM_TIM16_CH1CFG,
+      .mode    = CONFIG_STM32F7_TIM16_CH1MODE,
+    },
+#endif
+  },
+  .timtype     = TIMTYPE_TIM16,
+  .mode        = STM32_TIMMODE_COUNTUP,
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM16,
+#endif
+  .base        = STM32_TIM16_BASE,
+  .pclk        = TIMCLK_TIM16,
+};
+#endif
+
+#ifdef CONFIG_STM32F7_TIM17_PWM
+static struct stm32_pwmtimer_s g_pwm17dev =
+{
+  .ops         = &g_pwmops,
+  .timid       = 17,
+  .channels    =
+  {
+#ifdef CONFIG_STM32F7_TIM17_CHANNEL1
+    {
+      .channel = 1,
+      .pincfg  = PWM_TIM17_CH1CFG,
+      .mode    = CONFIG_STM32F7_TIM17_CH1MODE,
+    },
+#endif
+  },
+  .timtype     = TIMTYPE_TIM17,
+  .mode        = STM32_TIMMODE_COUNTUP,
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM17,
+#endif
+  .base        = STM32_TIM17_BASE,
+  .pclk        = TIMCLK_TIM17,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: pwm_getreg
+ *
+ * Description:
+ *   Read the value of an PWM timer register.
+ *
+ * Input Parameters:
+ *   priv - A reference to the PWM block status
+ *   offset - The offset to the register to read
+ *
+ * Returned Value:
+ *   The current contents of the specified register
+ *
+ ****************************************************************************/
+
+static uint16_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset)
+{
+  return getreg16(priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: pwm_putreg
+ *
+ * Description:
+ *   Read the value of an PWM timer register.
+ *
+ * Input Parameters:
+ *   priv - A reference to the PWM block status
+ *   offset - The offset to the register to read
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset,
+                       uint16_t value)
+{
+  if (priv->timtype == TIMTYPE_GENERAL32 &&
+      (offset == STM32_GTIM_CNT_OFFSET ||
+       offset == STM32_GTIM_ARR_OFFSET ||
+       offset == STM32_GTIM_CCR1_OFFSET ||
+       offset == STM32_GTIM_CCR2_OFFSET ||
+       offset == STM32_GTIM_CCR3_OFFSET ||
+       offset == STM32_GTIM_CCR4_OFFSET))
+    {
+      /* a 32 bit access is required for a 32 bit register:
+       * if only a 16 bit write would be performed, then the
+       * upper 16 bits of the 32 bit register will be a copy of
+       * the lower 16 bits.
+       */
+
+      putreg32(value, priv->base + offset);
+    }
+  else
+    {
+      putreg16(value, priv->base + offset);
+    }
+}
+
+/****************************************************************************
+ * Name: pwm_dumpregs
+ *
+ * Description:
+ *   Dump all timer registers.
+ *
+ * Input Parameters:
+ *   priv - A reference to the PWM block status
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_PWM_INFO
+static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg)
+{
+  pwminfo("%s:\n", msg);
+  if (priv->timid == 16 || priv->timid == 17)
+    {
+      pwminfo("  CR1: %04x CR2:  %04x DIER:  %04x\n",
+              pwm_getreg(priv, STM32_GTIM_CR1_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CR2_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_DIER_OFFSET));
+    }
+  else
+    {
+      pwminfo("  CR1: %04x CR2:  %04x SMCR:  %04x DIER:  %04x\n",
+              pwm_getreg(priv, STM32_GTIM_CR1_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CR2_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_DIER_OFFSET));
+    }
+
+  if (priv->timid >= 15 || priv->timid <= 17)
+    {
+      pwminfo("   SR: %04x EGR:  %04x CCMR1: %04x\n",
+              pwm_getreg(priv, STM32_GTIM_SR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_EGR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET));
+    }
+   else
+    {
+      pwminfo("   SR: %04x EGR:  %04x CCMR1: %04x CCMR2: %04x\n",
+              pwm_getreg(priv, STM32_GTIM_SR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_EGR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
+    }
+
+  /* REVISIT: CNT and ARR may be 32-bits wide */
+
+  pwminfo(" CCER: %04x CNT:  %04x PSC:   %04x ARR:   %04x\n",
+          pwm_getreg(priv, STM32_GTIM_CCER_OFFSET),
+          pwm_getreg(priv, STM32_GTIM_CNT_OFFSET),
+          pwm_getreg(priv, STM32_GTIM_PSC_OFFSET),
+          pwm_getreg(priv, STM32_GTIM_ARR_OFFSET));
+
+  if (priv->timid >= 15 || priv->timid <= 17)
+    {
+      pwminfo("  RCR: %04x BDTR: %04x\n",
+          pwm_getreg(priv, STM32_ATIM_RCR_OFFSET),
+          pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET));
+    }
+
+  /* REVISIT: CCR1-CCR4 may be 32-bits wide */
+
+  if (priv->timid == 16 || priv->timid == 17)
+    {
+      pwminfo(" CCR1: %04x\n",
+              pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET));
+    }
+  else
+    {
+      pwminfo(" CCR1: %04x CCR2: %04x CCR3:  %04x CCR4:  %04x\n",
+              pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET));
+    }
+
+  pwminfo("  DCR: %04x DMAR: %04x\n",
+      pwm_getreg(priv, STM32_GTIM_DCR_OFFSET),
+      pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET));
+}
+#endif
+
+/****************************************************************************
+ * Name: pwm_timer
+ *
+ * Description:
+ *   (Re-)initialize the timer resources and start the pulsed output
+ *
+ * Input Parameters:
+ *   priv - A reference to the lower half PWM driver state structure
+ *   info - A reference to the characteristics of the pulsed output
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_timer(FAR struct stm32_pwmtimer_s *priv,
+                     FAR const struct pwm_info_s *info)
+{
+#ifdef CONFIG_PWM_MULTICHAN
+  int      i;
+#endif
+
+  /* Calculated values */
+
+  uint32_t prescaler;
+  uint32_t timclk;
+  uint32_t reload;
+  uint32_t ccr;
+
+  /* Register contents */
+
+  uint16_t cr1;
+  uint16_t ccer;
+  uint16_t cr2;
+  uint16_t ccmr1;
+  uint16_t ccmr2;
+
+  /* New timer regiser bit settings */
+
+  uint16_t ccenable;
+  uint16_t ocmode1;
+  uint16_t ocmode2;
+
+  DEBUGASSERT(priv != NULL && info != NULL);
+
+#if defined(CONFIG_PWM_MULTICHAN)
+  pwminfo("TIM%u frequency: %u\n",
+          priv->timid, info->frequency);
+#elif defined(CONFIG_PWM_PULSECOUNT)
+  pwminfo("TIM%u channel: %u frequency: %u duty: %08x count: %u\n",
+          priv->timid, priv->channels[0].channel, info->frequency,
+          info->duty, info->count);
+#else
+  pwminfo("TIM%u channel: %u frequency: %u duty: %08x\n",
+          priv->timid, priv->channels[0].channel, info->frequency,
+          info->duty);
+#endif
+
+  DEBUGASSERT(info->frequency > 0);
+#ifndef CONFIG_PWM_MULTICHAN
+  DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100));
+#endif
+
+  /* Disable all interrupts and DMA requests, clear all pending status */
+
+#ifdef CONFIG_PWM_PULSECOUNT
+  pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0);
+  pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0);
+#endif
+
+  /* Calculate optimal values for the timer prescaler and for the timer reload
+   * register.  If 'frequency' is the desired frequency, then
+   *
+   *   reload = timclk / frequency
+   *   timclk = pclk / presc
+   *
+   * Or,
+   *
+   *   reload = pclk / presc / frequency
+   *
+   * There are many solutions to this this, but the best solution will be the
+   * one that has the largest reload value and the smallest prescaler value.
+   * That is the solution that should give us the most accuracy in the timer
+   * control.  Subject to:
+   *
+   *   0 <= presc  <= 65536
+   *   1 <= reload <= 65535
+   *
+   * So presc = pclk / 65535 / frequency would be optimal.
+   *
+   * Example:
+   *
+   *  pclk      = 42 MHz
+   *  frequency = 100 Hz
+   *
+   *  prescaler = 42,000,000 / 65,535 / 100
+   *            = 6.4 (or 7 -- taking the ceiling always)
+   *  timclk    = 42,000,000 / 7
+   *            = 6,000,000
+   *  reload    = 6,000,000 / 100
+   *            = 60,000
+   */
+
+  prescaler = (priv->pclk / info->frequency + 65534) / 65535;
+  if (prescaler < 1)
+    {
+      prescaler = 1;
+    }
+  else if (prescaler > 65536)
+    {
+      prescaler = 65536;
+    }
+
+  timclk = priv->pclk / prescaler;
+
+  reload = timclk / info->frequency;
+  if (reload < 2)
+    {
+      reload = 1;
+    }
+  else if (reload > 65535)
+    {
+      reload = 65535;
+    }
+  else
+    {
+      reload--;
+    }
+
+  pwminfo("TIM%u PCLK: %u frequency: %u TIMCLK: %u prescaler: %u reload: %u\n",
+          priv->timid, priv->pclk, info->frequency, timclk, prescaler, reload);
+
+  /* Set up the timer CR1 register:
+   *
+   * 1,8   CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN
+   * 2-5   CKD[1:0] ARPE CMS      DIR OPM URS UDIS CEN
+   * 6-7            ARPE              OPM URS UDIS CEN
+   * 9-14  CKD[1:0] ARPE                  URS UDIS CEN
+   * 15-17 CKD[1:0] ARPE              OPM URS UDIS CEN
+   */
+
+  cr1 = pwm_getreg(priv, STM32_GTIM_CR1_OFFSET);
+
+  /* Disable the timer until we get it configured */
+
+  cr1 &= ~GTIM_CR1_CEN;
+
+  /* Set the counter mode for the advanced timers (1,8) and most general
+   * purpose timers (all 2-5, but not 9-17), i.e., all but TIMTYPE_COUNTUP16
+   * and TIMTYPE_BASIC
+   */
+
+#if defined(CONFIG_STM32F7_TIM1_PWM) || defined(CONFIG_STM32F7_TIM2_PWM) || \
+    defined(CONFIG_STM32F7_TIM3_PWM) || defined(CONFIG_STM32F7_TIM4_PWM) || \
+    defined(CONFIG_STM32F7_TIM5_PWM) || defined(CONFIG_STM32F7_TIM8_PWM)
+
+  if (priv->timtype != TIMTYPE_BASIC && priv->timtype != TIMTYPE_COUNTUP16)
+    {
+      /* Select the Counter Mode:
+       *
+       * GTIM_CR1_EDGE: The counter counts up or down depending on the
+       *   direction bit (DIR).
+       * GTIM_CR1_CENTER1, GTIM_CR1_CENTER2, GTIM_CR1_CENTER3: The counter
+       *   counts up then down.
+       * GTIM_CR1_DIR: 0: count up, 1: count down
+       */
+
+      cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK);
+
+      switch (priv->mode)
+        {
+          case STM32_TIMMODE_COUNTUP:
+            cr1 |= GTIM_CR1_EDGE;
+            break;
+
+          case STM32_TIMMODE_COUNTDOWN:
+            cr1 |= GTIM_CR1_EDGE | GTIM_CR1_DIR;
+            break;
+
+          case STM32_TIMMODE_CENTER1:
+            cr1 |= GTIM_CR1_CENTER1;
+            break;
+
+          case STM32_TIMMODE_CENTER2:
+            cr1 |= GTIM_CR1_CENTER2;
+            break;
+
+          case STM32_TIMMODE_CENTER3:
+            cr1 |= GTIM_CR1_CENTER3;
+            break;
+
+          default:
+            pwmerr("ERROR: No such timer mode: %u\n",
+                   (unsigned int)priv->mode);
+            return -EINVAL;
+        }
+    }
+#endif
+
+  /* Set the clock division to zero for all (but the basic timers, but there
+   * should be no basic timers in this context
+   */
+
+  cr1 &= ~GTIM_CR1_CKD_MASK;
+  pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1);
+
+  /* Set the reload and prescaler values */
+
+  pwm_putreg(priv, STM32_GTIM_ARR_OFFSET, (uint16_t)reload);
+  pwm_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1));
+
+  /* Set the advanced timer's repetition counter */
+
+#if defined(CONFIG_STM32F7_TIM1_PWM) || defined(CONFIG_STM32F7_TIM8_PWM)
+  if (priv->timtype == TIMTYPE_ADVANCED)
+    {
+      /* If a non-zero repetition count has been selected, then set the
+       * repitition counter to the count-1 (pwm_start() has already
+       * assured us that the count value is within range).
+       */
+
+#ifdef CONFIG_PWM_PULSECOUNT
+      if (info->count > 0)
+        {
+          /* Save the remaining count and the number of counts that will have
+           * elapsed on the first interrupt.
+           */
+
+          /* If the first interrupt occurs at the end end of the first
+           * repetition count, then the count will be the same as the RCR
+           * value.
+           */
+
+          priv->prev  = pwm_pulsecount(info->count);
+          pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->prev - 1);
+
+          /* Generate an update event to reload the prescaler.  This should
+           * preload the RCR into active repetition counter.
+           */
+
+          pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, ATIM_EGR_UG);
+
+          /* Now set the value of the RCR that will be loaded on the next
+           * update event.
+           */
+
+          priv->count = info->count;
+          priv->curr  = pwm_pulsecount(info->count - priv->prev);
+          pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->curr - 1);
+        }
+
+      /* Otherwise, just clear the repetition counter */
+
+      else
+#endif
+        {
+          /* Set the repetition counter to zero */
+
+          pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, 0);
+
+          /* Generate an update event to reload the prescaler */
+
+          pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, ATIM_EGR_UG);
+        }
+    }
+  else
+#endif
+    {
+      /* Generate an update event to reload the prescaler (all timers) */
+
+      pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, ATIM_EGR_UG);
+    }
+
+  /* Handle channel specific setup */
+
+  ccenable = 0;
+  ocmode1  = 0;
+  ocmode2  = 0;
+
+#ifdef CONFIG_PWM_MULTICHAN
+  for (i = 0; i < CONFIG_PWM_NCHANNELS; i++)
+#endif
+    {
+      ub16_t                duty;
+      uint16_t              chanmode;
+      uint8_t               channel;
+#ifdef CONFIG_PWM_MULTICHAN
+      int                   j;
+#endif
+      enum stm32_chanmode_e mode;
+
+#ifdef CONFIG_PWM_MULTICHAN
+      duty = info->channels[i].duty;
+      channel = info->channels[i].channel;
+
+      /* A value of zero means to skip this channel */
+
+      if (channel == 0)
+        {
+          continue;
+        }
+
+      /* Find the channel */
+
+      for (j = 0; j < PWM_NCHANNELS; j++)
+        {
+          if (priv->channels[j].channel == channel)
+            {
+              mode = priv->channels[j].mode;
+              break;
+            }
+        }
+
+      if (j >= PWM_NCHANNELS)
+        {
+          pwmerr("ERROR: No such channel: %u\n", channel);
+          return -EINVAL;
+        }
+#else
+      duty = info->duty;
+      channel = priv->channels[0].channel;
+      mode = priv->channels[0].mode;
+#endif
+
+      /* Duty cycle:
+       *
+       * duty cycle = ccr / reload (fractional value)
+       */
+
+      ccr = b16toi(duty * reload + b16HALF);
+
+      pwminfo("ccr: %u\n", ccr);
+
+      switch (mode)
+        {
+          case STM32_CHANMODE_PWM1:
+            chanmode = ATIM_CCMR_MODE_PWM1;
+            break;
+
+          case STM32_CHANMODE_PWM2:
+            chanmode = ATIM_CCMR_MODE_PWM2;
+            break;
+
+          default:
+            pwmerr("ERROR: No such mode: %u\n", (unsigned int)mode);
+            return -EINVAL;
+        }
+
+      switch (channel)
+        {
+          case 1:  /* PWM Mode configuration: Channel 1 */
+            {
+              /* Select the CCER enable bit for this channel */
+
+              ccenable |= ATIM_CCER_CC1E;
+
+              /* Set the CCMR1 mode values (leave CCMR2 zero) */
+
+              ocmode1  |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) |
+                          (chanmode << ATIM_CCMR1_OC1M_SHIFT) |
+                          ATIM_CCMR1_OC1PE;
+
+              /* Set the duty cycle by writing to the CCR register for this channel */
+
+              pwm_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)ccr);
+            }
+            break;
+
+          case 2:  /* PWM Mode configuration: Channel 2 */
+            {
+              /* Select the CCER enable bit for this channel */
+
+              ccenable |= ATIM_CCER_CC2E;
+
+              /* Set the CCMR1 mode values (leave CCMR2 zero) */
+
+              ocmode1  |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT) |
+                          (chanmode << ATIM_CCMR1_OC2M_SHIFT) |
+                          ATIM_CCMR1_OC2PE;
+
+              /* Set the duty cycle by writing to the CCR register for this channel */
+
+              pwm_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)ccr);
+            }
+            break;
+
+          case 3:  /* PWM Mode configuration: Channel 3 */
+            {
+              /* Select the CCER enable bit for this channel */
+
+              ccenable |= ATIM_CCER_CC3E;
+
+              /* Set the CCMR2 mode values (leave CCMR1 zero) */
+
+              ocmode2  |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC3S_SHIFT) |
+                          (chanmode << ATIM_CCMR2_OC3M_SHIFT) |
+                          ATIM_CCMR2_OC3PE;
+
+              /* Set the duty cycle by writing to the CCR register for this channel */
+
+              pwm_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)ccr);
+            }
+            break;
+
+          case 4:  /* PWM Mode configuration: Channel 4 */
+            {
+              /* Select the CCER enable bit for this channel */
+
+              ccenable |= ATIM_CCER_CC4E;
+
+              /* Set the CCMR2 mode values (leave CCMR1 zero) */
+
+              ocmode2  |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR2_CC4S_SHIFT) |
+                          (chanmode << ATIM_CCMR2_OC4M_SHIFT) |
+                          ATIM_CCMR2_OC4PE;
+
+              /* Set the duty cycle by writing to the CCR register for this channel */
+
+              pwm_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)ccr);
+            }
+            break;
+
+          default:
+            pwmerr("ERROR: No such channel: %u\n", channel);
+            return -EINVAL;
+        }
+    }
+
+  /* Disable the Channel by resetting the CCxE Bit in the CCER register */
+
+  ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET);
+  ccer &= ~ccenable;
+  pwm_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer);
+
+  /* Fetch the CR2, CCMR1, and CCMR2 register (already have cr1 and ccer) */
+
+  cr2   = pwm_getreg(priv, STM32_GTIM_CR2_OFFSET);
+  ccmr1 = pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET);
+  ccmr2 = pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET);
+
+  /* Reset the Output Compare Mode Bits and set the select output compare mode */
+
+  ccmr1 &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK | ATIM_CCMR1_OC1PE |
+             ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK | ATIM_CCMR1_OC2PE);
+  ccmr2 &= ~(ATIM_CCMR2_CC3S_MASK | ATIM_CCMR2_OC3M_MASK | ATIM_CCMR2_OC3PE |
+             ATIM_CCMR2_CC4S_MASK | ATIM_CCMR2_OC4M_MASK | ATIM_CCMR2_OC4PE);
+  ccmr1 |= ocmode1;
+  ccmr2 |= ocmode2;
+
+  /* Reset the output polarity level of all channels (selects high polarity) */
+
+  ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | ATIM_CCER_CC3P |
+            ATIM_CCER_CC4P);
+
+  /* Enable the output state of the selected channels */
+
+  ccer &= ~(ATIM_CCER_CC1E | ATIM_CCER_CC2E | ATIM_CCER_CC3E |
+            ATIM_CCER_CC4E);
+  ccer |= ccenable;
+
+  /* Some special setup for advanced timers */
+
+#if defined(CONFIG_STM32F7_TIM1_PWM) || defined(CONFIG_STM32F7_TIM8_PWM) || \
+    defined(CONFIG_STM32F7_TIM15_PWM) || defined(CONFIG_STM32F7_TIM16_PWM) || \
+    defined(CONFIG_STM32F7_TIM17_PWM)
+  if (priv->timtype == TIMTYPE_ADVANCED || priv->timtype == TIMTYPE_COUNTUP16)
+    {
+      uint16_t bdtr;
+
+      /* Reset output N polarity level, output N state, output compare state,
+       * output compare N idle state.
+       */
+
+      ccer &= ~(ATIM_CCER_CC1NE | ATIM_CCER_CC1NP | ATIM_CCER_CC2NE |
+                ATIM_CCER_CC2NP | ATIM_CCER_CC3NE | ATIM_CCER_CC3NP |
+                ATIM_CCER_CC4NP);
+
+      /* Reset the output compare and output compare N IDLE State */
+
+      cr2 &= ~(ATIM_CR2_OIS1 | ATIM_CR2_OIS1N | ATIM_CR2_OIS2 |
+               ATIM_CR2_OIS2N | ATIM_CR2_OIS3 | ATIM_CR2_OIS3N |
+               ATIM_CR2_OIS4);
+
+      /* Set the main output enable (MOE) bit and clear the OSSI and OSSR
+       * bits in the BDTR register.
+       */
+
+      bdtr  = pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET);
+      bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR);
+      bdtr |= ATIM_BDTR_MOE;
+      pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr);
+    }
+  else
+#endif
+    {
+      /* CCxNP must be cleared in any case */
+
+      ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP |
+                GTIM_CCER_CC4NP);
+    }
+
+  /* Save the modified register values */
+
+  pwm_putreg(priv, STM32_GTIM_CR2_OFFSET, cr2);
+  pwm_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1);
+  pwm_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2);
+  pwm_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer);
+
+  /* Set the ARR Preload Bit */
+
+  cr1 = pwm_getreg(priv, STM32_GTIM_CR1_OFFSET);
+  cr1 |= GTIM_CR1_ARPE;
+  pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1);
+
+  /* Setup update interrupt.  If info->count is > 0, then we can be
+   * assured that pwm_start() has already verified: (1) that this is an
+   * advanced timer, and that (2) the repetition count is within range.
+   */
+
+#ifdef CONFIG_PWM_PULSECOUNT
+  if (info->count > 0)
+    {
+      /* Clear all pending interrupts and enable the update interrupt. */
+
+      pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0);
+      pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, ATIM_DIER_UIE);
+
+      /* Enable the timer */
+
+      cr1 |= GTIM_CR1_CEN;
+      pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1);
+
+      /* And enable timer interrupts at the NVIC */
+
+      up_enable_irq(priv->irq);
+    }
+  else
+#endif
+    {
+      /* Just enable the timer, leaving all interrupts disabled */
+
+      cr1 |= GTIM_CR1_CEN;
+      pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1);
+    }
+
+  pwm_dumpregs(priv, "After starting");
+  return OK;
+}
+
+#ifndef CONFIG_PWM_PULSECOUNT
+/****************************************************************************
+ * Name: pwm_update_duty
+ *
+ * Description:
+ *   Try to change only channel duty.
+ *
+ * Input Parameters:
+ *   priv    - A reference to the lower half PWM driver state structure
+ *   channel - Channel to by updated
+ *   duty    - New duty.
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static  int pwm_update_duty(FAR struct stm32_pwmtimer_s *priv,
+                            uint8_t channel, ub16_t duty)
+{
+  /* Register offset */
+
+  int ccr_offset;
+
+  /* Calculated values */
+
+  uint32_t reload;
+  uint32_t ccr;
+
+  DEBUGASSERT(priv != NULL);
+
+  pwminfo("TIM%u channel: %u duty: %08x\n",
+          priv->timid, channel, duty);
+
+#ifndef CONFIG_PWM_MULTICHAN
+  DEBUGASSERT(channel == priv->channels[0].channel);
+  DEBUGASSERT(duty >= 0 && duty < uitoub16(100));
+#endif
+
+  /* Get the reload values */
+
+  reload = pwm_getreg(priv, STM32_GTIM_ARR_OFFSET);
+
+  /* Duty cycle:
+   *
+   * duty cycle = ccr / reload (fractional value)
+   */
+
+  ccr = b16toi(duty * reload + b16HALF);
+
+  pwminfo("ccr: %u\n", ccr);
+
+  switch (channel)
+    {
+      case 1:  /* Register offset for Channel 1 */
+        ccr_offset = STM32_GTIM_CCR1_OFFSET;
+        break;
+
+      case 2:  /* Register offset for Channel 2 */
+        ccr_offset = STM32_GTIM_CCR2_OFFSET;
+        break;
+
+      case 3:  /* Register offset for Channel 3 */
+        ccr_offset = STM32_GTIM_CCR3_OFFSET;
+        break;
+
+      case 4:  /* Register offset for Channel 4 */
+        ccr_offset = STM32_GTIM_CCR4_OFFSET;
+        break;
+
+      default:
+        pwmerr("ERROR: No such channel: %u\n", channel);
+        return -EINVAL;
+    }
+
+  /* Set the duty cycle by writing to the CCR register for this channel */
+
+  pwm_putreg(priv, ccr_offset, (uint16_t)ccr);
+
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: pwm_interrupt
+ *
+ * Description:
+ *   Handle timer interrupts.
+ *
+ * Input Parameters:
+ *   priv - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_PWM_PULSECOUNT) && (defined(CONFIG_STM32F7_TIM1_PWM) || defined(CONFIG_STM32F7_TIM8_PWM))
+static int pwm_interrupt(struct stm32_pwmtimer_s *priv)
+{
+  uint16_t regval;
+
+  /* Verify that this is an update interrupt.  Nothing else is expected. */
+
+  regval = pwm_getreg(priv, STM32_ATIM_SR_OFFSET);
+  DEBUGASSERT((regval & ATIM_SR_UIF) != 0);
+
+  /* Clear the UIF interrupt bit */
+
+  pwm_putreg(priv, STM32_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF);
+
+  /* Calculate the new count by subtracting the number of pulses
+   * since the last interrupt.
+   */
+
+  if (priv->count <= priv->prev)
+    {
+      /* We are finished.  Turn off the mast output to stop the output as
+       * quickly as possible.
+       */
+
+      regval  = pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET);
+      regval &= ~ATIM_BDTR_MOE;
+      pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, regval);
+
+      /* Disable first interrtups, stop and reset the timer */
+
+      (void)pwm_stop((FAR struct pwm_lowerhalf_s *)priv);
+
+      /* Then perform the callback into the upper half driver */
+
+      pwm_expired(priv->handle);
+
+      priv->handle = NULL;
+      priv->count  = 0;
+      priv->prev   = 0;
+      priv->curr   = 0;
+    }
+  else
+    {
+      /* Decrement the count of pulses remaining using the number of
+       * pulses generated since the last interrupt.
+       */
+
+      priv->count -= priv->prev;
+
+      /* Set up the next RCR.  Set 'prev' to the value of the RCR that
+       * was loaded when the update occurred (just before this interrupt)
+       * and set 'curr' to the current value of the RCR register (which
+       * will bet loaded on the next update event).
+       */
+
+      priv->prev = priv->curr;
+      priv->curr = pwm_pulsecount(priv->count - priv->prev);
+      pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->curr - 1);
+    }
+
+  /* Now all of the time critical stuff is done so we can do some debug output */
+
+  pwminfo("Update interrupt SR: %04x prev: %u curr: %u count: %u\n",
+          regval, priv->prev, priv->curr, priv->count);
+
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: pwm_tim1/8interrupt
+ *
+ * Description:
+ *   Handle timer 1 and 8 interrupts.
+ *
+ * Input Parameters:
+ *   Standard NuttX interrupt inputs
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_STM32F7_TIM1_PWM)
+static int pwm_tim1interrupt(int irq, void *context, FAR void *arg)
+{
+  return pwm_interrupt(&g_pwm1dev);
+}
+#endif
+
+#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_STM32F7_TIM8_PWM)
+static int pwm_tim8interrupt(int irq, void *context, FAR void *arg)
+{
+  return pwm_interrupt(&g_pwm8dev);
+}
+#endif
+
+/****************************************************************************
+ * Name: pwm_pulsecount
+ *
+ * Description:
+ *   Pick an optimal pulse count to program the RCR.
+ *
+ * Input Parameters:
+ *   count - The total count remaining
+ *
+ * Returned Value:
+ *   The recommended pulse count
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_PWM_PULSECOUNT) && (defined(CONFIG_STM32F7_TIM1_PWM) || defined(CONFIG_STM32F7_TIM8_PWM))
+static uint8_t pwm_pulsecount(uint32_t count)
+{
+  /* The the remaining pulse count is less than or equal to the maximum, the
+   * just return the count.
+   */
+
+  if (count <= ATIM_RCR_REP_MAX)
+    {
+      return count;
+    }
+
+  /* Otherwise, we have to be careful.  We do not want a small number of
+   * counts at the end because we might have trouble responding fast enough.
+   * If the remaining count is less than 150% of the maximum, then return
+   * half of the maximum.  In this case the final sequence will be between 64
+   * and 128.
+   */
+
+  else if (count < (3 * ATIM_RCR_REP_MAX / 2))
+    {
+      return (ATIM_RCR_REP_MAX + 1) >> 1;
+    }
+
+  /* Otherwise, return the maximum.  The final count will be 64 or more */
+
+  else
+    {
+      return ATIM_RCR_REP_MAX;
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: pwm_set_apb_clock
+ *
+ * Description:
+ *   Enable or disable APB clock for the timer peripheral
+ *
+ * Input Parameters:
+ *   dev - A reference to the lower half PWM driver state structure
+ *   on  - Enable clock if 'on' is 'true' and disable if 'false'
+ *
+ ****************************************************************************/
+
+static void pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on)
+{
+  uint32_t en_bit;
+  uint32_t regaddr;
+
+  pwminfo("timer %d clock enable: %d\n", priv->timid, on ? 1 : 0);
+
+  /* Determine which timer to configure */
+
+  switch (priv->timid)
+    {
+#ifdef CONFIG_STM32F7_TIM1_PWM
+      case 1:
+        regaddr  = TIMRCCEN_TIM1;
+        en_bit   = TIMEN_TIM1;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM2_PWM
+      case 2:
+        regaddr  = TIMRCCEN_TIM2;
+        en_bit   = TIMEN_TIM2;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM3_PWM
+      case 3:
+        regaddr  = TIMRCCEN_TIM3;
+        en_bit   = TIMEN_TIM3;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM4_PWM
+      case 4:
+        regaddr  = TIMRCCEN_TIM4;
+        en_bit   = TIMEN_TIM4;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM5_PWM
+      case 5:
+        regaddr  = TIMRCCEN_TIM5;
+        en_bit   = TIMEN_TIM5;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM8_PWM
+      case 8:
+        regaddr  = TIMRCCEN_TIM8;
+        en_bit   = TIMEN_TIM8;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM9_PWM
+      case 9:
+        regaddr  = TIMRCCEN_TIM9;
+        en_bit   = TIMEN_TIM9;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM10_PWM
+      case 10:
+        regaddr  = TIMRCCEN_TIM10;
+        en_bit   = TIMEN_TIM10;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM11_PWM
+      case 11:
+        regaddr  = TIMRCCEN_TIM11;
+        en_bit   = TIMEN_TIM11;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM12_PWM
+      case 12:
+        regaddr  = TIMRCCEN_TIM12;
+        en_bit   = TIMEN_TIM12;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM13_PWM
+      case 13:
+        regaddr  = TIMRCCEN_TIM13;
+        en_bit   = TIMEN_TIM13;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM14_PWM
+      case 14:
+        regaddr  = TIMRCCEN_TIM14;
+        en_bit   = TIMEN_TIM14;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM15_PWM
+      case 15:
+        regaddr  = TIMRCCEN_TIM15;
+        en_bit   = TIMEN_TIM15;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM16_PWM
+      case 16:
+        regaddr  = TIMRCCEN_TIM16;
+        en_bit   = TIMEN_TIM16;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM17_PWM
+      case 17:
+        regaddr  = TIMRCCEN_TIM17;
+        en_bit   = TIMEN_TIM17;
+        break;
+#endif
+      default:
+        return;
+    }
+
+  /* Enable/disable APB 1/2 clock for timer */
+
+  pwminfo("RCC_APBxENR base: %08x  bits: %04x\n", regaddr, en_bit);
+
+  if (on)
+    {
+      modifyreg32(regaddr, 0, en_bit);
+    }
+  else
+    {
+      modifyreg32(regaddr, en_bit, 0);
+    }
+}
+
+/****************************************************************************
+ * Name: pwm_setup
+ *
+ * Description:
+ *   This method is called when the driver is opened.  The lower half driver
+ *   should configure and initialize the device so that it is ready for use.
+ *   It should not, however, output pulses until the start method is called.
+ *
+ * Input Parameters:
+ *   dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ * Assumptions:
+ *   APB1 or 2 clocking for the GPIOs has already been configured by the RCC
+ *   logic at power up.
+ *
+ ****************************************************************************/
+
+static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint32_t pincfg;
+  int i;
+
+  pwminfo("TIM%u\n", priv->timid);
+
+  /* Enable APB1/2 clocking for timer. */
+
+  pwm_set_apb_clock(priv, true);
+
+  pwm_dumpregs(priv, "Initially");
+
+  /* Configure the PWM output pins, but do not start the timer yet */
+
+  for (i = 0; i < PWM_NCHANNELS; i++)
+    {
+      pincfg = priv->channels[i].pincfg;
+      if (pincfg == 0)
+        {
+          continue;
+        }
+
+      pwminfo("pincfg: %08x\n", pincfg);
+
+      stm32_configgpio(pincfg);
+      pwm_dumpgpio(pincfg, "PWM setup");
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_shutdown
+ *
+ * Description:
+ *   This method is called when the driver is closed.  The lower half driver
+ *   stop pulsed output, free any resources, disable the timer hardware, and
+ *   put the system into the lowest possible power usage state
+ *
+ * Input Parameters:
+ *   dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint32_t pincfg;
+  int i;
+
+  pwminfo("TIM%u\n", priv->timid);
+
+  /* Make sure that the output has been stopped */
+
+  pwm_stop(dev);
+
+  /* Disable APB1/2 clocking for timer. */
+
+  pwm_set_apb_clock(priv, false);
+
+  /* Then put the GPIO pins back to the default state */
+
+  for (i = 0; i < PWM_NCHANNELS; i++)
+    {
+      pincfg = priv->channels[i].pincfg;
+      if (pincfg == 0)
+        {
+          continue;
+        }
+
+      pwminfo("pincfg: %08x\n", pincfg);
+
+      pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK);
+      pincfg |= GPIO_INPUT | GPIO_FLOAT;
+
+      stm32_configgpio(pincfg);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_start
+ *
+ * Description:
+ *   (Re-)initialize the timer resources and start the pulsed output
+ *
+ * Input Parameters:
+ *   dev - A reference to the lower half PWM driver state structure
+ *   info - A reference to the characteristics of the pulsed output
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PWM_PULSECOUNT
+static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
+                     FAR const struct pwm_info_s *info,
+                     FAR void *handle)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+
+  /* Check if a pulsecount has been selected */
+
+  if (info->count > 0)
+    {
+      /* Only the advanced timers (TIM1,8 can support the pulse counting) */
+
+      if (priv->timtype != TIMTYPE_ADVANCED)
+        {
+          pwmerr("ERROR: TIM%u cannot support pulse count: %u\n",
+                 priv->timid, info->count);
+          return -EPERM;
+        }
+    }
+
+  /* Save the handle */
+
+  priv->handle = handle;
+
+  /* Start the time */
+
+  return pwm_timer(priv, info);
+}
+#else
+static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
+                     FAR const struct pwm_info_s *info)
+{
+  int ret = OK;
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+
+#ifndef CONFIG_PWM_PULSECOUNT
+  /* if frequency has not changed we just update duty */
+
+  if (info->frequency == priv->frequency)
+    {
+#ifdef CONFIG_PWM_MULTICHAN
+      int i;
+
+      for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++)
+        {
+          ret = pwm_update_duty(priv, info->channels[i].channel,
+                                info->channels[i].duty);
+        }
+#else
+      ret = pwm_update_duty(priv, priv->channels[0].channel,
+                            info->duty);
+#endif
+    }
+  else
+#endif
+    {
+      ret = pwm_timer(priv, info);
+
+#ifndef CONFIG_PWM_PULSECOUNT
+      /* Save current frequency */
+
+      if (ret == OK)
+        {
+          priv->frequency = info->frequency;
+        }
+#endif
+    }
+
+  return ret;
+}
+#endif
+
+/****************************************************************************
+ * Name: pwm_stop
+ *
+ * Description:
+ *   Stop the pulsed output and reset the timer resources
+ *
+ * Input Parameters:
+ *   dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ * Assumptions:
+ *   This function is called to stop the pulsed output at anytime.  This
+ *   method is also called from the timer interrupt handler when a repetition
+ *   count expires... automatically stopping the timer.
+ *
+ ****************************************************************************/
+
+static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint32_t resetbit;
+  uint32_t regaddr;
+  uint32_t regval;
+  irqstate_t flags;
+
+  pwminfo("TIM%u\n", priv->timid);
+
+  /* Determine which timer to reset */
+
+  switch (priv->timid)
+    {
+#ifdef CONFIG_STM32F7_TIM1_PWM
+      case 1:
+        regaddr  = TIMRCCRST_TIM1;
+        resetbit = TIMRST_TIM1;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM2_PWM
+      case 2:
+        regaddr  = TIMRCCRST_TIM2;
+        resetbit = TIMRST_TIM2;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM3_PWM
+      case 3:
+        regaddr  = TIMRCCRST_TIM3;
+        resetbit = TIMRST_TIM3;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM4_PWM
+      case 4:
+        regaddr  = TIMRCCRST_TIM4;
+        resetbit = TIMRST_TIM4;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM5_PWM
+      case 5:
+        regaddr  = TIMRCCRST_TIM5;
+        resetbit = TIMRST_TIM5;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM8_PWM
+      case 8:
+        regaddr  = TIMRCCRST_TIM8;
+        resetbit = TIMRST_TIM8;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM9_PWM
+      case 9:
+        regaddr  = TIMRCCRST_TIM9;
+        resetbit = TIMRST_TIM9;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM10_PWM
+      case 10:
+        regaddr  = TIMRCCRST_TIM10;
+        resetbit = TIMRST_TIM10;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM11_PWM
+      case 11:
+        regaddr  = TIMRCCRST_TIM11;
+        resetbit = TIMRST_TIM11;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM12_PWM
+      case 12:
+        regaddr  = TIMRCCRST_TIM12;
+        resetbit = TIMRST_TIM12;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM13_PWM
+      case 13:
+        regaddr  = TIMRCCRST_TIM13;
+        resetbit = TIMRST_TIM13;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM14_PWM
+      case 14:
+        regaddr  = TIMRCCRST_TIM14;
+        resetbit = TIMRST_TIM14;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM15_PWM
+      case 15:
+        regaddr  = TIMRCCRST_TIM15;
+        resetbit = TIMRST_TIM15;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM16_PWM
+      case 16:
+        regaddr  = TIMRCCRST_TIM16;
+        resetbit = TIMRST_TIM16;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM17_PWM
+      case 17:
+        regaddr  = TIMRCCRST_TIM17;
+        resetbit = TIMRST_TIM17;
+        break;
+#endif
+      default:
+        return -EINVAL;
+    }
+
+  /* Disable interrupts momentary to stop any ongoing timer processing and
+   * to prevent any concurrent access to the reset register.
+   */
+
+  flags = enter_critical_section();
+
+#ifndef CONFIG_PWM_PULSECOUNT
+  /* Stopped so frequency is zero */
+
+  priv->frequency = 0;
+#endif
+
+  /* Disable further interrupts and stop the timer */
+
+  pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0);
+  pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0);
+
+  /* Reset the timer - stopping the output and putting the timer back
+   * into a state where pwm_start() can be called.
+   */
+
+  regval  = getreg32(regaddr);
+  regval |= resetbit;
+  putreg32(regval, regaddr);
+
+  regval &= ~resetbit;
+  putreg32(regval, regaddr);
+  leave_critical_section(flags);
+
+  pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
+  pwm_dumpregs(priv, "After stop");
+  return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_ioctl
+ *
+ * Description:
+ *   Lower-half logic may support platform-specific ioctl commands
+ *
+ * Input Parameters:
+ *   dev - A reference to the lower half PWM driver state structure
+ *   cmd - The ioctl command
+ *   arg - The argument accompanying the ioctl command
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd,
+                     unsigned long arg)
+{
+#ifdef CONFIG_DEBUG_PWM_INFO
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+
+  /* There are no platform-specific ioctl commands */
+
+  pwminfo("TIM%u\n", priv->timid);
+#endif
+  return -ENOTTY;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_pwminitialize
+ *
+ * Description:
+ *   Initialize one timer for use with the upper_level PWM driver.
+ *
+ * Input Parameters:
+ *   timer - A number identifying the timer use.  The number of valid timer
+ *     IDs varies with the STM32 MCU and MCU family but is somewhere in
+ *     the range of {1,..,17}.
+ *
+ * Returned Value:
+ *   On success, a pointer to the STM32 lower half PWM driver is returned.
+ *   NULL is returned on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer)
+{
+  FAR struct stm32_pwmtimer_s *lower;
+
+  pwminfo("TIM%u\n", timer);
+
+  switch (timer)
+    {
+#ifdef CONFIG_STM32F7_TIM1_PWM
+      case 1:
+        lower = &g_pwm1dev;
+
+        /* Attach but disable the TIM1 update interrupt */
+
+#ifdef CONFIG_PWM_PULSECOUNT
+        irq_attach(lower->irq, pwm_tim1interrupt, NULL);
+        up_disable_irq(lower->irq);
+#endif
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM2_PWM
+      case 2:
+        lower = &g_pwm2dev;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM3_PWM
+      case 3:
+        lower = &g_pwm3dev;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM4_PWM
+      case 4:
+        lower = &g_pwm4dev;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM5_PWM
+      case 5:
+        lower = &g_pwm5dev;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM8_PWM
+      case 8:
+        lower = &g_pwm8dev;
+
+        /* Attach but disable the TIM8 update interrupt */
+
+#ifdef CONFIG_PWM_PULSECOUNT
+        irq_attach(lower->irq, pwm_tim8interrupt, NULL);
+        up_disable_irq(lower->irq);
+#endif
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM9_PWM
+      case 9:
+        lower = &g_pwm9dev;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM10_PWM
+      case 10:
+        lower = &g_pwm10dev;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM11_PWM
+      case 11:
+        lower = &g_pwm11dev;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM12_PWM
+      case 12:
+        lower = &g_pwm12dev;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM13_PWM
+      case 13:
+        lower = &g_pwm13dev;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM14_PWM
+      case 14:
+        lower = &g_pwm14dev;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM15_PWM
+      case 15:
+        lower = &g_pwm15dev;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM16_PWM
+      case 16:
+        lower = &g_pwm16dev;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM17_PWM
+      case 17:
+        lower = &g_pwm17dev;
+        break;
+#endif
+
+      default:
+        pwmerr("ERROR: No such timer configured\n");
+        return NULL;
+    }
+
+  return (FAR struct pwm_lowerhalf_s *)lower;
+}
+
+#endif /* CONFIG_STM32F7_TIMn_PWM, n = 1,...,17 */
diff --git a/arch/arm/src/stm32f7/stm32_pwm.h b/arch/arm/src/stm32f7/stm32_pwm.h
new file mode 100644
index 00000000000..c648cc47200
--- /dev/null
+++ b/arch/arm/src/stm32f7/stm32_pwm.h
@@ -0,0 +1,1111 @@
+/****************************************************************************
+ * arch/arm/src/stm32f7/stm32_pwm.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *            Paul Alexander Patience 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_STM32_PWM_H
+#define __ARCH_ARM_SRC_STM32F7_STM32_PWM_H
+
+/* The STM32 does not have dedicated PWM hardware.  Rather, pulsed output
+ * control is a capabilitiy of the STM32 timers.  The logic in this file
+ * implements the lower half of the standard, NuttX PWM interface using the
+ * STM32 timers.  That interface is described in include/nuttx/drivers/pwm.h.
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* Timer devices may be used for different purposes.  One special purpose is
+ * to generate modulated outputs for such things as motor control.  If
+ * CONFIG_STM32F7_TIMn is defined then the CONFIG_STM32F7_TIMn_PWM must also
+ * be defined to indicate that timer "n" is intended to be used for pulsed
+ * output signal generation.
+ */
+
+#ifndef CONFIG_STM32F7_TIM1
+#  undef CONFIG_STM32F7_TIM1_PWM
+#endif
+#ifndef CONFIG_STM32F7_TIM2
+#  undef CONFIG_STM32F7_TIM2_PWM
+#endif
+#ifndef CONFIG_STM32F7_TIM3
+#  undef CONFIG_STM32F7_TIM3_PWM
+#endif
+#ifndef CONFIG_STM32F7_TIM4
+#  undef CONFIG_STM32F7_TIM4_PWM
+#endif
+#ifndef CONFIG_STM32F7_TIM5
+#  undef CONFIG_STM32F7_TIM5_PWM
+#endif
+#ifndef CONFIG_STM32F7_TIM8
+#  undef CONFIG_STM32F7_TIM8_PWM
+#endif
+#ifndef CONFIG_STM32F7_TIM9
+#  undef CONFIG_STM32F7_TIM9_PWM
+#endif
+#ifndef CONFIG_STM32F7_TIM10
+#  undef CONFIG_STM32F7_TIM10_PWM
+#endif
+#ifndef CONFIG_STM32F7_TIM11
+#  undef CONFIG_STM32F7_TIM11_PWM
+#endif
+#ifndef CONFIG_STM32F7_TIM12
+#  undef CONFIG_STM32F7_TIM12_PWM
+#endif
+#ifndef CONFIG_STM32F7_TIM13
+#  undef CONFIG_STM32F7_TIM13_PWM
+#endif
+#ifndef CONFIG_STM32F7_TIM14
+#  undef CONFIG_STM32F7_TIM14_PWM
+#endif
+#ifndef CONFIG_STM32F7_TIM15
+#  undef CONFIG_STM32F7_TIM15_PWM
+#endif
+#ifndef CONFIG_STM32F7_TIM16
+#  undef CONFIG_STM32F7_TIM16_PWM
+#endif
+#ifndef CONFIG_STM32F7_TIM17
+#  undef CONFIG_STM32F7_TIM17_PWM
+#endif
+
+/* The basic timers (timer 6 and 7) are not capable of generating output pulses */
+
+#undef CONFIG_STM32F7_TIM6_PWM
+#undef CONFIG_STM32F7_TIM7_PWM
+
+/* Check if PWM support for any channel is enabled. */
+
+#if defined(CONFIG_STM32F7_TIM1_PWM)  || defined(CONFIG_STM32F7_TIM2_PWM)  || \
+    defined(CONFIG_STM32F7_TIM3_PWM)  || defined(CONFIG_STM32F7_TIM4_PWM)  || \
+    defined(CONFIG_STM32F7_TIM5_PWM)  || defined(CONFIG_STM32F7_TIM8_PWM)  || \
+    defined(CONFIG_STM32F7_TIM9_PWM)  || defined(CONFIG_STM32F7_TIM10_PWM) || \
+    defined(CONFIG_STM32F7_TIM11_PWM) || defined(CONFIG_STM32F7_TIM12_PWM) || \
+    defined(CONFIG_STM32F7_TIM13_PWM) || defined(CONFIG_STM32F7_TIM14_PWM) || \
+    defined(CONFIG_STM32F7_TIM15_PWM) || defined(CONFIG_STM32F7_TIM16_PWM) || \
+    defined(CONFIG_STM32F7_TIM17_PWM)
+
+#include 
+#include "hardware/stm32_tim.h"
+
+#ifdef CONFIG_PWM_MULTICHAN
+
+#ifdef CONFIG_STM32F7_TIM1_CHANNEL1
+#  ifdef CONFIG_STM32F7_TIM1_CH1OUT
+#    define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
+#  else
+#    define PWM_TIM1_CH1CFG 0
+#  endif
+#  define PWM_TIM1_CHANNEL1 1
+#else
+#  define PWM_TIM1_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32F7_TIM1_CHANNEL2
+#  ifdef CONFIG_STM32F7_TIM1_CH2OUT
+#    define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
+#  else
+#    define PWM_TIM1_CH2CFG 0
+#  endif
+#  define PWM_TIM1_CHANNEL2 1
+#else
+#  define PWM_TIM1_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32F7_TIM1_CHANNEL3
+#  ifdef CONFIG_STM32F7_TIM1_CH3OUT
+#    define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
+#  else
+#    define PWM_TIM1_CH3CFG 0
+#  endif
+#  define PWM_TIM1_CHANNEL3 1
+#else
+#  define PWM_TIM1_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32F7_TIM1_CHANNEL4
+#  ifdef CONFIG_STM32F7_TIM1_CH4OUT
+#    define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT
+#  else
+#    define PWM_TIM1_CH4CFG 0
+#  endif
+#  define PWM_TIM1_CHANNEL4 1
+#else
+#  define PWM_TIM1_CHANNEL4 0
+#endif
+#define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \
+                            PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4)
+
+#ifdef CONFIG_STM32F7_TIM2_CHANNEL1
+#  ifdef CONFIG_STM32F7_TIM2_CH1OUT
+#    define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT_1
+#  else
+#    define PWM_TIM2_CH1CFG 0
+#  endif
+#  define PWM_TIM2_CHANNEL1 1
+#else
+#  define PWM_TIM2_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32F7_TIM2_CHANNEL2
+#  ifdef CONFIG_STM32F7_TIM2_CH2OUT
+#    define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT
+#  else
+#    define PWM_TIM2_CH2CFG 0
+#  endif
+#  define PWM_TIM2_CHANNEL2 1
+#else
+#  define PWM_TIM2_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32F7_TIM2_CHANNEL3
+#  ifdef CONFIG_STM32F7_TIM2_CH3OUT
+#    define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT
+#  else
+#    define PWM_TIM2_CH3CFG 0
+#  endif
+#  define PWM_TIM2_CHANNEL3 1
+#else
+#  define PWM_TIM2_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32F7_TIM2_CHANNEL4
+#  ifdef CONFIG_STM32F7_TIM2_CH4OUT
+#    define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT
+#  else
+#    define PWM_TIM2_CH4CFG 0
+#  endif
+#  define PWM_TIM2_CHANNEL4 1
+#else
+#  define PWM_TIM2_CHANNEL4 0
+#endif
+#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \
+                            PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4)
+
+#ifdef CONFIG_STM32F7_TIM3_CHANNEL1
+#  ifdef CONFIG_STM32F7_TIM3_CH1OUT
+#    define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT
+#  else
+#    define PWM_TIM3_CH1CFG 0
+#  endif
+#  define PWM_TIM3_CHANNEL1 1
+#else
+#  define PWM_TIM3_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32F7_TIM3_CHANNEL2
+#  ifdef CONFIG_STM32F7_TIM3_CH2OUT
+#    define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT
+#  else
+#    define PWM_TIM3_CH2CFG 0
+#  endif
+#  define PWM_TIM3_CHANNEL2 1
+#else
+#  define PWM_TIM3_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32F7_TIM3_CHANNEL3
+#  ifdef CONFIG_STM32F7_TIM3_CH3OUT
+#    define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT
+#  else
+#    define PWM_TIM3_CH3CFG 0
+#  endif
+#  define PWM_TIM3_CHANNEL3 1
+#else
+#  define PWM_TIM3_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32F7_TIM3_CHANNEL4
+#  ifdef CONFIG_STM32F7_TIM3_CH4OUT
+#    define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT
+#  else
+#    define PWM_TIM3_CH4CFG 0
+#  endif
+#  define PWM_TIM3_CHANNEL4 1
+#else
+#  define PWM_TIM3_CHANNEL4 0
+#endif
+#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \
+                            PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4)
+
+#ifdef CONFIG_STM32F7_TIM4_CHANNEL1
+#  ifdef CONFIG_STM32F7_TIM4_CH1OUT
+#    define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT
+#  else
+#    define PWM_TIM4_CH1CFG 0
+#  endif
+#  define PWM_TIM4_CHANNEL1 1
+#else
+#  define PWM_TIM4_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32F7_TIM4_CHANNEL2
+#  ifdef CONFIG_STM32F7_TIM4_CH2OUT
+#    define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT
+#  else
+#    define PWM_TIM4_CH2CFG 0
+#  endif
+#  define PWM_TIM4_CHANNEL2 1
+#else
+#  define PWM_TIM4_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32F7_TIM4_CHANNEL3
+#  ifdef CONFIG_STM32F7_TIM4_CH3OUT
+#    define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT
+#  else
+#    define PWM_TIM4_CH3CFG 0
+#  endif
+#  define PWM_TIM4_CHANNEL3 1
+#else
+#  define PWM_TIM4_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32F7_TIM4_CHANNEL4
+#  ifdef CONFIG_STM32F7_TIM4_CH4OUT
+#    define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT
+#  else
+#    define PWM_TIM4_CH4CFG 0
+#  endif
+#  define PWM_TIM4_CHANNEL4 1
+#else
+#  define PWM_TIM4_CHANNEL4 0
+#endif
+#define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \
+                            PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4)
+
+#ifdef CONFIG_STM32F7_TIM5_CHANNEL1
+#  ifdef CONFIG_STM32F7_TIM5_CH1OUT
+#    define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT
+#  else
+#    define PWM_TIM5_CH1CFG 0
+#  endif
+#  define PWM_TIM5_CHANNEL1 1
+#else
+#  define PWM_TIM5_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32F7_TIM5_CHANNEL2
+#  ifdef CONFIG_STM32F7_TIM5_CH2OUT
+#    define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT
+#  else
+#    define PWM_TIM5_CH2CFG 0
+#  endif
+#  define PWM_TIM5_CHANNEL2 1
+#else
+#  define PWM_TIM5_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32F7_TIM5_CHANNEL3
+#  ifdef CONFIG_STM32F7_TIM5_CH3OUT
+#    define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT
+#  else
+#    define PWM_TIM5_CH3CFG 0
+#  endif
+#  define PWM_TIM5_CHANNEL3 1
+#else
+#  define PWM_TIM5_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32F7_TIM5_CHANNEL4
+#  ifdef CONFIG_STM32F7_TIM5_CH4OUT
+#    define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT
+#  else
+#    define PWM_TIM5_CH4CFG 0
+#  endif
+#  define PWM_TIM5_CHANNEL4 1
+#else
+#  define PWM_TIM5_CHANNEL4 0
+#endif
+#define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \
+                            PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4)
+
+#ifdef CONFIG_STM32F7_TIM8_CHANNEL1
+#  ifdef CONFIG_STM32F7_TIM8_CH1OUT
+#    define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT
+#  else
+#    define PWM_TIM8_CH1CFG 0
+#  endif
+#  define PWM_TIM8_CHANNEL1 1
+#else
+#  define PWM_TIM8_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32F7_TIM8_CHANNEL2
+#  ifdef CONFIG_STM32F7_TIM8_CH2OUT
+#    define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT
+#  else
+#    define PWM_TIM8_CH2CFG 0
+#  endif
+#  define PWM_TIM8_CHANNEL2 1
+#else
+#  define PWM_TIM8_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32F7_TIM8_CHANNEL3
+#  ifdef CONFIG_STM32F7_TIM8_CH3OUT
+#    define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT
+#  else
+#    define PWM_TIM8_CH3CFG 0
+#  endif
+#  define PWM_TIM8_CHANNEL3 1
+#else
+#  define PWM_TIM8_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32F7_TIM8_CHANNEL4
+#  ifdef CONFIG_STM32F7_TIM8_CH4OUT
+#    define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT
+#  else
+#    define PWM_TIM8_CH4CFG 0
+#  endif
+#  define PWM_TIM8_CHANNEL4 1
+#else
+#  define PWM_TIM8_CHANNEL4 0
+#endif
+#define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \
+                            PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4)
+
+#ifdef CONFIG_STM32F7_TIM9_CHANNEL1
+#  ifdef CONFIG_STM32F7_TIM9_CH1OUT
+#    define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT
+#  else
+#    define PWM_TIM9_CH1CFG 0
+#  endif
+#  define PWM_TIM9_CHANNEL1 1
+#else
+#  define PWM_TIM9_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32F7_TIM9_CHANNEL2
+#  ifdef CONFIG_STM32F7_TIM9_CH2OUT
+#    define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT
+#  else
+#    define PWM_TIM9_CH2CFG 0
+#  endif
+#  define PWM_TIM9_CHANNEL2 1
+#else
+#  define PWM_TIM9_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32F7_TIM9_CHANNEL3
+#  ifdef CONFIG_STM32F7_TIM9_CH3OUT
+#    define PWM_TIM9_CH3CFG GPIO_TIM9_CH3OUT
+#  else
+#    define PWM_TIM9_CH3CFG 0
+#  endif
+#  define PWM_TIM9_CHANNEL3 1
+#else
+#  define PWM_TIM9_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32F7_TIM9_CHANNEL4
+#  ifdef CONFIG_STM32F7_TIM9_CH4OUT
+#    define PWM_TIM9_CH4CFG GPIO_TIM9_CH4OUT
+#  else
+#    define PWM_TIM9_CH4CFG 0
+#  endif
+#  define PWM_TIM9_CHANNEL4 1
+#else
+#  define PWM_TIM9_CHANNEL4 0
+#endif
+#define PWM_TIM9_NCHANNELS (PWM_TIM9_CHANNEL1 + PWM_TIM9_CHANNEL2 + \
+                            PWM_TIM9_CHANNEL3 + PWM_TIM9_CHANNEL4)
+
+#ifdef CONFIG_STM32F7_TIM10_CHANNEL1
+#  ifdef CONFIG_STM32F7_TIM10_CH1OUT
+#    define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT
+#  else
+#    define PWM_TIM10_CH1CFG 0
+#  endif
+#  define PWM_TIM10_CHANNEL1 1
+#else
+#  define PWM_TIM10_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32F7_TIM10_CHANNEL2
+#  ifdef CONFIG_STM32F7_TIM10_CH2OUT
+#    define PWM_TIM10_CH2CFG GPIO_TIM10_CH2OUT
+#  else
+#    define PWM_TIM10_CH2CFG 0
+#  endif
+#  define PWM_TIM10_CHANNEL2 1
+#else
+#  define PWM_TIM10_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32F7_TIM10_CHANNEL3
+#  ifdef CONFIG_STM32F7_TIM10_CH3OUT
+#    define PWM_TIM10_CH3CFG GPIO_TIM10_CH3OUT
+#  else
+#    define PWM_TIM10_CH3CFG 0
+#  endif
+#  define PWM_TIM10_CHANNEL3 1
+#else
+#  define PWM_TIM10_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32F7_TIM10_CHANNEL4
+#  ifdef CONFIG_STM32F7_TIM10_CH4OUT
+#    define PWM_TIM10_CH4CFG GPIO_TIM10_CH4OUT
+#  else
+#    define PWM_TIM10_CH4CFG 0
+#  endif
+#  define PWM_TIM10_CHANNEL4 1
+#else
+#  define PWM_TIM10_CHANNEL4 0
+#endif
+#define PWM_TIM10_NCHANNELS (PWM_TIM10_CHANNEL1 + PWM_TIM10_CHANNEL2 + \
+                             PWM_TIM10_CHANNEL3 + PWM_TIM10_CHANNEL4)
+
+#ifdef CONFIG_STM32F7_TIM11_CHANNEL1
+#  ifdef CONFIG_STM32F7_TIM11_CH1OUT
+#    define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT
+#  else
+#    define PWM_TIM11_CH1CFG 0
+#  endif
+#  define PWM_TIM11_CHANNEL1 1
+#else
+#  define PWM_TIM11_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32F7_TIM11_CHANNEL2
+#  ifdef CONFIG_STM32F7_TIM11_CH2OUT
+#    define PWM_TIM11_CH2CFG GPIO_TIM11_CH2OUT
+#  else
+#    define PWM_TIM11_CH2CFG 0
+#  endif
+#  define PWM_TIM11_CHANNEL2 1
+#else
+#  define PWM_TIM11_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32F7_TIM11_CHANNEL3
+#  ifdef CONFIG_STM32F7_TIM11_CH3OUT
+#    define PWM_TIM11_CH3CFG GPIO_TIM11_CH3OUT
+#  else
+#    define PWM_TIM11_CH3CFG 0
+#  endif
+#  define PWM_TIM11_CHANNEL3 1
+#else
+#  define PWM_TIM11_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32F7_TIM11_CHANNEL4
+#  ifdef CONFIG_STM32F7_TIM11_CH4OUT
+#    define PWM_TIM11_CH4CFG GPIO_TIM11_CH4OUT
+#  else
+#    define PWM_TIM11_CH4CFG 0
+#  endif
+#  define PWM_TIM11_CHANNEL4 1
+#else
+#  define PWM_TIM11_CHANNEL4 0
+#endif
+#define PWM_TIM11_NCHANNELS (PWM_TIM11_CHANNEL1 + PWM_TIM11_CHANNEL2 + \
+                             PWM_TIM11_CHANNEL3 + PWM_TIM11_CHANNEL4)
+
+#ifdef CONFIG_STM32F7_TIM12_CHANNEL1
+#  ifdef CONFIG_STM32F7_TIM12_CH1OUT
+#    define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT
+#  else
+#    define PWM_TIM12_CH1CFG 0
+#  endif
+#  define PWM_TIM12_CHANNEL1 1
+#else
+#  define PWM_TIM12_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32F7_TIM12_CHANNEL2
+#  ifdef CONFIG_STM32F7_TIM12_CH2OUT
+#    define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT
+#  else
+#    define PWM_TIM12_CH2CFG 0
+#  endif
+#  define PWM_TIM12_CHANNEL2 1
+#else
+#  define PWM_TIM12_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32F7_TIM12_CHANNEL3
+#  ifdef CONFIG_STM32F7_TIM12_CH3OUT
+#    define PWM_TIM12_CH3CFG GPIO_TIM12_CH3OUT
+#  else
+#    define PWM_TIM12_CH3CFG 0
+#  endif
+#  define PWM_TIM12_CHANNEL3 1
+#else
+#  define PWM_TIM12_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32F7_TIM12_CHANNEL4
+#  ifdef CONFIG_STM32F7_TIM12_CH4OUT
+#    define PWM_TIM12_CH4CFG GPIO_TIM12_CH4OUT
+#  else
+#    define PWM_TIM12_CH4CFG 0
+#  endif
+#  define PWM_TIM12_CHANNEL4 1
+#else
+#  define PWM_TIM12_CHANNEL4 0
+#endif
+#define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2 + \
+                             PWM_TIM12_CHANNEL3 + PWM_TIM12_CHANNEL4)
+
+#ifdef CONFIG_STM32F7_TIM13_CHANNEL1
+#  ifdef CONFIG_STM32F7_TIM13_CH1OUT
+#    define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT
+#  else
+#    define PWM_TIM13_CH1CFG 0
+#  endif
+#  define PWM_TIM13_CHANNEL1 1
+#else
+#  define PWM_TIM13_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32F7_TIM13_CHANNEL2
+#  ifdef CONFIG_STM32F7_TIM13_CH2OUT
+#    define PWM_TIM13_CH2CFG GPIO_TIM13_CH2OUT
+#  else
+#    define PWM_TIM13_CH2CFG 0
+#  endif
+#  define PWM_TIM13_CHANNEL2 1
+#else
+#  define PWM_TIM13_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32F7_TIM13_CHANNEL3
+#  ifdef CONFIG_STM32F7_TIM13_CH3OUT
+#    define PWM_TIM13_CH3CFG GPIO_TIM13_CH3OUT
+#  else
+#    define PWM_TIM13_CH3CFG 0
+#  endif
+#  define PWM_TIM13_CHANNEL3 1
+#else
+#  define PWM_TIM13_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32F7_TIM13_CHANNEL4
+#  ifdef CONFIG_STM32F7_TIM13_CH4OUT
+#    define PWM_TIM13_CH4CFG GPIO_TIM13_CH4OUT
+#  else
+#    define PWM_TIM13_CH4CFG 0
+#  endif
+#  define PWM_TIM13_CHANNEL4 1
+#else
+#  define PWM_TIM13_CHANNEL4 0
+#endif
+#define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1 + PWM_TIM13_CHANNEL2 + \
+                             PWM_TIM13_CHANNEL3 + PWM_TIM13_CHANNEL4)
+
+#ifdef CONFIG_STM32F7_TIM14_CHANNEL1
+#  ifdef CONFIG_STM32F7_TIM14_CH1OUT
+#    define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT
+#  else
+#    define PWM_TIM14_CH1CFG 0
+#  endif
+#  define PWM_TIM14_CHANNEL1 1
+#else
+#  define PWM_TIM14_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32F7_TIM14_CHANNEL2
+#  ifdef CONFIG_STM32F7_TIM14_CH2OUT
+#    define PWM_TIM14_CH2CFG GPIO_TIM14_CH2OUT
+#  else
+#    define PWM_TIM14_CH2CFG 0
+#  endif
+#  define PWM_TIM14_CHANNEL2 1
+#else
+#  define PWM_TIM14_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32F7_TIM14_CHANNEL3
+#  ifdef CONFIG_STM32F7_TIM14_CH3OUT
+#    define PWM_TIM14_CH3CFG GPIO_TIM14_CH3OUT
+#  else
+#    define PWM_TIM14_CH3CFG 0
+#  endif
+#  define PWM_TIM14_CHANNEL3 1
+#else
+#  define PWM_TIM14_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32F7_TIM14_CHANNEL4
+#  ifdef CONFIG_STM32F7_TIM14_CH4OUT
+#    define PWM_TIM14_CH4CFG GPIO_TIM14_CH4OUT
+#  else
+#    define PWM_TIM14_CH4CFG 0
+#  endif
+#  define PWM_TIM14_CHANNEL4 1
+#else
+#  define PWM_TIM14_CHANNEL4 0
+#endif
+#define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1 + PWM_TIM14_CHANNEL2 + \
+                             PWM_TIM14_CHANNEL3 + PWM_TIM14_CHANNEL4)
+
+#ifdef CONFIG_STM32F7_TIM15_CHANNEL1
+#  ifdef CONFIG_STM32F7_TIM15_CH1OUT
+#    define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT
+#  else
+#    define PWM_TIM15_CH1CFG 0
+#  endif
+#  define PWM_TIM15_CHANNEL1 1
+#else
+#  define PWM_TIM15_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32F7_TIM15_CHANNEL2
+#  ifdef CONFIG_STM32F7_TIM15_CH2OUT
+#    define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT
+#  else
+#    define PWM_TIM15_CH2CFG 0
+#  endif
+#  define PWM_TIM15_CHANNEL2 1
+#else
+#  define PWM_TIM15_CHANNEL2 0
+#endif
+#define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2)
+
+#ifdef CONFIG_STM32F7_TIM16_CHANNEL1
+#  ifdef CONFIG_STM32F7_TIM16_CH1OUT
+#    define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT
+#  else
+#    define PWM_TIM16_CH1CFG 0
+#  endif
+#  define PWM_TIM16_CHANNEL1 1
+#else
+#  define PWM_TIM16_CHANNEL1 0
+#endif
+#define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1
+
+#ifdef CONFIG_STM32F7_TIM17_CHANNEL1
+#  ifdef CONFIG_STM32F7_TIM17_CH1OUT
+#    define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT
+#  else
+#    define PWM_TIM17_CH1CFG 0
+#  endif
+#  define PWM_TIM17_CHANNEL1 1
+#else
+#  define PWM_TIM17_CHANNEL1 0
+#endif
+#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1
+
+#define PWM_MAX(a, b) ((a) > (b) ? (a) : (b))
+
+#define PWM_NCHANNELS PWM_MAX(PWM_TIM1_NCHANNELS, \
+                      PWM_MAX(PWM_TIM2_NCHANNELS, \
+                      PWM_MAX(PWM_TIM3_NCHANNELS, \
+                      PWM_MAX(PWM_TIM4_NCHANNELS, \
+                      PWM_MAX(PWM_TIM5_NCHANNELS, \
+                      PWM_MAX(PWM_TIM8_NCHANNELS, \
+                      PWM_MAX(PWM_TIM9_NCHANNELS, \
+                      PWM_MAX(PWM_TIM10_NCHANNELS, \
+                      PWM_MAX(PWM_TIM11_NCHANNELS, \
+                      PWM_MAX(PWM_TIM12_NCHANNELS, \
+                      PWM_MAX(PWM_TIM13_NCHANNELS, \
+                      PWM_MAX(PWM_TIM14_NCHANNELS, \
+                      PWM_MAX(PWM_TIM15_NCHANNELS, \
+                      PWM_MAX(PWM_TIM16_NCHANNELS, \
+                              PWM_TIM17_NCHANNELS))))))))))))))
+
+#else
+
+/* For each timer that is enabled for PWM usage, we need the following
+ * additional configuration settings:
+ *
+ * CONFIG_STM32F7_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
+ * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h.  In the
+ * case where there are multiple pin selections, the correct setting must be
+ * provided in the arch/board/board.h file.
+ *
+ * NOTE: The STM32 timers are each capable of generating different signals on
+ * each of the four channels with different duty cycles.  That capability is
+ * not supported by this driver:  Only one output channel per timer.
+ */
+
+#ifdef CONFIG_STM32F7_TIM1_PWM
+#  if !defined(CONFIG_STM32F7_TIM1_CHANNEL)
+#    error "CONFIG_STM32F7_TIM1_CHANNEL must be provided"
+#  elif CONFIG_STM32F7_TIM1_CHANNEL == 1
+#    define CONFIG_STM32F7_TIM1_CHANNEL1 1
+#    define CONFIG_STM32F7_TIM1_CH1MODE  CONFIG_STM32F7_TIM1_CHMODE
+#    define PWM_TIM1_CH1CFG            GPIO_TIM1_CH1OUT
+#  elif CONFIG_STM32F7_TIM1_CHANNEL == 2
+#    define CONFIG_STM32F7_TIM1_CHANNEL2 1
+#    define CONFIG_STM32F7_TIM1_CH2MODE  CONFIG_STM32F7_TIM1_CHMODE
+#    define PWM_TIM1_CH2CFG            GPIO_TIM1_CH2OUT
+#  elif CONFIG_STM32F7_TIM1_CHANNEL == 3
+#    define CONFIG_STM32F7_TIM1_CHANNEL3 1
+#    define CONFIG_STM32F7_TIM1_CH3MODE  CONFIG_STM32F7_TIM1_CHMODE
+#    define PWM_TIM1_CH3CFG            GPIO_TIM1_CH3OUT
+#  elif CONFIG_STM32F7_TIM1_CHANNEL == 4
+#    define CONFIG_STM32F7_TIM1_CHANNEL4 1
+#    define CONFIG_STM32F7_TIM1_CH4MODE  CONFIG_STM32F7_TIM1_CHMODE
+#    define PWM_TIM1_CH4CFG            GPIO_TIM1_CH4OUT
+#  else
+#    error "Unsupported value of CONFIG_STM32F7_TIM1_CHANNEL"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32F7_TIM2_PWM
+#  if !defined(CONFIG_STM32F7_TIM2_CHANNEL)
+#    error "CONFIG_STM32F7_TIM2_CHANNEL must be provided"
+#  elif CONFIG_STM32F7_TIM2_CHANNEL == 1
+#    define CONFIG_STM32F7_TIM2_CHANNEL1 1
+#    define CONFIG_STM32F7_TIM2_CH1MODE  CONFIG_STM32F7_TIM2_CHMODE
+#    define PWM_TIM2_CH1CFG            GPIO_TIM2_CH1OUT_1
+#  elif CONFIG_STM32F7_TIM2_CHANNEL == 2
+#    define CONFIG_STM32F7_TIM2_CHANNEL2 1
+#    define CONFIG_STM32F7_TIM2_CH2MODE  CONFIG_STM32F7_TIM2_CHMODE
+#    define PWM_TIM2_CH2CFG            GPIO_TIM2_CH2OUT
+#  elif CONFIG_STM32F7_TIM2_CHANNEL == 3
+#    define CONFIG_STM32F7_TIM2_CHANNEL3 1
+#    define CONFIG_STM32F7_TIM2_CH3MODE  CONFIG_STM32F7_TIM2_CHMODE
+#    define PWM_TIM2_CH3CFG            GPIO_TIM2_CH3OUT
+#  elif CONFIG_STM32F7_TIM2_CHANNEL == 4
+#    define CONFIG_STM32F7_TIM2_CHANNEL4 1
+#    define CONFIG_STM32F7_TIM2_CH4MODE  CONFIG_STM32F7_TIM2_CHMODE
+#    define PWM_TIM2_CH4CFG            GPIO_TIM2_CH4OUT
+#  else
+#    error "Unsupported value of CONFIG_STM32F7_TIM2_CHANNEL"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32F7_TIM3_PWM
+#  if !defined(CONFIG_STM32F7_TIM3_CHANNEL)
+#    error "CONFIG_STM32F7_TIM3_CHANNEL must be provided"
+#  elif CONFIG_STM32F7_TIM3_CHANNEL == 1
+#    define CONFIG_STM32F7_TIM3_CHANNEL1 1
+#    define CONFIG_STM32F7_TIM3_CH1MODE  CONFIG_STM32F7_TIM3_CHMODE
+#    define PWM_TIM3_CH1CFG            GPIO_TIM3_CH1OUT
+#  elif CONFIG_STM32F7_TIM3_CHANNEL == 2
+#    define CONFIG_STM32F7_TIM3_CHANNEL2 1
+#    define CONFIG_STM32F7_TIM3_CH2MODE  CONFIG_STM32F7_TIM3_CHMODE
+#    define PWM_TIM3_CH2CFG            GPIO_TIM3_CH2OUT
+#  elif CONFIG_STM32F7_TIM3_CHANNEL == 3
+#    define CONFIG_STM32F7_TIM3_CHANNEL3 1
+#    define CONFIG_STM32F7_TIM3_CH3MODE  CONFIG_STM32F7_TIM3_CHMODE
+#    define PWM_TIM3_CH3CFG            GPIO_TIM3_CH3OUT
+#  elif CONFIG_STM32F7_TIM3_CHANNEL == 4
+#    define CONFIG_STM32F7_TIM3_CHANNEL4 1
+#    define CONFIG_STM32F7_TIM3_CH4MODE  CONFIG_STM32F7_TIM3_CHMODE
+#    define PWM_TIM3_CH4CFG            GPIO_TIM3_CH4OUT
+#  else
+#    error "Unsupported value of CONFIG_STM32F7_TIM3_CHANNEL"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32F7_TIM4_PWM
+#  if !defined(CONFIG_STM32F7_TIM4_CHANNEL)
+#    error "CONFIG_STM32F7_TIM4_CHANNEL must be provided"
+#  elif CONFIG_STM32F7_TIM4_CHANNEL == 1
+#    define CONFIG_STM32F7_TIM4_CHANNEL1 1
+#    define CONFIG_STM32F7_TIM4_CH1MODE  CONFIG_STM32F7_TIM4_CHMODE
+#    define PWM_TIM4_CH1CFG            GPIO_TIM4_CH1OUT
+#  elif CONFIG_STM32F7_TIM4_CHANNEL == 2
+#    define CONFIG_STM32F7_TIM4_CHANNEL2 1
+#    define CONFIG_STM32F7_TIM4_CH2MODE  CONFIG_STM32F7_TIM4_CHMODE
+#    define PWM_TIM4_CH2CFG            GPIO_TIM4_CH2OUT
+#  elif CONFIG_STM32F7_TIM4_CHANNEL == 3
+#    define CONFIG_STM32F7_TIM4_CHANNEL3 1
+#    define CONFIG_STM32F7_TIM4_CH3MODE  CONFIG_STM32F7_TIM4_CHMODE
+#    define PWM_TIM4_CH3CFG            GPIO_TIM4_CH3OUT
+#  elif CONFIG_STM32F7_TIM4_CHANNEL == 4
+#    define CONFIG_STM32F7_TIM4_CHANNEL4 1
+#    define CONFIG_STM32F7_TIM4_CH4MODE  CONFIG_STM32F7_TIM4_CHMODE
+#    define PWM_TIM4_CH4CFG            GPIO_TIM4_CH4OUT
+#  else
+#    error "Unsupported value of CONFIG_STM32F7_TIM4_CHANNEL"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32F7_TIM5_PWM
+#  if !defined(CONFIG_STM32F7_TIM5_CHANNEL)
+#    error "CONFIG_STM32F7_TIM5_CHANNEL must be provided"
+#  elif CONFIG_STM32F7_TIM5_CHANNEL == 1
+#    define CONFIG_STM32F7_TIM5_CHANNEL1 1
+#    define CONFIG_STM32F7_TIM5_CH1MODE  CONFIG_STM32F7_TIM5_CHMODE
+#    define PWM_TIM5_CH1CFG            GPIO_TIM5_CH1OUT
+#  elif CONFIG_STM32F7_TIM5_CHANNEL == 2
+#    define CONFIG_STM32F7_TIM5_CHANNEL2 1
+#    define CONFIG_STM32F7_TIM5_CH2MODE  CONFIG_STM32F7_TIM5_CHMODE
+#    define PWM_TIM5_CH2CFG            GPIO_TIM5_CH2OUT
+#  elif CONFIG_STM32F7_TIM5_CHANNEL == 3
+#    define CONFIG_STM32F7_TIM5_CHANNEL3 1
+#    define CONFIG_STM32F7_TIM5_CH3MODE  CONFIG_STM32F7_TIM5_CHMODE
+#    define PWM_TIM5_CH3CFG            GPIO_TIM5_CH3OUT
+#  elif CONFIG_STM32F7_TIM5_CHANNEL == 4
+#    define CONFIG_STM32F7_TIM5_CHANNEL4 1
+#    define CONFIG_STM32F7_TIM5_CH4MODE  CONFIG_STM32F7_TIM5_CHMODE
+#    define PWM_TIM5_CH4CFG            GPIO_TIM5_CH4OUT
+#  else
+#    error "Unsupported value of CONFIG_STM32F7_TIM5_CHANNEL"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32F7_TIM8_PWM
+#  if !defined(CONFIG_STM32F7_TIM8_CHANNEL)
+#    error "CONFIG_STM32F7_TIM8_CHANNEL must be provided"
+#  elif CONFIG_STM32F7_TIM8_CHANNEL == 1
+#    define CONFIG_STM32F7_TIM8_CHANNEL1 1
+#    define CONFIG_STM32F7_TIM8_CH1MODE  CONFIG_STM32F7_TIM8_CHMODE
+#    define PWM_TIM8_CH1CFG            GPIO_TIM8_CH1OUT
+#  elif CONFIG_STM32F7_TIM8_CHANNEL == 2
+#    define CONFIG_STM32F7_TIM8_CHANNEL2 1
+#    define CONFIG_STM32F7_TIM8_CH2MODE  CONFIG_STM32F7_TIM8_CHMODE
+#    define PWM_TIM8_CH2CFG            GPIO_TIM8_CH2OUT
+#  elif CONFIG_STM32F7_TIM8_CHANNEL == 3
+#    define CONFIG_STM32F7_TIM8_CHANNEL3 1
+#    define CONFIG_STM32F7_TIM8_CH3MODE  CONFIG_STM32F7_TIM8_CHMODE
+#    define PWM_TIM8_CH3CFG            GPIO_TIM8_CH3OUT
+#  elif CONFIG_STM32F7_TIM8_CHANNEL == 4
+#    define CONFIG_STM32F7_TIM8_CHANNEL4 1
+#    define CONFIG_STM32F7_TIM8_CH4MODE  CONFIG_STM32F7_TIM8_CHMODE
+#    define PWM_TIM8_CH4CFG            GPIO_TIM8_CH4OUT
+#  else
+#    error "Unsupported value of CONFIG_STM32F7_TIM8_CHANNEL"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32F7_TIM9_PWM
+#  if !defined(CONFIG_STM32F7_TIM9_CHANNEL)
+#    error "CONFIG_STM32F7_TIM9_CHANNEL must be provided"
+#  elif CONFIG_STM32F7_TIM9_CHANNEL == 1
+#    define CONFIG_STM32F7_TIM9_CHANNEL1 1
+#    define CONFIG_STM32F7_TIM9_CH1MODE  CONFIG_STM32F7_TIM9_CHMODE
+#    define PWM_TIM9_CH1CFG            GPIO_TIM9_CH1OUT
+#  elif CONFIG_STM32F7_TIM9_CHANNEL == 2
+#    define CONFIG_STM32F7_TIM9_CHANNEL2 1
+#    define CONFIG_STM32F7_TIM9_CH2MODE  CONFIG_STM32F7_TIM9_CHMODE
+#    define PWM_TIM9_CH2CFG            GPIO_TIM9_CH2OUT
+#  elif CONFIG_STM32F7_TIM9_CHANNEL == 3
+#    define CONFIG_STM32F7_TIM9_CHANNEL3 1
+#    define CONFIG_STM32F7_TIM9_CH3MODE  CONFIG_STM32F7_TIM9_CHMODE
+#    define PWM_TIM9_CH3CFG            GPIO_TIM9_CH3OUT
+#  elif CONFIG_STM32F7_TIM9_CHANNEL == 4
+#    define CONFIG_STM32F7_TIM9_CHANNEL4 1
+#    define CONFIG_STM32F7_TIM9_CH4MODE  CONFIG_STM32F7_TIM9_CHMODE
+#    define PWM_TIM9_CH4CFG            GPIO_TIM9_CH4OUT
+#  else
+#    error "Unsupported value of CONFIG_STM32F7_TIM9_CHANNEL"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32F7_TIM10_PWM
+#  if !defined(CONFIG_STM32F7_TIM10_CHANNEL)
+#    error "CONFIG_STM32F7_TIM10_CHANNEL must be provided"
+#  elif CONFIG_STM32F7_TIM10_CHANNEL == 1
+#    define CONFIG_STM32F7_TIM10_CHANNEL1 1
+#    define CONFIG_STM32F7_TIM10_CH1MODE  CONFIG_STM32F7_TIM10_CHMODE
+#    define PWM_TIM10_CH1CFG            GPIO_TIM10_CH1OUT
+#  elif CONFIG_STM32F7_TIM10_CHANNEL == 2
+#    define CONFIG_STM32F7_TIM10_CHANNEL2 1
+#    define CONFIG_STM32F7_TIM10_CH2MODE  CONFIG_STM32F7_TIM10_CHMODE
+#    define PWM_TIM10_CH2CFG            GPIO_TIM10_CH2OUT
+#  elif CONFIG_STM32F7_TIM10_CHANNEL == 3
+#    define CONFIG_STM32F7_TIM10_CHANNEL3 1
+#    define CONFIG_STM32F7_TIM10_CH3MODE  CONFIG_STM32F7_TIM10_CHMODE
+#    define PWM_TIM10_CH3CFG            GPIO_TIM10_CH3OUT
+#  elif CONFIG_STM32F7_TIM10_CHANNEL == 4
+#    define CONFIG_STM32F7_TIM10_CHANNEL4 1
+#    define CONFIG_STM32F7_TIM10_CH4MODE  CONFIG_STM32F7_TIM10_CHMODE
+#    define PWM_TIM10_CH4CFG            GPIO_TIM10_CH4OUT
+#  else
+#    error "Unsupported value of CONFIG_STM32F7_TIM10_CHANNEL"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32F7_TIM11_PWM
+#  if !defined(CONFIG_STM32F7_TIM11_CHANNEL)
+#    error "CONFIG_STM32F7_TIM11_CHANNEL must be provided"
+#  elif CONFIG_STM32F7_TIM11_CHANNEL == 1
+#    define CONFIG_STM32F7_TIM11_CHANNEL1 1
+#    define CONFIG_STM32F7_TIM11_CH1MODE  CONFIG_STM32F7_TIM11_CHMODE
+#    define PWM_TIM11_CH1CFG            GPIO_TIM11_CH1OUT
+#  elif CONFIG_STM32F7_TIM11_CHANNEL == 2
+#    define CONFIG_STM32F7_TIM11_CHANNEL2 1
+#    define CONFIG_STM32F7_TIM11_CH2MODE  CONFIG_STM32F7_TIM11_CHMODE
+#    define PWM_TIM11_CH2CFG            GPIO_TIM11_CH2OUT
+#  elif CONFIG_STM32F7_TIM11_CHANNEL == 3
+#    define CONFIG_STM32F7_TIM11_CHANNEL3 1
+#    define CONFIG_STM32F7_TIM11_CH3MODE  CONFIG_STM32F7_TIM11_CHMODE
+#    define PWM_TIM11_CH3CFG            GPIO_TIM11_CH3OUT
+#  elif CONFIG_STM32F7_TIM11_CHANNEL == 4
+#    define CONFIG_STM32F7_TIM11_CHANNEL4 1
+#    define CONFIG_STM32F7_TIM11_CH4MODE  CONFIG_STM32F7_TIM11_CHMODE
+#    define PWM_TIM11_CH4CFG            GPIO_TIM11_CH4OUT
+#  else
+#    error "Unsupported value of CONFIG_STM32F7_TIM11_CHANNEL"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32F7_TIM12_PWM
+#  if !defined(CONFIG_STM32F7_TIM12_CHANNEL)
+#    error "CONFIG_STM32F7_TIM12_CHANNEL must be provided"
+#  elif CONFIG_STM32F7_TIM12_CHANNEL == 1
+#    define CONFIG_STM32F7_TIM12_CHANNEL1 1
+#    define CONFIG_STM32F7_TIM12_CH1MODE  CONFIG_STM32F7_TIM12_CHMODE
+#    define PWM_TIM12_CH1CFG            GPIO_TIM12_CH1OUT
+#  elif CONFIG_STM32F7_TIM12_CHANNEL == 2
+#    define CONFIG_STM32F7_TIM12_CHANNEL2 1
+#    define CONFIG_STM32F7_TIM12_CH2MODE  CONFIG_STM32F7_TIM12_CHMODE
+#    define PWM_TIM12_CH2CFG            GPIO_TIM12_CH2OUT
+#  elif CONFIG_STM32F7_TIM12_CHANNEL == 3
+#    define CONFIG_STM32F7_TIM12_CHANNEL3 1
+#    define CONFIG_STM32F7_TIM12_CH3MODE  CONFIG_STM32F7_TIM12_CHMODE
+#    define PWM_TIM12_CH3CFG            GPIO_TIM12_CH3OUT
+#  elif CONFIG_STM32F7_TIM12_CHANNEL == 4
+#    define CONFIG_STM32F7_TIM12_CHANNEL4 1
+#    define CONFIG_STM32F7_TIM12_CH4MODE  CONFIG_STM32F7_TIM12_CHMODE
+#    define PWM_TIM12_CH4CFG            GPIO_TIM12_CH4OUT
+#  else
+#    error "Unsupported value of CONFIG_STM32F7_TIM12_CHANNEL"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32F7_TIM13_PWM
+#  if !defined(CONFIG_STM32F7_TIM13_CHANNEL)
+#    error "CONFIG_STM32F7_TIM13_CHANNEL must be provided"
+#  elif CONFIG_STM32F7_TIM13_CHANNEL == 1
+#    define CONFIG_STM32F7_TIM13_CHANNEL1 1
+#    define CONFIG_STM32F7_TIM13_CH1MODE  CONFIG_STM32F7_TIM13_CHMODE
+#    define PWM_TIM13_CH1CFG            GPIO_TIM13_CH1OUT
+#  elif CONFIG_STM32F7_TIM13_CHANNEL == 2
+#    define CONFIG_STM32F7_TIM13_CHANNEL2 1
+#    define CONFIG_STM32F7_TIM13_CH2MODE  CONFIG_STM32F7_TIM13_CHMODE
+#    define PWM_TIM13_CH2CFG            GPIO_TIM13_CH2OUT
+#  elif CONFIG_STM32F7_TIM13_CHANNEL == 3
+#    define CONFIG_STM32F7_TIM13_CHANNEL3 1
+#    define CONFIG_STM32F7_TIM13_CH3MODE  CONFIG_STM32F7_TIM13_CHMODE
+#    define PWM_TIM13_CH3CFG            GPIO_TIM13_CH3OUT
+#  elif CONFIG_STM32F7_TIM13_CHANNEL == 4
+#    define CONFIG_STM32F7_TIM13_CHANNEL4 1
+#    define CONFIG_STM32F7_TIM13_CH4MODE  CONFIG_STM32F7_TIM13_CHMODE
+#    define PWM_TIM13_CH4CFG            GPIO_TIM13_CH4OUT
+#  else
+#    error "Unsupported value of CONFIG_STM32F7_TIM13_CHANNEL"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32F7_TIM14_PWM
+#  if !defined(CONFIG_STM32F7_TIM14_CHANNEL)
+#    error "CONFIG_STM32F7_TIM14_CHANNEL must be provided"
+#  elif CONFIG_STM32F7_TIM14_CHANNEL == 1
+#    define CONFIG_STM32F7_TIM14_CHANNEL1 1
+#    define CONFIG_STM32F7_TIM14_CH1MODE  CONFIG_STM32F7_TIM14_CHMODE
+#    define PWM_TIM14_CH1CFG            GPIO_TIM14_CH1OUT
+#  elif CONFIG_STM32F7_TIM14_CHANNEL == 2
+#    define CONFIG_STM32F7_TIM14_CHANNEL2 1
+#    define CONFIG_STM32F7_TIM14_CH2MODE  CONFIG_STM32F7_TIM14_CHMODE
+#    define PWM_TIM14_CH2CFG            GPIO_TIM14_CH2OUT
+#  elif CONFIG_STM32F7_TIM14_CHANNEL == 3
+#    define CONFIG_STM32F7_TIM14_CHANNEL3 1
+#    define CONFIG_STM32F7_TIM14_CH3MODE  CONFIG_STM32F7_TIM14_CHMODE
+#    define PWM_TIM14_CH3CFG            GPIO_TIM14_CH3OUT
+#  elif CONFIG_STM32F7_TIM14_CHANNEL == 4
+#    define CONFIG_STM32F7_TIM14_CHANNEL4 1
+#    define CONFIG_STM32F7_TIM14_CH4MODE  CONFIG_STM32F7_TIM14_CHMODE
+#    define PWM_TIM14_CH4CFG            GPIO_TIM14_CH4OUT
+#  else
+#    error "Unsupported value of CONFIG_STM32F7_TIM14_CHANNEL"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32F7_TIM15_PWM
+#  if !defined(CONFIG_STM32F7_TIM15_CHANNEL)
+#    error "CONFIG_STM32F7_TIM15_CHANNEL must be provided"
+#  elif CONFIG_STM32F7_TIM15_CHANNEL == 1
+#    define CONFIG_STM32F7_TIM15_CHANNEL1 1
+#    define CONFIG_STM32F7_TIM15_CH1MODE  CONFIG_STM32F7_TIM15_CHMODE
+#    define PWM_TIM15_CH1CFG            GPIO_TIM15_CH1OUT
+#  elif CONFIG_STM32F7_TIM15_CHANNEL == 2
+#    define CONFIG_STM32F7_TIM15_CHANNEL2 1
+#    define CONFIG_STM32F7_TIM15_CH2MODE  CONFIG_STM32F7_TIM15_CHMODE
+#    define PWM_TIM15_CH2CFG            GPIO_TIM15_CH2OUT
+#  else
+#    error "Unsupported value of CONFIG_STM32F7_TIM15_CHANNEL"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32F7_TIM16_PWM
+#  if !defined(CONFIG_STM32F7_TIM16_CHANNEL)
+#    error "CONFIG_STM32F7_TIM16_CHANNEL must be provided"
+#  elif CONFIG_STM32F7_TIM16_CHANNEL == 1
+#    define CONFIG_STM32F7_TIM16_CHANNEL1 1
+#    define CONFIG_STM32F7_TIM16_CH1MODE  CONFIG_STM32F7_TIM16_CHMODE
+#    define PWM_TIM16_CH1CFG            GPIO_TIM16_CH1OUT
+#  else
+#    error "Unsupported value of CONFIG_STM32F7_TIM16_CHANNEL"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32F7_TIM17_PWM
+#  if !defined(CONFIG_STM32F7_TIM17_CHANNEL)
+#    error "CONFIG_STM32F7_TIM17_CHANNEL must be provided"
+#  elif CONFIG_STM32F7_TIM17_CHANNEL == 1
+#    define CONFIG_STM32F7_TIM17_CHANNEL1 1
+#    define CONFIG_STM32F7_TIM17_CH1MODE  CONFIG_STM32F7_TIM17_CHMODE
+#    define PWM_TIM17_CH1CFG            GPIO_TIM17_CH1OUT
+#  else
+#    error "Unsupported value of CONFIG_STM32F7_TIM17_CHANNEL"
+#  endif
+#endif
+
+#define PWM_NCHANNELS 1
+
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_pwminitialize
+ *
+ * Description:
+ *   Initialize one timer for use with the upper_level PWM driver.
+ *
+ * Input Parameters:
+ *   timer - A number identifying the timer use.  The number of valid timer
+ *     IDs varies with the STM32 MCU and MCU family but is somewhere in
+ *     the range of {1,..,17}.
+ *
+ * Returned Value:
+ *   On success, a pointer to the STM32 lower half PWM driver is returned.
+ *   NULL is returned on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_STM32F7_TIMx_PWM */
+#endif /* __ARCH_ARM_SRC_STM32F7_STM32_PWM_H */
diff --git a/arch/arm/src/stm32f7/stm32_pwr.h b/arch/arm/src/stm32f7/stm32_pwr.h
index b332e424a0d..77174a2f65c 100644
--- a/arch/arm/src/stm32f7/stm32_pwr.h
+++ b/arch/arm/src/stm32f7/stm32_pwr.h
@@ -46,7 +46,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_pwr.h"
+#include "hardware/stm32_pwr.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32f7/stm32_qspi.c b/arch/arm/src/stm32f7/stm32_qspi.c
index 63ababa1341..7436390c8c6 100644
--- a/arch/arm/src/stm32f7/stm32_qspi.c
+++ b/arch/arm/src/stm32f7/stm32_qspi.c
@@ -68,7 +68,7 @@
 #include "stm32_gpio.h"
 #include "stm32_dma.h"
 #include "stm32_rcc.h"
-#include "chip/stm32_qspi.h"
+#include "hardware/stm32_qspi.h"
 
 #ifdef CONFIG_STM32F7_QUADSPI
 
diff --git a/arch/arm/src/stm32f7/stm32_qspi.h b/arch/arm/src/stm32f7/stm32_qspi.h
index 65732f2bc23..d63a27fd91c 100644
--- a/arch/arm/src/stm32f7/stm32_qspi.h
+++ b/arch/arm/src/stm32f7/stm32_qspi.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32l4/stm32l4_qspi.h
+ * arch/arm/src/stm32f7/stm32_qspi.h
  *
  *   Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved.
  *   Author: dev@ziggurat29.com
diff --git a/arch/arm/src/stm32f7/stm32_rcc.c b/arch/arm/src/stm32f7/stm32_rcc.c
index 27396e5ecea..a094dab1e8c 100644
--- a/arch/arm/src/stm32f7/stm32_rcc.c
+++ b/arch/arm/src/stm32f7/stm32_rcc.c
@@ -50,7 +50,7 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/stm32_flash.h"
+#include "hardware/stm32_flash.h"
 #include "stm32_gpio.h"
 #include "stm32_rcc.h"
 #include "stm32_pwr.h"
@@ -77,7 +77,7 @@
 /* Include chip-specific clocking initialization logic */
 
 #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
-#  include "chip/stm32f72xx73xx_rcc.c"
+#  include "stm32f72xx73xx_rcc.c"
 #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
 #  include "stm32f74xx75xx_rcc.c"
 #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
diff --git a/arch/arm/src/stm32f7/stm32_rcc.h b/arch/arm/src/stm32f7/stm32_rcc.h
index 073b972958f..b1c704afa3e 100644
--- a/arch/arm/src/stm32f7/stm32_rcc.h
+++ b/arch/arm/src/stm32f7/stm32_rcc.h
@@ -44,7 +44,7 @@
 
 #include "up_arch.h"
 
-#include "chip/stm32_rcc.h"
+#include "hardware/stm32_rcc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32f7/stm32_rng.c b/arch/arm/src/stm32f7/stm32_rng.c
index 854b5ba276b..947088cdf68 100644
--- a/arch/arm/src/stm32f7/stm32_rng.c
+++ b/arch/arm/src/stm32f7/stm32_rng.c
@@ -52,7 +52,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/stm32_rng.h"
+#include "hardware/stm32_rng.h"
 #include "up_internal.h"
 
 #if defined(CONFIG_STM32F7_RNG)
@@ -90,17 +90,15 @@ static struct rng_dev_s g_rngdev;
 
 static const struct file_operations g_rngops =
 {
-  0,               /* open */
-  0,               /* close */
+  NULL,            /* open */
+  NULL,            /* close */
   stm32_rngread,   /* read */
-  0,               /* write */
-  0,               /* seek */
-  0                /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0              /* poll */
-#endif
+  NULL,            /* write */
+  NULL,            /* seek */
+  NULL,            /* ioctl */
+  NULL             /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
-  , 0              /* unlink */
+  , NULL           /* unlink */
 #endif
 };
 
diff --git a/arch/arm/src/stm32f7/stm32_rtc.h b/arch/arm/src/stm32f7/stm32_rtc.h
index 8244e4c8d48..959aeead927 100644
--- a/arch/arm/src/stm32f7/stm32_rtc.h
+++ b/arch/arm/src/stm32f7/stm32_rtc.h
@@ -52,7 +52,7 @@
  * the RTCC in these families.
  */
 
-#include "chip/stm32_rtcc.h"
+#include "hardware/stm32_rtcc.h"
 #include "stm32_alarm.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.h b/arch/arm/src/stm32f7/stm32_sdmmc.h
index 095af548052..0d79a297ade 100644
--- a/arch/arm/src/stm32f7/stm32_sdmmc.h
+++ b/arch/arm/src/stm32f7/stm32_sdmmc.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_sdmmc.h"
+#include "hardware/stm32_sdmmc.h"
 
 
 /************************************************************************************
diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c
index a57db4aa221..cdf924ea093 100644
--- a/arch/arm/src/stm32f7/stm32_serial.c
+++ b/arch/arm/src/stm32f7/stm32_serial.c
@@ -64,7 +64,7 @@
 
 #include "chip.h"
 #include "stm32_gpio.h"
-#include "chip/stm32_pinmap.h"
+#include "hardware/stm32_pinmap.h"
 #include "stm32_dma.h"
 #include "stm32_rcc.h"
 #include "stm32_uart.h"
diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c
index d0c9da5fb1a..67c81266ec1 100644
--- a/arch/arm/src/stm32f7/stm32_spi.c
+++ b/arch/arm/src/stm32f7/stm32_spi.c
@@ -1680,7 +1680,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
   if ((priv->rxdma == NULL) || (priv->txdma == NULL) ||
       (txbuffer && !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) ||
       (rxbuffer && !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr)) ||
-      up_interrupt_context())
+      up_interrupt_context() || nwords < CONFIG_STM32F7_SPI_DMA_THRESHOLD)
     {
       /* Invalid DMA channels, unsupported memory region, or interrupt context, fall back to non-DMA method. */
 
diff --git a/arch/arm/src/stm32f7/stm32_spi.h b/arch/arm/src/stm32f7/stm32_spi.h
index f8c1ee9a1fc..094c1a67d05 100644
--- a/arch/arm/src/stm32f7/stm32_spi.h
+++ b/arch/arm/src/stm32f7/stm32_spi.h
@@ -46,7 +46,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_spi.h"
+#include "hardware/stm32_spi.h"
 
 /************************************************************************************
  * Public Functions
diff --git a/arch/arm/src/stm32f7/stm32_tickless.c b/arch/arm/src/stm32f7/stm32_tickless.c
new file mode 100644
index 00000000000..734a0800a28
--- /dev/null
+++ b/arch/arm/src/stm32f7/stm32_tickless.c
@@ -0,0 +1,1023 @@
+/****************************************************************************
+ * arch/arm/src/stm32/stm32_tickless.c
+ *
+ *   Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2017 Ansync Labs. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *            Konstantin Berezenko 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+/****************************************************************************
+ * Tickless OS Support.
+ *
+ * When CONFIG_SCHED_TICKLESS is enabled, all support for timer interrupts
+ * is suppressed and the platform specific code is expected to provide the
+ * following custom functions.
+ *
+ *   void arm_timer_initialize(void): Initializes the timer facilities.
+ *     Called early in the initialization sequence (by up_intialize()).
+ *   int up_timer_gettime(FAR struct timespec *ts):  Returns the current
+ *     time from the platform specific time source.
+ *   int up_timer_cancel(void):  Cancels the interval timer.
+ *   int up_timer_start(FAR const struct timespec *ts): Start (or re-starts)
+ *     the interval timer.
+ *
+ * The RTOS will provide the following interfaces for use by the platform-
+ * specific interval timer implementation:
+ *
+ *   void nxsched_timer_expiration(void):  Called by the platform-specific
+ *     logic when the interval timer expires.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * STM32 Timer Usage
+ *
+ * This implementation uses one timer:  A free running timer to provide
+ * the current time and a capture/compare channel for timed-events.
+ *
+ * BASIC timers that are found on some STM32 chips (timers 6 and 7) are
+ * incompatible with this implementation because they don't have capture/
+ * compare channels.  There are two interrupts generated from our timer,
+ * the overflow interrupt which drives the timing handler and the capture/
+ * compare interrupt which drives the interval handler.  There are some low
+ * level timer control functions implemented here because the API of
+ * stm32_tim.c does not provide adequate control over capture/compare
+ * interrupts.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "up_arch.h"
+
+#include "stm32_tim.h"
+#include "stm32_dbgmcu.h"
+
+#ifdef CONFIG_SCHED_TICKLESS
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Only TIM2 and TIM5 timers may be 32-bits in width
+ *
+ * Reference Table 2 of en.DM00042534.pdf
+ */
+
+#undef HAVE_32BIT_TICKLESS
+
+#if (CONFIG_STM32F7_TICKLESS_TIMER == 2) || \
+    (CONFIG_STM32F7_TICKLESS_TIMER == 5)
+ #define HAVE_32BIT_TICKLESS 1
+#endif
+
+#if CONFIG_STM32F7_TICKLESS_CHANNEL == 1
+#define DIER_CAPT_IE          ATIM_DIER_CC1IE
+#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 2
+#define DIER_CAPT_IE          ATIM_DIER_CC2IE
+#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 3
+#define DIER_CAPT_IE          ATIM_DIER_CC3IE
+#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 4
+#define DIER_CAPT_IE          ATIM_DIER_CC4IE
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct stm32_tickless_s
+{
+  uint8_t timer;                   /* The timer/counter in use */
+  uint8_t channel;                 /* The timer channel to use for intervals */
+  FAR struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */
+  uint32_t frequency;
+#ifdef CONFIG_CLOCK_TIMEKEEPING
+  uint64_t counter_mask;
+#else
+  uint32_t overflow;               /* Timer counter overflow */
+#endif
+  volatile bool pending;           /* True: pending task */
+  uint32_t period;                 /* Interval period */
+  uint32_t base;
+#if CONFIG_SCHED_TICKLESS_ALARM
+  uint64_t last_alrm;
+#endif
+};
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static struct stm32_tickless_s g_tickless;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_getreg16
+ *
+ * Description:
+ *   Get a 16-bit register value by offset
+ *
+ ****************************************************************************/
+
+static inline uint16_t stm32_getreg16(uint8_t offset)
+{
+  return getreg16(g_tickless.base + offset);
+}
+
+/****************************************************************************
+ * Name: stm32_putreg16
+ *
+ * Description:
+ *   Put a 16-bit register value by offset
+ *
+ ****************************************************************************/
+
+static inline void stm32_putreg16(uint8_t offset, uint16_t value)
+{
+  putreg16(value, g_tickless.base + offset);
+}
+
+/****************************************************************************
+ * Name: stm32_modifyreg16
+ *
+ * Description:
+ *   Modify a 16-bit register value by offset
+ *
+ ****************************************************************************/
+
+static inline void stm32_modifyreg16(uint8_t offset, uint16_t clearbits,
+                                     uint16_t setbits)
+{
+  modifyreg16(g_tickless.base + offset, clearbits, setbits);
+}
+
+/****************************************************************************
+ * Name: stm32_tickless_enableint
+ ****************************************************************************/
+
+static inline void stm32_tickless_enableint(int channel)
+{
+  stm32_modifyreg16(STM32_BTIM_DIER_OFFSET, 0, 1 << channel);
+}
+
+/****************************************************************************
+ * Name: stm32_tickless_disableint
+ ****************************************************************************/
+
+static inline void stm32_tickless_disableint(int channel)
+{
+  stm32_modifyreg16(STM32_BTIM_DIER_OFFSET, 1 << channel, 0);
+}
+
+/****************************************************************************
+ * Name: stm32_tickless_ackint
+ ****************************************************************************/
+
+static inline void stm32_tickless_ackint(int channel)
+{
+  stm32_putreg16(STM32_BTIM_SR_OFFSET, ~(1 << channel));
+}
+
+/****************************************************************************
+ * Name: stm32_tickless_getint
+ ******************************************************************************/
+
+static inline uint16_t stm32_tickless_getint(void)
+{
+  return stm32_getreg16(STM32_BTIM_SR_OFFSET);
+}
+
+/****************************************************************************
+ * Name: stm32_tickless_setchannel
+ ****************************************************************************/
+
+static int stm32_tickless_setchannel(uint8_t channel)
+{
+  uint16_t ccmr_orig   = 0;
+  uint16_t ccmr_val    = 0;
+  uint16_t ccmr_mask   = 0xff;
+  uint16_t ccer_val    = stm32_getreg16(STM32_GTIM_CCER_OFFSET);
+  uint8_t  ccmr_offset = STM32_GTIM_CCMR1_OFFSET;
+
+  /* Further we use range as 0..3; if channel=0 it will also overflow here */
+
+  if (--channel > 4)
+    {
+      return -EINVAL;
+    }
+
+  /* Assume that channel is disabled and polarity is active high */
+
+  ccer_val &= ~(3 << (channel << 2));
+
+  /* This function is not supported on basic timers. To enable or
+   * disable it, simply set its clock to valid frequency or zero.
+   */
+
+  if (g_tickless.base == STM32_TIM6_BASE ||
+      g_tickless.base == STM32_TIM7_BASE)
+    {
+      return -EINVAL;
+    }
+
+  /* Frozen mode because we don't want to change the GPIO, preload register
+   * disabled.
+   */
+
+  ccmr_val = (ATIM_CCMR_MODE_FRZN << ATIM_CCMR1_OC1M_SHIFT);
+
+  /* Set polarity */
+
+  ccer_val |= ATIM_CCER_CC1P << (channel << 2);
+
+  /* Define its position (shift) and get register offset */
+
+  if ((channel & 1) != 0)
+    {
+      ccmr_val  <<= 8;
+      ccmr_mask <<= 8;
+    }
+
+  if (channel > 1)
+    {
+      ccmr_offset = STM32_GTIM_CCMR2_OFFSET;
+    }
+
+  ccmr_orig  = stm32_getreg16(ccmr_offset);
+  ccmr_orig &= ~ccmr_mask;
+  ccmr_orig |= ccmr_val;
+  stm32_putreg16(ccmr_offset, ccmr_orig);
+  stm32_putreg16(STM32_GTIM_CCER_OFFSET, ccer_val);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32_interval_handler
+ *
+ * Description:
+ *   Called when the timer counter matches the compare register
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Called early in the initialization sequence before any special
+ *   concurrency protections are required.
+ *
+ ****************************************************************************/
+
+static void stm32_interval_handler(void)
+{
+#ifdef CONFIG_SCHED_TICKLESS_ALARM
+  struct timespec tv;
+#endif
+  tmrinfo("Expired...\n");
+
+  /* Disable the compare interrupt now. */
+
+  stm32_tickless_disableint(g_tickless.channel);
+  stm32_tickless_ackint(g_tickless.channel);
+
+  g_tickless.pending = false;
+
+#ifndef CONFIG_SCHED_TICKLESS_ALARM
+  nxsched_timer_expiration();
+#else
+  up_timer_gettime(&tv);
+  nxsched_alarm_expiration(&tv);
+#endif
+}
+
+/****************************************************************************
+ * Name: stm32_timing_handler
+ *
+ * Description:
+ *   Timer interrupt callback.  When the freerun timer counter overflows,
+ *   this interrupt will occur.  We will just increment an overflow count.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_CLOCK_TIMEKEEPING
+static void stm32_timing_handler(void)
+{
+  g_tickless.overflow++;
+
+  STM32_TIM_ACKINT(g_tickless.tch, 0);
+}
+#endif /* CONFIG_CLOCK_TIMEKEEPING */
+
+/****************************************************************************
+ * Name: stm32_tickless_handler
+ *
+ * Description:
+ *   Generic interrupt handler for this timer.  It checks the source of the
+ *   interrupt and fires the appropriate handler.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static int stm32_tickless_handler(int irq, void *context, void *arg)
+{
+  int interrupt_flags = stm32_tickless_getint();
+
+#ifndef CONFIG_CLOCK_TIMEKEEPING
+  if (interrupt_flags & ATIM_SR_UIF)
+    {
+      stm32_timing_handler();
+    }
+#endif /* CONFIG_CLOCK_TIMEKEEPING */
+
+  if (interrupt_flags & (1 << g_tickless.channel))
+    {
+      stm32_interval_handler();
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_timer_initialize
+ *
+ * Description:
+ *   Initializes all platform-specific timer facilities.  This function is
+ *   called early in the initialization sequence by up_intialize().
+ *   On return, the current up-time should be available from
+ *   up_timer_gettime() and the interval timer is ready for use (but not
+ *   actively timing.
+ *
+ *   Provided by platform-specific code and called from the architecture-
+ *   specific logic.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Called early in the initialization sequence before any special
+ *   concurrency protections are required.
+ *
+ ****************************************************************************/
+
+void arm_timer_initialize(void)
+{
+  switch (CONFIG_STM32F7_TICKLESS_TIMER)
+    {
+#ifdef CONFIG_STM32F7_TIM1
+      case 1:
+        g_tickless.base = STM32_TIM1_BASE;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM2
+      case 2:
+        g_tickless.base = STM32_TIM2_BASE;
+        modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM2STOP);
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM3
+      case 3:
+        g_tickless.base = STM32_TIM3_BASE;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM4
+      case 4:
+        g_tickless.base = STM32_TIM4_BASE;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM5
+      case 5:
+        g_tickless.base = STM32_TIM5_BASE;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM6
+      case 6:
+
+        /* Basic timers not supported by this implementation */
+
+        DEBUGASSERT(0);
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM7
+      case 7:
+
+        /* Basic timers not supported by this implementation */
+
+        DEBUGASSERT(0);
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM8
+      case 8:
+        g_tickless.base = STM32_TIM8_BASE;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM9
+      case 9:
+        g_tickless.base = STM32_TIM9_BASE;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM10
+      case 10:
+        g_tickless.base = STM32_TIM10_BASE;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM11
+      case 11:
+        g_tickless.base = STM32_TIM11_BASE;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM12
+      case 12:
+        g_tickless.base = STM32_TIM12_BASE;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM13
+      case 13:
+        g_tickless.base = STM32_TIM13_BASE;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM14
+      case 14:
+        g_tickless.base = STM32_TIM14_BASE;
+        break;
+#endif
+#ifdef CONFIG_STM32F7_TIM15
+      case 15:
+        g_tickless.base = STM32_TIM15_BASE;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM16
+      case 16:
+        g_tickless.base = STM32_TIM16_BASE;
+        break;
+#endif
+
+#ifdef CONFIG_STM32F7_TIM17
+      case 17:
+        g_tickless.base = STM32_TIM17_BASE;
+        break;
+#endif
+
+      default:
+        DEBUGASSERT(0);
+    }
+
+  /* Get the TC frequency that corresponds to the requested resolution */
+
+  g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK;
+  g_tickless.timer     = CONFIG_STM32F7_TICKLESS_TIMER;
+  g_tickless.channel   = CONFIG_STM32F7_TICKLESS_CHANNEL;
+  g_tickless.pending   = false;
+  g_tickless.period    = 0;
+
+  tmrinfo("timer=%d channel=%d frequency=%d Hz\n",
+           g_tickless.timer, g_tickless.channel, g_tickless.frequency);
+
+  g_tickless.tch = stm32_tim_init(g_tickless.timer);
+  if (!g_tickless.tch)
+    {
+      tmrerr("ERROR: Failed to allocate TIM%d\n", g_tickless.timer);
+      DEBUGASSERT(0);
+    }
+
+  STM32_TIM_SETCLOCK(g_tickless.tch, g_tickless.frequency);
+
+#ifdef CONFIG_CLOCK_TIMEKEEPING
+
+  /* Should this be changed to 0xffff because we use 16 bit timers? */
+
+  g_tickless.counter_mask = 0xffffffffull;
+#else
+  g_tickless.overflow     = 0;
+
+  /* Set up to receive the callback when the counter overflow occurs */
+
+  STM32_TIM_SETISR(g_tickless.tch, stm32_tickless_handler, NULL, 0);
+#endif
+
+  /* Initialize interval to zero */
+
+  STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, 0);
+
+  /* Setup compare channel for the interval timing */
+
+  stm32_tickless_setchannel(g_tickless.channel);
+
+  /* Set timer period */
+
+#ifdef HAVE_32BIT_TICKLESS
+  STM32_TIM_SETPERIOD(g_tickless.tch, UINT32_MAX);
+#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP
+  g_oneshot_maxticks = UINT32_MAX;
+#endif
+#else
+  STM32_TIM_SETPERIOD(g_tickless.tch, UINT16_MAX);
+#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP
+  g_oneshot_maxticks = UINT16_MAX;
+#endif
+#endif
+
+  /* Initialize the counter */
+
+  STM32_TIM_SETMODE(g_tickless.tch, STM32_TIM_MODE_UP);
+
+  /* Start the timer */
+
+  STM32_TIM_ACKINT(g_tickless.tch, 0);
+  STM32_TIM_ENABLEINT(g_tickless.tch, 0);
+}
+
+/****************************************************************************
+ * Name: up_timer_gettime
+ *
+ * Description:
+ *   Return the elapsed time since power-up (or, more correctly, since
+ *   arm_timer_initialize() was called).  This function is functionally
+ *   equivalent to:
+ *
+ *      int clock_gettime(clockid_t clockid, FAR struct timespec *ts);
+ *
+ *   when clockid is CLOCK_MONOTONIC.
+ *
+ *   This function provides the basis for reporting the current time and
+ *   also is used to eliminate error build-up from small errors in interval
+ *   time calculations.
+ *
+ *   Provided by platform-specific code and called from the RTOS base code.
+ *
+ * Input Parameters:
+ *   ts - Provides the location in which to return the up-time.
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure.
+ *
+ * Assumptions:
+ *   Called from the normal tasking context.  The implementation must
+ *   provide whatever mutual exclusion is necessary for correct operation.
+ *   This can include disabling interrupts in order to assure atomic register
+ *   operations.
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_CLOCK_TIMEKEEPING
+int up_timer_gettime(FAR struct timespec *ts)
+{
+  uint64_t usec;
+  uint32_t counter;
+  uint32_t verify;
+  uint32_t overflow;
+  uint32_t sec;
+  int pending;
+  irqstate_t flags;
+
+  DEBUGASSERT(ts);
+
+  /* Timer not initialized yet, return zero */
+
+  if (g_tickless.tch == 0)
+    {
+      ts->tv_nsec = 0;
+      ts->tv_sec  = 0;
+      return OK;
+    }
+
+  /* Temporarily disable the overflow counter.  NOTE that we have to be
+   * careful here because  stm32_tc_getpending() will reset the pending
+   * interrupt status.  If we do not handle the overflow here then, it will
+   * be lost.
+   */
+
+  flags    = enter_critical_section();
+
+  overflow = g_tickless.overflow;
+  counter  = STM32_TIM_GETCOUNTER(g_tickless.tch);
+  pending  = STM32_TIM_CHECKINT(g_tickless.tch, 0);
+  verify   = STM32_TIM_GETCOUNTER(g_tickless.tch);
+
+  /* If an interrupt was pending before we re-enabled interrupts,
+   * then the overflow needs to be incremented.
+   */
+
+  if (pending)
+    {
+      STM32_TIM_ACKINT(g_tickless.tch, 0);
+
+      /* Increment the overflow count and use the value of the
+       * guaranteed to be AFTER the overflow occurred.
+       */
+
+      overflow++;
+      counter = verify;
+
+      /* Update tickless overflow counter. */
+
+      g_tickless.overflow = overflow;
+    }
+
+  leave_critical_section(flags);
+
+  tmrinfo("counter=%lu (%lu) overflow=%lu, pending=%i\n",
+         (unsigned long)counter,  (unsigned long)verify,
+         (unsigned long)overflow, pending);
+  tmrinfo("frequency=%u\n", g_tickless.frequency);
+
+  /* Convert the whole thing to units of microseconds.
+   *
+   *   frequency = ticks / second
+   *   seconds   = ticks * frequency
+   *   usecs     = (ticks * USEC_PER_SEC) / frequency;
+   */
+#ifdef HAVE_32BIT_TICKLESS
+  usec = ((((uint64_t)overflow << 32) + (uint64_t)counter) * USEC_PER_SEC) /
+         g_tickless.frequency;
+#else
+  usec = ((((uint64_t)overflow << 16) + (uint64_t)counter) * USEC_PER_SEC) /
+         g_tickless.frequency;
+#endif
+
+  /* And return the value of the timer */
+
+  sec         = (uint32_t)(usec / USEC_PER_SEC);
+  ts->tv_sec  = sec;
+  ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC;
+
+  tmrinfo("usec=%llu ts=(%u, %lu)\n",
+          usec, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
+
+  return OK;
+}
+
+#else
+
+int up_timer_getcounter(FAR uint64_t *cycles)
+{
+  *cycles = (uint64_t)STM32_TIM_GETCOUNTER(g_tickless.tch);
+  return OK;
+}
+
+#endif /* CONFIG_CLOCK_TIMEKEEPING */
+
+/****************************************************************************
+ * Name: up_timer_getmask
+ *
+ * Description:
+ *   To be provided
+ *
+ * Input Parameters:
+ *   mask - Location to return the 64-bit mask
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_CLOCK_TIMEKEEPING
+void up_timer_getmask(FAR uint64_t *mask)
+{
+  DEBUGASSERT(mask != NULL);
+  *mask = g_tickless.counter_mask;
+}
+#endif /* CONFIG_CLOCK_TIMEKEEPING */
+
+/****************************************************************************
+ * Name: up_timer_cancel
+ *
+ * Description:
+ *   Cancel the interval timer and return the time remaining on the timer.
+ *   These two steps need to be as nearly atomic as possible.
+ *   nxsched_timer_expiration() will not be called unless the timer is
+ *   restarted with up_timer_start().
+ *
+ *   If, as a race condition, the timer has already expired when this
+ *   function is called, then that pending interrupt must be cleared so
+ *   that up_timer_start() and the remaining time of zero should be
+ *   returned.
+ *
+ *   NOTE: This function may execute at a high rate with no timer running (as
+ *   when pre-emption is enabled and disabled).
+ *
+ *   Provided by platform-specific code and called from the RTOS base code.
+ *
+ * Input Parameters:
+ *   ts - Location to return the remaining time.  Zero should be returned
+ *        if the timer is not active.  ts may be zero in which case the
+ *        time remaining is not returned.
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success.  A call to up_timer_cancel() when
+ *   the timer is not active should also return success; a negated errno
+ *   value is returned on any failure.
+ *
+ * Assumptions:
+ *   May be called from interrupt level handling or from the normal tasking
+ *   level.  Interrupts may need to be disabled internally to assure
+ *   non-reentrancy.
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SCHED_TICKLESS_ALARM
+int up_timer_cancel(FAR struct timespec *ts)
+{
+  irqstate_t flags;
+  uint64_t usec;
+  uint64_t sec;
+  uint64_t nsec;
+  uint32_t count;
+  uint32_t period;
+
+  /* Was the timer running? */
+
+  flags = enter_critical_section();
+  if (!g_tickless.pending)
+    {
+      /* No.. Just return zero timer remaining and successful cancellation.
+       * This function may execute at a high rate with no timer running
+       * (as when pre-emption is enabled and disabled).
+       */
+
+      if (ts)
+        {
+          ts->tv_sec  = 0;
+          ts->tv_nsec = 0;
+        }
+
+      leave_critical_section(flags);
+      return OK;
+    }
+
+  /* Yes.. Get the timer counter and period registers and disable the compare
+   * interrupt.
+   */
+
+  tmrinfo("Cancelling...\n");
+
+  /* Disable the interrupt. */
+
+  stm32_tickless_disableint(g_tickless.channel);
+
+  count  = STM32_TIM_GETCOUNTER(g_tickless.tch);
+  period = g_tickless.period;
+
+  g_tickless.pending = false;
+  leave_critical_section(flags);
+
+  /* Did the caller provide us with a location to return the time
+   * remaining?
+   */
+
+  if (ts != NULL)
+    {
+      /* Yes.. then calculate and return the time remaining on the
+       * oneshot timer.
+       */
+
+      tmrinfo("period=%lu count=%lu\n",
+             (unsigned long)period, (unsigned long)count);
+
+#ifndef HAVE_32BIT_TICKLESS
+      if (count > period)
+        {
+          /* Handle rollover */
+
+          period += UINT16_MAX;
+        }
+      else if (count == period)
+#else
+      if (count >= period)
+#endif
+        {
+          /* No time remaining */
+
+          ts->tv_sec  = 0;
+          ts->tv_nsec = 0;
+          return OK;
+        }
+
+      /* The total time remaining is the difference.  Convert that
+       * to units of microseconds.
+       *
+       *   frequency = ticks / second
+       *   seconds   = ticks * frequency
+       *   usecs     = (ticks * USEC_PER_SEC) / frequency;
+       */
+
+      usec        = (((uint64_t)(period - count)) * USEC_PER_SEC) /
+                    g_tickless.frequency;
+
+      /* Return the time remaining in the correct form */
+
+      sec         = usec / USEC_PER_SEC;
+      nsec        = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC;
+
+      ts->tv_sec  = (time_t)sec;
+      ts->tv_nsec = (unsigned long)nsec;
+
+      tmrinfo("remaining (%lu, %lu)\n",
+             (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
+    }
+
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: up_timer_start
+ *
+ * Description:
+ *   Start the interval timer.  nxsched_timer_expiration() will be
+ *   called at the completion of the timeout (unless up_timer_cancel
+ *   is called to stop the timing.
+ *
+ *   Provided by platform-specific code and called from the RTOS base code.
+ *
+ * Input Parameters:
+ *   ts - Provides the time interval until nxsched_timer_expiration() is
+ *        called.
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure.
+ *
+ * Assumptions:
+ *   May be called from interrupt level handling or from the normal tasking
+ *   level.  Interrupts may need to be disabled internally to assure
+ *   non-reentrancy.
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_SCHED_TICKLESS_ALARM
+int up_timer_start(FAR const struct timespec *ts)
+{
+  uint64_t usec;
+  uint64_t period;
+  uint32_t count;
+  irqstate_t flags;
+
+  tmrinfo("ts=(%lu, %lu)\n",
+          (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
+  DEBUGASSERT(ts);
+  DEBUGASSERT(g_tickless.tch);
+
+  /* Was an interval already running? */
+
+  flags = enter_critical_section();
+  if (g_tickless.pending)
+    {
+      /* Yes.. then cancel it */
+
+      tmrinfo("Already running... cancelling\n");
+      (void)up_timer_cancel(NULL);
+    }
+
+  /* Express the delay in microseconds */
+
+  usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
+         (uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
+
+  /* Get the timer counter frequency and determine the number of counts need
+   * to achieve the requested delay.
+   *
+   *   frequency = ticks / second
+   *   ticks     = seconds * frequency
+   *             = (usecs * frequency) / USEC_PER_SEC;
+   */
+
+  period = (usec * (uint64_t)g_tickless.frequency) / USEC_PER_SEC;
+  count  = STM32_TIM_GETCOUNTER(g_tickless.tch);
+
+  tmrinfo("usec=%llu period=%08llx\n", usec, period);
+
+  /* Set interval compare value. Rollover is fine,
+   * channel will trigger on the next period.
+   */
+
+#ifdef HAVE_32BIT_TICKLESS
+  DEBUGASSERT(period <= UINT32_MAX);
+  g_tickless.period = (uint32_t)(period + count);
+#else
+  DEBUGASSERT(period <= UINT16_MAX);
+  g_tickless.period = (uint16_t)(period + count);
+#endif
+
+  STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel,
+                       g_tickless.period);
+
+  /* Enable interrupts.  We should get the callback when the interrupt
+   * occurs.
+   */
+
+  stm32_tickless_ackint(g_tickless.channel);
+  stm32_tickless_enableint(g_tickless.channel);
+
+  g_tickless.pending = true;
+  leave_critical_section(flags);
+  return OK;
+}
+#endif
+
+int up_alarm_start(FAR const struct timespec *ts)
+{
+  uint64_t tm = ((uint64_t)ts->tv_sec * NSEC_PER_SEC + ts->tv_nsec) /
+                NSEC_PER_TICK;
+  uint64_t counter = ((uint64_t)g_tickless.overflow << 32) |
+                     STM32_TIM_GETCOUNTER(g_tickless.tch);
+
+  g_tickless.last_alrm = tm;
+
+  int32_t diff = tm / NSEC_PER_TICK + counter;
+
+  STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32F7_TICKLESS_CHANNEL, tm);
+
+  stm32_tickless_ackint(g_tickless.channel);
+  stm32_tickless_enableint(CONFIG_STM32F7_TICKLESS_CHANNEL);
+
+  return OK;
+}
+
+int up_alarm_cancel(FAR struct timespec *ts)
+{
+  uint64_t nsecs = (((uint64_t)g_tickless.overflow << 32) |
+                    STM32_TIM_GETCOUNTER(g_tickless.tch)) * NSEC_PER_TICK;
+
+  ts->tv_sec = nsecs / NSEC_PER_SEC;
+  ts->tv_nsec = nsecs - ts->tv_sec * NSEC_PER_SEC;
+
+  stm32_tickless_disableint(CONFIG_STM32F7_TICKLESS_CHANNEL);
+
+  return 0;
+}
+
+#endif /* CONFIG_SCHED_TICKLESS */
diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c
index 2f536543a13..8ad9fd1f8d7 100644
--- a/arch/arm/src/stm32f7/stm32_tim.c
+++ b/arch/arm/src/stm32f7/stm32_tim.c
@@ -66,24 +66,27 @@
 /************************************************************************************
  * Private Types
  ************************************************************************************/
+
 /* Configuration ********************************************************************/
+
 /* Timer devices may be used for different purposes.  Such special purposes include:
  *
- * - To generate modulated outputs for such things as motor control.  If CONFIG_STM32F7_TIMn
- *   is defined then the CONFIG_STM32F7_TIMn_PWM may also be defined to indicate that
- *   the timer is intended to be used for pulsed output modulation.
+ * - To generate modulated outputs for such things as motor control.  If
+ *   CONFIG_STM32F7_TIMn is defined then the CONFIG_STM32F7_TIMn_PWM may also be
+ *   defined to indicate that the timer is intended to be used for pulsed output
+ *   modulation.
  *
  * - To control periodic ADC input sampling.  If CONFIG_STM32F7_TIMn is defined then
- *   CONFIG_STM32F7_TIMn_ADC may also be defined to indicate that timer "n" is intended
- *   to be used for that purpose.
+ *   CONFIG_STM32F7_TIMn_ADC may also be defined to indicate that timer "n" is
+ *   intended to be used for that purpose.
  *
  * - To control periodic DAC outputs.  If CONFIG_STM32F7_TIMn is defined then
- *   CONFIG_STM32F7_TIMn_DAC may also be defined to indicate that timer "n" is intended
- *   to be used for that purpose.
+ *   CONFIG_STM32F7_TIMn_DAC may also be defined to indicate that timer "n" is
+ *   intended to be used for that purpose.
  *
  * - To use a Quadrature Encoder.  If CONFIG_STM32F7_TIMn is defined then
- *   CONFIG_STM32F7_TIMn_QE may also be defined to indicate that timer "n" is intended
- *   to be used for that purpose.
+ *   CONFIG_STM32F7_TIMn_QE may also be defined to indicate that timer "n" is
+ *   intended to be used for that purpose.
  *
  * In any of these cases, the timer will not be used by this timer module.
  */
@@ -228,9 +231,8 @@
 #endif
 #endif
 
-
-/* This module then only compiles if there are enabled timers that are not intended for
- * some other purpose.
+/* This module then only compiles if there are enabled timers that are not
+ * intended for some other purpose.
  */
 
 #if defined(CONFIG_STM32F7_TIM1)  || defined(CONFIG_STM32F7_TIM2)  || \
@@ -325,6 +327,70 @@ static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev)
   stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
 }
 
+/************************************************************************************
+ * Name: stm32_tim_getwidth
+ ************************************************************************************/
+
+static int stm32_tim_getwidth(FAR struct stm32_tim_dev_s *dev)
+{
+  /* Only TIM2 and TIM5 timers may be 32-bits in width
+   *
+   * Reference Table 2 of en.DM00042534.pdf
+   */
+
+  switch (((struct stm32_tim_priv_s *)dev)->base)
+    {
+      /* TIM2 is 32-bits on all except F10x, L0x, and L1x lines */
+
+#if defined(CONFIG_STM32F7_TIM2)
+      case STM32_TIM2_BASE:
+        return 32;
+#endif
+
+      /* TIM5 is 32-bits on all except F10x lines */
+
+#if defined(CONFIG_STM32F7_TIM5)
+      case STM32_TIM5_BASE:
+        return 32;
+#endif
+
+      /* All others are 16-bit times */
+
+      default:
+        return 16;
+    }
+}
+
+/************************************************************************************
+ * Name: stm32_tim_getcounter
+ ************************************************************************************/
+
+static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev)
+{
+  DEBUGASSERT(dev != NULL);
+  return stm32_tim_getwidth(dev) > 16 ?
+    stm32_getreg32(dev, STM32_BTIM_CNT_OFFSET) :
+    (uint32_t)stm32_getreg16(dev, STM32_BTIM_CNT_OFFSET);
+}
+
+/************************************************************************************
+ * Name: stm32_tim_setcounter
+ ************************************************************************************/
+
+static void stm32_tim_setcounter(FAR struct stm32_tim_dev_s *dev, uint32_t count)
+{
+  DEBUGASSERT(dev != NULL);
+
+  if (stm32_tim_getwidth(dev) > 16)
+    {
+      stm32_putreg32(dev, STM32_BTIM_CNT_OFFSET, count);
+    }
+  else
+    {
+      stm32_putreg16(dev, STM32_BTIM_CNT_OFFSET, (uint16_t)count);
+    }
+}
+
 /* Reset timer into system default state, but do not affect output/input pins */
 
 static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev)
@@ -601,6 +667,12 @@ static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source)
   stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0);
 }
 
+static int stm32_tim_checkint(FAR struct stm32_tim_dev_s *dev, int source)
+{
+  uint16_t regval = stm32_getreg16(dev, STM32_BTIM_SR_OFFSET);
+  return (regval & source) ? 1 : 0;
+}
+
 static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source)
 {
   stm32_putreg16(dev, STM32_BTIM_SR_OFFSET, ~ATIM_SR_UIF);
@@ -641,8 +713,9 @@ static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t m
         break;
 
       case STM32_TIM_MODE_UPDOWN:
+        /* Our default: Interrupts are generated on compare, when counting down */
+
         val |= ATIM_CR1_CENTER1;
-        // Our default: Interrupts are generated on compare, when counting down
         break;
 
       case STM32_TIM_MODE_PULSE:
@@ -699,7 +772,6 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
       return -EINVAL;
     }
 
-
   /* Decode configuration */
 
   switch (mode & STM32_TIM_CH_MODE_MASK)
@@ -708,12 +780,14 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
         break;
 
       case STM32_TIM_CH_OUTPWM:
-        ccmr_val  =  (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + ATIM_CCMR1_OC1PE;
+        ccmr_val  = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) +
+                     ATIM_CCMR1_OC1PE;
         ccer_val |= ATIM_CCER_CC1E << (channel << 2);
         break;
 
       case STM32_TIM_CH_OUTTOGGLE:
-          ccmr_val  =  (ATIM_CCMR_MODE_OCREFTOG << ATIM_CCMR1_OC1M_SHIFT) + ATIM_CCMR1_OC1PE;
+          ccmr_val  = (ATIM_CCMR_MODE_OCREFTOG << ATIM_CCMR1_OC1M_SHIFT) +
+                       ATIM_CCMR1_OC1PE;
           ccer_val |= ATIM_CCER_CC1E << (channel << 2);
           break;
 
@@ -1151,16 +1225,20 @@ static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel
 
 struct stm32_tim_ops_s stm32_tim_ops =
 {
-  .setmode        = &stm32_tim_setmode,
-  .setclock       = &stm32_tim_setclock,
-  .setperiod      = &stm32_tim_setperiod,
-  .setchannel     = &stm32_tim_setchannel,
-  .setcompare     = &stm32_tim_setcompare,
-  .getcapture     = &stm32_tim_getcapture,
-  .setisr         = &stm32_tim_setisr,
-  .enableint      = &stm32_tim_enableint,
-  .disableint     = &stm32_tim_disableint,
-  .ackint         = &stm32_tim_ackint
+  .setmode    = stm32_tim_setmode,
+  .setclock   = stm32_tim_setclock,
+  .setperiod  = stm32_tim_setperiod,
+  .getcounter = stm32_tim_getcounter,
+  .setcounter = stm32_tim_setcounter,
+  .getwidth   = stm32_tim_getwidth,
+  .setchannel = stm32_tim_setchannel,
+  .setcompare = stm32_tim_setcompare,
+  .getcapture = stm32_tim_getcapture,
+  .setisr     = stm32_tim_setisr,
+  .enableint  = stm32_tim_enableint,
+  .disableint = stm32_tim_disableint,
+  .ackint     = stm32_tim_ackint,
+  .checkint   = stm32_tim_checkint,
 };
 
 #ifdef CONFIG_STM32F7_TIM1
@@ -1288,7 +1366,6 @@ struct stm32_tim_priv_s stm32_tim14_priv =
 };
 #endif
 
-
 /************************************************************************************
  * Public Function - Initialization
  ************************************************************************************/
diff --git a/arch/arm/src/stm32f7/stm32_tim.h b/arch/arm/src/stm32f7/stm32_tim.h
index 86b7edd2321..becbc84cc86 100644
--- a/arch/arm/src/stm32f7/stm32_tim.h
+++ b/arch/arm/src/stm32f7/stm32_tim.h
@@ -48,7 +48,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_tim.h"
+#include "hardware/stm32_tim.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -58,6 +58,9 @@
 #define STM32_TIM_SETMODE(d,mode)       ((d)->ops->setmode(d,mode))
 #define STM32_TIM_SETCLOCK(d,freq)      ((d)->ops->setclock(d,freq))
 #define STM32_TIM_SETPERIOD(d,period)   ((d)->ops->setperiod(d,period))
+#define STM32_TIM_GETCOUNTER(d)         ((d)->ops->getcounter(d))
+#define STM32_TIM_SETCOUNTER(d,c)       ((d)->ops->setcounter(d,c))
+#define STM32_TIM_GETWIDTH(d)           ((d)->ops->getwidth(d))
 #define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
 #define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
 #define STM32_TIM_GETCAPTURE(d,ch)      ((d)->ops->getcapture(d,ch))
@@ -65,6 +68,7 @@
 #define STM32_TIM_ENABLEINT(d,s)        ((d)->ops->enableint(d,s))
 #define STM32_TIM_DISABLEINT(d,s)       ((d)->ops->disableint(d,s))
 #define STM32_TIM_ACKINT(d,s)           ((d)->ops->ackint(d,s))
+#define STM32_TIM_CHECKINT(d,s)         ((d)->ops->checkint(d,s))
 
 /************************************************************************************
  * Public Types
@@ -160,9 +164,12 @@ struct stm32_tim_ops_s
   int  (*setmode)(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode);
   int  (*setclock)(FAR struct stm32_tim_dev_s *dev, uint32_t freq);
   void (*setperiod)(FAR struct stm32_tim_dev_s *dev, uint32_t period);
+  uint32_t (*getcounter)(FAR struct stm32_tim_dev_s *dev);
+  void (*setcounter)(FAR struct stm32_tim_dev_s *dev, uint32_t count);
 
   /* General and Advanced Timers Adds */
 
+  int  (*getwidth)(FAR struct stm32_tim_dev_s *dev);
   int  (*setchannel)(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
                      stm32_tim_channel_t mode);
   int  (*setcompare)(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
@@ -171,11 +178,11 @@ struct stm32_tim_ops_s
 
   /* Timer interrupts */
 
-  int  (*setisr)(FAR struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg,
-                 int source);
+  int  (*setisr)(FAR struct stm32_tim_dev_s *dev, xcpt_t handler, void * arg, int source);
   void (*enableint)(FAR struct stm32_tim_dev_s *dev, int source);
   void (*disableint)(FAR struct stm32_tim_dev_s *dev, int source);
   void (*ackint)(FAR struct stm32_tim_dev_s *dev, int source);
+  int  (*checkint)(FAR struct stm32_tim_dev_s *dev, int source);
 };
 
 /************************************************************************************
diff --git a/arch/arm/src/stm32f7/stm32_uart.h b/arch/arm/src/stm32f7/stm32_uart.h
index b53f532693d..15ad3dfca5d 100644
--- a/arch/arm/src/stm32f7/stm32_uart.h
+++ b/arch/arm/src/stm32f7/stm32_uart.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/stm32_uart.h"
+#include "hardware/stm32_uart.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_gpio.h b/arch/arm/src/stm32f7/stm32_uid.c
similarity index 75%
rename from arch/arm/src/stm32f0l0/hardware/stm32_gpio.h
rename to arch/arm/src/stm32f7/stm32_uid.c
index f0b1f918c45..521a6274de0 100644
--- a/arch/arm/src/stm32f0l0/hardware/stm32_gpio.h
+++ b/arch/arm/src/stm32f7/stm32_uid.c
@@ -1,8 +1,8 @@
 /************************************************************************************
- * arch/arm/src/stm32f0l0/hardware/stm32_gpio.h
+ * arch/arm/src/stm32/stm32_uid.c
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt 
+ *   Copyright (C) 2015 Marawan Ragab. All rights reserved.
+ *   Author: Marawan Ragab 
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -33,24 +33,31 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H
-#define __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H
-
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip.h"
 
-/* Include the appropriate GPIO definitions for this MCU GPIO version */
+#include "hardware/stm32_memorymap.h"
 
-#if defined(CONFIG_ARCH_CHIP_STM32F0)
-#  include "hardware/stm32f0_gpio.h"
-#elif defined(CONFIG_ARCH_CHIP_STM32L0)
-#  include "hardware/stm32l0_gpio.h"
-#else
-#  error "Unrecognized STM32F0/L0 GPIO"
-#endif
+#include "stm32_uid.h"
+
+#ifdef STM32_SYSMEM_UID
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+void stm32_get_uniqueid(uint8_t uniqueid[12])
+{
+  int i;
+
+  for (i = 0; i < 12; i++)
+    {
+      uniqueid[i] = *((uint8_t*)(STM32_SYSMEM_UID)+i);
+    }
+}
+
+#endif /* STM32_SYSMEM_UID */
 
-#endif /* __ARCH_ARM_SRC_STM32F0L0_CHIP_STM32_GPIO_H */
diff --git a/arch/arm/src/stm32f7/stm32_uid.h b/arch/arm/src/stm32f7/stm32_uid.h
new file mode 100644
index 00000000000..cfa04461108
--- /dev/null
+++ b/arch/arm/src/stm32f7/stm32_uid.h
@@ -0,0 +1,51 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_uid.h
+ *
+ *   Copyright (C) 2015 Marawan Ragab. All rights reserved.
+ *   Author: Marawan Ragab 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_UID_H
+#define __ARCH_ARM_SRC_STM32_UID_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+void stm32_get_uniqueid(uint8_t uniqueid[12]);
+
+#endif /* __ARCH_ARM_SRC_STM32_UID_H */
diff --git a/arch/arm/src/stm32f7/stm32_usbhost.h b/arch/arm/src/stm32f7/stm32_usbhost.h
index 4d3ee1aa978..29431e144f9 100644
--- a/arch/arm/src/stm32f7/stm32_usbhost.h
+++ b/arch/arm/src/stm32f7/stm32_usbhost.h
@@ -43,7 +43,7 @@
  *  CONFIG_USBHOST        - Enable general USB host support
  *  CONFIG_STM32F7_OTGFS  - Enable the STM32 USB OTG FS block
  *     or
- *  CONFIG_STM32F7_OTGHS  - Enable the STM32 USB OTG HS block
+ *  CONFIG_STM32F7_OTGFSHS  - Enable the STM32 USB OTG HS block
  *  CONFIG_STM32F7_SYSCFG - Needed
  *
  * Options:
@@ -68,7 +68,7 @@
 #include 
 #include 
 
-#if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGHS)) && \
+#if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS)) && \
     defined(CONFIG_USBHOST)
 
 /************************************************************************************
@@ -120,5 +120,5 @@ void stm32_usbhost_vbusdrive(int iface, bool enable);
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* (CONFIG_STM32F7_OTGFS || CONFIG_STM32F7_OTGHS) && CONFIG_USBHOST */
+#endif /* (CONFIG_STM32F7_OTGFS || CONFIG_STM32F7_OTGFSHS) && CONFIG_USBHOST */
 #endif /* __ARCH_ARM_SRC_STM32F7_STM32_USBHOST_H */
diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c
index 39c9b188059..c6488538112 100644
--- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c
+++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c
@@ -227,8 +227,8 @@ static inline void rcc_enableahb1(void)
 #endif
 #endif
 
-#ifdef CONFIG_STM32F7_OTGHS
-#ifdef BOARD_ENABLE_USBOTG_HSULPI
+#ifdef CONFIG_STM32F7_OTGFSHS
+#if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI)
   /* Enable clocking for  USB OTG HS and external PHY */
 
   regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN);
@@ -237,7 +237,7 @@ static inline void rcc_enableahb1(void)
 
   regval |= RCC_AHB1ENR_OTGHSEN;
 #endif
-#endif  /* CONFIG_STM32F7_OTGHS */
+#endif  /* CONFIG_STM32F7_OTGFSHS */
 
   putreg32(regval, STM32_RCC_AHB1ENR);   /* Enable peripherals */
 }
@@ -657,6 +657,13 @@ static inline void rcc_enableapb2(void)
   regval |= RCC_APB2ENR_LTDCEN;
 #endif
 
+#ifdef CONFIG_STM32F7_OTGFSHS
+#ifdef CONFIG_STM32F7_INTERNAL_ULPI
+  regval |= RCC_APB2ENR_OTGPHYCEN;
+
+#endif
+#endif
+
   putreg32(regval, STM32_RCC_APB2ENR);   /* Enable peripherals */
 }
 
@@ -833,8 +840,8 @@ static void stm32_stdclockconfig(void)
       regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES);
 
 #ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR
-      /* The Flash memory interface accelerates code execution with a system of
-       * instruction prefetch and cache lines on ITCM interface (ART
+      /* The Flash memory interface accelerates code execution with a system
+       * of instruction prefetch and cache lines on ITCM interface (ART
        * Accelerator™).
        */
 
@@ -862,7 +869,7 @@ static void stm32_stdclockconfig(void)
        /* Configure PLLSAI */
 
       regval = getreg32(STM32_RCC_PLLSAICFGR);
-      regval &= ~(  RCC_PLLSAICFGR_PLLSAIN_MASK
+      regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK
                   | RCC_PLLSAICFGR_PLLSAIP_MASK
                   | RCC_PLLSAICFGR_PLLSAIQ_MASK
 #  if defined(CONFIG_STM32F7_LTDC)
@@ -899,7 +906,6 @@ static void stm32_stdclockconfig(void)
 
       putreg32(regval, STM32_RCC_DCKCFGR1);
 
-
       /* Enable PLLSAI */
 
       regval = getreg32(STM32_RCC_CR);
@@ -917,7 +923,7 @@ static void stm32_stdclockconfig(void)
       /* Configure PLLI2S */
 
       regval = getreg32(STM32_RCC_PLLI2SCFGR);
-      regval &= ~(  RCC_PLLI2SCFGR_PLLI2SN_MASK
+      regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK
 #  if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX)
                   | RCC_PLLI2SCFGR_PLLI2SP_MASK
 #  endif
@@ -932,7 +938,7 @@ static void stm32_stdclockconfig(void)
       putreg32(regval, STM32_RCC_PLLI2SCFGR);
 
       regval  = getreg32(STM32_RCC_DCKCFGR2);
-      regval &= ~(  RCC_DCKCFGR2_USART1SEL_MASK
+      regval &= ~(RCC_DCKCFGR2_USART1SEL_MASK
                   | RCC_DCKCFGR2_USART2SEL_MASK
                   | RCC_DCKCFGR2_UART4SEL_MASK
                   | RCC_DCKCFGR2_UART5SEL_MASK
@@ -951,7 +957,7 @@ static void stm32_stdclockconfig(void)
                   | RCC_DCKCFGR2_SDMMCSEL_MASK
                   | RCC_DCKCFGR2_SDMMC2SEL_MASK);
 
-      regval |= (  STM32_RCC_DCKCFGR2_USART1SRC
+      regval |= (STM32_RCC_DCKCFGR2_USART1SRC
                  | STM32_RCC_DCKCFGR2_USART2SRC
                  | STM32_RCC_DCKCFGR2_UART4SRC
                  | STM32_RCC_DCKCFGR2_UART5SRC
diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
index 0883a31b705..4f571e92566 100644
--- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
+++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
@@ -230,17 +230,18 @@ static inline void rcc_enableahb1(void)
 #endif
 #endif
 
-#ifdef CONFIG_STM32F7_OTGHS
-#ifdef BOARD_ENABLE_USBOTG_HSULPI
+#ifdef CONFIG_STM32F7_OTGFSHS
+ #if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI)
   /* Enable clocking for  USB OTG HS and external PHY */
 
   regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN);
 #else
+
   /* Enable only clocking for USB OTG HS */
 
   regval |= RCC_AHB1ENR_OTGHSEN;
 #endif
-#endif  /* CONFIG_STM32F7_OTGHS */
+#endif  /* CONFIG_STM32F7_OTGFSHS */
 
   putreg32(regval, STM32_RCC_AHB1ENR);   /* Enable peripherals */
 }
@@ -836,8 +837,8 @@ static void stm32_stdclockconfig(void)
       regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES);
 
 #ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR
-      /* The Flash memory interface accelerates code execution with a system of
-       * instruction prefetch and cache lines on ITCM interface (ART
+      /* The Flash memory interface accelerates code execution with a system
+       * of instruction prefetch and cache lines on ITCM interface (ART
        * Accelerator™).
        */
 
@@ -865,7 +866,7 @@ static void stm32_stdclockconfig(void)
        /* Configure PLLSAI */
 
       regval = getreg32(STM32_RCC_PLLSAICFGR);
-      regval &= ~(  RCC_PLLSAICFGR_PLLSAIN_MASK
+      regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK
                   | RCC_PLLSAICFGR_PLLSAIP_MASK
                   | RCC_PLLSAICFGR_PLLSAIQ_MASK
                   | RCC_PLLSAICFGR_PLLSAIR_MASK);
@@ -892,7 +893,6 @@ static void stm32_stdclockconfig(void)
 
       putreg32(regval, STM32_RCC_DCKCFGR1);
 
-
       /* Enable PLLSAI */
 
       regval = getreg32(STM32_RCC_CR);
@@ -910,7 +910,7 @@ static void stm32_stdclockconfig(void)
       /* Configure PLLI2S */
 
       regval = getreg32(STM32_RCC_PLLI2SCFGR);
-      regval &= ~(  RCC_PLLI2SCFGR_PLLI2SN_MASK
+      regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK
                   | RCC_PLLI2SCFGR_PLLI2SP_MASK
                   | RCC_PLLI2SCFGR_PLLI2SQ_MASK
                   | RCC_PLLI2SCFGR_PLLI2SR_MASK);
@@ -921,7 +921,7 @@ static void stm32_stdclockconfig(void)
       putreg32(regval, STM32_RCC_PLLI2SCFGR);
 
       regval  = getreg32(STM32_RCC_DCKCFGR2);
-      regval &= ~(  RCC_DCKCFGR2_USART1SEL_MASK
+      regval &= ~(RCC_DCKCFGR2_USART1SEL_MASK
                   | RCC_DCKCFGR2_USART2SEL_MASK
                   | RCC_DCKCFGR2_UART4SEL_MASK
                   | RCC_DCKCFGR2_UART5SEL_MASK
@@ -937,7 +937,7 @@ static void stm32_stdclockconfig(void)
                   | RCC_DCKCFGR2_CK48MSEL_MASK
                   | RCC_DCKCFGR2_SDMMCSEL_MASK);
 
-      regval |= (  STM32_RCC_DCKCFGR2_USART1SRC
+      regval |= (STM32_RCC_DCKCFGR2_USART1SRC
                  | STM32_RCC_DCKCFGR2_USART2SRC
                  | STM32_RCC_DCKCFGR2_UART4SRC
                  | STM32_RCC_DCKCFGR2_UART5SRC
diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
index f43e90c383d..cf89f52da1c 100644
--- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
+++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c
@@ -236,7 +236,7 @@ static inline void rcc_enableahb1(void)
 #endif
 #endif
 
-#ifdef CONFIG_STM32F7_OTGHS
+#ifdef CONFIG_STM32F7_OTGFSHS
 #ifdef BOARD_ENABLE_USBOTG_HSULPI
   /* Enable clocking for  USB OTG HS and external PHY */
 
@@ -246,7 +246,7 @@ static inline void rcc_enableahb1(void)
 
   regval |= RCC_AHB1ENR_OTGHSEN;
 #endif
-#endif  /* CONFIG_STM32F7_OTGHS */
+#endif  /* CONFIG_STM32F7_OTGFSHS */
 
   putreg32(regval, STM32_RCC_AHB1ENR);   /* Enable peripherals */
 }
@@ -503,7 +503,6 @@ static inline void rcc_enableapb1(void)
   regval |= (RCC_APB1ENR_CAN3EN);
 #endif
 
-
 #ifdef CONFIG_STM32F7_CEC
   /* CEC clock enable. */
 
@@ -855,8 +854,8 @@ static void stm32_stdclockconfig(void)
       regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES);
 
 #ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR
-      /* The Flash memory interface accelerates code execution with a system of
-       * instruction prefetch and cache lines on ITCM interface (ART
+      /* The Flash memory interface accelerates code execution with a system
+       * of instruction prefetch and cache lines on ITCM interface (ART
        * Accelerator™).
        */
 
@@ -884,7 +883,7 @@ static void stm32_stdclockconfig(void)
       /* Configure PLLSAI */
 
       regval = getreg32(STM32_RCC_PLLSAICFGR);
-      regval &= ~(  RCC_PLLSAICFGR_PLLSAIN_MASK
+      regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK
                   | RCC_PLLSAICFGR_PLLSAIP_MASK
                   | RCC_PLLSAICFGR_PLLSAIQ_MASK
                   | RCC_PLLSAICFGR_PLLSAIR_MASK);
@@ -932,7 +931,7 @@ static void stm32_stdclockconfig(void)
       /* Configure PLLI2S */
 
       regval = getreg32(STM32_RCC_PLLI2SCFGR);
-      regval &= ~(  RCC_PLLI2SCFGR_PLLI2SN_MASK
+      regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK
                   | RCC_PLLI2SCFGR_PLLI2SP_MASK
                   | RCC_PLLI2SCFGR_PLLI2SQ_MASK
                   | RCC_PLLI2SCFGR_PLLI2SR_MASK);
@@ -956,7 +955,7 @@ static void stm32_stdclockconfig(void)
 #endif
 
       regval  = getreg32(STM32_RCC_DCKCFGR2);
-      regval &= ~(  RCC_DCKCFGR2_USART1SEL_MASK
+      regval &= ~(RCC_DCKCFGR2_USART1SEL_MASK
                   | RCC_DCKCFGR2_USART2SEL_MASK
                   | RCC_DCKCFGR2_UART4SEL_MASK
                   | RCC_DCKCFGR2_UART5SEL_MASK
@@ -974,7 +973,7 @@ static void stm32_stdclockconfig(void)
                   | RCC_DCKCFGR2_SDMMC2SEL_MASK
                   | RCC_DCKCFGR2_DSISEL_MASK);
 
-      regval |= (  STM32_RCC_DCKCFGR2_USART1SRC
+      regval |= (STM32_RCC_DCKCFGR2_USART1SRC
                  | STM32_RCC_DCKCFGR2_USART2SRC
                  | STM32_RCC_DCKCFGR2_UART4SRC
                  | STM32_RCC_DCKCFGR2_UART5SRC
diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig
index 79cede6bb5e..9f19ece93ff 100644
--- a/arch/arm/src/stm32h7/Kconfig
+++ b/arch/arm/src/stm32h7/Kconfig
@@ -31,6 +31,7 @@ config STM32H7_STM32H7X3XX
 	select ARMV7M_HAVE_DCACHE
 	select ARMV7M_HAVE_ITCM
 	select ARMV7M_HAVE_DTCM
+	select STM32H7_HAVE_ETHERNET
 	select STM32H7_HAVE_SPI4
 	select STM32H7_HAVE_SPI5
 	select STM32H7_HAVE_SPI6
@@ -78,6 +79,10 @@ menu "STM32H7 Peripheral Selection"
 # These "hidden" settings determine is a peripheral option is available for the
 # selection MCU
 
+config STM32H7_HAVE_ETHERNET
+	bool
+	default n
+
 config STM32H7_HAVE_SPI4
 	bool
 	default n
@@ -129,6 +134,10 @@ config STM32H7_TIM
 	bool
 	default n
 
+config STM32H7_PWM
+	bool
+	default n
+
 config STM32H7_USART
 	bool
 	default n
@@ -161,6 +170,13 @@ config STM32H7_BDMA
 	select STM32H7_DMA
 	select ARCH_DMA
 
+config STM32H7_ETHMAC
+	bool "Ethernet MAC"
+	default n
+	depends on STM32H7_HAVE_ETHERNET
+	select NETDEVICES
+	select ARCH_HAVE_PHY
+
 config STM32H7_OTGFS
 	bool "OTG FS"
 	default n
@@ -195,6 +211,20 @@ config STM32H7_USBHOST_PKTDUMP
 	default n
 	depends on USBHOST
 
+config STM32H7_SDMMC1
+	bool "SDMMC1"
+	default n
+	select STM32H7_SDMMC
+	select ARCH_HAVE_SDIO
+	select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
+
+config STM32H7_SDMMC2
+	bool "SDMMC2"
+	default n
+	select STM32H7_SDMMC
+	select ARCH_HAVE_SDIO
+	select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
+
 menu "STM32H7 I2C Selection"
 
 config STM32H7_I2C1
@@ -269,6 +299,80 @@ config STM32H7_SYSCFG
 
 endmenu # STM32H7 SPI Selection
 
+menu "STM32H7 Timer Selection"
+
+config STM32H7_TIM1
+	bool "TIM1"
+	default n
+	select STM32H7_TIM
+
+config STM32H7_TIM2
+	bool "TIM2"
+	default n
+	select STM32H7_TIM
+
+config STM32H7_TIM3
+	bool "TIM3"
+	default n
+	select STM32H7_TIM
+
+config STM32H7_TIM4
+	bool "TIM4"
+	default n
+	select STM32H7_TIM
+
+config STM32H7_TIM5
+	bool "TIM5"
+	default n
+	select STM32H7_TIM
+
+config STM32H7_TIM6
+	bool "TIM6"
+	default n
+	select STM32H7_TIM
+
+config STM32H7_TIM7
+	bool "TIM7"
+	default n
+	select STM32H7_TIM
+
+config STM32H7_TIM8
+	bool "TIM8"
+	default n
+	select STM32H7_TIM
+
+config STM32H7_TIM12
+	bool "TIM12"
+	default n
+	select STM32H7_TIM
+
+config STM32H7_TIM13
+	bool "TIM13"
+	default n
+	select STM32H7_TIM
+
+config STM32H7_TIM14
+	bool "TIM14"
+	default n
+	select STM32H7_TIM
+
+config STM32H7_TIM15
+	bool "TIM15"
+	default n
+	select STM32H7_TIM
+
+config STM32H7_TIM16
+	bool "TIM16"
+	default n
+	select STM32H7_TIM
+
+config STM32H7_TIM17
+	bool "TIM17"
+	default n
+	select STM32H7_TIM
+
+endmenu # STM32H7 Timer Selection
+
 menu "STM32H7 U[S]ART Selection"
 
 config STM32H7_USART1
@@ -763,10 +867,3004 @@ config STM32H7_PM_SERIAL_ACTIVITY
 endif # PM
 endmenu # U[S]ART Configuration
 
+menu "SD/MMC Configuration"
+	depends on STM32H7_SDMMC
+
+config STM32H7_SDMMC_XFRDEBUG
+	bool "SDMMC transfer debug"
+	depends on DEBUG_FS_INFO
+	default n
+	---help---
+		Enable special debug instrumentation analyze SDMMC data transfers.
+		This logic is as non-invasive as possible:  It samples SDMMC
+		registers at key points in the data transfer and then dumps all of
+		the registers at the end of the transfer.  If DEBUG_DMA is also
+		enabled, then DMA register will be collected as well.  Requires also
+		DEBUG_FS and CONFIG_DEBUG_INFO.
+
+config STM32H7_SDMMC_IDMA
+	bool "Support IDMA data transfers"
+	default y
+	select STM32H7_SDMMC_DMA
+	depends on STM32H7_DMA
+	---help---
+		Support IDMA data transfers.
+
+menu "SDMMC1 Configuration"
+	depends on STM32H7_SDMMC1
+
+config SDMMC1_WIDTH_D1_ONLY
+	bool "Use D1 only on SDMMC1"
+	default n
+	---help---
+		Select 1-bit transfer mode.  Default: 4-bit transfer mode.
+
+config SDMMC1_SDIO_MODE
+	bool "SDIO Card Support"
+	default n
+	---help---
+		Build in additional support needed only for SDIO cards (vs. SD
+		memory cards)
+
+config SDMMC1_SDIO_PULLUP
+	bool "Enable internal Pull-Ups"
+	default n
+	---help---
+		If you are using an external SDCard module that does not have the
+		pull-up resistors for the SDIO interface (like the Gadgeteer SD Card
+		Module) then enable this option to activate the internal pull-up
+		resistors.
+
+endmenu # "SDMMC1 Configuration"
+
+menu "SDMMC2 Configuration"
+	depends on STM32H7_SDMMC2
+
+config SDMMC2_WIDTH_D1_ONLY
+	bool "Use D1 only on SDMMC2"
+	default n
+	---help---
+		Select 1-bit transfer mode.  Default: 4-bit transfer mode.
+
+config SDMMC2_SDIO_MODE
+	bool "SDIO Card Support"
+	default n
+	---help---
+		Build in additional support needed only for SDIO cards (vs. SD
+		memory cards)
+
+config SDMMC2_SDIO_PULLUP
+	bool "Enable internal Pull-Ups"
+	default n
+	---help---
+		If you are using an external SDCard module that does not have the
+		pull-up resistors for the SDIO interface (like the Gadgeteer SD Card
+		Module) then enable this option to activate the internal pull-up
+		resistors.
+
+endmenu # "SDMMC2 Configuration"
+endmenu # "SD/MMC Configuration"
 config STM32H7_CUSTOM_CLOCKCONFIG
 	bool "Custom clock configuration"
 	default n
 	---help---
 		Enables special, board-specific STM32 clock configuration.
 
+menu "Timer Configuration"
+
+config STM32H7_PWM_LL_OPS
+	bool "PWM low-level operations"
+	default n
+	---help---
+		Enable low-level PWM ops.
+
+config STM32H7_TIM1_PWM
+	bool "TIM1 PWM"
+	default n
+	depends on STM32H7_TIM1
+	select ARCH_HAVE_PWM_PULSECOUNT
+	select STM32H7_PWM
+	---help---
+		Reserve timer 1 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32H7_TIM1
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32H7_TIM1_PWM
+
+config STM32H7_TIM1_MODE
+	int "TIM1 Mode"
+	default 0
+	range 0 4
+	---help---
+		Specifies the timer mode.
+
+config STM32H7_TIM1_LOCK
+	int "TIM1 Lock Level Configuration"
+	default 0
+	range 0 3
+	---help---
+		Timer 1 lock level configuration
+
+config STM32H7_TIM1_TDTS
+	int "TIM1 t_DTS Division"
+	default 0
+	range 0 2
+	---help---
+		Timer 1 dead-time and sampling clock (t_DTS) division
+
+config STM32H7_TIM1_DEADTIME
+	int "TIM1 Initial Dead-time"
+	default 0
+	range 0 255
+	---help---
+		Timer 1 initial dead-time
+
+if STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM1_CHANNEL1
+	bool "TIM1 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32H7_TIM1_CHANNEL1
+
+config STM32H7_TIM1_CH1MODE
+	int "TIM1 Channel 1 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM1_CH1OUT
+	bool "TIM1 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+config STM32H7_TIM1_CH1NOUT
+	bool "TIM1 Channel 1 Complementary Output"
+	default n
+	---help---
+		Enables channel 1 Complementary Output.
+
+endif # STM32H7_TIM1_CHANNEL1
+
+config STM32H7_TIM1_CHANNEL2
+	bool "TIM1 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32H7_TIM1_CHANNEL2
+
+config STM32H7_TIM1_CH2MODE
+	int "TIM1 Channel 2 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM1_CH2OUT
+	bool "TIM1 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+config STM32H7_TIM1_CH2NOUT
+	bool "TIM1 Channel 2 Complementary Output"
+	default n
+	---help---
+		Enables channel 2 Complementary Output.
+
+endif # STM32H7_TIM1_CHANNEL2
+
+config STM32H7_TIM1_CHANNEL3
+	bool "TIM1 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32H7_TIM1_CHANNEL3
+
+config STM32H7_TIM1_CH3MODE
+	int "TIM1 Channel 3 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM1_CH3OUT
+	bool "TIM1 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+config STM32H7_TIM1_CH3NOUT
+	bool "TIM1 Channel 3 Complementary Output"
+	default n
+	---help---
+		Enables channel 3 Complementary Output.
+
+endif # STM32H7_TIM1_CHANNEL3
+
+config STM32H7_TIM1_CHANNEL4
+	bool "TIM1 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32H7_TIM1_CHANNEL4
+
+config STM32H7_TIM1_CH4MODE
+	int "TIM1 Channel 4 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM1_CH4OUT
+	bool "TIM1 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32H7_TIM1_CHANNEL4
+
+config STM32H7_TIM1_CHANNEL5
+	bool "TIM1 Channel 5 (internal)"
+	default n
+	---help---
+		Enables channel 5 (no available externaly)
+
+if STM32H7_TIM1_CHANNEL5
+
+config STM32H7_TIM1_CH5MODE
+	int "TIM1 Channel 5 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM1_CH5OUT
+	bool "TIM1 Channel 5 Output"
+	default n
+	---help---
+		Enables channel 5 output.
+
+endif # STM32H7_TIM1_CHANNEL5
+
+config STM32H7_TIM1_CHANNEL6
+	bool "TIM1 Channel 6 (internal)"
+	default n
+	---help---
+		Enables channel 6 (no available externaly)
+
+if STM32H7_TIM1_CHANNEL6
+
+config STM32H7_TIM1_CH6MODE
+	int "TIM1 Channel 6 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM1_CH6OUT
+	bool "TIM1 Channel 6 Output"
+	default n
+	---help---
+		Enables channel 6 output.
+
+endif # STM32H7_TIM1_CHANNEL6
+
+endif # STM32H7_PWM_MULTICHAN
+
+if !STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM1_CHANNEL
+	int "TIM1 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM1 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+if STM32H7_TIM1_CHANNEL = 1
+
+config STM32H7_TIM1_CH1OUT
+	bool "TIM1 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+config STM32H7_TIM1_CH1NOUT
+	bool "TIM1 Channel 1 Complementary Output"
+	default n
+	---help---
+		Enables channel 1 Complementary Output.
+
+endif # STM32H7_TIM1_CHANNEL = 1
+
+if STM32H7_TIM1_CHANNEL = 2
+
+config STM32H7_TIM1_CH2OUT
+	bool "TIM1 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+config STM32H7_TIM1_CH2NOUT
+	bool "TIM1 Channel 2 Complementary Output"
+	default n
+	---help---
+		Enables channel 2 Complementary Output.
+
+endif # STM32H7_TIM1_CHANNEL = 2
+
+if STM32H7_TIM1_CHANNEL = 3
+
+config STM32H7_TIM1_CH3OUT
+	bool "TIM1 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+config STM32H7_TIM1_CH3NOUT
+	bool "TIM1 Channel 3 Complementary Output"
+	default n
+	---help---
+		Enables channel 3 Complementary Output.
+
+endif # STM32H7_TIM1_CHANNEL = 3
+
+if STM32H7_TIM1_CHANNEL = 4
+
+config STM32H7_TIM1_CH4OUT
+	bool "TIM1 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32H7_TIM1_CHANNEL = 4
+
+config STM32H7_TIM1_CHMODE
+	int "TIM1 Channel Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+endif # !STM32H7_PWM_MULTICHAN
+
+endif # STM32H7_TIM1_PWM
+
+config STM32H7_TIM2_PWM
+	bool "TIM2 PWM"
+	default n
+	depends on STM32H7_TIM2
+	select ARCH_HAVE_PWM_PULSECOUNT
+	select STM32H7_PWM
+	---help---
+		Reserve timer 2 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32H7_TIM2
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32H7_TIM2_PWM
+
+config STM32H7_TIM2_MODE
+	int "TIM2 Mode"
+	default 0
+	range 0 4
+	---help---
+		Specifies the timer mode.
+
+if STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM2_CHANNEL1
+	bool "TIM2 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32H7_TIM2_CHANNEL1
+
+config STM32H7_TIM2_CH1MODE
+	int "TIM2 Channel 1 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM2_CH1OUT
+	bool "TIM2 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM2_CHANNEL1
+
+config STM32H7_TIM2_CHANNEL2
+	bool "TIM2 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32H7_TIM2_CHANNEL2
+
+config STM32H7_TIM2_CH2MODE
+	int "TIM2 Channel 2 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM2_CH2OUT
+	bool "TIM2 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32H7_TIM2_CHANNEL2
+
+config STM32H7_TIM2_CHANNEL3
+	bool "TIM2 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32H7_TIM2_CHANNEL3
+
+config STM32H7_TIM2_CH3MODE
+	int "TIM2 Channel 3 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM2_CH3OUT
+	bool "TIM2 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32H7_TIM2_CHANNEL3
+
+config STM32H7_TIM2_CHANNEL4
+	bool "TIM2 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32H7_TIM2_CHANNEL4
+
+config STM32H7_TIM2_CH4MODE
+	int "TIM2 Channel 4 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM2_CH4OUT
+	bool "TIM2 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32H7_TIM2_CHANNEL4
+
+endif # STM32H7_PWM_MULTICHAN
+
+if !STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM2_CHANNEL
+	int "TIM2 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM2 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+if STM32H7_TIM2_CHANNEL = 1
+
+config STM32H7_TIM2_CH1OUT
+	bool "TIM2 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM2_CHANNEL = 1
+
+if STM32H7_TIM2_CHANNEL = 2
+
+config STM32H7_TIM2_CH2OUT
+	bool "TIM2 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32H7_TIM2_CHANNEL = 2
+
+if STM32H7_TIM2_CHANNEL = 3
+
+config STM32H7_TIM2_CH3OUT
+	bool "TIM2 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32H7_TIM2_CHANNEL = 3
+
+if STM32H7_TIM2_CHANNEL = 4
+
+config STM32H7_TIM2_CH4OUT
+	bool "TIM2 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32H7_TIM2_CHANNEL = 4
+
+config STM32H7_TIM2_CHMODE
+	int "TIM2 Channel Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+endif # !STM32H7_PWM_MULTICHAN
+
+endif # STM32H7_TIM2_PWM
+
+config STM32H7_TIM3_PWM
+	bool "TIM3 PWM"
+	default n
+	depends on STM32H7_TIM3
+	select ARCH_HAVE_PWM_PULSECOUNT
+	select STM32H7_PWM
+	---help---
+		Reserve timer 3 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32H7_TIM3
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32H7_TIM3_PWM
+
+config STM32H7_TIM3_MODE
+	int "TIM3 Mode"
+	default 0
+	range 0 4
+	---help---
+		Specifies the timer mode.
+
+if STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM3_CHANNEL1
+	bool "TIM3 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32H7_TIM3_CHANNEL1
+
+config STM32H7_TIM3_CH1MODE
+	int "TIM3 Channel 1 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM3_CH1OUT
+	bool "TIM3 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM3_CHANNEL1
+
+config STM32H7_TIM3_CHANNEL2
+	bool "TIM3 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32H7_TIM3_CHANNEL2
+
+config STM32H7_TIM3_CH2MODE
+	int "TIM3 Channel 2 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM3_CH2OUT
+	bool "TIM3 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32H7_TIM3_CHANNEL2
+
+config STM32H7_TIM3_CHANNEL3
+	bool "TIM3 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32H7_TIM3_CHANNEL3
+
+config STM32H7_TIM3_CH3MODE
+	int "TIM3 Channel 3 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM3_CH3OUT
+	bool "TIM3 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32H7_TIM3_CHANNEL3
+
+config STM32H7_TIM3_CHANNEL4
+	bool "TIM3 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32H7_TIM3_CHANNEL4
+
+config STM32H7_TIM3_CH4MODE
+	int "TIM3 Channel 4 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM3_CH4OUT
+	bool "TIM3 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32H7_TIM3_CHANNEL4
+
+endif # STM32H7_PWM_MULTICHAN
+
+if !STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM3_CHANNEL
+	int "TIM3 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM3 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+if STM32H7_TIM3_CHANNEL = 1
+
+config STM32H7_TIM3_CH1OUT
+	bool "TIM3 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM3_CHANNEL = 1
+
+if STM32H7_TIM3_CHANNEL = 2
+
+config STM32H7_TIM3_CH2OUT
+	bool "TIM3 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32H7_TIM3_CHANNEL = 2
+
+if STM32H7_TIM3_CHANNEL = 3
+
+config STM32H7_TIM3_CH3OUT
+	bool "TIM3 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32H7_TIM3_CHANNEL = 3
+
+if STM32H7_TIM3_CHANNEL = 4
+
+config STM32H7_TIM3_CH4OUT
+	bool "TIM3 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32H7_TIM3_CHANNEL = 4
+
+config STM32H7_TIM3_CHMODE
+	int "TIM3 Channel Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+endif # !STM32H7_PWM_MULTICHAN
+
+endif # STM32H7_TIM3_PWM
+
+config STM32H7_TIM4_PWM
+	bool "TIM4 PWM"
+	default n
+	depends on STM32H7_TIM4
+	select ARCH_HAVE_PWM_PULSECOUNT
+	select STM32H7_PWM
+	---help---
+		Reserve timer 4 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32H7_TIM4
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32H7_TIM4_PWM
+
+config STM32H7_TIM4_MODE
+	int "TIM4 Mode"
+	default 0
+	range 0 4
+	---help---
+		Specifies the timer mode.
+
+if STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM4_CHANNEL1
+	bool "TIM4 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32H7_TIM4_CHANNEL1
+
+config STM32H7_TIM4_CH1MODE
+	int "TIM4 Channel 1 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM4_CH1OUT
+	bool "TIM4 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM4_CHANNEL1
+
+config STM32H7_TIM4_CHANNEL2
+	bool "TIM4 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32H7_TIM4_CHANNEL2
+
+config STM32H7_TIM4_CH2MODE
+	int "TIM4 Channel 2 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM4_CH2OUT
+	bool "TIM4 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32H7_TIM4_CHANNEL2
+
+config STM32H7_TIM4_CHANNEL3
+	bool "TIM4 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32H7_TIM4_CHANNEL3
+
+config STM32H7_TIM4_CH3MODE
+	int "TIM4 Channel 3 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM4_CH3OUT
+	bool "TIM4 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32H7_TIM4_CHANNEL3
+
+config STM32H7_TIM4_CHANNEL4
+	bool "TIM4 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32H7_TIM4_CHANNEL4
+
+config STM32H7_TIM4_CH4MODE
+	int "TIM4 Channel 4 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM4_CH4OUT
+	bool "TIM4 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32H7_TIM4_CHANNEL4
+
+endif # STM32H7_PWM_MULTICHAN
+
+if !STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM4_CHANNEL
+	int "TIM4 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM4 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+if STM32H7_TIM4_CHANNEL = 1
+
+config STM32H7_TIM4_CH1OUT
+	bool "TIM4 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM4_CHANNEL = 1
+
+if STM32H7_TIM4_CHANNEL = 2
+
+config STM32H7_TIM4_CH2OUT
+	bool "TIM4 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32H7_TIM4_CHANNEL = 2
+
+if STM32H7_TIM4_CHANNEL = 3
+
+config STM32H7_TIM4_CH3OUT
+	bool "TIM4 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32H7_TIM4_CHANNEL = 3
+
+if STM32H7_TIM4_CHANNEL = 4
+
+config STM32H7_TIM4_CH4OUT
+	bool "TIM4 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32H7_TIM4_CHANNEL = 4
+
+config STM32H7_TIM4_CHMODE
+	int "TIM4 Channel Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+endif # !STM32H7_PWM_MULTICHAN
+
+endif # STM32H7_TIM4_PWM
+
+config STM32H7_TIM5_PWM
+	bool "TIM5 PWM"
+	default n
+	depends on STM32H7_TIM5
+	select ARCH_HAVE_PWM_PULSECOUNT
+	select STM32H7_PWM
+	---help---
+		Reserve timer 5 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32H7_TIM5
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32H7_TIM5_PWM
+
+config STM32H7_TIM5_MODE
+	int "TIM5 Mode"
+	default 0
+	range 0 4
+	---help---
+		Specifies the timer mode.
+
+if STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM5_CHANNEL1
+	bool "TIM5 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32H7_TIM5_CHANNEL1
+
+config STM32H7_TIM5_CH1MODE
+	int "TIM5 Channel 1 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM5_CH1OUT
+	bool "TIM5 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM5_CHANNEL1
+
+config STM32H7_TIM5_CHANNEL2
+	bool "TIM5 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32H7_TIM5_CHANNEL2
+
+config STM32H7_TIM5_CH2MODE
+	int "TIM5 Channel 2 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM5_CH2OUT
+	bool "TIM5 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32H7_TIM5_CHANNEL2
+
+config STM32H7_TIM5_CHANNEL3
+	bool "TIM5 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32H7_TIM5_CHANNEL3
+
+config STM32H7_TIM5_CH3MODE
+	int "TIM5 Channel 3 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM5_CH3OUT
+	bool "TIM5 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32H7_TIM5_CHANNEL3
+
+config STM32H7_TIM5_CHANNEL4
+	bool "TIM5 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32H7_TIM5_CHANNEL4
+
+config STM32H7_TIM5_CH4MODE
+	int "TIM5 Channel 4 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM5_CH4OUT
+	bool "TIM5 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32H7_TIM5_CHANNEL4
+
+endif # STM32H7_PWM_MULTICHAN
+
+if !STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM5_CHANNEL
+	int "TIM5 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM5 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+if STM32H7_TIM5_CHANNEL = 1
+
+config STM32H7_TIM5_CH1OUT
+	bool "TIM5 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM5_CHANNEL = 1
+
+if STM32H7_TIM5_CHANNEL = 2
+
+config STM32H7_TIM5_CH2OUT
+	bool "TIM5 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32H7_TIM5_CHANNEL = 2
+
+if STM32H7_TIM5_CHANNEL = 3
+
+config STM32H7_TIM5_CH3OUT
+	bool "TIM5 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+endif # STM32H7_TIM5_CHANNEL = 3
+
+if STM32H7_TIM5_CHANNEL = 4
+
+config STM32H7_TIM5_CH4OUT
+	bool "TIM5 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32H7_TIM5_CHANNEL = 4
+
+config STM32H7_TIM5_CHMODE
+	int "TIM5 Channel Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+endif # !STM32H7_PWM_MULTICHAN
+
+endif # STM32H7_TIM5_PWM
+
+config STM32H7_TIM8_PWM
+	bool "TIM8 PWM"
+	default n
+	depends on STM32H7_TIM8
+	select ARCH_HAVE_PWM_PULSECOUNT
+	select STM32H7_PWM
+	---help---
+		Reserve timer 8 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32H7_TIM8
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32H7_TIM8_PWM
+
+config STM32H7_TIM8_MODE
+	int "TIM8 Mode"
+	default 0
+	range 0 4
+	---help---
+		Specifies the timer mode.
+
+config STM32H7_TIM8_LOCK
+	int "TIM8 Lock Level Configuration"
+	default 0
+	range 0 3
+	---help---
+		Timer 8 lock level configuration
+
+config STM32H7_TIM8_DEADTIME
+	int "TIM8 Initial Dead-time"
+	default 0
+	range 0 255
+	---help---
+		Timer 8 initial dead-time
+
+config STM32H7_TIM8_TDTS
+	int "TIM8 t_DTS Division"
+	default 0
+	range 0 2
+	---help---
+		Timer 8 dead-time and sampling clock (t_DTS) division
+
+if STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM8_CHANNEL1
+	bool "TIM8 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32H7_TIM8_CHANNEL1
+
+config STM32H7_TIM8_CH1MODE
+	int "TIM8 Channel 1 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM8_CH1OUT
+        bool "TIM8 Channel 1 Output"
+        default n
+        ---help---
+                Enables channel 1 output.
+
+config STM32H7_TIM8_CH1NOUT
+	bool "TIM8 Channel 1 Complementary Output"
+	default n
+	---help---
+		Enables channel 1 Complementary Output.
+
+endif # STM32H7_TIM8_CHANNEL1
+
+config STM32H7_TIM8_CHANNEL2
+	bool "TIM8 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32H7_TIM8_CHANNEL2
+
+config STM32H7_TIM8_CH2MODE
+	int "TIM8 Channel 2 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM8_CH2OUT
+	bool "TIM8 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+config STM32H7_TIM8_CH2NOUT
+	bool "TIM8 Channel 2 Complementary Output"
+	default n
+	---help---
+		Enables channel 2 Complementary Output.
+
+endif # STM32H7_TIM8_CHANNEL2
+
+config STM32H7_TIM8_CHANNEL3
+	bool "TIM8 Channel 3"
+	default n
+	---help---
+		Enables channel 3.
+
+if STM32H7_TIM8_CHANNEL3
+
+config STM32H7_TIM8_CH3MODE
+	int "TIM8 Channel 3 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM8_CH3OUT
+	bool "TIM8 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+config STM32H7_TIM8_CH3NOUT
+	bool "TIM8 Channel 3 Complementary Output"
+	default n
+	---help---
+		Enables channel 3 Complementary Output.
+
+endif # STM32H7_TIM8_CHANNEL3
+
+config STM32H7_TIM8_CHANNEL4
+	bool "TIM8 Channel 4"
+	default n
+	---help---
+		Enables channel 4.
+
+if STM32H7_TIM8_CHANNEL4
+
+config STM32H7_TIM8_CH4MODE
+	int "TIM8 Channel 4 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM8_CH4OUT
+	bool "TIM8 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32H7_TIM8_CHANNEL4
+
+config STM32H7_TIM8_CHANNEL5
+	bool "TIM8 Channel 5 (internal)"
+	default n
+	---help---
+		Enables channel 5 (no available externaly)
+
+if STM32H7_TIM8_CHANNEL5
+
+config STM32H7_TIM8_CH5MODE
+	int "TIM8 Channel 5 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM8_CH5OUT
+	bool "TIM8 Channel 5 Output"
+	default n
+	---help---
+		Enables channel 5 output.
+
+endif # STM32H7_TIM8_CHANNEL5
+
+config STM32H7_TIM8_CHANNEL6
+	bool "TIM8 Channel 6 (internal)"
+	default n
+	---help---
+		Enables channel 6 (no available externaly)
+
+if STM32H7_TIM8_CHANNEL6
+
+config STM32H7_TIM8_CH6MODE
+	int "TIM8 Channel 6 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM8_CH6OUT
+	bool "TIM8 Channel 6 Output"
+	default n
+	---help---
+		Enables channel 6 output.
+
+endif # STM32H7_TIM8_CHANNEL6
+
+endif # STM32H7_PWM_MULTICHAN
+
+if !STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM8_CHANNEL
+	int "TIM8 PWM Output Channel"
+	default 1
+	range 1 4
+	---help---
+		If TIM8 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,..,4}
+
+if STM32H7_TIM8_CHANNEL = 1
+
+config STM32H7_TIM8_CH1OUT
+	bool "TIM8 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+config STM32H7_TIM8_CH1NOUT
+	bool "TIM8 Channel 1 Complementary Output"
+	default n
+	---help---
+		Enables channel 1 Complementary Output.
+
+endif # STM32H7_TIM8_CHANNEL = 1
+
+if STM32H7_TIM8_CHANNEL = 2
+
+config STM32H7_TIM8_CH2OUT
+	bool "TIM8 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+config STM32H7_TIM8_CH2NOUT
+	bool "TIM8 Channel 2 Complementary Output"
+	default n
+	---help---
+		Enables channel 2 Complementary Output.
+
+endif # STM32H7_TIM8_CHANNEL = 2
+
+if STM32H7_TIM8_CHANNEL = 3
+
+config STM32H7_TIM8_CH3OUT
+	bool "TIM8 Channel 3 Output"
+	default n
+	---help---
+		Enables channel 3 output.
+
+config STM32H7_TIM8_CH3NOUT
+	bool "TIM8 Channel 3 Complementary Output"
+	default n
+	---help---
+		Enables channel 3 Complementary Output.
+
+endif # STM32H7_TIM8_CHANNEL = 3
+
+if STM32H7_TIM8_CHANNEL = 4
+
+config STM32H7_TIM8_CH4OUT
+	bool "TIM8 Channel 4 Output"
+	default n
+	---help---
+		Enables channel 4 output.
+
+endif # STM32H7_TIM8_CHANNEL = 4
+
+config STM32H7_TIM8_CHMODE
+	int "TIM8 Channel Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+endif # !STM32H7_PWM_MULTICHAN
+
+endif # STM32H7_TIM8_PWM
+
+config STM32H7_TIM12_PWM
+	bool "TIM12 PWM"
+	default n
+	depends on STM32H7_TIM12
+	select ARCH_HAVE_PWM_PULSECOUNT
+	select STM32H7_PWM
+	---help---
+		Reserve timer 12 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32H7_TIM12
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32H7_TIM12_PWM
+
+if STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM12_CHANNEL1
+	bool "TIM12 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32H7_TIM12_CHANNEL1
+
+config STM32H7_TIM12_CH1MODE
+	int "TIM12 Channel 1 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM12_CH1OUT
+	bool "TIM12 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM12_CHANNEL1
+
+config STM32H7_TIM12_CHANNEL2
+	bool "TIM12 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32H7_TIM12_CHANNEL2
+
+config STM32H7_TIM12_CH2MODE
+	int "TIM12 Channel 2 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM12_CH2OUT
+	bool "TIM12 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32H7_TIM12_CHANNEL2
+
+endif # STM32H7_PWM_MULTICHAN
+
+if !STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM12_CHANNEL
+	int "TIM12 PWM Output Channel"
+	default 1
+	range 1 2
+	---help---
+		If TIM12 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,2}
+
+if STM32H7_TIM12_CHANNEL = 1
+
+config STM32H7_TIM12_CH1OUT
+	bool "TIM12 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM12_CHANNEL = 1
+
+if STM32H7_TIM12_CHANNEL = 2
+
+config STM32H7_TIM12_CH2OUT
+	bool "TIM12 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32H7_TIM12_CHANNEL = 2
+
+config STM32H7_TIM12_CHMODE
+	int "TIM12 Channel Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+endif # !STM32H7_PWM_MULTICHAN
+
+endif # STM32H7_TIM12_PWM
+
+config STM32H7_TIM13_PWM
+	bool "TIM13 PWM"
+	default n
+	depends on STM32H7_TIM13
+	select ARCH_HAVE_PWM_PULSECOUNT
+	select STM32H7_PWM
+	---help---
+		Reserve timer 13 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32H7_TIM13
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32H7_TIM13_PWM
+
+if STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM13_CHANNEL1
+	bool "TIM13 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32H7_TIM13_CHANNEL1
+
+config STM32H7_TIM13_CH1MODE
+	int "TIM13 Channel 1 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM13_CH1OUT
+	bool "TIM13 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM13_CHANNEL1
+
+endif # STM32H7_PWM_MULTICHAN
+
+if !STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM13_CHANNEL
+	int "TIM13 PWM Output Channel"
+	default 1
+	range 1 1
+	---help---
+		If TIM13 is enabled for PWM usage, you also need specifies the timer output
+		channel {1}
+
+if STM32H7_TIM13_CHANNEL = 1
+
+config STM32H7_TIM13_CH1OUT
+	bool "TIM13 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM13_CHANNEL = 1
+
+config STM32H7_TIM13_CHMODE
+	int "TIM13 Channel Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+endif # !STM32H7_PWM_MULTICHAN
+
+endif # STM32H7_TIM13_PWM
+
+config STM32H7_TIM14_PWM
+	bool "TIM14 PWM"
+	default n
+	depends on STM32H7_TIM14
+	select ARCH_HAVE_PWM_PULSECOUNT
+	select STM32H7_PWM
+	---help---
+		Reserve timer 14 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32H7_TIM14
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32H7_TIM14_PWM
+
+if STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM14_CHANNEL1
+	bool "TIM14 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32H7_TIM14_CHANNEL1
+
+config STM32H7_TIM14_CH1MODE
+	int "TIM14 Channel 1 Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM14_CH1OUT
+	bool "TIM14 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM14_CHANNEL1
+
+endif # STM32H7_PWM_MULTICHAN
+
+if !STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM14_CHANNEL
+	int "TIM14 PWM Output Channel"
+	default 1
+	range 1 1
+	---help---
+		If TIM14 is enabled for PWM usage, you also need specifies the timer output
+		channel {1}
+
+if STM32H7_TIM14_CHANNEL = 1
+
+config STM32H7_TIM14_CH1OUT
+	bool "TIM14 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM14_CHANNEL = 1
+
+config STM32H7_TIM14_CHMODE
+	int "TIM14 Channel Mode"
+	default 6
+	range 0 11
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+endif # !STM32H7_PWM_MULTICHAN
+
+endif # STM32H7_TIM14_PWM
+
+config STM32H7_TIM15_PWM
+	bool "TIM15 PWM"
+	default n
+	depends on STM32H7_TIM15
+	select STM32H7_PWM
+	---help---
+		Reserve timer 15 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32H7_TIM15
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32H7_TIM15_PWM
+
+config STM32H7_TIM15_LOCK
+	int "TIM15 Lock Level Configuration"
+	default 0
+	range 0 3
+	---help---
+		Timer 15 lock level configuration
+
+config STM32H7_TIM15_TDTS
+	int "TIM15 t_DTS Division"
+	default 0
+	range 0 2
+	---help---
+		Timer 15 dead-time and sampling clock (t_DTS) division
+
+config STM32H7_TIM15_DEADTIME
+	int "TIM15 Initial Dead-time"
+	default 0
+	range 0 255
+	---help---
+		Timer 15 initial dead-time
+
+if STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM15_CHANNEL1
+	bool "TIM15 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32H7_TIM15_CHANNEL1
+
+config STM32H7_TIM15_CH1MODE
+	int "TIM15 Channel 1 Mode"
+	default 6
+	range 0 9
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM15_CH1OUT
+	bool "TIM15 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+config STM32H7_TIM15_CH1NOUT
+	bool "TIM15 Channel 1 Complementary Output"
+	default n
+	---help---
+		Enables channel 1 Complementary Output.
+
+endif # STM32H7_TIM15_CHANNEL1
+
+config STM32H7_TIM15_CHANNEL2
+	bool "TIM15 Channel 2"
+	default n
+	---help---
+		Enables channel 2.
+
+if STM32H7_TIM15_CHANNEL2
+
+config STM32H7_TIM15_CH2MODE
+	int "TIM15 Channel 2 Mode"
+	default 6
+	range 0 9
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM15_CH2OUT
+	bool "TIM15 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+endif # STM32H7_TIM15_CHANNEL2
+
+endif # STM32H7_PWM_MULTICHAN
+
+if !STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM15_CHANNEL
+	int "TIM15 PWM Output Channel"
+	default 1
+	range 1 2
+	---help---
+		If TIM15 is enabled for PWM usage, you also need specifies the timer output
+		channel {1,2}
+
+if STM32H7_TIM15_CHANNEL = 1
+
+config STM32H7_TIM15_CH1OUT
+	bool "TIM15 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+config STM32H7_TIM15_CH1NOUT
+	bool "TIM15 Channel 1 Complementary Output"
+	default n
+	---help---
+		Enables channel 1 Complementary Output.
+
+endif # STM32H7_TIM15_CHANNEL = 1
+
+if STM32H7_TIM15_CHANNEL = 2
+
+config STM32H7_TIM15_CH2OUT
+	bool "TIM15 Channel 2 Output"
+	default n
+	---help---
+		Enables channel 2 output.
+
+config STM32H7_TIM15_CH2NOUT
+	bool "TIM15 Channel 2 Complementary Output"
+	default n
+	---help---
+		Enables channel 2 Complementary Output.
+
+endif # STM32H7_TIM15_CHANNEL = 2
+
+config STM32H7_TIM15_CHMODE
+	int "TIM15 Channel Mode"
+	default 6
+	range 0 9
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+endif # !STM32H7_PWM_MULTICHAN
+
+endif # STM32H7_TIM15_PWM
+
+config STM32H7_TIM16_PWM
+	bool "TIM16 PWM"
+	default n
+	depends on STM32H7_TIM16
+	select STM32H7_PWM
+	---help---
+		Reserve timer 16 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32H7_TIM16
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32H7_TIM16_PWM
+
+config STM32H7_TIM16_LOCK
+	int "TIM16 Lock Level Configuration"
+	default 0
+	range 0 3
+	---help---
+		Timer 16 lock level configuration
+
+config STM32H7_TIM16_TDTS
+	int "TIM16 t_DTS division"
+	default 0
+	range 0 2
+	---help---
+		Timer 16 dead-time and sampling clock (t_DTS) division
+
+config STM32H7_TIM16_DEADTIME
+	int "TIM16 Initial Dead-time"
+	default 0
+	range 0 255
+	---help---
+		Timer 16 initial dead-time
+
+if STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM16_CHANNEL1
+	bool "TIM16 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32H7_TIM16_CHANNEL1
+
+config STM32H7_TIM16_CH1MODE
+	int "TIM16 Channel 1 Mode"
+	default 6
+	range 0 7
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM16_CH1OUT
+	bool "TIM16 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM16_CHANNEL1
+
+endif # STM32H7_PWM_MULTICHAN
+
+if !STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM16_CHANNEL
+	int "TIM16 PWM Output Channel"
+	default 1
+	range 1 1
+	---help---
+		If TIM16 is enabled for PWM usage, you also need specifies the timer output
+		channel {1}
+
+if STM32H7_TIM16_CHANNEL = 1
+
+config STM32H7_TIM16_CH1OUT
+	bool "TIM16 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM16_CHANNEL = 1
+
+config STM32H7_TIM16_CHMODE
+	int "TIM16 Channel Mode"
+	default 6
+	range 0 7
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+endif # !STM32H7_PWM_MULTICHAN
+
+endif # STM32H7_TIM16_PWM
+
+config STM32H7_TIM17_PWM
+	bool "TIM17 PWM"
+	default n
+	depends on STM32H7_TIM17
+	select STM32H7_PWM
+	---help---
+		Reserve timer 17 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If STM32H7_TIM17
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+if STM32H7_TIM17_PWM
+
+config STM32H7_TIM17_LOCK
+	int "TIM17 Lock Level Configuration"
+	default 0
+	range 0 3
+	---help---
+		Timer 17 lock level configuration
+
+config STM32H7_TIM17_TDTS
+	int "TIM17 t_DTS Division"
+	default 0
+	range 0 2
+	---help---
+		Timer 17 dead-time and sampling clock (t_DTS) division
+
+config STM32H7_TIM17_DEADTIME
+	int "TIM17 Initial Dead-time"
+	default 0
+	range 0 255
+	---help---
+		Timer 17 initial dead-time
+
+if STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM17_CHANNEL1
+	bool "TIM17 Channel 1"
+	default n
+	---help---
+		Enables channel 1.
+
+if STM32H7_TIM17_CHANNEL1
+
+config STM32H7_TIM17_CH1MODE
+	int "TIM17 Channel 1 Mode"
+	default 6
+	range 0 7
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+config STM32H7_TIM17_CH1OUT
+	bool "TIM17 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM17_CHANNEL1
+
+endif # STM32H7_PWM_MULTICHAN
+
+if !STM32H7_PWM_MULTICHAN
+
+config STM32H7_TIM17_CHANNEL
+	int "TIM17 PWM Output Channel"
+	default 1
+	range 1 1
+	---help---
+		If TIM17 is enabled for PWM usage, you also need specifies the timer output
+		channel {1}
+
+if STM32H7_TIM17_CHANNEL = 1
+
+config STM32H7_TIM17_CH1OUT
+	bool "TIM17 Channel 1 Output"
+	default n
+	---help---
+		Enables channel 1 output.
+
+endif # STM32H7_TIM17_CHANNEL = 1
+
+config STM32H7_TIM17_CHMODE
+	int "TIM17 Channel Mode"
+	default 6
+	range 0 7
+	---help---
+		Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h.
+
+endif # !STM32H7_PWM_MULTICHAN
+
+endif # STM32H7_TIM17_PWM
+
+config STM32H7_PWM_MULTICHAN
+	bool "PWM Multiple Output Channels"
+	default n
+	depends on STM32H7_TIM1_PWM || STM32H7_TIM2_PWM || STM32H7_TIM3_PWM || STM32H7_TIM4_PWM || STM32H7_TIM5_PWM || STM32H7_TIM8_PWM || STM32H7_TIM12_PWM || STM32H7_TIM15_PWM
+	select ARCH_HAVE_PWM_MULTICHAN
+	---help---
+		Specifies that the PWM driver supports multiple output
+		channels per timer.
+
+config STM32H7_TIM1_CAP
+	bool "TIM1 Capture"
+	default n
+	depends on STM32H7_TIM1
+	---help---
+		Reserve timer 1 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32H7_TIM2_CAP
+	bool "TIM2 Capture"
+	default n
+	depends on STM32H7_TIM2
+	---help---
+		Reserve timer 2 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32H7_TIM3_CAP
+	bool "TIM3 Capture"
+	default n
+	depends on STM32H7_TIM3
+	---help---
+		Reserve timer 3 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32H7_TIM4_CAP
+	bool "TIM4 Capture"
+	default n
+	depends on STM32H7_TIM4
+	---help---
+		Reserve timer 4 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32H7_TIM5_CAP
+	bool "TIM5 Capture"
+	default n
+	depends on STM32H7_TIM5
+	---help---
+		Reserve timer 5 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32H7_TIM8_CAP
+	bool "TIM8 Capture"
+	default n
+	depends on STM32H7_TIM8
+	---help---
+		Reserve timer 8 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32H7_TIM12_CAP
+	bool "TIM12 Capture"
+	default n
+	depends on STM32H7_TIM12
+	---help---
+		Reserve timer 12 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32H7_TIM13_CAP
+	bool "TIM13 Capture"
+	default n
+	depends on STM32H7_TIM13
+	---help---
+		Reserve timer 13 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32H7_TIM14_CAP
+	bool "TIM14 Capture"
+	default n
+	depends on STM32H7_TIM14
+	---help---
+		Reserve timer 14 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32H7_TIM15_CAP
+	bool "TIM15 Capture"
+	default n
+	depends on STM32H7_TIM15
+	---help---
+		Reserve timer 15 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32H7_TIM16_CAP
+	bool "TIM16 Capture"
+	default n
+	depends on STM32H7_TIM16
+	---help---
+		Reserve timer 16 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+config STM32H7_TIM17_CAP
+	bool "TIM14 Capture"
+	default n
+	depends on STM32H7_TIM17
+	---help---
+		Reserve timer 17 for use by Capture
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to capture input.
+
+
+menu "STM32 TIMx Outputs Configuration"
+
+config STM32H7_TIM1_CH1POL
+	int "TIM1 Channel 1 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH1OUT
+	---help---
+		TIM1 Channel 1 output polarity
+
+config STM32H7_TIM1_CH1IDLE
+	int "TIM1 Channel 1 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH1OUT
+	---help---
+		TIM1 Channel 1 output IDLE
+
+config STM32H7_TIM1_CH1NPOL
+	int "TIM1 Channel 1 Complementary Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH1NOUT
+	---help---
+		TIM1 Channel 1 Complementary Output polarity
+
+config STM32H7_TIM1_CH1NIDLE
+	int "TIM1 Channel 1 Complementary Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH1NOUT
+	---help---
+		TIM1 Channel 1 Complementary Output IDLE
+
+config STM32H7_TIM1_CH2POL
+	int "TIM1 Channel 2 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH2OUT
+	---help---
+		TIM1 Channel 2 output polarity
+
+config STM32H7_TIM1_CH2IDLE
+	int "TIM1 Channel 2 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH2OUT
+	---help---
+		TIM1 Channel 2 output IDLE
+
+config STM32H7_TIM1_CH2NPOL
+	int "TIM1 Channel 2 Complementary Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH2NOUT
+	---help---
+		TIM1 Channel 2 Complementary Output polarity
+
+config STM32H7_TIM1_CH2NIDLE
+	int "TIM1 Channel 2 Complementary Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH2NOUT
+	---help---
+		TIM1 Channel 2 Complementary Output IDLE
+
+config STM32H7_TIM1_CH3POL
+	int "TIM1 Channel 3 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH3OUT
+	---help---
+		TIM1 Channel 3 output polarity
+
+config STM32H7_TIM1_CH3IDLE
+	int "TIM1 Channel 3 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH3OUT
+	---help---
+		TIM1 Channel 3 output IDLE
+
+config STM32H7_TIM1_CH3NPOL
+	int "TIM1 Channel 3 Complementary Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH3NOUT
+	---help---
+		TIM1 Channel 3 Complementary Output polarity
+
+config STM32H7_TIM1_CH3NIDLE
+	int "TIM1 Channel 3 Complementary Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH3NOUT
+	---help---
+		TIM1 Channel 3 Complementary Output IDLE
+
+config STM32H7_TIM1_CH4POL
+	int "TIM1 Channel 4 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH4OUT
+	---help---
+		TIM1 Channel 4 output polarity
+
+config STM32H7_TIM1_CH4IDLE
+	int "TIM1 Channel 4 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH4OUT
+	---help---
+		TIM1 Channel 4 output IDLE
+
+config STM32H7_TIM1_CH5POL
+	int "TIM1 Channel 5 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH5OUT
+	---help---
+		TIM1 Channel 5 output polarity
+
+config STM32H7_TIM1_CH5IDLE
+	int "TIM1 Channel 5 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH5OUT
+	---help---
+		TIM1 Channel 5 output IDLE
+
+config STM32H7_TIM1_CH6POL
+	int "TIM1 Channel 6 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH6OUT
+	---help---
+		TIM1 Channel 6 output polarity
+
+config STM32H7_TIM1_CH6IDLE
+	int "TIM1 Channel 6 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM1_CH6OUT
+	---help---
+		TIM1 Channel 6 output IDLE
+
+config STM32H7_TIM2_CH1POL
+	int "TIM2 Channel 1 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM2_CH1OUT
+	---help---
+		TIM2 Channel 1 output polarity
+
+config STM32H7_TIM2_CH1IDLE
+	int "TIM2 Channel 1 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM2_CH1OUT
+	---help---
+		TIM2 Channel 1 output IDLE
+
+config STM32H7_TIM2_CH2POL
+	int "TIM2 Channel 2 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM2_CH2OUT
+	---help---
+		TIM2 Channel 2 output polarity
+
+config STM32H7_TIM2_CH2IDLE
+	int "TIM2 Channel 2 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM2_CH2OUT
+	---help---
+		TIM2 Channel 2 output IDLE
+
+config STM32H7_TIM2_CH3POL
+	int "TIM2 Channel 3 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM2_CH3OUT
+	---help---
+		TIM2 Channel 3 output polarity
+
+config STM32H7_TIM2_CH3IDLE
+	int "TIM2 Channel 3 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM2_CH3OUT
+	---help---
+		TIM2 Channel 3 output IDLE
+
+config STM32H7_TIM2_CH4POL
+	int "TIM2 Channel 4 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM2_CH4OUT
+	---help---
+		TIM2 Channel 4 output polarity
+
+config STM32H7_TIM2_CH4IDLE
+	int "TIM2 Channel 4 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM2_CH4OUT
+	---help---
+		TIM2 Channel 4 output IDLE
+
+config STM32H7_TIM3_CH1POL
+	int "TIM3 Channel 1 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM3_CH1OUT
+	---help---
+		TIM3 Channel 1 output polarity
+
+config STM32H7_TIM3_CH1IDLE
+	int "TIM3 Channel 1 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM3_CH1OUT
+	---help---
+		TIM3 Channel 1 output IDLE
+
+config STM32H7_TIM3_CH2POL
+	int "TIM3 Channel 2 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM3_CH2OUT
+	---help---
+		TIM3 Channel 2 output polarity
+
+config STM32H7_TIM3_CH2IDLE
+	int "TIM3 Channel 2 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM3_CH2OUT
+	---help---
+		TIM3 Channel 2 output IDLE
+
+config STM32H7_TIM3_CH3POL
+	int "TIM3 Channel 3 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM3_CH3OUT
+	---help---
+		TIM3 Channel 3 output polarity
+
+config STM32H7_TIM3_CH3IDLE
+	int "TIM3 Channel 3 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM3_CH3OUT
+	---help---
+		TIM3 Channel 3 output IDLE
+
+config STM32H7_TIM3_CH4POL
+	int "TIM3 Channel 4 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM3_CH4OUT
+	---help---
+		TIM3 Channel 4 output polarity
+
+config STM32H7_TIM3_CH4IDLE
+	int "TIM3 Channel 4 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM3_CH4OUT
+	---help---
+		TIM3 Channel 4 output IDLE
+
+config STM32H7_TIM4_CH1POL
+	int "TIM4 Channel 1 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM4_CH1OUT
+	---help---
+		TIM4 Channel 1 output polarity
+
+config STM32H7_TIM4_CH1IDLE
+	int "TIM4 Channel 1 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM4_CH1OUT
+	---help---
+		TIM4 Channel 1 output IDLE
+
+config STM32H7_TIM4_CH2POL
+	int "TIM4 Channel 2 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM4_CH2OUT
+	---help---
+		TIM4 Channel 2 output polarity
+
+config STM32H7_TIM4_CH2IDLE
+	int "TIM4 Channel 2 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM4_CH2OUT
+	---help---
+		TIM4 Channel 2 output IDLE
+
+config STM32H7_TIM4_CH3POL
+	int "TIM4 Channel 3 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM4_CH3OUT
+	---help---
+		TIM4 Channel 3 output polarity
+
+config STM32H7_TIM4_CH3IDLE
+	int "TIM4 Channel 3 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM4_CH3OUT
+	---help---
+		TIM4 Channel 3 output IDLE
+
+config STM32H7_TIM4_CH4POL
+	int "TIM4 Channel 4 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM4_CH4OUT
+	---help---
+		TIM4 Channel 4 output polarity
+
+config STM32H7_TIM4_CH4IDLE
+	int "TIM4 Channel 4 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM4_CH4OUT
+	---help---
+		TIM4 Channel 4 output IDLE
+
+config STM32H7_TIM5_CH1POL
+	int "TIM5 Channel 1 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM5_CH1OUT
+	---help---
+		TIM5 Channel 1 output polarity
+
+config STM32H7_TIM5_CH1IDLE
+	int "TIM5 Channel 1 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM5_CH1OUT
+	---help---
+		TIM5 Channel 1 output IDLE
+
+config STM32H7_TIM5_CH2POL
+	int "TIM5 Channel 2 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM5_CH2OUT
+	---help---
+		TIM5 Channel 2 output polarity
+
+config STM32H7_TIM5_CH2IDLE
+	int "TIM5 Channel 2 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM5_CH2OUT
+	---help---
+		TIM5 Channel 2 output IDLE
+
+config STM32H7_TIM5_CH3POL
+	int "TIM5 Channel 3 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM5_CH3OUT
+	---help---
+		TIM5 Channel 3 output polarity
+
+config STM32H7_TIM5_CH3IDLE
+	int "TIM5 Channel 3 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM5_CH3OUT
+	---help---
+		TIM5 Channel 3 output IDLE
+
+config STM32H7_TIM5_CH4POL
+	int "TIM5 Channel 4 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM5_CH4OUT
+	---help---
+		TIM5 Channel 4 output polarity
+
+config STM32H7_TIM5_CH4IDLE
+	int "TIM5 Channel 4 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM5_CH4OUT
+	---help---
+		TIM5 Channel 4 output IDLE
+
+config STM32H7_TIM8_CH1POL
+	int "TIM8 Channel 1 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH1OUT
+	---help---
+		TIM8 Channel 1 output polarity
+
+config STM32H7_TIM8_CH1IDLE
+	int "TIM8 Channel 1 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH1OUT
+	---help---
+		TIM8 Channel 1 output IDLE
+
+config STM32H7_TIM8_CH1NPOL
+	int "TIM8 Channel 1 Complementary Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH1NOUT
+	---help---
+		TIM8 Channel 1 Complementary Output polarity
+
+config STM32H7_TIM8_CH1NIDLE
+	int "TIM8 Channel 1 Complementary Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH1NOUT
+	---help---
+		TIM8 Channel 1 Complementary Output IDLE
+
+config STM32H7_TIM8_CH2POL
+	int "TIM8 Channel 2 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH2OUT
+	---help---
+		TIM8 Channel 2 output polarity
+
+config STM32H7_TIM8_CH2IDLE
+	int "TIM8 Channel 2 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH2OUT
+	---help---
+		TIM8 Channel 2 output IDLE
+
+config STM32H7_TIM8_CH2NPOL
+	int "TIM8 Channel 2 Complementary Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH2NOUT
+	---help---
+		TIM8 Channel 2 Complementary Output polarity
+
+config STM32H7_TIM8_CH2NIDLE
+	int "TIM8 Channel 2 Complementary Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH2NOUT
+	---help---
+		TIM8 Channel 2 Complementary Output IDLE
+
+config STM32H7_TIM8_CH3POL
+	int "TIM8 Channel 3 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH3OUT
+	---help---
+		TIM8 Channel 3 output polarity
+
+config STM32H7_TIM8_CH3IDLE
+	int "TIM8 Channel 3 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH3OUT
+	---help---
+		TIM8 Channel 3 output IDLE
+
+config STM32H7_TIM8_CH3NPOL
+	int "TIM8 Channel 3 Complementary Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH3NOUT
+	---help---
+		TIM8 Channel 3 Complementary Output polarity
+
+config STM32H7_TIM8_CH3NIDLE
+	int "TIM8 Channel 3 Complementary Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH3NOUT
+	---help---
+		TIM8 Channel 3 Complementary Output IDLE
+
+config STM32H7_TIM8_CH4POL
+	int "TIM8 Channel 4 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH4OUT
+	---help---
+		TIM8 Channel 4 output polarity
+
+config STM32H7_TIM8_CH4IDLE
+	int "TIM8 Channel 4 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH4OUT
+	---help---
+		TIM8 Channel 4 output IDLE
+
+config STM32H7_TIM8_CH5POL
+	int "TIM8 Channel 5 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH5OUT
+	---help---
+		TIM8 Channel 5 output polarity
+
+config STM32H7_TIM8_CH5IDLE
+	int "TIM8 Channel 5 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH5OUT
+	---help---
+		TIM8 Channel 5 output IDLE
+
+config STM32H7_TIM8_CH6POL
+	int "TIM8 Channel 6 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH6OUT
+	---help---
+		TIM8 Channel 6 output polarity
+
+config STM32H7_TIM8_CH6IDLE
+	int "TIM8 Channel 6 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM8_CH6OUT
+	---help---
+		TIM8 Channel 6 output IDLE
+
+config STM32H7_TIM12_CH1POL
+	int "TIM12 Channel 1 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM12_CH1OUT
+	---help---
+		TIM12 Channel 1 output polarity
+
+config STM32H7_TIM12_CH1IDLE
+	int "TIM12 Channel 1 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM12_CH1OUT
+	---help---
+		TIM12 Channel 1 output IDLE
+
+config STM32H7_TIM12_CH2POL
+	int "TIM12 Channel 2 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM12_CH2OUT
+	---help---
+		TIM12 Channel 2 output polarity
+
+config STM32H7_TIM12_CH2IDLE
+	int "TIM12 Channel 2 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM12_CH2OUT
+	---help---
+		TIM12 Channel 2 output IDLE
+
+config STM32H7_TIM13_CH1POL
+	int "TIM13 Channel 1 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM13_CH1OUT
+	---help---
+		TIM13 Channel 1 output polarity
+
+config STM32H7_TIM13_CH1IDLE
+	int "TIM13 Channel 1 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM13_CH1OUT
+	---help---
+		TIM13 Channel 1 output IDLE
+
+config STM32H7_TIM14_CH1POL
+	int "TIM14 Channel 1 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM14_CH1OUT
+	---help---
+		TIM14 Channel 1 output polarity
+
+config STM32H7_TIM14_CH1IDLE
+	int "TIM14 Channel 1 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM14_CH1OUT
+	---help---
+		TIM14 Channel 1 output IDLE
+
+config STM32H7_TIM15_CH1POL
+	int "TIM15 Channel 1 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM15_CH1OUT
+	---help---
+		TIM15 Channel 1 output polarity
+
+config STM32H7_TIM15_CH1IDLE
+	int "TIM15 Channel 1 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM15_CH1OUT
+	---help---
+		TIM15 Channel 1 output IDLE
+
+config STM32H7_TIM15_CH1NPOL
+	int "TIM15 Channel 1 Complementary Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM15_CH1NOUT
+	---help---
+		TIM15 Channel 1 Complementary Output polarity
+
+config STM32H7_TIM15_CH1NIDLE
+	int "TIM15 Channel 1 Complementary Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM15_CH1NOUT
+	---help---
+		TIM15 Channel 1 Complementary Output IDLE
+
+config STM32H7_TIM15_CH2POL
+	int "TIM15 Channel 2 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM15_CH2OUT
+	---help---
+		TIM15 Channel 2 output polarity
+
+config STM32H7_TIM15_CH2IDLE
+	int "TIM15 Channel 2 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM15_CH2OUT
+	---help---
+		TIM15 Channel 2 output IDLE
+
+config STM32H7_TIM15_CH2NPOL
+	int "TIM15 Channel 2 Complementary Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM15_CH2NOUT
+	---help---
+		TIM15 Channel 2 Complementary Output polarity
+
+config STM32H7_TIM15_CH2NIDLE
+	int "TIM15 Channel 2 Complementary Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM15_CH2NOUT
+	---help---
+		TIM15 Channel 2 Complementary Output IDLE
+
+config STM32H7_TIM16_CH1POL
+	int "TIM16 Channel 1 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM16_CH1OUT
+	---help---
+		TIM16 Channel 1 output polarity
+
+config STM32H7_TIM16_CH1IDLE
+	int "TIM16 Channel 1 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM16_CH1OUT
+	---help---
+		TIM16 Channel 1 output IDLE
+
+config STM32H7_TIM17_CH1POL
+	int "TIM17 Channel 1 Output polarity"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM17_CH1OUT
+	---help---
+		TIM17 Channel 1 output polarity
+
+config STM32H7_TIM17_CH1IDLE
+	int "TIM17 Channel 1 Output IDLE"
+	default 0
+	range 0 1
+	depends on STM32H7_TIM17_CH1OUT
+	---help---
+		TIM17 Channel 1 output IDLE
+
+endmenu #STM32 TIMx Outputs Configuration
+
+endmenu # Timer Configuration
+
+menu "Ethernet MAC configuration"
+	depends on STM32H7_ETHMAC
+
+config STM32H7_PHYADDR
+	int "PHY address"
+	default 0
+	---help---
+		The 5-bit address of the PHY on the board.  Default: 1
+
+config STM32H7_PHYINIT
+	bool "Board-specific PHY Initialization"
+	default n
+	---help---
+		Some boards require specialized initialization of the PHY before it can be used.
+		This may include such things as configuring GPIOs, resetting the PHY, etc.  If
+		STM32H7_PHYINIT is defined in the configuration then the board specific logic must
+		provide stm32_phyinitialize();  The STM32 Ethernet driver will call this function
+		one time before it first uses the PHY.
+
+config STM32H7_MII
+	bool "Use MII interface"
+	default n
+	---help---
+		Support Ethernet MII interface.
+
+choice
+	prompt "MII clock configuration"
+	default STM32H7_MII_EXTCLK
+	depends on STM32H7_MII
+
+config STM32H7_MII_MCO1
+	bool "Use MC01 as MII clock"
+	---help---
+		Use MCO1 to clock the MII interface.
+
+config STM32H7_MII_MCO2
+	bool "Use MC02 as MII clock"
+	---help---
+		Use MCO2 to clock the MII interface.
+
+config STM32H7_MII_EXTCLK
+	bool "External MII clock"
+	---help---
+		Clocking is provided by external logic.
+
+endchoice
+
+config STM32H7_AUTONEG
+	bool "Use autonegotiation"
+	default y
+	---help---
+		Use PHY autonegotiation to determine speed and mode
+
+config STM32H7_ETHFD
+	bool "Full duplex"
+	default n
+	depends on !STM32H7_AUTONEG
+	---help---
+		If STM32H7_AUTONEG is not defined, then this may be defined to select full duplex
+		mode. Default: half-duplex
+
+config STM32H7_ETH100MBPS
+	bool "100 Mbps"
+	default n
+	depends on !STM32H7_AUTONEG
+	---help---
+		If STM32H7_AUTONEG is not defined, then this may be defined to select 100 MBps
+		speed.  Default: 10 Mbps
+
+config STM32H7_PHYSR
+	int "PHY Status Register Address (decimal)"
+	depends on STM32H7_AUTONEG
+	---help---
+		This must be provided if STM32H7_AUTONEG is defined.  The PHY status register
+		address may diff from PHY to PHY.  This configuration sets the address of
+		the PHY status register.
+
+config STM32H7_PHYSR_ALTCONFIG
+	bool "PHY Status Alternate Bit Layout"
+	default n
+	depends on STM32H7_AUTONEG
+	---help---
+		Different PHYs present speed and mode information in different ways.  Some
+		will present separate information for speed and mode (this is the default).
+		Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
+		full/half duplex indication. This options selects an alternative representation
+		where speed and mode information are combined.  This might mean, for example,
+		separate bits for 10HD, 100HD, 10FD and 100FD.
+
+config STM32H7_PHYSR_SPEED
+	hex "PHY Speed Mask"
+	depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if STM32H7_AUTONEG is defined.  This provides bit mask
+		for isolating the 10 or 100MBps speed indication.
+
+config STM32H7_PHYSR_100MBPS
+	hex "PHY 100Mbps Speed Value"
+	depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if STM32H7_AUTONEG is defined.  This provides the value
+		of the speed bit(s) indicating 100MBps speed.
+
+config STM32H7_PHYSR_MODE
+	hex "PHY Mode Mask"
+	depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if STM32H7_AUTONEG is defined.  This provide bit mask
+		for isolating the full or half duplex mode bits.
+
+config STM32H7_PHYSR_FULLDUPLEX
+	hex "PHY Full Duplex Mode Value"
+	depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if STM32H7_AUTONEG is defined.  This provides the
+		value of the mode bits indicating full duplex mode.
+
+config STM32H7_PHYSR_ALTMODE
+	hex "PHY Mode Mask"
+	depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if STM32H7_AUTONEG is defined.  This provide bit mask
+		for isolating the speed and full/half duplex mode bits.
+
+config STM32H7_PHYSR_10HD
+	hex "10MBase-T Half Duplex Value"
+	depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if STM32H7_AUTONEG is defined.  This is the value
+		under the bit mask that represents the 10Mbps, half duplex setting.
+
+config STM32H7_PHYSR_100HD
+	hex "100Base-T Half Duplex Value"
+	depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if STM32H7_AUTONEG is defined.  This is the value
+		under the bit mask that represents the 100Mbps, half duplex setting.
+
+config STM32H7_PHYSR_10FD
+	hex "10Base-T Full Duplex Value"
+	depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if STM32H7_AUTONEG is defined.  This is the value
+		under the bit mask that represents the 10Mbps, full duplex setting.
+
+config STM32H7_PHYSR_100FD
+	hex "100Base-T Full Duplex Value"
+	depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if STM32H7_AUTONEG is defined.  This is the value
+		under the bit mask that represents the 100Mbps, full duplex setting.
+
+config STM32H7_ETH_PTP
+	bool "Precision Time Protocol (PTP)"
+	default n
+	---help---
+		Precision Time Protocol (PTP).  Not supported but some hooks are indicated
+		with this condition.
+
+config STM32H7_RMII
+	bool
+	default y if !STM32H7_MII
+
+choice
+	prompt "RMII clock configuration"
+	default STM32H7_RMII_EXTCLK
+	depends on STM32H7_RMII
+
+config STM32H7_RMII_MCO1
+	bool "Use MC01 as RMII clock"
+	---help---
+		Use MCO1 to clock the RMII interface.
+
+config STM32H7_RMII_MCO2
+	bool "Use MC02 as RMII clock"
+	---help---
+		Use MCO2 to clock the RMII interface.
+
+config STM32H7_RMII_EXTCLK
+	bool "External RMII clock"
+	---help---
+		Clocking is provided by external logic.
+
+endchoice # RMII clock configuration
+
+config STM32H7_ETHMAC_REGDEBUG
+	bool "Register-Level Debug"
+	default n
+	depends on DEBUG_NET_INFO
+	---help---
+		Enable very low-level register access debug.  Depends on
+		CONFIG_DEBUG_FEATURES.
+
+endmenu # Ethernet MAC configuration
+
 endif # ARCH_CHIP_STM32H7
diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs
index ba523251f56..6047e2a8e83 100644
--- a/arch/arm/src/stm32h7/Make.defs
+++ b/arch/arm/src/stm32h7/Make.defs
@@ -80,11 +80,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
@@ -116,6 +114,10 @@ ifeq ($(CONFIG_STM32H7_SPI),y)
 CHIP_CSRCS += stm32_spi.c
 endif
 
+ifeq ($(CONFIG_STM32H7_SDMMC),y)
+CHIP_CSRCS += stm32_sdmmc.c
+endif
+
 ifeq ($(CONFIG_USBDEV),y)
 CHIP_CSRCS += stm32_otgdev.c
 endif
@@ -123,3 +125,15 @@ endif
 ifeq ($(CONFIG_USBHOST),y)
 CHIP_CSRCS += stm32_otghost.c
 endif
+
+ifeq ($(CONFIG_STM32H7_TIM),y)
+CHIP_CSRCS += stm32_tim.c
+endif
+
+ifeq ($(CONFIG_STM32H7_PWM),y)
+CHIP_CSRCS += stm32_pwm.c
+endif
+
+ifeq ($(CONFIG_STM32H7_ETHMAC),y)
+CHIP_CSRCS += stm32_ethernet.c
+endif
diff --git a/arch/arm/src/stm32h7/chip.h b/arch/arm/src/stm32h7/chip.h
index 127f5c2a661..7326b8eb959 100644
--- a/arch/arm/src/stm32h7/chip.h
+++ b/arch/arm/src/stm32h7/chip.h
@@ -48,8 +48,12 @@
 
 #include 
 #include 
-#include "chip/stm32_pinmap.h"
-#include "chip/stm32_memorymap.h"
+#include "hardware/stm32_pinmap.h"
+#include "hardware/stm32_memorymap.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
 
 /* If the common ARMv7-M vector handling logic is used, then it expects the
  * following definition in this file that provides the number of supported external
@@ -64,10 +68,6 @@
 #define ARMV7M_DCACHE_LINESIZE 32  /* 32 bytes (8 words) */
 #define ARMV7M_ICACHE_LINESIZE 32  /* 32 bytes (8 words) */
 
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
 /************************************************************************************
  * Public Types
  ************************************************************************************/
diff --git a/arch/arm/src/stm32h7/chip/stm32_bdma.h b/arch/arm/src/stm32h7/hardware/stm32_bdma.h
similarity index 98%
rename from arch/arm/src/stm32h7/chip/stm32_bdma.h
rename to arch/arm/src/stm32h7/hardware/stm32_bdma.h
index e6b3fe52753..b989a460a5b 100644
--- a/arch/arm/src/stm32h7/chip/stm32_bdma.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_bdma.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_bdma.h
+ * arch/arm/src/stm32h7/hardware/stm32_bdma.h
  *
  *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_BDMA_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_BDMA_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_BDMA_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_BDMA_H
 
 /************************************************************************************
  * Included Files
@@ -260,4 +260,4 @@
 #define BDMA_CNDTR_NDT_SHIFT       (0)       /* Bits 15-0: Number of data to Transfer */
 #define BDMA_CNDTR_NDT_MASK        (0xffff << BDMA_CNDTR_NDT_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_BDMA_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_BDMA_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32_dma.h b/arch/arm/src/stm32h7/hardware/stm32_dma.h
similarity index 99%
rename from arch/arm/src/stm32h7/chip/stm32_dma.h
rename to arch/arm/src/stm32h7/hardware/stm32_dma.h
index ceeb5121160..94d7ed754ae 100644
--- a/arch/arm/src/stm32h7/chip/stm32_dma.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_dma.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_dma.h
+ * arch/arm/src/stm32h7/hardware/stm32_dma.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMA_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMA_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_DMA_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_DMA_H
 
 /************************************************************************************
  * Included Files
@@ -373,4 +373,4 @@
 #define DMA_SFCR_FEIE             (1 << 7)  /* Bit 7:  FIFO error interrupt enable */
                                             /* Bits 8-31: Reserved */
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMA_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_DMA_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32_dmamux.h b/arch/arm/src/stm32h7/hardware/stm32_dmamux.h
similarity index 97%
rename from arch/arm/src/stm32h7/chip/stm32_dmamux.h
rename to arch/arm/src/stm32h7/hardware/stm32_dmamux.h
index 10b6642e290..c4c37595838 100644
--- a/arch/arm/src/stm32h7/chip/stm32_dmamux.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_dmamux.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_dmamux.h
+ * arch/arm/src/stm32h7/hardware/stm32_dmamux.h
  *
  *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMAMUX_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMAMUX_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_DMAMUX_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_DMAMUX_H
 
 /************************************************************************************
  * Included Files
@@ -48,7 +48,7 @@
  ************************************************************************************/
 
 #define DMAMUX1 0
-#define DMAMUX2 0
+#define DMAMUX2 1
 
 /* Register Offsets *****************************************************************/
 
@@ -203,9 +203,9 @@
 /* Import DMAMUX map */
 
 #if defined(CONFIG_STM32H7_STM32H7X3XX)
-#  include "chip/stm32h7x3xx_dmamux.h"
+#  include "hardware/stm32h7x3xx_dmamux.h"
 #else
 #  error "Unsupported STM32 H7 sub family"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_DMAMUX_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_DMAMUX_H */
diff --git a/arch/arm/src/stm32h7/hardware/stm32_ethernet.h b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h
new file mode 100644
index 00000000000..c82dc805978
--- /dev/null
+++ b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h
@@ -0,0 +1,676 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32h7/hardware/stm32_ethernet.h
+ *
+ *   Authors: Jukka Laitinen 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_ETHERNET_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_ETHERNET_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include 
+
+/* Content of this file requires verification before it is used with other
+ * families
+ */
+
+#if defined(CONFIG_STM32H7_STM32H7X3XX)
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Register Offsets *********************************************************************************/
+
+/* MAC Registers */
+
+#define STM32_ETH_MACCR_OFFSET       0x0000 /* Ethernet MAC configuration register */
+#define STM32_ETH_MAECR_OFFSET       0x0004 /* Ethernet MAC Extended operating mode configuration register */
+#define STM32_ETH_MACPFR_OFFSET      0x0008 /* Ethernet MAC Packet filtering control register */
+#define STM32_ETH_MACWTR_OFFSET      0x000C /* Ethernet MAC Watchdog timeout register */
+#define STM32_ETH_MACHT0R_OFFSET     0x0010 /* Ethernet MAC hash table high register */
+#define STM32_ETH_MACHT1R_OFFSET     0x0014 /* Ethernet MAC hash table low register */
+#define STM32_ETH_MACVTR_OFFSET      0x0050 /* Ethernet MAC VLAN tag register */
+#define STM32_ETH_MACQTXFCR_OFFSET   0x0070 /* Ethernet MAC Tx Queue flow control register */
+#define STM32_ETH_MACRXFCR_OFFSET    0x0090 /* Ethernet MAC Tx Queue flow control register */
+
+#define STM32_ETH_MACISR_OFFSET      0x00B0 /* Ethernet MAC interrupt status register */
+#define STM32_ETH_MACIER_OFFSET      0x00B4 /* Ethernet MAC interrupt enable register */
+
+#define STM32_ETH_MACMDIOAR_OFFSET   0x0200 /* Ethernet MAC MDIO address register */
+#define STM32_ETH_MACMDIODR_OFFSET   0x0204 /* Ethernet MAC MDIO data register */
+#define STM32_ETH_MACA0LR_OFFSET     0x0304 /* Address 0 low register */
+#define STM32_ETH_MACA0HR_OFFSET     0x0308 /* Address 0 high register */
+
+/* MTL Registers */
+
+#define STM32_ETH_MTLOMR_OFFSET      0x0C00 /* Operating mode Register */
+#define STM32_ETH_MTLISR_OFFSET      0x0C20 /* Interrupt status Register */
+#define STM32_ETH_MTLTXQOMR_OFFSET   0x0D00 /* Tx queue operating mode Register */
+#define STM32_ETH_MTLTXQUR_OFFSET    0x0D04 /* Tx queue underflow register */
+#define STM32_ETH_MTLTXQDR_OFFSET    0x0D08 /* Tx queue debug register */
+#define STM32_ETH_MTLQICSR_OFFSET    0x0D2C /* Queue interrupt control status Register */
+#define STM32_ETH_MTLRXQOMR_OFFSET   0x0D30 /* Rx queue operating mode register */
+#define STM32_ETH_MTLRXQMPOCR_OFFSET 0x0D34 /* Rx queue missed packet and overflow counter register */
+#define STM32_ETH_MTLRXQDR_OFFSE     0x0D38 /* Rx queue debug register */
+
+/* DMA Registers */
+
+#define STM32_ETH_DMAMR_OFFSET       0x1000 /* Ethernet DMA Mode register */
+#define STM32_ETH_DMASBMR_OFFSET     0x1004 /* Ethernet DMA system bus mode register */
+#define STM32_ETH_DMAISR_OFFSET      0x1008 /* Ethernet DMA Interrupt status register */
+#define STM32_ETH_DMADSR_OFFSET      0x100C /* Ethernet DMA Debug status register */
+#define STM32_ETH_DMACCR_OFFSET      0x1100 /* Ethernet DMA Channel control register */
+#define STM32_ETH_DMACTXCR_OFFSET    0x1104 /* Ethernet DMA Channel transmit control register */
+#define STM32_ETH_DMACRXCR_OFFSET    0x1108 /* Ethernet DMA Channel receive control register */
+#define STM32_ETH_DMACTXDLAR_OFFSET  0x1114 /* Ethernet DMA Channel Tx descriptor list address register */
+#define STM32_ETH_DMACRXDLAR_OFFSET  0x111C /* Ethernet DMA Channel Rx descriptor list address register */
+#define STM32_ETH_DMACTXDTPR_OFFSET  0x1120 /* Ethernet DMA Channel Tx descriptor tail pointer register */
+#define STM32_ETH_DMACRXDTPR_OFFSET  0x1128 /* Ethernet DMA Channel Rx descriptor tail pointer register */
+#define STM32_ETH_DMACTXRLR_OFFSET   0x112C /* Ethernet DMA Channel Tx descriptor ring length register */
+#define STM32_ETH_DMACRXRLR_OFFSET   0x1130 /* Ethernet DMA Channel Rx descriptor ring length register */
+#define STM32_ETH_DMACIER_OFFSET     0x1134 /* Ethernet DMA Channel interrupt enable register */
+#define STM32_ETH_DMACRXIWTR_OFFSET  0x1138 /* Ethernet DMA Channel Rx interrupt wdt register */
+#define STM32_ETH_DMACCATXDR_OFFSET  0x1144 /* Ethernet DMA Channel current application transmit descriptor register */
+#define STM32_ETH_DMACCARXDR_OFFSET  0x114C /* Ethernet DMA Channel current application receive descriptor register */
+#define STM32_ETH_DMACCATXBR_OFFSET  0x1154 /* Ethernet DMA Channel current application transmit buffer register */
+#define STM32_ETH_DMACCARXBR_OFFSET  0x115C /* Ethernet DMA Channel current application receive buffer register */
+#define STM32_ETH_DMACSR_OFFSET      0x1160 /* Ethernet DMA Channel status register */
+#define STM32_ETH_DMACMFCR_OFFSET    0x116C /* Ethernet DMA Channel missed frame count register */
+
+/* Register Base Addresses **************************************************************************/
+
+/* MAC Registers */
+
+#define STM32_ETH_MACCR              (STM32_EMAC_BASE+STM32_ETH_MACCR_OFFSET)
+#define STM32_ETH_MACPFR             (STM32_EMAC_BASE+STM32_ETH_MACPFR_OFFSET)
+#define STM32_ETH_MACHT0R            (STM32_EMAC_BASE+STM32_ETH_MACHT0R_OFFSET)
+#define STM32_ETH_MACHT1R            (STM32_EMAC_BASE+STM32_ETH_MACHT1R_OFFSET)
+#define STM32_ETH_MACVTR             (STM32_EMAC_BASE+STM32_ETH_MACVTR_OFFSET)
+#define STM32_ETH_MACQTXFCR          (STM32_EMAC_BASE+STM32_ETH_MACQTXFCR_OFFSET)
+#define STM32_ETH_MACRXFCR           (STM32_EMAC_BASE+STM32_ETH_MACRXFCR_OFFSET)
+#define STM32_ETH_MACISR             (STM32_EMAC_BASE+STM32_ETH_MACISR_OFFSET)
+#define STM32_ETH_MACIER             (STM32_EMAC_BASE+STM32_ETH_MACIER_OFFSET)
+
+#define STM32_ETH_MACMDIOAR          (STM32_EMAC_BASE+STM32_ETH_MACMDIOAR_OFFSET)
+#define STM32_ETH_MACMDIODR          (STM32_EMAC_BASE+STM32_ETH_MACMDIODR_OFFSET)
+#define STM32_ETH_MACA0LR            (STM32_EMAC_BASE+STM32_ETH_MACA0LR_OFFSET)
+#define STM32_ETH_MACA0HR            (STM32_EMAC_BASE+STM32_ETH_MACA0HR_OFFSET)
+
+/* MTL Registers */
+
+#define STM32_ETH_MTLOMR             (STM32_EMAC_BASE+STM32_ETH_MTLOMR_OFFSET)
+#define STM32_ETH_MTLISR             (STM32_EMAC_BASE+STM32_ETH_MTLISR_OFFSET)
+#define STM32_ETH_MTLTXQOMR          (STM32_EMAC_BASE+STM32_ETH_MTLTXQOMR_OFFSET)
+#define STM32_ETH_MTLTXQUR           (STM32_EMAC_BASE+STM32_ETH_MTLTXQUR_OFFSET)
+#define STM32_ETH_MTLTXQDR           (STM32_EMAC_BASE+STM32_ETH_MTLTXQDR_OFFSET)
+#define STM32_ETH_MTLQICSR           (STM32_EMAC_BASE+STM32_ETH_MTLQICSR_OFFSET)
+#define STM32_ETH_MTLRXQOMR          (STM32_EMAC_BASE+STM32_ETH_MTLRXQOMR_OFFSET)
+#define STM32_ETH_MTLRXQMPOCR        (STM32_EMAC_BASE+STM32_ETH_MTLRXQMPOCR_OFFSET)
+#define STM32_ETH_MTLRXQDR           (STM32_EMAC_BASE+STM32_ETH_MTLRXQDR_OFFSE)
+
+/* DMA Registers */
+
+#define STM32_ETH_DMAMR              (STM32_EMAC_BASE+STM32_ETH_DMAMR_OFFSET)
+#define STM32_ETH_DMASBMR            (STM32_EMAC_BASE+STM32_ETH_DMASBMR_OFFSET)
+#define STM32_ETH_DMAISR             (STM32_EMAC_BASE+STM32_ETH_DMAISR_OFFSET)
+#define STM32_ETH_DMADSR             (STM32_EMAC_BASE+STM32_ETH_DMADSR_OFFSET)
+#define STM32_ETH_DMACCR             (STM32_EMAC_BASE+STM32_ETH_DMACCR_OFFSET)
+#define STM32_ETH_DMACTXCR           (STM32_EMAC_BASE+STM32_ETH_DMACTXCR_OFFSET)
+#define STM32_ETH_DMACRXCR           (STM32_EMAC_BASE+STM32_ETH_DMACRXCR_OFFSET)
+#define STM32_ETH_DMACTXDLAR         (STM32_EMAC_BASE+STM32_ETH_DMACTXDLAR_OFFSET)
+#define STM32_ETH_DMACRXDLAR         (STM32_EMAC_BASE+STM32_ETH_DMACRXDLAR_OFFSET)
+#define STM32_ETH_DMACTXDTPR         (STM32_EMAC_BASE+STM32_ETH_DMACTXDTPR_OFFSET)
+#define STM32_ETH_DMACRXDTPR         (STM32_EMAC_BASE+STM32_ETH_DMACRXDTPR_OFFSET)
+#define STM32_ETH_DMACTXRLR          (STM32_EMAC_BASE+STM32_ETH_DMACTXRLR_OFFSET)
+#define STM32_ETH_DMACRXRLR          (STM32_EMAC_BASE+STM32_ETH_DMACRXRLR_OFFSET)
+#define STM32_ETH_DMACIER            (STM32_EMAC_BASE+STM32_ETH_DMACIER_OFFSET)
+#define STM32_ETH_DMACRXIWTR         (STM32_EMAC_BASE+STM32_ETH_DMACRXIWTR_OFFSET)
+#define STM32_ETH_DMACCATXDR         (STM32_EMAC_BASE+STM32_ETH_DMACCATXDR_OFFSET)
+#define STM32_ETH_DMACCARXDR         (STM32_EMAC_BASE+STM32_ETH_DMACCARXDR_OFFSET)
+#define STM32_ETH_DMACCATXBR         (STM32_EMAC_BASE+STM32_ETH_DMACCATXBR_OFFSET)
+#define STM32_ETH_DMACCARXBR         (STM32_EMAC_BASE+STM32_ETH_DMACCARXBR_OFFSET)
+#define STM32_ETH_DMACSR             (STM32_EMAC_BASE+STM32_ETH_DMACSR_OFFSET)
+#define STM32_ETH_DMACMFCR           (STM32_EMAC_BASE+STM32_ETH_DMACMFCR_OFFSET)
+
+/* Register Bit-Field Definitions *******************************************************************/
+
+/* MAC Registers */
+
+/* Ethernet MAC configuration register */
+
+#define ETH_MACCR_RE                 (1 << 0)  /* Bit 0:  Receiver enable */
+#define ETH_MACCR_TE                 (1 << 1)  /* Bit 1:  Transmitter enable */
+#define ETH_MACCR_PRELEN_SHIFT       (2)       /* Bits 2-3: Preample length for transmit packets */
+#define ETH_MACCR_PRELEN_MASK        (3 << ETH_MACCR_PRELEN_SHIFT)
+#  define ETH_MACCR_PRELEN_7         (0 << ETH_MACCR_PRELEN_SHIFT) /* 00: 7 bytes of preamble */
+#  define ETH_MACCR_PRELEN_5         (1 << ETH_MACCR_PRELEN_SHIFT) /* 01: 5 bytes of preamble */
+#  define ETH_MACCR_PRELEN_3         (2 << ETH_MACCR_PRELEN_SHIFT) /* 10: 3 bytes of preamble */
+#define ETH_MACCR_DC                 (1 << 4)  /* Bit 4:  Deferral check */
+#define ETH_MACCR_BL_SHIFT           (5)       /* Bits 5-6: Back-off limit */
+#define ETH_MACCR_BL_MASK            (3 << ETH_MACCR_BL_SHIFT)
+#  define ETH_MACCR_BL_10            (0 << ETH_MACCR_BL_SHIFT) /* 00: k = min (n, 10) */
+#  define ETH_MACCR_BL_8             (1 << ETH_MACCR_BL_SHIFT) /* 01: k = min (n, 8) */
+#  define ETH_MACCR_BL_4             (2 << ETH_MACCR_BL_SHIFT) /* 10: k = min (n, 4) */
+#  define ETH_MACCR_BL_1             (3 << ETH_MACCR_BL_SHIFT) /* 11: k = min (n, 1) */
+#define ETH_MACCR_DR                 (1 << 8)  /* Bit 8:  Retry disable */
+#define ETH_MACCR_DCRS               (1 << 9)  /* Bit 9: Carrier sense disable */
+#define ETH_MACCR_DO                 (1 << 10) /* Bit 10: Disable receive own */
+#define ETH_MACCR_LM                 (1 << 12) /* Bit 12: Loopback mode */
+#define ETH_MACCR_DM                 (1 << 13) /* Bit 13: Duplex mode */
+#define ETH_MACCR_FES                (1 << 14) /* Bit 14: Fast Ethernet speed */
+#define ETH_MACCR_JE                 (1 << 16) /* Bit 16: Jumbo packet enable */
+#define ETH_MACCR_JD                 (1 << 17) /* Bit 17: Jabber disable */
+#define ETH_MACCR_WD                 (1 << 19) /* Bit 19: Watchdog disable */
+#define ETH_MACCR_ACS                (1 << 20) /* Bit 20:  Automatic pad/CRC stripping */
+#define ETH_MACCR_CST                (1 << 21) /* Bit 21: CRC stripping for Type frames */
+#define ETH_MACCR_S2KP               (1 << 22) /* Bit 22: IEEE 802.3as Support for 2K Packets */
+#define ETH_MACCR_GPSLCE             (1 << 23) /* Bit 23: Giant Packet Size Limit Control Enable */
+#define ETH_MACCR_IPG_SHIFT          (24)      /* Bits 24-26: Inter-packet gap */
+#define ETH_MACCR_IPG_MASK           (7 << ETH_MACCR_IPG_SHIFT)
+#  define ETH_MACCR_IPG(n)           ((12-((n) >> 3)) << ETH_MACCR_IPG_SHIFT) /* n bit times, n=40,48,..96 */
+#define ETH_MACCR_IPC                (1 << 27) /* Bit 27: IPv4 checksum offload */
+#define ETH_MACCR_SARC_SHIFT         (28)      /* Bits 28-30: Source Address Insertion or Replacement Control */
+#define ETH_MACCR_SARC_MASK          (7 << ETH_MACCR_SARC_SHIFT)
+#define ETH_MACCR_ARPEN              (1 << 31) /* Bit 31: ARP Offload Enable */
+
+/* Ethernet MAC frame filter register */
+
+#define ETH_MACPFR_PR                (1 << 0)  /* Bit 0: Promiscuous mode */
+#define ETH_MACPFR_HUC               (1 << 1)  /* Bit 1: Hash unicast */
+#define ETH_MACPFR_HMC               (1 << 2)  /* Bit 2: Hash multicast */
+#define ETH_MACPFR_DAIF              (1 << 3)  /* Bit 3: Destination address inverse filtering */
+#define ETH_MACPFR_PM                (1 << 4)  /* Bit 4: Pass all multicast */
+#define ETH_MACPFR_DBF               (1 << 5)  /* Bit 5: Disable broadcast packets */
+#define ETH_MACPFR_PCF_SHIFT         (6)       /* Bits 6-7: Pass control frames */
+#define ETH_MACPFR_PCF_MASK          (3 << ETH_MACPFR_PCF_SHIFT)
+#  define ETH_MACPFR_PCF_NONE        (0 << ETH_MACPFR_PCF_SHIFT) /* Prevents all control frames */
+#  define ETH_MACPFR_PCF_PAUSE       (1 << ETH_MACPFR_PCF_SHIFT) /* Prevents all except Pause control frames */
+#  define ETH_MACPFR_PCF_ALL         (2 << ETH_MACPFR_PCF_SHIFT) /* Forwards all control frames */
+#  define ETH_MACPFR_PCF_FILTER      (3 << ETH_MACPFR_PCF_SHIFT) /* Forwards all that pass address filter */
+#define ETH_MACPFR_SAIF              (1 << 8)  /* Bit 8: Source address inverse filtering */
+#define ETH_MACPFR_SAF               (1 << 9)  /* Bit 9: Source address filter */
+#define ETH_MACPFR_HPF               (1 << 10) /* Bit 10: Hash or perfect filter */
+#define ETH_MACPFR_VTFE              (1 << 16) /* Bit 16: VLAN Tag Filter Enable */
+#define ETH_MACPFR_IPFE              (1 << 20) /* Bit 20: Layer 3 and Layer 4 Filter Enable */
+#define ETH_MACPFR_DNTU              (1 << 21) /* Bit 21: Drop Non-TCP/UDP over IP Packets */
+#define ETH_MACPFR_RA                (1 << 31) /* Bit 31: Receive all */
+
+/* Ethernet MAC VLAN tag register */
+
+#define ETH_MACVTR_VL_SHIFT     (0)       /* Bits 0-15: VLAN tag identifier (for receive frames) */
+#define ETH_MACVTR_VL_MASK      (0xffff << ETH_MACVLANTR_VL_SHIFT)
+#  define ETH_MACVTR_VL(n)      ((uint32_t)(n) << ETH_MACVLANTR_VL_SHIFT)
+#define ETH_MACVLANTR_ETV       (1 << 16) /* Bit 16: Enable 12-Bit VLAN Tag Comparison */
+
+/* Ethernet MAC Tx Queue flow control register */
+
+#define ETH_MACQTXFCR_FCB_BPA           (1 << 0)  /* Bit 0: Flow control busy/back pressure activate */
+#define ETH_MACQTXFCR_TFE               (1 << 1)  /* Bit 1: Transmit flow control enable */
+#define ETH_MACQTXFCR_PLT_SHIFT         (4)       /* Bits 4-6: Pause low threshold */
+#define ETH_MACQTXFCR_PLT_MASK          (7 << ETH_MACQTXFCR_PLT_SHIFT)
+#  define ETH_MACQTXFCR_PLT_M4          (0 << ETH_MACQTXFCR_PLT_SHIFT) /* 000 PT - 4 slot times */
+#  define ETH_MACQTXFCR_PLT_M28         (1 << ETH_MACQTXFCR_PLT_SHIFT) /* 001 PT - 28 slot times */
+#  define ETH_MACQTXFCR_PLT_M36         (2 << ETH_MACQTXFCR_PLT_SHIFT) /* 010 PT - 36 slot times */
+#  define ETH_MACQTXFCR_PLT_M144        (3 << ETH_MACQTXFCR_PLT_SHIFT) /* 011 PT - 144 slot times */
+#  define ETH_MACQTXFCR_PLT_M256        (4 << ETH_MACQTXFCR_PLT_SHIFT) /* 100 PT - 256 slot times */
+#  define ETH_MACQTXFCR_PLT_M512        (5 << ETH_MACQTXFCR_PLT_SHIFT) /* 101 PT - 512 slot times */
+#define ETH_MACQTXFCR_DZPQ              (1 << 7)  /* Bit 7: Zero-quanta pause disable */
+#define ETH_MACQTXFCR_PT_SHIFT          (4)       /* Bits 16-31: Pause Time */
+#define ETH_MACQTXFCR_PT_MASK           (0xFFFF << ETH_MACQTXFCR_PT_SHIFT)
+#define ETH_MACQTXFCR_PT(n)             ((uint32_t)(n) << ETH_MACQTXFCR_PT_SHIFT)
+
+/* Ethernet MAC Rx flow control register */
+
+#define ETH_MACRXFCR_RFE              (1 << 0)  /* Bit 0: Receive flow control enable */
+#define ETH_MACRXFCR_UP               (1 << 1)  /* Bit 1: Unicast pause frame detect */
+
+/* Ethernet MAC interrupt status register */
+
+#define ETH_MACISR_PHYIS               (1 << 3)  /* Bit 3: PHY interrupt */
+#define ETH_MACISR_PMTIS               (1 << 4)  /* Bit 4: PMT Interrupt Status */
+#define ETH_MACISR_LPIIS               (1 << 5)  /* Bit 5: LPI Interrupt Status */
+#define ETH_MACISR_MMCIS               (1 << 8)  /* Bit 8: MMC Interrupt Status */
+#define ETH_MACISR_MMCRXIS             (1 << 9)  /* Bit 9: MMC Receive Interrupt Status */
+#define ETH_MACISR_MMCTXIS             (1 << 10) /* Bit 10: MMC Transmit Interrupt Status */
+#define ETH_MACISR_TSIS                (1 << 12) /* Bit 12: Timestamp Interrupt Status */
+#define ETH_MACISR_TXTSIS              (1 << 13) /* Bit 13: Transmit Status Interrupt */
+#define ETH_MACISR_RXSTSIS             (1 << 14) /* Bit 14: Receive Status Interrupt */
+
+/* Ethernet MAC interrupt mask register */
+
+#define ETH_MACIER_PHYIE             (1 << 3)  /* Bit 3: PHY interrupt mask */
+#define ETH_MACIER_PMTIE             (1 << 4)  /* Bit 4: PMT Interrupt Enable */
+#define ETH_MACIER_LPIIE             (1 << 5)  /* Bit 5: LPI Interrupt Enable */
+#define ETH_MACIER_TSIE              (1 << 12) /* Bit 12: Timestamp Interrupt Enable */
+#define ETH_MACIER_TXSTSIE           (1 << 13) /* Bit 13: Transmit Status Interrupt Enable */
+#define ETH_MACIER_RXSTSIE           (1 << 14) /* Bit 14: Receive Status Interrupt Enable */
+#define ETH_MACIER_ALLINTS           (ETH_MACIER_PHYIE | ETH_MACIER_PMTIE | ETH_MACIER_LPIIE |\
+                                      ETH_MACIER_TSIE | ETH_MACIER_TXSTSIE | ETH_MACIER_RXSTSIE)
+
+/* Ethernet MAC MDIO address register */
+
+#define ETH_MACMDIOAR_MB              (1 << 0)  /* Bit 0: MII busy */
+#define ETH_MACMDIOAR_C45E            (1 << 1)  /* Bit 1: Clause 45 PHY Enable */
+#define ETH_MACMDIOAR_GOC_SHIFT       (2)       /* Bits 2-3: MII Operation Command */
+#  define ETH_MACMDIOAR_GOC_WRITE     (1 << ETH_MACMDIOAR_GOC_SHIFT) /* Write */
+#  define ETH_MACMDIOAR_GOC_PRIA      (2 << ETH_MACMDIOAR_GOC_SHIFT) /* Post Read Increment Address for Clause 45 PHY */
+#  define ETH_MACMDIOAR_GOC_READ      (3 << ETH_MACMDIOAR_GOC_SHIFT) /* Read */
+#define ETH_MACMDIOAR_SKAP            (1 << 4)  /* Bit 4: Skip Address Packet */
+#define ETH_MACMDIOAR_CR_SHIFT        (8)       /* Bits 8-11: Clock range */
+#define ETH_MACMDIOAR_CR_MASK         (7 << ETH_MACMDIOAR_CR_SHIFT)
+#  define ETH_MACMDIOAR_CR_DIV42      (0 << ETH_MACMDIOAR_CR_SHIFT) /* 60-100  MHz HCLK/42 */
+#  define ETH_MACMDIOAR_CR_DIV62      (1 << ETH_MACMDIOAR_CR_SHIFT) /* 100-150 MHz HCLK/62 */
+#  define ETH_MACMDIOAR_CR_DIV16      (2 << ETH_MACMDIOAR_CR_SHIFT) /* 20-35   MHz HCLK/16 */
+#  define ETH_MACMDIOAR_CR_DIV26      (3 << ETH_MACMDIOAR_CR_SHIFT) /* 35-60   MHz HCLK/26 */
+#  define ETH_MACMDIOAR_CR_DIV102     (4 << ETH_MACMDIOAR_CR_SHIFT) /* 150-250 MHz HCLK/102 */
+#  define ETH_MACMDIOAR_CR_DIV124     (5 << ETH_MACMDIOAR_CR_SHIFT) /* 250-300 MHz HCLK/124 */
+#define ETH_MACMDIOAR_NTC_SHIFT       (12) /* Number of Training Clocks */
+#define ETH_MACMDIOAR_NTC_MASK        (7 << ETH_MACMDIOAR_NTC_SHIFT)
+#  define ETH_MACMDIOAR_NTC(n)        ((uint32_t)(n) << ETH_MACMDIOAR_NTC_SHIFT)
+#define ETH_MACMDIOAR_RDA_SHIFT       (16)       /* Bits 16-20: MII register */
+#define ETH_MACMDIOAR_RDA_MASK        (31 << ETH_MACMDIOAR_RDA_SHIFT)
+#  define ETH_MACMDIOAR_RDA(n)        ((uint32_t)(n) << ETH_MACMDIOAR_RDA_SHIFT)
+#define ETH_MACMDIOAR_PA_SHIFT        (11)      /* Bits 11-15: PHY address */
+#define ETH_MACMDIOAR_PA_MASK         (31 << ETH_MACMDIOAR_PA_SHIFT)
+#  define ETH_MACMDIOAR_PA(n)         ((uint32_t)(n) << ETH_MACMDIOAR_PA_SHIFT)
+#define ETH_MACMDIOAR_BTB             (1 << 26)  /* Bit 26: Back to Back transactions */
+#define ETH_MACMDIOAR_PSE             (1 << 27)  /* Bit 27: Preamble Suppression Enable */
+
+#define STM32_ETH_MACAxHR_MBC_SHIFT   (24) /* Bits 24-29: Mask Byte Control */
+#define STM32_ETH_MACAxHR_MBC_MASK    (0x3f << STM32_ETH_MACA0HR_MBC_SHIFT)
+#define STM32_ETH_MACAxHR_SA          (1 << 30) /* Bit 30: Source Address */
+#define STM32_ETH_MACAxHR_AE          (1 << 31) /* Bit 31: Address Enable */
+
+/* Ethernet MTL registers */
+
+#define ETH_MTLOMR_DTXSTS             (1 << 0)   /* Bit 0: Drop Transmit Status */
+#define ETH_MTLOMR_CNTPRST            (1 << 8)   /* Bit 8: Counters Preset */
+#define ETH_MTLOMR_CNTCLR             (1 << 9)   /* Bit 9: Counters Reset */
+
+#define ETH_MTLISR_Q0IS               (1 << 0)   /* Bit 0: Queue interrupt status */
+
+#define ETH_MTLTXQOMR_FTQ             (1 << 0)   /* Bit 0: Flush Transmit Queue */
+#define ETH_MTLTXQOMR_TSF             (1 << 1)   /* Bit 1: Transmit Store and Forward */
+#define ETH_MTLTXQOMR_TXQEN_SHIFT     (2)        /* Bits 2-3: Transmit Queue Enable */
+#define ETH_MTLTXQOMR_TXQEN_MASK      (0x3 << ETH_MTLTXQOMR_TXQEN_SHIFT)
+#define ETH_MTLTXQOMR_TXQEN_DISABLED  (0)
+#define ETH_MTLTXQOMR_TXQEN_ENABLED   (2)
+
+#define ETH_MTLTXQOMR_TTC_SHIFT       (4)        /* Bits 4-6: Transmit Threshold Control */
+#define ETH_MTLTXQOMR_TTC_MASK        (0x7 << ETH_MTLTXQOMR_TTC_SHIFT)
+#  define ETH_MTLTXQOMR_TTC_32        (0x0 << ETH_MTLTXQOMR_TTC_SHIFT)
+#  define ETH_MTLTXQOMR_TTC_64        (0x1 << ETH_MTLTXQOMR_TTC_SHIFT)
+#  define ETH_MTLTXQOMR_TTC_96        (0x2 << ETH_MTLTXQOMR_TTC_SHIFT)
+#  define ETH_MTLTXQOMR_TTC_128       (0x3 << ETH_MTLTXQOMR_TTC_SHIFT)
+#  define ETH_MTLTXQOMR_TTC_192       (0x4 << ETH_MTLTXQOMR_TTC_SHIFT)
+#  define ETH_MTLTXQOMR_TTC_256       (0x5 << ETH_MTLTXQOMR_TTC_SHIFT)
+#  define ETH_MTLTXQOMR_TTC_364       (0x6 << ETH_MTLTXQOMR_TTC_SHIFT)
+#  define ETH_MTLTXQOMR_TTC_512       (0x7 << ETH_MTLTXQOMR_TTC_SHIFT)
+#define ETH_MTLTXQOMR_TQS_SHIFT       (16)       /* Bits 16-24: Transmit Queue Size */
+#define ETH_MTLTXQOMR_TQS_MASK        (0x1ff << ETH_MTLTXQOMR_TQS_SHIFT)
+
+#define ETH_MTLTXQUR_UFFRMCNT_SHIFT   (0)       /* Underflow Packet Counter */
+#define ETH_MTLTXQUR_UFFRMCNT_MASK    (0x7ff << ETH_MTLTXQUR_UFFRMCNT_SHIFT)
+#define ETH_MTLTXQUR_UFCNTOVF         (1 << 11)
+
+#define ETH_MTLTXQDR_TXQPAUSED        (1 << 0)  /* Transmit Queue in Pause */
+#define ETH_MTLTXQDR_TRCSTS_SHIFT     (1)       /* MTL Tx Queue Read Controller Status */
+#define ETH_MTLTXQDR_TRCSTS_MASK      (0x3 << ETH_MTLTXQDR_TRCSTS_SHIFT)
+#define ETH_MTLTXQDR_TWCSTS           (1 << 3)  /* Bit 3: MTL Tx Queue Write Controller Status */
+#define ETH_MTLTXQDR_TXQSTS           (1 << 4)  /* Bit 4: MTL Tx Queue Not Empty Status */
+#define ETH_MTLTXQDR_TXSTSFSTS        (1 << 5)  /* Bit 5: MTL Tx Status FIFO Full Status */
+#define ETH_MTLTXQDR_PTXQ_SHIFT       (16)      /* Bits 16-18: Number of Packets in the Transmit Queue */
+#define ETH_MTLTXQDR_PTXQ_MASK        (0x7 << ETH_MTLTXQDR_PTXQ_SHIFT)
+#define ETH_MTLTXQDR_STXSTSF_SHIFT    (20)      /* Bits 20-22: Number of Status Words in Tx Status FIFO of Queue */
+#define ETH_MTLTXQDR_STXSTSF_MASK     (0x7 << ETH_MTLTXQDR_STXSTSF_SHIFT)
+
+#define ETH_MTLQICSR_TXUNFIS    (1 << 0)  /* Bit 0: Transmit Queue Underflow Interrupt Status */
+#define ETH_MTLQICSR_TXUIE      (1 << 8)  /* Bit 8: Transmit Queue Underflow Interrupt Enable */
+#define ETH_MTLQICSR_RXOVFIS    (1 << 16) /* Bit 16: Receive Queue Overflow Interrupt Status */
+#define ETH_MTLQICSR_RXOIE      (1 << 24) /* Bit 24: Receive Queue Overflow Interrupt Enable */
+
+#define ETH_MTLRXQOMR_RTC_SHIFT  (0)      /* Bits 0-1: Receive Queue Threshold Control */
+#define ETH_MTLRXQOMR_RTC_MASK   (0x3 << ETH_MTLRXQOMR_RTC_SHIFT)
+#  define ETH_MTLRXQOMR_RTC_64   (0x0 << ETH_MTLRXQOMR_RTC_SHIFT)
+#  define ETH_MTLRXQOMR_RTC_32   (0x1 << ETH_MTLRXQOMR_RTC_SHIFT)
+#  define ETH_MTLRXQOMR_RTC_96   (0x2 << ETH_MTLRXQOMR_RTC_SHIFT)
+#  define ETH_MTLRXQOMR_RTC_128  (0x3 << ETH_MTLRXQOMR_RTC_SHIFT)
+#define ETH_MTLRXQOMR_FUP        (1 << 3) /* Bit 3: Forward Undersized Good Packets */
+#define ETH_MTLRXQOMR_FEP        (1 << 4) /* Bit 4: Forward Error Packets */
+#define ETH_MTLRXQOMR_RSF        (1 << 5) /* Bit 5: Receive Queue Store and Forward */
+#define ETH_MTLRXQOMR_DIS_TCP_EF (1 << 6) /* Bit 6: Disable Dropping of TCP/IP Checksum Error Packets */
+#define ETH_MTLRXQOMR_EHFC       (1 << 7) /* Bit 7: Enable Hardware Flow Control */
+#define ETH_MTLRXQOMR_RFA_SHIFT  (8)      /* Bits 8-10: Threshold for Activating Flow Control */
+#define ETH_MTLRXQOMR_RFA_MASK   (0x7 << ETH_MTLRXQOMR_RFA_SHIFT)
+#define ETH_MTLRXQOMR_RFD_SHIFT  (14)     /* Bits 14-16: Threshold for Deactivating Flow Control */
+#define ETH_MTLRXQOMR_RFD_MASK   (0x7 << ETH_MTLRXQOMR_RFD_SHIFT)
+#define ETH_MTLRXQOMR_RQS_SHIFT  (20)     /* Bits 20-22: Receive Queue Size */
+#define ETH_MTLRXQOMR_RQS_MASK   (0x7 << ETH_MTLRXQOMR_RQS_SHIFT)
+
+#define ETH_MTLRXQMPOCR_OVFPKTCNT_SHIFT (0)       /* Bits 0-10: Overflow Packet Counter */
+#define ETH_MTLRXQMPOCR_OVFPKTCNT_MASK  (0x7ff << ETH_MTLRXQMPOCR_OVFPKTCNT_SHIFT)
+#define ETH_MTLRXQMPOCR_OVFCNTOVF       (1 << 11) /* Bit 11: Overflow Counter Overflow Bit */
+#define ETH_MTLRXQMPOCR_MISPKTCNT_SHIFT (16)      /* Bits 16-26: Missed Packet Counter */
+#define ETH_MTLRXQMPOCR_MISPKTCNT_MASK  (0x7ff << ETH_MTLRXQMPOCR_MISPKTCNT_SHIFT)
+#define ETH_MTLRXQMPOCR_MISCNTOVF       (1 << 27) /* Bit 27: Missed Packet Counter Overflow Bit */
+
+#define ETH_MTLRXQDR_RWCSTS         (1 << 0) /* Bit 0: MTL Rx Queue Write Controller Active Status */
+#define ETH_MTLRXQDR_RRCSTS_SHIFT   (1)      /* Bits 1-2: MTL Rx Queue Read Controller State */
+#define ETH_MTLRXQDR_RRCSTS_MASK    (0x3 << ETH_MTLRXQDR_RRCSTS_SHIFT)
+#define ETH_MTLRXQDR_RXQSTS_SHIFT   (4)      /* Bits 4-5: MTL Rx Queue Fill-Level Status */
+#define ETH_MTLRXQDR_RXQSTS_MASK    (0x3 << ETH_MTLRXQDR_RXQSTS_SHIFT)
+#define ETH_MTLRXQDR_PRXQ_SHIFT     (16)     /* Bits 16-29: Number of Packets in Receive Queue */
+#define ETH_MTLRXQDR_PRXQ_MASK      (0x3fff << ETH_MTLRXQDR_PRXQ_SHIFT)
+
+/* Ethernet MAC MDIO data register */
+
+/* Ethernet DMA registers ***************************************************************************/
+
+#define ETH_DMAMR_SWR          (1 << 0)  /* Bit 0: Software Reset */
+#define ETH_DMAMR_DA           (1 << 1)  /* Bit 1: DMA Tx or Rx Arbitration Scheme */
+#define ETH_DMAMR_TXPR         (1 << 11) /* Bit 11: Transmit priority */
+#define ETH_DMAMR_PR_SHIFT     (12)      /* Bits 12-14: Priority ratio */
+#define ETH_DMAMR_PR_MASK      (0x7 << ETH_DMAMR_PR_SHIFT)
+#  define ETH_DMAMR_PR_1TO1    (0x0 << ETH_DMAMR_PR_SHIFT)
+#  define ETH_DMAMR_PR_2TO1    (0x1 << ETH_DMAMR_PR_SHIFT)
+#  define ETH_DMAMR_PR_3TO1    (0x2 << ETH_DMAMR_PR_SHIFT)
+#  define ETH_DMAMR_PR_4TO1    (0x3 << ETH_DMAMR_PR_SHIFT)
+#  define ETH_DMAMR_PR_5TO1    (0x4 << ETH_DMAMR_PR_SHIFT)
+#  define ETH_DMAMR_PR_6TO1    (0x5 << ETH_DMAMR_PR_SHIFT)
+#  define ETH_DMAMR_PR_7TO1    (0x6 << ETH_DMAMR_PR_SHIFT)
+#  define ETH_DMAMR_PR_8TO1    (0x7 << ETH_DMAMR_PR_SHIFT)
+
+#define ETH_DMAMR_INTM_SHIFT   (16)    /* Bits 16-17: Interrupt Mode */
+#define ETH_DMAMR_INTM_MASK    (0x3 << ETH_DMAMR_INTM_SHIFT)
+
+#define STM32_ETH_DMASBMR_FB   (1 << 0)  /* Bit 0: Fixed Burst Length */
+#define STM32_ETH_DMASBMR_AAL  (1 << 12) /* Bit 12: Address-Aligned Beats */
+#define STM32_ETH_DMASBMR_MB   (1 << 14) /* Bit 14: Mixed Burst */
+#define STM32_ETH_DMASBMR_RB   (1 << 15) /* Bit 15: Rebuild INCRx Burst */
+
+#define ETH_DMACIER_TIE              (1 << 0)  /* Bit 0:  Transmit interrupt enable */
+#define ETH_DMACIER_TXSE             (1 << 1)  /* Bit 1:  Transmit process stopped interrupt enable */
+#define ETH_DMACIER_TBUE             (1 << 2)  /* Bit 2:  Transmit buffer unavailable interrupt enable */
+
+#define ETH_DMACIER_RIE              (1 << 6)  /* Bit 6:  Receive interrupt enable */
+#define ETH_DMACIER_RBUE             (1 << 7)  /* Bit 7:  Receive buffer unavailable interrupt enable */
+#define ETH_DMACIER_RSE              (1 << 8)  /* Bit 8:  Receive process stopped interrupt enable */
+#define ETH_DMACIER_RWTE             (1 << 9)  /* Bit 9:  Receive watchdog timeout interrupt enable */
+#define ETH_DMACIER_ETIE             (1 << 10) /* Bit 10: Early transmit interrupt enable */
+#define ETH_DMACIER_ERIE             (1 << 11) /* Bit 11: Early receive interrupt enable*/
+#define ETH_DMACIER_FBEE             (1 << 12) /* Bit 12: Fatal bus error interrupt enable*/
+#define ETH_DMACIER_CDEE             (1 << 13) /* Bit 13: Context descriptor error interrupt enable */
+#define ETH_DMACIER_AIE              (1 << 14) /* Bit 14: Abnormal interrupt summary interrupt enable */
+#define ETH_DMACIER_NIE              (1 << 15) /* Bit 15: Normal interrupt summary enable */
+
+#define ETH_DMACSR_TI                (1 << 0)  /* Bit 0:  Transmit interrupt */
+#define ETH_DMACSR_TPS               (1 << 1)  /* Bit 1:  Transmit process stopped interrupt */
+#define ETH_DMACSR_TBU               (1 << 2)  /* Bit 2:  Transmit buffer unavailable interrupt */
+
+#define ETH_DMACSR_RI                (1 << 6)  /* Bit 6:  Receive interrupt */
+#define ETH_DMACSR_RBU               (1 << 7)  /* Bit 7:  Receive buffer unavailable interrupt */
+#define ETH_DMACSR_RPS               (1 << 8)  /* Bit 8:  Receive process stopped interrupt */
+#define ETH_DMACSR_RWT               (1 << 9)  /* Bit 9:  Receive watchdog timeout interrupt */
+#define ETH_DMACSR_ETI               (1 << 10) /* Bit 10: Early transmit interrupt */
+#define ETH_DMACSR_ERI               (1 << 11) /* Bit 11: Early receive interrupt */
+#define ETH_DMACSR_FBE               (1 << 12) /* Bit 12: Fatal bus error interrupt */
+#define ETH_DMACSR_CDE               (1 << 13) /* Bit 13: Context descriptor error interrupt */
+#define ETH_DMACSR_AIS               (1 << 14) /* Bit 14: Abnormal interrupt summary interrupt */
+#define ETH_DMACSR_NIS               (1 << 15) /* Bit 15: Normal interrupt summary */
+#define ETH_DMACSR_TEB_SHIFT         (16)      /* Bits 16-18: Tx DMA error bits */
+#define ETH_DMACSR_TEB_MASK          (0x7 << ETH_DMACSR_TEB_SHIFT)
+#define ETH_DMACSR_REB_SHIFT         (19)      /* Bits 19-21: Rx DMA error bits */
+#define ETH_DMACSR_REB_MASK          (0x7 << ETH_DMACSR_REB_SHIFT)
+
+#define ETH_DMACTXDTPR_TDT_SHIFT      (2) /* Transmit Descriptor Tail Pointer */
+#define ETH_DMACTXDTPR_TDT_MASK       (0x3fffffff << ETH_DMACTXDTPR_TDT_SHIFT)
+
+#define ETH_DMACCR_MSS_SHIFT        (0)       /* Bits 0-13: Maximum Segment Size */
+#define ETH_DMACCR_MSS_MASK         (0x3fff << ETH_DMACCR_MSS_SHIFT)
+#define ETH_DMACCR_PBLX8            (1 << 16) /* Bit 16: 8xPBL mode */
+#define ETH_DMACCR_DSL_SHIFT        (18)      /* Bits 18-20: Descriptor Skip Length */
+#define ETH_DMACCR_DSL_MASK         (0x7 << ETH_DMACCR_DSL_SHIFT)
+#define ETH_DMACCR_DSL(n)           ((n) << ETH_DMACCR_DSL_SHIFT)
+
+#define ETH_DMACTXCR_ST             (1 << 0)  /* Bit 0: Start or Stop Transmission Command */
+#define ETH_DMACTXCR_OSF            (1 << 4)  /* Bit 4: Operate on Second Packet */
+#define ETH_DMACTXCR_TSE            (1 << 12) /* Bit 12: TCP Segmentation Enabled */
+#define ETH_DMACTXCR_TXPBL_SHIFT    (16)      /* Bits 16-21: Transmit Programmable Burst Length */
+#define ETH_DMACTXCR_TXPBL_MASK     (0x3f << ETH_DMACTXCR_TXPBL_SHIFT)
+#define ETH_DMACTXCR_TXPBL(n)       ((n) << ETH_DMACTXCR_TXPBL_SHIFT)
+
+#define ETH_DMACRXCR_SR             (1 << 0)  /* Bit0: Start or Stop Receive */
+#define ETH_DMACRXCR_RBSZ_SHIFT     (1)       /* Bits 1-14: Receive Buffer size */
+#define ETH_DMACRXCR_RBSZ_MASK      (0x3fff << ETH_DMACRXCR_RBSZ_SHIFT)
+#define ETH_DMACRXCR_RBSZ(n)        ((n) << ETH_DMACRXCR_RBSZ_SHIFT)
+#define ETH_DMACRXCR_RXPBL_SHIFT    (16)      /* Bits 16-21: Receive Programmable Burst Length */
+#define ETH_DMACRXCR_RXPBL_MASK     (0x3f << ETH_DMACRXCR_RXPBL_SHIFT)
+#define ETH_DMACRXCR_RXPBL(n)        ((n) << ETH_DMACRXCR_RXPBL_SHIFT)
+#define ETH_DMACRXCR_RPF            (1 << 31) /* Bit 31: DMA Rx Channel Packet Flush */
+
+/* DMA Descriptors **********************************************************************************/
+
+/* TDES0: TDES0 normal descriptor, read-format (header or buf 1 address[31:0])
+ * TDES1: TDES1 normal descriptor, read-format (buf2 address[31:0] or buf1 address[63:32]
+ * TDES2: TDES2 normal descriptor, read-format
+ */
+
+#define ETH_TDES2_RD_HL_BL1_SHIFT    (0) /* Header Length or Buffer 1 Length */
+#define ETH_TDES2_RD_HL_BL1_MASK     (0x3fff << ETH_TDES2_RD_HL_BL1_SHIFT)
+#define ETH_TDES2_RD_VTIR_SHIFT      (14) /* VLAN Tag Insertion or Replacement */
+#define ETH_TDES2_RD_VTIR_MASK       (0x3 << ETH_TDES2_RD_VTIR_SHIFT)
+#define ETH_TDES2_RD_B2L_SHIFT       (16) /* Buffer 2 Length */
+#define ETH_TDES2_RD_B2L_MASK        (0x3fff << ETH_TDES2_RD_B2L_SHIFT)
+#define ETH_TDES2_RD_TTSE            (1 << 30)  /* Bit 30: Transmit Timestamp Enable */
+#define ETH_TDES2_RD_IOC             (1 << 31)  /* Bit 31: Interrupt on Completion */
+
+/* TDES3: TDES3 normal descriptor, read-format */
+
+#define ETH_TDES3_RD_FL_TPL_SHIFT    (0) /* Packet Length or TCP Payload Length */
+#define ETH_TDES3_RD_FL_TPL_MASK     (0x7fff << ETH_TDES3_RD_FL_TPL_SHIFT)
+#define ETH_TDES3_RD_TPL             (1 << 15) /* Bit 15: Reserved or TCP Payload Length */
+#define ETH_TDES3_RD_CIC_TPL_SHIFT   (16) /* Checksum Insertion Control or TCP Payload Length */
+#define ETH_TDES3_RD_CIC_TPL_MASK    (0x3 << ETH_TDES3_RD_CIC_TPL_SHIFT)
+#define ETH_TDES3_RD_TSE             (1 << 18) /* Bit 18: TCP Segmentation Enable */
+#define ETH_TDES3_RD_THL_SHIFT       (19) /* TCP Header Length */
+#define ETH_TDES3_RD_THL_MASK        (0xf << ETH_TDES3_RD_THL_SHIFT)
+#define ETH_TDES3_RD_SAIC_SHIFT      (23) /* SA Insertion Control */
+#define ETH_TDES3_RD_SAIC_MASK       (0x7 << ETH_TDES3_RD_SAIC_SHIFT)
+#define ETH_TDES3_RD_CPC_SHIFT       (26) /* CRC Pad Control */
+#define ETH_TDES3_RD_CPC_MASK        (0x3 << ETH_TDES3_RD_CPC_SHIFT)
+#define ETH_TDES3_RD_LD              (1 << 28) /* Bit 28: Last Descriptor */
+#define ETH_TDES3_RD_FD              (1 << 29) /* Bit 29: First Descriptor */
+#define ETH_TDES3_RD_CTXT            (1 << 30) /* Bit 30: Context Type  */
+#define ETH_TDES3_RD_OWN             (1 << 31) /* Bit 31: Own bit */
+
+/* TDES0: TDES0 normal descriptor, write-back format (time stamp low)
+ * TDES1: TDES1 normal descriptor, write-back format (time stamp high)
+ * TDES2: TDES2 normal descriptor, write-back format (reserved)
+ * TDES3: TDES3 normal descriptor, write-back format
+ */
+
+#define ETH_TDES3_WB_IHE             (1 << 0)  /* Bit 0:  IP Header Error */
+#define ETH_TDES3_WB_DB              (1 << 1)  /* Bit 1:  Deferred bit */
+#define ETH_TDES3_WB_UF              (1 << 2)  /* Bit 1:  Underflow error */
+#define ETH_TDES3_WB_ED              (1 << 3)  /* Bit 2:  Excessive deferral */
+#define ETH_TDES3_WB_CC_SHIFT        (4)       /* Bits 4-7: Collision count */
+#define ETH_TDES3_WB_CC_MASK         (15 << ETH_TDES3_CC_WB_SHIFT)
+#define ETH_TDES3_WB_EC              (1 << 8)  /* Bit 8:  Excessive collision */
+#define ETH_TDES3_WB_LC              (1 << 9)  /* Bit 9:  Late collision */
+#define ETH_TDES3_WB_NC              (1 << 10) /* Bit 10: No carrier */
+#define ETH_TDES3_WB_LOC             (1 << 11) /* Bit 11: Loss of carrier */
+#define ETH_TDES3_WB_PCE             (1 << 12) /* Bit 12: Payload checksum error */
+#define ETH_TDES3_WB_FF              (1 << 13) /* Bit 13: Packet flushed */
+#define ETH_TDES3_WB_JT              (1 << 14) /* Bit 14: Jabber timeout */
+#define ETH_TDES3_WB_ES              (1 << 15) /* Bit 15: Error summary */
+#define ETH_TDES3_WB_TTSS            (1 << 17) /* Bit 17: Transmit time stamp status */
+#define ETH_TDES3_WB_LD              (1 << 28) /* Bit 28: Last Descriptor */
+#define ETH_TDES3_WB_FD              (1 << 29) /* Bit 29: First Descriptor */
+#define ETH_TDES3_WB_CTXT            (1 << 30) /* Bit 30: Context Type  */
+#define ETH_TDES0_WB_OWN             (1 << 31) /* Bit 31: Own bit */
+
+/* TDES0: TDES0 context descriptor (time stamp low)
+ * TDES1: TDES1 context descriptor (time stamp high)
+ * TDES2: TDES2 context descriptor
+ */
+
+#define ETH_CTX_TDES2_MSS_SHIFT      (0) /* Maximum Segment Size */
+#define ETH_CTX_TDES2_MSS_MASK       (0x3fff << ETH_CTX_TDES2_MSS_SHIFT)
+#define ETH_CTX_TDES2_IVT_SHIFT      (16) /* Inner VLAN Tag */
+#define ETH_CTX_TDES2_IVT_MASK       (0xffff << ETH_CTX_TDES2_IVT_SHIFT)
+
+/* TDES3: TDES3 context descriptor */
+
+#define ETH_CTX_TDES3_VT_SHIFT      (0) /* VLAN Tag */
+#define ETH_CTX_TDES3_VT_MASK       (0xffff << ETH_CTX_TDES3_VT_SHIFT)
+#define ETH_CTX_TDES3_VLTV          (1 << 16) /* Bit 16: VLAN Tag Valid */
+#define ETH_CTX_TDES3_IVLTV         (1 << 17) /* Bit 17: Inner VLAN Tag Valid */
+#define ETH_CTX_TDES3_IVTIR_SHIFT   (18) /* Inner VLAN Tag Insert or Replace */
+#define ETH_CTX_TDES3_IVTIR_MASK    (0x3 << ETH_CTX_TDES3_IVTIR_SHIFT)
+#define ETH_CTX_TDES3_CDE           (1 << 23) /* Bit 23: Context Descriptor Error */
+#define ETH_CTX_TDES3_TCMSSV        (1 << 26) /* Bit 26: One-Step Timestamp Correction Input or MSS Valid */
+#define ETH_CTX_TDES3_OSTC          (1 << 27) /* Bit 27: One-Step Timestamp Correction Enable */
+#define ETH_CTX_TDES3_CTXT          (1 << 30) /* Bit 30: Context Type */
+#define ETH_CTX_TDES3_OWN           (1 << 31) /* Bit 31: Own bit */
+
+/* RDES0: Receive descriptor Word0, read-format (Buffer 1 address[31:0])
+ * RDES1: Receive descriptor Word1, read-format (Reserved or Header/Buffer 1 Address[63:32] address)
+ * RDES2: Receive descriptor Word2, read-format (Payload or Buffer 2 Address[31:0])
+ * RDES3: Receive descriptor Word3, read-format
+ */
+
+#define ETH_RDES3_RD_BUF1V          (1 << 24) /* Bit 24: Buffer 1 Address Valid */
+#define ETH_RDES3_RD_BUF2V          (1 << 25) /* Bit 25: Buffer 2 Address Valid */
+#define ETH_RDES3_RD_IOC            (1 << 30) /* Bit 30: Interrupt Enabled on Completion */
+#define ETH_RDES3_RD_OWN            (1 << 31) /* Bit 31: Own bit */
+
+/* RDES0: Receive descriptor Word0, write-back format */
+
+#define ETH_RDES0_WB_OVT_SHIFT      (0)       /* Bits 0-15: Outer VLAN Tag */
+#define ETH_RDES0_WB_OVT_MASK       (0xffff << ETH_RDES0_WB_OVT_SHIFT)
+#define ETH_RDES0_WB_IVT_SHIFT      (16)      /* Bits 16-31: Inner VLAN Tag */
+#define ETH_RDES0_WB_IVT_MASK       (0xffff << ETH_RDES0_WB_IVT_SHIFT)
+
+/* RDES1: Receive descriptor Word1, write-back format */
+
+#define ETH_RDES1_WB_PT_SHIFT       (0)       /* Bits 0-2: Payload Type */
+#define ETH_RDES1_WB_PT_MASK        (0x7 << ETH_RDES1_WB_PT_SHIFT)
+#  define ETH_RDES1_WB_PT_UNKNOWN   (0x0)
+#  define ETH_RDES1_WB_PT_UDP       (0x1)
+#  define ETH_RDES1_WB_PT_TCP       (0x2)
+#  define ETH_RDES1_WB_PT_ICMP      (0x3)
+#define ETH_RDES1_WB_IPHE           (1 << 3)  /* Bit 3: IP Header Error */
+#define ETH_RDES1_WB_IPV4           (1 << 4)  /* Bit 4: IPv4 Header Present */
+#define ETH_RDES1_WB_IPV6           (1 << 5)  /* Bit 5: IPv6 Header Present */
+#define ETH_RDES1_WB_IPCB           (1 << 6)  /* Bit 6: IP Checksum Bypassed */
+#define ETH_RDES1_WB_IPCE           (1 << 7)  /* Bit 7: IP Payload Error */
+#define ETH_RDES1_WB_PMT_SHIFT      (8)       /* Bits 8-11: PTP Message Type */
+#define ETH_RDES1_WB_PMT_MASK       (0xf << ETH_RDES1_WB_PMT_SHIFT)
+#define ETH_RDES1_WB_PFT            (1 << 12) /* Bit 12: PTP Packet Type */
+#define ETH_RDES1_WB_PV             (1 << 13) /* Bit 13: PTP Version */
+#define ETH_RDES1_WB_TSA            (1 << 14) /* Bit 14: Timestamp Available */
+#define ETH_RDES1_WB_TD             (1 << 15) /* Bit 15: Timestamp Dropped */
+#define ETH_RDES1_WB_OPC_SHIFT      (16)      /* Bits 16-31: OAM Sub-Type Code, or MAC Control Packet opcode */
+#define ETH_RDES1_WB_OPC_MASK       (0xffff << ETH_RDES1_WB_OPC_SHIFT)
+
+/* RDES2: Receive descriptor Word2, write-back format */
+
+#define ETH_RDES2_WB_ARPNR          (1 << 10) /* Bit 10: ARP Reply Not Generated */
+#define ETH_RDES2_WB_VF             (1 << 15) /* Bit 15: VLAN Filter Status */
+#define ETH_RDES2_WB_SAF            (1 << 16) /* Bit 16: SA Address Filter Fail */
+#define ETH_RDES2_WB_DAF            (1 << 17) /* Bit 17: Destination Address Filter Fail */
+#define ETH_RDES2_WB_HF             (1 << 18) /* Bit 18: Hash Filter Status */
+#define ETH_RDES2_WB_MADRM_SHIFT    (19)      /* Bits 19-26: MAC Address Match or Hash Value */
+#define ETH_RDES2_WB_MADRM_MASK     (0xff << ETH_RDES1_WB_MADRM_SHIFT)
+#define ETH_RDES2_WB_L3FM           (1 << 27) /* Bit 27: Layer 3 Filter Match */
+#define ETH_RDES2_WB_L4FM           (1 << 28) /* Bit 28: Layer 4 Filter Match */
+#define ETH_RDES2_WB_L3L4FM_SHIFT   (29)      /* Bits 29-31: Layer 3 and Layer 4 Filter Number Matched */
+#define ETH_RDES2_WB_L3L4FM_MASK    (0x7 << ETH_RDES1_WB_L3L4FM_SHIFT)
+
+/* RDES3: Receive descriptor Word3, write-back format */
+
+#define ETH_RDES3_WB_PL_SHIFT       (0)      /* Bits 0-14: Packet Length */
+#define ETH_RDES3_WB_PL_MASK        (0x7fff << ETH_RDES3_WB_PL_SHIFT)
+#define ETH_RDES3_WB_ES             (1 << 15) /* Bit 15: Error Summary */
+#define ETH_RDES3_WB_LT_SHIFT       (16)      /* Bits 16-18: Length/Type Field */
+#define ETH_RDES3_WB_LT_MASK        (0x7 << ETH_RDES3_WB_LT_SHIFT)
+#define ETH_RDES3_WB_DE             (1 << 19) /* Bit 19: Dribble Bit Error */
+#define ETH_RDES3_WB_RE             (1 << 20) /* Bit 20: Receive Error */
+#define ETH_RDES3_WB_OE             (1 << 21) /* Bit 21: Overflow Error */
+#define ETH_RDES3_WB_RWT            (1 << 22) /* Bit 22: Receive Watchdog Timeout */
+#define ETH_RDES3_WB_GP             (1 << 23) /* Bit 23: Giant Packet */
+#define ETH_RDES3_WB_CE             (1 << 24) /* Bit 24: CRC Error */
+#define ETH_RDES3_WB_RS0V           (1 << 25) /* Bit 25: Receive Status RDES0 Valid */
+#define ETH_RDES3_WB_RS1V           (1 << 26) /* Bit 26: Receive Status RDES1 Valid */
+#define ETH_RDES3_WB_RS2V           (1 << 27) /* Bit 27: Receive Status RDES2 Valid */
+#define ETH_RDES3_WB_LD             (1 << 28) /* Bit 28: Last Descriptor */
+#define ETH_RDES3_WB_FD             (1 << 29) /* Bit 29: First Descriptor */
+#define ETH_RDES3_WB_CTXT           (1 << 30) /* Bit 30: Context Type  */
+#define ETH_RDES3_WB_OWN            (1 << 31) /* Bit 31: Own bit */
+
+/* RDES0: RDES0 context descriptor (time stamp low)
+ * RDES1: RDES1 context descriptor (time stamp high)
+ * RDES2: RDES2 context descriptor (reserved)
+ * RDES3: RDES3 context descriptor
+ */
+
+#define ETH_CTX_RDES3_CTXT          (1 << 30) /* Bit 30: Context Type  */
+#define ETH_CTX_RDES3_OWN           (1 << 31) /* Bit 31: Own bit */
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Ethernet RX/TX DMA Descriptor */
+
+struct eth_desc_s
+{
+  /* DMA descriptor words */
+
+  volatile uint32_t des0;
+  volatile uint32_t des1;
+  volatile uint32_t des2;
+  volatile uint32_t des3;
+};
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_STM32H7_STM32H7X3XX */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_ETHERNET_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32_exti.h b/arch/arm/src/stm32h7/hardware/stm32_exti.h
similarity index 98%
rename from arch/arm/src/stm32h7/chip/stm32_exti.h
rename to arch/arm/src/stm32h7/hardware/stm32_exti.h
index 716572fd5fc..e115c2b63dd 100644
--- a/arch/arm/src/stm32h7/chip/stm32_exti.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_exti.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_exti.h
+ * arch/arm/src/stm32h7/hardware/stm32_exti.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_EXTI_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_EXTI_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_EXTI_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_EXTI_H
 
 /************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 #include "chip.h"
-#include "chip/stm32_memorymap.h"
+#include "hardware/stm32_memorymap.h"
 
 /* Content of this file requires verification before it is used with other
  * families
@@ -246,4 +246,4 @@
 #define EXTI_EVENT_HSECSS           87  /* HSECSS interrupt */
 
 #endif /* CONFIG_STM32H7_STM32H7X3XX */
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_EXTI_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_EXTI_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32_flash.h b/arch/arm/src/stm32h7/hardware/stm32_flash.h
similarity index 89%
rename from arch/arm/src/stm32h7/chip/stm32_flash.h
rename to arch/arm/src/stm32h7/hardware/stm32_flash.h
index 131503038ff..d32488465a0 100644
--- a/arch/arm/src/stm32h7/chip/stm32_flash.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_flash.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_flash.h
+ * arch/arm/src/stm32h7/hardware/stm32_flash.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_FLASH_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_FLASH_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FLASH_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FLASH_H
 
 /************************************************************************************
  * Included Files
@@ -44,9 +44,9 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32H7_STM32H7X3XX)
-#  include "chip/stm32h7x3xx_flash.h"
+#  include "hardware/stm32h7x3xx_flash.h"
 #else
 #  error "Unsupported STM32 H7 part"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_FLASH_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FLASH_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32_gpio.h b/arch/arm/src/stm32h7/hardware/stm32_gpio.h
similarity index 89%
rename from arch/arm/src/stm32h7/chip/stm32_gpio.h
rename to arch/arm/src/stm32h7/hardware/stm32_gpio.h
index 12d11946499..e9aec1d858d 100644
--- a/arch/arm/src/stm32h7/chip/stm32_gpio.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_gpio.h
+ * arch/arm/src/stm32h7/hardware/stm32_gpio.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_GPIO_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_GPIO_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_GPIO_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -44,9 +44,9 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32H7_STM32H7X3XX)
-#  include "chip/stm32h7x3xx_gpio.h"
+#  include "hardware/stm32h7x3xx_gpio.h"
 #else
 #  error "Unsupported STM32 H7 part"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_GPIO_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_GPIO_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32_i2c.h b/arch/arm/src/stm32h7/hardware/stm32_i2c.h
similarity index 90%
rename from arch/arm/src/stm32h7/chip/stm32_i2c.h
rename to arch/arm/src/stm32h7/hardware/stm32_i2c.h
index 2e9428e5f33..f2681236f57 100644
--- a/arch/arm/src/stm32h7/chip/stm32_i2c.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_i2c.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_i2c.h
+ * arch/arm/src/stm32h7/hardware/stm32_i2c.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_I2C_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_I2C_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_I2C_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_I2C_H
 
 /************************************************************************************
  * Included Files
@@ -46,9 +46,9 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32H7_STM32H7X3XX)
-#  include "chip/stm32h7x3xx_i2c.h"
+#  include "hardware/stm32h7x3xx_i2c.h"
 #else
 #  error "Unsupported STM32 H7 sub family"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_I2C_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_I2C_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32_mdma.h b/arch/arm/src/stm32h7/hardware/stm32_mdma.h
similarity index 99%
rename from arch/arm/src/stm32h7/chip/stm32_mdma.h
rename to arch/arm/src/stm32h7/hardware/stm32_mdma.h
index 49e63d79c3f..2c3d86934d5 100644
--- a/arch/arm/src/stm32h7/chip/stm32_mdma.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_mdma.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_mdma.h
+ * arch/arm/src/stm32h7/hardware/stm32_mdma.h
  *
  *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_MDMA_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_MDMA_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_MDMA_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_MDMA_H
 
 /************************************************************************************
  * Included Files
@@ -644,4 +644,4 @@
 #define MDMA_TSEL_SBUS            (16) /* Bit 16: Source BUS select */
 #define MDMA_TSEL_DBUS            (17) /* Bit 16: Destination BUS select */
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_MDMA_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_MDMA_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32_memorymap.h b/arch/arm/src/stm32h7/hardware/stm32_memorymap.h
similarity index 88%
rename from arch/arm/src/stm32h7/chip/stm32_memorymap.h
rename to arch/arm/src/stm32h7/hardware/stm32_memorymap.h
index a9b42df39f4..1148a82591d 100644
--- a/arch/arm/src/stm32h7/chip/stm32_memorymap.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_memorymap.h
+ * arch/arm/src/stm32h7/hardware/stm32_memorymap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -45,9 +45,9 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32H7_STM32H7X3XX)
-#  include "chip/stm32h7x3xx_memorymap.h"
+#  include "hardware/stm32h7x3xx_memorymap.h"
 #else
 #  error "Unsupported STM32 H7 memory map"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32_otg.h b/arch/arm/src/stm32h7/hardware/stm32_otg.h
similarity index 99%
rename from arch/arm/src/stm32h7/chip/stm32_otg.h
rename to arch/arm/src/stm32h7/hardware/stm32_otg.h
index 9fb727138aa..d6b6fbfe185 100644
--- a/arch/arm/src/stm32h7/chip/stm32_otg.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_otg.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_otg.h
+ * arch/arm/src/stm32h7/hardware/stm32_otg.h
  * based on stm32f7/chip/stm32_otg.h
  *
  *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H
-#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_OTG_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_OTG_H
 
 /************************************************************************************
  * Included Files
@@ -929,4 +929,4 @@
 #define OTG_PCGCCTL_SUSP              (1 << 7)  /* Bit 7: PHY Suspended */
                                                 /* Bits 7-31: Reserved */
 
-#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_OTG_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32_pinmap.h b/arch/arm/src/stm32h7/hardware/stm32_pinmap.h
similarity index 89%
rename from arch/arm/src/stm32h7/chip/stm32_pinmap.h
rename to arch/arm/src/stm32h7/hardware/stm32_pinmap.h
index d4676dc5041..51c9aaeb57c 100644
--- a/arch/arm/src/stm32h7/chip/stm32_pinmap.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_pinmap.h
+ * arch/arm/src/stm32h7/hardware/stm32_pinmap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_PINMAP_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_PINMAP_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -44,10 +44,10 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32H7_STM32H7X3XX)
-#  include "chip/stm32h7x3xx_pinmap.h"
+#  include "hardware/stm32h7x3xx_pinmap.h"
 #else
 #  error "Unsupported STM32 H7 Pin map"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_PINMAP_H */
 
diff --git a/arch/arm/src/stm32h7/chip/stm32_pwr.h b/arch/arm/src/stm32h7/hardware/stm32_pwr.h
similarity index 89%
rename from arch/arm/src/stm32h7/chip/stm32_pwr.h
rename to arch/arm/src/stm32h7/hardware/stm32_pwr.h
index 64d7bbe07d4..39e7de5487e 100644
--- a/arch/arm/src/stm32h7/chip/stm32_pwr.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_pwr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_pwr.h
+ * arch/arm/src/stm32h7/hardware/stm32_pwr.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_PWR_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_PWR_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_PWR_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_PWR_H
 
 /************************************************************************************
  * Included Files
@@ -44,9 +44,9 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32H7_STM32H7X3XX)
-#  include "chip/stm32h7x3xx_pwr.h"
+#  include "hardware/stm32h7x3xx_pwr.h"
 #else
 #  error "Unsupported STM32 H7 part"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_PWR_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_PWR_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32_rcc.h b/arch/arm/src/stm32h7/hardware/stm32_rcc.h
similarity index 89%
rename from arch/arm/src/stm32h7/chip/stm32_rcc.h
rename to arch/arm/src/stm32h7/hardware/stm32_rcc.h
index a6bedbe8fc2..a9584396a25 100644
--- a/arch/arm/src/stm32h7/chip/stm32_rcc.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_rcc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_rcc.h
+ * arch/arm/src/stm32h7/hardware/stm32_rcc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_RCC_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_RCC_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_RCC_H
 
 /************************************************************************************
  * Included Files
@@ -45,9 +45,9 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32H7_STM32H7X3XX)
-#  include "chip/stm32h7x3xx_rcc.h"
+#  include "hardware/stm32h7x3xx_rcc.h"
 #else
 #  error "Unsupported STM32 H7 part"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_RCC_H */
diff --git a/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h b/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h
new file mode 100644
index 00000000000..752b226086a
--- /dev/null
+++ b/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h
@@ -0,0 +1,54 @@
+/************************************************************************************
+ * arch/arm/src/stm32h7/hardware/stm32_sdmmc.h
+ *
+ *   Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *            David Sidrane 
+ *            Jukka Laitinen 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_SDMMC_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_SDMMC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+#include "chip.h"
+
+#if defined(CONFIG_STM32H7_STM32H7X3XX)
+#  include "stm32h7x3xx_sdmmc.h"
+#else
+#  error "Unsupported STM32 H7 part"
+#endif
+
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_SDMMC_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32_spi.h b/arch/arm/src/stm32h7/hardware/stm32_spi.h
similarity index 89%
rename from arch/arm/src/stm32h7/chip/stm32_spi.h
rename to arch/arm/src/stm32h7/hardware/stm32_spi.h
index 8eab3d9167d..29f8ad73c7b 100644
--- a/arch/arm/src/stm32h7/chip/stm32_spi.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_spi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_spi.h
+ * arch/arm/src/stm32h7/hardware/stm32_spi.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_SPI_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_SPI_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_SPI_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_SPI_H
 
 /************************************************************************************
  * Included Files
@@ -44,9 +44,9 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32H7_STM32H7X3XX)
-#  include "chip/stm32h7x3xx_spi.h"
+#  include "hardware/stm32h7x3xx_spi.h"
 #else
 #  error "Unsupported STM32 H7 sub family"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_SPI_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_SPI_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32_syscfg.h b/arch/arm/src/stm32h7/hardware/stm32_syscfg.h
similarity index 89%
rename from arch/arm/src/stm32h7/chip/stm32_syscfg.h
rename to arch/arm/src/stm32h7/hardware/stm32_syscfg.h
index bbd13bbf307..fdab6b1d387 100644
--- a/arch/arm/src/stm32h7/chip/stm32_syscfg.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_syscfg.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_syscfg.h
+ * arch/arm/src/stm32h7/hardware/stm32_syscfg.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_SYSCFG_H
 
 /************************************************************************************
  * Included Files
@@ -44,9 +44,9 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32H7_STM32H7X3XX)
-#  include "chip/stm32h7x3xx_syscfg.h"
+#  include "hardware/stm32h7x3xx_syscfg.h"
 #else
 #  error "Unsupported STM32 H7 part"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_SYSCFG_H */
diff --git a/arch/arm/src/stm32h7/hardware/stm32_tim.h b/arch/arm/src/stm32h7/hardware/stm32_tim.h
new file mode 100644
index 00000000000..2ca0e169f5c
--- /dev/null
+++ b/arch/arm/src/stm32h7/hardware/stm32_tim.h
@@ -0,0 +1,1158 @@
+/****************************************************************************
+ * arch/arm/src/stm32h7/hardware/stm32_tim.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *            David Sidrane 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_TIM_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_TIM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include "chip.h"
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* The STM32H7 family uses STM32 TIMER IP version 2 */
+
+#define HAVE_IP_TIMERS_V2 1
+
+/* Register Offsets *********************************************************************************/
+
+/* Basic Timers - TIM6 and TIM7 */
+
+#define STM32_BTIM_CR1_OFFSET     0x0000  /* Control register 1 (16-bit) */
+#define STM32_BTIM_CR2_OFFSET     0x0004  /* Control register 2 (16-bit) */
+#define STM32_BTIM_DIER_OFFSET    0x000c  /* DMA/Interrupt enable register (16-bit) */
+#define STM32_BTIM_SR_OFFSET      0x0010  /* Status register (16-bit) */
+#define STM32_BTIM_EGR_OFFSET     0x0014  /* Event generation register (16-bit) */
+#define STM32_BTIM_CNT_OFFSET     0x0024  /* Counter (16-bit) */
+#define STM32_BTIM_PSC_OFFSET     0x0028  /* Prescaler (16-bit) */
+#define STM32_BTIM_ARR_OFFSET     0x002c  /* Auto-reload register (16-bit) */
+
+/* 16-/32-bit General Timers with DMA: TIM2, TM3, TIM4, and TIM5
+ * 16-bit General Timers without DMA: TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
+ * timers are 16-bit except for TIM2 and 5 are 32-bit
+ * timers TIM9 and 12 are different then  TIM10, TIM11, TIM13, and TIM14
+ */
+
+#define STM32_GTIM_CR1_OFFSET      0x0000  /* Control register 1 (16-bit) */
+#define STM32_GTIM_CR2_OFFSET      0x0004  /* Control register 2 (16-bit, TIM2, 5 only) */
+#define STM32_GTIM_SMCR_OFFSET     0x0008  /* Slave mode control register (32-bit, TIM2, 5, 9, 12 only) */
+#define STM32_GTIM_DIER_OFFSET     0x000c  /* DMA/Interrupt enable register (16-bit) */
+#define STM32_GTIM_SR_OFFSET       0x0010  /* Status register (16-bit) */
+#define STM32_GTIM_EGR_OFFSET      0x0014  /* Event generation register (16-bit) */
+#define STM32_GTIM_CCMR1_OFFSET    0x0018  /* Capture/compare mode register 1 (32-bit) */
+#define STM32_GTIM_CCMR2_OFFSET    0x001c  /* Capture/compare mode register 2 (32-bit on TIM2,5 only) */
+#define STM32_GTIM_CCER_OFFSET     0x0020  /* Capture/compare enable register (16-bit) */
+#define STM32_GTIM_CNT_OFFSET      0x0024  /* Counter (16 bit and 32-bit on TIM2, 5 only) */
+#define STM32_GTIM_PSC_OFFSET      0x0028  /* Prescaler (16-bit) */
+#define STM32_GTIM_ARR_OFFSET      0x002c  /* Auto-reload register (16 bit and 32-bit on TIM2, 5 only) */
+#define STM32_GTIM_CCR1_OFFSET     0x0034  /* Capture/compare register 1 (16-bit on all TIMx and 32-bit on TIM2,5 only) */
+#define STM32_GTIM_CCR2_OFFSET     0x0038  /* Capture/compare register 2 (16-bit TIM 3-4, 9, 12 and 32-bit on TIM2,5 only) */
+#define STM32_GTIM_CCR3_OFFSET     0x003c  /* Capture/compare register 3 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */
+#define STM32_GTIM_CCR4_OFFSET     0x0040  /* Capture/compare register 4 (16-bit TIM 3-4 and 32-bit on TIM2,5 only) */
+#define STM32_GTIM_DCR_OFFSET      0x0048  /* DMA control register (16-bit, TIM2-5 only) */
+#define STM32_GTIM_DMAR_OFFSET     0x004c  /* DMA address for burst mode (16-bit, TIM2-5 only) */
+
+/* Advanced Timers - TIM1 and TIM8 */
+
+#define STM32_ATIM_CR1_OFFSET      0x0000  /* Control register 1 (16-bit) */
+#define STM32_ATIM_CR2_OFFSET      0x0004  /* Control register 2 (32-bit*) */
+#define STM32_ATIM_SMCR_OFFSET     0x0008  /* Slave mode control register (32 -bit) */
+#define STM32_ATIM_DIER_OFFSET     0x000c  /* DMA/Interrupt enable register (16-bit) */
+#define STM32_ATIM_SR_OFFSET       0x0010  /* Status register (32-bit*) */
+#define STM32_ATIM_EGR_OFFSET      0x0014  /* Event generation register (16-bit) */
+#define STM32_ATIM_CCMR1_OFFSET    0x0018  /* Capture/compare mode register 1 (32-bit*) */
+#define STM32_ATIM_CCMR2_OFFSET    0x001c  /* Capture/compare mode register 2 (32-bit*) */
+#define STM32_ATIM_CCER_OFFSET     0x0020  /* Capture/compare enable register (32-bit*) */
+#define STM32_ATIM_CNT_OFFSET      0x0024  /* Counter (32-bit cnt in lower 16 bit ) */
+#define STM32_ATIM_PSC_OFFSET      0x0028  /* Prescaler (16-bit) */
+#define STM32_ATIM_ARR_OFFSET      0x002c  /* Auto-reload register (16-bit) */
+#define STM32_ATIM_RCR_OFFSET      0x0030  /* Repetition counter register (16-bit) */
+#define STM32_ATIM_CCR1_OFFSET     0x0034  /* Capture/compare register 1 (16-bit) */
+#define STM32_ATIM_CCR2_OFFSET     0x0038  /* Capture/compare register 2 (16-bit) */
+#define STM32_ATIM_CCR3_OFFSET     0x003c  /* Capture/compare register 3 (16-bit) */
+#define STM32_ATIM_CCR4_OFFSET     0x0040  /* Capture/compare register 4 (16-bit) */
+#define STM32_ATIM_BDTR_OFFSET     0x0044  /* Break and dead-time register (32-bit*) */
+#define STM32_ATIM_DCR_OFFSET      0x0048  /* DMA control register (16-bit) */
+#define STM32_ATIM_DMAR_OFFSET     0x004c  /* DMA address for burst mode (16-bit) */
+#define STM32_ATIM_CCMR3_OFFSET    0x0054  /* Capture/compare mode register 3 (32-bit) */
+#define STM32_ATIM_CCR5_OFFSET     0x0058  /* Capture/compare register 5 (32-bit) */
+#define STM32_ATIM_CCR6_OFFSET     0x005c  /* Capture/compare register 6 (16-bit) */
+#define STM32_ATIM_AF1_OFFSET      0x0060  /* Alternate function option register 1 (16-bit) */
+#define STM32_ATIM_AF2_OFFSET      0x0064  /* Alternate function option register 2 (16-bit) */
+#define STM32_ATIM_TISEL_OFFSET    0x0068  /* Timer input selection register (32-bit) */
+
+/* Register Addresses *******************************************************************************/
+
+/* Advanced Timers - TIM1 and TIM8 */
+
+#  define STM32_TIM1_CR1          (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET)
+#  define STM32_TIM1_CR2          (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET)
+#  define STM32_TIM1_SMCR         (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET)
+#  define STM32_TIM1_DIER         (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET)
+#  define STM32_TIM1_SR           (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET)
+#  define STM32_TIM1_EGR          (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET)
+#  define STM32_TIM1_CCMR1        (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET)
+#  define STM32_TIM1_CCMR2        (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET)
+#  define STM32_TIM1_CCER         (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET)
+#  define STM32_TIM1_CNT          (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET)
+#  define STM32_TIM1_PSC          (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET)
+#  define STM32_TIM1_ARR          (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET)
+#  define STM32_TIM1_RCR          (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET)
+#  define STM32_TIM1_CCR1         (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET)
+#  define STM32_TIM1_CCR2         (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET)
+#  define STM32_TIM1_CCR3         (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET)
+#  define STM32_TIM1_CCR4         (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET)
+#  define STM32_TIM1_BDTR         (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET)
+#  define STM32_TIM1_DCR          (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET)
+#  define STM32_TIM1_DMAR         (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET)
+#  define STM32_TIM1_CCMR3        (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET)
+#  define STM32_TIM1_CCR5         (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET)
+#  define STM32_TIM1_CCR6         (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET)
+#  define STM32_TIM1_AF1          (STM32_TIM1_BASE+STM32_ATIM_AF1_OFFSET)
+#  define STM32_TIM1_AF2          (STM32_TIM1_BASE+STM32_ATIM_AF2_OFFSET)
+#  define STM32_TIM1_TISEL        (STM32_TIM1_BASE+STM32_ATIM_TISEL_OFFSET)
+
+#  define STM32_TIM8_CR1          (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET)
+#  define STM32_TIM8_CR2          (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET)
+#  define STM32_TIM8_SMCR         (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET)
+#  define STM32_TIM8_DIER         (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET)
+#  define STM32_TIM8_SR           (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET)
+#  define STM32_TIM8_EGR          (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET)
+#  define STM32_TIM8_CCMR1        (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET)
+#  define STM32_TIM8_CCMR2        (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET)
+#  define STM32_TIM8_CCER         (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET)
+#  define STM32_TIM8_CNT          (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET)
+#  define STM32_TIM8_PSC          (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET)
+#  define STM32_TIM8_ARR          (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET)
+#  define STM32_TIM8_RCR          (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET)
+#  define STM32_TIM8_CCR1         (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET)
+#  define STM32_TIM8_CCR2         (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET)
+#  define STM32_TIM8_CCR3         (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET)
+#  define STM32_TIM8_CCR4         (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET)
+#  define STM32_TIM8_BDTR         (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET)
+#  define STM32_TIM8_DCR          (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET)
+#  define STM32_TIM8_DMAR         (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET)
+#  define STM32_TIM8_CCMR3        (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET)
+#  define STM32_TIM8_CCR5         (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET)
+#  define STM32_TIM8_CCR6         (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET)
+#  define STM32_TIM8_AF1          (STM32_TIM8_BASE+STM32_ATIM_AF1_OFFSET)
+#  define STM32_TIM8_AF2          (STM32_TIM8_BASE+STM32_ATIM_AF2_OFFSET)
+#  define STM32_TIM8_TISEL        (STM32_TIM8_BASE+STM32_ATIM_TISEL_OFFSET)
+
+/* 16-/32-bit General Timers - TIM2, TIM3, TIM4, and TIM5 with DMA.
+ * All timers are 16-bit except for TIM2 and 5 are 32-bit
+ */
+
+#  define STM32_TIM2_CR1          (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM2_CR2          (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM2_SMCR         (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET)
+#  define STM32_TIM2_DIER         (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM2_SR           (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM2_EGR          (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM2_CCMR1        (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM2_CCMR2        (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET)
+#  define STM32_TIM2_CCER         (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM2_CNT          (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM2_PSC          (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM2_ARR          (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM2_CCR1         (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM2_CCR2         (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET)
+#  define STM32_TIM2_CCR3         (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET)
+#  define STM32_TIM2_CCR4         (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET)
+#  define STM32_TIM2_DCR          (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET)
+#  define STM32_TIM2_DMAR         (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET)
+#  define STM32_TIM2_AF1          (STM32_TIM2_BASE+STM32_ATIM_AF1_OFFSET)
+#  define STM32_TIM2_AF2          (STM32_TIM2_BASE+STM32_ATIM_AF2_OFFSET)
+#  define STM32_TIM2_TISEL        (STM32_TIM2_BASE+STM32_ATIM_TISEL_OFFSET)
+
+#  define STM32_TIM3_CR1          (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM3_CR2          (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM3_SMCR         (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET)
+#  define STM32_TIM3_DIER         (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM3_SR           (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM3_EGR          (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM3_CCMR1        (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM3_CCMR2        (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET)
+#  define STM32_TIM3_CCER         (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM3_CNT          (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM3_PSC          (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM3_ARR          (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM3_CCR1         (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM3_CCR2         (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET)
+#  define STM32_TIM3_CCR3         (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET)
+#  define STM32_TIM3_CCR4         (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET)
+#  define STM32_TIM3_DCR          (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET)
+#  define STM32_TIM3_DMAR         (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET)
+#  define STM32_TIM3_AF1          (STM32_TIM3_BASE+STM32_ATIM_AF1_OFFSET)
+#  define STM32_TIM3_AF2          (STM32_TIM3_BASE+STM32_ATIM_AF2_OFFSET)
+#  define STM32_TIM3_TISEL        (STM32_TIM3_BASE+STM32_ATIM_TISEL_OFFSET)
+
+#  define STM32_TIM4_CR1          (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM4_CR2          (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM4_SMCR         (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET)
+#  define STM32_TIM4_DIER         (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM4_SR           (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM4_EGR          (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM4_CCMR1        (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM4_CCMR2        (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET)
+#  define STM32_TIM4_CCER         (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM4_CNT          (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM4_PSC          (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM4_ARR          (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM4_CCR1         (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM4_CCR2         (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET)
+#  define STM32_TIM4_CCR3         (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET)
+#  define STM32_TIM4_CCR4         (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET)
+#  define STM32_TIM4_DCR          (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET)
+#  define STM32_TIM4_DMAR         (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET)
+#  define STM32_TIM4_AF1          (STM32_TIM4_BASE+STM32_ATIM_AF1_OFFSET)
+#  define STM32_TIM4_AF2          (STM32_TIM4_BASE+STM32_ATIM_AF2_OFFSET)
+#  define STM32_TIM4_TISEL        (STM32_TIM4_BASE+STM32_ATIM_TISEL_OFFSET)
+
+#  define STM32_TIM5_CR1          (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM5_CR2          (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM5_SMCR         (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET)
+#  define STM32_TIM5_DIER         (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM5_SR           (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM5_EGR          (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM5_CCMR1        (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM5_CCMR2        (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET)
+#  define STM32_TIM5_CCER         (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM5_CNT          (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM5_PSC          (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM5_ARR          (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM5_CCR1         (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM5_CCR2         (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET)
+#  define STM32_TIM5_CCR3         (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET)
+#  define STM32_TIM5_CCR4         (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET)
+#  define STM32_TIM5_DCR          (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET)
+#  define STM32_TIM5_DMAR         (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET)
+#  define STM32_TIM5_AF1          (STM32_TIM5_BASE+STM32_ATIM_AF1_OFFSET)
+#  define STM32_TIM5_AF2          (STM32_TIM5_BASE+STM32_ATIM_AF2_OFFSET)
+#  define STM32_TIM5_TISEL        (STM32_TIM5_BASE+STM32_ATIM_TISEL_OFFSET)
+
+/* 16-bit General Timers - TIM12-14 without dma */
+
+#  define STM32_TIM12_CR1          (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM12_CR2          (STM32_TIM12_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM12_SMCR         (STM32_TIM12_BASE+STM32_GTIM_SMCR_OFFSET)
+#  define STM32_TIM12_DIER         (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM12_SR           (STM32_TIM12_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM12_EGR          (STM32_TIM12_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM12_CCMR1        (STM32_TIM12_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM12_CCER         (STM32_TIM12_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM12_CNT          (STM32_TIM12_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM12_PSC          (STM32_TIM12_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM12_ARR          (STM32_TIM12_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM12_CCR1         (STM32_TIM12_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM12_CCR2         (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET)
+#  define STM32_TIM12_TISEL        (STM32_TIM12_BASE+STM32_ATIM_TISEL_OFFSET)
+
+#  define STM32_TIM13_CR1          (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM13_DIER         (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM13_SR           (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM13_EGR          (STM32_TIM13_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM13_CCMR1        (STM32_TIM13_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM13_CCER         (STM32_TIM13_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM13_CNT          (STM32_TIM13_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM13_PSC          (STM32_TIM13_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM13_ARR          (STM32_TIM13_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM13_CCR1         (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM13_TISEL        (STM32_TIM13_BASE+STM32_ATIM_TISEL_OFFSET)
+
+#  define STM32_TIM14_CR1          (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM14_DIER         (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM14_SR           (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM14_EGR          (STM32_TIM14_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM14_CCMR1        (STM32_TIM14_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM14_CCER         (STM32_TIM14_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM14_CNT          (STM32_TIM14_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM14_PSC          (STM32_TIM14_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM14_ARR          (STM32_TIM14_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM14_CCR1         (STM32_TIM14_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM14_TISEL        (STM32_TIM14_BASE+STM32_ATIM_TISEL_OFFSET)
+
+/* 16-bit General Timers - TIM15-17 */
+
+#  define STM32_TIM15_CR1          (STM32_TIM15_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM15_CR2          (STM32_TIM15_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM15_SMCR         (STM32_TIM15_BASE+STM32_GTIM_SMCR_OFFSET)
+#  define STM32_TIM15_DIER         (STM32_TIM15_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM15_SR           (STM32_TIM15_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM15_EGR          (STM32_TIM15_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM15_CCMR1        (STM32_TIM15_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM15_CCER         (STM32_TIM15_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM15_CNT          (STM32_TIM15_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM15_PSC          (STM32_TIM15_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM15_ARR          (STM32_TIM15_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM15_CCR1         (STM32_TIM15_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM15_CCR2         (STM32_TIM15_BASE+STM32_GTIM_CCR2_OFFSET)
+#  define STM32_TIM15_BDTR         (STM32_TIM15_BASE+STM32_GTIM_BDTR_OFFSET)
+#  define STM32_TIM15_DCR          (STM32_TIM15_BASE+STM32_GTIM_DCR_OFFSET)
+#  define STM32_TIM15_DMAR         (STM32_TIM15_BASE+STM32_GTIM_DMAR_OFFSET)
+#  define STM32_TIM15_AF1          (STM32_TIM15_BASE+STM32_GTIM_AF1_OFFSET)
+#  define STM32_TIM15_TISEL        (STM32_TIM15_BASE+STM32_ATIM_TISEL_OFFSET)
+
+#  define STM32_TIM16_CR1          (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM16_CR2          (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM16_DIER         (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM16_SR           (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM16_EGR          (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM16_CCMR1        (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM16_CCER         (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM16_CNT          (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM16_PSC          (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM16_ARR          (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM16_RCR          (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET)
+#  define STM32_TIM16_CCR1         (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM16_BDTR         (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET)
+#  define STM32_TIM16_DCR          (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET)
+#  define STM32_TIM16_DMAR         (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET)
+#  define STM32_TIM16_AF1          (STM32_TIM16_BASE+STM32_GTIM_AF1_OFFSET)
+#  define STM32_TIM16_TISEL        (STM32_TIM16_BASE+STM32_ATIM_TISEL_OFFSET)
+
+#  define STM32_TIM17_CR1          (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET)
+#  define STM32_TIM17_CR2          (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET)
+#  define STM32_TIM17_DIER         (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET)
+#  define STM32_TIM17_SR           (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET)
+#  define STM32_TIM17_EGR          (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET)
+#  define STM32_TIM17_CCMR1        (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET)
+#  define STM32_TIM17_CCER         (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET)
+#  define STM32_TIM17_CNT          (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET)
+#  define STM32_TIM17_PSC          (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET)
+#  define STM32_TIM17_ARR          (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET)
+#  define STM32_TIM17_RCR          (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET)
+#  define STM32_TIM17_CCR1         (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET)
+#  define STM32_TIM17_BDTR         (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET)
+#  define STM32_TIM17_DCR          (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET)
+#  define STM32_TIM17_DMAR         (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET)
+#  define STM32_TIM17_AF1          (STM32_TIM17_BASE+STM32_GTIM_AF1_OFFSET)
+#  define STM32_TIM17_TISEL        (STM32_TIM17_BASE+STM32_ATIM_TISEL_OFFSET)
+
+/* Basic Timers - TIM6 and TIM7 */
+
+#  define STM32_TIM6_CR1          (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET)
+#  define STM32_TIM6_CR2          (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET)
+#  define STM32_TIM6_DIER         (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET)
+#  define STM32_TIM6_SR           (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET)
+#  define STM32_TIM6_EGR          (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET)
+#  define STM32_TIM6_CNT          (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET)
+#  define STM32_TIM6_PSC          (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET)
+#  define STM32_TIM6_ARR          (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET)
+
+#  define STM32_TIM7_CR1          (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET)
+#  define STM32_TIM7_CR2          (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET)
+#  define STM32_TIM7_DIER         (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET)
+#  define STM32_TIM7_SR           (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET)
+#  define STM32_TIM7_EGR          (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET)
+#  define STM32_TIM7_CNT          (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET)
+#  define STM32_TIM7_PSC          (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET)
+#  define STM32_TIM7_ARR          (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************************************/
+
+/* Control register 1 */
+
+#define ATIM_CR1_CEN              (1 << 0)  /* Bit 0: Counter enable */
+#define ATIM_CR1_UDIS             (1 << 1)  /* Bit 1: Update disable */
+#define ATIM_CR1_URS              (1 << 2)  /* Bit 2: Update request source */
+#define ATIM_CR1_OPM              (1 << 3)  /* Bit 3: One pulse mode */
+#define ATIM_CR1_DIR              (1 << 4)  /* Bit 4: Direction */
+#define ATIM_CR1_CMS_SHIFT        (5)       /* Bits 6-5: Center-aligned mode selection */
+#define ATIM_CR1_CMS_MASK         (3 << ATIM_CR1_CMS_SHIFT)
+#  define ATIM_CR1_EDGE           (0 << ATIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */
+#  define ATIM_CR1_CENTER1        (1 << ATIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
+#  define ATIM_CR1_CENTER2        (2 << ATIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
+#  define ATIM_CR1_CENTER3        (3 << ATIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
+#define ATIM_CR1_ARPE             (1 << 7)  /* Bit 7: Auto-reload preload enable */
+#define ATIM_CR1_CKD_SHIFT        (8)       /* Bits 9-8: Clock division */
+#define ATIM_CR1_CKD_MASK         (3 << ATIM_CR1_CKD_SHIFT)
+#  define ATIM_CR1_TCKINT         (0 << ATIM_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */
+#  define ATIM_CR1_2TCKINT        (1 << ATIM_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */
+#  define ATIM_CR1_4TCKINT        (2 << ATIM_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */
+#define ATIM_CR1_UIFREMAP         (1 << 11) /* Bit 11: UIF status bit remapping */
+
+/* Control register 2 */
+
+#define ATIM_CR2_CCPC             (1 << 0)  /* Bit 0:  Capture/Compare Preloaded Control */
+#define ATIM_CR2_CCUS             (1 << 2)  /* Bit 2:  Capture/Compare Control Update Selection */
+#define ATIM_CR2_CCDS             (1 << 3)  /* Bit 3:  Capture/Compare DMA Selection */
+#define ATIM_CR2_MMS_SHIFT        (4)       /* Bits 6-4: Master Mode Selection */
+#define ATIM_CR2_MMS_MASK         (7 << ATIM_CR2_MMS_SHIFT)
+#  define ATIM_CR2_MMS_RESET      (0 << ATIM_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */
+#  define ATIM_CR2_MMS_ENABLE     (1 << ATIM_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */
+#  define ATIM_CR2_MMS_UPDATE     (2 << ATIM_CR2_MMS_SHIFT) /* 010: Update event is TRGO */
+#  define ATIM_CR2_MMS_COMPP      (3 << ATIM_CR2_MMS_SHIFT) /* 010: Compare Pulse - CC1IF flag */
+#  define ATIM_CR2_MMS_OC1REF     (4 << ATIM_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */
+#  define ATIM_CR2_MMS_OC2REF     (5 << ATIM_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */
+#  define ATIM_CR2_MMS_OC3REF     (6 << ATIM_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */
+#  define ATIM_CR2_MMS_OC4REF     (7 << ATIM_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */
+#define ATIM_CR2_TI1S             (1 << 7)  /* Bit 7: TI1 Selection */
+#define ATIM_CR2_OIS1             (1 << 8)  /* Bit 8:  Output Idle state 1 (OC1 output) */
+#define ATIM_CR2_OIS1N            (1 << 9)  /* Bit 9:  Output Idle state 1 (OC1N output) */
+#define ATIM_CR2_OIS2             (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */
+#define ATIM_CR2_OIS2N            (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */
+#define ATIM_CR2_OIS3             (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */
+#define ATIM_CR2_OIS3N            (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */
+#define ATIM_CR2_OIS4             (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */
+#define ATIM_CR2_OIS5             (1 << 16) /* Bit 16: OOutput Idle state 5 (OC5 output) */
+#define ATIM_CR2_OIS6             (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */
+#define ATIM_CR2_MMS2_SHIFT       (20)      /* Bits 20-23: Master Mode Selection 2 */
+#define ATIM_CR2_MMS2_MASK        (15 << ATIM_CR2_MMS2_SHIFT)
+#  define ATIM_CR2_MMS2_RESET     (0 << ATIM_CR2_MMS2_SHIFT)  /* 0000: Reset - TIMx_EGR UG bit is TRG9 */
+#  define ATIM_CR2_MMS2_ENABLE    (1 << ATIM_CR2_MMS2_SHIFT)  /* 0001: Enable - CNT_EN is TRGO2 */
+#  define ATIM_CR2_MMS2_UPDATE    (2 << ATIM_CR2_MMS2_SHIFT)  /* 0010: Update event is TRGH0*/
+#  define ATIM_CR2_MMS2_COMPP     (3 << ATIM_CR2_MMS2_SHIFT)  /* 0010: Compare Pulse - CC1IF flag */
+#  define ATIM_CR2_MMS2_OC1REF    (4 << ATIM_CR2_MMS2_SHIFT)  /* 0100: Compare OC1REF is TRGO2 */
+#  define ATIM_CR2_MMS2_OC2REF    (5 << ATIM_CR2_MMS2_SHIFT)  /* 0101: Compare OC2REF is TRGO2 */
+#  define ATIM_CR2_MMS2_OC3REF    (6 << ATIM_CR2_MMS2_SHIFT)  /* 0110: Compare OC3REF is TRGO2 */
+#  define ATIM_CR2_MMS2_OC4REF    (7 << ATIM_CR2_MMS2_SHIFT)  /* 0111: Compare OC4REF is TRGO2 */
+#  define ATIM_CR2_MMS2_OC5REF    (8 << ATIM_CR2_MMS2_SHIFT)  /* 1000: Compare OC5REF is TRGO2 */
+#  define ATIM_CR2_MMS2_OC6REF    (9 << ATIM_CR2_MMS2_SHIFT)  /* 1001: Compare OC6REF is TRGO2 */
+#  define ATIM_CR2_MMS2_CMPOC4    (10 << ATIM_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */
+#  define ATIM_CR2_MMS2_CMPOC6    (11 << ATIM_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */
+#  define ATIM_CR2_MMS2_CMPOC4R6R (12 << ATIM_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */
+#  define ATIM_CR2_MMS2_CMPOC4R6F (13 << ATIM_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */
+#  define ATIM_CR2_MMS2_CMPOC5R6R (14 << ATIM_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */
+#  define ATIM_CR2_MMS2_CMPOC5R6F (15 << ATIM_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */
+
+/* Slave mode control register */
+
+#define ATIM_SMCR_SMS_SHIFT       (0)       /* Bits 0-2: Slave mode selection */
+#define ATIM_SMCR_SMS_MASK        (7 << ATIM_SMCR_SMS_SHIFT)
+#  define ATIM_SMCR_DISAB         (0 << ATIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
+#  define ATIM_SMCR_ENCMD1        (1 << ATIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
+#  define ATIM_SMCR_ENCMD2        (2 << ATIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
+#  define ATIM_SMCR_ENCMD3        (3 << ATIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
+#  define ATIM_SMCR_RESET         (4 << ATIM_SMCR_SMS_SHIFT) /* 100: Reset Mode */
+#  define ATIM_SMCR_GATED         (5 << ATIM_SMCR_SMS_SHIFT) /* 101: Gated Mode */
+#  define ATIM_SMCR_TRIGGER       (6 << ATIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
+#  define ATIM_SMCR_EXTCLK1       (7 << ATIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
+#define ATIM_SMCR_TS_SHIFT        (4)       /* Bits 4-6: Trigger selection */
+#define ATIM_SMCR_TS_MASK         (7 << ATIM_SMCR_TS_SHIFT)
+#  define ATIM_SMCR_ITR0          (0 << ATIM_SMCR_TS_SHIFT) /* 000: Internal trigger 0 (ITR0) */
+#  define ATIM_SMCR_ITR1          (1 << ATIM_SMCR_TS_SHIFT) /* 001: Internal trigger 1 (ITR1) */
+#  define ATIM_SMCR_ITR2          (2 << ATIM_SMCR_TS_SHIFT) /* 010: Internal trigger 2 (ITR2) */
+#  define ATIM_SMCR_ITR3          (3 << ATIM_SMCR_TS_SHIFT) /* 011: Internal trigger 3 (ITR3) */
+#  define ATIM_SMCR_T1FED         (4 << ATIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
+#  define ATIM_SMCR_TI1FP1        (5 << ATIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
+#  define ATIM_SMCR_T12FP2        (6 << ATIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
+#  define ATIM_SMCR_ETRF          (7 << ATIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
+#define ATIM_SMCR_MSM             (1 << 7)  /* Bit 7: Master/slave mode */
+#define ATIM_SMCR_ETF_SHIFT       (8)       /* Bits 8-11: External trigger filter */
+#define ATIM_SMCR_ETF_MASK        (0x0f << ATIM_SMCR_ETF_SHIFT)
+#  define ATIM_SMCR_NOFILT        (0 << ATIM_SMCR_ETF_SHIFT) /* 0000: No filter, sampling is done at fDTS */
+#  define ATIM_SMCR_FCKINT2       (1 << ATIM_SMCR_ETF_SHIFT) /* 0001: fSAMPLING=fCK_INT, N=2 */
+#  define ATIM_SMCR_FCKINT4       (2 << ATIM_SMCR_ETF_SHIFT) /* 0010: fSAMPLING=fCK_INT, N=4 */
+#  define ATIM_SMCR_FCKINT8       (3 << ATIM_SMCR_ETF_SHIFT) /* 0011: fSAMPLING=fCK_INT, N=8 */
+#  define ATIM_SMCR_FDTSd26       (4 << ATIM_SMCR_ETF_SHIFT) /* 0100: fSAMPLING=fDTS/2, N=6 */
+#  define ATIM_SMCR_FDTSd28       (5 << ATIM_SMCR_ETF_SHIFT) /* 0101: fSAMPLING=fDTS/2, N=8 */
+#  define ATIM_SMCR_FDTSd46       (6 << ATIM_SMCR_ETF_SHIFT) /* 0110: fSAMPLING=fDTS/4, N=6 */
+#  define ATIM_SMCR_FDTSd48       (7 << ATIM_SMCR_ETF_SHIFT) /* 0111: fSAMPLING=fDTS/4, N=8 */
+#  define ATIM_SMCR_FDTSd86       (8 << ATIM_SMCR_ETF_SHIFT) /* 1000: fSAMPLING=fDTS/8, N=6 */
+#  define ATIM_SMCR_FDTSd88       (9 << ATIM_SMCR_ETF_SHIFT) /* 1001: fSAMPLING=fDTS/8, N=8 */
+#  define ATIM_SMCR_FDTSd165      (10 << ATIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
+#  define ATIM_SMCR_FDTSd166      (11 << ATIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
+#  define ATIM_SMCR_FDTSd168      (12 << ATIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
+#  define ATIM_SMCR_FDTSd325      (13 << ATIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
+#  define ATIM_SMCR_FDTSd326      (14 << ATIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
+#  define ATIM_SMCR_FDTSd328      (15 << ATIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
+#define ATIM_SMCR_ETPS_SHIFT      (12)      /* Bits 12-13: External trigger prescaler */
+#define ATIM_SMCR_ETPS_MASK       (3 << ATIM_SMCR_ETPS_SHIFT)
+#  define ATIM_SMCR_PSCOFF        (0 << ATIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
+#  define ATIM_SMCR_ETRPd2        (1 << ATIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
+#  define ATIM_SMCR_ETRPd4        (2 << ATIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
+#  define ATIM_SMCR_ETRPd8        (3 << ATIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
+#define ATIM_SMCR_ECE             (1 << 14) /* Bit 14: External clock enable */
+#define ATIM_SMCR_ETP             (1 << 15) /* Bit 15: External trigger polarity */
+#define ATIM_SMCR_SMS             (1 << 16) /* Bit 16: Slave mode selection - bit 3 */
+
+/* DMA/Interrupt enable register */
+
+#define ATIM_DIER_UIE             (1 << 0)  /* Bit 0: Update interrupt enable */
+#define ATIM_DIER_CC1IE           (1 << 1)  /* Bit 1: Capture/Compare 1 interrupt enable */
+#define ATIM_DIER_CC2IE           (1 << 2)  /* Bit 2: Capture/Compare 2 interrupt enable */
+#define ATIM_DIER_CC3IE           (1 << 3)  /* Bit 3: Capture/Compare 3 interrupt enable */
+#define ATIM_DIER_CC4IE           (1 << 4)  /* Bit 4: Capture/Compare 4 interrupt enable */
+#define ATIM_DIER_COMIE           (1 << 5)  /* Bit 5: COM interrupt enable */
+#define ATIM_DIER_TIE             (1 << 6)  /* Bit 6: Trigger interrupt enable */
+#define ATIM_DIER_BIE             (1 << 7)  /* Bit 7: Break interrupt enable */
+#define ATIM_DIER_UDE             (1 << 8)  /* Bit 8: Update DMA request enable */
+#define ATIM_DIER_CC1DE           (1 << 9)  /* Bit 9: Capture/Compare 1 DMA request enable */
+#define ATIM_DIER_CC2DE           (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */
+#define ATIM_DIER_CC3DE           (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */
+#define ATIM_DIER_CC4DE           (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */
+#define ATIM_DIER_COMDE           (1 << 13) /* Bit 13: COM DMA request enable */
+#define ATIM_DIER_TDE             (1 << 14) /* Bit 14: Trigger DMA request enable */
+
+/* Status register */
+
+#define ATIM_SR_UIF               (1 << 0)  /* Bit 0:  Update interrupt Flag */
+#define ATIM_SR_CC1IF             (1 << 1)  /* Bit 1:  Capture/Compare 1 interrupt Flag */
+#define ATIM_SR_CC2IF             (1 << 2)  /* Bit 2:  Capture/Compare 2 interrupt Flag */
+#define ATIM_SR_CC3IF             (1 << 3)  /* Bit 3:  Capture/Compare 3 interrupt Flag */
+#define ATIM_SR_CC4IF             (1 << 4)  /* Bit 4:  Capture/Compare 4 interrupt Flag */
+#define ATIM_SR_COMIF             (1 << 5)  /* Bit 5:  COM interrupt Flag */
+#define ATIM_SR_TIF               (1 << 6)  /* Bit 6:  Trigger interrupt Flag */
+#define ATIM_SR_BIF               (1 << 7)  /* Bit 7:  Break interrupt Flag */
+#define ATIM_SR_B2IF              (1 << 8)  /* Bit 8:  Break 2 interrupt Flag */
+#define ATIM_SR_CC1OF             (1 << 9)  /* Bit 9:  Capture/Compare 1 Overcapture Flag */
+#define ATIM_SR_CC2OF             (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */
+#define ATIM_SR_CC3OF             (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */
+#define ATIM_SR_CC4OF             (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */
+#define ATIM_SR_CC5IF             (1 << 16) /* Bit 16: Compare 5 interrupt flag */
+#define ATIM_SR_CC6IF             (1 << 17) /* Bit 17: Compare 6 interrupt flag */
+
+/* Event generation register */
+
+#define ATIM_EGR_UG               (1 << 0)  /* Bit 0: Update Generation */
+#define ATIM_EGR_CC1G             (1 << 1)  /* Bit 1: Capture/Compare 1 Generation */
+#define ATIM_EGR_CC2G             (1 << 2)  /* Bit 2: Capture/Compare 2 Generation */
+#define ATIM_EGR_CC3G             (1 << 3)  /* Bit 3: Capture/Compare 3 Generation */
+#define ATIM_EGR_CC4G             (1 << 4)  /* Bit 4: Capture/Compare 4 Generation */
+#define ATIM_EGR_COMG             (1 << 5)  /* Bit 5: Capture/Compare Control Update Generation */
+#define ATIM_EGR_TG               (1 << 6)  /* Bit 6: Trigger Generation */
+#define ATIM_EGR_BG               (1 << 7)  /* Bit 7: Break Generation */
+#define ATIM_EGR_B2G              (1 << 8)  /* Bit 8: Break 2 Generation */
+
+/* Capture/compare mode register 1 -- Output compare mode */
+
+#define ATIM_CCMR1_CC1S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 1 Selection */
+#define ATIM_CCMR1_CC1S_MASK      (3 << ATIM_CCMR1_CC1S_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC1FE          (1 << 2)  /* Bit 2: Output Compare 1 Fast enable */
+#define ATIM_CCMR1_OC1PE          (1 << 3)  /* Bit 3: Output Compare 1 Preload enable */
+#define ATIM_CCMR1_OC1M_SHIFT     (4)       /* Bits 6-4: Output Compare 1 Mode */
+#define ATIM_CCMR1_OC1M_MASK      (7 << ATIM_CCMR1_OC1M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC1CE          (1 << 7)  /* Bit 7: Output Compare 1Clear Enable */
+#define ATIM_CCMR1_CC2S_SHIFT     (8)       /* Bits 8-9: Capture/Compare 2 Selection */
+#define ATIM_CCMR1_CC2S_MASK      (3 << ATIM_CCMR1_CC2S_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC2FE          (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
+#define ATIM_CCMR1_OC2PE          (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
+#define ATIM_CCMR1_OC2M_SHIFT     (12)      /* Bits 14-12: Output Compare 2 Mode */
+#define ATIM_CCMR1_OC2M_MASK      (7 << ATIM_CCMR1_OC2M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_OC2CE          (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
+#define ATIM_CCMR1_OC1M           (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */
+#define ATIM_CCMR1_OC2M           (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */
+
+/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
+
+#define ATIM_CCMR_CCS_CCOUT       (0)       /* 00: CCx channel  output */
+#define ATIM_CCMR_CCS_CCIN1       (1)       /* 01: CCx channel input, ICx is TIx */
+#define ATIM_CCMR_CCS_CCIN2       (2)       /* 10: CCx channel input, ICx is TIy */
+#define ATIM_CCMR_CCS_CCINTRC     (3)       /* 11: CCx channel input, ICx is TRC */
+
+/* Common CCMR (unshifted) Compare Mode bit field definitions */
+
+#define ATIM_CCMR_MODE_FRZN        (0)      /* 0000: Frozen */
+#define ATIM_CCMR_MODE_CHACT       (1)      /* 0001: Channel x active on match */
+#define ATIM_CCMR_MODE_CHINACT     (2)      /* 0010: Channel x inactive on match */
+#define ATIM_CCMR_MODE_OCREFTOG    (3)      /* 0011: OCxREF toggle ATIM_CNT=ATIM_CCRx */
+#define ATIM_CCMR_MODE_OCREFLO     (4)      /* 0100: OCxREF forced low */
+#define ATIM_CCMR_MODE_OCREFHI     (5)      /* 0101: OCxREF forced high */
+#define ATIM_CCMR_MODE_PWM1        (6)      /* 0110: PWM mode 1 */
+#define ATIM_CCMR_MODE_PWM2        (7)      /* 0111: PWM mode 2 */
+#define ATIM_CCMR_MODE_OPM1        (8)      /* 1000: Retrigerrable OPM mode 1 */
+#define ATIM_CCMR_MODE_OPM2        (9)      /* 1001: Retrigerrable OPM mode 2 */
+#define ATIM_CCMR_MODE_COMBINED1   (12)     /* 1100: Combined PWM mode 1 */
+#define ATIM_CCMR_MODE_COMBINED2   (13)     /* 1101: Combined PWM mode 2 */
+#define ATIM_CCMR_MODE_ASYMMETRIC1 (14)     /* 1110: Asymmetric PWM mode 1 */
+#define ATIM_CCMR_MODE_ASYMMETRIC2 (15)     /* 1111: Asymmetric PWM mode 2 */
+
+/* Capture/compare mode register 1 -- Input capture mode */
+
+                                            /* Bits 1-0:(same as output compare mode) */
+#define ATIM_CCMR1_IC1PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 1 Prescaler */
+#define ATIM_CCMR1_IC1PSC_MASK    (3 << ATIM_CCMR1_IC1PSC_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_IC1F_SHIFT     (4)       /* Bits 7-4: Input Capture 1 Filter */
+#define ATIM_CCMR1_IC1F_MASK      (0x0f << ATIM_CCMR1_IC1F_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+                                            /* Bits 9:8 (same as output compare mode) */
+#define ATIM_CCMR1_IC2PSC_SHIFT   (10)      /* Bits 11:10: Input Capture 2 Prescaler */
+#define ATIM_CCMR1_IC2PSC_MASK    (3 << ATIM_CCMR1_IC2PSC_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR1_IC2F_SHIFT     (12)      /* Bits 15-12: Input Capture 2 Filter */
+#define ATIM_CCMR1_IC2F_MASK      (0x0f << ATIM_CCMR1_IC2F_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+
+/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */
+
+#define ATIM_CCMR_ICPSC_NOPSC     (0)       /* 00: no prescaler, capture each edge */
+#define ATIM_CCMR_ICPSC_EVENTS2   (1)       /* 01: capture once every 2 events */
+#define ATIM_CCMR_ICPSC_EVENTS4   (2)       /* 10: capture once every 4 events */
+#define ATIM_CCMR_ICPSC_EVENTS8   (3)       /* 11: capture once every 8 events */
+
+/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */
+
+#define ATIM_CCMR_ICF_NOFILT      (0)       /* 0000: No filter, sampling at fDTS */
+#define ATIM_CCMR_ICF_FCKINT2     (1)       /* 0001: fSAMPLING=fCK_INT, N=2 */
+#define ATIM_CCMR_ICF_FCKINT4     (2)       /* 0010: fSAMPLING=fCK_INT, N=4 */
+#define ATIM_CCMR_ICF_FCKINT8     (3)       /* 0011: fSAMPLING=fCK_INT, N=8 */
+#define ATIM_CCMR_ICF_FDTSd26     (4)       /* 0100: fSAMPLING=fDTS/2, N=6 */
+#define ATIM_CCMR_ICF_FDTSd28     (5)       /* 0101: fSAMPLING=fDTS/2, N=8 */
+#define ATIM_CCMR_ICF_FDTSd46     (6)       /* 0110: fSAMPLING=fDTS/4, N=6 */
+#define ATIM_CCMR_ICF_FDTSd48     (7)       /* 0111: fSAMPLING=fDTS/4, N=8 */
+#define ATIM_CCMR_ICF_FDTSd86     (8)       /* 1000: fSAMPLING=fDTS/8, N=6 */
+#define ATIM_CCMR_ICF_FDTSd88     (9)       /* 1001: fSAMPLING=fDTS/8, N=8 */
+#define ATIM_CCMR_ICF_FDTSd165    (10)      /* 1010: fSAMPLING=fDTS/16, N=5 */
+#define ATIM_CCMR_ICF_FDTSd166    (11)      /* 1011: fSAMPLING=fDTS/16, N=6 */
+#define ATIM_CCMR_ICF_FDTSd168    (12)      /* 1100: fSAMPLING=fDTS/16, N=8 */
+#define ATIM_CCMR_ICF_FDTSd325    (13)      /* 1101: fSAMPLING=fDTS/32, N=5 */
+#define ATIM_CCMR_ICF_FDTSd326    (14)      /* 1110: fSAMPLING=fDTS/32, N=6 */
+#define ATIM_CCMR_ICF_FDTSd328    (15)      /* 1111: fSAMPLING=fDTS/32, N=8 */
+
+/* Capture/compare mode register 2 - Output Compare mode */
+
+#define ATIM_CCMR2_CC3S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 3 Selection */
+#define ATIM_CCMR2_CC3S_MASK      (3 << ATIM_CCMR2_CC3S_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC3FE          (1 << 2)  /* Bit 2: Output Compare 3 Fast enable */
+#define ATIM_CCMR2_OC3PE          (1 << 3)  /* Bit 3: Output Compare 3 Preload enable */
+#define ATIM_CCMR2_OC3M_SHIFT     (4)       /* Bits 6-4: Output Compare 3 Mode */
+#define ATIM_CCMR2_OC3M_MASK      (7 << ATIM_CCMR2_OC3M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC3CE          (1 << 7)  /* Bit 7: Output Compare 3 Clear Enable */
+#define ATIM_CCMR2_CC4S_SHIFT     (8)       /* Bits 9-8: Capture/Compare 4 Selection */
+#define ATIM_CCMR2_CC4S_MASK      (3 << ATIM_CCMR2_CC4S_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC4FE          (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
+#define ATIM_CCMR2_OC4PE          (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
+#define ATIM_CCMR2_OC4M_SHIFT     (12)      /* Bits 14-12: Output Compare 4 Mode */
+#define ATIM_CCMR2_OC4M_MASK      (7 << ATIM_CCMR2_OC4M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_OC4CE          (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
+#define ATIM_CCMR2_OC3M           (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */
+#define ATIM_CCMR2_OC4M           (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */
+
+/* Capture/compare mode register 2 - Input Capture Mode */
+
+                                            /* Bits 1-0:(same as output compare mode) */
+#define ATIM_CCMR2_IC3PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 3 Prescaler */
+#define ATIM_CCMR1_IC3PSC_MASK    (3 << ATIM_CCMR2_IC3PSC_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_IC3F_SHIFT     (4)       /* Bits 7-4: Input Capture 3 Filter */
+#define ATIM_CCMR2_IC3F_MASK      (0x0f << ATIM_CCMR2_IC3F_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+                                            /* Bits 9:8 (same as output compare mode) */
+#define ATIM_CCMR2_IC4PSC_SHIFT   (10)      /* Bits 11:10: Input Capture 4 Prescaler */
+#define ATIM_CCMR2_IC4PSC_MASK    (3 << ATIM_CCMR2_IC4PSC_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+#define ATIM_CCMR2_IC4F_SHIFT     (12)      /* Bits 15-12: Input Capture 4 Filter */
+#define ATIM_CCMR2_IC4F_MASK      (0x0f << ATIM_CCMR2_IC4F_SHIFT)
+                                            /* (See common (unshifted) bit field definitions above) */
+
+/* Capture/compare mode register 3 -- Output compare mode */
+
+#define ATIM_CCMR3_OC5FE          (1 << 2)  /* Bit 2: Output Compare 5 Fast enable */
+#define ATIM_CCMR3_OC5PE          (1 << 3)  /* Bit 3: Output Compare 5 Preload enable */
+#define ATIM_CCMR3_OC5M_SHIFT     (4)       /* Bits 6-4: Output Compare 5 Mode */
+#define ATIM_CCMR3_OC5M_MASK      (7 << ATIM_CCMR3_OC5M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR3_OC5CE          (1 << 7)  /* Bit 7: Output Compare 5 Clear Enable */
+#define ATIM_CCMR3_OC6FE          (1 << 10) /* Bit 10: Output Compare 6 Fast enable */
+#define ATIM_CCMR3_OC6PE          (1 << 11) /* Bit 11: Output Compare 6 Preload enable */
+#define ATIM_CCMR3_OC6M_SHIFT     (12)      /* Bits 14-12: Output Compare 7 Mode */
+#define ATIM_CCMR3_OC6M_MASK      (7 << ATIM_CCMR3_OC6M_SHIFT)
+                                            /* (See common (unshifted) bit field definitions below) */
+#define ATIM_CCMR3_OC6CE          (1 << 15) /* Bit 15: Output Compare 7 Clear Enable */
+#define ATIM_CCMR3_OC5M           (1 << 16) /* Bit 16: Output Compare 5 mode - bit 3 */
+#define ATIM_CCMR3_OC6M           (1 << 24) /* Bit 24: Output Compare 6 mode - bit 3 */
+
+/* Capture/compare enable register */
+
+#define ATIM_CCER_CC1E            (1 << 0)  /* Bit 0: Capture/Compare 1 output enable */
+#define ATIM_CCER_CC1P            (1 << 1)  /* Bit 1: Capture/Compare 1 output Polarity */
+#define ATIM_CCER_CC1NE           (1 << 2)  /* Bit 2: Capture/Compare 1 Complementary output enable */
+#define ATIM_CCER_CC1NP           (1 << 3)  /* Bit 3: Capture/Compare 1 Complementary output polarity */
+#define ATIM_CCER_CC2E            (1 << 4)  /* Bit 4: Capture/Compare 2 output enable */
+#define ATIM_CCER_CC2P            (1 << 5)  /* Bit 5: Capture/Compare 2 output Polarity */
+#define ATIM_CCER_CC2NE           (1 << 6)  /* Bit 6: Capture/Compare 2 Complementary output enable */
+#define ATIM_CCER_CC2NP           (1 << 7)  /* Bit 7: Capture/Compare 2 Complementary output polarity */
+#define ATIM_CCER_CC3E            (1 << 8)  /* Bit 8: Capture/Compare 3 output enable */
+#define ATIM_CCER_CC3P            (1 << 9)  /* Bit 9: Capture/Compare 3 output Polarity */
+#define ATIM_CCER_CC3NE           (1 << 10) /* Bit 10: Capture/Compare 3 Complementary output enable */
+#define ATIM_CCER_CC3NP           (1 << 11) /* Bit 11: Capture/Compare 3 Complementary output polarity */
+#define ATIM_CCER_CC4E            (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
+#define ATIM_CCER_CC4P            (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity */
+#define ATIM_CCER_CC4NP           (1 << 15) /* Bit 15: Capture/Compare 4 Complementary output polarity */
+#define ATIM_CCER_CC5E            (1 << 16) /* Bit 16: Capture/Compare 5 output enable */
+#define ATIM_CCER_CC5P            (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */
+#define ATIM_CCER_CC6E            (1 << 20) /* Bit 20: Capture/Compare 6 output enable */
+#define ATIM_CCER_CC6P            (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */
+
+/* 16-bit counter register */
+
+#define ATIM_CNT_SHIFT            (0)       /* Bits 0-15: Timer counter value */
+#define ATIM_CNT_MASK             (0xffff << ATIM_CNT_SHIFT)
+
+/* Repetition counter register */
+
+#define ATIM_RCR_REP_SHIFT        (0)       /* Bits 0-15: Repetition Counter Value */
+#define ATIM_RCR_REP_MASK         (0xffff << ATIM_RCR_REP_SHIFT)
+
+#define ATIM_RCR_REP_MAX          65536
+
+/* Capture/compare registers (CCR) */
+
+#define ATIM_CCR5_GC5C1           (1 << 29)  /* Bit 29: Group Channel 5 and Channel 1 */
+#define ATIM_CCR5_GC5C2           (1 << 30)  /* Bit 30: Group Channel 5 and Channel 2 */
+#define ATIM_CCR5_GC5C3           (1 << 31)  /* Bit 31: Group Channel 5 and Channel 3 */
+
+#define ATIM_CCR_MASK             (0xffff)
+
+/* Alternate function option register 1 (TIMx_AF1) */
+
+#define ATIM_AF1_BKINE            (1 << 0)  /* Bit 0: BRK BKIN input enable */
+#define ATIM_AF1_BKDFBKE          (1 << 8)  /* Bit 8: BRK DFSDM_BREAK[0] enable */
+#define ATIM_AF1_BKINP            (1 << 9)  /* Bit 9: BRK BKIN input polarity */
+
+/* Alternate function option register 2 (TIMx_AF2) */
+
+#define ATIM_AF1_BK2INE           (1 << 0)  /* Bit 0: BRK2 BKIN input enable */
+#define ATIM_AF1_BK2DFBKE         (1 << 8)  /* Bit 8: BRK2 DFSDM_BREAK enable */
+#define ATIM_AF1_BK2INP           (1 << 9)  /* Bit 9: BRK2 BKIN2 input polarity */
+
+/* Break and dead-time register */
+
+#define ATIM_BDTR_DTG_SHIFT       (0)       /* Bits 7:0 [7:0]: Dead-Time Generator set-up */
+#define ATIM_BDTR_DTG_MASK        (0xff << ATIM_BDTR_DTG_SHIFT)
+#define ATIM_BDTR_LOCK_SHIFT      (8)       /* Bits 9:8 [1:0]: Lock Configuration */
+#define ATIM_BDTR_LOCK_MASK       (3 << ATIM_BDTR_LOCK_SHIFT)
+#  define ATIM_BDTR_LOCKOFF       (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
+#  define ATIM_BDTR_LOCK1         (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
+#  define ATIM_BDTR_LOCK2         (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
+#  define ATIM_BDTR_LOCK3         (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
+#define ATIM_BDTR_OSSI            (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
+#define ATIM_BDTR_OSSR            (1 << 11) /* Bit 11: Off-State Selection for Run mode */
+#define ATIM_BDTR_BKE             (1 << 12) /* Bit 12: Break enable */
+#define ATIM_BDTR_BKP             (1 << 13) /* Bit 13: Break Polarity */
+#define ATIM_BDTR_AOE             (1 << 14) /* Bit 14: Automatic Output enable */
+#define ATIM_BDTR_MOE             (1 << 15) /* Bit 15: Main Output enable */
+#define ATIM_BDTR_BKF_SHIFT       (16)      /* Bits 16-19: Break filter */
+#define ATIM_BDTR_BKF_MASK        (0xf << ATIM_BDTR_BKF_SHIFT)
+#  define ATIM_BDTR_BKF_NOFILT    (0 << ATIM_BDTR_BKF_SHIFT)   /* 0000: No filter, BRK acts asynchronously */
+#  define ATIM_BDTR_BKF_FCKINT2   (1 << ATIM_BDTR_BKF_SHIFT)   /* 0001: fSAMPLING=fCK_INT, N=2 */
+#  define ATIM_BDTR_BKF_FCKINT4   (2 << ATIM_BDTR_BKF_SHIFT)   /* 0010: fSAMPLING=fCK_INT, N=4 */
+#  define ATIM_BDTR_BKF_FCKINT8   (3 << ATIM_BDTR_BKF_SHIFT)   /* 0011: fSAMPLING=fCK_INT, N=8 */
+#  define ATIM_BDTR_BKF_FDTSd26   (4 << ATIM_BDTR_BKF_SHIFT)   /* 0100: fSAMPLING=fDTS/2, N=6 */
+#  define ATIM_BDTR_BKF_FDTSd28   (5 << ATIM_BDTR_BKF_SHIFT)   /* 0101: fSAMPLING=fDTS/2, N=8 */
+#  define ATIM_BDTR_BKF_FDTSd36   (6 << ATIM_BDTR_BKF_SHIFT)   /* 0110: fSAMPLING=fDTS/4, N=6 */
+#  define ATIM_BDTR_BKF_FDTSd38   (7 << ATIM_BDTR_BKF_SHIFT)   /* 0111: fSAMPLING=fDTS/4, N=8 */
+#  define ATIM_BDTR_BKF_FDTSd86   (8 << ATIM_BDTR_BKF_SHIFT)   /* 1000: fSAMPLING=fDTS/8, N=6 */
+#  define ATIM_BDTR_BKF_FDTSd88   (9 << ATIM_BDTR_BKF_SHIFT)   /* 1001: fSAMPLING=fDTS/8, N=8 */
+#  define ATIM_BDTR_BKF_FDTSd165  (10 << ATIM_BDTR_BKF_SHIFT)  /* 1010: fSAMPLING=fDTS/16, N=5 */
+#  define ATIM_BDTR_BKF_FDTSd166  (11 << ATIM_BDTR_BKF_SHIFT)  /* 1011: fSAMPLING=fDTS/16, N=6 */
+#  define ATIM_BDTR_BKF_FDTSd168  (12 << ATIM_BDTR_BKF_SHIFT)  /* 1100: fSAMPLING=fDTS/16, N=8 */
+#  define ATIM_BDTR_BKF_FDTSd325  (13 << ATIM_BDTR_BKF_SHIFT)  /* 1101: fSAMPLING=fDTS/32, N=5 */
+#  define ATIM_BDTR_BKF_FDTSd326  (14 << ATIM_BDTR_BKF_SHIFT)  /* 1110: fSAMPLING=fDTS/32, N=6 */
+#  define ATIM_BDTR_BKF_FDTSd328  (15 << ATIM_BDTR_BKF_SHIFT)  /* 1111: fSAMPLING=fDTS/32, N=8 */
+#define ATIM_BDTR_BK2F_SHIFT      (20)      /* Bits 20-23: Break 2 filter */
+#define ATIM_BDTR_BK2F_MASK       (0xf << ATIM_BDTR_BK2F_SHIFT)
+#  define ATIM_BDTR_BK2F_NOFILT   (0 << ATIM_BDTR_BK2F_SHIFT)  /* 0000: No filter, BRK 2 acts asynchronously */
+#  define ATIM_BDTR_BK2F_FCKINT2  (1 << ATIM_BDTR_BK2F_SHIFT)  /* 0001: fSAMPLING=fCK_INT, N=2 */
+#  define ATIM_BDTR_BK2F_FCKINT4  (2 << ATIM_BDTR_BK2F_SHIFT)  /* 0010: fSAMPLING=fCK_INT, N=4 */
+#  define ATIM_BDTR_BK2F_FCKINT8  (3 << ATIM_BDTR_BK2F_SHIFT)  /* 0011: fSAMPLING=fCK_INT, N=8 */
+#  define ATIM_BDTR_BK2F_FDTSd26  (4 << ATIM_BDTR_BK2F_SHIFT)  /* 0100: fSAMPLING=fDTS/2, N=6 */
+#  define ATIM_BDTR_BK2F_FDTSd28  (5 << ATIM_BDTR_BK2F_SHIFT)  /* 0101: fSAMPLING=fDTS/2, N=8 */
+#  define ATIM_BDTR_BK2F_FDTSd36  (6 << ATIM_BDTR_BK2F_SHIFT)  /* 0110: fSAMPLING=fDTS/4, N=6 */
+#  define ATIM_BDTR_BK2F_FDTSd38  (7 << ATIM_BDTR_BK2F_SHIFT)  /* 0111: fSAMPLING=fDTS/4, N=8 */
+#  define ATIM_BDTR_BK2F_FDTSd86  (8 << ATIM_BDTR_BK2F_SHIFT)  /* 1000: fSAMPLING=fDTS/8, N=6 */
+#  define ATIM_BDTR_BK2F_FDTSd88  (9 << ATIM_BDTR_BK2F_SHIFT)  /* 1001: fSAMPLING=fDTS/8, N=8 */
+#  define ATIM_BDTR_BK2F_FDTSd165 (10 << ATIM_BDTR_BK2F_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
+#  define ATIM_BDTR_BK2F_FDTSd166 (11 << ATIM_BDTR_BK2F_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
+#  define ATIM_BDTR_BK2F_FDTSd168 (12 << ATIM_BDTR_BK2F_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
+#  define ATIM_BDTR_BK2F_FDTSd325 (13 << ATIM_BDTR_BK2F_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
+#  define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
+#  define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
+#define ATIM_BDTR_BK2E            (1 << 24) /* Bit 24: Break 2 enable */
+#define ATIM_BDTR_BK2P            (1 << 1525 /* Bit 25:Break 2 polarity */
+
+/* DMA control register */
+
+#define ATIM_DCR_DBA_SHIFT        (0)       /* Bits 4-0: DMA Base Address */
+#define ATIM_DCR_DBA_MASK         (0x1f << ATIM_DCR_DBA_SHIFT)
+#define ATIM_DCR_DBL_SHIFT        (8)       /* Bits 12-8: DMA Burst Length */
+#define ATIM_DCR_DBL_MASK         (0x1f << ATIM_DCR_DBL_SHIFT)
+#  define ATIM_DCR_DBL(n)         (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */
+
+/* Control register 1 (TIM2-5 and TIM9-14) */
+
+#define GTIM_CR1_CEN              (1 << 0)  /* Bit 0: Counter enable */
+#define GTIM_CR1_UDIS             (1 << 1)  /* Bit 1: Update Disable */
+#define GTIM_CR1_URS              (1 << 2)  /* Bit 2: Update Request Source */
+#define GTIM_CR1_OPM              (1 << 3)  /* Bit 3: One Pulse Mode (TIM2-5, 9, and 12 only) */
+#define GTIM_CR1_DIR              (1 << 4)  /* Bit 4: Direction (TIM2-5 only) */
+#define GTIM_CR1_CMS_SHIFT        (5)       /* Bits 6-5: Center-aligned Mode Selection (TIM2-5 only) */
+#define GTIM_CR1_CMS_MASK         (3 << GTIM_CR1_CMS_SHIFT)
+#  define GTIM_CR1_EDGE           (0 << GTIM_CR1_CMS_SHIFT) /* 00: Edge-aligned mode.  */
+#  define GTIM_CR1_CENTER1        (1 << GTIM_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
+#  define GTIM_CR1_CENTER2        (2 << GTIM_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
+#  define GTIM_CR1_CENTER3        (3 << GTIM_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
+#define GTIM_CR1_ARPE             (1 << 7)  /* Bit 7: Auto-Reload Preload enable */
+#define GTIM_CR1_CKD_SHIFT        (8)       /* Bits 9-8: Clock Division */
+#define GTIM_CR1_CKD_MASK         (3 << GTIM_CR1_CKD_SHIFT)
+#  define GTIM_CR1_TCKINT         (0 << GTIM_CR1_CKD_SHIFT) /* 00: tDTS = tCK_INT */
+#  define GTIM_CR1_2TCKINT        (1 << GTIM_CR1_CKD_SHIFT) /* 01: tDTS = 2 x tCK_INT */
+#  define GTIM_CR1_4TCKINT        (2 << GTIM_CR1_CKD_SHIFT) /* 10: tDTS = 4 x tCK_INT */
+#define GTIM_CR1_UIFREMAP         (1 << 11) /* Bit 11: UIF status bit remapping */
+
+/* Control register 2 (TIM2-5, TIM9-12) */
+
+#define GTIM_CR2_CCPC             (1 << 0)  /* Bit 0: Capture/compare preloaded control (TIM15-17 only) */
+#define GTIM_CR2_CCUS             (1 << 2)  /* Bit 2: Capture/compare control update selection (TIM15-17 only) */
+#define GTIM_CR2_CCDS             (1 << 3)  /* Bit 3: Capture/Compare DMA Selection (TIM2-5,1,&16 only) */
+#define GTIM_CR2_MMS_SHIFT        (4)       /* Bits 6-4: Master Mode Selection (not TIM16) */
+#define GTIM_CR2_MMS_MASK         (7 << GTIM_CR2_MMS_SHIFT)
+#  define GTIM_CR2_MMS_RESET      (0 << GTIM_CR2_MMS_SHIFT) /* 000: Reset */
+#  define GTIM_CR2_MMS_ENABLE     (1 << GTIM_CR2_MMS_SHIFT) /* 001: Enable */
+#  define GTIM_CR2_MMS_UPDATE     (2 << GTIM_CR2_MMS_SHIFT) /* 010: Update */
+#  define GTIM_CR2_MMS_COMPP      (3 << GTIM_CR2_MMS_SHIFT) /* 011: Compare Pulse */
+#  define GTIM_CR2_MMS_OC1REF     (4 << GTIM_CR2_MMS_SHIFT) /* 100: Compare - OC1REF signal is used as trigger output (TRGO) */
+#  define GTIM_CR2_MMS_OC2REF     (5 << GTIM_CR2_MMS_SHIFT) /* 101: Compare - OC2REF signal is used as trigger output (TRGO) */
+#  define GTIM_CR2_MMS_OC3REF     (6 << GTIM_CR2_MMS_SHIFT) /* 110: Compare - OC3REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */
+#  define GTIM_CR2_MMS_OC4REF     (7 << GTIM_CR2_MMS_SHIFT) /* 111: Compare - OC4REF signal is used as trigger output (TRGO, TIM2-5 and TIM15 only) */
+#define GTIM_CR2_TI1S             (1 << 7)  /* Bit 7: TI1 Selection (not TIM16) */
+#define GTIM_CR2_OIS1             (1 << 8)  /* Bit 8: COutput Idle state 1 (OC1 output) (TIM15-17 only) */
+#define GTIM_CR2_OIS1N            (1 << 9)  /* Bit 9: Output Idle state 1 (OC1N output) (TIM15-17 only) */
+#define GTIM_CR2_OIS2             (1 << 10) /* Bit 10: Output idle state 2 (OC2 output) (TIM15 only) */
+
+/* Slave mode control register (TIM2-5) */
+
+#define GTIM_SMCR_SMS_SHIFT       (0)       /* Bits 2-0: Slave Mode Selection */
+#define GTIM_SMCR_SMS_MASK        (7 << GTIM_SMCR_SMS_SHIFT)
+#  define GTIM_SMCR_DISAB         (0 << GTIM_SMCR_SMS_SHIFT) /* 000: Slave mode disabled */
+#  define GTIM_SMCR_ENCMD1        (1 << GTIM_SMCR_SMS_SHIFT) /* 001: Encoder mode 1 */
+#  define GTIM_SMCR_ENCMD2        (2 << GTIM_SMCR_SMS_SHIFT) /* 010: Encoder mode 2 */
+#  define GTIM_SMCR_ENCMD3        (3 << GTIM_SMCR_SMS_SHIFT) /* 011: Encoder mode 3 */
+#  define GTIM_SMCR_RESET         (4 << GTIM_SMCR_SMS_SHIFT) /* 100: Reset Mode  */
+#  define GTIM_SMCR_GATED         (5 << GTIM_SMCR_SMS_SHIFT) /* 101: Gated Mode  */
+#  define GTIM_SMCR_TRIGGER       (6 << GTIM_SMCR_SMS_SHIFT) /* 110: Trigger Mode */
+#  define GTIM_SMCR_EXTCLK1       (7 << GTIM_SMCR_SMS_SHIFT) /* 111: External Clock Mode 1 */
+#define GTIM_SMCR_TS_SHIFT        (4)       /* Bits 6-4: Trigger Selection */
+#define GTIM_SMCR_TS_MASK         (7 << GTIM_SMCR_TS_SHIFT)
+#  define GTIM_SMCR_ITR0          (0 << GTIM_SMCR_TS_SHIFT) /* 000: Internal Trigger 0 (ITR0). TIM1 */
+#  define GTIM_SMCR_ITR1          (1 << GTIM_SMCR_TS_SHIFT) /* 001: Internal Trigger 1 (ITR1). TIM2 */
+#  define GTIM_SMCR_ITR2          (2 << GTIM_SMCR_TS_SHIFT) /* 010: Internal Trigger 2 (ITR2). TIM3 */
+#  define GTIM_SMCR_ITR3          (3 << GTIM_SMCR_TS_SHIFT) /* 011: Internal Trigger 3 (ITR3). TIM4 */
+#  define GTIM_SMCR_TI1FED        (4 << GTIM_SMCR_TS_SHIFT) /* 100: TI1 Edge Detector (TI1F_ED) */
+#  define GTIM_SMCR_TI1FP1        (5 << GTIM_SMCR_TS_SHIFT) /* 101: Filtered Timer Input 1 (TI1FP1) */
+#  define GTIM_SMCR_TI2FP2        (6 << GTIM_SMCR_TS_SHIFT) /* 110: Filtered Timer Input 2 (TI2FP2) */
+#  define GTIM_SMCR_ETRF          (7 << GTIM_SMCR_TS_SHIFT) /* 111: External Trigger input (ETRF) */
+#define GTIM_SMCR_MSM             (1 << 7)  /* Bit 7: Master/Slave mode */
+#define GTIM_SMCR_ETF_SHIFT       (8)       /* Bits 11-8: External Trigger Filter (not TIM15) */
+#define GTIM_SMCR_ETF_MASK        (0x0f << GTIM_SMCR_ETF_SHIFT)
+#  define GTIM_SMCR_NOFILT        (0 << GTIM_SMCR_ETF_SHIFT)  /* 0000: No filter, sampling is done at fDTS */
+#  define GTIM_SMCR_FCKINT2       (1 << GTIM_SMCR_ETF_SHIFT)  /* 0001: fSAMPLING=fCK_INT, N=2 */
+#  define GTIM_SMCR_FCKINT4       (2 << GTIM_SMCR_ETF_SHIFT)  /* 0010: fSAMPLING=fCK_INT, N=4 */
+#  define GTIM_SMCR_FCKINT8       (3 << GTIM_SMCR_ETF_SHIFT)  /* 0011: fSAMPLING=fCK_INT, N=8 */
+#  define GTIM_SMCR_FDTSd26       (4 << GTIM_SMCR_ETF_SHIFT)  /* 0100: fSAMPLING=fDTS/2, N=6 */
+#  define GTIM_SMCR_FDTSd28       (5 << GTIM_SMCR_ETF_SHIFT)  /* 0101: fSAMPLING=fDTS/2, N=8 */
+#  define GTIM_SMCR_FDTSd36       (6 << GTIM_SMCR_ETF_SHIFT)  /* 0110: fSAMPLING=fDTS/4, N=6 */
+#  define GTIM_SMCR_FDTSd38       (7 << GTIM_SMCR_ETF_SHIFT)  /* 0111: fSAMPLING=fDTS/4, N=8 */
+#  define GTIM_SMCR_FDTSd86       (8 << GTIM_SMCR_ETF_SHIFT)  /* 1000: fSAMPLING=fDTS/8, N=6 */
+#  define GTIM_SMCR_FDTSd88       (9 << GTIM_SMCR_ETF_SHIFT)  /* 1001: fSAMPLING=fDTS/8, N=8 */
+#  define GTIM_SMCR_FDTSd165      (10 << GTIM_SMCR_ETF_SHIFT) /* 1010: fSAMPLING=fDTS/16, N=5 */
+#  define GTIM_SMCR_FDTSd166      (11 << GTIM_SMCR_ETF_SHIFT) /* 1011: fSAMPLING=fDTS/16, N=6 */
+#  define GTIM_SMCR_FDTSd168      (12 << GTIM_SMCR_ETF_SHIFT) /* 1100: fSAMPLING=fDTS/16, N=8 */
+#  define GTIM_SMCR_FDTSd325      (13 << GTIM_SMCR_ETF_SHIFT) /* 1101: fSAMPLING=fDTS/32, N=5 */
+#  define GTIM_SMCR_FDTSd326      (14 << GTIM_SMCR_ETF_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
+#  define GTIM_SMCR_FDTSd328      (15 << GTIM_SMCR_ETF_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
+#define GTIM_SMCR_ETPS_SHIFT      (12)      /* Bits 13-12: External Trigger Prescaler (not TIM15) */
+#define GTIM_SMCR_ETPS_MASK       (3 << GTIM_SMCR_ETPS_SHIFT)
+#  define GTIM_SMCR_PSCOFF        (0 << GTIM_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
+#  define GTIM_SMCR_ETRPd2        (1 << GTIM_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
+#  define GTIM_SMCR_ETRPd4        (2 << GTIM_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
+#  define GTIM_SMCR_ETRPd8        (3 << GTIM_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
+#define GTIM_SMCR_ECE             (1 << 14) /* Bit 14: External Clock enable */
+#define GTIM_SMCR_ETP             (1 << 15) /* Bit 15: External Trigger Polarity */
+#define GTIM_SMCR_SMS             (1 << 16) /* Bit 16: Slave mode selection - bit 3 */
+
+/* DMA/Interrupt enable register (TIM2-5 and TIM9-14) */
+
+#define GTIM_DIER_UIE             (1 << 0)  /* Bit 0: Update interrupt enable */
+#define GTIM_DIER_CC1IE           (1 << 1)  /* Bit 1: Capture/Compare 1 interrupt enable */
+#define GTIM_DIER_CC2IE           (1 << 2)  /* Bit 2: Capture/Compare 2 interrupt enable (TIM2-5,9,12,&15 only) */
+#define GTIM_DIER_CC3IE           (1 << 3)  /* Bit 3: Capture/Compare 3 interrupt enable (TIM2-5 only) */
+#define GTIM_DIER_CC4IE           (1 << 4)  /* Bit 4: Capture/Compare 4 interrupt enable (TIM2-5 only) */
+#define GTIM_DIER_COMIE           (1 << 5)  /* Bit 5: COM interrupt enable (TIM15-17 only) */
+#define GTIM_DIER_TIE             (1 << 6)  /* Bit 6: Trigger interrupt enable (TIM2-5,9,&12 only) */
+#define GTIM_DIER_BIE             (1 << 7)  /* Bit 7: Break interrupt enable (TIM15-17 only) */
+#define GTIM_DIER_UDE             (1 << 8)  /* Bit 8: Update DMA request enable (TIM2-5&15-17 only) */
+#define GTIM_DIER_CC1DE           (1 << 9)  /* Bit 9: Capture/Compare 1 DMA request enable (TIM2-5&15-17 only) */
+#define GTIM_DIER_CC2DE           (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable (TIM2-5&15 only) */
+#define GTIM_DIER_CC3DE           (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable (TIM2-5 only) */
+#define GTIM_DIER_CC4DE           (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable (TIM2-5 only) */
+#define GTIM_DIER_COMDE           (1 << 13) /* Bit 13: COM DMA request enable (TIM15-17 only) */
+#define GTIM_DIER_TDE             (1 << 14) /* Bit 14: Trigger DMA request enable (TIM2-5&15-17 only) */
+
+/* Status register */
+
+#define GTIM_SR_UIF               (1 << 0)  /* Bit 0: Update interrupt flag */
+#define GTIM_SR_CC1IF             (1 << 1)  /* Bit 1: Capture/compare 1 interrupt flag */
+#define GTIM_SR_CC2IF             (1 << 2)  /* Bit 2: Capture/Compare 2 interrupt flag (TIM2-5,9,12,&15 only) */
+#define GTIM_SR_CC3IF             (1 << 3)  /* Bit 3: Capture/Compare 3 interrupt flag (TIM2-5 only) */
+#define GTIM_SR_CC4IF             (1 << 4)  /* Bit 4: Capture/Compare 4 interrupt flag (TIM2-5 only) */
+#define GTIM_SR_COMIF             (1 << 5)  /* Bit 5: COM interrupt flag (TIM15-17 only) */
+#define GTIM_SR_TIF               (1 << 6)  /* Bit 6: Trigger interrupt Flag (TIM2-5,9,12&15-17 only) */
+#define GTIM_SR_BIF               (1 << 7)  /* Bit 7: Break interrupt flag (TIM15-17 only) */
+#define GTIM_SR_CC1OF             (1 << 9)  /* Bit 9: Capture/Compare 1 Overcapture flag */
+#define GTIM_SR_CC2OF             (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture flag (TIM2-5,9,12&15 only) */
+#define GTIM_SR_CC3OF             (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture flag (TIM2-5 only) */
+#define GTIM_SR_CC4OF             (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture flag (TIM2-5 only) */
+
+/* Event generation register (TIM2-5 and TIM9-14) */
+
+#define GTIM_EGR_UG               (1 << 0)  /* Bit 0: Update generation */
+#define GTIM_EGR_CC1G             (1 << 1)  /* Bit 1: Capture/compare 1 generation */
+#define GTIM_EGR_CC2G             (1 << 2)  /* Bit 2: Capture/compare 2 generation (TIM2-5,9,12,&15 only) */
+#define GTIM_EGR_CC3G             (1 << 3)  /* Bit 3: Capture/compare 3 generation (TIM2-5 only) */
+#define GTIM_EGR_CC4G             (1 << 4)  /* Bit 4: Capture/compare 4 generation (TIM2-5 only) */
+#define GTIM_EGR_COMIG            (1 << 5)  /* Bit 5: Capture/Compare control update generation (TIM15-17 only) */
+#define GTIM_EGR_TG               (1 << 6)  /* Bit 6: Trigger generation (TIM2-5,9,12&16-17 only) */
+#define GTIM_EGR_BG               (1 << 7)  /* Bit 7: Break generation (TIM15-17 only) */
+
+/* Capture/compare mode register 1 - Output compare mode (TIM2-5 and TIM9-14) */
+
+#define GTIM_CCMR1_CC1S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 1 Selection */
+#define GTIM_CCMR1_CC1S_MASK      (3 << GTIM_CCMR1_CC1S_SHIFT)
+                                            /* (See common CCMR Capture/Compare Selection definitions below) */
+#define GTIM_CCMR1_OC1FE          (1 << 2)  /* Bit 2: Output Compare 1 Fast enable */
+#define GTIM_CCMR1_OC1PE          (1 << 3)  /* Bit 3: Output Compare 1 Preload enable */
+#define GTIM_CCMR1_OC1M_SHIFT     (4)       /* Bits 6-4: Output Compare 1 Mode */
+#define GTIM_CCMR1_OC1M_MASK      (7 << GTIM_CCMR1_OC1M_SHIFT)
+                                            /* (See common CCMR Output Compare Mode definitions below) */
+#define GTIM_CCMR1_OC1CE          (1 << 7)  /* Bit 7: Output Compare 1Clear Enable */
+#define GTIM_CCMR1_CC2S_SHIFT     (8)       /* Bits 9-8: Capture/Compare 2 Selection */
+#define GTIM_CCMR1_CC2S_MASK      (3 << GTIM_CCMR1_CC2S_SHIFT)
+                                            /* (See common CCMR Capture/Compare Selection definitions below) */
+#define GTIM_CCMR1_OC2FE          (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
+#define GTIM_CCMR1_OC2PE          (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
+#define GTIM_CCMR1_OC2M_SHIFT     (12)      /* Bits 14-12: Output Compare 2 Mode */
+#define GTIM_CCMR1_OC2M_MASK      (7 << GTIM_CCMR1_OC2M_SHIFT)
+                                            /* (See common CCMR Output Compare Mode definitions below) */
+#define GTIM_CCMR1_OC2CE          (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
+#define GTIM_CCMR1_OC1M           (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */
+#define GTIM_CCMR1_OC2M           (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */
+
+/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
+
+#define GTIM_CCMR_CCS_CCOUT       (0)       /* 00: CCx channel output */
+#define GTIM_CCMR_CCS_CCIN1       (1)       /* 01: CCx channel input, ICx is TIx */
+#define GTIM_CCMR_CCS_CCIN2       (2)       /* 10: CCx channel input, ICx is TIy */
+#define GTIM_CCMR_CCS_CCINTRC     (3)       /* 11: CCx channel input, ICx is TRC */
+
+/* Common CCMR (unshifted) Compare Mode bit field definitions */
+
+#define GTIM_CCMR_MODE_FRZN       (0)       /* 000: Frozen */
+#define GTIM_CCMR_MODE_CHACT      (1)       /* 001: Channel x active on match */
+#define GTIM_CCMR_MODE_CHINACT    (2)       /* 010: Channel x inactive on match */
+#define GTIM_CCMR_MODE_OCREFTOG   (3)       /* 011: OCxREF toggle ATIM_CNT=ATIM_CCRx */
+#define GTIM_CCMR_MODE_OCREFLO    (4)       /* 100: OCxREF forced low */
+#define GTIM_CCMR_MODE_OCREFHI    (5)       /* 101: OCxREF forced high */
+#define GTIM_CCMR_MODE_PWM1       (6)       /* 110: PWM mode 1 */
+#define GTIM_CCMR_MODE_PWM2       (7)       /* 111: PWM mode 2 */
+
+/* Capture/compare mode register 1 - Input capture mode (TIM2-5 and TIM9-14) */
+
+                                            /* Bits 1-0 (Same as Output Compare Mode) */
+#define GTIM_CCMR1_IC1PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 1 Prescaler */
+#define GTIM_CCMR1_IC1PSC_MASK    (3 << GTIM_CCMR1_IC1PSC_SHIFT)
+                                            /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR1_IC1F_SHIFT     (4)       /* Bits 7-4: Input Capture 1 Filter */
+#define GTIM_CCMR1_IC1F_MASK      (0x0f << GTIM_CCMR1_IC1F_SHIFT)
+                                            /* (See common CCMR Input Capture Filter definitions below) */
+                                            /* Bits 9-8: (Same as Output Compare Mode) */
+#define GTIM_CCMR1_IC2PSC_SHIFT   (10)      /* Bits 11-10: Input Capture 2 Prescaler */
+#define GTIM_CCMR1_IC2PSC_MASK    (3 << GTIM_CCMR1_IC2PSC_SHIFT)
+                                            /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR1_IC2F_SHIFT     (12)      /* Bits 15-12: Input Capture 2 Filter */
+#define GTIM_CCMR1_IC2F_MASK      (0x0f << GTIM_CCMR1_IC2F_SHIFT)
+                                            /* (See common CCMR Input Capture Filter definitions below) */
+
+/* Common CCMR (unshifted) Input Capture Prescaler bit-field definitions */
+
+#define GTIM_CCMR_ICPSC_NOPSC     (0)       /* 00: no prescaler, capture each edge */
+#define GTIM_CCMR_ICPSC_EVENTS2   (1)       /* 01: capture once every 2 events */
+#define GTIM_CCMR_ICPSC_EVENTS4   (2)       /* 10: capture once every 4 events */
+#define GTIM_CCMR_ICPSC_EVENTS8   (3)       /* 11: capture once every 8 events */
+
+/* Common CCMR (unshifted) Input Capture Filter bit-field definitions */
+
+#define GTIM_CCMR_ICF_NOFILT      (0)       /* 0000: No filter, sampling at fDTS */
+#define GTIM_CCMR_ICF_FCKINT2     (1)       /* 0001: fSAMPLING=fCK_INT, N=2 */
+#define GTIM_CCMR_ICF_FCKINT4     (2)       /* 0010: fSAMPLING=fCK_INT, N=4 */
+#define GTIM_CCMR_ICF_FCKINT8     (3)       /* 0011: fSAMPLING=fCK_INT, N=8 */
+#define GTIM_CCMR_ICF_FDTSd26     (4)       /* 0100: fSAMPLING=fDTS/2, N=6 */
+#define GTIM_CCMR_ICF_FDTSd28     (5)       /* 0101: fSAMPLING=fDTS/2, N=8 */
+#define GTIM_CCMR_ICF_FDTSd46     (6)       /* 0110: fSAMPLING=fDTS/4, N=6 */
+#define GTIM_CCMR_ICF_FDTSd48     (7)       /* 0111: fSAMPLING=fDTS/4, N=8 */
+#define GTIM_CCMR_ICF_FDTSd86     (8)       /* 1000: fSAMPLING=fDTS/8, N=6 */
+#define GTIM_CCMR_ICF_FDTSd88     (9)       /* 1001: fSAMPLING=fDTS/8, N=8 */
+#define GTIM_CCMR_ICF_FDTSd165    (10)      /* 1010: fSAMPLING=fDTS/16, N=5 */
+#define GTIM_CCMR_ICF_FDTSd166    (11)      /* 1011: fSAMPLING=fDTS/16, N=6 */
+#define GTIM_CCMR_ICF_FDTSd168    (12)      /* 1100: fSAMPLING=fDTS/16, N=8 */
+#define GTIM_CCMR_ICF_FDTSd325    (13)      /* 1101: fSAMPLING=fDTS/32, N=5 */
+#define GTIM_CCMR_ICF_FDTSd326    (14)      /* 1110: fSAMPLING=fDTS/32, N=6 */
+#define GTIM_CCMR_ICF_FDTSd328    (15)      /* 1111: fSAMPLING=fDTS/32, N=8 */
+
+/* Capture/compare mode register 2 - Output Compare mode (TIM2-5 only) */
+
+#define GTIM_CCMR2_CC3S_SHIFT     (0)       /* Bits 1-0: Capture/Compare 3 Selection */
+#define GTIM_CCMR2_CC3S_MASK      (3 << GTIM_CCMR2_CC3S_SHIFT)
+                                            /* (See common CCMR Capture/Compare Selection definitions above) */
+#define GTIM_CCMR2_OC3FE          (1 << 2)  /* Bit 2: Output Compare 3 Fast enable */
+#define GTIM_CCMR2_OC3PE          (1 << 3)  /* Bit 3: Output Compare 3 Preload enable */
+#define GTIM_CCMR2_OC3M_SHIFT     (4)       /* Bits 6-4: Output Compare 3 Mode */
+#define GTIM_CCMR2_OC3M_MASK      (7 << GTIM_CCMR2_OC3M_SHIFT)
+                                            /* (See common CCMR Output Compare Mode definitions above) */
+#define GTIM_CCMR2_OC3CE          (1 << 7)  /* Bit 7: Output Compare 3 Clear Enable */
+#define GTIM_CCMR2_CC4S_SHIFT     (8)       /* Bits 9-8: Capture/Compare 4 Selection */
+#define GTIM_CCMR2_CC4S_MASK      (3 << GTIM_CCMR2_CC4S_SHIFT)
+                                            /* (See common CCMR Capture/Compare Selection definitions above) */
+#define GTIM_CCMR2_OC4FE          (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
+#define GTIM_CCMR2_OC4PE          (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
+#define GTIM_CCMR2_OC4M_SHIFT     (12)      /* Bits 14-12: Output Compare 4 Mode */
+#define GTIM_CCMR2_OC4M_MASK      (7 << GTIM_CCMR2_OC4M_SHIFT)
+                                            /* (See common CCMR Output Compare Mode definitions above) */
+#define GTIM_CCMR2_OC4CE          (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
+
+/* Capture/compare mode register 2 - Input capture mode (TIM2-5 only) */
+
+                                            /* Bits 1-0 (Same as Output Compare Mode) */
+#define GTIM_CCMR2_IC3PSC_SHIFT   (2)       /* Bits 3-2: Input Capture 3 Prescaler */
+#define GTIM_CCMR2_IC3PSC_MASK    (3 << GTIM_CCMR2_IC3PSC_SHIFT)
+                                            /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR2_IC3F_SHIFT     (4)       /* Bits 7-4: Input Capture 3 Filter */
+#define GTIM_CCMR2_IC3F_MASK      (0x0f << GTIM_CCMR2_IC3F_SHIFT)
+                                            /* (See common CCMR Input Capture Filter definitions below) */
+                                            /* Bits 9-8: (Same as Output Compare Mode) */
+#define GTIM_CCMR2_IC4PSC_SHIFT   (10)      /* Bits 11-10: Input Capture 4 Prescaler */
+#define GTIM_CCMR2_IC4PSC_MASK    (3 << GTIM_CCMR2_IC4PSC_SHIFT)
+                                            /* (See common CCMR Input Capture Prescaler definitions below) */
+#define GTIM_CCMR2_IC4F_SHIFT     (12)      /* Bits 15-12: Input Capture 4 Filter */
+#define GTIM_CCMR2_IC4F_MASK      (0x0f << GTIM_CCMR2_IC4F_SHIFT)
+                                            /* (See common CCMR Input Capture Filter definitions below) */
+
+/* Capture/compare enable register (TIM1 and TIM8, TIM2-5 and TIM9-14) */
+
+#define GTIM_CCER_CC1E            (1 << 0)  /* Bit 0: Capture/Compare 1 output enable */
+#define GTIM_CCER_CC1P            (1 << 1)  /* Bit 1: Capture/Compare 1 output polarity */
+#define GTIM_CCER_CC1NE           (1 << 2)  /* Bit 2: Capture/Compare 1 complementary output enable (TIM1 and TIM8 only) */
+#define GTIM_CCER_CC1NP           (1 << 3)  /* Bit 3: Capture/Compare 1 output Polarity (F2,F3,F4 and TIM15-17) */
+#define GTIM_CCER_CC2E            (1 << 4)  /* Bit 4: Capture/Compare 2 output enable (TIM2-5,9&12 only) */
+#define GTIM_CCER_CC2P            (1 << 5)  /* Bit 5: Capture/Compare 2 output polarity (TIM2-5,9&12 only) */
+#define GTIM_CCER_CC2NE           (1 << 6)  /* Bit 6: Capture/Compare 2 complementary output enable (TIM1 and TIM8 only) */
+#define GTIM_CCER_CC2NP           (1 << 7)  /* Bit 7: Capture/Compare 2 output Polarity (F2,F3,F4 and TIM2-5,9,12&15 only) */
+#define GTIM_CCER_CC3E            (1 << 8)  /* Bit 8: Capture/Compare 3 output enable (TIM2-5 only) */
+#define GTIM_CCER_CC3P            (1 << 9)  /* Bit 9: Capture/Compare 3 output Polarity (TIM2-5 only) */
+#define GTIM_CCER_CC3NE           (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable (TIM1 and TIM8 only) */
+#define GTIM_CCER_CC3NP           (1 << 11) /* Bit 11: Capture/Compare 3 output Polarity (F2,F4 and TIM2-5 only) */
+#define GTIM_CCER_CC4E            (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */
+#define GTIM_CCER_CC4P            (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */
+#define GTIM_CCER_CC4NP           (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */
+
+/* 16-bit counter register */
+
+#define GTIM_CNT_SHIFT            (0)       /* Bits 0-15: Timer counter value */
+#define GTIM_CNT_MASK             (0xffff << ATIM_CNT_SHIFT)
+
+/* DMA control register */
+
+#define GTIM_DCR_DBA_SHIFT        (0)       /* Bits 4-0: DMA Base Address */
+#define GTIM_DCR_DBA_MASK         (0x1f << GTIM_DCR_DBA_SHIFT)
+#define GTIM_DCR_DBL_SHIFT        (8)       /* Bits 12-8: DMA Burst Length */
+#define GTIM_DCR_DBL_MASK         (0x1f << GTIM_DCR_DBL_SHIFT)
+
+/* Timer 2/5 option register */
+
+#define TIM2_OR_ITR1_RMP_SHIFT    (10)     /* Bits 10-11: Internal trigger 1 remap */
+#define TIM2_OR_ITR1_RMP_MASK     (3 << TIM2_OR_ITR1_RMP_SHIFT)
+#  define TIM2_OR_ITR1_TIM8_TRGOUT (0 << TIM2_OR_ITR1_RMP_SHIFT) /* 00: TIM2_ITR1 input connected to TIM8_TRGOUT */
+#  define TIM2_OR_ITR1_PTP        (1 << TIM2_OR_ITR1_RMP_SHIFT) /* 01: TIM2_ITR1 input connected to PTP trigger output */
+#  define TIM2_OR_ITR1_OTGFSSOF   (2 << TIM2_OR_ITR1_RMP_SHIFT) /* 10: TIM2_ITR1 input connected to OTG FS SOF */
+#  define TIM2_OR_ITR1_OTGHSSOF   (3 << TIM2_OR_ITR1_RMP_SHIFT) /* 11: TIM2_ITR1 input connected to OTG HS SOF */
+
+#define TIM5_OR_TI4_RMP_SHIFT     (6)     /* Bits 6-7: Internal trigger 4 remap */
+#define TIM5_OR_TI4_RMP_MASK      (3 << TIM5_OR_TI4_RMP_SHIFT)
+#  define TIM5_OR_TI4_GPIO        (0 << TIM5_OR_TI4_RMP_SHIFT) /* 00: TIM5_CH4 input connected to GPIO */
+#  define TIM5_OR_TI4_LSI         (1 << TIM5_OR_TI4_RMP_SHIFT) /* 01: TIM5_CH4 input connected to LSI internal clock */
+#  define TIM5_OR_TI4_LSE         (2 << TIM5_OR_TI4_RMP_SHIFT) /* 10: TIM5_CH4 input connected to LSE internal clock */
+#  define TIM5_OR_TI4_RTC         (3 << TIM5_OR_TI4_RMP_SHIFT) /* 11: TIM5_CH4 input connected to RTC output event */
+
+#define TIM11_OR_TI1_RMP_SHIFT    (6)     /* Bits 6-7: Internal trigger 4 remap */
+#define TIM11_OR_TI1_RMP_MASK     (3 << TIM11_OR_TI1_RMP_SHIFT)
+#  define TIM11_OR_TI1_GPIO       (0 << TIM11_OR_TI1_RMP_SHIFT) /* 00-11: TIM11_CH1 input connected to GPIO */
+#  define TIM11_OR_TI1_HSERTC     (3 << TIM11_OR_TI1_RMP_SHIFT) /* 11: TIM11_CH1 input connected to HSE_RTC clock */
+
+/* Control register 1 */
+
+#define BTIM_CR1_CEN              (1 << 0)  /* Bit 0: Counter enable */
+#define BTIM_CR1_UDIS             (1 << 1)  /* Bit 1: Update Disable */
+#define BTIM_CR1_URS              (1 << 2)  /* Bit 2: Update Request Source */
+#define BTIM_CR1_OPM              (1 << 3)  /* Bit 3: One Pulse Mode */
+#define BTIM_CR1_ARPE             (1 << 7)  /* Bit 7: Auto-Reload Preload enable */
+
+/* Control register 2 */
+
+#define BTIM_CR2_MMS_SHIFT        (4)       /* Bits 6-4: Master Mode Selection */
+#define BTIM_CR2_MMS_MASK         (7 << BTIM_CR2_MMS_SHIFT)
+#  define BTIM_CR2_RESET          (0 << BTIM_CR2_MMS_SHIFT) /* 000: Reset */
+#  define BTIM_CR2_ENAB           (1 << BTIM_CR2_MMS_SHIFT) /* 001: Enable */
+#  define BTIM_CR2_UPDT           (2 << BTIM_CR2_MMS_SHIFT) /* 010: Update */
+
+/* DMA/Interrupt enable register */
+
+#define BTIM_DIER_UIE             (1 << 0)  /* Bit 0: Update interrupt enable */
+#define BTIM_DIER_UDE             (1 << 8)  /* Bit 8: Update DMA request enable */
+
+/* Status register */
+
+#define BTIM_SR_UIF               (1 << 0)  /* Bit 0: Update interrupt flag */
+
+/* Event generation register */
+
+#define BTIM_EGR_UG               (1 << 0)  /* Bit 0: Update generation */
+
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_TIM_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32_uart.h b/arch/arm/src/stm32h7/hardware/stm32_uart.h
similarity index 89%
rename from arch/arm/src/stm32h7/chip/stm32_uart.h
rename to arch/arm/src/stm32h7/hardware/stm32_uart.h
index 998c5861bc1..7929e07b304 100644
--- a/arch/arm/src/stm32h7/chip/stm32_uart.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32_uart.h
+ * arch/arm/src/stm32h7/hardware/stm32_uart.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_UART_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_UART_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_UART_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_UART_H
 
 /************************************************************************************
  * Included Files
@@ -44,9 +44,9 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32H7_STM32H7X3XX)
-#  include "chip/stm32h7x3xx_uart.h"
+#  include "hardware/stm32h7x3xx_uart.h"
 #else
 #  error "Unsupported STM32 H7 memory map"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_UART_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_dmamux.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_dmamux.h
similarity index 99%
rename from arch/arm/src/stm32h7/chip/stm32h7x3xx_dmamux.h
rename to arch/arm/src/stm32h7/hardware/stm32h7x3xx_dmamux.h
index 5d7bd9bcbac..04c4e7d95af 100644
--- a/arch/arm/src/stm32h7/chip/stm32h7x3xx_dmamux.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_dmamux.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32h7x3xx_dmamux.h
+ * arch/arm/src/stm32h7/hardware/stm32h7x3xx_dmamux.h
  *
  *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_DMAMUX_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_DMAMUX_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_DMAMUX_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_DMAMUX_H
 
 /************************************************************************************
  * Included Files
@@ -501,4 +501,4 @@
 #define DMAMAP_BDMA_SAI4B          DMAMAP_MAP(BDMA, DMAMUX2_SAI4B)
 #define DMAMAP_BDMA_ADC3           DMAMAP_MAP(BDMA, DMAMUX2_ADC3)
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_DMAMUX_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_DMAMUX_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_flash.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_flash.h
similarity index 98%
rename from arch/arm/src/stm32h7/chip/stm32h7x3xx_flash.h
rename to arch/arm/src/stm32h7/hardware/stm32h7x3xx_flash.h
index e2f389c516d..703ad400380 100644
--- a/arch/arm/src/stm32h7/chip/stm32h7x3xx_flash.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_flash.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32h7x3xx_flash.h
+ * arch/arm/src/stm32h7/hardware/stm32h7x3xx_flash.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM327_CHIP_STM32H7X3XX_FLASH_H
-#define __ARCH_ARM_SRC_STM327_CHIP_STM32H7X3XX_FLASH_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_FLASH_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_FLASH_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -261,4 +261,4 @@
 
 /* TODO: Flash CRC End Address Register (CRCSEDDR) */
 
-#endif /* __ARCH_ARM_SRC_STM327_CHIP_STM32H7X3XX_FLASH_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_FLASH_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_gpio.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h
similarity index 98%
rename from arch/arm/src/stm32h7/chip/stm32h7x3xx_gpio.h
rename to arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h
index 78168e2059f..78f8087928a 100644
--- a/arch/arm/src/stm32h7/chip/stm32h7x3xx_gpio.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32h7x3xx_gpio.h
+ * arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_GPIO_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_GPIO_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_GPIO_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -400,4 +400,4 @@
 #define GPIO_AFRH15_MASK           (15 << GPIO_AFRH15_SHIFT)
 
 #endif /* CONFIG_STM32H7_STM32H7X3XX */
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_GPIO_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_GPIO_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_i2c.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h
similarity index 99%
rename from arch/arm/src/stm32h7/chip/stm32h7x3xx_i2c.h
rename to arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h
index f51aeb7c1e0..d9b7990fc20 100644
--- a/arch/arm/src/stm32h7/chip/stm32h7x3xx_i2c.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32h7x3xx_i2c.h
+ * arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -260,4 +260,4 @@
 
 #define I2C_TXDR_MASK             (0xff)
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_I2C_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_I2C_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_memorymap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h
similarity index 97%
rename from arch/arm/src/stm32h7/chip/stm32h7x3xx_memorymap.h
rename to arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h
index 82e9258e766..6f2c5361dee 100644
--- a/arch/arm/src/stm32h7/chip/stm32h7x3xx_memorymap.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm3fr2/chip/stm32h7x3xx_memorymap.h
+ * arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_MEMORYMAP_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -231,4 +231,7 @@
 #define STM32_ADC3_BASE        0x58026000     /* 0x58026000-0x580263ff ADC3 */
 #define STM32_HSEM_BASE        0x58026400     /* 0x58026400-0x580267ff HSEM */
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_MEMORYMAP_H */
+#define STM32_SYSMEM_UID       0x1ff1e800
+#define STM32_DEBUGMCU_BASE    0xe00e1000
+
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_pinmap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h
similarity index 98%
rename from arch/arm/src/stm32h7/chip/stm32h7x3xx_pinmap.h
rename to arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h
index 29b0b5a984a..1367baba5e9 100644
--- a/arch/arm/src/stm32h7/chip/stm32h7x3xx_pinmap.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32h76xx77xx_pinmap.h
+ * arch/arm/src/stm32h7/hardware/stm32h76xx77xx_pinmap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32H7X3XX_PINMAP_H
-#define __ARCH_ARM_SRC_STM32_CHIP_STM32H7X3XX_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -61,7 +61,7 @@
  *
  * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
  *
- * The driver will then automatically configre PA11 as the CAN1 RX pin.
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -243,7 +243,7 @@
 #define GPIO_ETH_RMII_CRS_DV      (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
 #define GPIO_ETH_RMII_REF_CLK     (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
 #define GPIO_ETH_RMII_RXD0        (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4)
-#define GPIO_ETH_RMII_RXD         (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
+#define GPIO_ETH_RMII_RXD1        (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
 #define GPIO_ETH_RMII_TX_EN_1     (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
 #define GPIO_ETH_RMII_TX_EN_2     (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
 #define GPIO_ETH_RMII_TXD0_1      (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
@@ -1143,30 +1143,30 @@
 #define GPIO_TIM1_CH1OUT_1        (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
 #define GPIO_TIM1_CH1OUT_2        (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN9)
 #define GPIO_TIM1_CH1OUT_3        (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN1)
-#define GPIO_TIM1_CH1N_1          (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN7)
-#define GPIO_TIM1_CH1N_2          (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN13)
-#define GPIO_TIM1_CH1N_3          (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN8)
-#define GPIO_TIM1_CH1N_4          (GPIO_ALT|GPIO_AF1|GPIO_PORTK|GPIO_PIN0)
+#define GPIO_TIM1_CH1NOUT_1       (GPIO_ALT|GPIO_AF1|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM1_CH1NOUT_2       (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_TIM1_CH1NOUT_3       (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN8)
+#define GPIO_TIM1_CH1NOUT_4       (GPIO_ALT|GPIO_AF1|GPIO_PORTK|GPIO_PIN0)
 #define GPIO_TIM1_CH2IN_1         (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN9)
 #define GPIO_TIM1_CH2IN_2         (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN11)
 #define GPIO_TIM1_CH2IN_3         (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTJ|GPIO_PIN11)
 #define GPIO_TIM1_CH2OUT_1        (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
 #define GPIO_TIM1_CH2OUT_2        (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11)
 #define GPIO_TIM1_CH2OUT_3        (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN11)
-#define GPIO_TIM1_CH2N_1          (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN0)
-#define GPIO_TIM1_CH2N_2          (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN14)
-#define GPIO_TIM1_CH2N_3          (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN10)
-#define GPIO_TIM1_CH2N_4          (GPIO_ALT|GPIO_AF1|GPIO_PORTJ|GPIO_PIN10)
+#define GPIO_TIM1_CH2NOUT_1       (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_TIM1_CH2NOUT_2       (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_TIM1_CH2NOUT_3       (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN10)
+#define GPIO_TIM1_CH2NOUT_4       (GPIO_ALT|GPIO_AF1|GPIO_PORTJ|GPIO_PIN10)
 #define GPIO_TIM1_CH3IN_1         (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN10)
 #define GPIO_TIM1_CH3IN_2         (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN13)
 #define GPIO_TIM1_CH3IN_3         (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTJ|GPIO_PIN9)
 #define GPIO_TIM1_CH3OUT_1        (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
 #define GPIO_TIM1_CH3OUT_2        (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13)
 #define GPIO_TIM1_CH3OUT_3        (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN9)
-#define GPIO_TIM1_CH3N_1          (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN1)
-#define GPIO_TIM1_CH3N_2          (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN15)
-#define GPIO_TIM1_CH3N_3          (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN12)
-#define GPIO_TIM1_CH3N_4          (GPIO_ALT|GPIO_AF1|GPIO_PORTJ|GPIO_PIN8)
+#define GPIO_TIM1_CH3NOUT_1       (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_TIM1_CH3NOUT_2       (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_TIM1_CH3NOUT_3       (GPIO_ALT|GPIO_AF1|GPIO_PORTE|GPIO_PIN12)
+#define GPIO_TIM1_CH3NOUT_4       (GPIO_ALT|GPIO_AF1|GPIO_PORTJ|GPIO_PIN8)
 #define GPIO_TIM1_CH4IN_1         (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN11)
 #define GPIO_TIM1_CH4IN_2         (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN14)
 #define GPIO_TIM1_CH4OUT_1        (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
@@ -1276,10 +1276,10 @@
 #define GPIO_TIM8_CH1OUT_1        (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
 #define GPIO_TIM8_CH1OUT_2        (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN5)
 #define GPIO_TIM8_CH1OUT_3        (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN8)
-#define GPIO_TIM8_CH1N_1          (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN5)
-#define GPIO_TIM8_CH1N_2          (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN7)
-#define GPIO_TIM8_CH1N_3          (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN13)
-#define GPIO_TIM8_CH1N_4          (GPIO_ALT|GPIO_AF3|GPIO_PORTJ|GPIO_PIN9)
+#define GPIO_TIM8_CH1NOUT_1       (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_TIM8_CH1NOUT_2       (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM8_CH1NOUT_3       (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN13)
+#define GPIO_TIM8_CH1NOUT_4       (GPIO_ALT|GPIO_AF3|GPIO_PORTJ|GPIO_PIN9)
 #define GPIO_TIM8_CH2IN_1         (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN7)
 #define GPIO_TIM8_CH2IN_2         (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN6)
 #define GPIO_TIM8_CH2IN_3         (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTJ|GPIO_PIN10)
@@ -1288,21 +1288,21 @@
 #define GPIO_TIM8_CH2OUT_2        (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN6)
 #define GPIO_TIM8_CH2OUT_3        (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN10)
 #define GPIO_TIM8_CH2OUT_4        (GPIO_ALT|GPIO_AF3|GPIO_PORTJ|GPIO_PIN6)
-#define GPIO_TIM8_CH2N_1          (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0)
-#define GPIO_TIM8_CH2N_2          (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14)
-#define GPIO_TIM8_CH2N_3          (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN14)
-#define GPIO_TIM8_CH2N_4          (GPIO_ALT|GPIO_AF3|GPIO_PORTJ|GPIO_PIN11)
-#define GPIO_TIM8_CH2N_5          (GPIO_ALT|GPIO_AF3|GPIO_PORTJ|GPIO_PIN7)
+#define GPIO_TIM8_CH2NOUT_1       (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_TIM8_CH2NOUT_2       (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_TIM8_CH2NOUT_3       (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN14)
+#define GPIO_TIM8_CH2NOUT_4       (GPIO_ALT|GPIO_AF3|GPIO_PORTJ|GPIO_PIN11)
+#define GPIO_TIM8_CH2NOUT_5       (GPIO_ALT|GPIO_AF3|GPIO_PORTJ|GPIO_PIN7)
 #define GPIO_TIM8_CH3IN_1         (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN8)
 #define GPIO_TIM8_CH3IN_2         (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN7)
 #define GPIO_TIM8_CH3IN_3         (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTK|GPIO_PIN0)
 #define GPIO_TIM8_CH3OUT_1        (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
 #define GPIO_TIM8_CH3OUT_2        (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN7)
 #define GPIO_TIM8_CH3OUT_3        (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN0)
-#define GPIO_TIM8_CH3N_1          (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN1)
-#define GPIO_TIM8_CH3N_2          (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN15)
-#define GPIO_TIM8_CH3N_3          (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN15)
-#define GPIO_TIM8_CH3N_4          (GPIO_ALT|GPIO_AF3|GPIO_PORTK|GPIO_PIN1)
+#define GPIO_TIM8_CH3NOUT_1       (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_TIM8_CH3NOUT_2       (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_TIM8_CH3NOUT_3       (GPIO_ALT|GPIO_AF3|GPIO_PORTH|GPIO_PIN15)
+#define GPIO_TIM8_CH3NOUT_4       (GPIO_ALT|GPIO_AF3|GPIO_PORTK|GPIO_PIN1)
 #define GPIO_TIM8_CH4IN_1         (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTC|GPIO_PIN9)
 #define GPIO_TIM8_CH4IN_2         (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTI|GPIO_PIN2)
 #define GPIO_TIM8_CH4OUT_1        (GPIO_ALT|GPIO_AF3|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
@@ -1337,8 +1337,8 @@
 #define GPIO_TIM15_CH1OUT_1       (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
 #define GPIO_TIM15_CH1OUT_2       (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5)
 
-#define GPIO_TIM15_CH1N_1         (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN1)
-#define GPIO_TIM15_CH1N_2         (GPIO_ALT|GPIO_AF4|GPIO_PORTE|GPIO_PIN4)
+#define GPIO_TIM15_CH1NOUT_1      (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM15_CH1NOUT_2      (GPIO_ALT|GPIO_AF4|GPIO_PORTE|GPIO_PIN4)
 #define GPIO_TIM15_CH2IN_1        (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN3)
 #define GPIO_TIM15_CH2IN_2        (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTE|GPIO_PIN6)
 #define GPIO_TIM15_CH2OUT_1       (GPIO_ALT|GPIO_AF4|GPIO_PORTA|GPIO_PIN3)
@@ -1350,8 +1350,8 @@
 #define GPIO_TIM16_CH1IN_2        (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN6)
 #define GPIO_TIM16_CH1OUT_1       (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
 #define GPIO_TIM16_CH1OUT_2       (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6)
-#define GPIO_TIM16_CH1N_1         (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN6)
-#define GPIO_TIM16_CH1N_2         (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN8)
+#define GPIO_TIM16_CH1NOUT_1      (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_TIM16_CH1NOUT_2      (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN8)
 
 #define GPIO_TIM17_BKIN_1         (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN5)
 #define GPIO_TIM17_BKIN_2         (GPIO_ALT|GPIO_AF1|GPIO_PORTG|GPIO_PIN6)
@@ -1359,8 +1359,8 @@
 #define GPIO_TIM17_CH1IN_2        (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_FLOAT|GPIO_PORTF|GPIO_PIN7)
 #define GPIO_TIM17_CH1OUT_1       (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
 #define GPIO_TIM17_CH1OUT_2       (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN7)
-#define GPIO_TIM17_CH1N_1         (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN7)
-#define GPIO_TIM17_CH1N_2         (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN9)
+#define GPIO_TIM17_CH1NOUT_1      (GPIO_ALT|GPIO_AF1|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_TIM17_CH1NOUT_2      (GPIO_ALT|GPIO_AF1|GPIO_PORTF|GPIO_PIN9)
 
 /* Trace */
 
@@ -1479,4 +1479,4 @@
 #define GPIO_UART8_TX_2           (GPIO_ALT|GPIO_AF8|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTJ|GPIO_PIN8)
 
 #endif /* CONFIG_STM32H7_STM32H7X3XX */
-#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32H7X3XX_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PINMAP_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_pwr.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h
similarity index 96%
rename from arch/arm/src/stm32h7/chip/stm32h7x3xx_pwr.h
rename to arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h
index 5e466a1f2be..7192cd1325c 100644
--- a/arch/arm/src/stm32h7/chip/stm32h7x3xx_pwr.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32h7x3xx_pwr.h
+ * arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM327_CHIP_STM32H7X3XX_PWR_H
-#define __ARCH_ARM_SRC_STM327_CHIP_STM32H7X3XX_PWR_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PWR_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PWR_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -130,4 +130,4 @@
 
 /* Power wakeup enable and polarity register (WKUPEPR) */
 
-#endif /* __ARCH_ARM_SRC_STM327_CHIP_STM32H7X3XX_PWR_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PWR_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
similarity index 97%
rename from arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h
rename to arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
index 3eeaf38dac7..6691fa5642d 100644
--- a/arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h
+ * arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_RCC_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_RCC_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_RCC_H
 
 /****************************************************************************************************
  * Included Files
@@ -597,6 +597,14 @@
 #   define RCC_D2CCIP2R_I2C123SEL_PLL3     (1 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 01 */
 #   define RCC_D2CCIP2R_I2C123SEL_HSI      (2 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 10 */
 #   define RCC_D2CCIP2R_I2C123SEL_CSI      (3 << RCC_D2CCIP2R_I2C123SEL_SHIFT) /* 11 */
+
+#define RCC_D2CCIP2R_I2C4SEL_SHIFT         (8) /* Bits 8-9 */
+#define RCC_D2CCIP2R_I2C4SEL_MASK          (3 << RCC_D2CCIP2R_I2C4SEL_SHIFT)
+#   define RCC_D2CCIP2R_I2C4SEL_PCLK1      (0 << RCC_D2CCIP2R_I2C4SEL_SHIFT) /* 00 */
+#   define RCC_D2CCIP2R_I2C4SEL_PLL3       (1 << RCC_D2CCIP2R_I2C4SEL_SHIFT) /* 01 */
+#   define RCC_D2CCIP2R_I2C4SEL_HSI        (2 << RCC_D2CCIP2R_I2C4SEL_SHIFT) /* 10 */
+#   define RCC_D2CCIP2R_I2C4SEL_CSI        (3 << RCC_D2CCIP2R_I2C4SEL_SHIFT) /* 11 */
+
 #define RCC_D2CCIP2R_USBSEL_SHIFT          (20) /* Bits 20-21 */
 #  define RCC_D2CCIP2R_USBSEL_MASK         (3 << RCC_D2CCIP2R_USBSEL_SHIFT)
 #  define RCC_D2CCIP2R_USBSEL_DISABLE      (0 << RCC_D2CCIP2R_USBSEL_SHIFT)
@@ -874,7 +882,7 @@
 #define RCC_AHB4ENR_BDMAEN              (1 << 21)   /* RCC AHB4ENR: BDMAEN and DMAMUX2 */
 #define RCC_AHB4ENR_ADC3EN              (1 << 24)   /* RCC AHB4ENR: ADC3EN */
 #define RCC_AHB4ENR_HSEMEN              (1 << 25)   /* RCC AHB4ENR: HSEMEN */
-#define RCC_AHB4ENR_BKPRAMEN            (1 << 28)   /* RCC AHB4ENR: BKPRAMEN */
+#define RCC_AHB4ENR_BKPSRAMEN           (1 << 28)   /* RCC AHB4ENR: BKPRAMEN */
 
 /* APB3 Peripheral Clock enable register */
 
@@ -908,8 +916,8 @@
 #define RCC_APB1LENR_HDMICECEN          (1 << 27) /* RCC APB1LENR: HDMICECEN */
                                                   /* Bit 28: Reserved */
 #define RCC_APB1LENR_DAC1EN             (1 << 29) /* RCC APB1LENR: DAC1EN */
-#define RCC_APB1LENR_USART7EN           (1 << 30) /* RCC APB1LENR: USART7EN */
-#define RCC_APB1LENR_USART8EN           (1 << 31) /* RCC APB1LENR: USART8EN */
+#define RCC_APB1LENR_UART7EN            (1 << 30) /* RCC APB1LENR: USART7EN */
+#define RCC_APB1LENR_UART8EN            (1 << 31) /* RCC APB1LENR: USART8EN */
 
 /* APB1 H Peripheral Clock enable register */
 
@@ -1101,4 +1109,18 @@
 #define RCC_APB4LPENR_RTCAPBLPEN        (1 << 16)      /* RCC APB4LPENR: RTCAPBLPEN */
 #define RCC_APB4LPENR_SAI4LPEN          (1 << 21)      /* RCC APB4LPENR: SAI4LPEN */
 
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_RCC_H */
+/* Backup domain control register */
+
+#define RCC_BDCR_LSEON                  (1 << 0)  /* Bit 0: External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY                 (1 << 1)  /* Bit 1: External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP                 (1 << 2)  /* Bit 2: External Low Speed oscillator Bypass */
+#define RCC_BDCR_RTCSEL_SHIFT           (8)       /* Bits 9:8: RTC clock source selection */
+#define RCC_BDCR_RTCSEL_MASK            (3 << RCC_BDCR_RTCSEL_SHIFT)
+#  define RCC_BDCR_RTCSEL_NOCLK         (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */
+#  define RCC_BDCR_RTCSEL_LSE           (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */
+#  define RCC_BDCR_RTCSEL_LSI           (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */
+#  define RCC_BDCR_RTCSEL_HSE           (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCEN                  (1 << 15) /* Bit 15: RTC clock enable */
+#define RCC_BDCR_BDRST                  (1 << 16) /* Bit 16: Backup domain software reset */
+
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_RCC_H */
diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_sdmmc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_sdmmc.h
new file mode 100644
index 00000000000..0f165c54130
--- /dev/null
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_sdmmc.h
@@ -0,0 +1,246 @@
+/************************************************************************************
+ * arch/arm/src/stm32h7/hardware/stm32h7x3xx_sdmmc.h
+ *
+ *   Copyright (C) 2009, 2011-2016, 2019 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *            David Sidrane 
+ *            Jukka Laitinen 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SDMMC_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SDMMC_H
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_SDMMC_POWER_OFFSET              0x0000 /* SDMMC power control register */
+#define STM32_SDMMC_CLKCR_OFFSET              0x0004 /* SDMMC clock control register */
+#define STM32_SDMMC_ARG_OFFSET                0x0008 /* SDMMC argument register */
+#define STM32_SDMMC_CMD_OFFSET                0x000c /* SDMMC command register */
+#define STM32_SDMMC_RESPCMD_OFFSET            0x0010 /* SDMMC command response register */
+#define STM32_SDMMC_RESP_OFFSET(n)            (0x0010+4*(n))
+#define STM32_SDMMC_RESP1_OFFSET              0x0014 /* SDMMC response 1 register */
+#define STM32_SDMMC_RESP2_OFFSET              0x0018 /* SDMMC response 2 register */
+#define STM32_SDMMC_RESP3_OFFSET              0x001c /* SDMMC response 3 register */
+#define STM32_SDMMC_RESP4_OFFSET              0x0020 /* SDMMC response 4 register */
+#define STM32_SDMMC_DTIMER_OFFSET             0x0024 /* SDMMC data timer register */
+#define STM32_SDMMC_DLEN_OFFSET               0x0028 /* SDMMC data length register */
+#define STM32_SDMMC_DCTRL_OFFSET              0x002c /* SDMMC data control register */
+#define STM32_SDMMC_DCOUNT_OFFSET             0x0030 /* SDMMC data counter register */
+#define STM32_SDMMC_STA_OFFSET                0x0034 /* SDMMC status register */
+#define STM32_SDMMC_ICR_OFFSET                0x0038 /* SDMMC interrupt clear register */
+#define STM32_SDMMC_MASK_OFFSET               0x003c /* SDMMC mask register */
+#define STM32_SDMMC_IDMACTRLR_OFFSET          0x0050 /* SDMMC DMA control register */
+#define STM32_SDMMC_IDMABASE0R_OFFSET         0x0058 /* SDMMC IDMA buffer 0 base register */
+#define STM32_SDMMC_FIFO_OFFSET               0x0080 /* SDMMC data FIFO register */
+
+/* Register Bitfield Definitions ****************************************************/
+
+#define STM32_SDMMC_POWER_PWRCTRL_SHIFT       (0)       /* Bits 0-1: Power supply control bits */
+#define STM32_SDMMC_POWER_PWRCTRL_MASK        (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT)
+#  define STM32_SDMMC_POWER_PWRCTRL_OFF       (0 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */
+#  define STM32_SDMMC_POWER_PWRCTRL_CYCLE     (2 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */
+#  define STM32_SDMMC_POWER_PWRCTRL_ON        (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */
+
+#define STM32_SDMMC_POWER_RESET               (0)       /* Reset value */
+
+#define STM32_SDMMC_CLKCR_CLKDIV_SHIFT        (0)       /* Bits 9-0: Clock divide factor */
+#define STM32_SDMMC_CLKCR_CLKDIV_MASK         (0x3ff << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#define STM32_SDMMC_CLKCR_PWRSAV              (1 << 12)  /* Bit 12: Power saving configuration bit */
+#define STM32_SDMMC_CLKCR_WIDBUS_SHIFT        (14)      /* Bits 12-11: Wide bus mode enable bits */
+#define STM32_SDMMC_CLKCR_WIDBUS_MASK         (3 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT)
+#  define STM32_SDMMC_CLKCR_WIDBUS_D1         (0 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 00: Default (STM32_SDMMC_D0) */
+#  define STM32_SDMMC_CLKCR_WIDBUS_D4         (1 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (STM32_SDMMC_D[3:0]) */
+#  define STM32_SDMMC_CLKCR_WIDBUS_D8         (2 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (STM32_SDMMC_D[7:0]) */
+#define STM32_SDMMC_CLKCR_NEGEDGE             (1 << 16) /* Bit 16: STM32_SDMMC_CK dephasing selection bit */
+#define STM32_SDMMC_CLKCR_HWFC_EN             (1 << 17) /* Bit 17: HW Flow Control enable */
+
+#define STM32_SDMMC_CLKCR_RESET               (0)       /* Reset value */
+
+#define STM32_SDMMC_ARG_RESET                 (0)       /* Reset value */
+
+#define STM32_SDMMC_CMD_CMDINDEX_SHIFT        (0)
+#define STM32_SDMMC_CMD_CMDINDEX_MASK         (0x3f << STM32_SDMMC_CMD_CMDINDEX_SHIFT)
+#define STM32_SDMMC_CMD_CMDTRANS              (1 << 6)  /* Bit 6: The CPSM treats the command as a data transfer command */
+#define STM32_SDMMC_CMD_CMDSTOP               (1 << 7)  /* Bit 7: The CPSM treats the command as a Stop Transmission command */
+#define STM32_SDMMC_CMD_WAITRESP_SHIFT        (8)       /* Bits 8-9: Wait for response bits */
+#define STM32_SDMMC_CMD_WAITRESP_MASK         (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT)
+#  define STM32_SDMMC_CMD_NORESPONSE          (0 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 00/10: No response */
+#  define STM32_SDMMC_CMD_SHORTRESPONSE       (1 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */
+#  define STM32_SDMMC_CMD_SHORTRESPONSE_NOCRC (2 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response, no CRC */
+#  define STM32_SDMMC_CMD_LONGRESPONSE        (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */
+#define STM32_SDMMC_CMD_WAITINT               (1 << 10)  /* Bit 10: CPSM waits for interrupt request */
+#define STM32_SDMMC_CMD_WAITPEND              (1 << 11)  /* Bit 11: CPSM Waits for ends of data transfer */
+#define STM32_SDMMC_CMD_CPSMEN                (1 << 12) /* Bit 12: Command path state machine enable */
+#define STM32_SDMMC_CMD_DTHOLD                (1 << 13) /* Bit 13: Hold new data block transmission and reception in the DPSM */
+#define STM32_SDMMC_CMD_BOOTMODE              (1 << 14) /* Bit 14: Select bootmode */
+#define STM32_SDMMC_CMD_BOOTEN                (1 << 15) /* Bit 15: Enable boot mode */
+#define STM32_SDMMC_CMD_SUSPEND               (1 << 16) /* Bit 16: SD I/O suspend command */
+
+#define STM32_SDMMC_CMD_RESET                 (0)       /* Reset value */
+
+#define STM32_SDMMC_RESPCMD_SHIFT             (0)
+#define STM32_SDMMC_RESPCMD_MASK              (0x3f << STM32_SDMMC_RESPCMD_SHIFT)
+
+#define STM32_SDMMC_DTIMER_RESET              (0)       /* Reset value */
+
+#define STM32_SDMMC_DLEN_SHIFT                (0)
+#define STM32_SDMMC_DLEN_MASK                 (0x01ffffff << STM32_SDMMC_DLEN_SHIFT)
+
+#define STM32_SDMMC_DLEN_RESET                (0)       /* Reset value */
+
+#define STM32_SDMMC_DCTRL_DTEN                (1 << 0)  /* Bit 0: Data transfer enabled bit */
+#define STM32_SDMMC_DCTRL_DTDIR               (1 << 1)  /* Bit 1: Data transfer direction */
+#define STM32_SDMMC_DCTRL_DTMODE_SHIFT        (2)  /* Bits 2-3: Data transfer mode */
+#define STM32_SDMMC_DCTRL_DTMODE_MASK         (3 << STM32_SDMMC_DCTRL_DTMODE_SHIFT)
+#  define STM32_SDMMC_DCTRL_DTMODE_END        (0 << STM32_SDMMC_DCTRL_DTMODE_SHIFT)
+#  define STM32_SDMMC_DCTRL_DTMODE_SDIO       (1 << STM32_SDMMC_DCTRL_DTMODE_SHIFT)
+#  define STM32_SDMMC_DCTRL_DTMODE_EMMC       (2 << STM32_SDMMC_DCTRL_DTMODE_SHIFT)
+#  define STM32_SDMMC_DCTRL_DTMODE_BLOCK      (3 << STM32_SDMMC_DCTRL_DTMODE_SHIFT)
+
+#define STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT    (4)       /* Bits 7-4: Data block size */
+#define STM32_SDMMC_DCTRL_DBLOCKSIZE_MASK     (0xf << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_1BYTE             (0 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_2BYTES            (1 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_4BYTES            (2 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_8BYTES            (3 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_16BYTES           (4 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_32BYTES           (5 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_64BYTES           (6 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_128BYTES          (7 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_256BYTES          (8 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_512BYTES          (9 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_1KBYTE            (10 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_2KBYTES           (11 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_4KBYTES           (12 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_8KBYTES           (13 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_16KBYTES          (14 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#define STM32_SDMMC_DCTRL_RWSTART             (1 << 8)  /* Bit 8: Read wait start */
+#define STM32_SDMMC_DCTRL_RWSTOP              (1 << 9)  /* Bit 9: Read wait stop */
+#define STM32_SDMMC_DCTRL_RWMOD               (1 << 10) /* Bit 10: Read wait mode */
+#define STM32_SDMMC_DCTRL_SDIOEN              (1 << 11) /* Bit 11: SD I/O enable functions */
+#define STM32_SDMMC_DCTRL_BOOTACKEN           (1 << 12) /* Bit 12: Enable reception of boot ack */
+#define STM32_SDMMC_DCTRL_FIFORST             (1 << 13) /* Bit 13: FIFO reset */
+
+#define STM32_SDMMC_DCTRL_RESET               (0)       /* Reset value */
+
+#define STM32_SDMMC_DCOUNT_SHIFT              (0)
+#define STM32_SDMMC_DCOUNT_MASK               (0x01ffffff << STM32_SDMMC_DCOUNT_SHIFT)
+
+#define STM32_SDMMC_STA_CCRCFAIL              (1 << 0)  /* Bit 0: Command response CRC fail */
+#define STM32_SDMMC_STA_DCRCFAIL              (1 << 1)  /* Bit 1: Data block CRC fail */
+#define STM32_SDMMC_STA_CTIMEOUT              (1 << 2)  /* Bit 2: Command response timeout */
+#define STM32_SDMMC_STA_DTIMEOUT              (1 << 3)  /* Bit 3: Data timeout */
+#define STM32_SDMMC_STA_TXUNDERR              (1 << 4)  /* Bit 4: Transmit FIFO underrun error */
+#define STM32_SDMMC_STA_RXOVERR               (1 << 5)  /* Bit 5: Received FIFO overrun error */
+#define STM32_SDMMC_STA_CMDREND               (1 << 6)  /* Bit 6: Command response received  */
+#define STM32_SDMMC_STA_CMDSENT               (1 << 7)  /* Bit 7: Command sent  */
+#define STM32_SDMMC_STA_DATAEND               (1 << 8)  /* Bit 8: Data end */
+#define STM32_SDMMC_STA_DHOLD                 (1 << 9)  /* Bit 9: Data transfer hold  */
+#define STM32_SDMMC_STA_DBCKEND               (1 << 10) /* Bit 10: Data block sent/received  */
+#define STM32_SDMMC_STA_DABORT                (1 << 11) /* Bit 11: Data transfer aborted by CMD12 */
+#define STM32_SDMMC_STA_DPSMACT               (1 << 12) /* Bit 12: Data path state machine active */
+#define STM32_SDMMC_STA_CPSMACT               (1 << 13) /* Bit 13: Command path state machine active */
+#define STM32_SDMMC_STA_TXFIFOHE              (1 << 14) /* Bit 14: Transmit FIFO half empty */
+#define STM32_SDMMC_STA_RXFIFOHF              (1 << 15) /* Bit 15: Receive FIFO half full */
+#define STM32_SDMMC_STA_TXFIFOF               (1 << 16) /* Bit 16: Transmit FIFO full */
+#define STM32_SDMMC_STA_RXFIFOF               (1 << 17) /* Bit 17: Receive FIFO full */
+#define STM32_SDMMC_STA_TXFIFOE               (1 << 18) /* Bit 18: Transmit FIFO empty */
+#define STM32_SDMMC_STA_RXFIFOE               (1 << 19) /* Bit 19: Receive FIFO empty */
+#define STM32_SDMMC_STA_BUSYD0                (1 << 20) /* Bit 20: Card signals busy on SDMMC_D0 */
+#define STM32_SDMMC_STA_BUSYD0END             (1 << 21) /* Bit 21: card SDMMC_D0 signal changed from busy to NOT busy */
+#define STM32_SDMMC_STA_SDIOIT                (1 << 22) /* Bit 22: SDIO interrupt received */
+#define STM32_SDMMC_STA_ACKFAIL               (1 << 23) /* Bit 23: Boot ack check fail */
+#define STM32_SDMMC_STA_ACKTIMEOUT            (1 << 24) /* Bit 24: Boot ack timeout */
+#define STM32_SDMMC_STA_VSWEND                (1 << 25) /* Bit 25: Voltage switch critical timing section completion */
+#define STM32_SDMMC_STA_CKSTOP                (1 << 26) /* Bit 26: SDMMC_CK stopped in Voltage switch procedure */
+#define STM32_SDMMC_STA_IDMATE                (1 << 27) /* Bit 27: IDMA transfer error */
+#define STM32_SDMMC_STA_IDMABTC               (1 << 28) /* Bit 28: IDMA buffer transfer complete */
+
+#define STM32_SDMMC_ICR_CCRCFAILC             (1 << 0)  /* Bit 0: CCRCFAIL flag clear bit */
+#define STM32_SDMMC_ICR_DCRCFAILC             (1 << 1)  /* Bit 1: DCRCFAIL flag clear bit */
+#define STM32_SDMMC_ICR_CTIMEOUTC             (1 << 2)  /* Bit 2: CTIMEOUT flag clear bit */
+#define STM32_SDMMC_ICR_DTIMEOUTC             (1 << 3)  /* Bit 3: DTIMEOUT flag clear bit */
+#define STM32_SDMMC_ICR_TXUNDERRC             (1 << 4)  /* Bit 4: TXUNDERR flag clear bit */
+#define STM32_SDMMC_ICR_RXOVERRC              (1 << 5)  /* Bit 5: RXOVERR flag clear bit */
+#define STM32_SDMMC_ICR_CMDRENDC              (1 << 6)  /* Bit 6: CMDREND flag clear bit */
+#define STM32_SDMMC_ICR_CMDSENTC              (1 << 7)  /* Bit 7: CMDSENT flag clear bit */
+#define STM32_SDMMC_ICR_DATAENDC              (1 << 8)  /* Bit 8: DATAEND flag clear bit */
+#define STM32_SDMMC_ICR_DHOLDC                (1 << 9)  /* Bit 9: DHOLD flag clear bit */
+#define STM32_SDMMC_ICR_DBCKENDC              (1 << 10) /* Bit 10: DBCKEND flag clear bit */
+#define STM32_SDMMC_ICR_DABORTC               (1 << 11) /* Bit 11: DABORT flag clear bit */
+#define STM32_SDMMC_ICR_BUSYD0ENDC            (1 << 21) /* Bit 21: BUSYD0END flag clear bit */
+#define STM32_SDMMC_ICR_SDIOITC               (1 << 22) /* Bit 22: SDIOIT flag clear bit */
+#define STM32_SDMMC_ICR_ACKFAILC              (1 << 23) /* Bit 23: ACKFAIL flag clear bit */
+#define STM32_SDMMC_ICR_ACKTIMEOUTC           (1 << 24) /* Bit 24: ACKTIMEOUT flag clear bit */
+#define STM32_SDMMC_ICR_VSWENDC               (1 << 25) /* Bit 25: VSWEND flag clear bit */
+#define STM32_SDMMC_ICR_CKSTOPC               (1 << 26) /* Bit 26: CKSTOP flag clear bit */
+#define STM32_SDMMC_ICR_IDMATEC               (1 << 27) /* Bit 27: IDMA transfer error clear bit */
+#define STM32_SDMMC_ICR_IDMABTCC              (1 << 28) /* Bit 28: IDMA buffer transfer complete clear bit */
+
+#define STM32_SDMMC_ICR_RESET                 0x00000000
+#define STM32_SDMMC_ICR_ALLFLAGS              0x1fe00fff
+
+#define STM32_SDMMC_MASK_CCRCFAILIE           (1 << 0)  /* Bit 0: Command CRC fail interrupt enable */
+#define STM32_SDMMC_MASK_DCRCFAILIE           (1 << 1)  /* Bit 1: Data CRC fail interrupt enable */
+#define STM32_SDMMC_MASK_CTIMEOUTIE           (1 << 2)  /* Bit 2: Command timeout interrupt enable */
+#define STM32_SDMMC_MASK_DTIMEOUTIE           (1 << 3)  /* Bit 3: Data timeout interrupt enable */
+#define STM32_SDMMC_MASK_TXUNDERRIE           (1 << 4)  /* Bit 4: Tx FIFO underrun error interrupt enable */
+#define STM32_SDMMC_MASK_RXOVERRIE            (1 << 5)  /* Bit 5: Rx FIFO overrun error interrupt enable */
+#define STM32_SDMMC_MASK_CMDRENDIE            (1 << 6)  /* Bit 6: Command response received interrupt enable */
+#define STM32_SDMMC_MASK_CMDSENTIE            (1 << 7)  /* Bit 7: Command sent interrupt enable */
+#define STM32_SDMMC_MASK_DATAENDIE            (1 << 8)  /* Bit 8: Data end interrupt enable */
+#define STM32_SDMMC_MASK_DHOLDIE              (1 << 9)  /* Bit 9: Data hold interrupt enable */
+#define STM32_SDMMC_MASK_DBCKENDIE            (1 << 10) /* Bit 10: Data block end interrupt enable */
+#define STM32_SDMMC_MASK_DABOTRTIE            (1 << 11) /* Bit 11: Data transfer aborted interrupt enable */
+#define STM32_SDMMC_MASK_TXFIFOHEIE           (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */
+#define STM32_SDMMC_MASK_RXFIFOHFIE           (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */
+#define STM32_SDMMC_MASK_RXFIFOFIE            (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */
+#define STM32_SDMMC_MASK_TXFIFOFIE            (1 << 18) /* Bit 18: Tx FIFO full interrupt enable */
+#define STM32_SDMMC_MASK_BUSYD0ENDIE          (1 << 21) /* Bit 21: BUSYD0END interrupt enable */
+#define STM32_SDMMC_MASK_SDIOITIE             (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */
+#define STM32_SDMMC_MASK_ACKFAILIE            (1 << 23) /* Bit 23: Acknowledgment Fail interrupt enable */
+#define STM32_SDMMC_MASK_ACKTIMEOUTIE         (1 << 24) /* Bit 24: Acknowledgment timeout interrupt enable */
+#define STM32_SDMMC_MASK_VSWENDIE             (1 << 25) /* Bit 25: Voltage switch critical timing section completion interrupt enable */
+#define STM32_SDMMC_MASK_CKSTOPIE             (1 << 26) /* Bit 26: Voltage Switch clock stopped interrupt enable */
+#define STM32_SDMMC_MASK_IDMABTCIE            (1 << 28) /* Bit 28: IDMA buffer transfer complete interrupt enable */
+
+#define STM32_SDMMC_MASK_RESET                (0)
+
+#define STM32_SDMMC_IDMACTRLR_IDMAEN          (1 << 0)
+
+#define STM32_SDMMC_FIFOCNT_SHIFT             (0)
+#define STM32_SDMMC_FIFOCNT_MASK              (0x0ffffff << STM32_SDMMC_FIFOCNT_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SDMMC_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_spi.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h
similarity index 99%
rename from arch/arm/src/stm32h7/chip/stm32h7x3xx_spi.h
rename to arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h
index 3f68dc45710..adc8e857806 100644
--- a/arch/arm/src/stm32h7/chip/stm32h7x3xx_spi.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32h7x3xx_spi.h
+ * arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Mateusz Szafoni 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_SPI_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_SPI_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SPI_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SPI_H
 
 /************************************************************************************
  * Included Files
@@ -451,4 +451,4 @@
 
 
 #endif /* CONFIG_STM32H7_STM32H7X3XX */
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_SPI_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SPI_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_syscfg.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h
similarity index 97%
rename from arch/arm/src/stm32h7/chip/stm32h7x3xx_syscfg.h
rename to arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h
index c2a8e547ba1..fed8d8390d8 100644
--- a/arch/arm/src/stm32h7/chip/stm32h7x3xx_syscfg.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32h7x3xx_syscfg.h
+ * arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 
 #include 
 #include "chip.h"
-#include "chip/stm32_memorymap.h"
+#include "hardware/stm32_memorymap.h"
 
 #if defined(CONFIG_STM32H7_STM32H7X3XX)
 
@@ -210,4 +210,4 @@
 #define SYSCFG_UR17_
 
 #endif /* CONFIG_STM32H7_STM32H7X3XX */
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SYSCFG_H */
diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_uart.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h
similarity index 98%
rename from arch/arm/src/stm32h7/chip/stm32h7x3xx_uart.h
rename to arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h
index fc93b15c6eb..263f60b42f5 100644
--- a/arch/arm/src/stm32h7/chip/stm32h7x3xx_uart.h
+++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32h7/chip/stm32h7x3xx_uart.h
+ * arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_UART_H
-#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_UART_H
+#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_UART_H
+#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_UART_H
 
 /************************************************************************************
  * Included Files
@@ -42,7 +42,7 @@
 
 #include 
 #include "chip.h"
-#include "chip/stm32_memorymap.h"
+#include "hardware/stm32_memorymap.h"
 
 #if defined(CONFIG_STM32H7_STM32H7X3XX)
 
@@ -282,7 +282,7 @@
 #define USART_CR3_RTSE            (1 << 8)  /* Bit 8:  RTS Enable */
 #define USART_CR3_CTSE            (1 << 9)  /* Bit 9:  CTS Enable */
 #define USART_CR3_CTSIE           (1 << 10) /* Bit 10: CTS Interrupt Enable */
-#define USART_CR1_ONEBIT          (1 << 11) /* Bit 11: One sample bit method enable */
+#define USART_CR3_ONEBIT          (1 << 11) /* Bit 11: One sample bit method enable */
 #define USART_CR3_OVRDIS          (1 << 12) /* Bit 12: Overrun Disable */
 #define USART_CR3_DDRE            (1 << 13) /* Bit 13: DMA Disable on Reception Error */
 #define USART_CR3_DEM             (1 << 14) /* Bit 14: Driver enable mode */
@@ -423,4 +423,4 @@
 # define USART_PRESC_DIV256       (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */
 
 #endif /* CONFIG_STM32H7_STM32H7X3XX */
-#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_UART_H */
diff --git a/arch/arm/src/stm32h7/stm32_allocateheap.c b/arch/arm/src/stm32h7/stm32_allocateheap.c
index 5b81a89b343..cbc1456d614 100644
--- a/arch/arm/src/stm32h7/stm32_allocateheap.c
+++ b/arch/arm/src/stm32h7/stm32_allocateheap.c
@@ -57,7 +57,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/stm32_memorymap.h"
+#include "hardware/stm32_memorymap.h"
 #include "stm32_mpuinit.h"
 // TODO: #include "stm32_dtcm.h"
 
diff --git a/arch/arm/src/stm32h7/stm32_dma.c b/arch/arm/src/stm32h7/stm32_dma.c
index 8fba91912e0..d26758e5c55 100644
--- a/arch/arm/src/stm32h7/stm32_dma.c
+++ b/arch/arm/src/stm32h7/stm32_dma.c
@@ -53,9 +53,9 @@
 #include "up_internal.h"
 #include "sched/sched.h"
 #include "stm32_dma.h"
-#include "chip/stm32_bdma.h"
-#include "chip/stm32_mdma.h"
-#include "chip/stm32_dmamux.h"
+#include "hardware/stm32_bdma.h"
+#include "hardware/stm32_mdma.h"
+#include "hardware/stm32_dmamux.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32h7/stm32_dma.h b/arch/arm/src/stm32h7/stm32_dma.h
index f6376461da0..94c67666a7c 100644
--- a/arch/arm/src/stm32h7/stm32_dma.h
+++ b/arch/arm/src/stm32h7/stm32_dma.h
@@ -43,8 +43,8 @@
 #include 
 #include 
 
-#include "chip/stm32_dma.h"
-#include "chip/stm32_dmamux.h"
+#include "hardware/stm32_dma.h"
+#include "hardware/stm32_dmamux.h"
 
 /* These definitions provide the bit encoding of the 'status' parameter passed to the
  * DMA callback function (see dma_callback_t).
diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c
new file mode 100644
index 00000000000..84ef06053c6
--- /dev/null
+++ b/arch/arm/src/stm32h7/stm32_ethernet.c
@@ -0,0 +1,4410 @@
+/****************************************************************************
+ * arch/arm/src/stm32h7/stm32_ethernet.c
+ *
+ *   Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
+ *
+ *   Author: Gregory Nutt 
+ *   Author: Jukka Laitinen 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#if defined(CONFIG_NET_PKT)
+#  include 
+#endif
+
+#include 
+#include "up_internal.h"
+#include "barriers.h"
+
+#include "hardware/stm32_syscfg.h"
+#include "hardware/stm32_pinmap.h"
+#include "stm32_gpio.h"
+#include "stm32_rcc.h"
+#include "stm32_ethernet.h"
+
+#include 
+
+/* STM32H7_NETHERNET determines the number of physical interfaces that can
+ * be supported by the hardware.  CONFIG_STM32H7_ETHMAC will defined if
+ * any STM32H7 Ethernet support is enabled in the configuration.
+ */
+
+#if STM32H7_NETHERNET > 0 && defined(CONFIG_STM32H7_ETHMAC)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Memory synchronization */
+
+#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0)
+
+/* Configuration ************************************************************/
+
+/* See configs/stm3240g-eval/README.txt for an explanation of the
+ * configuration settings.
+ */
+
+#if STM32H7_NETHERNET > 1
+#  error "Logic to support multiple Ethernet interfaces is incomplete"
+#endif
+
+/* If processing is not done at the interrupt level, then work queue support
+ * is required.
+ */
+
+#if !defined(CONFIG_SCHED_WORKQUEUE)
+#  error Work queue support is required
+#else
+
+/* Select work queue */
+
+#  if defined(CONFIG_STM32H7_ETHMAC_HPWORK)
+#    define ETHWORK HPWORK
+#  elif defined(CONFIG_STM32H7_ETHMAC_LPWORK)
+#    define ETHWORK LPWORK
+#  else
+#    define ETHWORK LPWORK
+#  endif
+#endif
+
+#ifndef CONFIG_STM32H7_PHYADDR
+#  error "CONFIG_STM32H7_PHYADDR must be defined in the NuttX configuration"
+#endif
+
+#if !defined(CONFIG_STM32H7_MII) && !defined(CONFIG_STM32H7_RMII)
+#  warning "Neither CONFIG_STM32H7_MII nor CONFIG_STM32H7_RMII defined"
+#endif
+
+#if defined(CONFIG_STM32H7_MII) && defined(CONFIG_STM32H7_RMII)
+#  error "Both CONFIG_STM32H7_MII and CONFIG_STM32H7_RMII defined"
+#endif
+
+#ifdef CONFIG_STM32H7_MII
+#  if !defined(CONFIG_STM32H7_MII_MCO1) && !defined(CONFIG_STM32H7_MII_MCO2) && \
+      !defined(CONFIG_STM32H7_MII_EXTCLK)
+#    warning "Neither CONFIG_STM32H7_MII_MCO1, CONFIG_STM32H7_MII_MCO2, nor CONFIG_STM32H7_MII_EXTCLK defined"
+#  endif
+#  if defined(CONFIG_STM32H7_MII_MCO1) && defined(CONFIG_STM32H7_MII_MCO2)
+#    error "Both CONFIG_STM32H7_MII_MCO1 and CONFIG_STM32H7_MII_MCO2 defined"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32H7_RMII
+#  if !defined(CONFIG_STM32H7_RMII_MCO1) && !defined(CONFIG_STM32H7_RMII_MCO2) && \
+      !defined(CONFIG_STM32H7_RMII_EXTCLK)
+#    warning "Neither CONFIG_STM32H7_RMII_MCO1, CONFIG_STM32H7_RMII_MCO2, nor CONFIG_STM32H7_RMII_EXTCLK defined"
+#  endif
+#  if defined(CONFIG_STM32H7_RMII_MCO1) && defined(CONFIG_STM32H7_RMII_MCO2)
+#    error "Both CONFIG_STM32H7_RMII_MCO1 and CONFIG_STM32H7_RMII_MCO2 defined"
+#  endif
+#endif
+
+#ifdef CONFIG_STM32H7_AUTONEG
+#  ifndef CONFIG_STM32H7_PHYSR
+#    error "CONFIG_STM32H7_PHYSR must be defined in the NuttX configuration"
+#  endif
+#  ifdef CONFIG_STM32H7_PHYSR_ALTCONFIG
+#    ifndef CONFIG_STM32H7_PHYSR_ALTMODE
+#      error "CONFIG_STM32H7_PHYSR_ALTMODE must be defined in the NuttX configuration"
+#    endif
+#    ifndef CONFIG_STM32H7_PHYSR_10HD
+#      error "CONFIG_STM32H7_PHYSR_10HD must be defined in the NuttX configuration"
+#    endif
+#    ifndef CONFIG_STM32H7_PHYSR_100HD
+#      error "CONFIG_STM32H7_PHYSR_100HD must be defined in the NuttX configuration"
+#    endif
+#    ifndef CONFIG_STM32H7_PHYSR_10FD
+#      error "CONFIG_STM32H7_PHYSR_10FD must be defined in the NuttX configuration"
+#    endif
+#    ifndef CONFIG_STM32H7_PHYSR_100FD
+#      error "CONFIG_STM32H7_PHYSR_100FD must be defined in the NuttX configuration"
+#    endif
+#  else
+#    ifndef CONFIG_STM32H7_PHYSR_SPEED
+#      error "CONFIG_STM32H7_PHYSR_SPEED must be defined in the NuttX configuration"
+#    endif
+#    ifndef CONFIG_STM32H7_PHYSR_100MBPS
+#      error "CONFIG_STM32H7_PHYSR_100MBPS must be defined in the NuttX configuration"
+#    endif
+#    ifndef CONFIG_STM32H7_PHYSR_MODE
+#      error "CONFIG_STM32H7_PHYSR_MODE must be defined in the NuttX configuration"
+#    endif
+#    ifndef CONFIG_STM32H7_PHYSR_FULLDUPLEX
+#      error "CONFIG_STM32H7_PHYSR_FULLDUPLEX must be defined in the NuttX configuration"
+#    endif
+#  endif
+#endif
+
+#ifdef CONFIG_STM32H7_ETH_PTP
+#  warning "CONFIG_STM32H7_ETH_PTP is not yet supported"
+#endif
+
+#undef CONFIG_STM32H7_ETH_HWCHECKSUM
+
+/* Add 4 to the configured buffer size to account for the 2 byte checksum
+ * memory needed at the end of the maximum size packet.  Buffer sizes must
+ * be an even multiple of 4, 8, or 16 bytes (depending on buswidth).  We
+ * will use the 16-byte alignment in all cases.
+ */
+
+#define OPTIMAL_ETH_BUFSIZE ((CONFIG_NET_ETH_PKTSIZE + 4 + 15) & ~15)
+
+#ifdef CONFIG_STM32H7_ETH_BUFSIZE
+#  define ETH_BUFSIZE CONFIG_STM32H7_ETH_BUFSIZE
+#else
+#  define ETH_BUFSIZE OPTIMAL_ETH_BUFSIZE
+#endif
+
+#if ETH_BUFSIZE > ETH_CTX_TDES2_MSS_MASK
+#  error "ETH_BUFSIZE is too large"
+#endif
+
+#if (ETH_BUFSIZE & 15) != 0
+#  error "ETH_BUFSIZE must be aligned"
+#endif
+
+#if ETH_BUFSIZE != OPTIMAL_ETH_BUFSIZE
+#  warning "You using an incomplete/untested configuration"
+#endif
+
+#ifndef CONFIG_STM32H7_ETH_NRXDESC
+#  define CONFIG_STM32H7_ETH_NRXDESC 8
+#endif
+#ifndef CONFIG_STM32H7_ETH_NTXDESC
+#  define CONFIG_STM32H7_ETH_NTXDESC 4
+#endif
+
+/* We need at least one more free buffer than transmit buffers */
+
+#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32H7_ETH_NTXDESC+1)
+
+/* Buffers use fro DMA access must begin on an address aligned with the
+ * D-Cache line and must be an even multiple of the D-Cache line size.
+ * These size/alignment requirements are necessary so that D-Cache flush
+ * and invalidate operations will not have any additional effects.
+ *
+ * The TX and RX descriptors are 16 bytes in size
+ */
+
+#define DMA_BUFFER_MASK    (ARMV7M_DCACHE_LINESIZE - 1)
+#define DMA_ALIGN_UP(n)    (((n) + DMA_BUFFER_MASK) & ~DMA_BUFFER_MASK)
+#define DMA_ALIGN_DOWN(n)  ((n) & ~DMA_BUFFER_MASK)
+
+#define DESC_SIZE       16
+#define DESC_PADSIZE        DMA_ALIGN_UP(DESC_SIZE)
+#define ALIGNED_BUFSIZE     DMA_ALIGN_UP(ETH_BUFSIZE)
+
+#define RXTABLE_SIZE        (STM32H7_NETHERNET * CONFIG_STM32H7_ETH_NRXDESC)
+#define TXTABLE_SIZE        (STM32H7_NETHERNET * CONFIG_STM32H7_ETH_NTXDESC)
+
+#define RXBUFFER_SIZE       (CONFIG_STM32H7_ETH_NRXDESC * ALIGNED_BUFSIZE)
+#define RXBUFFER_ALLOC      (STM32H7_NETHERNET * RXBUFFER_SIZE)
+
+#define TXBUFFER_SIZE       (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE)
+#define TXBUFFER_ALLOC      (STM32H7_NETHERNET * TXBUFFER_SIZE)
+
+/* Extremely detailed register debug that you would normally never want
+ * enabled.
+ */
+
+#ifndef CONFIG_DEBUG_NET_INFO
+#  undef CONFIG_STM32H7_ETHMAC_REGDEBUG
+#endif
+
+/* Clocking *****************************************************************/
+
+/* Set MACMDIOAR CR bits depending on HCLK setting */
+
+#if STM32_HCLK_FREQUENCY >= 20000000 && STM32_HCLK_FREQUENCY < 35000000
+#  define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_DIV16
+#elif STM32_HCLK_FREQUENCY >= 35000000 && STM32_HCLK_FREQUENCY < 60000000
+#  define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_DIV26
+#elif STM32_HCLK_FREQUENCY >= 60000000 && STM32_HCLK_FREQUENCY < 100000000
+#  define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_DIV42
+#elif STM32_HCLK_FREQUENCY >= 100000000 && STM32_HCLK_FREQUENCY < 150000000
+#  define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_DIV62
+#elif STM32_HCLK_FREQUENCY >= 150000000 && STM32_HCLK_FREQUENCY <= 216000000
+#  define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_DIV102
+#else
+#  error "STM32_HCLK_FREQUENCY not supportable"
+#endif
+
+/* Timing *******************************************************************/
+
+/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
+ * second
+ */
+
+#define STM32_WDDELAY     (1*CLK_TCK)
+
+/* TX timeout = 1 minute */
+
+#define STM32_TXTIMEOUT   (60*CLK_TCK)
+
+/* PHY reset/configuration delays in milliseconds */
+
+#define PHY_RESET_DELAY   (65)
+#define PHY_CONFIG_DELAY  (1000)
+
+/* PHY read/write delays in loop counts */
+
+#define PHY_READ_TIMEOUT  (0x0004ffff)
+#define PHY_WRITE_TIMEOUT (0x0004ffff)
+#define PHY_RETRY_TIMEOUT (0x0004ffff)
+
+/* Register values **********************************************************/
+
+/* Clear the MACCR bits that will be setup during MAC initialization (or that
+ * are cleared unconditionally).  Per the reference manual, all reserved bits
+ * must be retained at their reset value.
+ *
+ * ETH_MACCR_RE     Bit 0:  Receiver enable
+ * ETH_MACCR_TE     Bit 1:  Transmitter enable
+ * ETH_MACCR_PRELEN Bits 2-3: Preamble length for transmit packets
+ * ETH_MACCR_DC     Bit 4:  Deferral check
+ * ETH_MACCR_BL     Bits 5-6: Back-off limit
+ * ETH_MACCR_DR     Bit 8:  Retry disable
+ * ETH_MACCR_DCRS   Bit 9:  Carrier sense disable
+ * ETH_MACCR_DO     Bit 10: Receive own disable
+ * ETH_MACCR_LM     Bit 12: Loopback mode
+ * ETH_MACCR_DM     Bit 13: Duplex mode
+ * ETH_MACCR_FES    Bit 14: Fast Ethernet speed
+ * ETH_MACCR_JE     Bit 16: Jumbo packet enable
+ * ETH_MACCR_JD     Bit 17: Jabber disable
+ * ETH_MACCR_WD     Bit 19: Watchdog disable
+ * ETH_MACCR_ACS    Bit 20: Automatic pad/CRC stripping
+ * ETH_MACCR_CST    Bit 21: CRC stripping for Type frames
+ * ETH_MACCR_S2KP   Bit 22: IEEE 802.3as Support for 2K Packets
+ * ETH_MACCR_GPSLCE Bit 23: Giant Packet Size Limit Control Enable
+ * ETH_MACCR_IPG    Bits 24-26: Inter-packet gap
+ * ETH_MACCR_IPC    Bit 27: IPv4 checksum offload
+ * ETH_MACCR_SARC   Bits 28-30: Src address insertion or replacement
+ * ETH_MACCR_ARPEN  Bit 31: ARP Offload Enable
+ */
+
+#define MACCR_CLEAR_BITS                                                \
+  (ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_PRELEN_MASK | ETH_MACCR_DC | \
+   ETH_MACCR_BL_MASK | ETH_MACCR_DR | ETH_MACCR_DCRS | ETH_MACCR_DO |   \
+   ETH_MACCR_LM | ETH_MACCR_DM | ETH_MACCR_FES | ETH_MACCR_JE |         \
+   ETH_MACCR_JD | ETH_MACCR_WD | ETH_MACCR_ACS | ETH_MACCR_CST |        \
+   ETH_MACCR_S2KP | ETH_MACCR_GPSLCE | ETH_MACCR_IPG_MASK |             \
+   ETH_MACCR_IPC | ETH_MACCR_SARC_MASK | ETH_MACCR_ARPEN)
+
+/* The following bits are set or left zero unconditionally in all modes.
+ *
+ * ETH_MACCR_RE    Receiver enable                0 (disabled)
+ * ETH_MACCR_TE    Transmitter enable             0 (disabled)
+ * ETH_MACCR_DC    Deferral check                 0 (disabled)
+ * ETH_MACCR_BL    Back-off limit                 0 (10)
+ * ETH_MACCR_ACS   Automatic pad/CRC stripping    0 (disabled)
+ * ETH_MACCR_DR    Retry disable                  1 (disabled)
+ * ETH_MACCR_IPC   IPv4 checksum offload          Depends on CONFIG_STM32H7_ETH_HWCHECKSUM
+ * ETH_MACCR_LM    Loopback mode                  0 (disabled)
+ * ETH_MACCR_DO    Receive own disable            0 (enabled)
+ * ETH_MACCR_DCRS  Carrier sense disable          0 (enabled)
+ * ETH_MACCR_IPG   Inter-packet gap               0 (96 bits)
+ * ETH_MACCR_JD    Jabber disable                 0 (enabled)
+ * ETH_MACCR_WD    Watchdog disable               0 (enabled)
+ * ETH_MACCR_CST   CRC stripping for Type frames  0 (disabled)
+ *
+ * The following are set conditionally based on mode and speed.
+ *
+ * ETH_MACCR_DM       Duplex mode                    Depends on priv->fduplex
+ * ETH_MACCR_FES      Fast Ethernet speed            Depends on priv->mbps100
+ */
+
+#ifdef CONFIG_STM32H7_ETH_HWCHECKSUM
+#  define MACCR_SET_BITS                                                \
+  (ETH_MACCR_BL_10 | ETH_MACCR_DR | ETH_MACCR_IPC | ETH_MACCR_IPG(96))
+#else
+#  define MACCR_SET_BITS                                \
+  (ETH_MACCR_BL_10 | ETH_MACCR_DR | ETH_MACCR_IPG(96))
+#endif
+
+/* Clear the MACCR bits that will be setup during MAC initialization (or that
+ * are cleared unconditionally).  Per the reference manual, all reserved bits
+ * must be retained at their reset value.
+ *
+ * ETH_MACPFR_PM    Bit 0: Promiscuous mode
+ * ETH_MACPFR_HUC   Bit 1: Hash unicast
+ * ETH_MACPFR_HMC   Bit 2: Hash multicast
+ * ETH_MACPFR_DAIF  Bit 3: Destination address inverse filtering
+ * ETH_MACPFR_PM    Bit 4: Pass all multicast
+ * ETH_MACPFR_DBF   Bit 5: Broadcast frames disable
+ * ETH_MACPFR_PCF   Bits 6-7: Pass control frames
+ * ETH_MACPFR_SAIF  Bit 8: Source address inverse filtering
+ * ETH_MACPFR_SAF   Bit 9: Source address filter
+ * ETH_MACPFR_HPF   Bit 10: Hash or perfect filter
+ * ETH_MACPFR_VTFE  Bit 16: VLAN Tag Filter Enable
+ * ETH_MACPFR_IPFE  Bit 20: Layer 3 and Layer 4 Filter Enable
+ * ETH_MACPFR_DNTU  Bit 21: Drop Non-TCP/UDP over IP Packets
+ * ETH_MACPFR_RA    Bit 31: Receive all
+ */
+
+#define MACPFR_CLEAR_BITS                                               \
+  (ETH_MACPFR_PM | ETH_MACPFR_HUC | ETH_MACPFR_HMC | ETH_MACPFR_DAIF |  \
+   ETH_MACPFR_PM | ETH_MACPFR_DBF | ETH_MACPFR_PCF_MASK | ETH_MACPFR_SAIF | \
+   ETH_MACPFR_SAF | ETH_MACPFR_HPF | ETH_MACPFR_VTFE | ETH_MACPFR_IPFE | \
+   ETH_MACPFR_DNTU | ETH_MACPFR_RA)
+
+/* The following bits are set or left zero unconditionally in all modes.
+ *
+ * ETH_MACPFR_PM    Promiscuous mode                       0 (disabled)
+ * ETH_MACPFR_HU    Hash unicast                           0 (perfect dest filtering)
+ * ETH_MACPFR_HM    Hash multicast                         0 (perfect dest filtering)
+ * ETH_MACPFR_DAIF  Destination address inverse filtering  0 (normal)
+ * ETH_MACPFR_PAM   Pass all multicast                     0 (Depends on HM bit)
+ * ETH_MACPFR_BFD   Broadcast frames disable               0 (enabled)
+ * ETH_MACPFR_PCF   Pass control frames                    1 (block all but PAUSE)
+ * ETH_MACPFR_SAIF  Source address inverse filtering       0 (not used)
+ * ETH_MACPFR_SAF   Source address filter                  0 (disabled)
+ * ETH_MACPFR_HPF   Hash or perfect filter                 0 (Only matching frames passed)
+ * ETH_MACPFR_RA    Receive all                            1 (enabled)
+ */
+
+/* TODO: use proper mac filtering and not RA */
+
+#define MACPFR_SET_BITS (ETH_MACPFR_RA | ETH_MACPFR_PCF_PAUSE)
+
+/* Clear the MACQTXFCR and MACRXFCR bits that will be setup during MAC
+ * initialization (or that are cleared unconditionally).  Per the reference
+ * manual, all reserved bits must be retained at their reset value.
+ *
+ * ETH_MACQTXFCR_FCB_BPA Bit 0: Flow control busy/back pressure activate
+ * ETH_MACQTXFCR_TFE     Bit 1: Transmit flow control enable
+
+ * ETH_MACQTXFCR_PLT     Bits 4-6: Pause low threshold
+ * ETH_MACQTXFCR_DZPQ    Bit 7: Zero-quanta pause disable
+ * ETH_MACQTXFCR_PT      Bits 16-31: Pause time
+
+ * ETH_MACRXFCR_RFE      Bit 0: Receive flow control enable
+ * ETH_MACRXFCR_UP       Bit 1: Unicast pause frame detect
+ */
+
+#define MACQTXFCR_CLEAR_MASK                                            \
+  (ETH_MACQTXFCR_FCB_BPA | ETH_MACQTXFCR_TFE |                          \
+   ETH_MACQTXFCR_PLT_MASK | ETH_MACQTXFCR_DZPQ | ETH_MACQTXFCR_PT_MASK)
+
+#define MACRXFCR_CLEAR_MASK                     \
+  (ETH_MACRXFCR_RFE | ETH_MACRXFCR_UP)
+
+/* The following bits are set or left zero unconditionally in all modes.
+ *
+ * ETH_MACQTXFCR_FCB_BPA Flow control busy/back pressure activate   0 (no pause control frame)
+ * ETH_MACQTXFCR_TFE     Transmit flow control enable               0 (disabled)
+ * ETH_MACQTXFCR_PLT     Pause low threshold                        0 (pause time - 4)
+ * ETH_MACQTXFCR_DZPQ    Zero-quanta pause disable                  1 (disabled)
+ * ETH_MACQTXFCR_PT      Pause time                                 0
+ * ETH_MACRXFCR_RFE      Receive flow control enable                0 (disabled)
+ * ETH_MACRXFCR_UP       Unicast pause frame detect                 0 (disabled)
+ */
+
+#define MACQTXFCR_SET_MASK (ETH_MACQTXFCR_PLT_M4 | ETH_MACQTXFCR_DZPQ)
+#define MACRXFCR_SET_MASK (0)
+
+/* Clear the MTLTXQOMR bits that will be setup during MAC initialization (or that
+ * are cleared unconditionally).  Per the reference manual, all reserved bits
+ * must be retained at their reset value.
+ * ETH_MTLTXQOMR_FTQ      Bit 0: Flush Transmit Queue
+ * ETH_MTLTXQOMR_TSF      Bit 1: Transmit Store and Forward
+ * ETH_MTLTXQOMR_TXQEN    Bits 2-3: Transmit Queue Enable
+ * ETH_MTLTXQOMR_TTC      Bits 4-6: Transmit Threshold Control
+ * ETH_MTLTXQOMR_TQS      Bits 16-24: Transmit Queue Size
+ */
+
+#define MTLTXQOMR_CLEAR_MASK                            \
+  (ETH_MTLTXQOMR_FTQ | ETH_MTLTXQOMR_TSF |              \
+   ETH_MTLTXQOMR_TXQEN_MASK | ETH_MTLTXQOMR_TTC_MASK |  \
+   ETH_MTLTXQOMR_TQS_MASK)
+
+/* Clear the MTLRXQOMR bits that will be setup during MAC initialization (or that
+ * are cleared unconditionally).  Per the reference manual, all reserved bits
+ * must be retained at their reset value.
+ *
+ * ETH_MTLRXQOMR_RTC_MASK    Bits 0-1: Receive Queue Threshold Control
+ * ETH_MTLRXQOMR_FUP         Bit 3: Forward Undersized Good Packets
+ * ETH_MTLRXQOMR_FEP         Bit 4: Forward Error Packets
+ * ETH_MTLRXQOMR_RSF         Bit 5: Receive Queue Store and Forward
+ * ETH_MTLRXQOMR_DIS_TCP_EF  Bit 6: Disable Dropping of TCP/IP Checksum Error Packets
+ * ETH_MTLRXQOMR_EHFC        Bit 7: Enable Hardware Flow Control
+ * ETH_MTLRXQOMR_RFA_MASK    Bits 8-10: Threshold for Activating Flow Control
+ * ETH_MTLRXQOMR_RFD_MASK    Bits 14-16: Threshold for Deactivating Flow Control
+ * ETH_MTLRXQOMR_RQS_MASK    Bits 20-22: Receive Queue Size
+ */
+
+#define MTLRXQOMR_CLEAR_MASK                            \
+  (ETH_MTLRXQOMR_RTC_MASK | ETH_MTLRXQOMR_FUP |         \
+   ETH_MTLRXQOMR_FEP | ETH_MTLRXQOMR_RSF |              \
+   ETH_MTLRXQOMR_DIS_TCP_EF | ETH_MTLRXQOMR_EHFC |      \
+   ETH_MTLRXQOMR_RFA_MASK | ETH_MTLRXQOMR_RFD_MASK |    \
+   ETH_MTLRXQOMR_RQS_MASK)
+
+#define MTLTXQOMR_SET_MASK                                      \
+  ((0xd << ETH_MTLTXQOMR_TQS_SHIFT) | ETH_MTLTXQOMR_TTC_64 |    \
+   ETH_MTLTXQOMR_TXQEN_ENABLED | ETH_MTLTXQOMR_FTQ)
+
+/* TODO: Check whether use flow control (bits RFD, RFA EHFC) */
+
+#define MTLRXQOMR_SET_MASK                                      \
+  ((0x7 << ETH_MTLRXQOMR_RQS_SHIFT) | ETH_MTLRXQOMR_RTC_64)
+
+#ifdef CONFIG_STM32H7_ETH_HWCHECKSUM
+/* TODO */
+
+#  error CONFIG_STM32H7_ETH_HWCHECKSUM not supported
+#endif
+
+/* Clear the DMAMR bits that will be setup during MAC initialization (or that
+ * are cleared unconditionally).  Per the reference manual, all reserved bits
+ * must be retained at their reset value.
+ *
+ * ETH_DMAMR_SWR     Bit 0: Software Reset
+ * ETH_DMAMR_DA      Bit 1: DMA Tx or Rx Arbitration Scheme
+ * ETH_DMAMR_TXPR    Bit 11: Transmit priority
+ * ETH_DMAMR_PR      Bits 12-14: Priority ratio
+ * ETH_DMAMR_INTM    Bits 16-17: Interrupt Mode
+ */
+
+#define DMAMR_CLEAR_MASK                                                \
+  (ETH_DMAMR_SWR | ETH_DMAMR_DA | ETH_DMAMR_TXPR | ETH_DMAMR_PR_MASK |  \
+   ETH_DMAMR_INTM_MASK)
+
+#define DMAMR_SET_MASK (ETH_DMAMR_PR_2TO1)
+
+/* TODO: Comment these bits */
+
+#define DMACCR_CLEAR_MASK                                               \
+  ( ETH_DMACCR_MSS_MASK | ETH_DMACCR_PBLX8 | ETH_DMACCR_DSL_MASK)
+
+/* Set the descriptor skip length in 32-bit words */
+
+#define DMACCR_SET_MASK                                 \
+  (ETH_DMACCR_DSL((DESC_PADSIZE - DESC_SIZE)/4))
+
+#define DMASBMR_CLEAR_MASK                              \
+  (STM32_ETH_DMASBMR_FB | STM32_ETH_DMASBMR_AAL |       \
+   STM32_ETH_DMASBMR_MB | STM32_ETH_DMASBMR_RB)
+
+#define DMASBMR_SET_MASK                                \
+  (STM32_ETH_DMASBMR_FB | STM32_ETH_DMASBMR_AAL)
+
+#define DMACTXCR_CLEAR_MASK                                     \
+  (ETH_DMACTXCR_ST | ETH_DMACTXCR_ST | ETH_DMACTXCR_OSF |       \
+   ETH_DMACTXCR_TSE | ETH_DMACTXCR_TXPBL_MASK)
+
+#define DMACTXCR_SET_MASK                       \
+  (ETH_DMACTXCR_OSF | ETH_DMACTXCR_TXPBL(32))
+
+#define DMACRXCR_CLEAR_MASK                     \
+  (ETH_DMACRXCR_SR | ETH_DMACRXCR_RBSZ_MASK |   \
+   ETH_DMACRXCR_RXPBL_MASK | ETH_DMACRXCR_RPF)
+
+#define DMACRXCR_SET_MASK                       \
+  (ETH_DMACRXCR_RBSZ(ALIGNED_BUFSIZE) | ETH_DMACRXCR_RXPBL(32))
+
+/* Interrupt bit sets *******************************************************/
+
+/* All interrupts in the normal and abnormal interrupt summary.  Early
+ * transmit interrupt (ETI) is excluded from the abnormal set because it
+ * causes too many interrupts and is not interesting.
+ */
+
+#define ETH_DMAINT_NORMAL                                               \
+  (ETH_DMACIER_TIE | ETH_DMACIER_TBUE | ETH_DMACIER_RIE | ETH_DMACIER_ERIE)
+
+#define ETH_DMAINT_ABNORMAL                                             \
+  (ETH_DMACIER_TXSE                                                     \
+   ETH_DMACIER_RBUE | ETH_DMACIER_RSE | ETH_DMACIER_RWTE | /* ETH_DMACIER_ETIE | */ \
+   ETH_DMACIER_FBEE)
+
+/* Normal receive, transmit, error interrupt enable bit sets */
+
+#define ETH_DMAINT_RECV_ENABLE    (ETH_DMACIER_NIE | ETH_DMACIER_RIE)
+#define ETH_DMAINT_XMIT_ENABLE    (ETH_DMACIER_NIE | ETH_DMACIER_TIE)
+#define ETH_DMAINT_XMIT_DISABLE   (ETH_DMACIER_TIE)
+
+#ifdef CONFIG_DEBUG_NET
+#  define ETH_DMAINT_ERROR_ENABLE (ETH_DMACIER_AIE | ETH_DMACIER_ABNORMAL)
+#else
+#  define ETH_DMAINT_ERROR_ENABLE (0)
+#endif
+
+/* Helpers ******************************************************************/
+
+/* This is a helper pointer for accessing the contents of the Ethernet
+ * header
+ */
+
+#define BUF ((struct eth_hdr_s *)priv->dev.d_buf)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This union type forces the allocated size of TX&RX descriptors to be the
+ * padded to a exact multiple of the Cortex-M7 D-Cache line size.
+ */
+
+union stm32_desc_u
+{
+  uint8_t             pad[DESC_PADSIZE];
+  struct eth_desc_s   desc;
+};
+
+/* The stm32_ethmac_s encapsulates all state information for a single hardware
+ * interface
+ */
+
+struct stm32_ethmac_s
+{
+  uint8_t              ifup    : 1; /* true:ifup false:ifdown */
+  uint8_t              mbps100 : 1; /* 100MBps operation (vs 10 MBps) */
+  uint8_t              fduplex : 1; /* Full (vs. half) duplex */
+  uint8_t              intf;        /* Ethernet interface number */
+  WDOG_ID              txpoll;      /* TX poll timer */
+  WDOG_ID              txtimeout;   /* TX timeout timer */
+  struct work_s        irqwork;     /* For deferring interrupt work to the work queue */
+  struct work_s        pollwork;    /* For deferring poll work to the work queue */
+
+  /* This holds the information visible to the NuttX network */
+
+  struct net_driver_s  dev;         /* Interface understood by the network */
+
+  /* Used to track transmit and receive descriptors */
+
+  struct eth_desc_s *txhead;        /* Next available TX descriptor */
+  struct eth_desc_s *rxhead;        /* Next available RX descriptor */
+
+  struct eth_desc_s *txchbase;      /* TX descriptor ring base address */
+  struct eth_desc_s *rxchbase;      /* RX descriptor ring base address */
+
+  struct eth_desc_s *txtail;        /* First "in_flight" TX descriptor */
+  struct eth_desc_s *rxcurr;        /* First RX descriptor of the segment */
+  uint16_t             segments;    /* RX segment count */
+  uint16_t             inflight;    /* Number of TX transfers "in_flight" */
+  sq_queue_t           freeb;       /* The free buffer list */
+};
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* DMA buffers.  DMA buffers must:
+ *
+ * 1. Be a multiple of the D-Cache line size.  This requirement is assured
+ *    by the definition of RXDMA buffer size above.
+ * 2. Be aligned a D-Cache line boundaries, and
+ * 3. Be positioned in DMA-able memory.  This must be managed by logic
+ *    in the linker script file.
+ *
+ * These DMA buffers are defined sequentially here to best assure optimal
+ * packing of the buffers.
+ */
+
+/* Descriptor allocations */
+
+static union stm32_desc_u g_rxtable[RXTABLE_SIZE]
+__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
+static union stm32_desc_u g_txtable[TXTABLE_SIZE]
+__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
+
+/* Buffer allocations */
+
+static uint8_t g_rxbuffer[RXBUFFER_ALLOC]
+__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
+static uint8_t g_txbuffer[TXBUFFER_ALLOC]
+__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
+
+/* These are the pre-allocated Ethernet device structures */
+
+static struct stm32_ethmac_s g_stm32ethmac[STM32H7_NETHERNET];
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Register operations ******************************************************/
+
+#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG
+static uint32_t stm32_getreg(uint32_t addr);
+static void stm32_putreg(uint32_t val, uint32_t addr);
+static void stm32_checksetup(void);
+#else
+# define stm32_getreg(addr)      getreg32(addr)
+# define stm32_putreg(val,addr)  putreg32(val,addr)
+# define stm32_checksetup()
+#endif
+
+/* Free buffer management */
+
+static void stm32_initbuffer(struct stm32_ethmac_s *priv,
+                             uint8_t *txbuffer);
+static inline uint8_t *stm32_allocbuffer(struct stm32_ethmac_s *priv);
+static inline void stm32_freebuffer(struct stm32_ethmac_s *priv,
+                                    uint8_t *buffer);
+static inline bool stm32_isfreebuffer(struct stm32_ethmac_s *priv);
+
+/* Common TX logic */
+
+static int  stm32_transmit(struct stm32_ethmac_s *priv);
+static int  stm32_txpoll(struct net_driver_s *dev);
+static void stm32_dopoll(struct stm32_ethmac_s *priv);
+
+/* Interrupt handling */
+
+static void stm32_enableint(struct stm32_ethmac_s *priv, uint32_t ierbit);
+static void stm32_disableint(struct stm32_ethmac_s *priv, uint32_t ierbit);
+
+static void stm32_freesegment(struct stm32_ethmac_s *priv,
+                              struct eth_desc_s *rxfirst, int segments);
+static int  stm32_recvframe(struct stm32_ethmac_s *priv);
+static void stm32_receive(struct stm32_ethmac_s *priv);
+static void stm32_freeframe(struct stm32_ethmac_s *priv);
+static void stm32_txdone(struct stm32_ethmac_s *priv);
+
+static void stm32_interrupt_work(void *arg);
+static int  stm32_interrupt(int irq, void *context, FAR void *arg);
+
+/* Watchdog timer expirations */
+
+static void stm32_txtimeout_work(void *arg);
+static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...);
+
+static void stm32_poll_work(void *arg);
+static void stm32_poll_expiry(int argc, uint32_t arg, ...);
+
+/* NuttX callback functions */
+
+static int  stm32_ifup(struct net_driver_s *dev);
+static int  stm32_ifdown(struct net_driver_s *dev);
+
+static void stm32_txavail_work(void *arg);
+static int  stm32_txavail(struct net_driver_s *dev);
+
+#if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6)
+static int  stm32_addmac(struct net_driver_s *dev, const uint8_t *mac);
+#endif
+#ifdef CONFIG_NET_IGMP
+static int  stm32_rmmac(struct net_driver_s *dev, const uint8_t *mac);
+#endif
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+static int  stm32_ioctl(struct net_driver_s *dev, int cmd,
+                        unsigned long arg);
+#endif
+
+/* Descriptor Initialization */
+
+static void stm32_txdescinit(struct stm32_ethmac_s *priv,
+                             union stm32_desc_u *txtable);
+static void stm32_rxdescinit(struct stm32_ethmac_s *priv,
+                             union stm32_desc_u *rxtable, uint8_t *rxbuffer);
+
+/* PHY Initialization */
+
+#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
+static int  stm32_phyintenable(struct stm32_ethmac_s *priv);
+#endif
+static int  stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr,
+                          uint16_t *value);
+static int  stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr,
+                           uint16_t value, uint16_t mask);
+#ifdef CONFIG_ETH0_PHY_DM9161
+static inline int stm32_dm9161(struct stm32_ethmac_s *priv);
+#endif
+static int  stm32_phyinit(struct stm32_ethmac_s *priv);
+#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG
+static void  stm32_phyregdump(void);
+#endif
+
+/* MAC/DMA Initialization */
+
+#ifdef CONFIG_STM32H7_MII
+static inline void stm32_selectmii(void);
+#endif
+#ifdef CONFIG_STM32H7_RMII
+static inline void stm32_selectrmii(void);
+#endif
+static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv);
+static void stm32_ethreset(struct stm32_ethmac_s *priv);
+static int  stm32_macconfig(struct stm32_ethmac_s *priv);
+static void stm32_macaddress(struct stm32_ethmac_s *priv);
+#ifdef CONFIG_NET_ICMPv6
+static void stm32_ipv6multicast(struct stm32_ethmac_s *priv);
+#endif
+static int  stm32_macenable(struct stm32_ethmac_s *priv);
+static int  stm32_ethconfig(struct stm32_ethmac_s *priv);
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+/****************************************************************************
+ * Name: stm32_getreg
+ *
+ * Description:
+ *   This function may to used to intercept an monitor all register accesses.
+ *   Clearly this is nothing you would want to do unless you are debugging
+ *   this driver.
+ *
+ * Input Parameters:
+ *   addr - The register address to read
+ *
+ * Returned Value:
+ *   The value read from the register
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG
+static uint32_t stm32_getreg(uint32_t addr)
+{
+  static uint32_t prevaddr = 0;
+  static uint32_t preval   = 0;
+  static uint32_t count    = 0;
+
+  /* Read the value from the register */
+
+  uint32_t val = getreg32(addr);
+
+  /* Is this the same value that we read from the same register last time?
+   * Are we polling the register?  If so, suppress some of the output.
+   */
+
+  if (addr == prevaddr && val == preval)
+    {
+      if (count == 0xffffffff || ++count > 3)
+        {
+          if (count == 4)
+            {
+              ninfo("...\n");
+            }
+
+          return val;
+        }
+    }
+
+  /* No this is a new address or value */
+
+  else
+    {
+        /* Did we print "..." for the previous value? */
+
+        if (count > 3)
+          {
+            /* Yes.. then show how many times the value repeated */
+
+            ninfo("[repeats %d more times]\n", count - 3);
+          }
+
+      /* Save the new address, value, and count */
+
+      prevaddr = addr;
+      preval   = val;
+      count    = 1;
+    }
+
+  /* Show the register value read */
+
+  ninfo("%08x->%08x\n", addr, val);
+  return val;
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_putreg
+ *
+ * Description:
+ *   This function may to used to intercept an monitor all register accesses.
+ *   Clearly this is nothing you would want to do unless you are debugging
+ *   this driver.
+ *
+ * Input Parameters:
+ *   val - The value to write to the register
+ *   addr - The register address to read
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG
+static void stm32_putreg(uint32_t val, uint32_t addr)
+{
+  /* Show the register value being written */
+
+  ninfo("%08x<-%08x\n", addr, val);
+
+  /* Write the value */
+
+  putreg32(val, addr);
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_checksetup
+ *
+ * Description:
+ *   Show the state of critical configuration registers.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG
+static void stm32_checksetup(void)
+{
+}
+#endif
+
+/****************************************************************************
+ * Function: stm32_initbuffer
+ *
+ * Description:
+ *   Initialize the free buffer list.
+ *
+ * Parameters:
+ *   priv     - Reference to the driver state structure
+ *   txbuffer - DMA memory allocated for TX buffers.
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Called during early driver initialization before Ethernet interrupts
+ *   are enabled.
+ *
+ ****************************************************************************/
+
+static void stm32_initbuffer(struct stm32_ethmac_s *priv, uint8_t *txbuffer)
+{
+  uint8_t *buffer;
+  int i;
+
+  /* Initialize the head of the free buffer list */
+
+  sq_init(&priv->freeb);
+
+  /* Add all of the pre-allocated buffers to the free buffer list */
+
+  for (i = 0, buffer = txbuffer;
+       i < STM32_ETH_NFREEBUFFERS;
+       i++, buffer += ALIGNED_BUFSIZE)
+    {
+      sq_addlast((sq_entry_t *)buffer, &priv->freeb);
+    }
+}
+
+/****************************************************************************
+ * Function: stm32_allocbuffer
+ *
+ * Description:
+ *   Allocate one buffer from the free buffer list.
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   Pointer to the allocated buffer on success; NULL on failure
+ *
+ * Assumptions:
+ *   May or may not be called from an interrupt handler.  In either case,
+ *   global interrupts are disabled, either explicitly or indirectly through
+ *   interrupt handling logic.
+ *
+ ****************************************************************************/
+
+static inline uint8_t *stm32_allocbuffer(struct stm32_ethmac_s *priv)
+{
+  /* Allocate a buffer by returning the head of the free buffer list */
+
+  return (uint8_t *)sq_remfirst(&priv->freeb);
+}
+
+/****************************************************************************
+ * Function: stm32_freebuffer
+ *
+ * Description:
+ *   Return a buffer to the free buffer list.
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *   buffer - A pointer to the buffer to be freed
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   May or may not be called from an interrupt handler.  In either case,
+ *   global interrupts are disabled, either explicitly or indirectly through
+ *   interrupt handling logic.
+ *
+ ****************************************************************************/
+
+static inline void stm32_freebuffer(struct stm32_ethmac_s *priv,
+                                    uint8_t *buffer)
+{
+  /* Free the buffer by adding it to to the end of the free buffer list */
+
+  sq_addlast((sq_entry_t *)buffer, &priv->freeb);
+}
+
+/****************************************************************************
+ * Function: stm32_isfreebuffer
+ *
+ * Description:
+ *   Return TRUE if the free buffer list is not empty.
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   True if there are one or more buffers in the free buffer list;
+ *   false if the free buffer list is empty
+ *
+ * Assumptions:
+ *   None.
+ *
+ ****************************************************************************/
+
+static inline bool stm32_isfreebuffer(struct stm32_ethmac_s *priv)
+{
+  /* Return TRUE if the free buffer list is not empty */
+
+  return !sq_empty(&priv->freeb);
+}
+
+/****************************************************************************
+ * Function: stm32_get_next_txdesc
+ *
+ * Description:
+ *   Returns the next tx descriptor in the list
+ *
+ * Parameters:
+ *   priv - Reference to the driver state structure
+ *   curr - Pointer to a tx descriptor
+ *
+ * Returned Value:
+ *   pointer to the next tx descriptor for the current interface
+ *
+ ****************************************************************************/
+static struct eth_desc_s *stm32_get_next_txdesc(struct stm32_ethmac_s *priv,
+                                                struct eth_desc_s * curr)
+{
+  union stm32_desc_u *first =
+    &g_txtable[priv->intf * CONFIG_STM32H7_ETH_NTXDESC];
+  union stm32_desc_u *last =
+    &g_txtable[priv->intf * CONFIG_STM32H7_ETH_NTXDESC +
+               CONFIG_STM32H7_ETH_NTXDESC - 1];
+  union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1;
+
+  if (next > last)
+    {
+      next = first;
+    }
+
+  return &next->desc;
+}
+
+/****************************************************************************
+ * Function: stm32_transmit
+ *
+ * Description:
+ *   Start hardware transmission.  Called either from the txdone interrupt
+ *   handling or from watchdog based polling.
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   OK on success; a negated errno on failure
+ *
+ * Assumptions:
+ *   May or may not be called from an interrupt handler.  In either case,
+ *   global interrupts are disabled, either explicitly or indirectly through
+ *   interrupt handling logic.
+ *
+ ****************************************************************************/
+
+static int stm32_transmit(struct stm32_ethmac_s *priv)
+{
+  struct eth_desc_s *txdesc;
+  struct eth_desc_s *txfirst;
+
+  /* The internal (optimal) network buffer size may be configured to be larger
+   * than the Ethernet buffer size.
+   */
+
+#if OPTIMAL_ETH_BUFSIZE > ALIGNED_BUFSIZE
+  uint8_t *buffer;
+  int bufcount;
+  int lastsize;
+  int i;
+#endif
+
+  /* Verify that the hardware is ready to send another packet.  If we get
+   * here, then we are committed to sending a packet; Higher level logic
+   * must have assured that there is no transmission in progress.
+   */
+
+  txdesc  = priv->txhead;
+  txfirst = txdesc;
+
+  ninfo("d_len: %d d_buf: %p txhead: %p tdes3: %08x\n",
+        priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->des3);
+
+  DEBUGASSERT(txdesc && (txdesc->des3 & ETH_TDES3_RD_OWN) == 0);
+
+  /* Flush the contents of the TX buffer into physical memory */
+
+  up_clean_dcache((uintptr_t)priv->dev.d_buf,
+                  (uintptr_t)priv->dev.d_buf + priv->dev.d_len);
+
+  /* Is the size to be sent greater than the size of the Ethernet buffer? */
+
+  DEBUGASSERT(priv->dev.d_len > 0 && priv->dev.d_buf != NULL);
+
+#if OPTIMAL_ETH_BUFSIZE > ALIGNED_BUFSIZE
+  if (priv->dev.d_len > ALIGNED_BUFSIZE)
+  {
+    /* Yes... how many buffers will be need to send the packet? */
+
+    bufcount = (priv->dev.d_len + (ALIGNED_BUFSIZE - 1)) / ALIGNED_BUFSIZE;
+    lastsize = priv->dev.d_len - (bufcount - 1) * ALIGNED_BUFSIZE;
+
+    ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize);
+
+    /* Set the first segment bit in the first TX descriptor */
+
+    txdesc->des3 = ETH_TDES3_RD_FD;
+
+    /* Set up all but the last TX descriptor */
+
+    buffer = priv->dev.d_buf;
+
+    for (i = 0; i < bufcount; i++)
+      {
+          /* This could be a normal event but the design does not handle it */
+
+          DEBUGASSERT((txdesc->des3 & ETH_TDES3_RD_OWN) == 0);
+
+          /* Set the Buffer1 address pointer */
+
+          txdesc->des0 = (uint32_t)buffer;
+
+          /* Set the Buffer2 address pointer */
+
+          txdesc->des1 = 0;
+
+          /* Set the buffer size in all TX descriptors */
+
+          if (i == (bufcount - 1))
+            {
+              /* This is the last segment.  Set the last segment bit in the
+               * last TX descriptor
+               */
+
+              txdesc->des3 |= ETH_TDES3_RD_LD;
+
+              /* This segement is, most likely, of fractional buffersize */
+
+              /* ask for an interrupt when this segment transfer completes. */
+
+              txdesc->des2 = lastsize | ETH_TDES2_RD_IOC;
+              buffer        += lastsize;
+            }
+          else
+            {
+              /* This is not the last segment.  We don't want an interrupt
+               * when this segment transfer completes.
+               */
+
+              /* The size of the transfer is the whole buffer */
+
+              txdesc->des2  = ALIGNED_BUFSIZE | ETH_TDES2_RD_IOC;
+              buffer        += ALIGNED_BUFSIZE;
+            }
+
+          /* Give the descriptor to DMA */
+
+          txdesc->des3 |= ETH_TDES3_RD_OWN;
+
+          /* Flush the contents of the modified TX descriptor into physical
+           * memory.
+           */
+
+          up_clean_dcache((uintptr_t)txdesc,
+                          (uintptr_t)txdesc + sizeof(struct eth_desc_s));
+
+          /* Point to the next available TX descriptor */
+
+          txdesc = stm32_get_next_txdesc(priv, txdesc);
+        }
+    }
+  else
+#endif
+    {
+      /* Set the Buffer1 address pointer */
+
+      txdesc->des0 = (uint32_t)priv->dev.d_buf;
+
+      /* Set the Buffer2 address pointer */
+
+      txdesc->des1 = 0;
+
+      /* Set frame size, and we do
+       * want an interrupt when the transfer completes.
+       */
+
+      DEBUGASSERT(priv->dev.d_len <= CONFIG_NET_ETH_PKTSIZE);
+      txdesc->des2 = priv->dev.d_len | ETH_TDES2_RD_IOC;
+
+      /* The single descriptor is both the first and last segment. */
+
+      /* Set OWN bit of the TX descriptor des3.  This gives the buffer to
+       * Ethernet DMA
+       */
+
+      txdesc->des3 = (ETH_TDES3_RD_OWN | ETH_TDES3_RD_LD | ETH_TDES3_RD_FD);
+
+      /* Flush the contents of the modified TX descriptor into physical
+       * memory.
+       */
+
+      up_clean_dcache((uintptr_t)txdesc,
+                        (uintptr_t)txdesc + sizeof(struct eth_desc_s));
+
+      /* Point to the next available TX descriptor */
+
+      txdesc = stm32_get_next_txdesc(priv, txdesc);
+    }
+
+  /* Remember where we left off in the TX descriptor chain */
+
+  priv->txhead = txdesc;
+
+  /* Detach the buffer from priv->dev structure.  That buffer is now
+   * "in-flight".
+   */
+
+  priv->dev.d_buf = NULL;
+  priv->dev.d_len = 0;
+
+  /* If there is no other TX buffer, in flight, then remember the location
+   * of the TX descriptor.  This is the location to check for TX done events.
+   */
+
+  if (!priv->txtail)
+    {
+      DEBUGASSERT(priv->inflight == 0);
+      priv->txtail = txfirst;
+    }
+
+  /* Increment the number of TX transfer in-flight */
+
+  priv->inflight++;
+
+  ninfo("txhead: %p txtail: %p inflight: %d\n",
+        priv->txhead, priv->txtail, priv->inflight);
+
+  /* If all TX descriptors are in-flight, then we have to disable receive
+   * interrupts too.  This is because receive events can trigger more un-
+   * stoppable transmit events.
+   */
+
+  if (priv->inflight >= CONFIG_STM32H7_ETH_NTXDESC)
+    {
+      stm32_disableint(priv, ETH_DMACIER_RIE);
+    }
+
+  /* Check if the TX Buffer unavailable flag is set */
+
+  MEMORY_SYNC();
+
+  /* Enable TX interrupts */
+
+  stm32_enableint(priv, ETH_DMACIER_TIE);
+
+  /* Setup the TX timeout watchdog (perhaps restarting the timer) */
+
+  (void)wd_start(priv->txtimeout, STM32_TXTIMEOUT, stm32_txtimeout_expiry,
+                 1, (uint32_t)priv);
+
+  /* Update the tx descriptor tail pointer register to start the DMA */
+
+  putreg32((uintptr_t)txdesc, STM32_ETH_DMACTXDTPR);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Function: stm32_txpoll
+ *
+ * Description:
+ *   The transmitter is available, check if the network has any outgoing
+ *   packets ready to send.  This is a callback from devif_poll().
+ *   devif_poll() may be called:
+ *
+ *   1. When the preceding TX packet send is complete,
+ *   2. When the preceding TX packet send timesout and the interface is reset
+ *   3. During normal TX polling
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ *   OK on success; a negated errno on failure
+ *
+ * Assumptions:
+ *   May or may not be called from an interrupt handler.  In either case,
+ *   global interrupts are disabled, either explicitly or indirectly through
+ *   interrupt handling logic.
+ *
+ ****************************************************************************/
+
+static int stm32_txpoll(struct net_driver_s *dev)
+{
+  struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)dev->d_private;
+
+  DEBUGASSERT(priv->dev.d_buf != NULL);
+
+  /* If the polling resulted in data that should be sent out on the network,
+   * the field d_len is set to a value > 0.
+   */
+
+  if (priv->dev.d_len > 0)
+    {
+      /* Look up the destination MAC address and add it to the Ethernet
+       * header.
+       */
+
+#ifdef CONFIG_NET_IPv4
+#ifdef CONFIG_NET_IPv6
+      if (IFF_IS_IPv4(priv->dev.d_flags))
+#endif
+        {
+          arp_out(&priv->dev);
+        }
+#endif /* CONFIG_NET_IPv4 */
+
+#ifdef CONFIG_NET_IPv6
+#ifdef CONFIG_NET_IPv4
+      else
+#endif
+        {
+          neighbor_out(&priv->dev);
+        }
+#endif /* CONFIG_NET_IPv6 */
+
+      /* Send the packet */
+
+      stm32_transmit(priv);
+      DEBUGASSERT(dev->d_len == 0 && dev->d_buf == NULL);
+
+      /* Check if the next TX descriptor is owned by the Ethernet DMA or
+       * CPU.  We cannot perform the TX poll if we are unable to accept
+       * another packet for transmission.
+       *
+       * In a race condition, ETH_TDES3_OWN may be cleared BUT still not
+       * available because stm32_freeframe() has not yet run.  If
+       * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be
+       * nullified (and inflight should be < CONFIG_STM32H7_ETH_NTXDESC).
+       */
+
+      if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) != 0 ||
+          priv->txhead->des0 != 0)
+        {
+          /* We have to terminate the poll if we have no more descriptors
+           * available for another transfer.
+           */
+
+          return -EBUSY;
+        }
+
+      /* We have the descriptor, we can continue the poll. Allocate a new
+       * buffer for the poll.
+       */
+
+      dev->d_buf = stm32_allocbuffer(priv);
+
+      /* We can't continue the poll if we have no buffers */
+
+      if (dev->d_buf == NULL)
+        {
+          /* Terminate the poll. */
+
+          return -ENOMEM;
+        }
+    }
+
+  /* If zero is returned, the polling will continue until all connections have
+   * been examined.
+   */
+
+  return 0;
+}
+
+/****************************************************************************
+ * Function: stm32_dopoll
+ *
+ * Description:
+ *   The function is called in order to perform an out-of-sequence TX poll.
+ *   This is done:
+ *
+ *   1. After completion of a transmission (stm32_txdone),
+ *   2. When new TX data is available (stm32_txavail_process), and
+ *   3. After a TX timeout to restart the sending process
+ *      (stm32_txtimeout_process).
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Global interrupts are disabled by interrupt handling logic.
+ *
+ ****************************************************************************/
+
+static void stm32_dopoll(struct stm32_ethmac_s *priv)
+{
+  struct net_driver_s *dev = &priv->dev;
+
+  /* Check if the next TX descriptor is owned by the Ethernet DMA or
+   * CPU.  We cannot perform the TX poll if we are unable to accept
+   * another packet for transmission.
+   *
+   * In a race condition, ETH_TDES3_RD_OWN may be cleared BUT still not
+   * available because stm32_freeframe() has not yet run.  If
+   * stm32_freeframe() has run, the buffer1 pointer (des0) will be
+   * nullified (and inflight should be < CONFIG_STM32H7_ETH_NTXDESC).
+   */
+
+  if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) == 0 &&
+      priv->txhead->des0 == 0)
+    {
+      /* If we have the descriptor, then poll the network for new XMIT data.
+       * Allocate a buffer for the poll.
+       */
+
+      DEBUGASSERT(dev->d_len == 0 && dev->d_buf == NULL);
+      dev->d_buf = stm32_allocbuffer(priv);
+
+      /* We can't poll if we have no buffers */
+
+      if (dev->d_buf)
+        {
+          (void)devif_poll(dev, stm32_txpoll);
+
+          /* We will, most likely end up with a buffer to be freed.  But it
+           * might not be the same one that we allocated above.
+           */
+
+          if (dev->d_buf)
+            {
+              DEBUGASSERT(dev->d_len == 0);
+              stm32_freebuffer(priv, dev->d_buf);
+              dev->d_buf = NULL;
+            }
+        }
+    }
+}
+
+/****************************************************************************
+ * Function: stm32_enableint
+ *
+ * Description:
+ *   Enable a "normal" interrupt
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Global interrupts are disabled by interrupt handling logic.
+ *
+ ****************************************************************************/
+
+static void stm32_enableint(struct stm32_ethmac_s *priv, uint32_t ierbit)
+{
+  uint32_t regval;
+
+  /* Enable the specified "normal" interrupt */
+
+  regval  = stm32_getreg(STM32_ETH_DMACIER);
+  regval |= (ETH_DMACIER_NIE | ierbit);
+  stm32_putreg(regval, STM32_ETH_DMACIER);
+}
+
+/****************************************************************************
+ * Function: stm32_disableint
+ *
+ * Description:
+ *   Disable a normal interrupt.
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Global interrupts are disabled by interrupt handling logic.
+ *
+ ****************************************************************************/
+
+static void stm32_disableint(struct stm32_ethmac_s *priv, uint32_t ierbit)
+{
+  uint32_t regval;
+
+  /* Disable the "normal" interrupt */
+
+  regval  = stm32_getreg(STM32_ETH_DMACIER);
+  regval &= ~ierbit;
+
+  /* Are all "normal" interrupts now disabled? */
+
+  if ((regval & ETH_DMAINT_NORMAL) == 0)
+    {
+      /* Yes.. disable normal interrupts */
+
+      regval &= ~ETH_DMACIER_NIE;
+    }
+
+  stm32_putreg(regval, STM32_ETH_DMACIER);
+}
+
+/****************************************************************************
+ * Function: stm32_get_next_rxdesc
+ *
+ * Description:
+ *   Returns the next rx descriptor in the list
+ *
+ * Parameters:
+ *   priv - Reference to the driver state structure
+ *   curr - Pointer to a rx descriptor
+ *
+ * Returned Value:
+ *   pointer to the next rx descriptor for the current interface
+ *
+ ****************************************************************************/
+static struct eth_desc_s *stm32_get_next_rxdesc(struct stm32_ethmac_s *priv,
+                                                struct eth_desc_s * curr)
+{
+  union stm32_desc_u *first =
+    &g_rxtable[priv->intf * CONFIG_STM32H7_ETH_NRXDESC];
+  union stm32_desc_u *last =
+    &g_rxtable[priv->intf * CONFIG_STM32H7_ETH_NRXDESC +
+               CONFIG_STM32H7_ETH_NRXDESC - 1];
+  union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1;
+
+  if (next > last)
+    {
+      next = first;
+    }
+
+  return &next->desc;
+}
+
+/****************************************************************************
+ * Function: stm32_freesegment
+ *
+ * Description:
+ *   The function is called when a frame is received using the DMA receive
+ *   interrupt.  It scans the RX descriptors to the received frame.
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Global interrupts are disabled by interrupt handling logic.
+ *
+ ****************************************************************************/
+
+static void stm32_freesegment(struct stm32_ethmac_s *priv,
+                              struct eth_desc_s *rxfirst, int segments)
+{
+  struct eth_desc_s *rxdesc;
+  int i;
+
+  ninfo("rxfirst: %p segments: %d\n", rxfirst, segments);
+
+  /* Give the freed RX buffers back to the Ethernet MAC to be refilled */
+
+  rxdesc = rxfirst;
+  for (i = 0; i < segments; i++)
+    {
+      /* Set OWN bit in RX descriptors.  This gives the buffers back to DMA */
+
+      rxdesc->des3 = ETH_RDES3_RD_OWN | ETH_RDES3_RD_IOC | ETH_RDES3_RD_BUF1V;
+
+      /* Make sure that the modified RX descriptor is written to physical
+       * memory.
+       */
+
+      up_clean_dcache((uintptr_t)rxdesc,
+                      (uintptr_t)rxdesc + sizeof(struct eth_desc_s));
+
+      /* Update the tail pointer */
+
+      stm32_putreg((uintptr_t)rxdesc, STM32_ETH_DMACRXDTPR);
+
+      /* Get the next RX descriptor in the chain (cache coherency should not
+       * be an issue because the link address is constant.
+       */
+
+      rxdesc = stm32_get_next_rxdesc(priv, rxdesc);
+    }
+
+  /* Reset the segment management logic */
+
+  priv->rxcurr   = NULL;
+  priv->segments = 0;
+
+  /* Check if the RX Buffer unavailable flag is set */
+
+  if ((stm32_getreg(STM32_ETH_DMACSR) & ETH_DMACSR_RBU) != 0)
+    {
+      /* TODO: This is probably not needed at all? */
+
+      nerr("ETH_DMACSR_RBU\n");
+
+      /* To resume processing Rx descriptors, the application should change
+       * the ownership of the descriptor and issue a Receive Poll Demand
+       * command. If this command is not issued, the Rx process resumes when
+       * the next recognized incoming packet is received. In ring mode, the
+       * application should advance the Receive Descriptor Tail Pointer
+       * register of a channel. This bit is set only when the DMA owns the
+       * previous Rx descriptor.
+       */
+    }
+}
+
+/****************************************************************************
+ * Function: stm32_recvframe
+ *
+ * Description:
+ *   The function is called when a frame is received using the DMA receive
+ *   interrupt.  It scans the RX descriptors of the received frame.
+ *
+ *   NOTE: This function will silently discard any packets containing errors.
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   OK if a packet was successfully returned; -EAGAIN if there are no
+ *   further packets available
+ *
+ * Assumptions:
+ *   Global interrupts are disabled by interrupt handling logic.
+ *
+ ****************************************************************************/
+
+static int stm32_recvframe(struct stm32_ethmac_s *priv)
+{
+  struct eth_desc_s *rxdesc;
+  struct eth_desc_s *rxcurr;
+  uint8_t *buffer;
+  int i;
+
+  ninfo("rxhead: %p rxcurr: %p segments: %d\n",
+        priv->rxhead, priv->rxcurr, priv->segments);
+
+  /* Check if there are free buffers.  We cannot receive new frames in this
+   * design unless there is at least one free buffer.
+   */
+
+  if (!stm32_isfreebuffer(priv))
+    {
+      nerr("ERROR: No free buffers\n");
+      return -ENOMEM;
+    }
+
+  /* Scan descriptors owned by the CPU.  Scan until:
+   *
+   *   1) We find a descriptor still owned by the DMA,
+   *   2) We have examined all of the RX descriptors, or
+   *   3) All of the TX descriptors are in flight.
+   *
+   * This last case is obscure.  It is due to that fact that each packet
+   * that we receive can generate an unstoppable transmisson.  So we have
+   * to stop receiving when we can not longer transmit.  In this case, the
+   * transmit logic should also have disabled further RX interrupts.
+   */
+
+  rxdesc = priv->rxhead;
+
+  /* Forces the first RX descriptor to be re-read from physical memory */
+
+  up_invalidate_dcache((uintptr_t)rxdesc,
+                         (uintptr_t)rxdesc + sizeof(struct eth_desc_s));
+
+  for (i = 0;
+       (rxdesc->des3 & ETH_RDES3_WB_OWN) == 0 &&
+         i < CONFIG_STM32H7_ETH_NRXDESC &&
+         priv->inflight < CONFIG_STM32H7_ETH_NTXDESC;
+       i++)
+    {
+      /* Check if this is a normal descriptor */
+
+      if (!(rxdesc->des3 & ETH_RDES3_WB_CTXT))
+        {
+          /* Check if this is the first segment in the frame */
+
+          if ((rxdesc->des3 & ETH_RDES3_WB_FD) != 0 &&
+              (rxdesc->des3 & ETH_RDES3_WB_LD) == 0)
+            {
+              priv->rxcurr   = rxdesc;
+              priv->segments = 1;
+            }
+
+          /* Check if this is an intermediate segment in the frame */
+
+          else if (((rxdesc->des3 & ETH_RDES3_WB_LD) == 0) &&
+                   ((rxdesc->des3 & ETH_RDES3_WB_FD) == 0))
+            {
+              priv->segments++;
+            }
+
+          /* Otherwise, it is the last segment in the frame */
+
+          else
+            {
+              priv->segments++;
+
+              /* Check if there is only one segment in the frame */
+
+              if (priv->segments == 1)
+                {
+                  rxcurr = rxdesc;
+                }
+              else
+                {
+                  rxcurr = priv->rxcurr;
+                }
+
+              ninfo("rxhead: %p rxcurr: %p segments: %d\n",
+                    priv->rxhead, priv->rxcurr, priv->segments);
+
+              /* Check if any errors are reported in the frame */
+
+              if ((rxdesc->des3 & ETH_RDES3_WB_ES) == 0)
+                {
+                  struct net_driver_s *dev = &priv->dev;
+
+                  /* Get the Frame Length of the received packet: subtract 4
+                   * bytes of the CRC
+                   */
+
+                  dev->d_len = ((rxdesc->des3 & ETH_RDES3_WB_PL_MASK) >>
+                               ETH_RDES3_WB_PL_SHIFT) - 4;
+
+                  /* Get a buffer from the free list.  We don't even check if
+                   * this is successful because we already assure the free
+                   * list is not empty above.
+                   */
+
+                  buffer = stm32_allocbuffer(priv);
+
+                  /* Take the buffer from the RX descriptor of the first free
+                   * segment, put it into the network device structure, then
+                   * replace the buffer in the RX descriptor with the newly
+                   * allocated buffer.
+                   */
+
+                  DEBUGASSERT(dev->d_buf == NULL);
+                  dev->d_buf    = (uint8_t *)rxcurr->des0;
+                  rxcurr->des0 = (uint32_t)buffer;
+
+                  /* Make sure that the modified RX descriptor is written to
+                   * physical memory.
+                   */
+
+                  up_clean_dcache((uintptr_t)rxcurr,
+                                  (uintptr_t)rxdesc + sizeof(struct eth_desc_s));
+
+                  /* Remember where we should re-start scanning and reset the
+                   * segment scanning logic
+                   */
+
+                  priv->rxhead   = stm32_get_next_rxdesc(priv, rxdesc);
+                  stm32_freesegment(priv, rxcurr, priv->segments);
+
+                  /* Force the completed RX DMA buffer to be re-read from
+                   * physical memory.
+                   */
+
+                  up_invalidate_dcache((uintptr_t)dev->d_buf,
+                                       (uintptr_t)dev->d_buf + dev->d_len);
+
+                  ninfo("rxhead: %p d_buf: %p d_len: %d\n",
+                        priv->rxhead, dev->d_buf, dev->d_len);
+
+                  /* Return success */
+
+                  return OK;
+                }
+              else
+                {
+                  /* Drop the frame that contains the errors, reset the
+                   * segment scanning logic, and continue scanning with the
+                   * next frame.
+                   */
+
+                  nwarn("WARNING: DROPPED RX descriptor errors: %08x\n",
+                        rxdesc->des3);
+                  stm32_freesegment(priv, rxcurr, priv->segments);
+                }
+            }
+        }
+      else
+        {
+          /* Drop the context descriptors, we are not interested */
+
+          stm32_freesegment(priv, rxcurr, 1);
+        }
+
+      /* Try the next descriptor */
+
+      rxdesc = stm32_get_next_rxdesc(priv, rxdesc);
+
+      /* Force the next RX descriptor to be re-read from physical memory */
+
+      up_invalidate_dcache((uintptr_t)rxdesc,
+                           (uintptr_t)rxdesc + sizeof(struct eth_desc_s));
+    }
+
+  /* We get here after all of the descriptors have been scanned or when
+   * rxdesc points to the first descriptor owned by the DMA.  Remember where
+   * we left off.
+   */
+
+  priv->rxhead = rxdesc;
+
+  ninfo("rxhead: %p rxcurr: %p segments: %d\n",
+        priv->rxhead, priv->rxcurr, priv->segments);
+
+  return -EAGAIN;
+}
+
+/****************************************************************************
+ * Function: stm32_receive
+ *
+ * Description:
+ *   An interrupt was received indicating the availability of a new RX packet
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Global interrupts are disabled by interrupt handling logic.
+ *
+ ****************************************************************************/
+
+static void stm32_receive(struct stm32_ethmac_s *priv)
+{
+  struct net_driver_s *dev = &priv->dev;
+
+  /* Loop while while stm32_recvframe() successfully retrieves valid
+   * Ethernet frames.
+   */
+
+  while (stm32_recvframe(priv) == OK)
+    {
+#ifdef CONFIG_NET_PKT
+      /* When packet sockets are enabled, feed the frame into the packet tap */
+
+      pkt_input(&priv->dev);
+#endif
+
+      /* Check if the packet is a valid size for the network buffer
+       * configuration (this should not happen)
+       */
+
+      if (dev->d_len > CONFIG_NET_ETH_PKTSIZE)
+        {
+          nwarn("WARNING: DROPPED Too big: %d\n", dev->d_len);
+          continue;
+        }
+
+      /* We only accept IP packets of the configured type and ARP packets */
+
+#ifdef CONFIG_NET_IPv4
+      if (BUF->type == HTONS(ETHTYPE_IP))
+        {
+          ninfo("IPv4 frame\n");
+
+          /* Handle ARP on input then give the IPv4 packet to the network
+           * layer
+           */
+
+          arp_ipin(&priv->dev);
+          ipv4_input(&priv->dev);
+
+          /* If the above function invocation resulted in data that should
+           * be sent out on the network, the field  d_len will set to a
+           * value > 0.
+           */
+
+          if (priv->dev.d_len > 0)
+            {
+              /* Update the Ethernet header with the correct MAC address */
+
+#ifdef CONFIG_NET_IPv6
+              if (IFF_IS_IPv4(priv->dev.d_flags))
+#endif
+                {
+                  arp_out(&priv->dev);
+                }
+#ifdef CONFIG_NET_IPv6
+              else
+                {
+                  neighbor_out(&priv->dev);
+                }
+#endif
+
+              /* And send the packet */
+
+              stm32_transmit(priv);
+            }
+        }
+      else
+#endif
+#ifdef CONFIG_NET_IPv6
+      if (BUF->type == HTONS(ETHTYPE_IP6))
+        {
+          ninfo("Iv6 frame\n");
+
+          /* Give the IPv6 packet to the network layer */
+
+          ipv6_input(&priv->dev);
+
+          /* If the above function invocation resulted in data that should
+           * be sent out on the network, the field  d_len will set to a
+           * value > 0.
+           */
+
+          if (priv->dev.d_len > 0)
+            {
+              /* Update the Ethernet header with the correct MAC address */
+
+#ifdef CONFIG_NET_IPv4
+              if (IFF_IS_IPv4(priv->dev.d_flags))
+                {
+                  arp_out(&priv->dev);
+                }
+              else
+#endif
+#ifdef CONFIG_NET_IPv6
+                {
+                  neighbor_out(&priv->dev);
+                }
+#endif
+
+              /* And send the packet */
+
+              stm32_transmit(priv);
+            }
+        }
+      else
+#endif
+#ifdef CONFIG_NET_ARP
+      if (BUF->type == htons(ETHTYPE_ARP))
+        {
+          ninfo("ARP frame\n");
+
+          /* Handle ARP packet */
+
+          arp_arpin(&priv->dev);
+
+          /* If the above function invocation resulted in data that should
+           * be sent out on the network, the field  d_len will set to a
+           * value > 0.
+           */
+
+          if (priv->dev.d_len > 0)
+            {
+              stm32_transmit(priv);
+            }
+        }
+      else
+#endif
+        {
+          nwarn("WARNING: DROPPED Unknown type: %04x\n", BUF->type);
+        }
+
+      /* We are finished with the RX buffer.  NOTE:  If the buffer is
+       * re-used for transmission, the dev->d_buf field will have been
+       * nullified.
+       */
+
+      if (dev->d_buf)
+        {
+          /* Free the receive packet buffer */
+
+          stm32_freebuffer(priv, dev->d_buf);
+          dev->d_buf = NULL;
+          dev->d_len = 0;
+        }
+    }
+}
+
+/****************************************************************************
+ * Function: stm32_freeframe
+ *
+ * Description:
+ *   Scans the TX descriptors and frees the buffers of completed TX transfers.
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   None.
+ *
+ * Assumptions:
+ *   Global interrupts are disabled by interrupt handling logic.
+ *
+ ****************************************************************************/
+
+static void stm32_freeframe(struct stm32_ethmac_s *priv)
+{
+  struct eth_desc_s *txdesc;
+  uint32_t des3_tmp;
+  int i;
+
+  ninfo("txhead: %p txtail: %p inflight: %d\n",
+        priv->txhead, priv->txtail, priv->inflight);
+
+  /* Scan for "in-flight" descriptors owned by the CPU */
+
+  txdesc = priv->txtail;
+  if (txdesc)
+    {
+      DEBUGASSERT(priv->inflight > 0);
+
+      /* Force re-reading of the TX descriptor for physical memory */
+
+      up_invalidate_dcache((uintptr_t)txdesc,
+                           (uintptr_t)txdesc + sizeof(struct eth_desc_s));
+
+      for (i = 0; (txdesc->des3 & ETH_TDES3_RD_OWN) == 0; i++)
+        {
+          /* There should be a buffer assigned to all in-flight
+           * TX descriptors.
+           */
+
+          ninfo("txtail: %p des0: %08x des2: %08x des3: %08x\n",
+                txdesc, txdesc->des0, txdesc->des2, txdesc->des3);
+
+          DEBUGASSERT(txdesc->des0 != 0);
+
+          /* Check if this is the first segment of a TX frame. */
+
+          if ((txdesc->des3 & ETH_TDES3_RD_FD) != 0)
+            {
+              /* Yes.. Free the buffer */
+
+              stm32_freebuffer(priv, (uint8_t *)txdesc->des0);
+            }
+
+          /* In any event, make sure that des0-3 are nullified. */
+
+          txdesc->des0 = 0;
+          txdesc->des1 = 0;
+          txdesc->des2 = 0;
+          des3_tmp = txdesc->des3;
+          txdesc->des3 = 0;
+
+          /* Flush the contents of the modified TX descriptor into
+           * physical memory.
+           */
+
+          up_clean_dcache((uintptr_t)txdesc,
+                          (uintptr_t)txdesc + sizeof(struct eth_desc_s));
+
+          /* Check if this was the last segment of a TX frame */
+
+          if ((des3_tmp & ETH_TDES3_RD_LD) != 0)
+            {
+              /* Yes.. Decrement the number of frames "in-flight". */
+
+              priv->inflight--;
+
+              /* If all of the TX descriptors were in-flight, then RX
+               * interruptsmay have been disabled... we can re-enable them
+               * now.
+               */
+
+              stm32_enableint(priv, ETH_DMACIER_RIE);
+
+              /* If there are no more frames in-flight, then bail. */
+
+              if (priv->inflight <= 0)
+                {
+                  priv->txtail   = NULL;
+                  priv->inflight = 0;
+                  return;
+                }
+            }
+
+          /* Try the next descriptor in the TX chain */
+
+          txdesc = stm32_get_next_txdesc(priv, txdesc);
+
+          /* Force re-reading of the TX descriptor for physical memory */
+
+          up_invalidate_dcache((uintptr_t)txdesc,
+                               (uintptr_t)txdesc + sizeof(struct eth_desc_s));
+        }
+
+      /* We get here if (1) there are still frames "in-flight". Remember
+       * where we left off.
+       */
+
+      priv->txtail = txdesc;
+
+      ninfo("txhead: %p txtail: %p inflight: %d\n",
+            priv->txhead, priv->txtail, priv->inflight);
+    }
+}
+
+/****************************************************************************
+ * Function: stm32_txdone
+ *
+ * Description:
+ *   An interrupt was received indicating that the last TX packet(s) is done
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Global interrupts are disabled by the watchdog logic.
+ *
+ ****************************************************************************/
+
+static void stm32_txdone(struct stm32_ethmac_s *priv)
+{
+  DEBUGASSERT(priv->txtail != NULL);
+
+  /* Scan the TX descriptor change, returning buffers to free list */
+
+  stm32_freeframe(priv);
+
+  /* If no further xmits are pending, then cancel the TX timeout */
+
+  if (priv->inflight <= 0)
+    {
+      /* Cancel the TX timeout */
+
+      wd_cancel(priv->txtimeout);
+
+      /* And disable further TX interrupts. */
+
+      stm32_disableint(priv, ETH_DMACIER_TIE);
+    }
+
+  /* Then poll the network for new XMIT data */
+
+  stm32_dopoll(priv);
+}
+
+/****************************************************************************
+ * Function: stm32_interrupt_work
+ *
+ * Description:
+ *   Perform interrupt related work from the worker thread
+ *
+ * Parameters:
+ *   arg - The argument passed when work_queue() was called.
+ *
+ * Returned Value:
+ *   OK on success
+ *
+ * Assumptions:
+ *   Ethernet interrupts are disabled
+ *
+ ****************************************************************************/
+
+static void stm32_interrupt_work(void *arg)
+{
+  struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg;
+  uint32_t dmasr;
+
+  DEBUGASSERT(priv);
+
+  /* Process pending Ethernet interrupts */
+
+  net_lock();
+
+  /* Get the DMA interrupt status bits (no MAC interrupts are expected) */
+
+  dmasr = stm32_getreg(STM32_ETH_DMACSR);
+
+  /* Mask only enabled interrupts.  This depends on the fact that the
+   * interrupt related bits (0-16) correspond in these two registers.
+   */
+
+  dmasr &= stm32_getreg(STM32_ETH_DMACIER);
+
+  /* Check if there are pending "normal" interrupts */
+
+  if ((dmasr & ETH_DMACSR_NIS) != 0)
+    {
+      /* Yes.. Check if we received an incoming packet, if so, call
+       * stm32_receive()
+       */
+
+      if ((dmasr & ETH_DMACSR_RI) != 0)
+        {
+          /* Clear the pending receive interrupt */
+
+          stm32_putreg(ETH_DMACSR_RI, STM32_ETH_DMACSR);
+
+          /* Handle the received package */
+
+          stm32_receive(priv);
+        }
+
+      /* Check if a packet transmission just completed.  If so, call
+       * stm32_txdone(). This may disable further TX interrupts if there
+       * are no pending transmissions.
+       */
+
+      if ((dmasr & ETH_DMACSR_TI) != 0)
+        {
+          /* Clear the pending receive interrupt */
+
+          stm32_putreg(ETH_DMACSR_TI, STM32_ETH_DMACSR);
+
+          /* Check if there are pending transmissions */
+
+          stm32_txdone(priv);
+        }
+
+      /* Clear the pending normal summary interrupt */
+
+      stm32_putreg(ETH_DMACSR_NIS, STM32_ETH_DMACSR);
+    }
+
+  /* Handle error interrupt only if CONFIG_DEBUG_NET is eanbled */
+
+#ifdef CONFIG_DEBUG_NET
+  /* Check if there are pending "abnormal" interrupts */
+
+  if ((dmasr & ETH_DMACSR_AIS) != 0)
+    {
+      /* Just let the user know what happened */
+
+      nerr("ERROR: Abormal event(s): %08x\n", dmasr);
+
+      /* Clear all pending abnormal events */
+
+      stm32_putreg(ETH_DMAINT_ABNORMAL, STM32_ETH_DMACSR);
+
+      /* Clear the pending abnormal summary interrupt */
+
+      stm32_putreg(ETH_DMACSR_AIS, STM32_ETH_DMACSR);
+    }
+#endif
+
+  net_unlock();
+
+  /* Re-enable Ethernet interrupts at the NVIC */
+
+  up_enable_irq(STM32_IRQ_ETH);
+}
+
+/****************************************************************************
+ * Function: stm32_interrupt
+ *
+ * Description:
+ *   Hardware interrupt handler
+ *
+ * Parameters:
+ *   irq     - Number of the IRQ that generated the interrupt
+ *   context - Interrupt register state save info (architecture-specific)
+ *
+ * Returned Value:
+ *   OK on success
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int stm32_interrupt(int irq, void *context, FAR void *arg)
+{
+  struct stm32_ethmac_s *priv = &g_stm32ethmac[0];
+  uint32_t dmasr;
+
+  /* Get the DMA interrupt status bits (no MAC interrupts are expected) */
+
+  dmasr = stm32_getreg(STM32_ETH_DMACSR);
+  if (dmasr != 0)
+    {
+      /* Disable further Ethernet interrupts.  Because Ethernet interrupts
+       * are also disabled if the TX timeout event occurs, there can be no
+       * race condition here.
+       */
+
+      up_disable_irq(STM32_IRQ_ETH);
+
+      /* Check if a packet transmission just completed. */
+
+      if ((dmasr & ETH_DMACSR_TI) != 0)
+        {
+          /* If a TX transfer just completed, then cancel the TX timeout so
+           * there will be no race condition between any subsequent timeout
+           * expiration and the deferred interrupt processing.
+           */
+
+          wd_cancel(priv->txtimeout);
+        }
+
+      DEBUGASSERT(work_available(&priv->irqwork));
+
+      /* Schedule to perform the interrupt processing on the worker thread. */
+
+      work_queue(ETHWORK, &priv->irqwork, stm32_interrupt_work, priv, 0);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Function: stm32_txtimeout_work
+ *
+ * Description:
+ *   Perform TX timeout related work from the worker thread
+ *
+ * Parameters:
+ *   arg - The argument passed when work_queue() as called.
+ *
+ * Returned Value:
+ *   OK on success
+ *
+ * Assumptions:
+ *   Ethernet interrupts are disabled
+ *
+ ****************************************************************************/
+
+static void stm32_txtimeout_work(void *arg)
+{
+  struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg;
+
+  /* Reset the hardware.  Just take the interface down, then back up again. */
+
+  net_lock();
+  stm32_ifdown(&priv->dev);
+  stm32_ifup(&priv->dev);
+
+  /* Then poll for new XMIT data */
+
+  stm32_dopoll(priv);
+  net_unlock();
+}
+
+/****************************************************************************
+ * Function: stm32_txtimeout_expiry
+ *
+ * Description:
+ *   Our TX watchdog timed out.  Called from the timer interrupt handler.
+ *   The last TX never completed.  Reset the hardware and start again.
+ *
+ * Parameters:
+ *   argc - The number of available arguments
+ *   arg  - The first argument
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Global interrupts are disabled by the watchdog logic.
+ *
+ ****************************************************************************/
+
+static void stm32_txtimeout_expiry(int argc, uint32_t arg, ...)
+{
+  struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg;
+
+  nerr("ERROR: Timeout!\n");
+
+  /* Disable further Ethernet interrupts.  This will prevent some race
+   * conditions with interrupt work.  There is still a potential race
+   * condition with interrupt work that is already queued and in progress.
+   *
+   * Interrupts will be re-enabled when stm32_ifup() is called.
+   */
+
+  up_disable_irq(STM32_IRQ_ETH);
+
+  /* Schedule to perform the TX timeout processing on the worker thread. */
+
+  DEBUGASSERT(work_available(&priv->irqwork));
+
+  work_queue(ETHWORK, &priv->irqwork, stm32_txtimeout_work, priv, 0);
+}
+
+/****************************************************************************
+ * Function: stm32_poll_work
+ *
+ * Description:
+ *   Perform periodic polling from the worker thread
+ *
+ * Parameters:
+ *   arg - The argument passed when work_queue() as called.
+ *
+ * Returned Value:
+ *   OK on success
+ *
+ * Assumptions:
+ *   Ethernet interrupts are disabled
+ *
+ ****************************************************************************/
+
+static void stm32_poll_work(void *arg)
+{
+  struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg;
+  struct net_driver_s *dev  = &priv->dev;
+
+  /* Check if the next TX descriptor is owned by the Ethernet DMA or CPU.  We
+   * cannot perform the timer poll if we are unable to accept another packet
+   * for transmission.  Hmmm.. might be bug here.  Does this mean if there is
+   * a transmit in progress, we will miss TCP time state updates?
+   *
+   * In a race condition, ETH_TDES3_OWN may be cleared BUT still not available
+   * because stm32_freeframe() has not yet run.  If stm32_freeframe() has run,
+   * the buffer1 pointer (des2) will be nullified (and inflight should be <
+   * CONFIG_STM32H7_ETH_NTXDESC).
+   */
+
+  net_lock();
+  if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) == 0 &&
+      priv->txhead->des0 == 0)
+    {
+      /* If we have the descriptor, then perform the timer poll.  Allocate a
+       * buffer for the poll.
+       */
+
+      DEBUGASSERT(dev->d_len == 0 && dev->d_buf == NULL);
+      dev->d_buf = stm32_allocbuffer(priv);
+
+      /* We can't poll if we have no buffers */
+
+      if (dev->d_buf)
+        {
+          /* Update TCP timing states and poll the network for new XMIT
+           * data.
+           */
+
+          (void)devif_timer(dev, stm32_txpoll);
+
+          /* We will, most likely end up with a buffer to be freed.  But it
+           * might not be the same one that we allocated above.
+           */
+
+          if (dev->d_buf)
+            {
+              DEBUGASSERT(dev->d_len == 0);
+              stm32_freebuffer(priv, dev->d_buf);
+              dev->d_buf = NULL;
+            }
+        }
+    }
+
+  /* Setup the watchdog poll timer again */
+
+  (void)wd_start(priv->txpoll, STM32_WDDELAY, stm32_poll_expiry, 1, priv);
+  net_unlock();
+}
+
+/****************************************************************************
+ * Function: stm32_poll_expiry
+ *
+ * Description:
+ *   Periodic timer handler.  Called from the timer interrupt handler.
+ *
+ * Parameters:
+ *   argc - The number of available arguments
+ *   arg  - The first argument
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Global interrupts are disabled by the watchdog logic.
+ *
+ ****************************************************************************/
+
+static void stm32_poll_expiry(int argc, uint32_t arg, ...)
+{
+  struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg;
+
+  /* Schedule to perform the interrupt processing on the worker thread. */
+
+  if (work_available(&priv->pollwork))
+    {
+      work_queue(ETHWORK, &priv->pollwork, stm32_poll_work, priv, 0);
+    }
+  else
+    {
+      (void)wd_start(priv->txpoll, STM32_WDDELAY, stm32_poll_expiry, 1, priv);
+    }
+}
+
+/****************************************************************************
+ * Function: stm32_ifup
+ *
+ * Description:
+ *   NuttX Callback: Bring up the Ethernet interface when an IP address is
+ *   provided
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int stm32_ifup(struct net_driver_s *dev)
+{
+  struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)dev->d_private;
+  int ret;
+
+#ifdef CONFIG_NET_IPv4
+  ninfo("Bringing up: %d.%d.%d.%d\n",
+        dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+        (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+#endif
+#ifdef CONFIG_NET_IPv6
+  ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n",
+        dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2],
+        dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5],
+        dev->d_ipv6addr[6], dev->d_ipv6addr[7]);
+#endif
+
+  /* Configure the Ethernet interface for DMA operation. */
+
+  ret = stm32_ethconfig(priv);
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+  /* Set and activate a timer process */
+
+  (void)wd_start(priv->txpoll, STM32_WDDELAY, stm32_poll_expiry, 1,
+                 (uint32_t)priv);
+
+  /* Enable the Ethernet interrupt */
+
+  priv->ifup = true;
+  up_enable_irq(STM32_IRQ_ETH);
+
+  stm32_checksetup();
+  return OK;
+}
+
+/****************************************************************************
+ * Function: stm32_ifdown
+ *
+ * Description:
+ *   NuttX Callback: Stop the interface.
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int stm32_ifdown(struct net_driver_s *dev)
+{
+  struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)dev->d_private;
+  irqstate_t flags;
+
+  ninfo("Taking the network down\n");
+
+  /* Disable the Ethernet interrupt */
+
+  flags = enter_critical_section();
+  up_disable_irq(STM32_IRQ_ETH);
+
+  /* Cancel the TX poll timer and TX timeout timers */
+
+  wd_cancel(priv->txpoll);
+  wd_cancel(priv->txtimeout);
+
+  /* Put the EMAC in its reset, non-operational state.  This should be
+   * a known configuration that will guarantee the stm32_ifup() always
+   * successfully brings the interface back up.
+   */
+
+  stm32_ethreset(priv);
+
+  /* Mark the device "down" */
+
+  priv->ifup = false;
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Function: stm32_txavail_work
+ *
+ * Description:
+ *   Perform an out-of-cycle poll on the worker thread.
+ *
+ * Parameters:
+ *   arg  - Reference to the NuttX driver state structure (cast to void*)
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Called on the higher priority worker thread.
+ *
+ ****************************************************************************/
+
+static void stm32_txavail_work(void *arg)
+{
+  struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)arg;
+
+  ninfo("ifup: %d\n", priv->ifup);
+
+  /* Ignore the notification if the interface is not yet up */
+
+  net_lock();
+  if (priv->ifup)
+    {
+      /* Poll the network for new XMIT data */
+
+      stm32_dopoll(priv);
+    }
+
+  net_unlock();
+}
+
+/****************************************************************************
+ * Function: stm32_txavail
+ *
+ * Description:
+ *   Driver callback invoked when new TX data is available.  This is a
+ *   stimulus perform an out-of-cycle poll and, thereby, reduce the TX
+ *   latency.
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Called in normal user mode
+ *
+ ****************************************************************************/
+
+static int stm32_txavail(struct net_driver_s *dev)
+{
+  struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)dev->d_private;
+
+  /* Is our single work structure available?  It may not be if there are
+   * pending interrupt actions and we will have to ignore the Tx
+   * availability action.
+   */
+
+  if (work_available(&priv->pollwork))
+    {
+      /* Schedule to serialize the poll on the worker thread. */
+
+      work_queue(ETHWORK, &priv->pollwork, stm32_txavail_work, priv, 0);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Function: stm32_calcethcrc
+ *
+ * Description:
+ *   Function to calculate the CRC used by STM32 to check an ethernet frame
+ *
+ * Parameters:
+ *   data   - the data to be checked
+ *   length - length of the data
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6)
+static uint32_t stm32_calcethcrc(const uint8_t *data, size_t length)
+{
+  uint32_t crc = 0xffffffff;
+  size_t i;
+  int j;
+
+  for (i = 0; i < length; i++)
+    {
+      for (j = 0; j < 8; j++)
+        {
+          if (((crc >> 31) ^ (data[i] >> j)) & 0x01)
+            {
+              /* x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */
+
+              crc = (crc << 1) ^ 0x04c11db7;
+            }
+          else
+            {
+              crc = crc << 1;
+            }
+        }
+    }
+
+  return ~crc;
+}
+#endif
+
+/****************************************************************************
+ * Function: stm32_addmac
+ *
+ * Description:
+ *   NuttX Callback: Add the specified MAC address to the hardware multicast
+ *   address filtering
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *   mac  - The MAC address to be added
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_ICMPv6)
+static int stm32_addmac(struct net_driver_s *dev, const uint8_t *mac)
+{
+  uint32_t crc;
+  uint32_t hashindex;
+  uint32_t temp;
+  uint32_t registeraddress;
+
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+
+  /* Add the MAC address to the hardware multicast hash table */
+
+  crc = stm32_calcethcrc(mac, 6);
+
+  hashindex = (crc >> 26) & 0x3f;
+
+  if (hashindex > 31)
+    {
+      registeraddress = STM32_ETH_MACHT0R;
+      hashindex -= 32;
+    }
+  else
+    {
+      registeraddress = STM32_ETH_MACHT1R;
+    }
+
+  temp  = stm32_getreg(registeraddress);
+  temp |= 1 << hashindex;
+  stm32_putreg(temp, registeraddress);
+
+  temp  = stm32_getreg(STM32_ETH_MACPFR);
+  temp |= (ETH_MACPFR_HM | ETH_MACPFR_HPF);
+  stm32_putreg(temp, STM32_ETH_MACPFR);
+
+  return OK;
+}
+#endif /* CONFIG_NET_IGMP || CONFIG_NET_ICMPv6 */
+
+/****************************************************************************
+ * Function: stm32_rmmac
+ *
+ * Description:
+ *   NuttX Callback: Remove the specified MAC address from the hardware
+ *   multicast address filtering
+ *
+ * Parameters:
+ *   dev  - Reference to the NuttX driver state structure
+ *   mac  - The MAC address to be removed
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NET_IGMP
+static int stm32_rmmac(struct net_driver_s *dev, const uint8_t *mac)
+{
+  uint32_t crc;
+  uint32_t hashindex;
+  uint32_t temp;
+  uint32_t registeraddress;
+
+  ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+
+  /* Remove the MAC address to the hardware multicast hash table */
+
+  crc = stm32_calcethcrc(mac, 6);
+
+  hashindex = (crc >> 26) & 0x3f;
+
+  if (hashindex > 31)
+    {
+      registeraddress = STM32_ETH_MACHT0R;
+      hashindex -= 32;
+    }
+  else
+    {
+      registeraddress = STM32_ETH_MACHT1R;
+    }
+
+  temp = stm32_getreg(registeraddress);
+  temp &= ~(1 << hashindex);
+  stm32_putreg(temp, registeraddress);
+
+  /* If there is no address registered any more, delete multicast filtering */
+
+  if (stm32_getreg(STM32_ETH_MACHT0R) == 0 &&
+      stm32_getreg(STM32_ETH_MACHT1R) == 0)
+    {
+      temp = stm32_getreg(STM32_ETH_MACPFR);
+      temp &= ~(ETH_MACPFR_HM | ETH_MACPFR_HPF);
+      stm32_putreg(temp, STM32_ETH_MACPFR);
+    }
+
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Function: stm32_txdescinit
+ *
+ * Description:
+ *   Initializes the DMA TX descriptors in chain mode.
+ *
+ * Parameters:
+ *   priv     - Reference to the driver state structure
+ *   txtable  - List of pre-allocated TX descriptors for the Ethernet
+ *              interface
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void stm32_txdescinit(struct stm32_ethmac_s *priv,
+                             union stm32_desc_u *txtable)
+
+{
+  struct eth_desc_s *txdesc;
+  int i;
+
+  /* priv->txhead will point to the first, available TX descriptor in the
+   * chain.  Set the priv->txhead pointer to the first descriptor in the
+   * table.
+   */
+
+  priv->txhead = &txtable[0].desc;
+  priv->txchbase = &txtable[0].desc;
+
+  /* priv->txtail will point to the first segment of the oldest pending
+   * "in-flight" TX transfer.  NULL means that there are no active TX
+   * transfers.
+   */
+
+  priv->txtail   = NULL;
+  priv->inflight = 0;
+
+  /* Initialize each TX descriptor */
+
+  for (i = 0; i < CONFIG_STM32H7_ETH_NTXDESC; i++)
+    {
+      txdesc = &txtable[i].desc;
+
+#ifdef CHECKSUM_BY_HARDWARE
+#if 0
+      /* Enable the checksum insertion for the TX frames TODO! */
+
+      txdesc->des0 |= ETH_TDES0_CIC_ALL;
+#endif
+#endif
+
+      /* Clear Buffer1 address pointer (buffers will be assigned as they
+       * are used)
+       */
+
+      txdesc->des0 = 0;
+
+      /* Clear the rest of the descriptor as well */
+
+      txdesc->des1 = 0;
+      txdesc->des2 = 0;
+      txdesc->des3 = 0;
+    }
+
+  /* Flush all of the initialized TX descriptors to physical memory */
+
+  up_clean_dcache((uintptr_t)txtable,
+                  (uintptr_t)txtable +
+                  TXTABLE_SIZE * sizeof(union stm32_desc_u));
+
+  /* Set Channel Tx descriptor ring length register
+   * TODO: Why -1 is needed? Without this the ring doesn't wrap around
+   * properly but the DMACCATXDR advances to outside the descriptor ring
+   */
+
+  stm32_putreg(CONFIG_STM32H7_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR);
+
+  /* Set Transmit Descriptor List Address Register */
+
+  stm32_putreg((uint32_t)&txtable[0].desc, STM32_ETH_DMACTXDLAR);
+
+  /* Set Transmit Descriptor Tail pointer */
+
+  stm32_putreg((uint32_t)&txtable[0].desc, STM32_ETH_DMACTXDTPR);
+}
+
+/****************************************************************************
+ * Function: stm32_rxdescinit
+ *
+ * Description:
+ *   Initializes the DMA RX descriptors in chain mode.
+ *
+ * Parameters:
+ *   priv  - Reference to the driver state structure
+ *   rxtable  - List of pre-allocated RX descriptors for the Ethernet
+ *              interface
+ *   txbuffer - List of pre-allocated DMA buffers for the Ethernet interface
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void stm32_rxdescinit(struct stm32_ethmac_s *priv,
+                             union stm32_desc_u *rxtable,
+                             uint8_t *rxbuffer)
+{
+  struct eth_desc_s *rxdesc;
+  int i;
+
+  /* priv->rxhead will point to the first,  RX descriptor in the chain.
+   * This will be where we receive the first incomplete frame.
+   */
+
+  priv->rxhead = &rxtable[0].desc;
+  priv->rxchbase = &rxtable[0].desc;
+
+  /* If we accumulate the frame in segments, priv->rxcurr points to the
+   * RX descriptor of the first segment in the current TX frame.
+   */
+
+  priv->rxcurr   = NULL;
+  priv->segments = 0;
+
+  /* Initialize each RX descriptor */
+
+  for (i = 0; i < CONFIG_STM32H7_ETH_NRXDESC; i++)
+    {
+      rxdesc = &rxtable[i].desc;
+
+      /* Set Buffer1 address pointer */
+
+      rxdesc->des0 = (uint32_t)&rxbuffer[i * ALIGNED_BUFSIZE];
+
+      /* Set Buffer1 address high bytes */
+
+      rxdesc->des1 = 0;
+
+      /* Set Buffer2 address high bytes */
+
+      rxdesc->des2 = 0;
+
+      /* Set Own bit of the RX descriptor des3 and buffer address valid */
+
+      rxdesc->des3 = ETH_RDES3_RD_OWN | ETH_RDES3_RD_IOC |
+                     ETH_RDES3_RD_BUF1V;
+    }
+
+  /* Flush all of the initialized RX descriptors to physical memory */
+
+  up_clean_dcache((uintptr_t)rxtable,
+                  (uintptr_t)rxtable +
+                  RXTABLE_SIZE * sizeof(union stm32_desc_u));
+
+  /* Set Receive Descriptor ring length register
+   * TODO: Why -1 is needed? Without this the ring doesn't wrap around
+   * properly but the DMACCARXDR advances to outside the descriptor ring
+   */
+
+  stm32_putreg(CONFIG_STM32H7_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR);
+
+  /* Set Receive Descriptor List Address Register */
+
+  stm32_putreg((uint32_t)&rxtable[0].desc, STM32_ETH_DMACRXDLAR);
+
+  /* Set Receive Descriptor Tail pointer Address */
+
+  stm32_putreg((uint32_t)&rxtable[CONFIG_STM32H7_ETH_NRXDESC - 1].desc,
+               STM32_ETH_DMACRXDTPR);
+}
+
+/****************************************************************************
+ * Function: stm32_ioctl
+ *
+ * Description:
+ *  Executes the SIOCxMIIxxx command and responds using the request struct
+ *  that must be provided as its 2nd parameter.
+ *
+ *  When called with SIOCGMIIPHY it will get the PHY address for the device
+ *  and write it to the req->phy_id field of the request struct.
+ *
+ *  When called with SIOCGMIIREG it will read a register of the PHY that is
+ *  specified using the req->reg_no struct field and then write its output
+ *  to the req->val_out field.
+ *
+ *  When called with SIOCSMIIREG it will write to a register of the PHY that
+ *  is specified using the req->reg_no struct field and use req->val_in as
+ *  its input.
+ *
+ * Parameters:
+ *   dev - Ethernet device structure
+ *   cmd - SIOCxMIIxxx command code
+ *   arg - Request structure also used to return values
+ *
+ * Returned Value: Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
+{
+#ifdef CONFIG_ARCH_PHY_INTERRUPT
+  struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)dev->d_private;
+#endif
+  int ret;
+
+  switch (cmd)
+    {
+#ifdef CONFIG_ARCH_PHY_INTERRUPT
+      case SIOCMIINOTIFY: /* Set up for PHY event notifications */
+        {
+          struct mii_iotcl_notify_s *req =
+            (struct mii_iotcl_notify_s *)((uintptr_t)arg);
+
+          ret = phy_notify_subscribe(dev->d_ifname, req->pid, req->signo,
+                                     req->arg);
+          if (ret == OK)
+            {
+              /* Enable PHY link up/down interrupts */
+
+              ret = stm32_phyintenable(priv);
+            }
+        }
+        break;
+#endif
+
+      case SIOCGMIIPHY: /* Get MII PHY address */
+        {
+          struct mii_ioctl_data_s *req =
+            (struct mii_ioctl_data_s *)((uintptr_t)arg);
+          req->phy_id = CONFIG_STM32H7_PHYADDR;
+          ret = OK;
+        }
+        break;
+
+      case SIOCGMIIREG: /* Get register from MII PHY */
+        {
+          struct mii_ioctl_data_s *req =
+            (struct mii_ioctl_data_s *)((uintptr_t)arg);
+          ret = stm32_phyread(req->phy_id, req->reg_num, &req->val_out);
+        }
+        break;
+
+      case SIOCSMIIREG: /* Set register in MII PHY */
+        {
+          struct mii_ioctl_data_s *req =
+            (struct mii_ioctl_data_s *)((uintptr_t)arg);
+          ret = stm32_phywrite(req->phy_id, req->reg_num, req->val_in,
+                               0xffff);
+        }
+        break;
+
+      default:
+        ret = -ENOTTY;
+        break;
+    }
+
+  return ret;
+}
+#endif /* CONFIG_NETDEV_PHY_IOCTL */
+
+/****************************************************************************
+ * Function: stm32_phyintenable
+ *
+ * Description:
+ *  Enable link up/down PHY interrupts.  The interrupt protocol is like this:
+ *
+ *  - Interrupt status is cleared when the interrupt is enabled.
+ *  - Interrupt occurs.  Interrupt is disabled (at the processor level) when
+ *    is received.
+ *  - Interrupt status is cleared when the interrupt is re-enabled.
+ *
+ * Parameters:
+ *   priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ *   OK on success; Negated errno (-ETIMEDOUT) on failure.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT)
+static int stm32_phyintenable(struct stm32_ethmac_s *priv)
+{
+#warning Missing logic
+  return -ENOSYS;
+}
+#endif
+
+/****************************************************************************
+ * Function: stm32_phyread
+ *
+ * Description:
+ *  Read a PHY register.
+ *
+ * Parameters:
+ *   phydevaddr - The PHY device address
+ *   phyregaddr - The PHY register address
+ *   value - The location to return the 16-bit PHY register value.
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr,
+                         uint16_t *value)
+{
+  volatile uint32_t timeout;
+  uint32_t regval;
+
+  /* Configure the MACMDIOAR register, preserving CSR Clock Range CR[2:0] bits */
+
+  regval  = stm32_getreg(STM32_ETH_MACMDIOAR);
+  regval &= ETH_MACMDIOAR_CR_MASK;
+
+  /* Set the PHY device address, PHY register address, and set the buy bit.
+   * the ETH_MACMDIOAR_GOC == 3, indicating a read operation.
+   */
+
+  regval |= (((uint32_t)phydevaddr << ETH_MACMDIOAR_PA_SHIFT) &
+            ETH_MACMDIOAR_PA_MASK);
+  regval |= (((uint32_t)phyregaddr << ETH_MACMDIOAR_RDA_SHIFT) &
+            ETH_MACMDIOAR_RDA_MASK);
+  regval |= ETH_MACMDIOAR_MB | ETH_MACMDIOAR_GOC_READ;
+
+  stm32_putreg(regval, STM32_ETH_MACMDIOAR);
+
+  /* Wait for the transfer to complete */
+
+  for (timeout = 0; timeout < PHY_READ_TIMEOUT; timeout++)
+    {
+      if ((stm32_getreg(STM32_ETH_MACMDIOAR) & ETH_MACMDIOAR_MB) == 0)
+        {
+          *value = (uint16_t)stm32_getreg(STM32_ETH_MACMDIODR);
+          return OK;
+        }
+    }
+
+  ninfo("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x\n",
+        phydevaddr, phyregaddr);
+
+  return -ETIMEDOUT;
+}
+
+/****************************************************************************
+ * Function: stm32_phywrite
+ *
+ * Description:
+ *  Write to a PHY register.
+ *
+ * Parameters:
+ *   phydevaddr - The PHY device address
+ *   phyregaddr - The PHY register address
+ *   value - The 16-bit value to write to the PHY register value.
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr,
+                          uint16_t set, uint16_t clear)
+{
+  volatile uint32_t timeout;
+  uint32_t regval;
+  uint16_t value;
+
+  /* Configure the MACMDIOAR register, preserving CSR Clock Range CR[2:0] bits */
+
+  regval  = stm32_getreg(STM32_ETH_MACMDIOAR);
+  regval &= ETH_MACMDIOAR_CR_MASK;
+
+  /* Read the existing register value, if clear mask is given */
+
+  if (clear != 0xffff)
+    {
+      if (stm32_phyread(phydevaddr, phyregaddr, &value) != OK)
+        {
+          return -ETIMEDOUT;
+        }
+
+      value &= ~clear;
+      value |= set;
+    }
+  else
+    {
+      value = set;
+    }
+
+  /* Set the PHY device address, PHY register address, and set the busy bit.
+   * the ETH_MACMDIOAR_GOC == 1, indicating a write operation.
+   */
+
+  regval |= (((uint32_t)phydevaddr << ETH_MACMDIOAR_PA_SHIFT) &
+            ETH_MACMDIOAR_PA_MASK);
+  regval |= (((uint32_t)phyregaddr << ETH_MACMDIOAR_RDA_SHIFT) &
+            ETH_MACMDIOAR_RDA_MASK);
+  regval |= (ETH_MACMDIOAR_MB | ETH_MACMDIOAR_GOC_WRITE);
+
+  /* Write the value into the MACIIDR register before setting the new
+   * MACMDIOAR register value.
+   */
+
+  stm32_putreg(value, STM32_ETH_MACMDIODR);
+  stm32_putreg(regval, STM32_ETH_MACMDIOAR);
+
+  /* Wait for the transfer to complete */
+
+  for (timeout = 0; timeout < PHY_WRITE_TIMEOUT; timeout++)
+    {
+      if ((stm32_getreg(STM32_ETH_MACMDIOAR) & ETH_MACMDIOAR_MB) == 0)
+        {
+          return OK;
+        }
+    }
+
+  ninfo("MII transfer timed out: phydevaddr: %04x phyregaddr: %04x value: %04x\n",
+        phydevaddr, phyregaddr, value);
+
+  return -ETIMEDOUT;
+}
+
+/****************************************************************************
+ * Function: stm32_dm9161
+ *
+ * Description:
+ *   Special workaround for the Davicom DM9161 PHY is required.  On power,
+ *   up, the PHY is not usually configured correctly but will work after
+ *   a powered-up reset.  This is really a workaround for some more
+ *   fundamental issue with the PHY clocking initialization, but the
+ *   root cause has not been studied (nor will it be with this workaround).
+ *
+ * Parameters:
+ *   priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ETH0_PHY_DM9161
+static inline int stm32_dm9161(struct stm32_ethmac_s *priv)
+{
+  uint16_t phyval;
+  int ret;
+
+  /* Read the PHYID1 register;  A failure to read the PHY ID is one
+   * indication that check if the DM9161 PHY CHIP is not ready.
+   */
+
+  ret = stm32_phyread(CONFIG_STM32H7_PHYADDR, MII_PHYID1, &phyval);
+  if (ret < 0)
+    {
+      nerr("ERROR: Failed to read the PHY ID1: %d\n", ret);
+      return ret;
+    }
+
+  /* If we failed to read the PHY ID1 register, the reset the MCU to recover */
+
+  else if (phyval == 0xffff)
+    {
+      up_systemreset();
+    }
+
+  ninfo("PHY ID1: 0x%04X\n", phyval);
+
+  /* Now check the "DAVICOM Specified Configuration Register (DSCR)", Register 16 */
+
+  ret = stm32_phyread(CONFIG_STM32H7_PHYADDR, 16, &phyval);
+  if (ret < 0)
+    {
+      nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret);
+      return ret;
+    }
+
+  /* Bit 8 of the DSCR register is zero, then the DM9161 has not selected
+   * RMII.  If RMII is not selected, then reset the MCU to recover.
+   */
+
+  else if ((phyval & (1 << 8)) == 0)
+    {
+      up_systemreset();
+    }
+
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Function: stm32_phyregdump
+ *
+ * Description:
+ *  Dump the MII registers 0-31
+ *
+ * Parameters:
+ *
+ * Returned Value:
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG
+static void stm32_phyregdump()
+{
+  uint16_t phyval;
+  int ret;
+  int i;
+
+  for (i = 0; i < 0x20; i++)
+    {
+      ret = stm32_phyread(CONFIG_STM32H7_PHYADDR, i, &phyval);
+      if (ret < 0)
+        {
+          nerr("ERROR: Failed to read reg: 0%2x\n", i);
+        }
+      else
+        {
+          ninfo("Phy reg 0x%02x == 0x%x\n", i, phyval);
+        }
+    }
+}
+#endif
+
+/****************************************************************************
+ * Function: stm32_phyinit
+ *
+ * Description:
+ *  Configure the PHY and determine the link speed/duplex.
+ *
+ * Parameters:
+ *   priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int stm32_phyinit(struct stm32_ethmac_s *priv)
+{
+#ifdef CONFIG_STM32H7_AUTONEG
+  volatile uint32_t timeout;
+#endif
+  uint32_t regval;
+  uint16_t phyval;
+  int ret;
+  int to;
+
+  /* Assume 10MBps and half duplex */
+
+  priv->mbps100 = 0;
+  priv->fduplex = 0;
+
+  /* Setup up PHY clocking by setting the SR field in the MACMDIOAR register */
+
+  regval  = stm32_getreg(STM32_ETH_MACMDIOAR);
+  regval &= ~ETH_MACMDIOAR_CR_MASK;
+  regval |= ETH_MACMDIOAR_CR;
+  stm32_putreg(regval, STM32_ETH_MACMDIOAR);
+
+  /* Put the PHY in reset mode */
+
+  ret = stm32_phywrite(CONFIG_STM32H7_PHYADDR, MII_MCR, MII_MCR_RESET,
+                       MII_MCR_RESET);
+  if (ret < 0)
+    {
+      nerr("ERROR: Failed to reset the PHY: %d\n", ret);
+      return ret;
+    }
+
+  to = PHY_RESET_DELAY;
+  do
+    {
+      up_mdelay(10);
+      to -= 10;
+      ret = stm32_phyread(CONFIG_STM32H7_PHYADDR, MII_MCR, &phyval);
+    }
+  while (phyval & MII_MCR_RESET && to > 0);
+
+  if (to <= 0)
+    {
+      nerr("ERROR: Phy reset timeout\n");
+      return ret;
+    }
+  else
+    {
+      ninfo("Phy reset in %d ms\n", PHY_RESET_DELAY - to);
+    }
+
+#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG
+  stm32_phyregdump();
+#endif
+
+  /* Perform any necessary, board-specific PHY initialization */
+
+#ifdef CONFIG_STM32H7_PHYINIT
+  ret = stm32_phy_boardinitialize(0);
+  if (ret < 0)
+    {
+      nerr("ERROR: Failed to initialize the PHY: %d\n", ret);
+      return ret;
+    }
+#endif
+
+  /* Special workaround for the Davicom DM9161 PHY is required. */
+
+#ifdef CONFIG_ETH0_PHY_DM9161
+  ret = stm32_dm9161(priv);
+  if (ret < 0)
+    {
+      return ret;
+    }
+#endif
+
+  /* Perform auto-negotiation if so configured */
+
+#ifdef CONFIG_STM32H7_AUTONEG
+  /* Wait for link status */
+
+  for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++)
+    {
+      ret = stm32_phyread(CONFIG_STM32H7_PHYADDR, MII_MSR, &phyval);
+      if (ret < 0)
+        {
+          nerr("ERROR: Failed to read the PHY MSR: %d\n", ret);
+          return ret;
+        }
+      else if ((phyval & MII_MSR_LINKSTATUS) != 0)
+        {
+          break;
+        }
+    }
+
+  if (timeout >= PHY_RETRY_TIMEOUT)
+    {
+      nerr("ERROR: Timed out waiting for link status: %04x\n", phyval);
+      return -ETIMEDOUT;
+    }
+
+  /* Enable auto-negotiation */
+
+  ret = stm32_phywrite(CONFIG_STM32H7_PHYADDR, MII_MCR, MII_MCR_ANENABLE,
+                       MII_MCR_ANENABLE);
+  if (ret < 0)
+    {
+      nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret);
+      return ret;
+    }
+
+  /* Wait until auto-negotiation completes */
+
+  for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++)
+    {
+      ret = stm32_phyread(CONFIG_STM32H7_PHYADDR, MII_MSR, &phyval);
+      if (ret < 0)
+        {
+          nerr("ERROR: Failed to read the PHY MSR: %d\n", ret);
+          return ret;
+        }
+      else if ((phyval & MII_MSR_ANEGCOMPLETE) != 0)
+        {
+          break;
+        }
+    }
+
+  if (timeout >= PHY_RETRY_TIMEOUT)
+    {
+      nerr("ERROR: Timed out waiting for auto-negotiation\n");
+      return -ETIMEDOUT;
+    }
+
+  /* Read the result of the auto-negotiation from the PHY-specific register */
+
+  ret = stm32_phyread(CONFIG_STM32H7_PHYADDR, CONFIG_STM32H7_PHYSR, &phyval);
+  if (ret < 0)
+    {
+      nerr("ERROR: Failed to read PHY status register\n");
+      return ret;
+    }
+
+  /* Remember the selected speed and duplex modes */
+
+  ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32H7_PHYSR, phyval);
+
+  /* Different PHYs present speed and mode information in different ways.  IF
+   * This CONFIG_STM32H7_PHYSR_ALTCONFIG is selected, this indicates that
+   * the PHY represents speed and mode information are combined, for
+   * example, with separate bits for 10HD, 100HD, 10FD and 100FD.
+   */
+
+#ifdef CONFIG_STM32H7_PHYSR_ALTCONFIG
+  switch (phyval & CONFIG_STM32H7_PHYSR_ALTMODE)
+    {
+      default:
+        nerr("ERROR: Unrecognized PHY status setting\n");
+
+      /* Falls through */
+
+      case CONFIG_STM32H7_PHYSR_10HD:
+        priv->fduplex = 0;
+        priv->mbps100 = 0;
+        break;
+
+      case CONFIG_STM32H7_PHYSR_100HD:
+        priv->fduplex = 0;
+        priv->mbps100 = 1;
+        break;
+
+      case CONFIG_STM32H7_PHYSR_10FD:
+        priv->fduplex = 1;
+        priv->mbps100 = 0;
+        break;
+
+      case CONFIG_STM32H7_PHYSR_100FD:
+        priv->fduplex = 1;
+        priv->mbps100 = 1;
+        break;
+    }
+
+  /* Different PHYs present speed and mode information in different ways.
+   * Some will present separate information for speed and mode (this is the
+   * default).  Those PHYs, for example, may provide a 10/100 Mbps
+   * indication and a separate full/half duplex indication.
+   */
+
+#else
+  if ((phyval & CONFIG_STM32H7_PHYSR_MODE) == CONFIG_STM32H7_PHYSR_FULLDUPLEX)
+    {
+      priv->fduplex = 1;
+    }
+
+  if ((phyval & CONFIG_STM32H7_PHYSR_SPEED) == CONFIG_STM32H7_PHYSR_100MBPS)
+    {
+      priv->mbps100 = 1;
+    }
+#endif
+
+#else /* Auto-negotion not selected */
+
+  phyval = 0;
+#ifdef CONFIG_STM32H7_ETHFD
+  phyval |= MII_MCR_FULLDPLX;
+#endif
+#ifdef CONFIG_STM32H7_ETH100MBPS
+  phyval |= MII_MCR_SPEED100;
+#endif
+
+  ret = stm32_phywrite(CONFIG_STM32H7_PHYADDR, MII_MCR, phyval, 0xffff);
+  if (ret < 0)
+    {
+      nerr("ERROR: Failed to write the PHY MCR: %d\n", ret);
+      return ret;
+    }
+
+  up_mdelay(PHY_CONFIG_DELAY);
+
+  /* Remember the selected speed and duplex modes */
+
+#ifdef CONFIG_STM32H7_ETHFD
+  priv->fduplex = 1;
+#endif
+#ifdef CONFIG_STM32H7_ETH100MBPS
+  priv->mbps100 = 1;
+#endif
+#endif
+
+  ninfo("Duplex: %s Speed: %d MBps\n",
+        priv->fduplex ? "FULL" : "HALF",
+        priv->mbps100 ? 100 : 10);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32_selectmii
+ *
+ * Description:
+ *   Selects the MII inteface.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32H7_MII
+static inline void stm32_selectmii(void)
+{
+  uint32_t regval;
+
+  regval  = getreg32(STM32_SYSCFG_PMC);
+  regval &= ~SYSCFG_PMC_EPIS_MASK;
+  regval |= SYSCFG_PMC_EPIS_MII;
+  putreg32(regval, STM32_SYSCFG_PMC);
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_selectrmii
+ *
+ * Description:
+ *   Selects the RMII inteface.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void stm32_selectrmii(void)
+{
+  uint32_t regval;
+
+  regval  = getreg32(STM32_SYSCFG_PMC);
+  regval &= ~SYSCFG_PMC_EPIS_MASK;
+  regval |= SYSCFG_PMC_EPIS_RMII;
+  putreg32(regval, STM32_SYSCFG_PMC);
+}
+
+/****************************************************************************
+ * Function: stm32_ethgpioconfig
+ *
+ * Description:
+ *  Configure GPIOs for the Ethernet interface.
+ *
+ * Parameters:
+ *   priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ *   None.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
+{
+  /* Configure GPIO pins to support Ethernet */
+
+#if defined(CONFIG_STM32H7_MII) || defined(CONFIG_STM32H7_RMII)
+
+  /* MDC and MDIO are common to both modes */
+
+  stm32_configgpio(GPIO_ETH_MDC);
+  stm32_configgpio(GPIO_ETH_MDIO);
+
+  /* Set up the MII interface */
+
+#if defined(CONFIG_STM32H7_MII)
+
+  /* Select the MII interface */
+
+  stm32_selectmii();
+
+  /* Provide clocking via MCO, MCO1 or MCO2:
+   *
+   * "MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
+   *  clock (through a configurable prescaler) on PA8 pin."
+   *
+   * "MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or
+   *  PLLI2S clock (through a configurable prescaler) on PC9 pin."
+   */
+
+# if defined(CONFIG_STM32H7_MII_MCO1)
+  /* Configure MC01 to drive the PHY.  Board logic must provide MC01 clocking
+   * info.
+   */
+
+  stm32_configgpio(GPIO_MCO1);
+  stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER);
+
+# elif defined(CONFIG_STM32H7_MII_MCO2)
+  /* Configure MC02 to drive the PHY.  Board logic must provide MC02 clocking
+   * info.
+   */
+
+  stm32_configgpio(GPIO_MCO2);
+  stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER);
+
+# elif defined(CONFIG_STM32H7_MII_MCO)
+  /* Setup MCO pin for alternative usage */
+
+  stm32_configgpio(GPIO_MCO);
+  stm32_mcoconfig(BOARD_CFGR_MCO_SOURCE);
+# endif
+
+  /* MII interface pins (17):
+   *
+   * MII_TX_CLK, MII_TXD[3:0], MII_TX_EN, MII_RX_CLK, MII_RXD[3:0], MII_RX_ER,
+   * MII_RX_DV, MII_CRS, MII_COL, MDC, MDIO
+   */
+
+  stm32_configgpio(GPIO_ETH_MII_COL);
+  stm32_configgpio(GPIO_ETH_MII_CRS);
+  stm32_configgpio(GPIO_ETH_MII_RXD0);
+  stm32_configgpio(GPIO_ETH_MII_RXD1);
+  stm32_configgpio(GPIO_ETH_MII_RXD2);
+  stm32_configgpio(GPIO_ETH_MII_RXD3);
+  stm32_configgpio(GPIO_ETH_MII_RX_CLK);
+  stm32_configgpio(GPIO_ETH_MII_RX_DV);
+  stm32_configgpio(GPIO_ETH_MII_RX_ER);
+  stm32_configgpio(GPIO_ETH_MII_TXD0);
+  stm32_configgpio(GPIO_ETH_MII_TXD1);
+  stm32_configgpio(GPIO_ETH_MII_TXD2);
+  stm32_configgpio(GPIO_ETH_MII_TXD3);
+  stm32_configgpio(GPIO_ETH_MII_TX_CLK);
+  stm32_configgpio(GPIO_ETH_MII_TX_EN);
+
+  /* Set up the RMII interface. */
+
+#elif defined(CONFIG_STM32H7_RMII)
+
+  /* Select the RMII interface */
+
+  stm32_selectrmii();
+
+  /* Provide clocking via MCO, MCO1 or MCO2:
+   *
+   * "MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
+   *  clock (through a configurable prescaler) on PA8 pin."
+   *
+   * "MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or
+   *  PLLI2S clock (through a configurable prescaler) on PC9 pin."
+   */
+
+# if defined(CONFIG_STM32H7_RMII_MCO1)
+  /* Configure MC01 to drive the PHY.  Board logic must provide MC01 clocking
+   * info.
+   */
+
+  stm32_configgpio(GPIO_MCO1);
+  stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER);
+
+# elif defined(CONFIG_STM32H7_RMII_MCO2)
+  /* Configure MC02 to drive the PHY.  Board logic must provide MC02 clocking
+   * info.
+   */
+
+  stm32_configgpio(GPIO_MCO2);
+  stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER);
+
+# elif defined(CONFIG_STM32H7_RMII_MCO)
+  /* Setup MCO pin for alternative usage */
+
+  stm32_configgpio(GPIO_MCO);
+  stm32_mcoconfig(BOARD_CFGR_MCO_SOURCE);
+# endif
+
+  /* RMII interface pins (7):
+   *
+   * RMII_TXD[1:0], RMII_TX_EN, RMII_RXD[1:0], RMII_CRS_DV, MDC, MDIO,
+   * RMII_REF_CLK
+   */
+
+  stm32_configgpio(GPIO_ETH_RMII_CRS_DV);
+  stm32_configgpio(GPIO_ETH_RMII_REF_CLK);
+  stm32_configgpio(GPIO_ETH_RMII_RXD0);
+  stm32_configgpio(GPIO_ETH_RMII_RXD1);
+  stm32_configgpio(GPIO_ETH_RMII_TXD0);
+  stm32_configgpio(GPIO_ETH_RMII_TXD1);
+  stm32_configgpio(GPIO_ETH_RMII_TX_EN);
+#endif
+#endif
+
+#ifdef CONFIG_STM32H7_ETH_PTP
+  /* Enable pulse-per-second (PPS) output signal */
+
+  stm32_configgpio(GPIO_ETH_PPS_OUT);
+#endif
+}
+
+/****************************************************************************
+ * Function: stm32_ethreset
+ *
+ * Description:
+ *  Reset the Ethernet block.
+ *
+ * Parameters:
+ *   priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ *   None.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void stm32_ethreset(struct stm32_ethmac_s *priv)
+{
+  uint32_t regval;
+
+  /* Reset the Ethernet on the AHB1 bus */
+
+  regval  = stm32_getreg(STM32_RCC_AHB1RSTR);
+  regval |= RCC_AHB1RSTR_ETH1MACRST;
+  stm32_putreg(regval, STM32_RCC_AHB1RSTR);
+
+  regval &= ~RCC_AHB1RSTR_ETH1MACRST;
+  stm32_putreg(regval, STM32_RCC_AHB1RSTR);
+
+  /* Perform a software reset by setting the SR bit in the DMAMR register.
+   * This Resets all MAC subsystem internal registers and logic.  After this
+   * reset all the registers holds their reset values.
+   */
+
+  regval  = stm32_getreg(STM32_ETH_DMAMR);
+  regval |= ETH_DMAMR_SWR;
+  stm32_putreg(regval, STM32_ETH_DMAMR);
+
+  /* Wait for software reset to complete. The SR bit is cleared automatically
+   * after the reset operation has completed in all of the core clock domains.
+   */
+
+  while ((stm32_getreg(STM32_ETH_DMAMR) & ETH_DMAMR_SWR) != 0);
+
+  /* Acording to the spec, these need to be done before creating
+   * the descriptor lists, so initialize these already here
+   */
+
+  /* Set up the DMAMR register */
+
+  regval  = stm32_getreg(STM32_ETH_DMAMR);
+  regval &= ~DMAMR_CLEAR_MASK;
+  regval |= DMAMR_SET_MASK;
+  stm32_putreg(regval, STM32_ETH_DMAMR);
+
+  /* Set up the DMASBMR register */
+
+  regval  = stm32_getreg(STM32_ETH_DMASBMR);
+  regval &= ~DMASBMR_CLEAR_MASK;
+  regval |= DMASBMR_SET_MASK;
+  stm32_putreg(regval, STM32_ETH_DMASBMR);
+}
+
+/****************************************************************************
+ * Function: stm32_macconfig
+ *
+ * Description:
+ *  Configure the Ethernet MAC for DMA operation.
+ *
+ * Parameters:
+ *   priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int stm32_macconfig(struct stm32_ethmac_s *priv)
+{
+  uint32_t regval;
+
+  /* DMA Configuration */
+
+  /* Set up the ETH_DMACCR register */
+
+  regval  = stm32_getreg(STM32_ETH_DMACCR);
+  regval &= ~DMACCR_CLEAR_MASK;
+  regval |= DMACCR_SET_MASK;
+  stm32_putreg(regval, STM32_ETH_DMACCR);
+
+  /* Set up the ETH_DMACTXCR register */
+
+  regval  = stm32_getreg(STM32_ETH_DMACTXCR);
+  regval &= ~DMACTXCR_CLEAR_MASK;
+  regval |= DMACTXCR_SET_MASK;
+  stm32_putreg(regval, STM32_ETH_DMACTXCR);
+
+  /* Set up the ETH_DMACRXCR register */
+
+  regval  = stm32_getreg(STM32_ETH_DMACRXCR);
+  regval &= ~DMACRXCR_CLEAR_MASK;
+  regval |= DMACRXCR_SET_MASK;
+  stm32_putreg(regval, STM32_ETH_DMACRXCR);
+
+  /* MTL configuration */
+
+  /* Set up the MTLTXQOMR register */
+
+  regval  = stm32_getreg(STM32_ETH_MTLTXQOMR);
+  regval &= ~MTLTXQOMR_CLEAR_MASK;
+  regval |= MTLTXQOMR_SET_MASK;
+  stm32_putreg(regval, STM32_ETH_MTLTXQOMR);
+
+  /* Set up the MTLRXQOMR register */
+
+  regval  = stm32_getreg(STM32_ETH_MTLRXQOMR);
+  regval &= ~MTLRXQOMR_CLEAR_MASK;
+  regval |= MTLRXQOMR_SET_MASK;
+  stm32_putreg(regval, STM32_ETH_MTLRXQOMR);
+
+  /* MAC Configuration */
+
+  /* Set up the MACCR register */
+
+  regval  = stm32_getreg(STM32_ETH_MACCR);
+  regval &= ~MACCR_CLEAR_BITS;
+  regval |= MACCR_SET_BITS;
+
+  if (priv->fduplex)
+    {
+      /* Set the DM bit for full duplex support */
+
+      regval |= ETH_MACCR_DM;
+    }
+
+  if (priv->mbps100)
+    {
+      /* Set the FES bit for 100Mbps fast ethernet support */
+
+      regval |= ETH_MACCR_FES;
+    }
+
+  stm32_putreg(regval, STM32_ETH_MACCR);
+
+  /* Set up the MACPFR register */
+
+  regval  = stm32_getreg(STM32_ETH_MACPFR);
+  regval &= ~MACPFR_CLEAR_BITS;
+  regval |= MACPFR_SET_BITS;
+  stm32_putreg(regval, STM32_ETH_MACPFR);
+
+  /* Set up the MACHT0R and MACHT1R registers */
+
+  stm32_putreg(0, STM32_ETH_MACHT0R);
+  stm32_putreg(0, STM32_ETH_MACHT1R);
+
+  /* Setup up the MACQTXFCR register */
+
+  regval  = stm32_getreg(STM32_ETH_MACQTXFCR);
+  regval &= ~MACQTXFCR_CLEAR_MASK;
+  regval |= MACQTXFCR_SET_MASK;
+  stm32_putreg(regval, STM32_ETH_MACQTXFCR);
+
+  /* Setup up the MACRXFCR register */
+
+  regval  = stm32_getreg(STM32_ETH_MACRXFCR);
+  regval &= ~MACRXFCR_CLEAR_MASK;
+  regval |= MACRXFCR_SET_MASK;
+  stm32_putreg(regval, STM32_ETH_MACRXFCR);
+
+  /* Setup up the MACVTR register */
+
+  stm32_putreg(0, STM32_ETH_MACVTR);
+  return OK;
+}
+
+/****************************************************************************
+ * Function: stm32_macaddress
+ *
+ * Description:
+ *   Configure the selected MAC address.
+ *
+ * Parameters:
+ *   priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static void stm32_macaddress(struct stm32_ethmac_s *priv)
+{
+  struct net_driver_s *dev = &priv->dev;
+  uint32_t regval;
+
+  ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        dev->d_ifname,
+        dev->d_mac.ether.ether_addr_octet[0],
+        dev->d_mac.ether.ether_addr_octet[1],
+        dev->d_mac.ether.ether_addr_octet[2],
+        dev->d_mac.ether.ether_addr_octet[3],
+        dev->d_mac.ether.ether_addr_octet[4],
+        dev->d_mac.ether.ether_addr_octet[5]);
+
+  /* Set the MAC address high register */
+
+  regval = ((uint32_t)dev->d_mac.ether.ether_addr_octet[5] << 8) |
+            (uint32_t)dev->d_mac.ether.ether_addr_octet[4];
+  stm32_putreg(regval, STM32_ETH_MACA0HR);
+
+  /* Set the MAC address low register */
+
+  regval = ((uint32_t)dev->d_mac.ether.ether_addr_octet[3] << 24) |
+           ((uint32_t)dev->d_mac.ether.ether_addr_octet[2] << 16) |
+           ((uint32_t)dev->d_mac.ether.ether_addr_octet[1] <<  8) |
+            (uint32_t)dev->d_mac.ether.ether_addr_octet[0];
+  stm32_putreg(regval, STM32_ETH_MACA0LR);
+}
+
+/****************************************************************************
+ * Function: stm32_ipv6multicast
+ *
+ * Description:
+ *   Configure the IPv6 multicast MAC address.
+ *
+ * Parameters:
+ *   priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NET_ICMPv6
+static void stm32_ipv6multicast(struct stm32_ethmac_s *priv)
+{
+  struct net_driver_s *dev;
+  uint16_t tmp16;
+  uint8_t mac[6];
+
+  /* For ICMPv6, we need to add the IPv6 multicast address
+   *
+   * For IPv6 multicast addresses, the Ethernet MAC is derived by
+   * the four low-order octets OR'ed with the MAC 33:33:00:00:00:00,
+   * so for example the IPv6 address FF02:DEAD:BEEF::1:3 would map
+   * to the Ethernet MAC address 33:33:00:01:00:03.
+   *
+   * NOTES:  This appears correct for the ICMPv6 Router Solicitation
+   * Message, but the ICMPv6 Neighbor Solicitation message seems to
+   * use 33:33:ff:01:00:03.
+   */
+
+  mac[0] = 0x33;
+  mac[1] = 0x33;
+
+  dev    = &priv->dev;
+  tmp16  = dev->d_ipv6addr[6];
+  mac[2] = 0xff;
+  mac[3] = tmp16 >> 8;
+
+  tmp16  = dev->d_ipv6addr[7];
+  mac[4] = tmp16 & 0xff;
+  mac[5] = tmp16 >> 8;
+
+  ninfo("IPv6 Multicast: %02x:%02x:%02x:%02x:%02x:%02x\n",
+        mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+
+  (void)stm32_addmac(dev, mac);
+
+#ifdef CONFIG_NET_ICMPv6_AUTOCONF
+  /* Add the IPv6 all link-local nodes Ethernet address.  This is the
+   * address that we expect to receive ICMPv6 Router Advertisement
+   * packets.
+   */
+
+  (void)stm32_addmac(dev, g_ipv6_ethallnodes.ether_addr_octet);
+
+#endif /* CONFIG_NET_ICMPv6_AUTOCONF */
+#ifdef CONFIG_NET_ICMPv6_ROUTER
+  /* Add the IPv6 all link-local routers Ethernet address.  This is the
+   * address that we expect to receive ICMPv6 Router Solicitation
+   * packets.
+   */
+
+  (void)stm32_addmac(dev, g_ipv6_ethallrouters.ether_addr_octet);
+
+#endif /* CONFIG_NET_ICMPv6_ROUTER */
+}
+#endif /* CONFIG_NET_ICMPv6 */
+
+/****************************************************************************
+ * Function: stm32_macenable
+ *
+ * Description:
+ *  Enable normal MAC operation.
+ *
+ * Parameters:
+ *   priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int stm32_macenable(struct stm32_ethmac_s *priv)
+{
+  uint32_t regval;
+
+  /* Set the MAC address */
+
+  stm32_macaddress(priv);
+
+#ifdef CONFIG_NET_ICMPv6
+  /* Set up the IPv6 multicast address */
+
+  stm32_ipv6multicast(priv);
+#endif
+
+  /* Enable transmit state machine of the MAC for transmission on the MII */
+
+  regval  = stm32_getreg(STM32_ETH_MACCR);
+  regval |= ETH_MACCR_TE;
+  stm32_putreg(regval, STM32_ETH_MACCR);
+
+  /* Flush Transmit FIFO */
+
+  regval  = stm32_getreg(STM32_ETH_MTLTXQOMR);
+  regval |= ETH_MTLTXQOMR_FTQ;
+  stm32_putreg(regval, STM32_ETH_MTLTXQOMR);
+
+  /* Enable receive state machine of the MAC for reception from the MII */
+
+  /* Enables or disables the MAC reception. */
+
+  regval  = stm32_getreg(STM32_ETH_MACCR);
+  regval |= ETH_MACCR_RE;
+  stm32_putreg(regval, STM32_ETH_MACCR);
+
+  /* Start DMA transmission */
+
+  regval  = stm32_getreg(STM32_ETH_DMACTXCR);
+  regval |= ETH_DMACTXCR_ST;
+  stm32_putreg(regval, STM32_ETH_DMACTXCR);
+
+  /* Start DMA reception */
+
+  regval  = stm32_getreg(STM32_ETH_DMACRXCR);
+  regval |= ETH_DMACRXCR_SR;
+  stm32_putreg(regval, STM32_ETH_DMACRXCR);
+
+  /* Enable Ethernet DMA interrupts */
+
+  stm32_putreg(ETH_MACIER_ALLINTS, STM32_ETH_MACIER);
+
+  /* Ethernet DMA supports two classes of interrupts: Normal interrupt
+   * summary (NIS) and Abnormal interrupt summary (AIS) with a variety
+   * individual normal and abnormal interrupting events.  Here only
+   * the normal receive event is enabled (unless DEBUG is enabled).  Transmit
+   * events will only be enabled when a transmit interrupt is expected.
+   */
+
+  stm32_putreg((ETH_DMAINT_RECV_ENABLE | ETH_DMAINT_XMIT_ENABLE |
+                ETH_DMAINT_ERROR_ENABLE), STM32_ETH_DMACIER);
+
+  /* Clear Tx and Rx process stopped flags */
+
+  regval  = stm32_getreg(STM32_ETH_DMACRXCR);
+  regval |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
+  stm32_putreg(regval, STM32_ETH_DMACRXCR);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Function: stm32_ethconfig
+ *
+ * Description:
+ *  Configure the Ethernet interface for DMA operation.
+ *
+ * Parameters:
+ *   priv - A reference to the private driver state structure
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int stm32_ethconfig(struct stm32_ethmac_s *priv)
+{
+  int ret;
+
+  /* NOTE: The Ethernet clocks were initialized early in the boot-up
+   * sequence in stm32_rcc.c.
+   */
+
+  /* Initialize the free buffer list */
+
+  stm32_initbuffer(priv, &g_txbuffer[priv->intf * TXBUFFER_SIZE]);
+
+  /* Reset the Ethernet block */
+
+  ninfo("Reset the Ethernet block\n");
+  stm32_ethreset(priv);
+
+  /* Initialize TX Descriptors list */
+
+  stm32_txdescinit(priv,
+                   &g_txtable[priv->intf * CONFIG_STM32H7_ETH_NTXDESC]);
+
+  /* Initialize RX Descriptors list */
+
+  stm32_rxdescinit(priv,
+                   &g_rxtable[priv->intf * CONFIG_STM32H7_ETH_NRXDESC],
+                   &g_rxbuffer[priv->intf * RXBUFFER_SIZE]);
+
+  /* Initialize the PHY */
+
+  ninfo("Initialize the PHY\n");
+  ret = stm32_phyinit(priv);
+  if (ret < 0)
+  {
+    return ret;
+  }
+
+  /* Initialize the MAC and DMA */
+
+  ninfo("Initialize the MAC and DMA\n");
+  ret = stm32_macconfig(priv);
+  if (ret < 0)
+  {
+    return ret;
+  }
+
+  /* Enable normal MAC operation */
+
+  ninfo("Enable normal operation\n");
+  return stm32_macenable(priv);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: stm32_ethinitialize
+ *
+ * Description:
+ *   Initialize the Ethernet driver for one interface.  If the STM32 chip
+ *   supports multiple Ethernet controllers, then board specific logic
+ *   must implement up_netinitialize() and call this function to initialize
+ *   the desired interfaces.
+ *
+ * Parameters:
+ *   intf - In the case where there are multiple EMACs, this value
+ *          identifies which EMAC is to be initialized.
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#if STM32H7_NETHERNET == 1 || defined(CONFIG_NETDEV_LATEINIT)
+static inline
+#endif
+
+int stm32_ethinitialize(int intf)
+{
+  struct stm32_ethmac_s *priv;
+
+  ninfo("intf: %d\n", intf);
+
+  /* Get the interface structure associated with this interface number. */
+
+  DEBUGASSERT(intf < STM32H7_NETHERNET);
+  priv = &g_stm32ethmac[intf];
+
+  /* Initialize the driver structure */
+
+  memset(priv, 0, sizeof(struct stm32_ethmac_s));
+  priv->dev.d_ifup    = stm32_ifup;     /* I/F up (new IP address) callback */
+  priv->dev.d_ifdown  = stm32_ifdown;   /* I/F down callback */
+  priv->dev.d_txavail = stm32_txavail;  /* New TX data callback */
+#ifdef CONFIG_NET_IGMP
+  priv->dev.d_addmac  = stm32_addmac;   /* Add multicast MAC address */
+  priv->dev.d_rmmac   = stm32_rmmac;    /* Remove multicast MAC address */
+#endif
+#ifdef CONFIG_NETDEV_PHY_IOCTL
+  priv->dev.d_ioctl   = stm32_ioctl;    /* Support PHY ioctl() calls */
+#endif
+  priv->dev.d_private = (void *)g_stm32ethmac; /* Used to recover private state from dev */
+  priv->intf          = intf;           /* Remember the interface number */
+
+  /* Create a watchdog for timing polling for and timing of transmissions */
+
+  priv->txpoll       = wd_create();     /* Create periodic poll timer */
+  priv->txtimeout    = wd_create();     /* Create TX timeout timer */
+
+  /* Configure GPIO pins to support Ethernet */
+
+  stm32_ethgpioconfig(priv);
+
+  /* Attach the IRQ to the driver */
+
+  if (irq_attach(STM32_IRQ_ETH, stm32_interrupt, NULL))
+  {
+    /* We could not attach the ISR to the interrupt */
+
+    return -EAGAIN;
+  }
+
+  /* Put the interface in the down state. */
+
+  stm32_ifdown(&priv->dev);
+
+  /* Register the device with the OS so that socket IOCTLs can be performed */
+
+  (void)netdev_register(&priv->dev, NET_LL_ETHERNET);
+  return OK;
+}
+
+/****************************************************************************
+ * Function: up_netinitialize
+ *
+ * Description:
+ *   This is the "standard" network initialization logic called from the
+ *   low-level initialization logic in up_initialize.c.  If STM32H7_NETHERNET
+ *   greater than one, then board specific logic will have to supply a
+ *   version of up_netinitialize() that calls stm32_ethinitialize() with
+ *   the appropriate interface number.
+ *
+ * Parameters:
+ *   None.
+ *
+ * Returned Value:
+ *   None.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#if STM32H7_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT)
+void up_netinitialize(void)
+{
+  (void)stm32_ethinitialize(0);
+}
+#endif
+
+#endif /* STM32H7_NETHERNET > 0 && CONFIG_STM32H7_ETHMAC */
diff --git a/arch/arm/src/stm32h7/stm32_ethernet.h b/arch/arm/src/stm32h7/stm32_ethernet.h
new file mode 100644
index 00000000000..fdb1ad51a98
--- /dev/null
+++ b/arch/arm/src/stm32h7/stm32_ethernet.h
@@ -0,0 +1,119 @@
+/****************************************************************************
+ * arch/arm/src/stm32h7/stm32_ethernet.h
+ *
+ *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H7_STM32_ETHERNET_H
+#define __ARCH_ARM_SRC_STM32H7_STM32_ETHERNET_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include "hardware/stm32_ethernet.h"
+
+#if STM32H7_NETHERNET > 0
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Function: stm32_ethinitialize
+ *
+ * Description:
+ *   Initialize the Ethernet driver for one interface.  If the STM32 chip
+ *   supports multiple Ethernet controllers, then board specific logic must
+ *   implement up_netinitialize() and call this function to initialize the
+ *   desired interfaces.
+ *
+ * Parameters:
+ *   intf - In the case where there are multiple EMACs, this value identifies
+ *          which EMAC is to be initialized.
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+#if STM32H7_NETHERNET > 1
+int stm32_ethinitialize(int intf);
+#endif
+
+/****************************************************************************
+ * Function: stm32_phy_boardinitialize
+ *
+ * Description:
+ *   Some boards require specialized initialization of the PHY before it can
+ *   be used.  This may include such things as configuring GPIOs, resetting
+ *   the PHY, etc.  If CONFIG_STM32H7_PHYINIT is defined in the configuration
+ *   then the board specific logic must provide stm32_phyinitialize();  The
+ *   STM32 Ethernet driver will call this function one time before it first
+ *   uses the PHY.
+ *
+ * Parameters:
+ *   intf - Always zero for now.
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ***************************************************************************/
+
+#ifdef CONFIG_STM32H7_PHYINIT
+int stm32_phy_boardinitialize(int intf);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* STM32H7_NETHERNET > 0 */
+#endif /* __ARCH_ARM_SRC_STM32H7_STM32_ETHERNET_H */
diff --git a/arch/arm/src/stm32h7/stm32_exti.h b/arch/arm/src/stm32h7/stm32_exti.h
index 4b0ea9555d9..981974581f3 100644
--- a/arch/arm/src/stm32h7/stm32_exti.h
+++ b/arch/arm/src/stm32h7/stm32_exti.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_exti.h"
+#include "hardware/stm32_exti.h"
 
 /****************************************************************************
  * Public Data
diff --git a/arch/arm/src/stm32h7/stm32_gpio.c b/arch/arm/src/stm32h7/stm32_gpio.c
index 31920c355af..ee708b78e28 100644
--- a/arch/arm/src/stm32h7/stm32_gpio.c
+++ b/arch/arm/src/stm32h7/stm32_gpio.c
@@ -50,7 +50,7 @@
 
 #include "up_arch.h"
 
-#include "chip/stm32_syscfg.h"
+#include "hardware/stm32_syscfg.h"
 #include "stm32_gpio.h"
 
 /* Content of this file requires verification before it is used with other
diff --git a/arch/arm/src/stm32h7/stm32_gpio.h b/arch/arm/src/stm32h7/stm32_gpio.h
index 99d5eb7fa28..d9207ee6f69 100644
--- a/arch/arm/src/stm32h7/stm32_gpio.h
+++ b/arch/arm/src/stm32h7/stm32_gpio.h
@@ -50,7 +50,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_gpio.h"
+#include "hardware/stm32_gpio.h"
 
 /************************************************************************************
  * Pre-Processor Declarations
diff --git a/arch/arm/src/stm32h7/stm32_i2c.c b/arch/arm/src/stm32h7/stm32_i2c.c
index 72f1a5df6af..94e96af3d5a 100644
--- a/arch/arm/src/stm32h7/stm32_i2c.c
+++ b/arch/arm/src/stm32h7/stm32_i2c.c
@@ -223,7 +223,7 @@
 #include "stm32_rcc.h"
 #include "stm32_i2c.h"
 #include "stm32_gpio.h"
-#include "chip/stm32_pinmap.h"
+#include "hardware/stm32_pinmap.h"
 
 /* At least one I2C peripheral must be enabled */
 
@@ -579,8 +579,8 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv =
 static const struct stm32_i2c_config_s stm32_i2c4_config =
 {
   .base          = STM32_I2C4_BASE,
-  .clk_bit       = RCC_APB1LENR_I2C4EN,
-  .reset_bit     = RCC_APB1LRSTR_I2C4RST,
+  .clk_bit       = RCC_APB4ENR_I2C4EN,
+  .reset_bit     = RCC_APB4RSTR_I2C4RST,
   .scl_pin       = GPIO_I2C4_SCL,
   .sda_pin       = GPIO_I2C4_SDA,
 #ifndef CONFIG_I2C_POLLED
diff --git a/arch/arm/src/stm32h7/stm32_i2c.h b/arch/arm/src/stm32h7/stm32_i2c.h
index 7c6847f8302..3013d46bde3 100644
--- a/arch/arm/src/stm32h7/stm32_i2c.h
+++ b/arch/arm/src/stm32h7/stm32_i2c.h
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_i2c.h"
+#include "hardware/stm32_i2c.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32h7/stm32_lowputc.c b/arch/arm/src/stm32h7/stm32_lowputc.c
index 25e400bd504..132a936597c 100644
--- a/arch/arm/src/stm32h7/stm32_lowputc.c
+++ b/arch/arm/src/stm32h7/stm32_lowputc.c
@@ -46,7 +46,7 @@
 
 #include "chip.h"
 
-#include "chip/stm32_pinmap.h"
+#include "hardware/stm32_pinmap.h"
 #include "stm32_rcc.h"
 #include "stm32_gpio.h"
 #include "stm32_uart.h"
@@ -261,7 +261,7 @@
 #  define USART_CR3_CLRBITS \
     (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \
      USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \
-     USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR1_ONEBIT | \
+     USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \
      USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \
      USART_CR3_SCARCNT_MASK)
 
diff --git a/arch/arm/src/stm32h7/stm32_otg.h b/arch/arm/src/stm32h7/stm32_otg.h
index e006a7bf63d..28312364542 100644
--- a/arch/arm/src/stm32h7/stm32_otg.h
+++ b/arch/arm/src/stm32h7/stm32_otg.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_otg.h"
+#include "hardware/stm32_otg.h"
 
 #if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_OTGHS)
 
diff --git a/arch/arm/src/stm32h7/stm32_otgdev.c b/arch/arm/src/stm32h7/stm32_otgdev.c
index 0e9da578735..3350ea4de78 100644
--- a/arch/arm/src/stm32h7/stm32_otgdev.c
+++ b/arch/arm/src/stm32h7/stm32_otgdev.c
@@ -58,7 +58,7 @@
 #include 
 #include 
 
-#include "chip/stm32_pwr.h"
+#include "hardware/stm32_pwr.h"
 #include "chip.h"
 #include "stm32_rcc.h"
 #include "stm32_gpio.h"
@@ -4926,15 +4926,15 @@ static int stm32_pullup(struct usbdev_s *dev, bool enable)
   if (enable)
     {
       /* Connect the device by clearing the soft disconnect bit in the DCTL
-       * register
+       * register.
        */
 
       regval &= ~OTG_DCTL_SDIS;
     }
   else
     {
-      /* Connect the device by setting the soft disconnect bit in the DCTL
-       * register
+      /* Disconnect the device by setting the soft disconnect bit in the DCTL
+       * register.
        */
 
       regval |= OTG_DCTL_SDIS;
diff --git a/arch/arm/src/stm32h7/stm32_otghost.c b/arch/arm/src/stm32h7/stm32_otghost.c
index 6c6903f2999..97c8b9e67dc 100644
--- a/arch/arm/src/stm32h7/stm32_otghost.c
+++ b/arch/arm/src/stm32h7/stm32_otghost.c
@@ -69,7 +69,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/stm32_pwr.h"
+#include "hardware/stm32_pwr.h"
 #include "stm32_gpio.h"
 #include "stm32_otg.h"
 #include "stm32_usbhost.h"
diff --git a/arch/arm/src/stm32h7/stm32_pwm.c b/arch/arm/src/stm32h7/stm32_pwm.c
new file mode 100644
index 00000000000..f74afda363f
--- /dev/null
+++ b/arch/arm/src/stm32h7/stm32_pwm.c
@@ -0,0 +1,4397 @@
+/****************************************************************************
+ * arch/arm/src/stm32h7/stm32_pwm.c
+ *
+ *   Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *            Paul Alexander Patience 
+ *            Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "stm32_pwm.h"
+#include "stm32.h"
+
+/* This module then only compiles if there is at least one enabled timer
+ * intended for use with the PWM upper half driver.
+ *
+ * It implements support for both:
+ *   1. STM32 TIMER IP version 1 - F0, F1, F2, F37x, F4, L0, L1
+ *   2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+
+ */
+
+#ifdef CONFIG_STM32H7_PWM
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* PWM/Timer Definitions ****************************************************/
+
+/* The following definitions are used to identify the various time types. */
+
+#define TIMTYPE_BASIC        0  /* Basic timers (no outputs) */
+#define TIMTYPE_GENERAL16    1  /* General 16-bit timers (up, down, up/down)*/
+#define TIMTYPE_COUNTUP16    2  /* General 16-bit count-up timers */
+#define TIMTYPE_COUNTUP16_N  3  /* General 16-bit count-up timers with
+                                 * complementary outptus
+                                 */
+#define TIMTYPE_GENERAL32    4  /* General 32-bit timers (up, down, up/down)*/
+#define TIMTYPE_ADVANCED     5  /* Advanced timers */
+
+#define TIMTYPE_TIM1       TIMTYPE_ADVANCED
+#define TIMTYPE_TIM2       TIMTYPE_GENERAL32
+#define TIMTYPE_TIM3       TIMTYPE_GENERAL16
+#define TIMTYPE_TIM4       TIMTYPE_GENERAL16
+#define TIMTYPE_TIM5       TIMTYPE_GENERAL32
+#define TIMTYPE_TIM6       TIMTYPE_BASIC
+#define TIMTYPE_TIM7       TIMTYPE_BASIC
+#define TIMTYPE_TIM8       TIMTYPE_ADVANCED
+/* No TIM9-11 */
+#define TIMTYPE_TIM12      TIMTYPE_COUNTUP16
+#define TIMTYPE_TIM13      TIMTYPE_COUNTUP16
+#define TIMTYPE_TIM14      TIMTYPE_COUNTUP16
+#define TIMTYPE_TIM15      TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */
+#define TIMTYPE_TIM16      TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */
+#define TIMTYPE_TIM17      TIMTYPE_COUNTUP16_N /* Treated as ADVTIM */
+
+/* Timer clock source, RCC EN offset, enable bit,
+ * RCC RST offset, reset bit to use
+ *
+ * TODO: simplify this and move somewhere else.
+ */
+
+#define TIMCLK_TIM1      STM32_APB2_TIM1_CLKIN
+#define TIMRCCEN_TIM1    STM32_RCC_APB2ENR
+#define TIMEN_TIM1       RCC_APB2ENR_TIM1EN
+#define TIMRCCRST_TIM1   STM32_RCC_APB2RSTR
+#define TIMRST_TIM1      RCC_APB2RSTR_TIM1RST
+#define TIMCLK_TIM2      STM32_APB1_TIM2_CLKIN
+#define TIMRCCEN_TIM2    STM32_RCC_APB1LENR
+#define TIMEN_TIM2       RCC_APB1LENR_TIM2EN
+#define TIMRCCRST_TIM2   STM32_RCC_APB1LRSTR
+#define TIMRST_TIM2      RCC_APB1LRSTR_TIM2RST
+#define TIMCLK_TIM3      STM32_APB1_TIM3_CLKIN
+#define TIMRCCEN_TIM3    STM32_RCC_APB1LENR
+#define TIMEN_TIM3       RCC_APB1LENR_TIM3EN
+#define TIMRCCRST_TIM3   STM32_RCC_APB1LRSTR
+#define TIMRST_TIM3      RCC_APB1LRSTR_TIM3RST
+#define TIMCLK_TIM4      STM32_APB1_TIM4_CLKIN
+#define TIMRCCEN_TIM4    STM32_RCC_APB1LENR
+#define TIMEN_TIM4       RCC_APB1LENR_TIM4EN
+#define TIMRCCRST_TIM4   STM32_RCC_APB1LRSTR
+#define TIMRST_TIM4      RCC_APB1LRSTR_TIM4RST
+#define TIMCLK_TIM5      STM32_APB1_TIM5_CLKIN
+#define TIMRCCEN_TIM5    STM32_RCC_APB1LENR
+#define TIMEN_TIM5       RCC_APB1LENR_TIM5EN
+#define TIMRCCRST_TIM5   STM32_RCC_APB1LRSTR
+#define TIMRST_TIM5      RCC_APB1LRSTR_TIM5RST
+#define TIMCLK_TIM8      STM32_APB2_TIM8_CLKIN
+#define TIMRCCEN_TIM8    STM32_RCC_APB2ENR
+#define TIMEN_TIM8       RCC_APB2ENR_TIM8EN
+#define TIMRCCRST_TIM8   STM32_RCC_APB2RSTR
+#define TIMRST_TIM8      RCC_APB2RSTR_TIM8RST
+#define TIMCLK_TIM12     STM32_APB1_TIM12_CLKIN
+#define TIMRCCEN_TIM12   STM32_RCC_APB1LENR
+#define TIMEN_TIM12      RCC_APB1LENR_TIM12EN
+#define TIMRCCRST_TIM12  STM32_RCC_APB1LRSTR
+#define TIMRST_TIM12     RCC_APB1LRSTR_TIM12RST
+#define TIMCLK_TIM13     STM32_APB1_TIM13_CLKIN
+#define TIMRCCEN_TIM13   STM32_RCC_APB1LENR
+#define TIMEN_TIM13      RCC_APB1LENR_TIM13EN
+#define TIMRCCRST_TIM13  STM32_RCC_APB1LRSTR
+#define TIMRST_TIM13     RCC_APB1LRSTR_TIM13RST
+#define TIMCLK_TIM14     STM32_APB1_TIM14_CLKIN
+#define TIMRCCEN_TIM14   STM32_RCC_APB1LENR
+#define TIMEN_TIM14      RCC_APB1LENR_TIM14EN
+#define TIMRCCRST_TIM14  STM32_RCC_APB1LRSTR
+#define TIMRST_TIM14     RCC_APB1LRSTR_TIM14RST
+#define TIMCLK_TIM15     STM32_APB2_TIM15_CLKIN
+#define TIMRCCEN_TIM15   STM32_RCC_APB2ENR
+#define TIMEN_TIM15      RCC_APB2ENR_TIM15EN
+#define TIMRCCRST_TIM15  STM32_RCC_APB2RSTR
+#define TIMRST_TIM15     RCC_APB2RSTR_TIM15RST
+#define TIMCLK_TIM16     STM32_APB2_TIM16_CLKIN
+#define TIMRCCEN_TIM16   STM32_RCC_APB2ENR
+#define TIMEN_TIM16      RCC_APB2ENR_TIM16EN
+#define TIMRCCRST_TIM16  STM32_RCC_APB2RSTR
+#define TIMRST_TIM16     RCC_APB2RSTR_TIM16RST
+#define TIMCLK_TIM17     STM32_APB2_TIM17_CLKIN
+#define TIMRCCEN_TIM17   STM32_RCC_APB2ENR
+#define TIMEN_TIM17      RCC_APB2ENR_TIM71EN
+#define TIMRCCRST_TIM17  STM32_RCC_APB2RSTR
+#define TIMRST_TIM17     RCC_APB2RSTR_TIM17RST
+
+/* Default GPIO pins state */
+
+#define PINCFG_DEFAULT (GPIO_INPUT | GPIO_FLOAT)
+
+/* Advanced Timer support
+ * NOTE: TIM15-17 are not ADVTIM but they support most of the
+ *       ADVTIM functionality.  The main difference is the number of
+ *       supported capture/compare.
+ */
+
+#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \
+  defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \
+  defined(CONFIG_STM32_TIM17_PWM)
+#  define HAVE_ADVTIM
+#else
+#  undef HAVE_ADVTIM
+#endif
+
+/* Pulsecount support */
+
+#ifdef CONFIG_PWM_PULSECOUNT
+#  ifndef HAVE_ADVTIM
+#    error "PWM_PULSECOUNT requires HAVE_ADVTIM"
+#  endif
+#  if defined(CONFIG_STM32H7_TIM1_PWM) || defined(CONFIG_STM32H7_TIM8_PWM)
+#    define HAVE_PWM_INTERRUPT
+#  endif
+#endif
+
+/* Synchronisation support */
+
+#ifdef CONFIG_STM32H7_PWM_TRGO
+#  define HAVE_TRGO
+#endif
+
+/* Break support */
+
+#if defined(CONFIG_STM32H7_TIM1_BREAK1) || defined(CONFIG_STM32H7_TIM1_BREAK2) || \
+    defined(CONFIG_STM32H7_TIM8_BREAK1) || defined(CONFIG_STM32H7_TIM8_BREAK2) || \
+    defined(CONFIG_STM32H7_TIM15_BREAK1) || defined(CONFIG_STM32H7_TIM16_BREAK1) || \
+    defined(CONFIG_STM32H7_TIM17_BREAK1)
+#  defined HAVE_BREAK
+#endif
+
+/* Debug ********************************************************************/
+
+#ifdef CONFIG_DEBUG_PWM_INFO
+#  define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
+#else
+#  define pwm_dumpgpio(p,m)
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* PWM output configuration */
+
+struct stm32_pwm_out_s
+{
+  uint8_t  in_use:1;                    /* Output in use */
+  uint8_t  pol:1;                       /* Polarity. Default: positive */
+  uint8_t  idle:1;                      /* Idle state. Default: inactive */
+  uint8_t  _res:5;                      /* Reserved */
+  uint32_t pincfg;                      /* Output pin configuration */
+};
+
+/* PWM break configuration */
+
+#ifdef HAVE_BREAK
+struct stm32_pwm_break_s
+{
+  uint8_t en1:1;                        /* Break 1 enable */
+  uint8_t pol1:1;                       /* Break 1 polarity */
+  uint8_t _res:6;                       /* Reserved */
+#ifdef HAVE_IP_TIMERS_V2
+  uint8_t en2:1;                        /* Break 2 enable */
+  uint8_t pol2:1;                       /* Break 2 polarity */
+  uint8_t flt2:6;                       /* Break 2 filter */
+#endif
+};
+#endif
+
+/* PWM channel configuration */
+
+struct stm32_pwmchan_s
+{
+  uint8_t                  channel:4;   /* Timer output channel: {1,..4} */
+  uint8_t                  mode:4;      /* PWM channel mode (see stm32_pwm_chanmode_e) */
+  struct stm32_pwm_out_s   out1;        /* PWM output configuration */
+#ifdef HAVE_BREAK
+  struct stm32_pwm_break_s brk;         /* PWM break configuration */
+#endif
+#ifdef HAVE_PWM_COMPLEMENTARY
+  struct stm32_pwm_out_s   out2;        /* PWM complementary output configuration */
+#endif
+};
+
+/* This structure represents the state of one PWM timer */
+
+struct stm32_pwmtimer_s
+{
+  FAR const struct pwm_ops_s *ops;      /* PWM operations */
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+  FAR const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */
+#endif
+  FAR struct stm32_pwmchan_s *channels; /* Channels configuration */
+  uint8_t  timid:5;                     /* Timer ID {1,...,17} */
+  uint8_t  chan_num:3;                  /* Number of configured channels */
+  uint8_t  timtype:3;                   /* See the TIMTYPE_* definitions */
+  uint8_t  mode:3;                      /* Timer mode (see stm32_pwm_tim_mode_e) */
+  uint8_t  lock:2;                      /* TODO: Lock configuration */
+  uint8_t  t_dts:3;                     /* Clock division for t_DTS */
+  uint8_t  _res:5;                      /* Reserved */
+#ifdef HAVE_PWM_COMPLEMENTARY
+  uint8_t  deadtime;                    /* Dead-time value */
+#endif
+#ifdef HAVE_TRGO
+  uint8_t  trgo;                        /* TRGO configuration:
+                                         * 4 LSB = TRGO, 4 MSB = TRGO2
+                                         */
+#endif
+#ifdef CONFIG_PWM_PULSECOUNT
+  uint8_t  irq;                         /* Timer update IRQ */
+  uint8_t  prev;                        /* The previous value of the RCR (pre-loaded) */
+  uint8_t  curr;                        /* The current value of the RCR (pre-loaded) */
+  uint32_t count;                       /* Remaining pluse count */
+#else
+  uint32_t frequency;                   /* Current frequency setting */
+#endif
+  uint32_t base;                        /* The base address of the timer */
+  uint32_t pclk;                        /* The frequency of the peripheral clock
+                                         * that drives the timer module.
+                                         */
+#ifdef CONFIG_PWM_PULSECOUNT
+  FAR void *handle;                     /* Handle used for upper-half callback */
+#endif
+};
+
+/****************************************************************************
+ * Static Function Prototypes
+ ****************************************************************************/
+
+/* Register access */
+
+static uint32_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset);
+static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset,
+                       uint32_t value);
+static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset,
+                          uint32_t clearbits, uint32_t setbits);
+
+#ifdef CONFIG_DEBUG_PWM_INFO
+static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg);
+#else
+#  define pwm_dumpregs(priv,msg)
+#endif
+
+/* Timer management */
+
+static int pwm_frequency_update(FAR struct pwm_lowerhalf_s *dev,
+                                uint32_t frequency);
+static int pwm_mode_configure(FAR struct pwm_lowerhalf_s *dev,
+                              uint8_t channel, uint32_t mode);
+static int pwm_timer_configure(FAR struct stm32_pwmtimer_s *priv);
+static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
+                                uint8_t channel);
+static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev,
+                              uint16_t outputs, bool state);
+static int pwm_soft_update(FAR struct pwm_lowerhalf_s *dev);
+static int pwm_soft_break(FAR struct pwm_lowerhalf_s *dev, bool state);
+static int pwm_ccr_update(FAR struct pwm_lowerhalf_s *dev, uint8_t index,
+                          uint32_t ccr);
+static int pwm_arr_update(FAR struct pwm_lowerhalf_s *dev, uint32_t arr);
+static uint32_t pwm_arr_get(FAR struct pwm_lowerhalf_s *dev);
+static int pwm_duty_update(FAR struct pwm_lowerhalf_s *dev, uint8_t channel,
+                           ub16_t duty);
+static int pwm_timer_enable(FAR struct pwm_lowerhalf_s *dev, bool state);
+
+#ifdef HAVE_ADVTIM
+static int pwm_break_dt_configure(FAR struct stm32_pwmtimer_s *priv);
+#endif
+#ifdef HAVE_TRGO
+static int pwm_sync_configure(FAR struct stm32_pwmtimer_s *priv,
+                              uint8_t trgo);
+#endif
+#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H7_PWM_LL_OPS)
+static int pwm_deadtime_update(FAR struct pwm_lowerhalf_s *dev, uint8_t dt);
+#endif
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+static uint32_t pwm_ccr_get(FAR struct pwm_lowerhalf_s *dev, uint8_t index);
+#endif
+
+#ifdef CONFIG_PWM_PULSECOUNT
+static int pwm_pulsecount_configure(FAR struct pwm_lowerhalf_s *dev);
+#else
+static int pwm_configure(FAR struct pwm_lowerhalf_s *dev);
+#endif
+#ifdef CONFIG_PWM_PULSECOUNT
+static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev,
+                                FAR const struct pwm_info_s *info);
+#else
+static int pwm_timer(FAR struct pwm_lowerhalf_s *dev,
+                     FAR const struct pwm_info_s *info);
+#endif
+#ifdef HAVE_PWM_INTERRUPT
+static int pwm_interrupt(FAR struct pwm_lowerhalf_s *dev);
+#  ifdef CONFIG_STM32H7_TIM1_PWM
+static int pwm_tim1interrupt(int irq, void *context, FAR void *arg);
+#  endif
+#  ifdef CONFIG_STM32H7_TIM8_PWM
+static int pwm_tim8interrupt(int irq, void *context, FAR void *arg);
+#  endif
+static uint8_t pwm_pulsecount(uint32_t count);
+#endif
+
+/* PWM driver methods */
+
+static int pwm_setup(FAR struct pwm_lowerhalf_s *dev);
+static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev);
+
+#ifdef CONFIG_PWM_PULSECOUNT
+static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
+                     FAR const struct pwm_info_s *info,
+                     FAR void *handle);
+#else
+static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
+                     FAR const struct pwm_info_s *info);
+#endif
+
+static int pwm_stop(FAR struct pwm_lowerhalf_s *dev);
+static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev,
+                     int cmd, unsigned long arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This is the list of lower half PWM driver methods used by the upper half
+ * driver.
+ */
+
+static const struct pwm_ops_s g_pwmops =
+{
+  .setup       = pwm_setup,
+  .shutdown    = pwm_shutdown,
+  .start       = pwm_start,
+  .stop        = pwm_stop,
+  .ioctl       = pwm_ioctl,
+};
+
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+static const struct stm32_pwm_ops_s g_llpwmops =
+{
+  .configure       = pwm_configure,
+  .soft_break      = pwm_soft_break,
+  .ccr_update      = pwm_ccr_update,
+  .mode_update     = pwm_mode_configure,
+  .ccr_get         = pwm_ccr_get,
+  .arr_update      = pwm_arr_update,
+  .arr_get         = pwm_arr_get,
+  .outputs_enable  = pwm_outputs_enable,
+  .soft_update     = pwm_soft_update,
+  .freq_update     = pwm_frequency_update,
+  .tim_enable      = pwm_timer_enable,
+#  ifdef CONFIG_DEBUG_PWM_INFO
+  .dump_regs       = pwm_dumpregs,
+#  endif
+#  ifdef HAVE_PWM_COMPLEMENTARY
+  .dt_update       = pwm_deadtime_update,
+#  endif
+};
+#endif
+
+#ifdef CONFIG_STM32H7_TIM1_PWM
+
+static struct stm32_pwmchan_s g_pwm1channels[] =
+{
+  /* TIM1 has 4 channels, 4 complementary */
+
+#ifdef CONFIG_STM32H7_TIM1_CHANNEL1
+  {
+    .channel = 1,
+    .mode    = CONFIG_STM32H7_TIM1_CH1MODE,
+#ifdef HAVE_BREAK
+    .brk =
+    {
+#ifdef CONFIG_STM32H7_TIM1_BREAK1
+      .en1 = 1,
+      .pol1 = CONFIG_STM32H7_TIM1_BRK1POL,
+#endif
+#ifdef CONFIG_STM32H7_TIM1_BREAK2
+      .en2 = 1,
+      .pol2 = CONFIG_STM32H7_TIM1_BRK2POL,
+      .flt2 = CONFIG_STM32H7_TIM1_BRK2FLT,
+#endif
+    },
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CH1OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM1_CH1POL,
+      .idle    = CONFIG_STM32H7_TIM1_CH1IDLE,
+      .pincfg  = PWM_TIM1_CH1CFG,
+    },
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CH1NOUT
+    .out2 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM1_CH1NPOL,
+      .idle    = CONFIG_STM32H7_TIM1_CH1NIDLE,
+      .pincfg  = PWM_TIM1_CH1NCFG,
+    }
+#endif
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CHANNEL2
+  {
+    .channel = 2,
+    .mode    = CONFIG_STM32H7_TIM1_CH2MODE,
+#ifdef CONFIG_STM32H7_TIM1_CH2OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM1_CH2POL,
+      .idle    = CONFIG_STM32H7_TIM1_CH2IDLE,
+      .pincfg  = PWM_TIM1_CH2CFG,
+    },
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CH2NOUT
+    .out2 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM1_CH2NPOL,
+      .idle    = CONFIG_STM32H7_TIM1_CH2NIDLE,
+      .pincfg  = PWM_TIM1_CH2NCFG,
+    }
+#endif
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CHANNEL3
+  {
+    .channel = 3,
+    .mode    = CONFIG_STM32H7_TIM1_CH3MODE,
+#ifdef CONFIG_STM32H7_TIM1_CH3OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM1_CH3POL,
+      .idle    = CONFIG_STM32H7_TIM1_CH3IDLE,
+      .pincfg  = PWM_TIM1_CH3CFG,
+    },
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CH3NOUT
+    .out2 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM1_CH3NPOL,
+      .idle    = CONFIG_STM32H7_TIM1_CH3NIDLE,
+      .pincfg  = PWM_TIM1_CH3NCFG,
+    }
+#endif
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CHANNEL4
+  {
+    .channel = 4,
+    .mode    = CONFIG_STM32H7_TIM1_CH4MODE,
+#ifdef CONFIG_STM32H7_TIM1_CH4OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM1_CH4POL,
+      .idle    = CONFIG_STM32H7_TIM1_CH4IDLE,
+      .pincfg  = PWM_TIM1_CH4CFG,
+    }
+#endif
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CHANNEL5
+  {
+    .channel = 5,
+    .mode    = CONFIG_STM32H7_TIM1_CH5MODE,
+#ifdef CONFIG_STM32H7_TIM1_CH5OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM1_CH5POL,
+      .idle    = CONFIG_STM32H7_TIM1_CH5IDLE,
+      .pincfg  = 0,    /* No available externaly */
+    }
+#endif
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CHANNEL6
+  {
+    .channel = 6,
+    .mode    = CONFIG_STM32H7_TIM1_CH6MODE,
+#ifdef CONFIG_STM32H7_TIM1_CH6OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM1_CH6POL,
+      .idle    = CONFIG_STM32H7_TIM1_CH6IDLE,
+      .pincfg  = 0,    /* No available externaly */
+    }
+#endif
+  }
+#endif
+};
+
+static struct stm32_pwmtimer_s g_pwm1dev =
+{
+  .ops         = &g_pwmops,
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+  .llops       = &g_llpwmops,
+#endif
+  .timid       = 1,
+  .chan_num    = PWM_TIM1_NCHANNELS,
+  .channels    = g_pwm1channels,
+  .timtype     = TIMTYPE_TIM1,
+  .mode        = CONFIG_STM32H7_TIM1_MODE,
+  .lock        = CONFIG_STM32H7_TIM1_LOCK,
+  .t_dts       = CONFIG_STM32H7_TIM1_TDTS,
+#ifdef HAVE_PWM_COMPLEMENTARY
+  .deadtime    = CONFIG_STM32H7_TIM1_DEADTIME,
+#endif
+#if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO)
+  .trgo        = STM32_TIM1_TRGO,
+#endif
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM1UP,
+#endif
+  .base        = STM32_TIM1_BASE,
+  .pclk        = TIMCLK_TIM1,
+};
+#endif  /* CONFIG_STM32H7_TIM1_PWM */
+
+#ifdef CONFIG_STM32H7_TIM2_PWM
+
+static struct stm32_pwmchan_s g_pwm2channels[] =
+{
+  /* TIM2 has 4 channels */
+
+#ifdef CONFIG_STM32H7_TIM2_CHANNEL1
+  {
+    .channel = 1,
+    .mode    = CONFIG_STM32H7_TIM2_CH1MODE,
+#ifdef CONFIG_STM32H7_TIM2_CH1OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM2_CH1POL,
+      .idle    = CONFIG_STM32H7_TIM2_CH1IDLE,
+      .pincfg  = PWM_TIM2_CH1CFG,
+    }
+#endif
+    /* No complementary outputs */
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM2_CHANNEL2
+  {
+    .channel = 2,
+    .mode    = CONFIG_STM32H7_TIM2_CH2MODE,
+#ifdef CONFIG_STM32H7_TIM2_CH2OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM2_CH2POL,
+      .idle    = CONFIG_STM32H7_TIM2_CH2IDLE,
+      .pincfg  = PWM_TIM2_CH2CFG,
+    }
+#endif
+    /* No complementary outputs */
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM2_CHANNEL3
+  {
+    .channel = 3,
+    .mode    = CONFIG_STM32H7_TIM2_CH3MODE,
+#ifdef CONFIG_STM32H7_TIM2_CH3OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM2_CH3POL,
+      .idle    = CONFIG_STM32H7_TIM2_CH3IDLE,
+      .pincfg  = PWM_TIM2_CH3CFG,
+    }
+#endif
+    /* No complementary outputs */
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM2_CHANNEL4
+  {
+    .channel = 4,
+    .mode    = CONFIG_STM32H7_TIM2_CH4MODE,
+#ifdef CONFIG_STM32H7_TIM2_CH4OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM2_CH4POL,
+      .idle    = CONFIG_STM32H7_TIM2_CH4IDLE,
+      .pincfg  = PWM_TIM2_CH4CFG,
+    }
+#endif
+    /* No complementary outputs */
+  }
+#endif
+};
+
+static struct stm32_pwmtimer_s g_pwm2dev =
+{
+  .ops         = &g_pwmops,
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+  .llops       = &g_llpwmops,
+#endif
+  .timid       = 2,
+  .chan_num    = PWM_TIM2_NCHANNELS,
+  .channels    = g_pwm2channels,
+  .timtype     = TIMTYPE_TIM2,
+  .mode        = CONFIG_STM32H7_TIM2_MODE,
+  .lock        = 0,             /* No lock */
+  .t_dts       = 0,             /* No t_dts */
+#ifdef HAVE_PWM_COMPLEMENTARY
+  .deadtime    = 0,             /* No deadtime */
+#endif
+#if defined(HAVE_TRGO) && defined(STM32_TIM2_TRGO)
+  .trgo        = STM32_TIM2_TRGO,
+#endif
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM2,
+#endif
+  .base        = STM32_TIM2_BASE,
+  .pclk        = TIMCLK_TIM2,
+};
+#endif  /* CONFIG_STM32H7_TIM2_PWM */
+
+#ifdef CONFIG_STM32H7_TIM3_PWM
+
+static struct stm32_pwmchan_s g_pwm3channels[] =
+{
+  /* TIM3 has 4 channels */
+
+#ifdef CONFIG_STM32H7_TIM3_CHANNEL1
+  {
+    .channel = 1,
+    .mode    = CONFIG_STM32H7_TIM3_CH1MODE,
+#ifdef CONFIG_STM32H7_TIM3_CH1OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM3_CH1POL,
+      .idle    = CONFIG_STM32H7_TIM3_CH1IDLE,
+      .pincfg  = PWM_TIM3_CH1CFG,
+    }
+#endif
+    /* No complementary outputs */
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM3_CHANNEL2
+  {
+    .channel = 2,
+    .mode    = CONFIG_STM32H7_TIM3_CH2MODE,
+#ifdef CONFIG_STM32H7_TIM3_CH2OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM3_CH2POL,
+      .idle    = CONFIG_STM32H7_TIM3_CH2IDLE,
+      .pincfg  = PWM_TIM3_CH2CFG,
+    }
+#endif
+    /* No complementary outputs */
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM3_CHANNEL3
+  {
+    .channel = 3,
+    .mode    = CONFIG_STM32H7_TIM3_CH3MODE,
+#ifdef CONFIG_STM32H7_TIM3_CH3OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM3_CH3POL,
+      .idle    = CONFIG_STM32H7_TIM3_CH3IDLE,
+      .pincfg  = PWM_TIM3_CH3CFG,
+    }
+#endif
+    /* No complementary outputs */
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM3_CHANNEL4
+  {
+    .channel = 4,
+    .mode    = CONFIG_STM32H7_TIM3_CH4MODE,
+#ifdef CONFIG_STM32H7_TIM3_CH4OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM3_CH4POL,
+      .idle    = CONFIG_STM32H7_TIM3_CH4IDLE,
+      .pincfg  = PWM_TIM3_CH4CFG,
+    }
+#endif
+    /* No complementary outputs */
+  }
+#endif
+};
+
+static struct stm32_pwmtimer_s g_pwm3dev =
+{
+  .ops         = &g_pwmops,
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+  .llops       = &g_llpwmops,
+#endif
+  .timid       = 3,
+  .chan_num    = PWM_TIM3_NCHANNELS,
+  .channels    = g_pwm3channels,
+  .timtype     = TIMTYPE_TIM3,
+  .mode        = CONFIG_STM32H7_TIM3_MODE,
+  .lock        = 0,             /* No lock */
+  .t_dts       = 0,             /* No t_dts */
+#ifdef HAVE_PWM_COMPLEMENTARY
+  .deadtime    = 0,             /* No deadtime */
+#endif
+#if defined(HAVE_TRGO) && defined(STM32_TIM3_TRGO)
+  .trgo        = STM32_TIM3_TRGO,
+#endif
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM3,
+#endif
+  .base        = STM32_TIM3_BASE,
+  .pclk        = TIMCLK_TIM3,
+};
+#endif  /* CONFIG_STM32H7_TIM3_PWM */
+
+#ifdef CONFIG_STM32H7_TIM4_PWM
+
+static struct stm32_pwmchan_s g_pwm4channels[] =
+{
+  /* TIM4 has 4 channels */
+
+#ifdef CONFIG_STM32H7_TIM4_CHANNEL1
+  {
+    .channel = 1,
+    .mode    = CONFIG_STM32H7_TIM4_CH1MODE,
+#ifdef CONFIG_STM32H7_TIM4_CH1OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM4_CH1POL,
+      .idle    = CONFIG_STM32H7_TIM4_CH1IDLE,
+      .pincfg  = PWM_TIM4_CH1CFG,
+    }
+#endif
+    /* No complementary outputs */
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM4_CHANNEL2
+  {
+    .channel = 2,
+    .mode    = CONFIG_STM32H7_TIM4_CH2MODE,
+#ifdef CONFIG_STM32H7_TIM4_CH2OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM4_CH2POL,
+      .idle    = CONFIG_STM32H7_TIM4_CH2IDLE,
+      .pincfg  = PWM_TIM4_CH2CFG,
+    }
+#endif
+    /* No complementary outputs */
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM4_CHANNEL3
+  {
+    .channel = 3,
+    .mode    = CONFIG_STM32H7_TIM4_CH3MODE,
+#ifdef CONFIG_STM32H7_TIM4_CH3OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM4_CH3POL,
+      .idle    = CONFIG_STM32H7_TIM4_CH3IDLE,
+      .pincfg  = PWM_TIM4_CH3CFG,
+    }
+#endif
+    /* No complementary outputs */
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM4_CHANNEL4
+  {
+    .channel = 4,
+    .mode    = CONFIG_STM32H7_TIM4_CH4MODE,
+#ifdef CONFIG_STM32H7_TIM4_CH4OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM4_CH4POL,
+      .idle    = CONFIG_STM32H7_TIM4_CH4IDLE,
+      .pincfg  = PWM_TIM4_CH4CFG,
+    }
+#endif
+    /* No complementary outputs */
+  }
+#endif
+};
+
+static struct stm32_pwmtimer_s g_pwm4dev =
+{
+  .ops         = &g_pwmops,
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+  .llops       = &g_llpwmops,
+#endif
+  .timid       = 4,
+  .chan_num    = PWM_TIM4_NCHANNELS,
+  .channels    = g_pwm4channels,
+  .timtype     = TIMTYPE_TIM4,
+  .mode        = CONFIG_STM32H7_TIM4_MODE,
+  .lock        = 0,             /* No lock */
+  .t_dts       = 0,             /* No t_dts */
+#ifdef HAVE_PWM_COMPLEMENTARY
+  .deadtime    = 0,             /* No deadtime */
+#endif
+#if defined(HAVE_TRGO) && defined(STM32_TIM4_TRGO)
+  .trgo        = STM32_TIM4_TRGO,
+#endif
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM4,
+#endif
+  .base        = STM32_TIM4_BASE,
+  .pclk        = TIMCLK_TIM4,
+};
+#endif  /* CONFIG_STM32H7_TIM4_PWM */
+
+#ifdef CONFIG_STM32H7_TIM5_PWM
+
+static struct stm32_pwmchan_s g_pwm5channels[] =
+{
+  /* TIM5 has 4 channels */
+
+#ifdef CONFIG_STM32H7_TIM5_CHANNEL1
+  {
+    .channel = 1,
+    .mode    = CONFIG_STM32H7_TIM5_CH1MODE,
+#ifdef CONFIG_STM32H7_TIM5_CH1OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM5_CH1POL,
+      .idle    = CONFIG_STM32H7_TIM5_CH1IDLE,
+      .pincfg  = PWM_TIM5_CH1CFG,
+    }
+#endif
+    /* No complementary outputs */
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM5_CHANNEL2
+  {
+    .channel = 2,
+    .mode    = CONFIG_STM32H7_TIM5_CH2MODE,
+#ifdef CONFIG_STM32H7_TIM5_CH2OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM5_CH2POL,
+      .idle    = CONFIG_STM32H7_TIM5_CH2IDLE,
+      .pincfg  = PWM_TIM5_CH2CFG,
+    }
+#endif
+    /* No complementary outputs */
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM5_CHANNEL3
+  {
+    .channel = 3,
+    .mode    = CONFIG_STM32H7_TIM5_CH3MODE,
+#ifdef CONFIG_STM32H7_TIM5_CH3OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM5_CH3POL,
+      .idle    = CONFIG_STM32H7_TIM5_CH3IDLE,
+      .pincfg  = PWM_TIM5_CH3CFG,
+    }
+#endif
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM5_CHANNEL4
+  {
+    .channel = 4,
+    .mode    = CONFIG_STM32H7_TIM5_CH4MODE,
+#ifdef CONFIG_STM32H7_TIM5_CH4OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM5_CH4POL,
+      .idle    = CONFIG_STM32H7_TIM5_CH4IDLE,
+      .pincfg  = PWM_TIM5_CH4CFG,
+    }
+#endif
+  },
+#endif
+};
+
+static struct stm32_pwmtimer_s g_pwm5dev =
+{
+  .ops         = &g_pwmops,
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+  .llops       = &g_llpwmops,
+#endif
+  .timid       = 5,
+  .chan_num    = PWM_TIM5_NCHANNELS,
+  .channels    = g_pwm5channels,
+  .timtype     = TIMTYPE_TIM5,
+  .mode        = CONFIG_STM32H7_TIM5_MODE,
+  .lock        = 0,             /* No lock */
+  .t_dts       = 0,             /* No t_dts */
+#ifdef HAVE_PWM_COMPLEMENTARY
+  .deadtime    = 0,             /* No deadtime */
+#endif
+#if defined(HAVE_TRGO) && defined(STM32_TIM5_TRGO)
+  .trgo        = STM32_TIM5_TRGO
+#endif
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM5,
+#endif
+  .base        = STM32_TIM5_BASE,
+  .pclk        = TIMCLK_TIM5,
+};
+#endif  /* CONFIG_STM32H7_TIM5_PWM */
+
+#ifdef CONFIG_STM32H7_TIM8_PWM
+
+static struct stm32_pwmchan_s g_pwm8channels[] =
+{
+  /* TIM8 has 4 channels, 4 complementary */
+
+#ifdef CONFIG_STM32H7_TIM8_CHANNEL1
+  {
+    .channel = 1,
+    .mode    = CONFIG_STM32H7_TIM8_CH1MODE,
+#ifdef HAVE_BREAK
+    .brk =
+    {
+#ifdef CONFIG_STM32H7_TIM8_BREAK1
+      .en1 = 1,
+      .pol1 = CONFIG_STM32H7_TIM8_BRK1POL,
+#endif
+#ifdef CONFIG_STM32H7_TIM8_BREAK2
+      .en2 = 1,
+      .pol2 = CONFIG_STM32H7_TIM8_BRK2POL,
+      .flt2 = CONFIG_STM32H7_TIM8_BRK2FLT,
+#endif
+    },
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CH1OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM8_CH1POL,
+      .idle    = CONFIG_STM32H7_TIM8_CH1IDLE,
+      .pincfg  = PWM_TIM8_CH1CFG,
+    },
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CH1NOUT
+    .out2 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM8_CH1NPOL,
+      .idle    = CONFIG_STM32H7_TIM8_CH1NIDLE,
+      .pincfg  = PWM_TIM8_CH1NCFG,
+    }
+#endif
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CHANNEL2
+  {
+    .channel = 2,
+    .mode    = CONFIG_STM32H7_TIM8_CH2MODE,
+#ifdef CONFIG_STM32H7_TIM8_CH2OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM8_CH2POL,
+      .idle    = CONFIG_STM32H7_TIM8_CH2IDLE,
+      .pincfg  = PWM_TIM8_CH2CFG,
+    },
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CH2NOUT
+    .out2 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM8_CH2NPOL,
+      .idle    = CONFIG_STM32H7_TIM8_CH2NIDLE,
+      .pincfg  = PWM_TIM8_CH2NCFG,
+    }
+#endif
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CHANNEL3
+  {
+    .channel = 3,
+    .mode    = CONFIG_STM32H7_TIM8_CH3MODE,
+#ifdef CONFIG_STM32H7_TIM8_CH3OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM8_CH3POL,
+      .idle    = CONFIG_STM32H7_TIM8_CH3IDLE,
+      .pincfg  = PWM_TIM8_CH3CFG,
+    },
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CH3NOUT
+    .out2 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM8_CH3NPOL,
+      .idle    = CONFIG_STM32H7_TIM8_CH3NIDLE,
+      .pincfg  = PWM_TIM8_CH3NCFG,
+    }
+#endif
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CHANNEL4
+  {
+    .channel = 4,
+    .mode    = CONFIG_STM32H7_TIM8_CH4MODE,
+#ifdef CONFIG_STM32H7_TIM8_CH4OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM8_CH4POL,
+      .idle    = CONFIG_STM32H7_TIM8_CH4IDLE,
+      .pincfg  = PWM_TIM8_CH4CFG,
+    }
+#endif
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CHANNEL5
+  {
+    .channel = 5,
+    .mode    = CONFIG_STM32H7_TIM8_CH5MODE,
+#ifdef CONFIG_STM32H7_TIM8_CH5OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM8_CH5POL,
+      .idle    = CONFIG_STM32H7_TIM8_CH5IDLE,
+      .pincfg  = 0,    /* No available externaly */
+    }
+#endif
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CHANNEL6
+  {
+    .channel = 6,
+    .mode    = CONFIG_STM32H7_TIM8_CH6MODE,
+#ifdef CONFIG_STM32H7_TIM8_CH6OUT
+    .out1 =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM8_CH6POL,
+      .idle    = CONFIG_STM32H7_TIM8_CH6IDLE,
+      .pincfg  = 0,    /* No available externaly */
+    }
+#endif
+  }
+#endif
+};
+
+static struct stm32_pwmtimer_s g_pwm8dev =
+{
+  .ops         = &g_pwmops,
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+  .llops       = &g_llpwmops,
+#endif
+  .timid       = 8,
+  .chan_num    = PWM_TIM8_NCHANNELS,
+  .channels    = g_pwm8channels,
+  .timtype     = TIMTYPE_TIM8,
+  .mode        = CONFIG_STM32H7_TIM8_MODE,
+  .lock        = CONFIG_STM32H7_TIM8_LOCK,
+  .t_dts       = CONFIG_STM32H7_TIM8_TDTS,
+#ifdef HAVE_PWM_COMPLEMENTARY
+  .deadtime    = CONFIG_STM32H7_TIM8_DEADTIME,
+#endif
+#if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO)
+  .trgo        = STM32_TIM8_TRGO,
+#endif
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM8UP,
+#endif
+  .base        = STM32_TIM8_BASE,
+  .pclk        = TIMCLK_TIM8,
+};
+#endif  /* CONFIG_STM32H7_TIM8_PWM */
+
+#ifdef CONFIG_STM32H7_TIM12_PWM
+
+static struct stm32_pwmchan_s g_pwm12channels[] =
+{
+  /* TIM12 has 2 channels */
+
+#ifdef CONFIG_STM32H7_TIM12_CHANNEL1
+  {
+    .channel = 1,
+    .mode    = CONFIG_STM32H7_TIM12_CH1MODE,
+#ifdef CONFIG_STM32H7_TIM12_CH1OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM12_CH1POL,
+      .idle    = CONFIG_STM32H7_TIM12_CH1IDLE,
+      .pincfg  = PWM_TIM12_CH1CFG,
+    }
+#endif
+    /* No complementary outputs */
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM12_CHANNEL2
+  {
+    .channel = 2,
+    .mode    = CONFIG_STM32H7_TIM12_CH2MODE,
+#ifdef CONFIG_STM32H7_TIM12_CH2OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM12_CH2POL,
+      .idle    = CONFIG_STM32H7_TIM12_CH2IDLE,
+      .pincfg  = PWM_TIM12_CH2CFG,
+    }
+#endif
+    /* No complementary outputs */
+  }
+#endif
+};
+
+static struct stm32_pwmtimer_s g_pwm12dev =
+{
+  .ops         = &g_pwmops,
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+  .llops       = &g_llpwmops,
+#endif
+  .timid       = 12,
+  .chan_num    = PWM_TIM12_NCHANNELS,
+  .channels    = g_pwm12channels,
+  .timtype     = TIMTYPE_TIM12,
+  .mode        = STM32_TIMMODE_COUNTUP,
+  .lock        = 0,             /* No lock */
+  .t_dts       = 0,             /* No t_dts */
+#ifdef HAVE_PWM_COMPLEMENTARY
+  .deadtime    = 0,             /* No deadtime */
+#endif
+#if defined(HAVE_TRGO)
+  .trgo        = 0,             /* TRGO not supported for TIM12 */
+#endif
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM12,
+#endif
+  .base        = STM32_TIM12_BASE,
+  .pclk        = TIMCLK_TIM12,
+};
+#endif  /* CONFIG_STM32H7_TIM12_PWM */
+
+#ifdef CONFIG_STM32H7_TIM13_PWM
+
+static struct stm32_pwmchan_s g_pwm13channels[] =
+{
+  /* TIM13 has 1 channel */
+
+#ifdef CONFIG_STM32H7_TIM13_CHANNEL1
+  {
+    .channel = 1,
+    .mode    = CONFIG_STM32H7_TIM13_CH1MODE,
+#ifdef CONFIG_STM32H7_TIM13_CH1OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM13_CH1POL,
+      .idle    = CONFIG_STM32H7_TIM13_CH1IDLE,
+      .pincfg  = PWM_TIM13_CH1CFG,
+    }
+#endif
+    /* No complementary outputs */
+  }
+#endif
+};
+
+static struct stm32_pwmtimer_s g_pwm13dev =
+{
+  .ops         = &g_pwmops,
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+  .llops       = &g_llpwmops,
+#endif
+  .timid       = 13,
+  .chan_num    = PWM_TIM13_NCHANNELS,
+  .channels    = g_pwm13channels,
+  .timtype     = TIMTYPE_TIM13,
+  .mode        = STM32_TIMMODE_COUNTUP,
+  .lock        = 0,             /* No lock */
+  .t_dts       = 0,             /* No t_dts */
+#ifdef HAVE_PWM_COMPLEMENTARY
+  .deadtime    = 0,             /* No deadtime */
+#endif
+#if defined(HAVE_TRGO)
+  .trgo        = 0,             /* TRGO not supported for TIM13 */
+#endif
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM13,
+#endif
+  .base        = STM32_TIM13_BASE,
+  .pclk        = TIMCLK_TIM13,
+};
+#endif  /* CONFIG_STM32H7_TIM13_PWM */
+
+#ifdef CONFIG_STM32H7_TIM14_PWM
+
+static struct stm32_pwmchan_s g_pwm14channels[] =
+{
+  /* TIM14 has 1 channel */
+
+#ifdef CONFIG_STM32H7_TIM14_CHANNEL1
+  {
+    .channel = 1,
+    .mode    = CONFIG_STM32H7_TIM14_CH1MODE,
+#ifdef CONFIG_STM32H7_TIM14_CH1OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM14_CH1POL,
+      .idle    = CONFIG_STM32H7_TIM14_CH1IDLE,
+      .pincfg  = PWM_TIM14_CH1CFG,
+    }
+#endif
+    /* No complementary outputs */
+  }
+#endif
+};
+
+static struct stm32_pwmtimer_s g_pwm14dev =
+{
+  .ops         = &g_pwmops,
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+  .llops       = &g_llpwmops,
+#endif
+  .timid       = 14,
+  .chan_num    = PWM_TIM14_NCHANNELS,
+  .channels    = g_pwm14channels,
+  .timtype     = TIMTYPE_TIM14,
+  .mode        = STM32_TIMMODE_COUNTUP,
+  .lock        = 0,             /* No lock */
+  .t_dts       = 0,             /* No t_dts */
+#ifdef HAVE_PWM_COMPLEMENTARY
+  .deadtime    = 0,             /* No deadtime */
+#endif
+#if defined(HAVE_TRGO)
+  .trgo        = 0,             /* TRGO not supported for TIM14 */
+#endif
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM14,
+#endif
+  .base        = STM32_TIM14_BASE,
+  .pclk        = TIMCLK_TIM14,
+};
+#endif  /* CONFIG_STM32H7_TIM14_PWM */
+
+#ifdef CONFIG_STM32H7_TIM15_PWM
+
+static struct stm32_pwmchan_s g_pwm15channels[] =
+{
+  /* TIM15 has 2 channels, 1 complementary */
+
+#ifdef CONFIG_STM32H7_TIM15_CHANNEL1
+  {
+    .channel = 1,
+    .mode    = CONFIG_STM32H7_TIM15_CH1MODE,
+#ifdef HAVE_BREAK
+    .brk =
+    {
+#ifdef CONFIG_STM32H7_TIM15_BREAK1
+      .en1 = 1,
+      .pol1 = CONFIG_STM32H7_TIM15_BRK1POL,
+#endif
+      /* No BREAK2 */
+    },
+#endif
+#ifdef CONFIG_STM32H7_TIM15_CH1OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM15_CH1POL,
+      .idle    = CONFIG_STM32H7_TIM15_CH1IDLE,
+      .pincfg  = PWM_TIM15_CH1CFG,
+    },
+#endif
+#ifdef CONFIG_STM32H7_TIM15_CH1NOUT
+    .out2    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM15_CH1NPOL,
+      .idle    = CONFIG_STM32H7_TIM15_CH1NIDLE,
+      .pincfg  = PWM_TIM15_CH2CFG,
+    }
+#endif
+  },
+#endif
+#ifdef CONFIG_STM32H7_TIM15_CHANNEL2
+  {
+    .channel = 2,
+    .mode    = CONFIG_STM32H7_TIM15_CH2MODE,
+#ifdef CONFIG_STM32H7_TIM12_CH2OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM15_CH2POL,
+      .idle    = CONFIG_STM32H7_TIM15_CH2IDLE,
+      .pincfg  = PWM_TIM15_CH2CFG,
+    }
+#endif
+    /* No complementary outputs */
+  },
+#endif
+};
+
+static struct stm32_pwmtimer_s g_pwm15dev =
+{
+  .ops         = &g_pwmops,
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+  .llops       = &g_llpwmops,
+#endif
+  .timid       = 15,
+  .chan_num    = PWM_TIM15_NCHANNELS,
+  .channels    = g_pwm15channels,
+  .timtype     = TIMTYPE_TIM15,
+  .mode        = STM32_TIMMODE_COUNTUP,
+  .lock        = CONFIG_STM32H7_TIM15_LOCK,
+  .t_dts       = CONFIG_STM32H7_TIM15_TDTS,
+#ifdef HAVE_PWM_COMPLEMENTARY
+  .deadtime    = CONFIG_STM32H7_TIM15_DEADTIME,
+#endif
+#if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO)
+  .trgo        = STM32_TIM15_TRGO,
+#endif
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM15,
+#endif
+  .base        = STM32_TIM15_BASE,
+  .pclk        = TIMCLK_TIM15,
+};
+#endif  /* CONFIG_STM32H7_TIM15_PWM */
+
+#ifdef CONFIG_STM32H7_TIM16_PWM
+
+static struct stm32_pwmchan_s g_pwm16channels[] =
+{
+  /* TIM16 has 1 channel, 1 complementary */
+
+#ifdef CONFIG_STM32H7_TIM16_CHANNEL1
+  {
+    .channel = 1,
+    .mode    = CONFIG_STM32H7_TIM16_CH1MODE,
+#ifdef HAVE_BREAK
+    .brk =
+    {
+#ifdef CONFIG_STM32H7_TIM16_BREAK1
+      .en1 = 1,
+      .pol1 = CONFIG_STM32H7_TIM16_BRK1POL,
+#endif
+      /* No BREAK2 */
+    },
+#endif
+#ifdef CONFIG_STM32H7_TIM16_CH1OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM16_CH1POL,
+      .idle    = CONFIG_STM32H7_TIM16_CH1IDLE,
+      .pincfg  = PWM_TIM16_CH1CFG,
+    },
+#endif
+#ifdef CONFIG_STM32H7_TIM16_CH1NOUT
+    .out2    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM16_CH1NPOL,
+      .idle    = CONFIG_STM32H7_TIM16_CH1NIDLE,
+      .pincfg  = PWM_TIM16_CH2CFG,
+    }
+#endif
+  },
+#endif
+};
+
+static struct stm32_pwmtimer_s g_pwm16dev =
+{
+  .ops         = &g_pwmops,
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+  .llops       = &g_llpwmops,
+#endif
+  .timid       = 16,
+  .chan_num    = PWM_TIM16_NCHANNELS,
+  .channels    = g_pwm16channels,
+  .timtype     = TIMTYPE_TIM16,
+  .mode        = STM32_TIMMODE_COUNTUP,
+  .lock        = CONFIG_STM32H7_TIM16_LOCK,
+  .t_dts       = CONFIG_STM32H7_TIM16_TDTS,
+#ifdef HAVE_PWM_COMPLEMENTARY
+  .deadtime    = CONFIG_STM32H7_TIM16_DEADTIME,
+#endif
+#if defined(HAVE_TRGO)
+  .trgo        = 0,             /* TRGO not supported for TIM16 */
+#endif
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM16,
+#endif
+  .base        = STM32_TIM16_BASE,
+  .pclk        = TIMCLK_TIM16,
+};
+#endif  /* CONFIG_STM32H7_TIM16_PWM */
+
+#ifdef CONFIG_STM32H7_TIM17_PWM
+
+static struct stm32_pwmchan_s g_pwm17channels[] =
+{
+  /* TIM17 has 1 channel, 1 complementary */
+
+#ifdef CONFIG_STM32H7_TIM17_CHANNEL1
+  {
+    .channel = 1,
+    .mode    = CONFIG_STM32H7_TIM17_CH1MODE,
+#ifdef HAVE_BREAK
+    .brk =
+    {
+#ifdef CONFIG_STM32H7_TIM17_BREAK1
+      .en1 = 1,
+      .pol1 = CONFIG_STM32H7_TIM17_BRK1POL,
+#endif
+      /* No BREAK2 */
+    },
+#endif
+#ifdef CONFIG_STM32H7_TIM17_CH1OUT
+    .out1    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM17_CH1POL,
+      .idle    = CONFIG_STM32H7_TIM17_CH1IDLE,
+      .pincfg  = PWM_TIM17_CH1CFG,
+    },
+#endif
+#ifdef CONFIG_STM32H7_TIM17_CH1NOUT
+    .out2    =
+    {
+      .in_use  = 1,
+      .pol     = CONFIG_STM32H7_TIM17_CH1NPOL,
+      .idle    = CONFIG_STM32H7_TIM17_CH1NIDLE,
+      .pincfg  = PWM_TIM17_CH2CFG,
+    }
+#endif
+  },
+#endif
+};
+
+static struct stm32_pwmtimer_s g_pwm17dev =
+{
+  .ops         = &g_pwmops,
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+  .llops       = &g_llpwmops,
+#endif
+  .timid       = 17,
+  .chan_num    = PWM_TIM17_NCHANNELS,
+  .channels    = g_pwm17channels,
+  .timtype     = TIMTYPE_TIM17,
+  .mode        = STM32_TIMMODE_COUNTUP,
+  .lock        = CONFIG_STM32H7_TIM17_LOCK,
+  .t_dts       = CONFIG_STM32H7_TIM17_TDTS,
+#ifdef HAVE_PWM_COMPLEMENTARY
+  .deadtime    = CONFIG_STM32H7_TIM17_DEADTIME,
+#endif
+#if defined(HAVE_TRGO)
+  .trgo        = 0,             /* TRGO not supported for TIM17 */
+#endif
+#ifdef CONFIG_PWM_PULSECOUNT
+  .irq         = STM32_IRQ_TIM17,
+#endif
+  .base        = STM32_TIM17_BASE,
+  .pclk        = TIMCLK_TIM17,
+};
+#endif  /* CONFIG_STM32H7_TIM17_PWM */
+
+/* TODO: support for TIM19,20,21,22 */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: pwm_reg_is_32bit
+ ****************************************************************************/
+
+static bool pwm_reg_is_32bit(uint8_t timtype, uint32_t offset)
+{
+  bool ret = false;
+
+  if (timtype == TIMTYPE_GENERAL32)
+    {
+      if (offset == STM32_GTIM_CNT_OFFSET ||
+          offset == STM32_GTIM_ARR_OFFSET ||
+          offset == STM32_GTIM_CCR1_OFFSET ||
+          offset == STM32_GTIM_CCR2_OFFSET ||
+          offset == STM32_GTIM_CCR3_OFFSET ||
+          offset == STM32_GTIM_CCR4_OFFSET)
+        {
+          ret = true;
+        }
+    }
+#ifdef HAVE_IP_TIMERS_V2
+  else if (timtype == TIMTYPE_ADVANCED)
+    {
+      if (offset == STM32_ATIM_CR2_OFFSET ||
+          offset == STM32_ATIM_CCMR1_OFFSET ||
+          offset == STM32_ATIM_CCMR2_OFFSET ||
+          offset == STM32_ATIM_CCER_OFFSET ||
+          offset == STM32_ATIM_BDTR_OFFSET ||
+          offset == STM32_ATIM_CCMR3_OFFSET ||
+          offset == STM32_ATIM_CCR5_OFFSET)
+        {
+          ret = true;
+        }
+    }
+#endif
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: pwm_getreg
+ *
+ * Description:
+ *   Read the value of an PWM timer register
+ *
+ * Input Parameters:
+ *   priv   - A reference to the PWM block status
+ *   offset - The offset to the register to read
+ *
+ * Returned Value:
+ *   The current contents of the specified register
+ *
+ ****************************************************************************/
+
+static uint32_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset)
+{
+  uint32_t retval = 0;
+
+  if (pwm_reg_is_32bit(priv->timtype, offset) == true)
+    {
+      /* 32-bit register */
+
+      retval = getreg32(priv->base + offset);
+    }
+  else
+    {
+      /* 16-bit register */
+
+      retval = getreg16(priv->base + offset);
+    }
+
+  /* Return 32-bit value */
+
+  return retval;
+}
+
+/****************************************************************************
+ * Name: pwm_putreg
+ *
+ * Description:
+ *   Read the value of an PWM timer register
+ *
+ * Input Parameters:
+ *   priv   - A reference to the PWM block status
+ *   offset - The offset to the register to read
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset,
+                       uint32_t value)
+{
+  if (pwm_reg_is_32bit(priv->timtype, offset) == true)
+    {
+      /* 32-bit register */
+
+      putreg32(value, priv->base + offset);
+    }
+  else
+    {
+      /* 16-bit register */
+
+      putreg16((uint16_t)value, priv->base + offset);
+    }
+}
+
+/****************************************************************************
+ * Name: pwm_modifyreg
+ *
+ * Description:
+ *   Modify PWM register (32-bit or 16-bit)
+ *
+ * Input Parameters:
+ *   priv    - A reference to the PWM block status
+ *   offset  - The offset to the register to read
+ *   clrbits - The bits to clear
+ *   setbits - The bits to set
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset,
+                            uint32_t clearbits, uint32_t setbits)
+{
+
+  if (pwm_reg_is_32bit(priv->timtype, offset) == true)
+    {
+      /* 32-bit register */
+
+      modifyreg32(priv->base + offset, clearbits, setbits);
+    }
+  else
+    {
+      /* 16-bit register */
+
+      modifyreg16(priv->base + offset, (uint16_t)clearbits,
+                  (uint16_t)setbits);
+    }
+}
+
+/****************************************************************************
+ * Name: pwm_dumpregs
+ *
+ * Description:
+ *   Dump all timer registers.
+ *
+ * Input Parameters:
+ *   priv - A reference to the PWM block status
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_PWM_INFO
+static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg)
+{
+  pwminfo("%s:\n", msg);
+  if (priv->timid == 16 || priv->timid == 17)
+    {
+      pwminfo("  CR1: %04x CR2:  %04x DIER:  %04x\n",
+              pwm_getreg(priv, STM32_GTIM_CR1_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CR2_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_DIER_OFFSET));
+    }
+  else
+    {
+      pwminfo("  CR1: %04x CR2:  %04x SMCR:  %04x DIER:  %04x\n",
+              pwm_getreg(priv, STM32_GTIM_CR1_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CR2_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_DIER_OFFSET));
+    }
+
+  if (priv->timid >= 15 && priv->timid <= 17)
+    {
+      pwminfo("   SR: %04x EGR:  %04x CCMR1: %04x\n",
+              pwm_getreg(priv, STM32_GTIM_SR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_EGR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET));
+    }
+   else
+    {
+      pwminfo("   SR: %04x EGR:  %04x CCMR1: %04x CCMR2: %04x\n",
+              pwm_getreg(priv, STM32_GTIM_SR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_EGR_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET));
+    }
+
+  /* REVISIT: CNT and ARR may be 32-bits wide */
+
+  pwminfo(" CCER: %04x CNT:  %04x PSC:   %04x ARR:   %04x\n",
+          pwm_getreg(priv, STM32_GTIM_CCER_OFFSET),
+          pwm_getreg(priv, STM32_GTIM_CNT_OFFSET),
+          pwm_getreg(priv, STM32_GTIM_PSC_OFFSET),
+          pwm_getreg(priv, STM32_GTIM_ARR_OFFSET));
+
+  if (priv->timid == 1 || priv->timid == 8 ||
+      (priv->timid >= 15 && priv->timid <= 17))
+    {
+      pwminfo("  RCR: %04x BDTR: %04x\n",
+          pwm_getreg(priv, STM32_ATIM_RCR_OFFSET),
+          pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET));
+    }
+
+  /* REVISIT: CCR1-CCR4 may be 32-bits wide */
+
+  if (priv->timid == 16 || priv->timid == 17)
+    {
+      pwminfo(" CCR1: %04x\n",
+              pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET));
+    }
+  else if (priv->timid == 15)
+    {
+      pwminfo(" CCR1: %04x CCR2: %04x\n",
+              pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET));
+    }
+  else
+    {
+      pwminfo(" CCR1: %04x CCR2: %04x CCR3:  %04x CCR4:  %04x\n",
+              pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET),
+              pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET));
+    }
+
+  pwminfo("  DCR: %04x DMAR: %04x\n",
+      pwm_getreg(priv, STM32_GTIM_DCR_OFFSET),
+      pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET));
+
+#ifdef HAVE_IP_TIMERS_V2
+  if (priv->timtype == TIMTYPE_ADVANCED)
+    {
+      pwminfo("  CCMR3: %04x CCR5: %04x CCR6: %04x\n",
+              pwm_getreg(priv, STM32_ATIM_CCMR3_OFFSET),
+              pwm_getreg(priv, STM32_ATIM_CCR5_OFFSET),
+              pwm_getreg(priv, STM32_ATIM_CCR6_OFFSET));
+    }
+#endif
+}
+#endif
+
+/****************************************************************************
+ * Name: pwm_ccr_update
+ ****************************************************************************/
+
+static int pwm_ccr_update(FAR struct pwm_lowerhalf_s *dev, uint8_t index,
+                          uint32_t ccr)
+
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint32_t offset = 0;
+
+  /* Only ADV timers have CC5 and CC6 */
+
+#ifdef HAVE_IP_TIMERS_V2
+  if (priv->timtype != TIMTYPE_ADVANCED && (index == 5 || index == 6))
+    {
+      pwmerr("ERROR: No such CCR: %u\n", index);
+      return -EINVAL;
+    }
+#endif
+
+  /* REVISIT: start index from 0? */
+
+  switch (index)
+    {
+      case STM32_PWM_CHAN1:
+        {
+          offset = STM32_GTIM_CCR1_OFFSET;
+          break;
+        }
+
+      case STM32_PWM_CHAN2:
+        {
+          offset = STM32_GTIM_CCR2_OFFSET;
+          break;
+        }
+
+      case STM32_PWM_CHAN3:
+        {
+          offset = STM32_GTIM_CCR3_OFFSET;
+          break;
+        }
+
+      case STM32_PWM_CHAN4:
+        {
+          offset = STM32_GTIM_CCR4_OFFSET;
+          break;
+        }
+
+#ifdef HAVE_IP_TIMERS_V2
+      case STM32_PWM_CHAN5:
+        {
+          offset = STM32_ATIM_CCR5_OFFSET;
+          break;
+        }
+
+      case STM32_PWM_CHAN6:
+        {
+          offset = STM32_ATIM_CCR6_OFFSET;
+          break;
+        }
+#endif
+
+      default:
+        {
+          pwmerr("ERROR: No such CCR: %u\n", index);
+          return -EINVAL;
+        }
+    }
+
+  /* Update CCR register */
+
+  pwm_putreg(priv, offset, ccr);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_ccr_get
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+static uint32_t pwm_ccr_get(FAR struct pwm_lowerhalf_s *dev, uint8_t index)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint32_t offset = 0;
+
+  switch (index)
+    {
+      case STM32_PWM_CHAN1:
+        {
+          offset = STM32_GTIM_CCR1_OFFSET;
+          break;
+        }
+
+      case STM32_PWM_CHAN2:
+        {
+          offset = STM32_GTIM_CCR2_OFFSET;
+          break;
+        }
+
+      case STM32_PWM_CHAN3:
+        {
+          offset = STM32_GTIM_CCR3_OFFSET;
+          break;
+        }
+
+      case STM32_PWM_CHAN4:
+        {
+          offset = STM32_GTIM_CCR4_OFFSET;
+          break;
+        }
+
+#ifdef HAVE_IP_TIMERS_V2
+      case STM32_PWM_CHAN5:
+        {
+          offset = STM32_ATIM_CCR5_OFFSET;
+          break;
+        }
+
+      case STM32_PWM_CHAN6:
+        {
+          offset = STM32_ATIM_CCR6_OFFSET;
+          break;
+        }
+#endif
+
+      default:
+        {
+          pwmerr("ERROR: No such CCR: %u\n", index);
+          return -EINVAL;
+        }
+    }
+
+  /* Return CCR register */
+
+  return pwm_getreg(priv, offset);
+}
+#endif  /* CONFIG_STM32H7_PWM_LL_OPS */
+
+/****************************************************************************
+ * Name: pwm_arr_update
+ ****************************************************************************/
+
+static int pwm_arr_update(FAR struct pwm_lowerhalf_s *dev, uint32_t arr)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+
+  /* Update ARR register */
+
+  pwm_putreg(priv, STM32_GTIM_ARR_OFFSET, arr);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_arr_get
+ ****************************************************************************/
+
+static uint32_t pwm_arr_get(FAR struct pwm_lowerhalf_s *dev)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+
+  return pwm_getreg(priv, STM32_GTIM_ARR_OFFSET);
+}
+
+/****************************************************************************
+ * Name: pwm_duty_update
+ *
+ * Description:
+ *   Try to change only channel duty
+ *
+ * Input Parameters:
+ *   dev     - A reference to the lower half PWM driver state structure
+ *   channel - Channel to by updated
+ *   duty    - New duty
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_duty_update(FAR struct pwm_lowerhalf_s *dev, uint8_t channel,
+                           ub16_t duty)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint32_t reload = 0;
+  uint32_t ccr    = 0;
+
+  /* We don't want compilation warnings if no DEBUGASSERT */
+
+  UNUSED(priv);
+
+  DEBUGASSERT(priv != NULL);
+
+  pwminfo("TIM%u channel: %u duty: %08x\n",
+          priv->timid, channel, duty);
+
+#ifndef CONFIG_PWM_MULTICHAN
+  DEBUGASSERT(channel == priv->channels[0].channel);
+  DEBUGASSERT(duty >= 0 && duty < uitoub16(100));
+#endif
+
+  /* Get the reload values */
+
+  reload = pwm_arr_get(dev);
+
+  /* Duty cycle:
+   *
+   * duty cycle = ccr / reload (fractional value)
+   */
+
+  ccr = b16toi(duty * reload + b16HALF);
+
+  pwminfo("ccr: %u\n", ccr);
+
+  /* Write coresponding CCR register */
+
+  pwm_ccr_update(dev, channel, ccr);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_timer_enable
+ ****************************************************************************/
+
+static int pwm_timer_enable(FAR struct pwm_lowerhalf_s *dev, bool state)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+
+  if (state == true)
+    {
+      /* Enable timer counter */
+
+      pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN);
+    }
+  else
+    {
+      /* Disable timer counter */
+
+      pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_frequency_update
+ *
+ * Description:
+ *   Update a PWM timer frequency
+ *
+ ****************************************************************************/
+
+static int pwm_frequency_update(FAR struct pwm_lowerhalf_s *dev,
+                                uint32_t frequency)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint32_t reload    = 0;
+  uint32_t timclk    = 0;
+  uint32_t prescaler = 0;
+
+  /* Calculate optimal values for the timer prescaler and for the timer reload
+   * register.  If 'frequency' is the desired frequency, then
+   *
+   *   reload = timclk / frequency
+   *   timclk = pclk / presc
+   *
+   * Or,
+   *
+   *   reload = pclk / presc / frequency
+   *
+   * There are many solutions to this this, but the best solution will be the
+   * one that has the largest reload value and the smallest prescaler value.
+   * That is the solution that should give us the most accuracy in the timer
+   * control.  Subject to:
+   *
+   *   0 <= presc  <= 65536
+   *   1 <= reload <= 65535
+   *
+   * So presc = pclk / 65535 / frequency would be optimal.
+   *
+   * Example:
+   *
+   *  pclk      = 42 MHz
+   *  frequency = 100 Hz
+   *
+   *  prescaler = 42,000,000 / 65,535 / 100
+   *            = 6.4 (or 7 -- taking the ceiling always)
+   *  timclk    = 42,000,000 / 7
+   *            = 6,000,000
+   *  reload    = 6,000,000 / 100
+   *            = 60,000
+   */
+
+  prescaler = (priv->pclk / frequency + 65534) / 65535;
+  if (prescaler < 1)
+    {
+      prescaler = 1;
+    }
+  else if (prescaler > 65536)
+    {
+      prescaler = 65536;
+    }
+
+  timclk = priv->pclk / prescaler;
+
+  reload = timclk / frequency;
+  if (reload < 2)
+    {
+      reload = 1;
+    }
+  else if (reload > 65535)
+    {
+      reload = 65535;
+    }
+  else
+    {
+      reload--;
+    }
+
+  pwminfo("TIM%u PCLK: %u frequency: %u TIMCLK: %u prescaler: %u reload: %u\n",
+          priv->timid, priv->pclk, frequency, timclk, prescaler, reload);
+
+  /* Set the reload and prescaler values */
+
+  pwm_arr_update(dev, reload);
+  pwm_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1));
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_timer_configure
+ *
+ * Description:
+ *   Initial configuration for PWM timer
+ *
+ ****************************************************************************/
+
+static int pwm_timer_configure(FAR struct stm32_pwmtimer_s *priv)
+{
+  uint16_t cr1 = 0;
+  int      ret = OK;
+
+  /* Set up the timer CR1 register:
+   *
+   * 1,8   CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN
+   * 2-5   CKD[1:0] ARPE CMS      DIR OPM URS UDIS CEN
+   * 6-7            ARPE              OPM URS UDIS CEN
+   * 9-14  CKD[1:0] ARPE                  URS UDIS CEN
+   * 15-17 CKD[1:0] ARPE              OPM URS UDIS CEN
+   */
+
+  cr1 = pwm_getreg(priv, STM32_GTIM_CR1_OFFSET);
+
+  /* Set the counter mode for the advanced timers (1,8) and most general
+   * purpose timers (all 2-5, but not 9-17), i.e., all but TIMTYPE_COUNTUP16
+   * and TIMTYPE_BASIC
+   */
+
+  if (priv->timtype != TIMTYPE_BASIC && priv->timtype != TIMTYPE_COUNTUP16)
+    {
+      /* Select the Counter Mode:
+       *
+       * GTIM_CR1_EDGE: The counter counts up or down depending on the
+       *   direction bit (DIR).
+       * GTIM_CR1_CENTER1, GTIM_CR1_CENTER2, GTIM_CR1_CENTER3: The counter
+       *   counts up then down.
+       * GTIM_CR1_DIR: 0: count up, 1: count down
+       */
+
+      cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK);
+
+      switch (priv->mode)
+        {
+          case STM32_TIMMODE_COUNTUP:
+            {
+              cr1 |= GTIM_CR1_EDGE;
+              break;
+            }
+
+          case STM32_TIMMODE_COUNTDOWN:
+            {
+              cr1 |= GTIM_CR1_EDGE | GTIM_CR1_DIR;
+              break;
+            }
+
+          case STM32_TIMMODE_CENTER1:
+            {
+              cr1 |= GTIM_CR1_CENTER1;
+              break;
+            }
+
+          case STM32_TIMMODE_CENTER2:
+            {
+              cr1 |= GTIM_CR1_CENTER2;
+              break;
+            }
+
+          case STM32_TIMMODE_CENTER3:
+            {
+              cr1 |= GTIM_CR1_CENTER3;
+              break;
+            }
+
+          default:
+            {
+              pwmerr("ERROR: No such timer mode: %u\n",
+                     (unsigned int)priv->mode);
+              ret = -EINVAL;
+              goto errout;
+            }
+        }
+    }
+
+  /* Enable ARR Preload
+   * TODO: this should be configurable
+   */
+
+  cr1 |= GTIM_CR1_ARPE;
+
+  /* Write CR1 */
+
+  pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1);
+
+errout:
+  return ret;
+}
+
+/****************************************************************************
+ * Name: pwm_mode_configure
+ *
+ * Description:
+ *   Configure a PWM mode for given channel
+ *
+ ****************************************************************************/
+
+static int pwm_mode_configure(FAR struct pwm_lowerhalf_s *dev,
+                              uint8_t channel, uint32_t mode)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint32_t chanmode = 0;
+  uint32_t ocmode   = 0;
+  uint32_t ccmr     = 0;
+  uint32_t offset   = 0;
+  int      ret      = OK;
+#ifdef HAVE_IP_TIMERS_V2
+  bool     ocmbit   = false;
+#endif
+
+#ifdef HAVE_IP_TIMERS_V2
+  /* Only advanced timers have channels 5-6 */
+
+  if (channel > 4 && priv->timtype != TIMTYPE_ADVANCED)
+    {
+      pwmerr("ERROR: No such channel: %u\n", channel);
+      ret = -EINVAL;
+      goto errout;
+    }
+#endif
+
+  /* Get channel mode
+   * TODO: configurable preload for CCxR
+   */
+
+  switch (mode)
+    {
+      case STM32_CHANMODE_FRZN:
+        {
+          chanmode = GTIM_CCMR_MODE_FRZN;
+          break;
+        }
+
+      case STM32_CHANMODE_CHACT:
+        {
+          chanmode = GTIM_CCMR_MODE_CHACT;
+          break;
+        }
+
+      case STM32_CHANMODE_CHINACT:
+        {
+          chanmode = GTIM_CCMR_MODE_CHINACT;
+          break;
+        }
+
+      case STM32_CHANMODE_OCREFTOG:
+        {
+          chanmode = GTIM_CCMR_MODE_OCREFTOG;
+          break;
+        }
+
+      case STM32_CHANMODE_OCREFLO:
+        {
+          chanmode = GTIM_CCMR_MODE_OCREFLO;
+          break;
+        }
+
+      case STM32_CHANMODE_OCREFHI:
+        {
+          chanmode = GTIM_CCMR_MODE_OCREFHI;
+          break;
+        }
+
+      case STM32_CHANMODE_PWM1:
+        {
+          chanmode = ATIM_CCMR_MODE_PWM1;
+          break;
+        }
+
+      case STM32_CHANMODE_PWM2:
+        {
+          chanmode = ATIM_CCMR_MODE_PWM2;
+          break;
+        }
+
+#ifdef HAVE_IP_TIMERS_V2
+      case STM32_CHANMODE_COMBINED1:
+        {
+          chanmode = ATIM_CCMR_MODE_COMBINED1;
+          ocmbit   = true;
+          break;
+        }
+
+      case STM32_CHANMODE_COMBINED2:
+        {
+          chanmode = ATIM_CCMR_MODE_COMBINED2;
+          ocmbit   = true;
+          break;
+        }
+
+      case STM32_CHANMODE_ASYMMETRIC1:
+        {
+          chanmode = ATIM_CCMR_MODE_ASYMMETRIC1;
+          ocmbit   = true;
+          break;
+        }
+
+      case STM32_CHANMODE_ASYMMETRIC2:
+        {
+          chanmode = ATIM_CCMR_MODE_ASYMMETRIC2;
+          ocmbit   = true;
+          break;
+        }
+#endif
+
+      default:
+        {
+          pwmerr("ERROR: No such mode: %u\n", (unsigned int)mode);
+          ret = -EINVAL;
+          goto errout;
+        }
+    }
+
+  /* Get CCMR offset */
+
+  switch (channel)
+    {
+      case STM32_PWM_CHAN1:
+      case STM32_PWM_CHAN2:
+        {
+          offset = STM32_GTIM_CCMR1_OFFSET;
+          break;
+        }
+
+      case STM32_PWM_CHAN3:
+      case STM32_PWM_CHAN4:
+        {
+          offset = STM32_GTIM_CCMR2_OFFSET;
+          break;
+        }
+
+#ifdef HAVE_IP_TIMERS_V2
+      case STM32_PWM_CHAN5:
+      case STM32_PWM_CHAN6:
+        {
+          offset = STM32_ATIM_CCMR3_OFFSET;
+          break;
+        }
+#endif
+
+      default:
+        {
+          pwmerr("ERROR: No such channel: %u\n", channel);
+          ret = -EINVAL;
+          goto errout;
+        }
+    }
+
+  /* Get current registers */
+
+  ccmr = pwm_getreg(priv, offset);
+
+  /* PWM mode configuration.
+   * NOTE: The CCMRx registers are identical if the channels are outputs.
+   */
+
+  switch (channel)
+    {
+      /* Configure channel 1/3/5 */
+
+      case STM32_PWM_CHAN1:
+      case STM32_PWM_CHAN3:
+#ifdef HAVE_IP_TIMERS_V2
+      case STM32_PWM_CHAN5:
+#endif
+        {
+          /* Reset current channel 1/3/5 mode configuration */
+
+          ccmr &= ~(ATIM_CCMR1_CC1S_MASK | ATIM_CCMR1_OC1M_MASK |
+                     ATIM_CCMR1_OC1PE);
+
+          /* Configure CC1/3/5 as output */
+
+          ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT);
+
+          /* Configure Compare 1/3/5 mode */
+
+          ocmode |= (chanmode << ATIM_CCMR1_OC1M_SHIFT);
+
+          /* Enable CCR1/3/5 preload */
+
+          ocmode |= ATIM_CCMR1_OC1PE;
+
+#ifdef HAVE_IP_TIMERS_V2
+          /* Reset current OC bit */
+
+          ccmr &= ~(ATIM_CCMR1_OC1M);
+
+          /* Set an additional OC1/3/5M bit */
+
+          if (ocmbit)
+            {
+              ocmode |= ATIM_CCMR1_OC1M;
+            }
+#endif
+          break;
+        }
+
+      /* Configure channel 2/4/6 */
+
+      case STM32_PWM_CHAN2:
+      case STM32_PWM_CHAN4:
+#ifdef HAVE_IP_TIMERS_V2
+      case STM32_PWM_CHAN6:
+#endif
+        {
+          /* Reset current channel 2/4/6 mode configuration */
+
+          ccmr &= ~(ATIM_CCMR1_CC2S_MASK | ATIM_CCMR1_OC2M_MASK |
+                     ATIM_CCMR1_OC2PE);
+
+          /* Configure CC2/4/6 as output */
+
+          ocmode |= (ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC2S_SHIFT);
+
+          /* Configure Compare 2/4/6 mode */
+
+          ocmode |= (chanmode << ATIM_CCMR1_OC2M_SHIFT);
+
+          /* Enable CCR2/4/6 preload */
+
+          ocmode |= ATIM_CCMR1_OC2PE;
+
+#ifdef HAVE_IP_TIMERS_V2
+          /* Reset current OC bit */
+
+          ccmr &= ~(ATIM_CCMR1_OC2M);
+
+          /* Set an additioneal OC2/4/6M bit */
+
+          if (ocmbit)
+            {
+              ocmode |= ATIM_CCMR1_OC2M;
+            }
+#endif
+          break;
+        }
+    }
+
+  /* Set the selected output compare mode */
+
+  ccmr |= ocmode;
+
+  /* Write CCMRx registers */
+
+  pwm_putreg(priv, offset, ccmr);
+
+errout:
+  return ret;
+}
+
+/****************************************************************************
+ * Name: pwm_output_configure
+ *
+ * Description:
+ *   Configure PWM output for given channel
+ *
+ ****************************************************************************/
+
+static int pwm_output_configure(FAR struct stm32_pwmtimer_s *priv,
+                                uint8_t channel)
+{
+  uint32_t cr2  = 0;
+  uint32_t ccer = 0;
+
+  /* Get current registers state */
+
+  cr2  = pwm_getreg(priv, STM32_GTIM_CR2_OFFSET);
+  ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET);
+
+  /* | OISx/OISxN  | IDLE | for ADVANCED and COUNTUP16 | CR2 register
+   * | CCxP/CCxNP  | POL  | all PWM timers             | CCER register
+   */
+
+  /* Configure output polarity (all PWM timers) */
+
+  if (priv->channels[channel-1].out1.pol == STM32_POL_NEG)
+    {
+      ccer |= (GTIM_CCER_CC1P << ((channel-1)*4));
+    }
+  else
+    {
+      ccer &= ~(GTIM_CCER_CC1P << ((channel-1)*4));
+    }
+
+#ifdef HAVE_ADVTIM
+  if (priv->timtype == TIMTYPE_ADVANCED ||
+      priv->timtype == TIMTYPE_COUNTUP16_N)
+    {
+      /* Configure output IDLE State */
+
+      if (priv->channels[channel-1].out1.idle == STM32_IDLE_ACTIVE)
+        {
+          cr2 |= (ATIM_CR2_OIS1 << ((channel-1)*2));
+        }
+      else
+        {
+          cr2 &= ~(ATIM_CR2_OIS1 << ((channel-1)*2));
+        }
+
+#ifdef HAVE_PWM_COMPLEMENTARY
+      /* Configure complementary output IDLE state */
+
+      if (priv->channels[channel-1].out2.idle == STM32_IDLE_ACTIVE)
+        {
+          cr2 |= (ATIM_CR2_OIS1N << ((channel-1)*2));
+        }
+      else
+        {
+          cr2 &= ~(ATIM_CR2_OIS1N << ((channel-1)*2));
+        }
+
+      /* Configure complementary output polarity */
+
+      if (priv->channels[channel-1].out2.pol == STM32_POL_NEG)
+        {
+          ccer |= (ATIM_CCER_CC1NP << ((channel-1)*4));
+        }
+      else
+        {
+          ccer &= ~(ATIM_CCER_CC1NP << ((channel-1)*4));
+        }
+#endif  /* HAVE_PWM_COMPLEMENTARY */
+
+#ifdef HAVE_IP_TIMERS_V2
+      /* TODO: OIS5 and OIS6 */
+
+      cr2 &= ~(ATIM_CR2_OIS5 | ATIM_CR2_OIS6);
+
+      /* TODO: CC5P and CC6P */
+
+      ccer &= ~(ATIM_CCER_CC5P | ATIM_CCER_CC6P);
+#endif  /* HAVE_IP_TIMERS_V2 */
+    }
+#ifdef HAVE_GTIM_CCXNP
+  else
+#endif  /* HAVE_GTIM_CCXNP */
+#endif  /* HAVE_ADVTIM */
+#ifdef HAVE_GTIM_CCXNP
+    {
+      /* CCxNP must be cleared if not ADVANCED timer.
+       *
+       * REVISIT: not all families have CCxNP bits for GTIM,
+       *          which causes an ugly condition above
+       */
+
+      ccer &= ~(GTIM_CCER_CC1NP << ((channel-1)*4));
+    }
+#endif  /* HAVE_GTIM_CCXNP */
+
+  /* Write registers */
+
+  pwm_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2);
+  pwm_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_outputs_enable
+ *
+ * Description:
+ *   Enable/disable given timer PWM outputs.
+ *
+ *   NOTE: This is bulk operation - we can enable/disable many outputs
+ *   at one time
+ *
+ * Input Parameters:
+ *   dev     - A reference to the lower half PWM driver state structure
+ *   outputs - outputs to set (look at enum stm32_chan_e in stm32_pwm.h)
+ *   state   - Enable/disable operation
+ *
+ ****************************************************************************/
+
+static int pwm_outputs_enable(FAR struct pwm_lowerhalf_s *dev,
+                              uint16_t outputs, bool state)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint32_t ccer   = 0;
+  uint32_t regval = 0;
+
+  /* Get curren register state */
+
+  ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET);
+
+  /* Get outputs configuration */
+
+  regval |= ((outputs & STM32_PWM_OUT1)  ? ATIM_CCER_CC1E  : 0);
+  regval |= ((outputs & STM32_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0);
+  regval |= ((outputs & STM32_PWM_OUT2)  ? ATIM_CCER_CC2E  : 0);
+  regval |= ((outputs & STM32_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0);
+  regval |= ((outputs & STM32_PWM_OUT3)  ? ATIM_CCER_CC3E  : 0);
+  regval |= ((outputs & STM32_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0);
+  regval |= ((outputs & STM32_PWM_OUT4)  ? ATIM_CCER_CC4E  : 0);
+
+  /* NOTE: CC4N does not exist, but some docs show configuration bits for it */
+
+#ifdef HAVE_IP_TIMERS_V2
+  regval |= ((outputs & STM32_PWM_OUT5)  ? ATIM_CCER_CC5E  : 0);
+  regval |= ((outputs & STM32_PWM_OUT6)  ? ATIM_CCER_CC6E  : 0);
+#endif
+
+  if (state == true)
+    {
+      /* Enable outpus - set bits */
+
+      ccer |= regval;
+    }
+  else
+    {
+      /* Disable outputs - reset bits */
+
+      ccer &= ~regval;
+    }
+
+  /* Write register */
+
+  pwm_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer);
+
+  return OK;
+}
+
+#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H7_PWM_LL_OPS)
+
+/****************************************************************************
+ * Name: pwm_deadtime_update
+ ****************************************************************************/
+
+static int pwm_deadtime_update(FAR struct pwm_lowerhalf_s *dev, uint8_t dt)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint32_t bdtr = 0;
+  int      ret  = OK;
+
+  /* Check if locked */
+
+  if (priv->lock > 0)
+    {
+      ret = -EACCES;
+      goto errout;
+    }
+
+  /* Get current register state */
+
+  bdtr = pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET);
+
+  /* TODO: check if BDTR not locked */
+
+  /* Update deadtime */
+
+  bdtr &= ~(ATIM_BDTR_DTG_MASK);
+  bdtr |= (dt << ATIM_BDTR_DTG_SHIFT);
+
+  /* Write BDTR register */
+
+  pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr);
+
+errout:
+  return ret;
+}
+#endif
+
+#ifdef HAVE_TRGO
+/****************************************************************************
+ * Name: pwm_sync_configure
+ *
+ * Description:
+ *   Confiugre an output synchronisation event for PWM timer (TRGO/TRGO2)
+ *
+ ****************************************************************************/
+
+static int pwm_sync_configure(FAR struct stm32_pwmtimer_s *priv, uint8_t trgo)
+{
+  uint32_t cr2 = 0;
+
+  /* Configure TRGO (4 LSB in trgo) */
+
+  cr2 |= (((trgo >> 0) & 0x0f) << ATIM_CR2_MMS_SHIFT) & ATIM_CR2_MMS_MASK;
+
+#ifdef HAVE_IP_TIMERS_V2
+  /* Configure TRGO2 (4 MSB in trgo) */
+
+  cr2 |= (((trgo >> 4) & 0x0f) << ATIM_CR2_MMS2_SHIFT) & ATIM_CR2_MMS2_MASK;
+#endif
+
+  /* Write register */
+
+  pwm_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2);
+
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: pwm_soft_update
+ *
+ * Description:
+ *   Generate an software update event
+ *
+ ****************************************************************************/
+
+static int pwm_soft_update(FAR struct pwm_lowerhalf_s *dev)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+
+  pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, ATIM_EGR_UG);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_soft_break
+ *
+ * Description:
+ *   Generate an software break event
+ *
+ *   Outputs are enabled if state is false.
+ *   Outputs are disabled if state is true.
+ *
+ *   NOTE: only timers with complementary outputs have BDTR register and
+ *         support software break.
+ *
+ ****************************************************************************/
+
+static int pwm_soft_break(FAR struct pwm_lowerhalf_s *dev, bool state)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+
+  if (state == true)
+    {
+      /* Reset MOE bit */
+
+      pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0);
+    }
+  else
+    {
+      /* Set MOE bit */
+
+      pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_outputs_from_channels
+ *
+ * Description:
+ *   Get enabled outputs configuration from the PWM timer state
+ *
+ ****************************************************************************/
+
+static uint16_t pwm_outputs_from_channels(FAR struct stm32_pwmtimer_s *priv)
+{
+  uint16_t outputs = 0;
+  uint8_t  channel = 0;
+  uint8_t  i       = 0;
+
+  for (i = 0; i < priv->chan_num; i += 1)
+    {
+      /* Get channel */
+
+      channel = priv->channels[i].channel;
+
+      /* Set outputs if channel configured */
+
+      if (channel != 0)
+        {
+          /* Enable output if confiugred */
+
+          if (priv->channels[i].out1.in_use == 1)
+            {
+              outputs |= (STM32_PWM_OUT1 << ((channel-1)*2));
+            }
+
+#ifdef HAVE_PWM_COMPLEMENTARY
+          /* Enable complementary output if configured */
+
+          if (priv->channels[i].out2.in_use == 1)
+            {
+              outputs |= (STM32_PWM_OUT1N << ((channel-1)*2));
+            }
+#endif
+        }
+    }
+
+  return outputs;
+}
+
+#ifdef HAVE_ADVTIM
+
+/****************************************************************************
+ * Name: pwm_break_dt_configure
+ *
+ * Description:
+ *   Configure break and deadtime
+ *
+ * NOTE: we have to configure all BDTR registers at once due to possible
+ *       lock configuration
+ *
+ ****************************************************************************/
+
+static int pwm_break_dt_configure(FAR struct stm32_pwmtimer_s *priv)
+{
+  uint32_t bdtr = 0;
+
+  /* Set the clock division to zero for all (but the basic timers, but there
+   * should be no basic timers in this context
+   */
+
+  pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CKD_MASK,
+                priv->t_dts << GTIM_CR1_CKD_SHIFT);
+
+#ifdef HAVE_PWM_COMPLEMENTARY
+  /* Initialize deadtime */
+
+  bdtr |= (priv->deadtime << ATIM_BDTR_DTG_SHIFT);
+#endif
+
+#ifdef HAVE_BREAK
+  /* Configure Break 1 */
+
+  if (priv->brk.en1 == 1)
+    {
+      /* Enable Break 1 */
+
+      bdtr |= ATIM_BDTR_BKE;
+
+      /* Set Break 1 polarity */
+
+      bdtr |= (priv->brk.pol1 == STM32_POL_NEG ? ATIM_BDTR_BKP : 0);
+    }
+
+#ifdef HAVE_IP_TIMERS_V2
+  /* Configure Break 1 */
+
+  if (priv->brk.en2 == 1)
+    {
+      /* Enable Break 2 */
+
+      bdtr |= ATIM_BDTR_BK2E;
+
+      /* Set Break 2 polarity */
+
+      bdtr |= (priv->brk.pol2 == STM32_POL_NEG ? ATIM_BDTR_BK2P : 0);
+
+      /* Configure BRK2 filter */
+
+      bdtr |= (priv->brk.flt2 << ATIM_BDTR_BK2F_SHIFT);
+
+    }
+#endif  /* HAVE_IP_TIMERS_V2 */
+#endif  /* HAVE_BREAK */
+
+  /* Clear the OSSI and OSSR bits in the BDTR register.
+   *
+   * REVISIT: this should be configurable
+   */
+
+  bdtr &= ~(ATIM_BDTR_OSSI | ATIM_BDTR_OSSR);
+
+  /* Configure lock */
+
+  bdtr |= priv->lock << ATIM_BDTR_LOCK_SHIFT;
+
+  /* Write BDTR register at once */
+
+  pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr);
+
+  return OK;
+}
+#endif
+
+#ifdef CONFIG_PWM_PULSECOUNT
+
+/****************************************************************************
+ * Name: pwm_pulsecount_configure
+ *
+ * Description:
+ *   Configure PWM timer in PULSECOUNT mode
+ *
+ ****************************************************************************/
+
+static int pwm_pulsecount_configure(FAR struct pwm_lowerhalf_s *dev)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint16_t outputs = 0;
+  uint8_t j        = 0;
+  int     ret      = OK;
+
+  UNUSED(priv);
+
+  /* NOTE: leave timer counter disabled and all outputs disabled! */
+
+  /* Disable the timer until we get it configured */
+
+  pwm_timer_enable(dev, false);
+
+  /* Get configured outputs */
+
+  outputs = pwm_outputs_from_channels(priv);
+
+  /* REVISIT: Disable outputs */
+
+  ret = pwm_outputs_enable(dev, outputs, false);
+  if (ret < 0)
+    {
+      goto errout;
+    }
+
+  /* Initial timer configuration */
+
+  ret = pwm_timer_configure(priv);
+  if (ret < 0)
+    {
+      goto errout;
+    }
+
+  /* Configure break and deadtime register */
+
+  ret = pwm_break_dt_configure(priv);
+  if (ret < 0)
+    {
+      goto errout;
+    }
+
+  /* Disable software break (enable outputs) */
+
+  ret = pwm_soft_break(dev, false);
+  if (ret < 0)
+    {
+      goto errout;
+    }
+
+#ifdef HAVE_TRGO
+  /* Configure TRGO/TRGO2 */
+
+  ret = pwm_sync_configure(priv, priv->trgo);
+  if (ret < 0)
+    {
+      goto errout;
+    }
+#endif
+
+  /* Configure timer channels */
+
+  for (j = 0; j < priv->chan_num; j++)
+    {
+      /* Skip channle if not in use */
+
+      if (priv->channels[j].channel != 0)
+        {
+          /* Update PWM mode */
+
+          pwm_mode_configure(dev, priv->channels[j].channel,
+                             priv->channels[j].mode);
+
+          /* PWM outputs configuration */
+
+          pwm_output_configure(priv, priv->channels[j].channel);
+        }
+    }
+
+errout:
+  return ret;
+}
+
+/****************************************************************************
+ * Name: pwm_pulsecount_timer
+ *
+ * Description:
+ *   (Re-)initialize the timer resources and start the pulsed output
+ *
+ * Input Parameters:
+ *   dev  - A reference to the lower half PWM driver state structure
+ *   info - A reference to the characteristics of the pulsed output
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ * TODO: PWM_PULSECOUNT should be configurable for each timer instance
+ * TODO: PULSECOUNT doesnt work with MULTICHAN at this moment
+ *
+ ****************************************************************************/
+
+static int pwm_pulsecount_timer(FAR struct pwm_lowerhalf_s *dev,
+                                FAR const struct pwm_info_s *info)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  ub16_t    duty    = 0;
+  uint8_t   channel = 0;
+  uint32_t  mode    = 0;
+  uint16_t  outputs = 0;
+  int       ret     = OK;
+
+  /* If we got here it means that timer instance support pulsecount mode! */
+
+  DEBUGASSERT(priv != NULL && info != NULL);
+
+  pwminfo("TIM%u channel: %u frequency: %u duty: %08x count: %u\n",
+          priv->timid, priv->channels[0].channel, info->frequency,
+          info->duty, info->count);
+
+  DEBUGASSERT(info->frequency > 0);
+
+  /* Channel specific setup */
+
+  duty    = info->duty;
+  channel = priv->channels[0].channel;
+  mode    = priv->channels[0].mode;
+
+  /* Disable all interrupts and DMA requests, clear all pending status */
+
+  pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0);
+  pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0);
+
+  /* Set timer frequency */
+
+  ret = pwm_frequency_update(dev, info->frequency);
+  if (ret < 0)
+    {
+      goto errout;
+    }
+
+  /* Update duty cycle */
+
+  ret = pwm_duty_update(dev, channel, duty);
+  if (ret < 0)
+    {
+      goto errout;
+    }
+
+  /* If a non-zero repetition count has been selected, then set the
+   * repitition counter to the count-1 (pwm_pulsecount_start() has already
+   * assured us that the count value is within range).
+   */
+
+  if (info->count > 0)
+    {
+      /* Save the remaining count and the number of counts that will have
+       * elapsed on the first interrupt.
+       */
+
+      /* If the first interrupt occurs at the end end of the first
+       * repetition count, then the count will be the same as the RCR
+       * value.
+       */
+
+      priv->prev  = pwm_pulsecount(info->count);
+      pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->prev - 1);
+
+      /* Generate an update event to reload the prescaler.  This should
+       * preload the RCR into active repetition counter.
+       */
+
+      pwm_soft_update(dev);
+
+#if 0
+      /* Now set the value of the RCR that will be loaded on the next
+       * update event.
+       */
+
+      priv->count = info->count;
+      priv->curr  = pwm_pulsecount(info->count - priv->prev);
+      pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->curr - 1);
+#endif
+    }
+
+  /* Otherwise, just clear the repetition counter */
+
+  else
+    {
+      /* Set the repetition counter to zero */
+
+      pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, 0);
+
+      /* Generate an update event to reload the prescaler */
+
+      pwm_soft_update(dev);
+    }
+
+  /* Get configured outputs */
+
+  outputs = pwm_outputs_from_channels(priv);
+
+  /* Enable output */
+
+  ret = pwm_outputs_enable(dev, outputs, true);
+  if (ret < 0)
+    {
+      goto errout;
+    }
+
+  /* Setup update interrupt.  If info->count is > 0, then we can be
+   * assured that pwm_pulsecount_start() has already verified: (1) that this
+   * is an advanced timer, and that (2) the repetition count is within range.
+   */
+
+  if (info->count > 0)
+    {
+      /* Clear all pending interrupts and enable the update interrupt. */
+
+      pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0);
+      pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, ATIM_DIER_UIE);
+
+      /* Enable the timer */
+
+      pwm_timer_enable(dev, true);
+
+      /* And enable timer interrupts at the NVIC */
+
+      up_enable_irq(priv->irq);
+    }
+
+  pwm_dumpregs(priv, "After starting");
+
+errout:
+  return ret;
+}
+
+#else  /* !CONFIG_PWM_PULSECOUNT */
+
+/****************************************************************************
+ * Name: pwm_configure
+ *
+ * Description:
+ *   Configure PWM timer in normal mode (no PULSECOUNT)
+ *
+ ****************************************************************************/
+
+static int pwm_configure(FAR struct pwm_lowerhalf_s *dev)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint16_t outputs = 0;
+  uint8_t j        = 0;
+  int     ret      = OK;
+
+  /* NOTE: leave timer counter disabled and all outputs disabled! */
+
+  /* Get configured outputs */
+
+  outputs = pwm_outputs_from_channels(priv);
+
+  /* Disable outputs */
+
+  ret = pwm_outputs_enable(dev, outputs, false);
+  if (ret < 0)
+    {
+      goto errout;
+    }
+
+  /* Disable the timer until we get it configured */
+
+  pwm_timer_enable(dev, false);
+
+  /* Initial timer configuration */
+
+  ret = pwm_timer_configure(priv);
+  if (ret < 0)
+    {
+      goto errout;
+    }
+
+  /* Some special setup for advanced timers */
+
+#ifdef HAVE_ADVTIM
+  if (priv->timtype == TIMTYPE_ADVANCED ||
+      priv->timtype == TIMTYPE_COUNTUP16_N)
+    {
+      /* Configure break and deadtime register */
+
+      ret = pwm_break_dt_configure(priv);
+      if (ret < 0)
+        {
+          goto errout;
+        }
+
+#ifdef HAVE_TRGO
+      /* Configure TRGO/TRGO2 */
+
+      ret = pwm_sync_configure(priv, priv->trgo);
+      if (ret < 0)
+        {
+          goto errout;
+        }
+#endif
+    }
+#endif
+
+  /* Configure timer channels */
+
+  for (j = 0; j < priv->chan_num; j++)
+    {
+      /* Skip channle if not in use */
+
+      if (priv->channels[j].channel != 0)
+        {
+          /* Update PWM mode */
+
+          ret = pwm_mode_configure(dev, priv->channels[j].channel,
+                                   priv->channels[j].mode);
+          if (ret < 0)
+            {
+              goto errout;
+            }
+
+          /* PWM outputs configuration */
+
+          ret = pwm_output_configure(priv, priv->channels[j].channel);
+          if (ret < 0)
+            {
+              goto errout;
+            }
+        }
+    }
+
+  /* Disable software break at the end of the outputs configuration (enablei
+   * outputs).
+   *
+   * NOTE: Only timers with complementary outputs have BDTR register and
+   *       support software break.
+   */
+
+  if (priv->timtype == TIMTYPE_ADVANCED ||
+      priv->timtype == TIMTYPE_COUNTUP16_N)
+    {
+      ret = pwm_soft_break(dev, false);
+      if (ret < 0)
+        {
+          goto errout;
+        }
+    }
+
+errout:
+  return ret;
+}
+
+/****************************************************************************
+ * Name: pwm_duty_channels_update
+ *
+ * Description:
+ *   Update duty cycle for given channels
+ *
+ ****************************************************************************/
+
+static int pwm_duty_channels_update(FAR struct pwm_lowerhalf_s *dev,
+                                    FAR const struct pwm_info_s *info)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint8_t   channel = 0;
+  ub16_t    duty    = 0;
+  int       ret     = OK;
+#ifdef CONFIG_PWM_MULTICHAN
+  int       i       = 0;
+  int       j       = 0;
+#endif
+
+#ifdef CONFIG_PWM_MULTICHAN
+  for (i = 0; i < CONFIG_PWM_NCHANNELS; i++)
+#endif
+    {
+#ifdef CONFIG_PWM_MULTICHAN
+      duty    = info->channels[i].duty;
+      channel = info->channels[i].channel;
+
+      /* A value of zero means to skip this channel */
+
+      if (channel != 0)
+        {
+          /* Find the channel */
+
+          for (j = 0; j < priv->chan_num; j++)
+            {
+              if (priv->channels[j].channel == channel)
+                {
+                  break;
+                }
+            }
+
+          /* Check range */
+
+          if (j >= priv->chan_num)
+            {
+              pwmerr("ERROR: No such channel: %u\n", channel);
+              ret = -EINVAL;
+              goto errout;
+            }
+#else
+          duty = info->duty;
+          channel = priv->channels[0].channel;
+#endif
+
+          /* Update duty cycle */
+
+          ret = pwm_duty_update(dev, channel, duty);
+          if (ret < 0)
+            {
+              goto errout;
+            }
+#ifdef CONFIG_PWM_MULTICHAN
+        }
+#endif
+    }
+
+errout:
+  return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_timer
+ *
+ * Description:
+ *   (Re-)initialize the timer resources and start the pulsed output
+ *
+ * Input Parameters:
+ *   dev  - A reference to the lower half PWM driver state structure
+ *   info - A reference to the characteristics of the pulsed output
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_timer(FAR struct pwm_lowerhalf_s *dev,
+                     FAR const struct pwm_info_s *info)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint16_t outputs = 0;
+  int      ret     = OK;
+
+  DEBUGASSERT(priv != NULL && info != NULL);
+
+#if defined(CONFIG_PWM_MULTICHAN)
+  pwminfo("TIM%u frequency: %u\n",
+          priv->timid, info->frequency);
+#else
+  pwminfo("TIM%u channel: %u frequency: %u duty: %08x\n",
+          priv->timid, priv->channels[0].channel,
+          info->frequency, info->duty);
+#endif
+
+  DEBUGASSERT(info->frequency > 0);
+#ifndef CONFIG_PWM_MULTICHAN
+  DEBUGASSERT(info->duty >= 0 && info->duty < uitoub16(100));
+#endif
+
+  /* TODO: what if we have pwm running and we want disable some channels ? */
+
+  /* Set timer frequency */
+
+  ret = pwm_frequency_update(dev, info->frequency);
+  if (ret < 0)
+    {
+      goto errout;
+    }
+
+  /* Channel specific configuration */
+
+  ret = pwm_duty_channels_update(dev, info);
+  if (ret < 0)
+    {
+      goto errout;
+    }
+
+  /* Set the advanced timer's repetition counter */
+
+#ifdef HAVE_ADVTIM
+  if (priv->timtype == TIMTYPE_ADVANCED ||
+      priv->timtype == TIMTYPE_COUNTUP16_N)
+    {
+      /* If a non-zero repetition count has been selected, then set the
+       * repitition counter to the count-1 (pwm_start() has already
+       * assured us that the count value is within range).
+       */
+
+      /* Set the repetition counter to zero */
+
+      pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, 0);
+
+      /* Generate an update event to reload the prescaler */
+
+      pwm_soft_update(dev);
+    }
+  else
+#endif
+    {
+      /* Generate an update event to reload the prescaler (all timers) */
+
+      pwm_soft_update(dev);
+    }
+
+  /* Get configured outputs */
+
+  outputs = pwm_outputs_from_channels(priv);
+
+  /* Enable outputs */
+
+  ret = pwm_outputs_enable(dev, outputs, true);
+  if (ret < 0)
+    {
+      goto errout;
+    }
+
+  /* Just enable the timer, leaving all interrupts disabled */
+
+  pwm_timer_enable(dev, true);
+
+  pwm_dumpregs(priv, "After starting");
+
+errout:
+  return ret;
+}
+#endif  /* CONFIG_PWM_PULSECOUNT */
+
+#ifdef HAVE_PWM_INTERRUPT
+
+/****************************************************************************
+ * Name: pwm_interrupt
+ *
+ * Description:
+ *   Handle timer interrupts.
+ *
+ * Input Parameters:
+ *   dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_interrupt(FAR struct pwm_lowerhalf_s *dev)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint16_t regval;
+
+  /* Verify that this is an update interrupt.  Nothing else is expected. */
+
+  regval = pwm_getreg(priv, STM32_ATIM_SR_OFFSET);
+  DEBUGASSERT((regval & ATIM_SR_UIF) != 0);
+
+  /* Clear the UIF interrupt bit */
+
+  pwm_putreg(priv, STM32_ATIM_SR_OFFSET, (regval & ~ATIM_SR_UIF));
+
+  /* Calculate the new count by subtracting the number of pulses
+   * since the last interrupt.
+   */
+
+  if (priv->count <= priv->prev)
+    {
+      /* We are finished.  Turn off the master output to stop the output as
+       * quickly as possible.
+       */
+
+      pwm_soft_break(dev, true);
+
+      /* Disable first interrtups, stop and reset the timer */
+
+      (void)pwm_stop(dev);
+
+      /* Then perform the callback into the upper half driver */
+
+      pwm_expired(priv->handle);
+
+      priv->handle = NULL;
+      priv->count  = 0;
+      priv->prev   = 0;
+      priv->curr   = 0;
+    }
+  else
+    {
+      /* Decrement the count of pulses remaining using the number of
+       * pulses generated since the last interrupt.
+       */
+
+      priv->count -= priv->prev;
+
+      /* Set up the next RCR.  Set 'prev' to the value of the RCR that
+       * was loaded when the update occurred (just before this interrupt)
+       * and set 'curr' to the current value of the RCR register (which
+       * will bet loaded on the next update event).
+       */
+
+      priv->prev = priv->curr;
+      priv->curr = pwm_pulsecount(priv->count - priv->prev);
+      pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->curr - 1);
+    }
+
+  /* Now all of the time critical stuff is done so we can do some debug
+   * output.
+   */
+
+  pwminfo("Update interrupt SR: %04x prev: %u curr: %u count: %u\n",
+          regval, priv->prev, priv->curr, priv->count);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: pwm_tim1/8interrupt
+ *
+ * Description:
+ *   Handle timer 1 and 8 interrupts.
+ *
+ * Input Parameters:
+ *   Standard NuttX interrupt inputs
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32H7_TIM1_PWM
+static int pwm_tim1interrupt(int irq, void *context, FAR void *arg)
+{
+  return pwm_interrupt((FAR struct pwm_lowerhalf_s *)&g_pwm1dev);
+}
+#endif  /* CONFIG_STM32H7_TIM1_PWM */
+
+#ifdef CONFIG_STM32H7_TIM8_PWM
+static int pwm_tim8interrupt(int irq, void *context, FAR void *arg)
+{
+  return pwm_interrupt((FAR struct pwm_lowerhalf_s *)&g_pwm8dev);
+}
+#endif  /* CONFIG_STM32H7_TIM8_PWM */
+
+/****************************************************************************
+ * Name: pwm_pulsecount
+ *
+ * Description:
+ *   Pick an optimal pulse count to program the RCR.
+ *
+ * Input Parameters:
+ *   count - The total count remaining
+ *
+ * Returned Value:
+ *   The recommended pulse count
+ *
+ ****************************************************************************/
+
+static uint8_t pwm_pulsecount(uint32_t count)
+{
+  /* REVISIT: RCR_REP_MAX for GTIM or ATIM ? */
+
+  /* The the remaining pulse count is less than or equal to the maximum, the
+   * just return the count.
+   */
+
+  if (count <= ATIM_RCR_REP_MAX)
+    {
+      return (uint8_t)count;
+    }
+
+  /* Otherwise, we have to be careful.  We do not want a small number of
+   * counts at the end because we might have trouble responding fast enough.
+   * If the remaining count is less than 150% of the maximum, then return
+   * half of the maximum.  In this case the final sequence will be between 64
+   * and 128.
+   */
+
+  else if (count < (3 * ATIM_RCR_REP_MAX / 2))
+    {
+      return (uint8_t)((ATIM_RCR_REP_MAX + 1) >> 1);
+    }
+
+  /* Otherwise, return the maximum.  The final count will be 64 or more */
+
+  else
+    {
+      return (uint8_t)ATIM_RCR_REP_MAX;
+    }
+}
+#endif  /* HAVE_PWM_INTERRUPT */
+
+/****************************************************************************
+ * Name: pwm_set_apb_clock
+ *
+ * Description:
+ *   Enable or disable APB clock for the timer peripheral
+ *
+ * Input Parameters:
+ *   priv - A reference to the PWM block status
+ *   on   - Enable clock if 'on' is 'true' and disable if 'false'
+ *
+ ****************************************************************************/
+
+static int pwm_set_apb_clock(FAR struct stm32_pwmtimer_s *priv, bool on)
+{
+  uint32_t en_bit  = 0;
+  uint32_t regaddr = 0;
+  int      ret     = OK;
+
+  pwminfo("timer %d clock enable: %d\n", priv->timid, on ? 1 : 0);
+
+  /* Determine which timer to configure */
+
+  switch (priv->timid)
+    {
+#ifdef CONFIG_STM32H7_TIM1_PWM
+      case 1:
+        {
+          regaddr = TIMRCCEN_TIM1;
+          en_bit  = TIMEN_TIM1;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM2_PWM
+      case 2:
+        {
+          regaddr = TIMRCCEN_TIM2;
+          en_bit  = TIMEN_TIM2;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM3_PWM
+      case 3:
+        {
+          regaddr = TIMRCCEN_TIM3;
+          en_bit  = TIMEN_TIM3;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM4_PWM
+      case 4:
+        {
+          regaddr = TIMRCCEN_TIM4;
+          en_bit  = TIMEN_TIM4;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM5_PWM
+      case 5:
+        {
+          regaddr = TIMRCCEN_TIM5;
+          en_bit  = TIMEN_TIM5;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM8_PWM
+      case 8:
+        {
+          regaddr = TIMRCCEN_TIM8;
+          en_bit  = TIMEN_TIM8;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM12_PWM
+      case 12:
+        {
+          regaddr = TIMRCCEN_TIM12;
+          en_bit  = TIMEN_TIM12;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM13_PWM
+      case 13:
+        {
+          regaddr = TIMRCCEN_TIM13;
+          en_bit  = TIMEN_TIM13;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM14_PWM
+      case 14:
+        {
+          regaddr = TIMRCCEN_TIM14;
+          en_bit  = TIMEN_TIM14;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM15_PWM
+      case 15:
+        {
+          regaddr = TIMRCCEN_TIM15;
+          en_bit  = TIMEN_TIM15;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM16_PWM
+      case 16:
+        {
+          regaddr = TIMRCCEN_TIM16;
+          en_bit  = TIMEN_TIM16;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM17_PWM
+      case 17:
+        {
+          regaddr = TIMRCCEN_TIM17;
+          en_bit  = TIMEN_TIM17;
+          break;
+        }
+#endif
+
+      default:
+        {
+          pwmerr("ERROR: No such timer configured %d\n", priv->timid);
+          ret = -EINVAL;
+          goto errout;
+        }
+    }
+
+  /* Enable/disable APB 1/2 clock for timer */
+
+  pwminfo("RCC_APBxENR base: %08x  bits: %04x\n", regaddr, en_bit);
+
+  if (on)
+    {
+      modifyreg32(regaddr, 0, en_bit);
+    }
+  else
+    {
+      modifyreg32(regaddr, en_bit, 0);
+    }
+
+errout:
+  return ret;
+}
+
+/****************************************************************************
+ * Name: pwm_setup
+ *
+ * Description:
+ *   This method is called when the driver is opened.  The lower half driver
+ *   should configure and initialize the device so that it is ready for use.
+ *   It should not, however, output pulses until the start method is called.
+ *
+ * Input Parameters:
+ *   dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ * Assumptions:
+ *   APB1 or 2 clocking for the GPIOs has already been configured by the RCC
+ *   logic at power up.
+ *
+ ****************************************************************************/
+
+static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint32_t pincfg = 0;
+  int      ret    = OK;
+  int      i      = 0;
+
+  pwminfo("TIM%u\n", priv->timid);
+
+  /* Enable APB1/2 clocking for timer. */
+
+  ret = pwm_set_apb_clock(priv, true);
+  if (ret < 0)
+    {
+      goto errout;
+    }
+
+  pwm_dumpregs(priv, "Initially");
+
+  /* Configure the PWM output pins, but do not start the timer yet */
+
+  for (i = 0; i < priv->chan_num; i++)
+    {
+      if (priv->channels[i].out1.in_use == 1)
+        {
+          pincfg = priv->channels[i].out1.pincfg;
+          pwminfo("pincfg: %08x\n", pincfg);
+
+          stm32_configgpio(pincfg);
+          pwm_dumpgpio(pincfg, "PWM setup");
+        }
+
+#ifdef HAVE_PWM_COMPLEMENTARY
+      if (priv->channels[i].out2.in_use == 1)
+        {
+          pincfg = priv->channels[i].out2.pincfg;
+          pwminfo("pincfg: %08x\n", pincfg);
+
+          stm32_configgpio(pincfg);
+          pwm_dumpgpio(pincfg, "PWM setup");
+        }
+#endif
+    }
+
+  /* Configure PWM timer with the selected configuration.
+   *
+   * NOTE: We configure PWM here during setup, but leave timer with disabled
+   *       counter, disabled outputs, not configured frequency and duty cycle
+   */
+
+#ifdef CONFIG_PWM_PULSECOUNT
+  ret = pwm_pulsecount_configure(dev);
+#else
+  ret = pwm_configure(dev);
+#endif
+  if (ret < 0)
+    {
+      pwmerr("failed to configure PWM %d\n", priv->timid);
+      ret = ERROR;
+      goto errout;
+    }
+
+errout:
+  return ret;
+}
+
+/****************************************************************************
+ * Name: pwm_shutdown
+ *
+ * Description:
+ *   This method is called when the driver is closed.  The lower half driver
+ *   stop pulsed output, free any resources, disable the timer hardware, and
+ *   put the system into the lowest possible power usage state
+ *
+ * Input Parameters:
+ *   dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  uint32_t pincfg = 0;
+  int      i      = 0;
+  int      ret    = OK;
+
+  pwminfo("TIM%u\n", priv->timid);
+
+  /* Make sure that the output has been stopped */
+
+  pwm_stop(dev);
+
+  /* Disable APB1/2 clocking for timer. */
+
+  ret = pwm_set_apb_clock(priv, false);
+  if (ret < 0)
+    {
+      goto errout;
+    }
+
+  /* Then put the GPIO pins back to the default state */
+
+  for (i = 0; i < priv->chan_num; i++)
+    {
+      pincfg = priv->channels[i].out1.pincfg;
+      if (pincfg != 0)
+        {
+          pwminfo("pincfg: %08x\n", pincfg);
+
+          pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK);
+          pincfg |= PINCFG_DEFAULT;
+
+          stm32_configgpio(pincfg);
+        }
+
+#ifdef HAVE_PWM_COMPLEMENTARY
+      pincfg = priv->channels[i].out2.pincfg;
+      if (pincfg != 0)
+        {
+          pwminfo("pincfg: %08x\n", pincfg);
+
+          pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK);
+          pincfg |= PINCFG_DEFAULT;
+
+          stm32_configgpio(pincfg);
+        }
+#endif
+    }
+
+errout:
+  return ret;
+}
+
+/****************************************************************************
+ * Name: pwm_start
+ *
+ * Description:
+ *   (Re-)initialize the timer resources and start the pulsed output
+ *
+ * Input Parameters:
+ *   dev  - A reference to the lower half PWM driver state structure
+ *   info - A reference to the characteristics of the pulsed output
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PWM_PULSECOUNT
+static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
+                     FAR const struct pwm_info_s *info,
+                     FAR void *handle)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+
+  /* Check if a pulsecount has been selected */
+
+  if (info->count > 0)
+    {
+      /* Only the advanced timers (TIM1,8 can support the pulse counting)
+       * REVISIT: verify if TIMTYPE_COUNTUP16_N works with it
+       */
+
+      if (priv->timtype != TIMTYPE_ADVANCED)
+        {
+          pwmerr("ERROR: TIM%u cannot support pulse count: %u\n",
+                 priv->timid, info->count);
+          return -EPERM;
+        }
+    }
+
+  /* Save the handle */
+
+  priv->handle = handle;
+
+  /* Start the time */
+
+  return pwm_pulsecount_timer(dev, info);
+}
+#else  /* !CONFIG_PWM_PULSECOUNT */
+static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
+                     FAR const struct pwm_info_s *info)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  int ret = OK;
+
+  /* if frequency has not changed we just update duty */
+
+  if (info->frequency == priv->frequency)
+    {
+#ifdef CONFIG_PWM_MULTICHAN
+      int i;
+
+      /* REVISIT: */
+
+      for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++)
+        {
+          ret = pwm_duty_update(dev, info->channels[i].channel,
+                                info->channels[i].duty);
+        }
+#else
+      ret = pwm_duty_update(dev, priv->channels[0].channel, info->duty);
+#endif  /* CONFIG_PWM_MULTICHAN */
+    }
+  else
+    {
+      ret = pwm_timer(dev, info);
+
+      /* Save current frequency */
+
+      if (ret == OK)
+        {
+          priv->frequency = info->frequency;
+        }
+    }
+
+  return ret;
+}
+#endif  /* CONFIG_PWM_PULSECOUNT */
+
+/****************************************************************************
+ * Name: pwm_stop
+ *
+ * Description:
+ *   Stop the pulsed output and reset the timer resources
+ *
+ * Input Parameters:
+ *   dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ * Assumptions:
+ *   This function is called to stop the pulsed output at anytime.  This
+ *   method is also called from the timer interrupt handler when a repetition
+ *   count expires... automatically stopping the timer.
+ *
+ ****************************************************************************/
+
+static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
+{
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+  irqstate_t flags    = 0;
+  uint32_t   resetbit = 0;
+  uint32_t   regaddr  = 0;
+  uint32_t   regval   = 0;
+  int        ret = OK;
+
+  pwminfo("TIM%u\n", priv->timid);
+
+  /* Determine which timer to reset */
+
+  switch (priv->timid)
+    {
+#ifdef CONFIG_STM32H7_TIM1_PWM
+      case 1:
+      {
+        regaddr  = TIMRCCRST_TIM1;
+        resetbit = TIMRST_TIM1;
+        break;
+      }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM2_PWM
+      case 2:
+      {
+        regaddr  = TIMRCCRST_TIM2;
+        resetbit = TIMRST_TIM2;
+        break;
+      }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM3_PWM
+      case 3:
+      {
+        regaddr  = TIMRCCRST_TIM3;
+        resetbit = TIMRST_TIM3;
+        break;
+      }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM4_PWM
+      case 4:
+      {
+        regaddr  = TIMRCCRST_TIM4;
+        resetbit = TIMRST_TIM4;
+        break;
+      }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM5_PWM
+      case 5:
+      {
+        regaddr  = TIMRCCRST_TIM5;
+        resetbit = TIMRST_TIM5;
+        break;
+      }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM8_PWM
+      case 8:
+      {
+        regaddr  = TIMRCCRST_TIM8;
+        resetbit = TIMRST_TIM8;
+        break;
+      }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM12_PWM
+      case 12:
+      {
+        regaddr  = TIMRCCRST_TIM12;
+        resetbit = TIMRST_TIM12;
+        break;
+      }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM13_PWM
+      case 13:
+      {
+        regaddr  = TIMRCCRST_TIM13;
+        resetbit = TIMRST_TIM13;
+        break;
+      }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM14_PWM
+      case 14:
+      {
+        regaddr  = TIMRCCRST_TIM14;
+        resetbit = TIMRST_TIM14;
+        break;
+      }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM15_PWM
+      case 15:
+      {
+        regaddr  = TIMRCCRST_TIM15;
+        resetbit = TIMRST_TIM15;
+        break;
+      }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM16_PWM
+      case 16:
+      {
+        regaddr  = TIMRCCRST_TIM16;
+        resetbit = TIMRST_TIM16;
+        break;
+      }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM17_PWM
+      case 17:
+      {
+        regaddr  = TIMRCCRST_TIM17;
+        resetbit = TIMRST_TIM17;
+        break;
+      }
+#endif
+
+      default:
+      {
+        ret = -EINVAL;
+        goto errout;
+      }
+    }
+
+  /* Disable interrupts momentary to stop any ongoing timer processing and
+   * to prevent any concurrent access to the reset register.
+   */
+
+  flags = enter_critical_section();
+
+#ifndef CONFIG_PWM_PULSECOUNT
+  /* Stopped so frequency is zero */
+
+  priv->frequency = 0;
+#endif
+
+  /* Disable further interrupts and stop the timer */
+
+  pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0);
+  pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0);
+
+  /* Reset the timer - stopping the output and putting the timer back
+   * into a state where pwm_start() can be called.
+   */
+
+  regval  = getreg32(regaddr);
+  regval |= resetbit;
+  putreg32(regval, regaddr);
+
+  regval &= ~resetbit;
+  putreg32(regval, regaddr);
+  leave_critical_section(flags);
+
+  pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
+  pwm_dumpregs(priv, "After stop");
+
+errout:
+  return ret;
+}
+
+/****************************************************************************
+ * Name: pwm_ioctl
+ *
+ * Description:
+ *   Lower-half logic may support platform-specific ioctl commands
+ *
+ * Input Parameters:
+ *   dev - A reference to the lower half PWM driver state structure
+ *   cmd - The ioctl command
+ *   arg - The argument accompanying the ioctl command
+ *
+ * Returned Value:
+ *   Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd,
+                     unsigned long arg)
+{
+#ifdef CONFIG_DEBUG_PWM_INFO
+  FAR struct stm32_pwmtimer_s *priv = (FAR struct stm32_pwmtimer_s *)dev;
+
+  /* There are no platform-specific ioctl commands */
+
+  pwminfo("TIM%u\n", priv->timid);
+#endif
+  return -ENOTTY;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_pwminitialize
+ *
+ * Description:
+ *   Initialize one timer for use with the upper_level PWM driver.
+ *
+ * Input Parameters:
+ *   timer - A number identifying the timer use.  The number of valid timer
+ *     IDs varies with the STM32 MCU and MCU family but is somewhere in
+ *     the range of {1,..,17}.
+ *
+ * Returned Value:
+ *   On success, a pointer to the STM32 lower half PWM driver is returned.
+ *   NULL is returned on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer)
+{
+  FAR struct stm32_pwmtimer_s *lower = NULL;
+
+  pwminfo("TIM%u\n", timer);
+
+  switch (timer)
+    {
+#ifdef CONFIG_STM32H7_TIM1_PWM
+      case 1:
+        {
+          lower = &g_pwm1dev;
+
+          /* Attach but disable the TIM1 update interrupt */
+
+#ifdef CONFIG_PWM_PULSECOUNT
+          irq_attach(lower->irq, pwm_tim1interrupt, NULL);
+          up_disable_irq(lower->irq);
+#endif
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM2_PWM
+      case 2:
+        {
+          lower = &g_pwm2dev;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM3_PWM
+      case 3:
+        {
+          lower = &g_pwm3dev;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM4_PWM
+      case 4:
+        {
+          lower = &g_pwm4dev;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM5_PWM
+      case 5:
+        {
+          lower = &g_pwm5dev;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM8_PWM
+      case 8:
+        {
+          lower = &g_pwm8dev;
+
+          /* Attach but disable the TIM8 update interrupt */
+
+#ifdef CONFIG_PWM_PULSECOUNT
+          irq_attach(lower->irq, pwm_tim8interrupt, NULL);
+          up_disable_irq(lower->irq);
+#endif
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM12_PWM
+      case 12:
+        {
+          lower = &g_pwm12dev;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM13_PWM
+      case 13:
+        {
+          lower = &g_pwm13dev;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM14_PWM
+      case 14:
+        {
+          lower = &g_pwm14dev;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM15_PWM
+      case 15:
+        {
+          lower = &g_pwm15dev;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM16_PWM
+      case 16:
+        {
+          lower = &g_pwm16dev;
+          break;
+        }
+#endif
+
+#ifdef CONFIG_STM32H7_TIM17_PWM
+      case 17:
+        {
+          lower = &g_pwm17dev;
+          break;
+        }
+#endif
+
+      default:
+        {
+          pwmerr("ERROR: No such timer configured %d\n", timer);
+          lower = NULL;
+          goto errout;
+        }
+    }
+
+errout:
+  return (FAR struct pwm_lowerhalf_s *)lower;
+}
+
+#endif /* CONFIG_STM32H7_PWM */
diff --git a/arch/arm/src/stm32h7/stm32_pwm.h b/arch/arm/src/stm32h7/stm32_pwm.h
new file mode 100644
index 00000000000..6d0b0609149
--- /dev/null
+++ b/arch/arm/src/stm32h7/stm32_pwm.h
@@ -0,0 +1,1059 @@
+/************************************************************************************
+ * arch/arm/src/stm32h7/stm32_pwm.h
+ *
+ *   Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *            Paul Alexander Patience 
+ *            Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H7_STM32_PWM_H
+#define __ARCH_ARM_SRC_STM32H7_STM32_PWM_H
+
+/* The STM32 does not have dedicated PWM hardware.  Rather, pulsed output control
+ * is a capabilitiy of the STM32 timers.  The logic in this file implements the
+ * lower half of the standard, NuttX PWM interface using the STM32 timers.  That
+ * interface is described in include/nuttx/drivers/pwm.h.
+ */
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include 
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+/* Configuration ********************************************************************/
+/* Timer devices may be used for different purposes.  One special purpose is
+ * to generate modulated outputs for such things as motor control.  If CONFIG_STM32H7_TIMn
+ * is defined then the CONFIG_STM32H7_TIMn_PWM must also be defined to indicate that
+ * timer "n" is intended to be used for pulsed output signal generation.
+ */
+
+#ifndef CONFIG_STM32H7_TIM1
+#  undef CONFIG_STM32H7_TIM1_PWM
+#endif
+#ifndef CONFIG_STM32H7_TIM2
+#  undef CONFIG_STM32H7_TIM2_PWM
+#endif
+#ifndef CONFIG_STM32H7_TIM3
+#  undef CONFIG_STM32H7_TIM3_PWM
+#endif
+#ifndef CONFIG_STM32H7_TIM4
+#  undef CONFIG_STM32H7_TIM4_PWM
+#endif
+#ifndef CONFIG_STM32H7_TIM5
+#  undef CONFIG_STM32H7_TIM5_PWM
+#endif
+#ifndef CONFIG_STM32H7_TIM8
+#  undef CONFIG_STM32H7_TIM8_PWM
+#endif
+#ifndef CONFIG_STM32H7_TIM12
+#  undef CONFIG_STM32H7_TIM12_PWM
+#endif
+#ifndef CONFIG_STM32H7_TIM13
+#  undef CONFIG_STM32H7_TIM13_PWM
+#endif
+#ifndef CONFIG_STM32H7_TIM14
+#  undef CONFIG_STM32H7_TIM14_PWM
+#endif
+#ifndef CONFIG_STM32H7_TIM15
+#  undef CONFIG_STM32H7_TIM15_PWM
+#endif
+#ifndef CONFIG_STM32H7_TIM16
+#  undef CONFIG_STM32H7_TIM16_PWM
+#endif
+#ifndef CONFIG_STM32H7_TIM17
+#  undef CONFIG_STM32H7_TIM17_PWM
+#endif
+
+/* The basic timers (timer 6 and 7) are not capable of generating output pulses */
+
+#undef CONFIG_STM32H7_TIM6_PWM
+#undef CONFIG_STM32H7_TIM7_PWM
+
+/* Check if PWM support for any channel is enabled. */
+
+#ifdef CONFIG_STM32H7_PWM
+
+#include 
+#include "hardware/stm32_tim.h"
+
+/* PWM driver channels configuration */
+
+#ifdef CONFIG_STM32H7_PWM_MULTICHAN
+
+#ifdef CONFIG_STM32H7_TIM1_CHANNEL1
+#  define PWM_TIM1_CHANNEL1 1
+#else
+#  define PWM_TIM1_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CHANNEL2
+#  define PWM_TIM1_CHANNEL2 1
+#else
+#  define PWM_TIM1_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CHANNEL3
+#  define PWM_TIM1_CHANNEL3 1
+#else
+#  define PWM_TIM1_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CHANNEL4
+#  define PWM_TIM1_CHANNEL4 1
+#else
+#  define PWM_TIM1_CHANNEL4 0
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CHANNEL5
+#  define PWM_TIM1_CHANNEL5 1
+#else
+#  define PWM_TIM1_CHANNEL5 0
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CHANNEL6
+#  define PWM_TIM1_CHANNEL6 1
+#else
+#  define PWM_TIM1_CHANNEL6 0
+#endif
+#define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \
+                            PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \
+                            PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6)
+
+#ifdef CONFIG_STM32H7_TIM2_CHANNEL1
+#  define PWM_TIM2_CHANNEL1 1
+#else
+#  define PWM_TIM2_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32H7_TIM2_CHANNEL2
+#  define PWM_TIM2_CHANNEL2 1
+#else
+#  define PWM_TIM2_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32H7_TIM2_CHANNEL3
+#  define PWM_TIM2_CHANNEL3 1
+#else
+#  define PWM_TIM2_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32H7_TIM2_CHANNEL4
+#  define PWM_TIM2_CHANNEL4 1
+#else
+#  define PWM_TIM2_CHANNEL4 0
+#endif
+#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \
+                            PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4)
+
+#ifdef CONFIG_STM32H7_TIM3_CHANNEL1
+#  define PWM_TIM3_CHANNEL1 1
+#else
+#  define PWM_TIM3_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32H7_TIM3_CHANNEL2
+#  define PWM_TIM3_CHANNEL2 1
+#else
+#  define PWM_TIM3_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32H7_TIM3_CHANNEL3
+#  define PWM_TIM3_CHANNEL3 1
+#else
+#  define PWM_TIM3_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32H7_TIM3_CHANNEL4
+#  define PWM_TIM3_CHANNEL4 1
+#else
+#  define PWM_TIM3_CHANNEL4 0
+#endif
+#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \
+                            PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4)
+
+#ifdef CONFIG_STM32H7_TIM4_CHANNEL1
+#  define PWM_TIM4_CHANNEL1 1
+#else
+#  define PWM_TIM4_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32H7_TIM4_CHANNEL2
+#  define PWM_TIM4_CHANNEL2 1
+#else
+#  define PWM_TIM4_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32H7_TIM4_CHANNEL3
+#  define PWM_TIM4_CHANNEL3 1
+#else
+#  define PWM_TIM4_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32H7_TIM4_CHANNEL4
+#  define PWM_TIM4_CHANNEL4 1
+#else
+#  define PWM_TIM4_CHANNEL4 0
+#endif
+#define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \
+                            PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4)
+
+#ifdef CONFIG_STM32H7_TIM5_CHANNEL1
+#  define PWM_TIM5_CHANNEL1 1
+#else
+#  define PWM_TIM5_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32H7_TIM5_CHANNEL2
+#  define PWM_TIM5_CHANNEL2 1
+#else
+#  define PWM_TIM5_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32H7_TIM5_CHANNEL3
+#  define PWM_TIM5_CHANNEL3 1
+#else
+#  define PWM_TIM5_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32H7_TIM5_CHANNEL4
+#  define PWM_TIM5_CHANNEL4 1
+#else
+#  define PWM_TIM5_CHANNEL4 0
+#endif
+#define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \
+                            PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4)
+
+#ifdef CONFIG_STM32H7_TIM8_CHANNEL1
+#  define PWM_TIM8_CHANNEL1 1
+#else
+#  define PWM_TIM8_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CHANNEL2
+#  define PWM_TIM8_CHANNEL2 1
+#else
+#  define PWM_TIM8_CHANNEL2 0
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CHANNEL3
+#  define PWM_TIM8_CHANNEL3 1
+#else
+#  define PWM_TIM8_CHANNEL3 0
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CHANNEL4
+#  define PWM_TIM8_CHANNEL4 1
+#else
+#  define PWM_TIM8_CHANNEL4 0
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CHANNEL5
+#  define PWM_TIM8_CHANNEL5 1
+#else
+#  define PWM_TIM8_CHANNEL5 0
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CHANNEL6
+#  define PWM_TIM8_CHANNEL6 1
+#else
+#  define PWM_TIM8_CHANNEL6 0
+#endif
+#define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \
+                            PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \
+                            PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6)
+
+#ifdef CONFIG_STM32H7_TIM12_CHANNEL1
+#  define PWM_TIM12_CHANNEL1 1
+#else
+#  define PWM_TIM12_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32H7_TIM12_CHANNEL2
+#  define PWM_TIM12_CHANNEL2 1
+#else
+#  define PWM_TIM12_CHANNEL2 0
+#endif
+#define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2)
+
+#ifdef CONFIG_STM32H7_TIM13_CHANNEL1
+#  define PWM_TIM13_CHANNEL1 1
+#else
+#  define PWM_TIM13_CHANNEL1 0
+#endif
+#define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1)
+
+#ifdef CONFIG_STM32H7_TIM14_CHANNEL1
+#  define PWM_TIM14_CHANNEL1 1
+#else
+#  define PWM_TIM14_CHANNEL1 0
+#endif
+#define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1)
+
+#ifdef CONFIG_STM32H7_TIM15_CHANNEL1
+#  define PWM_TIM15_CHANNEL1 1
+#else
+#  define PWM_TIM15_CHANNEL1 0
+#endif
+#ifdef CONFIG_STM32H7_TIM15_CHANNEL2
+#  define PWM_TIM15_CHANNEL2 1
+#else
+#  define PWM_TIM15_CHANNEL2 0
+#endif
+#define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2)
+
+#ifdef CONFIG_STM32H7_TIM16_CHANNEL1
+#  define PWM_TIM16_CHANNEL1 1
+#else
+#  define PWM_TIM16_CHANNEL1 0
+#endif
+#define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1
+
+#ifdef CONFIG_STM32H7_TIM17_CHANNEL1
+#  define PWM_TIM17_CHANNEL1 1
+#else
+#  define PWM_TIM17_CHANNEL1 0
+#endif
+#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1
+
+#else  /* !CONFIG_PWM_MULTICHAN */
+
+/* For each timer that is enabled for PWM usage, we need the following additional
+ * configuration settings:
+ *
+ * CONFIG_STM32H7_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
+ * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h.  In the case
+ *   where there are multiple pin selections, the correct setting must be provided
+ *   in the arch/board/board.h file.
+ *
+ * NOTE: The STM32 timers are each capable of generating different signals on
+ * each of the four channels with different duty cycles.  That capability is
+ * not supported by this driver:  Only one output channel per timer.
+ */
+
+#ifdef CONFIG_STM32H7_TIM1_PWM
+#  if !defined(CONFIG_STM32H7_TIM1_CHANNEL)
+#    error "CONFIG_STM32H7_TIM1_CHANNEL must be provided"
+#  elif CONFIG_STM32H7_TIM1_CHANNEL == 1
+#    define CONFIG_STM32H7_TIM1_CHANNEL1 1
+#    define CONFIG_STM32H7_TIM1_CH1MODE  CONFIG_STM32H7_TIM1_CHMODE
+#  elif CONFIG_STM32H7_TIM1_CHANNEL == 2
+#    define CONFIG_STM32H7_TIM1_CHANNEL2 1
+#    define CONFIG_STM32H7_TIM1_CH2MODE  CONFIG_STM32H7_TIM1_CHMODE
+#  elif CONFIG_STM32H7_TIM1_CHANNEL == 3
+#    define CONFIG_STM32H7_TIM1_CHANNEL3 1
+#    define CONFIG_STM32H7_TIM1_CH3MODE  CONFIG_STM32H7_TIM1_CHMODE
+#  elif CONFIG_STM32H7_TIM1_CHANNEL == 4
+#    define CONFIG_STM32H7_TIM1_CHANNEL4 1
+#    define CONFIG_STM32H7_TIM1_CH4MODE  CONFIG_STM32H7_TIM1_CHMODE
+#  else
+#    error "Unsupported value of CONFIG_STM32H7_TIM1_CHANNEL"
+#  endif
+#  define PWM_TIM1_NCHANNELS 1
+#endif
+
+#ifdef CONFIG_STM32H7_TIM2_PWM
+#  if !defined(CONFIG_STM32H7_TIM2_CHANNEL)
+#    error "CONFIG_STM32H7_TIM2_CHANNEL must be provided"
+#  elif CONFIG_STM32H7_TIM2_CHANNEL == 1
+#    define CONFIG_STM32H7_TIM2_CHANNEL1 1
+#    define CONFIG_STM32H7_TIM2_CH1MODE  CONFIG_STM32H7_TIM2_CHMODE
+#  elif CONFIG_STM32H7_TIM2_CHANNEL == 2
+#    define CONFIG_STM32H7_TIM2_CHANNEL2 1
+#    define CONFIG_STM32H7_TIM2_CH2MODE  CONFIG_STM32H7_TIM2_CHMODE
+#  elif CONFIG_STM32H7_TIM2_CHANNEL == 3
+#    define CONFIG_STM32H7_TIM2_CHANNEL3 1
+#    define CONFIG_STM32H7_TIM2_CH3MODE  CONFIG_STM32H7_TIM2_CHMODE
+#  elif CONFIG_STM32H7_TIM2_CHANNEL == 4
+#    define CONFIG_STM32H7_TIM2_CHANNEL4 1
+#    define CONFIG_STM32H7_TIM2_CH4MODE  CONFIG_STM32H7_TIM2_CHMODE
+#  else
+#    error "Unsupported value of CONFIG_STM32H7_TIM2_CHANNEL"
+#  endif
+#  define PWM_TIM2_NCHANNELS 1
+#endif
+
+#ifdef CONFIG_STM32H7_TIM3_PWM
+#  if !defined(CONFIG_STM32H7_TIM3_CHANNEL)
+#    error "CONFIG_STM32H7_TIM3_CHANNEL must be provided"
+#  elif CONFIG_STM32H7_TIM3_CHANNEL == 1
+#    define CONFIG_STM32H7_TIM3_CHANNEL1 1
+#    define CONFIG_STM32H7_TIM3_CH1MODE  CONFIG_STM32H7_TIM3_CHMODE
+#  elif CONFIG_STM32H7_TIM3_CHANNEL == 2
+#    define CONFIG_STM32H7_TIM3_CHANNEL2 1
+#    define CONFIG_STM32H7_TIM3_CH2MODE  CONFIG_STM32H7_TIM3_CHMODE
+#  elif CONFIG_STM32H7_TIM3_CHANNEL == 3
+#    define CONFIG_STM32H7_TIM3_CHANNEL3 1
+#    define CONFIG_STM32H7_TIM3_CH3MODE  CONFIG_STM32H7_TIM3_CHMODE
+#  elif CONFIG_STM32H7_TIM3_CHANNEL == 4
+#    define CONFIG_STM32H7_TIM3_CHANNEL4 1
+#    define CONFIG_STM32H7_TIM3_CH4MODE  CONFIG_STM32H7_TIM3_CHMODE
+#  else
+#    error "Unsupported value of CONFIG_STM32H7_TIM3_CHANNEL"
+#  endif
+#  define PWM_TIM3_NCHANNELS 1
+#endif
+
+#ifdef CONFIG_STM32H7_TIM4_PWM
+#  if !defined(CONFIG_STM32H7_TIM4_CHANNEL)
+#    error "CONFIG_STM32H7_TIM4_CHANNEL must be provided"
+#  elif CONFIG_STM32H7_TIM4_CHANNEL == 1
+#    define CONFIG_STM32H7_TIM4_CHANNEL1 1
+#    define CONFIG_STM32H7_TIM4_CH1MODE  CONFIG_STM32H7_TIM4_CHMODE
+#  elif CONFIG_STM32H7_TIM4_CHANNEL == 2
+#    define CONFIG_STM32H7_TIM4_CHANNEL2 1
+#    define CONFIG_STM32H7_TIM4_CH2MODE  CONFIG_STM32H7_TIM4_CHMODE
+#  elif CONFIG_STM32H7_TIM4_CHANNEL == 3
+#    define CONFIG_STM32H7_TIM4_CHANNEL3 1
+#    define CONFIG_STM32H7_TIM4_CH3MODE  CONFIG_STM32H7_TIM4_CHMODE
+#  elif CONFIG_STM32H7_TIM4_CHANNEL == 4
+#    define CONFIG_STM32H7_TIM4_CHANNEL4 1
+#    define CONFIG_STM32H7_TIM4_CH4MODE  CONFIG_STM32H7_TIM4_CHMODE
+#  else
+#    error "Unsupported value of CONFIG_STM32H7_TIM4_CHANNEL"
+#  endif
+#  define PWM_TIM4_NCHANNELS 1
+#endif
+
+#ifdef CONFIG_STM32H7_TIM5_PWM
+#  if !defined(CONFIG_STM32H7_TIM5_CHANNEL)
+#    error "CONFIG_STM32H7_TIM5_CHANNEL must be provided"
+#  elif CONFIG_STM32H7_TIM5_CHANNEL == 1
+#    define CONFIG_STM32H7_TIM5_CHANNEL1 1
+#    define CONFIG_STM32H7_TIM5_CH1MODE  CONFIG_STM32H7_TIM5_CHMODE
+#  elif CONFIG_STM32H7_TIM5_CHANNEL == 2
+#    define CONFIG_STM32H7_TIM5_CHANNEL2 1
+#    define CONFIG_STM32H7_TIM5_CH2MODE  CONFIG_STM32H7_TIM5_CHMODE
+#  elif CONFIG_STM32H7_TIM5_CHANNEL == 3
+#    define CONFIG_STM32H7_TIM5_CHANNEL3 1
+#    define CONFIG_STM32H7_TIM5_CH3MODE  CONFIG_STM32H7_TIM5_CHMODE
+#  elif CONFIG_STM32H7_TIM5_CHANNEL == 4
+#    define CONFIG_STM32H7_TIM5_CHANNEL4 1
+#    define CONFIG_STM32H7_TIM5_CH4MODE  CONFIG_STM32H7_TIM5_CHMODE
+#  else
+#    error "Unsupported value of CONFIG_STM32H7_TIM5_CHANNEL"
+#  endif
+#  define PWM_TIM5_NCHANNELS 1
+#endif
+
+#ifdef CONFIG_STM32H7_TIM8_PWM
+#  if !defined(CONFIG_STM32H7_TIM8_CHANNEL)
+#    error "CONFIG_STM32H7_TIM8_CHANNEL must be provided"
+#  elif CONFIG_STM32H7_TIM8_CHANNEL == 1
+#    define CONFIG_STM32H7_TIM8_CHANNEL1 1
+#    define CONFIG_STM32H7_TIM8_CH1MODE  CONFIG_STM32H7_TIM8_CHMODE
+#  elif CONFIG_STM32H7_TIM8_CHANNEL == 2
+#    define CONFIG_STM32H7_TIM8_CHANNEL2 1
+#    define CONFIG_STM32H7_TIM8_CH2MODE  CONFIG_STM32H7_TIM8_CHMODE
+#  elif CONFIG_STM32H7_TIM8_CHANNEL == 3
+#    define CONFIG_STM32H7_TIM8_CHANNEL3 1
+#    define CONFIG_STM32H7_TIM8_CH3MODE  CONFIG_STM32H7_TIM8_CHMODE
+#  elif CONFIG_STM32H7_TIM8_CHANNEL == 4
+#    define CONFIG_STM32H7_TIM8_CHANNEL4 1
+#    define CONFIG_STM32H7_TIM8_CH4MODE  CONFIG_STM32H7_TIM8_CHMODE
+#  else
+#    error "Unsupported value of CONFIG_STM32H7_TIM8_CHANNEL"
+#  endif
+#  define PWM_TIM8_NCHANNELS 1
+#endif
+
+#ifdef CONFIG_STM32H7_TIM12_PWM
+#  if !defined(CONFIG_STM32H7_TIM12_CHANNEL)
+#    error "CONFIG_STM32H7_TIM12_CHANNEL must be provided"
+#  elif CONFIG_STM32H7_TIM12_CHANNEL == 1
+#    define CONFIG_STM32H7_TIM12_CHANNEL1 1
+#    define CONFIG_STM32H7_TIM12_CH1MODE  CONFIG_STM32H7_TIM12_CHMODE
+#  elif CONFIG_STM32H7_TIM12_CHANNEL == 2
+#    define CONFIG_STM32H7_TIM12_CHANNEL2 1
+#    define CONFIG_STM32H7_TIM12_CH2MODE  CONFIG_STM32H7_TIM12_CHMODE
+#  else
+#    error "Unsupported value of CONFIG_STM32H7_TIM12_CHANNEL"
+#  endif
+#  define PWM_TIM12_NCHANNELS 1
+#endif
+
+#ifdef CONFIG_STM32H7_TIM13_PWM
+#  if !defined(CONFIG_STM32H7_TIM13_CHANNEL)
+#    error "CONFIG_STM32H7_TIM13_CHANNEL must be provided"
+#  elif CONFIG_STM32H7_TIM13_CHANNEL == 1
+#    define CONFIG_STM32H7_TIM13_CHANNEL1 1
+#    define CONFIG_STM32H7_TIM13_CH1MODE  CONFIG_STM32H7_TIM13_CHMODE
+#  else
+#    error "Unsupported value of CONFIG_STM32H7_TIM13_CHANNEL"
+#  endif
+#  define PWM_TIM13_NCHANNELS 1
+#endif
+
+#ifdef CONFIG_STM32H7_TIM14_PWM
+#  if !defined(CONFIG_STM32H7_TIM14_CHANNEL)
+#    error "CONFIG_STM32H7_TIM14_CHANNEL must be provided"
+#  elif CONFIG_STM32H7_TIM14_CHANNEL == 1
+#    define CONFIG_STM32H7_TIM14_CHANNEL1 1
+#    define CONFIG_STM32H7_TIM14_CH1MODE  CONFIG_STM32H7_TIM14_CHMODE
+#  else
+#    error "Unsupported value of CONFIG_STM32H7_TIM14_CHANNEL"
+#  endif
+#  define PWM_TIM14_NCHANNELS 1
+#endif
+
+#ifdef CONFIG_STM32H7_TIM15_PWM
+#  if !defined(CONFIG_STM32H7_TIM15_CHANNEL)
+#    error "CONFIG_STM32H7_TIM15_CHANNEL must be provided"
+#  elif CONFIG_STM32H7_TIM15_CHANNEL == 1
+#    define CONFIG_STM32H7_TIM15_CHANNEL1 1
+#    define CONFIG_STM32H7_TIM15_CH1MODE  CONFIG_STM32H7_TIM15_CHMODE
+#  elif CONFIG_STM32H7_TIM15_CHANNEL == 2
+#    define CONFIG_STM32H7_TIM15_CHANNEL2 1
+#    define CONFIG_STM32H7_TIM15_CH2MODE  CONFIG_STM32H7_TIM15_CHMODE
+#  else
+#    error "Unsupported value of CONFIG_STM32H7_TIM15_CHANNEL"
+#  endif
+#  define PWM_TIM15_NCHANNELS 1
+#endif
+
+#ifdef CONFIG_STM32H7_TIM16_PWM
+#  if !defined(CONFIG_STM32H7_TIM16_CHANNEL)
+#    error "CONFIG_STM32H7_TIM16_CHANNEL must be provided"
+#  elif CONFIG_STM32H7_TIM16_CHANNEL == 1
+#    define CONFIG_STM32H7_TIM16_CHANNEL1 1
+#    define CONFIG_STM32H7_TIM16_CH1MODE  CONFIG_STM32H7_TIM16_CHMODE
+#  else
+#    error "Unsupported value of CONFIG_STM32H7_TIM16_CHANNEL"
+#  endif
+#  define PWM_TIM16_NCHANNELS 1
+#endif
+
+#ifdef CONFIG_STM32H7_TIM17_PWM
+#  if !defined(CONFIG_STM32H7_TIM17_CHANNEL)
+#    error "CONFIG_STM32H7_TIM17_CHANNEL must be provided"
+#  elif CONFIG_STM32H7_TIM17_CHANNEL == 1
+#    define CONFIG_STM32H7_TIM17_CHANNEL1 1
+#    define CONFIG_STM32H7_TIM17_CH1MODE  CONFIG_STM32H7_TIM17_CHMODE
+#  else
+#    error "Unsupported value of CONFIG_STM32H7_TIM17_CHANNEL"
+#  endif
+#  define PWM_TIM17_NCHANNELS 1
+#endif
+
+#endif /* CONFIG_STM32H7_PWM_MULTICHAN */
+
+#ifdef CONFIG_STM32H7_TIM1_CH1OUT
+#  define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
+#else
+#  define PWM_TIM1_CH1CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CH1NOUT
+#  define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT
+#else
+#  define PWM_TIM1_CH1NCFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CH2OUT
+#  define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
+#else
+#  define PWM_TIM1_CH2CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CH2NOUT
+#  define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT
+#else
+#  define PWM_TIM1_CH2NCFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CH3OUT
+#  define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
+#else
+#  define PWM_TIM1_CH3CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CH3NOUT
+#  define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT
+#else
+#  define PWM_TIM1_CH3NCFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM1_CH4OUT
+#  define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT
+#else
+#  define PWM_TIM1_CH4CFG 0
+#endif
+
+#ifdef CONFIG_STM32H7_TIM2_CH1OUT
+#  define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT
+#else
+#  define PWM_TIM2_CH1CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM2_CH2OUT
+#  define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT
+#else
+#  define PWM_TIM2_CH2CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM2_CH3OUT
+#  define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT
+#else
+#  define PWM_TIM2_CH3CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM2_CH4OUT
+#  define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT
+#else
+#  define PWM_TIM2_CH4CFG 0
+#endif
+
+#ifdef CONFIG_STM32H7_TIM3_CH1OUT
+#  define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT
+#else
+#  define PWM_TIM3_CH1CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM3_CH2OUT
+#  define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT
+#else
+#  define PWM_TIM3_CH2CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM3_CH3OUT
+#  define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT
+#else
+#  define PWM_TIM3_CH3CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM3_CH4OUT
+#  define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT
+#else
+#  define PWM_TIM3_CH4CFG 0
+#endif
+
+#ifdef CONFIG_STM32H7_TIM4_CH1OUT
+#  define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT
+#else
+#  define PWM_TIM4_CH1CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM4_CH2OUT
+#  define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT
+#else
+#  define PWM_TIM4_CH2CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM4_CH3OUT
+#  define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT
+#else
+#  define PWM_TIM4_CH3CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM4_CH4OUT
+#  define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT
+#else
+#  define PWM_TIM4_CH4CFG 0
+#endif
+
+#ifdef CONFIG_STM32H7_TIM5_CH1OUT
+#  define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT
+#else
+#  define PWM_TIM5_CH1CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM5_CH2OUT
+#  define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT
+#else
+#  define PWM_TIM5_CH2CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM5_CH3OUT
+#  define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT
+#else
+#  define PWM_TIM5_CH3CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM5_CH4OUT
+#  define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT
+#else
+#  define PWM_TIM5_CH4CFG 0
+#endif
+
+#ifdef CONFIG_STM32H7_TIM8_CH1OUT
+#  define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT
+#else
+#  define PWM_TIM8_CH1CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CH1NOUT
+#  define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT
+#else
+#  define PWM_TIM8_CH1NCFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CH2OUT
+#  define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT
+#else
+#  define PWM_TIM8_CH2CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CH2NOUT
+#  define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT
+#else
+#  define PWM_TIM8_CH2NCFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CH3OUT
+#  define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT
+#else
+#  define PWM_TIM8_CH3CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CH3NOUT
+#  define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT
+#else
+#  define PWM_TIM8_CH3NCFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM8_CH4OUT
+#  define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT
+#else
+#  define PWM_TIM8_CH4CFG 0
+#endif
+
+#ifdef CONFIG_STM32H7_TIM12_CH1OUT
+#  define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT
+#else
+#  define PWM_TIM12_CH1CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM12_CH2OUT
+#  define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT
+#else
+#  define PWM_TIM12_CH2CFG 0
+#endif
+
+#ifdef CONFIG_STM32H7_TIM13_CH1OUT
+#  define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT
+#else
+#  define PWM_TIM13_CH1CFG 0
+#endif
+
+#ifdef CONFIG_STM32H7_TIM14_CH1OUT
+#  define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT
+#else
+#  define PWM_TIM14_CH1CFG 0
+#endif
+
+#ifdef CONFIG_STM32H7_TIM15_CH1OUT
+#  define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT
+#else
+#  define PWM_TIM15_CH1CFG 0
+#endif
+
+#ifdef CONFIG_STM32H7_TIM15_CH1NOUT
+#  define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT
+#else
+#  define PWM_TIM15_CH1NCFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM15_CH2OUT
+#  define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT
+#else
+#  define PWM_TIM15_CH2CFG 0
+#endif
+
+#ifdef CONFIG_STM32H7_TIM16_CH1OUT
+#  define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT
+#else
+#  define PWM_TIM16_CH1CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM16_CH1NOUT
+#  define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT
+#else
+#  define PWM_TIM16_CH1NCFG 0
+#endif
+
+#ifdef CONFIG_STM32H7_TIM17_CH1OUT
+#  define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT
+#else
+#  define PWM_TIM17_CH1CFG 0
+#endif
+#ifdef CONFIG_STM32H7_TIM17_CH1NOUT
+#  define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT
+#else
+#  define PWM_TIM17_CH1NCFG 0
+#endif
+
+/* Complementary outputs support */
+
+#if defined(CONFIG_STM32H7_TIM1_CH1NOUT) || defined(CONFIG_STM32H7_TIM1_CH2NOUT) || \
+    defined(CONFIG_STM32H7_TIM1_CH3NOUT)
+#  define HAVE_TIM1_COMPLEMENTARY
+#endif
+#if defined(CONFIG_STM32H7_TIM8_CH1NOUT) || defined(CONFIG_STM32H7_TIM8_CH2NOUT) || \
+    defined(CONFIG_STM32H7_TIM8_CH3NOUT)
+#  define HAVE_TIM8_COMPLEMENTARY
+#endif
+#if defined(CONFIG_STM32H7_TIM15_CH1NOUT)
+#  define HAVE_TIM15_COMPLEMENTARY
+#endif
+#if defined(CONFIG_STM32H7_TIM16_CH1NOUT)
+#  define HAVE_TIM16_COMPLEMENTARY
+#endif
+#if defined(CONFIG_STM32H7_TIM17_CH1NOUT)
+#  define HAVE_TIM17_COMPLEMENTARY
+#endif
+#if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) ||   \
+    defined(HAVE_TIM15_COMPLEMENTARY) || defined(HAVE_TIM16_COMPLEMENTARY) || \
+    defined(HAVE_TIM17_COMPLEMENTARY)
+#  define HAVE_PWM_COMPLEMENTARY
+#endif
+
+/* Low-level ops helpers ************************************************************/
+
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+
+/* NOTE: low-level ops accept pwm_lowerhalf_s as first argument, but llops access
+ *       can be found in stm32_pwm_dev_s
+ */
+
+#define PWM_SETUP(dev)                                                             \
+        (dev)->ops->setup((FAR struct pwm_lowerhalf_s *)dev)
+#define PWM_SHUTDOWN(dev)                                                          \
+        (dev)->ops->shutdown((FAR struct pwm_lowerhalf_s *)dev)
+#define PWM_CCR_UPDATE(dev, index, ccr)                                            \
+        (dev)->llops->ccr_update((FAR struct pwm_lowerhalf_s *)dev, index, ccr)
+#define PWM_MODE_UPDATE(dev, index, mode)                                          \
+        (dev)->llops->mode_update((FAR struct pwm_lowerhalf_s *)dev, index, mode)
+#define PWM_CCR_GET(dev, index)                                                    \
+        (dev)->llops->ccr_get((FAR struct pwm_lowerhalf_s *)dev, index)
+#define PWM_ARR_UPDATE(dev, arr)                                                   \
+        (dev)->llops->arr_update((FAR struct pwm_lowerhalf_s *)dev, arr)
+#define PWM_ARR_GET(dev)                                                           \
+        (dev)->llops->arr_get((FAR struct pwm_lowerhalf_s *)dev)
+#define PWM_OUTPUTS_ENABLE(dev, out, state)                                        \
+        (dev)->llops->outputs_enable((FAR struct pwm_lowerhalf_s *)dev, out, state)
+#define PWM_SOFT_UPDATE(dev)                                                       \
+        (dev)->llops->soft_update((FAR struct pwm_lowerhalf_s *)dev)
+#define PWM_CONFIGURE(dev)                                                         \
+        (dev)->llops->configure((FAR struct pwm_lowerhalf_s *)dev)
+#define PWM_SOFT_BREAK(dev, state)                                                 \
+        (dev)->llops->soft_break((FAR struct pwm_lowerhalf_s *)dev, state)
+#define PWM_FREQ_UPDATE(dev, freq)                                                 \
+        (dev)->llops->freq_update((FAR struct pwm_lowerhalf_s *)dev, freq)
+#define PWM_TIM_ENABLE(dev, state)                                                 \
+        (dev)->llops->tim_enable((FAR struct pwm_lowerhalf_s *)dev, state)
+#ifdef CONFIG_DEBUG_PWM_INFO
+#  define PWM_DUMP_REGS(dev)                                                       \
+        (dev)->llops->dump_regs((FAR struct pwm_lowerhalf_s *)dev)
+#else
+#  define PWM_DUMP_REGS(dev)
+#endif
+#define PWM_DT_UPDATE(dev, dt)                                                     \
+        (dev)->llops->dt_update((FAR struct pwm_lowerhalf_s *)dev, dt)
+
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/* Timer mode */
+
+enum stm32_pwm_tim_mode_e
+{
+  STM32_TIMMODE_COUNTUP   = 0,
+  STM32_TIMMODE_COUNTDOWN = 1,
+  STM32_TIMMODE_CENTER1   = 2,
+  STM32_TIMMODE_CENTER2   = 3,
+  STM32_TIMMODE_CENTER3   = 4,
+};
+
+/* Timer output polarity */
+
+enum stm32_pwm_pol_e
+{
+  STM32_POL_POS  = 0,
+  STM32_POL_NEG  = 1,
+};
+
+/* Timer output IDLE state */
+
+enum stm32_pwm_idle_e
+{
+  STM32_IDLE_INACTIVE = 0,
+  STM32_IDLE_ACTIVE   = 1
+};
+
+/* PWM channel mode */
+
+enum stm32_pwm_chanmode_e
+{
+  STM32_CHANMODE_FRZN        = 0,  /* CCRx matches has no effects on outputs */
+  STM32_CHANMODE_CHACT       = 1,  /* OCxREF active on match */
+  STM32_CHANMODE_CHINACT     = 2,  /* OCxREF inactive on match */
+  STM32_CHANMODE_OCREFTOG    = 3,  /* OCxREF toggles when TIMy_CNT=TIMyCCRx */
+  STM32_CHANMODE_OCREFLO     = 4,  /* OCxREF is forced low */
+  STM32_CHANMODE_OCREFHI     = 5,  /* OCxREF is forced high */
+  STM32_CHANMODE_PWM1        = 6,  /* PWM mode 1 */
+  STM32_CHANMODE_PWM2        = 7,  /* PWM mode 2 */
+#ifdef HAVE_IP_TIMERS_V2
+  STM32_CHANMODE_COMBINED1   = 8,  /* Combined PWM mode 1 */
+  STM32_CHANMODE_COMBINED2   = 9,  /* Combined PWM mode 2 */
+  STM32_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */
+  STM32_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */
+#endif
+};
+
+/* PWM timer channel */
+
+enum stm32_pwm_chan_e
+{
+  STM32_PWM_CHAN1  = 1,
+  STM32_PWM_CHAN2  = 2,
+  STM32_PWM_CHAN3  = 3,
+  STM32_PWM_CHAN4  = 4,
+#ifdef HAVE_IP_TIMERS_V2
+  STM32_PWM_CHAN5  = 5,
+  STM32_PWM_CHAN6  = 6,
+#endif
+};
+
+/* PWM timer channel output */
+
+enum stm32_pwm_output_e
+{
+  STM32_PWM_OUT1  = (1 << 0),
+  STM32_PWM_OUT1N = (1 << 1),
+  STM32_PWM_OUT2  = (1 << 2),
+  STM32_PWM_OUT2N = (1 << 3),
+  STM32_PWM_OUT3  = (1 << 4),
+  STM32_PWM_OUT3N = (1 << 5),
+  STM32_PWM_OUT4  = (1 << 6),
+  /* 1 << 7 reserved - no complementary output for CH4 */
+#ifdef HAVE_IP_TIMERS_V2
+  /* Only available inside micro */
+
+  STM32_PWM_OUT5  = (1 << 8),
+  /* 1 << 9 reserved - no complementary output for CH5 */
+  STM32_PWM_OUT6  = (1 << 10),
+  /* 1 << 11 reserved - no complementary output for CH6 */
+#endif
+};
+
+#ifdef CONFIG_STM32H7_PWM_LL_OPS
+
+/* This structure provides the publicly visable representation of the
+ * "lower-half" PWM driver structure.
+ */
+
+struct stm32_pwm_dev_s
+{
+  /* The first field of this state structure must be a pointer to the PWM
+   * callback structure to be consistent with upper-half PWM driver.
+   */
+
+  FAR const struct pwm_ops_s *ops;
+
+  /* Publicly visible portion of the "lower-half" PWM driver structure */
+
+  FAR const struct stm32_pwm_ops_s *llops;
+
+  /* Require cast-compatibility with private "lower-half" PWM strucutre */
+};
+
+/* Low-level operations for PWM */
+
+struct pwm_lowerhalf_s;
+struct stm32_pwm_ops_s
+{
+  /* Update CCR register */
+
+  int (*ccr_update)(FAR struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t ccr);
+
+  /* Update PWM mode */
+
+  int (*mode_update)(FAR struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t mode);
+
+  /* Get CCR register */
+
+  uint32_t (*ccr_get)(FAR struct pwm_lowerhalf_s *dev, uint8_t index);
+
+  /* Update ARR register */
+
+  int (*arr_update)(FAR struct pwm_lowerhalf_s *dev, uint32_t arr);
+
+  /* Get ARR register */
+
+  uint32_t (*arr_get)(FAR struct pwm_lowerhalf_s *dev);
+
+  /* Enable outputs */
+
+  int (*outputs_enable)(FAR struct pwm_lowerhalf_s *dev, uint16_t outputs, bool state);
+
+  /* Software update */
+
+  int (*soft_update)(FAR struct pwm_lowerhalf_s *dev);
+
+  /* PWM configure */
+
+  int (*configure)(FAR struct pwm_lowerhalf_s *dev);
+
+  /* Software break */
+
+  int (*soft_break)(FAR struct pwm_lowerhalf_s *dev, bool state);
+
+  /* Update frequency */
+
+  int (*freq_update)(FAR struct pwm_lowerhalf_s *dev, uint32_t frequency);
+
+  /* Enable timer counter */
+
+  int (*tim_enable)(FAR struct pwm_lowerhalf_s *dev, bool state);
+
+#ifdef CONFIG_DEBUG_PWM_INFO
+  /* Dump timer registers */
+
+  int (*dump_regs)(FAR struct pwm_lowerhalf_s *dev);
+#endif
+
+#ifdef HAVE_PWM_COMPLEMENTARY
+  /* Deadtime update */
+
+  int (*dt_update)(FAR struct pwm_lowerhalf_s *dev, uint8_t dt);
+#endif
+};
+
+#endif  /* CONFIG_STM32H7_PWM_LL_OPS */
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_pwminitialize
+ *
+ * Description:
+ *   Initialize one timer for use with the upper_level PWM driver.
+ *
+ * Input Parameters:
+ *   timer - A number identifying the timer use.  The number of valid timer
+ *     IDs varies with the STM32 MCU and MCU family but is somewhere in
+ *     the range of {1,..,17}.
+ *
+ * Returned Value:
+ *   On success, a pointer to the STM32 lower half PWM driver is returned.
+ *   NULL is returned on any failure.
+ *
+ ************************************************************************************/
+
+FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_STM32H7_PWM */
+#endif /* __ARCH_ARM_SRC_STM32H7_STM32_PWM_H */
diff --git a/arch/arm/src/stm32h7/stm32_pwr.h b/arch/arm/src/stm32h7/stm32_pwr.h
index f6f1b31e21a..9b024297dac 100644
--- a/arch/arm/src/stm32h7/stm32_pwr.h
+++ b/arch/arm/src/stm32h7/stm32_pwr.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_pwr.h"
+#include "hardware/stm32_pwr.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32h7/stm32_rcc.c b/arch/arm/src/stm32h7/stm32_rcc.c
index b82f9134fdf..e8c09894965 100644
--- a/arch/arm/src/stm32h7/stm32_rcc.c
+++ b/arch/arm/src/stm32h7/stm32_rcc.c
@@ -50,7 +50,7 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/stm32_flash.h"
+#include "hardware/stm32_flash.h"
 #include "stm32_rcc.h"
 #include "stm32_pwr.h"
 
diff --git a/arch/arm/src/stm32h7/stm32_rcc.h b/arch/arm/src/stm32h7/stm32_rcc.h
index 9a51833405f..afb36bc875e 100644
--- a/arch/arm/src/stm32h7/stm32_rcc.h
+++ b/arch/arm/src/stm32h7/stm32_rcc.h
@@ -44,7 +44,7 @@
 
 #include "up_arch.h"
 
-#include "chip/stm32_rcc.h"
+#include "hardware/stm32_rcc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c
new file mode 100644
index 00000000000..7d711a8fbf8
--- /dev/null
+++ b/arch/arm/src/stm32h7/stm32_sdmmc.c
@@ -0,0 +1,2995 @@
+/****************************************************************************
+ * arch/arm/src/stm32f7/stm32_sdmmc.c
+ *
+ *   Copyright (C) 2009, 2011-2017, 2019 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *            David Sidrane 
+ *            Jukka Laitinen 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+#include "chip.h"
+#include "up_arch.h"
+
+#include "stm32_dma.h"
+#include "stm32_gpio.h"
+#include "stm32_rcc.h"
+#include "stm32_sdmmc.h"
+
+#if defined(CONFIG_STM32H7_SDMMC1) || defined(CONFIG_STM32H7_SDMMC2)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* Required system configuration options:
+ *
+ *   CONFIG_ARCH_DMA - Enable architecture-specific DMA subsystem
+ *     initialization.  Required if CONFIG_SDMMC[1|2]_DMA is enabled.
+ *   CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support.
+ *
+ * Driver-specific configuration options:
+ *
+ *   CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking
+ *     APIs to manage concurrent accesses on the SDMMC bus.  This is not
+ *     needed for the simple case of a single SD card, for example.
+ *   CONFIG_STM32H7_SDMMC_IDMA - Enable SDMMC IDMA.
+ *   CONFIG_STM32H7_SDMMC_MDMA - Enable SDMMC MDMA.
+ *     DMA support for SDMMC. These are alternative to each other. If both are
+ *     disabled, the SDMMC will work in interrupt mode
+ *   CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver
+ *     operate with only a single data line (the default is to use all
+ *     4 SD data lines).
+ *   CONFIG_SDMMC_PRI - SDMMC interrupt priority.  This setting is not very
+ *     important since interrupt nesting is not currently supported.
+ *   CONFIG_CONFIG_STM32H7_SDMMC_XFRDEBUG - Enables some very low-level debug
+ *     output This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO
+ */
+
+#ifndef CONFIG_STM32H7_SDMMC_IDMA
+#  error "Currently only IDMA support implemented"
+#endif
+
+#if !defined(CONFIG_STM32H7_SDMMC_IDMA) && !defined (CONFIG_STM32H7_SDMMC_MDMA)
+#  warning "Large Non-DMA transfer may result in RX overrun failures"
+#else
+#  ifndef CONFIG_STM32H7_SDMMC_DMA
+#    define CONFIG_STM32H7_SDMMC_DMA
+#  endif
+#endif
+
+#ifndef CONFIG_SCHED_WORKQUEUE
+#  error "Callback support requires CONFIG_SCHED_WORKQUEUE"
+#endif
+
+#ifdef CONFIG_STM32H7_SDMMC1
+#  if defined(CONFIG_ARCH_IRQPRIO) && !defined(CONFIG_SDMMC1_PRI)
+#    define CONFIG_SDMMC1_PRI        NVIC_SYSH_PRIORITY_DEFAULT
+#  endif
+#endif
+
+#ifdef CONFIG_STM32H7_SDMMC2
+#  if defined(CONFIG_ARCH_IRQPRIO) && !defined(CONFIG_SDMMC2_PRI)
+#    define CONFIG_SDMMC2_PRI        NVIC_SYSH_PRIORITY_DEFAULT
+#  endif
+#endif
+
+#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES)
+#  undef CONFIG_CONFIG_STM32H7_SDMMC_XFRDEBUG
+#endif
+
+/* Friendly CLKCR bit re-definitions ****************************************/
+
+#define STM32_CLKCR_RISINGEDGE    (0)
+#define STM32_CLKCR_FALLINGEDGE   STM32_SDMMC_CLKCR_NEGEDGE
+
+/* Use the default of the rising edge but allow a configuration,
+ * that does not have the errata, to override the edge the SDIO
+ * command and data is changed on.
+ */
+
+#if !defined(STM32_SDMMC_CLKCR_EDGE)
+#  define STM32_SDMMC_CLKCR_EDGE STM32_CLKCR_RISINGEDGE
+#endif
+
+/* Mode dependent settings.  These depend on clock divisor settings that must
+ * be defined in the board-specific board.h header file: STM32_SDMMC_INIT_CLKDIV,
+ * STM32_SDMMC_MMCXFR_CLKDIV, and STM32_SDMMC_SDXFR_CLKDIV.
+ */
+
+#define STM32_CLCKCR_INIT           (STM32_SDMMC_INIT_CLKDIV      |     \
+                                     STM32_SDMMC_CLKCR_EDGE       |     \
+                                     STM32_SDMMC_CLKCR_WIDBUS_D1)
+#define STM32_SDMMC_CLKCR_MMCXFR    (STM32_SDMMC_MMCXFR_CLKDIV    |     \
+                                     STM32_SDMMC_CLKCR_EDGE       |     \
+                                     STM32_SDMMC_CLKCR_PWRSAV     |     \
+                                     STM32_SDMMC_CLKCR_WIDBUS_D1)
+#define STM32_SDMMC_CLCKR_SDXFR     (STM32_SDMMC_SDXFR_CLKDIV     |     \
+                                     STM32_SDMMC_CLKCR_EDGE       |     \
+                                     STM32_SDMMC_CLKCR_PWRSAV     |     \
+                                     STM32_SDMMC_CLKCR_WIDBUS_D1)
+#define STM32_SDMMC_CLCKR_SDWIDEXFR (STM32_SDMMC_SDXFR_CLKDIV     |     \
+                                     STM32_SDMMC_CLKCR_EDGE       |     \
+                                     STM32_SDMMC_CLKCR_PWRSAV     |     \
+                                     STM32_SDMMC_CLKCR_WIDBUS_D4)
+
+/* Timing */
+
+#define SDMMC_CMDTIMEOUT         (100000)
+#define SDMMC_LONGTIMEOUT        (0x7fffffff)
+
+/* Big DTIMER setting */
+
+#define SDMMC_DTIMER_DATATIMEOUT (0x000fffff)
+
+/* FIFO sizes */
+
+#define SDMMC_HALFFIFO_WORDS      (8)
+#define SDMMC_HALFFIFO_BYTES      (8*4)
+
+/* Data transfer interrupt mask bits */
+
+#if defined(CONFIG_STM32H7_SDMMC_DMA)
+/* DMA interrupts */
+
+#define STM32_SDMMC_RECV_MASK     (STM32_SDMMC_MASK_DCRCFAILIE |        \
+                                   STM32_SDMMC_MASK_DTIMEOUTIE |        \
+                                   STM32_SDMMC_MASK_DATAENDIE  |        \
+                                   STM32_SDMMC_MASK_RXOVERRIE)
+
+#define STM32_SDMMC_SEND_MASK     (STM32_SDMMC_MASK_DCRCFAILIE |        \
+                                   STM32_SDMMC_MASK_DTIMEOUTIE |        \
+                                   STM32_SDMMC_MASK_DATAENDIE  |        \
+                                   STM32_SDMMC_MASK_TXUNDERRIE)
+#define STM32_SDMMC_XFRDONE_MASK  (0)
+#else
+/* Interrupt mode */
+
+#define STM32_SDMMC_RECV_MASK     (STM32_SDMMC_MASK_DCRCFAILIE |        \
+                                   STM32_SDMMC_MASK_DTIMEOUTIE |        \
+                                   STM32_SDMMC_MASK_DATAENDIE  |        \
+                                   STM32_SDMMC_MASK_RXOVERRIE  |        \
+                                   STM32_SDMMC_MASK_RXFIFOHFIE)
+
+#define STM32_SDMMC_SEND_MASK     (STM32_SDMMC_MASK_DCRCFAILIE |        \
+                                   STM32_SDMMC_MASK_DTIMEOUTIE |        \
+                                   STM32_SDMMC_MASK_DATAENDIE  |        \
+                                   STM32_SDMMC_MASK_TXFIFOHEIE |        \
+                                   STM32_SDMMC_MASK_TXUNDERRIE)
+
+#endif
+
+/* Event waiting interrupt mask bits */
+
+#define STM32_SDMMC_CMDDONE_STA   (STM32_SDMMC_STA_CMDSENT)
+
+#define STM32_SDMMC_RESPDONE_STA  (STM32_SDMMC_STA_CTIMEOUT |    \
+                                   STM32_SDMMC_STA_CCRCFAIL |    \
+                                   STM32_SDMMC_STA_CMDREND)
+
+#define STM32_SDMMC_CMDDONE_MASK  (STM32_SDMMC_MASK_CMDSENTIE)
+
+#define STM32_SDMMC_RESPDONE_MASK (STM32_SDMMC_MASK_CCRCFAILIE | \
+                                   STM32_SDMMC_MASK_CTIMEOUTIE | \
+                                   STM32_SDMMC_MASK_CMDRENDIE)
+
+#define STM32_SDMMC_XFRDONE_MASK  (0)
+
+#define STM32_SDMMC_CMDDONE_ICR   (STM32_SDMMC_ICR_CMDSENTC |    \
+                                   STM32_SDMMC_ICR_DBCKENDC)
+
+#define STM32_SDMMC_RESPDONE_ICR  (STM32_SDMMC_ICR_CTIMEOUTC |   \
+                                   STM32_SDMMC_ICR_CCRCFAILC |   \
+                                   STM32_SDMMC_ICR_CMDRENDC  |   \
+                                   STM32_SDMMC_ICR_DBCKENDC)
+
+#define STM32_SDMMC_XFRDONE_ICR   (STM32_SDMMC_ICR_DATAENDC  |   \
+                                   STM32_SDMMC_ICR_DCRCFAILC |   \
+                                   STM32_SDMMC_ICR_DTIMEOUTC |   \
+                                   STM32_SDMMC_ICR_RXOVERRC  |   \
+                                   STM32_SDMMC_ICR_TXUNDERRC |   \
+                                   STM32_SDMMC_ICR_DBCKENDC)
+
+#define STM32_SDMMC_WAITALL_ICR   (STM32_SDMMC_CMDDONE_ICR   |   \
+                                   STM32_SDMMC_RESPDONE_ICR  |   \
+                                   STM32_SDMMC_XFRDONE_ICR   |   \
+                                   STM32_SDMMC_ICR_DBCKENDC)
+
+/* Let's wait until we have both SDIO transfer complete and DMA complete. */
+
+#define SDMMC_XFRDONE_FLAG  (1)
+#define SDMMC_DMADONE_FLAG  (2)
+#define SDMMC_ALLDONE       (3)
+
+/* Register logging support */
+
+#ifdef CONFIG_STM32H7_SDMMC_XFRDEBUG
+#  ifdef CONFIG_STM32H7_SDMMC_MDMA
+#    define SAMPLENDX_BEFORE_SETUP  0
+#    define SAMPLENDX_BEFORE_ENABLE 1
+#    define SAMPLENDX_AFTER_SETUP   2
+#    define SAMPLENDX_END_TRANSFER  3
+#    define SAMPLENDX_DMA_CALLBACK  4
+#    define DEBUG_NSAMPLES          5
+#  else
+#    define SAMPLENDX_BEFORE_SETUP  0
+#    define SAMPLENDX_AFTER_SETUP   1
+#    define SAMPLENDX_END_TRANSFER  2
+#    define DEBUG_NSAMPLES          3
+#  endif
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure defines the state of the STM32 SDMMC interface */
+
+struct stm32_dev_s
+{
+  struct sdio_dev_s  dev;        /* Standard, base SDIO interface */
+
+  /* STM32-specific extensions */
+
+  uint32_t          base;
+  int               nirq;
+#ifdef CONFIG_ARCH_IRQPRIO
+  int               irqprio;
+#endif
+#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
+  uint32_t          d0_gpio;
+#endif
+
+  /* Event support */
+
+  sem_t              waitsem;    /* Implements event waiting */
+  sdio_eventset_t    waitevents; /* Set of events to be waited for */
+  uint32_t           waitmask;   /* Interrupt enables for event waiting */
+  volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */
+  WDOG_ID            waitwdog;   /* Watchdog that handles event timeouts */
+
+  /* Callback support */
+
+  sdio_statset_t     cdstatus;   /* Card status */
+  sdio_eventset_t    cbevents;   /* Set of events to be cause callbacks */
+  worker_t           callback;   /* Registered callback function */
+  void              *cbarg;      /* Registered callback argument */
+  struct work_s      cbwork;     /* Callback work queue structure */
+
+  /* Interrupt mode data transfer support */
+
+  uint32_t          *buffer;     /* Address of current R/W buffer */
+  size_t             remaining;  /* Number of bytes remaining in the transfer */
+  uint32_t           xfrmask;    /* Interrupt enables for data transfer */
+
+  bool               widebus;
+  bool               onebit;     /* true: Only 1-bit transfers are supported */
+
+  bool               receive;    /* true: data receive transfer */
+
+  /* MDMA data transfer support */
+};
+
+/* Register logging support */
+
+#ifdef CONFIG_STM32H7_SDMMC_XFRDEBUG
+struct stm32_sdioregs_s
+{
+  uint8_t  power;
+  uint16_t clkcr;
+  uint16_t dctrl;
+  uint32_t dtimer;
+  uint32_t dlen;
+  uint32_t dcount;
+  uint32_t sta;
+  uint32_t mask;
+  uint32_t fifocnt;
+};
+
+struct stm32_sampleregs_s
+{
+  struct stm32_sdioregs_s sdio;
+};
+#endif
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Low-level helpers ********************************************************/
+
+static inline void sdmmc_putreg32(struct stm32_dev_s *priv, uint32_t value,
+                                  int offset);
+static inline uint32_t sdmmc_getreg32(struct stm32_dev_s *priv, int offset);
+static void stm32_takesem(struct stm32_dev_s *priv);
+#define     stm32_givesem(priv) (nxsem_post(&priv->waitsem))
+static inline void stm32_setclkcr(struct stm32_dev_s *priv, uint32_t clkcr);
+static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask,
+                                 sdio_eventset_t waitevents,
+                                 sdio_eventset_t wkupevents);
+static void stm32_configxfrints(struct stm32_dev_s *priv, uint32_t xfrmask);
+static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl);
+static inline uint32_t stm32_getpwrctrl(struct stm32_dev_s *priv);
+
+/* DMA Helpers **************************************************************/
+
+#ifdef CONFIG_STM32H7_SDMMC_XFRDEBUG
+static void stm32_sampleinit(void);
+static void stm32_sdiosample(struct stm32_dev_s *priv,
+                             struct stm32_sdioregs_s *regs);
+static void stm32_sample(struct stm32_dev_s *priv, int index);
+static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg);
+static void stm32_dumpsample(struct stm32_dev_s *priv,
+                             struct stm32_sampleregs_s *regs,
+                             const char *msg);
+static void stm32_dumpsamples(struct stm32_dev_s *priv);
+#else
+#  define   stm32_sampleinit()
+#  define   stm32_sample(priv,index)
+#  define   stm32_dumpsamples(priv)
+#endif
+
+/* Data Transfer Helpers ****************************************************/
+
+static uint8_t stm32_log2(uint16_t value);
+static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout,
+                             uint32_t dlen, uint32_t dctrl);
+static void stm32_datadisable(struct stm32_dev_s *priv);
+#ifndef CONFIG_STM32H7_SDMMC_IDMA
+static void stm32_sendfifo(struct stm32_dev_s *priv);
+static void stm32_recvfifo(struct stm32_dev_s *priv);
+#endif
+static void stm32_eventtimeout(int argc, uint32_t arg);
+static void stm32_endwait(struct stm32_dev_s *priv,
+                          sdio_eventset_t wkupevent);
+static void stm32_endtransfer(struct stm32_dev_s *priv,
+                              sdio_eventset_t wkupevent);
+
+/* Interrupt Handling *******************************************************/
+
+static int  stm32_sdmmc_interrupt(int irq, void *context, void *arg);
+#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
+static int  stm32_sdmmc_rdyinterrupt(int irq, void *context, void *arg);
+#endif
+
+/* SDIO interface methods ***************************************************/
+
+/* Mutual exclusion */
+
+#ifdef CONFIG_SDIO_MUXBUS
+static int stm32_lock(FAR struct sdio_dev_s *dev, bool lock);
+#endif
+
+/* Initialization/setup */
+
+static void stm32_reset(FAR struct sdio_dev_s *dev);
+static sdio_capset_t stm32_capabilities(FAR struct sdio_dev_s *dev);
+static sdio_statset_t stm32_status(FAR struct sdio_dev_s *dev);
+static void stm32_widebus(FAR struct sdio_dev_s *dev, bool enable);
+static void stm32_clock(FAR struct sdio_dev_s *dev,
+                        enum sdio_clock_e rate);
+static int  stm32_attach(FAR struct sdio_dev_s *dev);
+
+/* Command/Status/Data Transfer */
+
+static int  stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
+                          uint32_t arg);
+static int  stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
+                            size_t nbytes);
+static int  stm32_sendsetup(FAR struct sdio_dev_s *dev,
+                            FAR const uint8_t *buffer, uint32_t nbytes);
+static int  stm32_cancel(FAR struct sdio_dev_s *dev);
+
+static int  stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd);
+static int  stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
+                               uint32_t *rshort);
+static int  stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd,
+                           uint32_t rlong[4]);
+static int  stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd,
+                            uint32_t *rshort);
+static int  stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd,
+                              uint32_t *rnotimpl);
+
+/* EVENT handler */
+
+static void stm32_waitenable(FAR struct sdio_dev_s *dev,
+                             sdio_eventset_t eventset);
+static sdio_eventset_t
+stm32_eventwait(FAR struct sdio_dev_s *dev, uint32_t timeout);
+static void stm32_callbackenable(FAR struct sdio_dev_s *dev,
+                                 sdio_eventset_t eventset);
+static int  stm32_registercallback(FAR struct sdio_dev_s *dev,
+                                   worker_t callback, void *arg);
+
+/* DMA */
+
+#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_SDIO_PREFLIGHT
+static int  stm32_dmapreflight(FAR struct sdio_dev_s *dev,
+                               FAR const uint8_t *buffer, size_t buflen);
+#endif
+static int  stm32_dmarecvsetup(FAR struct sdio_dev_s *dev,
+                               FAR uint8_t *buffer, size_t buflen);
+static int  stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
+                               FAR const uint8_t *buffer, size_t buflen);
+#endif
+
+/* Initialization/uninitialization/reset ************************************/
+
+static void stm32_callback(void *arg);
+static void stm32_default(struct stm32_dev_s *priv);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+#ifdef CONFIG_STM32H7_SDMMC1
+struct stm32_dev_s g_sdmmcdev1 =
+{
+  .dev =
+  {
+#ifdef CONFIG_SDIO_MUXBUS
+    .lock             = stm32_lock,
+#endif
+    .reset            = stm32_reset,
+    .capabilities     = stm32_capabilities,
+    .status           = stm32_status,
+    .widebus          = stm32_widebus,
+    .clock            = stm32_clock,
+    .attach           = stm32_attach,
+    .sendcmd          = stm32_sendcmd,
+#ifdef CONFIG_SDIO_BLOCKSETUP
+    .blocksetup       = stm32_blocksetup, /* Not implemented yet */
+#endif
+    .recvsetup        = stm32_recvsetup,
+    .sendsetup        = stm32_sendsetup,
+    .cancel           = stm32_cancel,
+    .waitresponse     = stm32_waitresponse,
+    .recvR1           = stm32_recvshortcrc,
+    .recvR2           = stm32_recvlong,
+    .recvR3           = stm32_recvshort,
+    .recvR4           = stm32_recvnotimpl,
+    .recvR5           = stm32_recvnotimpl,
+    .recvR6           = stm32_recvshortcrc,
+    .recvR7           = stm32_recvshort,
+    .waitenable       = stm32_waitenable,
+    .eventwait        = stm32_eventwait,
+    .callbackenable   = stm32_callbackenable,
+    .registercallback = stm32_registercallback,
+#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_SDIO_PREFLIGHT
+    .dmapreflight     = stm32_dmapreflight,
+#endif
+    .dmarecvsetup     = stm32_dmarecvsetup,
+    .dmasendsetup     = stm32_dmasendsetup,
+#endif
+  },
+  .base              = STM32_SDMMC1_BASE,
+  .nirq              = STM32_IRQ_SDMMC1,
+#ifdef CONFIG_SDMMC1_PRI
+  .irqprio           = CONFIG_SDMMC1_PRI,
+#endif
+#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
+  .d0_gpio           = GPIO_SDMMC1_D0,
+#endif
+};
+#endif
+#ifdef CONFIG_STM32H7_SDMMC2
+struct stm32_dev_s g_sdmmcdev2 =
+{
+  .dev =
+  {
+#ifdef CONFIG_SDIO_MUXBUS
+    .lock             = stm32_lock,
+#endif
+    .reset            = stm32_reset,
+    .capabilities     = stm32_capabilities,
+    .status           = stm32_status,
+    .widebus          = stm32_widebus,
+    .clock            = stm32_clock,
+    .attach           = stm32_attach,
+    .sendcmd          = stm32_sendcmd,
+#ifdef CONFIG_SDIO_BLOCKSETUP
+    .blocksetup       = stm32_blocksetup, /* Not implemented yet */
+#endif
+    .recvsetup        = stm32_recvsetup,
+    .sendsetup        = stm32_sendsetup,
+    .cancel           = stm32_cancel,
+    .waitresponse     = stm32_waitresponse,
+    .recvR1           = stm32_recvshortcrc,
+    .recvR2           = stm32_recvlong,
+    .recvR3           = stm32_recvshort,
+    .recvR4           = stm32_recvnotimpl,
+    .recvR5           = stm32_recvnotimpl,
+    .recvR6           = stm32_recvshortcrc,
+    .recvR7           = stm32_recvshort,
+    .waitenable       = stm32_waitenable,
+    .eventwait        = stm32_eventwait,
+    .callbackenable   = stm32_callbackenable,
+    .registercallback = stm32_registercallback,
+#ifdef CONFIG_SDIO_DMA
+#ifdef CONFIG_SDIO_PREFLIGHT
+    .dmapreflight     = stm32_dmapreflight,
+#endif
+    .dmarecvsetup     = stm32_dmarecvsetup,
+    .dmasendsetup     = stm32_dmasendsetup,
+#endif
+  },
+  .base              = STM32_SDMMC2_BASE,
+  .nirq              = STM32_IRQ_SDMMC2,
+#ifdef CONFIG_SDMMC2_PRI
+  .irqprio           = CONFIG_SDMMC2_PRI,
+#endif
+#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
+  .d0_gpio           = GPIO_SDMMC2_D0,
+#endif
+};
+#endif
+/* Register logging support */
+
+#ifdef CONFIG_STM32H7_SDMMC_XFRDEBUG
+static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES];
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sdmmc_putreg32
+ ****************************************************************************/
+
+static inline void sdmmc_putreg32(struct stm32_dev_s *priv, uint32_t value,
+                                  int offset)
+{
+  putreg32(value, priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: sdmmc_gettreg32
+ ****************************************************************************/
+
+static inline uint32_t sdmmc_getreg32(struct stm32_dev_s *priv, int offset)
+{
+  return getreg32(priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: sdmmc_modifyreg32
+ ****************************************************************************/
+
+static inline void sdmmc_modifyreg32(struct stm32_dev_s *priv, int offset,
+                                     uint32_t clearbits, uint32_t setbits)
+{
+  irqstate_t flags;
+  int32_t   regval;
+
+  flags   = enter_critical_section();
+  regval  = getreg32(priv->base + offset);
+  regval &= ~clearbits;
+  regval |= setbits;
+  putreg32(regval, priv->base + offset);
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: stm32_takesem
+ *
+ * Description:
+ *   Take the wait semaphore (handling false alarm wakeups due to the receipt
+ *   of signals).
+ *
+ * Input Parameters:
+ *   priv  - Instance of the SDMMC private state structure.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void stm32_takesem(struct stm32_dev_s *priv)
+{
+  /* Take the semaphore (perhaps waiting) */
+
+  while (nxsem_wait(&priv->waitsem) != 0)
+    {
+      /* The only case that an error should occr here is if the wait was
+       * awakened by a signal.
+       */
+
+      DEBUGASSERT(errno == EINTR);
+    }
+}
+
+/****************************************************************************
+ * Name: stm32_setclkcr
+ *
+ * Description:
+ *   Modify oft-changed bits in the CLKCR register.  Only the following bit-
+ *   fields are changed:
+ *
+ *   CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, and HWFC_EN
+ *
+ * Input Parameters:
+ *   priv       - Instance of the SDMMC private state structure.
+ *   clkcr - A new CLKCR setting for the above mentions bits (other bits
+ *           are ignored.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void stm32_setclkcr(struct stm32_dev_s *priv, uint32_t clkcr)
+{
+  uint32_t regval = sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET);
+
+  /* Clear CLKDIV, PWRSAV, WIDBUS, NEGEDGE, HWFC_EN bits */
+
+  regval &= ~(STM32_SDMMC_CLKCR_CLKDIV_MASK | STM32_SDMMC_CLKCR_PWRSAV      |
+              STM32_SDMMC_CLKCR_WIDBUS_MASK |
+              STM32_SDMMC_CLKCR_NEGEDGE     | STM32_SDMMC_CLKCR_HWFC_EN);
+
+  /* Replace with user provided settings */
+
+  clkcr  &=  (STM32_SDMMC_CLKCR_CLKDIV_MASK | STM32_SDMMC_CLKCR_PWRSAV      |
+              STM32_SDMMC_CLKCR_WIDBUS_MASK |
+              STM32_SDMMC_CLKCR_NEGEDGE     | STM32_SDMMC_CLKCR_HWFC_EN);
+
+  regval |=  clkcr;
+  regval |= STM32_SDMMC_CLKCR_HWFC_EN;
+
+  sdmmc_putreg32(priv, regval, STM32_SDMMC_CLKCR_OFFSET);
+
+  mcinfo("CLKCR: %08x PWR: %08x\n",
+         sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET),
+         sdmmc_getreg32(priv, STM32_SDMMC_POWER_OFFSET));
+}
+
+/****************************************************************************
+ * Name: stm32_configwaitints
+ *
+ * Description:
+ *   Enable/disable SDIO interrupts needed to suport the wait function
+ *
+ * Input Parameters:
+ *   priv       - Instance of the SDMMC private state structure.
+ *   waitmask   - The set of bits in the SDIO MASK register to set
+ *   waitevents - Waited for events
+ *   wkupevent  - Wake-up events
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask,
+                                 sdio_eventset_t waitevents,
+                                 sdio_eventset_t wkupevent)
+{
+  irqstate_t flags;
+#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
+  int pinset;
+#endif
+
+  /* Save all of the data and set the new interrupt mask in one, atomic
+   * operation.
+   */
+  flags = enter_critical_section();
+
+#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
+  if ((waitmask & SDIOWAIT_WRCOMPLETE) != 0)
+  {
+    /* Do not use this in STM32_SDMMC_MASK register */
+
+    waitmask &= !SDIOWAIT_WRCOMPLETE;
+
+    pinset = priv->d0_gpio & (GPIO_PORT_MASK | GPIO_PIN_MASK);
+    pinset |= (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI);
+
+    /* Arm the SDMMC_D Ready and install Isr */
+
+    (void)stm32_gpiosetevent(pinset, true, false, false,
+                             stm32_sdmmc_rdyinterrupt, priv);
+  }
+
+  /* Disarm SDMMC_D ready */
+
+  if ((wkupevent & SDIOWAIT_WRCOMPLETE) != 0)
+  {
+    (void)stm32_gpiosetevent(priv->d0_gpio, false, false, false,
+                             NULL, NULL);
+    stm32_configgpio(priv->d0_gpio);
+  }
+#endif
+
+  priv->waitevents = waitevents;
+  priv->wkupevent  = wkupevent;
+  priv->waitmask   = waitmask;
+#ifdef CONFIG_STM32H7_SDMMC_MDMA
+  priv->xfrflags   = 0;
+#endif
+  sdmmc_putreg32(priv, priv->xfrmask | priv->waitmask,
+                 STM32_SDMMC_MASK_OFFSET);
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: stm32_configxfrints
+ *
+ * Description:
+ *   Enable SDIO interrupts needed to support the data transfer event
+ *
+ * Input Parameters:
+ *   priv    - Instance of the SDMMC private state structure.
+ *   xfrmask - The set of bits in the SDIO MASK register to set
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void stm32_configxfrints(struct stm32_dev_s *priv, uint32_t xfrmask)
+{
+  irqstate_t flags;
+
+  flags = enter_critical_section();
+  priv->xfrmask = xfrmask;
+  sdmmc_putreg32(priv, priv->xfrmask | priv->waitmask,
+                 STM32_SDMMC_MASK_OFFSET);
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: stm32_setpwrctrl
+ *
+ * Description:
+ *   Change the PWRCTRL field of the SDIO POWER register to turn the SDIO
+ *   ON or OFF
+ *
+ * Input Parameters:
+ *   priv  - Instance of the SDMMC private state structure.
+ *   clkcr - A new PWRCTRL setting
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl)
+{
+  uint32_t regval;
+
+  regval  = sdmmc_getreg32(priv, STM32_SDMMC_POWER_OFFSET);
+  regval &= ~STM32_SDMMC_POWER_PWRCTRL_MASK;
+  regval |= pwrctrl;
+  sdmmc_putreg32(priv, regval, STM32_SDMMC_POWER_OFFSET);
+}
+
+/****************************************************************************
+ * Name: stm32_getpwrctrl
+ *
+ * Description:
+ *   Return the current value of the  the PWRCTRL field of the SDIO POWER
+ *   register.  This function can be used to see if the SDIO is powered ON
+ *   or OFF
+ *
+ * Input Parameters:
+ *   priv  - Instance of the SDMMC private state structure.
+ *
+ * Returned Value:
+ *   The current value of the  the PWRCTRL field of the SDIO POWER register.
+ *
+ ****************************************************************************/
+
+static inline uint32_t stm32_getpwrctrl(struct stm32_dev_s *priv)
+{
+  return sdmmc_getreg32(priv, STM32_SDMMC_POWER_OFFSET) &
+    STM32_SDMMC_POWER_PWRCTRL_MASK;
+}
+
+/****************************************************************************
+ * Name: stm32_sample
+ *
+ * Description:
+ *   Sample SDIO/DMA registers
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32H7_SDMMC_XFRDEBUG
+static void stm32_sample(struct stm32_dev_s *priv, int index)
+{
+  struct stm32_sampleregs_s *regs = &g_sampleregs[index];
+
+  stm32_sdiosample(priv, ®s->sdio);
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_sdiodump
+ *
+ * Description:
+ *   Dump one register sample
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32H7_SDMMC_XFRDEBUG
+static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg)
+{
+  mcinfo("SDIO Registers: %s\n", msg);
+  mcinfo("  POWER[%08x]: %08x\n", STM32_SDMMC_POWER_OFFSET,   regs->power);
+  mcinfo("  CLKCR[%08x]: %08x\n", STM32_SDMMC_CLKCR_OFFSET,   regs->clkcr);
+  mcinfo("  DCTRL[%08x]: %08x\n", STM32_SDMMC_DCTRL_OFFSET,   regs->dctrl);
+  mcinfo(" DTIMER[%08x]: %08x\n", STM32_SDMMC_DTIMER_OFFSET,  regs->dtimer);
+  mcinfo("   DLEN[%08x]: %08x\n", STM32_SDMMC_DLEN_OFFSET,    regs->dlen);
+  mcinfo(" DCOUNT[%08x]: %08x\n", STM32_SDMMC_DCOUNT_OFFSET,  regs->dcount);
+  mcinfo("    STA[%08x]: %08x\n", STM32_SDMMC_STA_OFFSET,     regs->sta);
+  mcinfo("   MASK[%08x]: %08x\n", STM32_SDMMC_MASK_OFFSET,    regs->mask);
+  mcinfo("FIFOCNT[%08x]: %08x\n", STM32_SDMMC_FIFOCNT_OFFSET, regs->fifocnt);
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_dumpsample
+ *
+ * Description:
+ *   Dump one register sample
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32H7_SDMMC_XFRDEBUG
+static void stm32_dumpsample(struct stm32_dev_s *priv,
+                             struct stm32_sampleregs_s *regs,
+                             const char *msg)
+{
+  stm32_sdiodump(®s->sdio, msg);
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_dumpsamples
+ *
+ * Description:
+ *   Dump all sampled register data
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32H7_SDMMC_XFRDEBUG
+static void stm32_dumpsamples(struct stm32_dev_s *priv)
+{
+  stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP],
+                   "Before setup");
+  stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_AFTER_SETUP],
+                   "After setup");
+  stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER],
+                   "End of transfer");
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_log2
+ *
+ * Description:
+ *   Take (approximate) log base 2 of the provided number (Only works if the
+ *   provided number is a power of 2).
+ *
+ ****************************************************************************/
+
+static uint8_t stm32_log2(uint16_t value)
+{
+  uint8_t log2 = 0;
+
+  /* 0000 0000 0000 0001 -> return 0,
+   * 0000 0000 0000 001x -> return 1,
+   * 0000 0000 0000 01xx -> return 2,
+   * 0000 0000 0000 1xxx -> return 3,
+   * ...
+   * 1xxx xxxx xxxx xxxx -> return 15,
+   */
+
+  DEBUGASSERT(value > 0);
+  while (value != 1)
+  {
+    value >>= 1;
+    log2++;
+  }
+
+  return log2;
+}
+
+/****************************************************************************
+ * Name: stm32_dataconfig
+ *
+ * Description:
+ *   Configure the SDIO data path for the next data transfer
+ *
+ ****************************************************************************/
+
+static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout,
+                             uint32_t dlen, uint32_t dctrl)
+{
+  /* Enable data path */
+
+  sdmmc_putreg32(priv, timeout, STM32_SDMMC_DTIMER_OFFSET); /* Set DTIMER */
+  sdmmc_putreg32(priv, dlen,    STM32_SDMMC_DLEN_OFFSET);   /* Set DLEN */
+
+  /* Mask off any extra bits */
+
+  dctrl &= (STM32_SDMMC_DCTRL_DBLOCKSIZE_MASK |
+            STM32_SDMMC_DCTRL_DTDIR);
+
+  dctrl |= (dctrl | STM32_SDMMC_DCTRL_DTMODE_SDIO |
+            STM32_SDMMC_DCTRL_SDIOEN);
+
+#ifdef CONFIG_STM32H7_SDMMC_IDMA
+  sdmmc_putreg32(priv, (uintptr_t)priv->buffer,
+                 STM32_SDMMC_IDMABASE0R_OFFSET);
+  sdmmc_putreg32(priv, STM32_SDMMC_IDMACTRLR_IDMAEN,
+                 STM32_SDMMC_IDMACTRLR_OFFSET);
+#else
+#if 0
+  dctrl |= STM32_SDMMC_DCTRL_FIFORST;
+#endif
+#endif
+
+  sdmmc_putreg32(priv, dctrl, STM32_SDMMC_DCTRL_OFFSET);
+}
+
+/****************************************************************************
+ * Name: stm32_datadisable
+ *
+ * Description:
+ *   Disable the SDIO data path setup by stm32_dataconfig() and
+ *   disable DMA.
+ *
+ ****************************************************************************/
+
+static void stm32_datadisable(struct stm32_dev_s *priv)
+{
+  /* Disable the data path */
+
+  /* Reset DTIMER */
+
+  sdmmc_putreg32(priv, SDMMC_DTIMER_DATATIMEOUT, STM32_SDMMC_DTIMER_OFFSET);
+  sdmmc_putreg32(priv, 0, STM32_SDMMC_DLEN_OFFSET);   /* Reset DLEN */
+
+  /* Reset DCTRL */
+
+  sdmmc_putreg32(priv, 0, STM32_SDMMC_DCTRL_OFFSET);
+}
+
+#ifndef CONFIG_STM32H7_SDMMC_IDMA
+/****************************************************************************
+ * Name: stm32_sendfifo
+ *
+ * Description:
+ *   Send SDIO data in interrupt mode
+ *
+ * Input Parameters:
+ *   priv  - Instance of the SDMMC private state structure.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void stm32_sendfifo(struct stm32_dev_s *priv)
+{
+  union
+  {
+    uint32_t w;
+    uint8_t  b[4];
+  } data;
+
+  /* Loop while there is more data to be sent and the RX FIFO is not full */
+
+  while (priv->remaining > 0 &&
+         (sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET) &
+          STM32_SDMMC_STA_TXFIFOF) == 0)
+  {
+    /* Is there a full word remaining in the user buffer? */
+
+    if (priv->remaining >= sizeof(uint32_t))
+    {
+      /* Yes, transfer the word to the TX FIFO */
+
+      data.w           = *priv->buffer++;
+      priv->remaining -= sizeof(uint32_t);
+    }
+    else
+    {
+      /* No.. transfer just the bytes remaining in the user buffer,
+       * padding with zero as necessary to extend to a full word.
+       */
+
+      uint8_t *ptr = (uint8_t *)priv->remaining;
+      int i;
+
+      data.w = 0;
+      for (i = 0; i < (int)priv->remaining; i++)
+      {
+        data.b[i] = *ptr++;
+      }
+
+      /* Now the transfer is finished */
+
+      priv->remaining = 0;
+    }
+
+    /* Put the word in the FIFO */
+
+    sdmmc_putreg32(priv, data.w, STM32_SDMMC_FIFO_OFFSET);
+  }
+}
+
+/****************************************************************************
+ * Name: stm32_recvfifo
+ *
+ * Description:
+ *   Receive SDIO data in interrupt mode
+ *
+ * Input Parameters:
+ *   priv  - Instance of the SDMMC private state structure.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void stm32_recvfifo(struct stm32_dev_s *priv)
+{
+  union
+  {
+    uint32_t w;
+    uint8_t  b[4];
+  } data;
+
+  /* Loop while there is space to store the data and there is more
+   * data available in the RX FIFO.
+   */
+
+  while (priv->remaining > 0 &&
+         (sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET) &
+          STM32_SDMMC_STA_RXFIFOE) == 0)
+  {
+    /* Read the next word from the RX FIFO */
+
+    data.w = sdmmc_getreg32(priv, STM32_SDMMC_FIFO_OFFSET);
+    if (priv->remaining >= sizeof(uint32_t))
+    {
+      /* Transfer the whole word to the user buffer */
+
+      *priv->buffer++  = data.w;
+      priv->remaining -= sizeof(uint32_t);
+    }
+    else
+    {
+      /* Transfer any trailing fractional word */
+
+      uint8_t *ptr = (uint8_t *)priv->buffer;
+      int i;
+
+      for (i = 0; i < (int)priv->remaining; i++)
+      {
+        *ptr++ = data.b[i];
+      }
+
+      /* Now the transfer is finished */
+
+      priv->remaining = 0;
+    }
+  }
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_eventtimeout
+ *
+ * Description:
+ *   The watchdog timeout setup when the event wait start has expired without
+ *   any other waited-for event occurring.
+ *
+ * Input Parameters:
+ *   argc   - The number of arguments (should be 1)
+ *   arg    - The argument (the SDMMC private state structure reference cast
+ *            to uint32_t)
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Always called from the interrupt level with interrupts disabled.
+ *
+ ****************************************************************************/
+
+static void stm32_eventtimeout(int argc, uint32_t arg)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)arg;
+
+  /* There is always race conditions with timer expirations. */
+
+  DEBUGASSERT((priv->waitevents & SDIOWAIT_TIMEOUT) != 0 ||
+              priv->wkupevent != 0);
+
+  mcinfo("sta: %08x enabled irq: %08x\n",
+         sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET),
+         sdmmc_getreg32(priv, STM32_SDMMC_MASK_OFFSET));
+
+  /* Is a data transfer complete event expected? */
+
+  if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0)
+  {
+    /* Yes.. wake up any waiting threads */
+
+    stm32_endwait(priv, SDIOWAIT_TIMEOUT);
+    mcerr("Timeout: remaining: %d\n", priv->remaining);
+  }
+}
+
+/****************************************************************************
+ * Name: stm32_endwait
+ *
+ * Description:
+ *   Wake up a waiting thread if the waited-for event has occurred.
+ *
+ * Input Parameters:
+ *   priv  - Instance of the SDMMC private state structure.
+ *   wkupevent - The event that caused the wait to end
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Always called from the interrupt level with interrupts disabled.
+ *
+ ****************************************************************************/
+
+static void stm32_endwait(struct stm32_dev_s *priv, sdio_eventset_t wkupevent)
+{
+  /* Cancel the watchdog timeout */
+
+  (void)wd_cancel(priv->waitwdog);
+
+  /* Disable event-related interrupts */
+
+  stm32_configwaitints(priv, 0, 0, wkupevent);
+
+  /* Wake up the waiting thread */
+
+  stm32_givesem(priv);
+}
+
+/****************************************************************************
+ * Name: stm32_endtransfer
+ *
+ * Description:
+ *   Terminate a transfer with the provided status.  This function is called
+ *   only from the SDIO interrupt handler when end-of-transfer conditions
+ *   are detected.
+ *
+ * Input Parameters:
+ *   priv  - Instance of the SDMMC private state structure.
+ *   wkupevent - The event that caused the transfer to end
+ *
+ * Returned Value:
+ *   None
+ *
+ * Assumptions:
+ *   Always called from the interrupt level with interrupts disabled.
+ *
+ ****************************************************************************/
+
+static void stm32_endtransfer(struct stm32_dev_s *priv,
+                              sdio_eventset_t wkupevent)
+{
+  /* Disable all transfer related interrupts */
+
+  stm32_configxfrints(priv, 0);
+
+  /* If there were errors, send a stop command to DPSM */
+
+  if ((wkupevent & (~SDIOWAIT_TRANSFERDONE)) != 0)
+    {
+      stm32_sendcmd((FAR struct sdio_dev_s *)priv,
+                    STM32_SDMMC_CMD_CMDSTOP, 0);
+    }
+
+  /* Clearing pending interrupt status on all transfer related interrupts */
+
+  sdmmc_putreg32(priv, STM32_SDMMC_XFRDONE_ICR, STM32_SDMMC_ICR_OFFSET);
+
+  /* invalidate dcache in case of DMA receive. */
+
+  if (priv->receive)
+    {
+      up_invalidate_dcache((uintptr_t)priv->buffer,
+                           (uintptr_t)priv->buffer + priv->remaining);
+    }
+
+  /* Mark the transfer finished */
+
+  priv->remaining = 0;
+
+  /* Is a thread wait for these data transfer complete events? */
+
+  if ((priv->waitevents & wkupevent) != 0)
+    {
+      /* Yes.. wake up any waiting threads */
+
+      stm32_endwait(priv, wkupevent);
+    }
+}
+
+/****************************************************************************
+ * Name: stm32_sdmmc[1|2]_rdyinterrupt
+ *
+ * Description:
+ *   SDMMC ready interrupt handler
+ *
+ * Input Parameters:
+ *   irq     - not used
+ *   context - not used
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
+static int stm32_sdmmc_rdyinterrupt(int irq, void *context, void *arg)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)arg;
+  stm32_endwait(priv, SDIOWAIT_WRCOMPLETE);
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_sdmmc_interrupt
+ *
+ * Description:
+ *   SDMMC interrupt handler
+ *
+ * Input Parameters:
+ *   priv  - Instance of the SDMMC private state structure.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static int stm32_sdmmc_interrupt(int irq, void *context, void *arg)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)arg;
+  uint32_t enabled;
+  uint32_t pending;
+
+  DEBUGASSERT(priv != NULL);
+
+  /* Loop while there are pending interrupts.  Check the SDIO status
+   * register.  Mask out all bits that don't correspond to enabled
+   * interrupts.  (This depends on the fact that bits are ordered
+   * the same in both the STA and MASK register).  If there are non-zero
+   * bits remaining, then we have work to do here.
+   */
+
+  while ((enabled = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET) &
+          sdmmc_getreg32(priv, STM32_SDMMC_MASK_OFFSET)) != 0)
+    {
+      /* Handle in progress, interrupt driven data transfers ****************/
+
+      pending  = enabled & priv->xfrmask;
+      if (pending != 0)
+        {
+#ifndef CONFIG_STM32H7_SDMMC_IDMA
+#ifdef CONFIG_STM32H7_SDMMC_MDMA
+          if (!priv->dmamode)
+#endif
+            {
+              /* Is the RX FIFO half full or more?  Is so then we must be
+               * processing a receive transaction.
+               */
+
+              if ((pending & STM32_SDMMC_STA_RXFIFOHF) != 0)
+                {
+                  /* Receive data from the RX FIFO */
+
+                  stm32_recvfifo(priv);
+                }
+
+              /* Otherwise, Is the transmit FIFO half empty or less?  If so
+               * we must be processing a send transaction.  NOTE:  We can't
+               * be processing both!
+               */
+
+              else if ((pending & STM32_SDMMC_STA_TXFIFOHE) != 0)
+                {
+                  /* Send data via the TX FIFO */
+
+                  stm32_sendfifo(priv);
+                }
+            }
+#endif
+          /* Handle data end events */
+
+          if ((pending & STM32_SDMMC_STA_DATAEND) != 0)
+            {
+              /* Handle any data remaining the RX FIFO.  If the RX FIFO is
+               * less than half full at the end of the transfer, then no
+               * half-full interrupt will be received.
+               */
+
+#ifdef CONFIG_STM32H7_SDMMC_IDMA
+              /* Just end transfer */
+
+              stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
+#else
+#ifdef CONFIG_STM32H7_SDMMC_MDMA
+              /* Was this transfer performed in DMA mode? */
+
+              if (priv->dmamode)
+                {
+                  /* Yes.. Terminate the transfers only if the DMA has also
+                   * finished.
+                   */
+
+                  priv->xfrflags |= SDMMC_XFRDONE_FLAG;
+                  if (priv->xfrflags == SDMMC_ALLDONE)
+                    {
+                      stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
+                    }
+
+                  /* Otherwise, just disable futher transfer interrupts and
+                   * wait for the DMA complete event.
+                   */
+
+                  else
+                    {
+                      stm32_configxfrints(priv, 0);
+                    }
+                }
+             else
+#endif
+                {
+                  /* Receive data from the RX FIFO */
+
+                  stm32_recvfifo(priv);
+
+                  /* Then terminate the transfer */
+
+                  stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
+                }
+#endif
+            }
+
+          /* Handle data block send/receive CRC failure */
+
+          else if ((pending & STM32_SDMMC_STA_DCRCFAIL) != 0)
+            {
+              /* Terminate the transfer with an error */
+
+              mcerr("ERROR: Data block CRC failure, remaining: %d\n",
+                   priv->remaining);
+              stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
+            }
+
+          /* Handle data timeout error */
+
+          else if ((pending & STM32_SDMMC_STA_DTIMEOUT) != 0)
+            {
+              /* Terminate the transfer with an error */
+
+              mcerr("ERROR: Data timeout, remaining: %d\n",
+                    priv->remaining);
+              stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE |
+                                      SDIOWAIT_TIMEOUT);
+            }
+
+          /* Handle RX FIFO overrun error */
+
+          else if ((pending & STM32_SDMMC_STA_RXOVERR) != 0)
+            {
+              /* Terminate the transfer with an error */
+
+              mcerr("ERROR: RX FIFO overrun, remaining: %d\n",
+                    priv->remaining);
+              stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE |
+                                      SDIOWAIT_ERROR);
+            }
+
+          /* Handle TX FIFO underrun error */
+
+          else if ((pending & STM32_SDMMC_STA_TXUNDERR) != 0)
+            {
+              /* Terminate the transfer with an error */
+
+              mcerr("ERROR: TX FIFO underrun, remaining: %d\n",
+                    priv->remaining);
+              stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE |
+                                      SDIOWAIT_ERROR);
+            }
+        }
+
+      /* Handle wait events *************************************************/
+
+      pending  = enabled & priv->waitmask;
+      if (pending != 0)
+        {
+          /* Is this a response completion event? */
+
+          if ((pending & STM32_SDMMC_RESPDONE_STA) != 0)
+            {
+              sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR |
+                             STM32_SDMMC_CMDDONE_ICR, STM32_SDMMC_ICR_OFFSET);
+
+              /* Yes.. Is their a thread waiting for response done? */
+
+              if ((priv->waitevents & SDIOWAIT_RESPONSEDONE) != 0)
+               {
+                 /* Yes.. wake the thread up */
+
+                  stm32_endwait(priv, SDIOWAIT_RESPONSEDONE);
+                }
+            }
+
+          /* Is this a command completion event? */
+
+          if ((pending & STM32_SDMMC_CMDDONE_STA) != 0)
+            {
+              sdmmc_putreg32(priv, STM32_SDMMC_CMDDONE_ICR,
+                             STM32_SDMMC_ICR_OFFSET);
+
+              /* Yes.. Is their a thread waiting for command done? */
+
+              if ((priv->waitevents & SDIOWAIT_RESPONSEDONE) != 0)
+                {
+                  /* Yes.. wake the thread up */
+
+                  stm32_endwait(priv, SDIOWAIT_CMDDONE);
+                }
+            }
+        }
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * SDIO Interface Methods
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_lock
+ *
+ * Description:
+ *   Locks the bus. Function calls low-level multiplexed bus routines to
+ *   resolve bus requests and acknowledgment issues.
+ *
+ * Input Parameters:
+ *   dev    - An instance of the SDIO device interface
+ *   lock   - TRUE to lock, FALSE to unlock.
+ *
+ * Returned Value:
+ *   OK on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SDIO_MUXBUS
+static int stm32_lock(FAR struct sdio_dev_s *dev, bool lock)
+{
+  /* The multiplex bus is part of board support package. */
+
+  stm32_muxbus_sdio_lock(dev, lock);
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_reset
+ *
+ * Description:
+ *   Reset the SDIO controller.  Undo all setup and initialization.
+ *
+ * Input Parameters:
+ *   dev    - An instance of the SDIO device interface
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void stm32_reset(FAR struct sdio_dev_s *dev)
+{
+  FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev;
+  irqstate_t flags;
+
+  /* Disable clocking */
+
+  flags = enter_critical_section();
+
+  uint32_t regval;
+#ifdef CONFIG_STM32H7_SDMMC1
+  regval = getreg32(STM32_RCC_AHB3RSTR);
+  putreg32(regval | RCC_AHB3RSTR_SDMMC1RST, STM32_RCC_AHB3RSTR);
+#elif defined CONFIG_STM32H7_SDMMC2
+  regval = getreg32(STM32_RCC_AHB2RSTR);
+  putreg32(regval | RCC_AHB2RSTR_SDMMC2RST, STM32_RCC_AHB2RSTR);
+#else
+#  error CONFIG_STM32H7_SDMMC1 or CONFIG_STM32H7_SDMMC2 not defined
+#endif
+
+  usleep(2);
+
+#ifdef CONFIG_STM32H7_SDMMC1
+  putreg32(regval & ~RCC_AHB3RSTR_SDMMC1RST, STM32_RCC_AHB3RSTR);
+#elif defined CONFIG_STM32H7_SDMMC2
+  putreg32(regval & ~RCC_AHB2RSTR_SDMMC2RST, STM32_RCC_AHB2RSTR);
+#endif
+
+  stm32_setpwrctrl(priv, STM32_SDMMC_POWER_PWRCTRL_CYCLE);
+  usleep(1000);
+
+  /* Put SDIO registers in their default, reset state */
+
+  stm32_default(priv);
+
+  /* Reset data */
+
+  priv->waitevents = 0;      /* Set of events to be waited for */
+  priv->waitmask   = 0;      /* Interrupt enables for event waiting */
+  priv->wkupevent  = 0;      /* The event that caused the wakeup */
+#ifdef CONFIG_STM32H7_SDMMC_MDMA
+  priv->xfrflags   = 0;      /* Used to synchronize SDIO and DMA
+                              * completion events */
+#endif
+
+  wd_cancel(priv->waitwdog); /* Cancel any timeouts */
+
+  /* Interrupt mode data transfer support */
+
+  priv->buffer     = 0;      /* Address of current R/W buffer */
+  priv->remaining  = 0;      /* Number of bytes remaining in the transfer */
+  priv->xfrmask    = 0;      /* Interrupt enables for data transfer */
+
+  priv->widebus    = false;
+
+#ifdef CONFIG_STM32H7_SDMMC_MDMA
+  /* MDMA data transfer support */
+
+  priv->dmamode    = false;  /* true: DMA mode transfer */
+#endif
+
+  /* Configure the SDIO peripheral */
+
+  stm32_setpwrctrl(priv, STM32_SDMMC_POWER_PWRCTRL_OFF);
+  usleep(1000);
+  stm32_setpwrctrl(priv, STM32_SDMMC_POWER_PWRCTRL_ON);
+
+  stm32_setclkcr(priv, STM32_CLCKCR_INIT);
+
+  leave_critical_section(flags);
+
+  mcinfo("CLCKR: %08x POWER: %08x\n",
+         sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET),
+         sdmmc_getreg32(priv, STM32_SDMMC_POWER_OFFSET));
+}
+
+/****************************************************************************
+ * Name: stm32_capabilities
+ *
+ * Description:
+ *   Get capabilities (and limitations) of the SDIO driver (optional)
+ *
+ * Input Parameters:
+ *   dev   - Device-specific state data
+ *
+ * Returned Value:
+ *   Returns a bitset of status values (see SDIO_CAPS_* defines)
+ *
+ ****************************************************************************/
+
+static sdio_capset_t stm32_capabilities(FAR struct sdio_dev_s *dev)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  sdio_capset_t caps = 0;
+
+  if (priv->onebit)
+    {
+      caps |= SDIO_CAPS_1BIT_ONLY;
+    }
+
+  caps |= SDIO_CAPS_DMABEFOREWRITE;
+
+#ifdef CONFIG_STM32H7_SDMMC_MDMA
+  caps |= SDIO_CAPS_DMASUPPORTED;
+#endif
+
+  return caps;
+}
+
+/****************************************************************************
+ * Name: stm32_status
+ *
+ * Description:
+ *   Get SDIO status.
+ *
+ * Input Parameters:
+ *   dev   - Device-specific state data
+ *
+ * Returned Value:
+ *   Returns a bitset of status values (see stm32_status_* defines)
+ *
+ ****************************************************************************/
+
+static sdio_statset_t stm32_status(FAR struct sdio_dev_s *dev)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  return priv->cdstatus;
+}
+
+/****************************************************************************
+ * Name: stm32_widebus
+ *
+ * Description:
+ *   Called after change in Bus width has been selected (via ACMD6).  Most
+ *   controllers will need to perform some special operations to work
+ *   correctly in the new bus mode.
+ *
+ * Input Parameters:
+ *   dev  - An instance of the SDIO device interface
+ *   wide - true: wide bus (4-bit) bus mode enabled
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void stm32_widebus(FAR struct sdio_dev_s *dev, bool wide)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  priv->widebus = wide;
+}
+
+/****************************************************************************
+ * Name: stm32_clock
+ *
+ * Description:
+ *   Enable/disable SDIO clocking
+ *
+ * Input Parameters:
+ *   dev  - An instance of the SDIO device interface
+ *   rate - Specifies the clocking to use (see enum sdio_clock_e)
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  uint32_t clckr;
+
+  switch (rate)
+  {
+    /* Disable clocking (with default ID mode divisor) */
+
+    default:
+    case CLOCK_SDIO_DISABLED:
+      clckr = STM32_CLCKCR_INIT;
+      return;
+
+    /* Enable in initial ID mode clocking (<400KHz) */
+
+    case CLOCK_IDMODE:
+      clckr = (STM32_CLCKCR_INIT);
+      break;
+
+    /* Enable in MMC normal operation clocking */
+
+    case CLOCK_MMC_TRANSFER:
+      clckr = (STM32_SDMMC_CLKCR_MMCXFR);
+      break;
+
+    /* SD normal operation clocking (wide 4-bit mode) */
+
+    case CLOCK_SD_TRANSFER_4BIT:
+      if (!priv->onebit)
+        {
+          clckr = (STM32_SDMMC_CLCKR_SDWIDEXFR);
+          break;
+        }
+
+    /* SD normal operation clocking (narrow 1-bit mode) */
+
+    case CLOCK_SD_TRANSFER_1BIT:
+      clckr = (STM32_SDMMC_CLCKR_SDXFR);
+      break;
+  }
+
+  /* Set the new clock frequency along with the clock enable/disable bit */
+
+  stm32_setclkcr(priv, clckr);
+}
+
+/****************************************************************************
+ * Name: stm32_attach
+ *
+ * Description:
+ *   Attach and prepare interrupts
+ *
+ * Input Parameters:
+ *   dev - An instance of the SDIO device interface
+ *
+ * Returned Value:
+ *   OK on success; A negated errno on failure.
+ *
+ ****************************************************************************/
+
+static int stm32_attach(FAR struct sdio_dev_s *dev)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  int ret;
+
+  /* Attach the SDIO interrupt handler */
+
+  ret = irq_attach(priv->nirq, stm32_sdmmc_interrupt, priv);
+  if (ret == OK)
+    {
+      /* Disable all interrupts at the SDIO controller and clear
+       * interrupt flags
+       */
+
+      sdmmc_putreg32(priv, STM32_SDMMC_MASK_RESET, STM32_SDMMC_MASK_OFFSET);
+      sdmmc_putreg32(priv, STM32_SDMMC_ICR_ALLFLAGS, STM32_SDMMC_ICR_OFFSET);
+
+      /* Enable SDIO interrupts at the NVIC.  They can now be enabled at
+       * the SDIO controller as needed.
+       */
+
+      up_enable_irq(priv->nirq);
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: stm32_sendcmd
+ *
+ * Description:
+ *   Send the SDIO command
+ *
+ * Input Parameters:
+ *   dev  - An instance of the SDIO device interface
+ *   cmd  - The command to send (32-bits, encoded)
+ *   arg  - 32-bit argument required with some commands
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
+                         uint32_t arg)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  uint32_t regval;
+  uint32_t cmdidx;
+
+  /* Clear CMDINDEX, CMDTRANS, WAITRESP, WAITINT, WAITPEND, and CPSMEN bits */
+
+  regval = sdmmc_getreg32(priv, STM32_SDMMC_CMD_OFFSET);
+
+  /* Make sure the register is clear */
+
+  if (regval & STM32_SDMMC_CMD_CPSMEN)
+    sdmmc_putreg32(priv, STM32_SDMMC_CMD_OFFSET, 0);
+
+  regval &= ~(STM32_SDMMC_CMD_CMDINDEX_MASK | STM32_SDMMC_CMD_CMDTRANS |
+              STM32_SDMMC_CMD_WAITRESP_MASK | STM32_SDMMC_CMD_WAITINT |
+              STM32_SDMMC_CMD_WAITPEND | STM32_SDMMC_CMD_CPSMEN);
+
+  /* Set WAITRESP bits */
+
+  switch (cmd & MMCSD_RESPONSE_MASK)
+    {
+      case MMCSD_NO_RESPONSE:
+        regval |= STM32_SDMMC_CMD_NORESPONSE;
+        break;
+
+      case MMCSD_R1_RESPONSE:
+      case MMCSD_R1B_RESPONSE:
+      case MMCSD_R3_RESPONSE:
+      case MMCSD_R4_RESPONSE:
+      case MMCSD_R5_RESPONSE:
+      case MMCSD_R6_RESPONSE:
+      case MMCSD_R7_RESPONSE:
+        regval |= STM32_SDMMC_CMD_SHORTRESPONSE;
+        break;
+
+      case MMCSD_R2_RESPONSE:
+        regval |= STM32_SDMMC_CMD_LONGRESPONSE;
+        break;
+    }
+
+  /* Set CPSMEN and the command index */
+
+  cmdidx  = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT;
+  regval |= cmdidx | STM32_SDMMC_CMD_CPSMEN;
+
+  /* Clear interrupts */
+
+  uint32_t icr_mask = STM32_SDMMC_CMDDONE_ICR | STM32_SDMMC_RESPDONE_ICR;
+  sdmmc_putreg32(priv, icr_mask, STM32_SDMMC_ICR_OFFSET);
+
+  if (cmd & MMCSD_DATAXFR_MASK)
+    {
+      regval |= STM32_SDMMC_CMD_CMDTRANS;
+
+      /* Enable receive/send interrupts */
+
+      if (priv->receive)
+        {
+          stm32_configxfrints(priv, STM32_SDMMC_RECV_MASK);
+        }
+      else
+        {
+          stm32_configxfrints(priv, STM32_SDMMC_SEND_MASK);
+        }
+    }
+
+  mcinfo("cmd: %08x arg: %08x regval: %08x enabled irq: %08x\n",
+         cmd, arg, regval, sdmmc_getreg32(priv, STM32_SDMMC_MASK_OFFSET));
+
+  /* Set the SDIO Argument value */
+
+  sdmmc_putreg32(priv, arg, STM32_SDMMC_ARG_OFFSET);
+
+  /* Write the SDIO CMD */
+
+  sdmmc_putreg32(priv, regval, STM32_SDMMC_CMD_OFFSET);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32_recvsetup
+ *
+ * Description:
+ *   Setup hardware in preparation for data transfer from the card in non-DMA
+ *   (interrupt driven mode).  This method will do whatever controller setup
+ *   is necessary.  This would be called for SD memory just BEFORE sending
+ *   CMD13 (SEND_STATUS), CMD17 (READ_SINGLE_BLOCK), CMD18
+ *   (READ_MULTIPLE_BLOCKS), ACMD51 (SEND_SCR), etc.  Normally,
+ *   SDMMC_WAITEVENT will be called to receive the indication that the
+ *   transfer is complete.
+ *
+ * Input Parameters:
+ *   dev    - An instance of the SDIO device interface
+ *   buffer - Address of the buffer in which to receive the data
+ *   nbytes - The number of bytes in the transfer
+ *
+ * Returned Value:
+ *   Number of bytes sent on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
+                           size_t nbytes)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  uint32_t dblocksize;
+
+  DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0);
+  DEBUGASSERT(((uint32_t)buffer & 3) == 0);
+
+  /* Reset the DPSM configuration */
+
+  stm32_datadisable(priv);
+  stm32_sampleinit();
+  stm32_sample(priv, SAMPLENDX_BEFORE_SETUP);
+
+  /* Save the destination buffer information for use by the interrupt
+   * handler
+   */
+
+  priv->buffer    = (uint32_t *)buffer;
+  priv->remaining = nbytes;
+#ifdef CONFIG_STM32H7_SDMMC_MDMA
+  priv->dmamode   = false;
+#endif
+  priv->receive   = true;
+
+  /* Then set up the SDIO data path */
+
+  dblocksize = stm32_log2(nbytes) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
+  stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT, nbytes, dblocksize |
+                   STM32_SDMMC_DCTRL_DTDIR);
+
+  stm32_sample(priv, SAMPLENDX_AFTER_SETUP);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32_sendsetup
+ *
+ * Description:
+ *   Setup hardware in preparation for data transfer from the card.  This
+ *   method will do whatever controller setup is necessary.  This would be
+ *   called for SD memory just AFTER sending CMD24 (WRITE_BLOCK), CMD25
+ *   (WRITE_MULTIPLE_BLOCK), ... and before SDMMC_SENDDATA is called.
+ *
+ * Input Parameters:
+ *   dev    - An instance of the SDIO device interface
+ *   buffer - Address of the buffer containing the data to send
+ *   nbytes - The number of bytes in the transfer
+ *
+ * Returned Value:
+ *   Number of bytes sent on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const
+                           uint8_t *buffer, size_t nbytes)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  uint32_t dblocksize;
+
+  DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0);
+  DEBUGASSERT(((uint32_t)buffer & 3) == 0);
+
+  /* Reset the DPSM configuration */
+
+  stm32_datadisable(priv);
+  stm32_sampleinit();
+  stm32_sample(priv, SAMPLENDX_BEFORE_SETUP);
+
+  /* Save the source buffer information for use by the interrupt handler */
+
+  priv->buffer    = (uint32_t *)buffer;
+  priv->remaining = nbytes;
+#ifdef CONFIG_STM32H7_SDMMC_MDMA
+  priv->dmamode   = false;
+#endif
+  priv->receive   = false;
+
+  /* Then set up the SDIO data path */
+
+  dblocksize = stm32_log2(nbytes) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
+  stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT, nbytes,
+                   dblocksize);
+
+  /* Flush dcache if enabled */
+
+  up_clean_dcache((uintptr_t)priv->buffer, (uintptr_t)priv->buffer + nbytes);
+
+  stm32_sample(priv, SAMPLENDX_AFTER_SETUP);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32_cancel
+ *
+ * Description:
+ *   Cancel the data transfer setup of SDMMC_RECVSETUP, SDMMC_SENDSETUP,
+ *   SDMMC_DMARECVSETUP or SDMMC_DMASENDSETUP.  This must be called to cancel
+ *   the data transfer setup if, for some reason, you cannot perform the
+ *   transfer.
+ *
+ * Input Parameters:
+ *   dev  - An instance of the SDIO device interface
+ *
+ * Returned Value:
+ *   OK is success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+static int stm32_cancel(FAR struct sdio_dev_s *dev)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+
+  /* Disable all transfer- and event- related interrupts */
+
+  stm32_configxfrints(priv, 0);
+  stm32_configwaitints(priv, 0, 0, 0);
+
+  /* Send a stop command to DPSM */
+
+  stm32_sendcmd(dev, STM32_SDMMC_CMD_CMDSTOP, 0);
+
+  /* If this was a DMA transfer, make sure that DMA is stopped */
+
+  sdmmc_putreg32(priv, 0, STM32_SDMMC_IDMACTRLR_OFFSET);
+
+  /* Clearing pending interrupt status on all transfer- and event- related
+   * interrupts
+   */
+
+  sdmmc_putreg32(priv, STM32_SDMMC_WAITALL_ICR, STM32_SDMMC_ICR_OFFSET);
+
+  /* Cancel any watchdog timeout */
+
+  (void)wd_cancel(priv->waitwdog);
+
+  /* Mark no transfer in progress */
+
+  priv->remaining = 0;
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32_waitresponse
+ *
+ * Description:
+ *   Poll-wait for the response to the last command to be ready.
+ *
+ * Input Parameters:
+ *   dev  - An instance of the SDIO device interface
+ *   cmd  - The command that was sent.  See 32-bit command definitions above.
+ *
+ * Returned Value:
+ *   OK is success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  int32_t timeout = SDMMC_CMDTIMEOUT;
+  uint32_t events;
+
+  switch (cmd & MMCSD_RESPONSE_MASK)
+    {
+      case MMCSD_NO_RESPONSE:
+        events  = STM32_SDMMC_CMDDONE_STA;
+        timeout = SDMMC_CMDTIMEOUT;
+        break;
+
+      case MMCSD_R1_RESPONSE:
+      case MMCSD_R1B_RESPONSE:
+      case MMCSD_R2_RESPONSE:
+      case MMCSD_R6_RESPONSE:
+        events  = STM32_SDMMC_RESPDONE_STA;
+        timeout = SDMMC_LONGTIMEOUT;
+        break;
+
+      case MMCSD_R4_RESPONSE:
+      case MMCSD_R5_RESPONSE:
+        return -ENOSYS;
+
+      case MMCSD_R3_RESPONSE:
+      case MMCSD_R7_RESPONSE:
+        events  = STM32_SDMMC_RESPDONE_STA;
+        timeout = SDMMC_CMDTIMEOUT;
+        break;
+
+      default:
+        return -EINVAL;
+    }
+
+  /* Then wait for the response (or timeout) */
+
+  while ((sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET) & events) == 0)
+    {
+      if (--timeout <= 0)
+        {
+          mcerr("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n",
+                cmd, events, sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET));
+
+          return -ETIMEDOUT;
+        }
+    }
+
+  sdmmc_putreg32(priv, STM32_SDMMC_CMDDONE_ICR, STM32_SDMMC_ICR_OFFSET);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32_recvRx
+ *
+ * Description:
+ *   Receive response to SDIO command.  Only the critical payload is
+ *   returned -- that is 32 bits for 48 bit status and 128 bits for 136 bit
+ *   status.  The driver implementation should verify the correctness of
+ *   the remaining, non-returned bits (CRCs, CMD index, etc.).
+ *
+ * Input Parameters:
+ *   dev    - An instance of the SDIO device interface
+ *   Rx - Buffer in which to receive the response
+ *
+ * Returned Value:
+ *   Number of bytes sent on success; a negated errno on failure.  Here a
+ *   failure means only a faiure to obtain the requested response (due to
+ *   transport problem -- timeout, CRC, etc.).  The implementation only
+ *   assures that the response is returned intact and does not check errors
+ *   within the response itself.
+ *
+ ****************************************************************************/
+
+static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
+                              uint32_t *rshort)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+#ifdef CONFIG_DEBUG_FEATURES
+  uint32_t respcmd;
+#endif
+  uint32_t regval;
+  int ret = OK;
+
+  /* R1  Command response (48-bit)
+   *     47        0               Start bit
+   *     46        0               Transmission bit (0=from card)
+   *     45:40     bit5   - bit0   Command index (0-63)
+   *     39:8      bit31  - bit0   32-bit card status
+   *     7:1       bit6   - bit0   CRC7
+   *     0         1               End bit
+   *
+   * R1b Identical to R1 with the additional busy signaling via the data
+   *     line.
+   *
+   * R6  Published RCA Response (48-bit, SD card only)
+   *     47        0               Start bit
+   *     46        0               Transmission bit (0=from card)
+   *     45:40     bit5   - bit0   Command index (0-63)
+   *     39:8      bit31  - bit0   32-bit Argument Field, consisting of:
+   *                               [31:16] New published RCA of card
+   *                               [15:0]  Card status bits {23,22,19,12:0}
+   *     7:1       bit6   - bit0   CRC7
+   *     0         1               End bit
+   */
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!rshort)
+    {
+      mcerr("ERROR: rshort=NULL\n");
+      ret = -EINVAL;
+    }
+
+  /* Check that this is the correct response to this command */
+
+  else if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1_RESPONSE &&
+           (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE &&
+           (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE)
+    {
+      mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
+      ret = -EINVAL;
+    }
+  else
+#endif
+    {
+      /* Check if a timeout or CRC error occurred */
+
+      regval = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET);
+      if ((regval & STM32_SDMMC_STA_CTIMEOUT) != 0)
+        {
+          mcerr("ERROR: Command timeout: %08x\n", regval);
+          ret = -ETIMEDOUT;
+        }
+      else if ((regval & STM32_SDMMC_STA_CCRCFAIL) != 0)
+        {
+          mcerr("ERROR: CRC failure: %08x\n", regval);
+          ret = -EIO;
+        }
+#ifdef CONFIG_DEBUG_FEATURES
+    else
+        {
+          /* Check response received is of desired command */
+
+          respcmd = sdmmc_getreg32(priv, STM32_SDMMC_RESPCMD_OFFSET);
+          if ((uint8_t)(respcmd & STM32_SDMMC_RESPCMD_MASK) !=
+              (cmd & MMCSD_CMDIDX_MASK))
+            {
+              mcerr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd);
+              ret = -EINVAL;
+            }
+        }
+#endif
+    }
+
+  /* Clear all pending message completion events and return the R1/R6 response */
+
+  sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR | STM32_SDMMC_CMDDONE_ICR,
+                 STM32_SDMMC_ICR_OFFSET);
+  *rshort = sdmmc_getreg32(priv, STM32_SDMMC_RESP1_OFFSET);
+  return ret;
+}
+
+static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd,
+                          uint32_t rlong[4])
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  uint32_t regval;
+  int ret = OK;
+
+  /* R2  CID, CSD register (136-bit)
+   *     135       0               Start bit
+   *     134       0               Transmission bit (0=from card)
+   *     133:128   bit5   - bit0   Reserved
+   *     127:1     bit127 - bit1   127-bit CID or CSD register
+   *                               (including internal CRC)
+   *     0         1               End bit
+   */
+
+#ifdef CONFIG_DEBUG_FEATURES
+  /* Check that R1 is the correct response to this command */
+
+  if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE)
+    {
+      mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
+      ret = -EINVAL;
+    }
+  else
+#endif
+    {
+      /* Check if a timeout or CRC error occurred */
+
+      regval = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET);
+      if (regval & STM32_SDMMC_STA_CTIMEOUT)
+        {
+          mcerr("ERROR: Timeout STA: %08x\n", regval);
+          ret = -ETIMEDOUT;
+        }
+      else if (regval & STM32_SDMMC_STA_CCRCFAIL)
+        {
+          mcerr("ERROR: CRC fail STA: %08x\n", regval);
+          ret = -EIO;
+        }
+    }
+
+  /* Return the long response */
+
+  sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR | STM32_SDMMC_CMDDONE_ICR,
+                 STM32_SDMMC_ICR_OFFSET);
+  if (rlong)
+    {
+      rlong[0] = sdmmc_getreg32(priv, STM32_SDMMC_RESP1_OFFSET);
+      rlong[1] = sdmmc_getreg32(priv, STM32_SDMMC_RESP2_OFFSET);
+      rlong[2] = sdmmc_getreg32(priv, STM32_SDMMC_RESP3_OFFSET);
+      rlong[3] = sdmmc_getreg32(priv, STM32_SDMMC_RESP4_OFFSET);
+    }
+
+  return ret;
+}
+
+static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd,
+                           uint32_t *rshort)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  uint32_t regval;
+  int ret = OK;
+
+  /* R3  OCR (48-bit)
+   *     47        0               Start bit
+   *     46        0               Transmission bit (0=from card)
+   *     45:40     bit5   - bit0   Reserved
+   *     39:8      bit31  - bit0   32-bit OCR register
+   *     7:1       bit6   - bit0   Reserved
+   *     0         1               End bit
+   */
+
+  /* Check that this is the correct response to this command */
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE &&
+      (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
+    {
+      mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
+      ret = -EINVAL;
+    }
+  else
+#endif
+    {
+      /* Check if a timeout occurred (Apparently a CRC error can terminate
+       * a good response)
+       */
+
+      regval = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET);
+      if (regval & STM32_SDMMC_STA_CTIMEOUT)
+        {
+          mcerr("ERROR: Timeout STA: %08x\n", regval);
+          ret = -ETIMEDOUT;
+        }
+    }
+
+  sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR | STM32_SDMMC_CMDDONE_ICR,
+                 STM32_SDMMC_ICR_OFFSET);
+  if (rshort)
+    {
+      *rshort = sdmmc_getreg32(priv, STM32_SDMMC_RESP1_OFFSET);
+    }
+
+  return ret;
+}
+
+/* MMC responses not supported */
+
+static int stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd,
+                             uint32_t *rnotimpl)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR | STM32_SDMMC_CMDDONE_ICR,
+                 STM32_SDMMC_ICR_OFFSET);
+  return -ENOSYS;
+}
+
+/****************************************************************************
+ * Name: stm32_waitenable
+ *
+ * Description:
+ *   Enable/disable of a set of SDIO wait events.  This is part of the
+ *   the SDMMC_WAITEVENT sequence.  The set of to-be-waited-for events is
+ *   configured before calling stm32_eventwait.  This is done in this way
+ *   to help the driver to eliminate race conditions between the command
+ *   setup and the subsequent events.
+ *
+ *   The enabled events persist until either (1) SDMMC_WAITENABLE is called
+ *   again specifying a different set of wait events, or (2) SDMMC_EVENTWAIT
+ *   returns.
+ *
+ * Input Parameters:
+ *   dev      - An instance of the SDIO device interface
+ *   eventset - A bitset of events to enable or disable (see SDIOWAIT_*
+ *              definitions). 0=disable; 1=enable.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void stm32_waitenable(FAR struct sdio_dev_s *dev,
+                             sdio_eventset_t eventset)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  uint32_t waitmask;
+
+  DEBUGASSERT(priv != NULL);
+
+  /* Disable event-related interrupts */
+
+  stm32_configwaitints(priv, 0, 0, 0);
+
+  /* Select the interrupt mask that will give us the appropriate wakeup
+   * interrupts.
+   */
+
+#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE)
+  if ((eventset & SDIOWAIT_WRCOMPLETE) != 0)
+    {
+      waitmask = SDIOWAIT_WRCOMPLETE;
+    }
+  else
+#endif
+    {
+      waitmask = 0;
+      if ((eventset & SDIOWAIT_CMDDONE) != 0)
+        {
+          waitmask |= STM32_SDMMC_CMDDONE_MASK;
+        }
+
+      if ((eventset & SDIOWAIT_RESPONSEDONE) != 0)
+        {
+          waitmask |= STM32_SDMMC_RESPDONE_MASK;
+        }
+
+      if ((eventset & SDIOWAIT_TRANSFERDONE) != 0)
+        {
+          waitmask |= STM32_SDMMC_XFRDONE_MASK;
+        }
+
+      /* Enable event-related interrupts */
+
+      sdmmc_putreg32(priv, STM32_SDMMC_WAITALL_ICR, STM32_SDMMC_ICR_OFFSET);
+    }
+
+  stm32_configwaitints(priv, waitmask, eventset, 0);
+}
+
+/****************************************************************************
+ * Name: stm32_eventwait
+ *
+ * Description:
+ *   Wait for one of the enabled events to occur (or a timeout).  Note that
+ *   all events enabled by SDMMC_WAITEVENTS are disabled when stm32_eventwait
+ *   returns.  SDMMC_WAITEVENTS must be called again before stm32_eventwait
+ *   can be used again.
+ *
+ * Input Parameters:
+ *   dev     - An instance of the SDIO device interface
+ *   timeout - Maximum time in milliseconds to wait.  Zero means immediate
+ *             timeout with no wait.  The timeout value is ignored if
+ *             SDIOWAIT_TIMEOUT is not included in the waited-for eventset.
+ *
+ * Returned Value:
+ *   Event set containing the event(s) that ended the wait.  Should always
+ *   be non-zero.  All events are disabled after the wait concludes.
+ *
+ ****************************************************************************/
+
+static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
+                                       uint32_t timeout)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  sdio_eventset_t wkupevent = 0;
+  irqstate_t flags;
+  int ret;
+
+  /* There is a race condition here... the event may have completed before
+   * we get here.  In this case waitevents will be zero, but wkupevents will
+   * be non-zero (and, hopefully, the semaphore count will also be non-zero.
+   */
+
+  flags = enter_critical_section();
+  DEBUGASSERT(priv->waitevents != 0 || priv->wkupevent != 0);
+
+  /* Check if the timeout event is specified in the event set */
+
+  if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0)
+    {
+      int delay;
+
+      /* Yes.. Handle a cornercase: The user request a timeout event but
+       * with timeout == 0?
+       */
+
+      if (!timeout)
+        {
+          /* Then just tell the caller that we already timed out */
+
+          wkupevent = SDIOWAIT_TIMEOUT;
+          goto errout;
+        }
+
+      /* Start the watchdog timer */
+
+      delay = MSEC2TICK(timeout);
+      ret   = wd_start(priv->waitwdog, delay, (wdentry_t)stm32_eventtimeout,
+                       1, (uint32_t)priv);
+      if (ret != OK)
+        {
+          mcerr("ERROR: wd_start failed: %d\n", ret);
+        }
+    }
+
+#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE)
+  if ((priv->waitevents & SDIOWAIT_WRCOMPLETE) != 0)
+    {
+      /* Atomically read pin to see if ready (true) and determine if ISR fired
+       * If Pin is ready and if ISR did NOT fire end the wait here
+       */
+
+      if (stm32_gpioread(priv->d0_gpio) &&
+          (priv->wkupevent & SDIOWAIT_WRCOMPLETE) == 0)
+        {
+          stm32_endwait(priv, SDIOWAIT_WRCOMPLETE);
+        }
+    }
+#endif
+
+  /* Loop until the event (or the timeout occurs). Race conditions are avoided
+   * by calling stm32_waitenable prior to triggering the logic that will cause
+   * the wait to terminate.  Under certain race conditions, the waited-for
+   * may have already occurred before this function was called!
+   */
+
+  for (; ; )
+    {
+      /* Wait for an event in event set to occur.  If this the event has already
+       * occurred, then the semaphore will already have been incremented and
+       * there will be no wait.
+       */
+
+      stm32_takesem(priv);
+      wkupevent = priv->wkupevent;
+
+      /* Check if the event has occurred.  When the event has occurred, then
+       * evenset will be set to 0 and wkupevent will be set to a nonzero value.
+       */
+
+      if (wkupevent != 0)
+        {
+          /* Yes... break out of the loop with wkupevent non-zero */
+
+          break;
+        }
+    }
+
+  /* Disable event-related interrupts */
+
+  stm32_configwaitints(priv, 0, 0, 0);
+#ifdef CONFIG_STM32H7_SDMMC_MDMA
+  priv->xfrflags   = 0;
+#endif
+
+errout:
+  leave_critical_section(flags);
+  stm32_dumpsamples(priv);
+  return wkupevent;
+}
+
+/****************************************************************************
+ * Name: stm32_callbackenable
+ *
+ * Description:
+ *   Enable/disable of a set of SDIO callback events.  This is part of the
+ *   the SDIO callback sequence.  The set of events is configured to enabled
+ *   callbacks to the function provided in stm32_registercallback.
+ *
+ *   Events are automatically disabled once the callback is performed and no
+ *   further callback events will occur until they are again enabled by
+ *   calling this methos.
+ *
+ * Input Parameters:
+ *   dev      - An instance of the SDIO device interface
+ *   eventset - A bitset of events to enable or disable (see SDIOMEDIA_*
+ *              definitions). 0=disable; 1=enable.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static void stm32_callbackenable(FAR struct sdio_dev_s *dev,
+                                 sdio_eventset_t eventset)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+
+  mcinfo("eventset: %02x\n", eventset);
+  DEBUGASSERT(priv != NULL);
+
+  priv->cbevents = eventset;
+  stm32_callback(priv);
+}
+
+/****************************************************************************
+ * Name: stm32_registercallback
+ *
+ * Description:
+ *   Register a callback that that will be invoked on any media status
+ *   change.  Callbacks should not be made from interrupt handlers, rather
+ *   interrupt level events should be handled by calling back on the work
+ *   thread.
+ *
+ *   When this method is called, all callbacks should be disabled until they
+ *   are enabled via a call to SDMMC_CALLBACKENABLE
+ *
+ * Input Parameters:
+ *   dev -      Device-specific state data
+ *   callback - The funtion to call on the media change
+ *   arg -      A caller provided value to return with the callback
+ *
+ * Returned Value:
+ *   0 on success; negated errno on failure.
+ *
+ ****************************************************************************/
+
+static int stm32_registercallback(FAR struct sdio_dev_s *dev,
+                                  worker_t callback, void *arg)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+
+  /* Disable callbacks and register this callback and is argument */
+
+  mcinfo("Register %p(%p)\n", callback, arg);
+  DEBUGASSERT(priv != NULL);
+
+  priv->cbevents = 0;
+  priv->cbarg    = arg;
+  priv->callback = callback;
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32_dmapreflight
+ *
+ * Description:
+ *   Preflight an SDIO DMA operation.  If the buffer is not well-formed for
+ *   SDIO DMA transfer (alignment, size, etc.) returns an error.
+ *
+ * Input Parameters:
+ *   dev    - An instance of the SDIO device interface
+ *   buffer - The memory to DMA to/from
+ *   buflen - The size of the DMA transfer in bytes
+ *
+ * Returned Value:
+ *   OK on success; a negated errno on failure
+ ****************************************************************************/
+
+#if defined(CONFIG_STM32H7_SDMMC_DMA) && defined(CONFIG_SDIO_PREFLIGHT)
+static int stm32_dmapreflight(FAR struct sdio_dev_s *dev,
+                              FAR const uint8_t *buffer, size_t buflen)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+
+  DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
+
+  /* DMA must be possible to the buffer */
+  /* TODO */
+
+  if (1)
+    {
+      return -EFAULT;
+    }
+
+  return 0;
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_callback
+ *
+ * Description:
+ *   Perform callback.
+ *
+ * Assumptions:
+ *   This function does not execute in the context of an interrupt handler.
+ *   It may be invoked on any user thread or scheduled on the work thread
+ *   from an interrupt handler.
+ *
+ ****************************************************************************/
+
+static void stm32_callback(void *arg)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)arg;
+
+  /* Is a callback registered? */
+
+  DEBUGASSERT(priv != NULL);
+  mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
+         priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
+
+  if (priv->callback)
+    {
+      /* Yes.. Check for enabled callback events */
+
+      if ((priv->cdstatus & SDIO_STATUS_PRESENT) != 0)
+        {
+          /* Media is present.  Is the media inserted event enabled? */
+
+          if ((priv->cbevents & SDIOMEDIA_INSERTED) == 0)
+            {
+              /* No... return without performing the callback */
+
+              return;
+            }
+        }
+      else
+        {
+          /* Media is not present.  Is the media eject event enabled? */
+
+          if ((priv->cbevents & SDIOMEDIA_EJECTED) == 0)
+            {
+              /* No... return without performing the callback */
+
+              return;
+            }
+        }
+
+      /* Perform the callback, disabling further callbacks.  Of course, the
+       * the callback can (and probably should) re-enable callbacks.
+       */
+
+      priv->cbevents = 0;
+
+      /* Callbacks cannot be performed in the context of an interrupt handler.
+       * If we are in an interrupt handler, then queue the callback to be
+       * performed later on the work thread.
+       */
+
+      if (up_interrupt_context())
+        {
+          /* Yes.. queue it */
+
+          mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
+          (void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback,
+                           priv->cbarg, 0);
+        }
+      else
+        {
+          /* No.. then just call the callback here */
+
+          mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg);
+          priv->callback(priv->cbarg);
+        }
+    }
+}
+
+/****************************************************************************
+ * Name: stm32_default
+ *
+ * Description:
+ *   Restore SDIO registers to their default, reset values
+ *
+ ****************************************************************************/
+
+static void stm32_default(struct stm32_dev_s *priv)
+{
+  sdmmc_putreg32(priv, STM32_SDMMC_POWER_RESET,  STM32_SDMMC_POWER_OFFSET);
+  sdmmc_putreg32(priv, STM32_SDMMC_CLKCR_RESET,  STM32_SDMMC_CLKCR_OFFSET);
+  sdmmc_putreg32(priv, STM32_SDMMC_ARG_RESET,    STM32_SDMMC_ARG_OFFSET);
+  sdmmc_putreg32(priv, STM32_SDMMC_CMD_RESET,    STM32_SDMMC_CMD_OFFSET);
+  sdmmc_putreg32(priv, STM32_SDMMC_DTIMER_RESET, STM32_SDMMC_DTIMER_OFFSET);
+  sdmmc_putreg32(priv, STM32_SDMMC_DLEN_RESET,   STM32_SDMMC_DLEN_OFFSET);
+  sdmmc_putreg32(priv, STM32_SDMMC_DCTRL_RESET,  STM32_SDMMC_DCTRL_OFFSET);
+  sdmmc_putreg32(priv, STM32_SDMMC_ICR_RESET,    STM32_SDMMC_ICR_OFFSET);
+  sdmmc_putreg32(priv, STM32_SDMMC_MASK_RESET,   STM32_SDMMC_MASK_OFFSET);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sdio_initialize
+ *
+ * Description:
+ *   Initialize SDIO for operation.
+ *
+ * Input Parameters:
+ *   slotno - Not used.
+ *
+ * Returned Values:
+ *   A reference to an SDIO interface structure.  NULL is returned on
+ *   failures.
+ *
+ ****************************************************************************/
+
+FAR struct sdio_dev_s *sdio_initialize(int slotno)
+{
+  struct stm32_dev_s *priv = NULL;
+#ifdef CONFIG_STM32H7_SDMMC_MDMA
+  unsigned int dmachan;
+#endif
+
+#ifdef CONFIG_STM32H7_SDMMC1
+  if (slotno == 0)
+    {
+      /* Select SDMMC 1 */
+
+      priv = &g_sdmmcdev1;
+
+#ifdef CONFIG_STM32H7_SDMMC_MDMA
+      dmachan = SDMMC1_DMACHAN;
+#endif
+
+#ifdef CONFIG_SDMMC1_WIDTH_D1_ONLY
+      priv->onebit = true;
+#else
+      priv->onebit = false;
+#endif
+
+      /* Configure GPIOs for 4-bit, wide-bus operation (the chip is capable
+       * of 8-bit wide bus operation but D4-D7 are not configured).
+       *
+       * If bus is multiplexed then there is a custom bus configuration
+       * utility in the scope of the board support package.
+       */
+
+#ifndef CONFIG_SDIO_MUXBUS
+      stm32_configgpio(GPIO_SDMMC1_D0);
+#ifndef CONFIG_SDMMC1_WIDTH_D1_ONLY
+      stm32_configgpio(GPIO_SDMMC1_D1);
+      stm32_configgpio(GPIO_SDMMC1_D2);
+      stm32_configgpio(GPIO_SDMMC1_D3);
+#endif
+      stm32_configgpio(GPIO_SDMMC1_CK);
+      stm32_configgpio(GPIO_SDMMC1_CMD);
+#endif
+    }
+  else
+#endif
+#ifdef CONFIG_STM32H7_SDMMC2
+  if (slotno == 1)
+    {
+      /* Select SDMMC 2 */
+
+      priv = &g_sdmmcdev2;
+
+#ifdef CONFIG_STM32H7_SDMMC_DMA
+      dmachan = SDMMC2_DMACHAN;
+#endif
+
+#ifdef CONFIG_SDMMC2_WIDTH_D1_ONLY
+      priv->onebit = true;
+#else
+      priv->onebit = false;
+#endif
+
+      /* Configure GPIOs for 4-bit, wide-bus operation (the chip is capable
+       * of 8-bit wide bus operation but D4-D7 are not configured).
+       *
+       * If bus is multiplexed then there is a custom bus configuration
+       * utilityin the scope of the board support package.
+       */
+
+#ifndef CONFIG_SDIO_MUXBUS
+      stm32_configgpio(GPIO_SDMMC2_D0);
+#ifndef CONFIG_SDMMC2_WIDTH_D1_ONLY
+      stm32_configgpio(GPIO_SDMMC2_D1);
+      stm32_configgpio(GPIO_SDMMC2_D2);
+      stm32_configgpio(GPIO_SDMMC2_D3);
+#endif
+      stm32_configgpio(GPIO_SDMMC2_CK);
+      stm32_configgpio(GPIO_SDMMC2_CMD);
+#endif
+    }
+  else
+#endif
+    {
+      mcerr("ERROR: Unsupported SDMMC slot: %d\n", slotno);
+      return NULL;
+    }
+
+  /* Initialize the SDIO slot structure */
+  /* Initialize semaphores */
+
+  nxsem_init(&priv->waitsem, 0, 0);
+
+  /* The waitsem semaphore is used for signaling and, hence, should not have
+   * priority inheritance enabled.
+   */
+
+  nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
+
+  /* Create a watchdog timer */
+
+  priv->waitwdog = wd_create();
+  DEBUGASSERT(priv->waitwdog);
+
+#ifdef CONFIG_STM32H7_SDMMC_MDMA
+  /* Allocate a DMA channel */
+
+  priv->dma = stm32_dmachannel(dmachan);
+  DEBUGASSERT(priv->dma);
+#endif
+
+  /* Reset the card and assure that it is in the initial, unconfigured
+   * state.
+   */
+
+  stm32_reset(&priv->dev);
+  return &priv->dev;
+}
+
+/****************************************************************************
+ * Name: sdio_mediachange
+ *
+ * Description:
+ *   Called by board-specific logic -- possible from an interrupt handler --
+ *   in order to signal to the driver that a card has been inserted or
+ *   removed from the slot
+ *
+ * Input Parameters:
+ *   dev        - An instance of the SDIO driver device state structure.
+ *   cardinslot - true is a card has been detected in the slot; false if a
+ *                card has been removed from the slot.  Only transitions
+ *                (inserted->removed or removed->inserted should be reported)
+ *
+ * Returned Values:
+ *   None
+ *
+ ****************************************************************************/
+
+void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  sdio_statset_t cdstatus;
+  irqstate_t flags;
+
+  /* Update card status */
+
+  flags = enter_critical_section();
+  cdstatus = priv->cdstatus;
+  if (cardinslot)
+    {
+      priv->cdstatus |= SDIO_STATUS_PRESENT;
+    }
+  else
+    {
+      priv->cdstatus &= ~SDIO_STATUS_PRESENT;
+    }
+
+  leave_critical_section(flags);
+
+  mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
+
+  /* Perform any requested callback if the status has changed */
+
+  if (cdstatus != priv->cdstatus)
+    {
+      stm32_callback(priv);
+    }
+}
+
+/****************************************************************************
+ * Name: sdio_wrprotect
+ *
+ * Description:
+ *   Called by board-specific logic to report if the card in the slot is
+ *   mechanically write protected.
+ *
+ * Input Parameters:
+ *   dev       - An instance of the SDIO driver device state structure.
+ *   wrprotect - true is a card is writeprotected.
+ *
+ * Returned Values:
+ *   None
+ *
+ ****************************************************************************/
+
+void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
+{
+  struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
+  irqstate_t flags;
+
+  /* Update card status */
+
+  flags = enter_critical_section();
+  if (wrprotect)
+    {
+      priv->cdstatus |= SDIO_STATUS_WRPROTECTED;
+    }
+  else
+    {
+      priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
+    }
+
+  mcinfo("cdstatus: %02x\n", priv->cdstatus);
+  leave_critical_section(flags);
+}
+
+#endif /* CONFIG_STM32H7_SDMMC1 || CONFIG_STM32H7_SDMMC2 */
diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.h b/arch/arm/src/stm32h7/stm32_sdmmc.h
new file mode 100644
index 00000000000..b295a6a906d
--- /dev/null
+++ b/arch/arm/src/stm32h7/stm32_sdmmc.h
@@ -0,0 +1,128 @@
+/****************************************************************************
+ * arch/arm/src/stm32f7/stm32_sdmmc.h
+ *
+ *   Copyright (C) 2009, 2011, 2016, 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H7_STM32_SDMMC_H
+#define __ARCH_ARM_SRC_STM32H7_STM32_SDMMC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include 
+#include 
+
+#include "chip.h"
+#include "hardware/stm32_sdmmc.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: sdio_initialize
+ *
+ * Description:
+ *   Initialize SDIO for operation.
+ *
+ * Input Parameters:
+ *   slotno - Not used.
+ *
+ * Returned Values:
+ *   A reference to an SDIO interface structure.  NULL is returned on
+ *   failures.
+ *
+ ****************************************************************************/
+
+struct sdio_dev_s; /* See include/nuttx/sdio.h */
+FAR struct sdio_dev_s *sdio_initialize(int slotno);
+
+/****************************************************************************
+ * Name: sdio_mediachange
+ *
+ * Description:
+ *   Called by board-specific logic -- posssible from an interrupt handler --
+ *   in order to signal to the driver that a card has been inserted or
+ *   removed from the slot
+ *
+ * Input Parameters:
+ *   dev        - An instance of the SDIO driver device state structure.
+ *   cardinslot - true is a card has been detected in the slot; false if a
+ *                card has been removed from the slot.  Only transitions
+ *                (inserted->removed or removed->inserted should be reported)
+ *
+ * Returned Values:
+ *   None
+ *
+ ****************************************************************************/
+
+void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
+
+/****************************************************************************
+ * Name: sdio_wrprotect
+ *
+ * Description:
+ *   Called by board-specific logic to report if the card in the slot is
+ *   mechanically write protected.
+ *
+ * Input Parameters:
+ *   dev       - An instance of the SDIO driver device state structure.
+ *   wrprotect - true is a card is writeprotected.
+ *
+ * Returned Values:
+ *   None
+ *
+ ****************************************************************************/
+
+void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_STM32H7_STM32_SDMMC_H */
diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c
index a63beaadee8..09d2c84bc46 100644
--- a/arch/arm/src/stm32h7/stm32_serial.c
+++ b/arch/arm/src/stm32h7/stm32_serial.c
@@ -64,7 +64,7 @@
 
 #include "chip.h"
 #include "stm32_gpio.h"
-#include "chip/stm32_pinmap.h"
+#include "hardware/stm32_pinmap.h"
 #include "stm32_rcc.h"
 #include "stm32_uart.h"
 
diff --git a/arch/arm/src/stm32h7/stm32_spi.h b/arch/arm/src/stm32h7/stm32_spi.h
index c536504c7c5..6d5183010bd 100644
--- a/arch/arm/src/stm32h7/stm32_spi.h
+++ b/arch/arm/src/stm32h7/stm32_spi.h
@@ -47,7 +47,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32_spi.h"
+#include "hardware/stm32_spi.h"
 
 /************************************************************************************
  * Public Functions
diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c
index 6b92bec6fc5..6a2f392b7a5 100644
--- a/arch/arm/src/stm32h7/stm32_start.c
+++ b/arch/arm/src/stm32h7/stm32_start.c
@@ -50,10 +50,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 #include "barriers.h"
-
-#ifdef CONFIG_ARCH_FPU
-#  include "nvic.h"
-#endif
+#include "nvic.h"
 
 #include "stm32_rcc.h"
 #include "stm32_userspace.h"
diff --git a/arch/arm/src/stm32h7/stm32_tim.c b/arch/arm/src/stm32h7/stm32_tim.c
new file mode 100644
index 00000000000..a3e96c29537
--- /dev/null
+++ b/arch/arm/src/stm32h7/stm32_tim.c
@@ -0,0 +1,1482 @@
+/***************************************************************************
+ * arm/arm/src/stm32f7/stm32_tim.c
+ *
+ *   Copyright (C) 2011 Uros Platise. All rights reserved.
+ *   Author: Uros Platise 
+ *
+ * With modifications and updates by:
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *            David Sidrane 
+ *            Jukka Laitinen 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "chip.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "stm32_rcc.h"
+#include "stm32_gpio.h"
+#include "stm32_tim.h"
+
+/***************************************************************************
+ * Private Types
+ ***************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* Timer devices may be used for different purposes.  Such special purposes
+ * include:
+ *
+ * - To generate modulated outputs for such things as motor control.  If
+ *   CONFIG_STM32H7_TIMn is defined then the CONFIG_STM32H7_TIMn_PWM may
+ *   also be defined to indicate that the timer is intended to be used for
+ *   pulsed output modulation.
+ *
+ * - To control periodic ADC input sampling.  If CONFIG_STM32H7_TIMn is
+ *   defined then CONFIG_STM32H7_TIMn_ADC may also be defined to indicate
+ *   that timer "n" is intended to be used for that purpose.
+ *
+ * - To control periodic DAC outputs.  If CONFIG_STM32H7_TIMn is defined
+ *   then CONFIG_STM32H7_TIMn_DAC may also be defined to indicate that
+ *   timer "n" is intended to be used for that purpose.
+ *
+ * - To use a Quadrature Encoder.  If CONFIG_STM32H7_TIMn is defined then
+ *   CONFIG_STM32H7_TIMn_QE may also be defined to indicate that timer "n"
+ *   is intended to be used for that purpose.
+ *
+ * In any of these cases, the timer will not be used by this timer module.
+ */
+
+#if defined(CONFIG_STM32H7_TIM1_PWM) || defined (CONFIG_STM32H7_TIM1_ADC) || \
+    defined(CONFIG_STM32H7_TIM1_DAC) || defined(CONFIG_STM32H7_TIM1_QE)
+#  undef CONFIG_STM32H7_TIM1
+#endif
+
+#if defined(CONFIG_STM32H7_TIM2_PWM) || defined (CONFIG_STM32H7_TIM2_ADC) || \
+    defined(CONFIG_STM32H7_TIM2_DAC) || defined(CONFIG_STM32H7_TIM2_QE)
+#  undef CONFIG_STM32H7_TIM2
+#endif
+
+#if defined(CONFIG_STM32H7_TIM3_PWM) || defined (CONFIG_STM32H7_TIM3_ADC) || \
+    defined(CONFIG_STM32H7_TIM3_DAC) || defined(CONFIG_STM32H7_TIM3_QE)
+#  undef CONFIG_STM32H7_TIM3
+#endif
+
+#if defined(CONFIG_STM32H7_TIM4_PWM) || defined (CONFIG_STM32H7_TIM4_ADC) || \
+    defined(CONFIG_STM32H7_TIM4_DAC) || defined(CONFIG_STM32H7_TIM4_QE)
+#  undef CONFIG_STM32H7_TIM4
+#endif
+
+#if defined(CONFIG_STM32H7_TIM5_PWM) || defined (CONFIG_STM32H7_TIM5_ADC) || \
+    defined(CONFIG_STM32H7_TIM5_DAC) || defined(CONFIG_STM32H7_TIM5_QE)
+#  undef CONFIG_STM32H7_TIM5
+#endif
+
+#if defined(CONFIG_STM32H7_TIM6_PWM) || defined (CONFIG_STM32H7_TIM6_ADC) || \
+    defined(CONFIG_STM32H7_TIM6_DAC) || defined(CONFIG_STM32H7_TIM6_QE)
+#  undef CONFIG_STM32H7_TIM6
+#endif
+
+#if defined(CONFIG_STM32H7_TIM7_PWM) || defined (CONFIG_STM32H7_TIM7_ADC) || \
+    defined(CONFIG_STM32H7_TIM7_DAC) || defined(CONFIG_STM32H7_TIM7_QE)
+#  undef CONFIG_STM32H7_TIM7
+#endif
+
+#if defined(CONFIG_STM32H7_TIM8_PWM) || defined (CONFIG_STM32H7_TIM8_ADC) || \
+    defined(CONFIG_STM32H7_TIM8_DAC) || defined(CONFIG_STM32H7_TIM8_QE)
+#  undef CONFIG_STM32H7_TIM8
+#endif
+
+#if defined(CONFIG_STM32H7_TIM12_PWM) || defined (CONFIG_STM32H7_TIM12_ADC) || \
+    defined(CONFIG_STM32H7_TIM12_DAC) || defined(CONFIG_STM32H7_TIM12_QE)
+#  undef CONFIG_STM32H7_TIM12
+#endif
+
+#if defined(CONFIG_STM32H7_TIM13_PWM) || defined (CONFIG_STM32H7_TIM13_ADC) || \
+    defined(CONFIG_STM32H7_TIM13_DAC) || defined(CONFIG_STM32H7_TIM13_QE)
+#  undef CONFIG_STM32H7_TIM13
+#endif
+
+#if defined(CONFIG_STM32H7_TIM14_PWM) || defined (CONFIG_STM32H7_TIM14_ADC) || \
+    defined(CONFIG_STM32H7_TIM14_DAC) || defined(CONFIG_STM32H7_TIM14_QE)
+#  undef CONFIG_STM32H7_TIM14
+#endif
+
+#if defined(CONFIG_STM32H7_TIM15_PWM) || defined (CONFIG_STM32H7_TIM15_ADC) || \
+    defined(CONFIG_STM32H7_TIM15_DAC) || defined(CONFIG_STM32H7_TIM15_QE)
+#  undef CONFIG_STM32H7_TIM15
+#endif
+
+#if defined(CONFIG_STM32H7_TIM16_PWM) || defined (CONFIG_STM32H7_TIM16_ADC) || \
+    defined(CONFIG_STM32H7_TIM16_DAC) || defined(CONFIG_STM32H7_TIM16_QE)
+#  undef CONFIG_STM32H7_TIM16
+#endif
+
+#if defined(CONFIG_STM32H7_TIM17_PWM) || defined (CONFIG_STM32H7_TIM17_ADC) || \
+    defined(CONFIG_STM32H7_TIM17_DAC) || defined(CONFIG_STM32H7_TIM17_QE)
+#  undef CONFIG_STM32H7_TIM17
+#endif
+
+#if defined(CONFIG_STM32H7_TIM1)
+#  if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\
+      defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)||\
+      defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT)
+#    define HAVE_TIM1_GPIOCONFIG 1
+#  endif
+#endif
+
+#if defined(CONFIG_STM32H7_TIM2)
+#  if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\
+      defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT)
+#    define HAVE_TIM2_GPIOCONFIG 1
+#  endif
+#endif
+
+#if defined(CONFIG_STM32H7_TIM3)
+#  if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\
+      defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT)
+#    define HAVE_TIM3_GPIOCONFIG 1
+#  endif
+#endif
+
+#if defined(CONFIG_STM32H7_TIM4)
+#  if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\
+      defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT)
+#    define HAVE_TIM4_GPIOCONFIG 1
+#  endif
+#endif
+
+#if defined(CONFIG_STM32H7_TIM5)
+#  if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\
+      defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT)
+#    define HAVE_TIM5_GPIOCONFIG 1
+#  endif
+#endif
+
+#if defined(CONFIG_STM32H7_TIM8)
+#  if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\
+      defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\
+      defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT)
+#    define HAVE_TIM8_GPIOCONFIG 1
+#  endif
+#endif
+
+#if defined(CONFIG_STM32H7_TIM12)
+#  if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)
+#    define HAVE_TIM12_GPIOCONFIG 1
+#  endif
+#endif
+
+#if defined(CONFIG_STM32H7_TIM13)
+#  if defined(GPIO_TIM13_CH1OUT)
+#    define HAVE_TIM13_GPIOCONFIG 1
+#  endif
+#endif
+
+#if defined(CONFIG_STM32H7_TIM14)
+#  if defined(GPIO_TIM14_CH1OUT)
+#    define HAVE_TIM14_GPIOCONFIG 1
+#  endif
+#endif
+
+#if defined(CONFIG_STM32H7_TIM15)
+#  if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)
+#    define HAVE_TIM15_GPIOCONFIG 1
+#  endif
+#endif
+
+#if defined(CONFIG_STM32H7_TIM16)
+#  if defined(GPIO_TIM16_CH1OUT)
+#    define HAVE_TIM16_GPIOCONFIG 1
+#  endif
+#endif
+
+#if defined(CONFIG_STM32H7_TIM17)
+#  if defined(GPIO_TIM17_CH1OUT)
+#    define HAVE_TIM17_GPIOCONFIG 1
+#  endif
+#endif
+
+/* This module then only compiles if there are enabled timers that are not
+ * intended for some other purpose.
+ */
+
+#if defined(CONFIG_STM32H7_TIM1)  || defined(CONFIG_STM32H7_TIM2)  || \
+    defined(CONFIG_STM32H7_TIM3)  || defined(CONFIG_STM32H7_TIM4)  || \
+    defined(CONFIG_STM32H7_TIM5)  || defined(CONFIG_STM32H7_TIM6)  || \
+    defined(CONFIG_STM32H7_TIM7)  || defined(CONFIG_STM32H7_TIM8)  || \
+    defined(CONFIG_STM32H7_TIM12) || defined(CONFIG_STM32H7_TIM13) || \
+    defined(CONFIG_STM32H7_TIM14) || defined(CONFIG_STM32H7_TIM15) || \
+    defined(CONFIG_STM32H7_TIM16) || defined(CONFIG_STM32H7_TIM17)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* TIM Device Structure */
+
+struct stm32_tim_priv_s
+{
+  const struct stm32_tim_ops_s *ops;
+  stm32_tim_mode_t        mode;
+  uint32_t                base;   /* TIMn base address */
+};
+
+/****************************************************************************
+ * Private Function prototypes
+ ****************************************************************************/
+
+/* Timer methods */
+
+static int  stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode);
+static int  stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq);
+static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev,
+                                uint32_t period);
+static int  stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
+                                 stm32_tim_channel_t mode);
+static int  stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
+                                 uint32_t compare);
+static int  stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel);
+static int  stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, xcpt_t handler,
+                             void *arg, int source);
+static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source);
+static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source);
+static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct stm32_tim_ops_s stm32_tim_ops =
+{
+  .setmode        = &stm32_tim_setmode,
+  .setclock       = &stm32_tim_setclock,
+  .setperiod      = &stm32_tim_setperiod,
+  .setchannel     = &stm32_tim_setchannel,
+  .setcompare     = &stm32_tim_setcompare,
+  .getcapture     = &stm32_tim_getcapture,
+  .setisr         = &stm32_tim_setisr,
+  .enableint      = &stm32_tim_enableint,
+  .disableint     = &stm32_tim_disableint,
+  .ackint         = &stm32_tim_ackint
+};
+
+#ifdef CONFIG_STM32H7_TIM1
+struct stm32_tim_priv_s stm32_tim1_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM1_BASE,
+};
+#endif
+#ifdef CONFIG_STM32H7_TIM2
+struct stm32_tim_priv_s stm32_tim2_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM2_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32H7_TIM3
+struct stm32_tim_priv_s stm32_tim3_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM3_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32H7_TIM4
+struct stm32_tim_priv_s stm32_tim4_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM4_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32H7_TIM5
+struct stm32_tim_priv_s stm32_tim5_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM5_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32H7_TIM6
+struct stm32_tim_priv_s stm32_tim6_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM6_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32H7_TIM7
+struct stm32_tim_priv_s stm32_tim7_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM7_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32H7_TIM8
+struct stm32_tim_priv_s stm32_tim8_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM8_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32H7_TIM12
+struct stm32_tim_priv_s stm32_tim12_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM12_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32H7_TIM13
+struct stm32_tim_priv_s stm32_tim12_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM13_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32H7_TIM14
+struct stm32_tim_priv_s stm32_tim12_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM14_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32H7_TIM15
+struct stm32_tim_priv_s stm32_tim15_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM15_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32H7_TIM16
+struct stm32_tim_priv_s stm32_tim16_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM16_BASE,
+};
+#endif
+
+#ifdef CONFIG_STM32H7_TIM17
+struct stm32_tim_priv_s stm32_tim17_priv =
+{
+  .ops        = &stm32_tim_ops,
+  .mode       = STM32_TIM_MODE_UNUSED,
+  .base       = STM32_TIM17_BASE,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/* Get a 16-bit register value by offset */
+
+static inline uint16_t stm32_getreg16(FAR struct stm32_tim_dev_s *dev,
+                                      uint8_t offset)
+{
+  return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset);
+}
+
+/* Put a 16-bit register value by offset */
+
+static inline void stm32_putreg16(FAR struct stm32_tim_dev_s *dev,
+                                  uint8_t offset, uint16_t value)
+{
+  putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset);
+}
+
+/* Modify a 16-bit register value by offset */
+
+static inline void stm32_modifyreg16(FAR struct stm32_tim_dev_s *dev,
+                                     uint8_t offset, uint16_t clearbits,
+                                     uint16_t setbits)
+{
+  modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits,
+              setbits);
+}
+
+/* Get a 32-bit register value by offset.  This applies only for the STM32 F4
+ * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5.
+ */
+
+static inline uint32_t stm32_getreg32(FAR struct stm32_tim_dev_s *dev,
+                                      uint8_t offset)
+{
+  return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset);
+}
+
+/* Put a 32-bit register value by offset.  This applies only for the STM32 F4
+ * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5.
+ */
+
+static inline void stm32_putreg32(FAR struct stm32_tim_dev_s *dev,
+                                  uint8_t offset, uint32_t value)
+{
+  putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset);
+}
+
+static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev)
+{
+  uint16_t val = stm32_getreg16(dev, STM32_BTIM_EGR_OFFSET);
+  val |= ATIM_EGR_UG;
+  stm32_putreg16(dev, STM32_BTIM_EGR_OFFSET, val);
+}
+
+static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev)
+{
+  uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET);
+  val |= ATIM_CR1_CEN;
+  stm32_tim_reload_counter(dev);
+  stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
+}
+
+static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev)
+{
+  uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET);
+  val &= ~ATIM_CR1_CEN;
+  stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
+}
+
+/* Reset timer into system default state, but do not affect output/input pins */
+
+static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev)
+{
+  ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED;
+  stm32_tim_disable(dev);
+}
+
+#if defined(HAVE_TIM1_GPIOCONFIG)||defined(HAVE_TIM2_GPIOCONFIG)||\
+    defined(HAVE_TIM3_GPIOCONFIG)||defined(HAVE_TIM4_GPIOCONFIG)||\
+    defined(HAVE_TIM5_GPIOCONFIG)||defined(HAVE_TIM6_GPIOCONFIG)||\
+    defined(HAVE_TIM7_GPIOCONFIG)||defined(HAVE_TIM8_GPIOCONFIG)||\
+    defined(HAVE_TIM12_GPIOCONFIG)||defined(HAVE_TIM13_GPIOCONFIG)||\
+    defined(HAVE_TIM14_GPIOCONFIG)||defined(HAVE_TIM15_GPIOCONFIG)||\
+    defined(HAVE_TIM16_GPIOCONFIG)||defined(HAVE_TIM17_GPIOCONFIG)
+static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode)
+{
+  /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */
+
+  if (mode & STM32_TIM_CH_MODE_MASK)
+    {
+      stm32_configgpio(cfg);
+    }
+  else
+    {
+      stm32_unconfiggpio(cfg);
+    }
+}
+#endif
+
+/****************************************************************************
+ * Basic Functions
+ ****************************************************************************/
+
+static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq)
+{
+  uint32_t freqin;
+  int prescaler;
+
+  DEBUGASSERT(dev != NULL);
+
+  /* Disable Timer? */
+
+  if (freq == 0)
+    {
+      stm32_tim_disable(dev);
+      return 0;
+    }
+
+  /* Get the input clock frequency for this timer.  These vary with
+   * different timer clock sources, MCU-specific timer configuration, and
+   * board-specific clock configuration.  The correct input clock frequency
+   * must be defined in the board.h header file.
+   */
+
+  switch (((struct stm32_tim_priv_s *)dev)->base)
+    {
+#ifdef CONFIG_STM32H7_TIM1
+      case STM32_TIM1_BASE:
+        freqin = STM32_APB2_TIM1_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM2
+      case STM32_TIM2_BASE:
+        freqin = STM32_APB1_TIM2_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM3
+      case STM32_TIM3_BASE:
+        freqin = STM32_APB1_TIM3_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM4
+      case STM32_TIM4_BASE:
+        freqin = STM32_APB1_TIM4_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM5
+      case STM32_TIM5_BASE:
+        freqin = STM32_APB1_TIM5_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM6
+      case STM32_TIM6_BASE:
+        freqin = STM32_APB1_TIM6_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM7
+      case STM32_TIM7_BASE:
+        freqin = STM32_APB1_TIM7_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM8
+      case STM32_TIM8_BASE:
+        freqin = STM32_APB2_TIM8_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM12
+      case STM32_TIM12_BASE:
+        freqin = STM32_APB1_TIM12_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM13
+      case STM32_TIM13_BASE:
+        freqin = STM32_APB1_TIM13_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM14
+      case STM32_TIM14_BASE:
+        freqin = STM32_APB1_TIM14_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM15
+      case STM32_TIM15_BASE:
+        freqin = STM32_APB2_TIM15_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM16
+      case STM32_TIM16_BASE:
+        freqin = STM32_APB2_TIM16_CLKIN;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM17
+      case STM32_TIM17_BASE:
+        freqin = STM32_APB2_TIM17_CLKIN;
+        break;
+#endif
+      default:
+        return -EINVAL;
+    }
+
+  /* Select a pre-scaler value for this timer using the input clock
+   * frequency.
+   */
+
+  prescaler = freqin / freq;
+
+  /* We need to decrement value for '1', but only, if that will not to
+   * cause underflow.
+   */
+
+  if (prescaler > 0)
+    {
+      prescaler--;
+    }
+
+  /* Check for overflow as well. */
+
+  if (prescaler > 0xffff)
+    {
+      prescaler = 0xffff;
+    }
+
+  stm32_putreg16(dev, STM32_BTIM_PSC_OFFSET, prescaler);
+  stm32_tim_enable(dev);
+
+  return prescaler;
+}
+
+static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev,
+                                uint32_t period)
+{
+  DEBUGASSERT(dev != NULL);
+  stm32_putreg32(dev, STM32_BTIM_ARR_OFFSET, period);
+}
+
+static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
+                            xcpt_t handler, void *arg, int source)
+{
+  int vectorno;
+
+  DEBUGASSERT(dev != NULL);
+  DEBUGASSERT(source == 0);
+
+  switch (((struct stm32_tim_priv_s *)dev)->base)
+    {
+#ifdef CONFIG_STM32H7_TIM1
+      case STM32_TIM1_BASE:
+        vectorno = STM32_IRQ_TIM1UP;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM2
+      case STM32_TIM2_BASE:
+        vectorno = STM32_IRQ_TIM2;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM3
+      case STM32_TIM3_BASE:
+        vectorno = STM32_IRQ_TIM3;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM4
+      case STM32_TIM4_BASE:
+        vectorno = STM32_IRQ_TIM4;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM5
+      case STM32_TIM5_BASE:
+        vectorno = STM32_IRQ_TIM5;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM6
+      case STM32_TIM6_BASE:
+        vectorno = STM32_IRQ_TIM6;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM7
+      case STM32_TIM7_BASE:
+        vectorno = STM32_IRQ_TIM7;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM8
+      case STM32_TIM8_BASE:
+        vectorno = STM32_IRQ_TIM8UP;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM12
+      case STM32_TIM12_BASE:
+        vectorno = STM32_IRQ_TIM12;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM13
+      case STM32_TIM13_BASE:
+        vectorno = STM32_IRQ_TIM13;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM14
+      case STM32_TIM14_BASE:
+        vectorno = STM32_IRQ_TIM14;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM15
+      case STM32_TIM15_BASE:
+        vectorno = STM32_IRQ_TIM15;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM16
+      case STM32_TIM16_BASE:
+        vectorno = STM32_IRQ_TIM16;
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM17
+      case STM32_TIM17_BASE:
+        vectorno = STM32_IRQ_TIM17;
+        break;
+#endif
+
+      default:
+        return -EINVAL;
+    }
+
+  /* Disable interrupt when callback is removed */
+
+  if (!handler)
+    {
+      up_disable_irq(vectorno);
+      irq_detach(vectorno);
+      return OK;
+    }
+
+  /* Otherwise set callback and enable interrupt */
+
+  irq_attach(vectorno, handler, arg);
+  up_enable_irq(vectorno);
+
+#ifdef CONFIG_ARCH_IRQPRIO
+  /* Set the interrupt priority */
+
+  up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT);
+#endif
+
+  return OK;
+}
+
+static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source)
+{
+  DEBUGASSERT(dev != NULL);
+  stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, source);
+}
+
+static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source)
+{
+  DEBUGASSERT(dev != NULL);
+  stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, source, 0);
+}
+
+static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source)
+{
+  stm32_putreg16(dev, STM32_BTIM_SR_OFFSET, ~source);
+}
+
+/****************************************************************************
+ * General Functions
+ ****************************************************************************/
+
+static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev,
+                             stm32_tim_mode_t mode)
+{
+  uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE;
+
+  DEBUGASSERT(dev != NULL);
+
+  /* This function is not supported on basic timers. To enable or
+   * disable it, simply set its clock to valid frequency or zero.
+   */
+
+  if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \
+      ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE)
+    {
+      return -EINVAL;
+    }
+
+  /* Decode operational modes */
+
+  switch (mode & STM32_TIM_MODE_MASK)
+    {
+      case STM32_TIM_MODE_DISABLED:
+        val = 0;
+        break;
+
+      case STM32_TIM_MODE_DOWN:
+        val |= ATIM_CR1_DIR;
+
+      case STM32_TIM_MODE_UP:
+        break;
+
+      case STM32_TIM_MODE_UPDOWN:
+        val |= ATIM_CR1_CENTER1;
+
+        /* Our default: Interrupts are generated on compare, when counting
+         * down
+         */
+
+        break;
+
+      case STM32_TIM_MODE_PULSE:
+        val |= ATIM_CR1_OPM;
+        break;
+
+      default:
+        return -EINVAL;
+    }
+
+  stm32_tim_reload_counter(dev);
+  stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
+
+  /* Advanced registers require Main Output Enable */
+
+    if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE ||
+        ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE)
+      {
+        stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE);
+      }
+
+  return OK;
+}
+
+static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev,
+                                uint8_t channel, stm32_tim_channel_t mode)
+{
+  uint16_t ccmr_orig   = 0;
+  uint16_t ccmr_val    = 0;
+  uint16_t ccmr_mask   = 0xff;
+  uint16_t ccer_val    = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET);
+  uint8_t  ccmr_offset = STM32_GTIM_CCMR1_OFFSET;
+
+  DEBUGASSERT(dev != NULL);
+
+  /* Further we use range as 0..3; if channel=0 it will also overflow here */
+
+  if (--channel > 4)
+    {
+      return -EINVAL;
+    }
+
+  /* Assume that channel is disabled and polarity is active high */
+
+  ccer_val &= ~(3 << (channel << 2));
+
+  /* This function is not supported on basic timers. To enable or
+   * disable it, simply set its clock to valid frequency or zero.
+   */
+
+  if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE || \
+      ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE)
+    {
+      return -EINVAL;
+    }
+
+  /* Decode configuration */
+
+  switch (mode & STM32_TIM_CH_MODE_MASK)
+    {
+      case STM32_TIM_CH_DISABLED:
+        break;
+
+      case STM32_TIM_CH_OUTPWM:
+        ccmr_val  = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) +
+                    ATIM_CCMR1_OC1PE;
+        ccer_val |= ATIM_CCER_CC1E << (channel << 2);
+        break;
+
+      default:
+        return -EINVAL;
+    }
+
+  /* Set polarity */
+
+  if (mode & STM32_TIM_CH_POLARITY_NEG)
+    {
+      ccer_val |= ATIM_CCER_CC1P << (channel << 2);
+    }
+
+  /* Define its position (shift) and get register offset */
+
+  if (channel & 1)
+    {
+      ccmr_val  <<= 8;
+      ccmr_mask <<= 8;
+    }
+
+  if (channel > 1)
+    {
+      ccmr_offset = STM32_GTIM_CCMR2_OFFSET;
+    }
+
+  ccmr_orig  = stm32_getreg16(dev, ccmr_offset);
+  ccmr_orig &= ~ccmr_mask;
+  ccmr_orig |= ccmr_val;
+  stm32_putreg16(dev, ccmr_offset, ccmr_orig);
+  stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val);
+
+  /* set GPIO */
+
+  switch (((struct stm32_tim_priv_s *)dev)->base)
+    {
+#ifdef CONFIG_STM32H7_TIM1
+      case STM32_TIM1_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM1_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
+#  endif
+#  if defined(GPIO_TIM1_CH2OUT)
+            case 1:
+              stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
+#  endif
+#  if defined(GPIO_TIM1_CH3OUT)
+            case 2:
+              stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
+#  endif
+#  if defined(GPIO_TIM1_CH4OUT)
+            case 3:
+              stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
+#  endif
+#  if defined(GPIO_TIM1_CH5OUT)
+            case 4:
+              stm32_tim_gpioconfig(GPIO_TIM1_CH5OUT, mode); break;
+#  endif
+#  if defined(GPIO_TIM1_CH6OUT)
+            case 5:
+              stm32_tim_gpioconfig(GPIO_TIM1_CH6OUT, mode); break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM2
+      case STM32_TIM2_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM2_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM2_CH2OUT)
+            case 1:
+              stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM2_CH3OUT)
+            case 2:
+              stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM2_CH4OUT)
+            case 3:
+              stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode);
+              break;
+#endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM3
+      case STM32_TIM3_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM3_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM3_CH2OUT)
+            case 1:
+              stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM3_CH3OUT)
+            case 2:
+              stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM3_CH4OUT)
+            case 3:
+              stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode);
+              break;
+#endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM4
+      case STM32_TIM4_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM4_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM4_CH2OUT)
+            case 1:
+              stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM4_CH3OUT)
+            case 2:
+              stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM4_CH4OUT)
+            case 3:
+              stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode);
+              break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM5
+      case STM32_TIM5_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM5_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM5_CH2OUT)
+            case 1:
+              stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM5_CH3OUT)
+            case 2:
+              stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM5_CH4OUT)
+            case 3:
+              stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode);
+              break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM8
+      case STM32_TIM8_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM8_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
+#  endif
+#  if defined(GPIO_TIM8_CH2OUT)
+            case 1:
+              stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break;
+#  endif
+#  if defined(GPIO_TIM8_CH3OUT)
+            case 2:
+              stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break;
+#  endif
+#  if defined(GPIO_TIM8_CH4OUT)
+            case 3:
+              stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
+#  endif
+#  if defined(GPIO_TIM8_CH5OUT)
+            case 4:
+              stm32_tim_gpioconfig(GPIO_TIM8_CH5OUT, mode); break;
+#  endif
+#  if defined(GPIO_TIM8_CH6OUT)
+            case 5:
+              stm32_tim_gpioconfig(GPIO_TIM8_CH6OUT, mode); break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+
+#ifdef CONFIG_STM32H7_TIM12
+      case STM32_TIM12_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM12_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM12_CH1OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM12_CH2OUT)
+            case 1:
+              stm32_tim_gpioconfig(GPIO_TIM12_CH2OUT, mode);
+              break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM13
+      case STM32_TIM13_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM13_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM13_CH1OUT, mode);
+              break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM14
+      case STM32_TIM14_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM14_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM14_CH1OUT, mode);
+              break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+
+#ifdef CONFIG_STM32H7_TIM15
+      case STM32_TIM15_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM15_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode);
+              break;
+#  endif
+#  if defined(GPIO_TIM15_CH2OUT)
+            case 1:
+              stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode);
+              break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM16
+      case STM32_TIM16_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM16_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode);
+              break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM17
+      case STM32_TIM17_BASE:
+        switch (channel)
+          {
+#  if defined(GPIO_TIM17_CH1OUT)
+            case 0:
+              stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode);
+              break;
+#  endif
+            default:
+              return -EINVAL;
+          }
+        break;
+#endif
+    }
+  return OK;
+}
+
+static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev,
+                                uint8_t channel, uint32_t compare)
+{
+  DEBUGASSERT(dev != NULL);
+
+  switch (channel)
+    {
+      case 1:
+        stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare);
+        break;
+
+      case 2:
+        stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare);
+        break;
+
+      case 3:
+        stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare);
+        break;
+
+      case 4:
+        stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare);
+        break;
+
+      default:
+        return -EINVAL;
+    }
+
+  return OK;
+}
+
+static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev,
+                                uint8_t channel)
+{
+  DEBUGASSERT(dev != NULL);
+
+  switch (channel)
+    {
+      case 1:
+        return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET);
+
+      case 2:
+        return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET);
+
+      case 3:
+        return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET);
+
+      case 4:
+        return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET);
+    }
+
+  return -EINVAL;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
+{
+  struct stm32_tim_dev_s *dev = NULL;
+
+  /* Get structure and enable power */
+
+  switch (timer)
+    {
+#ifdef CONFIG_STM32H7_TIM1
+      case 1:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
+        modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM2
+      case 2:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv;
+        modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM2EN);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM3
+      case 3:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv;
+        modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM3EN);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM4
+      case 4:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv;
+        modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM4EN);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM5
+      case 5:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv;
+        modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM5EN);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM6
+      case 6:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv;
+        modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM6EN);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM7
+      case 7:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv;
+        modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM7EN);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM8
+      case 8:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv;
+        modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM12
+      case 12:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv;
+        modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM12EN);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM13
+      case 13:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv;
+        modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM14
+      case 14:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv;
+        modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM15
+      case 15:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv;
+        modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM16
+      case 16:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv;
+        modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM17
+      case 17:
+        dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv;
+        modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN);
+        break;
+#endif
+      default:
+        return NULL;
+    }
+
+  /* Is device already allocated */
+
+  if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED)
+    {
+      return NULL;
+    }
+
+  stm32_tim_reset(dev);
+
+  return dev;
+}
+
+/* TODO: Detach interrupts, and close down all TIM Channels */
+
+int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
+{
+  DEBUGASSERT(dev != NULL);
+
+  /* Disable power */
+
+  switch (((struct stm32_tim_priv_s *)dev)->base)
+    {
+#ifdef CONFIG_STM32H7_TIM1
+      case STM32_TIM1_BASE:
+        modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM2
+      case STM32_TIM2_BASE:
+        modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM2EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM3
+      case STM32_TIM3_BASE:
+        modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM3EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM4
+      case STM32_TIM4_BASE:
+        modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM4EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM5
+      case STM32_TIM5_BASE:
+        modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM5EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM6
+      case STM32_TIM6_BASE:
+        modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM6EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM7
+      case STM32_TIM7_BASE:
+        modifyreg32(STM32_RCC_APB1LENR, RCC_APB1ENR_TIM7EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM8
+      case STM32_TIM8_BASE:
+        modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM12
+      case STM32_TIM12_BASE:
+        modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM12EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM13
+      case STM32_TIM12_BASE:
+        modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM13EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM14
+      case STM32_TIM14_BASE:
+        modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM14EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM15
+      case STM32_TIM15_BASE:
+        modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM16
+      case STM32_TIM16_BASE:
+        modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0);
+        break;
+#endif
+#ifdef CONFIG_STM32H7_TIM17
+      case STM32_TIM17_BASE:
+        modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0);
+        break;
+#endif
+      default:
+        return -EINVAL;
+    }
+
+  /* Mark it as free */
+
+  ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED;
+
+  return OK;
+}
+
+#endif /* defined(CONFIG_STM32H7_TIM1 || ... || TIM17) */
diff --git a/arch/arm/src/stm32h7/stm32_tim.h b/arch/arm/src/stm32h7/stm32_tim.h
new file mode 100644
index 00000000000..ab935cdbbf7
--- /dev/null
+++ b/arch/arm/src/stm32h7/stm32_tim.h
@@ -0,0 +1,223 @@
+/****************************************************************************
+ * arch/arm/src/stm32h7/stm32_tim.h
+ *
+ *   Copyright (C) 2011 Uros Platise. All rights reserved.
+ *   Author: Uros Platise 
+ *
+ * With modifications and updates by:
+ *
+ *   Copyright (C) 2011-2012, 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32H7_STM32_TIM_H
+#define __ARCH_ARM_SRC_STM32H7_STM32_TIM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include "chip.h"
+#include "hardware/stm32_tim.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Helpers ******************************************************************/
+
+#define STM32_TIM_SETMODE(d,mode)       ((d)->ops->setmode(d,mode))
+#define STM32_TIM_SETCLOCK(d,freq)      ((d)->ops->setclock(d,freq))
+#define STM32_TIM_SETPERIOD(d,period)   ((d)->ops->setperiod(d,period))
+#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
+#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
+#define STM32_TIM_GETCAPTURE(d,ch)      ((d)->ops->getcapture(d,ch))
+#define STM32_TIM_SETISR(d,hnd,arg,s)   ((d)->ops->setisr(d,hnd,arg,s))
+#define STM32_TIM_ENABLEINT(d,s)        ((d)->ops->enableint(d,s))
+#define STM32_TIM_DISABLEINT(d,s)       ((d)->ops->disableint(d,s))
+#define STM32_TIM_ACKINT(d,s)           ((d)->ops->ackint(d,s))
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* TIM Device Structure */
+
+struct stm32_tim_dev_s
+{
+  struct stm32_tim_ops_s *ops;
+};
+
+/* TIM Modes of Operation */
+
+typedef enum
+{
+  STM32_TIM_MODE_UNUSED       = -1,
+
+  /* One of the following */
+
+  STM32_TIM_MODE_MASK         = 0x0310,
+  STM32_TIM_MODE_DISABLED     = 0x0000,
+  STM32_TIM_MODE_UP           = 0x0100,
+  STM32_TIM_MODE_DOWN         = 0x0110,
+  STM32_TIM_MODE_UPDOWN       = 0x0200,
+  STM32_TIM_MODE_PULSE        = 0x0300,
+
+  /* One of the following */
+
+  STM32_TIM_MODE_CK_INT       = 0x0000,
+#if 0
+  STM32_TIM_MODE_CK_INT_TRIG  = 0x0400,
+  STM32_TIM_MODE_CK_EXT       = 0x0800,
+  STM32_TIM_MODE_CK_EXT_TRIG  = 0x0c00,
+
+  /* Clock sources, OR'ed with CK_EXT */
+
+  STM32_TIM_MODE_CK_CHINVALID = 0x0000,
+  STM32_TIM_MODE_CK_CH1       = 0x0001,
+  STM32_TIM_MODE_CK_CH2       = 0x0002,
+  STM32_TIM_MODE_CK_CH3       = 0x0003,
+  STM32_TIM_MODE_CK_CH4       = 0x0004
+#endif
+
+  /* Todo: external trigger block */
+} stm32_tim_mode_t;
+
+/* TIM Channel Modes */
+
+typedef enum
+{
+  STM32_TIM_CH_DISABLED       = 0x00,
+
+  /* Common configuration */
+
+  STM32_TIM_CH_POLARITY_POS   = 0x00,
+  STM32_TIM_CH_POLARITY_NEG   = 0x01,
+
+  /* MODES: */
+
+  STM32_TIM_CH_MODE_MASK      = 0x06,
+
+  /* Output Compare Modes */
+
+  STM32_TIM_CH_OUTPWM         = 0x04,    /* Enable standard PWM mode, active high when counter < compare */
+#if 0
+  STM32_TIM_CH_OUTCOMPARE     = 0x06,
+
+  /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */
+
+  STM32_TIM_CH_INCAPTURE      = 0x10,
+  STM32_TIM_CH_INPWM          = 0x20
+  STM32_TIM_CH_DRIVE_OC   -- open collector mode
+#endif
+} stm32_tim_channel_t;
+
+/* TIM Operations */
+
+struct stm32_tim_ops_s
+{
+  /* Basic Timers */
+
+  int  (*setmode)(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode);
+  int  (*setclock)(FAR struct stm32_tim_dev_s *dev, uint32_t freq);
+  void (*setperiod)(FAR struct stm32_tim_dev_s *dev, uint32_t period);
+
+  /* General and Advanced Timers Adds */
+
+  int  (*setchannel)(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
+                     stm32_tim_channel_t mode);
+  int  (*setcompare)(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
+                     uint32_t compare);
+  int  (*getcapture)(FAR struct stm32_tim_dev_s *dev, uint8_t channel);
+
+  /* Timer interrupts */
+
+  int  (*setisr)(FAR struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg,
+                 int source);
+  void (*enableint)(FAR struct stm32_tim_dev_s *dev, int source);
+  void (*disableint)(FAR struct stm32_tim_dev_s *dev, int source);
+  void (*ackint)(FAR struct stm32_tim_dev_s *dev, int source);
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/* Power-up timer and get its structure */
+
+FAR struct stm32_tim_dev_s *stm32_tim_init(int timer);
+
+/* Power-down timer, mark it as unused */
+
+int stm32_tim_deinit(FAR struct stm32_tim_dev_s *dev);
+
+/****************************************************************************
+ * Name: stm32_timer_initialize
+ *
+ * Description:
+ *   Bind the configuration timer to a timer lower half instance and
+ *   register the timer drivers at 'devpath'
+ *
+ * Input Parameters:
+ *   devpath - The full path to the timer device. This should be of the
+ *             form /dev/timer0
+ *   timer   - the timer number.
+ *
+ * Returned Values:
+ *   Zero (OK) is returned on success; A negated errno value is returned
+ *   to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_TIMER
+int stm32_timer_initialize(FAR const char *devpath, int timer);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_STM32H7_STM32_TIM_H */
diff --git a/arch/arm/src/stm32h7/stm32_uart.h b/arch/arm/src/stm32h7/stm32_uart.h
index 874fcfedd43..bdd6bc9d81e 100644
--- a/arch/arm/src/stm32h7/stm32_uart.h
+++ b/arch/arm/src/stm32h7/stm32_uart.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/stm32_uart.h"
+#include "hardware/stm32_uart.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
index ded312dbb99..63bbcf3fe62 100644
--- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
+++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
@@ -104,7 +104,13 @@ static inline void rcc_reset(void)
   regval  = getreg32(STM32_RCC_CR);
   regval &= ~(RCC_CR_HSEON | RCC_CR_HSI48ON |
               RCC_CR_CSION | RCC_CR_PLL1ON |
-              RCC_CR_PLL2ON | RCC_CR_PLL3ON);
+              RCC_CR_PLL2ON | RCC_CR_PLL3ON |
+              RCC_CR_HSIDIV_MASK);
+
+  /* Set HSI predivider to default (4, 16MHz) */
+
+  regval |= RCC_CR_HSIDIV_4;
+
   putreg32(regval, STM32_RCC_CR);
 
   /* Reset PLLCFGR register to reset default */
@@ -170,6 +176,13 @@ static inline void rcc_enableahb1(void)
 #endif
 #endif
 
+#ifdef CONFIG_STM32H7_ETHMAC
+  /* Enable ethernet clocks */
+
+  regval |= (RCC_AHB1ENR_ETH1MACEN | RCC_AHB1ENR_ETH1TXEN |
+             RCC_AHB1ENR_ETH1RXEN);
+#endif
+
   putreg32(regval, STM32_RCC_AHB1ENR);   /* Enable peripherals */
 }
 
@@ -220,6 +233,12 @@ static inline void rcc_enableahb3(void)
   regval |= RCC_AHB3ENR_MDMAEN;
 #endif
 
+#ifdef CONFIG_STM32H7_SDMMC1
+  /* SDMMC clock enable */
+
+  regval |= RCC_AHB3ENR_SDMMC1EN;
+#endif
+
   // TODO: ...
 
   putreg32(regval, STM32_RCC_AHB3ENR);   /* Enable peripherals */
@@ -396,7 +415,11 @@ static inline void rcc_enableapb2(void)
   regval |= RCC_APB2ENR_SPI5EN;
 #endif
 
-  // TODO: ...
+#ifdef CONFIG_STM32H7_SDMMC2
+  /* SDMMC2 clock enable */
+
+  regval |= RCC_APB2ENR_SDMMC2EN;
+#endif
 
   putreg32(regval, STM32_RCC_APB2ENR);   /* Enable peripherals */
 }
diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig
index ee3451bb3c1..99ec2395c4c 100644
--- a/arch/arm/src/stm32l4/Kconfig
+++ b/arch/arm/src/stm32l4/Kconfig
@@ -459,6 +459,7 @@ config STM32L4_STM32L4X2
 	bool
 	default n
 	select STM32L4_STM32L4X3
+	select STM32L4_HAVE_USBFS
 
 config STM32L4_STM32L4X3
 	# STM32L4 devices documented in RM0394, regardless of what ST's
@@ -474,6 +475,7 @@ config STM32L4_STM32L4X3
 	select STM32L4_HAVE_COMP
 	select STM32L4_HAVE_SAI1
 	select STM32L4_HAVE_LCD if !(STM32L4_STM32L4X1 || STM32L4_STM32L4X2)
+	select STM32L4_HAVE_HSI48
 
 config STM32L4_STM32L4X5
 	# STM32L4 USB OTG Lines (documented in RM0351)
@@ -563,6 +565,7 @@ config STM32L4_STM32L4XR
 	select STM32L4_HAVE_I2C4
 	select STM32L4_HAVE_DCMI
 	select STM32L4_HAVE_DFSDM1
+	select STM32L4_HAVE_HSI48
 
 # Chip subfamilies:
 
@@ -679,6 +682,7 @@ config STM32L4_STM32L496XX
 	select STM32L4_HAVE_DCMI
 	select STM32L4_HAVE_DMA2D
 	select STM32L4_HAVE_DFSDM1
+	select STM32L4_HAVE_HSI48
 
 config STM32L4_STM32L4A6XX
 	bool
@@ -932,6 +936,10 @@ config STM32L4_HAVE_HASH
 	bool
 	default n
 
+config STM32L4_HAVE_HSI48
+	bool
+	default n
+
 config STM32L4_HAVE_I2C4
 	bool
 	default n
@@ -956,6 +964,10 @@ config STM32L4_HAVE_OTGFS
 	bool
 	default n
 
+config STM32L4_HAVE_USBFS
+	bool
+	default n
+
 config STM32L4_HAVE_SAI1
 	bool
 	default n
@@ -1448,6 +1460,12 @@ config STM32L4_LPTIM2
 	select STM32L4_LPTIM
 	depends on STM32L4_HAVE_LPTIM2
 
+config STM32L4_USBFS
+	bool "USB FS"
+	default n
+	depends on STM32L4_HAVE_USBFS
+	select USBDEV
+
 comment "APB2 Peripherals"
 
 config STM32L4_SYSCFG
diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs
index 034e3991abe..20f5f6f509a 100644
--- a/arch/arm/src/stm32l4/Make.defs
+++ b/arch/arm/src/stm32l4/Make.defs
@@ -80,11 +80,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
@@ -125,6 +123,10 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CHIP_CSRCS += stm32l4_userspace.c stm32l4_mpuinit.c
 endif
 
+ifeq ($(CONFIG_STM32L4_HAVE_HSI48),y)
+CHIP_CSRCS += stm32l4_hsi48.c
+endif
+
 ifeq ($(CONFIG_STM32L4_ADC),y)
 CHIP_CSRCS += stm32l4_adc.c
 endif
@@ -142,6 +144,9 @@ CHIP_CSRCS += stm32l4_dma.c
 endif
 
 ifeq ($(CONFIG_USBDEV),y)
+ifeq ($(CONFIG_STM32L4_USBFS),y)
+CHIP_CSRCS += stm32l4_usbdev.c
+endif
 ifeq ($(CONFIG_STM32L4_OTGFS),y)
 CHIP_CSRCS += stm32l4_otgfsdev.c
 endif
diff --git a/arch/arm/src/stm32l4/chip.h b/arch/arm/src/stm32l4/chip.h
index 2d19fa59e29..fb5ae336d5f 100644
--- a/arch/arm/src/stm32l4/chip.h
+++ b/arch/arm/src/stm32l4/chip.h
@@ -48,8 +48,8 @@
 
 #include 
 #include 
-#include "chip/stm32l4_pinmap.h"
-#include "chip/stm32l4_memorymap.h"
+#include "hardware/stm32l4_pinmap.h"
+#include "hardware/stm32l4_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_adc.h b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4_adc.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_adc.h
index 657dfac82e9..99e71f764f6 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_adc.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_adc.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_adc.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_ADC_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_ADC_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_ADC_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_ADC_H
 
 /************************************************************************************
  * Included Files
@@ -594,4 +594,4 @@
 #  define ADC_CDR_RDATA_SLV_MASK     (0xffff << ADC_CDR_RDATA_SLV_SHIFT)
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_ADC_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_ADC_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_can.h b/arch/arm/src/stm32l4/hardware/stm32l4_can.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4_can.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_can.h
index 6319282e48e..2eca71947d7 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_can.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_can.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_can.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_can.h
  *
  *   Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -37,8 +37,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_CAN_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_CAN_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CAN_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CAN_H
 
 /************************************************************************************
  * Included Files
@@ -426,4 +426,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_CAN_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CAN_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_comp.h b/arch/arm/src/stm32l4/hardware/stm32l4_comp.h
similarity index 97%
rename from arch/arm/src/stm32l4/chip/stm32l4_comp.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_comp.h
index 61355abbf3e..3501b88fb4c 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_comp.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_comp.h
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_COMP_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_COMP_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_COMP_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_COMP_H
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -121,4 +121,4 @@
 #  define COMP_CSR_LOCK_RW         (0)
 #  define COMP_CSR_LOCK_RO         COMP_CSR_LOCK_MASK
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_COMP_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_COMP_H */
diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_crs.h b/arch/arm/src/stm32l4/hardware/stm32l4_crs.h
new file mode 100644
index 00000000000..57a95ef8750
--- /dev/null
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_crs.h
@@ -0,0 +1,115 @@
+/************************************************************************************
+ * arch/arm/src/stm32l4/hardware/stm32l4_crs.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *           Alan Carvalho de Assis 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CRS_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CRS_H
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32L4_CRS_CR_OFFSET        0x0000  /* CRS control register */
+#define STM32L4_CRS_CFGR_OFFSET      0x0004  /* CRS configuration register */
+#define STM32L4_CRS_ISR_OFFSET       0x0008  /* CRS interrupt and status register */
+#define STM32L4_CRS_ICR_OFFSET       0x000c  /* CRS interrupt flag clear register */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32L4_CRS_CR               (STM32L4_CRS_BASE + STM32L4_CRS_CR_OFFSET)
+#define STM32L4_CRS_CFGR             (STM32L4_CRS_BASE + STM32L4_CRS_CFGR_OFFSET)
+#define STM32L4_CRS_ISR              (STM32L4_CRS_BASE + STM32L4_CRS_ISR_OFFSET)
+#define STM32L4_CRS_ICR              (STM32L4_CRS_BASE + STM32L4_CRS_ICR_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* CRS control register */
+
+#define CRS_CR_SYNCOKIE            (1 << 0)  /* Bit 0: SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE          (1 << 1)  /* Bit 1: SYNC warning interrupt enable */
+#define CRS_CR_ERRIE               (1 << 2)  /* Bit 2: Syncronization or Trimming error interrupt enabled */
+#define CRS_CR_ESYNCIE             (1 << 3)  /* Bit 3: Expected SYNC interrupt enable */
+#define CRS_CR_CEN                 (1 << 5)  /* Bit 5: Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN          (1 << 6)  /* Bit 6: Automatic trimming enabled */
+#define CRS_CR_SWSYNC              (1 << 7)  /* Bit 7: Generate sofware SYNC event */
+#define CRS_CR_TRIM_SHIFT          8         /* Bits 8-13: HSI48 oscillator smooth trimming */
+#define CRS_CR_TRIM_MASK           (0x3f << CRS_CR_TRIM_SHIFT)
+
+/* CRS configuration register */
+
+#define CRS_CFGR_RELOAD_SHIFT      0         /* Bits 0-15: Counter reload value */
+#define CRS_CFGR_RELOAD_MASK       (0xffff << CRS_CFGR_RELOAD_SHIFT)
+#define CRS_CFGR_FELIM_SHIFT       16        /* Bits 16-23: Frequency error limit */
+#define CRS_CFGR_FELIM_MASK        (0xff << CRS_CFGR_FELIM_SHIFT)
+#define CRS_CFGR_SYNCDIV_SHIFT     24        /* Bits 24-26: SYNC divider */
+#define CRS_CFGR_SYNCDIV_MASK      (7 << CRS_CFGR_SYNCDIV_SHIFT)
+#  define CRS_CFGR_SYNCDIV_d1      (0 << CRS_CFGR_SYNCDIV_SHIFT) /* Not divided */
+#  define CRS_CFGR_SYNCDIV_d2      (1 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 2 */
+#  define CRS_CFGR_SYNCDIV_d4      (2 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 4 */
+#  define CRS_CFGR_SYNCDIV_d8      (3 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 8 */
+#  define CRS_CFGR_SYNCDIV_d16     (4 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 16 */
+#  define CRS_CFGR_SYNCDIV_d32     (5 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 32 */
+#  define CRS_CFGR_SYNCDIV_d64     (6 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 64 */
+#  define CRS_CFGR_SYNCDIV_d128    (7 << CRS_CFGR_SYNCDIV_SHIFT) /* divided by 128 */
+#define CRS_CFGR_SYNCSRC_SHIFT     28        /* Bits 28-29: SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_MASK      (3 << CRS_CFGR_SYNCSRC_SHIFT)
+#  define CRS_CFGR_SYNCSRC_GPIO    (0 << CRS_CFGR_SYNCSRC_SHIFT) /* GPIO as SYNC signal source */
+#  define CRS_CFGR_SYNCSRC_LSE     (1 << CRS_CFGR_SYNCSRC_SHIFT) /* LSE as SYNC signal source */
+#  define CRS_CFGR_SYNCSRC_USBSOF  (2 << CRS_CFGR_SYNCSRC_SHIFT) /* USB SOF as SYNC signal source */
+#define CRS_CFGR_SYNCPOL           (1 << 31) /* SYNC polarity selection */
+
+/* CRS interrupt and status register */
+
+#define CRS_ISR_SYNCOKF            (1 << 0)  /* Bit 0: SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF          (1 << 1)  /* Bit 1: SYNC warning flag */
+#define CRS_ISR_ERRF               (1 << 2)  /* Bit 2: Errot flag */
+#define CRS_ISR_ESYNCF             (1 << 3)  /* Bit 3: Expected SYNC flag */
+#define CRS_ISR_SYNCERR            (1 << 8)  /* Bit 8: SYNC error */
+#define CRS_ISR_SYNCMISS           (1 << 9)  /* Bit 9: SYNC missed */
+#define CRS_ISR_TRIMOVF            (1 << 10) /* Bit 10: Trimming overflow or underflow */
+#define CRS_ISR_FEDIR              (1 << 15) /* Bit 15: Frequency error direction */
+#define CRS_ISR_FECAP_SHIFT        16        /* Bits 16-31: Frequency error capture */
+#define CRS_ISR_FECAP_MASK         (0xffff << CRS_ISR_FECAP_SHIFT)
+
+/* CRS interrupt flag clear register */
+
+#define CRS_ICR_SYNCOKC            (1 << 0)  /* Bit 0: SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC          (1 << 1)  /* Bit 1: SYNC waring clear flag */
+#define CRS_ICR_ERRC               (1 << 2)  /* Bit 2: Error clear flag */
+#define CRS_ICR_ESYNCC             (1 << 3)  /* Bit 3: Expected SYNC clear flag */
+
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_CRS_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_dac.h b/arch/arm/src/stm32l4/hardware/stm32l4_dac.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4_dac.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_dac.h
index 234bdfd2722..2c2fb81c502 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_dac.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_dac.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_dac.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_dac.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_DAC_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_DAC_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DAC_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DAC_H
 
 /************************************************************************************
  * Included Files
@@ -338,4 +338,4 @@
 #define DAC_SHRR_TREFRESH2_SHIFT   (16)     /* Bits 16-23: DAC channel 2 refresh time */
 #define DAC_SHRR_TREFRESH2_MASK    (0xff << DAC_SHRR_TREFRESH2_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_DAC_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DAC_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4_dfsdm.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h
index 2f67832c6bc..0d0f564a03a 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_dfsdm.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_dfsdm.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h
  *
  *   Copyright (C) 2017-2018 Haltian Ltd. All rights reserved.
  *   Author: Juha Niskanen 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_DFSDM_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_DFSDM_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DFSDM_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DFSDM_H
 
 /************************************************************************************
  * Included Files
@@ -470,4 +470,4 @@
 #define DFSDM_CNVTIMR_CNVCNT_SHIFT       (4)     /* Bits 4-31: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK */
 #define DFSDM_CNVTIMR_CNVCNT_MASK        (~0xfu)
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_DFSDM_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_DFSDM_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_exti.h b/arch/arm/src/stm32l4/hardware/stm32l4_exti.h
similarity index 97%
rename from arch/arm/src/stm32l4/chip/stm32l4_exti.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_exti.h
index 4af53eb3474..05970c97391 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_exti.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_exti.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_exti.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_exti.h
  *
  *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_EXTI_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_EXTI_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_EXTI_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_EXTI_H
 
 /************************************************************************************
  * Included Files
@@ -176,5 +176,5 @@
 #define EXTI_PR2_SHIFT            (0)                /* Bits 0-X: Pending bit for all lines */
 #define EXTI_PR2_MASK             STM32L4_EXTI2_MASK
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_EXTI_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_EXTI_H */
 
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_flash.h b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h
similarity index 98%
rename from arch/arm/src/stm32l4/chip/stm32l4_flash.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_flash.h
index 8bdb73c8287..23f48add233 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_flash.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_flash.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_flash.h
  *
  *   Copyright (C) 2009, 2011, 2015, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_FLASH_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_FLASH_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_FLASH_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_FLASH_H
 
 /************************************************************************************
  * Included Files
@@ -293,4 +293,4 @@
 #  define FLASH_CFGR_LVEN           (1 << 0)                /* Bit 0: Low voltage enable */
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_FLASH_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_FLASH_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_gpio.h b/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h
similarity index 98%
rename from arch/arm/src/stm32l4/chip/stm32l4_gpio.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_gpio.h
index 08e0e9e5197..6e91d67f044 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_gpio.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_gpio.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_gpio.h
  *
  *   Copyright (C) 2016, Sebastien Lorquet. All rights reserved.
  *   Author: Sebastien Lorquet 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_GPIO_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_GPIO_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_GPIO_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_GPIO_H
 
 /************************************************************************************
  * Included Files
@@ -371,5 +371,5 @@
 #define GPIO_AFRH15_SHIFT          (28)
 #define GPIO_AFRH15_MASK           (15 << GPIO_AFRH15_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_GPIO_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_GPIO_H */
 
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_i2c.h b/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h
similarity index 98%
rename from arch/arm/src/stm32l4/chip/stm32l4_i2c.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_i2c.h
index 398073514a0..4720c00254e 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_i2c.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_i2c.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_i2c.h
  *
  *   Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_I2C_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_I2C_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_I2C_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_I2C_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -259,5 +259,5 @@
 
 #define I2C_TXDR_MASK             (0xff)
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_I2C_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_I2C_H */
 
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_lptim.h b/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h
similarity index 97%
rename from arch/arm/src/stm32l4/chip/stm32l4_lptim.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_lptim.h
index 1822effec45..325373bb3f8 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_lptim.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h
@@ -34,8 +34,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_LPTIM_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_LPTIM_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_LPTIM_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_LPTIM_H
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -114,4 +114,4 @@
 #define LPTIM_CR_SNGSTRT          (1 << 1)   /* Bit 1: Single Mode */
 #define LPTIM_CR_CNTSTRT          (1 << 2)   /* Bit 2: Continuous Mode */
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_LPTIM_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_LPTIM_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_memorymap.h b/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4_memorymap.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h
index aeab28e2fbd..3b1631ad487 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_memorymap.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_memorymap.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h
  *
  *   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_pinmap.h b/arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h
similarity index 85%
rename from arch/arm/src/stm32l4/chip/stm32l4_pinmap.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h
index cf6fd5c2e75..77e053f2fbf 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_pinmap.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_pinmap.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2015 Sebastien Lorquet. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_PINMAP_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PINMAP_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -45,16 +45,16 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32L4_STM32L4X3)
-#  include "chip/stm32l4x3xx_pinmap.h"
+#  include "hardware/stm32l4x3xx_pinmap.h"
 #elif defined(CONFIG_STM32L4_STM32L4X5)
-#  include "chip/stm32l4x5xx_pinmap.h"
+#  include "hardware/stm32l4x5xx_pinmap.h"
 #elif defined(CONFIG_STM32L4_STM32L4X6)
-#  include "chip/stm32l4x6xx_pinmap.h"
+#  include "hardware/stm32l4x6xx_pinmap.h"
 #elif defined(CONFIG_STM32L4_STM32L4XR)
-#  include "chip/stm32l4xrxx_pinmap.h"
+#  include "hardware/stm32l4xrxx_pinmap.h"
 #else
 #  error "Unsupported STM32 L4 pin map"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PINMAP_H */
 
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_pwr.h b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h
similarity index 93%
rename from arch/arm/src/stm32l4/chip/stm32l4_pwr.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_pwr.h
index fbcf9a6a163..0677c51f99d 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_pwr.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_pwr.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_pwr.h
  *
  *   Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_PWR_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_PWR_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PWR_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PWR_H
 
 /************************************************************************************
  * Included Files
@@ -74,6 +74,9 @@
 #define STM32L4_PWR_PDCRH_OFFSET 0x005C  /* Power Port H pull-down control register */
 #define STM32L4_PWR_PUCRI_OFFSET 0x0060  /* Power Port I pull-up control register */
 #define STM32L4_PWR_PDCRI_OFFSET 0x0064  /* Power Port I pull-down control register */
+#if defined(CONFIG_STM32L4_STM32L4XR)
+#  define STM32L4_PWR_CR5_OFFSET 0x0080  /* Power control register 5 */
+#endif
 
 /* Register Addresses ***************************************************************/
 
@@ -102,6 +105,9 @@
 #define STM32L4_PWR_PDCRH        (STM32L4_PWR_BASE+STM32L4_PWR_PDCRH_OFFSET)
 #define STM32L4_PWR_PUCRI        (STM32L4_PWR_BASE+STM32L4_PWR_PUCRI_OFFSET)
 #define STM32L4_PWR_PDCRI        (STM32L4_PWR_BASE+STM32L4_PWR_PDCRI_OFFSET)
+#if defined(CONFIG_STM32L4_STM32L4XR)
+#  define STM32L4_PWR_CR5        (STM32L4_PWR_BASE+STM32L4_PWR_CR5_OFFSET)
+#endif
 
 /* Register Bitfield Definitions ****************************************************/
 
@@ -114,6 +120,9 @@
 #  define PWR_CR1_LPMS_STOP2     (2 << PWR_CR1_LPMS_SHIFT) /* 010: Stop 2 mode */
 #  define PWR_CR1_LPMS_STANDBY   (3 << PWR_CR1_LPMS_SHIFT) /* 011: Standby mode */
 #  define PWR_CR1_LPMS_SHUTDOWN  (4 << PWR_CR1_LPMS_SHIFT) /* 1xx: Shutdown mode */
+#if defined(CONFIG_STM32L4_STM32L4XR)
+#  define PWR_CR1_RRSTP          (1 <<  4) /* Bit  4: SRAM3 retention in Stop 2 mode */
+#endif
 #define PWR_CR1_DBP              (1 <<  8) /* Bit  8: Disable Backup domain write protection */
 #define PWR_CR1_VOS_SHIFT        9
 #define PWR_CR1_VOS_MASK         (3 << PWR_CR1_VOS_SHIFT) /* Bits 9-10: Voltage scaling range selection */
@@ -154,6 +163,9 @@
 #define PWR_CR3_EWUP5            (1 <<  4) /* Bit  4: Enable Wakeup pin WKUP5 */
 #define PWR_CR3_RRS              (1 <<  8) /* Bit  8: SRAM2 retention in Standby mode */
 #define PWR_CR3_APC              (1 << 10) /* Bit 10: Apply pull-up and pull-down configuration */
+#if defined(CONFIG_STM32L4_STM32L4XR)
+#  define PWR_CR3_DSIPDEN        (1 << 12) /* Bit 12: Enable Pull-down activation on DSI pins */
+#endif
 #define PWR_CR3_EIWUL            (1 << 15) /* Bit 15: Enable internal wakeup line */
 
 /* Power control register 4 */
@@ -202,4 +214,10 @@
 
 /* Port X pull-up/down registers have one bit per port line, with a few exceptions */
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_PWR_H */
+/* Power control register 5 */
+
+#if defined(CONFIG_STM32L4_STM32L4XR)
+#  define PWR_CR5_R1MODE         (1 <<  8) /* Bit  8: Main regulator in Range 1 normal mode. */
+#endif
+
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PWR_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_qspi.h b/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h
similarity index 98%
rename from arch/arm/src/stm32l4/chip/stm32l4_qspi.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_qspi.h
index ecb6c927afa..33e771d9dd8 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_qspi.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_qspi.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_qspi.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: dev@ziggurat29.com
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_QSPI_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_QSPI_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_QSPI_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_QSPI_H
 
 /****************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/stm32l4_memorymap.h"
+#include "hardware/stm32l4_memorymap.h"
 
 /****************************************************************************************
  * Pre-processor Definitions
@@ -234,6 +234,6 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_QSPI_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_QSPI_H */
 
 
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_rng.h b/arch/arm/src/stm32l4/hardware/stm32l4_rng.h
similarity index 94%
rename from arch/arm/src/stm32l4/chip/stm32l4_rng.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_rng.h
index 7812110b620..094ed66b286 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_rng.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_rng.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32l4_rng.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_rng.h
  *
  *   Copyright (C) 2012 Max Holtzberg. All rights reserved.
  *   Author: Max Holtzberg 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_RNG_H
-#define __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_RNG_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RNG_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RNG_H
 
 /************************************************************************************
  * Included Files
@@ -74,4 +74,4 @@
 #define RNG_SR_CEIS               (1 << 5) /* Bit 5: Clock error interrupt status */
 #define RNG_SR_SEIS               (1 << 6) /* Bit 6: Seed error interrupt status */
 
-#endif /* __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_RNG_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RNG_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_rtcc.h b/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4_rtcc.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h
index 2014ae1316e..4853936a8b9 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_rtcc.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_rtcc.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h
  *
  *   Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.
  *   Author: dev@ziggurat29.com
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_RTCC_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_RTCC_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RTCC_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RTCC_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -398,4 +398,4 @@
 #define RTC_OR_OUTRMP             (1 << 1)  /* Bit 1:  remap output to PB14 */
 
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_RTCC_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_RTCC_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_sai.h b/arch/arm/src/stm32l4/hardware/stm32l4_sai.h
similarity index 98%
rename from arch/arm/src/stm32l4/chip/stm32l4_sai.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_sai.h
index f411fb72baf..59d80332593 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_sai.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_sai.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32/chip/stm32l4_sai.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_sai.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author:  Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_SAI_H
-#define __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_SAI_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SAI_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SAI_H
 
 /************************************************************************************
  * Included Files
@@ -256,4 +256,4 @@
 
 /* SAI Data Register (32-bit data) */
 
-#endif /* __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_SAI_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SAI_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_sdmmc.h b/arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h
similarity index 98%
rename from arch/arm/src/stm32l4/chip/stm32l4_sdmmc.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h
index ad15be57f76..f68a6a9366a 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_sdmmc.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_sdmmc.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_sdmmc.h
  *
  *   Copyright (C) 2009, 2011-2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_SDMMC_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_SDMMC_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SDMMC_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SDMMC_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -215,5 +215,5 @@
 #define STM32_SDMMC_FIFOCNT_SHIFT             (0)
 #define STM32_SDMMC_FIFOCNT_MASK              (0x0ffffff << STM32_SDMMC_FIFOCNT_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L46XX_SDMMC_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L46XX_SDMMC_H */
 
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_spi.h b/arch/arm/src/stm32l4/hardware/stm32l4_spi.h
similarity index 97%
rename from arch/arm/src/stm32l4/chip/stm32l4_spi.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_spi.h
index c9a1a03ef28..4bc10ab8931 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_spi.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_spi.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_spi.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_spi.h
  *
  *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_SPI_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_SPI_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SPI_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SPI_H
 
 /************************************************************************************
  * Included Files
@@ -177,5 +177,5 @@
 #  define SPI_SR_FTLVL_HALF      (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
 #  define SPI_SR_FTLVL_FULL      (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_SPI_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SPI_H */
 
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h
similarity index 84%
rename from arch/arm/src/stm32l4/chip/stm32l4_syscfg.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h
index 74c3c1851ed..4537397c45f 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_syscfg.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_syscfg.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h
  *
  *   Copyright (C) 2015 Sebastien Lorquet. All rights reserved.
  *   Author: Sebastien Lorquet 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SYSCFG_H
 
 /************************************************************************************
  * Included Files
@@ -44,15 +44,15 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32L4_STM32L4X3)
-#  include "chip/stm32l4x3xx_syscfg.h"
+#  include "hardware/stm32l4x3xx_syscfg.h"
 #elif defined(CONFIG_STM32L4_STM32L4X5)
-#  include "chip/stm32l4x5xx_syscfg.h"
+#  include "hardware/stm32l4x5xx_syscfg.h"
 #elif defined(CONFIG_STM32L4_STM32L4X6)
-#  include "chip/stm32l4x6xx_syscfg.h"
+#  include "hardware/stm32l4x6xx_syscfg.h"
 #elif defined(CONFIG_STM32L4_STM32L4XR)
-#  include "chip/stm32l4xrxx_syscfg.h"
+#  include "hardware/stm32l4xrxx_syscfg.h"
 #else
 #  error "Unsupported STM32 L4 chip"
 #endif
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_SYSCFG_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_tim.h b/arch/arm/src/stm32l4/hardware/stm32l4_tim.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4_tim.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_tim.h
index 78d5004f557..329ea556fdd 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_tim.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_tim.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_tim.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_tim.h
  *
  *   Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_TIM_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_TIM_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_TIM_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_TIM_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -1119,4 +1119,4 @@
 
 #define BTIM_EGR_UG               (1 << 0)  /* Bit 0: Update generation */
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_TIM_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_TIM_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_uart.h b/arch/arm/src/stm32l4/hardware/stm32l4_uart.h
similarity index 98%
rename from arch/arm/src/stm32l4/chip/stm32l4_uart.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_uart.h
index c7605ab8ad8..efd5a95a3bb 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_uart.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_uart.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_uart.h
  *
  *   Copyright (C) 2009, 2011-2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_UART_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_UART_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_UART_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_UART_H
 
 /************************************************************************************
  * Included Files
@@ -314,5 +314,5 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_STC_STM32L4_CHIP_STM32L4_UART_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_UART_H */
 
diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h b/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h
new file mode 100644
index 00000000000..f1a9cc44bbb
--- /dev/null
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h
@@ -0,0 +1,265 @@
+/************************************************************************************
+ * arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h
+ *
+ *   Copyright (C) 2009, 2011, 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_USBDEV_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_USBDEV_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+#include 
+
+#if defined(CONFIG_STM32L4_STM32L4X2)
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+/* Endpoint Registers */
+
+#define STM32L4_USB_EPR_OFFSET(n)    ((n) << 2) /* USB endpoint n register (16-bits) */
+#define STM32L4_USB_EP0R_OFFSET      0x0000  /* USB endpoint 0 register (16-bits) */
+#define STM32L4_USB_EP1R_OFFSET      0x0004  /* USB endpoint 1 register (16-bits) */
+#define STM32L4_USB_EP2R_OFFSET      0x0008  /* USB endpoint 2 register (16-bits) */
+#define STM32L4_USB_EP3R_OFFSET      0x000c  /* USB endpoint 3 register (16-bits) */
+#define STM32L4_USB_EP4R_OFFSET      0x0010  /* USB endpoint 4 register (16-bits) */
+#define STM32L4_USB_EP5R_OFFSET      0x0014  /* USB endpoint 5 register (16-bits) */
+#define STM32L4_USB_EP6R_OFFSET      0x0018  /* USB endpoint 6 register (16-bits) */
+#define STM32L4_USB_EP7R_OFFSET      0x001c  /* USB endpoint 7 register (16-bits) */
+
+/* Common Registers */
+
+#define STM32L4_USB_CNTR_OFFSET      0x0040  /* USB control register (16-bits) */
+#define STM32L4_USB_ISTR_OFFSET      0x0044  /* USB interrupt status register (16-bits) */
+#define STM32L4_USB_FNR_OFFSET       0x0048  /* USB frame number register (16-bits) */
+#define STM32L4_USB_DADDR_OFFSET     0x004c  /* USB device address (16-bits) */
+#define STM32L4_USB_BTABLE_OFFSET    0x0050  /* Buffer table address (16-bits) */
+#define STM32L4_USB_LPMCSR_OFFSET    0x0054  /* LPM control and status register */
+#define STM32L4_USB_BCDR_OFFSET      0x0058  /* Battery charging detector */
+
+/* Buffer Descriptor Table (Relatative to BTABLE address) */
+
+#define STM32L4_USB_ADDR_TX_WOFFSET   (0)    /* Transmission buffer address n (16-bits) */
+#define STM32L4_USB_COUNT_TX_WOFFSET  (2)    /* Transmission byte count n (16-bits) */
+#define STM32L4_USB_ADDR_RX_WOFFSET   (4)    /* Reception buffer address n (16-bits) */
+#define STM32L4_USB_COUNT_RX_WOFFSET  (6)    /* Reception byte count n (16-bits) */
+
+#define STM32L4_USB_BTABLE_RADDR(ep,o)  (((uint32_t)getreg16(STM32L4_USB_BTABLE) + ((ep) << 3)) + (o))
+#define STM32L4_USB_ADDR_TX_OFFSET(ep)  STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET)
+#define STM32L4_USB_COUNT_TX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET)
+#define STM32L4_USB_ADDR_RX_OFFSET(ep)  STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET)
+#define STM32L4_USB_COUNT_RX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET)
+
+/* Register Addresses ***************************************************************/
+
+/* Endpoint Registers */
+
+#define STM32L4_USB_EPR(n)           (STM32L4_USB_FS_BASE + STM32L4_USB_EPR_OFFSET(n))
+#define STM32L4_USB_EP0R             (STM32L4_USB_FS_BASE + STM32L4_USB_EP0R_OFFSET)
+#define STM32L4_USB_EP1R             (STM32L4_USB_FS_BASE + STM32L4_USB_EP1R_OFFSET)
+#define STM32L4_USB_EP2R             (STM32L4_USB_FS_BASE + STM32L4_USB_EP2R_OFFSET)
+#define STM32L4_USB_EP3R             (STM32L4_USB_FS_BASE + STM32L4_USB_EP3R_OFFSET)
+#define STM32L4_USB_EP4R             (STM32L4_USB_FS_BASE + STM32L4_USB_EP4R_OFFSET)
+#define STM32L4_USB_EP5R             (STM32L4_USB_FS_BASE + STM32L4_USB_EP5R_OFFSET)
+#define STM32L4_USB_EP6R             (STM32L4_USB_FS_BASE + STM32L4_USB_EP6R_OFFSET)
+#define STM32L4_USB_EP7R             (STM32L4_USB_FS_BASE + STM32L4_USB_EP7R_OFFSET)
+
+/* Common Registers */
+
+#define STM32L4_USB_CNTR             (STM32L4_USB_FS_BASE + STM32L4_USB_CNTR_OFFSET)
+#define STM32L4_USB_ISTR             (STM32L4_USB_FS_BASE + STM32L4_USB_ISTR_OFFSET)
+#define STM32L4_USB_FNR              (STM32L4_USB_FS_BASE + STM32L4_USB_FNR_OFFSET)
+#define STM32L4_USB_DADDR            (STM32L4_USB_FS_BASE + STM32L4_USB_DADDR_OFFSET)
+#define STM32L4_USB_BTABLE           (STM32L4_USB_FS_BASE + STM32L4_USB_BTABLE_OFFSET)
+#define STM32L4_USB_LPMCSR           (STM32L4_USB_FS_BASE + STM32L4_USB_LPMCSR_OFFSET)
+#define STM32L4_USB_BCDR             (STM32L4_USB_FS_BASE + STM32L4_USB_BCDR_OFFSET)
+
+/* Buffer Descriptor Table (Relatative to BTABLE address) */
+
+#define STM32L4_USB_BTABLE_ADDR(ep,o)  (STM32L4_USB_SRAM_BASE + STM32L4_USB_BTABLE_RADDR(ep,o))
+#define STM32L4_USB_ADDR_TX(ep)        STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET)
+#define STM32L4_USB_COUNT_TX(ep)       STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET)
+#define STM32L4_USB_ADDR_RX(ep)        STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET)
+#define STM32L4_USB_COUNT_RX(ep)       STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* USB endpoint register */
+
+#define USB_EPR_EA_SHIFT             (0)       /* Bits 3:0 [3:0]: Endpoint Address */
+#define USB_EPR_EA_MASK              (0x0f << USB_EPR_EA_SHIFT)
+#define USB_EPR_STATTX_SHIFT         (4)       /* Bits 5-4: Status bits, for transmission transfers */
+#define USB_EPR_STATTX_MASK          (3 << USB_EPR_STATTX_SHIFT)
+#  define USB_EPR_STATTX_DIS         (0 << USB_EPR_STATTX_SHIFT) /* EndPoint TX DISabled */
+#  define USB_EPR_STATTX_STALL       (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX STALLed */
+#  define USB_EPR_STATTX_NAK         (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX NAKed */
+#  define USB_EPR_STATTX_VALID       (3 << USB_EPR_STATTX_SHIFT) /* EndPoint TX VALID */
+#  define USB_EPR_STATTX_DTOG1       (1 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit1 */
+#  define USB_EPR_STATTX_DTOG2       (2 << USB_EPR_STATTX_SHIFT) /* EndPoint TX Data Toggle bit2 */
+#define USB_EPR_DTOG_TX              (1 << 6)  /* Bit 6: Data Toggle, for transmission transfers */
+#define USB_EPR_CTR_TX               (1 << 7)  /* Bit 7: Correct Transfer for transmission */
+#define USB_EPR_EP_KIND              (1 << 8)  /* Bit 8: Endpoint Kind */
+#define USB_EPR_EPTYPE_SHIFT         (9)       /* Bits 10-9: Endpoint type */
+#define USB_EPR_EPTYPE_MASK          (3 << USB_EPR_EPTYPE_SHIFT)
+#  define USB_EPR_EPTYPE_BULK        (0 << USB_EPR_EPTYPE_SHIFT) /* EndPoint BULK */
+#  define USB_EPR_EPTYPE_CONTROL     (1 << USB_EPR_EPTYPE_SHIFT) /* EndPoint CONTROL */
+#  define USB_EPR_EPTYPE_ISOC        (2 << USB_EPR_EPTYPE_SHIFT) /* EndPoint ISOCHRONOUS */
+#  define USB_EPR_EPTYPE_INTERRUPT   (3 << USB_EPR_EPTYPE_SHIFT) /* EndPoint INTERRUPT */
+#define USB_EPR_SETUP                (1 << 11) /* Bit 11: Setup transaction completed */
+#define USB_EPR_STATRX_SHIFT         (12)      /* Bits 13-12: Status bits, for reception transfers */
+#define USB_EPR_STATRX_MASK          (3 << USB_EPR_STATRX_SHIFT)
+#  define USB_EPR_STATRX_DIS         (0 << USB_EPR_STATRX_SHIFT) /* EndPoint RX DISabled */
+#  define USB_EPR_STATRX_STALL       (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX STALLed */
+#  define USB_EPR_STATRX_NAK         (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX NAKed */
+#  define USB_EPR_STATRX_VALID       (3 << USB_EPR_STATRX_SHIFT) /* EndPoint RX VALID */
+#  define USB_EPR_STATRX_DTOG1       (1 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit1 */
+#  define USB_EPR_STATRX_DTOG2       (2 << USB_EPR_STATRX_SHIFT) /* EndPoint RX Data TOGgle bit2 */
+#define USB_EPR_DTOG_RX              (1 << 14) /* Bit 14: Data Toggle, for reception transfers */
+#define USB_EPR_CTR_RX               (1 << 15) /* Bit 15: Correct Transfer for reception */
+
+/* USB control register */
+
+#define USB_CNTR_FRES                (1 << 0)  /* Bit 0: Force USB Reset */
+#define USB_CNTR_PDWN                (1 << 1)  /* Bit 1: Power down */
+#define USB_CNTR_LPMODE              (1 << 2)  /* Bit 2: Low-power mode */
+#define USB_CNTR_FSUSP               (1 << 3)  /* Bit 3: Force suspend */
+#define USB_CNTR_RESUME              (1 << 4)  /* Bit 4: Resume request */
+#define USB_CNTR_L1RESUME            (1 << 5)  /* Bit 5: LPM L1 Resume request */
+#define USB_CNTR_L1REQM              (1 << 7)  /* Bit 7: LPM L1 State Request Interrupt Mask */
+#define USB_CNTR_ESOFM               (1 << 8)  /* Bit 8: Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM                (1 << 9)  /* Bit 9: Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM              (1 << 10) /* Bit 10: USB Reset Interrupt Mask */
+#define USB_CNTR_SUSPM               (1 << 11) /* Bit 11: Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM               (1 << 12) /* Bit 12: Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM                (1 << 13) /* Bit 13: Error Interrupt Mask */
+#define USB_CNTR_PMAOVRNM            (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM                (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */
+
+#define USB_CNTR_ALLINTS             (USB_CNTR_L1REQM | USB_CNTR_ESOFM|USB_CNTR_SOFM | USB_CNTR_RESETM | \
+                                      USB_CNTR_SUSPM | USB_CNTR_WKUPM | USB_CNTR_ERRM | USB_CNTR_PMAOVRNM | \
+                                      USB_CNTR_CTRM)
+
+/* USB interrupt status register */
+
+#define USB_ISTR_EPID_SHIFT          (0)       /* Bits 3-0: Endpoint Identifier */
+#define USB_ISTR_EPID_MASK           (0x0f << USB_ISTR_EPID_SHIFT)
+#define USB_ISTR_DIR                 (1 << 4)  /* Bit 4: Direction of transaction */
+#define USB_ISTR_L1REQ               (1 << 7)  /* Bit 7: LPM L1 state request */
+#define USB_ISTR_ESOF                (1 << 8)  /* Bit 8: Expected Start Of Frame */
+#define USB_ISTR_SOF                 (1 << 9)  /* Bit 9: Start Of Frame */
+#define USB_ISTR_RESET               (1 << 10) /* Bit 10: USB RESET request */
+#define USB_ISTR_SUSP                (1 << 11) /* Bit 11: Suspend mode request */
+#define USB_ISTR_WKUP                (1 << 12) /* Bit 12: Wake up */
+#define USB_ISTR_ERR                 (1 << 13) /* Bit 13: Error */
+#define USB_ISTR_PMAOVRN             (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR                 (1 << 15) /* Bit 15: Correct Transfer */
+
+#define USB_ISTR_ALLINTS             (USB_ISTR_L1REQ | USB_ISTR_ESOF | USB_ISTR_SOF | USB_ISTR_RESET | \
+                                      USB_ISTR_SUSP | USB_ISTR_WKUP | USB_ISTR_ERR | USB_ISTR_PMAOVRN | \
+                                      USB_ISTR_CTR)
+
+/* USB frame number register */
+
+#define USB_FNR_FN_SHIFT             (0)       /* Bits 10-0: Frame Number */
+#define USB_FNR_FN_MASK              (0x07ff << USB_FNR_FN_SHIFT)
+#define USB_FNR_LSOF_SHIFT           (11)      /* Bits 12-11: Lost SOF */
+#define USB_FNR_LSOF_MASK            (3 << USB_FNR_LSOF_SHIFT)
+#define USB_FNR_LCK                  (1 << 13) /* Bit 13: Locked */
+#define USB_FNR_RXDM                 (1 << 14) /* Bit 14: Receive Data - Line Status */
+#define USB_FNR_RXDP                 (1 << 15) /* Bit 15: Receive Data + Line Status */
+
+/* USB device address */
+
+#define USB_DADDR_ADD_SHIFT          (0)       /* Bits 6-0: Device Address */
+#define USB_DADDR_ADD_MASK           (0x7f << USB_DADDR_ADD_SHIFT)
+#define USB_DADDR_EF                 (1 << 7)  /* Bit 7: Enable Function */
+
+/* Buffer table address */
+
+#define USB_BTABLE_SHIFT             (3)       /* Bits 15:3: Buffer Table */
+#define USB_BTABLE_MASK              (0x1fff << USB_BTABLE_SHIFT)
+
+/* Transmission buffer address */
+
+#define USB_ADDR_TX_ZERO             (1 << 0)  /* Bit 0 Must always be written as ‘0’ */
+#define USB_ADDR_TX_SHIFT            (1)       /* Bits 15-1: Transmission Buffer Address */
+#define USB_ADDR_TX_MASK             (0x7fff << USB_ADDR_ADDR_TX_SHIFT)
+
+/* Transmission byte count */
+
+#define USB_COUNT_TX_SHIFT           (0)       /* Bits 9-0: Transmission Byte Count */
+#define USB_COUNT_TX_MASK            (0x03ff << USB_COUNT_COUNT_TX_SHIFT)
+
+/* Reception buffer address */
+
+#define USB_ADDR_RX_ZERO             (1 << 0)  /* Bit 0 This bit must always be written as ‘0’ */
+#define USB_ADDR_RX_SHIFT            (1)       /* Bits 15:1 ADDRn_RX[15:1]: Reception Buffer Address */
+#define USB_ADDR_RX_MASK             (0x7fff << USB_ADDR_RX_SHIFT)
+
+/* Reception byte count */
+
+#define USB_COUNT_RX_BL_SIZE         (1 << 15) /* Bit 15: BLock SIZE. */
+#define USB_COUNT_RX_NUM_BLOCK_SHIFT (10)      /* Bits 14-10: Number of blocks */
+#define USB_COUNT_RX_NUM_BLOCK_MASK  (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT)
+#define USB_COUNT_RX_SHIFT           (0)       /* Bits 9-0: Reception Byte Count */
+#define USB_COUNT_RX_MASK            (0x03ff << USB_COUNT_RX_SHIFT)
+
+/* LPM control and status register */
+
+#define USB_LPMCSR_LPMEN             (1 << 0) /* Bit 0: LPM support enable */
+#define USB_LPMCSR_LPMACK            (1 << 1) /* Bit 1: LPM Token acknowledge enable */
+#define USB_LPMCSR_REMWAKE           (1 << 3) /* Bit 3: bRemoteWake value */
+#define USB_LPMCSR_BESL_SHIFT        (4)      /* Bits 7-4: BESL value */
+#define USB_LPMCSR_BESL_MASK         (0x0f << USB_LPMCSR_BESL_SHIFT)
+
+/* Battery charging detector */
+
+#define USB_BCDR_BCDEN               (1 << 0)  /* Bit 0: Battery charging detector (BCD) enable */
+#define USB_BCDR_DCDEN               (1 << 1)  /* Bit 1: Data contact detection (DCD) mode enable */
+#define USB_BCDR_PDEN                (1 << 2)  /* Bit 2: Primary detection (PD) mode enable */
+#define USB_BCDR_SDEN                (1 << 3)  /* Bit 3: Secondary detection (SD) mode enable */
+#define USB_BCDR_DCDET               (1 << 4)  /* Bit 4: Data contact detection (DCD) status */
+#define USB_BCDR_PDET                (1 << 5)  /* Bit 5: Primary detection (PD) status */
+#define USB_BCDR_SDET                (1 << 6)  /* Bit 6: Secondary detection (SD) status */
+#define USB_BCDR_PS2DET              (1 << 7)  /* Bit 7: DM pull-up detection status */
+#define USB_BCDR_DPPU                (1 << 15) /* Bit 15: DP pull-up control */
+
+#endif /* CONFIG_STM32L4_STM32L4X2 */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_USBDEV_H */
+
diff --git a/arch/arm/src/stm32l4/chip/stm32l4_wdg.h b/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h
similarity index 97%
rename from arch/arm/src/stm32l4/chip/stm32l4_wdg.h
rename to arch/arm/src/stm32l4/hardware/stm32l4_wdg.h
index 9c381f790a4..38831acaebc 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4_wdg.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4_wdg.h
+ * arch/arm/src/stm32l4/hardware/stm32l4_wdg.h
  *
  *   Copyright (C) 2009, 2011-2013, 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_WDG_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_WDG_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_WDG_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_WDG_H
 
 /************************************************************************************
  * Included Files
@@ -151,4 +151,4 @@
  * Public Functions
  ************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_WDG_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_WDG_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x3xx_dbgmcu.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dbgmcu.h
similarity index 95%
rename from arch/arm/src/stm32l4/chip/stm32l4x3xx_dbgmcu.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x3xx_dbgmcu.h
index aaf9c780daa..f4ce46bd548 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x3xx_dbgmcu.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dbgmcu.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x3xx_dbgmcu.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x3xx_dbgmcu.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_DBGMCU_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_DBGMCU_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_DBGMCU_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_DBGMCU_H
 
 /****************************************************************************
  * Included Files
@@ -105,4 +105,4 @@
 #define DBGMCU_APB2_TIM15STOP     (1 << 16)  /* Bit 16: TIM15 stopped when core is halted */
 #define DBGMCU_APB2_TIM16STOP     (1 << 17)  /* Bit 17: TIM16 stopped when core is halted */
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XXDBGMCU_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XXDBGMCU_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x3xx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4x3xx_dma.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h
index a00945deb96..bcefef8ca8a 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x3xx_dma.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x3xx_dma.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h
  *
  *   Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_DMA_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_DMA_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_DMA_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_DMA_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -460,4 +460,4 @@
 #define DMACHAN_LPUART_RX       DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4)
 #define DMACHAN_LPUART_TX       DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4)
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_DMA_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_DMA_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x3xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h
similarity index 94%
rename from arch/arm/src/stm32l4/chip/stm32l4x3xx_firewall.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h
index 6dbd4cd99d7..dcd754e2935 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x3xx_firewall.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x3xx_firewall.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h
  *
  *   Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
  *   Author: Sebastien Lorquet 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_FIREWALL_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_FIREWALL_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_FIREWALL_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_FIREWALL_H
 
 /************************************************************************************
  * Included Files
@@ -100,4 +100,4 @@
 #define FIREWALL_CR_VDS                 (1 << 1) /* Bit 1: Volatile data shared */
 #define FIREWALL_CR_VDE                 (1 << 2) /* Bit 2: Volatile data execution */
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_FIREWALL_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_FIREWALL_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x3xx_pinmap.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_pinmap.h
similarity index 98%
rename from arch/arm/src/stm32l4/chip/stm32l4x3xx_pinmap.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x3xx_pinmap.h
index 1db48548160..93adb335de6 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x3xx_pinmap.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x3xx_pinmap.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x3xx_pinmap.h
  *
  *   Copyright (C) 2015-2016 Sebastien Lorquet. All rights reserved.
  *   Authors: Sebastien Lorquet 
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_PINMAP_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -58,7 +58,7 @@
  *
  * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
  *
- * The driver will then automatically configre PA11 as the CAN1 RX pin.
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -598,4 +598,9 @@
 #define GPIO_LPUART1_RTS_DE_1  (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN1)
 #define GPIO_LPUART1_RTS_DE_2  (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN12)
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_PINMAP_H */
+/* USB */
+
+#define GPIO_USB_DM  (GPIO_ALT|GPIO_AF10|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_USB_DP  (GPIO_ALT|GPIO_AF10|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12)
+
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_PINMAP_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x3xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h
similarity index 95%
rename from arch/arm/src/stm32l4/chip/stm32l4x3xx_rcc.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h
index 9092e540cb2..ab5b4d181b1 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x3xx_rcc.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x3xx_rcc.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
@@ -36,8 +36,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_RCC_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_RCC_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_RCC_H
 
 /****************************************************************************************************
  * Included Files
@@ -84,6 +84,7 @@
 #define STM32L4_RCC_BDCR_OFFSET       0x0090  /* Backup domain control register */
 #define STM32L4_RCC_CSR_OFFSET        0x0094  /* Control/status register */
 #define STM32L4_RCC_CRRCR_OFFSET      0x0098  /* Clock recovery RC register */
+#define STM32L4_RCC_CCIPR2_OFFSET     0x009c  /* Peripherals independent clock configuration register 2 */
 
 /* Register Addresses *******************************************************************************/
 
@@ -118,6 +119,7 @@
 #define STM32L4_RCC_BDCR              (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET)
 #define STM32L4_RCC_CSR               (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET)
 #define STM32L4_RCC_CRRCR             (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET)
+#define STM32L4_RCC_CCIPR2            (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET)
 
 /* Register Bitfield Definitions ********************************************************************/
 
@@ -217,24 +219,24 @@
 #  define RCC_CFGR_STOPWUCK_MSI     (0 << 15) /* 0: MSI */
 #  define RCC_CFGR_STOPWUCK_HSI     (1 << 15) /* 0: HSI */
 
-#define RCC_CFGR_MCO_SHIFT         (24)      /* Bits 24-26: Microcontroller Clock Output */
-#define RCC_CFGR_MCO_MASK          (7 << RCC_CFGR_MCO_SHIFT)
-#  define RCC_CFGR_MCO_NONE        (0 << RCC_CFGR_MCO_SHIFT) /* 000: Disabled */
-#  define RCC_CFGR_MCO_SYSCLK      (1 << RCC_CFGR_MCO_SHIFT) /* 001: SYSCLK system clock selected */
-#  define RCC_CFGR_MCO_MSI         (2 << RCC_CFGR_MCO_SHIFT) /* 010: MSI clock selected */
-#  define RCC_CFGR_MCO_HSI         (3 << RCC_CFGR_MCO_SHIFT) /* 011: HSI clock selected */
-#  define RCC_CFGR_MCO_HSE         (4 << RCC_CFGR_MCO_SHIFT) /* 100: HSE clock selected */
-#  define RCC_CFGR_MCO_PLL         (5 << RCC_CFGR_MCO_SHIFT) /* 101: Main PLL selected  */
-#  define RCC_CFGR_MCO_LSI         (6 << RCC_CFGR_MCO_SHIFT) /* 110: LSI clock selected */
-#  define RCC_CFGR_MCO_LSE         (7 << RCC_CFGR_MCO_SHIFT) /* 111: LSE clock selected */
+#define RCC_CFGR_MCO_SHIFT          (24)      /* Bits 24-26: Microcontroller Clock Output */
+#define RCC_CFGR_MCO_MASK           (7 << RCC_CFGR_MCO_SHIFT)
+#  define RCC_CFGR_MCO_NONE         (0 << RCC_CFGR_MCO_SHIFT) /* 000: Disabled */
+#  define RCC_CFGR_MCO_SYSCLK       (1 << RCC_CFGR_MCO_SHIFT) /* 001: SYSCLK system clock selected */
+#  define RCC_CFGR_MCO_MSI          (2 << RCC_CFGR_MCO_SHIFT) /* 010: MSI clock selected */
+#  define RCC_CFGR_MCO_HSI          (3 << RCC_CFGR_MCO_SHIFT) /* 011: HSI clock selected */
+#  define RCC_CFGR_MCO_HSE          (4 << RCC_CFGR_MCO_SHIFT) /* 100: HSE clock selected */
+#  define RCC_CFGR_MCO_PLL          (5 << RCC_CFGR_MCO_SHIFT) /* 101: Main PLL selected  */
+#  define RCC_CFGR_MCO_LSI          (6 << RCC_CFGR_MCO_SHIFT) /* 110: LSI clock selected */
+#  define RCC_CFGR_MCO_LSE          (7 << RCC_CFGR_MCO_SHIFT) /* 111: LSE clock selected */
 
-#define RCC_CFGR_MCOPRE_SHIFT      (28)      /* Bits 28-30: MCO prescaler */
-#define RCC_CFGR_MCOPRE_MASK       (7 << RCC_CFGR_MCOPRE_SHIFT)
-#  define RCC_CFGR_MCOPRE_NONE     (0 << RCC_CFGR_MCOPRE_SHIFT) /* 000: no division */
-#  define RCC_CFGR_MCOPRE_DIV2     (1 << RCC_CFGR_MCOPRE_SHIFT) /* 001: division by 2 */
-#  define RCC_CFGR_MCOPRE_DIV4     (2 << RCC_CFGR_MCOPRE_SHIFT) /* 010: division by 4 */
-#  define RCC_CFGR_MCOPRE_DIV8     (3 << RCC_CFGR_MCOPRE_SHIFT) /* 011: division by 8 */
-#  define RCC_CFGR_MCOPRE_DIV16    (4 << RCC_CFGR_MCOPRE_SHIFT) /* 100: division by 16 */
+#define RCC_CFGR_MCOPRE_SHIFT       (28)      /* Bits 28-30: MCO prescaler */
+#define RCC_CFGR_MCOPRE_MASK        (7 << RCC_CFGR_MCOPRE_SHIFT)
+#  define RCC_CFGR_MCOPRE_NONE      (0 << RCC_CFGR_MCOPRE_SHIFT) /* 000: no division */
+#  define RCC_CFGR_MCOPRE_DIV2      (1 << RCC_CFGR_MCOPRE_SHIFT) /* 001: division by 2 */
+#  define RCC_CFGR_MCOPRE_DIV4      (2 << RCC_CFGR_MCOPRE_SHIFT) /* 010: division by 4 */
+#  define RCC_CFGR_MCOPRE_DIV8      (3 << RCC_CFGR_MCOPRE_SHIFT) /* 011: division by 8 */
+#  define RCC_CFGR_MCOPRE_DIV16     (4 << RCC_CFGR_MCOPRE_SHIFT) /* 100: division by 16 */
 
 /* PLL configuration register */
 
@@ -705,7 +707,7 @@
 
 #define RCC_CCIPR_CLK48SEL_SHIFT      (26)
 #define RCC_CCIPR_CLK48SEL_MASK       (3 << RCC_CCIPR_CLK48SEL_SHIFT)
-#  define RCC_CCIPR_CLK48SEL_NONE     (0 << RCC_CCIPR_CLK48SEL_SHIFT)
+#  define RCC_CCIPR_CLK48SEL_HSI48    (0 << RCC_CCIPR_CLK48SEL_SHIFT)
 #  define RCC_CCIPR_CLK48SEL_PLLSAI1  (1 << RCC_CCIPR_CLK48SEL_SHIFT)
 #  define RCC_CCIPR_CLK48SEL_PLLMAIN  (2 << RCC_CCIPR_CLK48SEL_SHIFT)
 #  define RCC_CCIPR_CLK48SEL_MSI      (3 << RCC_CCIPR_CLK48SEL_SHIFT)
@@ -785,5 +787,14 @@
 #define RCC_CRRCR_HSI48ON           (1 << 0)  /* Bit 0: HSI48 clock enable */
 #define RCC_CRRCR_HSI48RDY          (1 << 1)  /* Bit 1: HSI48 clock ready flag */
 
+/* Peripheral Independent Clock Configuration 2 register (only on STM32L45x and STM32L46x) */
+
+#define RCC_CCIPR2_I2C4SEL_SHIFT    (0)    /* Bits 0-1: I2C4 clock source selection */
+#define RCC_CCIPR2_I2C4SEL_MASK     (3 << RCC_CCIPR2_I2C4SEL_SHIFT)
+#  define RCC_CCIPR2_I2C4SEL_PCLK   (0 << RCC_CCIPR2_I2C4SEL_SHIFT)
+#  define RCC_CCIPR2_I2C4SEL_SYSCLK (1 << RCC_CCIPR2_I2C4SEL_SHIFT)
+#  define RCC_CCIPR2_I2C4SEL_HSI    (2 << RCC_CCIPR2_I2C4SEL_SHIFT)
+
 #endif /* CONFIG_STM32L4_STM32L4X3 */
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_RCC_H */
+
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x3xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h
similarity index 97%
rename from arch/arm/src/stm32l4/chip/stm32l4x3xx_syscfg.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h
index 446ce1811a1..e3c41fb2c07 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x3xx_syscfg.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x3xx_syscfg.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -179,4 +179,4 @@
 #define SYSCFG_SKR_MASK               (0xFF << SYSCFG_SKR_SHIFT)
 
 #endif /* CONFIG_STM32L4_STM32L4X3 */
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X3XX_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_SYSCFG_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x5xx_dbgmcu.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dbgmcu.h
similarity index 96%
rename from arch/arm/src/stm32l4/chip/stm32l4x5xx_dbgmcu.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x5xx_dbgmcu.h
index 27afd39fe65..5c89eee3194 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x5xx_dbgmcu.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dbgmcu.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x5xx_dbgmcu.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x5xx_dbgmcu.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_DBGMCU_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_DBGMCU_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_DBGMCU_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_DBGMCU_H
 
 /****************************************************************************
  * Included Files
@@ -110,4 +110,4 @@
 #define DBGMCU_APB2_TIM16STOP     (1 << 17)  /* Bit 17: TIM16 stopped when core is halted */
 #define DBGMCU_APB2_TIM17STOP     (1 << 18)  /* Bit 18: TIM17 stopped when core is halted */
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XXDBGMCU_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XXDBGMCU_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x5xx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4x5xx_dma.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h
index 2eceae8292e..2c3fa4fd7c1 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x5xx_dma.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x6xx_dma.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_DMA_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_DMA_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_DMA_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_DMA_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -482,4 +482,4 @@
 #define DMACHAN_LPUART_RX       DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4)
 #define DMACHAN_LPUART_TX       DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4)
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_DMA_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_DMA_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x5xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h
similarity index 95%
rename from arch/arm/src/stm32l4/chip/stm32l4x5xx_firewall.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h
index 878a04ee687..6cd2433c971 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x5xx_firewall.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x5xx_firewall.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_FIREWALL_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_FIREWALL_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_FIREWALL_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_FIREWALL_H
 
 /************************************************************************************
  * Included Files
@@ -109,4 +109,4 @@
 #define FIREWALL_CR_VDS                 (1 << 1) /* Bit 1: Volatile data shared */
 #define FIREWALL_CR_VDE                 (1 << 2) /* Bit 2: Volatile data execution */
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_FIREWALL_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_FIREWALL_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x5xx_otgfs.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4x5xx_otgfs.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h
index efdde6fcc13..e2af3a17d6d 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x5xx_otgfs.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x5xx_otgfs.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
@@ -36,8 +36,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_OTGFS_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_OTGFS_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_OTGFS_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_OTGFS_H
 
 /****************************************************************************************************
  * Included Files
@@ -944,4 +944,4 @@
 #define OTGFS_PCGCCTL_SUSP              (1 << 7)  /* Bit 7: Deep Sleep */
                                                   /* Bits 8-31: Reserved, must be kept at reset value */
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_OTGFS_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_OTGFS_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x5xx_pinmap.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_pinmap.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4x5xx_pinmap.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x5xx_pinmap.h
index 93b48fb559b..77b8c431c25 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x5xx_pinmap.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x5xx_pinmap.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x5xx_pinmap.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2015-2016 Sebastien Lorquet. All rights reserved.
@@ -34,8 +34,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_PINMAP_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -58,7 +58,7 @@
  *
  * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
  *
- * The driver will then automatically configre PA11 as the CAN1 RX pin.
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -784,4 +784,4 @@
 #define GPIO_LPUART1_RTS_DE_1  (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN12)
 #define GPIO_LPUART1_RTS_DE_2  (GPIO_ALT|GPIO_AF8 |GPIO_PORTG|GPIO_PIN6)
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_PINMAP_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x5xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4x5xx_rcc.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h
index 412c786883d..42e36229a07 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x5xx_rcc.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
@@ -35,8 +35,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_RCC_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_RCC_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_RCC_H
 
 /****************************************************************************************************
  * Included Files
@@ -707,4 +707,4 @@
 #define RCC_CSR_LPWRRSTF            (1 << 31) /* Bit 31: Low-Power reset flag */
 
 #endif /* CONFIG_STM32L4_STM32L4X5 */
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_RCC_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x5xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h
similarity index 97%
rename from arch/arm/src/stm32l4/chip/stm32l4x5xx_syscfg.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h
index 2078261227e..f1bf322e341 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x5xx_syscfg.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x5xx_syscfg.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -174,4 +174,4 @@
 #define SYSCFG_CFGR2_SPF              (1 <<  8) /* Bit  8: SRAM2 parity error flag */
 
 #endif /* CONFIG_STM32L4_STM32L4X5 */
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X5XX_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_SYSCFG_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_dbgmcu.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h
similarity index 96%
rename from arch/arm/src/stm32l4/chip/stm32l4x6xx_dbgmcu.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h
index 09438cda7b9..4e8acff1baf 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_dbgmcu.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x6xx_dbgmcu.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_DBGMCU_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_DBGMCU_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_DBGMCU_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_DBGMCU_H
 
 /****************************************************************************
  * Included Files
@@ -116,4 +116,4 @@
 #define DBGMCU_APB2_TIM16STOP     (1 << 17)  /* Bit 17: TIM16 stopped when core is halted */
 #define DBGMCU_APB2_TIM17STOP     (1 << 18)  /* Bit 18: TIM17 stopped when core is halted */
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XXDBGMCU_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XXDBGMCU_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4x6xx_dma.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h
index cf90c3e18dc..3ff7e3cbeec 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_dma.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x6xx_dma.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h
  *
  *   Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_DMA_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_DMA_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_DMA_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_DMA_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -501,4 +501,4 @@
 #define DMACHAN_LPUART_RX       DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4)
 #define DMACHAN_LPUART_TX       DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4)
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_DMA_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_DMA_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h
similarity index 95%
rename from arch/arm/src/stm32l4/chip/stm32l4x6xx_firewall.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h
index 5a422d419fd..c6cb47c8025 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_firewall.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x6xx_firewall.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h
  *
  *   Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
  *   Author: Sebastien Lorquet 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_FIREWALL_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_FIREWALL_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_FIREWALL_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_FIREWALL_H
 
 /************************************************************************************
  * Included Files
@@ -115,4 +115,4 @@
 #define FIREWALL_CR_VDS                 (1 << 1) /* Bit 1: Volatile data shared */
 #define FIREWALL_CR_VDE                 (1 << 2) /* Bit 2: Volatile data execution */
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_FIREWALL_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_FIREWALL_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h
index b2843a0b4a5..1eb229d297f 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x6xx_otgfs.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h
  *
  *   Copyright (C) 2012, 2014-2015 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
@@ -36,8 +36,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_OTGFS_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_OTGFS_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_OTGFS_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_OTGFS_H
 
 /****************************************************************************************************
  * Included Files
@@ -949,4 +949,4 @@
 #define OTGFS_PCGCCTL_SUSP              (1 << 7)  /* Bit 7: Deep Sleep */
                                                   /* Bits 8-31: Reserved, must be kept at reset value */
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_OTGFS_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_OTGFS_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_pinmap.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x6xx_pinmap.h
index 13e659eee55..93cd5b29d1a 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x6xx_pinmap.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x6xx_pinmap.h
  *
  *   Copyright (C) 2015-2016 Sebastien Lorquet. All rights reserved.
  *   Author: Sebastien Lorquet 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_PINMAP_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -57,7 +57,7 @@
  *
  * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
  *
- * The driver will then automatically configre PA11 as the CAN1 RX pin.
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -902,4 +902,4 @@
 #define GPIO_LPUART1_RTS_DE_1  (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN12)
 #define GPIO_LPUART1_RTS_DE_2  (GPIO_ALT|GPIO_AF8 |GPIO_PORTG|GPIO_PIN6)
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_PINMAP_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h
index 416e75bc327..eea6a8a68e3 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
@@ -35,8 +35,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_RCC_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_RCC_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_RCC_H
 
 /****************************************************************************************************
  * Included Files
@@ -718,7 +718,11 @@
 
 #define RCC_CCIPR_CLK48SEL_SHIFT      (26)
 #define RCC_CCIPR_CLK48SEL_MASK       (3 << RCC_CCIPR_CLK48SEL_SHIFT)
+#if defined(CONFIG_STM32L4_STM32L496XX)
+#  define RCC_CCIPR_CLK48SEL_HSI48    (0 << RCC_CCIPR_CLK48SEL_SHIFT)
+#else
 #  define RCC_CCIPR_CLK48SEL_NONE     (0 << RCC_CCIPR_CLK48SEL_SHIFT)
+#endif
 #  define RCC_CCIPR_CLK48SEL_PLLSAI1  (1 << RCC_CCIPR_CLK48SEL_SHIFT)
 #  define RCC_CCIPR_CLK48SEL_PLLMAIN  (2 << RCC_CCIPR_CLK48SEL_SHIFT)
 #  define RCC_CCIPR_CLK48SEL_MSI      (3 << RCC_CCIPR_CLK48SEL_SHIFT)
@@ -807,4 +811,4 @@
 #  define RCC_CCIPR2_I2C4SEL_HSI       (2 << RCC_CCIPR2_I2C4SEL_SHIFT)
 
 #endif /* CONFIG_STM32L4_STM32L4X6 */
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_RCC_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h
similarity index 98%
rename from arch/arm/src/stm32l4/chip/stm32l4x6xx_syscfg.h
rename to arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h
index e7446cfb29c..4625ac8a293 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_syscfg.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x6xx_syscfg.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -188,4 +188,4 @@
 /* There is one bit per SRAM2 page (32 to 63) */
 
 #endif /* CONFIG_STM32L4_STM32L4X6 */
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_SYSCFG_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4xrxx_dbgmcu.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dbgmcu.h
similarity index 96%
rename from arch/arm/src/stm32l4/chip/stm32l4xrxx_dbgmcu.h
rename to arch/arm/src/stm32l4/hardware/stm32l4xrxx_dbgmcu.h
index fdc5a54ceea..2e92797159c 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4xrxx_dbgmcu.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dbgmcu.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4xrxx_dbgmcu.h
+ * arch/arm/src/stm32l4/hardware/stm32l4xrxx_dbgmcu.h
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_DBGMCU_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_DBGMCU_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_DBGMCU_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_DBGMCU_H
 
 /****************************************************************************
  * Included Files
@@ -110,4 +110,4 @@
 #define DBGMCU_APB2_TIM16STOP     (1 << 17)  /* Bit 17: TIM16 stopped when core is halted */
 #define DBGMCU_APB2_TIM17STOP     (1 << 18)  /* Bit 18: TIM17 stopped when core is halted */
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXXDBGMCU_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXXDBGMCU_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4xrxx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4xrxx_dma.h
rename to arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h
index c0bba35c673..2c82fd4eb3d 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4xrxx_dma.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4xrxx_dma.h
+ * arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h
  *
  *   Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_DMA_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_DMA_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_DMA_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_DMA_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -504,4 +504,4 @@
 #define DMACHAN_LPUART_RX       DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4)
 #define DMACHAN_LPUART_TX       DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4)
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_DMA_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_DMA_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4xrxx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h
similarity index 94%
rename from arch/arm/src/stm32l4/chip/stm32l4xrxx_firewall.h
rename to arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h
index 07714edc87c..f16208cdc0c 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4xrxx_firewall.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4xrxx_firewall.h
+ * arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h
  *
  *   Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
  *   Author: Sebastien Lorquet 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_FIREWALL_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_FIREWALL_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_FIREWALL_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_FIREWALL_H
 
 /************************************************************************************
  * Included Files
@@ -107,4 +107,4 @@
 #define FIREWALL_CR_VDS                 (1 << 1) /* Bit 1: Volatile data shared */
 #define FIREWALL_CR_VDE                 (1 << 2) /* Bit 2: Volatile data execution */
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_FIREWALL_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_FIREWALL_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4xrxx_pinmap.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_pinmap.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4xrxx_pinmap.h
rename to arch/arm/src/stm32l4/hardware/stm32l4xrxx_pinmap.h
index af862623df5..f64565f0cdd 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4xrxx_pinmap.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_pinmap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4xrxx_pinmap.h
+ * arch/arm/src/stm32l4/hardware/stm32l4xrxx_pinmap.h
  *
  *   Copyright (C) 2015-2016 Sebastien Lorquet. All rights reserved.
  *   Author: Sebastien Lorquet 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_PINMAP_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_PINMAP_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_PINMAP_H
 
 /************************************************************************************
  * Included Files
@@ -57,7 +57,7 @@
  *
  * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
  *
- * The driver will then automatically configre PA11 as the CAN1 RX pin.
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -847,4 +847,4 @@
 #define GPIO_LPUART1_RTS_DE_1  (GPIO_ALT|GPIO_AF8 |GPIO_PORTB|GPIO_PIN12)
 #define GPIO_LPUART1_RTS_DE_2  (GPIO_ALT|GPIO_AF8 |GPIO_PORTG|GPIO_PIN6)
 
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_PINMAP_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_PINMAP_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4xrxx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h
similarity index 99%
rename from arch/arm/src/stm32l4/chip/stm32l4xrxx_rcc.h
rename to arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h
index 07448e2aa5a..49b080c6f1d 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4xrxx_rcc.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h
+ * arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h
  *
  *   Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
@@ -36,8 +36,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_RCC_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4X6XX_RCC_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_RCC_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_RCC_H
 
 /****************************************************************************************************
  * Included Files
@@ -755,7 +755,7 @@
 
 #define RCC_CCIPR_CLK48SEL_SHIFT      (26)
 #define RCC_CCIPR_CLK48SEL_MASK       (3 << RCC_CCIPR_CLK48SEL_SHIFT)
-#  define RCC_CCIPR_CLK48SEL_NONE     (0 << RCC_CCIPR_CLK48SEL_SHIFT)
+#  define RCC_CCIPR_CLK48SEL_HSI48    (0 << RCC_CCIPR_CLK48SEL_SHIFT)
 #  define RCC_CCIPR_CLK48SEL_PLLSAI1  (1 << RCC_CCIPR_CLK48SEL_SHIFT)
 #  define RCC_CCIPR_CLK48SEL_PLLMAIN  (2 << RCC_CCIPR_CLK48SEL_SHIFT)
 #  define RCC_CCIPR_CLK48SEL_MSI      (3 << RCC_CCIPR_CLK48SEL_SHIFT)
@@ -863,4 +863,4 @@
 
 
 #endif /* CONFIG_STM32L4_STM32L4XR */
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_RCC_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_RCC_H */
diff --git a/arch/arm/src/stm32l4/chip/stm32l4xrxx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h
similarity index 98%
rename from arch/arm/src/stm32l4/chip/stm32l4xrxx_syscfg.h
rename to arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h
index f9142e4dade..d92924e240f 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4xrxx_syscfg.h
+++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/stm32l4/chip/stm32l4xrxx_syscfg.h
+ * arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h
  *
  *   Copyright (C) 2014-2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_SYSCFG_H
-#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_SYSCFG_H
+#ifndef __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_SYSCFG_H
 
 /****************************************************************************************************
  * Included Files
@@ -190,4 +190,4 @@
 /* There is one bit per SRAM2 page (32 to 63) */
 
 #endif /* CONFIG_STM32L4_STM32L4XR */
-#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4XRXX_SYSCFG_H */
+#endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_SYSCFG_H */
diff --git a/arch/arm/src/stm32l4/stm32l4_adc.h b/arch/arm/src/stm32l4/stm32l4_adc.h
index d75aad0d39a..bd03f3669f8 100644
--- a/arch/arm/src/stm32l4/stm32l4_adc.h
+++ b/arch/arm/src/stm32l4/stm32l4_adc.h
@@ -46,7 +46,7 @@
 #include 
 #include 
 #include "chip.h"
-#include "chip/stm32l4_adc.h"
+#include "hardware/stm32l4_adc.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32l4/stm32l4_can.h b/arch/arm/src/stm32l4/stm32l4_can.h
index 53aeea817d2..a493743bc45 100644
--- a/arch/arm/src/stm32l4/stm32l4_can.h
+++ b/arch/arm/src/stm32l4/stm32l4_can.h
@@ -47,7 +47,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32l4_can.h"
+#include "hardware/stm32l4_can.h"
 
 #include 
 
diff --git a/arch/arm/src/stm32l4/stm32l4_comp.h b/arch/arm/src/stm32l4/stm32l4_comp.h
index 36cbcfc6c17..939b983140d 100644
--- a/arch/arm/src/stm32l4/stm32l4_comp.h
+++ b/arch/arm/src/stm32l4/stm32l4_comp.h
@@ -44,7 +44,7 @@
 
 #include 
 
-#include "chip/stm32l4_comp.h"
+#include "hardware/stm32l4_comp.h"
 
 /************************************************************************************
  * Public Types
diff --git a/arch/arm/src/stm32l4/stm32l4_dac.h b/arch/arm/src/stm32l4/stm32l4_dac.h
index b6e370f0e02..38867245992 100644
--- a/arch/arm/src/stm32l4/stm32l4_dac.h
+++ b/arch/arm/src/stm32l4/stm32l4_dac.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32l4_dac.h"
+#include "hardware/stm32l4_dac.h"
 
 #include 
 
diff --git a/arch/arm/src/stm32l4/stm32l4_dbgmcu.h b/arch/arm/src/stm32l4/stm32l4_dbgmcu.h
index e698354b9e9..2dbb6792b70 100644
--- a/arch/arm/src/stm32l4/stm32l4_dbgmcu.h
+++ b/arch/arm/src/stm32l4/stm32l4_dbgmcu.h
@@ -46,13 +46,13 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32L4_STM32L4X3)
-#  include "chip/stm32l4x3xx_dbgmcu.h"
+#  include "hardware/stm32l4x3xx_dbgmcu.h"
 #elif defined(CONFIG_STM32L4_STM32L4X5)
-#  include "chip/stm32l4x5xx_dbgmcu.h"
+#  include "hardware/stm32l4x5xx_dbgmcu.h"
 #elif defined(CONFIG_STM32L4_STM32L4X6)
-#  include "chip/stm32l4x6xx_dbgmcu.h"
+#  include "hardware/stm32l4x6xx_dbgmcu.h"
 #elif defined(CONFIG_STM32L4_STM32L4XR)
-#  include "chip/stm32l4xrxx_dbgmcu.h"
+#  include "hardware/stm32l4xrxx_dbgmcu.h"
 #else
 #  error "Unsupported STM32L4 chip"
 #endif
diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/stm32l4_dfsdm.h
index b751f187767..ed53a891994 100644
--- a/arch/arm/src/stm32l4/stm32l4_dfsdm.h
+++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 #include "chip.h"
-#include "chip/stm32l4_dfsdm.h"
+#include "hardware/stm32l4_dfsdm.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32l4/stm32l4_dma.h b/arch/arm/src/stm32l4/stm32l4_dma.h
index 06f4210f35b..be5dc34fad8 100644
--- a/arch/arm/src/stm32l4/stm32l4_dma.h
+++ b/arch/arm/src/stm32l4/stm32l4_dma.h
@@ -50,13 +50,13 @@
 /* Include the correct DMA register definitions for this STM32 family */
 
 #if defined(CONFIG_STM32L4_STM32L4X3)
-#  include "chip/stm32l4x3xx_dma.h"
+#  include "hardware/stm32l4x3xx_dma.h"
 #elif defined(CONFIG_STM32L4_STM32L4X5)
-#  include "chip/stm32l4x5xx_dma.h"
+#  include "hardware/stm32l4x5xx_dma.h"
 #elif defined(CONFIG_STM32L4_STM32L4X6)
-#  include "chip/stm32l4x6xx_dma.h"
+#  include "hardware/stm32l4x6xx_dma.h"
 #elif defined(CONFIG_STM32L4_STM32L4XR)
-#  include "chip/stm32l4xrxx_dma.h"
+#  include "hardware/stm32l4xrxx_dma.h"
 #else
 #  error "Unsupported STM32L4 chip"
 #endif
diff --git a/arch/arm/src/stm32l4/stm32l4_exti.h b/arch/arm/src/stm32l4/stm32l4_exti.h
index d50e9e48a69..49a8fe3206f 100644
--- a/arch/arm/src/stm32l4/stm32l4_exti.h
+++ b/arch/arm/src/stm32l4/stm32l4_exti.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32l4_exti.h"
+#include "hardware/stm32l4_exti.h"
 
 /************************************************************************************
  * Public Data
diff --git a/arch/arm/src/stm32l4/stm32l4_exti_comp.c b/arch/arm/src/stm32l4/stm32l4_exti_comp.c
index 6cc2d8048d9..e4cb7e15d18 100644
--- a/arch/arm/src/stm32l4/stm32l4_exti_comp.c
+++ b/arch/arm/src/stm32l4/stm32l4_exti_comp.c
@@ -45,7 +45,7 @@
 #include "up_arch.h"
 #include "stm32l4_comp.h"
 #include "stm32l4_exti.h"
-#include "chip/stm32l4_exti.h"
+#include "hardware/stm32l4_exti.h"
 
 /****************************************************************************
  * Private Types
diff --git a/arch/arm/src/stm32l4/stm32l4_firewall.c b/arch/arm/src/stm32l4/stm32l4_firewall.c
index 810acfd3f1d..30378c858f4 100644
--- a/arch/arm/src/stm32l4/stm32l4_firewall.c
+++ b/arch/arm/src/stm32l4/stm32l4_firewall.c
@@ -44,7 +44,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/stm32l4_syscfg.h"
+#include "hardware/stm32l4_syscfg.h"
 
 #include "stm32l4_firewall.h"
 
diff --git a/arch/arm/src/stm32l4/stm32l4_firewall.h b/arch/arm/src/stm32l4/stm32l4_firewall.h
index 3f8f585acf8..7ef3a19a210 100644
--- a/arch/arm/src/stm32l4/stm32l4_firewall.h
+++ b/arch/arm/src/stm32l4/stm32l4_firewall.h
@@ -48,13 +48,13 @@
 /* Include the correct firewall register definitions for this STM32L4 family */
 
 #if defined(CONFIG_STM32L4_STM32L4X3)
-#  include "chip/stm32l4x3xx_firewall.h"
+#  include "hardware/stm32l4x3xx_firewall.h"
 #elif defined(CONFIG_STM32L4_STM32L4X5)
-#  include "chip/stm32l4x5xx_firewall.h"
+#  include "hardware/stm32l4x5xx_firewall.h"
 #elif defined(CONFIG_STM32L4_STM32L4X6)
-#  include "chip/stm32l4x6xx_firewall.h"
+#  include "hardware/stm32l4x6xx_firewall.h"
 #elif defined(CONFIG_STM32L4_STM32L4XR)
-#  include "chip/stm32l4xrxx_firewall.h"
+#  include "hardware/stm32l4xrxx_firewall.h"
 #else
 #  error "Unsupported STM32L4 chip"
 #endif
diff --git a/arch/arm/src/stm32l4/stm32l4_flash.h b/arch/arm/src/stm32l4/stm32l4_flash.h
index 6316232cab4..b33c28704bf 100644
--- a/arch/arm/src/stm32l4/stm32l4_flash.h
+++ b/arch/arm/src/stm32l4/stm32l4_flash.h
@@ -43,7 +43,7 @@
  ************************************************************************************/
 
 #include 
-#include "chip/stm32l4_flash.h"
+#include "hardware/stm32l4_flash.h"
 
 /************************************************************************************
  * Public Functions
diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.c b/arch/arm/src/stm32l4/stm32l4_gpio.c
index a33b88c08fe..8715b905749 100644
--- a/arch/arm/src/stm32l4/stm32l4_gpio.c
+++ b/arch/arm/src/stm32l4/stm32l4_gpio.c
@@ -55,7 +55,7 @@
 #include "chip.h"
 #include "stm32l4_gpio.h"
 
-#include "chip/stm32l4_syscfg.h"
+#include "hardware/stm32l4_syscfg.h"
 
 /****************************************************************************
  * Public Data
diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.h b/arch/arm/src/stm32l4/stm32l4_gpio.h
index d9c20e67ca3..c7ceb75a628 100644
--- a/arch/arm/src/stm32l4/stm32l4_gpio.h
+++ b/arch/arm/src/stm32l4/stm32l4_gpio.h
@@ -56,7 +56,7 @@
 
 #if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
     defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
-#  include "chip/stm32l4_gpio.h"
+#  include "hardware/stm32l4_gpio.h"
 #else
 #  error "Unsupported STM32L4 chip"
 #endif
diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.c b/arch/arm/src/stm32l4/stm32l4_hsi48.c
new file mode 100644
index 00000000000..11234c1fd47
--- /dev/null
+++ b/arch/arm/src/stm32l4/stm32l4_hsi48.c
@@ -0,0 +1,181 @@
+/****************************************************************************
+ *  arch/arm/src/stm32l4/stm32l4_hsi48.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include "up_arch.h"
+#include "chip.h"
+#include "stm32l4_rcc.h"
+#include "hardware/stm32l4_crs.h"
+
+#include "stm32l4_hsi48.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32l4_enable_hsi48
+ *
+ * Description:
+ *   On STM32L4X3, STM32L496xx/4A6xx and STM32L4XR devices only, the HSI48
+ *   clock signal is generated from an internal 48 MHz RC oscillator and can
+ *   be used directly as a system clock or divided and be used as PLL input.
+ *
+ *   The internal 48MHz RC oscillator is mainly dedicated to provide a high
+ *   precision clock to the USB peripheral by means of a special Clock
+ *   Recovery System (CRS) circuitry, which could use the USB SOF signal or
+ *   the LSE or an external signal to automatically adjust the oscillator
+ *   frequency on-fly, in a very small steps. This oscillator can also be
+ *   used as a system clock source when the system is in run mode; it will
+ *   be disabled as soon as the system enters in Stop or Standby mode. When
+ *   the CRS is not used, the HSI48 RC oscillator runs on its default
+ *   frequency which is subject to manufacturing process variations.
+ *
+ * Input Parameters:
+ *   Identifies the syncrhonization source for the HSI48.  When used as the
+ *   USB source clock, this must be set to SYNCSRC_USB.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void stm32l4_enable_hsi48(enum syncsrc_e syncsrc)
+{
+  uint32_t regval;
+
+  /* Enable the HSI48 clock.
+   *
+   * The HSI48 RC can be switched on and off using the HSI48ON bit in the
+   * Clock control register (RCC_CRRCR).
+   *
+   * The USB clock may be derived from either the PLL clock or from the
+   * HSI48 clock.  This oscillator will be also automatically enabled (by
+   * hardware forcing HSI48ON bit to one) as soon as it is chosen as a clock
+   * source for the USB and the peripheral is
+   * enabled.
+   */
+
+  regval  = getreg32(STM32L4_RCC_CRRCR);
+  regval |= RCC_CRRCR_HSI48ON;
+  putreg32(regval, STM32L4_RCC_CRRCR);
+
+  /* Wait for the HSI48 clock to stabilize */
+
+  while ((getreg32(STM32L4_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0);
+
+  /* Return if no synchronization */
+
+  if (syncsrc == SYNCSRC_NONE)
+    {
+      return;
+    }
+
+  /* The CRS synchronization (SYNC) source, selectable through the CRS_CFGR
+   * register, can be the signal from the external CRS_SYNC pin, the LSE
+   * clock or the USB SOF signal.
+   */
+
+  regval = getreg32(STM32L4_CRS_CFGR);
+  regval &= ~CRS_CFGR_SYNCSRC_MASK;
+
+  switch (syncsrc)
+    {
+      default:
+      case SYNCSRC_GPIO: /* GPIO selected as SYNC signal source */
+        regval |= CRS_CFGR_SYNCSRC_GPIO;
+        break;
+
+      case SYNCSRC_LSE:  /* LSE selected as SYNC signal source */
+        regval |= CRS_CFGR_SYNCSRC_LSE;
+        break;
+
+      case SYNCSRC_USB:  /* USB SOF selected as SYNC signal source */
+        regval |= CRS_CFGR_SYNCSRC_USBSOF;
+        break;
+    }
+
+  putreg32(regval, STM32L4_CRS_CFGR);
+
+  /* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic
+   * hardware adjustment of TRIM bits according to the measured frequency
+   * error between the selected SYNC event. Also enable CEN bit to enable
+   * frequency error counter and SYNC events.
+   */
+
+  regval  = getreg32(STM32L4_CRS_CR);
+  regval |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN;
+  putreg32(regval, STM32L4_CRS_CR);
+}
+
+/****************************************************************************
+ * Name: stm32l4_disable_hsi48
+ *
+ * Description:
+ *   Disable the HSI48 clock.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void stm32l4_disable_hsi48(void)
+{
+  uint32_t regval;
+
+  /* Disable the HSI48 clock */
+
+  regval  = getreg32(STM32L4_RCC_CRRCR);
+  regval &= ~RCC_CRRCR_HSI48ON;
+  putreg32(regval, STM32L4_RCC_CRRCR);
+
+  /* Set other registers to the default settings. */
+
+  regval  = getreg32(STM32L4_CRS_CFGR);
+  regval &= ~CRS_CFGR_SYNCSRC_MASK;
+  putreg32(regval, STM32L4_CRS_CFGR);
+
+  regval  = getreg32(STM32L4_CRS_CR);
+  regval &= ~CRS_CR_AUTOTRIMEN;
+  putreg32(regval, STM32L4_CRS_CR);
+}
diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.h b/arch/arm/src/stm32l4/stm32l4_hsi48.h
new file mode 100644
index 00000000000..7e62dabc84e
--- /dev/null
+++ b/arch/arm/src/stm32l4/stm32l4_hsi48.h
@@ -0,0 +1,110 @@
+/****************************************************************************
+ * arch/arm/src/stm32l4/stm32l4_hsi48.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *           Alan Carvalho de Assis 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_HSI48_H
+#define __ARCH_ARM_SRC_STM32L4_STM32L4_HSI48_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#ifdef CONFIG_STM32L4_HAVE_HSI48
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+enum syncsrc_e
+{
+  SYNCSRC_NONE = 0, /* No SYNC signal */
+  SYNCSRC_GPIO,     /* GPIO selected as SYNC signal source */
+  SYNCSRC_LSE,      /* LSE selected as SYNC signal source */
+  SYNCSRC_USB,      /* USB SOF selected as SYNC signal source */
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32l4_enable_hsi48
+ *
+ * Description:
+ *   On STM32L4X3, STM32L496xx/4A6xx and STM32L4XR devices only, the HSI48
+ *   clock signal is generated from an internal 48 MHz RC oscillator and can
+ *   be used directly as a system clock or divided and be used as PLL input.
+ *
+ *   The internal 48MHz RC oscillator is mainly dedicated to provide a high
+ *   precision clock to the USB peripheral by means of a special Clock
+ *   Recovery System (CRS) circuitry, which could use the USB SOF signal or
+ *   the LSE or an external signal to automatically adjust the oscillator
+ *   frequency on-fly, in a very small steps. This oscillator can also be
+ *   used as a system clock source when the system is in run mode; it will
+ *   be disabled as soon as the system enters in Stop or Standby mode. When
+ *   the CRS is not used, the HSI48 RC oscillator runs on its default
+ *   frequency which is subject to manufacturing process variations.
+ *
+ * Input Parameters:
+ *   Identifies the syncrhonization source for the HSI48.  When used as the
+ *   USB source clock, this must be set to SYNCSRC_USB.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void stm32l4_enable_hsi48(enum syncsrc_e syncsrc);
+
+/****************************************************************************
+ * Name: stm32l4_disable_hsi48
+ *
+ * Description:
+ *   Disable the HSI48 clock.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void stm32l4_disable_hsi48(void);
+
+#endif /* CONFIG_STM32L4_HAVE_HSI48 */
+#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_HSI48_H */
diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c
index 06d4dcf0853..9e1fa505145 100644
--- a/arch/arm/src/stm32l4/stm32l4_i2c.c
+++ b/arch/arm/src/stm32l4/stm32l4_i2c.c
@@ -1330,133 +1330,125 @@ static void stm32l4_i2c_setclock(FAR struct stm32l4_i2c_priv_s *priv,
           stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
         }
 
-      /*  The Speed and timing calculation are based on the following
-       *  fI2CCLK = PCLK and is 80Mhz
-       *  Analog filter is on,
-       *  Digital filter off
-       *  Rise Time is 120 ns and fall is 10ns
-       *  Mode is FastMode
-       */
-
+#if defined(STM32L4_I2C_USE_HSI16) || (STM32L4_PCLK1_FREQUENCY == 16000000)
+      i2cclk_mhz = 16;
+#elif STM32L4_PCLK1_FREQUENCY == 80000000
       i2cclk_mhz = 80;
+#elif STM32L4_PCLK1_FREQUENCY == 120000000
+      i2cclk_mhz = 120;
+#else
+#   warning STM32_I2C_INIT: Peripheral clock is PCLK and the speed/timing calculations need to be redone.
+#endif
 
       if (i2cclk_mhz == 80)
         {
-          uint8_t h_time;
-          uint8_t s_time;
+          /* Default timing calculations from original STM32L4 driver: */
 
-          /* Default timing calculations from original STM32L4 driver,
-           * fI2CCLK = PCLK, 80 Mhz */
+          /*  The Speed and timing calculation are based on the following
+           *  fI2CCLK = PCLK and is 80 Mhz
+           *  Analog filter is on,
+           *  Digital filter off
+           *  Rise Time is 120 ns and fall is 10 ns
+           *  Mode is FastMode
+           */
 
           if (frequency == 100000)
             {
-              /* 100 KHz values from I2C timing tool with clock 80mhz */
+              /* 100 KHz values from I2C timing tool with clock 80 MHz */
 
               presc        = 0x01;    /* PRESC - (+1) prescale I2CCLK */
               scl_l_period = 0xe7;    /* SCLL - SCL low period in master mode */
               scl_h_period = 0x9b;    /* SCLH - SCL high period in master mode */
-              h_time       = 0x00;    /* SDADEL - (+1) data hold time after SCL falling edge */
-              s_time       = 0x0d;    /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
+              sda_delay    = 0x00;    /* SDADEL - (+1) data hold time after SCL falling edge */
+              scl_delay    = 0x0d;    /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
             }
           else if (frequency == 400000)
              {
-              /* 400 KHz values from I2C timing tool for clock of 80mhz */
+              /* 400 KHz values from I2C timing tool for clock of 80 MHz */
 
               presc        = 0x01;    /* PRESC - (+1) prescale I2CCLK */
               scl_l_period = 0x43;    /* SCLL - SCL low period in master mode */
               scl_h_period = 0x13;    /* SCLH - SCL high period in master mode */
-              h_time       = 0x00;    /* SDADEL - (+1) data hold time after SCL falling edge */
-              s_time       = 0x07;    /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
+              sda_delay    = 0x00;    /* SDADEL - (+1) data hold time after SCL falling edge */
+              scl_delay    = 0x07;    /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
              }
           else if (frequency == 1000000)
              {
-              /* 1000 KHhz values from I2C timing tool for clock of 80mhz */
+              /* 1000 KHz values from I2C timing tool for clock of 80 MHz */
 
               presc        = 0x01;    /* PRESC - (+1) prescale I2CCLK */
               scl_l_period = 0x14;    /* SCLL - SCL low period in master mode */
               scl_h_period = 0x13;    /* SCLH - SCL high period in master mode */
-              h_time       = 0x00;    /* SDADEL - (+1) data hold time after SCL falling edge */
-              s_time       = 0x05;    /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
-
-              frequency = 1000000;
+              sda_delay    = 0x00;    /* SDADEL - (+1) data hold time after SCL falling edge */
+              scl_delay    = 0x05;    /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
              }
           else
             {
-              /* 10 KHz values from I2C timing tool with clock 80mhz */
+              /* 10 KHz values from I2C timing tool with clock 80 MHz */
 
               presc        = 0x0b;    /* PRESC - (+1) prescale I2CCLK */
               scl_l_period = 0xff;    /* SCLL - SCL low period in master mode */
               scl_h_period = 0xba;    /* SCLH - SCL high period in master mode */
-              h_time       = 0x00;    /* SDADEL - (+1) data hold time after SCL falling edge */
-              s_time       = 0x01;    /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
+              sda_delay    = 0x00;    /* SDADEL - (+1) data hold time after SCL falling edge */
+              scl_delay    = 0x01;    /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
             }
-
-          scl_delay = s_time;
-          sda_delay = h_time;
         }
-
-#if 0
-      /* TODO: Alternative clock configurations. Through Kconfig?
-       *       Or auto-detect? */
-
-      else if (i2cclk_mhz == 8)
+      else if (i2cclk_mhz == 120)
         {
-          uint8_t h_time;
-          uint8_t s_time;
-
-          /* Alternative timing calculations from original STM32L4 driver,
-           * fI2CCLK = PCLK, 8 Mhz */
+          /*  The Speed and timing calculation are based on the following
+           *  fI2CCLK = PCLK and is 120 Mhz
+           *  Analog filter is on,
+           *  Digital filter off
+           *  Rise Time is 120 ns and fall is 25 ns
+           *  Mode is FastMode
+           */
 
           if (frequency == 100000)
             {
-              /* 100 KHz values from datasheet with clock 8mhz */
+              /* 100 KHz values from I2C timing tool with clock 120 MHz */
 
-              presc        = 0x01;
-              scl_l_period = 0x13;
-              scl_h_period = 0x0f;
-              h_time       = 0x02;
-              s_time       = 0x04;
+              presc        = 2;
+              scl_delay    = 14;
+              sda_delay    = 0;
+              scl_h_period = 157;
+              scl_l_period = 230;
             }
           else if (frequency == 400000)
              {
-              /* 400 KHz values from datasheet for clock of 8mhz */
+              /* 400 KHz values from I2C timing tool for clock of 120 MHz */
 
-              presc        = 0x00;
-              scl_l_period = 0x09;
-              scl_h_period = 0x03;
-              h_time       = 0x01;
-              s_time       = 0x03;
+               presc        = 2;
+               scl_delay    = 8;
+               sda_delay    = 0;
+               scl_h_period = 21;
+               scl_l_period = 66;
              }
           else if (frequency == 1000000)
              {
-              /* 500 KHhz values from datasheet for clock of 8mhz */
+              /* 1000 KHz values from I2C timing tool for clock of 120 MHz */
 
-              presc        = 0x00;
-              scl_l_period = 0x06;
-              scl_h_period = 0x03;
-              h_time       = 0x00;
-              s_time       = 0x01;
-
-              frequency = 500000;
+              presc        = 2;
+              scl_delay    = 6;
+              sda_delay    = 0;
+              scl_h_period = 7;
+              scl_l_period = 20;
              }
           else
             {
-              /* 10 KHz values from I2C timing tool with clock 8mhz */
+              /* 10 KHz values not supported */
 
-              presc        = 0x03;    /* PRESC - (+1) prescale I2CCLK */
-              scl_l_period = 0xc7;    /* SCLL - SCL low period in master mode */
-              scl_h_period = 0xc3;    /* SCLH - SCL high period in master mode */
-              h_time       = 0x02;    /* SDADEL - (+1) data hold time after SCL falling edge */
-              s_time       = 0x04;    /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
+              DEBUGPANIC();
             }
-
-          scl_delay = s_time;
-          sda_delay = h_time;
         }
-
       else if (i2cclk_mhz == 16)
         {
-          /* Timing calculations from STM32F7 driver, fI2CCLK = HSI 16 MHz */
+          /*  The Speed and timing calculation are based on the following
+           *  fI2CCLK = HSI and is 16Mhz
+           *  Analog filter is on,
+           *  Digital filter off
+           *  Rise Time is 120 ns and fall is 10ns
+           *  Mode is FastMode
+           */
 
           if (frequency == 100000)
             {
@@ -1465,24 +1457,23 @@ static void stm32l4_i2c_setclock(FAR struct stm32l4_i2c_priv_s *priv,
               sda_delay    = 0;
               scl_h_period = 61;
               scl_l_period = 89;
-
             }
           else if (frequency == 400000)
-             {
-               presc        = 0;
-               scl_delay    = 3;
-               sda_delay    = 0;
-               scl_h_period = 6;
-               scl_l_period = 24;
-             }
+            {
+              presc        = 0;
+              scl_delay    = 3;
+              sda_delay    = 0;
+              scl_h_period = 6;
+              scl_l_period = 24;
+            }
           else if (frequency == 1000000)
-             {
-               presc        = 0;
-               scl_delay    = 2;
-               sda_delay    = 0;
-               scl_h_period = 1;
-               scl_l_period = 5;
-             }
+            {
+              presc        = 0;
+              scl_delay    = 2;
+              sda_delay    = 0;
+              scl_h_period = 1;
+              scl_l_period = 5;
+            }
           else
             {
               presc        = 7;
@@ -1492,7 +1483,6 @@ static void stm32l4_i2c_setclock(FAR struct stm32l4_i2c_priv_s *priv,
               scl_l_period = 162;
             }
         }
-#endif
       else
         {
           DEBUGPANIC();
@@ -2917,11 +2907,6 @@ FAR struct i2c_master_s *stm32l4_i2cbus_initialize(int port)
   int ret;
 #endif
 
-#if STM32L4_PCLK1_FREQUENCY != 80000000
-#   warning STM32_I2C_INIT: Peripheral clock is PCLK and it must be 80mHz or the speed/timing calculations need to be redone.
-    return NULL;
-#endif
-
   /* Get I2C private structure */
 
   switch (port)
diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.h b/arch/arm/src/stm32l4/stm32l4_i2c.h
index 3a38cc14bdc..6a88b0b97da 100644
--- a/arch/arm/src/stm32l4/stm32l4_i2c.h
+++ b/arch/arm/src/stm32l4/stm32l4_i2c.h
@@ -44,7 +44,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32l4_i2c.h"
+#include "hardware/stm32l4_i2c.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32l4/stm32l4_iwdg.c b/arch/arm/src/stm32l4/stm32l4_iwdg.c
index bfabd4bb52b..6660d9717ef 100644
--- a/arch/arm/src/stm32l4/stm32l4_iwdg.c
+++ b/arch/arm/src/stm32l4/stm32l4_iwdg.c
@@ -52,7 +52,7 @@
 
 #include "up_arch.h"
 #include "stm32l4_rcc.h"
-#include "chip/stm32l4_dbgmcu.h"
+#include "stm32l4_dbgmcu.h"
 #include "stm32l4_wdg.h"
 
 #if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32L4_IWDG)
diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.c b/arch/arm/src/stm32l4/stm32l4_lptim.c
index 951e0ab9259..dc73a52f0bd 100644
--- a/arch/arm/src/stm32l4/stm32l4_lptim.c
+++ b/arch/arm/src/stm32l4/stm32l4_lptim.c
@@ -136,7 +136,7 @@ static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv =
   .ops        = &stm32l4_lptim_ops,
   .mode       = STM32L4_LPTIM_MODE_UNUSED,
   .base       = STM32L4_LPTIM1_BASE,
-  .freq       = STM32L4_LPTIM1_FREQUENCY,  /* Must be efined in board.h */
+  .freq       = STM32L4_LPTIM1_FREQUENCY,  /* Must be defined in board.h */
 };
 #endif
 
@@ -146,7 +146,7 @@ static struct stm32l4_lptim_priv_s stm32l4_lptim2_priv =
   .ops        = &stm32l4_lptim_ops,
   .mode       = STM32L4_LPTIM_MODE_UNUSED,
   .base       = STM32L4_LPTIM2_BASE,
-  .freq       = STM32L4_LPTIM2_FREQUENCY,  /* Must be efined in board.h */
+  .freq       = STM32L4_LPTIM2_FREQUENCY,  /* Must be defined in board.h */
 };
 #endif
 
diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.h b/arch/arm/src/stm32l4/stm32l4_lptim.h
index 90e0cb0d3bb..150b20fcc3b 100644
--- a/arch/arm/src/stm32l4/stm32l4_lptim.h
+++ b/arch/arm/src/stm32l4/stm32l4_lptim.h
@@ -78,7 +78,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32l4_lptim.h"
+#include "hardware/stm32l4_lptim.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32l4/stm32l4_otgfs.h b/arch/arm/src/stm32l4/stm32l4_otgfs.h
index da4e6673cdb..bb3122de77c 100644
--- a/arch/arm/src/stm32l4/stm32l4_otgfs.h
+++ b/arch/arm/src/stm32l4/stm32l4_otgfs.h
@@ -50,9 +50,9 @@
 #if defined(CONFIG_STM32L4_OTGFS)
 
 #if defined(CONFIG_STM32L4_STM32L4X5)
-#  include "chip/stm32l4x5xx_otgfs.h"
+#  include "hardware/stm32l4x5xx_otgfs.h"
 #elif defined(CONFIG_STM32L4_STM32L4X6)
-#  include "chip/stm32l4x6xx_otgfs.h"
+#  include "hardware/stm32l4x6xx_otgfs.h"
 #else
 #  error "Unsupported STM32L4 chip"
 #endif
diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c
index 03639445845..1058558cfb1 100644
--- a/arch/arm/src/stm32l4/stm32l4_pwm.c
+++ b/arch/arm/src/stm32l4/stm32l4_pwm.c
@@ -1623,25 +1623,25 @@ static void stm32l4pwm_setapbclock(FAR struct stm32l4_pwmtimer_s *priv, bool on)
 #endif
 #ifdef CONFIG_STM32L4_TIM2_PWM
       case 2:
-        regaddr  = STM32L4_RCC_APB1ENR;
-        en_bit   = RCC_APB1ENR_TIM2EN;
+        regaddr  = STM32L4_RCC_APB1ENR1;
+        en_bit   = RCC_APB1ENR1_TIM2EN;
         break;
 #endif
 #ifdef CONFIG_STM32L4_TIM3_PWM
       case 3:
-        regaddr  = STM32L4_RCC_APB1ENR;
+        regaddr  = STM32L4_RCC_APB1ENR1;
         en_bit   = RCC_APB1ENR_TIM3EN;
         break;
 #endif
 #ifdef CONFIG_STM32L4_TIM4_PWM
       case 4:
-        regaddr  = STM32L4_RCC_APB1ENR;
-        en_bit   = RCC_APB1ENR_TIM4EN;
+        regaddr  = STM32L4_RCC_APB1ENR1;
+        en_bit   = RCC_APB1ENR1_TIM4EN;
         break;
 #endif
 #ifdef CONFIG_STM32L4_TIM5_PWM
       case 5:
-        regaddr  = STM32L4_RCC_APB1ENR;
+        regaddr  = STM32L4_RCC_APB1ENR1;
         en_bit   = RCC_APB1ENR_TIM5EN;
         break;
 #endif
@@ -1953,25 +1953,25 @@ static int stm32l4pwm_stop(FAR struct pwm_lowerhalf_s *dev)
 #endif
 #ifdef CONFIG_STM32L4_TIM2_PWM
       case 2:
-        regaddr  = STM32L4_RCC_APB1RSTR;
-        resetbit = RCC_APB1RSTR_TIM2RST;
+        regaddr  = STM32L4_RCC_APB1RSTR1;
+        resetbit = RCC_APB1RSTR1_TIM2RST;
         break;
 #endif
 #ifdef CONFIG_STM32L4_TIM3_PWM
       case 3:
-        regaddr  = STM32L4_RCC_APB1RSTR;
+        regaddr  = STM32L4_RCC_APB1RSTR1;
         resetbit = RCC_APB1RSTR_TIM3RST;
         break;
 #endif
 #ifdef CONFIG_STM32L4_TIM4_PWM
       case 4:
-        regaddr  = STM32L4_RCC_APB1RSTR;
-        resetbit = RCC_APB1RSTR_TIM4RST;
+        regaddr  = STM32L4_RCC_APB1RSTR1;
+        resetbit = RCC_APB1RSTR1_TIM4RST;
         break;
 #endif
 #ifdef CONFIG_STM32L4_TIM5_PWM
       case 5:
-        regaddr  = STM32L4_RCC_APB1RSTR;
+        regaddr  = STM32L4_RCC_APB1RSTR1;
         resetbit = RCC_APB1RSTR_TIM5RST;
         break;
 #endif
diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.h b/arch/arm/src/stm32l4/stm32l4_pwm.h
index ff98f6e509f..2abe8be255a 100644
--- a/arch/arm/src/stm32l4/stm32l4_pwm.h
+++ b/arch/arm/src/stm32l4/stm32l4_pwm.h
@@ -104,7 +104,7 @@
     defined(CONFIG_STM32L4_TIM17_PWM)
 
 #include 
-#include "chip/stm32l4_tim.h"
+#include "hardware/stm32l4_tim.h"
 
 #ifdef CONFIG_PWM_MULTICHAN
 
diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.c b/arch/arm/src/stm32l4/stm32l4_pwr.c
index 816392895c8..eb93e89afa5 100644
--- a/arch/arm/src/stm32l4/stm32l4_pwr.c
+++ b/arch/arm/src/stm32l4/stm32l4_pwr.c
@@ -185,24 +185,33 @@ bool stm32l4_pwr_enablebkp(bool writable)
 
 bool stm32l4_pwr_enableusv(bool set)
 {
-  uint16_t regval;
-  bool wasset;
+  uint32_t regval;
+  bool was_set;
+  bool was_clk_enabled;
+
+  regval = getreg32(STM32L4_RCC_APB1ENR1);
+  was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0);
+
+  if (!was_clk_enabled)
+    {
+      stm32l4_pwr_enableclk(true);
+    }
 
   /* Get the current state of the STM32L4 PWR control register 2 */
 
-  regval      = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET);
-  wasset = ((regval & PWR_CR2_USV) != 0);
+  regval  = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET);
+  was_set = ((regval & PWR_CR2_USV) != 0);
 
   /* Enable or disable the ability to write */
 
-  if (wasset && !set)
+  if (was_set && !set)
     {
       /* Disable the Vddusb monitoring */
 
       regval &= ~PWR_CR2_USV;
       stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval);
     }
-  else if (!wasset && set)
+  else if (!was_set && set)
     {
       /* Enable the Vddusb monitoring */
 
@@ -210,5 +219,10 @@ bool stm32l4_pwr_enableusv(bool set)
       stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval);
     }
 
-  return wasset;
+  if (!was_clk_enabled)
+    {
+      stm32l4_pwr_enableclk(false);
+    }
+
+  return was_set;
 }
diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.h b/arch/arm/src/stm32l4/stm32l4_pwr.h
index 77d87b3dfe2..e709a3f7336 100644
--- a/arch/arm/src/stm32l4/stm32l4_pwr.h
+++ b/arch/arm/src/stm32l4/stm32l4_pwr.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32l4_pwr.h"
+#include "hardware/stm32l4_pwr.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c
index d240968ad1e..b3bb57c76a4 100644
--- a/arch/arm/src/stm32l4/stm32l4_qspi.c
+++ b/arch/arm/src/stm32l4/stm32l4_qspi.c
@@ -66,8 +66,8 @@
 #include "stm32l4_dma.h"
 #include "stm32l4_qspi.h"
 #include "stm32l4_rcc.h"
-#include "chip/stm32l4_qspi.h"
-#include "chip/stm32l4_pinmap.h"
+#include "hardware/stm32l4_qspi.h"
+#include "hardware/stm32l4_pinmap.h"
 
 #ifdef CONFIG_STM32L4_QSPI
 
diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.h b/arch/arm/src/stm32l4/stm32l4_rcc.h
index 0909a1d6bea..360a686da61 100644
--- a/arch/arm/src/stm32l4/stm32l4_rcc.h
+++ b/arch/arm/src/stm32l4/stm32l4_rcc.h
@@ -46,13 +46,13 @@
 #include "chip.h"
 
 #if defined(CONFIG_STM32L4_STM32L4X3)
-#  include "chip/stm32l4x3xx_rcc.h"
+#  include "hardware/stm32l4x3xx_rcc.h"
 #elif defined(CONFIG_STM32L4_STM32L4X5)
-#  include "chip/stm32l4x5xx_rcc.h"
+#  include "hardware/stm32l4x5xx_rcc.h"
 #elif defined(CONFIG_STM32L4_STM32L4X6)
-#  include "chip/stm32l4x6xx_rcc.h"
+#  include "hardware/stm32l4x6xx_rcc.h"
 #elif defined(CONFIG_STM32L4_STM32L4XR)
-#  include "chip/stm32l4xrxx_rcc.h"
+#  include "hardware/stm32l4xrxx_rcc.h"
 #else
 #  error "Unsupported STM32L4 chip"
 #endif
diff --git a/arch/arm/src/stm32l4/stm32l4_rng.c b/arch/arm/src/stm32l4/stm32l4_rng.c
index cb5a8ce2ab0..84b6fdd5ff9 100644
--- a/arch/arm/src/stm32l4/stm32l4_rng.c
+++ b/arch/arm/src/stm32l4/stm32l4_rng.c
@@ -52,7 +52,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/stm32l4_rng.h"
+#include "hardware/stm32l4_rng.h"
 #include "up_internal.h"
 
 #if defined(CONFIG_STM32L4_RNG)
@@ -90,15 +90,13 @@ static struct rng_dev_s g_rngdev;
 
 static const struct file_operations g_rngops =
 {
-  0,               /* open */
-  0,               /* close */
+  NULL,            /* open */
+  NULL,            /* close */
   stm32l4_rngread, /* read */
-  0,               /* write */
-  0,               /* seek */
-  0                /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0              /* poll */
-#endif
+  NULL,            /* write */
+  NULL,            /* seek */
+  NULL,            /* ioctl */
+  NULL             /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , 0              /* unlink */
 #endif
diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h
index 51c0e51dae1..bb43de875e7 100644
--- a/arch/arm/src/stm32l4/stm32l4_rtc.h
+++ b/arch/arm/src/stm32l4/stm32l4_rtc.h
@@ -48,7 +48,7 @@
 
 #include "chip.h"
 
-#include "chip/stm32l4_rtcc.h"
+#include "hardware/stm32l4_rtcc.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32l4/stm32l4_sai.h b/arch/arm/src/stm32l4/stm32l4_sai.h
index b1b4955185e..8f6bab98a9e 100644
--- a/arch/arm/src/stm32l4/stm32l4_sai.h
+++ b/arch/arm/src/stm32l4/stm32l4_sai.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32l4_sai.h"
+#include "hardware/stm32l4_sai.h"
 
 #include 
 
diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.h b/arch/arm/src/stm32l4/stm32l4_sdmmc.h
index 0882acbb74e..8ebe6793289 100644
--- a/arch/arm/src/stm32l4/stm32l4_sdmmc.h
+++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.h
@@ -46,7 +46,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32l4_sdmmc.h"
+#include "hardware/stm32l4_sdmmc.h"
 
 
 /************************************************************************************
diff --git a/arch/arm/src/stm32l4/stm32l4_spi.h b/arch/arm/src/stm32l4/stm32l4_spi.h
index 5d9f74db704..f5540860589 100644
--- a/arch/arm/src/stm32l4/stm32l4_spi.h
+++ b/arch/arm/src/stm32l4/stm32l4_spi.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32l4_spi.h"
+#include "hardware/stm32l4_spi.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32l4/stm32l4_start.c b/arch/arm/src/stm32l4/stm32l4_start.c
index 4d85fae6e3e..05badb5a7ef 100644
--- a/arch/arm/src/stm32l4/stm32l4_start.c
+++ b/arch/arm/src/stm32l4/stm32l4_start.c
@@ -1,6 +1,5 @@
 /****************************************************************************
  * arch/arm/src/stm32l4/stm32l4_start.c
- * arch/arm/src/chip/stm32l4_start.c
  *
  *   Copyright (C) 2009, 2011-2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -49,16 +48,13 @@
 
 #include "up_arch.h"
 #include "up_internal.h"
+#include "nvic.h"
 
 #include "stm32l4.h"
 #include "stm32l4_gpio.h"
 #include "stm32l4_userspace.h"
 #include "stm32l4_start.h"
 
-#ifdef CONFIG_ARCH_FPU
-#  include "nvic.h"
-#endif
-
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
diff --git a/arch/arm/src/stm32l4/stm32l4_tim.h b/arch/arm/src/stm32l4/stm32l4_tim.h
index 0caf411cf1d..b5b939051bd 100644
--- a/arch/arm/src/stm32l4/stm32l4_tim.h
+++ b/arch/arm/src/stm32l4/stm32l4_tim.h
@@ -49,7 +49,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32l4_tim.h"
+#include "hardware/stm32l4_tim.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/stm32l4/stm32l4_uart.h b/arch/arm/src/stm32l4/stm32l4_uart.h
index 5c5b3815307..4948b90c634 100644
--- a/arch/arm/src/stm32l4/stm32l4_uart.h
+++ b/arch/arm/src/stm32l4/stm32l4_uart.h
@@ -47,7 +47,7 @@
 
 #if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \
     defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)
-#  include "chip/stm32l4_uart.h"
+#  include "hardware/stm32l4_uart.h"
 #else
 #  error "Unsupported STM32L4 chip"
 #endif
diff --git a/arch/arm/src/stm32l4/stm32l4_uid.c b/arch/arm/src/stm32l4/stm32l4_uid.c
index 4547dcc4560..007d0076235 100644
--- a/arch/arm/src/stm32l4/stm32l4_uid.c
+++ b/arch/arm/src/stm32l4/stm32l4_uid.c
@@ -40,8 +40,7 @@
 
 #include 
 
-#include 
-
+#include "hardware/stm32l4_memorymap.h"
 #include "stm32l4_uid.h"
 
 #ifdef STM32L4_SYSMEM_UID
diff --git a/arch/arm/src/stm32l4/stm32l4_usbdev.c b/arch/arm/src/stm32l4/stm32l4_usbdev.c
new file mode 100644
index 00000000000..a608eb7b237
--- /dev/null
+++ b/arch/arm/src/stm32l4/stm32l4_usbdev.c
@@ -0,0 +1,3890 @@
+/****************************************************************************
+ * arch/arm/src/stm32l4/stm32l4_usbdev.c
+ *
+ *   Copyright (C) 2009-2013, 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "up_arch.h"
+#include "stm32l4.h"
+#include "stm32l4_gpio.h"
+#include "stm32l4_usbdev.h"
+
+#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32L4_USBFS)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#ifndef CONFIG_USBDEV_EP0_MAXSIZE
+#  define CONFIG_USBDEV_EP0_MAXSIZE 64
+#endif
+
+#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE
+#  define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE
+#endif
+
+/* Extremely detailed register debug that you would normally never want
+ * enabled.
+ */
+
+#ifndef CONFIG_DEBUG_USB_INFO
+#  undef CONFIG_STM32L4_USBDEV_REGDEBUG
+#endif
+
+/* Initial interrupt mask: Reset + Suspend + Correct Transfer */
+
+#define STM32L4_CNTR_SETUP     (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM)
+
+/* Endpoint identifiers. The STM32L4 supports up to 16 mono-directional or 8
+ * bidirectional endpoints.  However, when you take into account PMA buffer
+ * usage (see below) and the fact that EP0 is bidirectional, then there is
+ * a functional limitation of EP0 + 5 mono-directional endpoints = 6.  We'll
+ * define STM32L4_NENDPOINTS to be 8, however, because that is how many
+ * endpoint register sets there are.
+ */
+
+#define STM32L4_NENDPOINTS    (8)
+#define EP0                   (0)
+#define EP1                   (1)
+#define EP2                   (2)
+#define EP3                   (3)
+#define EP4                   (4)
+#define EP5                   (5)
+#define EP6                   (6)
+#define EP7                   (7)
+
+#define STM32L4_ENDP_BIT(ep)  (1 << (ep))
+#define STM32L4_ENDP_ALLSET   0xff
+
+/* Packet sizes.  We us a fixed 64 max packet size for all endpoint types */
+
+#define STM32L4_MAXPACKET_SHIFT (6)
+#define STM32L4_MAXPACKET_SIZE  (1 << (STM32L4_MAXPACKET_SHIFT))
+#define STM32L4_MAXPACKET_MASK  (STM32L4_MAXPACKET_SIZE-1)
+
+#define STM32L4_EP0MAXPACKET    STM32L4_MAXPACKET_SIZE
+
+/* Buffer descriptor table.
+ * The buffer table is positioned at the beginning of the 1024-byte
+ * USB memory.  We will use the first STM32L4_NENDPOINTS*8 bytes for the buffer
+ * table.  That is exactly 64 bytes, leaving 15*64 bytes for endpoint buffers.
+ */
+
+#define STM32L4_BTABLE_ADDRESS  (0x00)   /* Start at the beginning of USB RAM */
+#define STM32L4_DESC_SIZE       (8)      /* Each descriptor is 4*2=8 bytes in size */
+#define STM32L4_BTABLE_SIZE     (STM32L4_NENDPOINTS*STM32L4_DESC_SIZE)
+
+/* Buffer layout.  Assume that all buffers are 64-bytes (maxpacketsize), then
+ * we have space for only 7 buffers; endpoint 0 will require two buffers, leaving
+ * 5 for other endpoints.
+ */
+
+#define STM32L4_BUFFER_START    STM32L4_BTABLE_SIZE
+#define STM32L4_EP0_RXADDR      STM32L4_BUFFER_START
+#define STM32L4_EP0_TXADDR      (STM32L4_EP0_RXADDR+STM32L4_EP0MAXPACKET)
+
+#define STM32L4_BUFFER_EP0      0x03
+#define STM32L4_NBUFFERS        7
+#define STM32L4_BUFFER_BIT(bn)  (1 << (bn))
+#define STM32L4_BUFFER_ALLSET   0x7f
+#define STM32L4_BUFNO2BUF(bn)   (STM32L4_BUFFER_START+((bn)<head == NULL)
+#define stm32l4_rqpeek(ep)      ((ep)->head)
+
+/* USB trace ****************************************************************/
+/* Trace error codes */
+
+#define STM32L4_TRACEERR_ALLOCFAIL            0x0001
+#define STM32L4_TRACEERR_BADCLEARFEATURE      0x0002
+#define STM32L4_TRACEERR_BADDEVGETSTATUS      0x0003
+#define STM32L4_TRACEERR_BADEPGETSTATUS       0x0004
+#define STM32L4_TRACEERR_BADEPNO              0x0005
+#define STM32L4_TRACEERR_BADEPTYPE            0x0006
+#define STM32L4_TRACEERR_BADGETCONFIG         0x0007
+#define STM32L4_TRACEERR_BADGETSETDESC        0x0008
+#define STM32L4_TRACEERR_BADGETSTATUS         0x0009
+#define STM32L4_TRACEERR_BADSETADDRESS        0x000a
+#define STM32L4_TRACEERR_BADSETCONFIG         0x000b
+#define STM32L4_TRACEERR_BADSETFEATURE        0x000c
+#define STM32L4_TRACEERR_BINDFAILED           0x000d
+#define STM32L4_TRACEERR_DISPATCHSTALL        0x000e
+#define STM32L4_TRACEERR_DRIVER               0x000f
+#define STM32L4_TRACEERR_DRIVERREGISTERED     0x0010
+#define STM32L4_TRACEERR_EP0BADCTR            0x0011
+#define STM32L4_TRACEERR_EP0SETUPSTALLED      0x0012
+#define STM32L4_TRACEERR_EPBUFFER             0x0013
+#define STM32L4_TRACEERR_EPDISABLED           0x0014
+#define STM32L4_TRACEERR_EPOUTNULLPACKET      0x0015
+#define STM32L4_TRACEERR_EPRESERVE            0x0016
+#define STM32L4_TRACEERR_INVALIDCTRLREQ       0x0017
+#define STM32L4_TRACEERR_INVALIDPARMS         0x0018
+#define STM32L4_TRACEERR_IRQREGISTRATION      0x0019
+#define STM32L4_TRACEERR_NOTCONFIGURED        0x001a
+#define STM32L4_TRACEERR_REQABORTED           0x001b
+
+/* Trace interrupt codes */
+
+#define STM32L4_TRACEINTID_CLEARFEATURE       0x0001
+#define STM32L4_TRACEINTID_DEVGETSTATUS       0x0002
+#define STM32L4_TRACEINTID_DISPATCH           0x0003
+#define STM32L4_TRACEINTID_EP0IN              0x0004
+#define STM32L4_TRACEINTID_EP0INDONE          0x0005
+#define STM32L4_TRACEINTID_EP0OUTDONE         0x0006
+#define STM32L4_TRACEINTID_EP0SETUPDONE       0x0007
+#define STM32L4_TRACEINTID_EP0SETUPSETADDRESS 0x0008
+#define STM32L4_TRACEINTID_EPGETSTATUS        0x0009
+#define STM32L4_TRACEINTID_EPINDONE           0x000a
+#define STM32L4_TRACEINTID_EPINQEMPTY         0x000b
+#define STM32L4_TRACEINTID_EPOUTDONE          0x000c
+#define STM32L4_TRACEINTID_EPOUTPENDING       0x000d
+#define STM32L4_TRACEINTID_EPOUTQEMPTY        0x000e
+#define STM32L4_TRACEINTID_ESOF               0x000f
+#define STM32L4_TRACEINTID_GETCONFIG          0x0010
+#define STM32L4_TRACEINTID_GETSETDESC         0x0011
+#define STM32L4_TRACEINTID_GETSETIF           0x0012
+#define STM32L4_TRACEINTID_GETSTATUS          0x0013
+/* HPINTERRUPT not used */
+#define STM32L4_TRACEINTID_IFGETSTATUS        0x0015
+#define STM32L4_TRACEINTID_USBCTR             0x0016
+#define STM32L4_TRACEINTID_USBINTERRUPT       0x0017
+#define STM32L4_TRACEINTID_NOSTDREQ           0x0018
+#define STM32L4_TRACEINTID_RESET              0x0019
+#define STM32L4_TRACEINTID_SETCONFIG          0x001a
+#define STM32L4_TRACEINTID_SETFEATURE         0x001b
+#define STM32L4_TRACEINTID_SUSP               0x001c
+#define STM32L4_TRACEINTID_SYNCHFRAME         0x001d
+#define STM32L4_TRACEINTID_WKUP               0x001e
+#define STM32L4_TRACEINTID_EP0SETUPOUT        0x001f
+#define STM32L4_TRACEINTID_EP0SETUPOUTDATA    0x0020
+
+/* Ever-present MIN and MAX macros */
+
+#ifndef MIN
+#  define MIN(a,b) (a < b ? a : b)
+#endif
+
+#ifndef MAX
+#  define MAX(a,b) (a > b ? a : b)
+#endif
+
+/* Byte ordering in host-based values */
+
+#ifdef CONFIG_ENDIAN_BIG
+#  define LSB 1
+#  define MSB 0
+#else
+#  define LSB 0
+#  define MSB 1
+#endif
+
+/****************************************************************************
+ * Private Type Definitions
+ ****************************************************************************/
+
+/* The various states of a control pipe */
+
+enum stm32l4_ep0state_e
+{
+  EP0STATE_IDLE = 0,        /* No request in progress */
+  EP0STATE_SETUP_OUT,       /* Set up recived with data for device OUT in progress */
+  EP0STATE_SETUP_READY,     /* Set up was recived prior and is in ctrl,
+                             * now the data has arrived */
+  EP0STATE_WRREQUEST,       /* Write request in progress */
+  EP0STATE_RDREQUEST,       /* Read request in progress */
+  EP0STATE_STALLED          /* We are stalled */
+};
+
+/* Resume states */
+
+enum stm32l4_rsmstate_e
+{
+  RSMSTATE_IDLE = 0,        /* Device is either fully suspended or running */
+  RSMSTATE_STARTED,         /* Resume sequence has been started */
+  RSMSTATE_WAITING          /* Waiting (on ESOFs) for end of sequence */
+};
+
+union wb_u
+{
+  uint16_t w;
+  uint8_t  b[2];
+};
+
+/* A container for a request so that the request make be retained in a list */
+
+struct stm32l4_req_s
+{
+  struct usbdev_req_s    req;           /* Standard USB request */
+  struct stm32l4_req_s  *flink;         /* Supports a singly linked list */
+};
+
+/* This is the internal representation of an endpoint */
+
+struct stm32l4_ep_s
+{
+  /* Common endpoint fields.  This must be the first thing defined in the
+   * structure so that it is possible to simply cast from struct usbdev_ep_s
+   * to struct stm32l4_ep_s.
+   */
+
+  struct usbdev_ep_s     ep;            /* Standard endpoint structure */
+
+  /* STM32-specific fields */
+
+  struct stm32l4_usbdev_s *dev;           /* Reference to private driver data */
+  struct stm32l4_req_s    *head;          /* Request list for this endpoint */
+  struct stm32l4_req_s    *tail;
+  uint8_t                  bufno;         /* Allocated buffer number */
+  uint8_t                  stalled:1;     /* true: Endpoint is stalled */
+  uint8_t                  halted:1;      /* true: Endpoint feature halted */
+  uint8_t                  txbusy:1;      /* true: TX endpoint FIFO full */
+  uint8_t                  txnullpkt:1;   /* Null packet needed at end of transfer */
+};
+
+struct stm32l4_usbdev_s
+{
+  /* Common device fields.  This must be the first thing defined in the
+   * structure so that it is possible to simply cast from struct usbdev_s
+   * to structstm32l4_usbdev_s.
+   */
+
+  struct usbdev_s usbdev;
+
+  /* The bound device class driver */
+
+  struct usbdevclass_driver_s *driver;
+
+  /* STM32-specific fields */
+
+  uint8_t                ep0state;      /* State of EP0 (see enum stm32l4_ep0state_e) */
+  uint8_t                rsmstate;      /* Resume state (see enum stm32l4_rsmstate_e) */
+  uint8_t                nesofs;        /* ESOF counter (for resume support) */
+  uint8_t                rxpending:1;   /* 1: OUT data in PMA, but no read requests */
+  uint8_t                selfpowered:1; /* 1: Device is self powered */
+  uint8_t                epavail;       /* Bitset of available endpoints */
+  uint8_t                bufavail;      /* Bitset of available buffers */
+  uint16_t               rxstatus;      /* Saved during interrupt processing */
+  uint16_t               txstatus;      /* "   " "    " "       " "        " */
+  uint16_t               imask;         /* Current interrupt mask */
+
+  /* E0 SETUP data buffering.
+   *
+   * ctrl
+   *   The 8-byte SETUP request is received on the EP0 OUT endpoint and is
+   *   saved.
+   *
+   * ep0data
+   *   For OUT SETUP requests, the SETUP data phase must also complete before
+   *   the SETUP command can be processed.  The ep0 packet receipt logic
+   *   stm32l4_ep0_rdrequest will save the accompanying EP0 OUT data in
+   *   ep0data[] before the SETUP command is re-processed.
+   *
+   * ep0datlen
+   *   Lenght of OUT DATA received in ep0data[]
+   */
+
+  struct usb_ctrlreq_s   ctrl;          /* Last EP0 request */
+
+  uint8_t                ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE];
+  uint16_t               ep0datlen;
+
+  /* The endpoint list */
+
+  struct stm32l4_ep_s      eplist[STM32L4_NENDPOINTS];
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Register operations ******************************************************/
+
+#ifdef CONFIG_STM32L4_USBDEV_REGDEBUG
+static uint16_t stm32l4_getreg(uint32_t addr);
+static void stm32l4_putreg(uint16_t val, uint32_t addr);
+static void stm32l4_checksetup(void);
+static void stm32l4_dumpep(int epno);
+#else
+# define stm32l4_getreg(addr)      getreg16(addr)
+# define stm32l4_putreg(val,addr)  putreg16(val,addr)
+# define stm32l4_checksetup()
+# define stm32l4_dumpep(epno)
+#endif
+
+/* Low-Level Helpers ********************************************************/
+
+static inline void
+              stm32l4_seteptxcount(uint8_t epno, uint16_t count);
+static inline void
+              stm32l4_seteptxaddr(uint8_t epno, uint16_t addr);
+static inline uint16_t
+              stm32l4_geteptxaddr(uint8_t epno);
+static void   stm32l4_seteprxcount(uint8_t epno, uint16_t count);
+static inline uint16_t
+              stm32l4_geteprxcount(uint8_t epno);
+static inline void
+              stm32l4_seteprxaddr(uint8_t epno, uint16_t addr);
+static inline uint16_t
+              stm32l4_geteprxaddr(uint8_t epno);
+static inline void
+              stm32l4_setepaddress(uint8_t epno, uint16_t addr);
+static inline void
+              stm32l4_seteptype(uint8_t epno, uint16_t type);
+static inline void
+              stm32l4_seteptxaddr(uint8_t epno, uint16_t addr);
+static inline void
+              stm32l4_setstatusout(uint8_t epno);
+static inline void
+              stm32l4_clrstatusout(uint8_t epno);
+static void   stm32l4_clrrxdtog(uint8_t epno);
+static void   stm32l4_clrtxdtog(uint8_t epno);
+static void   stm32l4_clrepctrrx(uint8_t epno);
+static void   stm32l4_clrepctrtx(uint8_t epno);
+static void   stm32l4_seteptxstatus(uint8_t epno, uint16_t state);
+static void   stm32l4_seteprxstatus(uint8_t epno, uint16_t state);
+static inline uint16_t
+              stm32l4_geteptxstatus(uint8_t epno);
+static inline uint16_t
+              stm32l4_geteprxstatus(uint8_t epno);
+static bool   stm32l4_eptxstalled(uint8_t epno);
+static bool   stm32l4_eprxstalled(uint8_t epno);
+static void   stm32l4_setimask(struct stm32l4_usbdev_s *priv, uint16_t setbits,
+                uint16_t clrbits);
+
+/* Suspend/Resume Helpers ***************************************************/
+
+static void   stm32l4_suspend(struct stm32l4_usbdev_s *priv);
+static void   stm32l4_initresume(struct stm32l4_usbdev_s *priv);
+static void   stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) ;
+
+/* Request Helpers **********************************************************/
+
+static void   stm32l4_copytopma(const uint8_t *buffer, uint16_t pma,
+                uint16_t nbytes);
+static inline void
+              stm32l4_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes);
+static struct stm32l4_req_s *
+              stm32l4_rqdequeue(struct stm32l4_ep_s *privep);
+static void   stm32l4_rqenqueue(struct stm32l4_ep_s *privep,
+                struct stm32l4_req_s *req);
+static inline void
+              stm32l4_abortrequest(struct stm32l4_ep_s *privep,
+                struct stm32l4_req_s *privreq, int16_t result);
+static void   stm32l4_reqcomplete(struct stm32l4_ep_s *privep, int16_t result);
+static void   stm32l4_epwrite(struct stm32l4_usbdev_s *buf,
+                struct stm32l4_ep_s *privep, const uint8_t *data, uint32_t nbytes);
+static int    stm32l4_wrrequest(struct stm32l4_usbdev_s *priv,
+                struct stm32l4_ep_s *privep);
+inline static int
+              stm32l4_wrrequest_ep0(struct stm32l4_usbdev_s *priv,
+                struct stm32l4_ep_s *privep);
+static inline int
+              stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv);
+static int    stm32l4_rdrequest(struct stm32l4_usbdev_s *priv,
+                struct stm32l4_ep_s *privep);
+static void   stm32l4_cancelrequests(struct stm32l4_ep_s *privep);
+
+/* Interrupt level processing ***********************************************/
+
+static void   stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv);
+static void   stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno);
+static void   stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, uint8_t value);
+static void   stm32l4_ep0setup(struct stm32l4_usbdev_s *priv);
+static void   stm32l4_ep0out(struct stm32l4_usbdev_s *priv);
+static void   stm32l4_ep0in(struct stm32l4_usbdev_s *priv);
+static inline void
+              stm32l4_ep0done(struct stm32l4_usbdev_s *priv, uint16_t istr);
+static void   stm32l4_lptransfer(struct stm32l4_usbdev_s *priv);
+static int    stm32l4_usbinterrupt(int irq, void *context, FAR void *arg);
+
+/* Endpoint helpers *********************************************************/
+
+static inline struct stm32l4_ep_s *
+              stm32l4_epreserve(struct stm32l4_usbdev_s *priv, uint8_t epset);
+static inline void
+              stm32l4_epunreserve(struct stm32l4_usbdev_s *priv,
+                struct stm32l4_ep_s *privep);
+static inline bool
+              stm32l4_epreserved(struct stm32l4_usbdev_s *priv, int epno);
+static int    stm32l4_epallocpma(struct stm32l4_usbdev_s *priv);
+static inline void
+              stm32l4_epfreepma(struct stm32l4_usbdev_s *priv,
+                struct stm32l4_ep_s *privep);
+
+/* Endpoint operations ******************************************************/
+
+static int    stm32l4_epconfigure(struct usbdev_ep_s *ep,
+                const struct usb_epdesc_s *desc, bool last);
+static int    stm32l4_epdisable(struct usbdev_ep_s *ep);
+static struct usbdev_req_s *
+              stm32l4_epallocreq(struct usbdev_ep_s *ep);
+static void   stm32l4_epfreereq(struct usbdev_ep_s *ep,
+                struct usbdev_req_s *);
+static int    stm32l4_epsubmit(struct usbdev_ep_s *ep,
+                struct usbdev_req_s *req);
+static int    stm32l4_epcancel(struct usbdev_ep_s *ep,
+                struct usbdev_req_s *req);
+static int    stm32l4_epstall(struct usbdev_ep_s *ep, bool resume);
+
+/* USB device controller operations *****************************************/
+
+static struct usbdev_ep_s *
+              stm32l4_allocep(struct usbdev_s *dev, uint8_t epno, bool in,
+                uint8_t eptype);
+static void   stm32l4_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep);
+static int    stm32l4_getframe(struct usbdev_s *dev);
+static int    stm32l4_wakeup(struct usbdev_s *dev);
+static int    stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered);
+static int    stm32l4_pullup(struct usbdev_s *dev, bool enable);
+
+/* Initialization/Reset *****************************************************/
+
+static void   stm32l4_reset(struct stm32l4_usbdev_s *priv);
+static void   stm32l4_hwreset(struct stm32l4_usbdev_s *priv);
+static void   stm32l4_hwsetup(struct stm32l4_usbdev_s *priv);
+static void   stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Since there is only a single USB interface, all status information can be
+ * be simply retained in a single global instance.
+ */
+
+static struct stm32l4_usbdev_s g_usbdev;
+
+static const struct usbdev_epops_s g_epops =
+{
+  .configure   = stm32l4_epconfigure,
+  .disable     = stm32l4_epdisable,
+  .allocreq    = stm32l4_epallocreq,
+  .freereq     = stm32l4_epfreereq,
+  .submit      = stm32l4_epsubmit,
+  .cancel      = stm32l4_epcancel,
+  .stall       = stm32l4_epstall,
+};
+
+static const struct usbdev_ops_s g_devops =
+{
+  .allocep     = stm32l4_allocep,
+  .freeep      = stm32l4_freeep,
+  .getframe    = stm32l4_getframe,
+  .wakeup      = stm32l4_wakeup,
+  .selfpowered = stm32l4_selfpowered,
+  .pullup      = stm32l4_pullup,
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifdef CONFIG_USBDEV_TRACE_STRINGS
+const struct trace_msg_t g_usb_trace_strings_intdecode[] =
+{
+  TRACE_STR(STM32L4_TRACEINTID_CLEARFEATURE       ),
+  TRACE_STR(STM32L4_TRACEINTID_DEVGETSTATUS       ),
+  TRACE_STR(STM32L4_TRACEINTID_DISPATCH           ),
+  TRACE_STR(STM32L4_TRACEINTID_EP0IN              ),
+  TRACE_STR(STM32L4_TRACEINTID_EP0INDONE          ),
+  TRACE_STR(STM32L4_TRACEINTID_EP0OUTDONE         ),
+  TRACE_STR(STM32L4_TRACEINTID_EP0SETUPDONE       ),
+  TRACE_STR(STM32L4_TRACEINTID_EP0SETUPSETADDRESS ),
+  TRACE_STR(STM32L4_TRACEINTID_EPGETSTATUS        ),
+  TRACE_STR(STM32L4_TRACEINTID_EPINDONE           ),
+  TRACE_STR(STM32L4_TRACEINTID_EPINQEMPTY         ),
+  TRACE_STR(STM32L4_TRACEINTID_EPOUTDONE          ),
+  TRACE_STR(STM32L4_TRACEINTID_EPOUTPENDING       ),
+  TRACE_STR(STM32L4_TRACEINTID_EPOUTQEMPTY        ),
+  TRACE_STR(STM32L4_TRACEINTID_ESOF               ),
+  TRACE_STR(STM32L4_TRACEINTID_GETCONFIG          ),
+  TRACE_STR(STM32L4_TRACEINTID_GETSETDESC         ),
+  TRACE_STR(STM32L4_TRACEINTID_GETSETIF           ),
+  TRACE_STR(STM32L4_TRACEINTID_GETSTATUS          ),
+  TRACE_STR(STM32L4_TRACEINTID_IFGETSTATUS        ),
+  TRACE_STR(STM32L4_TRACEINTID_USBCTR             ),
+  TRACE_STR(STM32L4_TRACEINTID_USBINTERRUPT       ),
+  TRACE_STR(STM32L4_TRACEINTID_NOSTDREQ           ),
+  TRACE_STR(STM32L4_TRACEINTID_RESET              ),
+  TRACE_STR(STM32L4_TRACEINTID_SETCONFIG          ),
+  TRACE_STR(STM32L4_TRACEINTID_SETFEATURE         ),
+  TRACE_STR(STM32L4_TRACEINTID_SUSP               ),
+  TRACE_STR(STM32L4_TRACEINTID_SYNCHFRAME         ),
+  TRACE_STR(STM32L4_TRACEINTID_WKUP               ),
+  TRACE_STR(STM32L4_TRACEINTID_EP0SETUPOUT        ),
+  TRACE_STR(STM32L4_TRACEINTID_EP0SETUPOUTDATA    ),
+  TRACE_STR_END
+};
+#endif
+
+#ifdef CONFIG_USBDEV_TRACE_STRINGS
+const struct trace_msg_t g_usb_trace_strings_deverror[] =
+{
+  TRACE_STR(STM32L4_TRACEERR_ALLOCFAIL            ),
+  TRACE_STR(STM32L4_TRACEERR_BADCLEARFEATURE      ),
+  TRACE_STR(STM32L4_TRACEERR_BADDEVGETSTATUS      ),
+  TRACE_STR(STM32L4_TRACEERR_BADEPGETSTATUS       ),
+  TRACE_STR(STM32L4_TRACEERR_BADEPNO              ),
+  TRACE_STR(STM32L4_TRACEERR_BADEPTYPE            ),
+  TRACE_STR(STM32L4_TRACEERR_BADGETCONFIG         ),
+  TRACE_STR(STM32L4_TRACEERR_BADGETSETDESC        ),
+  TRACE_STR(STM32L4_TRACEERR_BADGETSTATUS         ),
+  TRACE_STR(STM32L4_TRACEERR_BADSETADDRESS        ),
+  TRACE_STR(STM32L4_TRACEERR_BADSETCONFIG         ),
+  TRACE_STR(STM32L4_TRACEERR_BADSETFEATURE        ),
+  TRACE_STR(STM32L4_TRACEERR_BINDFAILED           ),
+  TRACE_STR(STM32L4_TRACEERR_DISPATCHSTALL        ),
+  TRACE_STR(STM32L4_TRACEERR_DRIVER               ),
+  TRACE_STR(STM32L4_TRACEERR_DRIVERREGISTERED     ),
+  TRACE_STR(STM32L4_TRACEERR_EP0BADCTR            ),
+  TRACE_STR(STM32L4_TRACEERR_EP0SETUPSTALLED      ),
+  TRACE_STR(STM32L4_TRACEERR_EPBUFFER             ),
+  TRACE_STR(STM32L4_TRACEERR_EPDISABLED           ),
+  TRACE_STR(STM32L4_TRACEERR_EPOUTNULLPACKET      ),
+  TRACE_STR(STM32L4_TRACEERR_EPRESERVE            ),
+  TRACE_STR(STM32L4_TRACEERR_INVALIDCTRLREQ       ),
+  TRACE_STR(STM32L4_TRACEERR_INVALIDPARMS         ),
+  TRACE_STR(STM32L4_TRACEERR_IRQREGISTRATION      ),
+  TRACE_STR(STM32L4_TRACEERR_NOTCONFIGURED        ),
+  TRACE_STR(STM32L4_TRACEERR_REQABORTED           ),
+  TRACE_STR_END
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32l4_getreg
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32L4_USBDEV_REGDEBUG
+static uint16_t stm32l4_getreg(uint32_t addr)
+{
+  static uint32_t prevaddr = 0;
+  static uint16_t preval = 0;
+  static uint32_t count = 0;
+
+  /* Read the value from the register */
+
+  uint16_t val = getreg16(addr);
+
+  /* Is this the same value that we read from the same register last time?
+   * Are we polling the register?  If so, suppress some of the output.
+   */
+
+  if (addr == prevaddr && val == preval)
+    {
+      if (count == 0xffffffff || ++count > 3)
+        {
+           if (count == 4)
+             {
+               uinfo("...\n");
+             }
+          return val;
+        }
+    }
+
+  /* No this is a new address or value */
+
+  else
+    {
+       /* Did we print "..." for the previous value? */
+
+       if (count > 3)
+         {
+           /* Yes.. then show how many times the value repeated */
+
+           uinfo("[repeats %d more times]\n", count - 3);
+         }
+
+       /* Save the new address, value, and count */
+
+       prevaddr = addr;
+       preval   = val;
+       count    = 1;
+    }
+
+  /* Show the register value read */
+
+  uinfo("%08x->%04x\n", addr, val);
+  return val;
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32l4_putreg
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32L4_USBDEV_REGDEBUG
+static void stm32l4_putreg(uint16_t val, uint32_t addr)
+{
+  /* Show the register value being written */
+
+  uinfo("%08x<-%04x\n", addr, val);
+
+  /* Write the value */
+
+  putreg16(val, addr);
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32l4_dumpep
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32L4_USBDEV_REGDEBUG
+static void stm32l4_dumpep(int epno)
+{
+  uint32_t addr;
+
+  /* Common registers */
+
+  uinfo("CNTR:   %04x\n", getreg16(STM32L4_USB_CNTR));
+  uinfo("ISTR:   %04x\n", getreg16(STM32L4_USB_ISTR));
+  uinfo("FNR:    %04x\n", getreg16(STM32L4_USB_FNR));
+  uinfo("DADDR:  %04x\n", getreg16(STM32L4_USB_DADDR));
+  uinfo("BTABLE: %04x\n", getreg16(STM32L4_USB_BTABLE));
+
+  /* Endpoint register */
+
+  addr = STM32L4_USB_EPR(epno);
+  uinfo("EPR%d:   [%08x] %04x\n", epno, addr, getreg16(addr));
+
+  /* Endpoint descriptor */
+
+  addr = STM32L4_USB_BTABLE_ADDR(epno, 0);
+  uinfo("DESC:   %08x\n", addr);
+
+  /* Endpoint buffer descriptor */
+
+  addr = STM32L4_USB_ADDR_TX(epno);
+  uinfo("  TX ADDR:  [%08x] %04x\n",  addr, getreg16(addr));
+
+  addr = STM32L4_USB_COUNT_TX(epno);
+  uinfo("     COUNT: [%08x] %04x\n",  addr, getreg16(addr));
+
+  addr = STM32L4_USB_ADDR_RX(epno);
+  uinfo("  RX ADDR:  [%08x] %04x\n",  addr, getreg16(addr));
+
+  addr = STM32L4_USB_COUNT_RX(epno);
+  uinfo("     COUNT: [%08x] %04x\n",  addr, getreg16(addr));
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32l4_checksetup
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32L4_USBDEV_REGDEBUG
+static void stm32l4_checksetup(void)
+{
+  uint32_t cfgr     = getreg32(STM32L4_RCC_CFGR);
+  uint32_t apb1rstr = getreg32(STM32L4_RCC_APB1RSTR1);
+  uint32_t apb1enr  = getreg32(STM32L4_RCC_APB1ENR1);
+
+  uinfo("CFGR: %08x APB1RSTR1: %08x APB1ENR1: %08x\n", cfgr, apb1rstr, apb1enr);
+
+  if ((apb1rstr & RCC_APB1RSTR1_USBFSRST) != 0 ||
+      (apb1enr & RCC_APB1ENR1_USBFSEN) == 0)
+    {
+      uerr("ERROR: USB is NOT setup correctly\n");
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32l4_seteptxcount
+ ****************************************************************************/
+
+static inline void stm32l4_seteptxcount(uint8_t epno, uint16_t count)
+{
+  volatile uint16_t *epaddr = (uint16_t *)STM32L4_USB_COUNT_TX(epno);
+  *epaddr = count;
+}
+
+/****************************************************************************
+ * Name: stm32l4_seteptxaddr
+ ****************************************************************************/
+
+static inline void stm32l4_seteptxaddr(uint8_t epno, uint16_t addr)
+{
+  volatile uint16_t *txaddr = (uint16_t *)STM32L4_USB_ADDR_TX(epno);
+  *txaddr = addr;
+}
+
+/****************************************************************************
+ * Name: stm32l4_geteptxaddr
+ ****************************************************************************/
+
+static inline uint16_t stm32l4_geteptxaddr(uint8_t epno)
+{
+  volatile uint16_t *txaddr = (uint16_t *)STM32L4_USB_ADDR_TX(epno);
+  return (uint16_t)*txaddr;
+}
+
+/****************************************************************************
+ * Name: stm32l4_seteprxcount
+ ****************************************************************************/
+
+static void stm32l4_seteprxcount(uint8_t epno, uint16_t count)
+{
+  volatile uint16_t *epaddr = (uint16_t *)STM32L4_USB_COUNT_RX(epno);
+  uint32_t rxcount = 0;
+  uint16_t nblocks;
+
+  /* The upper bits of the RX COUNT value contain the size of allocated
+   * RX buffer.  This is based on a block size of 2 or 32:
+   *
+   * USB_COUNT_RX_BL_SIZE not set:
+   *   nblocks is in units of 2 bytes.
+   *     00000 - not allowed
+   *     00001 - 2 bytes
+   *     ....
+   *     11111 - 62 bytes
+   *
+   * USB_COUNT_RX_BL_SIZE set:
+   *     00000 - 32 bytes
+   *     00001 - 64 bytes
+   *     ...
+   *     01111 - 512 bytes
+   *     1xxxx - Not allowed
+   */
+
+  if (count > 62)
+    {
+      /* Blocks of 32 (with 0 meaning one block of 32) */
+
+      nblocks = (count >> 5) - 1 ;
+      DEBUGASSERT(nblocks <= 0x0f);
+      rxcount = (uint32_t)((nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT) |
+                USB_COUNT_RX_BL_SIZE);
+    }
+  else if (count > 0)
+    {
+      /* Blocks of 2 (with 1 meaning one block of 2) */
+
+      nblocks = (count + 1) >> 1;
+      DEBUGASSERT(nblocks > 0 && nblocks < 0x1f);
+      rxcount = (uint32_t)(nblocks << USB_COUNT_RX_NUM_BLOCK_SHIFT);
+    }
+  *epaddr = rxcount;
+}
+
+/****************************************************************************
+ * Name: stm32l4_geteprxcount
+ ****************************************************************************/
+
+static inline uint16_t stm32l4_geteprxcount(uint8_t epno)
+{
+  volatile uint16_t *epaddr = (uint16_t *)STM32L4_USB_COUNT_RX(epno);
+  return (*epaddr) & USB_COUNT_RX_MASK;
+}
+
+/****************************************************************************
+ * Name: stm32l4_seteprxaddr
+ ****************************************************************************/
+
+static inline void stm32l4_seteprxaddr(uint8_t epno, uint16_t addr)
+{
+  volatile uint16_t *rxaddr = (uint16_t *)STM32L4_USB_ADDR_RX(epno);
+  *rxaddr = addr;
+}
+
+/****************************************************************************
+ * Name: stm32l4_seteprxaddr
+ ****************************************************************************/
+
+static inline uint16_t stm32l4_geteprxaddr(uint8_t epno)
+{
+  volatile uint16_t *rxaddr = (uint16_t *)STM32L4_USB_ADDR_RX(epno);
+  return (uint16_t)*rxaddr;
+}
+
+/****************************************************************************
+ * Name: stm32l4_setepaddress
+ ****************************************************************************/
+
+static inline void stm32l4_setepaddress(uint8_t epno, uint16_t addr)
+{
+  uint32_t epaddr = STM32L4_USB_EPR(epno);
+  uint16_t regval;
+
+  regval  = stm32l4_getreg(epaddr);
+  regval &= EPR_NOTOG_MASK;
+  regval &= ~USB_EPR_EA_MASK;
+  regval |= (addr << USB_EPR_EA_SHIFT);
+  stm32l4_putreg(regval, epaddr);
+}
+
+/****************************************************************************
+ * Name: stm32l4_seteptype
+ ****************************************************************************/
+
+static inline void stm32l4_seteptype(uint8_t epno, uint16_t type)
+{
+  uint32_t epaddr = STM32L4_USB_EPR(epno);
+  uint16_t regval;
+
+  regval  = stm32l4_getreg(epaddr);
+  regval &= EPR_NOTOG_MASK;
+  regval &= ~USB_EPR_EPTYPE_MASK;
+  regval |= type;
+  stm32l4_putreg(regval, epaddr);
+}
+
+/****************************************************************************
+ * Name: stm32l4_setstatusout
+ ****************************************************************************/
+
+static inline void stm32l4_setstatusout(uint8_t epno)
+{
+  uint32_t epaddr = STM32L4_USB_EPR(epno);
+  uint16_t regval;
+
+  /* For a BULK endpoint the EP_KIND bit is used to enabled double buffering;
+   * for a CONTROL endpoint, it is set to indicate that a status OUT
+   * transaction is expected.  The bit is not used with out endpoint types.
+   */
+
+  regval  = stm32l4_getreg(epaddr);
+  regval &= EPR_NOTOG_MASK;
+  regval |= USB_EPR_EP_KIND;
+  stm32l4_putreg(regval, epaddr);
+}
+
+/****************************************************************************
+ * Name: stm32l4_clrstatusout
+ ****************************************************************************/
+
+static inline void stm32l4_clrstatusout(uint8_t epno)
+{
+  uint32_t epaddr = STM32L4_USB_EPR(epno);
+  uint16_t regval;
+
+  /* For a BULK endpoint the EP_KIND bit is used to enabled double buffering;
+   * for a CONTROL endpoint, it is set to indicate that a status OUT
+   * transaction is expected.  The bit is not used with out endpoint types.
+   */
+
+  regval  = stm32l4_getreg(epaddr);
+  regval &= EPR_NOTOG_MASK;
+  regval &= ~USB_EPR_EP_KIND;
+  stm32l4_putreg(regval, epaddr);
+}
+
+/****************************************************************************
+ * Name: stm32l4_clrrxdtog
+ ****************************************************************************/
+
+static void stm32l4_clrrxdtog(uint8_t epno)
+{
+  uint32_t epaddr = STM32L4_USB_EPR(epno);
+  uint16_t regval;
+
+  regval = stm32l4_getreg(epaddr);
+  if ((regval & USB_EPR_DTOG_RX) != 0)
+    {
+      regval &= EPR_NOTOG_MASK;
+      regval |= USB_EPR_DTOG_RX;
+      stm32l4_putreg(regval, epaddr);
+    }
+}
+
+/****************************************************************************
+ * Name: stm32l4_clrtxdtog
+ ****************************************************************************/
+
+static void stm32l4_clrtxdtog(uint8_t epno)
+{
+  uint32_t epaddr = STM32L4_USB_EPR(epno);
+  uint16_t regval;
+
+  regval = stm32l4_getreg(epaddr);
+  if ((regval & USB_EPR_DTOG_TX) != 0)
+    {
+      regval &= EPR_NOTOG_MASK;
+      regval |= USB_EPR_DTOG_TX;
+      stm32l4_putreg(regval, epaddr);
+    }
+}
+
+/****************************************************************************
+ * Name: stm32l4_clrepctrrx
+ ****************************************************************************/
+
+static void stm32l4_clrepctrrx(uint8_t epno)
+{
+  uint32_t epaddr = STM32L4_USB_EPR(epno);
+  uint16_t regval;
+
+  regval  = stm32l4_getreg(epaddr);
+  regval &= EPR_NOTOG_MASK;
+  regval &= ~USB_EPR_CTR_RX;
+  stm32l4_putreg(regval, epaddr);
+}
+
+/****************************************************************************
+ * Name: stm32l4_clrepctrtx
+ ****************************************************************************/
+
+static void stm32l4_clrepctrtx(uint8_t epno)
+{
+  uint32_t epaddr = STM32L4_USB_EPR(epno);
+  uint16_t regval;
+
+  regval  = stm32l4_getreg(epaddr);
+  regval &= EPR_NOTOG_MASK;
+  regval &= ~USB_EPR_CTR_TX;
+  stm32l4_putreg(regval, epaddr);
+}
+
+/****************************************************************************
+ * Name: stm32l4_geteptxstatus
+ ****************************************************************************/
+
+static inline uint16_t stm32l4_geteptxstatus(uint8_t epno)
+{
+  return (uint16_t)(stm32l4_getreg(STM32L4_USB_EPR(epno)) & USB_EPR_STATTX_MASK);
+}
+
+/****************************************************************************
+ * Name: stm32l4_geteprxstatus
+ ****************************************************************************/
+
+static inline uint16_t stm32l4_geteprxstatus(uint8_t epno)
+{
+  return (stm32l4_getreg(STM32L4_USB_EPR(epno)) & USB_EPR_STATRX_MASK);
+}
+
+/****************************************************************************
+ * Name: stm32l4_seteptxstatus
+ ****************************************************************************/
+
+static void stm32l4_seteptxstatus(uint8_t epno, uint16_t state)
+{
+  uint32_t epaddr = STM32L4_USB_EPR(epno);
+  uint16_t regval;
+
+  /* The bits in the STAT_TX field can be toggled by software to set their
+   * value. When set to 0, the value remains unchanged; when set to one,
+   * value toggles.
+   */
+
+  regval = stm32l4_getreg(epaddr);
+
+  /* The exclusive OR will set STAT_TX bits to 1 if there value is different
+   * from the bits requested in 'state'
+   */
+
+  regval ^= state;
+  regval &= EPR_TXDTOG_MASK;
+  stm32l4_putreg(regval, epaddr);
+}
+
+/****************************************************************************
+ * Name: stm32l4_seteprxstatus
+ ****************************************************************************/
+
+static void stm32l4_seteprxstatus(uint8_t epno, uint16_t state)
+{
+  uint32_t epaddr = STM32L4_USB_EPR(epno);
+  uint16_t regval;
+
+  /* The bits in the STAT_RX field can be toggled by software to set their
+   * value. When set to 0, the value remains unchanged; when set to one,
+   * value toggles.
+   */
+
+  regval = stm32l4_getreg(epaddr);
+
+  /* The exclusive OR will set STAT_RX bits to 1 if there value is different
+   * from the bits requested in 'state'
+   */
+
+  regval ^= state;
+  regval &= EPR_RXDTOG_MASK;
+  stm32l4_putreg(regval, epaddr);
+}
+
+/****************************************************************************
+ * Name: stm32l4_eptxstalled
+ ****************************************************************************/
+
+static inline bool stm32l4_eptxstalled(uint8_t epno)
+{
+  return (stm32l4_geteptxstatus(epno) == USB_EPR_STATTX_STALL);
+}
+
+/****************************************************************************
+ * Name: stm32l4_eprxstalled
+ ****************************************************************************/
+
+static inline bool stm32l4_eprxstalled(uint8_t epno)
+{
+  return (stm32l4_geteprxstatus(epno) == USB_EPR_STATRX_STALL);
+}
+
+/****************************************************************************
+ * Name: stm32l4_copytopma
+ ****************************************************************************/
+
+static void stm32l4_copytopma(const uint8_t *buffer, uint16_t pma,
+                              uint16_t nbytes)
+{
+  volatile uint16_t *dest;
+  uint16_t ms;
+  uint16_t ls;
+  int     nwords = (nbytes + 1) >> 1;
+  int     i;
+
+  /* Copy loop.  Source=user buffer, Dest=packet memory */
+
+  dest = (volatile uint16_t *)(STM32L4_USB_SRAM_BASE + (uint32_t)pma);
+  for (i = nwords; i != 0; i--)
+    {
+      /* Read two bytes and pack into on 16-bit word */
+
+      ls = (uint16_t)(*buffer++);
+      ms = (uint16_t)(*buffer++);
+      *dest = ms << 8 | ls;
+
+      /* Source address increments by 2*sizeof(uint8_t) = 2; Dest address
+       * increments by 1*sizeof(uint16_t) = 2.
+       */
+
+      dest += 1;
+    }
+}
+
+/****************************************************************************
+ * Name: stm32l4_copyfrompma
+ ****************************************************************************/
+
+static inline void
+stm32l4_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes)
+{
+  volatile uint16_t *src;
+  int nwords = (nbytes + 1) >> 1;
+  int i;
+
+  /* Copy loop.  Source=packet memory, Dest=user buffer */
+
+  src = (volatile uint16_t *)(STM32L4_USB_SRAM_BASE + (uint32_t)pma);
+  for (i = nwords; i != 0; i--)
+    {
+      /* Copy 16-bits from packet memory to user buffer. */
+
+      *(uint16_t *)buffer = *src++;
+
+      /* Source address increments by 1*sizeof(uint16_t) = 2; Dest address
+       * increments by 2*sizeof(uint8_t) = 2.
+       */
+
+      buffer += 2;
+    }
+}
+
+/****************************************************************************
+ * Name: stm32l4_rqdequeue
+ ****************************************************************************/
+
+static struct stm32l4_req_s *stm32l4_rqdequeue(struct stm32l4_ep_s *privep)
+{
+  struct stm32l4_req_s *ret = privep->head;
+
+  if (ret)
+    {
+      privep->head = ret->flink;
+      if (!privep->head)
+        {
+          privep->tail = NULL;
+        }
+
+      ret->flink = NULL;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: stm32l4_rqenqueue
+ ****************************************************************************/
+
+static void stm32l4_rqenqueue(struct stm32l4_ep_s *privep,
+                              struct stm32l4_req_s *req)
+{
+  req->flink = NULL;
+  if (!privep->head)
+    {
+      privep->head = req;
+      privep->tail = req;
+    }
+  else
+    {
+      privep->tail->flink = req;
+      privep->tail        = req;
+    }
+}
+
+/****************************************************************************
+ * Name: stm32l4_abortrequest
+ ****************************************************************************/
+
+static inline void
+stm32l4_abortrequest(struct stm32l4_ep_s *privep,
+                     struct stm32l4_req_s *privreq, int16_t result)
+{
+  usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_REQABORTED),
+           (uint16_t)USB_EPNO(privep->ep.eplog));
+
+  /* Save the result in the request structure */
+
+  privreq->req.result = result;
+
+  /* Callback to the request completion handler */
+
+  privreq->req.callback(&privep->ep, &privreq->req);
+}
+
+/****************************************************************************
+ * Name: stm32l4_reqcomplete
+ ****************************************************************************/
+
+static void stm32l4_reqcomplete(struct stm32l4_ep_s *privep, int16_t result)
+{
+  struct stm32l4_req_s *privreq;
+  irqstate_t flags;
+
+  /* Remove the completed request at the head of the endpoint request list */
+
+  flags = enter_critical_section();
+  privreq = stm32l4_rqdequeue(privep);
+  leave_critical_section(flags);
+
+  if (privreq)
+    {
+      /* If endpoint 0, temporarily reflect the state of protocol stalled
+       * in the callback.
+       */
+
+      bool stalled = privep->stalled;
+      if (USB_EPNO(privep->ep.eplog) == EP0)
+        {
+          privep->stalled = (privep->dev->ep0state == EP0STATE_STALLED);
+        }
+
+      /* Save the result in the request structure */
+
+      privreq->req.result = result;
+
+      /* Callback to the request completion handler */
+
+      privreq->flink = NULL;
+      privreq->req.callback(&privep->ep, &privreq->req);
+
+      /* Restore the stalled indication */
+
+      privep->stalled = stalled;
+    }
+}
+
+/****************************************************************************
+ * Name: tm32_epwrite
+ ****************************************************************************/
+
+static void stm32l4_epwrite(struct stm32l4_usbdev_s *priv,
+                          struct stm32l4_ep_s *privep,
+                          const uint8_t *buf, uint32_t nbytes)
+{
+  uint8_t epno = USB_EPNO(privep->ep.eplog);
+  usbtrace(TRACE_WRITE(epno), nbytes);
+
+  /* Check for a zero-length packet */
+
+  if (nbytes > 0)
+    {
+      /* Copy the data from the user buffer into packet memory for this
+       * endpoint
+       */
+
+      stm32l4_copytopma(buf, stm32l4_geteptxaddr(epno), nbytes);
+    }
+
+  /* Send the packet (might be a null packet nbytes == 0) */
+
+  stm32l4_seteptxcount(epno, nbytes);
+  priv->txstatus = USB_EPR_STATTX_VALID;
+
+  /* Indicate that there is data in the TX packet memory.  This will be cleared
+   * when the next data out interrupt is received.
+   */
+
+  privep->txbusy = true;
+}
+
+/****************************************************************************
+ * Name: stm32l4_wrrequest_ep0
+ *
+ * Description:
+ *   Handle the ep0 state on writes.
+ *
+ ****************************************************************************/
+
+inline static int stm32l4_wrrequest_ep0(struct stm32l4_usbdev_s *priv,
+                                      struct stm32l4_ep_s *privep)
+{
+  int ret;
+  ret = stm32l4_wrrequest(priv, privep);
+  priv->ep0state = ((ret == OK) ? EP0STATE_WRREQUEST : EP0STATE_IDLE);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: stm32l4_wrrequest
+ ****************************************************************************/
+
+static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv,
+                             struct stm32l4_ep_s *privep)
+{
+  struct stm32l4_req_s *privreq;
+  uint8_t *buf;
+  uint8_t epno;
+  int nbytes;
+  int bytesleft;
+
+  /* We get here when an IN endpoint interrupt occurs.  So now we know that
+   * there is no TX transfer in progress.
+   */
+
+  privep->txbusy = false;
+
+  /* Check the request from the head of the endpoint request queue */
+
+  privreq = stm32l4_rqpeek(privep);
+  if (!privreq)
+    {
+      /* There is no TX transfer in progress and no new pending TX
+       * requests to send.
+       */
+
+      usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPINQEMPTY), 0);
+      return -ENOENT;
+    }
+
+  epno = USB_EPNO(privep->ep.eplog);
+  uinfo("epno=%d req=%p: len=%d xfrd=%d nullpkt=%d\n",
+        epno, privreq, privreq->req.len, privreq->req.xfrd, privep->txnullpkt);
+  UNUSED(epno);
+
+  /* Get the number of bytes left to be sent in the packet */
+
+  bytesleft         = privreq->req.len - privreq->req.xfrd;
+  nbytes            = bytesleft;
+
+#warning "REVISIT: If the EP supports double buffering, then we can do better"
+
+  /* Either (1) we are committed to sending the null packet (because txnullpkt == 1
+   * && nbytes == 0), or (2) we have not yet send the last packet (nbytes > 0).
+   * In either case, it is appropriate to clearn txnullpkt now.
+   */
+
+  privep->txnullpkt = 0;
+
+  /* If we are not sending a NULL packet, then clip the size to maxpacket
+   * and check if we need to send a following NULL packet.
+   */
+
+  if (nbytes > 0)
+    {
+      /* Either send the maxpacketsize or all of the remaining data in
+       * the request.
+       */
+
+      if (nbytes >= privep->ep.maxpacket)
+        {
+          nbytes =  privep->ep.maxpacket;
+
+          /* Handle the case where this packet is exactly the
+           * maxpacketsize.  Do we need to send a zero-length packet
+           * in this case?
+           */
+
+          if (bytesleft ==  privep->ep.maxpacket &&
+             (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0)
+            {
+              privep->txnullpkt = 1;
+            }
+        }
+    }
+
+  /* Send the packet (might be a null packet nbytes == 0) */
+
+  buf = privreq->req.buf + privreq->req.xfrd;
+  stm32l4_epwrite(priv, privep, buf, nbytes);
+
+  /* Update for the next data IN interrupt */
+
+  privreq->req.xfrd += nbytes;
+  bytesleft          = privreq->req.len - privreq->req.xfrd;
+
+  /* If all of the bytes were sent (including any final null packet)
+   * then we are finished with the request buffer).
+   */
+
+  if (bytesleft == 0 && !privep->txnullpkt)
+    {
+      /* Return the write request to the class driver */
+
+      usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd);
+      privep->txnullpkt = 0;
+      stm32l4_reqcomplete(privep, OK);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32l4_ep0_rdrequest
+ *
+ * Description:
+ *   This function is called from the stm32l4_ep0out handler when the ep0state
+ *   is EP0STATE_SETUP_OUT and uppon new incoming data is available in the
+ *   endpoint 0's buffer.  This function will simply copy the OUT data into
+ *   ep0data.
+ *
+ ****************************************************************************/
+
+static inline int stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv)
+{
+  uint32_t src;
+  int pmalen;
+  int readlen;
+
+  /* Get the number of bytes to read from packet memory */
+
+  pmalen  = stm32l4_geteprxcount(EP0);
+
+  uinfo("EP0: pmalen=%d\n", pmalen);
+  usbtrace(TRACE_READ(EP0), pmalen);
+
+  /* Read the data into our special buffer for SETUP data */
+
+  readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, pmalen);
+  src     = stm32l4_geteprxaddr(EP0);
+
+  /* Receive the next packet */
+
+  stm32l4_copyfrompma(&priv->ep0data[0], src, readlen);
+
+  /* Now we can process the setup command */
+
+  priv->ep0state  = EP0STATE_SETUP_READY;
+  priv->ep0datlen = readlen;
+  usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPOUTDATA), readlen);
+
+  stm32l4_ep0setup(priv);
+  priv->ep0datlen = 0; /* mark the date consumed */
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32l4_rdrequest
+ ****************************************************************************/
+
+static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep)
+{
+  struct stm32l4_req_s *privreq;
+  uint32_t src;
+  uint8_t *dest;
+  uint8_t epno;
+  int pmalen;
+  int readlen;
+
+  /* Check the request from the head of the endpoint request queue */
+
+  epno    = USB_EPNO(privep->ep.eplog);
+  privreq = stm32l4_rqpeek(privep);
+  if (!privreq)
+    {
+      /* Incoming data available in PMA, but no packet to receive the data.
+       * Mark that the RX data is pending and hope that a packet is returned
+       * soon.
+       */
+
+      usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUTQEMPTY), epno);
+      return -ENOENT;
+    }
+
+  uinfo("EP%d: len=%d xfrd=%d\n", epno, privreq->req.len, privreq->req.xfrd);
+
+  /* Ignore any attempt to receive a zero length packet */
+
+  if (privreq->req.len == 0)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTNULLPACKET), 0);
+      stm32l4_reqcomplete(privep, OK);
+      return OK;
+    }
+
+  usbtrace(TRACE_READ(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd);
+
+  /* Get the source and destination transfer addresses */
+
+  dest    = privreq->req.buf + privreq->req.xfrd;
+  src     = stm32l4_geteprxaddr(epno);
+
+  /* Get the number of bytes to read from packet memory */
+
+  pmalen  = stm32l4_geteprxcount(epno);
+  readlen = MIN(privreq->req.len, pmalen);
+
+  /* Receive the next packet */
+
+  stm32l4_copyfrompma(dest, src, readlen);
+
+  /* If the receive buffer is full or this is a partial packet,
+   * then we are finished with the request buffer).
+   */
+
+  privreq->req.xfrd += readlen;
+  if (pmalen < privep->ep.maxpacket || privreq->req.xfrd >= privreq->req.len)
+    {
+      /* Return the read request to the class driver. */
+
+      usbtrace(TRACE_COMPLETE(epno), privreq->req.xfrd);
+      stm32l4_reqcomplete(privep, OK);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32l4_cancelrequests
+ ****************************************************************************/
+
+static void stm32l4_cancelrequests(struct stm32l4_ep_s *privep)
+{
+  while (!stm32l4_rqempty(privep))
+    {
+      usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)),
+               (stm32l4_rqpeek(privep))->req.xfrd);
+      stm32l4_reqcomplete(privep, -ESHUTDOWN);
+    }
+}
+
+/****************************************************************************
+ * Interrupt Level Processing
+ ****************************************************************************/
+/****************************************************************************
+ * Name: stm32l4_dispatchrequest
+ ****************************************************************************/
+
+static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv)
+{
+  int ret;
+
+  usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_DISPATCH), 0);
+  if (priv && priv->driver)
+    {
+      /* Forward to the control request to the class driver implementation */
+
+      ret = CLASS_SETUP(priv->driver, &priv->usbdev, &priv->ctrl,
+                        priv->ep0data, priv->ep0datlen);
+      if (ret < 0)
+        {
+          /* Stall on failure */
+
+          usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DISPATCHSTALL), 0);
+          priv->ep0state = EP0STATE_STALLED;
+        }
+    }
+}
+
+/****************************************************************************
+ * Name: stm32l4_epdone
+ ****************************************************************************/
+
+static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno)
+{
+  struct stm32l4_ep_s *privep;
+  uint16_t epr;
+
+  /* Decode and service non control endpoints interrupt */
+
+  epr    = stm32l4_getreg(STM32L4_USB_EPR(epno));
+  privep = &priv->eplist[epno];
+
+  /* OUT: host-to-device
+   * CTR_RX is set by the hardware when an OUT/SETUP transaction
+   * successfully completed on this endpoint.
+   */
+
+  if ((epr & USB_EPR_CTR_RX) != 0)
+    {
+      usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUTDONE), epr);
+
+      /* Handle read requests.  First check if a read request is available to
+       * accept the host data.
+       */
+
+      if (!stm32l4_rqempty(privep))
+        {
+          /* Read host data into the current read request */
+
+          (void)stm32l4_rdrequest(priv, privep);
+
+          /* "After the received data is processed, the application software
+           *  should set the STAT_RX bits to '11' (Valid) in the USB_EPnR,
+           *  enabling further transactions. "
+           */
+
+          priv->rxstatus  = USB_EPR_STATRX_VALID;
+        }
+
+      /* NAK further OUT packets if there there no more read requests */
+
+      if (stm32l4_rqempty(privep))
+        {
+          usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUTPENDING),
+                   (uint16_t)epno);
+
+          /* Mark the RX processing as pending and NAK any OUT actions
+           * on this endpoint.  "While the STAT_RX bits are equal to '10'
+           * (NAK), any OUT request addressed to that endpoint is NAKed,
+           * indicating a flow control condition: the USB host will retry
+           * the transaction until it succeeds."
+           */
+
+          priv->rxstatus  = USB_EPR_STATRX_NAK;
+          priv->rxpending = true;
+        }
+
+      /* Clear the interrupt status and set the new RX status */
+
+      stm32l4_clrepctrrx(epno);
+      stm32l4_seteprxstatus(epno, priv->rxstatus);
+    }
+
+  /* IN: device-to-host
+   * CTR_TX is set when an IN transaction successfully completes on
+   * an endpoint
+   */
+
+  else if ((epr & USB_EPR_CTR_TX) != 0)
+    {
+      /* Clear interrupt status */
+
+      stm32l4_clrepctrtx(epno);
+      usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPINDONE), epr);
+
+      /* Handle write requests */
+
+      priv->txstatus = USB_EPR_STATTX_NAK;
+      if (epno == EP0)
+        {
+          (void)stm32l4_wrrequest_ep0(priv, privep);
+        }
+      else
+        {
+          (void)stm32l4_wrrequest(priv, privep);
+        }
+
+      /* Set the new TX status */
+
+      stm32l4_seteptxstatus(epno, priv->txstatus);
+    }
+}
+
+/****************************************************************************
+ * Name: stm32l4_setdevaddr
+ ****************************************************************************/
+
+static void stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, uint8_t value)
+{
+  int epno;
+
+  /* Set address in every allocated endpoint */
+
+  for (epno = 0; epno < STM32L4_NENDPOINTS; epno++)
+    {
+      if (stm32l4_epreserved(priv, epno))
+        {
+          stm32l4_setepaddress((uint8_t)epno, (uint8_t)epno);
+        }
+    }
+
+  /* Set the device address and enable function */
+
+  stm32l4_putreg(value | USB_DADDR_EF, STM32L4_USB_DADDR);
+}
+
+/****************************************************************************
+ * Name: stm32l4_ep0setup
+ ****************************************************************************/
+
+static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv)
+{
+  struct stm32l4_ep_s   *ep0     = &priv->eplist[EP0];
+  struct stm32l4_req_s  *privreq = stm32l4_rqpeek(ep0);
+  struct stm32l4_ep_s   *privep;
+  union wb_u           value;
+  union wb_u           index;
+  union wb_u           len;
+  union wb_u           response;
+  bool                 handled = false;
+  uint8_t              epno;
+  int                  nbytes = 0; /* Assume zero-length packet */
+
+  /* Terminate any pending requests (doesn't work if the pending request
+   * was a zero-length transfer!)
+   */
+
+  while (!stm32l4_rqempty(ep0))
+    {
+      int16_t result = OK;
+      if (privreq->req.xfrd != privreq->req.len)
+        {
+          result = -EPROTO;
+        }
+
+      usbtrace(TRACE_COMPLETE(ep0->ep.eplog), privreq->req.xfrd);
+      stm32l4_reqcomplete(ep0, result);
+    }
+
+  /* Assume NOT stalled; no TX in progress */
+
+  ep0->stalled  = 0;
+  ep0->txbusy   = 0;
+
+  /* Check to see if called from the DATA phase of a SETUP Transfer */
+
+  if (priv->ep0state != EP0STATE_SETUP_READY)
+    {
+      /* Not the data phase
+       *
+       * Get a 32-bit PMA address and use that to get the 8-byte setup
+       * request
+       */
+
+      stm32l4_copyfrompma((uint8_t *)&priv->ctrl, stm32l4_geteprxaddr(EP0),
+                        USB_SIZEOF_CTRLREQ);
+
+      /* And extract the little-endian 16-bit values to host order */
+
+      value.w = GETUINT16(priv->ctrl.value);
+      index.w = GETUINT16(priv->ctrl.index);
+      len.w   = GETUINT16(priv->ctrl.len);
+
+      uinfo("SETUP: type=%02x req=%02x value=%04x index=%04x len=%04x\n",
+            priv->ctrl.type, priv->ctrl.req, value.w, index.w, len.w);
+
+      /* Is this an setup with OUT and data of length > 0 */
+
+      if (USB_REQ_ISOUT(priv->ctrl.type) && len.w > 0)
+        {
+          usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPOUT), len.w);
+
+          /* At this point priv->ctrl is the setup packet. */
+
+          priv->ep0state = EP0STATE_SETUP_OUT;
+          return;
+        }
+      else
+        {
+          priv->ep0state = EP0STATE_SETUP_READY;
+        }
+    }
+
+  /* Dispatch any non-standard requests */
+
+  if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD)
+    {
+      usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_NOSTDREQ), priv->ctrl.type);
+
+      /* Let the class implementation handle all non-standar requests */
+
+      stm32l4_dispatchrequest(priv);
+      return;
+    }
+
+  /* Handle standard request.  Pick off the things of interest to the
+   * USB device controller driver; pass what is left to the class driver
+   */
+
+  switch (priv->ctrl.req)
+    {
+    case USB_REQ_GETSTATUS:
+      {
+        /* type:  device-to-host; recipient = device, interface, endpoint
+         * value: 0
+         * index: zero interface endpoint
+         * len:   2; data = status
+         */
+
+        usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSTATUS), priv->ctrl.type);
+        if (len.w != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 ||
+            index.b[MSB] != 0 || value.w != 0)
+          {
+            usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPGETSTATUS), 0);
+            priv->ep0state = EP0STATE_STALLED;
+          }
+        else
+          {
+            switch (priv->ctrl.type & USB_REQ_RECIPIENT_MASK)
+              {
+               case USB_REQ_RECIPIENT_ENDPOINT:
+                {
+                  epno = USB_EPNO(index.b[LSB]);
+                  usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPGETSTATUS),
+                           epno);
+                  if (epno >= STM32L4_NENDPOINTS)
+                    {
+                      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPGETSTATUS),
+                               epno);
+                      priv->ep0state = EP0STATE_STALLED;
+                    }
+                  else
+                    {
+                      response.w = 0; /* Not stalled */
+                      nbytes     = 2; /* Response size: 2 bytes */
+
+                      if (USB_ISEPIN(index.b[LSB]))
+                        {
+                          /* IN endpoint */
+
+                          if (stm32l4_eptxstalled(epno))
+                            {
+                              /* IN Endpoint stalled */
+
+                              response.b[LSB] = 1; /* Stalled */
+                            }
+                          }
+                      else
+                        {
+                          /* OUT endpoint */
+
+                          if (stm32l4_eprxstalled(epno))
+                            {
+                              /* OUT Endpoint stalled */
+
+                              response.b[LSB] = 1; /* Stalled */
+                            }
+                        }
+                    }
+                }
+                break;
+
+              case USB_REQ_RECIPIENT_DEVICE:
+                {
+                 if (index.w == 0)
+                    {
+                      usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_DEVGETSTATUS), 0);
+
+                      /* Features:  Remote Wakeup=YES; selfpowered=? */
+
+                      response.w      = 0;
+                      response.b[LSB] = (priv->selfpowered << USB_FEATURE_SELFPOWERED) |
+                                        (1 << USB_FEATURE_REMOTEWAKEUP);
+                      nbytes          = 2; /* Response size: 2 bytes */
+                    }
+                  else
+                    {
+                      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADDEVGETSTATUS), 0);
+                      priv->ep0state = EP0STATE_STALLED;
+                    }
+                }
+                break;
+
+              case USB_REQ_RECIPIENT_INTERFACE:
+                {
+                  usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IFGETSTATUS), 0);
+                  response.w = 0;
+                  nbytes     = 2; /* Response size: 2 bytes */
+                }
+                break;
+
+              default:
+                {
+                  usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETSTATUS), 0);
+                  priv->ep0state = EP0STATE_STALLED;
+                }
+                break;
+              }
+          }
+      }
+      break;
+
+    case USB_REQ_CLEARFEATURE:
+      {
+        /* type:  host-to-device; recipient = device, interface or endpoint
+         * value: feature selector
+         * index: zero interface endpoint;
+         * len:   zero, data = none
+         */
+
+        usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_CLEARFEATURE),
+                 priv->ctrl.type);
+        if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) !=
+            USB_REQ_RECIPIENT_ENDPOINT)
+          {
+            /* Let the class implementation handle all recipients (except for the
+             * endpoint recipient)
+             */
+
+            stm32l4_dispatchrequest(priv);
+            handled = true;
+          }
+        else
+          {
+            /* Endpoint recipient */
+
+            epno = USB_EPNO(index.b[LSB]);
+            if (epno < STM32L4_NENDPOINTS && index.b[MSB] == 0 &&
+                value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0)
+              {
+                privep         = &priv->eplist[epno];
+                privep->halted = 0;
+                (void)stm32l4_epstall(&privep->ep, true);
+              }
+            else
+              {
+                usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADCLEARFEATURE), 0);
+                priv->ep0state = EP0STATE_STALLED;
+              }
+          }
+      }
+      break;
+
+    case USB_REQ_SETFEATURE:
+      {
+        /* type:  host-to-device; recipient = device, interface, endpoint
+         * value: feature selector
+         * index: zero interface endpoint;
+         * len:   0; data = none
+         */
+
+        usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETFEATURE),
+                 priv->ctrl.type);
+        if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) ==
+            USB_REQ_RECIPIENT_DEVICE) && value.w == USB_FEATURE_TESTMODE)
+          {
+            /* Special case recipient=device test mode */
+
+            uinfo("test mode: %d\n", index.w);
+          }
+        else if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) !=
+                 USB_REQ_RECIPIENT_ENDPOINT)
+          {
+            /* The class driver handles all recipients except recipient=
+             * endpoint
+             */
+
+            stm32l4_dispatchrequest(priv);
+            handled = true;
+          }
+        else
+          {
+            /* Handler recipient=endpoint */
+
+            epno = USB_EPNO(index.b[LSB]);
+            if (epno < STM32L4_NENDPOINTS && index.b[MSB] == 0 &&
+                value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0)
+              {
+                privep         = &priv->eplist[epno];
+                privep->halted = 1;
+                (void)stm32l4_epstall(&privep->ep, false);
+              }
+            else
+              {
+                usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETFEATURE), 0);
+                priv->ep0state = EP0STATE_STALLED;
+              }
+          }
+      }
+      break;
+
+    case USB_REQ_SETADDRESS:
+      {
+        /* type:  host-to-device; recipient = device
+         * value: device address
+         * index: 0
+         * len:   0; data = none
+         */
+
+        usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPSETADDRESS),
+                 value.w);
+        if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) !=
+            USB_REQ_RECIPIENT_DEVICE ||
+            index.w != 0 || len.w != 0 || value.w > 127)
+          {
+            usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETADDRESS), 0);
+            priv->ep0state = EP0STATE_STALLED;
+          }
+
+        /* Note that setting of the device address will be deferred.  A zero-l
+         * ength packet will be sent and the device address will be set when
+         * the zero-length packet transfer completes.
+         */
+      }
+      break;
+
+    case USB_REQ_GETDESCRIPTOR:
+      /* type:  device-to-host; recipient = device
+       * value: descriptor type and index
+       * index: 0 or language ID;
+       * len:   descriptor len; data = descriptor
+       */
+    case USB_REQ_SETDESCRIPTOR:
+      /* type:  host-to-device; recipient = device
+       * value: descriptor type and index
+       * index: 0 or language ID;
+       * len:   descriptor len; data = descriptor
+       */
+
+      {
+        usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETDESC), priv->ctrl.type);
+
+        /* The request seems valid... let the class implementation handle it */
+
+        stm32l4_dispatchrequest(priv);
+        handled = true;
+      }
+      break;
+
+    case USB_REQ_GETCONFIGURATION:
+      /* type:  device-to-host; recipient = device
+       * value: 0;
+       * index: 0;
+       * len:   1; data = configuration value
+       */
+
+      {
+        usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETCONFIG),
+                 priv->ctrl.type);
+        if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) ==
+            USB_REQ_RECIPIENT_DEVICE &&
+            value.w == 0 && index.w == 0 && len.w == 1)
+          {
+            /* The request seems valid... let the class implementation handle it */
+
+            stm32l4_dispatchrequest(priv);
+            handled = true;
+          }
+        else
+          {
+            usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETCONFIG), 0);
+            priv->ep0state = EP0STATE_STALLED;
+          }
+      }
+      break;
+
+    case USB_REQ_SETCONFIGURATION:
+      /* type:  host-to-device; recipient = device
+       * value: configuration value
+       * index: 0;
+       * len:   0; data = none
+       */
+
+      {
+        usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETCONFIG),
+                 priv->ctrl.type);
+        if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) ==
+            USB_REQ_RECIPIENT_DEVICE && index.w == 0 && len.w == 0)
+          {
+             /* The request seems valid... let the class implementation handle it */
+
+             stm32l4_dispatchrequest(priv);
+             handled = true;
+          }
+        else
+          {
+            usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETCONFIG), 0);
+            priv->ep0state = EP0STATE_STALLED;
+          }
+      }
+      break;
+
+    case USB_REQ_GETINTERFACE:
+      /* type:  device-to-host; recipient = interface
+       * value: 0
+       * index: interface;
+       * len:   1; data = alt interface
+       */
+    case USB_REQ_SETINTERFACE:
+      /* type:  host-to-device; recipient = interface
+       * value: alternate setting
+       * index: interface;
+       * len:   0; data = none
+       */
+
+      {
+        /* Let the class implementation handle the request */
+
+        usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETIF), priv->ctrl.type);
+        stm32l4_dispatchrequest(priv);
+        handled = true;
+      }
+      break;
+
+    case USB_REQ_SYNCHFRAME:
+      /* type:  device-to-host; recipient = endpoint
+       * value: 0
+       * index: endpoint;
+       * len:   2; data = frame number
+       */
+
+      {
+        usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SYNCHFRAME), 0);
+      }
+      break;
+
+    default:
+      {
+        usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDCTRLREQ), priv->ctrl.req);
+        priv->ep0state = EP0STATE_STALLED;
+      }
+      break;
+    }
+
+  /* At this point, the request has been handled and there are three possible
+   * outcomes:
+   *
+   * 1. The setup request was successfully handled above and a response packet
+   *    must be sent (may be a zero length packet).
+   * 2. The request was successfully handled by the class implementation.  In
+   *    case, the EP0 IN response has already been queued and the local variable
+   *    'handled' will be set to true and ep0state != EP0STATE_STALLED;
+   * 3. An error was detected in either the above logic or by the class
+   *    implementationlogic.  In either case, priv->state will be set
+   *    EP0STATE_STALLED to indicate this case.
+   *
+   * NOTE: Non-standard requests are a special case.  They are handled by the
+   * class implementation and this function returned early above, skipping this
+   * logic altogether.
+   */
+
+  if (priv->ep0state != EP0STATE_STALLED && !handled)
+    {
+      /* We will response.  First, restrict the data length to the length
+       * requested in the setup packet
+       */
+
+      if (nbytes > len.w)
+        {
+          nbytes = len.w;
+        }
+
+      /* Send the response (might be a zero-length packet) */
+
+      stm32l4_epwrite(priv, ep0, response.b, nbytes);
+      priv->ep0state = EP0STATE_IDLE;
+    }
+}
+
+/****************************************************************************
+ * Name: stm32l4_ep0in
+ ****************************************************************************/
+
+static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv)
+{
+  /* There is no longer anything in the EP0 TX packet memory */
+
+  priv->eplist[EP0].txbusy = false;
+
+  /* Are we processing the completion of one packet of an outgoing request
+   * from the class driver?
+   */
+
+  if (priv->ep0state == EP0STATE_WRREQUEST)
+    {
+      stm32l4_wrrequest_ep0(priv, &priv->eplist[EP0]);
+    }
+
+  /* No.. Are we processing the completion of a status response? */
+
+  else if (priv->ep0state == EP0STATE_IDLE)
+    {
+      /* Look at the saved SETUP command.  Was it a SET ADDRESS request?
+       * If so, then now is the time to set the address.
+       */
+
+      if (priv->ctrl.req == USB_REQ_SETADDRESS &&
+          (priv->ctrl.type & REQRECIPIENT_MASK) ==
+           (USB_REQ_TYPE_STANDARD | USB_REQ_RECIPIENT_DEVICE))
+        {
+          union wb_u value;
+          value.w = GETUINT16(priv->ctrl.value);
+          stm32l4_setdevaddr(priv, value.b[LSB]);
+        }
+    }
+  else
+    {
+      priv->ep0state = EP0STATE_STALLED;
+    }
+}
+
+/****************************************************************************
+ * Name: stm32l4_ep0out
+ ****************************************************************************/
+
+static void stm32l4_ep0out(struct stm32l4_usbdev_s *priv)
+{
+  int ret;
+
+  struct stm32l4_ep_s *privep = &priv->eplist[EP0];
+  switch (priv->ep0state)
+    {
+      case EP0STATE_RDREQUEST:           /* Read request in progress */
+      case EP0STATE_IDLE:                /* No transfer in progress */
+        ret = stm32l4_rdrequest(priv, privep);
+        priv->ep0state = ((ret == OK) ? EP0STATE_RDREQUEST : EP0STATE_IDLE);
+        break;
+
+      case EP0STATE_SETUP_OUT:           /* SETUP was waiting for data */
+        ret = stm32l4_ep0_rdrequest(priv); /* Off load the data and run the
+                                          * last set up command with the OUT
+                                          * data
+                                          */
+        priv->ep0state = EP0STATE_IDLE;  /* There is no notion of reciving OUT
+                                          * data greater then the length of
+                                          * CONFIG_USBDEV_SETUP_MAXDATASIZE
+                                          * so we are done
+                                          */
+        break;
+
+      default:
+        /* Unexpected state OR host aborted the OUT transfer before it
+         * completed, STALL the endpoint in either case
+         */
+
+        priv->ep0state = EP0STATE_STALLED;
+        break;
+    }
+}
+
+/****************************************************************************
+ * Name: stm32l4_ep0done
+ ****************************************************************************/
+
+static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, uint16_t istr)
+{
+  uint16_t epr;
+
+  /* Initialize RX and TX status.  We shouldn't have to actually look at the
+   * status because the hardware is supposed to set the both RX and TX status
+   * to NAK when an EP0 SETUP occurs (of course, this might not be a setup)
+   */
+
+  priv->rxstatus = USB_EPR_STATRX_NAK;
+  priv->txstatus = USB_EPR_STATTX_NAK;
+
+  /* Set both RX and TX status to NAK  */
+
+  stm32l4_seteprxstatus(EP0, USB_EPR_STATRX_NAK);
+  stm32l4_seteptxstatus(EP0, USB_EPR_STATTX_NAK);
+
+  /* Check the direction bit to determine if this the completion of an EP0
+   * packet sent to or received from the host PC.
+   */
+
+  if ((istr & USB_ISTR_DIR) == 0)
+    {
+      /* EP0 IN: device-to-host (DIR=0) */
+
+      usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0IN), istr);
+      stm32l4_clrepctrtx(EP0);
+      stm32l4_ep0in(priv);
+    }
+  else
+    {
+      /* EP0 OUT: host-to-device (DIR=1) */
+
+      epr = stm32l4_getreg(STM32L4_USB_EPR(EP0));
+
+      /* CTR_TX is set when an IN transaction successfully
+       * completes on an endpoint
+       */
+
+      if ((epr & USB_EPR_CTR_TX) != 0)
+        {
+          usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0INDONE), epr);
+          stm32l4_clrepctrtx(EP0);
+          stm32l4_ep0in(priv);
+        }
+
+      /* SETUP is set by the hardware when the last completed
+       * transaction was a control endpoint SETUP
+       */
+
+      else if ((epr & USB_EPR_SETUP) != 0)
+        {
+          usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPDONE), epr);
+          stm32l4_clrepctrrx(EP0);
+          stm32l4_ep0setup(priv);
+        }
+
+      /* Set by the hardware when an OUT/SETUP transaction successfully
+       * completed on this endpoint.
+       */
+
+      else if ((epr & USB_EPR_CTR_RX) != 0)
+        {
+          usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0OUTDONE), epr);
+          stm32l4_clrepctrrx(EP0);
+          stm32l4_ep0out(priv);
+        }
+
+      /* None of the above */
+
+      else
+        {
+          usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0BADCTR), epr);
+          return; /* Does this ever happen? */
+        }
+    }
+
+  /* Make sure that the EP0 packet size is still OK (superstitious?) */
+
+  stm32l4_seteprxcount(EP0, STM32L4_EP0MAXPACKET);
+
+  /* Now figure out the new RX/TX status.  Here are all possible
+   * consequences of the above EP0 operations:
+   *
+   * rxstatus txstatus ep0state  MEANING
+   * -------- -------- --------- ---------------------------------
+   * NAK      NAK      IDLE      Nothing happened
+   * NAK      VALID    IDLE      EP0 response sent from USBDEV driver
+   * NAK      VALID    WRREQUEST EP0 response sent from class driver
+   * NAK      ---      STALL     Some protocol error occurred
+   *
+   * First handle the STALL condition:
+   */
+
+  if (priv->ep0state == EP0STATE_STALLED)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0SETUPSTALLED), priv->ep0state);
+      priv->rxstatus = USB_EPR_STATRX_STALL;
+      priv->txstatus = USB_EPR_STATTX_STALL;
+    }
+
+  /* Was a transmission started?  If so, txstatus will be VALID.  The
+   * only special case to handle is when both are set to NAK.  In that
+   * case, we need to set RX status to VALID in order to accept the next
+   * SETUP request.
+   */
+
+  else if (priv->rxstatus == USB_EPR_STATRX_NAK &&
+           priv->txstatus == USB_EPR_STATTX_NAK)
+    {
+      priv->rxstatus = USB_EPR_STATRX_VALID;
+    }
+
+  /* Now set the new TX and RX status */
+
+  stm32l4_seteprxstatus(EP0, priv->rxstatus);
+  stm32l4_seteptxstatus(EP0, priv->txstatus);
+}
+
+/****************************************************************************
+ * Name: stm32l4_lptransfer
+ ****************************************************************************/
+
+static void stm32l4_lptransfer(struct stm32l4_usbdev_s *priv)
+{
+  uint8_t  epno;
+  uint16_t istr;
+
+  /* Stay in loop while LP interrupts are pending */
+
+  while (((istr = stm32l4_getreg(STM32L4_USB_ISTR)) & USB_ISTR_CTR) != 0)
+    {
+      stm32l4_putreg((uint16_t)~USB_ISTR_CTR, STM32L4_USB_ISTR);
+
+      /* Extract highest priority endpoint number */
+
+      epno = (uint8_t)(istr & USB_ISTR_EPID_MASK);
+
+      /* Handle EP0 completion events */
+
+      if (epno == 0)
+        {
+          stm32l4_ep0done(priv, istr);
+        }
+
+      /* Handle other endpoint completion events */
+
+      else
+        {
+          stm32l4_epdone(priv, epno);
+        }
+    }
+}
+
+/****************************************************************************
+ * Name: stm32l4_usbinterrupt
+ ****************************************************************************/
+
+static int stm32l4_usbinterrupt(int irq, void *context, FAR void *arg)
+{
+  /* For now there is only one USB controller, but we will always refer to
+   * it using a pointer to make any future ports to multiple USB controllers
+   * easier.
+   */
+
+  struct stm32l4_usbdev_s *priv = &g_usbdev;
+  uint16_t istr = stm32l4_getreg(STM32L4_USB_ISTR);
+
+  usbtrace(TRACE_INTENTRY(STM32L4_TRACEINTID_USBINTERRUPT), istr);
+
+  /* Handle Reset interrupts.  When this event occurs, the peripheral is left
+   * in the same conditions it is left by the system reset (but with the
+   * USB controller enabled).
+   */
+
+  if ((istr & USB_ISTR_RESET) != 0)
+    {
+      /* Reset interrupt received. Clear the RESET interrupt status. */
+
+      stm32l4_putreg(~USB_ISTR_RESET, STM32L4_USB_ISTR);
+      usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_RESET), istr);
+
+      /* Restore our power-up state and exit now because istr is no longer
+       * valid.
+       */
+
+      stm32l4_reset(priv);
+      goto out;
+    }
+
+  /* Handle Wakeup interrupts.  This interrupt is only enable while the USB is
+   * suspended.
+   */
+
+  if ((istr & USB_ISTR_WKUP & priv->imask) != 0)
+    {
+      /* Wakeup interrupt received. Clear the WKUP interrupt status.  The
+       * cause of the resume is indicated in the FNR register
+       */
+
+      stm32l4_putreg(~USB_ISTR_WKUP, STM32L4_USB_ISTR);
+      usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_WKUP),
+               stm32l4_getreg(STM32L4_USB_FNR));
+
+      /* Perform the wakeup action */
+
+      stm32l4_initresume(priv);
+      priv->rsmstate = RSMSTATE_IDLE;
+
+      /* Disable ESOF polling, disable the wakeup interrupt, and
+       * re-enable the suspend interrupt.  Clear any pending SUSP
+       * interrupts.
+       */
+
+      stm32l4_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM);
+      stm32l4_putreg(~USB_CNTR_SUSPM, STM32L4_USB_ISTR);
+    }
+
+  if ((istr & USB_ISTR_SUSP & priv->imask) != 0)
+    {
+        usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SUSP), 0);
+        stm32l4_suspend(priv);
+
+        /* Clear of the ISTR bit must be done after setting of USB_CNTR_FSUSP */
+
+        stm32l4_putreg(~USB_ISTR_SUSP, STM32L4_USB_ISTR);
+    }
+
+  if ((istr & USB_ISTR_ESOF & priv->imask) != 0)
+    {
+      stm32l4_putreg(~USB_ISTR_ESOF, STM32L4_USB_ISTR);
+
+      /* Resume handling timing is made with ESOFs */
+
+      usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_ESOF), 0);
+      stm32l4_esofpoll(priv);
+    }
+
+  if ((istr & USB_ISTR_CTR & priv->imask) != 0)
+    {
+      /* Low priority endpoint correct transfer interrupt */
+
+      usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_USBCTR), istr);
+      stm32l4_lptransfer(priv);
+    }
+
+out:
+  usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USBINTERRUPT),
+           stm32l4_getreg(STM32L4_USB_EP0R));
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32l4_setimask
+ ****************************************************************************/
+
+static void stm32l4_setimask(struct stm32l4_usbdev_s *priv,
+                             uint16_t setbits, uint16_t clrbits)
+{
+  uint16_t regval;
+
+  /* Adjust the interrupt mask bits in the shadow copy first */
+
+  priv->imask &= ~clrbits;
+  priv->imask |= setbits;
+
+  /* Then make the interrupt mask bits in the CNTR register match the shadow
+   * register (Hmmm... who is shadowing whom?)
+   */
+
+  regval  = stm32l4_getreg(STM32L4_USB_CNTR);
+  regval &= ~USB_CNTR_ALLINTS;
+  regval |= priv->imask;
+  stm32l4_putreg(regval, STM32L4_USB_CNTR);
+}
+
+/****************************************************************************
+ * Suspend/Resume Helpers
+ ****************************************************************************/
+/****************************************************************************
+ * Name: stm32l4_suspend
+ ****************************************************************************/
+
+static void stm32l4_suspend(struct stm32l4_usbdev_s *priv)
+{
+  uint16_t regval;
+
+  /* Notify the class driver of the suspend event */
+
+  if (priv->driver)
+    {
+      CLASS_SUSPEND(priv->driver, &priv->usbdev);
+    }
+
+  /* Disable ESOF polling, disable the SUSP interrupt, and enable the WKUP
+   * interrupt.  Clear any pending WKUP interrupt.
+   */
+
+  stm32l4_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM);
+  stm32l4_putreg(~USB_ISTR_WKUP, STM32L4_USB_ISTR);
+
+  /* Set the FSUSP bit in the CNTR register.  This activates suspend mode
+   * within the USB peripheral and disables further SUSP interrupts.
+   */
+
+  regval  = stm32l4_getreg(STM32L4_USB_CNTR);
+  regval |= USB_CNTR_FSUSP;
+  stm32l4_putreg(regval, STM32L4_USB_CNTR);
+
+  /* If we are not a self-powered device, the got to low-power mode */
+
+  if (!priv->selfpowered)
+    {
+      /* Setting LPMODE in the CNTR register removes static power
+       * consumption in the USB analog transceivers but keeps them
+       * able to detect resume activity
+       */
+
+      regval = stm32l4_getreg(STM32L4_USB_CNTR);
+      regval |= USB_CNTR_LPMODE;
+      stm32l4_putreg(regval, STM32L4_USB_CNTR);
+    }
+
+  /* Let the board-specific logic know that we have entered the suspend
+   * state
+   */
+
+  stm32l4_usbsuspend((struct usbdev_s *)priv, false);
+}
+
+/****************************************************************************
+ * Name: stm32l4_initresume
+ ****************************************************************************/
+
+static void stm32l4_initresume(struct stm32l4_usbdev_s *priv)
+{
+  uint16_t regval;
+
+  /* This function is called when either (1) a WKUP interrupt is received from
+   * the host PC, or (2) the class device implementation calls the wakeup()
+   * method.
+   */
+
+  /* Clear the USB low power mode (lower power mode was not set if this is
+   * a self-powered device.  Also, low power mode is automatically cleared by
+   * hardware when a WKUP interrupt event occurs).
+   */
+
+  regval = stm32l4_getreg(STM32L4_USB_CNTR);
+  regval &= (~USB_CNTR_LPMODE);
+  stm32l4_putreg(regval, STM32L4_USB_CNTR);
+
+  /* Restore full power -- whatever that means for this particular board */
+
+  stm32l4_usbsuspend((struct usbdev_s *)priv, true);
+
+  /* Reset FSUSP bit and enable normal interrupt handling */
+
+  stm32l4_putreg(STM32L4_CNTR_SETUP, STM32L4_USB_CNTR);
+
+  /* Notify the class driver of the resume event */
+
+  if (priv->driver)
+    {
+      CLASS_RESUME(priv->driver, &priv->usbdev);
+    }
+}
+
+/****************************************************************************
+ * Name: stm32l4_esofpoll
+ ****************************************************************************/
+
+static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv)
+{
+  uint16_t regval;
+
+    /* Called periodically from ESOF interrupt after RSMSTATE_STARTED */
+
+  switch (priv->rsmstate)
+    {
+    /* One ESOF after internal resume requested */
+
+    case RSMSTATE_STARTED:
+      regval         = stm32l4_getreg(STM32L4_USB_CNTR);
+      regval        |= USB_CNTR_RESUME;
+      stm32l4_putreg(regval, STM32L4_USB_CNTR);
+      priv->rsmstate = RSMSTATE_WAITING;
+      priv->nesofs   = 10;
+      break;
+
+    /* Countdown before completing the operation */
+
+    case RSMSTATE_WAITING:
+      priv->nesofs--;
+      if (priv->nesofs == 0)
+        {
+          /* Okay.. we are ready to resume normal operation */
+
+          regval         = stm32l4_getreg(STM32L4_USB_CNTR);
+          regval        &= (~USB_CNTR_RESUME);
+          stm32l4_putreg(regval, STM32L4_USB_CNTR);
+          priv->rsmstate = RSMSTATE_IDLE;
+
+          /* Disable ESOF polling, disable the SUSP interrupt, and enable
+           * the WKUP interrupt.  Clear any pending WKUP interrupt.
+           */
+
+          stm32l4_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM);
+          stm32l4_putreg(~USB_ISTR_WKUP, STM32L4_USB_ISTR);
+        }
+      break;
+
+    case RSMSTATE_IDLE:
+    default:
+      priv->rsmstate = RSMSTATE_IDLE;
+      break;
+    }
+}
+
+/****************************************************************************
+ * Endpoint Helpers
+ ****************************************************************************/
+/****************************************************************************
+ * Name: stm32l4_epreserve
+ ****************************************************************************/
+
+static inline struct stm32l4_ep_s *
+stm32l4_epreserve(struct stm32l4_usbdev_s *priv, uint8_t epset)
+{
+  struct stm32l4_ep_s *privep = NULL;
+  irqstate_t flags;
+  int epndx = 0;
+
+  flags = enter_critical_section();
+  epset &= priv->epavail;
+  if (epset)
+    {
+      /* Select the lowest bit in the set of matching, available endpoints
+       * (skipping EP0)
+       */
+
+      for (epndx = 1; epndx < STM32L4_NENDPOINTS; epndx++)
+        {
+          uint8_t bit = STM32L4_ENDP_BIT(epndx);
+          if ((epset & bit) != 0)
+            {
+              /* Mark the endpoint no longer available */
+
+              priv->epavail &= ~bit;
+
+              /* And return the pointer to the standard endpoint structure */
+
+              privep = &priv->eplist[epndx];
+              break;
+            }
+        }
+    }
+
+  leave_critical_section(flags);
+  return privep;
+}
+
+/****************************************************************************
+ * Name: stm32l4_epunreserve
+ ****************************************************************************/
+
+static inline void
+stm32l4_epunreserve(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep)
+{
+  irqstate_t flags = enter_critical_section();
+  priv->epavail   |= STM32L4_ENDP_BIT(USB_EPNO(privep->ep.eplog));
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: stm32l4_epreserved
+ ****************************************************************************/
+
+static inline bool
+stm32l4_epreserved(struct stm32l4_usbdev_s *priv, int epno)
+{
+  return ((priv->epavail & STM32L4_ENDP_BIT(epno)) == 0);
+}
+
+/****************************************************************************
+ * Name: stm32l4_epallocpma
+ ****************************************************************************/
+
+static int stm32l4_epallocpma(struct stm32l4_usbdev_s *priv)
+{
+  irqstate_t flags;
+  int bufno = ERROR;
+  int bufndx;
+
+  flags = enter_critical_section();
+  for (bufndx = 2; bufndx < STM32L4_NBUFFERS; bufndx++)
+    {
+      /* Check if this buffer is available */
+
+      uint8_t bit = STM32L4_BUFFER_BIT(bufndx);
+      if ((priv->bufavail & bit) != 0)
+        {
+          /* Yes.. Mark the endpoint no longer available */
+
+          priv->bufavail &= ~bit;
+
+          /* And return the index of the allocated buffer */
+
+          bufno = bufndx;
+          break;
+        }
+    }
+
+  leave_critical_section(flags);
+  return bufno;
+}
+
+/****************************************************************************
+ * Name: stm32l4_epfreepma
+ ****************************************************************************/
+
+static inline void
+stm32l4_epfreepma(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep)
+{
+  irqstate_t flags = enter_critical_section();
+  priv->epavail   |= STM32L4_ENDP_BIT(privep->bufno);
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Endpoint operations
+ ****************************************************************************/
+/****************************************************************************
+ * Name: stm32l4_epconfigure
+ ****************************************************************************/
+
+static int stm32l4_epconfigure(struct usbdev_ep_s *ep,
+                             const struct usb_epdesc_s *desc,
+                             bool last)
+{
+  struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep;
+  uint16_t pma;
+  uint16_t setting;
+  uint16_t maxpacket;
+  uint8_t  epno;
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!ep || !desc)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0);
+      uerr("ERROR: ep=%p desc=%p\n");
+      return -EINVAL;
+    }
+#endif
+
+  /* Get the unadorned endpoint address */
+
+  epno = USB_EPNO(desc->addr);
+  usbtrace(TRACE_EPCONFIGURE, (uint16_t)epno);
+  DEBUGASSERT(epno == USB_EPNO(ep->eplog));
+
+  /* Set the requested type */
+
+  switch (desc->attr & USB_EP_ATTR_XFERTYPE_MASK)
+   {
+    case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */
+      setting = USB_EPR_EPTYPE_INTERRUPT;
+      break;
+
+    case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */
+      setting = USB_EPR_EPTYPE_BULK;
+      break;
+
+    case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */
+#warning "REVISIT: Need to review isochronous EP setup"
+      setting = USB_EPR_EPTYPE_ISOC;
+      break;
+
+    case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint */
+      setting = USB_EPR_EPTYPE_CONTROL;
+      break;
+
+    default:
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPTYPE), (uint16_t)desc->type);
+      return -EINVAL;
+    }
+
+  stm32l4_seteptype(epno, setting);
+
+  /* Get the address of the PMA buffer allocated for this endpoint */
+
+#warning "REVISIT: Should configure BULK EPs using double buffer feature"
+  pma = STM32L4_BUFNO2BUF(privep->bufno);
+
+  /* Get the maxpacket size of the endpoint. */
+
+  maxpacket = GETUINT16(desc->mxpacketsize);
+  DEBUGASSERT(maxpacket <= STM32L4_MAXPACKET_SIZE);
+  ep->maxpacket = maxpacket;
+
+  /* Get the subset matching the requested direction */
+
+  if (USB_ISEPIN(desc->addr))
+    {
+      /* The full, logical EP number includes direction */
+
+      ep->eplog = USB_EPIN(epno);
+
+      /* Set up TX; disable RX */
+
+      stm32l4_seteptxaddr(epno, pma);
+      stm32l4_seteptxstatus(epno, USB_EPR_STATTX_NAK);
+      stm32l4_seteprxstatus(epno, USB_EPR_STATRX_DIS);
+    }
+  else
+    {
+      /* The full, logical EP number includes direction */
+
+      ep->eplog = USB_EPOUT(epno);
+
+      /* Set up RX; disable TX */
+
+      stm32l4_seteprxaddr(epno, pma);
+      stm32l4_seteprxcount(epno, maxpacket);
+      stm32l4_seteprxstatus(epno, USB_EPR_STATRX_VALID);
+      stm32l4_seteptxstatus(epno, USB_EPR_STATTX_DIS);
+    }
+
+   stm32l4_dumpep(epno);
+   return OK;
+}
+
+/****************************************************************************
+ * Name: stm32l4_epdisable
+ ****************************************************************************/
+
+static int stm32l4_epdisable(struct usbdev_ep_s *ep)
+{
+  struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep;
+  irqstate_t flags;
+  uint8_t epno;
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!ep)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0);
+      uerr("ERROR: ep=%p\n", ep);
+      return -EINVAL;
+    }
+#endif
+
+  epno = USB_EPNO(ep->eplog);
+  usbtrace(TRACE_EPDISABLE, epno);
+
+  /* Cancel any ongoing activity */
+
+  flags = enter_critical_section();
+  stm32l4_cancelrequests(privep);
+
+  /* Disable TX; disable RX */
+
+  stm32l4_seteprxcount(epno, 0);
+  stm32l4_seteprxstatus(epno, USB_EPR_STATRX_DIS);
+  stm32l4_seteptxstatus(epno, USB_EPR_STATTX_DIS);
+
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32l4_epallocreq
+ ****************************************************************************/
+
+static struct usbdev_req_s *stm32l4_epallocreq(struct usbdev_ep_s *ep)
+{
+  struct stm32l4_req_s *privreq;
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!ep)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0);
+      return NULL;
+    }
+#endif
+  usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog));
+
+  privreq = (struct stm32l4_req_s *)kmm_malloc(sizeof(struct stm32l4_req_s));
+  if (!privreq)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_ALLOCFAIL), 0);
+      return NULL;
+    }
+
+  memset(privreq, 0, sizeof(struct stm32l4_req_s));
+  return &privreq->req;
+}
+
+/****************************************************************************
+ * Name: stm32l4_epfreereq
+ ****************************************************************************/
+
+static void stm32l4_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
+{
+  struct stm32l4_req_s *privreq = (struct stm32l4_req_s *)req;
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!ep || !req)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0);
+      return;
+    }
+#endif
+  usbtrace(TRACE_EPFREEREQ, USB_EPNO(ep->eplog));
+
+  kmm_free(privreq);
+}
+
+/****************************************************************************
+ * Name: stm32l4_epsubmit
+ ****************************************************************************/
+
+static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
+{
+  struct stm32l4_req_s *privreq = (struct stm32l4_req_s *)req;
+  struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep;
+  struct stm32l4_usbdev_s *priv;
+  irqstate_t flags;
+  uint8_t epno;
+  int ret = OK;
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!req || !req->callback || !req->buf || !ep)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0);
+      uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n",
+           req, req->callback, req->buf, ep);
+      return -EINVAL;
+    }
+#endif
+
+  usbtrace(TRACE_EPSUBMIT, USB_EPNO(ep->eplog));
+  priv = privep->dev;
+
+#ifdef CONFIG_DEBUG_FEATURES
+  if (!priv->driver)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOTCONFIGURED),
+               priv->usbdev.speed);
+      uerr("ERROR: driver=%p\n", priv->driver);
+      return -ESHUTDOWN;
+    }
+#endif
+
+  /* Handle the request from the class driver */
+
+  epno        = USB_EPNO(ep->eplog);
+  req->result = -EINPROGRESS;
+  req->xfrd   = 0;
+  flags       = enter_critical_section();
+
+  /* If we are stalled, then drop all requests on the floor */
+
+  if (privep->stalled)
+    {
+      stm32l4_abortrequest(privep, privreq, -EBUSY);
+      uerr("ERROR: stalled\n");
+      ret = -EBUSY;
+    }
+
+  /* Handle IN (device-to-host) requests.  NOTE:  If the class device is
+   * using the bi-directional EP0, then we assume that they intend the EP0
+   * IN functionality.
+   */
+
+  else if (USB_ISEPIN(ep->eplog) || epno == EP0)
+    {
+      /* Add the new request to the request queue for the IN endpoint */
+
+      stm32l4_rqenqueue(privep, privreq);
+      usbtrace(TRACE_INREQQUEUED(epno), req->len);
+
+      /* If the IN endpoint FIFO is available, then transfer the data now */
+
+      if (!privep->txbusy)
+        {
+          priv->txstatus = USB_EPR_STATTX_NAK;
+          if (epno == EP0)
+            {
+              ret = stm32l4_wrrequest_ep0(priv, privep);
+            }
+          else
+            {
+              ret = stm32l4_wrrequest(priv, privep);
+            }
+
+          /* Set the new TX status */
+
+          stm32l4_seteptxstatus(epno, priv->txstatus);
+        }
+    }
+
+  /* Handle OUT (host-to-device) requests */
+
+  else
+    {
+      /* Add the new request to the request queue for the OUT endpoint */
+
+      privep->txnullpkt = 0;
+      stm32l4_rqenqueue(privep, privreq);
+      usbtrace(TRACE_OUTREQQUEUED(epno), req->len);
+
+      /* This there a incoming data pending the availability of a request? */
+
+      if (priv->rxpending)
+        {
+          /* Set STAT_RX bits to '11' in the USB_EPnR, enabling further
+           * transactions. "While the STAT_RX bits are equal to '10'
+           * (NAK), any OUT request addressed to that endpoint is NAKed,
+           * indicating a flow control condition: the USB host will retry
+           * the transaction until it succeeds."
+           */
+
+          priv->rxstatus  = USB_EPR_STATRX_VALID;
+          stm32l4_seteprxstatus(epno, priv->rxstatus);
+
+          /* Data is no longer pending */
+
+          priv->rxpending = false;
+        }
+    }
+
+  leave_critical_section(flags);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: stm32l4_epcancel
+ ****************************************************************************/
+
+static int stm32l4_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
+{
+  struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep;
+  irqstate_t flags;
+
+#ifdef CONFIG_DEBUG_USB
+  if (!ep || !req)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0);
+      return -EINVAL;
+    }
+#endif
+  usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog));
+
+  flags = enter_critical_section();
+  stm32l4_cancelrequests(privep);
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32l4_epstall
+ ****************************************************************************/
+
+static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume)
+{
+  struct stm32l4_ep_s *privep;
+  struct stm32l4_usbdev_s *priv;
+  uint8_t epno;
+  uint16_t status;
+  irqstate_t flags;
+
+#ifdef CONFIG_DEBUG_USB
+  if (!ep)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0);
+      return -EINVAL;
+    }
+#endif
+
+  privep = (struct stm32l4_ep_s *)ep;
+  priv   = (struct stm32l4_usbdev_s *)privep->dev;
+  epno   = USB_EPNO(ep->eplog);
+
+  /* STALL or RESUME the endpoint */
+
+  flags = enter_critical_section();
+  usbtrace(resume ? TRACE_EPRESUME : TRACE_EPSTALL, USB_EPNO(ep->eplog));
+
+  /* Get status of the endpoint; stall the request if the endpoint is
+   * disabled
+   */
+
+  if (USB_ISEPIN(ep->eplog))
+    {
+      status = stm32l4_geteptxstatus(epno);
+    }
+  else
+    {
+      status = stm32l4_geteprxstatus(epno);
+    }
+
+  if (status == 0)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPDISABLED), 0);
+
+      if (epno == 0)
+        {
+          priv->ep0state = EP0STATE_STALLED;
+        }
+
+      return -ENODEV;
+    }
+
+  /* Handle the resume condition */
+
+  if (resume)
+    {
+      /* Resuming a stalled endpoint */
+
+      usbtrace(TRACE_EPRESUME, epno);
+      privep->stalled = false;
+
+      if (USB_ISEPIN(ep->eplog))
+        {
+          /* IN endpoint */
+
+          if (stm32l4_eptxstalled(epno))
+            {
+              stm32l4_clrtxdtog(epno);
+
+              /* Restart any queued write requests */
+
+              priv->txstatus = USB_EPR_STATTX_NAK;
+              if (epno == EP0)
+                {
+                  (void)stm32l4_wrrequest_ep0(priv, privep);
+                }
+              else
+                {
+                  (void)stm32l4_wrrequest(priv, privep);
+                }
+
+              /* Set the new TX status */
+
+              stm32l4_seteptxstatus(epno, priv->txstatus);
+            }
+        }
+      else
+        {
+          /* OUT endpoint */
+
+          if (stm32l4_eprxstalled(epno))
+            {
+              if (epno == EP0)
+                {
+                  /* After clear the STALL, enable the default endpoint receiver */
+
+                  stm32l4_seteprxcount(epno, ep->maxpacket);
+                }
+              else
+                {
+                  stm32l4_clrrxdtog(epno);
+                }
+
+              priv->rxstatus = USB_EPR_STATRX_VALID;
+              stm32l4_seteprxstatus(epno, USB_EPR_STATRX_VALID);
+            }
+        }
+    }
+
+  /* Handle the stall condition */
+
+  else
+    {
+      usbtrace(TRACE_EPSTALL, epno);
+      privep->stalled = true;
+
+      if (USB_ISEPIN(ep->eplog))
+        {
+          /* IN endpoint */
+
+          priv->txstatus = USB_EPR_STATTX_STALL;
+          stm32l4_seteptxstatus(epno, USB_EPR_STATTX_STALL);
+        }
+      else
+        {
+          /* OUT endpoint */
+
+          priv->rxstatus = USB_EPR_STATRX_STALL;
+          stm32l4_seteprxstatus(epno, USB_EPR_STATRX_STALL);
+        }
+    }
+
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Device Controller Operations
+ ****************************************************************************/
+/****************************************************************************
+ * Name: stm32l4_allocep
+ ****************************************************************************/
+
+static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, uint8_t epno,
+                                         bool in, uint8_t eptype)
+{
+  struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev;
+  struct stm32l4_ep_s *privep = NULL;
+  uint8_t epset = STM32L4_ENDP_ALLSET;
+  int bufno;
+
+  usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno);
+#ifdef CONFIG_DEBUG_USB
+  if (!dev)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0);
+      return NULL;
+    }
+#endif
+
+  /* Ignore any direction bits in the logical address */
+
+  epno = USB_EPNO(epno);
+
+  /* A logical address of 0 means that any endpoint will do */
+
+  if (epno > 0)
+    {
+      /* Otherwise, we will return the endpoint structure only for the requested
+       * 'logical' endpoint.  All of the other checks will still be performed.
+       *
+       * First, verify that the logical endpoint is in the range supported by
+       * by the hardware.
+       */
+
+      if (epno >= STM32L4_NENDPOINTS)
+        {
+          usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPNO), (uint16_t)epno);
+          return NULL;
+        }
+
+      /* Convert the logical address to a physical OUT endpoint address and
+       * remove all of the candidate endpoints from the bitset except for the
+       * the IN/OUT pair for this logical address.
+       */
+
+      epset = STM32L4_ENDP_BIT(epno);
+    }
+
+  /* Check if the selected endpoint number is available */
+
+  privep = stm32l4_epreserve(priv, epset);
+  if (!privep)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPRESERVE), (uint16_t)epset);
+      goto errout;
+    }
+
+  /* Allocate a PMA buffer for this endpoint */
+
+#warning "REVISIT: Should configure BULK EPs using double buffer feature"
+  bufno = stm32l4_epallocpma(priv);
+  if (bufno < 0)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPBUFFER), 0);
+      goto errout_with_ep;
+    }
+
+  privep->bufno = (uint8_t)bufno;
+  return &privep->ep;
+
+errout_with_ep:
+  stm32l4_epunreserve(priv, privep);
+errout:
+  return NULL;
+}
+
+/****************************************************************************
+ * Name: stm32l4_freeep
+ ****************************************************************************/
+
+static void stm32l4_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep)
+{
+  struct stm32l4_usbdev_s *priv;
+  struct stm32l4_ep_s *privep;
+
+#ifdef CONFIG_DEBUG_USB
+  if (!dev || !ep)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0);
+      return;
+    }
+#endif
+  priv   = (struct stm32l4_usbdev_s *)dev;
+  privep = (struct stm32l4_ep_s *)ep;
+  usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog));
+
+  if (priv && privep)
+    {
+      /* Free the PMA buffer assigned to this endpoint */
+
+      stm32l4_epfreepma(priv, privep);
+
+      /* Mark the endpoint as available */
+
+      stm32l4_epunreserve(priv, privep);
+    }
+}
+
+/****************************************************************************
+ * Name: stm32l4_getframe
+ ****************************************************************************/
+
+static int stm32l4_getframe(struct usbdev_s *dev)
+{
+  uint16_t fnr;
+
+#ifdef CONFIG_DEBUG_USB
+  if (!dev)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0);
+      return -EINVAL;
+    }
+#endif
+
+  /* Return the last frame number detected by the hardware */
+
+  fnr = stm32l4_getreg(STM32L4_USB_FNR);
+  usbtrace(TRACE_DEVGETFRAME, fnr);
+  return (fnr & USB_FNR_FN_MASK);
+}
+
+/****************************************************************************
+ * Name: stm32l4_wakeup
+ ****************************************************************************/
+
+static int stm32l4_wakeup(struct usbdev_s *dev)
+{
+  struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev;
+  irqstate_t flags;
+
+  usbtrace(TRACE_DEVWAKEUP, 0);
+#ifdef CONFIG_DEBUG_USB
+  if (!dev)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0);
+      return -EINVAL;
+    }
+#endif
+
+  /* Start the resume sequence.  The actual resume steps will be driven
+   * by the ESOF interrupt.
+   */
+
+  flags = enter_critical_section();
+  stm32l4_initresume(priv);
+  priv->rsmstate = RSMSTATE_STARTED;
+
+  /* Disable the SUSP interrupt (until we are fully resumed), disable
+   * the WKUP interrupt (we are already waking up), and enable the
+   * ESOF interrupt that will drive the resume operations.  Clear any
+   * pending ESOF interrupt.
+   */
+
+  stm32l4_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM);
+  stm32l4_putreg(~USB_ISTR_ESOF, STM32L4_USB_ISTR);
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32l4_selfpowered
+ ****************************************************************************/
+
+static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered)
+{
+  struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev;
+
+  usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered);
+
+#ifdef CONFIG_DEBUG_USB
+  if (!dev)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0);
+      return -ENODEV;
+    }
+#endif
+
+  priv->selfpowered = selfpowered;
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32l4_pullup
+ ****************************************************************************/
+
+static int stm32l4_pullup(struct usbdev_s *dev, bool enable)
+{
+  uint32_t regval;
+  irqstate_t flags;
+
+  usbtrace(TRACE_DEVPULLUP, (uint16_t)enable);
+
+  flags = enter_critical_section();
+  regval = stm32l4_getreg(STM32L4_USB_BCDR);
+  if (enable)
+    {
+      /* Connect the device by setting the DP pull-up bit in the BCDR
+       * register.
+       */
+
+      regval |= USB_BCDR_DPPU;
+    }
+  else
+    {
+      /* Disconnect the device by clearing the DP pull-up bit in the BCDR
+       * register.
+       */
+
+      regval &= ~USB_BCDR_DPPU;
+    }
+
+  stm32l4_putreg(regval, STM32L4_USB_BCDR);
+  leave_critical_section(flags);
+  return OK;
+}
+
+/****************************************************************************
+ * Initialization/Reset
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32l4_reset
+ ****************************************************************************/
+
+static void stm32l4_reset(struct stm32l4_usbdev_s *priv)
+{
+  int epno;
+
+  /* Put the USB controller in reset, disable all interrupts */
+
+  stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR);
+
+  /* Tell the class driver that we are disconnected.  The class driver
+   * should then accept any new configurations.
+   */
+
+  CLASS_DISCONNECT(priv->driver, &priv->usbdev);
+
+  /* Reset the device state structure */
+
+  priv->ep0state  = EP0STATE_IDLE;
+  priv->rsmstate  = RSMSTATE_IDLE;
+  priv->rxpending = false;
+
+  /* Reset endpoints */
+
+  for (epno = 0; epno < STM32L4_NENDPOINTS; epno++)
+    {
+      struct stm32l4_ep_s *privep = &priv->eplist[epno];
+
+      /* Cancel any queued requests.  Since they are canceled
+       * with status -ESHUTDOWN, then will not be requeued
+       * until the configuration is reset.  NOTE:  This should
+       * not be necessary... the CLASS_DISCONNECT above should
+       * result in the class implementation calling stm32l4_epdisable
+       * for each of its configured endpoints.
+       */
+
+      stm32l4_cancelrequests(privep);
+
+      /* Reset endpoint status */
+
+      privep->stalled   = false;
+      privep->halted    = false;
+      privep->txbusy    = false;
+      privep->txnullpkt = false;
+    }
+
+  /* Re-configure the USB controller in its initial, unconnected state */
+
+  stm32l4_hwreset(priv);
+  priv->usbdev.speed = USB_SPEED_FULL;
+}
+
+/****************************************************************************
+ * Name: stm32l4_hwreset
+ ****************************************************************************/
+
+static void stm32l4_hwreset(struct stm32l4_usbdev_s *priv)
+{
+  /* Put the USB controller into reset, clear all interrupt enables */
+
+  stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR);
+
+  /* Disable interrupts (and perhaps take the USB controller out of reset) */
+
+  priv->imask = 0;
+  stm32l4_putreg(priv->imask, STM32L4_USB_CNTR);
+
+  /* Set the STM32 BTABLE address */
+
+  stm32l4_putreg(STM32L4_BTABLE_ADDRESS & 0xfff8, STM32L4_USB_BTABLE);
+
+  /* Initialize EP0 */
+
+  stm32l4_seteptype(EP0, USB_EPR_EPTYPE_CONTROL);
+  stm32l4_seteptxstatus(EP0, USB_EPR_STATTX_NAK);
+  stm32l4_seteprxaddr(EP0, STM32L4_EP0_RXADDR);
+  stm32l4_seteprxcount(EP0, STM32L4_EP0MAXPACKET);
+  stm32l4_seteptxaddr(EP0, STM32L4_EP0_TXADDR);
+  stm32l4_clrstatusout(EP0);
+  stm32l4_seteprxstatus(EP0, USB_EPR_STATRX_VALID);
+
+  /* Set the device to respond on default address */
+
+  stm32l4_setdevaddr(priv, 0);
+
+  /* Clear any pending interrupts */
+
+  stm32l4_putreg(0, STM32L4_USB_ISTR);
+
+  /* Enable interrupts at the USB controller */
+
+  stm32l4_setimask(priv, STM32L4_CNTR_SETUP,
+                   (USB_CNTR_ALLINTS & ~STM32L4_CNTR_SETUP));
+  stm32l4_dumpep(EP0);
+}
+
+/****************************************************************************
+ * Name: stm32l4_hwsetup
+ ****************************************************************************/
+
+static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv)
+{
+  int epno;
+
+  /* Power the USB controller, put the USB controller into reset, disable
+   * all USB interrupts
+   */
+
+  stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32L4_USB_CNTR);
+
+  /* Disconnect the device / disable the pull-up.  We don't want the
+   * host to enumerate us until the class driver is registered.
+   */
+
+  stm32l4_pullup(&priv->usbdev, false);
+
+  /* Initialize the device state structure.  NOTE: many fields
+   * have the initial value of zero and, hence, are not explicitly
+   * initialized here.
+   */
+
+  memset(priv, 0, sizeof(struct stm32l4_usbdev_s));
+  priv->usbdev.ops   = &g_devops;
+  priv->usbdev.ep0   = &priv->eplist[EP0].ep;
+  priv->epavail      = STM32L4_ENDP_ALLSET & ~STM32L4_ENDP_BIT(EP0);
+  priv->bufavail     = STM32L4_BUFFER_ALLSET & ~STM32L4_BUFFER_EP0;
+
+  /* Initialize the endpoint list */
+
+  for (epno = 0; epno < STM32L4_NENDPOINTS; epno++)
+    {
+      /* Set endpoint operations, reference to driver structure (not
+       * really necessary because there is only one controller), and
+       * the (physical) endpoint number which is just the index to the
+       * endpoint.
+       */
+
+      priv->eplist[epno].ep.ops    = &g_epops;
+      priv->eplist[epno].dev       = priv;
+      priv->eplist[epno].ep.eplog  = epno;
+
+      /* We will use a fixed maxpacket size for all endpoints (perhaps
+       * ISOC endpoints could have larger maxpacket???).  A smaller
+       * packet size can be selected when the endpoint is configured.
+       */
+
+      priv->eplist[epno].ep.maxpacket = STM32L4_MAXPACKET_SIZE;
+    }
+
+  /* Select a smaller endpoint size for EP0 */
+
+#if STM32L4_EP0MAXPACKET < STM32L4_MAXPACKET_SIZE
+  priv->eplist[EP0].ep.maxpacket = STM32L4_EP0MAXPACKET;
+#endif
+
+  /* Configure the USB controller.  USB uses the following GPIO pins:
+   *
+   *   PA9  - VBUS
+   *   PA10 - ID
+   *   PA11 - DM
+   *   PA12 - DP
+   *
+   * "As soon as the USB is enabled, these pins [DM and DP] are connected to
+   * the USB internal transceiver automatically."
+   */
+
+  /* Power up the USB controller, holding it in reset.  There is a delay of
+   * about 1uS after applying power before the USB will behave predictably.
+   * A 5MS delay is more than enough.  NOTE that we leave the USB controller
+   * in the reset state; the hardware will not be initialized until the
+   * class driver has been bound.
+   */
+
+  stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR);
+  up_mdelay(5);
+}
+
+/****************************************************************************
+ * Name: stm32l4_hwshutdown
+ ****************************************************************************/
+
+static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv)
+{
+  priv->usbdev.speed = USB_SPEED_UNKNOWN;
+
+  /* Disable all interrupts and force the USB controller into reset */
+
+  stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR);
+
+  /* Clear any pending interrupts */
+
+  stm32l4_putreg(0, STM32L4_USB_ISTR);
+
+  /* Disconnect the device / disable the pull-up */
+
+  stm32l4_pullup(&priv->usbdev, false);
+
+  /* Power down the USB controller */
+
+  stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32L4_USB_CNTR);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+/****************************************************************************
+ * Name: up_usbinitialize
+ *
+ * Description:
+ *   Initialize the USB driver
+ *
+ ****************************************************************************/
+
+void up_usbinitialize(void)
+{
+  /* For now there is only one USB controller, but we will always refer to
+   * it using a pointer to make any future ports to multiple USB controllers
+   * easier.
+   */
+
+  struct stm32l4_usbdev_s *priv = &g_usbdev;
+
+  usbtrace(TRACE_DEVINIT, 0);
+  stm32l4_checksetup();
+
+  /* Enable Vbus monitoring in the Power control */
+
+  stm32l4_pwr_enableusv(true);
+
+  /* Power up the USB controller, but leave it in the reset state */
+
+  stm32l4_hwsetup(priv);
+
+  /* Attach USB controller interrupt handler.  The hardware will not be
+   * initialized and interrupts will not be enabled until the class device
+   * driver is bound.
+   */
+
+  if (irq_attach(STM32L4_IRQ_USB_FS, stm32l4_usbinterrupt, NULL) != 0)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_IRQREGISTRATION),
+               (uint16_t)STM32L4_IRQ_USB_FS);
+      up_usbuninitialize();
+    }
+}
+
+/****************************************************************************
+ * Name: up_usbuninitialize
+ *
+ * Description:
+ *   Initialize the USB driver
+ *
+ ****************************************************************************/
+
+void up_usbuninitialize(void)
+{
+  /* For now there is only one USB controller, but we will always refer to
+   * it using a pointer to make any future ports to multiple USB controllers
+   * easier.
+   */
+
+  struct stm32l4_usbdev_s *priv = &g_usbdev;
+  irqstate_t flags;
+
+  flags = enter_critical_section();
+  usbtrace(TRACE_DEVUNINIT, 0);
+
+  /* Disable and detach the USB IRQ */
+
+  up_disable_irq(STM32L4_IRQ_USB_FS);
+  irq_detach(STM32L4_IRQ_USB_FS);
+
+  if (priv->driver)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVERREGISTERED), 0);
+      usbdev_unregister(priv->driver);
+    }
+
+  /* Put the hardware in an inactive state */
+
+  stm32l4_hwshutdown(priv);
+
+  /* Disable Vbus monitoring in the Power control */
+
+  stm32l4_pwr_enableusv(false);
+
+  leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: usbdev_register
+ *
+ * Description:
+ *   Register a USB device class driver. The class driver's bind() method will be
+ *   called to bind it to a USB device driver.
+ *
+ ****************************************************************************/
+
+int usbdev_register(struct usbdevclass_driver_s *driver)
+{
+  /* For now there is only one USB controller, but we will always refer to
+   * it using a pointer to make any future ports to multiple USB controllers
+   * easier.
+   */
+
+  struct stm32l4_usbdev_s *priv = &g_usbdev;
+  int ret;
+
+  usbtrace(TRACE_DEVREGISTER, 0);
+
+#ifdef CONFIG_DEBUG_USB
+  if (!driver || !driver->ops->bind || !driver->ops->unbind ||
+      !driver->ops->disconnect || !driver->ops->setup)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0);
+      return -EINVAL;
+    }
+
+  if (priv->driver)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVER), 0);
+      return -EBUSY;
+    }
+#endif
+
+  /* First hook up the driver */
+
+  priv->driver = driver;
+
+  /* Then bind the class driver */
+
+  ret = CLASS_BIND(driver, &priv->usbdev);
+  if (ret)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BINDFAILED), (uint16_t)-ret);
+    }
+  else
+    {
+      /* Setup the USB controller -- enabling interrupts at the USB controller */
+
+      stm32l4_hwreset(priv);
+
+      /* Enable USB controller interrupt at the NVIC */
+
+      up_enable_irq(STM32L4_IRQ_USB_FS);
+
+      /* Enable pull-up to connect the device.  The host should enumerate us
+       * some time after this
+       */
+
+      stm32l4_pullup(&priv->usbdev, true);
+      priv->usbdev.speed = USB_SPEED_FULL;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: usbdev_unregister
+ *
+ * Description:
+ *   Un-register usbdev class driver. If the USB device is connected to a
+ *   USB host, it will first disconnect().  The driver is also requested to
+ *   unbind() and clean up any device state, before this procedure finally
+ *   returns.
+ *
+ ****************************************************************************/
+
+int usbdev_unregister(struct usbdevclass_driver_s *driver)
+{
+  /* For now there is only one USB controller, but we will always refer to
+   * it using a pointer to make any future ports to multiple USB controllers
+   * easier.
+   */
+
+  struct stm32l4_usbdev_s *priv = &g_usbdev;
+  irqstate_t flags;
+
+  usbtrace(TRACE_DEVUNREGISTER, 0);
+
+#ifdef CONFIG_DEBUG_USB
+  if (driver != priv->driver)
+    {
+      usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0);
+      return -EINVAL;
+    }
+#endif
+
+  /* Reset the hardware and cancel all requests.  All requests must be
+   * canceled while the class driver is still bound.
+   */
+
+  flags = enter_critical_section();
+  stm32l4_reset(priv);
+
+  /* Unbind the class driver */
+
+  CLASS_UNBIND(driver, &priv->usbdev);
+
+  /* Disable USB controller interrupt (but keep attached) */
+
+  up_disable_irq(STM32L4_IRQ_USB_FS);
+
+  /* Put the hardware in an inactive state.  Then bring the hardware back up
+   * in the reset state (this is probably not necessary, the stm32l4_reset()
+   * call above was probably sufficient).
+   */
+
+  stm32l4_hwshutdown(priv);
+  stm32l4_hwsetup(priv);
+
+  /* Unhook the driver */
+
+  priv->driver = NULL;
+  leave_critical_section(flags);
+  return OK;
+}
+
+#endif /* CONFIG_USBDEV && CONFIG_STM32L4_USB */
diff --git a/arch/arm/src/stm32l4/stm32l4_usbdev.h b/arch/arm/src/stm32l4/stm32l4_usbdev.h
index e69de29bb2d..08b92200418 100644
--- a/arch/arm/src/stm32l4/stm32l4_usbdev.h
+++ b/arch/arm/src/stm32l4/stm32l4_usbdev.h
@@ -0,0 +1,85 @@
+/************************************************************************************
+ * arch/arm/src/stm32l4/stm32l4_usbdev.h
+ *
+ *   Copyright (C) 2009, 2011, 2015, 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_USBDEV_H
+#define __ARCH_ARM_SRC_STM32L4_STM32L4_USBDEV_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+#include 
+#include 
+
+#include "chip.h"
+#include "hardware/stm32l4_usbdev.h"
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Name:  stm32l4_usbsuspend
+ *
+ * Description:
+ *   Board logic must provide the stm32l4_usbsuspend logic if the USBDEV driver is
+ *   used.  This function is called whenever the USB enters or leaves suspend mode.
+ *   This is an opportunity for the board logic to shutdown clocks, power, etc.
+ *   while the USB is suspended.
+ *
+ ************************************************************************************/
+
+void stm32l4_usbsuspend(FAR struct usbdev_s *dev, bool resume);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_USBDEV_H */
+
diff --git a/arch/arm/src/stm32l4/stm32l4_usbhost.h b/arch/arm/src/stm32l4/stm32l4_usbhost.h
index 6c695ece1f8..27280620d38 100644
--- a/arch/arm/src/stm32l4/stm32l4_usbhost.h
+++ b/arch/arm/src/stm32l4/stm32l4_usbhost.h
@@ -51,9 +51,9 @@
 #if defined(CONFIG_STM32L4_OTGFS) && defined(CONFIG_USBHOST)
 
 #if defined(CONFIG_STM32L4_STM32L4X5)
-#  include "chip/stm32l4x5xx_otgfs.h"
+#  include "hardware/stm32l4x5xx_otgfs.h"
 #elif defined(CONFIG_STM32L4_STM32L4X6)
-#  include "chip/stm32l4x6xx_otgfs.h"
+#  include "hardware/stm32l4x6xx_otgfs.h"
 #else
 #  error "Unsupported STM32L4 chip"
 #endif
diff --git a/arch/arm/src/stm32l4/stm32l4_wdg.h b/arch/arm/src/stm32l4/stm32l4_wdg.h
index 0d2b0032538..c78f337b53c 100644
--- a/arch/arm/src/stm32l4/stm32l4_wdg.h
+++ b/arch/arm/src/stm32l4/stm32l4_wdg.h
@@ -43,7 +43,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/stm32l4_wdg.h"
+#include "hardware/stm32l4_wdg.h"
 
 #ifdef CONFIG_WATCHDOG
 
diff --git a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c
index f2891edb5bf..e84253cdf2c 100644
--- a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c
+++ b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c
@@ -45,6 +45,7 @@
 
 #include "stm32l4_pwr.h"
 #include "stm32l4_flash.h"
+#include "stm32l4_hsi48.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -67,6 +68,14 @@
 
 #define HSE_DIVISOR (STM32L4_HSE_FREQUENCY + 500000) / 1000000
 
+/* Determine if board wants to use HSI48 as 48 MHz oscillator. */
+
+#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32L4_USE_CLK48)
+#  if STM32L4_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48
+#    define STM32L4_USE_HSI48
+#  endif
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -360,6 +369,15 @@ static inline void rcc_enableapb1(void)
   regval |= RCC_APB1ENR1_USBFSEN;
 #endif
 
+#ifdef STM32L4_USE_HSI48
+  if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE)
+    {
+      /* Clock Recovery System clock enable */
+
+      regval |= RCC_APB1ENR1_CRSEN;
+    }
+#endif
+
   /* Power interface clock enable.  The PWR block is always enabled so that
    * we can set the internal voltage regulator as required.
    */
@@ -519,6 +537,24 @@ static inline void rcc_enableccip(void)
 
   regval = getreg32(STM32L4_RCC_CCIPR);
 
+#if defined(STM32L4_I2C_USE_HSI16)
+#ifdef CONFIG_STM32L4_I2C1
+  /* Select HSI16 as I2C1 clock source. */
+
+  regval |= RCC_CCIPR_I2C1SEL_HSI;
+#endif
+#ifdef CONFIG_STM32L4_I2C2
+  /* Select HSI16 as I2C2 clock source. */
+
+  regval |= RCC_CCIPR_I2C2SEL_HSI;
+#endif
+#ifdef CONFIG_STM32L4_I2C3
+  /* Select HSI16 as I2C3 clock source. */
+
+  regval |= RCC_CCIPR_I2C3SEL_HSI;
+#endif
+#endif /* STM32L4_I2C_USE_HSI16 */
+
 #if defined(STM32L4_USE_CLK48)
   /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source
    * and then we can also do away with STM32L4_USE_CLK48, and give better
@@ -547,6 +583,20 @@ static inline void rcc_enableccip(void)
 #endif
 
   putreg32(regval, STM32L4_RCC_CCIPR);
+
+  /* I2C4 alone has their clock selection in CCIPR2 register. */
+
+#if defined(STM32L4_I2C_USE_HSI16)
+#ifdef CONFIG_STM32L4_I2C4
+  regval = getreg32(STM32L4_RCC_CCIPR2);
+
+  /* Select HSI16 as I2C4 clock source. */
+
+  regval |= RCC_CCIPR_I2C4SEL_HSI;
+
+  putreg32(regval, STM32L4_RCC_CCIPR2);
+#endif
+#endif
 }
 
 /****************************************************************************
@@ -565,7 +615,7 @@ static void stm32l4_stdclockconfig(void)
   uint32_t regval;
   volatile int32_t timeout;
 
-#ifdef STM32L4_BOARD_USEHSI
+#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16)
   /* Enable Internal High-Speed Clock (HSI) */
 
   regval  = getreg32(STM32L4_RCC_CR);
@@ -585,6 +635,10 @@ static void stm32l4_stdclockconfig(void)
           break;
         }
     }
+#endif
+
+#if defined(STM32L4_BOARD_USEHSI)
+  /* Already set above */
 
 #elif defined(STM32L4_BOARD_USEMSI)
   /* Enable Internal Multi-Speed Clock (MSI) */
@@ -877,7 +931,7 @@ static void stm32l4_stdclockconfig(void)
       regval |= RCC_CR_MSIPLLEN;
       putreg32(regval, STM32L4_RCC_CR);
 #  endif
-#endif
+#endif /* STM32L4_USE_LSE */
     }
 }
 #endif
@@ -894,6 +948,12 @@ static inline void rcc_enableperipherals(void)
   rcc_enableahb3();
   rcc_enableapb1();
   rcc_enableapb2();
+
+#ifdef STM32L4_USE_HSI48
+  /* Enable HSI48 clocking to to support USB transfers or RNG */
+
+  stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC);
+#endif
 }
 
 /****************************************************************************
diff --git a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c
index 32d39e25bc2..5bbaf153a49 100644
--- a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c
+++ b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c
@@ -548,6 +548,24 @@ static inline void rcc_enableccip(void)
 
   regval = getreg32(STM32L4_RCC_CCIPR);
 
+#if defined(STM32L4_I2C_USE_HSI16)
+#ifdef CONFIG_STM32L4_I2C1
+  /* Select HSI16 as I2C1 clock source. */
+
+  regval |= RCC_CCIPR_I2C1SEL_HSI;
+#endif
+#ifdef CONFIG_STM32L4_I2C2
+  /* Select HSI16 as I2C2 clock source. */
+
+  regval |= RCC_CCIPR_I2C2SEL_HSI;
+#endif
+#ifdef CONFIG_STM32L4_I2C3
+  /* Select HSI16 as I2C3 clock source. */
+
+  regval |= RCC_CCIPR_I2C3SEL_HSI;
+#endif
+#endif /* STM32L4_I2C_USE_HSI16 */
+
 #if defined(STM32L4_USE_CLK48)
   /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source
    * and then we can also do away with STM32L4_USE_CLK48, and give better
@@ -588,7 +606,7 @@ static void stm32l4_stdclockconfig(void)
   uint32_t regval;
   volatile int32_t timeout;
 
-#ifdef STM32L4_BOARD_USEHSI
+#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16)
   /* Enable Internal High-Speed Clock (HSI) */
 
   regval  = getreg32(STM32L4_RCC_CR);
@@ -608,6 +626,10 @@ static void stm32l4_stdclockconfig(void)
           break;
         }
     }
+#endif
+
+#if defined(STM32L4_BOARD_USEHSI)
+  /* Already set above */
 
 #elif defined(STM32L4_BOARD_USEMSI)
   /* Enable Internal Multi-Speed Clock (MSI) */
@@ -900,7 +922,7 @@ static void stm32l4_stdclockconfig(void)
       regval |= RCC_CR_MSIPLLEN;
       putreg32(regval, STM32L4_RCC_CR);
 #  endif
-#endif
+#endif /* STM32L4_USE_LSE */
     }
 }
 #endif
diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
index eea24cbfc41..60098e47bd2 100644
--- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
+++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c
@@ -44,6 +44,7 @@
 
 #include "stm32l4_pwr.h"
 #include "stm32l4_flash.h"
+#include "stm32l4_hsi48.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -66,6 +67,14 @@
 
 #define HSE_DIVISOR (STM32L4_HSE_FREQUENCY + 500000) / 1000000
 
+/* Determine if board wants to use HSI48 as 48 MHz oscillator. */
+
+#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32L4_USE_CLK48)
+#  if STM32L4_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48
+#    define STM32L4_USE_HSI48
+#  endif
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -416,6 +425,15 @@ static inline void rcc_enableapb1(void)
   regval |= RCC_APB1ENR1_CAN2EN;
 #endif
 
+#ifdef STM32L4_USE_HSI48
+  if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE)
+    {
+      /* Clock Recovery System clock enable */
+
+      regval |= RCC_APB1ENR1_CRSEN;
+    }
+#endif
+
   /* Power interface clock enable.  The PWR block is always enabled so that
    * we can set the internal voltage regulator as required.
    */
@@ -593,6 +611,24 @@ static inline void rcc_enableccip(void)
 
   regval = getreg32(STM32L4_RCC_CCIPR);
 
+#if defined(STM32L4_I2C_USE_HSI16)
+#ifdef CONFIG_STM32L4_I2C1
+  /* Select HSI16 as I2C1 clock source. */
+
+  regval |= RCC_CCIPR_I2C1SEL_HSI;
+#endif
+#ifdef CONFIG_STM32L4_I2C2
+  /* Select HSI16 as I2C2 clock source. */
+
+  regval |= RCC_CCIPR_I2C2SEL_HSI;
+#endif
+#ifdef CONFIG_STM32L4_I2C3
+  /* Select HSI16 as I2C3 clock source. */
+
+  regval |= RCC_CCIPR_I2C3SEL_HSI;
+#endif
+#endif /* STM32L4_I2C_USE_HSI16 */
+
 #if defined(STM32L4_USE_CLK48)
   /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source
    * and then we can also do away with STM32L4_USE_CLK48, and give better
@@ -615,6 +651,20 @@ static inline void rcc_enableccip(void)
 #endif
 
   putreg32(regval, STM32L4_RCC_CCIPR);
+
+  /* I2C4 alone has their clock selection in CCIPR2 register. */
+
+#if defined(STM32L4_I2C_USE_HSI16)
+#ifdef CONFIG_STM32L4_I2C4
+  regval = getreg32(STM32L4_RCC_CCIPR2);
+
+  /* Select HSI16 as I2C4 clock source. */
+
+  regval |= RCC_CCIPR_I2C4SEL_HSI;
+
+  putreg32(regval, STM32L4_RCC_CCIPR2);
+#endif
+#endif
 }
 
 /****************************************************************************
@@ -633,7 +683,7 @@ static void stm32l4_stdclockconfig(void)
   uint32_t regval;
   volatile int32_t timeout;
 
-#ifdef STM32L4_BOARD_USEHSI
+#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16)
   /* Enable Internal High-Speed Clock (HSI) */
 
   regval  = getreg32(STM32L4_RCC_CR);
@@ -653,6 +703,10 @@ static void stm32l4_stdclockconfig(void)
           break;
         }
     }
+#endif
+
+#if defined(STM32L4_BOARD_USEHSI)
+  /* Already set above */
 
 #elif defined(STM32L4_BOARD_USEMSI)
   /* Enable Internal Multi-Speed Clock (MSI) */
@@ -945,7 +999,7 @@ static void stm32l4_stdclockconfig(void)
       regval |= RCC_CR_MSIPLLEN;
       putreg32(regval, STM32L4_RCC_CR);
 #  endif
-#endif
+#endif /* STM32L4_USE_LSE */
     }
 }
 #endif
@@ -962,6 +1016,12 @@ static inline void rcc_enableperipherals(void)
   rcc_enableahb3();
   rcc_enableapb1();
   rcc_enableapb2();
+
+#ifdef STM32L4_USE_HSI48
+  /* Enable HSI48 clocking to to support USB transfers or RNG */
+
+  stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC);
+#endif
 }
 
 /****************************************************************************
diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c
index c9fdbcdd726..6c2c12d9a18 100644
--- a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c
+++ b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c
@@ -44,6 +44,7 @@
 
 #include "stm32l4_pwr.h"
 #include "stm32l4_flash.h"
+#include "stm32l4_hsi48.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -66,6 +67,14 @@
 
 #define HSE_DIVISOR (STM32L4_HSE_FREQUENCY + 500000) / 1000000
 
+/* Determine if board wants to use HSI48 as 48 MHz oscillator. */
+
+#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32L4_USE_CLK48)
+#  if STM32L4_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48
+#    define STM32L4_USE_HSI48
+#  endif
+#endif
+
 /****************************************************************************
  * Private Data
  ****************************************************************************/
@@ -403,6 +412,15 @@ static inline void rcc_enableapb1(void)
   regval |= RCC_APB1ENR1_CAN1EN;
 #endif
 
+#ifdef STM32L4_USE_HSI48
+  if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE)
+    {
+      /* Clock Recovery System clock enable */
+
+      regval |= RCC_APB1ENR1_CRSEN;
+    }
+#endif
+
   /* Power interface clock enable.  The PWR block is always enabled so that
    * we can set the internal voltage regulator as required.
    */
@@ -568,6 +586,24 @@ static inline void rcc_enableccip(void)
 
   regval = getreg32(STM32L4_RCC_CCIPR);
 
+#if defined(STM32L4_I2C_USE_HSI16)
+#ifdef CONFIG_STM32L4_I2C1
+  /* Select HSI16 as I2C1 clock source. */
+
+  regval |= RCC_CCIPR_I2C1SEL_HSI;
+#endif
+#ifdef CONFIG_STM32L4_I2C2
+  /* Select HSI16 as I2C2 clock source. */
+
+  regval |= RCC_CCIPR_I2C2SEL_HSI;
+#endif
+#ifdef CONFIG_STM32L4_I2C3
+  /* Select HSI16 as I2C3 clock source. */
+
+  regval |= RCC_CCIPR_I2C3SEL_HSI;
+#endif
+#endif /* STM32L4_I2C_USE_HSI16 */
+
 #if defined(STM32L4_USE_CLK48)
   /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source
    * and then we can also do away with STM32L4_USE_CLK48, and give better
@@ -589,6 +625,14 @@ static inline void rcc_enableccip(void)
 
   regval = getreg32(STM32L4_RCC_CCIPR2);
 
+#if defined(STM32L4_I2C_USE_HSI16)
+#ifdef CONFIG_STM32L4_I2C4
+  /* Select HSI16 as I2C4 clock source. */
+
+  regval |= RCC_CCIPR2_I2C4SEL_HSI;
+#endif
+#endif
+
 #ifdef CONFIG_STM32L4_DFSDM1
   /* Select SAI1 as DFSDM audio clock source. */
 
@@ -618,7 +662,7 @@ static void stm32l4_stdclockconfig(void)
   uint32_t regval;
   volatile int32_t timeout;
 
-#ifdef STM32L4_BOARD_USEHSI
+#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16)
   /* Enable Internal High-Speed Clock (HSI) */
 
   regval  = getreg32(STM32L4_RCC_CR);
@@ -638,6 +682,10 @@ static void stm32l4_stdclockconfig(void)
           break;
         }
     }
+#endif
+
+#if defined(STM32L4_BOARD_USEHSI)
+  /* Already set above */
 
 #elif defined(STM32L4_BOARD_USEMSI)
   /* Enable Internal Multi-Speed Clock (MSI) */
@@ -708,21 +756,20 @@ static void stm32l4_stdclockconfig(void)
   if (timeout > 0)
     {
 #warning todo: regulator voltage according to clock freq
-#if 0
       /* Ensure Power control is enabled before modifying it. */
 
-      regval  = getreg32(STM32L4_RCC_APB1ENR);
-      regval |= RCC_APB1ENR_PWREN;
-      putreg32(regval, STM32L4_RCC_APB1ENR);
+      regval  = getreg32(STM32L4_RCC_APB1ENR1);
+      regval |= RCC_APB1ENR1_PWREN;
+      putreg32(regval, STM32L4_RCC_APB1ENR1);
 
-      /* Select regulator voltage output Scale 1 mode to support system
-       * frequencies up to 168 MHz.
+      /* Switch to Range 1 boost mode to support system
+       * frequencies up to 120 MHz. Range 2 is not supported.
        */
 
-      regval  = getreg32(STM32L4_PWR_CR);
-      regval &= ~PWR_CR_VOS_MASK;
-      regval |= PWR_CR_VOS_SCALE_1;
-      putreg32(regval, STM32L4_PWR_CR);
+#if STM32L4_SYSCLK_FREQUENCY > 80000000
+      regval  = getreg32(STM32L4_PWR_CR5);
+      regval &= ~PWR_CR5_R1MODE;
+      putreg32(regval, STM32L4_PWR_CR5);
 #endif
 
       /* Set the HCLK source/divider */
@@ -915,15 +962,6 @@ static void stm32l4_stdclockconfig(void)
        * XXX and other cases, like automatic trimming of MSI for USB use
        */
 
-      /* ensure Power control is enabled since it is indirectly required
-       * to alter the LSE parameters.
-       */
-      stm32l4_pwr_enableclk(true);
-
-      /* XXX other LSE settings must be made before turning on the oscillator
-       * and we need to ensure it is first off before doing so.
-       */
-
       /* Turn on the LSE oscillator
        * XXX this will almost surely get moved since we also want to use
        * this for automatically trimming MSI, etc.
@@ -938,7 +976,7 @@ static void stm32l4_stdclockconfig(void)
       regval |= RCC_CR_MSIPLLEN;
       putreg32(regval, STM32L4_RCC_CR);
 #  endif
-#endif
+#endif /* STM32L4_USE_LSE */
     }
 }
 #endif
@@ -955,6 +993,12 @@ static inline void rcc_enableperipherals(void)
   rcc_enableahb3();
   rcc_enableapb1();
   rcc_enableapb2();
+
+#ifdef STM32L4_USE_HSI48
+  /* Enable HSI48 clocking to to support USB transfers or RNG */
+
+  stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC);
+#endif
 }
 
 /****************************************************************************
diff --git a/arch/arm/src/str71x/Make.defs b/arch/arm/src/str71x/Make.defs
index 7c0ac475076..4bfe680d4b8 100644
--- a/arch/arm/src/str71x/Make.defs
+++ b/arch/arm/src/str71x/Make.defs
@@ -44,16 +44,13 @@ CMN_CSRCS += up_exit.c up_initialize.c up_initialstate.c
 CMN_CSRCS += up_interruptcontext.c up_prefetchabort.c up_releasepending.c
 CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_stackframe.c
 CMN_CSRCS += up_syscall.c up_unblocktask.c up_undefinedinsn.c up_usestack.c
+CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c
 CMN_CSRCS += up_lowputs.c up_vfork.c
 
 ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
 CMN_CSRCS += up_idle.c
 endif
 
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
-CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c
-endif
-
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
 endif
diff --git a/arch/arm/src/tiva/Make.defs b/arch/arm/src/tiva/Make.defs
index ee8b83dcccd..b92fcc0df81 100644
--- a/arch/arm/src/tiva/Make.defs
+++ b/arch/arm/src/tiva/Make.defs
@@ -75,10 +75,8 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
   CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
   CMN_CSRCS += up_signal_dispatch.c
   CMN_UASRCS += up_signal_handler.S
-endif
 else
   CMN_CSRCS += up_allocateheap.c
 endif
diff --git a/arch/arm/src/tiva/cc13xx/cc13xx_start.c b/arch/arm/src/tiva/cc13xx/cc13xx_start.c
index d361076a602..cecc72d10c3 100644
--- a/arch/arm/src/tiva/cc13xx/cc13xx_start.c
+++ b/arch/arm/src/tiva/cc13xx/cc13xx_start.c
@@ -46,10 +46,7 @@
 #include 
 #include 
 
-#ifdef CONFIG_ARCH_FPU
-#  include "nvic.h"
-#endif
-
+#include "nvic.h"
 #include "up_arch.h"
 #include "up_internal.h"
 
diff --git a/arch/arm/src/tiva/common/lmxx_tm4c_start.c b/arch/arm/src/tiva/common/lmxx_tm4c_start.c
index d09c0fc75e3..14514d27c3f 100644
--- a/arch/arm/src/tiva/common/lmxx_tm4c_start.c
+++ b/arch/arm/src/tiva/common/lmxx_tm4c_start.c
@@ -46,10 +46,7 @@
 #include 
 #include 
 
-#ifdef CONFIG_ARCH_FPU
-#  include "nvic.h"
-#endif
-
+#include "nvic.h"
 #include "up_arch.h"
 #include "up_internal.h"
 
diff --git a/arch/arm/src/tiva/hardware/lm/lm4f_pinmap.h b/arch/arm/src/tiva/hardware/lm/lm4f_pinmap.h
index fec57c34059..622f1ce6a2c 100644
--- a/arch/arm/src/tiva/hardware/lm/lm4f_pinmap.h
+++ b/arch/arm/src/tiva/hardware/lm/lm4f_pinmap.h
@@ -56,7 +56,7 @@
  *
  * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
  *
- * The driver will then automatically configre PA11 as the CAN1 RX pin.
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
diff --git a/arch/arm/src/tms570/Make.defs b/arch/arm/src/tms570/Make.defs
index 4e6a2318062..2661fbb7a97 100644
--- a/arch/arm/src/tms570/Make.defs
+++ b/arch/arm/src/tms570/Make.defs
@@ -74,11 +74,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += arm_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += arm_signal_dispatch.c
 CMN_UASRCS += arm_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_ARMV7R_L2CC_PL310),y)
 CMN_CSRCS += arm_l2cc_pl310.c
diff --git a/arch/arm/src/tms570/chip.h b/arch/arm/src/tms570/chip.h
index 9985e49363f..76e3a8cc383 100644
--- a/arch/arm/src/tms570/chip.h
+++ b/arch/arm/src/tms570/chip.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/tms570_memorymap.h"
+#include "hardware/tms570_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/tms570/chip/tms570_esm.h b/arch/arm/src/tms570/hardware/tms570_esm.h
similarity index 97%
rename from arch/arm/src/tms570/chip/tms570_esm.h
rename to arch/arm/src/tms570/hardware/tms570_esm.h
index cd1ac9877c6..04289492f2d 100644
--- a/arch/arm/src/tms570/chip/tms570_esm.h
+++ b/arch/arm/src/tms570/hardware/tms570_esm.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/tms570/chip/tms570_esm.h
+ * arch/arm/src/tms570/hardware/tms570_esm.h
  * Error Signalling Module Error Definitions
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -39,15 +39,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_ESM_H
-#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_ESM_H
+#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_ESM_H
+#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_ESM_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/tms570_memorymap.h"
+#include "hardware/tms570_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -208,4 +208,4 @@
 
 #define ESM_ILCR4_CHAN(n)         (1 << (n)) /* Bit n: Maps channel n low level interrupt */
 
-#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_ESM_H */
+#endif /* __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_ESM_H */
diff --git a/arch/arm/src/tms570/chip/tms570_flash.h b/arch/arm/src/tms570/hardware/tms570_flash.h
similarity index 98%
rename from arch/arm/src/tms570/chip/tms570_flash.h
rename to arch/arm/src/tms570/hardware/tms570_flash.h
index d1b14666760..80b1af6ec89 100644
--- a/arch/arm/src/tms570/chip/tms570_flash.h
+++ b/arch/arm/src/tms570/hardware/tms570_flash.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/tms570/chip/tms570_flash.h
+ * arch/arm/src/tms570/hardware/tms570_flash.h
  * FLASH Module Controller Register Definitions
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -39,15 +39,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_FLASH_H
-#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_FLASH_H
+#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_FLASH_H
+#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_FLASH_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/tms570_memorymap.h"
+#include "hardware/tms570_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -268,4 +268,4 @@
 /* Flash Bank Configuration Register */
 #define FLASH_FCFGBANK_
 
-#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_FLASH_H */
+#endif /* __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_FLASH_H */
diff --git a/arch/arm/src/tms570/chip/tms570_gio.h b/arch/arm/src/tms570/hardware/tms570_gio.h
similarity index 99%
rename from arch/arm/src/tms570/chip/tms570_gio.h
rename to arch/arm/src/tms570/hardware/tms570_gio.h
index 1599e58ff5a..1e5c5929b2f 100644
--- a/arch/arm/src/tms570/chip/tms570_gio.h
+++ b/arch/arm/src/tms570/hardware/tms570_gio.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/tms570/chip/tms570_gio.h
+ * arch/arm/src/tms570/hardware/tms570_gio.h
  * Secondary System Control Register Definitions
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -39,15 +39,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_GIO_H
-#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_GIO_H
+#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_GIO_H
+#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_GIO_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/tms570_memorymap.h"
+#include "hardware/tms570_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -442,4 +442,4 @@
 
 #define GIO_PIN(n)                     (1 << (n)) /* Bit n:  Corresponds to pin n */
 
-#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_GIO_H */
+#endif /* __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_GIO_H */
diff --git a/arch/arm/src/tms570/chip/tms570_iomm.h b/arch/arm/src/tms570/hardware/tms570_iomm.h
similarity index 97%
rename from arch/arm/src/tms570/chip/tms570_iomm.h
rename to arch/arm/src/tms570/hardware/tms570_iomm.h
index bafd17420a1..ead7d1c5f8e 100644
--- a/arch/arm/src/tms570/chip/tms570_iomm.h
+++ b/arch/arm/src/tms570/hardware/tms570_iomm.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/tms570/chip/tms570_iomm.h
+ * arch/arm/src/tms570/hardware/tms570_iomm.h
  * I/O Muliplexing and Control Module (IOMM) Definitions
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -39,15 +39,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_IOMM_H
-#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_IOMM_H
+#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_IOMM_H
+#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_IOMM_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/tms570_memorymap.h"
+#include "hardware/tms570_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -188,4 +188,4 @@
 #define IOMM_PINMMR_PINMASK(n)          (0xff << IOMM_PINMMR_PINSHIFT(n))
 #  define IOMM_PINMMR_PINVALUE(n,v)     ((uint32_t)(v) << IOMM_PINMMR_PINSHIFT(n))
 
-#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_IOMM_H */
+#endif /* __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_IOMM_H */
diff --git a/arch/arm/src/tms570/chip/tms570_memorymap.h b/arch/arm/src/tms570/hardware/tms570_memorymap.h
similarity index 87%
rename from arch/arm/src/tms570/chip/tms570_memorymap.h
rename to arch/arm/src/tms570/hardware/tms570_memorymap.h
index fafb946b79d..06d91e79c66 100644
--- a/arch/arm/src/tms570/chip/tms570_memorymap.h
+++ b/arch/arm/src/tms570/hardware/tms570_memorymap.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/tms570/chip/tms570_memorymap.h
+ * arch/arm/src/tms570/hardware/tms570_memorymap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_MEMORYMAP_H
-#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_MEMORYMAP_H
+#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_MEMORYMAP_H
 
 /****************************************************************************************************
  * Included Files
@@ -45,9 +45,9 @@
 #if defined(CONFIG_ARCH_CHIP_TMS570LS0232PZ)
 #  error No memory map for the TMS570LS0232PZ
 #elif defined(CONFIG_ARCH_CHIP_TMS570LS0332PZ)
-#  include "chip/tms570ls04x03x_memorymap.h"
+#  include "hardware/tms570ls04x03x_memorymap.h"
 #elif defined(CONFIG_ARCH_CHIP_TMS570LS0432PZ)
-#  include "chip/tms570ls04x03x_memorymap.h"
+#  include "hardware/tms570ls04x03x_memorymap.h"
 #elif defined(CONFIG_ARCH_CHIP_TMS570LS0714PZ)
 #  error No memory map for the TMS570LS0714PZ
 #elif defined(CONFIG_ARCH_CHIP_TMS570LS0714PGE)
@@ -57,9 +57,9 @@
 #elif defined(CONFIG_ARCH_CHIP_TMS570LS1227ZWT)
 #  error No memory map for the TMS570LS1227ZWT
 #elif defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT)
-#  include "chip/tms570ls31xx_memorymap.h"
+#  include "hardware/tms570ls31xx_memorymap.h"
 #else
 #  error "Unrecognized Hercules chip"
 #endif
 
-#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_MEMORYMAP_H */
diff --git a/arch/arm/src/tms570/chip/tms570_pbist.h b/arch/arm/src/tms570/hardware/tms570_pbist.h
similarity index 98%
rename from arch/arm/src/tms570/chip/tms570_pbist.h
rename to arch/arm/src/tms570/hardware/tms570_pbist.h
index 2e4cfb5d725..b3f21fd7842 100644
--- a/arch/arm/src/tms570/chip/tms570_pbist.h
+++ b/arch/arm/src/tms570/hardware/tms570_pbist.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/tms570/chip/tms570_pbist.h
+ * arch/arm/src/tms570/hardware/tms570_pbist.h
  * Secondary System Control Register Definitions
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -39,15 +39,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PBIST_H
-#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PBIST_H
+#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PBIST_H
+#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PBIST_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/tms570_memorymap.h"
+#include "hardware/tms570_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -245,4 +245,4 @@
 
 /* RAM Info Mask Upper Register */
 
-#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PBIST_H */
+#endif /* __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PBIST_H */
diff --git a/arch/arm/src/tms570/chip/tms570_pcr.h b/arch/arm/src/tms570/hardware/tms570_pcr.h
similarity index 99%
rename from arch/arm/src/tms570/chip/tms570_pcr.h
rename to arch/arm/src/tms570/hardware/tms570_pcr.h
index c928da5e6ce..b75c4c00b64 100644
--- a/arch/arm/src/tms570/chip/tms570_pcr.h
+++ b/arch/arm/src/tms570/hardware/tms570_pcr.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/tms570/chip/tms570_pcr.h
+ * arch/arm/src/tms570/hardware/tms570_pcr.h
  * Peripheral Control Register (PCR) Definitions
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -39,15 +39,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PCR_H
-#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PCR_H
+#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PCR_H
+#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PCR_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/tms570_memorymap.h"
+#include "hardware/tms570_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -393,4 +393,4 @@
 #  define PCR_PSPWERDWN3_PS31_Q4        (8 << PCR_PSPWERDWN3_PS31_SHIFT)
 #  define PCR_PSPWERDWN3_PS31_QALL      (15 << PCR_PSPWERDWN3_PS31_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PCR_H */
+#endif /* __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PCR_H */
diff --git a/arch/arm/src/tms570/chip/tms570_pinmux.h b/arch/arm/src/tms570/hardware/tms570_pinmux.h
similarity index 90%
rename from arch/arm/src/tms570/chip/tms570_pinmux.h
rename to arch/arm/src/tms570/hardware/tms570_pinmux.h
index af97106b7c1..db708c02a79 100644
--- a/arch/arm/src/tms570/chip/tms570_pinmux.h
+++ b/arch/arm/src/tms570/hardware/tms570_pinmux.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/tms570/chip/tms570_pinmux.h
+ * arch/arm/src/tms570/hardware/tms570_pinmux.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PINMUX_H
-#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PINMUX_H
+#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PINMUX_H
+#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PINMUX_H
 
 /****************************************************************************************************
  * Included Files
@@ -45,9 +45,9 @@
 #if defined(CONFIG_ARCH_CHIP_TMS570LS0232PZ)
 #  error No pin multiplexing for the TMS570LS0232PZ
 #elif defined(CONFIG_ARCH_CHIP_TMS570LS0332PZ)
-#  include "chip/tms570ls04x03x_pinmux.h"
+#  include "hardware/tms570ls04x03x_pinmux.h"
 #elif defined(CONFIG_ARCH_CHIP_TMS570LS0432PZ)
-#  include "chip/tms570ls04x03x_pinmux.h"
+#  include "hardware/tms570ls04x03x_pinmux.h"
 #elif defined(CONFIG_ARCH_CHIP_TMS570LS0714PZ)
 #  error No pin multiplexing for the TMS570LS0714PZ
 #elif defined(CONFIG_ARCH_CHIP_TMS570LS0714PGE)
@@ -57,7 +57,7 @@
 #elif defined(CONFIG_ARCH_CHIP_TMS570LS1227ZWT)
 #  error No pin multiplexing for the TMS570LS1227ZWT
 #elif defined(CONFIG_ARCH_CHIP_TMS570LS3137ZWT)
-#  include "chip/tms570ls04x03x_pinmux.h"
+#  include "hardware/tms570ls04x03x_pinmux.h"
 #else
 #  error "Unrecognized Hercules chip"
 #endif
@@ -75,4 +75,4 @@ struct tms570_pinmux_s
   uint8_t value;   /* The new value for the pin field in the PINMMR register */
 };
 
-#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PINMUX_H */
+#endif /* __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_PINMUX_H */
diff --git a/arch/arm/src/tms570/chip/tms570_rti.h b/arch/arm/src/tms570/hardware/tms570_rti.h
similarity index 98%
rename from arch/arm/src/tms570/chip/tms570_rti.h
rename to arch/arm/src/tms570/hardware/tms570_rti.h
index 69fc30739d3..8c6bd5e8092 100644
--- a/arch/arm/src/tms570/chip/tms570_rti.h
+++ b/arch/arm/src/tms570/hardware/tms570_rti.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/tms570/chip/tms570_rti.h
+ * arch/arm/src/tms570/hardware/tms570_rti.h
  * Real Time Interrupt (RTI) Module Register Definitions
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -39,15 +39,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_RTI_H
-#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_RTI_H
+#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_RTI_H
+#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_RTI_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/tms570_memorymap.h"
+#include "hardware/tms570_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -200,4 +200,4 @@
 /* RTI Compare 3 Clear Register */
 #define RTI_COMP3CLR_
 
-#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_RTI_H */
+#endif /* __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_RTI_H */
diff --git a/arch/arm/src/tms570/chip/tms570_sci.h b/arch/arm/src/tms570/hardware/tms570_sci.h
similarity index 98%
rename from arch/arm/src/tms570/chip/tms570_sci.h
rename to arch/arm/src/tms570/hardware/tms570_sci.h
index 71c4857c68b..81e85eabe1b 100644
--- a/arch/arm/src/tms570/chip/tms570_sci.h
+++ b/arch/arm/src/tms570/hardware/tms570_sci.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/tms570/chip/tms570_sci.h
+ * arch/arm/src/tms570/hardware/tms570_sci.h
  * Secondary System Control Register Definitions
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -39,15 +39,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_SCI_H
-#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_SCI_H
+#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SCI_H
+#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SCI_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/tms570_memorymap.h"
+#include "hardware/tms570_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -362,4 +362,4 @@
 /* Input/Output Error Enable Register */
 #define SCI_IODFTCTRL_
 
-#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_SCI_H */
+#endif /* __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SCI_H */
diff --git a/arch/arm/src/tms570/chip/tms570_sys.h b/arch/arm/src/tms570/hardware/tms570_sys.h
similarity index 99%
rename from arch/arm/src/tms570/chip/tms570_sys.h
rename to arch/arm/src/tms570/hardware/tms570_sys.h
index 8357d8923eb..e1ce9289651 100644
--- a/arch/arm/src/tms570/chip/tms570_sys.h
+++ b/arch/arm/src/tms570/hardware/tms570_sys.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/tms570/chip/tms570_sys.h
+ * arch/arm/src/tms570/hardware/tms570_sys.h
  * Primary System Control Register Definitions
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -39,15 +39,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_SYS_H
-#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_SYS_H
+#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS_H
+#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/tms570_memorymap.h"
+#include "hardware/tms570_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -658,4 +658,4 @@
 /* System Software Interrupt Flag Register */
 #define SYS_SSIF_
 
-#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_SYS_H */
+#endif /* __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS_H */
diff --git a/arch/arm/src/tms570/chip/tms570_sys2.h b/arch/arm/src/tms570/hardware/tms570_sys2.h
similarity index 97%
rename from arch/arm/src/tms570/chip/tms570_sys2.h
rename to arch/arm/src/tms570/hardware/tms570_sys2.h
index 9772b8dd235..23570a018ed 100644
--- a/arch/arm/src/tms570/chip/tms570_sys2.h
+++ b/arch/arm/src/tms570/hardware/tms570_sys2.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/tms570/chip/tms570_sys2.h
+ * arch/arm/src/tms570/hardware/tms570_sys2.h
  * Secondary System Control Register Definitions
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -39,15 +39,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_SYS2_H
-#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_SYS2_H
+#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS2_H
+#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS2_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/tms570_memorymap.h"
+#include "hardware/tms570_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -156,4 +156,4 @@
 
 #endif
 
-#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_SYS2_H */
+#endif /* __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_SYS2_H */
diff --git a/arch/arm/src/tms570/chip/tms570_vim.h b/arch/arm/src/tms570/hardware/tms570_vim.h
similarity index 97%
rename from arch/arm/src/tms570/chip/tms570_vim.h
rename to arch/arm/src/tms570/hardware/tms570_vim.h
index 9b30c33374c..8da356a21c2 100644
--- a/arch/arm/src/tms570/chip/tms570_vim.h
+++ b/arch/arm/src/tms570/hardware/tms570_vim.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/tms570/chip/tms570_vim.h
+ * arch/arm/src/tms570/hardware/tms570_vim.h
  * Vector Intererrupt Manager (VIM) Register Definitions
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -39,15 +39,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_VIM_H
-#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_VIM_H
+#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_VIM_H
+#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_VIM_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/tms570_memorymap.h"
+#include "hardware/tms570_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -215,4 +215,4 @@
 #define VIM_CHANCTRL_MASK(n)            (0xff << VIM_CHANCTRL_SHIFT(n))
 #  define VIM_CHANCTRL(n,v)             ((uint32_t)(v) << VIM_CHANCTRL_SHIFT(n))
 
-#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_VIM_H */
+#endif /* __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570_VIM_H */
diff --git a/arch/arm/src/tms570/chip/tms570ls04x03x_memorymap.h b/arch/arm/src/tms570/hardware/tms570ls04x03x_memorymap.h
similarity index 96%
rename from arch/arm/src/tms570/chip/tms570ls04x03x_memorymap.h
rename to arch/arm/src/tms570/hardware/tms570ls04x03x_memorymap.h
index df12323497d..22378571ce2 100644
--- a/arch/arm/src/tms570/chip/tms570ls04x03x_memorymap.h
+++ b/arch/arm/src/tms570/hardware/tms570ls04x03x_memorymap.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/tms570/chip/tms570ls04x03x_memorymap.h
+ * arch/arm/src/tms570/hardware/tms570ls04x03x_memorymap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570LS04X03X_MEMORYMAP_H
-#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570LS04X03X_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_MEMORYMAP_H
+#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_MEMORYMAP_H
 
 /****************************************************************************************************
  * Included Files
@@ -128,4 +128,4 @@
 #define TMS570_VIM_BASE           0xfffffe00 /* 0xfffffe00-0xfffffeff: VIM */
 #define TMS570_SYS_BASE           0xffffff00 /* 0xffffff00-0xffffffff: System Module - Frame 1 */
 
-#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570LS04X03X_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_MEMORYMAP_H */
diff --git a/arch/arm/src/tms570/chip/tms570ls04x03x_pinmux.h b/arch/arm/src/tms570/hardware/tms570ls04x03x_pinmux.h
similarity index 97%
rename from arch/arm/src/tms570/chip/tms570ls04x03x_pinmux.h
rename to arch/arm/src/tms570/hardware/tms570ls04x03x_pinmux.h
index 113d9dfc757..d46633bfcb5 100644
--- a/arch/arm/src/tms570/chip/tms570ls04x03x_pinmux.h
+++ b/arch/arm/src/tms570/hardware/tms570ls04x03x_pinmux.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/arm/src/tms570/chip/tms570ls04x03x_pinmux.h
+ * arch/arm/src/tms570/hardware/tms570ls04x03x_pinmux.h
  * Secondary System Control Register Definitions
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
@@ -39,15 +39,15 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570LS04X03X_PINMUX_H
-#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570LS04X03X_PINMUX_H
+#ifndef __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_PINMUX_H
+#define __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_PINMUX_H
 
 /****************************************************************************************************
  * Included Files
  ****************************************************************************************************/
 
 #include 
-#include "chip/tms570_memorymap.h"
+#include "hardware/tms570_memorymap.h"
 
 /****************************************************************************************************
  * Pre-processor Definitions
@@ -254,4 +254,4 @@
 #define PINMUX_N2HET17_VALUE      4
 #define PINMUX_N2HET17_PIN        {PINMUX_N2HET17_PINMMR, PINMUX_N2HET17_SHIFT, PINMUX_N2HET17_VALUE}
 
-#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570LS04X03X_PINMUX_H */
+#endif /* __ARCH_ARM_SRC_TMS570_HARDWARE_TMS570LS04X03X_PINMUX_H */
diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c
index 94e9cd9745d..ba8b552cab8 100644
--- a/arch/arm/src/tms570/tms570_boot.c
+++ b/arch/arm/src/tms570/tms570_boot.c
@@ -61,9 +61,9 @@
 
 #include 
 
-#include "chip/tms570_sys.h"
-#include "chip/tms570_esm.h"
-#include "chip/tms570_pbist.h"
+#include "hardware/tms570_sys.h"
+#include "hardware/tms570_esm.h"
+#include "hardware/tms570_pbist.h"
 #include "tms570_clockconfig.h"
 #include "tms570_selftest.h"
 #include "tms570_gio.h"
diff --git a/arch/arm/src/tms570/tms570_clockconfig.c b/arch/arm/src/tms570/tms570_clockconfig.c
index a1f6815d0ed..1dd057fab36 100644
--- a/arch/arm/src/tms570/tms570_clockconfig.c
+++ b/arch/arm/src/tms570/tms570_clockconfig.c
@@ -50,13 +50,13 @@
 
 #include "up_arch.h"
 
-#include "chip/tms570_esm.h"
-#include "chip/tms570_sys.h"
-#include "chip/tms570_sys2.h"
-#include "chip/tms570_pcr.h"
-#include "chip/tms570_flash.h"
-#include "chip/tms570_iomm.h"
-#include "chip/tms570_pinmux.h"
+#include "hardware/tms570_esm.h"
+#include "hardware/tms570_sys.h"
+#include "hardware/tms570_sys2.h"
+#include "hardware/tms570_pcr.h"
+#include "hardware/tms570_flash.h"
+#include "hardware/tms570_iomm.h"
+#include "hardware/tms570_pinmux.h"
 
 #include "tms570_selftest.h"
 #include "tms570_clockconfig.h"
diff --git a/arch/arm/src/tms570/tms570_esm.c b/arch/arm/src/tms570/tms570_esm.c
index f267f1a8fde..da72b0d3601 100644
--- a/arch/arm/src/tms570/tms570_esm.c
+++ b/arch/arm/src/tms570/tms570_esm.c
@@ -55,7 +55,7 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/tms570_esm.h"
+#include "hardware/tms570_esm.h"
 #include "tms570_esm.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/tms570/tms570_gio.c b/arch/arm/src/tms570/tms570_gio.c
index 34ffb4cfd21..089fd67bfb4 100644
--- a/arch/arm/src/tms570/tms570_gio.c
+++ b/arch/arm/src/tms570/tms570_gio.c
@@ -51,7 +51,7 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/tms570_gio.h"
+#include "hardware/tms570_gio.h"
 #include "tms570_gio.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/tms570/tms570_gio.h b/arch/arm/src/tms570/tms570_gio.h
index 45fa7073fb0..e509a81a646 100644
--- a/arch/arm/src/tms570/tms570_gio.h
+++ b/arch/arm/src/tms570/tms570_gio.h
@@ -46,7 +46,7 @@
 #include 
 #include 
 
-#include "chip/tms570_gio.h"
+#include "hardware/tms570_gio.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/tms570/tms570_gioirq.c b/arch/arm/src/tms570/tms570_gioirq.c
index b4b5cf327b2..4c7d1c03386 100644
--- a/arch/arm/src/tms570/tms570_gioirq.c
+++ b/arch/arm/src/tms570/tms570_gioirq.c
@@ -54,7 +54,7 @@
 #include "up_internal.h"
 
 #include "tms570_gio.h"
-#include "chip/tms570_gio.h"
+#include "hardware/tms570_gio.h"
 
 #ifdef CONFIG_TMS570_GIO_IRQ
 
diff --git a/arch/arm/src/tms570/tms570_irq.c b/arch/arm/src/tms570/tms570_irq.c
index 44d423b4707..87b74952672 100644
--- a/arch/arm/src/tms570/tms570_irq.c
+++ b/arch/arm/src/tms570/tms570_irq.c
@@ -51,7 +51,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/tms570_vim.h"
+#include "hardware/tms570_vim.h"
 #include "tms570_gio.h"
 #include "tms570_esm.h"
 #include "tms570_irq.h"
diff --git a/arch/arm/src/tms570/tms570_lowputc.c b/arch/arm/src/tms570/tms570_lowputc.c
index cba122a546d..e9ae4824303 100644
--- a/arch/arm/src/tms570/tms570_lowputc.c
+++ b/arch/arm/src/tms570/tms570_lowputc.c
@@ -54,8 +54,8 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/tms570_sci.h"
-#include "chip/tms570_iomm.h"
+#include "hardware/tms570_sci.h"
+#include "hardware/tms570_iomm.h"
 #include "tms570_lowputc.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/tms570/tms570_selftest.c b/arch/arm/src/tms570/tms570_selftest.c
index 3abb8d71224..8a1d55aaf14 100644
--- a/arch/arm/src/tms570/tms570_selftest.c
+++ b/arch/arm/src/tms570/tms570_selftest.c
@@ -52,8 +52,8 @@
 
 #include "up_arch.h"
 
-#include "chip/tms570_sys.h"
-#include "chip/tms570_pbist.h"
+#include "hardware/tms570_sys.h"
+#include "hardware/tms570_pbist.h"
 #include "tms570_selftest.h"
 
 #ifdef CONFIG_TMS570_SELFTEST
diff --git a/arch/arm/src/tms570/tms570_serial.c b/arch/arm/src/tms570/tms570_serial.c
index f1f39003114..2313d4d142b 100644
--- a/arch/arm/src/tms570/tms570_serial.c
+++ b/arch/arm/src/tms570/tms570_serial.c
@@ -62,7 +62,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/tms570_sci.h"
+#include "hardware/tms570_sci.h"
 #include "tms570_lowputc.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/tms570/tms570_timerisr.c b/arch/arm/src/tms570/tms570_timerisr.c
index 38b5072c3dd..33962249ef0 100644
--- a/arch/arm/src/tms570/tms570_timerisr.c
+++ b/arch/arm/src/tms570/tms570_timerisr.c
@@ -46,7 +46,7 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/tms570_rti.h"
+#include "hardware/tms570_rti.h"
 
 #include 
 
diff --git a/arch/arm/src/xmc4/Make.defs b/arch/arm/src/xmc4/Make.defs
index 3c71357021c..ffbccadb035 100644
--- a/arch/arm/src/xmc4/Make.defs
+++ b/arch/arm/src/xmc4/Make.defs
@@ -67,11 +67,9 @@ endif
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 CMN_CSRCS += up_signal_dispatch.c
 CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += up_checkstack.c
diff --git a/arch/arm/src/xmc4/chip.h b/arch/arm/src/xmc4/chip.h
index d8094698a48..93c2f4a506a 100644
--- a/arch/arm/src/xmc4/chip.h
+++ b/arch/arm/src/xmc4/chip.h
@@ -48,7 +48,7 @@
 
 #include 
 #include 
-#include "chip/xmc4_memorymap.h"
+#include "hardware/xmc4_memorymap.h"
 
 /* If the common ARMv7-M vector handling logic is used, then it expects the
  * following definition in this file that provides the number of supported external
diff --git a/arch/arm/src/xmc4/chip/xmc4_ethernet.h b/arch/arm/src/xmc4/hardware/xmc4_ethernet.h
similarity index 99%
rename from arch/arm/src/xmc4/chip/xmc4_ethernet.h
rename to arch/arm/src/xmc4/hardware/xmc4_ethernet.h
index 22c163b661f..33266463474 100644
--- a/arch/arm/src/xmc4/chip/xmc4_ethernet.h
+++ b/arch/arm/src/xmc4/hardware/xmc4_ethernet.h
@@ -1,5 +1,5 @@
 /********************************************************************************************************************
- * arch/arm/src/xmc4/chip/xmc4_ethernet.h
+ * arch/arm/src/xmc4/hardware/xmc4_ethernet.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -49,8 +49,8 @@
  *
  ********************************************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_ETHERNET_H
-#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_ETHERNET_H
+#ifndef __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_ETHERNET_H
+#define __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_ETHERNET_H
 
 /********************************************************************************************************************
  * Included Files
@@ -58,7 +58,7 @@
 
 #include 
 
-#include "chip/xmc4_memorymap.h"
+#include "hardware/xmc4_memorymap.h"
 
 /********************************************************************************************************************
  * Pre-processor Definitions
@@ -647,4 +647,4 @@
 /* HW Feature Register */
 #define ETH_HW_FEATURE_
 
-#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_ETHERNET_H */
+#endif /* __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_ETHERNET_H */
diff --git a/arch/arm/src/xmc4/chip/xmc4_flash.h b/arch/arm/src/xmc4/hardware/xmc4_flash.h
similarity index 98%
rename from arch/arm/src/xmc4/chip/xmc4_flash.h
rename to arch/arm/src/xmc4/hardware/xmc4_flash.h
index 0432e465b0a..93bd81a619f 100644
--- a/arch/arm/src/xmc4/chip/xmc4_flash.h
+++ b/arch/arm/src/xmc4/hardware/xmc4_flash.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/xmc4/chip/xmc4_flash.h
+ * arch/arm/src/xmc4/hardware/xmc4_flash.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -49,8 +49,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H
-#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H
+#ifndef __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_FLASH_H
+#define __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_FLASH_H
 
 /************************************************************************************
  * Included Files
@@ -58,7 +58,7 @@
 
 #include 
 
-#include "chip/xmc4_memorymap.h"
+#include "hardware/xmc4_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -202,4 +202,4 @@
 #define FLASH_PROCON2_S12_S13ROM    (1 << 11) /* Bit 11: Sectors 12 and 13 Locked Forever by User 2 */
 #define FLASH_PROCON2_S14_S15ROM    (1 << 12) /* Bit 12: Sectors 14 and 15 Locked Forever by User 2 */
 
-#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_FLASH_H */
+#endif /* __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_FLASH_H */
diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/hardware/xmc4_memorymap.h
similarity index 98%
rename from arch/arm/src/xmc4/chip/xmc4_memorymap.h
rename to arch/arm/src/xmc4/hardware/xmc4_memorymap.h
index a326460cc7b..8be351d52e9 100644
--- a/arch/arm/src/xmc4/chip/xmc4_memorymap.h
+++ b/arch/arm/src/xmc4/hardware/xmc4_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/xmc4/chip/xmc4_memorymap.h
+ * arch/arm/src/xmc4/hardware/xmc4_memorymap.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -49,8 +49,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H
-#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H
+#ifndef __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_MEMORYMAP_H
+#define __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -240,4 +240,4 @@
 
 #define XMC4_PPB_BASE               0xe000e000
 
-#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H */
+#endif /* __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_MEMORYMAP_H */
diff --git a/arch/arm/src/xmc4/chip/xmc4_pinmux.h b/arch/arm/src/xmc4/hardware/xmc4_pinmux.h
similarity index 99%
rename from arch/arm/src/xmc4/chip/xmc4_pinmux.h
rename to arch/arm/src/xmc4/hardware/xmc4_pinmux.h
index daece1f509b..1c253fad803 100644
--- a/arch/arm/src/xmc4/chip/xmc4_pinmux.h
+++ b/arch/arm/src/xmc4/hardware/xmc4_pinmux.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/xmc4/chip/xmc4_pinmux.h
+ * arch/arm/src/xmc4/hardware/xmc4_pinmux.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -35,8 +35,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PINMUX_H
-#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PINMUX_H
+#ifndef __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_PINMUX_H
+#define __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_PINMUX_H
 
 /************************************************************************************
  * Included Files
@@ -58,7 +58,7 @@
  *
  * #define GPIO_CAN_N2TXD GPIO_CAN_N2TXD_1
  *
- * The driver will then automatically configre PA11 as the CAN1 RX pin.
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
  */
 
 /* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
@@ -801,4 +801,4 @@
 #define GPIO_WWDT_SERVICEOUT_1   (GPIO_OUTPUT_ALT1 | GPIO_PORT0 | GPIO_PIN7)
 #define GPIO_WWDT_SERVICEOUT_2   (GPIO_OUTPUT_ALT1 | GPIO_PORT1 | GPIO_PIN4)
 
-#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PINMXU_H */
+#endif /* __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_PINMXU_H */
diff --git a/arch/arm/src/xmc4/chip/xmc4_ports.h b/arch/arm/src/xmc4/hardware/xmc4_ports.h
similarity index 99%
rename from arch/arm/src/xmc4/chip/xmc4_ports.h
rename to arch/arm/src/xmc4/hardware/xmc4_ports.h
index a769ddf73c9..b5f2a60c9fd 100644
--- a/arch/arm/src/xmc4/chip/xmc4_ports.h
+++ b/arch/arm/src/xmc4/hardware/xmc4_ports.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/xmc4/chip/xmc4_ports.h
+ * arch/arm/src/xmc4/hardware/xmc4_ports.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -49,8 +49,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PORTS_H
-#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PORTS_H
+#ifndef __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_PORTS_H
+#define __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_PORTS_H
 
 /************************************************************************************
  * Included Files
@@ -58,7 +58,7 @@
 
 #include 
 
-#include "chip/xmc4_memorymap.h"
+#include "hardware/xmc4_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -507,4 +507,4 @@
 #define PORT_HWSEL_HW15_MASK        (3 << PORT_HWSEL_HW15_SHIFT)
 #  define PORT_HWSEL_HW15(n)        ((uint32_t)(n) << PORT_HWSEL_HW15_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_PORTS_H */
+#endif /* __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_PORTS_H */
diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/hardware/xmc4_scu.h
similarity index 99%
rename from arch/arm/src/xmc4/chip/xmc4_scu.h
rename to arch/arm/src/xmc4/hardware/xmc4_scu.h
index afa4d0f8a7f..d3cf9399515 100644
--- a/arch/arm/src/xmc4/chip/xmc4_scu.h
+++ b/arch/arm/src/xmc4/hardware/xmc4_scu.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/xmc4/chip/xmc4_scu.h
+ * arch/arm/src/xmc4/hardware/xmc4_scu.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -49,15 +49,15 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H
-#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H
+#ifndef __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_SCU_H
+#define __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_SCU_H
 
 /************************************************************************************
  * Included Files
  ************************************************************************************/
 
 #include 
-#include "chip/xmc4_memorymap.h"
+#include "hardware/xmc4_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -1119,4 +1119,4 @@
 #  define SCU_CLKMXSTAT_SYSCLKMUX_OFI (1 << SCU_CLKMXSTAT_SYSCLKMUX_SHIFT)
 #  define SCU_CLKMXSTAT_SYSCLKMUX_PLL (2 << SCU_CLKMXSTAT_SYSCLKMUX_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */
+#endif /* __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_SCU_H */
diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/hardware/xmc4_usic.h
similarity index 99%
rename from arch/arm/src/xmc4/chip/xmc4_usic.h
rename to arch/arm/src/xmc4/hardware/xmc4_usic.h
index af43e11f900..0e25807f52d 100644
--- a/arch/arm/src/xmc4/chip/xmc4_usic.h
+++ b/arch/arm/src/xmc4/hardware/xmc4_usic.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/arm/src/xmc4/chip/xmc4_usic.h
+ * arch/arm/src/xmc4/hardware/xmc4_usic.h
  *
  *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -49,8 +49,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_USIC_H
-#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_USIC_H
+#ifndef __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_USIC_H
+#define __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_USIC_H
 
 /************************************************************************************
  * Included Files
@@ -58,7 +58,7 @@
 
 #include 
 
-#include "chip/xmc4_memorymap.h"
+#include "hardware/xmc4_memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -1098,4 +1098,4 @@
 #define USIC_IN_TDATA_SHIFT         (0)      /* Bits 0-15: Transmit Data */
 #define USIC_IN_TDATA_MASK          (0xffff << USIC_IN_TDATA_SHIFT)
 
-#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_USIC_H */
+#endif /* __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_USIC_H */
diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c
index e05998a9ff5..9aa78bd752f 100644
--- a/arch/arm/src/xmc4/xmc4_clockconfig.c
+++ b/arch/arm/src/xmc4/xmc4_clockconfig.c
@@ -56,9 +56,9 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/xmc4_scu.h"
+#include "hardware/xmc4_scu.h"
 #include "xmc4_clockconfig.h"
-#include "chip/xmc4_ports.h"
+#include "hardware/xmc4_ports.h"
 
 #include 
 
diff --git a/arch/arm/src/xmc4/xmc4_clockutils.c b/arch/arm/src/xmc4/xmc4_clockutils.c
index 2a391ca3861..9e4b3f775ae 100644
--- a/arch/arm/src/xmc4/xmc4_clockutils.c
+++ b/arch/arm/src/xmc4/xmc4_clockutils.c
@@ -56,7 +56,7 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/xmc4_scu.h"
+#include "hardware/xmc4_scu.h"
 #include "xmc4_clockconfig.h"
 
 #include 
diff --git a/arch/arm/src/xmc4/xmc4_dma.h b/arch/arm/src/xmc4/xmc4_dma.h
index 8f2edba4326..85845128143 100644
--- a/arch/arm/src/xmc4/xmc4_dma.h
+++ b/arch/arm/src/xmc4/xmc4_dma.h
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/xmc4_dma.h"
+#include "hardware/xmc4_dma.h"
 
 /****************************************************************************
  * Pre-processor Declarations
diff --git a/arch/arm/src/xmc4/xmc4_gpio.c b/arch/arm/src/xmc4/xmc4_gpio.c
index 70bc6257560..415d4da3177 100644
--- a/arch/arm/src/xmc4/xmc4_gpio.c
+++ b/arch/arm/src/xmc4/xmc4_gpio.c
@@ -49,7 +49,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/xmc4_ports.h"
+#include "hardware/xmc4_ports.h"
 #include "xmc4_gpio.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/xmc4/xmc4_gpio.h b/arch/arm/src/xmc4/xmc4_gpio.h
index ef6ad3b46df..1c97c60c38e 100644
--- a/arch/arm/src/xmc4/xmc4_gpio.h
+++ b/arch/arm/src/xmc4/xmc4_gpio.h
@@ -42,7 +42,7 @@
 #include 
 #include 
 
-#include "chip/xmc4_ports.h"
+#include "hardware/xmc4_ports.h"
 
 /****************************************************************************
  * Preprocessor Definitions
diff --git a/arch/arm/src/xmc4/xmc4_i2c.h b/arch/arm/src/xmc4/xmc4_i2c.h
index 74f8acb1684..c78bacda4af 100644
--- a/arch/arm/src/xmc4/xmc4_i2c.h
+++ b/arch/arm/src/xmc4/xmc4_i2c.h
@@ -42,7 +42,7 @@
 
 #include 
 #include 
-#include "chip/xmc4_i2c.h"
+#include "hardware/xmc4_i2c.h"
 
 /****************************************************************************
  * Public Function Prototypes
diff --git a/arch/arm/src/xmc4/xmc4_lowputc.c b/arch/arm/src/xmc4/xmc4_lowputc.c
index 5c673644632..e51cba1def9 100644
--- a/arch/arm/src/xmc4/xmc4_lowputc.c
+++ b/arch/arm/src/xmc4/xmc4_lowputc.c
@@ -50,9 +50,9 @@
 #include 
 
 #include "xmc4_config.h"
-#include "chip/xmc4_usic.h"
-#include "chip/xmc4_ports.h"
-#include "chip/xmc4_pinmux.h"
+#include "hardware/xmc4_usic.h"
+#include "hardware/xmc4_ports.h"
+#include "hardware/xmc4_pinmux.h"
 #include "xmc4_usic.h"
 #include "xmc4_gpio.h"
 #include "xmc4_lowputc.h"
diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c
index 36a23e91d76..c74d661f1f4 100644
--- a/arch/arm/src/xmc4/xmc4_serial.c
+++ b/arch/arm/src/xmc4/xmc4_serial.c
@@ -59,7 +59,7 @@
 
 #include "chip.h"
 #include "xmc4_config.h"
-#include "chip/xmc4_usic.h"
+#include "hardware/xmc4_usic.h"
 #include "xmc4_lowputc.h"
 
 /****************************************************************************
diff --git a/arch/arm/src/xmc4/xmc4_spi.c b/arch/arm/src/xmc4/xmc4_spi.c
index 1c9a0ab791a..1e84a525175 100644
--- a/arch/arm/src/xmc4/xmc4_spi.c
+++ b/arch/arm/src/xmc4/xmc4_spi.c
@@ -66,9 +66,9 @@
 #include "xmc4_gpio.h"
 #include "xmc4_spi.h"
 #include "xmc4_usic.h"
-#include "chip/xmc4_spi.h"
-#include "chip/xmc4_usic.h"
-#include "chip/xmc4_pinmux.h"
+#include "hardware/xmc4_spi.h"
+#include "hardware/xmc4_usic.h"
+#include "hardware/xmc4_pinmux.h"
 
 #if defined(CONFIG_XMC4_SPI0) || defined(CONFIG_XMC4_SPI1) || \
     defined(CONFIG_XMC4_SPI2) || defined(CONFIG_XMC4_SPI3) || \
diff --git a/arch/arm/src/xmc4/xmc4_spi.h b/arch/arm/src/xmc4/xmc4_spi.h
index 03a4efcc50d..eae9d47ad30 100644
--- a/arch/arm/src/xmc4/xmc4_spi.h
+++ b/arch/arm/src/xmc4/xmc4_spi.h
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/xmc4_usic.h"
+#include "hardware/xmc4_usic.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/arm/src/xmc4/xmc4_start.c b/arch/arm/src/xmc4/xmc4_start.c
index 3dfd9a731c6..8c1a028e84b 100644
--- a/arch/arm/src/xmc4/xmc4_start.c
+++ b/arch/arm/src/xmc4/xmc4_start.c
@@ -49,17 +49,13 @@
 #include "nvic.h"
 #include "up_arch.h"
 #include "up_internal.h"
-#include "chip/xmc4_flash.h"
+#include "hardware/xmc4_flash.h"
 
 #include "xmc4_clockconfig.h"
 #include "xmc4_lowputc.h"
 #include "xmc4_userspace.h"
 #include "xmc4_start.h"
 
-#ifdef CONFIG_ARCH_FPU
-#  include "nvic.h"
-#endif
-
 /****************************************************************************
  * Private Function prototypes
  ****************************************************************************/
diff --git a/arch/arm/src/xmc4/xmc4_usic.c b/arch/arm/src/xmc4/xmc4_usic.c
index 925c9c0f411..5327066587d 100644
--- a/arch/arm/src/xmc4/xmc4_usic.c
+++ b/arch/arm/src/xmc4/xmc4_usic.c
@@ -61,8 +61,8 @@
 #include 
 
 #include "up_arch.h"
-#include "chip/xmc4_usic.h"
-#include "chip/xmc4_scu.h"
+#include "hardware/xmc4_usic.h"
+#include "hardware/xmc4_scu.h"
 #include "xmc4_clockconfig.h"
 #include "xmc4_usic.h"
 
diff --git a/arch/avr/include/avr/irq.h b/arch/avr/include/avr/irq.h
index 4b6636d3b9c..913065b2f05 100644
--- a/arch/avr/include/avr/irq.h
+++ b/arch/avr/include/avr/irq.h
@@ -106,7 +106,6 @@
 #ifndef __ASSEMBLY__
 struct xcptcontext
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there are pending signals
    * to be processed.
    */
@@ -123,11 +122,10 @@ struct xcptcontext
 
   uint8_t saved_pc1;
   uint8_t saved_pc0;
-# if defined(REG_PC2)
+#if defined(REG_PC2)
   uint8_t saved_pc2;
-# endif
-  uint8_t saved_sreg;
 #endif
+  uint8_t saved_sreg;
 
   /* Register save area */
 
diff --git a/arch/avr/include/avr32/irq.h b/arch/avr/include/avr32/irq.h
index ee2724a5658..22066752051 100644
--- a/arch/avr/include/avr32/irq.h
+++ b/arch/avr/include/avr32/irq.h
@@ -107,7 +107,6 @@
 #ifndef __ASSEMBLY__
 struct xcptcontext
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there are pending signals
    * to be processed.
    */
@@ -124,7 +123,6 @@ struct xcptcontext
 
   uint32_t saved_pc;
   uint32_t saved_sr;
-#endif
 
   /* Register save area */
 
diff --git a/arch/avr/src/avr/up_schedulesigaction.c b/arch/avr/src/avr/up_schedulesigaction.c
index 16f7a335870..955606d7822 100644
--- a/arch/avr/src/avr/up_schedulesigaction.c
+++ b/arch/avr/src/avr/up_schedulesigaction.c
@@ -51,8 +51,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -212,5 +210,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/avr/src/avr/up_sigdeliver.c b/arch/avr/src/avr/up_sigdeliver.c
index 39cdfa5cb03..0f309cdd497 100644
--- a/arch/avr/src/avr/up_sigdeliver.c
+++ b/arch/avr/src/avr/up_sigdeliver.c
@@ -52,8 +52,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -148,5 +146,3 @@ void up_sigdeliver(void)
   board_autoled_off(LED_SIGNAL);
   up_fullcontextrestore(regs);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/avr/src/avr32/up_schedulesigaction.c b/arch/avr/src/avr32/up_schedulesigaction.c
index 4ec759448da..15ffc011888 100644
--- a/arch/avr/src/avr32/up_schedulesigaction.c
+++ b/arch/avr/src/avr32/up_schedulesigaction.c
@@ -51,8 +51,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -190,6 +188,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
-
diff --git a/arch/avr/src/avr32/up_sigdeliver.c b/arch/avr/src/avr32/up_sigdeliver.c
index 52a017a1ee3..758e0567a1c 100644
--- a/arch/avr/src/avr32/up_sigdeliver.c
+++ b/arch/avr/src/avr32/up_sigdeliver.c
@@ -52,8 +52,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -148,6 +146,3 @@ void up_sigdeliver(void)
   board_autoled_off(LED_SIGNAL);
   up_fullcontextrestore(regs);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
-
diff --git a/arch/avr/src/xmega/chip/xmegac_memorymap.h b/arch/avr/src/xmega/hardware/xmegac_memorymap.h
similarity index 96%
rename from arch/avr/src/xmega/chip/xmegac_memorymap.h
rename to arch/avr/src/xmega/hardware/xmegac_memorymap.h
index 0a015c0a5a8..5cac21bc5da 100644
--- a/arch/avr/src/xmega/chip/xmegac_memorymap.h
+++ b/arch/avr/src/xmega/hardware/xmegac_memorymap.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/avr/src/xmega/chip/xmegac_memorymap.h
+ * arch/avr/src/xmega/hardware/xmegac_memorymap.h
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_AVR_SRC_XMEGA_CHIP_XMEGAC_MEMORYMAP_H
-#define __ARCH_AVR_SRC_XMEGA_CHIP_XMEGAC_MEMORYMAP_H
+#ifndef __ARCH_AVR_SRC_XMEGA_HARDWARE_XMEGAC_MEMORYMAP_H
+#define __ARCH_AVR_SRC_XMEGA_HARDWARE_XMEGAC_MEMORYMAP_H
 
 /****************************************************************************
  * Included Files
@@ -102,4 +102,4 @@
 #define XMEGA_TCF0_BASE      0x0b00 /* Timer/Counter 0 on port F */
 #define XMEGA_USARTF0_BASE   0x0ba0 /* USART 0 on port F */
 
-#endif /* __ARCH_AVR_SRC_XMEGA_CHIP_XMEGAC_MEMORYMAP_H */
+#endif /* __ARCH_AVR_SRC_XMEGA_HARDWARE_XMEGAC_MEMORYMAP_H */
diff --git a/arch/mips/include/mips32/cp0.h b/arch/mips/include/mips32/cp0.h
index 12c02e63b22..d77e25ef6a3 100644
--- a/arch/mips/include/mips32/cp0.h
+++ b/arch/mips/include/mips32/cp0.h
@@ -417,11 +417,37 @@
 #define CP0_CONFIG2_M               (1 << 31) /* Bit 31: Config3 register is present */
 
 /* Register Number: 16 Sel: 3 Name: Config3
- * Function: Configuration register 3
+ * Function: Configuration register 3 (Section 50: "CPU for Devices with MIPS32
+ *            microAptive and M-Class Cores")
  * Compliance Level: Optional.
  */
-#define CP0_CONFIG3_TL              (1 << 0)  /* Bit 0: Trace Logic implemented */
-#define CP0_CONFIG3_SM              (1 << 1)  /* Bit 1: SmartMIPS ASE implemented */
+
+#define CP0_CONFIG3_TL              (1 << 0)  /* Bit 0:  Trace Logic implemented */
+#define CP0_CONFIG3_SM              (1 << 1)  /* Bit 1:  SmartMIPS ASE implemented */
+#define CP0_CONFIG3_CDMM            (1 << 3)  /* Bit 3:  Common Device Memory Map */
+#define CP0_CONFIG3_SP              (1 << 4)  /* Bit 4:  Small page bit */
+#define CP0_CONFIG3_VINT            (1 << 5)  /* Bit 5:  Vector interrupt bit */
+#define CP0_CONFIG3_VEIC            (1 << 6)  /* Bit 6:  External interrupt controller supported */
+#define CP0_CONFIG3_ITL             (1 << 8)  /* Bit 8:  Flowtrace Hardware bit */
+#define CP0_CONFIG3_DSPP            (1 << 10) /* Bit 10: MIPS DSP ASE Presence bit */
+#define CP0_CONFIG3_DSP2            (1 << 11) /* Bit 11: MIPS DSP ASE Revision 2 Presence bit */
+#define CP0_CONFIG3_RXI             (1 << 12) /* Bit 12: RIE and XIE Implemented in PageGrain bit */
+#define CP0_CONFIG3_ULRI            (1 << 13) /* Bit 13: UserLocal register implemented bit */
+#define CP0_CONFIG3_ISA_SHIFT       (14)      /* Bits 14-15: Indicates Instruction Set Availability */
+#define CP0_CONFIG3_ISA_MASK        (3 << CP0_CONFIG3_ISA_SHIFT)
+#  define CP0_CONFIG3_ISA_MIPS32    (0 << CP0_CONFIG3_ISA_SHIFT) /* Only MIPS32 is implemented */
+#  define CP0_CONFIG3_ISA_MICROMIPS (1 << CP0_CONFIG3_ISA_SHIFT) /* Only microMIPS is implemented */
+#  define CP0_CONFIG3_ISA_BOTHMIP32 (2 << CP0_CONFIG3_ISA_SHIFT) /* Both supported, MIPS32 on reset */
+#  define CP0_CONFIG3_ISA_BOTHUMIPS (3 << CP0_CONFIG3_ISA_SHIFT) /* Both supported, microMIPS on reset */
+#define CP0_CONFIG3_ISAONEXC        (1 << 16) /* Bit 16: ISA on Exception bit */
+#define CP0_CONFIG3_MCU             (1 << 17) /* Bit 17: MIPS MCU ASE Implemented bit */
+#define CP0_CONFIG3_MMAR_SHIFT      (18)      /* Bits 18-20: microMIPS Architecture Revision level bits */
+#define CP0_CONFIG3_MMAR_MASK       (7 << CP0_CONFIG3_MMAR_SHIFT)
+#  define CP0_CONFIG3_MMAR_REL1     (0 << CP0_CONFIG3_MMAR_SHIFT) /* Release 1 */
+#define CP0_CONFIG3_IPLW_SHIFT      (21)      /* Bits 21-22: Width of the Status IPL and Cause RIPL bits */
+#define CP0_CONFIG3_IPLW_MASK       (3 << CP0_CONFIG3_IPLW_SHIFT)
+#  define CP0_CONFIG3_IPLW_6BITS    (0 << CP0_CONFIG3_IPLW_SHIFT) /* 6 bits */
+#  define CP0_CONFIG3_IPLW_8BITS    (1 << CP0_CONFIG3_IPLW_SHIFT) /* 8 bits */
 #define CP0_CONFIG3_M               (1 << 31) /* Bit 31: Config4 register is present */
 
 /* Register Number: 16 Sel: 6-7 (Available for implementation dependent use) */
diff --git a/arch/mips/include/mips32/irq.h b/arch/mips/include/mips32/irq.h
index bb111708fa1..016c0689270 100644
--- a/arch/mips/include/mips32/irq.h
+++ b/arch/mips/include/mips32/irq.h
@@ -329,7 +329,6 @@ struct xcpt_syscall_s
 
 struct xcptcontext
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-NULL if there are pending signals
    * to be processed.
    */
@@ -348,14 +347,13 @@ struct xcptcontext
   uint32_t saved_epc;    /* Trampoline PC */
   uint32_t saved_status; /* Status with interrupts disabled. */
 
-# ifdef CONFIG_BUILD_KERNEL
+#ifdef CONFIG_BUILD_KERNEL
   /* This is the saved address to use when returning from a user-space
    * signal handler.
    */
 
   uint32_t sigreturn;
 
-# endif
 #endif
 
 #ifdef CONFIG_BUILD_KERNEL
diff --git a/arch/mips/include/pic32mx/cp0.h b/arch/mips/include/pic32mx/cp0.h
index 81e542cd07a..1007262a17c 100644
--- a/arch/mips/include/pic32mx/cp0.h
+++ b/arch/mips/include/pic32mx/cp0.h
@@ -299,10 +299,6 @@
  *   See arch/mips/include/mips32/cp0.h
  */
 
-#define CP0_CONFIG3_SP              (1 << 4)  /* Bit 4: Support page bit */
-#define CP0_CONFIG3_VINT            (1 << 5)  /* Bit 5: Vector interrupt bit */
-#define CP0_CONFIG3_VEIC            (1 << 6)  /* Bit 6: External interrupt controller supported */
-
 /* Register Number: 17-22 Reserved
  * Compliance Level: Optional.
  */
diff --git a/arch/mips/include/pic32mz/cp0.h b/arch/mips/include/pic32mz/cp0.h
index 01ebbe21118..90d0ade0853 100644
--- a/arch/mips/include/pic32mz/cp0.h
+++ b/arch/mips/include/pic32mz/cp0.h
@@ -421,10 +421,6 @@
  *   See arch/mips/include/mips32/cp0.h
  */
 
-#define CP0_CONFIG3_SP              (1 << 4)  /* Bit 4: Support page bit */
-#define CP0_CONFIG3_VINT            (1 << 5)  /* Bit 5: Vector interrupt bit */
-#define CP0_CONFIG3_VEIC            (1 << 6)  /* Bit 6: External interrupt controller supported */
-
 /* Register Number: 16 Sel: 4 Name: Config4
  * To be provided
  */
diff --git a/arch/mips/src/common/up_exit.c b/arch/mips/src/common/up_exit.c
index cce67178df3..5f7e2f3e588 100644
--- a/arch/mips/src/common/up_exit.c
+++ b/arch/mips/src/common/up_exit.c
@@ -190,10 +190,11 @@ void _exit(int status)
 
   up_fullcontextrestore(tcb->xcp.regs);
 
-  /* up_fullcontextrestore() should not return but could if the software
-   * interrupts are disabled.
+  /* up_fullcontextrestore() should not return but could if software
+   * interrupts are disabled.  NOTE:  Can't use DEBUGPANIC here because
+   * that results in a GCC compilation warning: "No return function does
+   * return"
    */
 
-  DEBUGPANIC();
+  PANIC();
 }
-
diff --git a/arch/mips/src/mips32/up_schedulesigaction.c b/arch/mips/src/mips32/up_schedulesigaction.c
index e44384c5aa5..b8bf89df3dc 100644
--- a/arch/mips/src/mips32/up_schedulesigaction.c
+++ b/arch/mips/src/mips32/up_schedulesigaction.c
@@ -51,8 +51,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -205,5 +203,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/mips/src/mips32/up_sigdeliver.c b/arch/mips/src/mips32/up_sigdeliver.c
index dd9c6297d9e..73b41664a49 100644
--- a/arch/mips/src/mips32/up_sigdeliver.c
+++ b/arch/mips/src/mips32/up_sigdeliver.c
@@ -53,8 +53,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -140,6 +138,3 @@ void up_sigdeliver(void)
 
   DEBUGPANIC();
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
-
diff --git a/arch/mips/src/mips32/up_vfork.c b/arch/mips/src/mips32/up_vfork.c
index dacad2c460d..6f1616fb9db 100644
--- a/arch/mips/src/mips32/up_vfork.c
+++ b/arch/mips/src/mips32/up_vfork.c
@@ -251,7 +251,7 @@ pid_t up_vfork(const struct vfork_s *context)
 #endif
   child->cmn.xcp.regs[REG_SP]  = newsp;        /* Stack pointer */
 #ifdef MIPS32_SAVE_GP
-  child->cmn.xcp.regs[REG_GP]  = newsp;        /* Global pointer */
+  child->cmn.xcp.regs[REG_GP]  = context->gp;  /* Global pointer */
 #endif
 
   /* And, finally, start the child task.  On a failure, nxtask_vforkstart()
diff --git a/arch/mips/src/pic32mz/chip/pic32mz-dma.h b/arch/mips/src/pic32mz/hardware/pic32mz-dma.h
similarity index 99%
rename from arch/mips/src/pic32mz/chip/pic32mz-dma.h
rename to arch/mips/src/pic32mz/hardware/pic32mz-dma.h
index cc6367b7532..76095ca8ba7 100644
--- a/arch/mips/src/pic32mz/chip/pic32mz-dma.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mz-dma.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/mips/src/pic32mz/pic32mz-dma.h
+ * arch/mips/src/pic32mz/hardware/pic32mz-dma.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_DMA_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_DMA_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_DMA_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_DMA_H
 
 /********************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/pic32mz-memorymap.h"
+#include "hardware/pic32mz-memorymap.h"
 
 #if CHIP_NDMACH > 0
 
@@ -797,4 +797,4 @@ extern "C"
 
 #endif /* __ASSEMBLY__ */
 #endif /* CHIP_NDMACH > 0 */
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_DMA_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_DMA_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mz-ethernet.h b/arch/mips/src/pic32mz/hardware/pic32mz-ethernet.h
similarity index 99%
rename from arch/mips/src/pic32mz/chip/pic32mz-ethernet.h
rename to arch/mips/src/pic32mz/hardware/pic32mz-ethernet.h
index ae0836589b7..0b497a991cb 100644
--- a/arch/mips/src/pic32mz/chip/pic32mz-ethernet.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mz-ethernet.h
@@ -1,5 +1,5 @@
 /****************************************************************************************************
- * arch/mips/src/pic32mz/chip/pic32mz-ethernet.h
+ * arch/mips/src/pic32mz/hardware/pic32mz-ethernet.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_ETHERNET_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_ETHERNET_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_ETHERNET_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_ETHERNET_H
 
 /****************************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/pic32mz-memorymap.h"
+#include "hardware/pic32mz-memorymap.h"
 
 #if CHIP_NETHERNET > 0
 
@@ -998,4 +998,4 @@ extern "C"
 
 #endif /* __ASSEMBLY__ */
 #endif /* CHIP_NETHERNET > 0 */
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_ETHERNET_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_ETHERNET_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mz-features.h b/arch/mips/src/pic32mz/hardware/pic32mz-features.h
similarity index 86%
rename from arch/mips/src/pic32mz/chip/pic32mz-features.h
rename to arch/mips/src/pic32mz/hardware/pic32mz-features.h
index 6e80282a395..96bb7d62189 100644
--- a/arch/mips/src/pic32mz/chip/pic32mz-features.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mz-features.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/mips/src/pic32mz/chip/pic32mz-features.h
+ * arch/mips/src/pic32mz/hardware/pic32mz-features.h
  *
  *   Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_FEATURES_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_FEATURES_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_FEATURES_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_FEATURES_H
 
 /************************************************************************************
  * Included Files
@@ -43,11 +43,11 @@
 #include 
 
 #if defined(CONFIG_ARCH_CHIP_PIC32MZEC)
-#  include 
+#  include "hardware/pic32mzec-features.h"
 #elif defined(CONFIG_ARCH_CHIP_PIC32MZEF)
-#  include 
+#  include "hardware/pic32mzef-features.h"
 #else
 #  error Unknown PIC32MZ family
 #endif
 
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_FEATURES_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_FEATURES_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mz-i2c.h b/arch/mips/src/pic32mz/hardware/pic32mz-i2c.h
similarity index 98%
rename from arch/mips/src/pic32mz/chip/pic32mz-i2c.h
rename to arch/mips/src/pic32mz/hardware/pic32mz-i2c.h
index ee064a466e4..d59c6c9ec2d 100644
--- a/arch/mips/src/pic32mz/chip/pic32mz-i2c.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mz-i2c.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/mips/src/pic32mz/pic32mz-i2c.h
+ * arch/mips/src/pic32mz/hardware/pic32mz-i2c.h
  *
  *   Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_I2C_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_I2C_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_I2C_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_I2C_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/pic32mz-memorymap.h"
+#include "hardware/pic32mz-memorymap.h"
 
 #if CHIP_NI2C > 0
 
@@ -371,4 +371,4 @@ extern "C"
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_I2C_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_I2C_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mz-int.h b/arch/mips/src/pic32mz/hardware/pic32mz-int.h
similarity index 99%
rename from arch/mips/src/pic32mz/chip/pic32mz-int.h
rename to arch/mips/src/pic32mz/hardware/pic32mz-int.h
index 9c07b5f6baa..51e655e9834 100644
--- a/arch/mips/src/pic32mz/chip/pic32mz-int.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mz-int.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/mips/src/pic32mz/pic32mz-int.h
+ * arch/mips/src/pic32mz/hardware/pic32mz-int.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_INT_H
-#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_INT_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_INT_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_INT_H
 
 /****************************************************************************
  * Included Files
@@ -1260,4 +1260,4 @@ extern "C"
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_INT_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_INT_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mz-ioport.h b/arch/mips/src/pic32mz/hardware/pic32mz-ioport.h
similarity index 99%
rename from arch/mips/src/pic32mz/chip/pic32mz-ioport.h
rename to arch/mips/src/pic32mz/hardware/pic32mz-ioport.h
index 8e590a3c806..60adef40fa4 100644
--- a/arch/mips/src/pic32mz/chip/pic32mz-ioport.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mz-ioport.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/mips/src/pic32mz/pic32mz-ioport.h
+ * arch/mips/src/pic32mz/hardware/pic32mz-ioport.h
  *
  *   Copyright (C) 2015, 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_IOPORT_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_IOPORT_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_IOPORT_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_IOPORT_H
 
 /********************************************************************************************
  * Included Files
@@ -906,4 +906,4 @@ extern "C"
 
 #endif /* __ASSEMBLY__ */
 #endif /* CHIP_NPORTS > 0 */
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_IOPORT_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_IOPORT_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mz-memorymap.h b/arch/mips/src/pic32mz/hardware/pic32mz-memorymap.h
similarity index 86%
rename from arch/mips/src/pic32mz/chip/pic32mz-memorymap.h
rename to arch/mips/src/pic32mz/hardware/pic32mz-memorymap.h
index cb50d344347..6ccfd667222 100644
--- a/arch/mips/src/pic32mz/chip/pic32mz-memorymap.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mz-memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/mips/src/pic32mz/chip/pic32mz-memorymap.h
+ * arch/mips/src/pic32mz/hardware/pic32mz-memorymap.h
  *
  *   Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_MEMORYMAP_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_MEMORYMAP_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_MEMORYMAP_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -43,11 +43,11 @@
 #include 
 
 #if defined(CONFIG_ARCH_CHIP_PIC32MZEC)
-#  include "chip/pic32mzec-memorymap.h"
+#  include "hardware/pic32mzec-memorymap.h"
 #elif defined(CONFIG_ARCH_CHIP_PIC32MZEF)
-#  include "chip/pic32mzef-memorymap.h"
+#  include "hardware/pic32mzef-memorymap.h"
 #else
 #  error Unknown PIC32MZ family
 #endif
 
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_MEMORYMAP_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_MEMORYMAP_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mz-osc.h b/arch/mips/src/pic32mz/hardware/pic32mz-osc.h
similarity index 98%
rename from arch/mips/src/pic32mz/chip/pic32mz-osc.h
rename to arch/mips/src/pic32mz/hardware/pic32mz-osc.h
index 7e5668d90f4..bffe84c93e3 100644
--- a/arch/mips/src/pic32mz/chip/pic32mz-osc.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mz-osc.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/mips/src/pic32mz/chip/pic32mz-osc.h
+ * arch/mips/src/pic32mz/hardware/pic32mz-osc.h
  *
  *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_OSC_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_OSC_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_OSC_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_OSC_H
 
 /****************************************************************************
  * Included Files
@@ -231,4 +231,4 @@ extern "C"
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_OSC_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_OSC_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mz-pps.h b/arch/mips/src/pic32mz/hardware/pic32mz-pps.h
similarity index 94%
rename from arch/mips/src/pic32mz/chip/pic32mz-pps.h
rename to arch/mips/src/pic32mz/hardware/pic32mz-pps.h
index c59ebab6df1..d20815ba1be 100644
--- a/arch/mips/src/pic32mz/chip/pic32mz-pps.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mz-pps.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/mips/src/pic32mz/pic32mz-pps.h
+ * arch/mips/src/pic32mz/hardware/pic32mz-pps.h
  *
  *   Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_PPS_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_PPS_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_PPS_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_PPS_H
 
 /********************************************************************************************
  * Included Files
@@ -50,9 +50,9 @@
 /* Depends on the peripherals supported by the particular device */
 
 #if defined(CONFIG_ARCH_CHIP_PIC32MZEC)
-#  include "chip/pic32mzec-pps.h"
+#  include "hardware/pic32mzec-pps.h"
 #elif defined(CONFIG_ARCH_CHIP_PIC32MZEF)
-#  include "chip/pic32mzef-pps.h"
+#  include "hardware/pic32mzef-pps.h"
 #else
 #  error Unknown PIC32MZ family
 #endif
@@ -114,4 +114,4 @@ extern "C"
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_PPS_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_PPS_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mz-prefetch.h b/arch/mips/src/pic32mz/hardware/pic32mz-prefetch.h
similarity index 94%
rename from arch/mips/src/pic32mz/chip/pic32mz-prefetch.h
rename to arch/mips/src/pic32mz/hardware/pic32mz-prefetch.h
index 1279451c7aa..5d3f380b0c0 100644
--- a/arch/mips/src/pic32mz/chip/pic32mz-prefetch.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mz-prefetch.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/mips/src/pic32mz/chip/pic32mz-prefetch.h
+ * arch/mips/src/pic32mz/hardware/pic32mz-prefetch.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_PREFETCH_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_PREFETCH_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_PREFETCH_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_PREFETCH_H
 
 /********************************************************************************************
  * Included Files
@@ -79,4 +79,4 @@
 #define PRESTAT_PFMSEC          (1 << 26) /* Bit 26: Flash Single-bit Error Corrected Status */
 #define PRESTAT_PFMDED          (1 << 27) /* Bit 27: Flash Double-bit Error Detected Status */
 
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_PREFETCH_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_PREFETCH_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mz-spi.h b/arch/mips/src/pic32mz/hardware/pic32mz-spi.h
similarity index 98%
rename from arch/mips/src/pic32mz/chip/pic32mz-spi.h
rename to arch/mips/src/pic32mz/hardware/pic32mz-spi.h
index c2359c0ae44..6939daba245 100644
--- a/arch/mips/src/pic32mz/chip/pic32mz-spi.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mz-spi.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/mips/src/pic32mz/chip/pic32mz-spi.h
+ * arch/mips/src/pic32mz/hardware/pic32mz-spi.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_SPI_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_SPI_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_SPI_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_SPI_H
 
 /****************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/pic32mz-memorymap.h"
+#include "hardware/pic32mz-memorymap.h"
 
 #if CHIP_NSPI > 0
 
@@ -329,4 +329,4 @@ extern "C"
 
 #endif /* __ASSEMBLY__ */
 #endif /* CHIP_NSPI > 0 */
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_SPI_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_SPI_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mz-timer.h b/arch/mips/src/pic32mz/hardware/pic32mz-timer.h
similarity index 98%
rename from arch/mips/src/pic32mz/chip/pic32mz-timer.h
rename to arch/mips/src/pic32mz/hardware/pic32mz-timer.h
index da54777ba9b..9350d0c3b6d 100644
--- a/arch/mips/src/pic32mz/chip/pic32mz-timer.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mz-timer.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/mips/src/pic32mz/pic32mz-timer.h
+ * arch/mips/src/pic32mz/hardware/pic32mz-timer.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_TIMER_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_TIMER_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_TIMER_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_TIMER_H
 
 /************************************************************************************
  * Included Files
@@ -308,4 +308,4 @@ extern "C"
 
 #endif /* __ASSEMBLY__ */
 #endif /* CHIP_NTIMERS > 0 */
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZ_TIMER_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZ_TIMER_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mz-uart.h b/arch/mips/src/pic32mz/hardware/pic32mz-uart.h
similarity index 98%
rename from arch/mips/src/pic32mz/chip/pic32mz-uart.h
rename to arch/mips/src/pic32mz/hardware/pic32mz-uart.h
index 37affc2b89c..7f035e5668e 100644
--- a/arch/mips/src/pic32mz/chip/pic32mz-uart.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mz-uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/mips/src/pic42mz/pic42mz-uart.h
+ * arch/mips/src/pic32mz/hardware/pic32mz-uart.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_CHIP_UART_H
-#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_CHIP_UART_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_UART_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_UART_H
 
 /************************************************************************************
  * Included Files
@@ -43,7 +43,7 @@
 #include 
 
 #include 
-#include "chip/pic32mz-memorymap.h"
+#include "hardware/pic32mz-memorymap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -290,4 +290,4 @@ extern "C"
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_CHIP_UART_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_UART_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mzec-features.h b/arch/mips/src/pic32mz/hardware/pic32mzec-features.h
similarity index 99%
rename from arch/mips/src/pic32mz/chip/pic32mzec-features.h
rename to arch/mips/src/pic32mz/hardware/pic32mzec-features.h
index 270f58d1768..a4b22dca37c 100644
--- a/arch/mips/src/pic32mz/chip/pic32mzec-features.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mzec-features.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/mips/src/pic32mz/chip/pic32mzec-features.h
+ * arch/mips/src/pic32mz/hardware/pic32mzec-features.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_FEATURES_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_FEATURES_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_FEATURES_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_FEATURES_H
 
 /************************************************************************************
  * Included Files
@@ -511,4 +511,4 @@
 /* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASE) */
 /* Device serial number 0-1: 32-bit serial number data */
 
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_FEATURES_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_FEATURES_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h b/arch/mips/src/pic32mz/hardware/pic32mzec-memorymap.h
similarity index 97%
rename from arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h
rename to arch/mips/src/pic32mz/hardware/pic32mzec-memorymap.h
index 54d95e49ba7..a72ef1a97ff 100644
--- a/arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mzec-memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/mips/src/pic32mz/chip/pic32mzec-memorymap.h
+ * arch/mips/src/pic32mz/hardware/pic32mzec-memorymap.h
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_MEMORYMAP_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_MEMORYMAP_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_MEMORYMAP_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -146,4 +146,4 @@
 
 #define PIC32MZ_SYSBUS_K1BASE       (PIC32MZ_SFR_K1BASE + 0x000f0000) /* System Bus */
 
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_MEMORYMAP_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_MEMORYMAP_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mzec-pps.h b/arch/mips/src/pic32mz/hardware/pic32mzec-pps.h
similarity index 99%
rename from arch/mips/src/pic32mz/chip/pic32mzec-pps.h
rename to arch/mips/src/pic32mz/hardware/pic32mzec-pps.h
index d8b3a12eed8..6c44ed9af1f 100644
--- a/arch/mips/src/pic32mz/chip/pic32mzec-pps.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mzec-pps.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/mips/src/pic32mz/pic32mzec-pps.h
+ * arch/mips/src/pic32mz/hardware/pic32mzec-pps.h
  *
  *   Copyright (C) 2015, 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_PPS_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_PPS_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_PPS_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_PPS_H
 
 /********************************************************************************************
  * Included Files
@@ -1715,4 +1715,4 @@
 #define U6TX_RPG6R                       4, PIC32MZ_RPG6R
 #define U6TX_RPG9R                       4, PIC32MZ_RPG9R
 
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEC_PPS_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEC_PPS_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mzef-features.h b/arch/mips/src/pic32mz/hardware/pic32mzef-features.h
similarity index 99%
rename from arch/mips/src/pic32mz/chip/pic32mzef-features.h
rename to arch/mips/src/pic32mz/hardware/pic32mzef-features.h
index 9a042287bf0..5d7fc8d524c 100644
--- a/arch/mips/src/pic32mz/chip/pic32mzef-features.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mzef-features.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/mips/src/pic32mz/chip/pic32mzef-features.h
+ * arch/mips/src/pic32mz/hardware/pic32mzef-features.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_FEATURES_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_FEATURES_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_FEATURES_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_FEATURES_H
 
 /************************************************************************************
  * Included Files
@@ -537,4 +537,4 @@
 /* Device Serial Number (Boot Flash PIC32MZ_DEVSN_K1BASE) */
 /* Device serial number 0-1: 32-bit serial number data */
 
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_FEATURES_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_FEATURES_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mzef-memorymap.h b/arch/mips/src/pic32mz/hardware/pic32mzef-memorymap.h
similarity index 97%
rename from arch/mips/src/pic32mz/chip/pic32mzef-memorymap.h
rename to arch/mips/src/pic32mz/hardware/pic32mzef-memorymap.h
index d54e7296bd5..0c407791e4c 100644
--- a/arch/mips/src/pic32mz/chip/pic32mzef-memorymap.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mzef-memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/mips/src/pic32mz/chip/pic32mzef-memorymap.h
+ * arch/mips/src/pic32mz/hardware/pic32mzef-memorymap.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_MEMORYMAP_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_MEMORYMAP_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_MEMORYMAP_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_MEMORYMAP_H
 
 /************************************************************************************
  * Included Files
@@ -144,4 +144,4 @@
 
 #define PIC32MZ_SYSBUS_K1BASE       (PIC32MZ_SFR_K1BASE + 0x000f0000) /* System Bus */
 
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_MEMORYMAP_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_MEMORYMAP_H */
diff --git a/arch/mips/src/pic32mz/chip/pic32mzef-pps.h b/arch/mips/src/pic32mz/hardware/pic32mzef-pps.h
similarity index 99%
rename from arch/mips/src/pic32mz/chip/pic32mzef-pps.h
rename to arch/mips/src/pic32mz/hardware/pic32mzef-pps.h
index 89bc403f2bc..d26e24c844e 100644
--- a/arch/mips/src/pic32mz/chip/pic32mzef-pps.h
+++ b/arch/mips/src/pic32mz/hardware/pic32mzef-pps.h
@@ -1,5 +1,5 @@
 /********************************************************************************************
- * arch/mips/src/pic32mz/pic32mzef-pps.h
+ * arch/mips/src/pic32mz/hardware/pic32mzef-pps.h
  *
  *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -33,8 +33,8 @@
  *
  ********************************************************************************************/
 
-#ifndef __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_PPS_H
-#define __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_PPS_H
+#ifndef __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_PPS_H
+#define __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_PPS_H
 
 /********************************************************************************************
  * Included Files
@@ -1716,4 +1716,4 @@
 #define U6TX_RPG6R                       4, PIC32MZ_RPG6R
 #define U6TX_RPG9R                       4, PIC32MZ_RPG9R
 
-#endif /* __ARCH_MIPS_SRC_PIC32MZ_CHIP_PIC32MZEF_PPS_H */
+#endif /* __ARCH_MIPS_SRC_PIC32MZ_HARDWARE_PIC32MZEF_PPS_H */
diff --git a/arch/mips/src/pic32mz/pic32mz-decodeirq.c b/arch/mips/src/pic32mz/pic32mz-decodeirq.c
index 14b980c3f56..a9e249be19e 100644
--- a/arch/mips/src/pic32mz/pic32mz-decodeirq.c
+++ b/arch/mips/src/pic32mz/pic32mz-decodeirq.c
@@ -52,7 +52,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/pic32mz-int.h"
+#include "hardware/pic32mz-int.h"
 
 #include "group/group.h"
 
diff --git a/arch/mips/src/pic32mz/pic32mz-ethernet.c b/arch/mips/src/pic32mz/pic32mz-ethernet.c
index 866bf651e95..b9cecf62181 100644
--- a/arch/mips/src/pic32mz/pic32mz-ethernet.c
+++ b/arch/mips/src/pic32mz/pic32mz-ethernet.c
@@ -72,7 +72,7 @@
 #include "up_internal.h"
 
 #include "pic32mz-config.h"
-#include "chip/pic32mz-ethernet.h"
+#include "hardware/pic32mz-ethernet.h"
 
 /* Does this chip have and Ethernet controller? */
 
diff --git a/arch/mips/src/pic32mz/pic32mz-exception.c b/arch/mips/src/pic32mz/pic32mz-exception.c
index 256010e910a..0c19918cf39 100644
--- a/arch/mips/src/pic32mz/pic32mz-exception.c
+++ b/arch/mips/src/pic32mz/pic32mz-exception.c
@@ -53,7 +53,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/pic32mz-int.h"
+#include "hardware/pic32mz-int.h"
 
 /****************************************************************************
  * Public Functions
diff --git a/arch/mips/src/pic32mz/pic32mz-gpio.c b/arch/mips/src/pic32mz/pic32mz-gpio.c
index 466754fde23..7b12f0bcdd6 100644
--- a/arch/mips/src/pic32mz/pic32mz-gpio.c
+++ b/arch/mips/src/pic32mz/pic32mz-gpio.c
@@ -49,7 +49,7 @@
 
 #include "up_arch.h"
 
-#include "chip/pic32mz-ioport.h"
+#include "hardware/pic32mz-ioport.h"
 #include "pic32mz-gpio.h"
 
 #if CHIP_NPORTS > 0
diff --git a/arch/mips/src/pic32mz/pic32mz-gpioirq.c b/arch/mips/src/pic32mz/pic32mz-gpioirq.c
index 44911fd40b7..9d5b5f3ad23 100644
--- a/arch/mips/src/pic32mz/pic32mz-gpioirq.c
+++ b/arch/mips/src/pic32mz/pic32mz-gpioirq.c
@@ -49,7 +49,7 @@
 
 #include "up_arch.h"
 #include "up_internal.h"
-#include "chip/pic32mz-ioport.h"
+#include "hardware/pic32mz-ioport.h"
 #include "pic32mz-gpio.h"
 
 #ifdef CONFIG_PIC32MZ_GPIOIRQ
diff --git a/arch/mips/src/pic32mz/pic32mz-head.S b/arch/mips/src/pic32mz/pic32mz-head.S
index 07cff97933c..bc631db9f70 100644
--- a/arch/mips/src/pic32mz/pic32mz-head.S
+++ b/arch/mips/src/pic32mz/pic32mz-head.S
@@ -43,7 +43,7 @@
 #include 
 
 #include "pic32mz-config.h"
-#include "chip/pic32mz-features.h"
+#include "hardware/pic32mz-features.h"
 #include "pic32mz-excptmacros.h"
 
 /****************************************************************************
@@ -544,9 +544,9 @@ __start:
 	 * config3ISAOnExc now that exception vectors have been [re]located.
 	 */
 
-	mfc0	t0, MICROAPTIV_CP0_CONFIG3		/* Load CONFIG3 register */
+	mfc0	t0, MIPS32_CP0_CONFIG3		/* Load CONFIG3 register */
 	or		t0, t0, CP0_CONFIG3_ISAONEXC	/* Specify microMIPS mode on exceptions */
-	mtc0	t0, MICROAPTIV_CP0_CONFIG3		/* Update CONFIG3 register */
+	mtc0	t0, MIPS32_CP0_CONFIG3		/* Update CONFIG3 register */
 #endif
 
 	/* Start NuttX. We do this via a thunk in the text section so that
diff --git a/arch/mips/src/pic32mz/pic32mz-i2c.c b/arch/mips/src/pic32mz/pic32mz-i2c.c
index a03816053a5..195c840c38d 100644
--- a/arch/mips/src/pic32mz/pic32mz-i2c.c
+++ b/arch/mips/src/pic32mz/pic32mz-i2c.c
@@ -59,7 +59,7 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/pic32mz-i2c.h"
+#include "hardware/pic32mz-i2c.h"
 #include "pic32mz-i2c.h"
 
 /* At least one I2C peripheral must be enabled */
diff --git a/arch/mips/src/pic32mz/pic32mz-irq.c b/arch/mips/src/pic32mz/pic32mz-irq.c
index bb1fda5108e..9cceb5eac6f 100644
--- a/arch/mips/src/pic32mz/pic32mz-irq.c
+++ b/arch/mips/src/pic32mz/pic32mz-irq.c
@@ -52,7 +52,7 @@
 #include "up_arch.h"
 #include "up_internal.h"
 
-#include "chip/pic32mz-int.h"
+#include "hardware/pic32mz-int.h"
 #include "pic32mz-gpio.h"
 
 /****************************************************************************
diff --git a/arch/mips/src/pic32mz/pic32mz-lowconsole.c b/arch/mips/src/pic32mz/pic32mz-lowconsole.c
index d16e81631ab..ed582864c7a 100644
--- a/arch/mips/src/pic32mz/pic32mz-lowconsole.c
+++ b/arch/mips/src/pic32mz/pic32mz-lowconsole.c
@@ -48,8 +48,8 @@
 #include "up_internal.h"
 
 #include "pic32mz-config.h"
-#include "chip/pic32mz-uart.h"
-#include "chip/pic32mz-pps.h"
+#include "hardware/pic32mz-uart.h"
+#include "hardware/pic32mz-pps.h"
 
 #include 
 
diff --git a/arch/mips/src/pic32mz/pic32mz-lowinit.c b/arch/mips/src/pic32mz/pic32mz-lowinit.c
index 50306ca40c3..b74ce89fa3d 100644
--- a/arch/mips/src/pic32mz/pic32mz-lowinit.c
+++ b/arch/mips/src/pic32mz/pic32mz-lowinit.c
@@ -47,9 +47,9 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/pic32mz-features.h"
-#include "chip/pic32mz-prefetch.h"
-#include "chip/pic32mz-osc.h"
+#include "hardware/pic32mz-features.h"
+#include "hardware/pic32mz-prefetch.h"
+#include "hardware/pic32mz-osc.h"
 
 #include "pic32mz-config.h"
 #include "pic32mz-lowconsole.h"
diff --git a/arch/mips/src/pic32mz/pic32mz-serial.c b/arch/mips/src/pic32mz/pic32mz-serial.c
index e930232beaa..6728a3032b4 100644
--- a/arch/mips/src/pic32mz/pic32mz-serial.c
+++ b/arch/mips/src/pic32mz/pic32mz-serial.c
@@ -62,7 +62,7 @@
 #include "up_internal.h"
 
 #include "pic32mz-config.h"
-#include "chip/pic32mz-uart.h"
+#include "hardware/pic32mz-uart.h"
 #include "pic32mz-lowconsole.h"
 
 /****************************************************************************
diff --git a/arch/mips/src/pic32mz/pic32mz-spi.c b/arch/mips/src/pic32mz/pic32mz-spi.c
index ea2f906cb91..58ca9f79fdb 100644
--- a/arch/mips/src/pic32mz/pic32mz-spi.c
+++ b/arch/mips/src/pic32mz/pic32mz-spi.c
@@ -54,8 +54,8 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/pic32mz-spi.h"
-#include "chip/pic32mz-pps.h"
+#include "hardware/pic32mz-spi.h"
+#include "hardware/pic32mz-pps.h"
 #include "pic32mz-spi.h"
 
 #ifdef CONFIG_PIC32MZ_SPI
diff --git a/arch/mips/src/pic32mz/pic32mz-timer.c b/arch/mips/src/pic32mz/pic32mz-timer.c
index 8c814c2e97b..6ac854538cd 100644
--- a/arch/mips/src/pic32mz/pic32mz-timer.c
+++ b/arch/mips/src/pic32mz/pic32mz-timer.c
@@ -59,7 +59,7 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#include "chip/pic32mz-timer.h"
+#include "hardware/pic32mz-timer.h"
 #include "pic32mz-timer.h"
 #include "pic32mz-gpio.h"
 
diff --git a/arch/mips/src/pic32mz/pic32mz-timerisr.c b/arch/mips/src/pic32mz/pic32mz-timerisr.c
index 78e53ea89b8..6d93837453c 100644
--- a/arch/mips/src/pic32mz/pic32mz-timerisr.c
+++ b/arch/mips/src/pic32mz/pic32mz-timerisr.c
@@ -51,8 +51,8 @@
 #include "up_arch.h"
 
 #include "pic32mz-config.h"
-#include "chip/pic32mz-timer.h"
-#include "chip/pic32mz-int.h"
+#include "hardware/pic32mz-timer.h"
+#include "hardware/pic32mz-int.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/misoc/include/lm32/irq.h b/arch/misoc/include/lm32/irq.h
index 700e70f9251..b6d4b3137e9 100644
--- a/arch/misoc/include/lm32/irq.h
+++ b/arch/misoc/include/lm32/irq.h
@@ -195,7 +195,6 @@
 
 struct xcptcontext
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-NULL if there are pending signals
    * to be processed.
    */
@@ -214,14 +213,12 @@ struct xcptcontext
   uint32_t saved_epc;     /* Trampoline PC */
   uint32_t saved_int_ctx; /* Interrupt context with interrupts disabled. */
 
-# ifdef CONFIG_BUILD_KERNEL
+#ifdef CONFIG_BUILD_KERNEL
   /* This is the saved address to use when returning from a user-space
    * signal handler.
    */
 
   uint32_t sigreturn;
-
-# endif
 #endif
 
 #ifdef CONFIG_BUILD_KERNEL
diff --git a/arch/misoc/include/minerva/irq.h b/arch/misoc/include/minerva/irq.h
index 32a720bfe0f..2be04919175 100644
--- a/arch/misoc/include/minerva/irq.h
+++ b/arch/misoc/include/minerva/irq.h
@@ -276,7 +276,6 @@ struct xcpt_syscall_s
 
 struct xcptcontext
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-NULL if there are pending signals
    * to be processed.
    */
@@ -296,8 +295,6 @@ struct xcptcontext
    */
 
   uint32_t sigreturn;
-
-#endif
 #endif
 
 #ifdef CONFIG_BUILD_KERNEL
diff --git a/arch/misoc/src/lm32/lm32_schedulesigaction.c b/arch/misoc/src/lm32/lm32_schedulesigaction.c
index d72e68cf64c..03470f2caa9 100644
--- a/arch/misoc/src/lm32/lm32_schedulesigaction.c
+++ b/arch/misoc/src/lm32/lm32_schedulesigaction.c
@@ -55,8 +55,6 @@
 #include "sched/sched.h"
 #include "lm32.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -202,5 +200,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/misoc/src/lm32/lm32_sigdeliver.c b/arch/misoc/src/lm32/lm32_sigdeliver.c
index f1925624c56..5b51edd8fe6 100644
--- a/arch/misoc/src/lm32/lm32_sigdeliver.c
+++ b/arch/misoc/src/lm32/lm32_sigdeliver.c
@@ -52,8 +52,6 @@
 #include "sched/sched.h"
 #include "lm32.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -139,5 +137,3 @@ void lm32_sigdeliver(void)
 
   DEBUGPANIC();
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/misoc/src/minerva/minerva_schedulesigaction.c b/arch/misoc/src/minerva/minerva_schedulesigaction.c
index 2f1a11205a4..f9a7cfc4e14 100644
--- a/arch/misoc/src/minerva/minerva_schedulesigaction.c
+++ b/arch/misoc/src/minerva/minerva_schedulesigaction.c
@@ -56,8 +56,6 @@
 #include "sched/sched.h"
 #include "minerva.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -198,5 +196,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif  /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/misoc/src/minerva/minerva_sigdeliver.c b/arch/misoc/src/minerva/minerva_sigdeliver.c
index b3d7816107d..6f342a12290 100644
--- a/arch/misoc/src/minerva/minerva_sigdeliver.c
+++ b/arch/misoc/src/minerva/minerva_sigdeliver.c
@@ -53,8 +53,6 @@
 #include "sched/sched.h"
 #include "minerva.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -135,5 +133,3 @@ void minerva_sigdeliver(void)
 
   DEBUGPANIC();
 }
-
-#endif  /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/or1k/include/mor1kx/irq.h b/arch/or1k/include/mor1kx/irq.h
index 6bebbc5f9e0..a27ac858921 100644
--- a/arch/or1k/include/mor1kx/irq.h
+++ b/arch/or1k/include/mor1kx/irq.h
@@ -171,7 +171,6 @@ struct xcptcontext
 
   uint32_t regs[XCPTCONTEXT_REGS];
 
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there
    * are pending signals to be processed.
    */
@@ -189,8 +188,6 @@ struct xcptcontext
 
   uint32_t saved_pc;
   uint32_t saved_flags;
-#endif
-
 };
 #endif
 
diff --git a/arch/or1k/src/common/up_schedulesigaction.c b/arch/or1k/src/common/up_schedulesigaction.c
index 2ffb71762cd..10278e89049 100644
--- a/arch/or1k/src/common/up_schedulesigaction.c
+++ b/arch/or1k/src/common/up_schedulesigaction.c
@@ -50,8 +50,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -188,5 +186,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/or1k/src/mor1kx/Make.defs b/arch/or1k/src/mor1kx/Make.defs
index 7f139671b45..d21276c0e4f 100644
--- a/arch/or1k/src/mor1kx/Make.defs
+++ b/arch/or1k/src/mor1kx/Make.defs
@@ -66,11 +66,9 @@ CMN_CSRCS  = up_initialize.c \
 
 ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CMN_CSRCS += up_task_start.c up_pthread_start.c
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
 #CMN_CSRCS += up_signal_dispatch.c
 #CMN_UASRCS += up_signal_handler.S
 endif
-endif
 
 ifeq ($(CONFIG_STACK_COLORATION),y)
 #CMN_CSRCS += up_checkstack.c
diff --git a/arch/or1k/src/mor1kx/chip/irq.h b/arch/or1k/src/mor1kx/hardware/irq.h
similarity index 100%
rename from arch/or1k/src/mor1kx/chip/irq.h
rename to arch/or1k/src/mor1kx/hardware/irq.h
diff --git a/arch/renesas/include/m16c/irq.h b/arch/renesas/include/m16c/irq.h
index 64de4752080..9fbb16927df 100644
--- a/arch/renesas/include/m16c/irq.h
+++ b/arch/renesas/include/m16c/irq.h
@@ -242,7 +242,6 @@
 #ifndef __ASSEMBLY__
 struct xcptcontext
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there are pending signals
    * to be processed.
    */
@@ -259,7 +258,6 @@ struct xcptcontext
 
   uint8_t saved_pc[2];
   uint8_t saved_flg;
-#endif
 
   /* Register save area */
 
diff --git a/arch/renesas/include/sh1/irq.h b/arch/renesas/include/sh1/irq.h
index d8be9c52c10..693a6e939dc 100644
--- a/arch/renesas/include/sh1/irq.h
+++ b/arch/renesas/include/sh1/irq.h
@@ -459,7 +459,6 @@
 #ifndef __ASSEMBLY__
 struct xcptcontext
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there are pending signals
    * to be processed.
    */
@@ -476,7 +475,6 @@ struct xcptcontext
 
   uint32_t saved_pc;
   uint32_t saved_sr;
-#endif
 
   /* Register save area */
 
diff --git a/arch/renesas/src/m16c/Make.defs b/arch/renesas/src/m16c/Make.defs
index d44d9b2f097..1c0bb8d57f4 100644
--- a/arch/renesas/src/m16c/Make.defs
+++ b/arch/renesas/src/m16c/Make.defs
@@ -44,12 +44,9 @@ CMN_CSRCS += up_stackframe.c up_udelay.c up_unblocktask.c up_usestack.c
 
 CHIP_ASRCS  = m16c_vectors.S
 CHIP_CSRCS  = m16c_initialstate.c m16c_copystate.c m16c_lowputc.c m16c_irq.c
+CHIP_CSRCS += m16c_schedulesigaction.c m16c_sigdeliver.c
 CHIP_CSRCS += m16c_serial.c m16c_dumpstate.c
 
 ifneq ($(CONFIG_SCHED_TICKLESS),y)
 CHIP_CSRCS += m16c_timerisr.c
 endif
-
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
-CHIP_CSRCS += m16c_schedulesigaction.c m16c_sigdeliver.c
-endif
diff --git a/arch/renesas/src/m16c/m16c_schedulesigaction.c b/arch/renesas/src/m16c/m16c_schedulesigaction.c
index 69913944663..eab47c609f5 100644
--- a/arch/renesas/src/m16c/m16c_schedulesigaction.c
+++ b/arch/renesas/src/m16c/m16c_schedulesigaction.c
@@ -50,8 +50,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Funictions
  ****************************************************************************/
@@ -186,5 +184,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/renesas/src/m16c/m16c_sigdeliver.c b/arch/renesas/src/m16c/m16c_sigdeliver.c
index 512aebca354..577f6b6a1db 100644
--- a/arch/renesas/src/m16c/m16c_sigdeliver.c
+++ b/arch/renesas/src/m16c/m16c_sigdeliver.c
@@ -52,8 +52,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -70,7 +68,6 @@
 
 void up_sigdeliver(void)
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   struct tcb_s *rtcb = this_task();
   uint8_t regs[XCPTCONTEXT_SIZE];
 
@@ -133,8 +130,4 @@ void up_sigdeliver(void)
 
   board_autoled_off(LED_SIGNAL);
   up_fullcontextrestore(regs);
-#endif
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
-
diff --git a/arch/renesas/src/sh1/Make.defs b/arch/renesas/src/sh1/Make.defs
index adbfd361986..ee1e291aca7 100644
--- a/arch/renesas/src/sh1/Make.defs
+++ b/arch/renesas/src/sh1/Make.defs
@@ -41,6 +41,7 @@ CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c
 CMN_CSRCS += up_initialstate.c up_interruptcontext.c up_lowputs.c
 CMN_CSRCS += up_mdelay.c up_puts.c up_releasepending.c up_releasestack.c
 CMN_CSRCS += up_reprioritizertr.c up_stackframe.c up_udelay.c
+CMN_CSRCS += sh1_schedulesigaction.c sh1_sigdeliver.c
 CMN_CSRCS += up_unblocktask.c up_usestack.c
 
 CHIP_ASRCS  = sh1_vector.S sh1_saveusercontext.S
@@ -51,10 +52,6 @@ ifneq ($(CONFIG_SCHED_TICKLESS),y)
 CHIP_CSRCS += sh1_timerisr.c
 endif
 
-ifneq ($(CONFIG_DISABLE_SIGNALS),y)
-CMN_CSRCS += sh1_schedulesigaction.c sh1_sigdeliver.c
-endif
-
 ifeq ($(CONFIG_USBDEV),y)
 CHIP_CSRCS +=
 endif
diff --git a/arch/renesas/src/sh1/sh1_schedulesigaction.c b/arch/renesas/src/sh1/sh1_schedulesigaction.c
index 503272b5a95..4f2b4c0333e 100644
--- a/arch/renesas/src/sh1/sh1_schedulesigaction.c
+++ b/arch/renesas/src/sh1/sh1_schedulesigaction.c
@@ -50,8 +50,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Funictions
  ****************************************************************************/
@@ -182,5 +180,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/renesas/src/sh1/sh1_sigdeliver.c b/arch/renesas/src/sh1/sh1_sigdeliver.c
index aac0cf92bbb..a17e2d661d7 100644
--- a/arch/renesas/src/sh1/sh1_sigdeliver.c
+++ b/arch/renesas/src/sh1/sh1_sigdeliver.c
@@ -52,8 +52,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -70,7 +68,6 @@
 
 void up_sigdeliver(void)
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   struct tcb_s  *rtcb = this_task();
   uint32_t regs[XCPTCONTEXT_REGS];
 
@@ -130,8 +127,4 @@ void up_sigdeliver(void)
 
   board_autoled_off(LED_SIGNAL);
   up_fullcontextrestore(regs);
-#endif
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
-
diff --git a/arch/risc-v/include/rv32im/irq.h b/arch/risc-v/include/rv32im/irq.h
index fa9cf5fdcba..76941758490 100644
--- a/arch/risc-v/include/rv32im/irq.h
+++ b/arch/risc-v/include/rv32im/irq.h
@@ -303,7 +303,6 @@ struct xcpt_syscall_s
 
 struct xcptcontext
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-NULL if there are pending signals
    * to be processed.
    */
@@ -322,14 +321,12 @@ struct xcptcontext
   uint32_t saved_epc;     /* Trampoline PC */
   uint32_t saved_int_ctx; /* Interrupt context with interrupts disabled. */
 
-# ifdef CONFIG_BUILD_KERNEL
+#ifdef CONFIG_BUILD_KERNEL
   /* This is the saved address to use when returning from a user-space
    * signal handler.
    */
 
   uint32_t sigreturn;
-
-# endif
 #endif
 
 #ifdef CONFIG_BUILD_KERNEL
diff --git a/arch/risc-v/src/gap8/gap8_schedulesigaction.c b/arch/risc-v/src/gap8/gap8_schedulesigaction.c
index ff691d32e9a..d7a7d0a3f0c 100644
--- a/arch/risc-v/src/gap8/gap8_schedulesigaction.c
+++ b/arch/risc-v/src/gap8/gap8_schedulesigaction.c
@@ -55,8 +55,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -199,5 +197,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/risc-v/src/nr5m100/chip.h b/arch/risc-v/src/nr5m100/chip.h
index dbe9928c6f6..a9d670fcc10 100644
--- a/arch/risc-v/src/nr5m100/chip.h
+++ b/arch/risc-v/src/nr5m100/chip.h
@@ -45,7 +45,7 @@
 
 #ifdef CONFIG_RV32IM_CMNVECTOR
 #  if defined(CONFIG_NR5_NR5M1XX)
-#    include "chip/nr5m1xx_vectors.h"
+#    include "hardware/nr5m1xx_vectors.h"
 #  else
 #    error "No vector file for this NanoRisc5 family"
 #  endif
diff --git a/arch/risc-v/src/nr5m100/chip/nr5m1xx_epic.h b/arch/risc-v/src/nr5m100/hardware/nr5m1xx_epic.h
similarity index 97%
rename from arch/risc-v/src/nr5m100/chip/nr5m1xx_epic.h
rename to arch/risc-v/src/nr5m100/hardware/nr5m1xx_epic.h
index 3fa13aed104..3aa3756f99a 100644
--- a/arch/risc-v/src/nr5m100/chip/nr5m1xx_epic.h
+++ b/arch/risc-v/src/nr5m100/hardware/nr5m1xx_epic.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/risc-v/src/nr5m100/chip/nr5_epic.h
+ * arch/risc-v/src/nr5m100/hardware/nr5_epic.h
  *
  *   Copyright (C) 2016 Ken Pettit. All rights reserved.
  *   Author: Ken Pettit 
diff --git a/arch/risc-v/src/nr5m100/chip/nr5m1xx_memorymap.h b/arch/risc-v/src/nr5m100/hardware/nr5m1xx_memorymap.h
similarity index 91%
rename from arch/risc-v/src/nr5m100/chip/nr5m1xx_memorymap.h
rename to arch/risc-v/src/nr5m100/hardware/nr5m1xx_memorymap.h
index 4ebc6879d13..bffc90d426f 100644
--- a/arch/risc-v/src/nr5m100/chip/nr5m1xx_memorymap.h
+++ b/arch/risc-v/src/nr5m100/hardware/nr5m1xx_memorymap.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/risc-v/src/nr5m100/chip/nr5m1xx_memorymap.h
+ * arch/risc-v/src/nr5m100/hardware/nr5m1xx_memorymap.h
  *
  *   Copyright (C) 2016 Ken Pettit. All rights reserved.
  *   Author: Ken Pettit 
@@ -30,8 +30,8 @@
  *
  ************************************************************************************/
 
-#ifndef __ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_MEMORYMAP_H
-#define __ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_MEMORYMAP_H
+#ifndef __ARCH_RISCV_SRC_NR5M100_HARDWARE_NR5M1XX_MEMORYMAP_H
+#define __ARCH_RISCV_SRC_NR5M100_HARDWARE_NR5M1XX_MEMORYMAP_H
 
 /************************************************************************************
  * Pre-processor Definitions
@@ -53,5 +53,5 @@
 #define NR5_TIMER2_BASE     0x40005000      /* 0x40005000 - 0x40005fff: TIMER1 timer */
 #define NR5_EXTMEM_BASE     0x40006000      /* 0x40006000 - 0x40006fff: EXTMEM Controller*/
 
-#endif /* __ARCH_RISCV_SRC_NR5M100_CHIP_NR5M1XX_MEMORYMAP_H */
+#endif /* __ARCH_RISCV_SRC_NR5M100_HARDWARE_NR5M1XX_MEMORYMAP_H */
 
diff --git a/arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h b/arch/risc-v/src/nr5m100/hardware/nr5m1xx_timer.h
similarity index 99%
rename from arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h
rename to arch/risc-v/src/nr5m100/hardware/nr5m1xx_timer.h
index 98ea8aa8035..5884c2c303d 100644
--- a/arch/risc-v/src/nr5m100/chip/nr5m1xx_timer.h
+++ b/arch/risc-v/src/nr5m100/hardware/nr5m1xx_timer.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/risc-v/src/nr5m100/chip/nr5_timer.h
+ * arch/risc-v/src/nr5m100/hardware/nr5_timer.h
  *
  *   Copyright (C) 2016 Ken Pettit. All rights reserved.
  *   Author: Ken Pettit 
diff --git a/arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h b/arch/risc-v/src/nr5m100/hardware/nr5m1xx_uart.h
similarity index 98%
rename from arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h
rename to arch/risc-v/src/nr5m100/hardware/nr5m1xx_uart.h
index 215f8916fee..ba9b7286525 100644
--- a/arch/risc-v/src/nr5m100/chip/nr5m1xx_uart.h
+++ b/arch/risc-v/src/nr5m100/hardware/nr5m1xx_uart.h
@@ -1,5 +1,5 @@
 /************************************************************************************
- * arch/risc-v/src/nr5m100/chip/nr5_uart.h
+ * arch/risc-v/src/nr5m100/hardware/nr5_uart.h
  *
  *   Copyright (C) 2016 Ken Pettit. All rights reserved.
  *   Author: Ken Pettit 
diff --git a/arch/risc-v/src/nr5m100/nr5_csr.h b/arch/risc-v/src/nr5m100/nr5_csr.h
index 025a5098865..ddd6e8b046b 100644
--- a/arch/risc-v/src/nr5m100/nr5_csr.h
+++ b/arch/risc-v/src/nr5m100/nr5_csr.h
@@ -47,7 +47,7 @@
 #endif
 
 #if defined(CONFIG_NR5_NR5M1XX)
-#  include "chip/nr5m1xx_epic.h"
+#  include "hardware/nr5m1xx_epic.h"
 #endif
 
 #include 
diff --git a/arch/risc-v/src/nr5m100/nr5_memorymap.h b/arch/risc-v/src/nr5m100/nr5_memorymap.h
index 8ebcfedd685..b8aaeca62b4 100644
--- a/arch/risc-v/src/nr5m100/nr5_memorymap.h
+++ b/arch/risc-v/src/nr5m100/nr5_memorymap.h
@@ -36,7 +36,7 @@
 //#include 
 
 #ifdef CONFIG_NR5_NR5MXXX
-#include "chip/nr5m1xx_memorymap.h"
+#include "hardware/nr5m1xx_memorymap.h"
 #endif
 
 #endif  /* _ARCH_RISCV_SRC_NR5M100_NR5_MEMORYMAP_H */
diff --git a/arch/risc-v/src/nr5m100/nr5_timer.h b/arch/risc-v/src/nr5m100/nr5_timer.h
index 5994df9bee1..8bd36aec330 100644
--- a/arch/risc-v/src/nr5m100/nr5_timer.h
+++ b/arch/risc-v/src/nr5m100/nr5_timer.h
@@ -45,7 +45,7 @@
 #include 
 
 #include "chip.h"
-#include "chip/nr5m1xx_timer.h"
+#include "hardware/nr5m1xx_timer.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/risc-v/src/nr5m100/nr5_uart.h b/arch/risc-v/src/nr5m100/nr5_uart.h
index 7f40dfc0ab3..7fe20348c43 100644
--- a/arch/risc-v/src/nr5m100/nr5_uart.h
+++ b/arch/risc-v/src/nr5m100/nr5_uart.h
@@ -36,7 +36,7 @@
 #include 
 
 #ifdef CONFIG_NR5_NR5M1XX
-#include "chip/nr5m1xx_uart.h"
+#include "hardware/nr5m1xx_uart.h"
 #endif
 
 void nr5_uart_init(int uart_num);
diff --git a/arch/risc-v/src/nr5m100/up_schedulesigaction.c b/arch/risc-v/src/nr5m100/up_schedulesigaction.c
index d7b8698a56c..7fba9a2d68b 100644
--- a/arch/risc-v/src/nr5m100/up_schedulesigaction.c
+++ b/arch/risc-v/src/nr5m100/up_schedulesigaction.c
@@ -56,8 +56,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -209,5 +207,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/risc-v/src/rv32im/up_sigdeliver.c b/arch/risc-v/src/rv32im/up_sigdeliver.c
index 616148bc948..24d63d6ee83 100644
--- a/arch/risc-v/src/rv32im/up_sigdeliver.c
+++ b/arch/risc-v/src/rv32im/up_sigdeliver.c
@@ -58,8 +58,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -145,6 +143,3 @@ void up_sigdeliver(void)
 
   DEBUGPANIC();
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
-
diff --git a/arch/sim/Kconfig b/arch/sim/Kconfig
index b24412ab023..a64b7446a43 100644
--- a/arch/sim/Kconfig
+++ b/arch/sim/Kconfig
@@ -222,7 +222,7 @@ endif # SIM_X11FB && INPUT
 config SIM_TCNWAITERS
 	bool "Maximum number poll() waiters"
 	default 4
-	depends on !POLL_DISABLE && SIM_TOUCHSCREEN
+	depends on SIM_TOUCHSCREEN
 	---help---
 		The maximum number of threads that can be waiting on poll() for a
 		touchscreen event. Default: 4
diff --git a/arch/sim/src/up_devconsole.c b/arch/sim/src/up_devconsole.c
index ffe24f0d55a..6cfee4e3cec 100644
--- a/arch/sim/src/up_devconsole.c
+++ b/arch/sim/src/up_devconsole.c
@@ -57,10 +57,8 @@ static ssize_t devconsole_read(FAR struct file *filep, FAR char *buffer,
                  size_t buflen);
 static ssize_t devconsole_write(FAR struct file *filep,
                  FAR const char *buffer, size_t buflen);
-#ifndef CONFIG_DISABLE_POLL
 static int     devconsole_poll(FAR struct file *filep, FAR struct pollfd *fds,
                  bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -70,9 +68,7 @@ static const struct file_operations devconsole_fops =
 {
   .read   = devconsole_read,
   .write  = devconsole_write,
-#ifndef CONFIG_DISABLE_POLL
   .poll   = devconsole_poll,
-#endif
 };
 
 /****************************************************************************
@@ -151,13 +147,11 @@ static ssize_t devconsole_write(struct file *filep, const char *buffer, size_t l
  * Name: devconsole_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int devconsole_poll(FAR struct file *filep, FAR struct pollfd *fds,
                            bool setup)
 {
   return OK;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/arch/sim/src/up_framebuffer.c b/arch/sim/src/up_framebuffer.c
index 45105692585..8178c3994d9 100644
--- a/arch/sim/src/up_framebuffer.c
+++ b/arch/sim/src/up_framebuffer.c
@@ -152,12 +152,12 @@ static struct fb_planeinfo_s g_planeinfo;
 /* Current cursor position */
 
 #ifdef CONFIG_FB_HWCURSOR
-static struct cursor_pos_s g_cpos;
+static struct fb_cursorpos_s g_cpos;
 
 /* Current cursor size */
 
 #ifdef CONFIG_FB_HWCURSORSIZE
-static struct cursor_size_s g_csize;
+static struct fb_cursorsize_s g_csize;
 #endif
 #endif
 
diff --git a/arch/sim/src/up_touchscreen.c b/arch/sim/src/up_touchscreen.c
index f08ca56a0a4..ab13353202e 100644
--- a/arch/sim/src/up_touchscreen.c
+++ b/arch/sim/src/up_touchscreen.c
@@ -69,12 +69,8 @@
  ****************************************************************************/
 /* Configuration ************************************************************/
 
-#ifdef CONFIG_DISABLE_POLL
-#  undef CONFIG_SIM_TCNWAITERS
-#else
-#  ifndef CONFIG_SIM_TCNWAITERS
-#    define CONFIG_SIM_TCNWAITERS 4
-#  endif
+#ifndef CONFIG_SIM_TCNWAITERS
+#  define CONFIG_SIM_TCNWAITERS 4
 #endif
 
 /* Driver support ***********************************************************/
@@ -127,9 +123,7 @@ struct up_dev_s
    * retained in the f_priv field of the 'struct file'.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_SIM_TCNWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -148,9 +142,7 @@ static int up_open(FAR struct file *filep);
 static int up_close(FAR struct file *filep);
 static ssize_t up_read(FAR struct file *filep, FAR char *buffer, size_t len);
 static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int up_poll(FAR struct file *filep, struct pollfd *fds, bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -163,12 +155,10 @@ static const struct file_operations up_fops =
   up_open,    /* open */
   up_close,   /* close */
   up_read,    /* read */
-  0,          /* write */
-  0,          /* seek */
-  up_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , up_poll   /* poll */
-#endif
+  NULL,       /* write */
+  NULL,       /* seek */
+  up_ioctl,   /* ioctl */
+  up_poll     /* poll */
 };
 
 /* Only one simulated touchscreen is supported so the driver state
@@ -187,9 +177,7 @@ static struct up_dev_s g_simtouchscreen;
 
 static void up_notify(FAR struct up_dev_s *priv)
 {
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   /* If there are threads waiting for read data, then signal one of them
    * that the read data is available.
@@ -211,7 +199,6 @@ static void up_notify(FAR struct up_dev_s *priv)
    * then some make end up blocking after all.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   for (i = 0; i < CONFIG_SIM_TCNWAITERS; i++)
     {
       struct pollfd *fds = priv->fds[i];
@@ -222,7 +209,6 @@ static void up_notify(FAR struct up_dev_s *priv)
           nxsem_post(fds->sem);
         }
     }
-#endif
 }
 
 /****************************************************************************
@@ -530,7 +516,6 @@ static int up_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: up_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int up_poll(FAR struct file *filep, FAR struct pollfd *fds,
                    bool setup)
 {
@@ -616,7 +601,6 @@ errout:
   nxsem_post(&priv->devsem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/arch/x86/include/i486/irq.h b/arch/x86/include/i486/irq.h
index 9befc78b5c0..8c090a0c986 100644
--- a/arch/x86/include/i486/irq.h
+++ b/arch/x86/include/i486/irq.h
@@ -166,7 +166,6 @@
 #ifndef __ASSEMBLY__
 struct xcptcontext
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there are pending signals
    * to be processed.
    */
@@ -184,7 +183,6 @@ struct xcptcontext
 
   uint32_t saved_eip;
   uint32_t saved_eflags;
-#endif
 
   /* Register save area */
 
diff --git a/arch/x86/src/i486/up_schedulesigaction.c b/arch/x86/src/i486/up_schedulesigaction.c
index 5faf6d1ebd5..e8812516268 100644
--- a/arch/x86/src/i486/up_schedulesigaction.c
+++ b/arch/x86/src/i486/up_schedulesigaction.c
@@ -50,20 +50,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -195,5 +181,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/x86/src/i486/up_sigdeliver.c b/arch/x86/src/i486/up_sigdeliver.c
index 0f6164565a9..4a9b8e59ecf 100644
--- a/arch/x86/src/i486/up_sigdeliver.c
+++ b/arch/x86/src/i486/up_sigdeliver.c
@@ -52,8 +52,6 @@
 #include "up_internal.h"
 #include "up_arch.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -130,6 +128,3 @@ void up_sigdeliver(void)
   board_autoled_off(LED_SIGNAL);
   up_fullcontextrestore(regs);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
-
diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h
index 49fca1e4e67..1c883a85e8a 100644
--- a/arch/xtensa/include/irq.h
+++ b/arch/xtensa/include/irq.h
@@ -146,7 +146,6 @@
 
 struct xcptcontext
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there are pending signals
    * to be processed.
    */
@@ -163,7 +162,6 @@ struct xcptcontext
 
   uint32_t saved_pc;
   uint32_t saved_ps;
-#endif
 
   /* Register save area */
 
diff --git a/arch/xtensa/src/common/xtensa_schedsigaction.c b/arch/xtensa/src/common/xtensa_schedsigaction.c
index bbddd01ef6f..c9c3de139bd 100644
--- a/arch/xtensa/src/common/xtensa_schedsigaction.c
+++ b/arch/xtensa/src/common/xtensa_schedsigaction.c
@@ -51,8 +51,6 @@
 
 #include "irq/irq.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -390,5 +388,3 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
   leave_critical_section(flags);
 }
 #endif /* CONFIG_SMP */
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/xtensa/src/common/xtensa_sigdeliver.c b/arch/xtensa/src/common/xtensa_sigdeliver.c
index 197d5d90ade..70e5ad27a45 100644
--- a/arch/xtensa/src/common/xtensa_sigdeliver.c
+++ b/arch/xtensa/src/common/xtensa_sigdeliver.c
@@ -51,8 +51,6 @@
 #include "sched/sched.h"
 #include "xtensa.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -175,5 +173,3 @@ void xtensa_sig_deliver(void)
   board_autoled_off(LED_SIGNAL);
   xtensa_context_restore(regs);
 }
-
-#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c
index 8d43741ac03..fa2a7ee31d2 100644
--- a/arch/xtensa/src/esp32/esp32_cpuint.c
+++ b/arch/xtensa/src/esp32/esp32_cpuint.c
@@ -49,7 +49,7 @@
 #include 
 #include 
 
-#include "chip/esp32_dport.h"
+#include "hardware/esp32_dport.h"
 #include "esp32_cpuint.h"
 #include "xtensa.h"
 
diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c
index e79e7c3345b..cb233d29b85 100644
--- a/arch/xtensa/src/esp32/esp32_cpustart.c
+++ b/arch/xtensa/src/esp32/esp32_cpustart.c
@@ -51,8 +51,8 @@
 
 #include "sched/sched.h"
 #include "xtensa.h"
-#include "chip/esp32_dport.h"
-#include "chip/esp32_rtccntl.h"
+#include "hardware/esp32_dport.h"
+#include "hardware/esp32_rtccntl.h"
 #include "esp32_region.h"
 #include "esp32_cpuint.h"
 #include "esp32_smp.h"
diff --git a/arch/xtensa/src/esp32/esp32_gpio.c b/arch/xtensa/src/esp32/esp32_gpio.c
index 15e431973da..d83eb2e63e2 100644
--- a/arch/xtensa/src/esp32/esp32_gpio.c
+++ b/arch/xtensa/src/esp32/esp32_gpio.c
@@ -39,8 +39,8 @@
 #include 
 
 #include "xtensa.h"
-#include "chip/esp32_iomux.h"
-#include "chip/esp32_gpio.h"
+#include "hardware/esp32_iomux.h"
+#include "hardware/esp32_gpio.h"
 #include "esp32_cpuint.h"
 #include "esp32_gpio.h"
 
diff --git a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c
index ce27269f213..eade8e5ff4c 100644
--- a/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c
+++ b/arch/xtensa/src/esp32/esp32_intercpu_interrupt.c
@@ -47,7 +47,7 @@
 #include 
 #include 
 
-#include "chip/esp32_dport.h"
+#include "hardware/esp32_dport.h"
 #include "xtensa.h"
 
 #ifdef CONFIG_SMP
diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c
index 7a4c5accf51..4c27dee8ee8 100644
--- a/arch/xtensa/src/esp32/esp32_serial.c
+++ b/arch/xtensa/src/esp32/esp32_serial.c
@@ -60,10 +60,10 @@
 #include 
 
 #include "xtensa.h"
-#include "chip/esp32_soc.h"
-#include "chip/esp32_iomux.h"
-#include "chip/esp32_gpio_sigmap.h"
-#include "chip/esp32_uart.h"
+#include "hardware/esp32_soc.h"
+#include "hardware/esp32_iomux.h"
+#include "hardware/esp32_gpio_sigmap.h"
+#include "hardware/esp32_uart.h"
 #include "rom/esp32_gpio.h"
 #include "esp32_config.h"
 #include "esp32_gpio.h"
diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c
index 4f3e9e77032..8cca41fa320 100644
--- a/arch/xtensa/src/esp32/esp32_start.c
+++ b/arch/xtensa/src/esp32/esp32_start.c
@@ -38,8 +38,8 @@
 #include "xtensa.h"
 #include "xtensa_attr.h"
 
-#include "chip/esp32_dport.h"
-#include "chip/esp32_rtccntl.h"
+#include "hardware/esp32_dport.h"
+#include "hardware/esp32_rtccntl.h"
 #include "esp32_clockconfig.h"
 #include "esp32_region.h"
 #include "esp32_start.h"
diff --git a/arch/xtensa/src/esp32/chip/esp32_dport.h b/arch/xtensa/src/esp32/hardware/esp32_dport.h
similarity index 99%
rename from arch/xtensa/src/esp32/chip/esp32_dport.h
rename to arch/xtensa/src/esp32/hardware/esp32_dport.h
index 6175b29f0d3..b242c476c89 100644
--- a/arch/xtensa/src/esp32/chip/esp32_dport.h
+++ b/arch/xtensa/src/esp32/hardware/esp32_dport.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/xtensa/src/esp32/chip/esp32_dport.h
+ * arch/xtensa/src/esp32/hardware/esp32_dport.h
  *
  * Adapted from use in NuttX by:
  *
@@ -24,14 +24,14 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_DPORT_H
-#define __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_DPORT_H
+#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_DPORT_H
+#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_DPORT_H
 
 /****************************************************************************
  * Included Files
  ****************************************************************************/
 
-#include "chip/esp32_soc.h"
+#include "hardware/esp32_soc.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -4859,4 +4859,5 @@
 #define DPORT_DATE_S  0
 #define DPORT_DPORT_DATE_VERSION 0x1605190
 
-#endif /*__ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_DPORT_H */
+#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_DPORT_H */
+
diff --git a/arch/xtensa/src/esp32/chip/esp32_gpio.h b/arch/xtensa/src/esp32/hardware/esp32_gpio.h
similarity index 99%
rename from arch/xtensa/src/esp32/chip/esp32_gpio.h
rename to arch/xtensa/src/esp32/hardware/esp32_gpio.h
index 17cc102ed4a..a69b38ba707 100644
--- a/arch/xtensa/src/esp32/chip/esp32_gpio.h
+++ b/arch/xtensa/src/esp32/hardware/esp32_gpio.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/xtensa/src/esp32/chip/esp32_gpio.h
+ * arch/xtensa/src/esp32/hardware/esp32_gpio.h
  *
  * Adapted from use in NuttX by:
  *
@@ -24,14 +24,14 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_GPIO_H
-#define __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_GPIO_H
+#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_GPIO_H
+#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_GPIO_H
 
 /****************************************************************************
  * Included Files
  ****************************************************************************/
 
-#include "chip/esp32_soc.h"
+#include "hardware/esp32_soc.h"
 
 /****************************************************************************
  * Pre-preprocessor Definitions
@@ -11640,4 +11640,4 @@
 #define GPIO_FUNC39_OUT_SEL_V  0x1FF
 #define GPIO_FUNC39_OUT_SEL_S  0
 
-#endif /* __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_GPIO_H */
+#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_GPIO_H */
diff --git a/arch/xtensa/src/esp32/chip/esp32_gpio_sigmap.h b/arch/xtensa/src/esp32/hardware/esp32_gpio_sigmap.h
similarity index 98%
rename from arch/xtensa/src/esp32/chip/esp32_gpio_sigmap.h
rename to arch/xtensa/src/esp32/hardware/esp32_gpio_sigmap.h
index f6a6ce7ba88..0999451f13e 100644
--- a/arch/xtensa/src/esp32/chip/esp32_gpio_sigmap.h
+++ b/arch/xtensa/src/esp32/hardware/esp32_gpio_sigmap.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/xtensa/src/esp32/chip/esp32_gpio_sigmap.h
+ * arch/xtensa/src/esp32/hardware/esp32_gpio_sigmap.h
  *
  * Adapted from use in NuttX by:
  *
@@ -24,8 +24,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_GPIO_SIGMAP_H
-#define __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_GPIO_SIGMAP_H
+#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_GPIO_SIGMAP_H
+#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_GPIO_SIGMAP_H
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -436,4 +436,4 @@
 #define SIG_IN_FUNC227_IDX            227
 #define SIG_IN_FUNC228_IDX            228
 
-#endif /* __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_GPIO_SIGMAP_H */
+#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_GPIO_SIGMAP_H */
diff --git a/arch/xtensa/src/esp32/chip/esp32_iomux.h b/arch/xtensa/src/esp32/hardware/esp32_iomux.h
similarity index 97%
rename from arch/xtensa/src/esp32/chip/esp32_iomux.h
rename to arch/xtensa/src/esp32/hardware/esp32_iomux.h
index f424fae1e2f..a741eb4b983 100644
--- a/arch/xtensa/src/esp32/chip/esp32_iomux.h
+++ b/arch/xtensa/src/esp32/hardware/esp32_iomux.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/xtensa/src/esp32/esp32_gpio.c
+ * arch/xtensa/src/esp32/hardware/esp32_gpio.c
  *
  * Developed for NuttX by:
  *
@@ -24,14 +24,14 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_MUX_H
-#define __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_MUX_H 1
+#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_MUX_H
+#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_MUX_H 1
 
 /****************************************************************************
  * Included Files
  ****************************************************************************/
 
-#include "chip/esp32_soc.h"
+#include "hardware/esp32_soc.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -285,4 +285,4 @@
 #define FUNC_GPIO39_GPIO39                2
 #define FUNC_GPIO39_GPIO39_0              0
 
-#endif /* __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_MUX_H */
+#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_MUX_H */
diff --git a/arch/xtensa/src/esp32/chip/esp32_rtccntl.h b/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h
similarity index 99%
rename from arch/xtensa/src/esp32/chip/esp32_rtccntl.h
rename to arch/xtensa/src/esp32/hardware/esp32_rtccntl.h
index 23a0102234c..fd9d81f7710 100644
--- a/arch/xtensa/src/esp32/chip/esp32_rtccntl.h
+++ b/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/xtensa/src/esp32/chip/esp32_rtccnt.h
+ * arch/xtensa/src/esp32/hardware/esp32_rtccnt.h
  *
  * Adapted from use in NuttX by:
  *
@@ -24,14 +24,14 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_ESP32_H
-#define __ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_ESP32_H
+#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_XTENSA_ESP32_H
+#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_XTENSA_ESP32_H
 
 /****************************************************************************
  * Included Files
  ****************************************************************************/
 
-#include "chip/esp32_soc.h"
+#include "hardware/esp32_soc.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -2001,4 +2001,4 @@
 #define RTC_CNTL_CNTL_DATE_S  0
 #define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280
 
-#endif /*__ARCH_XTENSA_SRC_ESP32_CHIP_XTENSA_ESP32_H */
+#endif /*__ARCH_XTENSA_SRC_ESP32_HARDWARE_XTENSA_ESP32_H */
diff --git a/arch/xtensa/src/esp32/chip/esp32_soc.h b/arch/xtensa/src/esp32/hardware/esp32_soc.h
similarity index 98%
rename from arch/xtensa/src/esp32/chip/esp32_soc.h
rename to arch/xtensa/src/esp32/hardware/esp32_soc.h
index 0073508ab6a..a8597c1f807 100644
--- a/arch/xtensa/src/esp32/chip/esp32_soc.h
+++ b/arch/xtensa/src/esp32/hardware/esp32_soc.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/xtensa/src/esp32/chip/esp32_soc.h
+ * arch/xtensa/src/esp32/hardware/esp32_soc.h
  *
  * Adapted from use in NuttX by:
  *
@@ -24,8 +24,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_SOC_H
-#define __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_SOC_H
+#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H
+#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H
 
 /****************************************************************************
  * Included Files
@@ -354,4 +354,4 @@
 
 /* Other interrupt numbers should be managed by the user */
 
-#endif /* __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_SOC_H */
+#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H */
diff --git a/arch/xtensa/src/esp32/chip/esp32_uart.h b/arch/xtensa/src/esp32/hardware/esp32_uart.h
similarity index 99%
rename from arch/xtensa/src/esp32/chip/esp32_uart.h
rename to arch/xtensa/src/esp32/hardware/esp32_uart.h
index 710ef41beb1..e6bcfdefd8b 100644
--- a/arch/xtensa/src/esp32/chip/esp32_uart.h
+++ b/arch/xtensa/src/esp32/hardware/esp32_uart.h
@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/xtensa/src/esp32/chip/esp32_uart.h
+ * arch/xtensa/src/esp32/hardware/esp32_uart.h
  *
  * Adapted from use in NuttX by:
  *
@@ -24,14 +24,14 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_UART_H
-#define __ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_UART_H
+#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_UART_H
+#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_UART_H
 
 /****************************************************************************
  * Included Files
  ****************************************************************************/
 
-#include "chip/esp32_soc.h"
+#include "hardware/esp32_soc.h"
 
 /****************************************************************************
  * Pre-processor Macros
@@ -1695,4 +1695,5 @@
 #define UART_ID_V                       0xFFFFFFFF
 #define UART_ID_S                       0
 
-#endif /*__ARCH_XTENSA_SRC_ESP32_CHIP_ESP32_UART_H */
+#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_UART_H */
+
diff --git a/arch/xtensa/src/esp32/rom/esp32_gpio.h b/arch/xtensa/src/esp32/rom/esp32_gpio.h
index 38eae27c80a..f4f278cb74c 100644
--- a/arch/xtensa/src/esp32/rom/esp32_gpio.h
+++ b/arch/xtensa/src/esp32/rom/esp32_gpio.h
@@ -36,7 +36,7 @@
 #include 
 #include 
 
-#include "chip/esp32_gpio.h"
+#include "hardware/esp32_gpio.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/z16/include/z16f/irq.h b/arch/z16/include/z16f/irq.h
index 2c9aa7cf2e0..eb136a61469 100644
--- a/arch/z16/include/z16f/irq.h
+++ b/arch/z16/include/z16f/irq.h
@@ -178,7 +178,6 @@ struct xcptcontext
 
   uint16_t regs[XCPTCONTEXT_REGS];
 
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there
    * are pending signals to be processed.
    */
@@ -195,7 +194,6 @@ struct xcptcontext
 
   uint32_t saved_pc;  /* Saved return address */
   uint16_t saved_i;   /* Saved interrupt state */
-#endif
 };
 #endif
 
diff --git a/arch/z16/src/Makefile b/arch/z16/src/Makefile
index 3cfe75a97ba..c4b5f67a500 100644
--- a/arch/z16/src/Makefile
+++ b/arch/z16/src/Makefile
@@ -40,14 +40,14 @@ COMPILER = ${shell basename "$(CC)"}
 ARCHSRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
 
 ifeq ($(CONFIG_WINDOWS_NATIVE),y)
-  USRINCLUDES = -usrinc:'.;$(TOPDIR)/sched;$(ARCHSRCDIR);$(ARCHSRCDIR)/common'
+  USRINCLUDES = -usrinc:'.;$(TOPDIR)/sched;$(ARCHSRCDIR)$(DELIM)chip;$(ARCHSRCDIR)$(DELIM)common'
 else
 ifeq ($(COMPILER),zneocc.exe)
   WARCHSRCDIR := ${shell cygpath -w $(ARCHSRCDIR)}
-  USRINCLUDES = -usrinc:'.;$(WTOPDIR)\sched;$(WARCHSRCDIR);$(WARCHSRCDIR)\common'
+  USRINCLUDES = -usrinc:'.;$(WTOPDIR)\sched;$(WARCHSRCDIR)$(DELIM)chip;$(WARCHSRCDIR)$(DELIM)common'
 else
   WARCHSRCDIR = $(ARCHSRCDIR)
-  USRINCLUDES = -I$(TOPDIR)/sched -I$(ARCHSRCDIR) -I$(ARCHSRCDIR)/common
+  USRINCLUDES = -I$(TOPDIR)/sched -I$(ARCHSRCDIR)$(DELIM)chip -I$(ARCHSRCDIR)$(DELIM)common
 endif
 endif
 
diff --git a/arch/z16/src/common/up_allocateheap.c b/arch/z16/src/common/up_allocateheap.c
index 948f770210a..73a9f1cd032 100644
--- a/arch/z16/src/common/up_allocateheap.c
+++ b/arch/z16/src/common/up_allocateheap.c
@@ -47,7 +47,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "up_internal.h"
 
 /****************************************************************************
diff --git a/arch/z16/src/common/up_arch.h b/arch/z16/src/common/up_arch.h
index 1b98ccc2aea..159344a4246 100644
--- a/arch/z16/src/common/up_arch.h
+++ b/arch/z16/src/common/up_arch.h
@@ -43,7 +43,7 @@
 #include 
 
 #include 
-#include "chip/chip.h"
+#include "chip.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/z16/src/common/up_assert.c b/arch/z16/src/common/up_assert.c
index f22e9822860..ee2aaa26a1b 100644
--- a/arch/z16/src/common/up_assert.c
+++ b/arch/z16/src/common/up_assert.c
@@ -53,7 +53,7 @@
 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "sched/sched.h"
 #include "up_internal.h"
 
diff --git a/arch/z16/src/common/up_createstack.c b/arch/z16/src/common/up_createstack.c
index 0bab2d3ab36..0ec33206fc2 100644
--- a/arch/z16/src/common/up_createstack.c
+++ b/arch/z16/src/common/up_createstack.c
@@ -49,7 +49,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "up_internal.h"
 
 /****************************************************************************
diff --git a/arch/z16/src/common/up_doirq.c b/arch/z16/src/common/up_doirq.c
index fb4954fc618..52112166ef6 100644
--- a/arch/z16/src/common/up_doirq.c
+++ b/arch/z16/src/common/up_doirq.c
@@ -46,7 +46,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "up_internal.h"
 
 /****************************************************************************
diff --git a/arch/z16/src/common/up_exit.c b/arch/z16/src/common/up_exit.c
index 27eed07ff09..3fe1e4f392a 100644
--- a/arch/z16/src/common/up_exit.c
+++ b/arch/z16/src/common/up_exit.c
@@ -49,7 +49,7 @@
 #  include 
 #endif
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "task/task.h"
 #include "sched/sched.h"
 #include "up_internal.h"
diff --git a/arch/z16/src/common/up_initialstate.c b/arch/z16/src/common/up_initialstate.c
index 4509e1eba0e..afae71b2138 100644
--- a/arch/z16/src/common/up_initialstate.c
+++ b/arch/z16/src/common/up_initialstate.c
@@ -43,7 +43,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "up_internal.h"
 
 /****************************************************************************
diff --git a/arch/z16/src/common/up_internal.h b/arch/z16/src/common/up_internal.h
index 98ccae82ada..92984031fc4 100644
--- a/arch/z16/src/common/up_internal.h
+++ b/arch/z16/src/common/up_internal.h
@@ -42,7 +42,7 @@
  ****************************************************************************/
 
 #include 
-#include "chip/chip.h"
+#include "chip.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/z16/src/common/up_releasepending.c b/arch/z16/src/common/up_releasepending.c
index 41ee99c7ed1..4df9fdc75c9 100644
--- a/arch/z16/src/common/up_releasepending.c
+++ b/arch/z16/src/common/up_releasepending.c
@@ -45,7 +45,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "sched/sched.h"
 #include "up_internal.h"
 
diff --git a/arch/z16/src/common/up_reprioritizertr.c b/arch/z16/src/common/up_reprioritizertr.c
index 76fe4a1f5da..33215d42c62 100644
--- a/arch/z16/src/common/up_reprioritizertr.c
+++ b/arch/z16/src/common/up_reprioritizertr.c
@@ -47,7 +47,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "sched/sched.h"
 #include "up_internal.h"
 
diff --git a/arch/z16/src/common/up_schedulesigaction.c b/arch/z16/src/common/up_schedulesigaction.c
index 8fde953c393..54c80774cfe 100644
--- a/arch/z16/src/common/up_schedulesigaction.c
+++ b/arch/z16/src/common/up_schedulesigaction.c
@@ -49,8 +49,6 @@
 #include "sched/sched.h"
 #include "up_internal.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -184,6 +182,3 @@ void up_schedule_sigaction(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* CONFIG_DISABLE_SIGNALS */
-
diff --git a/arch/z16/src/common/up_sigdeliver.c b/arch/z16/src/common/up_sigdeliver.c
index a7c874cb0ef..8ef03ea4318 100644
--- a/arch/z16/src/common/up_sigdeliver.c
+++ b/arch/z16/src/common/up_sigdeliver.c
@@ -52,8 +52,6 @@
 #include "sched/sched.h"
 #include "up_internal.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -70,7 +68,6 @@
 
 void up_sigdeliver(void)
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   FAR struct tcb_s *rtcb = this_task();
   chipreg_t regs[XCPTCONTEXT_REGS];
   FAR uint32_t *regs32 = (FAR uint32_t*)regs;
@@ -131,7 +128,4 @@ void up_sigdeliver(void)
 
   board_autoled_off(LED_SIGNAL);
   SIGNAL_RETURN(regs);
-#endif
 }
-
-#endif /* CONFIG_DISABLE_SIGNALS */
diff --git a/arch/z16/src/common/up_stackdump.c b/arch/z16/src/common/up_stackdump.c
index 0802612a05b..40abf3777e8 100644
--- a/arch/z16/src/common/up_stackdump.c
+++ b/arch/z16/src/common/up_stackdump.c
@@ -41,7 +41,7 @@
 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "sched/sched.h"
 #include "up_internal.h"
 
diff --git a/arch/z16/src/common/up_unblocktask.c b/arch/z16/src/common/up_unblocktask.c
index db1a43aaeb5..ecaae236087 100644
--- a/arch/z16/src/common/up_unblocktask.c
+++ b/arch/z16/src/common/up_unblocktask.c
@@ -45,7 +45,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "sched/sched.h"
 #include "clock/clock.h"
 #include "up_internal.h"
diff --git a/arch/z16/src/z16f/Kconfig b/arch/z16/src/z16f/Kconfig
index 56067cae663..1a958cebb91 100644
--- a/arch/z16/src/z16f/Kconfig
+++ b/arch/z16/src/z16f/Kconfig
@@ -36,4 +36,21 @@ config Z16F_ESPI_REGDEBUG
 	depends on DEBUG_FEATURES
 
 endmenu # Z16F ESPI Configuration
+
+# The ZiLOG ZDS-II Windows toolchain is the only toolchain available for
+# the ZNeo.
+#
+
+choice
+	prompt "ZDS-II Toolchain version"
+	default Z16F_ZDSII_V521
+
+config Z16F_ZDSII_V501
+	bool "ZDS-II 5.0.1"
+
+config Z16F_ZDSII_V521
+	bool "ZDS-II 5.2.1"
+
+endchoice # ZDS-II Toolchain version
+
 endif # ARCH_CHIP_Z16F
diff --git a/arch/z16/src/z16f/z16f_clkinit.c b/arch/z16/src/z16f/z16f_clkinit.c
index 41690dd8298..9a5c6f8ecd1 100644
--- a/arch/z16/src/z16f/z16f_clkinit.c
+++ b/arch/z16/src/z16f/z16f_clkinit.c
@@ -39,7 +39,7 @@
  * Included Files
  ****************************************************************************/
 
-#include "chip/chip.h"
+#include "chip.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/z16/src/z16f/z16f_irq.c b/arch/z16/src/z16f/z16f_irq.c
index bc2c6ba118c..69a244725bb 100644
--- a/arch/z16/src/z16f/z16f_irq.c
+++ b/arch/z16/src/z16f/z16f_irq.c
@@ -44,7 +44,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "up_internal.h"
 
 /****************************************************************************
diff --git a/arch/z16/src/z16f/z16f_lowuart.S b/arch/z16/src/z16f/z16f_lowuart.S
index f9209626522..327c0085fcf 100644
--- a/arch/z16/src/z16f/z16f_lowuart.S
+++ b/arch/z16/src/z16f/z16f_lowuart.S
@@ -39,7 +39,7 @@
  *************************************************************************/
 
 #include 
-#include "chip/chip.h"
+#include "chip.h"
 #include "common/up_internal.h"
 
 #ifdef USE_LOWUARTINIT
diff --git a/arch/z16/src/z16f/z16f_restoreusercontext.S b/arch/z16/src/z16f/z16f_restoreusercontext.S
index 673fe0a98f8..8e5aca02adf 100644
--- a/arch/z16/src/z16f/z16f_restoreusercontext.S
+++ b/arch/z16/src/z16f/z16f_restoreusercontext.S
@@ -39,7 +39,7 @@
 
 #include 
 #include 
-#include "chip/chip.h"
+#include "chip.h"
 
 /*************************************************************************
  * External References / External Definitions
diff --git a/arch/z16/src/z16f/z16f_saveusercontext.S b/arch/z16/src/z16f/z16f_saveusercontext.S
index 43fc8a0bcb2..c3b43ef52bd 100644
--- a/arch/z16/src/z16f/z16f_saveusercontext.S
+++ b/arch/z16/src/z16f/z16f_saveusercontext.S
@@ -39,7 +39,7 @@
 
 #include 
 #include 
-#include "chip/chip.h"
+#include "chip.h"
 
 /*************************************************************************
  * External References / External Definitions
diff --git a/arch/z16/src/z16f/z16f_serial.c b/arch/z16/src/z16f/z16f_serial.c
index f3e7d41f595..c05ac306a18 100644
--- a/arch/z16/src/z16f/z16f_serial.c
+++ b/arch/z16/src/z16f/z16f_serial.c
@@ -52,7 +52,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "up_internal.h"
 
 #ifdef USE_SERIALDRIVER
diff --git a/arch/z16/src/z16f/z16f_sysexec.c b/arch/z16/src/z16f/z16f_sysexec.c
index 86ed1e4eb0b..c21d9e377ab 100644
--- a/arch/z16/src/z16f/z16f_sysexec.c
+++ b/arch/z16/src/z16f/z16f_sysexec.c
@@ -44,7 +44,7 @@
 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "up_internal.h"
 
 /****************************************************************************
diff --git a/arch/z16/src/z16f/z16f_timerisr.c b/arch/z16/src/z16f/z16f_timerisr.c
index 36d7c3c9dce..aaaa04f7edd 100644
--- a/arch/z16/src/z16f/z16f_timerisr.c
+++ b/arch/z16/src/z16f/z16f_timerisr.c
@@ -45,7 +45,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "clock/clock.h"
 #include "up_internal.h"
 
diff --git a/arch/z80/include/ez80/io.h b/arch/z80/include/ez80/io.h
index e843db3567d..643da9eed0b 100644
--- a/arch/z80/include/ez80/io.h
+++ b/arch/z80/include/ez80/io.h
@@ -46,22 +46,6 @@
 
 #include 
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Inline functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
 /****************************************************************************
  * Public Function Prototypes
  ****************************************************************************/
diff --git a/arch/z80/include/ez80/irq.h b/arch/z80/include/ez80/irq.h
index c93ff6ddcdf..7e77fbb7dbf 100644
--- a/arch/z80/include/ez80/irq.h
+++ b/arch/z80/include/ez80/irq.h
@@ -213,7 +213,6 @@ struct xcptcontext
 
   chipreg_t regs[XCPTCONTEXT_REGS];
 
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there
    * are pending signals to be processed.
    */
@@ -230,7 +229,6 @@ struct xcptcontext
 
   chipreg_t saved_pc;    /* Saved return address */
   chipreg_t saved_i;     /* Saved interrupt state */
-#endif
 };
 #endif
 
diff --git a/arch/z80/include/irq.h b/arch/z80/include/irq.h
index da9131cab89..f3d16aafd82 100644
--- a/arch/z80/include/irq.h
+++ b/arch/z80/include/irq.h
@@ -47,21 +47,4 @@
 #include 
 #include 
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
 #endif /* __ARCH_Z80_INCLUDE_IRQ_H */
-
diff --git a/arch/z80/include/z180/irq.h b/arch/z80/include/z180/irq.h
index d2ed93e04b6..910bcb3c989 100644
--- a/arch/z80/include/z180/irq.h
+++ b/arch/z80/include/z180/irq.h
@@ -186,7 +186,6 @@ struct xcptcontext
 
   chipreg_t regs[XCPTCONTEXT_REGS];
 
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there
    * are pending signals to be processed.
    */
@@ -203,7 +202,6 @@ struct xcptcontext
 
   uint16_t saved_pc;    /* Saved return address */
   uint16_t saved_i;     /* Saved interrupt state */
-#endif
 };
 #endif
 
diff --git a/arch/z80/include/z180/limits.h b/arch/z80/include/z180/limits.h
index 283c10e33aa..7c58487d250 100644
--- a/arch/z80/include/z180/limits.h
+++ b/arch/z80/include/z180/limits.h
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/z80/include/z180/limits.h
  *
- *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2012, 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -73,6 +73,10 @@
 #define LONG_MAX    2147483647L
 #define ULONG_MAX   4294967295UL
 
+#define LLONG_MIN   (-LLONG_MAX - 1)
+#define LLONG_MAX   9223372036854775807LL
+#define ULLONG_MAX  18446744073709551615ULL
+
 /* A pointer is 2 bytes */
 
 #define PTR_MIN     (-PTR_MAX - 1)
diff --git a/arch/z80/include/z180/types.h b/arch/z80/include/z180/types.h
index 16460dca5c2..0e723b333a7 100644
--- a/arch/z80/include/z180/types.h
+++ b/arch/z80/include/z180/types.h
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/z80/include/z180/types.h
  *
- *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2012, 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -80,6 +80,10 @@ typedef unsigned int       _uint16_t;
 typedef signed long        _int32_t;
 typedef unsigned long      _uint32_t;
 
+typedef signed long long   _int64_t;
+typedef unsigned long long _uint64_t;
+#define __INT64_DEFINED
+
 /* A pointer is 2 bytes */
 
 typedef signed int         _intptr_t;
diff --git a/arch/z80/include/z8/irq.h b/arch/z80/include/z8/irq.h
index 2641d5307db..ca95ec68a69 100644
--- a/arch/z80/include/z8/irq.h
+++ b/arch/z80/include/z8/irq.h
@@ -319,7 +319,6 @@ struct xcptcontext
 
   chipreg_t regs[XCPTCONTEXT_REGS];
 
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there
    * are pending signals to be processed.
    */
@@ -336,7 +335,6 @@ struct xcptcontext
 
   uint16_t saved_pc;        /* Saved return address */
   uint16_t saved_irqctl;    /* Saved interrupt state */
-#endif
 };
 #endif
 
diff --git a/arch/z80/include/z80/irq.h b/arch/z80/include/z80/irq.h
index d11717440b4..eca37affc24 100644
--- a/arch/z80/include/z80/irq.h
+++ b/arch/z80/include/z80/irq.h
@@ -103,7 +103,6 @@ struct xcptcontext
 
   chipreg_t regs[XCPTCONTEXT_REGS];
 
-#ifndef CONFIG_DISABLE_SIGNALS
   /* The following function pointer is non-zero if there
    * are pending signals to be processed.
    */
@@ -120,7 +119,6 @@ struct xcptcontext
 
   uint16_t saved_pc;    /* Saved return address */
   uint16_t saved_i;     /* Saved interrupt state */
-#endif
 };
 #endif
 
diff --git a/arch/z80/src/Makefile.sdccl b/arch/z80/src/Makefile.sdccl
index 3a5078a8db4..ba5f7a1c0be 100644
--- a/arch/z80/src/Makefile.sdccl
+++ b/arch/z80/src/Makefile.sdccl
@@ -226,7 +226,6 @@ clean:
 	$(call DELFILE, libarch$(LIBEXT))
 	$(call CLEAN)
 
-
 distclean: clean
 	$(Q) if [ -e board/Makefile ]; then \
 		$(MAKE) -C board TOPDIR="$(TOPDIR)" distclean ; \
diff --git a/arch/z80/src/Makefile.zdsiil b/arch/z80/src/Makefile.zdsiil
index bce2662b7f6..810253ec03e 100644
--- a/arch/z80/src/Makefile.zdsiil
+++ b/arch/z80/src/Makefile.zdsiil
@@ -37,12 +37,16 @@
 
 ############################################################################
 # Tools
+
 SCHEDSRCDIR = $(TOPDIR)$(DELIM)sched
 ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
+ARCHCHIPDIR = $(ARCHSRCDIR)$(DELIM)chip
+ARCHCMDDIR = $(ARCHSRCDIR)$(DELIM)common
 
 WSCHEDSRCDIR = ${shell cygpath -w $(SCHEDSRCDIR)}
-WARCHSRCDIR = ${shell cygpath -w $(ARCHSRCDIR)}
-USRINCLUDES = -usrinc:'.;$(WSCHEDSRCDIR);$(WARCHSRCDIR);$(WARCHSRCDIR)\common'
+WARCHCHIPDIR = ${shell cygpath -w $(ARCHCHIPDIR)}
+WARCHCMNDIR = ${shell cygpath -w $(ARCHCMDDIR)}
+USRINCLUDES = -usrinc:'.;$(WSCHEDSRCDIR);$(WARCHCHIPDIR);$(WARCHCMNDIR)'
 
 INCLUDES = $(ARCHSTDINCLUDES) $(USRINCLUDES)
 CFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(INCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
diff --git a/arch/z80/src/Makefile.zdsiiw b/arch/z80/src/Makefile.zdsiiw
index d66a8f80056..b1503485a8c 100644
--- a/arch/z80/src/Makefile.zdsiiw
+++ b/arch/z80/src/Makefile.zdsiiw
@@ -39,7 +39,7 @@
 
 SCHEDSRCDIR = $(TOPDIR)$(DELIM)sched
 ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
-USRINCLUDES = -usrinc:".;$(SCHEDSRCDIR);$(ARCHSRCDIR);$(ARCHSRCDIR)\common"
+USRINCLUDES = -usrinc:".;$(SCHEDSRCDIR);$(ARCHSRCDIR)$(DELIM)chip;$(ARCHSRCDIR)$(DELIM)common"
 
 INCLUDES = $(ARCHSTDINCLUDES) $(USRINCLUDES)
 CFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(INCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
diff --git a/arch/z80/src/common/up_doirq.c b/arch/z80/src/common/up_doirq.c
index 878594a126c..5bfb42131d1 100644
--- a/arch/z80/src/common/up_doirq.c
+++ b/arch/z80/src/common/up_doirq.c
@@ -47,27 +47,13 @@
 #include 
 #include 
 
+#include 
+
 #include "chip/switch.h"
 #include "up_internal.h"
 
 #include "group/group.h"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
diff --git a/arch/z80/src/common/up_initialize.c b/arch/z80/src/common/up_initialize.c
index 4f836eb630b..eb286638ffd 100644
--- a/arch/z80/src/common/up_initialize.c
+++ b/arch/z80/src/common/up_initialize.c
@@ -48,6 +48,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/arch/z80/src/ez80/Kconfig b/arch/z80/src/ez80/Kconfig
index 7529e2c7adc..d8bee2483d8 100644
--- a/arch/z80/src/ez80/Kconfig
+++ b/arch/z80/src/ez80/Kconfig
@@ -22,6 +22,14 @@ config EZ80_UART2
 	select UART2_SERIALDRIVER
 	default n
 
+config EZ80_I2C
+	bool "I2C"
+	default n
+
+config EZ80_SPI
+	bool "SPI"
+	default n
+
 config EZ80_EMAC
 	bool "Ethernet MAC"
 	default n
@@ -43,7 +51,7 @@ config EZ80_TOOLCHAIN_ZDSII
 
 choice
 	prompt "ZDS-II Toolchain version"
-	default EZ80_ZDSII_V521
+	default EZ80_ZDSII_V530
 
 config EZ80_ZDSII_V511
 	bool "ZDS-II 5.1.1"
@@ -51,6 +59,9 @@ config EZ80_ZDSII_V511
 config EZ80_ZDSII_V521
 	bool "ZDS-II 5.2.1"
 
+config EZ80_ZDSII_V530
+	bool "ZDS-II 5.3.0"
+
 endchoice # ZDS-II Toolchain version
 
 if EZ80_EMAC
diff --git a/arch/z80/src/ez80/Make.defs b/arch/z80/src/ez80/Make.defs
index 5b4defd8e78..43e95b98dff 100644
--- a/arch/z80/src/ez80/Make.defs
+++ b/arch/z80/src/ez80/Make.defs
@@ -53,14 +53,18 @@ endif
 CHIP_SSRCS  =
 CHIP_CSRCS  = ez80_clock.c ez80_initialstate.c ez80_irq.c ez80_copystate.c
 CHIP_CSRCS += ez80_schedulesigaction.c ez80_sigdeliver.c ez80_lowuart.c
-CHIP_CSRCS += ez80_serial.c ez80_spi.c ez80_i2c.c ez80_registerdump.c
+CHIP_CSRCS += ez80_timerisr.c ez80_serial.c ez80_registerdump.c
 
-ifneq ($(CONFIG_SCHED_TICKLESS),y)
-CHIP_CSRCS += ez80_timerisr.c
+ifneq ($(CONFIG_EZ80_I2C),y)
+CHIP_CSRCS += ez80_i2c.c
+endif
+
+ifneq ($(CONFIG_EZ80_SPI),y)
+CHIP_CSRCS += ez80_spi.c
 endif
 
 ifeq ($(CONFIG_ARCH_CHIP_EZ80F91),y)
 ifeq ($(CONFIG_EZ80_EMAC),y)
-CHIP_CSRCS	+= ez80_emac.c
+CHIP_CSRCS += ez80_emac.c
 endif
 endif
diff --git a/arch/z80/src/ez80/chip.h b/arch/z80/src/ez80/chip.h
index 637a0cd3e02..a3c04736e5c 100644
--- a/arch/z80/src/ez80/chip.h
+++ b/arch/z80/src/ez80/chip.h
@@ -58,7 +58,7 @@
 #define EZ80_Z_FLAG            0x40        /* Bit 5: Zero flag */
 #define EZ80_S_FLAG            0x80        /* Bit 7: Sign flag */
 
-/* Include chip-specific regiser definitions */
+/* Include chip-specific register definitions */
 
 #if defined(CONFIG_ARCH_CHIP_EZ80F91)
 #  include "ez80f91.h"
diff --git a/arch/z80/src/ez80/ez80_i2c.c b/arch/z80/src/ez80/ez80_i2c.c
index 1c30139ddb5..b70ef737804 100644
--- a/arch/z80/src/ez80/ez80_i2c.c
+++ b/arch/z80/src/ez80/ez80_i2c.c
@@ -208,65 +208,65 @@ static uint16_t ez80_i2c_getccr(uint32_t fscl)
    *   fscl = sysclock / 10 / (M + 1) / 2**N
    *        = fsamp / 10 / (M + 1)
    *
-   * The fsmp must be >= 10 * fscl.  The best solution is the smallest value of
-   * N so that the sampling rate is the highest subject to:
+   * The fsmp must be >= 10 * fscl.  The best solution is the smallest value
+   * of N so that the sampling rate is the highest subject to:
    *
    * The minimum value of the fsamp is given by:
    */
 
    fsamp = 10 * fscl;
 
-   /* Now, serarch for the smallest value of N that results in the actual
-    * fsamp >= the ideal fsamp.  Fortunately, we only have to check at most
-    * eight values.
-    */
+  /* Now, serarch for the smallest value of N that results in the actual
+   * fsamp >= the ideal fsamp.  Fortunately, we only have to check at most
+   * eight values.
+   */
 
-   if (fsamp >= EZ80_SYS_CLK_FREQ)
-     {
-       ftmp = EZ80_SYS_CLK_FREQ / 10;
-       n    = 0;
-     }
-   else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 1))
-     {
-       ftmp = (EZ80_SYS_CLK_FREQ >> 1) / 10;
-       n    = 1;
-     }
-   else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 2))
-     {
-       ftmp = (EZ80_SYS_CLK_FREQ >> 2) / 10;
-       n    = 2;
-     }
-   else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 3))
-     {
-       ftmp = (EZ80_SYS_CLK_FREQ >> 3) / 10;
-       n    = 3;
-     }
-   else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 4))
-     {
-       ftmp = (EZ80_SYS_CLK_FREQ >> 4) / 10;
-       n     = 4;
-     }
-   else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 5))
-     {
-       ftmp = (EZ80_SYS_CLK_FREQ >> 5) / 10;
-       n    = 5;
-     }
-   else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 6))
-     {
-       ftmp = (EZ80_SYS_CLK_FREQ >> 6) / 10;
-       n     = 6;
-     }
-   else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 7))
-     {
-       ftmp  = (EZ80_SYS_CLK_FREQ >> 7) / 10;
-       n     = 7;
-     }
-   else
-     {
-       ftmp  = (EZ80_SYS_CLK_FREQ >> 7) / 10;
-       fscl  = ftmp;
-       n     = 7;
-     }
+  if (fsamp >= EZ80_SYS_CLK_FREQ)
+    {
+      ftmp = EZ80_SYS_CLK_FREQ / 10;
+      n    = 0;
+    }
+  else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 1))
+    {
+      ftmp = (EZ80_SYS_CLK_FREQ >> 1) / 10;
+      n    = 1;
+    }
+  else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 2))
+    {
+      ftmp = (EZ80_SYS_CLK_FREQ >> 2) / 10;
+      n    = 2;
+    }
+  else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 3))
+    {
+      ftmp = (EZ80_SYS_CLK_FREQ >> 3) / 10;
+      n    = 3;
+    }
+  else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 4))
+    {
+      ftmp = (EZ80_SYS_CLK_FREQ >> 4) / 10;
+      n     = 4;
+    }
+  else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 5))
+    {
+      ftmp = (EZ80_SYS_CLK_FREQ >> 5) / 10;
+      n    = 5;
+    }
+  else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 6))
+    {
+      ftmp = (EZ80_SYS_CLK_FREQ >> 6) / 10;
+      n     = 6;
+    }
+  else if (fsamp >= (EZ80_SYS_CLK_FREQ >> 7))
+    {
+      ftmp  = (EZ80_SYS_CLK_FREQ >> 7) / 10;
+      n     = 7;
+    }
+  else
+    {
+      ftmp  = (EZ80_SYS_CLK_FREQ >> 7) / 10;
+      fscl  = ftmp;
+      n     = 7;
+    }
 
   /* Finally, get M:
    *
@@ -291,9 +291,10 @@ static uint16_t ez80_i2c_getccr(uint32_t fscl)
  * Name: ez80_i2c_waitiflg
  *
  * Description:
- *   In polled mode, we have to spin until the IFLG bit in the xxx register
- *   goes to 1, signalling that the last send or receive is complete.  This
- *   could be used to generate an interrupt for a non-polled driver.
+ *   In polled mode, we have to spin until the IFLG bit in the I2C_CTL
+ *   register goes to 1, signaling that the last send or receive is
+ *   complete.  This could be used to generate an interrupt for a non-
+ *   polled driver.
  *
  * Input Parameters:
  *   priv -    Device-specific state data
@@ -383,7 +384,7 @@ static void ez80_i2c_stop(void)
  *   Send the 8- or 11-bit address for either a read or a write transaction.
  *
  * Input Parameters:
- *   priv -    Device-specific state data
+ *   priv    - Device-specific state data
  *   readbit - 0 or I2C_READBIT
  *
  * Returned Value:
@@ -410,7 +411,7 @@ static int ez80_i2c_sendaddr(struct ez80_i2cdev_s *priv, uint8_t readbit)
     {
       /* This error should never occur */
 
-      _err("ERROR: Bad START status: %02x\n", sr);
+      i2cerr("ERROR: Bad START status: %02x\n", sr);
       ez80_i2c_clriflg();
       return -EIO;
     }
@@ -432,7 +433,7 @@ static int ez80_i2c_sendaddr(struct ez80_i2cdev_s *priv, uint8_t readbit)
       sr = ez80_i2c_waitiflg();
       if (sr != I2C_SR_MADDRWRACK && sr != I2C_SR_MADDRWR)
         {
-          _err("ERROR: Bad ADDR8 status: %02x\n", sr);
+          i2cerr("ERROR: Bad ADDR8 status: %02x\n", sr);
           goto failure;
         }
     }
@@ -451,7 +452,7 @@ static int ez80_i2c_sendaddr(struct ez80_i2cdev_s *priv, uint8_t readbit)
       sr = ez80_i2c_waitiflg();
       if (sr != I2C_SR_MADDRWRACK && sr != I2C_SR_MADDRWR)
         {
-         _err("ERROR: Bad ADDR10H status: %02x\n", sr);
+         i2cerr("ERROR: Bad ADDR10H status: %02x\n", sr);
          goto failure;
         }
 
@@ -465,7 +466,7 @@ static int ez80_i2c_sendaddr(struct ez80_i2cdev_s *priv, uint8_t readbit)
       sr = ez80_i2c_waitiflg();
       if (sr != I2C_SR_MADDR2WRACK && sr != I2C_SR_MADDR2WR)
         {
-          _err("ERROR: Bad ADDR10L status: %02x\n", sr);
+          i2cerr("ERROR: Bad ADDR10L status: %02x\n", sr);
           goto failure;
         }
     }
@@ -480,17 +481,18 @@ failure:
     {
       case I2C_SR_ARBLOST1: /* Arbitration lost in address or data byte */
       case I2C_SR_ARBLOST2: /* Arbitration lost in address as master, slave
-                             * address and Write bit received, ACK transmitted */
+                             * address and Write bit received, ACK
+                             * transmitted */
       case I2C_SR_ARBLOST3: /* Arbitration lost in address as master, General
                              * Call address received, ACK transmitted */
       case I2C_SR_ARBLOST4: /* Arbitration lost in address as master, slave
                              * address and Read bit received, ACK transmitted */
-        _err("ERROR: Arbitration lost: %02x\n", sr);
+        i2cerr("ERROR: Arbitration lost: %02x\n", sr);
         ez80_i2c_clriflg();
         return -EAGAIN;
 
       default:
-        _err("ERROR: Unexpected status: %02x\n", sr);
+        i2cerr("ERROR: Unexpected status: %02x\n", sr);
         ez80_i2c_clriflg();
         return -EIO;
     }
@@ -511,7 +513,8 @@ failure:
  *
  * Input Parameters:
  *   dev    - Device-specific state data
- *   buffer - A pointer to a buffer of data to receive the data from the device
+ *   buffer - A pointer to a buffer of data to receive the data from the
+ *            device
  *   buflen - The requested number of bytes to be read
  *   flags  - Determines is a START and/or STOP indication is needed.
  *
@@ -598,61 +601,64 @@ static int ez80_i2c_read_transfer(FAR struct ez80_i2cdev_s *priv,
           /* Data byte received in MASTER mode, ACK transmitted */
 
           if (regval == I2C_SR_MDATARDACK)
-          {
-            /* Since we just ACKed the incoming byte, it must NOT be the last */
+            {
+              /* Since we just ACKed the incoming byte, it must NOT be the
+               * last
+               */
 
-            DEBUGASSERT(count > 1);
+              DEBUGASSERT(count > 1);
 
-            /* Receive the data and clear the IFLGS */
+              /* Receive the data and clear the IFLGS */
 
-            *ptr++ = inp(EZ80_I2C_DR);
-            ez80_i2c_clriflg();
-          }
+              *ptr++ = inp(EZ80_I2C_DR);
+              ez80_i2c_clriflg();
+            }
 
-        /* Data byte received in MASTER mode, NACK transmitted */
+          /* Data byte received in MASTER mode, NACK transmitted */
 
-        else if (regval == I2C_SR_MDATARDNAK)
-          {
-            /* Since we just NACKed the incoming byte, it must be the last */
+          else if (regval == I2C_SR_MDATARDNAK)
+            {
+              /* Since we just NACKed the incoming byte, it must be the last */
 
-            DEBUGASSERT(count <= 1);
+              DEBUGASSERT(count <= 1);
 
               if ((flags & EZ80_NOSTOP) == 0)
                 {
                   /* When all bytes are received and the NACK has been sent,
                    * then the microcontroller must write 1 to the STP bit in
                    * the I2C_CTL register. The I2C then transmits a STOP
-                   * condition, clears the STP bit and returns to an idle state.
+                   * condition, clears the STP bit and returns to an idle
+                   * state.
                    */
 
                   ez80_i2c_stop();
                 }
 
-            ez80_i2c_clriflg();
-            return OK;
-          }
+              ez80_i2c_clriflg();
+              return OK;
+            }
 
-        /* Arbitration lost in address or data byte */
+          /* Arbitration lost in address or data byte */
 
-        else if (regval == I2C_SR_ARBLOST1)
-          {
-            /* Clear the IFLG and break out of the inner loop.
-             * this will cause the whole transfer to start over
-             */
+          else if (regval == I2C_SR_ARBLOST1)
+            {
+              /* Clear the IFLG and break out of the inner loop.
+               * this will cause the whole transfer to start over
+               */
 
-            _err("ERROR: Arbitration lost: %02x\n", regval);
-            ez80_i2c_clriflg();
-            break;
-          }
+              i2cerr("ERROR: Arbitration lost: %02x\n", regval);
+              ez80_i2c_clriflg();
+              break;
+            }
 
-        /* Unexpected status response */
+          /* Unexpected status response */
 
-        else
-          {
-            _err("ERROR: Unexpected status: %02x\n", regval);
-            ez80_i2c_clriflg();
-            return-EIO;
-          }
+          else
+            {
+              i2cerr("ERROR: Unexpected status: %02x\n", regval);
+              ez80_i2c_clriflg();
+              return -EIO;
+            }
         }
     }
 
@@ -669,8 +675,9 @@ static int ez80_i2c_read_transfer(FAR struct ez80_i2cdev_s *priv,
  *   and pend until this write completes. Required.
  *
  * Input Parameters:
- *   dev -    Device-specific state data
- *   buffer - A pointer to the read-only buffer of data to be written to device
+ *   dev    - Device-specific state data
+ *   buffer - A pointer to the read-only buffer of data to be written to
+ *            device
  *   buflen - The number of bytes to send from the buffer
  *   flags  - Determines is a START and/or STOP indication is needed.
  *
@@ -725,8 +732,8 @@ static int ez80_i2c_write_transfer(FAR struct ez80_i2cdev_s *priv,
       ptr = buffer;
       for (count = buflen; count; count--)
         {
-          /* Load the I2C_DR with next data byte and clear the IFLG.  Clearing
-           * the IFLAG will cause the data to be transferred.
+          /* Load the I2C_DR with next data byte and clear the IFLG.
+           * Clearing the IFLAG will cause the data to be transferred.
            */
 
           outp(EZ80_I2C_DR, *ptr++);
@@ -737,15 +744,15 @@ static int ez80_i2c_write_transfer(FAR struct ez80_i2cdev_s *priv,
           sr = ez80_i2c_waitiflg();
           if (sr != I2C_SR_MDATAWRACK && sr != I2C_SR_MDATAWR)
             {
-              _err("ERROR: Bad DATA status: %02x\n", sr);
+              i2cerr("ERROR: Bad DATA status: %02x\n", sr);
               ez80_i2c_clriflg();
               if (sr == I2C_SR_ARBLOST1)
                 {
-                   /* Arbitration lost, break out of the inner loop and
-                    * try sending the message again
-                    */
+                  /* Arbitration lost, break out of the inner loop and
+                   * try sending the message again
+                   */
 
-                   break;
+                  break;
                 }
 
               /* Otherwise, it is fatal (shouldn't happen) */
@@ -879,7 +886,8 @@ static int ez80_i2c_transfer(FAR struct i2c_master_s *dev,
 
           next = &msgs[i + 1];
           if ((msg->flags & I2C_M_NOSTART) != 0 &&
-              (msg->flags & (I2C_M_READ | I2C_M_TEN)) == (next->flags & (I2C_M_READ | I2C_M_TEN)) &&
+              (msg->flags & (I2C_M_READ | I2C_M_TEN)) ==
+              (next->flags & (I2C_M_READ | I2C_M_TEN)) &&
               msg->addr == next->addr)
             {
               nostop = true;
@@ -891,11 +899,13 @@ static int ez80_i2c_transfer(FAR struct i2c_master_s *dev,
       flags |= (nostop) ? EZ80_NOSTOP : 0;
       if ((msg->flags & I2C_M_READ) != 0)
         {
-          ret = ez80_i2c_read_transfer(priv, msg->buffer, msg->length, flags);
+          ret = ez80_i2c_read_transfer(priv, msg->buffer, msg->length,
+                                       flags);
         }
       else
         {
-          ret = ez80_i2c_write_transfer(priv, msg->buffer, msg->length, flags);
+          ret = ez80_i2c_write_transfer(priv, msg->buffer, msg->length,
+                                        flags);
         }
 
       /* Check for I2C transfer errors */
@@ -930,10 +940,10 @@ static int ez80_i2c_transfer(FAR struct i2c_master_s *dev,
  *   different frequency and slave address.
  *
  * Input Parameters:
- *   Port number (for hardware that has mutiple I2C interfaces)
+ *   Port number (for hardware that has multiple I2C interfaces)
  *
  * Returned Value:
- *   Valid I2C device structre reference on succcess; a NULL on failure
+ *   Valid I2C device structure reference on success; a NULL on failure
  *
  ****************************************************************************/
 
@@ -947,7 +957,7 @@ FAR struct i2c_master_s *ez80_i2cbus_initialize(int port)
     {
       /* Set up some initial BRG value */
 
-      ccr = ez80_i2c_getccr(100*1000);
+      ccr = ez80_i2c_getccr(100 * 1000);
       ez80_i2c_setccr(ccr);
 
       /* No GPIO setup is required -- I2C pints, SCL/SDA are not multiplexed */
@@ -965,8 +975,9 @@ FAR struct i2c_master_s *ez80_i2cbus_initialize(int port)
 
   /* Now, allocate an I2C instance for this caller */
 
-  i2c = (FAR struct ez80_i2cdev_s *)kmm_zalloc(sizeof(FAR struct ez80_i2cdev_s));
-  if (i2c)
+  i2c = (FAR struct ez80_i2cdev_s *)
+    kmm_zalloc(sizeof(FAR struct ez80_i2cdev_s));
+  if (i2c != NULL)
     {
       /* Initialize the allocated instance */
 
diff --git a/arch/z80/src/ez80/ez80_initialstate.c b/arch/z80/src/ez80/ez80_initialstate.c
index 727ba368be7..9e87efc0acc 100644
--- a/arch/z80/src/ez80/ez80_initialstate.c
+++ b/arch/z80/src/ez80/ez80_initialstate.c
@@ -43,22 +43,10 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "up_internal.h"
 #include "up_arch.h"
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
diff --git a/arch/z80/src/ez80/ez80_irqsave.asm b/arch/z80/src/ez80/ez80_irqsave.asm
index 75df49561ae..56aadee7f5e 100644
--- a/arch/z80/src/ez80/ez80_irqsave.asm
+++ b/arch/z80/src/ez80/ez80_irqsave.asm
@@ -38,11 +38,12 @@
 ;**************************************************************************
 
 ;**************************************************************************
-; Global Symbols Expported
+; Global Symbols Exported
 ;**************************************************************************
 
 	xdef	_up_irq_save
 	xdef	_up_irq_restore
+	xdef	_up_irq_enable
 
 ;**************************************************************************
 ; Code
@@ -93,7 +94,7 @@ _disabled:
 ;*
 ;**************************************************************************
 
-up_irq_enable:
+_up_irq_enable:
 	ld		a, i			; AF = interrupt state
 	ei						; Interrupts are enabled (does not affect F)
 	push	af				; Transfer to HL via the stack
diff --git a/arch/z80/src/ez80/ez80_lowuart.c b/arch/z80/src/ez80/ez80_lowuart.c
index 062419b54a9..6b38e03fac7 100644
--- a/arch/z80/src/ez80/ez80_lowuart.c
+++ b/arch/z80/src/ez80/ez80_lowuart.c
@@ -46,8 +46,8 @@
 #include 
 #include 
 
-#include "chip/chip.h"
-#include "common/up_internal.h"
+#include "chip.h"
+#include "up_internal.h"
 
 #ifdef USE_LOWSERIALINIT
 
diff --git a/arch/z80/src/ez80/ez80_schedulesigaction.c b/arch/z80/src/ez80/ez80_schedulesigaction.c
index 6cc6b57c66b..5a862cd9881 100644
--- a/arch/z80/src/ez80/ez80_schedulesigaction.c
+++ b/arch/z80/src/ez80/ez80_schedulesigaction.c
@@ -50,16 +50,6 @@
 #include "sched/sched.h"
 #include "up_internal.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -187,6 +177,3 @@ void up_schedule_sigaction(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* CONFIG_DISABLE_SIGNALS */
-
diff --git a/arch/z80/src/ez80/ez80_serial.c b/arch/z80/src/ez80/ez80_serial.c
index 1aa7a50c63c..8b43caaf5c5 100644
--- a/arch/z80/src/ez80/ez80_serial.c
+++ b/arch/z80/src/ez80/ez80_serial.c
@@ -53,7 +53,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "up_internal.h"
 
 #ifdef USE_SERIALDRIVER
@@ -154,6 +154,7 @@ static uart_dev_t g_uart0port =
   { 0 },                    /* closesem */
   { 0 },                    /* xmitsem */
   { 0 },                    /* recvsem */
+  { 0 },                    /* pollsem */
   {
     { 0 },                  /* xmit.sem */
     0,                      /* xmit.head */
@@ -170,6 +171,7 @@ static uart_dev_t g_uart0port =
   },
   &g_uart_ops,              /* ops */
   &g_uart0priv,             /* priv */
+  NULL,                     /* pollfds */
 };
 #endif
 
@@ -199,6 +201,7 @@ static uart_dev_t g_uart1port =
   { 0 },                    /* closesem */
   { 0 },                    /* xmitsem */
   { 0 },                    /* recvsem */
+  { 0 },                    /* pollsem */
   {
     { 0 },                  /* xmit.sem */
     0,                      /* xmit.head */
@@ -215,6 +218,7 @@ static uart_dev_t g_uart1port =
   },
   &g_uart_ops,              /* ops */
   &g_uart1priv,             /* priv */
+  NULL,                     /* pollfds */
 };
 #endif
 
diff --git a/arch/z80/src/ez80/ez80_sigdeliver.c b/arch/z80/src/ez80/ez80_sigdeliver.c
index 229d8604b92..6d7f50d5ac7 100644
--- a/arch/z80/src/ez80/ez80_sigdeliver.c
+++ b/arch/z80/src/ez80/ez80_sigdeliver.c
@@ -46,14 +46,14 @@
 #include 
 #include 
 #include 
+
+#include 
 #include 
 
 #include "chip/switch.h"
 #include "sched/sched.h"
 #include "up_internal.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -70,7 +70,6 @@
 
 void up_sigdeliver(void)
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   FAR struct tcb_s *rtcb = this_task();
   chipreg_t regs[XCPTCONTEXT_REGS];
 
@@ -142,7 +141,4 @@ void up_sigdeliver(void)
 
   board_autoled_off(LED_SIGNAL);
   ez80_restorecontext(regs);
-#endif
 }
-
-#endif /* CONFIG_DISABLE_SIGNALS */
diff --git a/arch/z80/src/ez80/ez80_spi.c b/arch/z80/src/ez80/ez80_spi.c
index 5f337d441ab..fabba0d9674 100644
--- a/arch/z80/src/ez80/ez80_spi.c
+++ b/arch/z80/src/ez80/ez80_spi.c
@@ -111,8 +111,14 @@ static const struct spi_ops_s g_spiops =
  * array with one 'struct spi_dev_s' instance per bus.
  */
 
-static struct spi_dev_s g_spidev = {&g_spiops};
-static sem_t g_exclsem = SEM_INITIALIZER(1);  /* For mutually exclusive access */
+static struct spi_dev_s g_spidev =
+{
+  &g_spiops
+};
+
+/* Semaphore supports mutually exclusive access */
+
+static sem_t g_exclsem = SEM_INITIALIZER(1);
 
 /****************************************************************************
  * Private Functions
@@ -183,10 +189,11 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
  *
  ****************************************************************************/
 
-static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
+static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
+                                 uint32_t frequency)
 {
-  /* We want select divisor to provide the highest frequency (SPIR) that does NOT
-   * exceed the requested frequency.:
+  /* We want select divisor to provide the highest frequency (SPIR) that does
+   * NOT exceed the requested frequency.:
    *
    *   SPIR <= System Clock Frequency / (2 * BRG)
    *
@@ -195,7 +202,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
    *   BRG >= System Clock Frequency / (2 * SPIR)
    */
 
-  uint32_t brg = ((EZ80_SYS_CLK_FREQ+1)/2 + frequency - 1) / frequency;
+  uint32_t brg = ((EZ80_SYS_CLK_FREQ + 1) / 2 + frequency - 1) / frequency;
 
   /* "When configured as a Master, the 16-bit divisor value must be between
    * 0003h and FFFFh, inclusive. When configured as a Slave, the 16-bit
@@ -214,7 +221,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
   outp(EZ80_SPI_BRG_L, brg & 0xff);
   outp(EZ80_SPI_BRG_L, (brg >> 8) & 0xff);
 
-  return ((EZ80_SYS_CLK_FREQ+1)/2 + brg - 1) / brg;
+  return ((EZ80_SYS_CLK_FREQ + 1) / 2 + brg - 1) / brg;
 }
 
 /****************************************************************************
@@ -241,32 +248,32 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
 
   switch (mode)
     {
-    case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */
-      modebits = 0;
-      break;
+      case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */
+        modebits = 0;
+        break;
 
-    case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */
-      modebits = SPI_CTL_CPHA;
-      break;
+      case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */
+        modebits = SPI_CTL_CPHA;
+        break;
 
-    case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */
-      modebits = SPI_CTL_CPOL;
-      break;
+      case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */
+        modebits = SPI_CTL_CPOL;
+        break;
 
-    case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
-      modebits = (SPI_CTL_CPOL|SPI_CTL_CPHA);
-      break;
+      case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
+        modebits = (SPI_CTL_CPOL | SPI_CTL_CPHA);
+        break;
 
-    default:
-      return;
+      default:
+        return;
     }
 
-    /* Then set those bits in the CTL register */
+  /* Then set those bits in the CTL register */
 
-    regval = inp(EZ80_SPI_CTL);
-    regval &= ~(SPI_CTL_CPOL|SPI_CTL_CPHA);
-    regval |= modebits;
-    outp(EZ80_SPI_CTL, regval);
+  regval  = inp(EZ80_SPI_CTL);
+  regval &= ~(SPI_CTL_CPOL | SPI_CTL_CPHA);
+  regval |= modebits;
+  outp(EZ80_SPI_CTL, regval);
 }
 
 /****************************************************************************
@@ -294,9 +301,10 @@ static uint8_t spi_waitspif(void)
 
   do
     {
-      status = inp(EZ80_SPI_SR) & (SPI_SR_SPIF|SPI_SR_WCOL|SPI_SR_MODF);
+      status = inp(EZ80_SPI_SR) & (SPI_SR_SPIF | SPI_SR_WCOL | SPI_SR_MODF);
     }
   while (status == 0);
+
   return status;
 }
 
@@ -320,7 +328,7 @@ static uint8_t spi_transfer(uint8_t ch)
 
   /* Send the byte, repeating if some error occurs */
 
-  for (;;)
+  for (; ; )
     {
       outp(EZ80_SPI_TSR, ch);
 
@@ -378,7 +386,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
 static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
                          size_t buflen)
 {
-  FAR const uint8_t *ptr = (FAR const uint8_t*)buffer;
+  FAR const uint8_t *ptr = (FAR const uint8_t *)buffer;
 
   /* Loop while there are bytes remaining to be sent */
 
@@ -397,20 +405,21 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer,
  * Input Parameters:
  *   dev -    Device-specific state data
  *   buffer - A pointer to the buffer in which to recieve data
- *   buflen - the length of data that can be received in the buffer in number
- *            of words.  The wordsize is determined by the number of bits-per-word
- *            selected for the SPI interface.  If nbits <= 8, the data is
- *            packed into uint8_t's; if nbits >8, the data is packed into
- *            uint16_t's
+ *   buflen - The length of data that can be received in the buffer in
+ *            number of words.  The wordsize is determined by the number of
+ *            bits-per-word selected for the SPI interface.  If nbits <= 8,
+ *            the data is packed into uint8_t's; if nbits >8, the data is
+ *            packed into uint16_t's
  *
  * Returned Value:
  *   None
  *
  ****************************************************************************/
 
-static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t buflen)
+static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
+                          size_t buflen)
 {
-  FAR uint8_t *ptr = (FAR uint8_t*)buffer;
+  FAR uint8_t *ptr = (FAR uint8_t *)buffer;
 
   /* Loop while thre are bytes remaining to be sent */
 
@@ -501,7 +510,7 @@ FAR struct spi_dev_s *ez80_spibus_initialize(int port)
    * NOTE 2: Initial mode is mode=0.
    */
 
-  outp(EZ80_SPI_CTL, SPI_CTL_SPIEN|SPI_CTL_MASTEREN);
+  outp(EZ80_SPI_CTL, SPI_CTL_SPIEN | SPI_CTL_MASTEREN);
 
   return &g_spidev;
 }
diff --git a/arch/z80/src/ez80/ez80_timerisr.c b/arch/z80/src/ez80/ez80_timerisr.c
index 411c844799b..6aee7ebdb00 100644
--- a/arch/z80/src/ez80/ez80_timerisr.c
+++ b/arch/z80/src/ez80/ez80_timerisr.c
@@ -45,7 +45,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "clock/clock.h"
 #include "up_internal.h"
 
diff --git a/arch/z80/src/ez80/ez80_vectors.asm b/arch/z80/src/ez80/ez80_vectors.asm
index 107b570c4be..e26bddf32cf 100644
--- a/arch/z80/src/ez80/ez80_vectors.asm
+++ b/arch/z80/src/ez80/ez80_vectors.asm
@@ -138,7 +138,7 @@ _nmi:
 					;----------------- --- ----- -----
 _ez80_handlers:
 	irqhandler	 0		; EZ80_EMACRX_IRQ   0    0   0x040
-	handlersize equ $-_ez80handlers
+	handlersize equ $-_ez80_handlers
 	irqhandler	 1		; EZ80_EMACTX_IRQ   1    1   0x044
 	irqhandler	 2		; EZ80_EMACSYS_IRQ  2    2   0x048
 	irqhandler	 3		; EZ80_PLL_IRQ      3    3   0x04c
diff --git a/arch/z80/src/ez80/ez80f91_spi.h b/arch/z80/src/ez80/ez80f91_spi.h
index 0c49cad1d7b..31aca65502e 100644
--- a/arch/z80/src/ez80/ez80f91_spi.h
+++ b/arch/z80/src/ez80/ez80f91_spi.h
@@ -1,6 +1,5 @@
 /************************************************************************************
  * arch/z80/src/ez80/ez80f91_spi.h
- * arch/z80/src/chip/ez80f91_spi.h
  *
  *   Copyright (C) 2009-2010, 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -61,7 +60,7 @@
  * No bit definitions -- These two 8-bit registers set the 16-bit BRG divider value
  */
 
-/* SPI Control (CTL} Register Definitions */
+/* SPI Control (CTL) Register Definitions */
 
 #define SPI_CTL_IRQEN    (1 << 7) /* Bit 7: 1=SPI system interrupt is enabled */
 #define SPI_CTL_SPIEN    (1 << 5) /* Bit 5: 1=SPI is enabled */
diff --git a/arch/z80/src/ez80/switch.h b/arch/z80/src/ez80/switch.h
index fae313befd3..b390cdab6bd 100644
--- a/arch/z80/src/ez80/switch.h
+++ b/arch/z80/src/ez80/switch.h
@@ -44,7 +44,7 @@
 #  include 
 #  include 
 #endif
-#include "common/up_internal.h"
+#include "up_internal.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/z80/src/z180/z180_initialstate.c b/arch/z80/src/z180/z180_initialstate.c
index f163738c916..2c54b5b3b28 100644
--- a/arch/z80/src/z180/z180_initialstate.c
+++ b/arch/z80/src/z180/z180_initialstate.c
@@ -42,7 +42,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "up_internal.h"
 #include "up_arch.h"
 
diff --git a/arch/z80/src/z180/z180_lowscc.c b/arch/z80/src/z180/z180_lowscc.c
index 59caa4c561f..c36bb9afc7e 100644
--- a/arch/z80/src/z180/z180_lowscc.c
+++ b/arch/z80/src/z180/z180_lowscc.c
@@ -46,7 +46,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "common/up_internal.h"
 #include "z180_config.h"
 
diff --git a/arch/z80/src/z180/z180_lowuart.c b/arch/z80/src/z180/z180_lowuart.c
index cd80e3987b5..18de900abcf 100644
--- a/arch/z80/src/z180/z180_lowuart.c
+++ b/arch/z80/src/z180/z180_lowuart.c
@@ -46,7 +46,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "common/up_internal.h"
 #include "z180_config.h"
 
diff --git a/arch/z80/src/z180/z180_mmu.c b/arch/z80/src/z180/z180_mmu.c
index acc9065b943..fa435c7c089 100644
--- a/arch/z80/src/z180/z180_mmu.c
+++ b/arch/z80/src/z180/z180_mmu.c
@@ -44,9 +44,10 @@
 #include 
 #include 
 
+#include 
 #include 
 
-#include 
+#include 
 #include 
 
 #include "up_internal.h"
@@ -273,7 +274,7 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
 
   /* Now allocate the physical memory to back up the address environment */
 
-  alloc = (uintptr_t)gran_alloc(npages);
+  alloc = (uintptr_t)gran_alloc(g_physhandle, npages);
   if (alloc == NULL)
     {
       serr("ERROR: Failed to allocate %d pages\n", npages);
@@ -522,7 +523,7 @@ int up_addrenv_coherent(FAR const group_addrenv_t *addrenv)
  ****************************************************************************/
 
 int up_addrenv_clone(FAR const group_addrenv_t *src,
-                     FAR group_addrenv_t *dest);
+                     FAR group_addrenv_t *dest)
 {
   DEBUGASSERT(src && dest);
 
@@ -582,7 +583,7 @@ int up_addrenv_attach(FAR struct task_group_s *group, FAR struct tcb_s *tcb)
  *
  ****************************************************************************/
 
-int up_addrenv_detach(FAR struct task_group_s *group, FAR struct tcb_s *tcb);
+int up_addrenv_detach(FAR struct task_group_s *group, FAR struct tcb_s *tcb)
 {
   /* There is nothing that needs to be done */
 
diff --git a/arch/z80/src/z180/z180_scc.c b/arch/z80/src/z180/z180_scc.c
index 72f5961edf1..78c244043e2 100644
--- a/arch/z80/src/z180/z180_scc.c
+++ b/arch/z80/src/z180/z180_scc.c
@@ -53,7 +53,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "up_internal.h"
 
 #include "z180_config.h"
diff --git a/arch/z80/src/z180/z180_schedulesigaction.c b/arch/z80/src/z180/z180_schedulesigaction.c
index c53663f783b..9c8e21a8c85 100644
--- a/arch/z80/src/z180/z180_schedulesigaction.c
+++ b/arch/z80/src/z180/z180_schedulesigaction.c
@@ -44,22 +44,15 @@
 #include 
 
 #include 
+#include 
 #include 
 
-#include "chip/switch.h"
+#include 
+
+#include "switch.h"
 #include "sched/sched.h"
 #include "up_internal.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -68,7 +61,8 @@
  * Name: z180_sigsetup
  ****************************************************************************/
 
-static void z180_sigsetup(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver, FAR chipreg_t *regs)
+static void z180_sigsetup(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver,
+                          FAR chipreg_t *regs)
 {
   /* Save the return address and interrupt state. These will be restored by
    * the signal trampoline after the signals have been delivered.
@@ -187,6 +181,3 @@ void up_schedule_sigaction(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* CONFIG_DISABLE_SIGNALS */
-
diff --git a/arch/z80/src/z180/z180_sigdeliver.c b/arch/z80/src/z180/z180_sigdeliver.c
index f0e9319ff2a..845c39aae8a 100644
--- a/arch/z80/src/z180/z180_sigdeliver.c
+++ b/arch/z80/src/z180/z180_sigdeliver.c
@@ -50,8 +50,6 @@
 #include "sched/sched.h"
 #include "up_internal.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -68,7 +66,6 @@
 
 void up_sigdeliver(void)
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   FAR struct tcb_s  *rtcb = this_task();
   chipreg_t regs[XCPTCONTEXT_REGS];
 
@@ -128,7 +125,4 @@ void up_sigdeliver(void)
 
   board_autoled_off(LED_SIGNAL);
   z180_restoreusercontext(regs);
-#endif
 }
-
-#endif /* CONFIG_DISABLE_SIGNALS */
diff --git a/arch/z80/src/z8/chip.h b/arch/z80/src/z8/chip.h
index 1e9035a3bf1..20d4477246b 100644
--- a/arch/z80/src/z8/chip.h
+++ b/arch/z80/src/z8/chip.h
@@ -1,6 +1,6 @@
 /************************************************************************************
  * arch/z80/src/z8/chip.h
- * arch/z80/src/chip/chip.h
+ * arch/z80/src/chip.h
  *
  *   Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
diff --git a/arch/z80/src/z8/switch.h b/arch/z80/src/z8/switch.h
index 7c54e34ca5e..a32308ada0c 100644
--- a/arch/z80/src/z8/switch.h
+++ b/arch/z80/src/z8/switch.h
@@ -46,7 +46,7 @@
 #  include 
 #  include 
 #endif
-#include "common/up_internal.h"
+#include "up_internal.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/arch/z80/src/z8/z8_initialstate.c b/arch/z80/src/z8/z8_initialstate.c
index 17299e17a58..9e36896e49d 100644
--- a/arch/z80/src/z8/z8_initialstate.c
+++ b/arch/z80/src/z8/z8_initialstate.c
@@ -44,7 +44,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "up_internal.h"
 #include "up_arch.h"
 
diff --git a/arch/z80/src/z8/z8_lowuart.c b/arch/z80/src/z8/z8_lowuart.c
index a568a94a9ba..4d16dd296e6 100644
--- a/arch/z80/src/z8/z8_lowuart.c
+++ b/arch/z80/src/z8/z8_lowuart.c
@@ -46,8 +46,8 @@
 #include 
 #include 
 
-#include "chip/chip.h"
-#include "common/up_internal.h"
+#include "chip.h"
+#include "up_internal.h"
 
 #ifdef USE_LOWSERIALINIT
 
diff --git a/arch/z80/src/z8/z8_schedulesigaction.c b/arch/z80/src/z8/z8_schedulesigaction.c
index 6c6b1a74b0c..3c73c516447 100644
--- a/arch/z80/src/z8/z8_schedulesigaction.c
+++ b/arch/z80/src/z8/z8_schedulesigaction.c
@@ -50,8 +50,6 @@
 #include "sched/sched.h"
 #include "up_internal.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -180,6 +178,3 @@ void up_schedule_sigaction(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* CONFIG_DISABLE_SIGNALS */
-
diff --git a/arch/z80/src/z8/z8_serial.c b/arch/z80/src/z8/z8_serial.c
index 443226259d4..cef30e31d5b 100644
--- a/arch/z80/src/z8/z8_serial.c
+++ b/arch/z80/src/z8/z8_serial.c
@@ -53,7 +53,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "up_internal.h"
 
 #ifdef USE_SERIALDRIVER
@@ -163,6 +163,7 @@ static uart_dev_t g_uart0port =
   { 0 },                    /* closesem */
   { 0 },                    /* xmitsem */
   { 0 },                    /* recvsem */
+  { 0 },                    /* pollsem */
   {
     { 0 },                  /* xmit.sem */
     0,                      /* xmit.head */
@@ -179,6 +180,7 @@ static uart_dev_t g_uart0port =
   },
   &g_uart_ops,              /* ops */
   &g_uart0priv,             /* priv */
+  NULL,                     /* pollfds */
 };
 
 /* This describes the state of the DM320 uart1 port. */
@@ -208,6 +210,7 @@ static uart_dev_t g_uart1port =
   { 0 },                    /* closesem */
   { 0 },                    /* xmitsem */
   { 0 },                    /* recvsem */
+  { 0 },                    /* pollsem */
   {
     { 0 },                  /* xmit.sem */
     0,                      /* xmit.head */
@@ -224,6 +227,7 @@ static uart_dev_t g_uart1port =
   },
   &g_uart_ops,              /* ops */
   &g_uart1priv,             /* priv */
+  NULL,                     /* pollfds */
 };
 
 /* Now, which one with be tty0/console and which tty1? */
diff --git a/arch/z80/src/z8/z8_sigdeliver.c b/arch/z80/src/z8/z8_sigdeliver.c
index 3f80b8d2456..63cc25d2078 100644
--- a/arch/z80/src/z8/z8_sigdeliver.c
+++ b/arch/z80/src/z8/z8_sigdeliver.c
@@ -51,8 +51,6 @@
 #include "sched/sched.h"
 #include "up_internal.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -88,7 +86,6 @@ static void z8_copystate(FAR chipreg_t *dest, FAR const chipreg_t *src)
 
 void up_sigdeliver(void)
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   FAR struct tcb_s *rtcb = this_task();
   chipreg_t regs[XCPTCONTEXT_REGS];
 
@@ -148,7 +145,4 @@ void up_sigdeliver(void)
 
   board_autoled_off(LED_SIGNAL);
   z8_restorecontext(regs);
-#endif
 }
-
-#endif /* CONFIG_DISABLE_SIGNALS */
diff --git a/arch/z80/src/z8/z8_timerisr.c b/arch/z80/src/z8/z8_timerisr.c
index 0363eaef202..a38598af361 100644
--- a/arch/z80/src/z8/z8_timerisr.c
+++ b/arch/z80/src/z8/z8_timerisr.c
@@ -45,7 +45,7 @@
 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "clock/clock.h"
 #include "up_internal.h"
 
diff --git a/arch/z80/src/z80/z80_initialstate.c b/arch/z80/src/z80/z80_initialstate.c
index 7191f03ebed..00c058489d1 100644
--- a/arch/z80/src/z80/z80_initialstate.c
+++ b/arch/z80/src/z80/z80_initialstate.c
@@ -42,7 +42,7 @@
 #include 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 #include "up_internal.h"
 #include "up_arch.h"
 
diff --git a/arch/z80/src/z80/z80_schedulesigaction.c b/arch/z80/src/z80/z80_schedulesigaction.c
index 2b16b8deebd..9caaac0c44a 100644
--- a/arch/z80/src/z80/z80_schedulesigaction.c
+++ b/arch/z80/src/z80/z80_schedulesigaction.c
@@ -51,8 +51,6 @@
 #include "sched/sched.h"
 #include "up_internal.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -181,5 +179,3 @@ void up_schedule_sigaction(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver)
 
   leave_critical_section(flags);
 }
-
-#endif /* CONFIG_DISABLE_SIGNALS */
diff --git a/arch/z80/src/z80/z80_sigdeliver.c b/arch/z80/src/z80/z80_sigdeliver.c
index 3089ac423fc..0689a9ba621 100644
--- a/arch/z80/src/z80/z80_sigdeliver.c
+++ b/arch/z80/src/z80/z80_sigdeliver.c
@@ -51,8 +51,6 @@
 #include "sched/sched.h"
 #include "up_internal.h"
 
-#ifndef CONFIG_DISABLE_SIGNALS
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -69,7 +67,6 @@
 
 void up_sigdeliver(void)
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   FAR struct tcb_s *rtcb = this_task();
   chipreg_t regs[XCPTCONTEXT_REGS];
 
@@ -129,7 +126,4 @@ void up_sigdeliver(void)
 
   board_autoled_off(LED_SIGNAL);
   z80_restoreusercontext(regs);
-#endif
 }
-
-#endif /* CONFIG_DISABLE_SIGNALS */
diff --git a/audio/audio.c b/audio/audio.c
index 848a7b04964..25371770f8a 100644
--- a/audio/audio.c
+++ b/audio/audio.c
@@ -122,11 +122,9 @@ static const struct file_operations g_audioops =
   audio_close, /* close */
   audio_read,  /* read */
   audio_write, /* write */
-  0,           /* seek */
-  audio_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0          /* poll */
-#endif
+  NULL,        /* seek */
+  audio_ioctl, /* ioctl */
+  NULL         /* poll */
 };
 
 /****************************************************************************
diff --git a/configs/Board.mk b/configs/Board.mk
index 076de67c4ea..db423ccec99 100644
--- a/configs/Board.mk
+++ b/configs/Board.mk
@@ -58,9 +58,9 @@ ifneq ($(ZDSVERSION),)
 ifeq ($(WINTOOL),y)
   WSCHEDSRCDIR = ${shell cygpath -w $(SCHEDSRCDIR)}
   WARCHSRCDIR = ${shell cygpath -w $(ARCHSRCDIR)}
-  USRINCLUDES = -usrinc:'.;$(WSCHEDSRCDIR);$(WARCHSRCDIR);$(WARCHSRCDIR)\common'
+  USRINCLUDES = -usrinc:'.;$(WSCHEDSRCDIR);$(WARCHSRCDIR)$(DELIM)chip;$(WARCHSRCDIR)$(DELIM)common'
 else
-  USRINCLUDES = -usrinc:".;$(SCHEDSRCDIR);$(ARCHSRCDIR);$(ARCHSRCDIR)\common"
+  USRINCLUDES = -usrinc:".;$(SCHEDSRCDIR);$(ARCHSRCDIR)$(DELIMI)chip;$(ARCHSRCDIR)$(DELIM)common"
 endif
 else
 ifeq ($(WINTOOL),y)
diff --git a/configs/Kconfig b/configs/Kconfig
index b40474c8542..11c4c4ba137 100644
--- a/configs/Kconfig
+++ b/configs/Kconfig
@@ -49,6 +49,16 @@ config ARCH_BOARD_AVR32DEV1
 		Atmel website.  STATUS: This port is functional but very basic.  There
 		are configurations for NSH and the OS test.
 
+config ARCH_BOARD_AXOLOTI
+	bool "Axoloti board"
+	depends on ARCH_CHIP_STM32F427I
+	select ARCH_HAVE_LEDS
+	select ARCH_HAVE_BUTTONS
+	select ARCH_HAVE_IRQBUTTONS
+	---help---
+		Axoloti synthesizer board based on the STMicro STM32F427IGH6 MCU.
+		See: http://www.axoloti.com/
+
 config ARCH_BOARD_C5471EVM
 	bool "Spectrum Digital C5471 evaluation board"
 	depends on ARCH_CHIP_C5471
@@ -601,6 +611,17 @@ config ARCH_BOARD_LPC1766STK
 		This port uses the Olimex LPC1766-STK board and a GNU GCC toolchain* under
 		Linux or Cygwin.  STATUS: Complete and mature.
 
+config ARCH_BOARD_MAKERLISP
+	bool "MakerLisp"
+	depends on ARCH_CHIP_EZ80F91
+	select ARCH_HAVE_LEDS
+	---help---
+		ez80Acclaim! Microcontroller.  This port use the MakerLips machine
+		based on an eZ80F091 part, and the Zilog ZDS-II Windows command line
+		tools.  The development environment is Cygwin under Windows. A
+		Windows native development environment is available but has not
+		been verified.
+
 config ARCH_BOARD_MAPLE
 	bool "maple board"
 	depends on ARCH_CHIP_STM32F103RB || ARCH_CHIP_STM32F103CB
@@ -1034,6 +1055,16 @@ config ARCH_BOARD_NUCLEO_F446RE
 		This is a minimal configuration that supports low-level test of the
 		Nucleo F446RE in the NuttX source tree.
 
+config ARCH_BOARD_NUCLEO_G071RB
+	bool "STM32G071 Nucleo G071RB"
+	depends on ARCH_CHIP_STM32G071RB
+	select ARCH_HAVE_LEDS
+	select ARCH_HAVE_BUTTONS
+	select ARCH_HAVE_IRQBUTTONS
+	---help---
+		This is a minimal configuration that supports low-level test of the
+		Nucleo G071RB in the NuttX source tree.
+
 config ARCH_BOARD_NUCLEO_H743ZI
 	bool "STM32H743 Nucleo H743ZI"
 	depends on ARCH_CHIP_STM32H743ZI
@@ -1492,7 +1523,7 @@ config ARCH_BOARD_STM32L_DISCOVERY
 	select ARCH_HAVE_IRQBUTTONS
 	---help---
 		STMicro STM32L-Discovery board based on the STMicro STM32L152RBT6 or
-		STM32L1 MCUs.
+		STM32L152RCT6 MCUs.
 
 config ARCH_BOARD_STM32VL_DISCOVERY
 	bool "STMicro STM32VL-Discovery board"
@@ -1713,6 +1744,16 @@ config ARCH_BOARD_ZKITARM
 		Zilogic System's ARM development Kit, ZKIT-ARM-1769.  This board is based
 		on the NXP LPC1769.  The Nuttx Buildroot toolchain is used by default.
 
+config ARCH_BOARD_SPRESENSE
+	bool "Sony Spresense Board"
+	depends on ARCH_CHIP_CXD56XX
+	select ARCH_HAVE_LEDS
+	select ARCH_HAVE_BUTTONS
+	select ARCH_HAVE_IRQBUTTONS
+	select ARCH_HAVE_POWEROFF
+	---help---
+		none
+
 config ARCH_BOARD_SIM
 	bool "User mode simulation"
 	depends on ARCH_SIM
@@ -1794,6 +1835,7 @@ config ARCH_BOARD
 	default "arduino-mega2560"         if ARCH_BOARD_ARDUINO_MEGA2560
 	default "arduino-due"              if ARCH_BOARD_ARDUINO_DUE
 	default "avr32dev1"                if ARCH_BOARD_AVR32DEV1
+	default "axoloti"                  if ARCH_BOARD_AXOLOTI
 	default "bambino-200e"             if ARCH_BOARD_BAMBINO_200E
 	default "c5471evm"                 if ARCH_BOARD_C5471EVM
 	default "clicker2-stm32"           if ARCH_BOARD_CLICKER2_STM32
@@ -1839,6 +1881,7 @@ config ARCH_BOARD
 	default "lpcxpresso-lpc1768"       if ARCH_BOARD_LPCXPRESSO
 	default "lpcxpresso-lpc54628"      if ARCH_BOARD_LPCXPRESSO_LPC54628
 	default "maple"                    if ARCH_BOARD_MAPLE
+	default "makerlisp"                if ARCH_BOARD_MAKERLISP
 	default "max32660-evsys"           if ARCH_BOARD_MAX32660_EVSYS
 	default "mbed"                     if ARCH_BOARD_MBED
 	default "mcb1700"                  if ARCH_BOARD_MCB1700
@@ -1863,6 +1906,7 @@ config ARCH_BOARD
 	default "nucleo-f4x1re"            if ARCH_BOARD_NUCLEO_F401RE || ARCH_BOARD_NUCLEO_F411RE
 	default "nucleo-f446re"            if ARCH_BOARD_NUCLEO_F446RE
 	default "nucleo-f410rb"            if ARCH_BOARD_NUCLEO_F410RB
+	default "nucleo-g071rb"            if ARCH_BOARD_NUCLEO_G071RB
 	default "nucleo-h743zi"            if ARCH_BOARD_NUCLEO_H743ZI
 	default "nucleo-l073rz"            if ARCH_BOARD_NUCLEO_L073RZ
 	default "nucleo-l152re"            if ARCH_BOARD_NUCLEO_L152RE
@@ -1959,6 +2003,7 @@ config ARCH_BOARD
 	default "zkit-arm-1769"            if ARCH_BOARD_ZKITARM
 	default "sim"                      if ARCH_BOARD_SIM
 	default "moxa"                     if ARCH_BOARD_MOXA
+	default "spresense"                if ARCH_BOARD_SPRESENSE
 
 comment "Common Board Options"
 
@@ -2136,6 +2181,9 @@ endif
 if ARCH_BOARD_LPCXPRESSO_LPC54628
 source "configs/lpcxpresso-lpc54628/Kconfig"
 endif
+if ARCH_BOARD_MAKERLISP
+source "configs/makerlisp/Kconfig"
+endif
 if ARCH_BOARD_MAPLE
 source "configs/maple/Kconfig"
 endif
@@ -2217,6 +2265,9 @@ endif
 if ARCH_BOARD_NUCLEO_F410RB
 source "configs/nucleo-f410rb/Kconfig"
 endif
+if ARCH_BOARD_NUCLEO_G071RB
+source "configs/nucleo-g071rb/Kconfig"
+endif
 if ARCH_BOARD_NUCLEO_H743ZI
 source "configs/nucleo-h743zi/Kconfig"
 endif
@@ -2484,6 +2535,9 @@ endif
 if ARCH_BOARD_ZKITARM
 source "configs/zkit-arm-1769/Kconfig"
 endif
+if ARCH_BOARD_SPRESENSE
+source "configs/spresense/Kconfig"
+endif
 if ARCH_BOARD_SIM
 source "configs/sim/Kconfig"
 endif
diff --git a/configs/Makefile b/configs/Makefile
index cee8bdafed8..b0c3508f518 100644
--- a/configs/Makefile
+++ b/configs/Makefile
@@ -65,7 +65,7 @@ BOARD_INSTALLED = $(if $(wildcard $(BOARD_DIR)$(DELIM)Makefile),y,)
 # Basic
 
 CONFIG_ASRCS =
-CONFIG_CSRCS =
+CONFIG_CSRCS = dummy.c
 CONFIG_CXXSRCS =
 
 # boardctl support
@@ -83,8 +83,8 @@ COBJS = $(CSRCS:.c=$(OBJEXT))
 CXXSRCS = $(CONFIG_CXXSRCS)
 CXXOBJS = $(CXXSRCS:.cxx=$(OBJEXT))
 
-SRCS = $(ASRCS) $(CSRCS)
-OBJS = $(AOBJS) $(COBJS)
+SRCS = $(ASRCS) $(CSRCS) $(CXXSRCS)
+OBJS = $(AOBJS) $(COBJS) $(CXXOBJS)
 
 BIN = libconfigs$(LIBEXT)
 
@@ -100,10 +100,10 @@ $(COBJS): %$(OBJEXT): %.c
 $(CXXOBJS): %$(OBJEXT): %.cxx
 	$(call COMPILEXX, $<, $@)
 
-$(BIN): $(OBJS) $(CXXOBJS)
-	$(call ARCHIVE, $@, $(OBJS) $(CXXOBJS))
+$(BIN): $(OBJS)
+	$(call ARCHIVE, $@, $(OBJS))
 
-.depend: Makefile $(SRCS) $(CXXSRCS)
+.depend: Makefile $(SRCS)
 ifneq ($(SRCS),)
 	$(Q) $(MKDEP) --dep-path . "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep
 endif
diff --git a/configs/README.txt b/configs/README.txt
index 82cb757c51a..af3740039a2 100644
--- a/configs/README.txt
+++ b/configs/README.txt
@@ -183,6 +183,10 @@ configs/avr32dev1
   Atmel website.  STATUS: This port is functional but very basic.  There
   are configurations for NSH and the OS test.
 
+configs/axoloti
+  Support for the Axoloti synthesizer board based on the STMicro
+  STM32F427IGH6 MCU.  See: http://www.axoloti.com/
+
 configs/b-l072z-lrwan1
   STMicro STM32L0 Discovery kit with LoRa/SigFox based on STM32L072CZ MCU.
 
@@ -364,6 +368,12 @@ configs/lpc4370-link2
   LPC4370FET100 MCU.  Based on the LPC4300 Xplorer port and provided by
   Lok Tep.
 
+configs/makerlisp
+  This port use the MakerLips machine based on an eZ80F091 ez80Acclaim!
+  Microcontroller, and the Zilog ZDS-II Windows command line tools.  The
+  development environment is Cygwin under Windows. A Windows native
+  development environment is available but has not been verified.
+
 configs/maple
   NuttX support for the LeafLab's Maple and Maple Mini boards. These boards
   are based on the STM32F103RBT6 chip for the standard version and on the
diff --git a/configs/amber/hello/defconfig b/configs/amber/hello/defconfig
index 17b06e87db7..1fd8582c7b9 100644
--- a/configs/amber/hello/defconfig
+++ b/configs/amber/hello/defconfig
@@ -19,9 +19,7 @@ CONFIG_DEFAULT_SMALL=y
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_IDLETHREAD_STACKSIZE=512
diff --git a/configs/arduino-due/README.txt b/configs/arduino-due/README.txt
index a81bd42ad92..35b68618b66 100644
--- a/configs/arduino-due/README.txt
+++ b/configs/arduino-due/README.txt
@@ -845,9 +845,6 @@ Configuration sub-directories
          CONFIG_SAM34_GPIO_IRQ=y           : GPIO interrupt support
          CONFIG_SAM34_GPIOC_IRQ=y          : Enable GPIO interrupts from port C
 
-       RTOS Features:
-         CONFIG_DISABLE_SIGNALS=n          : Signals are required
-
        Library Support:
          CONFIG_SCHED_WORKQUEUE=y          : Work queue support required
 
diff --git a/configs/arduino-due/src/arduino-due.h b/configs/arduino-due/src/arduino-due.h
index 780385deddb..3036c2c8d99 100644
--- a/configs/arduino-due/src/arduino-due.h
+++ b/configs/arduino-due/src/arduino-due.h
@@ -48,7 +48,7 @@
 #include 
 #include 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/configs/arduino-due/src/sam_mmcsd.c b/configs/arduino-due/src/sam_mmcsd.c
index e6d461d58fa..2d0e0e21554 100644
--- a/configs/arduino-due/src/sam_mmcsd.c
+++ b/configs/arduino-due/src/sam_mmcsd.c
@@ -49,7 +49,7 @@
 
 #include "up_arch.h"
 #include "sam_gpio.h"
-#include "chip/sam3u_pio.h"
+#include "hardware/sam3u_pio.h"
 
 #include "arduino-due.h"
 
diff --git a/configs/arduino-due/src/sam_touchscreen.c b/configs/arduino-due/src/sam_touchscreen.c
index 48dae4c1625..67d8d7e7025 100644
--- a/configs/arduino-due/src/sam_touchscreen.c
+++ b/configs/arduino-due/src/sam_touchscreen.c
@@ -53,7 +53,7 @@
 
 #include "up_arch.h"
 #include "sam_gpio.h"
-#include "chip/sam3u_pio.h"
+#include "hardware/sam3u_pio.h"
 
 #include "arduino-due.h"
 
diff --git a/configs/arduino-mega2560/hello/defconfig b/configs/arduino-mega2560/hello/defconfig
index 7c35dc2f920..afcf3f4f75d 100644
--- a/configs/arduino-mega2560/hello/defconfig
+++ b/configs/arduino-mega2560/hello/defconfig
@@ -20,9 +20,7 @@ CONFIG_DEFAULT_SMALL=y
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_IDLETHREAD_STACKSIZE=128
diff --git a/configs/arduino-mega2560/nsh/defconfig b/configs/arduino-mega2560/nsh/defconfig
index c6dff947c2e..08a5a640cbc 100644
--- a/configs/arduino-mega2560/nsh/defconfig
+++ b/configs/arduino-mega2560/nsh/defconfig
@@ -21,9 +21,7 @@ CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_IDLETHREAD_STACKSIZE=128
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/avr32dev1/nsh/defconfig b/configs/avr32dev1/nsh/defconfig
index 2e745e2b5ef..da78afddadf 100644
--- a/configs/avr32dev1/nsh/defconfig
+++ b/configs/avr32dev1/nsh/defconfig
@@ -21,7 +21,6 @@ CONFIG_AVR32_GPIOIRQSETA=0
 CONFIG_AVR32_GPIOIRQSETB=0x0000000c
 CONFIG_AVR32_USART1=y
 CONFIG_BOARD_LOOPSPERMSEC=1140
-CONFIG_DISABLE_POLL=y
 CONFIG_ENDIAN_BIG=y
 CONFIG_FS_FAT=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/avr32dev1/ostest/defconfig b/configs/avr32dev1/ostest/defconfig
index eaea659169a..bdb8d324242 100644
--- a/configs/avr32dev1/ostest/defconfig
+++ b/configs/avr32dev1/ostest/defconfig
@@ -22,7 +22,6 @@ CONFIG_BOARD_LOOPSPERMSEC=1140
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_ENDIAN_BIG=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/axoloti/Kconfig b/configs/axoloti/Kconfig
new file mode 100644
index 00000000000..cc8297892e0
--- /dev/null
+++ b/configs/axoloti/Kconfig
@@ -0,0 +1,8 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_AXOLOTI
+
+endif
diff --git a/configs/axoloti/README.txt b/configs/axoloti/README.txt
new file mode 100644
index 00000000000..ee0bc922517
--- /dev/null
+++ b/configs/axoloti/README.txt
@@ -0,0 +1,20 @@
+README
+======
+
+This README discusses issues unique to NuttX configurations for the
+Axoloti open source synthesizer board featuring the STM32F427IGH6
+MCU. The STM32F427IGH6 has a 180MHz Cortex-M4 core with 1MiB Flash
+memory and 256KiB of SRAM. The board features:
+
+  - ADAU1961 24-bit 96 kHz stereo CODEC
+  - 1/4" in/out jacks for analog audio signals
+  - 3.5 mm jack for analog audio signals
+  - 8 MiB of SDRAM (Alliance Memory AS4C4M16SA)
+  - Serial MIDI in/out ports
+  - SD Card slot
+  - Two user LEDs and one (GPIO) push-button
+  - USB OTG FS with Micro-AB connector (USB device mode operation)
+  - USB OTG HS with Type-A connector (USB host mode operation)
+  - Easy access to most IO pins
+
+Refer to http://www.axoloti.com/ for further information about this board.
diff --git a/configs/axoloti/include/board.h b/configs/axoloti/include/board.h
new file mode 100644
index 00000000000..6c16644fa0d
--- /dev/null
+++ b/configs/axoloti/include/board.h
@@ -0,0 +1,275 @@
+/************************************************************************************
+ * configs/axoloti/include/board.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Jason T. Harris 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __CONFIGS_AXOLOTI_INCLUDE_BOARD_H
+#define __CONFIGS_AXOLOTI_INCLUDE_BOARD_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#ifndef __ASSEMBLY__
+#  include 
+#  include 
+#endif
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Clocking
+ * The Axoloti board has an external 8MHz crystal.
+ * The SoC can run at 180MHz, but the required USB clock of 48MHz cannot be
+ * configured at that system clock rate, so the core clock is 168MHz.
+ *
+ * This is the canonical configuration:
+ *   System Clock source           : PLL (HSE)
+ *   SYSCLK(Hz)                    : 168000000    Determined by PLL configuration
+ *   HCLK(Hz)                      : 168000000    (STM32_RCC_CFGR_HPRE)
+ *   AHB Prescaler                 : 1            (STM32_RCC_CFGR_HPRE)
+ *   APB1 Prescaler                : 4            (STM32_RCC_CFGR_PPRE1)
+ *   APB2 Prescaler                : 2            (STM32_RCC_CFGR_PPRE2)
+ *   HSE Frequency(Hz)             : 8000000      (STM32_BOARD_XTAL)
+ *   PLLM                          : 8            (STM32_PLLCFG_PLLM)
+ *   PLLN                          : 336          (STM32_PLLCFG_PLLN)
+ *   PLLP                          : 2            (STM32_PLLCFG_PLLP)
+ *   PLLQ                          : 7            (STM32_PLLCFG_PLLQ)
+ *   Main regulator output voltage : Scale1 mode  Needed for high speed SYSCLK
+ *   Flash Latency(WS)             : 5
+ *   Prefetch Buffer               : OFF
+ *   Instruction cache             : ON
+ *   Data cache                    : ON
+ *   Require 48MHz for USB OTG FS, : Enabled
+ *   SDIO and RNG clock
+ */
+
+/* HSI - 16 MHz RC factory-trimmed
+ * LSI - 32 KHz RC
+ * HSE - On-board crystal frequency is 8MHz
+ * LSE - 32.768 kHz
+ */
+
+#define STM32_BOARD_XTAL        8000000ul
+
+#define STM32_HSI_FREQUENCY     16000000ul
+#define STM32_LSI_FREQUENCY     32000
+#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY     32768
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE
+ * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
+ *         = (8,000,000 / 8) * 336
+ *         = 336,000,000
+ * SYSCLK  = PLL_VCO / PLLP
+ *         = 336,000,000 / 2 = 168,000,000
+ * USB OTG FS, SDIO and RNG Clock
+ *         =  PLL_VCO / PLLQ
+ *         = 48,000,000
+ */
+
+#define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(8)
+#define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(336)
+#define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP_2
+#define STM32_PLLCFG_PLLQ       RCC_PLLCFG_PLLQ(7)
+
+#define STM32_SYSCLK_FREQUENCY  168000000ul
+
+/* AHB clock (HCLK) is SYSCLK (168MHz) */
+
+#define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK    /* HCLK  = SYSCLK / 1 */
+#define STM32_HCLK_FREQUENCY    STM32_SYSCLK_FREQUENCY
+#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY    /* same as above, to satisfy compiler */
+
+/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
+
+#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd4   /* PCLK1 = HCLK / 4 */
+#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/4)
+
+/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
+
+#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLKd2   /* PCLK2 = HCLK / 2 */
+#define STM32_PCLK2_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
+
+/************************************************************************************
+ * LED Definitions
+ * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any
+ * way.  The following definitions are used to access individual LEDs.
+ */
+
+/* LED index values for use with board_userled() */
+
+#define BOARD_LED1        0
+#define BOARD_LED2        1
+#define BOARD_NLEDS       2
+#define BOARD_LED_GREEN   BOARD_LED1
+#define BOARD_LED_RED     BOARD_LED2
+
+/* LED bits for use with board_userled_all() */
+
+#define BOARD_LED1_BIT    (1 << BOARD_LED1)
+#define BOARD_LED2_BIT    (1 << BOARD_LED2)
+
+/************************************************************************************
+ * Button Definitions
+ * There are two buttons on the axoloti, one of them is GPIO connected. The other
+ * is a reset button and is not under software control.
+ */
+
+#define BUTTON_USER        0
+#define NUM_BUTTONS        1
+#define BUTTON_USER_BIT    (1 << BUTTON_USER)
+
+/************************************************************************************
+ * UARTs
+ * The MIDI in/out ports of the axoloti are connected on USART6.
+ * It maybe convenient to run a serial port connected to the header pins,
+ * so we can optionally use USART1 for that.
+ */
+
+/* USART1 - console on header pins */
+
+#define GPIO_USART1_RX GPIO_USART1_RX_2 /* AF7, PB7 */
+#define GPIO_USART1_TX GPIO_USART1_TX_2 /* AF7, PB6 */
+
+/* USART6 - midi in/out */
+
+#define GPIO_USART6_RX (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN9| \
+                        GPIO_PULLUP|GPIO_SPEED_2MHz|GPIO_PUSHPULL)
+
+#define GPIO_USART6_TX (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN14| \
+                        GPIO_FLOAT|GPIO_SPEED_2MHz|GPIO_OPENDRAIN)
+
+/************************************************************************************
+ * I2C Bus
+ * Turn on the internal pullups since there are no external pullups.
+ */
+
+/* I2C1 - for external devices */
+
+#define GPIO_I2C1_SCL (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN8| \
+                       GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP)
+
+#define GPIO_I2C1_SDA  (GPIO_ALT|GPIO_AF4|GPIO_PORTB|GPIO_PIN9| \
+                       GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP)
+
+/* I2C3 - for the ADAU1961 codec */
+
+#define GPIO_I2C3_SCL (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN7| \
+                       GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP)
+
+#define GPIO_I2C3_SDA (GPIO_ALT|GPIO_AF4|GPIO_PORTH|GPIO_PIN8| \
+                       GPIO_SPEED_2MHz|GPIO_OPENDRAIN|GPIO_PULLUP)
+
+/************************************************************************************
+ * SAI Bus
+ * Used with the ADAU1961 CODEC
+ * PE3_SAI1_SD_B (GPIO_SAI1_SD_B_1)
+ * PE4_SAI1_FS_A (GPIO_SAI1_FS_A)
+ * PE5_SAI1_SCK_A (GPIO_SAI1_SCK_A)
+ * PE6_SAI1_SD_A (GPIO_SAI1_SD_A_2)
+ * PA8_MCO1
+ */
+
+#define GPIO_SAI1_SD_B GPIO_SAI1_SD_B_1 /* AF6, PE3 */
+#define GPIO_SAI1_SD_A GPIO_SAI1_SD_A_2 /* AF6, PE6 */
+
+#define STM32_SAI1_FREQUENCY (48000 * 2 * 256)  /* TODO ?? */
+
+/* DAC DMA to Codec
+ * dma 2, stream 1, channel 0
+ * memory to peripheral
+ * 32 bits
+ */
+#define DMACHAN_SAI1_A DMAMAP_SAI1_A_1
+
+/* ADC DMA from Codec
+ * dma 2, stream 4, channel 1,
+ * peripheral to memory
+ * 32 bits
+ */
+#define DMACHAN_SAI1_B DMAMAP_SAI1_B_2
+
+/************************************************************************************
+ * SDIO
+ * Used for the SD card interface.
+ * d0 (AF12, PC8)
+ * d1 (AF12, PC9)
+ * d2 (AF12, PC10)
+ * d3 (AF12, PC11)
+ * clk (AF12, PC12)
+ * cmd (AF12, PD2)
+ * cd1 PD13
+ */
+
+/* SDIO dividers. Note that slower clocking is required when DMA is disabled
+ * in order to avoid RX overrun/TX underrun errors due to delayed responses
+ * to service FIFOs in interrupt driven mode.  These values have not been
+ * tuned!!!
+ *
+ * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz
+ */
+
+#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT)
+
+/* DMA ON:  SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
+ * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
+ */
+
+#ifdef CONFIG_SDIO_DMA
+#  define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
+#else
+#  define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
+#endif
+
+/* DMA ON:  SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
+ * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
+ */
+
+#ifdef CONFIG_SDIO_DMA
+#  define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
+#else
+#  define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
+#endif
+
+/* dma 2, stream 6, channel 4 */
+
+#define DMAMAP_SDIO DMAMAP_SDIO_2
+
+#endif /* __CONFIG_AXOLOTI_INCLUDE_BOARD_H */
diff --git a/configs/axoloti/nsh/defconfig b/configs/axoloti/nsh/defconfig
new file mode 100644
index 00000000000..ef743ced625
--- /dev/null
+++ b/configs/axoloti/nsh/defconfig
@@ -0,0 +1,41 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_FPU is not set
+# CONFIG_ARCH_LEDS is not set
+# CONFIG_NSH_DISABLE_PRINTF is not set
+# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="axoloti"
+CONFIG_ARCH_BOARD_AXOLOTI=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CHIP_STM32=y
+CONFIG_ARCH_CHIP_STM32F427I=y
+CONFIG_ARCH_IRQBUTTONS=y
+CONFIG_BOARD_LATE_INITIALIZE=y
+CONFIG_BOARD_LOOPSPERMSEC=16717
+CONFIG_BUTTONS=y
+CONFIG_BUTTONS_LOWER=y
+CONFIG_CLOCK_MONOTONIC=y
+CONFIG_INPUT=y
+CONFIG_LIBC_FLOATINGPOINT=y
+CONFIG_MM_REGIONS=2
+CONFIG_RAW_BINARY=y
+CONFIG_STM32_CCMEXCLUDE=y
+CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
+CONFIG_STM32_JTAG_FULL_ENABLE=y
+CONFIG_STM32_USART1=y
+CONFIG_STM32_USART6=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_USART1_SERIAL_CONSOLE=y
+CONFIG_USART6_BAUD=31250
+CONFIG_USART6_RXBUFSIZE=128
+CONFIG_USART6_TXBUFSIZE=32
+CONFIG_USERLED=y
+CONFIG_USERLED_LOWER=y
+CONFIG_USER_ENTRYPOINT="nsh_main"
diff --git a/configs/axoloti/scripts/Make.defs b/configs/axoloti/scripts/Make.defs
new file mode 100644
index 00000000000..83e57ec3341
--- /dev/null
+++ b/configs/axoloti/scripts/Make.defs
@@ -0,0 +1,138 @@
+############################################################################
+# configs/axoloti/scripts/Make.defs
+#
+#   Copyright (C) 2011-2012, 2016-2017 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt 
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
+
+LDSCRIPT = ld.script
+
+ifeq ($(WINTOOL),y)
+  # Windows-native toolchains
+  DIRLINK = $(TOPDIR)/tools/copydir.sh
+  DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+  MKDEP = $(TOPDIR)/tools/mkwindeps.sh
+  ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+  ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+  # Linux/Cygwin-native toolchain
+  MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+  ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+  ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+STRIP = $(CROSSDEV)strip --strip-unneeded
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+  ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+# Loadable module definitions
+
+CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs
+
+LDMODULEFLAGS = -r -e module_initialize
+ifeq ($(WINTOOL),y)
+  LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}"
+else
+  LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld
+endif
+
+# ELF module definitions
+
+CELFFLAGS = $(CFLAGS) -mlong-calls # --target1-abs
+CXXELFFLAGS = $(CXXFLAGS) -mlong-calls # --target1-abs
+
+LDELFFLAGS = -r -e main
+ifeq ($(WINTOOL),y)
+  LDELFFLAGS += -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/gnu-elf.ld}"
+else
+  LDELFFLAGS += -T $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/gnu-elf.ld
+endif
+
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+  LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  LDFLAGS += -g
+endif
+
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =
+
diff --git a/configs/axoloti/scripts/gnu-elf.ld b/configs/axoloti/scripts/gnu-elf.ld
new file mode 100644
index 00000000000..45590f51b33
--- /dev/null
+++ b/configs/axoloti/scripts/gnu-elf.ld
@@ -0,0 +1,139 @@
+/****************************************************************************
+ * configs/axoloti/scripts/gnu-elf.ld
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+SECTIONS
+{
+  .text 0x00000000 :
+    {
+      _stext = . ;
+      *(.text)
+      *(.text.*)
+      *(.gnu.warning)
+      *(.stub)
+      *(.glue_7)
+      *(.glue_7t)
+      *(.jcr)
+
+      /* C++ support:  The .init and .fini sections contain specific logic
+       * to manage static constructors and destructors.
+       */
+
+      *(.gnu.linkonce.t.*)
+      *(.init)             /* Old ABI */
+      *(.fini)             /* Old ABI */
+      _etext = . ;
+    }
+
+  .ARM.extab :
+    {
+      *(.ARM.extab*)
+    }
+
+  .ARM.exidx :
+    {
+      *(.ARM.exidx*)
+    }
+
+  .rodata :
+    {
+      _srodata = . ;
+      *(.rodata)
+      *(.rodata1)
+      *(.rodata.*)
+      *(.gnu.linkonce.r*)
+      _erodata = . ;
+    }
+
+  .data :
+    {
+      _sdata = . ;
+      *(.data)
+      *(.data1)
+      *(.data.*)
+      *(.gnu.linkonce.d*)
+      _edata = . ;
+    }
+
+  /* C++ support. For each global and static local C++ object,
+   * GCC creates a small subroutine to construct the object. Pointers
+   * to these routines (not the routines themselves) are stored as
+   * simple, linear arrays in the .ctors section of the object file.
+   * Similarly, pointers to global/static destructor routines are
+   * stored in .dtors.
+   */
+
+  .ctors :
+    {
+      _sctors = . ;
+      *(.ctors)       /* Old ABI:  Unallocated */
+      *(.init_array)  /* New ABI:  Allocated */
+      _edtors = . ;
+    }
+
+  .dtors :
+    {
+      _sdtors = . ;
+      *(.dtors)       /* Old ABI:  Unallocated */
+      *(.fini_array)  /* New ABI:  Allocated */
+      _edtors = . ;
+    }
+
+  .bss :
+    {
+      _sbss = . ;
+      *(.bss)
+      *(.bss.*)
+      *(.sbss)
+      *(.sbss.*)
+      *(.gnu.linkonce.b*)
+      *(COMMON)
+      _ebss = . ;
+    }
+
+    /* Stabs debugging sections.    */
+
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+    .debug_abbrev 0 : { *(.debug_abbrev) }
+    .debug_info 0 : { *(.debug_info) }
+    .debug_line 0 : { *(.debug_line) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    .debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/configs/axoloti/scripts/kernel-space.ld b/configs/axoloti/scripts/kernel-space.ld
new file mode 100644
index 00000000000..68287ec7661
--- /dev/null
+++ b/configs/axoloti/scripts/kernel-space.ld
@@ -0,0 +1,110 @@
+/****************************************************************************
+ * configs/axoloti/scripts/kernel-space.ld
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* NOTE:  This depends on the memory.ld script having been included prior to
+ * this script.
+ */
+
+OUTPUT_ARCH(arm)
+EXTERN(_vectors)
+ENTRY(_stext)
+SECTIONS
+{
+    .text : {
+        _stext = ABSOLUTE(.);
+        *(.vectors)
+        *(.text .text.*)
+        *(.fixup)
+        *(.gnu.warning)
+        *(.rodata .rodata.*)
+        *(.gnu.linkonce.t.*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.got)
+        *(.gcc_except_table)
+        *(.gnu.linkonce.r.*)
+        _etext = ABSOLUTE(.);
+    } > kflash
+
+    .init_section : {
+        _sinit = ABSOLUTE(.);
+        *(.init_array .init_array.*)
+        _einit = ABSOLUTE(.);
+    } > kflash
+
+    .ARM.extab : {
+        *(.ARM.extab*)
+    } > kflash
+
+    __exidx_start = ABSOLUTE(.);
+    .ARM.exidx : {
+        *(.ARM.exidx*)
+    } > kflash
+
+    __exidx_end = ABSOLUTE(.);
+
+    _eronly = ABSOLUTE(.);
+
+    .data : {
+        _sdata = ABSOLUTE(.);
+        *(.data .data.*)
+        *(.gnu.linkonce.d.*)
+        CONSTRUCTORS
+        _edata = ABSOLUTE(.);
+    } > ksram AT > kflash
+
+    .bss : {
+        _sbss = ABSOLUTE(.);
+        *(.bss .bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        _ebss = ABSOLUTE(.);
+    } > ksram
+
+    /* Stabs debugging sections */
+
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+    .debug_abbrev 0 : { *(.debug_abbrev) }
+    .debug_info 0 : { *(.debug_info) }
+    .debug_line 0 : { *(.debug_line) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    .debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/configs/axoloti/scripts/ld.script b/configs/axoloti/scripts/ld.script
new file mode 100644
index 00000000000..135aaf128c6
--- /dev/null
+++ b/configs/axoloti/scripts/ld.script
@@ -0,0 +1,130 @@
+/****************************************************************************
+ * configs/axoloti/scripts/ld.script
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The STM32F427IGH6 has 1024KiB of FLASH beginning at address 0x0800:0000 and
+ * 256KiB of SRAM. SRAM is split up into four blocks:
+ *
+ * 1) 112KiB of SRAM beginning at address 0x2000:0000
+ * 2)  16KiB of SRAM beginning at address 0x2001:c000
+ * 3)  64KiB of SRAM beginning at address 0x2002:0000
+ * 4)  64KiB of CCM SRAM beginning at address 0x1000:0000
+ *
+ * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
+ * where the code expects to begin execution by jumping to the entry point in
+ * the 0x0800:0000 address
+ * range.
+ */
+
+MEMORY
+{
+    flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+    sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K
+}
+
+OUTPUT_ARCH(arm)
+EXTERN(_vectors)
+ENTRY(_stext)
+SECTIONS
+{
+	.text : {
+		_stext = ABSOLUTE(.);
+		*(.vectors)
+		*(.text .text.*)
+		*(.fixup)
+		*(.gnu.warning)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.t.*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.got)
+		*(.gcc_except_table)
+		*(.gnu.linkonce.r.*)
+		_etext = ABSOLUTE(.);
+	} > flash
+
+	.init_section : {
+		_sinit = ABSOLUTE(.);
+		*(.init_array .init_array.*)
+		_einit = ABSOLUTE(.);
+	} > flash
+
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} > flash
+
+	__exidx_start = ABSOLUTE(.);
+	.ARM.exidx : {
+		*(.ARM.exidx*)
+	} > flash
+	__exidx_end = ABSOLUTE(.);
+
+	_eronly = ABSOLUTE(.);
+
+	/* The RAM vector table (if present) should lie at the beginning of SRAM */
+
+	.ram_vectors : {
+		*(.ram_vectors)
+	} > sram
+
+	.data : {
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		CONSTRUCTORS
+		_edata = ABSOLUTE(.);
+	} > sram AT > flash
+
+	.bss : {
+		_sbss = ABSOLUTE(.);
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		_ebss = ABSOLUTE(.);
+	} > sram
+
+	/* Stabs debugging sections. */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/configs/axoloti/scripts/memory.ld b/configs/axoloti/scripts/memory.ld
new file mode 100644
index 00000000000..109a893f974
--- /dev/null
+++ b/configs/axoloti/scripts/memory.ld
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * configs/axoloti/scripts/memory.ld
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The STM32F427IGH6 has 1024KiB of FLASH beginning at address 0x0800:0000 and
+ * 256KiB of SRAM. SRAM is split up into four blocks:
+ *
+ * 1) 112KiB of SRAM beginning at address 0x2000:0000
+ * 2)  16KiB of SRAM beginning at address 0x2001:c000
+ * 3)  64KiB of SRAM beginning at address 0x2002:0000
+ * 4)  64KiB of CCM SRAM beginning at address 0x1000:0000
+ *
+ * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
+ * where the code expects to begin execution by jumping to the entry point in
+ * the 0x0800:0000 address range.
+ *
+ * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of
+ * FLASH and 4Kb of SRAM.  That is an excessive amount for the kernel which
+ * should fit into 64KB and, of course, can be optimized as needed (See
+ * also configs/axoloti/scripts/kernel-space.ld).  Allowing the
+ * additional does permit addition debug instrumentation to be added to the
+ * kernel space without overflowing the partition.
+ *
+ * Alignment of the user space FLASH partition is also a critical factor:
+ * The user space FLASH partition will be spanned with a single region of
+ * size 2**n bytes.  The alignment of the user-space region must be the same.
+ * As a consequence, as the user-space increases in size, the alignmment
+ * requirement also increases.
+ *
+ * This alignment requirement means that the largest user space FLASH region
+ * you can have will be 512KB at it would have to be positioned at
+ * 0x08800000.  If you change this address, don't forget to change the
+ * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify
+ * the check in kernel/userspace.c.
+ *
+ * For the same reasons, the maximum size of the SRAM mapping is limited to
+ * 4KB.  Both of these alignment limitations could be reduced by using
+ * multiple regions to map the FLASH/SDRAM range or perhaps with some
+ * clever use of subregions.
+ *
+ * A detailed memory map for the 112KB SRAM region is as follows:
+ *
+ *   0x20000 0000:  Kernel .data region.  Typical size: 0.1KB
+ *   ------- ----   Kernel .bss  region.  Typical size: 1.8KB
+ *   0x20000 0800:  Kernel IDLE thread stack (approximate).  Size is
+ *                  determined by CONFIG_IDLETHREAD_STACKSIZE and
+ *                  adjustments for alignment.  Typical is 1KB.
+ *   ------- ----   Padded to 4KB
+ *   0x20000 1000:  User .data region.  Size is variable.
+ *   ------- ----   User .bss region  Size is variable.
+ *   0x20000 2000:  Beginning of kernel heap.  Size determined by
+ *                  CONFIG_MM_KERNEL_HEAPSIZE.
+ *   ------- ----   Beginning of user heap.  Can vary with other settings.
+ *   0x20001 c000:  End+1 of CPU RAM
+ */
+
+MEMORY
+{
+    /* 1024Kb FLASH */
+
+    kflash (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+    uflash (rx)      : ORIGIN = 0x08020000, LENGTH = 128K
+    xflash (rx)      : ORIGIN = 0x08040000, LENGTH = 768K
+
+    /* 112Kb of contiguous SRAM */
+
+    ksram (rwx)      : ORIGIN = 0x20000000, LENGTH = 4K
+    usram (rwx)      : ORIGIN = 0x20001000, LENGTH = 4K
+    xsram (rwx)      : ORIGIN = 0x20002000, LENGTH = 104K
+}
diff --git a/configs/axoloti/scripts/user-space.ld b/configs/axoloti/scripts/user-space.ld
new file mode 100644
index 00000000000..0197a91896a
--- /dev/null
+++ b/configs/axoloti/scripts/user-space.ld
@@ -0,0 +1,126 @@
+/****************************************************************************
+ * configs/axoloti/scripts/user-space.ld
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* NOTE:  This depends on the memory.ld script having been included prior to
+ * this script.
+ */
+
+/* Make sure that the critical memory management functions are in user-space.
+ * the user heap memory manager will reside in user-space but be usable both
+ * by kernel- and user-space code
+ */
+
+EXTERN(umm_initialize)
+EXTERN(umm_addregion)
+EXTERN(umm_trysemaphore)
+EXTERN(umm_givesemaphore)
+
+EXTERN(malloc)
+EXTERN(realloc)
+EXTERN(zalloc)
+EXTERN(free)
+
+OUTPUT_ARCH(arm)
+SECTIONS
+{
+    .userspace : {
+        *(.userspace)
+    } > uflash
+
+    .text : {
+        _stext = ABSOLUTE(.);
+        *(.text .text.*)
+        *(.fixup)
+        *(.gnu.warning)
+        *(.rodata .rodata.*)
+        *(.gnu.linkonce.t.*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.got)
+        *(.gcc_except_table)
+        *(.gnu.linkonce.r.*)
+        _etext = ABSOLUTE(.);
+    } > uflash
+
+    .init_section : {
+        _sinit = ABSOLUTE(.);
+        *(.init_array .init_array.*)
+        _einit = ABSOLUTE(.);
+    } > uflash
+
+    .ARM.extab : {
+        *(.ARM.extab*)
+    } > uflash
+
+    __exidx_start = ABSOLUTE(.);
+    .ARM.exidx : {
+        *(.ARM.exidx*)
+    } > uflash
+
+    __exidx_end = ABSOLUTE(.);
+
+    _eronly = ABSOLUTE(.);
+
+    .data : {
+        _sdata = ABSOLUTE(.);
+        *(.data .data.*)
+        *(.gnu.linkonce.d.*)
+        CONSTRUCTORS
+        _edata = ABSOLUTE(.);
+    } > usram AT > uflash
+
+    .bss : {
+        _sbss = ABSOLUTE(.);
+        *(.bss .bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        _ebss = ABSOLUTE(.);
+    } > usram
+
+    /* Stabs debugging sections */
+
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+    .debug_abbrev 0 : { *(.debug_abbrev) }
+    .debug_info 0 : { *(.debug_info) }
+    .debug_line 0 : { *(.debug_line) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    .debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/configs/axoloti/src/.gitignore b/configs/axoloti/src/.gitignore
new file mode 100644
index 00000000000..726d936e1e3
--- /dev/null
+++ b/configs/axoloti/src/.gitignore
@@ -0,0 +1,2 @@
+/.depend
+/Make.dep
diff --git a/configs/axoloti/src/Makefile b/configs/axoloti/src/Makefile
new file mode 100644
index 00000000000..fad7ec90952
--- /dev/null
+++ b/configs/axoloti/src/Makefile
@@ -0,0 +1,67 @@
+############################################################################
+# configs/axoloti/src/Makefile
+#
+#   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+#   Author: Jason T. Harris 
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+
+ASRCS =
+CSRCS = stm32_boot.c stm32_bringup.c
+
+ifeq ($(CONFIG_STM32_FMC),y)
+CSRCS += stm32_extmem.c
+endif
+
+ifeq ($(CONFIG_ARCH_LEDS),y)
+CSRCS += stm32_autoleds.c
+else
+CSRCS += stm32_userleds.c
+endif
+
+ifeq ($(CONFIG_AUDIO_ADAU1961),y)
+CSRCS += stm32_adau1961.c
+endif
+
+ifeq ($(CONFIG_ARCH_BUTTONS),y)
+CSRCS +=  stm32_buttons.c
+endif
+
+ifeq ($(CONFIG_STM32_SDIO),y)
+CSRCS += stm32_sdio.c
+endif
+
+ifeq ($(CONFIG_USBHOST),y)
+CSRCS += stm32_usbhost.c
+endif
+
+include $(TOPDIR)/configs/Board.mk
diff --git a/configs/axoloti/src/axoloti.h b/configs/axoloti/src/axoloti.h
new file mode 100644
index 00000000000..7e01355129f
--- /dev/null
+++ b/configs/axoloti/src/axoloti.h
@@ -0,0 +1,251 @@
+/****************************************************************************
+ * configs/axoloti/src/axoloti.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Jason T. Harris 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __CONFIGS_AXOLOTI_SRC_AXOLOTI_H
+#define __CONFIGS_AXOLOTI_SRC_AXOLOTI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include 
+#include 
+#include 
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * configuration
+ */
+
+/* Assume that we have everything */
+
+#define HAVE_USBDEV     1
+#define HAVE_USBHOST    1
+#define HAVE_SDIO       1
+#define HAVE_ADAU1961   1
+#define HAVE_SDRAM      1
+
+/* Can't support USB host if USB OTG HS is not enabled */
+
+#if !defined(CONFIG_STM32_OTGHS) || !defined(CONFIG_USBHOST)
+#  undef HAVE_USBHOST
+#endif
+
+/* Can't support USB device if USB OTG FS is not enabled */
+
+#if !defined(CONFIG_STM32_OTGFS) || !defined(CONFIG_USBDEV)
+#  undef HAVE_USBDEV
+#endif
+
+/* Can't support MMC/SD features if mountpoints or SDIO support are disabled */
+
+#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_STM32_SDIO)
+#  undef HAVE_SDIO
+#endif
+
+/* The ADAU1961 depends on the ADAU1961 driver, I2C3, and SAI1 support */
+
+#if !defined(CONFIG_AUDIO_ADAU1961) || !defined(CONFIG_STM32_I2C3) || \
+    !defined(CONFIG_STM32_SAI1)
+#  undef HAVE_ADAU1961
+#endif
+
+/* Can't support SDRAM if the memory controller is disabled */
+
+#if !defined(CONFIG_STM32_FMC)
+#  undef HAVE_SDRAM
+#endif
+
+/****************************************************************************
+ * Audio Configuration
+ */
+
+#define ADAU1961_I2C_BUS 3      /* i2c3 */
+#define ADAU1961_I2C_ADDRESS 0x38
+#define ADAU1961_SAI_BUS SAI1_BLOCK_A
+
+/****************************************************************************
+ * SDIO Configuration
+ */
+
+#define SDIO_MINOR CONFIG_NSH_MMCSDMINOR
+#define SDIO_SLOTNO CONFIG_NSH_MMCSDSLOTNO
+
+/* SD Slot Card detect */
+
+#define GPIO_SDIO_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTD|GPIO_PIN13)
+
+/****************************************************************************
+ * PROC File System Configuration
+ */
+
+#ifdef CONFIG_FS_PROCFS
+#  ifdef CONFIG_NSH_PROC_MOUNTPOINT
+#    define STM32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT
+#  else
+#    define STM32_PROCFS_MOUNTPOINT "/proc"
+#  endif
+#endif
+
+/****************************************************************************
+ * LEDs
+ */
+
+#define GPIO_LED1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \
+                   GPIO_OUTPUT_CLEAR|GPIO_PORTG|GPIO_PIN6)
+
+#define GPIO_LED2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz| \
+                   GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6)
+
+/****************************************************************************
+ * Buttons
+ */
+
+#define MIN_IRQBUTTON BUTTON_USER
+#define MAX_IRQBUTTON BUTTON_USER
+#define NUM_IRQBUTTONS  1
+#define GPIO_BTN_USER (GPIO_INPUT|GPIO_PULLDOWN|GPIO_EXTI|GPIO_PORTA|GPIO_PIN10)
+
+/****************************************************************************
+ * USB Host (OTG High Speed)
+ */
+
+#define GPIO_OTGHS_PWRON (GPIO_OUTPUT|GPIO_OUTPUT_SET|GPIO_FLOAT| \
+                          GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7)
+
+#define GPIO_OTGHS_OVER  (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT| \
+                          GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13)
+
+/* #define GPIO_OTGHS_VBUS no vbus monitoring.... */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y :
+ *     Called from board_late_initialize().
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
+ *     Called from the NSH library
+ *
+ ****************************************************************************/
+
+int stm32_bringup(void);
+
+/****************************************************************************
+ * Name: stm32_sdio_initialize
+ *
+ * Description:
+ *   Initialize SDIO-based MMC/SD card support
+ *
+ ****************************************************************************/
+
+#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32_SDIO)
+int stm32_sdio_initialize(void);
+#endif
+
+/****************************************************************************
+ * Name: stm32_usbinitialize
+ *
+ * Description:
+ *   Called from stm32_usbinitialize very early in initialization to setup
+ *   USB-related GPIO pins for the STM32F4Discovery board.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32_OTGHS
+void weak_function stm32_usbinitialize(void);
+#endif
+
+/****************************************************************************
+ * Name: stm32_usbhost_initialize
+ *
+ * Description:
+ *   Called at application startup time to initialize the USB host
+ *   functionality. This function will start a thread that will monitor for
+ *   device connection/disconnection events.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_STM32_OTGHS) && defined(CONFIG_USBHOST)
+int stm32_usbhost_initialize(void);
+#endif
+
+/****************************************************************************
+ * Name: stm32_adau1961_initialize
+ *
+ * Description:
+ *   Called from stm32_bringup to initialize the adau1961 audio driver.
+ *
+ ****************************************************************************/
+
+#if defined(HAVE_ADAU1961)
+int stm32_adau1961_initialize(int minor);
+#endif
+
+/****************************************************************************
+ * Name: stm32_sdram_initialize
+ *
+ * Description:
+ *   Called from stm32_bringup to initialize external SDRAM access.
+ *
+ ****************************************************************************/
+
+#if defined(HAVE_SDRAM)
+int stm32_sdram_initialize(void);
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __CONFIGS_AXOLOTI_SRC_AXOLOTI_H */
diff --git a/configs/axoloti/src/stm32_adau1961.c b/configs/axoloti/src/stm32_adau1961.c
new file mode 100644
index 00000000000..a6cfc7714d0
--- /dev/null
+++ b/configs/axoloti/src/stm32_adau1961.c
@@ -0,0 +1,221 @@
+/****************************************************************************
+ * configs/axoloti/src/stm32_adau1961.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Jason T. Harris 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include "stm32.h"
+#include "axoloti.h"
+
+#ifdef HAVE_ADAU1961
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct stm32_mwinfo_s
+{
+  /* Standard ADAU1961 interface */
+
+  struct adau1961_lower_s lower;
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static int adau1961_attach(FAR const struct adau1961_lower_s *lower,
+                           adau1961_handler_t isr, FAR void *arg)
+{
+  audinfo("TODO\n");
+  return 0;
+}
+
+static bool adau1961_enable(FAR const struct adau1961_lower_s *lower,
+                            bool enable)
+{
+  audinfo("TODO\n");
+  return 0;
+}
+
+static void adau1961_hw_reset(FAR const struct adau1961_lower_s *lower)
+{
+  audinfo("TODO\n");
+}
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* A reference to a structure of this type must be passed to the ADAU1961
+ * driver.  This structure provides information about the configuration
+ * of the ADAU1961 and provides some board-specific hooks.
+ *
+ * Memory for this structure is provided by the caller.  It is not copied
+ * by the driver and is presumed to persist while the driver is active.
+ */
+
+static struct stm32_mwinfo_s g_adau1961info =
+{
+  .lower =
+  {
+    .address   = ADAU1961_I2C_ADDRESS,
+    .frequency = I2C_SPEED_FAST,        /* 400 kHz */
+    .mclk      = STM32_HSE_FREQUENCY,   /* see MCO1 configuration */
+    .attach    = adau1961_attach,
+    .enable    = adau1961_enable,
+    .reset     = adau1961_hw_reset,
+  }
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_adau1961_initialize
+ *
+ * Description:
+ *   This function is called by platform-specific, setup logic to configure
+ *   and register the ADAU1961 device.  This function will register the driver
+ *   as /dev/audio/pcm[x] where x is determined by the minor device number.
+ *
+ * Input Parameters:
+ *   minor - The input device minor number
+ *
+ * Returned Value:
+ *   Zero is returned on success.  Otherwise, a negated errno value is
+ *   returned to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int stm32_adau1961_initialize(int minor)
+{
+  FAR struct audio_lowerhalf_s *adau1961;
+  FAR struct i2c_master_s *i2c;
+  FAR struct i2s_dev_s *i2s;
+  static bool initialized = false;
+  char devname[12];
+  int ret;
+
+  audinfo("minor %d\n", minor);
+  DEBUGASSERT(minor >= 0 && minor <= 25);
+
+  /* Initialize the CODEC if we have not already done so */
+
+  if (!initialized)
+    {
+      /* Configure MC01 to drive the master clock of the CODEC at 8MHz */
+
+      stm32_configgpio(GPIO_MCO1);
+      stm32_mco1config(RCC_CFGR_MCO1_HSE, RCC_CFGR_MCO1PRE_NONE);
+
+      /* Get an instance of the I2C interface for the CODEC */
+
+      i2c = stm32_i2cbus_initialize(ADAU1961_I2C_BUS);
+      if (!i2c)
+        {
+          auderr("stm32_i2cbus_initialize failed\n");
+          ret = -ENODEV;
+          goto error;
+        }
+
+      /* Get an instance of the I2S interface for the CODEC data streams */
+
+      i2s = stm32_sai_initialize(ADAU1961_SAI_BUS);
+      if (!i2s)
+        {
+          auderr("stm32_sai_initialize failed\n");
+          ret = -ENODEV;
+          goto error;
+        }
+
+      /* Now we can use these I2C and I2S interfaces to initialize the
+       * CODEC which will return an audio interface.
+       */
+
+      adau1961 = adau1961_initialize(i2c, i2s, &g_adau1961info.lower);
+      if (!adau1961)
+        {
+          auderr("adau1961_initialize failed\n");
+          ret = -ENODEV;
+          goto error;
+        }
+
+      /* Create a device name */
+
+      snprintf(devname, 12, "pcm%d", minor);
+
+      /* Finally, we can register the ADAU1961/I2C/I2S audio device. */
+
+      ret = audio_register(devname, adau1961);
+      if (ret < 0)
+        {
+          auderr("failed to register /dev/%s device: %d\n", devname, ret);
+          goto error;
+        }
+
+      /* Now we are initialized */
+
+      initialized = true;
+    }
+
+  return OK;
+
+  /* Error exits. Unfortunately there is no mechanism in place now to
+   * recover resources from most errors on initialization failures.
+   */
+
+error:
+  return ret;
+}
+
+#endif /* HAVE_ADAU1961 */
diff --git a/configs/axoloti/src/stm32_boot.c b/configs/axoloti/src/stm32_boot.c
new file mode 100644
index 00000000000..8f2fa7e9152
--- /dev/null
+++ b/configs/axoloti/src/stm32_boot.c
@@ -0,0 +1,107 @@
+/****************************************************************************
+ * configs/axoloti/src/stm32_boot.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Jason T. Harris 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include 
+#include 
+
+#include "up_arch.h"
+#include "itm.h"
+
+#include "stm32.h"
+#include "axoloti.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_boardinitialize
+ *
+ * Description:
+ *   All STM32 architectures must provide the following entry point.  This
+ *   entry point is called early in the initialization -- after all memory
+ *   has been configured and mapped but before any devices have been
+ *   initialized.
+ *
+ ****************************************************************************/
+
+void stm32_boardinitialize(void)
+{
+#ifdef CONFIG_SCHED_CRITMONITOR
+  /* Make sure the high speed cycle counter is running.  It will be started
+   * automatically only if a debugger is connected.
+   */
+
+  putreg32(0xc5acce55, ITM_LAR);
+  modifyreg32(DWT_CTRL, 0, DWT_CTRL_CYCCNTENA_MASK);
+#endif
+
+#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \
+    defined(CONFIG_STM32_SPI3)
+  stm32_spidev_initialize();
+#endif
+
+#if defined(CONFIG_STM32_OTGHS) || defined(CONFIG_STM32_OTGFS)
+  stm32_usbinitialize();
+#endif
+}
+
+/****************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ *   If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
+ *   initialization call will be performed in the boot-up sequence to a
+ *   function called board_late_initialize().  board_late_initialize() will be
+ *   called immediately after up_initialize() is called and just before the
+ *   initial application is started.  This additional initialization phase
+ *   may be used, for example, to initialize board-specific device drivers.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+  (void)stm32_bringup();
+}
+#endif
diff --git a/configs/axoloti/src/stm32_bringup.c b/configs/axoloti/src/stm32_bringup.c
new file mode 100644
index 00000000000..8e80bd0b209
--- /dev/null
+++ b/configs/axoloti/src/stm32_bringup.c
@@ -0,0 +1,191 @@
+/****************************************************************************
+ * config/axoloti/src/stm32_bringup.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Jason T. Harris 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#ifdef CONFIG_USBMONITOR
+#  include 
+#endif
+
+#include "stm32.h"
+
+#ifdef CONFIG_STM32_OTGHS
+#  include "stm32_usbhost.h"
+#endif
+
+#ifdef CONFIG_BUTTONS
+#  include 
+#endif
+
+#ifdef CONFIG_USERLED
+#  include 
+#endif
+
+#include "axoloti.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y :
+ *     Called from board_late_initialize().
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
+ *     Called from the NSH library
+ *
+ ****************************************************************************/
+
+int stm32_bringup(void)
+{
+#ifdef HAVE_RTC_DRIVER
+  FAR struct rtc_lowerhalf_s *lower;
+#endif
+  int ret = OK;
+
+#ifdef HAVE_SDRAM
+  /* Initialize access to the SDRAM device */
+
+  ret = stm32_sdram_initialize();
+  if (ret != OK)
+    {
+      syslog(LOG_ERR, "stm32_sdram_initialize failed %d\n", ret);
+      return ret;
+    }
+#endif
+
+#ifdef HAVE_SDIO
+  /* Initialize the SDIO block driver */
+
+  ret = stm32_sdio_initialize();
+  if (ret != OK)
+    {
+      syslog(LOG_ERR, "stm32_sdio_initialize failed %d\n", ret);
+      return ret;
+    }
+#endif
+
+#ifdef HAVE_USBHOST
+  /* Initialize USB host operation.  stm32_usbhost_initialize() starts a
+   * thread will monitor for USB connection and disconnection events.
+   */
+
+  ret = stm32_usbhost_initialize();
+  if (ret != OK)
+    {
+      syslog(LOG_ERR, "stm32_usbhost_initialize failed %d\n", ret);
+      return ret;
+    }
+#endif
+
+#ifdef HAVE_USBMONITOR
+  /* Start the USB Monitor */
+
+  ret = usbmonitor_start();
+  if (ret != OK)
+    {
+      syslog(LOG_ERR, "usbmonitor_start failed %d\n", ret);
+      return ret;
+    }
+#endif
+
+#ifdef CONFIG_BUTTONS
+  /* Register the BUTTON driver */
+
+  ret = btn_lower_initialize("/dev/buttons");
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "btn_lower_initialize failed %d\n", ret);
+    }
+#endif
+
+#ifdef CONFIG_INPUT_REI2C
+  /* Register the rei2c driver */
+
+  ret = rei2c_initialize("/dev/re0");
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "rei2c_initialize failed %d\n", ret);
+    }
+#endif
+
+#ifdef CONFIG_USERLED
+  /* Register the LED driver */
+
+  ret = userled_lower_initialize("/dev/userleds");
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "userled_lower_initialize failed %d\n", ret);
+    }
+#endif
+
+#ifdef HAVE_ADAU1961
+  /* Configure ADAU1961 audio */
+
+  ret = stm32_adau1961_initialize(1);
+  if (ret != OK)
+    {
+      syslog(LOG_ERR, "stm32_adau1961_initialize failed %d\n", ret);
+    }
+#endif
+
+#ifdef CONFIG_FS_PROCFS
+  /* Mount the procfs file system */
+
+  ret = mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL);
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "failed to mount procfs at %s %d\n",
+             STM32_PROCFS_MOUNTPOINT, ret);
+    }
+#endif
+
+  return ret;
+}
diff --git a/configs/axoloti/src/stm32_buttons.c b/configs/axoloti/src/stm32_buttons.c
new file mode 100644
index 00000000000..ade97cfd88b
--- /dev/null
+++ b/configs/axoloti/src/stm32_buttons.c
@@ -0,0 +1,162 @@
+/****************************************************************************
+ * configs/axoloti/src/stm32_buttons.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Jason T. Harris 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "stm32.h"
+#include "axoloti.h"
+
+#ifdef CONFIG_ARCH_BUTTONS
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Pin configuration for each axoloti button.  This array is indexed by
+ * the BUTTON_* definitions in board.h
+ */
+
+static const uint32_t g_buttons[NUM_BUTTONS] =
+{
+  GPIO_BTN_USER,
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_button_initialize
+ *
+ * Description:
+ *   board_button_initialize() must be called to initialize button resources.
+ *   After that, board_buttons() may be called to collect the current state
+ *   of all buttons or board_button_irq() may be called to register button
+ *   interrupt handlers.
+ *
+ ****************************************************************************/
+
+void board_button_initialize(void)
+{
+  int i;
+
+  /* Configure the GPIO pins as inputs.
+   * EXTI interrupts are configured for all pins.
+   */
+
+  for (i = 0; i < NUM_BUTTONS; i++)
+    {
+      stm32_configgpio(g_buttons[i]);
+    }
+}
+
+/****************************************************************************
+ * Name: board_buttons
+ ****************************************************************************/
+
+uint32_t board_buttons(void)
+{
+  uint32_t ret = 0;
+  int i;
+
+  /* Check that state of each key */
+
+  for (i = 0; i < NUM_BUTTONS; i++)
+    {
+      /* A HI value means that the key is pressed. */
+
+      bool pressed = stm32_gpioread(g_buttons[i]);
+
+      /* Accumulate the set of depressed (not released) keys */
+
+      if (pressed)
+        {
+          ret |= (1 << i);
+        }
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Button support.
+ *
+ * Description:
+ *   board_button_initialize() must be called to initialize button resources.
+ *   After that, board_buttons() may be called to collect the current state
+ *   of all buttons or board_button_irq() may be called to register button
+ *   interrupt handlers.
+ *
+ *   After board_button_initialize() has been called, board_buttons() may be
+ *   called to collect the state of all buttons.  board_buttons() returns an
+ *   32-bit bit set with each bit associated with a button.  See the
+ *   BUTTON_*_BIT definitions in board.h for the meaning of each bit.
+ *
+ *   board_button_irq() may be called to register an interrupt handler that
+ *   will be called when a button is depressed or released.  The ID value is
+ *   a button enumeration value that uniquely identifies a button resource.
+ *   See the BUTTON_* definitions in board.h for the meaning of enumeration
+ *   value.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_IRQBUTTONS
+int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
+{
+  int ret = -EINVAL;
+
+  /* The following should be atomic */
+
+  if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON)
+    {
+      ret =
+        stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg);
+    }
+
+  return ret;
+}
+#endif
+#endif /* CONFIG_ARCH_BUTTONS */
diff --git a/configs/axoloti/src/stm32_extmem.c b/configs/axoloti/src/stm32_extmem.c
new file mode 100644
index 00000000000..e8ac1273a62
--- /dev/null
+++ b/configs/axoloti/src/stm32_extmem.c
@@ -0,0 +1,323 @@
+/****************************************************************************
+ * configs/axoloti/src/stm32_extmem.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Jason T. Harris 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+#include "chip.h"
+#include "up_arch.h"
+
+#include "stm32.h"
+#include "axoloti.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_STM32_FMC
+#warning "FMC is not enabled"
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Axoloti SDRAM GPIO configuration */
+
+static const uint32_t g_sdram_config[] =
+{
+  /* Data lines */
+
+  GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3,
+  GPIO_FMC_D4, GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7,
+  GPIO_FMC_D8, GPIO_FMC_D9, GPIO_FMC_D10, GPIO_FMC_D11,
+  GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14, GPIO_FMC_D15,
+
+  /* Address lines */
+
+  GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3,
+  GPIO_FMC_A4, GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7,
+  GPIO_FMC_A8, GPIO_FMC_A9, GPIO_FMC_A10, GPIO_FMC_A11,
+  GPIO_FMC_A12,
+
+  /* Control lines */
+
+  GPIO_FMC_BA0,                 /* ba0 */
+  GPIO_FMC_BA1,                 /* ba1 */
+  GPIO_FMC_NBL0,                /* ldqm */
+  GPIO_FMC_NBL1,                /* udqm */
+  GPIO_FMC_SDCLK,               /* clk */
+  GPIO_FMC_SDCKE0_1,            /* cke */
+  GPIO_FMC_SDNWE_2,             /* we */
+  GPIO_FMC_SDNCAS,              /* cas */
+  GPIO_FMC_SDNRAS,              /* ras */
+  GPIO_FMC_SDNE0_1,             /* cs0 */
+  GPIO_FMC_SDNE1_2,             /* cs1 */
+};
+
+#define NUM_SDRAM_GPIOS (sizeof(g_sdram_config) / sizeof(uint32_t))
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_sdram_memtest
+ *
+ * Description:
+ *  Test the SDRAM.
+ *
+ ****************************************************************************/
+
+#define RAND_A 22695477
+#define RAND_C 1
+#define TEST_ITERATIONS 16
+
+int stm32_sdram_memtest(void *base, uint32_t size)
+{
+  volatile int iter;
+  volatile int i;
+
+  /* Linear write with linear congruential generator values */
+
+  for (iter = 0; iter < TEST_ITERATIONS; iter++)
+    {
+      uint32_t x = iter;
+
+      /* Write */
+
+      for (i = 0; i < size / 4; i++)
+        {
+          x = (RAND_A * x) + RAND_C;
+          ((volatile uint32_t *)base)[i] = x;
+        }
+
+      /* Read/verify */
+
+      x = iter;
+      for (i = 0; i < size / 4; i++)
+        {
+          x = (RAND_A * x) + RAND_C;
+          if (((volatile uint32_t *)base)[i] != x)
+            {
+              return -1;
+            }
+        }
+    }
+
+  /* Scattered byte write at linear congruential generator addresses */
+
+  for (iter = 0; iter < TEST_ITERATIONS; iter++)
+    {
+      uint32_t x = iter;
+
+      /* Write */
+
+      for (i = 0; i < 1024 * 1024; i++)
+        {
+          x = (RAND_A * x) + RAND_C;
+          ((volatile uint8_t *)base)[x & (size - 1)] = (uint8_t) i;
+        }
+
+      /* Read/verify */
+
+      x = iter;
+      for (i = 0; i < 1024 * 1024; i++)
+        {
+          x = (RAND_A * x) + RAND_C;
+          if (((volatile uint8_t *)base)[x & (size - 1)] != (uint8_t) i)
+            {
+              return -1;
+            }
+        }
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: stm32_sdram_initialize
+ *
+ * Description:
+ *   Called from stm32_bringup to initialize external SDRAM access.
+ *   The Axoloti uses an Alliance Memory AS4C4M16SA SDRAM.
+ *
+ ****************************************************************************/
+
+int stm32_sdram_initialize(void)
+{
+  uint32_t val;
+  int i;
+
+  /* Configure SDRAM GPIOs */
+
+  for (i = 0; i < NUM_SDRAM_GPIOS; i++)
+    {
+      stm32_configgpio(g_sdram_config[i]);
+    }
+
+  /* Enable the FMC */
+
+  stm32_fmc_enable();
+
+  /* Go through the SDRAM initialization steps per the reference manual.
+   * The sdclk period is set to 2 x hclk. That is: 168 /2 = 84 MHz
+   * This gives a clock period of about 11.9 ns
+   */
+
+  /* Step 1:
+   * Program the memory device features into the FMC_SDCRx register. The
+   * SDRAM clock frequency, RBURST and RPIPE must be programmed in the
+   * FMC_SDCR1 register.
+   */
+
+  val = FMC_SDCR_RPIPE_1 |      /* rpipe = 1 hclk */
+    FMC_SDCR_READBURST |        /* read burst enabled */
+    FMC_SDCR_SDCLK_2X |         /* sdclk = 2 hclk */
+    FMC_SDCR_CAS_LATENCY_2 |    /* cas latency = 2 cycles */
+    FMC_SDCR_NBANKS_4 |         /* 4 internal banks */
+    FMC_SDCR_WIDTH_16 |         /* width = 16 bits */
+    FMC_SDCR_ROWS_12 |          /* numrows = 12 */
+    FMC_SDCR_COLS_8;            /* numcols = 8 bits */
+  stm32_fmc_sdram_set_control(1, val);
+
+  /* Step 2:
+   * Program the memory device timing into the FMC_SDTRx register.  The
+   * TRP and TRC timings must be programmed in the FMC_SDTR1 register.
+   */
+
+  val = FMC_SDTR_TRCD(2) |      /* ras to cas delay 21ns => 2x11.90ns */
+    FMC_SDTR_TRP(2) |           /* row precharge 21ns => 2x11.90ns */
+    FMC_SDTR_TRC(6) |           /* row cycle time 63ns => 6x11.9ns */
+    FMC_SDTR_TRAS(4) |          /* row active time 42ns = >4x11.9ns */
+    FMC_SDTR_TWR(4) |           /* write to precharge 42ns => 4x11.9ns */
+    FMC_SDTR_TXSR(6) |          /* exit self refresh 65ns => 6x11.9ns */
+    FMC_SDTR_TMRD(2);           /* load mode register to active 2 clks */
+  stm32_fmc_sdram_set_timing(1, val);
+
+  /* Step 3:
+   * Set MODE bits to ‘001’ and configure the Target Bank bits (CTB1
+   * and/or CTB2) in the FMC_SDCMR register to start delivering the clock
+   * to the memory (SDCKE is driven high).
+   */
+
+  val = FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_CLK_ENABLE;
+  stm32_fmc_sdram_command(val);
+
+  /* Step 4:
+   * Wait during the prescribed delay period. Typical delay is around 100
+   * μs (refer to the SDRAM datasheet for the required delay after power-up).
+   */
+
+  nxsig_usleep(1000);
+
+  /* Step 5:
+   * Set MODE bits to ‘010’ and configure the Target Bank bits (CTB1
+   * and/or CTB2) in the FMC_SDCMR register to issue a “Precharge All”
+   * command.
+   */
+
+  val = FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_PALL;
+  stm32_fmc_sdram_command(val);
+
+  /* Step 6:
+   * Set MODE bits to ‘011’, and configure the Target Bank bits (CTB1
+   * and/or CTB2) as well as the number of consecutive Auto-refresh
+   * commands (NRFS) in the FMC_SDCMR register. Refer to the SDRAM
+   * datasheet for the number of Auto-refresh commands that should be
+   * issued. Typical number is 8.
+   */
+
+  val = FMC_SDCMR_NRFS(5) | FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_AUTO_REFRESH;
+  stm32_fmc_sdram_command(val);
+
+  /* Step 7:
+   * Configure the MRD field according to your SDRAM device, set the MODE
+   * bits to '100', and configure the Target Bank bits (CTB1 and/or CTB2)
+   * in the FMC_SDCMR register to issue a "Load Mode Register" command in
+   * order to program the SDRAM. In particular:
+   * a) The CAS latency must be selected following configured value in
+   *    FMC_SDCR1/2 registers
+   * b) The Burst Length (BL) of 1 must be selected by configuring the
+   *    M[2:0] bits to 000 in the mode register (refer to the SDRAM
+   *    datasheet). If the Mode Register is not the same for both SDRAM
+   *    banks, this step has to be repeated twice, once for each bank,
+   *    and the Target Bank bits set accordingly.
+   */
+
+  val = FMC_SDCMR_MDR_BURST_LENGTH_2 |
+    FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL |
+    FMC_SDCMR_MDR_CAS_LATENCY_2 |
+    FMC_SDCMR_MDR_MODE_NORMAL |
+    FMC_SDCMR_MDR_WBL_SINGLE | FMC_SDCMR_BANK_1 | FMC_SDCMR_CMD_LOAD_MODE;
+  stm32_fmc_sdram_command(val);
+
+  /* Step 8:
+   * Program the refresh rate in the FMC_SDRTR register
+   * The refresh rate corresponds to the delay between refresh cycles. Its
+   * value must be adapted to SDRAM devices.
+   */
+
+  stm32_fmc_sdram_set_refresh_rate(1292);       /* (64ms/4096rows) x 84MHz) - 20 */
+
+  /* Step 9:
+   * For mobile SDRAM devices, to program the extended mode register it
+   * should be done once the SDRAM device is initialized: First, a dummy
+   * read access should be performed while BA1=1 and BA=0 (refer to SDRAM
+   * address mapping section for BA[1:0] address mapping) in order to select
+   * the extended mode register instead of Load mode register and then
+   * program the needed value.
+   */
+
+  /* Setting EMRS is optional and we're not bothering ... */
+
+  /* Enable memory writes for bank 1 */
+
+  stm32_fmc_sdram_write_protect(1, false);
+
+  /* Wait for the controller to be ready */
+
+  stm32_fmc_sdram_wait();
+  return OK;
+}
diff --git a/configs/axoloti/src/stm32_sdio.c b/configs/axoloti/src/stm32_sdio.c
new file mode 100644
index 00000000000..9eadf24dd55
--- /dev/null
+++ b/configs/axoloti/src/stm32_sdio.c
@@ -0,0 +1,172 @@
+/****************************************************************************
+ * config/axoloti/src/stm32_sdio.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Jason T. Harris 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "stm32.h"
+#include "axoloti.h"
+
+#ifdef HAVE_SDIO
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Card detections requires card support and a card detection GPIO */
+
+#define HAVE_NCD 1
+#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD)
+#undef HAVE_NCD
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static FAR struct sdio_dev_s *g_sdio_dev;
+#ifdef HAVE_NCD
+static bool g_sd_inserted = 0xff;       /* Impossible value */
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_ncd_interrupt
+ *
+ * Description:
+ *   Card detect interrupt handler.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_NCD
+static int stm32_ncd_interrupt(int irq, FAR void *context, FAR void *arg)
+{
+  bool present;
+
+  present = !stm32_gpioread(GPIO_SDIO_NCD);
+  if (present != g_sd_inserted)
+    {
+      sdio_mediachange(g_sdio_dev, present);
+      g_sd_inserted = present;
+    }
+
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_sdio_initialize
+ *
+ * Description:
+ *   Initialize SDIO-based MMC/SD card support
+ *
+ ****************************************************************************/
+
+int stm32_sdio_initialize(void)
+{
+  int ret;
+
+#ifdef HAVE_NCD
+  bool cd_status;
+
+  /* Configure the card detect GPIO */
+
+  stm32_configgpio(GPIO_SDIO_NCD);
+
+  /* Register an interrupt handler for the card detect pin */
+
+  (void)stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true,
+                           stm32_ncd_interrupt, NULL);
+
+#endif
+
+  /* Mount the SDIO-based MMC/SD block driver.
+   * First, get an instance of the SDIO interface
+   */
+
+  finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO);
+  g_sdio_dev = sdio_initialize(SDIO_SLOTNO);
+  if (!g_sdio_dev)
+    {
+      ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO);
+      return -ENODEV;
+    }
+
+  /* Now bind the SDIO interface to the MMC/SD driver */
+
+  finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR);
+  ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev);
+  if (ret != OK)
+    {
+      ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret);
+      return ret;
+    }
+
+  finfo("Successfully bound SDIO to the MMC/SD driver\n");
+
+#ifdef HAVE_NCD
+  /* Use SD card detect pin to check if a card is g_sd_inserted */
+
+  cd_status = !stm32_gpioread(GPIO_SDIO_NCD);
+  finfo("Card detect : %d\n", cd_status);
+  sdio_mediachange(g_sdio_dev, cd_status);
+#else
+  /* Assume that the SD card is inserted.  What choice do we have? */
+
+  sdio_mediachange(g_sdio_dev, true);
+#endif
+
+  return OK;
+}
+
+#endif /* HAVE_SDIO */
diff --git a/configs/axoloti/src/stm32_usbhost.c b/configs/axoloti/src/stm32_usbhost.c
new file mode 100644
index 00000000000..9ca099c949b
--- /dev/null
+++ b/configs/axoloti/src/stm32_usbhost.c
@@ -0,0 +1,279 @@
+/****************************************************************************
+ * configs/axoloti/src/stm32_usbhost.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Jason T. Harris 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "up_arch.h"
+#include "stm32.h"
+#include "stm32_otghs.h"
+#include "axoloti.h"
+
+#ifdef CONFIG_STM32_OTGHS
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)
+#define HAVE_USB 1
+#else
+#warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST"
+#undef HAVE_USB
+#endif
+
+#ifndef CONFIG_AXOLOTI_USBHOST_PRIO
+#define CONFIG_AXOLOTI_USBHOST_PRIO 100
+#endif
+
+#ifndef CONFIG_AXOLOTI_USBHOST_STACKSIZE
+#define CONFIG_AXOLOTI_USBHOST_STACKSIZE 1024
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+static struct usbhost_connection_s *g_usbconn;
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: usbhost_waiter
+ *
+ * Description:
+ *   Wait for USB devices to be connected.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+static int usbhost_waiter(int argc, char *argv[])
+{
+  struct usbhost_hubport_s *hport;
+  uinfo("Running\n");
+
+  for (; ; )
+    {
+      /* Wait for the device to change state */
+
+      DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport));
+      uinfo("%s\n", hport->connected ? "connected" : "disconnected");
+
+      /* Did we just become connected? */
+
+      if (hport->connected)
+        {
+          /* Yes.. enumerate the newly connected device */
+
+         (void)CONN_ENUMERATE(g_usbconn, hport);
+        }
+    }
+
+  /* Keep the compiler from complaining */
+
+  return 0;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_usbinitialize
+ *
+ * Description:
+ *   Called from stm32_usbinitialize very early in inialization to setup
+ *   USB-related GPIO pins for the Axoloti board.
+ *
+ ****************************************************************************/
+
+void stm32_usbinitialize(void)
+{
+#ifdef CONFIG_STM32_OTGHS
+  stm32_configgpio(GPIO_OTGHS_PWRON);
+  stm32_configgpio(GPIO_OTGHS_OVER);
+#endif
+}
+
+/****************************************************************************
+ * Name: stm32_usbhost_vbusdrive
+ *
+ * Description:
+ *   Enable/disable driving of VBUS 5V output. This function must be provided
+ *   be each platform that implements the STM32 OTG HS host interface
+ *
+ * Input Parameters:
+ *   iface  - For future growth to handle multiple USB host interface. Should
+ *            be zero.
+ *   enable - true: enable VBUS power; false: disable VBUS power
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+void stm32_usbhost_vbusdrive(int iface, bool enable)
+{
+  DEBUGASSERT(iface == 0);
+  if (enable)
+    {
+      /* Enable the Power Switch by driving the enable pin low */
+
+      stm32_gpiowrite(GPIO_OTGHS_PWRON, false);
+    }
+  else
+    {
+      /* Disable the Power Switch by driving the enable pin high */
+
+      stm32_gpiowrite(GPIO_OTGHS_PWRON, true);
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_setup_overcurrent
+ *
+ * Description:
+ *   Setup to receive an interrupt-level callback if an overcurrent condition
+ *   is detected.
+ *
+ * Input Parameters:
+ *   handler - New overcurrent interrupt handler
+ *   arg     - The argument provided for the interrupt handler
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success. Otherwise, a negated errno value is
+ *   returned to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+int stm32_setup_overcurrent(xcpt_t handler, void *arg)
+{
+  return stm32_gpiosetevent(GPIO_OTGHS_OVER, true, true, true, handler, arg);
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_usbhost_initialize
+ *
+ * Description:
+ *   Called at application startup time to initialize the USB host
+ *   functionality. This function will start a thread that will monitor for
+ *   device connection/disconnection events.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_USBHOST
+int stm32_usbhost_initialize(void)
+{
+  int pid;
+  int ret;
+
+  /* First, register all of the class drivers needed to support the drivers
+   * that we care about:
+   */
+  uinfo("Register class drivers\n");
+
+#ifdef CONFIG_USBHOST_MSC
+  /* Register the USB mass storage class class */
+
+  ret = usbhost_msc_initialize();
+  if (ret != OK)
+    {
+      uerr("ERROR: Failed to register the mass storage class: %d\n", ret);
+    }
+#endif
+
+#ifdef CONFIG_USBHOST_HIDKBD
+  /* Initialize the HID keyboard class */
+
+  ret = usbhost_kbdinit();
+  if (ret != OK)
+    {
+      uerr("ERROR: Failed to register the HID keyboard class\n");
+    }
+#endif
+
+#ifdef CONFIG_USBHOST_HIDMOUSE
+  /* Initialize the HID mouse class */
+
+  ret = usbhost_mouse_init();
+  if (ret != OK)
+    {
+      uerr("ERROR: Failed to register the HID mouse class\n");
+    }
+#endif
+
+  /* Then get an instance of the USB host interface */
+
+  uinfo("Initialize USB host\n");
+  g_usbconn = stm32_otghshost_initialize(0);
+  if (g_usbconn)
+    {
+      /* Start a thread to handle device connection. */
+
+      uinfo("Start usbhost_waiter\n");
+      pid =
+        kthread_create("usbhost", CONFIG_AXOLOTI_USBHOST_PRIO,
+                       CONFIG_AXOLOTI_USBHOST_STACKSIZE,
+                       (main_t) usbhost_waiter, (FAR char *const *)NULL);
+      return pid < 0 ? -ENOEXEC : OK;
+    }
+
+  return -ENODEV;
+}
+#endif
+
+#endif /* CONFIG_STM32_OTGHS */
diff --git a/configs/axoloti/src/stm32_userleds.c b/configs/axoloti/src/stm32_userleds.c
new file mode 100644
index 00000000000..da60ac09979
--- /dev/null
+++ b/configs/axoloti/src/stm32_userleds.c
@@ -0,0 +1,108 @@
+/****************************************************************************
+ * configs/axoloti/src/stm32_userleds.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Jason T. Harris 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "stm32.h"
+#include "axoloti.h"
+
+#ifndef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This array maps an LED number to GPIO pin configuration */
+
+static uint32_t g_ledcfg[BOARD_NLEDS] =
+{
+  GPIO_LED1, GPIO_LED2,
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_userled_initialize
+ ****************************************************************************/
+
+void board_userled_initialize(void)
+{
+  /* Configure LED1-2 GPIOs for output */
+
+  stm32_configgpio(GPIO_LED1);
+  stm32_configgpio(GPIO_LED2);
+}
+
+/****************************************************************************
+ * Name: board_userled
+ ****************************************************************************/
+
+void board_userled(int led, bool ledon)
+{
+  if ((unsigned)led < BOARD_NLEDS)
+    {
+      stm32_gpiowrite(g_ledcfg[led], ledon);
+    }
+}
+
+/****************************************************************************
+ * Name: board_userled_all
+ ****************************************************************************/
+
+void board_userled_all(uint8_t ledset)
+{
+  stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0);
+  stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0);
+}
+
+#endif /* !CONFIG_ARCH_LEDS */
diff --git a/configs/b-l072z-lrwan1/adc/defconfig b/configs/b-l072z-lrwan1/adc/defconfig
new file mode 100644
index 00000000000..6c5aa20f724
--- /dev/null
+++ b/configs/b-l072z-lrwan1/adc/defconfig
@@ -0,0 +1,66 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_LIBC_LONG_LONG is not set
+# CONFIG_NSH_ARGCAT is not set
+CONFIG_ADC=y
+CONFIG_ANALOG=y
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="b-l072z-lrwan1"
+CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y
+CONFIG_ARCH_CHIP_STM32L072CZ=y
+CONFIG_ARCH_CHIP_STM32L072XX=y
+CONFIG_ARCH_CHIP_STM32L0=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=2796
+CONFIG_BUILTIN=y
+CONFIG_DISABLE_ENVIRON=y
+CONFIG_DISABLE_MOUNTPOINT=y
+CONFIG_DISABLE_MQUEUE=y
+CONFIG_DISABLE_POSIX_TIMERS=y
+CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
+CONFIG_EXAMPLES_ADC=y
+CONFIG_EXAMPLES_ADC_SWTRIG=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_INTELHEX_BINARY=y
+CONFIG_MAX_TASKS=8
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_NFILE_DESCRIPTORS=6
+CONFIG_NFILE_STREAMS=6
+CONFIG_NPTHREAD_KEYS=0
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=64
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_NUNGET_CHARS=0
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_PTHREAD_MUTEX_UNSAFE=y
+CONFIG_PTHREAD_STACK_DEFAULT=1536
+CONFIG_RAM_SIZE=20480
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_START_DAY=19
+CONFIG_START_MONTH=5
+CONFIG_START_YEAR=2013
+CONFIG_STDIO_DISABLE_BUFFERING=y
+CONFIG_STM32F0L0G0_ADC1=y
+CONFIG_STM32F0L0G0_ADC1_DMA=y
+CONFIG_STM32F0L0G0_DMA1=y
+CONFIG_STM32F0L0G0_PWR=y
+CONFIG_STM32F0L0G0_USART2=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
+CONFIG_USART2_SERIAL_CONSOLE=y
+CONFIG_USERMAIN_STACKSIZE=1536
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_WDOG_INTRESERVE=0
diff --git a/configs/b-l072z-lrwan1/include/board.h b/configs/b-l072z-lrwan1/include/board.h
index d4a2dbafb41..73d7fee954d 100644
--- a/configs/b-l072z-lrwan1/include/board.h
+++ b/configs/b-l072z-lrwan1/include/board.h
@@ -98,6 +98,14 @@
 #define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd2
 #define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
 
+/* 48MHz clock configuration */
+
+#if defined(CONFIG_STM32F0L0G0_USB) || defined(CONFIG_STM32F0L0G0_RNG)
+#  define STM32_USE_CLK48       1
+#  define STM32_CLK48_SEL       RCC_CCIPR_CLK48SEL_HSI48
+#  define STM32_HSI48_SYNCSRC   SYNCSRC_NONE
+#endif
+
 /* TODO: timers */
 
 /* LED definitions **********************************************************/
@@ -243,11 +251,11 @@
 /* I2C1 */
 
 #define GPIO_I2C1_SDA  GPIO_I2C1_SDA_2 /* PB9 */
-#define GPIO_I2C1_SCLK GPIO_I2C1_SCL_2 /* PB8 */
+#define GPIO_I2C1_SCL  GPIO_I2C1_SCL_2 /* PB8 */
 
 /* DMA channels *************************************************************/
 /* ADC */
 
-#define ADC1_DMA_CHAN DMACHAN_ADC1     /* DMA1_CH1 */
+#define ADC1_DMA_CHAN DMACHAN_ADC1_1    /* DMA1_CH1 */
 
 #endif /* __CONFIG_NUCLEO_LO73RZ_INCLUDE_BOARD_H */
diff --git a/configs/b-l072z-lrwan1/nsh/defconfig b/configs/b-l072z-lrwan1/nsh/defconfig
index df93e20dccc..1889cfb3e46 100644
--- a/configs/b-l072z-lrwan1/nsh/defconfig
+++ b/configs/b-l072z-lrwan1/nsh/defconfig
@@ -18,7 +18,6 @@ CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 CONFIG_EXAMPLES_HELLO=y
@@ -48,8 +47,8 @@ CONFIG_START_DAY=19
 CONFIG_START_MONTH=5
 CONFIG_START_YEAR=2013
 CONFIG_STDIO_DISABLE_BUFFERING=y
-CONFIG_STM32F0L0_PWR=y
-CONFIG_STM32F0L0_USART2=y
+CONFIG_STM32F0L0G0_PWR=y
+CONFIG_STM32F0L0G0_USART2=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_TASK_NAME_SIZE=0
 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
diff --git a/configs/b-l072z-lrwan1/nxlines_oled/defconfig b/configs/b-l072z-lrwan1/nxlines_oled/defconfig
new file mode 100644
index 00000000000..8eea9cc24ab
--- /dev/null
+++ b/configs/b-l072z-lrwan1/nxlines_oled/defconfig
@@ -0,0 +1,72 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set
+# CONFIG_LIBC_LONG_LONG is not set
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NX_DISABLE_1BPP is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="b-l072z-lrwan1"
+CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y
+CONFIG_ARCH_CHIP_STM32L072CZ=y
+CONFIG_ARCH_CHIP_STM32L072XX=y
+CONFIG_ARCH_CHIP_STM32L0=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=2796
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_EXAMPLES_NXLINES=y
+CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=1
+CONFIG_EXAMPLES_NXLINES_BPP=1
+CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xff
+CONFIG_EXAMPLES_NXLINES_LINEWIDTH=1
+CONFIG_EXPERIMENTAL=y
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LCD=y
+CONFIG_LCD_MAXCONTRAST=255
+CONFIG_LCD_SH1106_OLED_132=y
+CONFIG_LCD_SSD1306_I2C=y
+CONFIG_MAX_TASKS=8
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_MQ_MAXMSGSIZE=64
+CONFIG_NFILE_DESCRIPTORS=6
+CONFIG_NFILE_STREAMS=6
+CONFIG_NPTHREAD_KEYS=0
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=64
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_NUNGET_CHARS=0
+CONFIG_NX=y
+CONFIG_NXFONT_MONO5X8=y
+CONFIG_NX_BLOCKING=y
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_PTHREAD_MUTEX_UNSAFE=y
+CONFIG_PTHREAD_STACK_DEFAULT=1536
+CONFIG_RAM_SIZE=20480
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_START_DAY=19
+CONFIG_START_MONTH=5
+CONFIG_START_YEAR=2013
+CONFIG_STDIO_DISABLE_BUFFERING=y
+CONFIG_STM32F0L0G0_I2C1=y
+CONFIG_STM32F0L0G0_PWR=y
+CONFIG_STM32F0L0G0_USART2=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_NSH_STACKSIZE=1024
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
+CONFIG_USART2_SERIAL_CONSOLE=y
+CONFIG_USERMAIN_STACKSIZE=1536
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_WDOG_INTRESERVE=0
diff --git a/configs/b-l072z-lrwan1/scripts/ld.script b/configs/b-l072z-lrwan1/scripts/ld.script
index 08655e1641c..c65394ecf6f 100644
--- a/configs/b-l072z-lrwan1/scripts/ld.script
+++ b/configs/b-l072z-lrwan1/scripts/ld.script
@@ -52,73 +52,77 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The RAM vector table (if present) should lie at the beginning of SRAM */
+        /* The RAM vector table (if present) should lie at the beginning of SRAM */
 
-	.ram_vectors : {
-		*(.ram_vectors)
-	} > sram
+        .ram_vectors : {
+                *(.ram_vectors)
+        } > sram
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/b-l072z-lrwan1/src/Makefile b/configs/b-l072z-lrwan1/src/Makefile
index e862eb92386..246c7eec061 100644
--- a/configs/b-l072z-lrwan1/src/Makefile
+++ b/configs/b-l072z-lrwan1/src/Makefile
@@ -48,7 +48,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
 CSRCS += stm32_buttons.c
 endif
 
-ifeq ($(CONFIG_STM32F0L0_SPI),y)
+ifeq ($(CONFIG_STM32F0L0G0_SPI),y)
 CSRCS += stm32_spi.c
 endif
 
@@ -60,4 +60,12 @@ ifeq ($(CONFIG_LPWAN_SX127X),y)
 CSRCS += stm32_sx127x.c
 endif
 
+ifeq ($(CONFIG_ADC),y)
+CSRCS += stm32_adc.c
+endif
+
+ifeq ($(CONFIG_LCD_SSD1306),y)
+CSRCS += stm32_ssd1306.c
+endif
+
 include $(TOPDIR)/configs/Board.mk
diff --git a/configs/b-l072z-lrwan1/src/b-l072z-lrwan1.h b/configs/b-l072z-lrwan1/src/b-l072z-lrwan1.h
index 6c3e1bbb2d2..19ea9565c06 100644
--- a/configs/b-l072z-lrwan1/src/b-l072z-lrwan1.h
+++ b/configs/b-l072z-lrwan1/src/b-l072z-lrwan1.h
@@ -114,6 +114,10 @@
 #define GPIO_SX127X_CRF2  (GPIO_SPEED_HIGH | GPIO_PORTC | GPIO_PIN2)
 #define GPIO_SX127X_CRF3  (GPIO_SPEED_HIGH | GPIO_PORTC | GPIO_PIN1)
 
+/* Oled configuration */
+
+#define OLED_I2C_PORT   1
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/
@@ -146,7 +150,7 @@ int stm32_bringup(void);
  *
  ************************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI
+#ifdef CONFIG_STM32F0L0G0_SPI
 void stm32_spidev_initialize(void);
 #endif
 
@@ -161,4 +165,16 @@ void stm32_spidev_initialize(void);
 int stm32_lpwaninitialize(void);
 #endif
 
+/************************************************************************************
+ * Name: stm32_adc_setup
+ *
+ * Description:
+ *   Initialize ADC and register the ADC driver.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_ADC
+int stm32_adc_setup(void);
+#endif
+
 #endif /* __CONFIGS_B_L072Z_LRWAN1_SRC_B_L072Z_LRWAN1_H */
diff --git a/configs/b-l072z-lrwan1/src/stm32_adc.c b/configs/b-l072z-lrwan1/src/stm32_adc.c
new file mode 100644
index 00000000000..b7a6b657d6e
--- /dev/null
+++ b/configs/b-l072z-lrwan1/src/stm32_adc.c
@@ -0,0 +1,145 @@
+/****************************************************************************
+ * configs/b-l072z-lrwan1/src/stm32_adc.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "stm32.h"
+
+#if defined(CONFIG_ADC) && defined(CONFIG_STM32F0L0G0_ADC1)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* The number of ADC channels in the conversion list */
+
+#define ADC1_NCHANNELS 2
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Identifying number of each ADC channel (even if NCHANNELS is less ) */
+
+static const uint8_t g_chanlist1[2] =
+{
+  0,
+  4,
+};
+
+/* Configurations of pins used by each ADC channel */
+
+static const uint32_t g_pinlist1[2]  =
+{
+  GPIO_ADC1_IN0,                /* PA0/A0 */
+  GPIO_ADC1_IN4                 /* PA4/A2 */
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_adc_setup
+ *
+ * Description:
+ *   Initialize ADC and register the ADC driver.
+ *
+ ****************************************************************************/
+
+int stm32_adc_setup(void)
+{
+  static bool initialized = false;
+  FAR struct adc_dev_s *adc;
+  int ret;
+  int i;
+
+  /* Check if we have already initialized */
+
+  if (!initialized)
+    {
+      /* Configure the pins as analog inputs for the selected channels */
+
+      for (i = 0; i < ADC1_NCHANNELS; i++)
+        {
+          stm32_configgpio(g_pinlist1[i]);
+        }
+
+      /* Call stm32_adcinitialize() to get an instance of the ADC interface */
+
+      adc = stm32_adcinitialize(1, g_chanlist1, ADC1_NCHANNELS);
+      if (adc == NULL)
+        {
+          aerr("ERROR: Failed to get ADC interface 1\n");
+          return -ENODEV;
+        }
+
+      /* Register the ADC driver at "/dev/adc0" */
+
+      ret = adc_register("/dev/adc0", adc);
+      if (ret < 0)
+        {
+          aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret);
+          return ret;
+        }
+
+      initialized = true;
+    }
+
+  return OK;
+}
+
+#endif /* CONFIG_ADC && CONFIG_STM32F0L0G0_ADC1 */
diff --git a/configs/b-l072z-lrwan1/src/stm32_boot.c b/configs/b-l072z-lrwan1/src/stm32_boot.c
index 6c3a45d4623..91dd57707a5 100644
--- a/configs/b-l072z-lrwan1/src/stm32_boot.c
+++ b/configs/b-l072z-lrwan1/src/stm32_boot.c
@@ -84,7 +84,7 @@ void stm32_boardinitialize(void)
   board_autoled_initialize();
 #endif
 
-#ifdef CONFIG_STM32F0L0_SPI
+#ifdef CONFIG_STM32F0L0G0_SPI
   /* Configure SPI chip selects */
 
   stm32_spidev_initialize();
diff --git a/configs/b-l072z-lrwan1/src/stm32_bringup.c b/configs/b-l072z-lrwan1/src/stm32_bringup.c
index 322d621f40c..65d12f6ab01 100644
--- a/configs/b-l072z-lrwan1/src/stm32_bringup.c
+++ b/configs/b-l072z-lrwan1/src/stm32_bringup.c
@@ -63,6 +63,65 @@
 #  define HAVE_DAC2 1
 #endif
 
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_i2c_register
+ *
+ * Description:
+ *   Register one I2C drivers for the I2C tool.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL)
+static void stm32_i2c_register(int bus)
+{
+  FAR struct i2c_master_s *i2c;
+  int ret;
+
+  i2c = stm32_i2cbus_initialize(bus);
+  if (i2c == NULL)
+    {
+      syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus);
+    }
+  else
+    {
+      ret = i2c_register(i2c, bus);
+      if (ret < 0)
+        {
+          syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n",
+                 bus, ret);
+          stm32_i2cbus_uninitialize(i2c);
+        }
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_i2ctool
+ *
+ * Description:
+ *   Register I2C drivers for the I2C tool.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL)
+static void stm32_i2ctool(void)
+{
+#ifdef CONFIG_STM32F0L0G0_I2C1
+  stm32_i2c_register(1);
+#endif
+#ifdef CONFIG_STM32F0L0G0_I2C2
+  stm32_i2c_register(2);
+#endif
+#ifdef CONFIG_STM32F0L0G0_I2C3
+  stm32_i2c_register(3);
+#endif
+}
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
diff --git a/configs/b-l072z-lrwan1/src/stm32_spi.c b/configs/b-l072z-lrwan1/src/stm32_spi.c
index 4cdc1de26a8..11ea02946ae 100644
--- a/configs/b-l072z-lrwan1/src/stm32_spi.c
+++ b/configs/b-l072z-lrwan1/src/stm32_spi.c
@@ -54,7 +54,7 @@
 #include "b-l072z-lrwan1.h"
 #include 
 
-#ifdef CONFIG_STM32F0L0_SPI
+#ifdef CONFIG_STM32F0L0G0_SPI
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -92,7 +92,7 @@ void stm32_spidev_initialize(void)
    *       architecture.
    */
 
-#ifdef CONFIG_STM32F0L0_SPI1
+#ifdef CONFIG_STM32F0L0G0_SPI1
 #  ifdef CONFIG_LPWAN_SX127X
   /* Configure the SPI-based SX127X chip select GPIO */
 
@@ -130,7 +130,7 @@ void stm32_spidev_initialize(void)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI1
+#ifdef CONFIG_STM32F0L0G0_SPI1
 void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid,
                       bool selected)
 {
@@ -177,9 +177,9 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
 
   return status;
 }
-#endif  /* CONFIG_STM32F0L0_SPI1 */
+#endif  /* CONFIG_STM32F0L0G0_SPI1 */
 
-#ifdef CONFIG_STM32F0L0_SPI2
+#ifdef CONFIG_STM32F0L0G0_SPI2
 void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid,
                       bool selected)
 {
@@ -190,7 +190,7 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid)
 {
   return 0;
 }
-#endif  /* CONFIG_STM32F0L0_SPI2 */
+#endif  /* CONFIG_STM32F0L0G0_SPI2 */
 
-#endif  /* CONFIG_STM32F0L0_SPI */
+#endif  /* CONFIG_STM32F0L0G0_SPI */
 
diff --git a/configs/b-l072z-lrwan1/src/stm32_ssd1306.c b/configs/b-l072z-lrwan1/src/stm32_ssd1306.c
new file mode 100644
index 00000000000..6234d0a80b2
--- /dev/null
+++ b/configs/b-l072z-lrwan1/src/stm32_ssd1306.c
@@ -0,0 +1,124 @@
+/****************************************************************************
+ * config/b-l072z-lrwan1/src/stm32_ssd1306.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "stm32.h"
+#include "b-l072z-lrwan1.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#ifndef CONFIG_LCD_MAXPOWER
+#  define CONFIG_LCD_MAXPOWER 1
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+FAR struct i2c_master_s *g_i2c;
+FAR struct lcd_dev_s    *g_lcddev;
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_lcd_initialize
+ ****************************************************************************/
+
+int board_lcd_initialize(void)
+{
+  /* Initialize I2C */
+
+  g_i2c = stm32_i2cbus_initialize(OLED_I2C_PORT);
+  if (!g_i2c)
+    {
+      lcderr("ERROR: Failed to initialize I2C port %d\n", OLED_I2C_PORT);
+      return -ENODEV;
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: board_lcd_getdev
+ ****************************************************************************/
+
+FAR struct lcd_dev_s *board_lcd_getdev(int devno)
+{
+  /* Bind the I2C port to the OLED */
+
+  g_lcddev = ssd1306_initialize(g_i2c, NULL, devno);
+  if (!g_lcddev)
+    {
+      lcderr("ERROR: Failed to bind I2C port 1 to OLED %d: %d\n", devno);
+    }
+  else
+    {
+      lcdinfo("Bound I2C port %d to OLED %d\n", OLED_I2C_PORT, devno);
+
+      /* And turn the OLED on */
+
+      (void)g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER);
+      return g_lcddev;
+    }
+
+  return NULL;
+}
+
+/****************************************************************************
+ * Name: board_lcd_uninitialize
+ ****************************************************************************/
+
+void board_lcd_uninitialize(void)
+{
+  /* TO-FIX */
+}
diff --git a/configs/b-l072z-lrwan1/sx127x/defconfig b/configs/b-l072z-lrwan1/sx127x/defconfig
index e5658f16a5a..65e839cd12a 100644
--- a/configs/b-l072z-lrwan1/sx127x/defconfig
+++ b/configs/b-l072z-lrwan1/sx127x/defconfig
@@ -18,7 +18,6 @@ CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 CONFIG_DRIVERS_LPWAN=y
@@ -58,9 +57,9 @@ CONFIG_START_DAY=19
 CONFIG_START_MONTH=5
 CONFIG_START_YEAR=2013
 CONFIG_STDIO_DISABLE_BUFFERING=y
-CONFIG_STM32F0L0_PWR=y
-CONFIG_STM32F0L0_SPI1=y
-CONFIG_STM32F0L0_USART2=y
+CONFIG_STM32F0L0G0_PWR=y
+CONFIG_STM32F0L0G0_SPI1=y
+CONFIG_STM32F0L0G0_USART2=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_TASK_NAME_SIZE=0
 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
diff --git a/configs/b-l475e-iot01a/include/board.h b/configs/b-l475e-iot01a/include/board.h
index e4d408990f1..207b9ed25e4 100644
--- a/configs/b-l475e-iot01a/include/board.h
+++ b/configs/b-l475e-iot01a/include/board.h
@@ -173,7 +173,6 @@
 #define GPIO_QSPI_IO3 (GPIO_QSPI_BK1_IO3_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
 #define GPIO_QSPI_SCK (GPIO_QSPI_CLK_2     | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz)
 
-
 /************************************************************************************
  * Public Data
  ************************************************************************************/
diff --git a/configs/b-l475e-iot01a/nsh/defconfig b/configs/b-l475e-iot01a/nsh/defconfig
index 24428b21c0c..72410ea4b56 100644
--- a/configs/b-l475e-iot01a/nsh/defconfig
+++ b/configs/b-l475e-iot01a/nsh/defconfig
@@ -16,7 +16,6 @@ CONFIG_ARCH_CHIP_STM32L4=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=8025
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
diff --git a/configs/b-l475e-iot01a/spirit-6lowpan/defconfig b/configs/b-l475e-iot01a/spirit-6lowpan/defconfig
index 00339bed568..0055fb0c9e8 100644
--- a/configs/b-l475e-iot01a/spirit-6lowpan/defconfig
+++ b/configs/b-l475e-iot01a/spirit-6lowpan/defconfig
@@ -53,6 +53,8 @@ CONFIG_NETDEVICES=y
 CONFIG_NETDEV_LATEINIT=y
 CONFIG_NETDEV_STATISTICS=y
 CONFIG_NETDEV_WIRELESS_IOCTL=y
+CONFIG_NETINIT_NETLOCAL=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NET_6LOWPAN=y
 CONFIG_NET_BROADCAST=y
@@ -72,8 +74,6 @@ CONFIG_NSH_DISABLE_PUT=y
 CONFIG_NSH_DISABLE_WGET=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETLOCAL=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/b-l475e-iot01a/spirit-starhub/defconfig b/configs/b-l475e-iot01a/spirit-starhub/defconfig
index d8beec746e8..9e0519ce4c1 100644
--- a/configs/b-l475e-iot01a/spirit-starhub/defconfig
+++ b/configs/b-l475e-iot01a/spirit-starhub/defconfig
@@ -42,6 +42,8 @@ CONFIG_NETDEVICES=y
 CONFIG_NETDEV_LATEINIT=y
 CONFIG_NETDEV_STATISTICS=y
 CONFIG_NETDEV_WIRELESS_IOCTL=y
+CONFIG_NETINIT_NETLOCAL=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NET_6LOWPAN=y
 CONFIG_NET_BROADCAST=y
@@ -63,8 +65,6 @@ CONFIG_NSH_DISABLE_PUT=y
 CONFIG_NSH_DISABLE_WGET=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETLOCAL=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/b-l475e-iot01a/spirit-starpoint/defconfig b/configs/b-l475e-iot01a/spirit-starpoint/defconfig
index f31da9ecb17..1aee5bca757 100644
--- a/configs/b-l475e-iot01a/spirit-starpoint/defconfig
+++ b/configs/b-l475e-iot01a/spirit-starpoint/defconfig
@@ -54,6 +54,8 @@ CONFIG_NETDEVICES=y
 CONFIG_NETDEV_LATEINIT=y
 CONFIG_NETDEV_STATISTICS=y
 CONFIG_NETDEV_WIRELESS_IOCTL=y
+CONFIG_NETINIT_NETLOCAL=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NET_6LOWPAN=y
 CONFIG_NET_BROADCAST=y
@@ -74,8 +76,6 @@ CONFIG_NSH_DISABLE_PUT=y
 CONFIG_NSH_DISABLE_WGET=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETLOCAL=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/bambino-200e/kernel/lpc43_userspace.c b/configs/bambino-200e/kernel/lpc43_userspace.c
index 8e87c9a101c..8e732d4bc7e 100644
--- a/configs/bambino-200e/kernel/lpc43_userspace.c
+++ b/configs/bambino-200e/kernel/lpc43_userspace.c
@@ -115,9 +115,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/bambino-200e/netnsh/defconfig b/configs/bambino-200e/netnsh/defconfig
index 7be95833d75..6c7cc93867a 100644
--- a/configs/bambino-200e/netnsh/defconfig
+++ b/configs/bambino-200e/netnsh/defconfig
@@ -40,6 +40,12 @@ CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSCLIENT_ENTRIES=4
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_DHCPC=y
+CONFIG_NETINIT_DRIPADDR=0xc0a80001
+CONFIG_NETINIT_MACADDR_1=0x3c4d5e6f
+CONFIG_NETINIT_MACADDR_2=0x1a2b
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_DISCOVER=y
 CONFIG_NETUTILS_TELNETD=y
@@ -51,7 +57,6 @@ CONFIG_NET_ETH_PKTSIZE=650
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=40
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -62,13 +67,8 @@ CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
-CONFIG_NSH_DHCPC=y
-CONFIG_NSH_DRIPADDR=0xc0a80001
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_MACADDR=0x1a2b3c4d5e6f
-CONFIG_NSH_NETINIT_THREAD=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=10
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/bambino-200e/scripts/memory.ld b/configs/bambino-200e/scripts/memory.ld
index 02e1f729768..3beb58402bd 100644
--- a/configs/bambino-200e/scripts/memory.ld
+++ b/configs/bambino-200e/scripts/memory.ld
@@ -54,7 +54,7 @@
  * Alignment of the user space FLASH partition is also a critical factor:
  * The user space FLASH partition will be spanned with a single region of
  * size 2**n bytes.  The alignment of the user-space region must be the same.
- * As a consequence, as the user-space increases in size, the alignmment
+ * As a consequence, as the user-space increases in size, the alignment
  * requirement also increases.
  *
  * This alignment requirement means that the largest user space FLASH region
diff --git a/configs/bambino-200e/src/lpc43_ostest.c b/configs/bambino-200e/src/lpc43_ostest.c
index 4fb9e1fffa6..fac37f9af57 100644
--- a/configs/bambino-200e/src/lpc43_ostest.c
+++ b/configs/bambino-200e/src/lpc43_ostest.c
@@ -60,7 +60,7 @@
 
 #undef HAVE_FPU
 #if defined(CONFIG_ARCH_FPU) && defined(CONFIG_TESTING_OSTEST_FPUSIZE) && \
-    defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_DISABLE_SIGNALS)
+    defined(CONFIG_SCHED_WAITPID)
 #    define HAVE_FPU 1
 #endif
 
diff --git a/configs/beaglebone-black/include/board.h b/configs/beaglebone-black/include/board.h
index dfcab9ba112..1f67da73f1e 100644
--- a/configs/beaglebone-black/include/board.h
+++ b/configs/beaglebone-black/include/board.h
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/am335x_pinmux.h"
+#include "hardware/am335x_pinmux.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/configs/beaglebone-black/nsh/defconfig b/configs/beaglebone-black/nsh/defconfig
index f9566b7dff4..f2b729b01c6 100644
--- a/configs/beaglebone-black/nsh/defconfig
+++ b/configs/beaglebone-black/nsh/defconfig
@@ -23,7 +23,6 @@ CONFIG_BOARD_LOOPSPERMSEC=49341
 CONFIG_BOOT_RUNFROMSDRAM=y
 CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
 CONFIG_FAT_LCNAMES=y
diff --git a/configs/boardctl.c b/configs/boardctl.c
index ea238183478..4817e8279cb 100644
--- a/configs/boardctl.c
+++ b/configs/boardctl.c
@@ -512,47 +512,25 @@ int boardctl(unsigned int cmd, uintptr_t arg)
         }
         break;
 
-      /* CMD:           BOARDIOC_NXTERM_REDRAW
-       * DESCRIPTION:   Re-draw a portion of the NX console.  This function
-       *                should be called from the appropriate window callback
-       *                logic.
-       * ARG:           A reference readable instance of struct
-       *                boardioc_nxterm_redraw_s
+      /* CMD:           BOARDIOC_NXTERM_IOCTL
+       * DESCRIPTION:   Create an NX terminal IOCTL command.  Normal IOCTLs
+       *                cannot be be performed in most graphics contexts since
+       *                the depend on the task holding an open file descriptor
+       * ARG:           A reference readable/writable instance of struct
+       *                boardioc_nxterm_ioctl_s
        * CONFIGURATION: CONFIG_NXTERM
-       * DEPENDENCIES:  Base NX terminal logic provides nxterm_redraw()
+       * DEPENDENCIES:  Base NX terminal logic provides nxterm_ioctl_tap()
        */
 
-       case BOARDIOC_NXTERM_REDRAW:
-         {
-           FAR struct boardioc_nxterm_redraw_s *redraw =
-             (FAR struct boardioc_nxterm_redraw_s *)((uintptr_t)arg);
+      case BOARDIOC_NXTERM_IOCTL:
+        {
+          FAR struct boardioc_nxterm_ioctl_s *nxterm =
+            (FAR struct boardioc_nxterm_ioctl_s *)arg;
 
-           nxterm_redraw(redraw->handle, &redraw->rect, redraw->more);
-           ret = OK;
-         }
-         break;
+          ret = nxterm_ioctl_tap(nxterm->cmd, nxterm->arg);
+        }
+        break;
 
-      /* CMD:           BOARDIOC_NXTERM_KBDIN
-       * DESCRIPTION:   Provide NxTerm keyboard input to NX.
-       * ARG:           A reference readable instance of struct
-       *                boardioc_nxterm_kbdin_s
-       * CONFIGURATION: CONFIG_NXTERM_NXKBDIN
-       * DEPENDENCIES:  Base NX terminal logic provides nxterm_kbdin()
-       */
-
-       case BOARDIOC_NXTERM_KBDIN:
-         {
-#ifdef CONFIG_NXTERM_NXKBDIN
-           FAR struct boardioc_nxterm_kbdin_s *kbdin =
-             (FAR struct boardioc_nxterm_kbdin_s *)((uintptr_t)arg);
-
-           nxterm_kbdin(kbdin->handle, kbdin->buffer, kbdin->buflen);
-           ret = OK;
-#else
-           ret = -ENOSYS;
-#endif
-         }
-         break;
 #endif /* CONFIG_NXTERM */
 
 #ifdef CONFIG_BOARDCTL_TESTSET
diff --git a/configs/c5471evm/httpd/defconfig b/configs/c5471evm/httpd/defconfig
index 38576c28db3..aef58aaffa5 100644
--- a/configs/c5471evm/httpd/defconfig
+++ b/configs/c5471evm/httpd/defconfig
@@ -16,7 +16,6 @@ CONFIG_BOARD_LOOPSPERMSEC=1250
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_WEBSERVER=y
 CONFIG_IDLETHREAD_STACKSIZE=4096
 CONFIG_MAX_TASKS=64
diff --git a/configs/c5471evm/nettest/defconfig b/configs/c5471evm/nettest/defconfig
index 0f2973aa9a2..698e87c4ac3 100644
--- a/configs/c5471evm/nettest/defconfig
+++ b/configs/c5471evm/nettest/defconfig
@@ -16,7 +16,6 @@ CONFIG_BOARD_LOOPSPERMSEC=1250
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_EXAMPLES_NETTEST=y
 CONFIG_EXAMPLES_NETTEST_NOMAC=y
diff --git a/configs/c5471evm/nsh/defconfig b/configs/c5471evm/nsh/defconfig
index ca353a62ff0..25c690c7b92 100644
--- a/configs/c5471evm/nsh/defconfig
+++ b/configs/c5471evm/nsh/defconfig
@@ -19,27 +19,25 @@ CONFIG_BOARD_LOOPSPERMSEC=1250
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_IDLETHREAD_STACKSIZE=4096
 CONFIG_MAX_TASKS=16
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSCLIENT_ENTRIES=4
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_MAX_LISTENPORTS=8
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_UDP=y
 CONFIG_NET_UDP_CHECKSUMS=y
 CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_WDOGS=8
 CONFIG_PTHREAD_STACK_DEFAULT=4096
diff --git a/configs/c5471evm/scripts/ld.script b/configs/c5471evm/scripts/ld.script
index b2beda678c2..193241d91d5 100644
--- a/configs/c5471evm/scripts/ld.script
+++ b/configs/c5471evm/scripts/ld.script
@@ -37,71 +37,72 @@ OUTPUT_ARCH(arm)
 ENTRY(_stext)
 SECTIONS
 {
-	/* Interrupt vector trampoline and command line parameters
-	 * are provided in IRAM by the rrload bootloader.  Vectors will be
-	 * copied into _svectors.
-	 */
+        /* Interrupt vector trampoline and command line parameters
+         * are provided in IRAM by the rrload bootloader.  Vectors will be
+         * copied into _svectors.
+         */
 
-	. = 0xffc00000;
-	_svectors = ABSOLUTE(.);
+        . = 0xffc00000;
+        _svectors = ABSOLUTE(.);
 
-	/* These are locations in IRAM where the rrload bootloader passes
-	 * information to the running program
-	 */
+        /* These are locations in IRAM where the rrload bootloader passes
+         * information to the running program
+         */
 
-	. = 0xffc00020;
-	__KernCommandLineMagicStr = .;	/* magic pattern string == "kcmdline-->" */
-	. = 0xffc0002C;			/* advance to .+strlen("kcmdline-->")+1 */
-	__KernCommandLineOverride = .;	/* location of kernel command line string */
+        . = 0xffc00020;
+        __KernCommandLineMagicStr = .;  /* magic pattern string == "kcmdline-->" */
+        . = 0xffc0002C;                 /* advance to .+strlen("kcmdline-->")+1 */
+        __KernCommandLineOverride = .;  /* location of kernel command line string */
 
-	. = 0xffc00100;
-	__EtherMACMagicStr = .;		/* magic pattern string == "etherMAC-->" */
-	. = 0xffc0010C;			/* advance to .+strlen("etherMAC-->")+1 */
-	__EtherMAC = .;
+        . = 0xffc00100;
+        __EtherMACMagicStr = .;         /* magic pattern string == "etherMAC-->" */
+        . = 0xffc0010C;                 /* advance to .+strlen("etherMAC-->")+1 */
+        __EtherMAC = .;
 
 
-	/* The OS entry point is here */
+        /* The OS entry point is here */
 
-	. = 0x10300000;
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.text)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)			/* Global offset table		*/
-		_etext = ABSOLUTE(.);
-	}
+        . = 0x10300000;
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.text)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)                 /* Global offset table          */
+                _etext = ABSOLUTE(.);
+        }
 
-	_eronly = ABSOLUTE(.);		/* See below                    */
-	. = ALIGN(4096);
+        _eronly = ABSOLUTE(.);          /* See below                    */
+        . = ALIGN(4096);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	}
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        }
 
-	.bss : {			/* BSS				*/
-		_sbss = ABSOLUTE(.);
-		*(.bss)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	}
-					/* Stabs debugging sections.	*/
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        .bss : {                        /* BSS                          */
+                _sbss = ABSOLUTE(.);
+                *(.bss)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        }
+                                        /* Stabs debugging sections.    */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/clicker2-stm32/kernel/stm32_userspace.c b/configs/clicker2-stm32/kernel/stm32_userspace.c
index cc8f207c56d..b844531ca7d 100644
--- a/configs/clicker2-stm32/kernel/stm32_userspace.c
+++ b/configs/clicker2-stm32/kernel/stm32_userspace.c
@@ -115,9 +115,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/clicker2-stm32/knsh/defconfig b/configs/clicker2-stm32/knsh/defconfig
index ee9c4769258..6ecbefb78d5 100644
--- a/configs/clicker2-stm32/knsh/defconfig
+++ b/configs/clicker2-stm32/knsh/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARM_MPU=y
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILD_PROTECTED=y
-CONFIG_DISABLE_POLL=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
 CONFIG_FS_PROCFS=y
diff --git a/configs/clicker2-stm32/mrf24j40-6lowpan/defconfig b/configs/clicker2-stm32/mrf24j40-6lowpan/defconfig
index 3603647f9b9..9bcb6df6044 100644
--- a/configs/clicker2-stm32/mrf24j40-6lowpan/defconfig
+++ b/configs/clicker2-stm32/mrf24j40-6lowpan/defconfig
@@ -8,7 +8,6 @@
 # CONFIG_DEV_CONSOLE is not set
 # CONFIG_NET_ETHERNET is not set
 # CONFIG_NET_IPv4 is not set
-# CONFIG_NSH_DISABLE_TELNETD is not set
 CONFIG_ARCH="arm"
 CONFIG_ARCH_BOARD="clicker2-stm32"
 CONFIG_ARCH_BOARD_CLICKER2_STM32=y
@@ -68,6 +67,8 @@ CONFIG_NETDEVICES=y
 CONFIG_NETDEV_LATEINIT=y
 CONFIG_NETDEV_STATISTICS=y
 CONFIG_NETDEV_WIRELESS_IOCTL=y
+CONFIG_NETINIT_NETLOCAL=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NET_6LOWPAN=y
 CONFIG_NET_BROADCAST=y
@@ -87,8 +88,6 @@ CONFIG_NSH_DISABLE_PUT=y
 CONFIG_NSH_DISABLE_WGET=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETLOCAL=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/clicker2-stm32/mrf24j40-mac/defconfig b/configs/clicker2-stm32/mrf24j40-mac/defconfig
index 090f11d10ae..ff063e12b36 100644
--- a/configs/clicker2-stm32/mrf24j40-mac/defconfig
+++ b/configs/clicker2-stm32/mrf24j40-mac/defconfig
@@ -16,7 +16,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_IEEE802154=y
 CONFIG_DRIVERS_WIRELESS=y
 CONFIG_SYSTEM_NSH=y
diff --git a/configs/clicker2-stm32/mrf24j40-starhub/defconfig b/configs/clicker2-stm32/mrf24j40-starhub/defconfig
index af55c344cb0..a00f7c5bcb1 100644
--- a/configs/clicker2-stm32/mrf24j40-starhub/defconfig
+++ b/configs/clicker2-stm32/mrf24j40-starhub/defconfig
@@ -8,7 +8,6 @@
 # CONFIG_DEV_CONSOLE is not set
 # CONFIG_NET_ETHERNET is not set
 # CONFIG_NET_IPv4 is not set
-# CONFIG_NSH_DISABLE_TELNETD is not set
 CONFIG_ARCH="arm"
 CONFIG_ARCH_BOARD="clicker2-stm32"
 CONFIG_ARCH_BOARD_CLICKER2_STM32=y
@@ -52,6 +51,8 @@ CONFIG_NETDEV_LATEINIT=y
 CONFIG_NETDEV_STATISTICS=y
 CONFIG_NETDEV_TELNET=y
 CONFIG_NETDEV_WIRELESS_IOCTL=y
+CONFIG_NETINIT_NETLOCAL=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NET_6LOWPAN=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_IPv6=y
@@ -72,8 +73,6 @@ CONFIG_NSH_DISABLE_PUT=y
 CONFIG_NSH_DISABLE_WGET=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETLOCAL=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/clicker2-stm32/mrf24j40-starpoint/defconfig b/configs/clicker2-stm32/mrf24j40-starpoint/defconfig
index 81b2e6da23b..c71ca557fd4 100644
--- a/configs/clicker2-stm32/mrf24j40-starpoint/defconfig
+++ b/configs/clicker2-stm32/mrf24j40-starpoint/defconfig
@@ -8,7 +8,6 @@
 # CONFIG_DEV_CONSOLE is not set
 # CONFIG_NET_ETHERNET is not set
 # CONFIG_NET_IPv4 is not set
-# CONFIG_NSH_DISABLE_TELNETD is not set
 CONFIG_ARCH="arm"
 CONFIG_ARCH_BOARD="clicker2-stm32"
 CONFIG_ARCH_BOARD_CLICKER2_STM32=y
@@ -68,6 +67,8 @@ CONFIG_NETDEVICES=y
 CONFIG_NETDEV_LATEINIT=y
 CONFIG_NETDEV_STATISTICS=y
 CONFIG_NETDEV_WIRELESS_IOCTL=y
+CONFIG_NETINIT_NETLOCAL=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NET_6LOWPAN=y
@@ -89,8 +90,6 @@ CONFIG_NSH_DISABLE_PUT=y
 CONFIG_NSH_DISABLE_WGET=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETLOCAL=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/clicker2-stm32/nsh/defconfig b/configs/clicker2-stm32/nsh/defconfig
index 0ee8b2b1047..44cc12f1fc2 100644
--- a/configs/clicker2-stm32/nsh/defconfig
+++ b/configs/clicker2-stm32/nsh/defconfig
@@ -16,7 +16,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_FS_WRITABLE=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/clicker2-stm32/scripts/memory.ld b/configs/clicker2-stm32/scripts/memory.ld
index 8a67bca4cd4..99b2a1c5852 100644
--- a/configs/clicker2-stm32/scripts/memory.ld
+++ b/configs/clicker2-stm32/scripts/memory.ld
@@ -54,7 +54,7 @@
  * Alignment of the user space FLASH partition is also a critical factor:
  * The user space FLASH partition will be spanned with a single region of
  * size 2**n bytes.  The alignment of the user-space region must be the same.
- * As a consequence, as the user-space increases in size, the alignmment
+ * As a consequence, as the user-space increases in size, the alignment
  * requirement also increases.
  *
  * This alignment requirement means that the largest user space FLASH region
diff --git a/configs/clicker2-stm32/usbnsh/defconfig b/configs/clicker2-stm32/usbnsh/defconfig
index c327fe14984..b4467d076e2 100644
--- a/configs/clicker2-stm32/usbnsh/defconfig
+++ b/configs/clicker2-stm32/usbnsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_CDCACM=y
 CONFIG_CDCACM_CONSOLE=y
 CONFIG_CDCACM_RXBUFSIZE=256
 CONFIG_CDCACM_TXBUFSIZE=256
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/clicker2-stm32/xbee-6lowpan/defconfig b/configs/clicker2-stm32/xbee-6lowpan/defconfig
index 8082d78eeb7..6f8256a4449 100644
--- a/configs/clicker2-stm32/xbee-6lowpan/defconfig
+++ b/configs/clicker2-stm32/xbee-6lowpan/defconfig
@@ -8,7 +8,6 @@
 # CONFIG_DEV_CONSOLE is not set
 # CONFIG_NET_ETHERNET is not set
 # CONFIG_NET_IPv4 is not set
-# CONFIG_NSH_DISABLE_TELNETD is not set
 CONFIG_ARCH="arm"
 CONFIG_ARCH_BOARD="clicker2-stm32"
 CONFIG_ARCH_BOARD_CLICKER2_STM32=y
@@ -64,6 +63,8 @@ CONFIG_NET=y
 CONFIG_NETDEVICES=y
 CONFIG_NETDEV_LATEINIT=y
 CONFIG_NETDEV_WIRELESS_IOCTL=y
+CONFIG_NETINIT_NETLOCAL=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NET_6LOWPAN=y
 CONFIG_NET_BROADCAST=y
@@ -83,8 +84,6 @@ CONFIG_NSH_DISABLE_PUT=y
 CONFIG_NSH_DISABLE_WGET=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETLOCAL=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/cloudctrl/nsh/defconfig b/configs/cloudctrl/nsh/defconfig
index 90aa0ef0fd0..2cfbdcb2c12 100644
--- a/configs/cloudctrl/nsh/defconfig
+++ b/configs/cloudctrl/nsh/defconfig
@@ -32,13 +32,13 @@ CONFIG_MMCSD_SPICLOCK=12500000
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=40
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -52,7 +52,6 @@ CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
 CONFIG_NSH_MMCSDSPIPORTNO=1
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=10
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/demo9s12ne64/ostest/defconfig b/configs/demo9s12ne64/ostest/defconfig
index 9b18943bd18..6cda35f0fd2 100644
--- a/configs/demo9s12ne64/ostest/defconfig
+++ b/configs/demo9s12ne64/ostest/defconfig
@@ -17,7 +17,6 @@ CONFIG_BOARD_LOOPSPERMSEC=5483
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_HCS12_NONBANKED=y
diff --git a/configs/dk-tm4c129x/README.txt b/configs/dk-tm4c129x/README.txt
index 3efff8286a4..af738e7fd27 100644
--- a/configs/dk-tm4c129x/README.txt
+++ b/configs/dk-tm4c129x/README.txt
@@ -425,8 +425,7 @@ f Application Configuration -> Network Utilities
         CONFIG_ARCH_PHY_INTERRUPT in the board configuration file to
         advertise that it supports arch_phy_irq().
 
-        And a few other things: UDP support is required (CONFIG_NET_UDP) and
-        signals must not be disabled (CONFIG_DISABLE_SIGNALS).
+        One other thing: UDP support is required (CONFIG_NET_UDP).
 
   Given those prerequisites, the network monitor can be selected with these
   additional settings.
diff --git a/configs/dk-tm4c129x/ipv6/defconfig b/configs/dk-tm4c129x/ipv6/defconfig
index 1a108d6d011..03018684350 100644
--- a/configs/dk-tm4c129x/ipv6/defconfig
+++ b/configs/dk-tm4c129x/ipv6/defconfig
@@ -31,6 +31,9 @@ CONFIG_LIBM=y
 CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_NET=y
+CONFIG_NETINIT_IPv6NETMASK_8=0xff80
+CONFIG_NETINIT_MONITOR=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_ETH_PKTSIZE=590
 CONFIG_NET_ICMPv6=y
@@ -49,10 +52,7 @@ CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_IPv6NETMASK_8=0xff80
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETINIT_MONITOR=y
-CONFIG_NSH_NETINIT_THREAD=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/dk-tm4c129x/nsh/defconfig b/configs/dk-tm4c129x/nsh/defconfig
index 8a464b08551..c5c48b7ebbb 100644
--- a/configs/dk-tm4c129x/nsh/defconfig
+++ b/configs/dk-tm4c129x/nsh/defconfig
@@ -31,6 +31,8 @@ CONFIG_MAX_WDOGPARMS=2
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_MONITOR=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -39,7 +41,6 @@ CONFIG_NET_ARP_SEND=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_SOLINGER=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
@@ -52,8 +53,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETINIT_MONITOR=y
-CONFIG_NSH_NETINIT_THREAD=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/dk-tm4c129x/scripts/ld.script b/configs/dk-tm4c129x/scripts/ld.script
index c53b6a7184c..6b5f5179eaf 100644
--- a/configs/dk-tm4c129x/scripts/ld.script
+++ b/configs/dk-tm4c129x/scripts/ld.script
@@ -49,68 +49,72 @@ ENTRY(_stext)
 
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
+        /* Stabs debugging sections. */
 
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/dummy.c b/configs/dummy.c
new file mode 100644
index 00000000000..2f312070ffa
--- /dev/null
+++ b/configs/dummy.c
@@ -0,0 +1,59 @@
+/****************************************************************************
+ * configs/dummy.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: __configs_dummy
+ *
+ * Description:
+ *   This is a dummy C file.  It is used to generate a useless object.  The
+ *   purpose of the useless object is to assure that libconfigs.a/lib is
+ *   created.  Some archivers (ZDS-II, SDCC) require a non-empty library or
+ *   they will generate errors
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void __configs_dummy(void)
+{
+}
diff --git a/configs/ea3131/locked/mklocked.sh b/configs/ea3131/locked/mklocked.sh
index 86e593b51d2..0459cbf1d13 100755
--- a/configs/ea3131/locked/mklocked.sh
+++ b/configs/ea3131/locked/mklocked.sh
@@ -166,11 +166,7 @@ if [ "$answer" = n ]; then
 	echo "EXTERN(timer_initialize)" >>ld-locked.inc
 fi
 
-answer=$(checkconfig CONFIG_DISABLE_SIGNALS)
-if [ "$answer" = n ]; then
-	echo "EXTERN(nxsig_initialize)" >>ld-locked.inc
-fi
-
+echo "EXTERN(nxsig_initialize)" >>ld-locked.inc
 echo "EXTERN(sem_initialize)" >>ld-locked.inc
 
 answer=$(checkconfig CONFIG_DISABLE_MQUEUE)
diff --git a/configs/ea3131/nsh/defconfig b/configs/ea3131/nsh/defconfig
index 711f0623487..4215576dcee 100644
--- a/configs/ea3131/nsh/defconfig
+++ b/configs/ea3131/nsh/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARM_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=16945
 CONFIG_BOOT_RUNFROMISRAM=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_FAT=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_LPC31_UART=y
diff --git a/configs/ea3131/pgnsh/defconfig b/configs/ea3131/pgnsh/defconfig
index 9858b24e177..d7d53913bab 100644
--- a/configs/ea3131/pgnsh/defconfig
+++ b/configs/ea3131/pgnsh/defconfig
@@ -18,7 +18,6 @@ CONFIG_ARM_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=16945
 CONFIG_BOOT_RUNFROMISRAM=y
 CONFIG_BUILD_2PASS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_FAT=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_LPC31_SPI=y
diff --git a/configs/ea3131/scripts/ld.script b/configs/ea3131/scripts/ld.script
index 72a3d9f97dc..18c4a316abe 100644
--- a/configs/ea3131/scripts/ld.script
+++ b/configs/ea3131/scripts/ld.script
@@ -48,67 +48,71 @@ OUTPUT_ARCH(arm)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > isram
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > isram
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > isram
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > isram
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > isram
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > isram
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > isram
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > isram
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > isram
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > isram
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > isram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > isram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/ea3131/usbserial/defconfig b/configs/ea3131/usbserial/defconfig
index bf5e5cd5e82..2ef0b1d9434 100644
--- a/configs/ea3131/usbserial/defconfig
+++ b/configs/ea3131/usbserial/defconfig
@@ -18,7 +18,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16945
 CONFIG_BOOT_RUNFROMISRAM=y
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_USBSERIAL=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_LIB_BOARDCTL=y
diff --git a/configs/ea3152/ostest/defconfig b/configs/ea3152/ostest/defconfig
index 71703747951..2ecf70f9f78 100644
--- a/configs/ea3152/ostest/defconfig
+++ b/configs/ea3152/ostest/defconfig
@@ -19,7 +19,6 @@ CONFIG_BOOT_RUNFROMISRAM=y
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_LPC31_UART=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/eagle100/httpd/defconfig b/configs/eagle100/httpd/defconfig
index 715b2a24e19..2a30fe42e77 100644
--- a/configs/eagle100/httpd/defconfig
+++ b/configs/eagle100/httpd/defconfig
@@ -18,7 +18,6 @@ CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_WEBSERVER=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_MAX_TASKS=8
diff --git a/configs/eagle100/nettest/defconfig b/configs/eagle100/nettest/defconfig
index 5b092c1ea91..d1eae910105 100644
--- a/configs/eagle100/nettest/defconfig
+++ b/configs/eagle100/nettest/defconfig
@@ -18,7 +18,6 @@ CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_EXAMPLES_NETTEST=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/eagle100/nxflat/defconfig b/configs/eagle100/nxflat/defconfig
index 40f38baed56..27a0960b949 100644
--- a/configs/eagle100/nxflat/defconfig
+++ b/configs/eagle100/nxflat/defconfig
@@ -17,7 +17,6 @@ CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=4531
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NXFLAT=y
 CONFIG_FS_ROMFS=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/eagle100/scripts/ld.script b/configs/eagle100/scripts/ld.script
index 9bff0b1c5c1..3dcc209b73b 100644
--- a/configs/eagle100/scripts/ld.script
+++ b/configs/eagle100/scripts/ld.script
@@ -51,69 +51,73 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The LM3S6918 has 64Kb of SRAM beginning at the following address */
+        /* The LM3S6918 has 64Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/efm32-g8xx-stk/include/board.h b/configs/efm32-g8xx-stk/include/board.h
index 55b00720242..4e9c8f0fe8a 100644
--- a/configs/efm32-g8xx-stk/include/board.h
+++ b/configs/efm32-g8xx-stk/include/board.h
@@ -44,8 +44,8 @@
 
 #include 
 
-#include "chip/efm32_cmu.h"
-#include "chip/efm32_usart.h"
+#include "hardware/efm32_cmu.h"
+#include "hardware/efm32_usart.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/configs/efm32-g8xx-stk/nsh/defconfig b/configs/efm32-g8xx-stk/nsh/defconfig
index 58b6cb0c49b..70bceb4a88d 100644
--- a/configs/efm32-g8xx-stk/nsh/defconfig
+++ b/configs/efm32-g8xx-stk/nsh/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=2662
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EFM32_GPIO_IRQ=y
 CONFIG_EFM32_LEUART0=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/efm32gg-stk3700/include/board.h b/configs/efm32gg-stk3700/include/board.h
index f8816cc9a7a..30543b1622f 100644
--- a/configs/efm32gg-stk3700/include/board.h
+++ b/configs/efm32gg-stk3700/include/board.h
@@ -44,8 +44,8 @@
 
 #include 
 
-#include "chip/efm32_cmu.h"
-#include "chip/efm32_usart.h"
+#include "hardware/efm32_cmu.h"
+#include "hardware/efm32_usart.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/configs/efm32gg-stk3700/nsh/defconfig b/configs/efm32gg-stk3700/nsh/defconfig
index 4672b1c28b8..27e5a932b99 100644
--- a/configs/efm32gg-stk3700/nsh/defconfig
+++ b/configs/efm32gg-stk3700/nsh/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=4787
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EFM32_GPIO_IRQ=y
 CONFIG_EFM32_LEUART0=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/efm32gg-stk3700/scripts/ld.script b/configs/efm32gg-stk3700/scripts/ld.script
index a2069de6b51..07769aaa874 100644
--- a/configs/efm32gg-stk3700/scripts/ld.script
+++ b/configs/efm32gg-stk3700/scripts/ld.script
@@ -44,67 +44,71 @@ ENTRY(_stext)
 
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/ekk-lm3s9b96/nsh/defconfig b/configs/ekk-lm3s9b96/nsh/defconfig
index 0aecd9434c2..dfb7097b185 100644
--- a/configs/ekk-lm3s9b96/nsh/defconfig
+++ b/configs/ekk-lm3s9b96/nsh/defconfig
@@ -25,13 +25,13 @@ CONFIG_MMCSD_NSLOTS=0
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=8
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_UDP=y
@@ -42,7 +42,6 @@ CONFIG_NFS=y
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=40
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/esp32-core/nsh/defconfig b/configs/esp32-core/nsh/defconfig
index defe42f5519..85b194b3f59 100644
--- a/configs/esp32-core/nsh/defconfig
+++ b/configs/esp32-core/nsh/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_XTENSA=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_FEATURES=y
-CONFIG_DISABLE_POLL=y
 CONFIG_ESP32_UART0=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_FS_PROCFS=y
diff --git a/configs/esp32-core/ostest/defconfig b/configs/esp32-core/ostest/defconfig
index 4d3fcd52fd0..be44375862c 100644
--- a/configs/esp32-core/ostest/defconfig
+++ b/configs/esp32-core/ostest/defconfig
@@ -14,7 +14,6 @@ CONFIG_ARCH_XTENSA=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_FEATURES=y
-CONFIG_DISABLE_POLL=y
 CONFIG_ESP32_UART0=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_FS_PROCFS=y
diff --git a/configs/esp32-core/smp/defconfig b/configs/esp32-core/smp/defconfig
index ba20df6e1a9..f1bfbb2b223 100644
--- a/configs/esp32-core/smp/defconfig
+++ b/configs/esp32-core/smp/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_XTENSA=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_FEATURES=y
-CONFIG_DISABLE_POLL=y
 CONFIG_ESP32_UART0=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_FS_PROCFS=y
diff --git a/configs/ez80f910200kitg/README.txt b/configs/ez80f910200kitg/README.txt
index 0872dd52af4..582476d996a 100644
--- a/configs/ez80f910200kitg/README.txt
+++ b/configs/ez80f910200kitg/README.txt
@@ -60,12 +60,48 @@ Version 5.2.1
   however, I encountered compiler internal errors.  I did not pursue that
   build any further.
 
+Version 5.3.0
+
+  I started verification using 5.30 on June 2, 2019.  To use this toolchain,
+  I had to suppress the gmtime() and gmtimer() because these were causing an
+  internal compiler error:
+
+    time\lib_gmtimer.c
+    P2: Internal Error(0xB47E59):
+            Please contact Technical Support
+
+  This is the change to suppress building these files:
+
+    diff --git a/libs/libc/time/Make.defs b/libs/libc/time/Make.defs
+    index 5c9b746778..8327e287f4 100644
+    --- a/libs/libc/time/Make.defs
+    +++ b/libs/libc/time/Make.defs
+    @@ -44,7 +44,7 @@ ifdef CONFIG_LIBC_LOCALTIME
+     CSRCS += lib_localtime.c lib_asctime.c lib_asctimer.c lib_ctime.c
+     CSRCS += lib_ctimer.c
+     else
+    -CSRCS += lib_mktime.c lib_gmtime.c lib_gmtimer.c
+    +CSRCS += lib_mktime.c # lib_gmtime.c lib_gmtimer.c
+     ifdef CONFIG_TIME_EXTENDED
+     CSRCS += lib_dayofweek.c lib_asctime.c lib_asctimer.c lib_ctime.c
+     CSRCS += lib_ctimer.c
+
+  The consequence is, of course, that these interfaces will not be available
+  to applications.
+
+  Alternatively, you can use 'make -i' to build the system.  The above
+  errors will occur, but will not stop the build (unless the failed build
+  objects are brought into the link).  The has the negative side effects
+  that (1) the archives will always be rebuild in the directories where
+  the error occur, and (2) you might miss other, real compilation error
+  since these will no longer stop the compilation.
+
 Other Versions
-  If you use any version of ZDS-II other than 5.1.1 or 5.2.1 or if you install
-  ZDS-II at any location other than the default location, you will have to
-  modify one or two files:  (1) configs/ez80f910200kitg/*/Make.defs and
-  (2) arch/z80/src/ez80/Toolchain.defs.  You probably have to modify the
-  path to your toolchain in the PATH environment variable.
+  If you use any version of ZDS-II other than 5.1.1, 5.2.1, or 5.3.0 or
+  if you install ZDS-II at any location other than the default location,
+  you will have to modify three files:  (1) arch/arm/z80/src/ez80/Kconfig,
+  (2) configs/ez80f910200kitg/scripts/Make.defs and, perhaps, (3)
+  arch/z80/src/ez80/Toolchain.defs.
 
 Configuration Subdirectories
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/configs/ez80f910200kitg/ostest/defconfig b/configs/ez80f910200kitg/ostest/defconfig
index 5cb4882d509..8652f216a30 100644
--- a/configs/ez80f910200kitg/ostest/defconfig
+++ b/configs/ez80f910200kitg/ostest/defconfig
@@ -17,7 +17,6 @@ CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_EZ80_UART0=y
diff --git a/configs/ez80f910200kitg/ostest/Make.defs b/configs/ez80f910200kitg/scripts/Make.defs
similarity index 83%
rename from configs/ez80f910200kitg/ostest/Make.defs
rename to configs/ez80f910200kitg/scripts/Make.defs
index 719b4419bd4..fe5b68598f9 100644
--- a/configs/ez80f910200kitg/ostest/Make.defs
+++ b/configs/ez80f910200kitg/scripts/Make.defs
@@ -1,5 +1,5 @@
 ############################################################################
-# configs/ez80f910200kitg/ostest/Make.defs
+# configs/ez80f910200kitg/scripts/Make.defs
 #
 #   Copyright (C) 2008, 2009, 2013 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt 
@@ -36,23 +36,31 @@
 include $(TOPDIR)/.config
 include $(TOPDIR)/tools/Config.mk
 
-# These are the directories where the ZDS-II toolchain is installed.  NOTE
-# that short 8.3 path names are used in order to avoid spaces.  On my machine
-# I have:
+# These are the default directories where the ZDS-II toolchain is installed.
+# NOTE that short 8.3 path names are used in order to avoid spaces.  On my
+# machine I have:
 #
-# C:\PROGRA~1\ = C:\Profram Files\
-# C:\PROGRA~2\ = C:\Program Files (x86)\
+# Versions 5.1.1 and 5.2.1
+#   C:\PROGRA~1\ = C:\Program Files\
+#   C:\PROGRA~2\ = C:\Program Files (x86)\
 #
 # Your PC may be configured differently.
+#
+# Version 5.3.0, the default install location is C:\ZiLOG
 
-ifeq ($(CONFIG_EZ80_ZDSII_V521),y)
-ZDSVERSION := 5.2.1
-else # ifeq ($(CONFIGEZ80_ZDSII_V511),y)
+ifeq ($(CONFIG_EZ80_ZDSII_V511),y)
+INSTALLROOT = C:/PROGRA~2/ZiLOG
 ZDSVERSION := 5.1.1
+else ifeq ($(CONFIG_EZ80_ZDSII_V521),y)
+INSTALLROOT = C:/PROGRA~2/ZiLOG
+ZDSVERSION := 5.2.1
+else ifeq ($(CONFIG_EZ80_ZDSII_V530),y)
+INSTALLROOT = C:/ZiLOG
+ZDSVERSION := 5.3.0
 endif
 
 ifeq ($(CONFIG_WINDOWS_NATIVE),y)
-  ZDSINSTALLDIR := C:/PROGRA~2/ZiLOG/ZDSII_eZ80Acclaim!_$(ZDSVERSION)
+  ZDSINSTALLDIR := $(INSTALLROOT)/ZDSII_eZ80Acclaim!_$(ZDSVERSION)
   INSTALLDIR = ${shell echo $(ZDSINSTALLDIR)| sed -e "s/\//\\/g"}
   ZDSBINDIR := $(INSTALLDIR)\bin
   ZDSSTDINCDIR := $(INSTALLDIR)\include\std
@@ -68,7 +76,7 @@ ifeq ($(CONFIG_WINDOWS_NATIVE),y)
   ARCHUSRINCLUDES = -usrinc:.
 else
   WINTOOL := y
-  ZDSINSTALLDIR := C:/PROGRA~2/ZiLOG/ZDSII_eZ80Acclaim!_$(ZDSVERSION)
+  ZDSINSTALLDIR := $(INSTALLROOT)/ZDSII_eZ80Acclaim!_$(ZDSVERSION)
   INSTALLDIR = ${shell cygpath -u "$(ZDSINSTALLDIR)"}
   ZDSBINDIR := $(INSTALLDIR)/bin
   ZDSSTDINCDIR := $(INSTALLDIR)/include/std
@@ -134,7 +142,7 @@ else
 endif
 
 ARCHCPUFLAGS = -chartype:S -promote -cpu:$(ARCHCPU) -NOgenprintf -NOmodsect \
-			   -asmsw:" $(ARCHASMCPUFLAGS) $(EARCHASMINCLUDES) $(ARCHASMWARNINGS) $(ARCHASMOPTIMIZATION)"
+               -asmsw:" $(ARCHASMCPUFLAGS) $(EARCHASMINCLUDES) $(ARCHASMWARNINGS) $(ARCHASMOPTIMIZATION)"
 ARCHLIST = -keeplst -NOlist -NOlistinc -keepasm
 ARCHPICFLAGS =
 ARCHWARNINGS = -warn
@@ -152,16 +160,16 @@ ARFLAGS = -quiet -warn
 
 # Linker definitions
 
-LINKCMDTEMPLATE = $(TOPDIR)$(DELIM)configs$(DELIM)ez80f910200kitg$(DELIM)ostest$(DELIM)ostest.linkcmd
+LINKCMDTEMPLATE = $(TOPDIR)$(DELIM)configs$(DELIM)ez80f910200kitg$(DELIM)scripts$(DELIM)ez80f910200kitg.linkcmd.linkcmd
 
-# Tool names/pathes
+# Tool names/paths.
 
 CROSSDEV =
-CC = ez80cc.exe
+CC = $(ZDSBINDIR)$(DELIM)ez80cc.exe
 CPP = gcc -E
-LD = ez80link.exe
-AS = ez80asm.exe
-AR = ez80lib.exe
+LD = $(ZDSBINDIR)$(DELIM)ez80link.exe
+AS = $(ZDSBINDIR)$(DELIM)ez80asm.exe
+AR = $(ZDSBINDIR)$(DELIM)ez80lib.exe
 
 # File extensions
 
@@ -179,15 +187,15 @@ ifeq ($(CONFIG_WINDOWS_NATIVE),y)
 
 define PREPROCESS
 	@echo CPP: $1->$2
-	$(Q) "$(CPP)" $(CPPFLAGS) $1 -o $2
+	$(Q) $(CPP) $(CPPFLAGS) $1 -o $2
 endef
 
 define COMPILE
-	$(Q) "$(CC)" $(CFLAGS)  ${shell echo $1 | sed -e "s/\//\\/g"}
+	$(Q) $(CC) $(CFLAGS)  ${shell echo $1 | sed -e "s/\//\\/g"}
 endef
 
 define ASSEMBLE
-	$(Q) "$(AS)" $(AFLAGS) ${shell echo $1 | sed -e "s/\//\\/g"}
+	$(Q) $(AS) $(AFLAGS) ${shell echo $1 | sed -e "s/\//\\/g"}
 endef
 
 define MOVEOBJ
@@ -198,7 +206,7 @@ endef
 
 define ARCHIVE
 	@echo AR: $2
-	$(Q) for %%G in ($(2)) do ( "$(AR)" $(ARFLAGS) $1=-+%%G )
+	$(Q) for %%G in ($(2)) do ( $(AR) $(ARFLAGS) $1=-+%%G )
 endef
 
 define CLEAN
@@ -214,15 +222,15 @@ else
 
 define PREPROCESS
 	@echo "CPP: $1->$2"
-	$(Q) "$(CPP)" $(CPPFLAGS) $1 -o $2
+	$(Q) $(CPP) $(CPPFLAGS) $1 -o $2
 endef
 
 define COMPILE
-	$(Q) (wfile=`cygpath -w "$1"`; "$(CC)" $(CFLAGS) $$wfile)
+	$(Q) $(CC) $(CFLAGS) `cygpath -w "$1"`
 endef
 
 define ASSEMBLE
-	$(Q) (wfile=`cygpath -w "$1"`; "$(AS)" $(AFLAGS) $$wfile)
+	$(Q) $(AS) $(AFLAGS) `cygpath -w "$1"`
 endef
 
 define MOVEOBJ
@@ -234,7 +242,7 @@ endef
 define ARCHIVE
 	$(Q) for __obj in $(2) ; do \
 		echo "AR: $$__obj"; \
-		"$(AR)" $(ARFLAGS) $1=-+$$__obj || { echo "$(AR) $1=-+$$__obj FAILED!" ; exit 1 ; } \
+		$(AR) $(ARFLAGS) $1=-+$$__obj || { echo "$(AR) $1=-+$$__obj FAILED!" ; exit 1 ; } \
 	done
 endef
 
diff --git a/configs/ez80f910200kitg/ostest/ostest.linkcmd b/configs/ez80f910200kitg/scripts/ez80f910200kitg.linkcmd
similarity index 97%
rename from configs/ez80f910200kitg/ostest/ostest.linkcmd
rename to configs/ez80f910200kitg/scripts/ez80f910200kitg.linkcmd
index 3ddee5f855a..66c90c79b47 100644
--- a/configs/ez80f910200kitg/ostest/ostest.linkcmd
+++ b/configs/ez80f910200kitg/scripts/ez80f910200kitg.linkcmd
@@ -1,8 +1,8 @@
 /****************************************************************************/
-/* configs/ez80f910200kitg/ostest/ostest.linkcmd                             */
+/* configs/ez80f910200kitg/scripts/ez80f910200kitg.linkcmd                  */
 /*                                                                          */
 /*   Copyright (C) 2008 Gregory Nutt. All rights reserved.                  */
-/*   Author: Gregory Nutt                           */
+/*   Author: Gregory Nutt                                  */
 /*                                                                          */
 /* Redistribution and use in source and binary forms, with or without       */
 /* modification, are permitted provided that the following conditions       */
diff --git a/configs/ez80f910200kitg/src/ez80_lowinit.c b/configs/ez80f910200kitg/src/ez80_lowinit.c
index bd41a9542bd..bd2c5a19149 100644
--- a/configs/ez80f910200kitg/src/ez80_lowinit.c
+++ b/configs/ez80f910200kitg/src/ez80_lowinit.c
@@ -41,7 +41,7 @@
 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/configs/ez80f910200zco/README.txt b/configs/ez80f910200zco/README.txt
index 08d809cfa30..15c5ef1d474 100644
--- a/configs/ez80f910200zco/README.txt
+++ b/configs/ez80f910200zco/README.txt
@@ -60,12 +60,56 @@ Version 5.2.1
   however, I encountered compiler internal errors.  I did not pursue that
   build any further.
 
+Version 5.3.0
+
+  I started verification using 5.30 on June 2, 2019.  To use this toolchain,
+  I had to suppress the gmtime() and gmtimer() because these were causing an
+  internal compiler error:
+
+    time\lib_gmtimer.c
+    P2: Internal Error(0xB47E59):
+            Please contact Technical Support
+
+  This is the change to suppress building these files:
+
+    diff --git a/libs/libc/time/Make.defs b/libs/libc/time/Make.defs
+    index 5c9b746778..8327e287f4 100644
+    --- a/libs/libc/time/Make.defs
+    +++ b/libs/libc/time/Make.defs
+    @@ -44,7 +44,7 @@ ifdef CONFIG_LIBC_LOCALTIME
+     CSRCS += lib_localtime.c lib_asctime.c lib_asctimer.c lib_ctime.c
+     CSRCS += lib_ctimer.c
+     else
+    -CSRCS += lib_mktime.c lib_gmtime.c lib_gmtimer.c
+    +CSRCS += lib_mktime.c # lib_gmtime.c lib_gmtimer.c
+     ifdef CONFIG_TIME_EXTENDED
+     CSRCS += lib_dayofweek.c lib_asctime.c lib_asctimer.c lib_ctime.c
+     CSRCS += lib_ctimer.c
+
+  And this:
+
+     stdlib\lib_strtof.c
+     stdlib\lib_strtof.c     (76,36) :       WARNING (32) Division by zero encountered
+     stdlib\lib_strtof.c     (102,36) :      WARNING (32) Division by zero encountered
+
+   Which can be worked around by removing it from the build
+
+  The consequence is, of course, that these interfaces will not be available
+  to applications.
+
+  Alternatively, you can use 'make -i' to build the system.  The above
+  errors will occur, but will not stop the build (unless the failed build
+  objects are brought into the link).  The has the negative side effects
+  that (1) the archives will always be rebuild in the directories where
+  the error occur, and (2) you might miss other, real compilation error
+  since these will no longer stop the compilation.
+
 Other Versions
-  If you use any version of ZDS-II other than 5.1.1 or 5.2.1 or if you install
-  ZDS-II at any location other than the default location, you will have to
-  modify one or two files:  (2) configs/ez80f910200zco/*/Make.defs and (2)
-  arch/z80/src/ez80/Toolchain.defs.  You may also have to modify you PATH
-  environment variable.
+  If you use any version of ZDS-II other than 5.1.1, 5.2.1, or 5.3.0 or
+  if you install ZDS-II at any location other than the default location,
+  you will have to modify three files:  (1) arch/arm/z80/src/ez80/Kconfig,
+  (2) configs/ez80f910200zco/scripts/Make.defs and, perhaps, (3)
+  arch/z80/src/ez80/Toolchain.defs.
 
 Configurations
 ^^^^^^^^^^^^^^
diff --git a/configs/ez80f910200zco/dhcpd/defconfig b/configs/ez80f910200zco/dhcpd/defconfig
index ad4aa4bc31a..904903ce07b 100644
--- a/configs/ez80f910200zco/dhcpd/defconfig
+++ b/configs/ez80f910200zco/dhcpd/defconfig
@@ -18,7 +18,6 @@ CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_ETH0_PHY_AM79C874=y
 CONFIG_EXAMPLES_DHCPD_IPADDR=0x0a000001
diff --git a/configs/ez80f910200zco/httpd/defconfig b/configs/ez80f910200zco/httpd/defconfig
index c433b08b9eb..af450561165 100644
--- a/configs/ez80f910200zco/httpd/defconfig
+++ b/configs/ez80f910200zco/httpd/defconfig
@@ -17,7 +17,6 @@ CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_ETH0_PHY_AM79C874=y
 CONFIG_EXAMPLES_WEBSERVER=y
 CONFIG_EZ80_EMAC=y
diff --git a/configs/ez80f910200zco/nettest/defconfig b/configs/ez80f910200zco/nettest/defconfig
index cd61ec03a3d..a3dba1086ab 100644
--- a/configs/ez80f910200zco/nettest/defconfig
+++ b/configs/ez80f910200zco/nettest/defconfig
@@ -17,7 +17,6 @@ CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_ETH0_PHY_AM79C874=y
 CONFIG_EXAMPLES_NETTEST_NOMAC=y
diff --git a/configs/ez80f910200zco/nsh/defconfig b/configs/ez80f910200zco/nsh/defconfig
index ff070cc18a7..3cfad970ce6 100644
--- a/configs/ez80f910200zco/nsh/defconfig
+++ b/configs/ez80f910200zco/nsh/defconfig
@@ -7,17 +7,16 @@
 #
 # CONFIG_NSH_DISABLE_IFCONFIG is not set
 # CONFIG_NSH_DISABLE_PS is not set
-CONFIG_ARCH_BOARD_EZ80F910200ZCO=y
+CONFIG_ARCH="z80"
 CONFIG_ARCH_BOARD="ez80f910200zco"
+CONFIG_ARCH_BOARD_EZ80F910200ZCO=y
 CONFIG_ARCH_CHIP_EZ80=y
 CONFIG_ARCH_CHIP_EZ80F91=y
 CONFIG_ARCH_TIMERHOOK=y
 CONFIG_ARCH_Z80=y
-CONFIG_ARCH="z80"
 CONFIG_BOARD_LOOPSPERMSEC=1250
 CONFIG_DISABLE_MQUEUE=y
 CONFIG_ETH0_PHY_AM79C874=y
-CONFIG_SYSTEM_NSH=y
 CONFIG_EZ80_EMAC=y
 CONFIG_EZ80_PHYCONFIG=1
 CONFIG_EZ80_RAMADDR=0xf7c000
@@ -25,27 +24,26 @@ CONFIG_EZ80_UART0=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
-CONFIG_NET_BROADCAST=y
-CONFIG_NET_ICMP_SOCKET=y
-CONFIG_NET_ICMP=y
-CONFIG_NET_MAX_LISTENPORTS=8
-CONFIG_NET_SOCKOPTS=y
-CONFIG_NET_STATISTICS=y
-CONFIG_NET_TCP=y
-CONFIG_NET_UDP_CHECKSUMS=y
-CONFIG_NET_UDP=y
 CONFIG_NET=y
-CONFIG_NETDB_DNSCLIENT_ENTRIES=4
 CONFIG_NETDB_DNSCLIENT=y
+CONFIG_NETDB_DNSCLIENT_ENTRIES=4
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
+CONFIG_NET_BROADCAST=y
+CONFIG_NET_ICMP=y
+CONFIG_NET_ICMP_SOCKET=y
+CONFIG_NET_MAX_LISTENPORTS=8
+CONFIG_NET_STATISTICS=y
+CONFIG_NET_TCP=y
+CONFIG_NET_UDP=y
+CONFIG_NET_UDP_CHECKSUMS=y
 CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_TIMERS=4
 CONFIG_PREALLOC_WDOGS=8
@@ -57,6 +55,7 @@ CONFIG_SDCLONE_DISABLE=y
 CONFIG_START_DAY=14
 CONFIG_START_MONTH=3
 CONFIG_START_YEAR=2009
+CONFIG_SYSTEM_NSH=y
 CONFIG_SYSTEM_PING=y
 CONFIG_TASK_NAME_SIZE=0
 CONFIG_UART0_BAUD=57600
diff --git a/configs/ez80f910200zco/scripts/Make.defs b/configs/ez80f910200zco/scripts/Make.defs
index 92189957e3b..535dbea0c0a 100644
--- a/configs/ez80f910200zco/scripts/Make.defs
+++ b/configs/ez80f910200zco/scripts/Make.defs
@@ -36,23 +36,31 @@
 include $(TOPDIR)/.config
 include $(TOPDIR)/tools/Config.mk
 
-# These are the directories where the ZDS-II toolchain is installed.  NOTE
-# that short 8.3 path names are used in order to avoid spaces.  On my machine
-# I have:
+# These are the default directories where the ZDS-II toolchain is installed.
+# NOTE that short 8.3 path names are used in order to avoid spaces.  On my
+# machine I have:
 #
-# C:\PROGRA~1\ = C:\Profram Files\
-# C:\PROGRA~2\ = C:\Program Files (x86)\
+# Versions 5.1.1 and 5.2.1
+#   C:\PROGRA~1\ = C:\Program Files\
+#   C:\PROGRA~2\ = C:\Program Files (x86)\
 #
 # Your PC may be configured differently.
+#
+# Version 5.3.0, the default install location is C:\ZiLOG
 
-ifeq ($(CONFIG_EZ80_ZDSII_V521),y)
-ZDSVERSION := 5.2.1
-else # ifeq ($(CONFIGEZ80_ZDSII_V511),y)
+ifeq ($(CONFIG_EZ80_ZDSII_V511),y)
+INSTALLROOT = C:/PROGRA~2/ZiLOG
 ZDSVERSION := 5.1.1
+else ifeq ($(CONFIG_EZ80_ZDSII_V521),y)
+INSTALLROOT = C:/PROGRA~2/ZiLOG
+ZDSVERSION := 5.2.1
+else ifeq ($(CONFIG_EZ80_ZDSII_V530),y)
+INSTALLROOT = C:/ZiLOG
+ZDSVERSION := 5.3.0
 endif
 
 ifeq ($(CONFIG_WINDOWS_NATIVE),y)
-  ZDSINSTALLDIR := C:/PROGRA~2/ZiLOG/ZDSII_eZ80Acclaim!_$(ZDSVERSION)
+  ZDSINSTALLDIR := $(INSTALLROOT)/ZDSII_eZ80Acclaim!_$(ZDSVERSION)
   INSTALLDIR = ${shell echo $(ZDSINSTALLDIR)| sed -e "s/\//\\/g"}
   ZDSBINDIR := $(INSTALLDIR)\bin
   ZDSSTDINCDIR := $(INSTALLDIR)\include\std
@@ -68,7 +76,7 @@ ifeq ($(CONFIG_WINDOWS_NATIVE),y)
   ARCHUSRINCLUDES = -usrinc:.
 else
   WINTOOL := y
-  ZDSINSTALLDIR := C:/PROGRA~2/ZiLOG/ZDSII_eZ80Acclaim!_$(ZDSVERSION)
+  ZDSINSTALLDIR := $(INSTALLROOT)/ZDSII_eZ80Acclaim!_$(ZDSVERSION)
   INSTALLDIR = ${shell cygpath -u "$(ZDSINSTALLDIR)"}
   ZDSBINDIR := $(INSTALLDIR)/bin
   ZDSSTDINCDIR := $(INSTALLDIR)/include/std
@@ -134,7 +142,7 @@ else
 endif
 
 ARCHCPUFLAGS = -chartype:S -promote -cpu:$(ARCHCPU) -NOgenprintf -NOmodsect \
-			   -asmsw:" $(ARCHASMCPUFLAGS) $(EARCHASMINCLUDES) $(ARCHASMWARNINGS) $(ARCHASMOPTIMIZATION)"
+               -asmsw:" $(ARCHASMCPUFLAGS) $(EARCHASMINCLUDES) $(ARCHASMWARNINGS) $(ARCHASMOPTIMIZATION)"
 ARCHLIST = -keeplst -NOlist -NOlistinc -keepasm
 ARCHPICFLAGS =
 ARCHWARNINGS = -warn
@@ -154,14 +162,14 @@ ARFLAGS = -quiet -warn
 
 LINKCMDTEMPLATE = $(TOPDIR)$(DELIM)configs$(DELIM)ez80f910200zco$(DELIM)scripts$(DELIM)ez80f910200zco.linkcmd
 
-# Tool names/pathes
+# Tool names/paths.
 
 CROSSDEV =
-CC = ez80cc.exe
+CC = $(ZDSBINDIR)$(DELIM)ez80cc.exe
 CPP = gcc -E
-LD = ez80link.exe
-AS = ez80asm.exe
-AR = ez80lib.exe
+LD = $(ZDSBINDIR)$(DELIM)ez80link.exe
+AS = $(ZDSBINDIR)$(DELIM)ez80asm.exe
+AR = $(ZDSBINDIR)$(DELIM)ez80lib.exe
 
 # File extensions
 
@@ -179,15 +187,15 @@ ifeq ($(CONFIG_WINDOWS_NATIVE),y)
 
 define PREPROCESS
 	@echo CPP: $1->$2
-	$(Q) "$(CPP)" $(CPPFLAGS) $1 -o $2
+	$(Q) $(CPP) $(CPPFLAGS) $1 -o $2
 endef
 
 define COMPILE
-	$(Q) "$(CC)" $(CFLAGS)  ${shell echo $1 | sed -e "s/\//\\/g"}
+	$(Q) $(CC) $(CFLAGS)  ${shell echo $1 | sed -e "s/\//\\/g"}
 endef
 
 define ASSEMBLE
-	$(Q) "$(AS)" $(AFLAGS) ${shell echo $1 | sed -e "s/\//\\/g"}
+	$(Q) $(AS) $(AFLAGS) ${shell echo $1 | sed -e "s/\//\\/g"}
 endef
 
 define MOVEOBJ
@@ -198,7 +206,7 @@ endef
 
 define ARCHIVE
 	@echo AR: $2
-	$(Q) for %%G in ($(2)) do ( "$(AR)" $(ARFLAGS) $1=-+%%G )
+	$(Q) for %%G in ($(2)) do ( $(AR) $(ARFLAGS) $1=-+%%G )
 endef
 
 define CLEAN
@@ -214,15 +222,15 @@ else
 
 define PREPROCESS
 	@echo "CPP: $1->$2"
-	$(Q) "$(CPP)" $(CPPFLAGS) $1 -o $2
+	$(Q) $(CPP) $(CPPFLAGS) $1 -o $2
 endef
 
 define COMPILE
-	$(Q) (wfile=`cygpath -w "$1"`; "$(CC)" $(CFLAGS) $$wfile)
+	$(Q) $(CC) $(CFLAGS) `cygpath -w "$1"`
 endef
 
 define ASSEMBLE
-	$(Q) (wfile=`cygpath -w "$1"`; "$(AS)" $(AFLAGS) $$wfile)
+	$(Q) $(AS) $(AFLAGS) `cygpath -w "$1"`
 endef
 
 define MOVEOBJ
@@ -234,7 +242,7 @@ endef
 define ARCHIVE
 	$(Q) for __obj in $(2) ; do \
 		echo "AR: $$__obj"; \
-		"$(AR)" $(ARFLAGS) $1=-+$$__obj || { echo "$(AR) $1=-+$$__obj FAILED!" ; exit 1 ; } \
+		$(AR) $(ARFLAGS) $1=-+$$__obj || { echo "$(AR) $1=-+$$__obj FAILED!" ; exit 1 ; } \
 	done
 endef
 
diff --git a/configs/ez80f910200zco/src/ez80_lowinit.c b/configs/ez80f910200zco/src/ez80_lowinit.c
index 5983e5509bf..3dbe7f2fdcb 100644
--- a/configs/ez80f910200zco/src/ez80_lowinit.c
+++ b/configs/ez80f910200zco/src/ez80_lowinit.c
@@ -41,7 +41,7 @@
 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/configs/fire-stm32v2/nsh/defconfig b/configs/fire-stm32v2/nsh/defconfig
index c0302411319..7be03c3bfe9 100644
--- a/configs/fire-stm32v2/nsh/defconfig
+++ b/configs/fire-stm32v2/nsh/defconfig
@@ -38,6 +38,7 @@ CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
 CONFIG_NETDEVICES=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -45,7 +46,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=16
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCP_CONNS=16
@@ -57,7 +57,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=16
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/fire-stm32v2/src/stm32_selectlcd.c b/configs/fire-stm32v2/src/stm32_selectlcd.c
index cf8336101a6..f85b3734144 100644
--- a/configs/fire-stm32v2/src/stm32_selectlcd.c
+++ b/configs/fire-stm32v2/src/stm32_selectlcd.c
@@ -49,7 +49,6 @@
 #include "chip.h"
 #include "up_arch.h"
 
-#include "stm32_fsmc.h"
 #include "stm32_gpio.h"
 #include "stm32.h"
 #include "fire-stm32v2.h"
@@ -140,25 +139,6 @@ static const uint16_t g_lcdconfig[NCOMMON_CONFIG] =
  * Private Functions
  ************************************************************************************/
 
-/************************************************************************************
- * Name: stm32_enablefsmc
- *
- * Description:
- *  Enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-static inline void stm32_enablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Enable AHB clocking to the FSMC */
-
-  regval  = getreg32( STM32_RCC_AHBENR);
-  regval |= RCC_AHBENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHBENR);
-}
-
 /************************************************************************************
  * Public Functions
  ************************************************************************************/
@@ -186,7 +166,7 @@ void stm32_selectlcd(void)
 
   /* Enable AHB clocking to the FSMC */
 
-  stm32_enablefsmc();
+  stm32_fsmc_enable();
 
   /* Bank1 NOR/SRAM control register configuration */
 
diff --git a/configs/flipnclick-sam3x/src/flipnclick-sam3x.h b/configs/flipnclick-sam3x/src/flipnclick-sam3x.h
index 9b6a563d3b4..9e3e7e19c69 100644
--- a/configs/flipnclick-sam3x/src/flipnclick-sam3x.h
+++ b/configs/flipnclick-sam3x/src/flipnclick-sam3x.h
@@ -48,7 +48,7 @@
 #include 
 #include 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/configs/freedom-k28f/nsh/defconfig b/configs/freedom-k28f/nsh/defconfig
index b889330231c..dc8de79748f 100644
--- a/configs/freedom-k28f/nsh/defconfig
+++ b/configs/freedom-k28f/nsh/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_CHIP_MK28FN2M0VMI15=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=10401
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/freedom-k28f/src/k28_usbdev.c b/configs/freedom-k28f/src/k28_usbdev.c
index 3eec89b6994..0e95258b29c 100644
--- a/configs/freedom-k28f/src/k28_usbdev.c
+++ b/configs/freedom-k28f/src/k28_usbdev.c
@@ -50,7 +50,7 @@
 #include "up_arch.h"
 #include "kinetis.h"
 #include "kinetis_usbotg.h"
-#include "chip/kinetis_sim.h"
+#include "hardware/kinetis_sim.h"
 #include "freedom-k28f.h"
 
 /************************************************************************************
diff --git a/configs/freedom-k64f/README.txt b/configs/freedom-k64f/README.txt
index c0ac8a9e971..fdd5387d5b7 100644
--- a/configs/freedom-k64f/README.txt
+++ b/configs/freedom-k64f/README.txt
@@ -394,8 +394,7 @@ f Application Configuration -> Network Utilities
         CONFIG_ARCH_PHY_INTERRUPT in the board configuration file to
         advertise that it supports arch_phy_irq().
 
-        And a few other things: UDP support is required (CONFIG_NET_UDP) and
-        signals must not be disabled (CONFIG_DISABLE_SIGNALS).
+        One other thing: UDP support is required (CONFIG_NET_UDP).
 
   Given those prerequisites, the network monitor can be selected with these
   additional settings.
@@ -862,7 +861,7 @@ Where  is one of the following:
 
        CONFIG_NSH_NOMAC=y
        CONFIG_NSH_SWMAC=y
-       CONFIG_NSH_MACADDR=0x00e0deadbeef
+       CONFIG_NETINIT_MACADDR=0x00e0deadbeef
 
   nsh:
   ---
diff --git a/configs/freedom-k64f/netnsh/defconfig b/configs/freedom-k64f/netnsh/defconfig
index 94f6888a273..66499fafa82 100644
--- a/configs/freedom-k64f/netnsh/defconfig
+++ b/configs/freedom-k64f/netnsh/defconfig
@@ -32,6 +32,8 @@ CONFIG_MOTOROLA_SREC=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDEV_PHY_IOCTL=y
 CONFIG_NETDEV_STATISTICS=y
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -39,7 +41,6 @@ CONFIG_NET_ARP_SEND=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -52,8 +53,6 @@ CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_DISABLE_IFUPDOWN=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETINIT_THREAD=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/freedom-k64f/nsh/defconfig b/configs/freedom-k64f/nsh/defconfig
index 00e974d527d..111b2ab82a6 100644
--- a/configs/freedom-k64f/nsh/defconfig
+++ b/configs/freedom-k64f/nsh/defconfig
@@ -19,7 +19,6 @@ CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_EXAMPLES_PWM=y
 CONFIG_FAT_LCNAMES=y
diff --git a/configs/freedom-k64f/src/k64_uid.c b/configs/freedom-k64f/src/k64_uid.c
index 0fc1527637c..5fe781c37b5 100644
--- a/configs/freedom-k64f/src/k64_uid.c
+++ b/configs/freedom-k64f/src/k64_uid.c
@@ -38,13 +38,14 @@
 
 #include 
 
-#include 
-#include 
 #include 
-#include "kinetis_uid.h"
 
 #include 
 
+#include "hardware/kinetis_k64memorymap.h"
+#include "hardware/kinetis_sim.h"
+#include "kinetis_uid.h"
+
 #if defined(CONFIG_BOARDCTL_UNIQUEID)
 
 /****************************************************************************
diff --git a/configs/freedom-k66f/README.txt b/configs/freedom-k66f/README.txt
index 40c6b4f6039..f024c73b7c9 100644
--- a/configs/freedom-k66f/README.txt
+++ b/configs/freedom-k66f/README.txt
@@ -397,8 +397,7 @@ Networking Support
         CONFIG_ARCH_PHY_INTERRUPT in the board configuration file to
         advertise that it supports arch_phy_irq().
 
-        And a few other things: UDP support is required (CONFIG_NET_UDP) and
-        signals must not be disabled (CONFIG_DISABLE_SIGNALS).
+        One other thing: UDP support is required (CONFIG_NET_UDP).
 
   Given those prerequisites, the network monitor can be selected with these
   additional settings.
@@ -869,7 +868,7 @@ Where  is one of the following:
 
        CONFIG_NSH_NOMAC=y
        CONFIG_NSH_SWMAC=y
-       CONFIG_NSH_MACADDR=0x00e0deadbeef
+       CONFIG_NETINIT_MACADDR=0x00e0deadbeef
 
   nsh:
   ---
diff --git a/configs/freedom-k66f/netnsh/defconfig b/configs/freedom-k66f/netnsh/defconfig
index 3e5ab283d0c..6f5da7a9932 100644
--- a/configs/freedom-k66f/netnsh/defconfig
+++ b/configs/freedom-k66f/netnsh/defconfig
@@ -40,6 +40,8 @@ CONFIG_MAX_WDOGPARMS=2
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDEV_PHY_IOCTL=y
 CONFIG_NETDEV_STATISTICS=y
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -47,7 +49,6 @@ CONFIG_NET_ARP_SEND=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -59,8 +60,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETINIT_THREAD=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_CHILDSTATUS=2
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/freedom-k66f/src/k66_uid.c b/configs/freedom-k66f/src/k66_uid.c
index 7d9e44cb0e7..a2e649792b5 100644
--- a/configs/freedom-k66f/src/k66_uid.c
+++ b/configs/freedom-k66f/src/k66_uid.c
@@ -38,10 +38,11 @@
 
 #include 
 
-#include 
-#include 
 #include 
 #include 
+
+#include "hardware/kinetis_k66memorymap.h"
+#include "hardware/kinetis_sim.h"
 #include "kinetis_uid.h"
 
 #include 
diff --git a/configs/freedom-kl25z/nsh/defconfig b/configs/freedom-kl25z/nsh/defconfig
index c69200dc4f9..0148ad1edfb 100644
--- a/configs/freedom-kl25z/nsh/defconfig
+++ b/configs/freedom-kl25z/nsh/defconfig
@@ -23,7 +23,6 @@ CONFIG_BUILTIN=y
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_PWM=y
 CONFIG_KL_TPM0=y
 CONFIG_KL_TPM0_PWM=y
diff --git a/configs/freedom-kl25z/src/kl_tsi.c b/configs/freedom-kl25z/src/kl_tsi.c
index 9f7f1f70cca..49909abd806 100644
--- a/configs/freedom-kl25z/src/kl_tsi.c
+++ b/configs/freedom-kl25z/src/kl_tsi.c
@@ -52,9 +52,9 @@
 
 #include "up_arch.h"
 #include "kl_gpio.h"
-#include "chip/kl_tsi.h"
-#include "chip/kl_pinmux.h"
-#include "chip/kl_sim.h"
+#include "hardware/kl_tsi.h"
+#include "hardware/kl_pinmux.h"
+#include "hardware/kl_sim.h"
 
 #ifdef CONFIG_KL_TSI
 
diff --git a/configs/freedom-kl26z/nsh/defconfig b/configs/freedom-kl26z/nsh/defconfig
index b328cd2d108..871a7f0425a 100644
--- a/configs/freedom-kl26z/nsh/defconfig
+++ b/configs/freedom-kl26z/nsh/defconfig
@@ -23,7 +23,6 @@ CONFIG_BUILTIN=y
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_PWM=y
 CONFIG_KL_TPM0=y
 CONFIG_KL_TPM0_PWM=y
diff --git a/configs/freedom-kl26z/src/kl_tsi.c b/configs/freedom-kl26z/src/kl_tsi.c
index 1d4a2837720..64b857d2abf 100644
--- a/configs/freedom-kl26z/src/kl_tsi.c
+++ b/configs/freedom-kl26z/src/kl_tsi.c
@@ -52,9 +52,9 @@
 
 #include "up_arch.h"
 #include "kl_gpio.h"
-#include "chip/kl_tsi.h"
-#include "chip/kl_pinmux.h"
-#include "chip/kl_sim.h"
+#include "hardware/kl_tsi.h"
+#include "hardware/kl_pinmux.h"
+#include "hardware/kl_sim.h"
 
 #ifdef CONFIG_KL_TSI
 
diff --git a/configs/gapuino/nsh/defconfig b/configs/gapuino/nsh/defconfig
index b7f3e68d607..74cbe2d7257 100644
--- a/configs/gapuino/nsh/defconfig
+++ b/configs/gapuino/nsh/defconfig
@@ -18,7 +18,6 @@ CONFIG_BUILTIN=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_FS_WRITABLE=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
diff --git a/configs/hymini-stm32v/nsh/defconfig b/configs/hymini-stm32v/nsh/defconfig
index 143c8c8e51b..cb379765ed0 100644
--- a/configs/hymini-stm32v/nsh/defconfig
+++ b/configs/hymini-stm32v/nsh/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_IRQBUTTONS=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BINFMT_DISABLE=y
 CONFIG_BOARD_LOOPSPERMSEC=5483
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FS_FAT=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig
index c16eb217ce6..34e6d0e1645 100644
--- a/configs/hymini-stm32v/nsh2/defconfig
+++ b/configs/hymini-stm32v/nsh2/defconfig
@@ -22,7 +22,6 @@ CONFIG_ARCH_IRQBUTTONS=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=5483
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NXHELLO=y
 CONFIG_EXAMPLES_NXHELLO_BPP=16
diff --git a/configs/hymini-stm32v/scripts/ld.script b/configs/hymini-stm32v/scripts/ld.script
index f1b2b1d7fad..546c06bc1cb 100644
--- a/configs/hymini-stm32v/scripts/ld.script
+++ b/configs/hymini-stm32v/scripts/ld.script
@@ -52,69 +52,73 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */
+        /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/hymini-stm32v/src/stm32_r61505u.c b/configs/hymini-stm32v/src/stm32_r61505u.c
index 443f469f06b..1a973395a70 100644
--- a/configs/hymini-stm32v/src/stm32_r61505u.c
+++ b/configs/hymini-stm32v/src/stm32_r61505u.c
@@ -64,6 +64,10 @@
  * Pre-processor Definitions
  **************************************************************************************/
 
+#ifndef CONFIG_STM32_FSMC
+#  error CONFIG_STM32_FSMC is required for LCD support
+#endif
+
 /* Color depth and format */
 
 #define LCD_BPP          16
@@ -278,48 +282,6 @@ static inline void stm32_extmemgpios(const uint16_t *gpios, int ngpios)
     }
 }
 
-/************************************************************************************
- * Name: stm32_enablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-#ifndef CONFIG_STM32_FSMC
-#  error CONFIG_STM32_FSMC is required for LCD support
-#endif
-
-static void stm32_enablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Enable AHB clocking to the FSMC */
-
-  regval  = getreg32( STM32_RCC_AHBENR);
-  regval |= RCC_AHBENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHBENR);
-}
-
-/************************************************************************************
- * Name: stm32_disablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-static void stm32_disablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Enable AHB clocking to the FSMC */
-
-  regval  = getreg32( STM32_RCC_AHBENR);
-  regval &= ~RCC_AHBENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHBENR);
-}
-
 /************************************************************************************
  * Name: stm32_selectlcd
  *
@@ -336,7 +298,7 @@ static void stm32_selectlcd(void)
 
   /* Enable AHB clocking to the FSMC */
 
-  stm32_enablefsmc();
+  stm32_fsmc_enable();
 
   /* Bank1 NOR/SRAM control register configuration */
 
@@ -379,7 +341,7 @@ static void stm32_deselectlcd(void)
 
   /* Disable AHB clocking to the FSMC */
 
-  stm32_disablefsmc();
+  stm32_fsmc_disable();
 }
 
 /**************************************************************************************
diff --git a/configs/hymini-stm32v/src/stm32_ssd1289.c b/configs/hymini-stm32v/src/stm32_ssd1289.c
index d09d884f960..894ffe2b0e8 100644
--- a/configs/hymini-stm32v/src/stm32_ssd1289.c
+++ b/configs/hymini-stm32v/src/stm32_ssd1289.c
@@ -105,7 +105,6 @@ static void stm32_write(FAR struct ssd1289_lcd_s *dev, uint16_t data);
 static void stm32_backlight(FAR struct ssd1289_lcd_s *dev, int power);
 
 static void stm32_extmemgpios(const uint16_t *gpios, int ngpios);
-static void stm32_enablefsmc(void);
 
 /**************************************************************************************
  * Private Data
@@ -372,7 +371,7 @@ static void stm32_selectlcd(void)
 
   /* Enable AHB clocking to the FSMC */
 
-  stm32_enablefsmc();
+  stm32_fsmc_enable();
 
   /* Bank1 NOR/SRAM control register configuration */
 
@@ -415,29 +414,6 @@ static void stm32_extmemgpios(const uint16_t *gpios, int ngpios)
   }
 }
 
-/************************************************************************************
- * Name: stm32_enablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-#ifndef CONFIG_STM32_FSMC
-#  error CONFIG_STM32_FSMC is required for LCD support
-#endif
-
-static void stm32_enablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Enable AHB clocking to the FSMC */
-
-  regval  = getreg32( STM32_RCC_AHBENR);
-  regval |= RCC_AHBENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHBENR);
-}
-
 /**************************************************************************************
  * Public Functions
  **************************************************************************************/
diff --git a/configs/hymini-stm32v/usbmsc/defconfig b/configs/hymini-stm32v/usbmsc/defconfig
index 63d19bde9a3..b12fd54a193 100644
--- a/configs/hymini-stm32v/usbmsc/defconfig
+++ b/configs/hymini-stm32v/usbmsc/defconfig
@@ -15,7 +15,6 @@ CONFIG_ARCH_CHIP_STM32F103VC=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
 CONFIG_BOARD_LOOPSPERMSEC=5483
-CONFIG_DISABLE_POLL=y
 CONFIG_LIB_BOARDCTL=y
 CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
diff --git a/configs/hymini-stm32v/usbnsh/defconfig b/configs/hymini-stm32v/usbnsh/defconfig
index 52761ada7a5..33b7c413f8c 100644
--- a/configs/hymini-stm32v/usbnsh/defconfig
+++ b/configs/hymini-stm32v/usbnsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_CDCACM=y
 CONFIG_CDCACM_CONSOLE=y
 CONFIG_CDCACM_RXBUFSIZE=256
 CONFIG_CDCACM_TXBUFSIZE=256
-CONFIG_DISABLE_POLL=y
 CONFIG_LIB_BOARDCTL=y
 CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
diff --git a/configs/hymini-stm32v/usbserial/defconfig b/configs/hymini-stm32v/usbserial/defconfig
index 70d639dffc5..55534d750e2 100644
--- a/configs/hymini-stm32v/usbserial/defconfig
+++ b/configs/hymini-stm32v/usbserial/defconfig
@@ -14,7 +14,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
 CONFIG_BOARD_LOOPSPERMSEC=5483
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_USBSERIAL=y
 CONFIG_LIB_BOARDCTL=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/imxrt1050-evk/include/board.h b/configs/imxrt1050-evk/include/board.h
index 9cfd9ddb2c4..257a9156b26 100644
--- a/configs/imxrt1050-evk/include/board.h
+++ b/configs/imxrt1050-evk/include/board.h
@@ -206,6 +206,14 @@
 #define BOARD_USDHC_SD4MODE_PRESCALER   USDHC_SYSCTL_SDCLKFS_DIV8
 #define BOARD_USDHC_SD4MODE_DIVISOR     USDHC_SYSCTL_DVS_DIV(1)
 
+/* ETH Disambiguation ***************************************************************/
+#define GPIO_ENET_MDIO                  GPIO_ENET_MDIO_3
+#define GPIO_ENET_MDC                   GPIO_ENET_MDC_3
+#define GPIO_ENET_RX_EN                 GPIO_ENET_RX_EN_1
+#define GPIO_ENET_RX_ER                 GPIO_ENET_RX_ER_1
+#define GPIO_ENET_TX_CLK                GPIO_ENET_TX_CLK_1
+#define GPIO_ENET_TX_EN                 GPIO_ENET_TX_EN_1
+
 /* PIO Disambiguation ***************************************************************/
 
 /* LPUARTs
diff --git a/configs/imxrt1050-evk/kernel/imxrt_userspace.c b/configs/imxrt1050-evk/kernel/imxrt_userspace.c
index 92067a08d4a..1b120f0498d 100644
--- a/configs/imxrt1050-evk/kernel/imxrt_userspace.c
+++ b/configs/imxrt1050-evk/kernel/imxrt_userspace.c
@@ -114,9 +114,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/imxrt1050-evk/netnsh/defconfig b/configs/imxrt1050-evk/netnsh/defconfig
index 4df9b417afe..ea595ee3030 100644
--- a/configs/imxrt1050-evk/netnsh/defconfig
+++ b/configs/imxrt1050-evk/netnsh/defconfig
@@ -30,6 +30,7 @@ CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_NET=y
 CONFIG_NETDEV_STATISTICS=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NET_ARP_SEND=y
 CONFIG_NET_BROADCAST=y
@@ -52,7 +53,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_WDOGS=16
diff --git a/configs/imxrt1060-evk/include/board.h b/configs/imxrt1060-evk/include/board.h
index a77946df855..d0153fdd3b7 100644
--- a/configs/imxrt1060-evk/include/board.h
+++ b/configs/imxrt1060-evk/include/board.h
@@ -1,9 +1,10 @@
 /************************************************************************************
  * configs/imxrt1060/include/board.h
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
  *            David Sidrane 
+ *            Dave Marples 
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -197,6 +198,15 @@
 #define BOARD_USDHC_SD4MODE_PRESCALER   USDHC_SYSCTL_SDCLKFS_DIV8
 #define BOARD_USDHC_SD4MODE_DIVISOR     USDHC_SYSCTL_DVS_DIV(1)
 
+/* ETH Disambiguation ***************************************************************/
+
+#define GPIO_ENET_MDIO                  GPIO_ENET_MDIO_3
+#define GPIO_ENET_MDC                   GPIO_ENET_MDC_3
+#define GPIO_ENET_RX_EN                 GPIO_ENET_RX_EN_1
+#define GPIO_ENET_RX_ER                 GPIO_ENET_RX_ER_1
+#define GPIO_ENET_TX_CLK                GPIO_ENET_TX_CLK_1
+#define GPIO_ENET_TX_EN                 GPIO_ENET_TX_EN_1
+
 /* PIO Disambiguation ***************************************************************/
 /* LPUARTs
  *
diff --git a/configs/imxrt1060-evk/kernel/imxrt_userspace.c b/configs/imxrt1060-evk/kernel/imxrt_userspace.c
index f2e072b0da2..c441cbbbfd9 100644
--- a/configs/imxrt1060-evk/kernel/imxrt_userspace.c
+++ b/configs/imxrt1060-evk/kernel/imxrt_userspace.c
@@ -114,9 +114,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/imxrt1060-evk/netnsh/defconfig b/configs/imxrt1060-evk/netnsh/defconfig
index e5fc5207c8e..75f44386467 100644
--- a/configs/imxrt1060-evk/netnsh/defconfig
+++ b/configs/imxrt1060-evk/netnsh/defconfig
@@ -30,6 +30,7 @@ CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_NET=y
 CONFIG_NETDEV_STATISTICS=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NET_ARP_SEND=y
 CONFIG_NET_BROADCAST=y
@@ -52,7 +53,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_WDOGS=16
diff --git a/configs/kwikstik-k40/ostest/defconfig b/configs/kwikstik-k40/ostest/defconfig
index ff29976d0b8..0120a411d4b 100644
--- a/configs/kwikstik-k40/ostest/defconfig
+++ b/configs/kwikstik-k40/ostest/defconfig
@@ -18,7 +18,6 @@ CONFIG_BOARD_LOOPSPERMSEC=9535
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_KINETIS_UART5=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/launchxl-cc1310/nsh/defconfig b/configs/launchxl-cc1310/nsh/defconfig
index c55eec66e02..70a3bf91ac6 100644
--- a/configs/launchxl-cc1310/nsh/defconfig
+++ b/configs/launchxl-cc1310/nsh/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_USEBASEPRI=y
 CONFIG_BOARD_LOOPSPERMSEC=8192
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_FS_PROCFS=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/launchxl-cc1312r1/nsh/defconfig b/configs/launchxl-cc1312r1/nsh/defconfig
index ff560516c58..88410627eda 100644
--- a/configs/launchxl-cc1312r1/nsh/defconfig
+++ b/configs/launchxl-cc1312r1/nsh/defconfig
@@ -21,7 +21,6 @@ CONFIG_ARMV7M_LAZYFPU=y
 CONFIG_ARMV7M_USEBASEPRI=y
 CONFIG_BOARD_LOOPSPERMSEC=8192
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_FS_PROCFS=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/launchxl-tms57004/nsh/defconfig b/configs/launchxl-tms57004/nsh/defconfig
index c3d1cdb5eb6..2464fea1ab6 100644
--- a/configs/launchxl-tms57004/nsh/defconfig
+++ b/configs/launchxl-tms57004/nsh/defconfig
@@ -18,7 +18,6 @@ CONFIG_ARCH_LOWVECTORS=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7R_TOOLCHAIN_BUILDROOT=y
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/lc823450-xgevk/bt/defconfig b/configs/lc823450-xgevk/bt/defconfig
index 0435de16822..efe3096b597 100644
--- a/configs/lc823450-xgevk/bt/defconfig
+++ b/configs/lc823450-xgevk/bt/defconfig
@@ -82,6 +82,11 @@ CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSCLIENT_MAXRESPONSE=176
 CONFIG_NETDEVICES=y
+CONFIG_NETINIT_DRIPADDR=0xa9feab5a
+CONFIG_NETINIT_MACADDR_1=0xdeadbeff
+CONFIG_NETINIT_NETMASK=0xffff0000
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_CODECS=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -93,7 +98,6 @@ CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_LOOPBACK=y
 CONFIG_NET_PKT=y
 CONFIG_NET_ROUTE=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCP_KEEPALIVE=y
@@ -118,14 +122,9 @@ CONFIG_NSH_DISABLE_MKRD=y
 CONFIG_NSH_DISABLE_PUT=y
 CONFIG_NSH_DISABLE_SH=y
 CONFIG_NSH_DISABLE_XD=y
-CONFIG_NSH_DRIPADDR=0xa9feab5a
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=128
-CONFIG_NSH_MACADDR=0x00e0deadbeff
 CONFIG_NSH_MAXARGUMENTS=10
-CONFIG_NSH_NETINIT_THREAD=y
-CONFIG_NSH_NETMASK=0xffff0000
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSH_WGET_USERAGENT="NuttX/7.2x.x (; http://www.nuttx.org/)"
 CONFIG_NX=y
diff --git a/configs/lc823450-xgevk/kernel/lc823450_userspace.c b/configs/lc823450-xgevk/kernel/lc823450_userspace.c
index 82f764d9579..5407c4c6b02 100644
--- a/configs/lc823450-xgevk/kernel/lc823450_userspace.c
+++ b/configs/lc823450-xgevk/kernel/lc823450_userspace.c
@@ -117,9 +117,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/lc823450-xgevk/kostest/defconfig b/configs/lc823450-xgevk/kostest/defconfig
index 6cd2055dab7..d49aa847916 100644
--- a/configs/lc823450-xgevk/kostest/defconfig
+++ b/configs/lc823450-xgevk/kostest/defconfig
@@ -18,7 +18,6 @@ CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_LC823450_MTM0_TICK=y
 CONFIG_LC823450_SPIFI=y
diff --git a/configs/lc823450-xgevk/krndis/defconfig b/configs/lc823450-xgevk/krndis/defconfig
index 7cca32a8466..9ac74ce6c45 100644
--- a/configs/lc823450-xgevk/krndis/defconfig
+++ b/configs/lc823450-xgevk/krndis/defconfig
@@ -87,6 +87,13 @@ CONFIG_NAME_MAX=765
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDEVICES=y
+CONFIG_NETINIT_DHCPC=y
+CONFIG_NETINIT_DRIPADDR=0xa9feab5a
+CONFIG_NETINIT_MACADDR_1=0xdeadbeff
+CONFIG_NETINIT_MACADDR_2=0x00e0
+CONFIG_NETINIT_NETMASK=0xffff0000
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_CODECS=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_TELNETD=y
@@ -99,7 +106,6 @@ CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_LOOPBACK=y
 CONFIG_NET_PKT=y
 CONFIG_NET_ROUTE=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_UDP=y
@@ -108,7 +114,6 @@ CONFIG_NFILE_DESCRIPTORS=45
 CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_CMDOPT_DD_STATS=y
-CONFIG_NSH_DHCPC=y
 CONFIG_NSH_DISABLE_BASENAME=y
 CONFIG_NSH_DISABLE_DIRNAME=y
 CONFIG_NSH_DISABLE_EXEC=y
@@ -121,15 +126,10 @@ CONFIG_NSH_DISABLE_MKRD=y
 CONFIG_NSH_DISABLE_PUT=y
 CONFIG_NSH_DISABLE_SH=y
 CONFIG_NSH_DISABLE_XD=y
-CONFIG_NSH_DRIPADDR=0xa9feab5a
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_FILE_APPS=y
 CONFIG_NSH_LINELEN=128
-CONFIG_NSH_MACADDR=0x00e0deadbeff
 CONFIG_NSH_MAXARGUMENTS=10
-CONFIG_NSH_NETINIT_THREAD=y
-CONFIG_NSH_NETMASK=0xffff0000
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSH_WGET_USERAGENT="NuttX/7.2x.x (; http://www.nuttx.org/)"
 CONFIG_NUTTX_USERSPACE=0x05020000
diff --git a/configs/lc823450-xgevk/rndis/defconfig b/configs/lc823450-xgevk/rndis/defconfig
index 108bddabef9..0a834bfd63c 100644
--- a/configs/lc823450-xgevk/rndis/defconfig
+++ b/configs/lc823450-xgevk/rndis/defconfig
@@ -84,6 +84,13 @@ CONFIG_NAME_MAX=765
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDEVICES=y
+CONFIG_NETINIT_DHCPC=y
+CONFIG_NETINIT_DRIPADDR=0xa9feab5a
+CONFIG_NETINIT_MACADDR_1=0xdeadbeff
+CONFIG_NETINIT_MACADDR_2=0x00e0
+CONFIG_NETINIT_NETMASK=0xffff0000
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_CODECS=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_TELNETD=y
@@ -96,7 +103,6 @@ CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_LOOPBACK=y
 CONFIG_NET_PKT=y
 CONFIG_NET_ROUTE=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_UDP=y
@@ -108,7 +114,6 @@ CONFIG_NFS_STATISTICS=y
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_CMDOPT_DD_STATS=y
-CONFIG_NSH_DHCPC=y
 CONFIG_NSH_DISABLE_BASENAME=y
 CONFIG_NSH_DISABLE_DIRNAME=y
 CONFIG_NSH_DISABLE_EXEC=y
@@ -121,15 +126,10 @@ CONFIG_NSH_DISABLE_MKRD=y
 CONFIG_NSH_DISABLE_PUT=y
 CONFIG_NSH_DISABLE_SH=y
 CONFIG_NSH_DISABLE_XD=y
-CONFIG_NSH_DRIPADDR=0xa9feab5a
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_FILE_APPS=y
 CONFIG_NSH_LINELEN=128
-CONFIG_NSH_MACADDR=0x00e0deadbeff
 CONFIG_NSH_MAXARGUMENTS=10
-CONFIG_NSH_NETINIT_THREAD=y
-CONFIG_NSH_NETMASK=0xffff0000
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSH_TELNETD_CLIENTSTACKSIZE=3072
 CONFIG_NSH_WGET_USERAGENT="NuttX/7.2x.x (; http://www.nuttx.org/)"
diff --git a/configs/lc823450-xgevk/scripts/ld-ipl2.script b/configs/lc823450-xgevk/scripts/ld-ipl2.script
index e9ace773cf8..a0189134698 100644
--- a/configs/lc823450-xgevk/scripts/ld-ipl2.script
+++ b/configs/lc823450-xgevk/scripts/ld-ipl2.script
@@ -47,75 +47,79 @@ ENTRY(_stext)
 SECTIONS
 {
 
-	.text : {
-		_stext = ABSOLUTE(.);
-		KEEP(*(.vectors))
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > progmem
+        .text : {
+                _stext = ABSOLUTE(.);
+                KEEP(*(.vectors))
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > progmem
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		KEEP(*(.init_array .init_array.*))
-		_einit = ABSOLUTE(.);
-	} > progmem
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                KEEP(*(.init_array .init_array.*))
+                _einit = ABSOLUTE(.);
+        } > progmem
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > progmem
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > progmem
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > progmem
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > progmem
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(LOADADDR(.data));
+        _eronly = ABSOLUTE(LOADADDR(.data));
 
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		. = ALIGN(4);
-		_edata = ABSOLUTE(.);
-	} > sram AT > progmem
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                . = ALIGN(4);
+                _edata = ABSOLUTE(.);
+        } > sram AT > progmem
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		. = ALIGN(4);
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                . = ALIGN(4);
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	.ramlog : {
-		*(.ramlog)
-	} > ramlog
+        .ramlog : {
+                *(.ramlog)
+        } > ramlog
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/lc823450-xgevk/scripts/ld-spif-boot.script b/configs/lc823450-xgevk/scripts/ld-spif-boot.script
index 036a665bd8d..4631d8bd140 100644
--- a/configs/lc823450-xgevk/scripts/ld-spif-boot.script
+++ b/configs/lc823450-xgevk/scripts/ld-spif-boot.script
@@ -62,6 +62,7 @@ SECTIONS
       _etext = ABSOLUTE(.);
     } > flash
 
+  . = ALIGN(4);
   .init_section :
     {
       _sinit = ABSOLUTE(.);
@@ -74,6 +75,7 @@ SECTIONS
       *(.ARM.extab*)
     } > flash
 
+  . = ALIGN(4);
   __exidx_start = ABSOLUTE(.);
   .ARM.exidx :
     {
@@ -83,6 +85,7 @@ SECTIONS
 
   _eronly = ABSOLUTE(LOADADDR(.data));
 
+  . = ALIGN(4);
   .data :
     {
       _sdata = ABSOLUTE(.);
diff --git a/configs/lc823450-xgevk/scripts/ld.script b/configs/lc823450-xgevk/scripts/ld.script
index 5a153ee5033..2876760330b 100644
--- a/configs/lc823450-xgevk/scripts/ld.script
+++ b/configs/lc823450-xgevk/scripts/ld.script
@@ -69,6 +69,7 @@ SECTIONS
       _etext = ABSOLUTE(.);
     } > progmem
 
+  . = ALIGN(4);
   .init_section :
     {
       _sinit = ABSOLUTE(.);
@@ -81,6 +82,7 @@ SECTIONS
       *(.ARM.extab*)
     } > progmem
 
+  . = ALIGN(4);
   __exidx_start = ABSOLUTE(.);
   .ARM.exidx :
     {
@@ -90,6 +92,7 @@ SECTIONS
 
   _eronly = ABSOLUTE(LOADADDR(.data));
 
+  . = ALIGN(4);
   .data :
     {
       _sdata = ABSOLUTE(.);
diff --git a/configs/lc823450-xgevk/src/lc823450_bringup.c b/configs/lc823450-xgevk/src/lc823450_bringup.c
index b6f35319528..647aaab2628 100644
--- a/configs/lc823450-xgevk/src/lc823450_bringup.c
+++ b/configs/lc823450-xgevk/src/lc823450_bringup.c
@@ -116,14 +116,14 @@ int lc823450_bringup(void)
   lc823450_wm8776initialize(0);
 #endif
 
-#if defined(CONFIG_RNDIS) && defined(CONFIG_NSH_MACADDR)
+#if defined(CONFIG_RNDIS) && defined(CONFIG_NETINIT_MACADDR)
   uint8_t mac[6];
   mac[0] = 0xa0; /* TODO */
-  mac[1] = (CONFIG_NSH_MACADDR >> (8 * 4)) & 0xff;
-  mac[2] = (CONFIG_NSH_MACADDR >> (8 * 3)) & 0xff;
-  mac[3] = (CONFIG_NSH_MACADDR >> (8 * 2)) & 0xff;
-  mac[4] = (CONFIG_NSH_MACADDR >> (8 * 1)) & 0xff;
-  mac[5] = (CONFIG_NSH_MACADDR >> (8 * 0)) & 0xff;
+  mac[1] = (CONFIG_NETINIT_MACADDR >> (8 * 4)) & 0xff;
+  mac[2] = (CONFIG_NETINIT_MACADDR >> (8 * 3)) & 0xff;
+  mac[3] = (CONFIG_NETINIT_MACADDR >> (8 * 2)) & 0xff;
+  mac[4] = (CONFIG_NETINIT_MACADDR >> (8 * 1)) & 0xff;
+  mac[5] = (CONFIG_NETINIT_MACADDR >> (8 * 0)) & 0xff;
   usbdev_rndis_initialize(mac);
 #endif
 
diff --git a/configs/lincoln60/netnsh/defconfig b/configs/lincoln60/netnsh/defconfig
index 71f74401bb0..d13f5b84ed1 100644
--- a/configs/lincoln60/netnsh/defconfig
+++ b/configs/lincoln60/netnsh/defconfig
@@ -32,6 +32,7 @@ CONFIG_MM_REGIONS=2
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
@@ -41,7 +42,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=8
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -53,7 +53,6 @@ CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/lincoln60/nsh/defconfig b/configs/lincoln60/nsh/defconfig
index 9982cf7d1e8..46c85664465 100644
--- a/configs/lincoln60/nsh/defconfig
+++ b/configs/lincoln60/nsh/defconfig
@@ -15,7 +15,6 @@ CONFIG_ARCH_CHIP_LPC17XX=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
 CONFIG_BOARD_LOOPSPERMSEC=7982
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_FAT=y
 CONFIG_LPC17_SSP0=y
 CONFIG_LPC17_UART0=y
diff --git a/configs/lincoln60/scripts/ld.script b/configs/lincoln60/scripts/ld.script
index b5f78128723..fe4307b52a0 100644
--- a/configs/lincoln60/scripts/ld.script
+++ b/configs/lincoln60/scripts/ld.script
@@ -51,66 +51,70 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
-					/* Stabs debugging sections.	*/
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
+                                        /* Stabs debugging sections.    */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/lm3s6965-ek/discover/defconfig b/configs/lm3s6965-ek/discover/defconfig
index 8154bb7a8f5..94e0e34824c 100644
--- a/configs/lm3s6965-ek/discover/defconfig
+++ b/configs/lm3s6965-ek/discover/defconfig
@@ -26,6 +26,7 @@ CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSCLIENT_ENTRIES=4
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
@@ -34,7 +35,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=8
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_UDP=y
@@ -44,7 +44,6 @@ CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/lm3s6965-ek/nsh/defconfig b/configs/lm3s6965-ek/nsh/defconfig
index 8154bb7a8f5..94e0e34824c 100644
--- a/configs/lm3s6965-ek/nsh/defconfig
+++ b/configs/lm3s6965-ek/nsh/defconfig
@@ -26,6 +26,7 @@ CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSCLIENT_ENTRIES=4
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
@@ -34,7 +35,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=8
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_UDP=y
@@ -44,7 +44,6 @@ CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/lm3s6965-ek/nx/defconfig b/configs/lm3s6965-ek/nx/defconfig
index bb6a8125c1c..ed093cbcc89 100644
--- a/configs/lm3s6965-ek/nx/defconfig
+++ b/configs/lm3s6965-ek/nx/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=4531
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NX_BGCOLOR=0x02
diff --git a/configs/lm3s6965-ek/scripts/ld.script b/configs/lm3s6965-ek/scripts/ld.script
index 69b2a35ac86..ee9a22ad542 100644
--- a/configs/lm3s6965-ek/scripts/ld.script
+++ b/configs/lm3s6965-ek/scripts/ld.script
@@ -48,68 +48,72 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The LM3S6918 has 64Kb of SRAM beginning at the following address */
+        /* The LM3S6918 has 64Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {			/* BSS				*/
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
-					/* Stabs debugging sections.	*/
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        .bss : {                        /* BSS                          */
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
+                                        /* Stabs debugging sections.    */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/lm3s8962-ek/nsh/defconfig b/configs/lm3s8962-ek/nsh/defconfig
index 1f3815efabc..22449c8d4f8 100644
--- a/configs/lm3s8962-ek/nsh/defconfig
+++ b/configs/lm3s8962-ek/nsh/defconfig
@@ -26,6 +26,7 @@ CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSCLIENT_ENTRIES=4
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -33,7 +34,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=8
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_UDP=y
@@ -43,7 +43,6 @@ CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/lm3s8962-ek/nx/defconfig b/configs/lm3s8962-ek/nx/defconfig
index 82ac9c6fc4e..c5fc22a8851 100644
--- a/configs/lm3s8962-ek/nx/defconfig
+++ b/configs/lm3s8962-ek/nx/defconfig
@@ -19,7 +19,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=4531
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NX_BGCOLOR=2
diff --git a/configs/lm3s8962-ek/scripts/ld.script b/configs/lm3s8962-ek/scripts/ld.script
index 529b596cf72..16840d040ed 100644
--- a/configs/lm3s8962-ek/scripts/ld.script
+++ b/configs/lm3s8962-ek/scripts/ld.script
@@ -48,68 +48,72 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The LM3S6918 has 64Kb of SRAM beginning at the following address */
+        /* The LM3S6918 has 64Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {			/* BSS				*/
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
-					/* Stabs debugging sections.	*/
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        .bss : {                        /* BSS                          */
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
+                                        /* Stabs debugging sections.    */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/lm4f120-launchpad/nsh/defconfig b/configs/lm4f120-launchpad/nsh/defconfig
index 6fef4a67ccd..017a3e8fb20 100644
--- a/configs/lm4f120-launchpad/nsh/defconfig
+++ b/configs/lm4f120-launchpad/nsh/defconfig
@@ -19,7 +19,6 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=4531
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_NFILE_DESCRIPTORS=8
diff --git a/configs/lpc4330-xplorer/src/lpc43_ostest.c b/configs/lpc4330-xplorer/src/lpc43_ostest.c
index b0656ab48b2..26aec01a73e 100644
--- a/configs/lpc4330-xplorer/src/lpc43_ostest.c
+++ b/configs/lpc4330-xplorer/src/lpc43_ostest.c
@@ -58,7 +58,7 @@
 
 #undef HAVE_FPU
 #if defined(CONFIG_ARCH_FPU) && defined(CONFIG_TESTING_OSTEST_FPUSIZE) && \
-    defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_DISABLE_SIGNALS)
+    defined(CONFIG_SCHED_WAITPID)
 #    define HAVE_FPU 1
 #endif
 
diff --git a/configs/lpc4357-evb/src/lpc43_ostest.c b/configs/lpc4357-evb/src/lpc43_ostest.c
index 8ac41b2aaf1..3c5cb05b2fc 100644
--- a/configs/lpc4357-evb/src/lpc43_ostest.c
+++ b/configs/lpc4357-evb/src/lpc43_ostest.c
@@ -58,7 +58,7 @@
 
 #undef HAVE_FPU
 #if defined(CONFIG_ARCH_FPU) && defined(CONFIG_TESTING_OSTEST_FPUSIZE) && \
-    defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_DISABLE_SIGNALS)
+    defined(CONFIG_SCHED_WAITPID)
 #    define HAVE_FPU 1
 #endif
 
diff --git a/configs/lpc4370-link2/src/lpc43_ostest.c b/configs/lpc4370-link2/src/lpc43_ostest.c
index cd058b9918a..6e880a5446e 100644
--- a/configs/lpc4370-link2/src/lpc43_ostest.c
+++ b/configs/lpc4370-link2/src/lpc43_ostest.c
@@ -58,7 +58,7 @@
 
 #undef HAVE_FPU
 #if defined(CONFIG_ARCH_FPU) && defined(CONFIG_TESTING_OSTEST_FPUSIZE) && \
-    defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_DISABLE_SIGNALS)
+    defined(CONFIG_SCHED_WAITPID)
 #    define HAVE_FPU 1
 #endif
 
diff --git a/configs/lpcxpresso-lpc1115/nsh/defconfig b/configs/lpcxpresso-lpc1115/nsh/defconfig
index 2517ed4136c..d0c0dec232c 100644
--- a/configs/lpcxpresso-lpc1115/nsh/defconfig
+++ b/configs/lpcxpresso-lpc1115/nsh/defconfig
@@ -24,7 +24,6 @@ CONFIG_BUILTIN=y
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_MAX_TASKS=4
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_MM_SMALL=y
diff --git a/configs/lpcxpresso-lpc1768/dhcpd/defconfig b/configs/lpcxpresso-lpc1768/dhcpd/defconfig
index 9676f2cee4f..e74d98b38bb 100644
--- a/configs/lpcxpresso-lpc1768/dhcpd/defconfig
+++ b/configs/lpcxpresso-lpc1768/dhcpd/defconfig
@@ -17,7 +17,6 @@ CONFIG_BOARD_LOOPSPERMSEC=8079
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_ETH0_PHY_LAN8720=y
 CONFIG_EXAMPLES_DHCPD=y
diff --git a/configs/lpcxpresso-lpc1768/nsh/defconfig b/configs/lpcxpresso-lpc1768/nsh/defconfig
index 2f9ab654246..7e6d02bc2c5 100644
--- a/configs/lpcxpresso-lpc1768/nsh/defconfig
+++ b/configs/lpcxpresso-lpc1768/nsh/defconfig
@@ -38,6 +38,7 @@ CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSCLIENT_ENTRIES=4
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -45,7 +46,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=8
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_UDP=y
@@ -56,7 +56,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
 CONFIG_NSH_MMCSDSPIPORTNO=1
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/lpcxpresso-lpc1768/nx/defconfig b/configs/lpcxpresso-lpc1768/nx/defconfig
index 7653946ae38..435500e3784 100644
--- a/configs/lpcxpresso-lpc1768/nx/defconfig
+++ b/configs/lpcxpresso-lpc1768/nx/defconfig
@@ -19,7 +19,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODEREDL=y
 CONFIG_BOARD_LOOPSPERMSEC=8079
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NX_BGCOLOR=0
diff --git a/configs/lpcxpresso-lpc1768/scripts/ld.script b/configs/lpcxpresso-lpc1768/scripts/ld.script
index acb1c083ba6..b2b8bcf425c 100644
--- a/configs/lpcxpresso-lpc1768/scripts/ld.script
+++ b/configs/lpcxpresso-lpc1768/scripts/ld.script
@@ -51,68 +51,72 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections */
+        /* Stabs debugging sections */
 
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/lpcxpresso-lpc1768/usbmsc/defconfig b/configs/lpcxpresso-lpc1768/usbmsc/defconfig
index c54187a57f6..cbef1483aff 100644
--- a/configs/lpcxpresso-lpc1768/usbmsc/defconfig
+++ b/configs/lpcxpresso-lpc1768/usbmsc/defconfig
@@ -15,7 +15,6 @@ CONFIG_ARCH_CHIP_LPC17XX=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_CODEREDL=y
 CONFIG_BOARD_LOOPSPERMSEC=8079
-CONFIG_DISABLE_POLL=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_LIB_BOARDCTL=y
 CONFIG_LPC17_SSP1=y
diff --git a/configs/lpcxpresso-lpc54628/README.txt b/configs/lpcxpresso-lpc54628/README.txt
index 70165225038..08ef714b0ae 100644
--- a/configs/lpcxpresso-lpc54628/README.txt
+++ b/configs/lpcxpresso-lpc54628/README.txt
@@ -115,10 +115,17 @@ STATUS
   2018-10-24:  Dave Marples now has the LPC43 SD/MMC working reliably.  I
     have ported all of Dave's change to the LPC54 but have done no further
     testing as of this writing.  The feature is still marked EXPERIMENTAL.
+  2019-05-08:  I brought in the USB0 OHCI USB host driver from LPC17.  Since
+    OHCI is well standardized, this should work out of the box provided that
+    the peripheral is properly configured, initialized, and clocked.  The
+    clock setup logic is missing as of this writing (the driver is not yet
+    even included in the build and completely unverified).
 
   There is still no support for the Accelerometer, SPIFI, or USB.  There is
   a complete but not entirely functional SD card driver and and tested SPI
-  driver.  There are no on-board devices to support SPI testing.
+  driver.  There is also a partial port of the USB0 OHCI host driver if
+  anyone is ambitious enought to finish that off.  There are no on-board
+  devices to support SPI testing.
 
 Configurations
 ==============
@@ -508,3 +515,55 @@ Configurations
     graphic (based on the rotating line of apps/examples/nslines).
 
       2019-03-20:  Everything works fine!
+
+  twm4nx1 and twmnx2:
+
+    These configuration exercises the port of TWM to NuttX.  A description of
+    that port is available at apps/graphics/twm4nx/README.txt.  The two
+    configurations are identical, differing on in the "theme" of the UI.
+    twm4nx1 uses framed windows in dark, bright primary colors reminiscent of
+    Windows98. twm4nx2 uses border-less windows in pastel shades for a more
+    contemporary look.
+
+    NOTES:
+    1. This version uses the on-board display with the touchscreen for
+       positional input (instead of a mouse).  Keyboard input is currently
+       disabled only because (1) there is no Twm4Nx application that needs
+       it, and (2) I will first need to create a USB host driver to support
+       a USB keyboard.
+
+    STATUS:
+
+    Refer to apps/graphics/twm4nx/README.txt for an overall status.  Here
+    just some issues/topics unique to the LPCXpresso-LPC54628 and/or this
+    configuration.
+
+    1. There is a responsive-ness issue the the FT5x06 touchscreen controller.
+       The pin selected by the board designers will not support interrupts.
+       Therefore, a fallback polled mode is use.  This polled mode has
+       significant inherent delays that effect the user experience when
+       touching buttons or grabbing and moving objects on the desktop.
+
+    2. The NxTerm application is available as the "NuttShell" entry in the
+       Main Menu.  When pressed, this will bring up an NSH session in a
+       Twm4Nx window.  There is a performance issue, however, due to another
+       issue with the polled mode in the ft5x06 driver.  When that driver
+       runs in polled mode, it samples the touch data at a high rate.  Each
+       sample is sufficient to wake up the Twm4Nx poll() with POLLIN data
+       availability.  But when Twm4Nx tries to read the data, it falls under
+       the FT5x06.c there threshold and no data is returned.
+
+       The actual delay various dynamically from 50 to 200 millisecond
+       intervals.
+
+       A possible solution might be to beef up the POLLIN notification logic
+       in FT5x06.c to avoid these false poll() wake-ups.  That, however, is
+       non-trivial since it would have to support the polled as well as the
+       non-polled mode.
+
+    3. Color artifacts:  In the CLASSIC configuration, the background of the
+       cental NX image is a slightly different hue of blue.  For the
+       CONTEMPORARY configuration, the toolbar buttons are supposed to be
+       borderless.  There is however, a fine border around each toolbar
+       widget with ruins the feel that the theme was trying for.
+
diff --git a/configs/lpcxpresso-lpc54628/netnsh/defconfig b/configs/lpcxpresso-lpc54628/netnsh/defconfig
index 557f281a072..a53210e0eb0 100644
--- a/configs/lpcxpresso-lpc54628/netnsh/defconfig
+++ b/configs/lpcxpresso-lpc54628/netnsh/defconfig
@@ -35,6 +35,7 @@ CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_MM_REGIONS=2
 CONFIG_NET=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NET_ARP_SEND=y
@@ -54,7 +55,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/lpcxpresso-lpc54628/src/lpc54_sdram.c b/configs/lpcxpresso-lpc54628/src/lpc54_sdram.c
index febfbec82f9..5e50b8367c6 100644
--- a/configs/lpcxpresso-lpc54628/src/lpc54_sdram.c
+++ b/configs/lpcxpresso-lpc54628/src/lpc54_sdram.c
@@ -39,7 +39,7 @@
 
 #include 
 
-#include "chip/lpc54_pinmux.h"
+#include "hardware/lpc54_pinmux.h"
 #include "lpc54_gpio.h"
 #include "lpc54_emc.h"
 #include "lpcxpresso-lpc54628.h"
diff --git a/configs/lpcxpresso-lpc54628/twm4nx1/defconfig b/configs/lpcxpresso-lpc54628/twm4nx1/defconfig
new file mode 100644
index 00000000000..0757e17288f
--- /dev/null
+++ b/configs/lpcxpresso-lpc54628/twm4nx1/defconfig
@@ -0,0 +1,108 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_FPU is not set
+# CONFIG_NSH_DISABLE_DATE is not set
+# CONFIG_NXFONTS_DISABLE_16BPP is not set
+# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set
+# CONFIG_NX_DISABLE_16BPP is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="lpcxpresso-lpc54628"
+CONFIG_ARCH_BOARD_LPCXPRESSO_LPC54628=y
+CONFIG_ARCH_CHIP_LPC54628=y
+CONFIG_ARCH_CHIP_LPC54XX=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_STDARG_H=y
+CONFIG_BOARD_LOOPSPERMSEC=21082
+CONFIG_EXPERIMENTAL=y
+CONFIG_FS_PROCFS=y
+CONFIG_FT5X06_POLLMODE=y
+CONFIG_FT5X06_SINGLEPOINT=y
+CONFIG_FT5X06_SWAPXY=y
+CONFIG_FT5X06_THRESHX=8
+CONFIG_FT5X06_THRESHY=8
+CONFIG_GRAPHICS_TWM4NX=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_INPUT=y
+CONFIG_INPUT_FT5X06=y
+CONFIG_LIB_HOSTNAME="LPCXpresso-LPC54628"
+CONFIG_LPC54_EMC=y
+CONFIG_LPC54_EMC_DYNAMIC_CS0=y
+CONFIG_LPC54_EMC_DYNAMIC_CS0_OFFSET=0x00080000
+CONFIG_LPC54_EMC_DYNAMIC_CS0_SIZE=0x00f80000
+CONFIG_LPC54_GPIOIRQ=y
+CONFIG_LPC54_I2C2_MASTER=y
+CONFIG_LPC54_LCD=y
+CONFIG_LPC54_LCD_BGR=y
+CONFIG_LPC54_LCD_BPP16_565=y
+CONFIG_LPC54_LCD_HBACKPORCH=43
+CONFIG_LPC54_LCD_HFRONTPORCH=8
+CONFIG_LPC54_LCD_VBACKPORCH=12
+CONFIG_LPC54_LCD_VFRONTPORCH=4
+CONFIG_LPC54_LCD_VPULSE=10
+CONFIG_LPC54_LCD_VRAMBASE=0xa0000000
+CONFIG_LPC54_USART0=y
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_MM_REGIONS=2
+CONFIG_MQ_MAXMSGSIZE=64
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LIBRARY=y
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_NX=y
+CONFIG_NXFONT_SANS22X29B=y
+CONFIG_NXFONT_SANS23X27=y
+CONFIG_NXGLYPHS_BACKGROUNDCOLOR=0x9dfb
+CONFIG_NXTERM=y
+CONFIG_NXTERM_CACHESIZE=32
+CONFIG_NXTERM_CURSORCHAR=95
+CONFIG_NXTERM_MXCHARS=325
+CONFIG_NXTERM_NXKBDIN=y
+CONFIG_NXTK_BORDERCOLOR1=0x5cb7
+CONFIG_NXTK_BORDERCOLOR2=0x21c9
+CONFIG_NXTK_BORDERCOLOR3=0xffdf
+CONFIG_NXWIDGETS_BPP=16
+CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y
+CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y
+CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0x9dfb
+CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618
+CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xd73e
+CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9
+CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf
+CONFIG_NXWIDGETS_SIZEOFCHAR=1
+CONFIG_NX_BLOCKING=y
+CONFIG_NX_KBD=y
+CONFIG_NX_SWCURSOR=y
+CONFIG_NX_XYINPUT_TOUCHSCREEN=y
+CONFIG_PREALLOC_MQ_MSGS=64
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PREALLOC_WDOGS=8
+CONFIG_RAM_SIZE=163840
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_ONEXIT=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_START_DAY=4
+CONFIG_START_MONTH=5
+CONFIG_START_YEAR=2019
+CONFIG_SYMTAB_ORDEREDBYNAME=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_TWM4NX_ARCHINIT=y
+CONFIG_TWM4NX_ICONMGR_NCOLUMNS=2
+CONFIG_TWM4NX_KEYBOARD_DEVPATH="/dev/console"
+CONFIG_TWM4NX_TOUCHSCREEN=y
+CONFIG_USART0_SERIAL_CONSOLE=y
+CONFIG_USER_ENTRYPOINT="twm4nx_main"
+CONFIG_WDOG_INTRESERVE=0
diff --git a/configs/lpcxpresso-lpc54628/twm4nx2/defconfig b/configs/lpcxpresso-lpc54628/twm4nx2/defconfig
new file mode 100644
index 00000000000..cd3f077f232
--- /dev/null
+++ b/configs/lpcxpresso-lpc54628/twm4nx2/defconfig
@@ -0,0 +1,110 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_FPU is not set
+# CONFIG_NSH_DISABLE_DATE is not set
+# CONFIG_NXFONTS_DISABLE_16BPP is not set
+# CONFIG_NXTK_DEFAULT_BORDERCOLORS is not set
+# CONFIG_NX_DISABLE_16BPP is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="lpcxpresso-lpc54628"
+CONFIG_ARCH_BOARD_LPCXPRESSO_LPC54628=y
+CONFIG_ARCH_CHIP_LPC54628=y
+CONFIG_ARCH_CHIP_LPC54XX=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_STDARG_H=y
+CONFIG_BOARD_LOOPSPERMSEC=21082
+CONFIG_EXPERIMENTAL=y
+CONFIG_FS_PROCFS=y
+CONFIG_FT5X06_POLLMODE=y
+CONFIG_FT5X06_SINGLEPOINT=y
+CONFIG_FT5X06_SWAPXY=y
+CONFIG_FT5X06_THRESHX=8
+CONFIG_FT5X06_THRESHY=8
+CONFIG_GRAPHICS_TWM4NX=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_INPUT=y
+CONFIG_INPUT_FT5X06=y
+CONFIG_LIB_HOSTNAME="LPCXpresso-LPC54628"
+CONFIG_LPC54_EMC=y
+CONFIG_LPC54_EMC_DYNAMIC_CS0=y
+CONFIG_LPC54_EMC_DYNAMIC_CS0_OFFSET=0x00080000
+CONFIG_LPC54_EMC_DYNAMIC_CS0_SIZE=0x00f80000
+CONFIG_LPC54_GPIOIRQ=y
+CONFIG_LPC54_I2C2_MASTER=y
+CONFIG_LPC54_LCD=y
+CONFIG_LPC54_LCD_BGR=y
+CONFIG_LPC54_LCD_BPP16_565=y
+CONFIG_LPC54_LCD_HBACKPORCH=43
+CONFIG_LPC54_LCD_HFRONTPORCH=8
+CONFIG_LPC54_LCD_VBACKPORCH=12
+CONFIG_LPC54_LCD_VFRONTPORCH=4
+CONFIG_LPC54_LCD_VPULSE=10
+CONFIG_LPC54_LCD_VRAMBASE=0xa0000000
+CONFIG_LPC54_USART0=y
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_MM_REGIONS=2
+CONFIG_MQ_MAXMSGSIZE=64
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LIBRARY=y
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_NX=y
+CONFIG_NXFONT_SANS22X29B=y
+CONFIG_NXFONT_SANS23X27=y
+CONFIG_NXGLYPHS_BACKGROUNDCOLOR=0xc54a
+CONFIG_NXTERM=y
+CONFIG_NXTERM_CACHESIZE=32
+CONFIG_NXTERM_CURSORCHAR=95
+CONFIG_NXTERM_MXCHARS=325
+CONFIG_NXTERM_NXKBDIN=y
+CONFIG_NXTK_BORDERCOLOR1=0x5cb7
+CONFIG_NXTK_BORDERCOLOR2=0x21c9
+CONFIG_NXTK_BORDERCOLOR3=0xffdf
+CONFIG_NXTK_BORDERWIDTH=0
+CONFIG_NXWIDGETS_BPP=16
+CONFIG_NXWIDGETS_CUSTOM_EDGECOLORS=y
+CONFIG_NXWIDGETS_CUSTOM_FILLCOLORS=y
+CONFIG_NXWIDGETS_DEFAULT_BACKGROUNDCOLOR=0xdd71
+CONFIG_NXWIDGETS_DEFAULT_HIGHLIGHTCOLOR=0xc618
+CONFIG_NXWIDGETS_DEFAULT_SELECTEDBACKGROUNDCOLOR=0xfeb0
+CONFIG_NXWIDGETS_DEFAULT_SHADOWEDGECOLOR=0x21e9
+CONFIG_NXWIDGETS_DEFAULT_SHINEEDGECOLOR=0xffdf
+CONFIG_NXWIDGETS_SIZEOFCHAR=1
+CONFIG_NX_BLOCKING=y
+CONFIG_NX_KBD=y
+CONFIG_NX_SWCURSOR=y
+CONFIG_NX_XYINPUT_TOUCHSCREEN=y
+CONFIG_PREALLOC_MQ_MSGS=64
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PREALLOC_WDOGS=8
+CONFIG_RAM_SIZE=163840
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_ONEXIT=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_START_DAY=4
+CONFIG_START_MONTH=5
+CONFIG_START_YEAR=2019
+CONFIG_SYMTAB_ORDEREDBYNAME=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_TWM4NX_ARCHINIT=y
+CONFIG_TWM4NX_CONTEMPORARY=y
+CONFIG_TWM4NX_ICONMGR_NCOLUMNS=2
+CONFIG_TWM4NX_KEYBOARD_DEVPATH="/dev/console"
+CONFIG_TWM4NX_TOUCHSCREEN=y
+CONFIG_USART0_SERIAL_CONSOLE=y
+CONFIG_USER_ENTRYPOINT="twm4nx_main"
+CONFIG_WDOG_INTRESERVE=0
diff --git a/configs/makerlisp/Kconfig b/configs/makerlisp/Kconfig
new file mode 100644
index 00000000000..c1fd169749e
--- /dev/null
+++ b/configs/makerlisp/Kconfig
@@ -0,0 +1,15 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_MAKERLISP
+
+config MAKERLISP_VGA
+	bool "VGA Controller attached?"
+	default n
+	---help---
+		Select this option if you have an I/O Controller and a VGA vide card
+		connected.
+
+endif # ARCH_BOARD_MAKERLISP
diff --git a/configs/makerlisp/README.txt b/configs/makerlisp/README.txt
new file mode 100644
index 00000000000..ff11ef26f8b
--- /dev/null
+++ b/configs/makerlisp/README.txt
@@ -0,0 +1,298 @@
+README.txt
+==========
+
+The MakerLisp machine is a portable, modular computer system, designed to
+recapture the feel of classic computing, with modern hardware.
+
+The machine centers on a 2" x 3.5" business card-sized CPU, which can be used
+stand-alone, or plugged in to a 2" x 8" main board, for expansion into a full
+computer system.  A laser-cut wood enclosure holds a small keyboard, an LCD
+monitor, the circuit boards, and a prototyping area with a breadboard for
+electronics experimentation and development.
+
+The CPU is a Zilog eZ80 running at 50 MHz, with up to 16 Mb of zero-wait state
+RAM. A VGA display adapter provides an IBM PC-like color text-mode display. A
+USB Host Controller supports a USB keyboard and other USB communications.
+Data storage and interchange is accomplished by a micro-SD card supporting the
+FAT file system. All four of these circuit boards (shown on the web site's cover
+page) are new MakerLisp products, and will be available as part of the first
+product offering
+
+Contents
+========
+
+  o ZDS-II Compiler Versions
+  o Serial Console
+    - UARTs
+    - Serial Keyboard and VGA Display
+  o LEDs and Buttons
+    - LEDs
+    - Buttons
+  o Configurations
+    - Common Configuration Notes
+    - Configuration Subdirectories
+
+ZDS-II Compiler Versions
+========================
+
+Version 5.3.0
+
+  The initial bring-up of the MakerLisp board used the ZiLOG ZDS-II 5.3.0
+  toolchain.  To use this toolchain, I had to suppress the gmtime() and
+  gmtimer() because these were causing an internal compiler error:
+
+    time\lib_gmtimer.c
+    P2: Internal Error(0xB47E59):
+            Please contact Technical Support
+
+  This is the change to suppress building these files:
+
+    diff --git a/libs/libc/time/Make.defs b/libs/libc/time/Make.defs
+    index 5c9b746778..8327e287f4 100644
+    --- a/libs/libc/time/Make.defs
+    +++ b/libs/libc/time/Make.defs
+    @@ -44,7 +44,7 @@ ifdef CONFIG_LIBC_LOCALTIME
+     CSRCS += lib_localtime.c lib_asctime.c lib_asctimer.c lib_ctime.c
+     CSRCS += lib_ctimer.c
+     else
+    -CSRCS += lib_mktime.c lib_gmtime.c lib_gmtimer.c
+    +CSRCS += lib_mktime.c # lib_gmtime.c lib_gmtimer.c
+     ifdef CONFIG_TIME_EXTENDED
+     CSRCS += lib_dayofweek.c lib_asctime.c lib_asctimer.c lib_ctime.c
+     CSRCS += lib_ctimer.c
+
+  And there is also this:
+
+     stdlib\lib_strtof.c
+     stdlib\lib_strtof.c     (76,36) :       WARNING (32) Division by zero encountered
+     stdlib\lib_strtof.c     (102,36) :      WARNING (32) Division by zero encountered
+
+   Which can be worked around by removing it from the build
+
+  The consequence is, of course, that these interfaces will not be available
+  to applications.
+
+  Alternatively, you can use 'make -i' to build the system.  The above
+  errors will occur, but will not stop the build (unless the failed build
+  objects are brought into the link).  The has the negative side effects
+  that (1) the archives will always be rebuild in the directories where
+  the error occur, and (2) you might miss other, real compilation error
+  since these will no longer stop the compilation.
+
+Other Versions
+  If you use any version of ZDS-II other than 5.3.0 or if you install ZDS-II
+  at any location other than the default location, you will have to modify
+  three files:  (1) arch/arm/z80/src/ez80/Kconfig, (2)
+  configs/makerlisp/scripts/Make.defs and, perhaps, (3)
+  arch/z80/src/ez80/Toolchain.defs.
+
+Serial Console
+==============
+
+  There are two options for a serial console:  (1) A UART connected to a
+  terminal program or (2) the MakerLisp Serial Keyboard and VGA display.
+
+UARTs
+-----
+
+  The eZ80 has two UART peripherals:
+
+  UART 0:  All of Port D pins can support UART0 functions when configured
+  for the alternate function 7.  For typical configurations only RXD and TXD
+  need be configured.
+
+    eZ80 PIN        BOARD SIGNAL CN1 ACCESS
+    =======================================
+    PD0/TXD0/IR_IXD CN1_TX0      Pin 61
+    PD1/RXD0/IR_RXD CN1_RX0      Pin 59
+    PD2/RTS0        CN1_RTS0     Pin 63
+    PD3/CTS0        CN1_CTS0     Pin 65
+    PD4/DTR0        CN1_DTR0     Pin 67
+    PD5/DSR0        CN1_DSR0     Pin 69
+    PD6/DCD0        CN1_DCD0     Pin 71
+    PD7/RIO0        CN1_RI0      Pin 73
+
+  UART 0:  All of Port C pins can support UART1 functions when configured
+  for the alternate function 7.  For typical configurations only RXD and TXD
+  need be configured.
+
+    eZ80 PIN        BOARD SIGNAL CN1 ACCESS
+    =======================================
+    PC0/TXD1        CN1_TX1      Pin 62
+    PC1/RXD1        CN1_RX1      Pin 60
+    PC2/RTS1        CN1_RTS1     Pin 64
+    PC3/CTS1        CN1_CTS1     Pin 66
+    PC4/DTR1        CN1_DTR1     Pin 68
+    PC5/DSR1        CN1_DSR1     Pin 70
+    PC6/DCD1        CN1_DCD1     Pin 72
+    PC7/RIO1        CN1_RI1      Pin 74
+
+  For use with a host terminal emulation, it will be necessary to connect
+  either a TTL-to-RS232 or a TTL-to-USB Serial adapter to CN1 pins 59 and
+  61, and 60 and 62, depending on the selected UART.
+
+Serial Keyboard and VGA Display
+-------------------------------
+
+  The serial console can also be implemented using the MakerLisp USB
+  Keyboard Controller Board and VGA Display Controller.  These are accessed
+  via the one UART port, UART0.
+
+  In the default MakerLisp configuration.  These boards are connected as
+  follows:
+
+  1. VGA display controller connections (UART0 TX)
+
+     Board interface header
+     5  – 5V regulated power input
+     RX – VGA Display Controller serial input
+     C  – VGA Display Controller ready output
+     TX – VGA Display Controller serial output
+     G  – GND
+
+     Connections:
+
+     a. 5V '5' pin on VGA board to expansion board power distribution 5V.
+     b. Ground 'G' pin on VGA board to expansion board power distribution
+        ground.
+     c. Receive 'RX' pin on VGA board to expansion board GPIO PD0 (TXD0).
+     d. Communication, terminal ready indicator 'C' pin on VGA board to
+        expansion board GPIO PB1.
+     e. Transmit 'TX' pin on VGA board to USB keyboard controller 'R'
+
+     To use the VGA display controller with stdout and stderr, you also
+     need to selection CONFIG_MAKERLISP_VGA=y in your configuration.  This
+     enables a required VGA initialization sequence.
+
+  2. USB keyboard controller (UART0 RX)
+
+     Board interface header
+
+     5 – 5V regulated power input
+     R – USB Keyboard Controller serial input
+     T – USB Keyboard Controller serial output
+     G – GND
+
+     Connections:
+
+     a. 5V '5' pin on USB board to (other) expansion board power
+        distribution 5V.
+     b. Ground 'G' pin on USB board to (other) expansion board power
+        distribution ground.
+     c. Receive 'R' pin on USB board to VGA board 'TX' (see above).
+     d. Transmit 'T' pin on USB board to expansion board GPIO PD1 (RXD0).
+
+     If your keyboard does not seem to be doing anything, check the 'RX'
+     jumper on the expansion board. For input from a USB keyboard, and NOT
+     the USB/UART connection, you want this jumper REMOVED, not bridging the
+     two header pins front to back.
+
+  TBD:  What is the UART configuration when used with the VGA and Keyboard
+        adapters?
+
+Default Serial Console
+----------------------
+
+  UART0 is the default serial console in all configurations unless
+  otherwise noted in the description of the configuration.
+
+LEDs and Buttons
+================
+
+LEDs
+----
+
+  Three LEDs are available on the CPU Card, but none are available for
+  general use by applications:
+
+  D2 RED:    CPU Card power.  Not under eZ80 control
+  D3 GREEN:  Driven by CPU GPI/O pin.  However, it has some additional
+             properties:
+
+             1. On input, it will be '1' if the I/O expansion board is
+                present.
+             2. Setting it to an output of '0' will generate a system reset.
+             3. Setting it to an output of '1' will not only illuminate the
+                LED take the card out of reset and enable power to the SD
+                card slot.
+
+             As a consequence, the GREEN LED will not be illuminated if
+             SD card support or SPI is disabled.  The only effect of
+             CONFIG_ARCH_LEDS is that the GREEN LED will turned off in
+             the event of a crash.
+
+  D1 AMBER:  Controlled by the on-board MCP2221A USB bridge and provides USB
+             enumeration status.  Not under eZ80 control.
+
+Buttons
+-------
+
+  The MakerLisp CPU board has no on-board buttons that can be sensed by the
+  eZ80.
+
+Configurations
+==============
+
+Common Configuration Notes
+--------------------------
+
+  1. src/ and include/
+
+     These directories contain common logic for all MakerLisp
+     configurations.
+
+  2. Variations on the basic MakerLisp configuration are maintained
+     in subdirectories.  To configure any specific configuration, do the
+     following steps:
+
+       tools/configure.sh [OPTIONS] makerlisp/
+       make
+
+     Where  is the specific board configuration that you
+     wish to build.  Use 'tools/configure.sh -h' to see the possible
+     options.  Typical options are:
+
+       -l Configure for a Linux host
+       -c Configure for a Windows Cygwin host
+       -g Configure for a Windows MYS2 host
+
+     Use configure.bat instead of configure.sh if you are building in a
+     native Windows environment.
+
+     The available board-specific configurations are  summarized in the
+     following paragraphs.
+
+  3. This configuration uses the mconf-based configuration tool.  To
+     change this configurations using that tool, you should:
+
+     a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+        see additional README.txt files in the NuttX tools repository.
+
+     b. Execute 'make menuconfig' in nuttx/ in order to start the
+        reconfiguration process.
+
+Configuration Subdirectories
+----------------------------
+
+  nsh:
+
+    This configuration builds the NuttShell (NSH).  That code can be
+    found in examples/nsh.  For more information see:  examples/nsh/README.txt
+    and Documentation/NuttShell.html.
+
+    NOTES:
+
+    1. A serial console is provided on UART0.  This configuration may work
+       with or without the the VGA and Keyboard adapter boards.  For use
+       with a host terminal emulation without the accessory boards, it will
+       be necessary to connect either a TTL-to-RS232 or a TTL-to-USB Serial
+       adapter to CN1 pins 59 and 61.
+
+       The default baud setting is 57600N1.
+
+       To use the VGA display controller with stdout and stderr, you also
+       need to selection CONFIG_MAKERLISP_VGA=y in your configuration.  This
+       enables a required VGA initialization sequence.
+
+       TBD:  What is the UART configuration when used with the VGA and
+       Keyboard controllers?
diff --git a/configs/makerlisp/include/board.h b/configs/makerlisp/include/board.h
new file mode 100644
index 00000000000..a294d7505fa
--- /dev/null
+++ b/configs/makerlisp/include/board.h
@@ -0,0 +1,101 @@
+/****************************************************************************
+ * arch/makerlisp/include/board.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __CONFIGS_MAKERLISP_INCLUDE_BOARD_H
+#define __CONFIGS_MAKERLISP_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking */
+
+#define EZ80_SYS_CLK_FREQ           50000000
+
+/* LEDs */
+
+/* The D3 GREEN LED is driven by an eZ80 GPI/O pin.  However, it has some
+ * additional properties:
+ *
+ * 1. On input, it will be '1' if the I/O expansion board is present.
+ * 2. Setting it to an output of '0' will generate a system reset.
+ * 3. Setting it to an output of '1' will not only illuminate the LED
+ *    take the card out of reset and enable power to the SD card slot.
+ *
+ * As a consequence, the GREEN LED will not be illuminated if SD card
+ * support or SPI is disabled.  The only effect of CONFIG_ARCH_LEDS is that
+ * the GREEN LED will turned off in the event of a crash.
+ */
+
+#define LED_STARTED                 0
+#define LED_HEAPALLOCATE            0
+#define LED_IRQSENABLED             0
+#define LED_STACKCREATED            0
+#define LED_IDLE                    0
+#define LED_INIRQ                   0
+#define LED_ASSERTION               1
+#define LED_SIGNAL                  0
+#define LED_PANIC                   1
+
+/* Button definitions
+ * The MakerLisp CPU board has no on-board buttons that can be sensed by the
+ * eZ80.
+ */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif  /* __CONFIGS_MAKERLISP_INCLUDE_BOARD_H */
diff --git a/configs/makerlisp/nsh/.gitignore b/configs/makerlisp/nsh/.gitignore
new file mode 100644
index 00000000000..739b8373b85
--- /dev/null
+++ b/configs/makerlisp/nsh/.gitignore
@@ -0,0 +1,7 @@
+nsh.hex
+nsh.map
+nsh.lod
+nsh.wsp
+*.asm
+Debug
+
diff --git a/configs/makerlisp/nsh/README.txt b/configs/makerlisp/nsh/README.txt
new file mode 100644
index 00000000000..72e48fc2bed
--- /dev/null
+++ b/configs/makerlisp/nsh/README.txt
@@ -0,0 +1,5 @@
+README.txt
+^^^^^^^^^^
+
+nsh.zdsproj is a simple ZDS-II project that will allow you
+  to use the ZDS-II debugger.
diff --git a/configs/makerlisp/nsh/defconfig b/configs/makerlisp/nsh/defconfig
new file mode 100644
index 00000000000..cd83ba49612
--- /dev/null
+++ b/configs/makerlisp/nsh/defconfig
@@ -0,0 +1,46 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+# CONFIG_NSH_DISABLE_PS is not set
+CONFIG_ARCH="z80"
+CONFIG_ARCH_BOARD="makerlisp"
+CONFIG_ARCH_BOARD_MAKERLISP=y
+CONFIG_ARCH_CHIP_EZ80=y
+CONFIG_ARCH_CHIP_EZ80F91=y
+CONFIG_ARCH_LEDS=y
+CONFIG_ARCH_Z80=y
+CONFIG_BOARD_LOOPSPERMSEC=1250
+CONFIG_DISABLE_MQUEUE=y
+CONFIG_EZ80_UART0=y
+CONFIG_HOST_WINDOWS=y
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PREALLOC_WDOGS=8
+CONFIG_PTHREAD_STACK_DEFAULT=1024
+CONFIG_RAM_SIZE=65536
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_HPWORK=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_START_DAY=14
+CONFIG_START_MONTH=3
+CONFIG_START_YEAR=2009
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_UART0_BAUD=57600
+CONFIG_UART0_BITS=0
+CONFIG_UART0_RXBUFSIZE=192
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_UART0_TXBUFSIZE=64
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_WDOG_INTRESERVE=1
diff --git a/configs/makerlisp/nsh/nsh.zdsproj b/configs/makerlisp/nsh/nsh.zdsproj
new file mode 100644
index 00000000000..605c8a0fce3
--- /dev/null
+++ b/configs/makerlisp/nsh/nsh.zdsproj
@@ -0,0 +1,247 @@
+
+eZ80F91
+
+
+
+..\..\..\nuttx.hex
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
diff --git a/configs/makerlisp/scripts/Make.defs b/configs/makerlisp/scripts/Make.defs
new file mode 100644
index 00000000000..18f8e973f1e
--- /dev/null
+++ b/configs/makerlisp/scripts/Make.defs
@@ -0,0 +1,284 @@
+############################################################################
+# configs/makerlisp/nsh/Make.defs
+#
+#   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt 
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include $(TOPDIR)/.config
+include $(TOPDIR)/tools/Config.mk
+
+# These are the default directories where the ZDS-II toolchain is installed.
+# NOTE that short 8.3 path names are used in order to avoid spaces.  On my
+# machine I have:
+#
+# Versions 5.1.1 and 5.2.1
+#   C:\PROGRA~1\ = C:\Program Files\
+#   C:\PROGRA~2\ = C:\Program Files (x86)\
+#
+# Your PC may be configured differently.
+#
+# Version 5.3.0, the default install location is C:\ZiLOG
+
+ifeq ($(CONFIG_EZ80_ZDSII_V511),y)
+INSTALLROOT = C:/PROGRA~2/ZiLOG
+ZDSVERSION := 5.1.1
+else ifeq ($(CONFIG_EZ80_ZDSII_V521),y)
+INSTALLROOT = C:/PROGRA~2/ZiLOG
+ZDSVERSION := 5.2.1
+else ifeq ($(CONFIG_EZ80_ZDSII_V530),y)
+INSTALLROOT = C:/ZiLOG
+ZDSVERSION := 5.3.0
+endif
+
+ifeq ($(CONFIG_WINDOWS_NATIVE),y)
+  ZDSINSTALLDIR := $(INSTALLROOT)/ZDSII_eZ80Acclaim!_$(ZDSVERSION)
+  INSTALLDIR = ${shell echo $(ZDSINSTALLDIR)| sed -e "s/\//\\/g"}
+  ZDSBINDIR := $(INSTALLDIR)\bin
+  ZDSSTDINCDIR := $(INSTALLDIR)\include\std
+  ZDSZILOGINCDIR := $(INSTALLDIR)\include\zilog
+  ZDSSTDLIBDIR := $(INSTALLDIR)\lib\std
+  ZDSZILOGLIBDIR := $(INSTALLDIR)\lib\zilog
+
+  # CFLAGs
+
+  ARCHASMINCLUDES = -include:$(TOPDIR)\include;$(ZDSSTDINCDIR);$(ZDSZILOGINCDIR)
+  EARCHASMINCLUDES = -include:$(TOPDIR)\include;$(ZDSSTDINCDIR);$(ZDSZILOGINCDIR)
+  ARCHSTDINCLUDES = -stdinc:$(TOPDIR)\include;$(ZDSSTDINCDIR);$(ZDSZILOGINCDIR)
+  ARCHUSRINCLUDES = -usrinc:.
+else
+  WINTOOL := y
+  ZDSINSTALLDIR := $(INSTALLROOT)/ZDSII_eZ80Acclaim!_$(ZDSVERSION)
+  INSTALLDIR = ${shell cygpath -u "$(ZDSINSTALLDIR)"}
+  ZDSBINDIR := $(INSTALLDIR)/bin
+  ZDSSTDINCDIR := $(INSTALLDIR)/include/std
+  ZDSZILOGINCDIR := $(INSTALLDIR)/include/zilog
+  ZDSSTDLIBDIR := $(INSTALLDIR)/lib/std
+  ZDSZILOGLIBDIR := $(INSTALLDIR)/lib/zilog
+
+  # These are the same directories but with the directory separator
+  # character swapped as needed by the ZDS-II compiler
+
+  WTOPDIR := ${shell cygpath -w "$(TOPDIR)"}
+  WZDSSTDINCDIR := ${shell cygpath -w "$(ZDSSTDINCDIR)"}
+  WZDSZILOGINCDIR := ${shell cygpath -w "$(ZDSZILOGINCDIR)"}
+  WZDSSTDLIBDIR := ${shell cygpath -w "$(ZDSSTDLIBDIR)"}
+  WZDSZILOGLIBDIR := ${shell cygpath -w "$(ZDSZILOGLIBDIR)"}
+
+  # Escaped versions
+
+  ETOPDIR := ${shell echo "$(WTOPDIR)" | sed -e "s/ /%20/g"}
+  EZDSSTDINCDIR := ${shell echo "$(WZDSSTDINCDIR)" | sed -e "s/ /%20/g"}
+  EZDSZILOGINCDIR := ${shell echo "$(WZDSZILOGINCDIR)" | sed -e "s/ /%20/g"}
+
+  # CFLAGs
+
+  ARCHASMINCLUDES = -include:'$(WTOPDIR)\include;$(WZDSSTDINCDIR);$(WZDSZILOGINCDIR)'
+  EARCHASMINCLUDES = -include:'$(ETOPDIR)\include;$(EZDSSTDINCDIR);$(EZDSZILOGINCDIR)'
+  ARCHSTDINCLUDES = -stdinc:'$(WTOPDIR)\include;$(WZDSSTDINCDIR);$(WZDSZILOGINCDIR)'
+  ARCHUSRINCLUDES = -usrinc:'.'
+endif
+
+# Assembler definitions
+
+ifeq ($(CONFIG_ARCH_CHIP_EZ80F91),y)
+  ARCHCPU = eZ80F91
+  ARCHCPUDEF = _EZ80F91
+  ARCHFAMILY = _EZ80ACCLAIM!
+endif
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  ARCHASMOPTIMIZATION = -debug -NOsdiopt
+else
+  ARCHASMOPTIMIZATION = -nodebug -NOsdiopt
+endif
+
+ARCHASMCPUFLAGS = -cpu:$(ARCHCPU) -NOigcase
+ARCHASMLIST = -list -NOlistmac -name -pagelen:56 -pagewidth:80 -quiet
+ARCHASMWARNINGS = -warn
+ARCHASMDEFINES = -define:$(ARCHCPUDEF)=1 -define:$(ARCHFAMILYDEF)=1 -define:__ASSEMBLY__
+AFLAGS = $(ARCHASMCPUFLAGS) $(ARCHASMINCLUDES) $(ARCHASMLIST) $(ARCHASMWARNINGS) $(ARCHASMOPTIMIZATION)
+
+# Compiler definitions
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  ARCHOPTIMIZATION = -debug
+else
+  ARCHOPTIMIZATION = -nodebug
+endif
+
+ifeq ($(CONFIG_DEBUG_NOOPT),y)
+  ARCHOPTIMIZATION += -reduceopt
+else
+  ARCHOPTIMIZATION += -optsize
+endif
+
+ARCHCPUFLAGS = -chartype:S -promote -cpu:$(ARCHCPU) -NOgenprintf -NOmodsect \
+               -asmsw:" $(ARCHASMCPUFLAGS) $(EARCHASMINCLUDES) $(ARCHASMWARNINGS) $(ARCHASMOPTIMIZATION)"
+ARCHLIST = -keeplst -NOlist -NOlistinc -keepasm
+ARCHPICFLAGS =
+ARCHWARNINGS = -warn
+ARCHDEFINES = -define:$(ARCHCPUDEF) -define:$(ARCHFAMILYDEF)
+ARCHINCLUDES = $(ARCHSTDINCLUDES) $(ARCHUSRINCLUDES)
+CFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHLIST) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+
+CPPDEFINES = -D$(ARCHFAMILYDEF) -D$(ARCHCPUDEF) -D__ASSEMBLY__
+CPPINCLUDES = -I$(TOPDIR)$(DELIM)include
+CPPFLAGS = $(CPPDEFINES) $(CPPINCLUDES)
+
+# Librarian definitions
+
+ARFLAGS = -quiet -warn
+
+# Linker definitions
+
+LINKCMDTEMPLATE = $(TOPDIR)$(DELIM)configs$(DELIM)makerlisp$(DELIM)scripts$(DELIM)makerlisp.linkcmd
+
+# Tool names/paths.
+
+CROSSDEV =
+CC = $(ZDSBINDIR)$(DELIM)ez80cc.exe
+CPP = gcc -E
+LD = $(ZDSBINDIR)$(DELIM)ez80link.exe
+AS = $(ZDSBINDIR)$(DELIM)ez80asm.exe
+AR = $(ZDSBINDIR)$(DELIM)ez80lib.exe
+
+# File extensions
+
+ASMEXT = .asm
+OBJEXT = .obj
+LIBEXT = .lib
+EXEEXT = .lod
+HEXEXT = .hex
+
+# These are the macros that will be used in the NuttX make system
+# to compile and assembly source files and to insert the resulting
+# object files into an archive
+
+ifeq ($(CONFIG_WINDOWS_NATIVE),y)
+
+define PREPROCESS
+	@echo CPP: $1->$2
+	$(Q) $(CPP) $(CPPFLAGS) $1 -o $2
+endef
+
+define COMPILE
+	$(Q) $(CC) $(CFLAGS)  ${shell echo $1 | sed -e "s/\//\\/g"}
+endef
+
+define ASSEMBLE
+	$(Q) $(AS) $(AFLAGS) ${shell echo $1 | sed -e "s/\//\\/g"}
+endef
+
+define MOVEOBJ
+	$(call MOVEFILE, "$1.obj", "$2$(DELIM)$1.obj")
+	$(call MOVEFILE, "$1.lst", "$2$(DELIM)$1.lst")
+	$(call MOVEFILE, "$1.src", "$2$(DELIM)$1.src")
+endef
+
+define ARCHIVE
+	@echo AR: $2
+	$(Q) for %%G in ($(2)) do ( $(AR) $(ARFLAGS) $1=-+%%G )
+endef
+
+define CLEAN
+	$(Q) if exist *.obj (del /f /q *.obj)
+	$(Q) if exist *.src (del /f /q *.src)
+	$(Q) if exist *.lib (del /f /q *.lib)
+	$(Q) if exist *.hex (del /f /q *.hex)
+	$(Q) if exist *.lod (del /f /q *.lod)
+	$(Q) if exist *.lst (del /f /q *.lst)
+endef
+
+else
+
+define PREPROCESS
+	@echo "CPP: $1->$2"
+	$(Q) $(CPP) $(CPPFLAGS) $1 -o $2
+endef
+
+define COMPILE
+	$(Q) $(CC) $(CFLAGS) `cygpath -w "$1"`
+endef
+
+define ASSEMBLE
+	$(Q) $(AS) $(AFLAGS) `cygpath -w "$1"`
+endef
+
+define MOVEOBJ
+	$(call MOVEFILE, "$1.obj", "$2$(DELIM)$1.obj")
+	$(call MOVEFILE, "$1.lst", "$2$(DELIM)$1.lst")
+	$(call MOVEFILE, "$1.src", "$2$(DELIM)$1.src")
+endef
+
+define ARCHIVE
+	$(Q) for __obj in $(2) ; do \
+		echo "AR: $$__obj"; \
+		$(AR) $(ARFLAGS) $1=-+$$__obj || { echo "$(AR) $1=-+$$__obj FAILED!" ; exit 1 ; } \
+	done
+endef
+
+define CLEAN
+	$(Q) rm -f *.obj *.src *.lib *.hex *.lod *.lst
+endef
+endif
+
+# Windows native host tool definitions
+
+ifeq ($(CONFIG_WINDOWS_NATIVE),y)
+  HOSTCC = mingw32-gcc.exe
+  HOSTINCLUDES = -I.
+  HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+  HOSTLDFLAGS =
+  HOSTEXEEXT = .exe
+
+  # Windows-native host tools
+
+  #MKDEP = $(TOPDIR)\tools\mkdeps.exe --winnative
+  MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mknulldeps.sh
+else
+
+# Linux/Cygwin host tool definitions
+
+  HOSTCC = gcc
+  HOSTINCLUDES = -I.
+  HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+  HOSTLDFLAGS =
+
+  # This is the tool to use for dependencies (i.e., none)
+
+  MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mknulldeps.sh
+
+  # ZDS-II cannot follow Cygwin soft links, so we will have to use directory copies
+
+  DIRLINK = $(TOPDIR)$(DELIM)tools$(DELIM)copydir.sh
+  DIRUNLINK = $(TOPDIR)$(DELIM)tools$(DELIM)unlink.sh
+endif
diff --git a/configs/makerlisp/scripts/makerlisp.linkcmd b/configs/makerlisp/scripts/makerlisp.linkcmd
new file mode 100644
index 00000000000..3be276acbc0
--- /dev/null
+++ b/configs/makerlisp/scripts/makerlisp.linkcmd
@@ -0,0 +1,94 @@
+/****************************************************************************/
+/* configs/makerlisp/scripts/makerlisp.linkcmd                              */
+/*                                                                          */
+/*   Copyright (C) 2019 Gregory Nutt. All rights reserved.                  */
+/*   Author: Gregory Nutt                                  */
+/*                                                                          */
+/* Redistribution and use in source and binary forms, with or without       */
+/* modification, are permitted provided that the following conditions       */
+/* are met:                                                                 */
+/*                                                                          */
+/* 1. Redistributions of source code must retain the above copyright        */
+/*    notice, this list of conditions and the following disclaimer.         */
+/* 2. Redistributions in binary form must reproduce the above copyright     */
+/*    notice, this list of conditions and the following disclaimer in       */
+/*    the documentation and/or other materials provided with the            */
+/*    distribution.                                                         */
+/* 3. Neither the name NuttX nor the names of its contributors may be       */
+/*    used to endorse or promote products derived from this software        */
+/*    without specific prior written permission.                            */
+/*                                                                          */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS      */
+/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT        */
+/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        */
+/* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE           */
+/* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,      */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,     */
+/* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS    */
+/* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED       */
+/* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT              */
+/* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN        */
+/* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE          */
+/* POSSIBILITY OF SUCH DAMAGE.                                              */
+/*                                                                          */
+/****************************************************************************/
+
+-FORMAT=OMF695,INTEL32
+-map -maxhexlen=64 -quiet -NOwarnoverlap -xref -unresolved=fatal
+-sort ADDRESS=ascending -warn -NOdebug -NOigcase
+
+RANGE ROM $000000 : $03FFFF
+RANGE RAM $B80000 : $BFFFFF
+RANGE EXTIO $000000 : $00FFFF
+RANGE INTIO $000000 : $0000FF
+
+CHANGE STRSECT is ROM
+
+ORDER .RESET,.IVECTS,.STARTUP,CODE,DATA
+COPY DATA ROM
+
+DEFINE __low_romdata = copy base of DATA
+DEFINE __low_data = base of DATA
+DEFINE __len_data = length of DATA
+DEFINE __low_bss = base of BSS
+DEFINE __len_bss = length of BSS
+DEFINE __stack = highaddr of RAM + 1
+DEFINE __heaptop = highaddr of RAM
+DEFINE __heapbot = top of RAM + 1
+DEFINE __low_romcode = copy base of CODE
+DEFINE __low_code = base of CODE
+DEFINE __len_code = length of CODE
+DEFINE __copy_code_to_ram = 0
+DEFINE __crtl = 1
+DEFINE __CS0_LBR_INIT_PARAM = $10
+DEFINE __CS0_UBR_INIT_PARAM = $1f
+DEFINE __CS0_CTL_INIT_PARAM = $a8
+DEFINE __CS0_BMC_INIT_PARAM = $02
+DEFINE __CS1_LBR_INIT_PARAM = $c0
+DEFINE __CS1_UBR_INIT_PARAM = $c7
+DEFINE __CS1_CTL_INIT_PARAM = $28
+DEFINE __CS1_BMC_INIT_PARAM = $02
+DEFINE __CS2_LBR_INIT_PARAM = $80
+DEFINE __CS2_UBR_INIT_PARAM = $bf
+DEFINE __CS2_CTL_INIT_PARAM = $28
+DEFINE __CS2_BMC_INIT_PARAM = $81
+DEFINE __CS3_LBR_INIT_PARAM = $00
+DEFINE __CS3_UBR_INIT_PARAM = $00
+DEFINE __CS3_CTL_INIT_PARAM = $00
+DEFINE __CS3_BMC_INIT_PARAM = $02
+DEFINE __RAM_CTL_INIT_PARAM = $C0
+DEFINE __RAM_ADDR_U_INIT_PARAM = $B7
+DEFINE __FLASH_CTL_INIT_PARAM = $68
+DEFINE __FLASH_ADDR_U_INIT_PARAM = $00
+
+define _SYS_CLK_FREQ = 50000000
+
+define _OSC_FREQ = 50000000
+define _SYS_CLK_SRC = 0
+define _OSC_FREQ_MULT = 1
+define __PLL_CTL0_INIT_PARAM = $40
+
+define _zsl_g_clock_xdefine = 50000000
+
+/* arch/z80/src/Makefile.zdsii will append target, object and library paths below */
+
diff --git a/configs/makerlisp/src/.gitignore b/configs/makerlisp/src/.gitignore
new file mode 100644
index 00000000000..4b32ec6a3da
--- /dev/null
+++ b/configs/makerlisp/src/.gitignore
@@ -0,0 +1,10 @@
+/Make.dep
+/.depend
+/*.asm
+/*.obj
+/*.rel
+/*.lst
+/*.sym
+/*.adb
+/*.lib
+/*.src
diff --git a/configs/makerlisp/src/Makefile b/configs/makerlisp/src/Makefile
new file mode 100644
index 00000000000..f14a81b1413
--- /dev/null
+++ b/configs/makerlisp/src/Makefile
@@ -0,0 +1,55 @@
+############################################################################
+# configs/makerlisp/Makefile
+#
+#   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt 
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+
+ASRCS =
+CSRCS = ez80_lowinit.c ez80_bringup.c
+
+ifeq ($(CONFIG_LIB_BOARDCTL),y)
+CSRCS += ez80_appinit.c
+endif
+
+ifeq ($(CONFIG_ARCH_LEDS),y)
+CSRCS += ez80_leds.c
+endif
+
+ifeq ($(CONFIG_MMCSD_SPI),y)
+ifeq ($(CONFIG_EZ80_SPI),y)
+CSRCS += ez80_spimmcsd.c
+endif
+endif
+
+include $(TOPDIR)/configs/Board.mk
diff --git a/configs/makerlisp/src/ez80_appinit.c b/configs/makerlisp/src/ez80_appinit.c
new file mode 100644
index 00000000000..7740be760de
--- /dev/null
+++ b/configs/makerlisp/src/ez80_appinit.c
@@ -0,0 +1,94 @@
+/****************************************************************************
+ * config/makerlisp/src/ez80_appinit.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include "makerlisp.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef OK
+#  define OK 0
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ *   Perform application specific initialization.  This function is never
+ *   called directly from application code, but only indirectly via the
+ *   (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ *   arg - The boardctl() argument is passed to the board_app_initialize()
+ *         implementation without modification.  The argument has no
+ *         meaning to NuttX; the meaning of the argument is a contract
+ *         between the board-specific initialization logic and the
+ *         matching application logic.  The value cold be such things as a
+ *         mode enumeration value, a set of DIP switch switch settings, a
+ *         pointer to configuration data read from a file or serial FLASH,
+ *         or whatever you would like to do with it.  Every implementation
+ *         should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int board_app_initialize(uintptr_t arg)
+{
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+  /* Board initialization already performed by board_late_initialize() */
+
+  return OK;
+#else
+  /* Perform board-specific initialization */
+
+  return ez80_bringup();
+#endif
+}
diff --git a/include/nuttx/video/cursor.h b/configs/makerlisp/src/ez80_bringup.c
similarity index 63%
rename from include/nuttx/video/cursor.h
rename to configs/makerlisp/src/ez80_bringup.c
index 22359ea90ff..311418b6a97 100644
--- a/include/nuttx/video/cursor.h
+++ b/configs/makerlisp/src/ez80_bringup.c
@@ -1,8 +1,7 @@
 /****************************************************************************
- * include/nuttx/video/cursor.h
+ * config/makerlisp/src/ez80_bringup.c
  *
- *   Copyright (C) 2008-2011, 2013, 2016-2019 Gregory Nutt. All rights
- *     reserved.
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -34,9 +33,6 @@
  *
  ****************************************************************************/
 
-#ifndef __INCLUDE_NUTTX_VIDEO_CURSOR_H
-#define __INCLUDE_NUTTX_VIDEO_CURSOR_H
-
 /****************************************************************************
  * Included Files
  ****************************************************************************/
@@ -44,50 +40,51 @@
 #include 
 
 #include 
-#include 
+#include 
+#include 
 
 /****************************************************************************
- * Pre-processor definitions
+ * Public Functions
  ****************************************************************************/
 
 /****************************************************************************
- * Public Types
+ * Name: ez80_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y :
+ *     Called from board_late_initialize().
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
+ *     Called from the NSH library
+ *
  ****************************************************************************/
 
-/* If any dimension of the display exceeds 65,536 pixels, then the following
- * type will need to change.  This should match the types of fb_coord_t and
- * nxgl_coord_t.
- */
-
-typedef uint16_t cursor_coord_t;
-
-/* For cursor controllers that support custem cursor images, this structure
- * is used to provide the cursor image.
- */
-
-struct cursor_image_s
+int ez80_bringup(void)
 {
-  cursor_coord_t width;        /* Width of the cursor image in pixels */
-  cursor_coord_t height;       /* Height of the cursor image in pixels */
-  FAR const uint8_t *image;    /* Pointer to bitmap image data */
-};
+  int ret = OK;
 
-/* The following structure defines the cursor position */
+#ifdef CONFIG_FS_PROCFS
+  /* Mount the procfs file system */
 
-struct cursor_pos_s
-{
-  cursor_coord_t x;            /* X position in pixels */
-  cursor_coord_t y;            /* Y position in rows */
-};
+  ret = mount(NULL, "/proc", "procfs", 0, NULL);
+  if (ret < 0)
+    {
+      serr("ERROR: Failed to mount procfs at /proc: %d\n", ret);
+    }
+#endif
 
-/* If the hardware supports setting the cursor size, then this structure
- * is used to provide the cursor size.
- */
+#ifdef HAVE_MMCSD
+  /* Initialize SPI-based SD card slot */
 
-struct cursor_size_s
-{
-  cursor_coord_t h;            /* Height in rows */
-  cursor_coord_t w;            /* Width in pixels */
-};
+  ret = ez80_mmcsd_initialize(void);
+  if (ret < 0)
+    {
+      serr("ERROR: Failed to initialize SD card: %d\n", ret);
+    }
+#endif
 
-#endif /* __INCLUDE_NUTTX_VIDEO_CURSOR_H */
+  UNUSED(ret);
+  return ret;
+}
diff --git a/configs/makerlisp/src/ez80_leds.c b/configs/makerlisp/src/ez80_leds.c
new file mode 100644
index 00000000000..f19cdff18be
--- /dev/null
+++ b/configs/makerlisp/src/ez80_leds.c
@@ -0,0 +1,98 @@
+/****************************************************************************
+ * configs/makerlisp/src/ez80_leds.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The D3 GREEN LED is driven by an eZ80 GPI/O pin.  However, it has some
+ * additional properties:
+ *
+ * 1. On input, it will be '1' if the I/O expansion board is present.
+ * 2. Setting it to an output of '0' will generate a system reset.
+ * 3. Setting it to an output of '1' will not only illuminate the LED
+ *    take the card out of reset and enable power to the SD card slot.
+ *
+ * As a consequence, the GREEN LED will not be illuminated if SD card
+ * support or SPI is disabled.  The only effect of CONFIG_ARCH_LEDS is that
+ * the GREEN LED will turned off in the event of a crash.
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include 
+#include 
+
+#include "up_internal.h"
+#include "makerlisp.h"
+
+#ifdef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_autoled_initialize
+ ****************************************************************************/
+
+void board_autoled_initialize(void)
+{
+}
+
+/****************************************************************************
+ * Name: board_autoled_on
+ ****************************************************************************/
+
+void board_autoled_on(int led)
+{
+  if (led != 0)  /* LED_ASSERTION or LED_PANIC */
+    {
+      /* To be provided */
+    }
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
+
+void board_autoled_off(int led)
+{
+  /* Ignored */
+}
+
+#endif /* CONFIG_ARCH_LEDS */
diff --git a/configs/makerlisp/src/ez80_lowinit.c b/configs/makerlisp/src/ez80_lowinit.c
new file mode 100644
index 00000000000..63f1878905f
--- /dev/null
+++ b/configs/makerlisp/src/ez80_lowinit.c
@@ -0,0 +1,232 @@
+/****************************************************************************
+ * configs/makerlisp/src/ez80_lowinit.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Parts of this file are based on MakerLisp sample code by Luther Johnson
+ * which has a compatible MIT license
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include 
+#include 
+
+#include "chip.h"
+#include "up_internal.h"
+#include "makerlisp.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+bool g_ebpresent = false;  /* True:  I/O Expansion board is present */
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define VGA_MAX_DELAY 2000000
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ez80_vga_initialize
+ *
+ * Description:
+ *   If CONFIG_MAKERLISP_VGA is defined and the I/O controller is attached,
+ *   then initialize the VGA interface.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_MAKERLISP_VGA
+static void ez80_vga_initialize(void)
+{
+  /* I/O Expansion board attached? */
+
+  if (g_ebpresent)
+    {
+      bool vgapresent = false;
+      int delay;
+
+      /* Wait for VGA ready */
+
+      for (delay = 0; delay < VGA_MAX_DELAY; delay++)
+       {
+          if *(inp(EZ80_PB_DR) & EZ80_GPIOD1) != 0)
+            {
+              vgapresent = true;
+              break;
+            }
+        }
+
+      /* Is VGA ready (and, hence, present)? */
+
+      if (vgapresent)
+        {
+          /* Yes.. set newline mode, graphic attributes:
+           *
+           * \033 = ESCAPE character
+           * Assumption:  VGA is on the console UART.
+           */
+
+          up_puts("\033[20h\033[0m");
+
+          /* Clear, home cursor, beep */
+
+          up_puts("\033[2J\033[H\a");
+        }
+    }
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ez80_lowinit
+ *
+ * Description:
+ *   All eZ80 architectures must provide the following entry point.  This
+ *   entry point is called early in the initialization -- after basic CPU
+ *   configuration is complete but before any devices have been initialized.
+ *
+ ****************************************************************************/
+
+void ez80_lowinit(void)
+{
+  register uint8_t regval;
+
+  /* Port B pin 5 is set if the I/O expansion board is present */
+
+  regval = inp(EZ80_PB_DR);
+  g_ebpresent = (regval & EZ80_GPIOD5 != 0);
+
+  /* Set Port B pin 5 as output, assert /sysreset, SD card power off */
+
+  regval &= ~EZ80_GPIOD5;
+  outp(EZ80_PB_DR, regval);
+
+  regval  = inp(EZ80_PB_ALT1);
+  regval &= ~EZ80_GPIOD5;
+  outp(EZ80_PB_ALT1, regval);
+
+  regval  = inp(EZ80_PB_ALT2);
+  regval &= ~EZ80_GPIOD5;
+  outp(EZ80_PB_ALT2, regval);
+
+  regval  = inp(EZ80_PB_DDR);
+  regval &= ~EZ80_GPIOD5;
+  outp(EZ80_PB_DDR, regval);
+
+  /* Set port B pins 7 (MOSI), 6 (MISO), 3 (SCK), 2 (/SS) to SPI */
+
+  regval  = inp(EZ80_PB_ALT1);
+  regval &= ~(EZ80_GPIOD2 | EZ80_GPIOD3 | EZ80_GPIOD6 | EZ80_GPIOD7);
+  outp(EZ80_PB_ALT1, regval);
+
+  regval  = inp(EZ80_PB_ALT2);
+  regval &= ~(EZ80_GPIOD2 | EZ80_GPIOD3 | EZ80_GPIOD6 | EZ80_GPIOD7);
+  outp(EZ80_PB_ALT2, regval);
+
+  /* Set port B pin 4 as output, high - use for /CS */
+
+  regval  = inp(EZ80_PB_DR);
+  regval |= EZ80_GPIOD4;
+  outp(EZ80_PB_DR, regval);
+
+  regval  = inp(EZ80_PB_ALT1);
+  regval &= ~EZ80_GPIOD4;
+  outp(EZ80_PB_ALT1, regval);
+
+  regval  = inp(EZ80_PB_ALT2);
+  regval &= ~EZ80_GPIOD4;
+  outp(EZ80_PB_ALT2, regval);
+
+  regval  = inp(EZ80_PB_DDR);
+  regval &= ~EZ80_GPIOD4;
+  outp(EZ80_PB_DDR, regval);
+
+  /* Leave /sysreset asserted for a while */
+
+  up_udelay(150);
+
+  /* Take the system out of reset and and turn on SD card power */
+
+  regval  = inp(EZ80_PB_DR);
+  regval |= EZ80_GPIOD5;
+  outp(EZ80_PB_DR, regval);
+
+  /* Wait for the SD card to power up */
+
+  up_udelay(750);
+
+#ifdef CONFIG_MAKERLISP_VGA
+  /* Initialize the VGA interface.  We want to do this as early as possible
+   * in the boot-up sequence.  Debug output prior initializing VGA will be
+   * lost.
+   */
+
+  ez80_vga_initialize();
+#endif
+}
+
+/****************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ *   If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
+ *   initialization call will be performed in the boot-up sequence to a
+ *   function called board_late_initialize().  board_late_initialize() will be
+ *   called immediately after up_initialize() is called and just before the
+ *   initial application is started.  This additional initialization phase
+ *   may be used, for example, to initialize board-specific device drivers.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+  /* Perform board-specific initialization */
+
+  (void)ez80_bringup();
+}
+#endif
diff --git a/configs/makerlisp/src/ez80_spimmcsd.c b/configs/makerlisp/src/ez80_spimmcsd.c
new file mode 100644
index 00000000000..dff41eb84fe
--- /dev/null
+++ b/configs/makerlisp/src/ez80_spimmcsd.c
@@ -0,0 +1,121 @@
+/*****************************************************************************
+ * configs/makerlisp/src/ez80_spimmcsd.c
+ *
+ *   Copyright (C) 2019 Greg Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "chip.h"
+#include "ez80f91_spi.h"
+#include "makerlisp.h"
+
+#ifdef HAVE_MMCSD
+
+/*****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/* NOTE:  We are using a SDCard adapter/module without Card Detect pin!
+ * Then we don't need to Card Detect callback here.
+ */
+
+/*****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Name: ez80_spi1register
+ *
+ * Description:
+ *   Registers media change callback
+ *
+ ****************************************************************************/
+
+int ez80_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback,
+                      void *arg)
+{
+  spiinfo("INFO: Registering spi1 device\n");
+  return OK;
+}
+
+/*****************************************************************************
+ * Name: ez80_mmcsd_initialize
+ *
+ * Description:
+ *   Initialize SPI-based SD card.
+ *
+ ****************************************************************************/
+
+int ez80_mmcsd_initialize(void)
+{
+  struct spi_dev_s *spi;
+  int ret;
+
+  mcinfo("INFO: Initializing mmcsd card\n");
+
+  /* Get/initialize the SPI interface */
+
+  spi = ez80_spibus_initialize(1);
+  if (spi == NULL)
+    {
+      mcerr("ERROR: Failed to initialize SPI\n");
+      return -ENODEV;
+    }
+
+  /* Register the MMC/SD block driver for slot 0 with device minor number 0. */
+
+  ret = mmcsd_spislotinitialize(0, 0, spi);
+  if (ret < 0)
+    {
+      mcerr("ERROR: Failed to bind SPI to SD slot 0\n");
+      return ret;
+    }
+
+  mcinfo("INFO: mmcsd card has been initialized successfully\n");
+  return OK;
+}
+
+#endif /* HAVE_MMCSD */
diff --git a/configs/makerlisp/src/makerlisp.h b/configs/makerlisp/src/makerlisp.h
new file mode 100644
index 00000000000..5d0d504c447
--- /dev/null
+++ b/configs/makerlisp/src/makerlisp.h
@@ -0,0 +1,165 @@
+/****************************************************************************
+ * arch/makerlisp/src/makerlisp.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef _CONFIGS_MAKERLISP_SRC_MAKERLISP_H
+#define _CONFIGS_MAKERLISP_SRC_MAKERLISP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+# include 
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration */
+
+#define HAVE_MMCSD 1
+#if !defined(CONFIG_MMCSD_SPI) || !defined(CONFIG_EZ80_SPI)
+#  undef HAVE_MMCSD
+#endif
+
+/* Helpers for accessing memory mapped registers */
+
+#define ez80_getreg8(a)   (*(uint8_t*)(a))
+#define ez80_putreg8(v,a) (*(uint8_t*)(a) = (v))
+
+/* Memory map.  Board-specific extensions to the basic ez80f91 memory map
+ * (see arch/z80/src/ez80/ez80f91.h)
+ */
+                                   /* CS0: 0x000000 256Kb of on-chip flash */
+#define EZ80_OFFCHIPFLASH 0x400000 /* CS0: Off chip flash (Up to 4Mb-256Kb) */
+#define EZ80_LEDGPIOCNTRL 0x800000 /* CS2: (See below) */
+#define EZ80_PLTFMSRAM    0xb80000 /* CS2: Platform SRAM (512Kb) */
+#define EZ80_MODULESRAM   0xc00000 /* CS1: Module SRAM (up to 2Mb) */
+                                   /* 0xffc000 On-chip EMAC SRAM (8Kb) */
+                                   /* 0xffe000 On-chip SRAM (8Kb) */
+
+/* LED and port emulation memory register addresses */
+
+/* GPIO data bit definitions */
+
+#define EZ80_GPIOD0       (1 << 0)
+#define EZ80_GPIOD1       (1 << 1)
+#define EZ80_GPIOD2       (1 << 2)
+#define EZ80_GPIOD3       (1 << 3)
+#define EZ80_GPIOD4       (1 << 4)
+#define EZ80_GPIOD5       (1 << 5)
+#define EZ80_GPIOD6       (1 << 6)
+#define EZ80_GPIOD7       (1 << 7)
+
+/* Modem Signals:
+ *
+ * DCD:
+ *   The Data Carrier Detect (DCD) signal at D1 indicates that a good carrier
+ *   signal is being received from the remove mode.
+ * RX:
+ *   The RX signal at D2 indicates that data is received from the modem.
+ * DTR:
+ *   The Data Terminal Ready (DTR) signal at D3 informs the modem that the PC
+ *   is ready.
+ * TX:
+ *   The TX signal at D4 indicates that data is transmitted to the modem.
+ */
+
+ /* Push buttons:
+  *
+  * PB0   SW1 Bit 0 of GPIO Port B
+  * PB1   SW2 Bit 1 of GPIO Port B
+  * PB2   SW3 Bit 2 of GPIO Port B
+  * RESET SW4
+  */
+
+#define EZ80_PB0_IRQ EZ80_PORTB0_IRQ  /* Vector Oxa0 */
+#define EZ80_PB1_IRQ EZ80_PORTB1_IRQ  /* Vector Oxa4 */
+#define EZ80_PB2_IRQ EZ80_PORTB2_IRQ  /* Vector Oxa8 */
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+extern bool g_ebpresent;  /* True:  I/O Expansion board is present */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: ez80_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y :
+ *     Called from board_late_initialize().
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
+ *     Called from the NSH library
+ *
+ ****************************************************************************/
+
+int ez80_bringup(void);
+
+/*****************************************************************************
+ * Name: ez80_mmcsd_initialize
+ *
+ * Description:
+ *   Initialize SPI-based SD card.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_MMCSD
+int ez80_mmcsd_initialize(void);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif  /* _CONFIGS_MAKERLISP_SRC_MAKERLISP_H */
diff --git a/configs/maple/nsh/defconfig b/configs/maple/nsh/defconfig
index ddffe2294ce..c6dc2515af0 100644
--- a/configs/maple/nsh/defconfig
+++ b/configs/maple/nsh/defconfig
@@ -30,7 +30,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=5483
 CONFIG_BUILTIN=y
 CONFIG_DEFAULT_SMALL=y
-CONFIG_DISABLE_POLL=y
 CONFIG_LIB_RAND_ORDER=2
 CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
diff --git a/configs/maple/nx/defconfig b/configs/maple/nx/defconfig
index 76158d230d0..c33a039f06f 100644
--- a/configs/maple/nx/defconfig
+++ b/configs/maple/nx/defconfig
@@ -36,7 +36,6 @@ CONFIG_CDCACM_CONSOLE=y
 CONFIG_CDCACM_RXBUFSIZE=256
 CONFIG_CDCACM_TXBUFSIZE=256
 CONFIG_DEFAULT_SMALL=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NXHELLO=y
 CONFIG_EXAMPLES_NXHELLO_BPP=1
diff --git a/configs/maple/scripts/ld.script b/configs/maple/scripts/ld.script
index 84d5cccc494..036d44e1138 100644
--- a/configs/maple/scripts/ld.script
+++ b/configs/maple/scripts/ld.script
@@ -52,69 +52,73 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */
+        /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/maple/scripts/ld.script.dfu b/configs/maple/scripts/ld.script.dfu
index bb0de615ac8..47d2111d2d7 100644
--- a/configs/maple/scripts/ld.script.dfu
+++ b/configs/maple/scripts/ld.script.dfu
@@ -52,69 +52,73 @@ ENTRY(_stext)
 
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */
+        /* The STM32F103VCT6 has 48Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/maple/usbnsh/defconfig b/configs/maple/usbnsh/defconfig
index 3f4b5d94d7f..922fee34f92 100644
--- a/configs/maple/usbnsh/defconfig
+++ b/configs/maple/usbnsh/defconfig
@@ -35,7 +35,6 @@ CONFIG_CDCACM_CONSOLE=y
 CONFIG_CDCACM_RXBUFSIZE=256
 CONFIG_CDCACM_TXBUFSIZE=256
 CONFIG_DEFAULT_SMALL=y
-CONFIG_DISABLE_POLL=y
 CONFIG_I2C=y
 CONFIG_LIB_BOARDCTL=y
 CONFIG_LIB_RAND_ORDER=2
diff --git a/configs/max32660-evsys/nsh/defconfig b/configs/max32660-evsys/nsh/defconfig
index f76fa5aa0a1..e0ba2130364 100644
--- a/configs/max32660-evsys/nsh/defconfig
+++ b/configs/max32660-evsys/nsh/defconfig
@@ -19,7 +19,6 @@ CONFIG_ARMV7M_LAZYFPU=y
 CONFIG_ARMV7M_USEBASEPRI=y
 CONFIG_BOARD_LOOPSPERMSEC=8192
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_MAX326XX_UART1=y
diff --git a/configs/mbed/nsh/defconfig b/configs/mbed/nsh/defconfig
index f40b74a6d1c..b9a5de39557 100644
--- a/configs/mbed/nsh/defconfig
+++ b/configs/mbed/nsh/defconfig
@@ -21,7 +21,6 @@ CONFIG_ARCH_CHIP_LPC17XX=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=7982
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_FAT=y
 CONFIG_LPC17_SSP0=y
 CONFIG_LPC17_UART0=y
diff --git a/configs/mbed/scripts/ld.script b/configs/mbed/scripts/ld.script
index 82722f7c7a7..ddd3bc20cb3 100644
--- a/configs/mbed/scripts/ld.script
+++ b/configs/mbed/scripts/ld.script
@@ -51,66 +51,70 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {			/* BSS				*/
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
-					/* Stabs debugging sections.	*/
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        .bss : {                        /* BSS                          */
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
+                                        /* Stabs debugging sections.    */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/mcb1700/nsh/defconfig b/configs/mcb1700/nsh/defconfig
index efe071b0159..ebccbd12ef5 100644
--- a/configs/mcb1700/nsh/defconfig
+++ b/configs/mcb1700/nsh/defconfig
@@ -21,7 +21,6 @@ CONFIG_ARCH_CHIP_LPC17XX=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=7982
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_FAT=y
 CONFIG_LPC17_SSP0=y
 CONFIG_LPC17_UART0=y
diff --git a/configs/mcb1700/scripts/ld.script b/configs/mcb1700/scripts/ld.script
index 8bd2a32e385..4e43d9dda72 100644
--- a/configs/mcb1700/scripts/ld.script
+++ b/configs/mcb1700/scripts/ld.script
@@ -51,66 +51,70 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {			/* BSS				*/
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
-					/* Stabs debugging sections.	*/
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        .bss : {                        /* BSS                          */
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
+                                        /* Stabs debugging sections.    */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/mcu123-lpc214x/composite/defconfig b/configs/mcu123-lpc214x/composite/defconfig
index 6d2b2abbafe..9386422a044 100644
--- a/configs/mcu123-lpc214x/composite/defconfig
+++ b/configs/mcu123-lpc214x/composite/defconfig
@@ -27,7 +27,6 @@ CONFIG_COMPOSITE_PRODUCTSTR="Composite Device"
 CONFIG_COMPOSITE_SERIALSTR="12345"
 CONFIG_COMPOSITE_VENDORID=0x03eb
 CONFIG_COMPOSITE_VERSIONNO=0x0101
-CONFIG_DISABLE_POLL=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_INTELHEX_BINARY=y
 CONFIG_LIB_BOARDCTL=y
diff --git a/configs/mcu123-lpc214x/nsh/defconfig b/configs/mcu123-lpc214x/nsh/defconfig
index d4cd0ef6669..79ea01db997 100644
--- a/configs/mcu123-lpc214x/nsh/defconfig
+++ b/configs/mcu123-lpc214x/nsh/defconfig
@@ -16,7 +16,6 @@ CONFIG_ARCH_CHIP_LPC214X=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARM_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=3270
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/mcu123-lpc214x/scripts/ld.script b/configs/mcu123-lpc214x/scripts/ld.script
index bc025dfb7f4..7102110e75a 100644
--- a/configs/mcu123-lpc214x/scripts/ld.script
+++ b/configs/mcu123-lpc214x/scripts/ld.script
@@ -46,75 +46,79 @@
 
 MEMORY
 {
-	flash (rx) : ORIGIN = 0x00000000, LENGTH = 500K
-	sram  (rw) : ORIGIN = 0x40000000, LENGTH = 32K - 32
+        flash (rx) : ORIGIN = 0x00000000, LENGTH = 500K
+        sram  (rw) : ORIGIN = 0x40000000, LENGTH = 32K - 32
 }
 
 OUTPUT_ARCH(arm)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections.	*/
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections.    */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/mcu123-lpc214x/usbmsc/defconfig b/configs/mcu123-lpc214x/usbmsc/defconfig
index 95da1a36f46..c9a94c1076c 100644
--- a/configs/mcu123-lpc214x/usbmsc/defconfig
+++ b/configs/mcu123-lpc214x/usbmsc/defconfig
@@ -16,7 +16,6 @@ CONFIG_ARCH_INTERRUPTSTACK=1024
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARM_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=3270
-CONFIG_DISABLE_POLL=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_LIB_BOARDCTL=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/mcu123-lpc214x/usbserial/defconfig b/configs/mcu123-lpc214x/usbserial/defconfig
index 77f5a826d88..1926201c51f 100644
--- a/configs/mcu123-lpc214x/usbserial/defconfig
+++ b/configs/mcu123-lpc214x/usbserial/defconfig
@@ -15,7 +15,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARM_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=3270
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_USBSERIAL=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_LIB_BOARDCTL=y
diff --git a/configs/metro-m4/nsh/defconfig b/configs/metro-m4/nsh/defconfig
index 36f6d58b47a..f399b2b41d8 100644
--- a/configs/metro-m4/nsh/defconfig
+++ b/configs/metro-m4/nsh/defconfig
@@ -16,7 +16,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=7225
 CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/micropendous3/hello/defconfig b/configs/micropendous3/hello/defconfig
index 337647acc72..7d710e73f1a 100644
--- a/configs/micropendous3/hello/defconfig
+++ b/configs/micropendous3/hello/defconfig
@@ -19,9 +19,7 @@ CONFIG_DEFAULT_SMALL=y
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_IDLETHREAD_STACKSIZE=512
diff --git a/configs/mikroe-stm32f4/fulldemo/defconfig b/configs/mikroe-stm32f4/fulldemo/defconfig
index 08bf778e618..7b556de2127 100644
--- a/configs/mikroe-stm32f4/fulldemo/defconfig
+++ b/configs/mikroe-stm32f4/fulldemo/defconfig
@@ -34,7 +34,6 @@ CONFIG_CDCACM_TXBUFSIZE=256
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEV_LOOP=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_AUDIO=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NX_BPP=16
diff --git a/configs/mikroe-stm32f4/kernel/stm32_userspace.c b/configs/mikroe-stm32f4/kernel/stm32_userspace.c
index c7c89018ad7..2568bd1d9f4 100644
--- a/configs/mikroe-stm32f4/kernel/stm32_userspace.c
+++ b/configs/mikroe-stm32f4/kernel/stm32_userspace.c
@@ -114,9 +114,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/mikroe-stm32f4/kostest/defconfig b/configs/mikroe-stm32f4/kostest/defconfig
index d1e3e20a966..0e46c516ba5 100644
--- a/configs/mikroe-stm32f4/kostest/defconfig
+++ b/configs/mikroe-stm32f4/kostest/defconfig
@@ -27,7 +27,6 @@ CONFIG_CDCACM_TXBUFSIZE=256
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEV_LOOP=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_FAT=y
 CONFIG_FS_ROMFS=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/mikroe-stm32f4/nsh/defconfig b/configs/mikroe-stm32f4/nsh/defconfig
index 055f80c59ba..6399bda36b8 100644
--- a/configs/mikroe-stm32f4/nsh/defconfig
+++ b/configs/mikroe-stm32f4/nsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEV_LOOP=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_FAT=y
 CONFIG_FS_ROMFS=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/mikroe-stm32f4/nx/defconfig b/configs/mikroe-stm32f4/nx/defconfig
index bff43e15fdc..b73329aac68 100644
--- a/configs/mikroe-stm32f4/nx/defconfig
+++ b/configs/mikroe-stm32f4/nx/defconfig
@@ -23,7 +23,6 @@ CONFIG_ARCH_CHIP_STM32F407VG=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NX_BPP=16
 CONFIG_HAVE_CXX=y
diff --git a/configs/mikroe-stm32f4/nxlines/defconfig b/configs/mikroe-stm32f4/nxlines/defconfig
index bb1d478eb47..9a8040e26ea 100644
--- a/configs/mikroe-stm32f4/nxlines/defconfig
+++ b/configs/mikroe-stm32f4/nxlines/defconfig
@@ -25,7 +25,6 @@ CONFIG_ARCH_CHIP_STM32F407VG=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NXLINES=y
 CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0
 CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xFFE0
diff --git a/configs/mikroe-stm32f4/nxtext/defconfig b/configs/mikroe-stm32f4/nxtext/defconfig
index 1b405b144f8..8d55499df65 100644
--- a/configs/mikroe-stm32f4/nxtext/defconfig
+++ b/configs/mikroe-stm32f4/nxtext/defconfig
@@ -24,7 +24,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NXTEXT=y
 CONFIG_EXAMPLES_NXTEXT_BPP=16
 CONFIG_HAVE_CXX=y
diff --git a/configs/mikroe-stm32f4/scripts/ld.script b/configs/mikroe-stm32f4/scripts/ld.script
index 33df010b9a5..0b4bd074570 100644
--- a/configs/mikroe-stm32f4/scripts/ld.script
+++ b/configs/mikroe-stm32f4/scripts/ld.script
@@ -57,67 +57,71 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/mikroe-stm32f4/scripts/memory.ld b/configs/mikroe-stm32f4/scripts/memory.ld
index 3a7480d8714..f81320551a5 100644
--- a/configs/mikroe-stm32f4/scripts/memory.ld
+++ b/configs/mikroe-stm32f4/scripts/memory.ld
@@ -54,7 +54,7 @@
  * Alignment of the user space FLASH partition is also a critical factor:
  * The user space FLASH partition will be spanned with a single region of
  * size 2**n bytes.  The alignment of the user-space region must be the same.
- * As a consequence, as the user-space increases in size, the alignmment
+ * As a consequence, as the user-space increases in size, the alignment
  * requirement also increases.
  *
  * This alignment requirement means that the largest user space FLASH region
diff --git a/configs/mikroe-stm32f4/src/stm32_extmem.c b/configs/mikroe-stm32f4/src/stm32_extmem.c
index 40996822e94..3c9337fe847 100644
--- a/configs/mikroe-stm32f4/src/stm32_extmem.c
+++ b/configs/mikroe-stm32f4/src/stm32_extmem.c
@@ -48,7 +48,6 @@
 #include "chip.h"
 #include "up_arch.h"
 
-#include "stm32_fsmc.h"
 #include "stm32_gpio.h"
 #include "stm32.h"
 #include "mikroe-stm32f4.h"
@@ -148,40 +147,3 @@ void stm32_extmemdata(int ndata)
   stm32_extmemgpios(g_dataconfig, ndata);
 }
 
-/************************************************************************************
- * Name: stm32_enablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-void stm32_enablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Enable AHB clocking to the FSMC */
-
-  regval  = getreg32( STM32_RCC_AHB3ENR);
-  regval |= RCC_AHB3ENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHB3ENR);
-}
-
-/************************************************************************************
- * Name: stm32_disablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-void stm32_disablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Disable AHB clocking to the FSMC */
-
-  regval  = getreg32(STM32_RCC_AHB3ENR);
-  regval &= ~RCC_AHB3ENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHB3ENR);
-}
diff --git a/configs/mikroe-stm32f4/src/stm32_touchscreen.c b/configs/mikroe-stm32f4/src/stm32_touchscreen.c
index f76100a9a86..d52ab0a6e24 100644
--- a/configs/mikroe-stm32f4/src/stm32_touchscreen.c
+++ b/configs/mikroe-stm32f4/src/stm32_touchscreen.c
@@ -231,9 +231,7 @@ struct tc_dev_s
    * retained in the f_priv field of the 'struct file'.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_TOUCHSCREEN_NPOLLWAITERS];
-#endif
 };
 
 /************************************************************************************
@@ -260,9 +258,7 @@ static int tc_open(FAR struct file *filep);
 static int tc_close(FAR struct file *filep);
 static ssize_t tc_read(FAR struct file *filep, FAR char *buffer, size_t len);
 static int tc_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int tc_poll(FAR struct file *filep, struct pollfd *fds, bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -277,10 +273,8 @@ static const struct file_operations tc_fops =
   tc_read,    /* read */
   0,          /* write */
   0,          /* seek */
-  tc_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , tc_poll   /* poll */
-#endif
+  tc_ioctl,   /* ioctl */
+  tc_poll     /* poll */
 };
 
 /* If only a single touchscreen device is supported, then the driver state
@@ -581,9 +575,7 @@ static inline bool tc_valid_sample(uint16_t sample)
 
 static void tc_notify(FAR struct tc_dev_s *priv)
 {
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   /* If no threads have the driver open, then just dump the state */
 
@@ -616,7 +608,6 @@ static void tc_notify(FAR struct tc_dev_s *priv)
    * then some make end up blocking after all.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   for (i = 0; i < CONFIG_TOUCHSCREEN_NPOLLWAITERS; i++)
     {
       struct pollfd *fds = priv->fds[i];
@@ -627,7 +618,6 @@ static void tc_notify(FAR struct tc_dev_s *priv)
           nxsem_post(fds->sem);
         }
     }
-#endif
 }
 
 /****************************************************************************
@@ -1379,7 +1369,6 @@ static int tc_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: tc_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int tc_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup)
 {
@@ -1467,7 +1456,6 @@ errout:
   nxsem_post(&priv->devsem);
   return ret;
 }
-#endif
 
 /************************************************************************************
  * Public Functions
diff --git a/configs/mikroe-stm32f4/usbnsh/defconfig b/configs/mikroe-stm32f4/usbnsh/defconfig
index 12cbbcae08e..b6b921d7c1b 100644
--- a/configs/mikroe-stm32f4/usbnsh/defconfig
+++ b/configs/mikroe-stm32f4/usbnsh/defconfig
@@ -26,7 +26,6 @@ CONFIG_CDCACM_RXBUFSIZE=256
 CONFIG_CDCACM_TXBUFSIZE=256
 CONFIG_DEV_LOOP=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_FAT=y
 CONFIG_FS_ROMFS=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/mirtoo/nsh/defconfig b/configs/mirtoo/nsh/defconfig
index a4f69f917b6..b50b1a6e857 100644
--- a/configs/mirtoo/nsh/defconfig
+++ b/configs/mirtoo/nsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=8079
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/mirtoo/nxffs/defconfig b/configs/mirtoo/nxffs/defconfig
index cd1e5cdd990..d8541a3482c 100644
--- a/configs/mirtoo/nxffs/defconfig
+++ b/configs/mirtoo/nxffs/defconfig
@@ -22,7 +22,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=8079
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_FS_NXFFS=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/misoc/hello/defconfig b/configs/misoc/hello/defconfig
index 5828174060f..d3b4a7df95c 100644
--- a/configs/misoc/hello/defconfig
+++ b/configs/misoc/hello/defconfig
@@ -9,7 +9,7 @@
 # CONFIG_STANDARD_SERIAL is not set
 CONFIG_ARCH="misoc"
 CONFIG_ARCH_BOARD="misoc"
-CONFIG_ARCH_BOARD_MISOC=y
+CONFIG_ARCH_BOARD_MISOC_QEMU=y
 CONFIG_ARCH_CHIP_LM32=y
 CONFIG_ARCH_MISOC=y
 CONFIG_ARCH_STACKDUMP=y
@@ -42,6 +42,10 @@ CONFIG_MISOC_UART1=y
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x08080808
+CONFIG_NETINIT_DRIPADDR=0xc0a80101
+CONFIG_NETINIT_IPADDR=0xc0a80132
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_DISCOVER=y
 CONFIG_NETUTILS_TELNETD=y
@@ -54,7 +58,6 @@ CONFIG_NET_GUARDSIZE=648
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=40
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCP_CONNS=40
 CONFIG_NET_TCP_WRITE_BUFFERS=y
@@ -63,10 +66,6 @@ CONFIG_NET_UDP_CHECKSUMS=y
 CONFIG_NFILE_DESCRIPTORS=4
 CONFIG_NFILE_STREAMS=4
 CONFIG_NSH_BUILTIN_APPS=y
-CONFIG_NSH_DRIPADDR=0xc0a80101
-CONFIG_NSH_IPADDR=0xc0a80132
-CONFIG_NSH_NETINIT_THREAD=y
-CONFIG_NSH_NOMAC=y
 CONFIG_PREALLOC_TIMERS=4
 CONFIG_PREALLOC_WDOGS=8
 CONFIG_RAM_SIZE=67108864
diff --git a/configs/misoc/nsh/defconfig b/configs/misoc/nsh/defconfig
index b8ac18aa6da..87b994a6e15 100644
--- a/configs/misoc/nsh/defconfig
+++ b/configs/misoc/nsh/defconfig
@@ -45,7 +45,6 @@ CONFIG_DEBUG_WARN=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 CONFIG_DISABLE_PTHREAD=y
diff --git a/configs/moteino-mega/hello/defconfig b/configs/moteino-mega/hello/defconfig
index e9a7cf0cbd3..579d1dbca9f 100644
--- a/configs/moteino-mega/hello/defconfig
+++ b/configs/moteino-mega/hello/defconfig
@@ -18,9 +18,7 @@ CONFIG_DEFAULT_SMALL=y
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_HOST_MACOS=y
 CONFIG_IDLETHREAD_STACKSIZE=512
diff --git a/configs/moteino-mega/nsh/defconfig b/configs/moteino-mega/nsh/defconfig
index 3bf0acfd1df..7253a883965 100644
--- a/configs/moteino-mega/nsh/defconfig
+++ b/configs/moteino-mega/nsh/defconfig
@@ -21,7 +21,6 @@ CONFIG_BOARD_LOOPSPERMSEC=888
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_HOST_MACOS=y
 CONFIG_IDLETHREAD_STACKSIZE=512
diff --git a/configs/ne64badge/ostest/defconfig b/configs/ne64badge/ostest/defconfig
index 8dcbd39718e..8bfdacb9ced 100644
--- a/configs/ne64badge/ostest/defconfig
+++ b/configs/ne64badge/ostest/defconfig
@@ -17,7 +17,6 @@ CONFIG_BOARD_LOOPSPERMSEC=5483
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_HCS12_NONBANKED=y
diff --git a/configs/nr5m100-nexys4/nsh/defconfig b/configs/nr5m100-nexys4/nsh/defconfig
index 880fcec3489..ab091f01194 100644
--- a/configs/nr5m100-nexys4/nsh/defconfig
+++ b/configs/nr5m100-nexys4/nsh/defconfig
@@ -21,7 +21,6 @@ CONFIG_BUILTIN=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_FS_WRITABLE=y
diff --git a/configs/nr5m100-nexys4/scripts/ld.script b/configs/nr5m100-nexys4/scripts/ld.script
index b2f1036ae2e..4aeb414c10b 100644
--- a/configs/nr5m100-nexys4/scripts/ld.script
+++ b/configs/nr5m100-nexys4/scripts/ld.script
@@ -225,10 +225,12 @@ SECTIONS
   /*--------------------------------------------------------------------*/
 
   /* Start of initialized data segment */
+
   . = ALIGN(16);
    _fdata = .;
 
   /* data: Writable data */
+
   _sdata = .;
   .data :
   {
@@ -242,16 +244,18 @@ SECTIONS
   _edata = .;
 
   /* Have _gp point to middle of sdata/sbss to maximize displacement range */
+
   . = ALIGN(16);
   _gp = . + 0x7FF0;
 
   /* Writable small data segment */
+
   .sdata :
   {
     *(.sdata)
     *(.sdata.*)
     *(.srodata.*)
-  . = ALIGN(16);
+    . = ALIGN(16);
     *(.gnu.linkonce.s.*)
   }
 
@@ -260,10 +264,12 @@ SECTIONS
   /*--------------------------------------------------------------------*/
 
   /* Start of uninitialized data segment */
+
   . = ALIGN(8);
   _fbss = .;
 
   /* Writable uninitialized small data segment */
+
   .sbss :
   {
     *(.sbss)
@@ -272,6 +278,7 @@ SECTIONS
   }
 
   /* bss: Uninitialized writeable data section */
+
   . = .;
   _bss_start = .;
   .bss :
@@ -285,21 +292,22 @@ SECTIONS
   _ebss = .;
 
   /* End of uninitialized data segment (used by syscalls.c for heap) */
+
   . = ALIGN(16);
   PROVIDE( end = . );
   _end = ALIGN(16);
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/ntosd-dm320/nettest/defconfig b/configs/ntosd-dm320/nettest/defconfig
index a36147f39d3..54a25e2ead4 100644
--- a/configs/ntosd-dm320/nettest/defconfig
+++ b/configs/ntosd-dm320/nettest/defconfig
@@ -15,7 +15,6 @@ CONFIG_BOOT_RUNFROMSDRAM=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_DM9X_BASE=0xd0000300
 CONFIG_DM9X_IRQ=27
diff --git a/configs/ntosd-dm320/udp/defconfig b/configs/ntosd-dm320/udp/defconfig
index a2223f756eb..81fdc522df1 100644
--- a/configs/ntosd-dm320/udp/defconfig
+++ b/configs/ntosd-dm320/udp/defconfig
@@ -16,7 +16,6 @@ CONFIG_BOOT_RUNFROMSDRAM=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_DM9X_BASE=0xd0000300
 CONFIG_DM9X_IRQ=27
diff --git a/configs/ntosd-dm320/webserver/defconfig b/configs/ntosd-dm320/webserver/defconfig
index 03f06576ccb..411cf460830 100644
--- a/configs/ntosd-dm320/webserver/defconfig
+++ b/configs/ntosd-dm320/webserver/defconfig
@@ -16,7 +16,6 @@ CONFIG_BOOT_RUNFROMSDRAM=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DM9X_BASE=0xd0000300
 CONFIG_DM9X_IRQ=27
 CONFIG_EXAMPLES_WEBSERVER=y
diff --git a/configs/nucleo-144/README.txt b/configs/nucleo-144/README.txt
index fdccb3bc2de..ab492526fcb 100644
--- a/configs/nucleo-144/README.txt
+++ b/configs/nucleo-144/README.txt
@@ -71,7 +71,7 @@ Common Board Features:
                   provide a ST-Link for programming, debug similar to the
                   OpenOcd FTDI function - USB to JTAG front-end.
 
-  Expansion I/F:  ST Zio and Extended Ardino and Morpho Headers
+  Expansion I/F:  ST Zio and Extended Arduino and Morpho Headers
 
 Nucleo F746ZG
 =============
@@ -94,10 +94,10 @@ NUCLEO-F746ZG Features:
   ADC:            3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in
                   triple interleaved mode
   DMA:            2 X 16-stream DMA controllers with FIFOs and burst support
-  Timers:         Up to 18 timers: up to thirteen 16-bit (1x 16-bit lowpower),
+  Timers:         Up to 18 timers: up to thirteen 16-bit (1x 16-bit low power),
                   two 32-bit timers, 2x watchdogs, SysTick
   GPIO:           114 I/O ports with interrupt capability
-  LCD:            LCD-TFT Controllerwith (DMA2D), Parallel interface
+  LCD:            LCD-TFT Controller with (DMA2D), Parallel interface
   I2C:            4 × I2C interfaces (SMBus/PMBus)
   U[S]ARTs:       4 USARTs, 4 UARTs (27 Mbit/s, ISO7816 interface, LIN, IrDA,
                   modem control)
@@ -142,10 +142,10 @@ NUCLEO-F767ZI Features:
   ADC:            3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in
                   triple interleaved mode
   DMA:            2 X 16-stream DMA controllers with FIFOs and burst support
-  Timers:         Up to 18 timers: up to thirteen 16-bit (1x 16-bit lowpower),
+  Timers:         Up to 18 timers: up to thirteen 16-bit (1x 16-bit low power),
                   two 32-bit timers, 2x watchdogs, SysTick
   GPIO:           114 I/O ports with interrupt capability
-  LCD:            LCD-TFT Controllerwith (DMA2D), Parallel interface
+  LCD:            LCD-TFT Controller with (DMA2D), Parallel interface
   I2C:            4 × I2C interfaces (SMBus/PMBus)
   U[S]ARTs:       4 USARTs, 4 UARTs (27 Mbit/s, ISO7816 interface, LIN, IrDA,
                   modem control)
@@ -166,9 +166,11 @@ NUCLEO-F767ZI Features:
   TRG:            True random number generator
   RTC             subsecond accuracy, hardware calendar
 
-As of this writting the NUCLEO-F767ZI is not available on developer.mbed.org
-However, See https://developer.mbed.org/platforms/ST-Nucleo-F746ZG  for additional
-useful information.
+For pinout and details Check NUCLEO-F767ZI page on developer.mbed.org:
+https://os.mbed.com/platforms/ST-Nucleo-F767ZI/
+
+Also https://developer.mbed.org/platforms/ST-Nucleo-F746ZG 
+may contain some related useful information.
 
 Development Environment
 =======================
@@ -347,7 +349,7 @@ Serial Consoles
   USART6 (CONFIG_NUCLEO_CONSOLE_ARDUINO)
   ------
                 STM32F7
-    ARDUIONO FUNCTION  GPIO
+    ARDUINO FUNCTION  GPIO
     -- ----- --------- -----
     DO RX    USART6_RX PG9
     D1 TX    USART6_TX PG14
@@ -436,15 +438,15 @@ Serial Consoles
 
 SPI
 ---
-  Since this board is so generic, having a quick way to vet the SPI
+  Since this board is so generic, having a quick way to set the SPI
   configuration seams in order. So the board provides a quick test
-  that can be selected vi CONFIG_NUCLEO_SPI_TEST that will initalise
+  that can be selected vi CONFIG_NUCLEO_SPI_TEST that will initialize
   the selected buses (SPI1-SPI3) and send some text on the bus at
-  application initalization time board_app_initialize.
+  application initialization time board_app_initialize.
 
 SDIO
 ----
-  To test the SD performace one can use a SparkFun microSD Sniffer
+  To test the SD performance one can use a SparkFun microSD Sniffer
   from https://www.sparkfun.com/products/9419 or similar board
   and connect it as follows:
 
diff --git a/configs/nucleo-144/f722-nsh/defconfig b/configs/nucleo-144/f722-nsh/defconfig
index 9cdf6866e45..d9030035a7b 100644
--- a/configs/nucleo-144/f722-nsh/defconfig
+++ b/configs/nucleo-144/f722-nsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_ARMV7M_ICACHE=y
 CONFIG_BOARD_LOOPSPERMSEC=43103
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/nucleo-144/f746-evalos/defconfig b/configs/nucleo-144/f746-evalos/defconfig
index cf66b547e63..9522f317875 100644
--- a/configs/nucleo-144/f746-evalos/defconfig
+++ b/configs/nucleo-144/f746-evalos/defconfig
@@ -25,7 +25,6 @@ CONFIG_ARMV7M_ICACHE=y
 CONFIG_BOARD_LOOPSPERMSEC=43103
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLOXX=y
 CONFIG_EXAMPLES_LEDS=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/nucleo-144/f746-nsh/defconfig b/configs/nucleo-144/f746-nsh/defconfig
index b9e39ca3c0d..e5d06439a0f 100644
--- a/configs/nucleo-144/f746-nsh/defconfig
+++ b/configs/nucleo-144/f746-nsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_ARMV7M_ICACHE=y
 CONFIG_BOARD_LOOPSPERMSEC=43103
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/nucleo-144/f767-evalos/defconfig b/configs/nucleo-144/f767-evalos/defconfig
index e7dddb6ffdd..fd7a2e15e0c 100644
--- a/configs/nucleo-144/f767-evalos/defconfig
+++ b/configs/nucleo-144/f767-evalos/defconfig
@@ -25,7 +25,6 @@ CONFIG_ARMV7M_ICACHE=y
 CONFIG_BOARD_LOOPSPERMSEC=43103
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLOXX=y
 CONFIG_EXAMPLES_LEDS=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/nucleo-144/f767-netnsh/defconfig b/configs/nucleo-144/f767-netnsh/defconfig
index c2c02a48e01..72f51d849d9 100644
--- a/configs/nucleo-144/f767-netnsh/defconfig
+++ b/configs/nucleo-144/f767-netnsh/defconfig
@@ -42,7 +42,6 @@ CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_IGMP=y
 CONFIG_NET_LOOPBACK=y
 CONFIG_NET_ROUTE=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_SOLINGER=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
@@ -50,6 +49,7 @@ CONFIG_NET_UDP=y
 CONFIG_NET_UDP_CHECKSUMS=y
 CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
diff --git a/configs/nucleo-144/f767-nsh/defconfig b/configs/nucleo-144/f767-nsh/defconfig
index e9181b27a7c..6aa5f5875a3 100644
--- a/configs/nucleo-144/f767-nsh/defconfig
+++ b/configs/nucleo-144/f767-nsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_ARMV7M_ICACHE=y
 CONFIG_BOARD_LOOPSPERMSEC=43103
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/nucleo-144/include/board.h b/configs/nucleo-144/include/board.h
index dd1491568b0..564af8f4a90 100644
--- a/configs/nucleo-144/include/board.h
+++ b/configs/nucleo-144/include/board.h
@@ -61,6 +61,7 @@
  ************************************************************************************/
 
 /* Clocking *************************************************************************/
+
 /* The Nucleo-144  board provides the following clock sources:
  *
  *   MCO: 8 MHz from MCO output of ST-LINK is used as input clock
@@ -143,8 +144,6 @@
 #define STM32_RCC_DCKCFGR1_DFSDM1SRC   0
 #define STM32_RCC_DCKCFGR1_ADFSDM1SRC  0
 
-
-
 /* Configure factors for  PLLI2S clock */
 
 #define CONFIG_STM32F7_PLLI2S 1
@@ -253,7 +252,9 @@
 #  define GPIO_SDMMC2_D2 GPIO_SDMMC2_D2_1
 #  define GPIO_SDMMC2_D3 GPIO_SDMMC2_D3_1
 #endif
+
 /* DMA Channl/Stream Selections *****************************************************/
+
 /* Stream selections are arbitrary for now but might become important in the future
  * if we set aside more DMA channels/streams.
  *
@@ -287,6 +288,7 @@
 #define BOARD_FLASH_WAITSTATES 7
 
 /* LED definitions ******************************************************************/
+
 /* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a Blue
  * LED and LD3 a Red LED, that can be controlled by software. The following
  * definitions assume the default Solder Bridges are installed.
@@ -338,6 +340,7 @@
  */
 
 /* Button definitions ***************************************************************/
+
 /* The STM32F7 Discovery supports one button:  Pushbutton B1, labeled "User", is
  * connected to GPIO PI11.  A high value will be sensed when the button is depressed.
  */
@@ -348,6 +351,13 @@
 
 /* Alternate function pin selections ************************************************/
 
+/* TIM */
+
+#define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_1
+#define GPIO_TIM2_CH1OUT GPIO_TIM2_CH1OUT_1
+#define GPIO_TIM3_CH1OUT GPIO_TIM3_CH1OUT_1
+#define GPIO_TIM4_CH1OUT GPIO_TIM4_CH1OUT_1
+
 #if defined(CONFIG_NUCLEO_CONSOLE_ARDUINO)
 /* USART6:
  *
@@ -369,7 +379,7 @@
 
 /* USART3:
  * Use  USART3 and the USB virtual COM port
-*/
+ */
 
 #if defined(CONFIG_NUCLEO_CONSOLE_VIRTUAL)
  # define GPIO_USART3_RX GPIO_USART3_RX_3
@@ -391,18 +401,18 @@
  *   -------  --------- -----
  */
 
- # define GPIO_UART4_RX GPIO_UART4_RX_1
- # define GPIO_UART4_TX GPIO_UART4_TX_1
+#  define GPIO_UART4_RX GPIO_UART4_RX_1
+#  define GPIO_UART4_TX GPIO_UART4_TX_1
 
 /* USART3 seems to be forced selected by the Nucleo-F746ZG kconfig - bug */
 
- # define GPIO_USART3_RX GPIO_USART3_RX_1
- # define GPIO_USART3_TX GPIO_USART3_TX_1
+#  define GPIO_USART3_RX GPIO_USART3_RX_1
+#  define GPIO_USART3_TX GPIO_USART3_TX_1
 
 /* USART6 seems to be forced selected by the Nucleo-F722E kconfig - bug */
 
- # define GPIO_USART6_RX GPIO_USART6_RX_2
- # define GPIO_USART6_TX GPIO_USART6_TX_2
+#  define GPIO_USART6_RX GPIO_USART6_RX_2
+#  define GPIO_USART6_TX GPIO_USART6_TX_2
 
 #endif
 
@@ -416,6 +426,7 @@
  */
 
 /* DMA channels *************************************************************/
+
 /* ADC */
 
 #define ADC1_DMA_CHAN DMAMAP_ADC1_1
@@ -500,3 +511,4 @@
 #define GPIO_ETH_RMII_TXD1    GPIO_ETH_RMII_TXD1_1
 
 #endif  /* __CONFIG_NUCLEO_144_INCLUDE_BOARD_H */
+
diff --git a/configs/nucleo-144/src/Makefile b/configs/nucleo-144/src/Makefile
index 52068fbe354..d31876d272c 100644
--- a/configs/nucleo-144/src/Makefile
+++ b/configs/nucleo-144/src/Makefile
@@ -61,6 +61,10 @@ ifeq ($(CONFIG_ADC),y)
 CSRCS += stm32_adc.c
 endif
 
+ifeq ($(CONFIG_PWM),y)
+CSRCS += stm32_pwm.c
+endif
+
 ifeq ($(CONFIG_MMCSD),y)
 CSRCS += stm32_sdio.c
 endif
diff --git a/configs/nucleo-144/src/nucleo-144.h b/configs/nucleo-144/src/nucleo-144.h
index 5939dd09543..e09c81a101e 100644
--- a/configs/nucleo-144/src/nucleo-144.h
+++ b/configs/nucleo-144/src/nucleo-144.h
@@ -255,6 +255,18 @@ int stm32_sdio_initialize(void);
 void stm32_usbinitialize(void);
 #endif
 
+/************************************************************************************
+ * Name: stm32_pwm_setup
+ *
+ * Description:
+ *   Initialize PWM and register the PWM device.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_PWM
+int stm32_pwm_setup(void);
+#endif
+
 /************************************************************************************
  * Name: stm32_adc_setup
  *
diff --git a/configs/nucleo-144/src/stm32_appinitialize.c b/configs/nucleo-144/src/stm32_appinitialize.c
index 1b3c3150ac3..4b9aa18f3f9 100644
--- a/configs/nucleo-144/src/stm32_appinitialize.c
+++ b/configs/nucleo-144/src/stm32_appinitialize.c
@@ -149,6 +149,16 @@ int board_app_initialize(uintptr_t arg)
     }
 #endif
 
+#if defined(CONFIG_PWM)
+  /* Initialize PWM and register the PWM device */
+
+  ret = stm32_pwm_setup();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret);
+    }
+#endif
+
   UNUSED(ret);
   return OK;
 }
diff --git a/configs/nucleo-144/src/stm32_pwm.c b/configs/nucleo-144/src/stm32_pwm.c
new file mode 100644
index 00000000000..f3b6a4a9e02
--- /dev/null
+++ b/configs/nucleo-144/src/stm32_pwm.c
@@ -0,0 +1,162 @@
+/************************************************************************************
+ * configs/nucleo-144/src/stm32_pwm.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *   Author: Philippe Coval 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "chip.h"
+#include "up_arch.h"
+#include "stm32_pwm.h"
+#include "nucleo-144.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+#define HAVE_PWM 1
+#ifndef CONFIG_PWM
+#  undef HAVE_PWM
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_pwm_setup
+ *
+ * Description:
+ *   Initialize PWM and register the PWM device.
+ *
+ ************************************************************************************/
+
+int stm32_pwm_setup(void)
+{
+#ifdef HAVE_PWM
+  static bool initialized = false;
+  struct pwm_lowerhalf_s *pwm;
+  int ret;
+
+  /* Have we already initialized? */
+
+  if (!initialized)
+    {
+      /* Call stm32_pwminitialize() to get an instance of the PWM interface */
+
+#if defined(CONFIG_STM32F7_TIM1_PWM)
+      pwm = stm32_pwminitialize(1);
+      if (!pwm)
+        {
+          aerr("ERROR: Failed to get the STM32F7 PWM lower half\n");
+          return -ENODEV;
+        }
+
+      ret = pwm_register("/dev/pwm0", pwm);
+      if (ret < 0)
+        {
+          aerr("ERROR: pwm_register failed: %d\n", ret);
+          return ret;
+        }
+#endif
+
+#if defined(CONFIG_STM32F7_TIM2_PWM)
+      pwm = stm32_pwminitialize(2);
+      if (!pwm)
+        {
+          aerr("ERROR: Failed to get the STM32F7 PWM lower half\n");
+          return -ENODEV;
+        }
+
+      ret = pwm_register("/dev/pwm1", pwm);
+      if (ret < 0)
+        {
+          aerr("ERROR: pwm_register failed: %d\n", ret);
+          return ret;
+        }
+#endif
+
+#if defined(CONFIG_STM32F7_TIM3_PWM)
+      pwm = stm32_pwminitialize(3);
+      if (!pwm)
+        {
+          aerr("ERROR: Failed to get the STM32F7 PWM lower half\n");
+          return -ENODEV;
+        }
+
+      ret = pwm_register("/dev/pwm2", pwm);
+      if (ret < 0)
+        {
+          aerr("ERROR: pwm_register failed: %d\n", ret);
+          return ret;
+        }
+#endif
+
+#if defined(CONFIG_STM32F7_TIM4_PWM)
+      pwm = stm32_pwminitialize(4);
+      if (!pwm)
+        {
+          aerr("ERROR: Failed to get the STM32F7 PWM lower half\n");
+          return -ENODEV;
+        }
+
+      ret = pwm_register("/dev/pwm3", pwm);
+      if (ret < 0)
+        {
+          aerr("ERROR: pwm_register failed: %d\n", ret);
+          return ret;
+        }
+#endif
+      /* Now we are initialized */
+
+      initialized = true;
+    }
+
+  return OK;
+#else
+  return -ENODEV;
+#endif
+}
diff --git a/configs/nucleo-f072rb/include/board.h b/configs/nucleo-f072rb/include/board.h
index 873e0cce0b0..8a363981649 100644
--- a/configs/nucleo-f072rb/include/board.h
+++ b/configs/nucleo-f072rb/include/board.h
@@ -113,7 +113,7 @@
 
 #define STM32_CFGR_PLLSRC        RCC_CFGR_PLLSRC_HSId2       /* Source is HSI/2 */
 #define STM32_PLLSRC_FREQUENCY   (STM32_HSI_FREQUENCY/2)     /* 8MHz / 2 = 4MHz */
-#ifdef CONFIG_STM32F0L0_USB
+#ifdef CONFIG_STM32F0L0G0_USB
 #  undef  STM32_CFGR2_PREDIV                                 /* Not used with source HSI/2 */
 #  define STM32_CFGR_PLLMUL      RCC_CFGR_PLLMUL_CLKx12      /* PLLMUL = 12 */
 #  define STM32_PLL_FREQUENCY    (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
@@ -129,7 +129,7 @@
 
 #define STM32_SYSCLK_SW          RCC_CFGR_SW_PLL     /* Use the PLL as the SYSCLK */
 #define STM32_SYSCLK_SWS         RCC_CFGR_SWS_PLL
-#ifdef CONFIG_STM32F0L0_USB
+#ifdef CONFIG_STM32F0L0G0_USB
 #  define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
 #else
 #  define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
diff --git a/configs/nucleo-f072rb/nsh/defconfig b/configs/nucleo-f072rb/nsh/defconfig
index d054284a47a..3cdb7e50633 100644
--- a/configs/nucleo-f072rb/nsh/defconfig
+++ b/configs/nucleo-f072rb/nsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_BOARD_LOOPSPERMSEC=2796
 CONFIG_BUILTIN=y
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_MAX_TASKS=8
 CONFIG_MAX_WDOGPARMS=2
@@ -55,8 +54,8 @@ CONFIG_START_DAY=19
 CONFIG_START_MONTH=5
 CONFIG_START_YEAR=2013
 CONFIG_STDIO_DISABLE_BUFFERING=y
-CONFIG_STM32F0L0_PWR=y
-CONFIG_STM32F0L0_USART2=y
+CONFIG_STM32F0L0G0_PWR=y
+CONFIG_STM32F0L0G0_USART2=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_TASK_NAME_SIZE=0
 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
diff --git a/configs/nucleo-f072rb/src/nucleo-f072rb.h b/configs/nucleo-f072rb/src/nucleo-f072rb.h
index 03eae5d48a6..7197480355a 100644
--- a/configs/nucleo-f072rb/src/nucleo-f072rb.h
+++ b/configs/nucleo-f072rb/src/nucleo-f072rb.h
@@ -55,14 +55,14 @@
 /* How many SPI modules does this chip support? */
 
 #if STM32_NSPI < 1
-#  undef CONFIG_STM32F0L0_SPI1
-#  undef CONFIG_STM32F0L0_SPI2
-#  undef CONFIG_STM32F0L0_SPI3
+#  undef CONFIG_STM32F0L0G0_SPI1
+#  undef CONFIG_STM32F0L0G0_SPI2
+#  undef CONFIG_STM32F0L0G0_SPI3
 #elif STM32_NSPI < 2
-#  undef CONFIG_STM32F0L0_SPI2
-#  undef CONFIG_STM32F0L0_SPI3
+#  undef CONFIG_STM32F0L0G0_SPI2
+#  undef CONFIG_STM32F0L0G0_SPI3
 #elif STM32_NSPI < 3
-#  undef CONFIG_STM32F0L0_SPI3
+#  undef CONFIG_STM32F0L0G0_SPI3
 #endif
 
 /* Nucleo-F072RB GPIOs ******************************************************/
diff --git a/configs/nucleo-f072rb/src/stm32_bringup.c b/configs/nucleo-f072rb/src/stm32_bringup.c
index bfaa991e0a1..e3d4f24670c 100644
--- a/configs/nucleo-f072rb/src/stm32_bringup.c
+++ b/configs/nucleo-f072rb/src/stm32_bringup.c
@@ -53,7 +53,7 @@
  ****************************************************************************/
 
 #undef HAVE_I2C_DRIVER
-#if defined(CONFIG_STM32F0L0_I2C1) && defined(CONFIG_I2C_DRIVER)
+#if defined(CONFIG_STM32F0L0G0_I2C1) && defined(CONFIG_I2C_DRIVER)
 #  define HAVE_I2C_DRIVER 1
 #endif
 
diff --git a/configs/nucleo-f091rc/include/board.h b/configs/nucleo-f091rc/include/board.h
index 02fea162297..2cf25a579f5 100644
--- a/configs/nucleo-f091rc/include/board.h
+++ b/configs/nucleo-f091rc/include/board.h
@@ -113,7 +113,7 @@
 
 #define STM32_CFGR_PLLSRC        RCC_CFGR_PLLSRC_HSId2       /* Source is HSI/2 */
 #define STM32_PLLSRC_FREQUENCY   (STM32_HSI_FREQUENCY/2)     /* 8MHz / 2 = 4MHz */
-#ifdef CONFIG_STM32F0L0_USB
+#ifdef CONFIG_STM32F0L0G0_USB
 #  undef  STM32_CFGR2_PREDIV                                 /* Not used with source HSI/2 */
 #  define STM32_CFGR_PLLMUL      RCC_CFGR_PLLMUL_CLKx12      /* PLLMUL = 12 */
 #  define STM32_PLL_FREQUENCY    (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
@@ -129,7 +129,7 @@
 
 #define STM32_SYSCLK_SW          RCC_CFGR_SW_PLL     /* Use the PLL as the SYSCLK */
 #define STM32_SYSCLK_SWS         RCC_CFGR_SWS_PLL
-#ifdef CONFIG_STM32F0L0_USB
+#ifdef CONFIG_STM32F0L0G0_USB
 #  define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
 #else
 #  define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
diff --git a/configs/nucleo-f091rc/nsh/defconfig b/configs/nucleo-f091rc/nsh/defconfig
index 8e2ab98d4f8..c168d81cacd 100644
--- a/configs/nucleo-f091rc/nsh/defconfig
+++ b/configs/nucleo-f091rc/nsh/defconfig
@@ -24,7 +24,6 @@ CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_FS_PROCFS=y
 CONFIG_MAX_TASKS=8
@@ -58,8 +57,8 @@ CONFIG_START_DAY=19
 CONFIG_START_MONTH=5
 CONFIG_START_YEAR=2013
 CONFIG_STDIO_DISABLE_BUFFERING=y
-CONFIG_STM32F0L0_PWR=y
-CONFIG_STM32F0L0_USART2=y
+CONFIG_STM32F0L0G0_PWR=y
+CONFIG_STM32F0L0G0_USART2=y
 CONFIG_TASK_NAME_SIZE=0
 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
 CONFIG_USART2_SERIAL_CONSOLE=y
diff --git a/configs/nucleo-f091rc/src/Makefile b/configs/nucleo-f091rc/src/Makefile
index 31f84b485a1..0028d08be68 100644
--- a/configs/nucleo-f091rc/src/Makefile
+++ b/configs/nucleo-f091rc/src/Makefile
@@ -49,7 +49,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
 CSRCS += stm32_buttons.c
 endif
 
-ifeq ($(CONFIG_STM32F0L0_SPI),y)
+ifeq ($(CONFIG_STM32F0L0G0_SPI),y)
 CSRCS += stm32_spi.c
 endif
 
diff --git a/configs/nucleo-f091rc/src/nucleo-f091rc.h b/configs/nucleo-f091rc/src/nucleo-f091rc.h
index ad7279f4c3b..30418e4271b 100644
--- a/configs/nucleo-f091rc/src/nucleo-f091rc.h
+++ b/configs/nucleo-f091rc/src/nucleo-f091rc.h
@@ -55,14 +55,14 @@
 /* How many SPI modules does this chip support? */
 
 #if STM32_NSPI < 1
-#  undef CONFIG_STM32F0L0_SPI1
-#  undef CONFIG_STM32F0L0_SPI2
-#  undef CONFIG_STM32F0L0_SPI3
+#  undef CONFIG_STM32F0L0G0_SPI1
+#  undef CONFIG_STM32F0L0G0_SPI2
+#  undef CONFIG_STM32F0L0G0_SPI3
 #elif STM32_NSPI < 2
-#  undef CONFIG_STM32F0L0_SPI2
-#  undef CONFIG_STM32F0L0_SPI3
+#  undef CONFIG_STM32F0L0G0_SPI2
+#  undef CONFIG_STM32F0L0G0_SPI3
 #elif STM32_NSPI < 3
-#  undef CONFIG_STM32F0L0_SPI3
+#  undef CONFIG_STM32F0L0G0_SPI3
 #endif
 
 /* Nucleo-F091RC GPIOs ******************************************************/
@@ -139,7 +139,7 @@ int stm32_bringup(void);
  *
  ****************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI
+#ifdef CONFIG_STM32F0L0G0_SPI
 void stm32_spidev_initialize(void);
 #endif
 
diff --git a/configs/nucleo-f091rc/src/stm32_boot.c b/configs/nucleo-f091rc/src/stm32_boot.c
index 80f4deee82f..d54e17d57a2 100644
--- a/configs/nucleo-f091rc/src/stm32_boot.c
+++ b/configs/nucleo-f091rc/src/stm32_boot.c
@@ -70,7 +70,7 @@ void stm32_boardinitialize(void)
   board_autoled_initialize();
 #endif
 
-#ifdef CONFIG_STM32F0L0_SPI
+#ifdef CONFIG_STM32F0L0G0_SPI
   /* Configure SPI chip selects */
 
   stm32_spidev_initialize();
diff --git a/configs/nucleo-f091rc/src/stm32_spi.c b/configs/nucleo-f091rc/src/stm32_spi.c
index cbfac40aa27..fcd965ef0dd 100644
--- a/configs/nucleo-f091rc/src/stm32_spi.c
+++ b/configs/nucleo-f091rc/src/stm32_spi.c
@@ -54,7 +54,7 @@
 #include "nucleo-f091rc.h"
 #include 
 
-#ifdef CONFIG_STM32F0L0_SPI
+#ifdef CONFIG_STM32F0L0G0_SPI
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -92,7 +92,7 @@ void stm32_spidev_initialize(void)
    *       architecture.
    */
 
-#ifdef CONFIG_STM32F0L0_SPI1
+#ifdef CONFIG_STM32F0L0G0_SPI1
 
 #  ifdef CONFIG_LPWAN_SX127X
   /* Configure the SPI-based SX127X chip select GPIO */
@@ -103,7 +103,7 @@ void stm32_spidev_initialize(void)
   stm32_gpiowrite(GPIO_SX127X_CS, true);
 #  endif
 
-#endif  /*  CONFIG_STM32F0L0_SPI1 */
+#endif  /*  CONFIG_STM32F0L0G0_SPI1 */
 }
 
 /****************************************************************************
@@ -132,7 +132,7 @@ void stm32_spidev_initialize(void)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI1
+#ifdef CONFIG_STM32F0L0G0_SPI1
 void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
 {
   spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
@@ -178,9 +178,9 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
 
   return status;
 }
-#endif  /* CONFIG_STM32F0L0_SPI1 */
+#endif  /* CONFIG_STM32F0L0G0_SPI1 */
 
-#ifdef CONFIG_STM32F0L0_SPI2
+#ifdef CONFIG_STM32F0L0G0_SPI2
 void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid,
                       bool selected)
 {
@@ -191,6 +191,6 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid)
 {
   return 0;
 }
-#endif  /* CONFIG_STM32F0L0_SPI2 */
+#endif  /* CONFIG_STM32F0L0G0_SPI2 */
 
 #endif
diff --git a/configs/nucleo-f091rc/sx127x/defconfig b/configs/nucleo-f091rc/sx127x/defconfig
index 53b5ba6eba9..832ceae063a 100644
--- a/configs/nucleo-f091rc/sx127x/defconfig
+++ b/configs/nucleo-f091rc/sx127x/defconfig
@@ -20,7 +20,6 @@ CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 CONFIG_DRIVERS_LPWAN=y
@@ -60,9 +59,9 @@ CONFIG_START_DAY=19
 CONFIG_START_MONTH=5
 CONFIG_START_YEAR=2013
 CONFIG_STDIO_DISABLE_BUFFERING=y
-CONFIG_STM32F0L0_PWR=y
-CONFIG_STM32F0L0_SPI1=y
-CONFIG_STM32F0L0_USART2=y
+CONFIG_STM32F0L0G0_PWR=y
+CONFIG_STM32F0L0G0_SPI1=y
+CONFIG_STM32F0L0G0_USART2=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_TASK_NAME_SIZE=0
 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
diff --git a/configs/nucleo-f103rb/scripts/ld.script b/configs/nucleo-f103rb/scripts/ld.script
index c9119edbc08..77a50d820ca 100644
--- a/configs/nucleo-f103rb/scripts/ld.script
+++ b/configs/nucleo-f103rb/scripts/ld.script
@@ -52,73 +52,77 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The RAM vector table (if present) should lie at the beginning of SRAM */
+        /* The RAM vector table (if present) should lie at the beginning of SRAM */
 
-	.ram_vectors : {
-		*(.ram_vectors)
-	} > sram
+        .ram_vectors : {
+                *(.ram_vectors)
+        } > sram
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/nucleo-f207zg/adc/defconfig b/configs/nucleo-f207zg/adc/defconfig
index e714ddfe6bb..d4758836eeb 100644
--- a/configs/nucleo-f207zg/adc/defconfig
+++ b/configs/nucleo-f207zg/adc/defconfig
@@ -18,7 +18,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=6522
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_ADC=y
 CONFIG_EXAMPLES_ADC_GROUPSIZE=3
 CONFIG_IDLETHREAD_STACKSIZE=2048
diff --git a/configs/nucleo-f207zg/nsh/defconfig b/configs/nucleo-f207zg/nsh/defconfig
index 3ccf79effb4..2f8f1a76c15 100644
--- a/configs/nucleo-f207zg/nsh/defconfig
+++ b/configs/nucleo-f207zg/nsh/defconfig
@@ -15,7 +15,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=6522
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f207zg/pwm/defconfig b/configs/nucleo-f207zg/pwm/defconfig
index b353af6bb10..70ad14900cc 100644
--- a/configs/nucleo-f207zg/pwm/defconfig
+++ b/configs/nucleo-f207zg/pwm/defconfig
@@ -15,7 +15,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=6522
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_PWM=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f207zg/scripts/ld.script b/configs/nucleo-f207zg/scripts/ld.script
index 92af9e1e38f..089988311a5 100644
--- a/configs/nucleo-f207zg/scripts/ld.script
+++ b/configs/nucleo-f207zg/scripts/ld.script
@@ -55,67 +55,71 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/nucleo-f302r8/highpri/defconfig b/configs/nucleo-f302r8/highpri/defconfig
index 044cdf4b1c4..86c31b6e9db 100644
--- a/configs/nucleo-f302r8/highpri/defconfig
+++ b/configs/nucleo-f302r8/highpri/defconfig
@@ -21,7 +21,6 @@ CONFIG_BUILTIN=y
 CONFIG_BUILTIN_PROXY_STACKSIZE=512
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_FDCLONE_STDIO=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f302r8/nsh/defconfig b/configs/nucleo-f302r8/nsh/defconfig
index d97ed3d1611..d6c8af4aa20 100644
--- a/configs/nucleo-f302r8/nsh/defconfig
+++ b/configs/nucleo-f302r8/nsh/defconfig
@@ -24,10 +24,8 @@ CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_FDCLONE_STDIO=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f302r8/scripts/ld.script b/configs/nucleo-f302r8/scripts/ld.script
index 76a9f63e6b2..f1084c121b0 100644
--- a/configs/nucleo-f302r8/scripts/ld.script
+++ b/configs/nucleo-f302r8/scripts/ld.script
@@ -52,73 +52,77 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The RAM vector table (if present) should lie at the beginning of SRAM */
+        /* The RAM vector table (if present) should lie at the beginning of SRAM */
 
-	.ram_vectors : {
-		*(.ram_vectors)
-	} > sram
+        .ram_vectors : {
+                *(.ram_vectors)
+        } > sram
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/nucleo-f302r8/src/stm32_highpri.c b/configs/nucleo-f302r8/src/stm32_highpri.c
index 93fe9c859d8..8ea02f9a957 100644
--- a/configs/nucleo-f302r8/src/stm32_highpri.c
+++ b/configs/nucleo-f302r8/src/stm32_highpri.c
@@ -405,9 +405,9 @@ int highpri_main(int argc, char *argv[])
 
   PWM_CCR_UPDATE(pwm1, 1, 0x0f00);
 
-  /* Enable TIM1 CHAN1 */
+  /* Enable TIM1 OUT1 */
 
-  PWM_OUTPUTS_ENABLE(pwm1, STM32_CHAN1, true);
+  PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true);
 #else
 #  error T1CC1 only supported for now
 #endif
diff --git a/configs/nucleo-f303re/adc/defconfig b/configs/nucleo-f303re/adc/defconfig
index 78d60019120..5d3d5a58b47 100644
--- a/configs/nucleo-f303re/adc/defconfig
+++ b/configs/nucleo-f303re/adc/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_CHIP_STM32F303RE=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=6522
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_ADC=y
 CONFIG_EXAMPLES_ADC_GROUPSIZE=3
 CONFIG_EXAMPLES_ADC_SWTRIG=y
diff --git a/configs/nucleo-f303re/can/defconfig b/configs/nucleo-f303re/can/defconfig
index 0092a1a18dd..d9b8ab9ef27 100644
--- a/configs/nucleo-f303re/can/defconfig
+++ b/configs/nucleo-f303re/can/defconfig
@@ -16,7 +16,6 @@ CONFIG_ARCH_CHIP_STM32=y
 CONFIG_ARCH_CHIP_STM32F303RE=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=6522
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_CAN=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f303re/hello/defconfig b/configs/nucleo-f303re/hello/defconfig
index 5e4103903c9..aa1bd5c0da9 100644
--- a/configs/nucleo-f303re/hello/defconfig
+++ b/configs/nucleo-f303re/hello/defconfig
@@ -15,7 +15,6 @@ CONFIG_ARCH_CHIP_STM32F303RE=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=6522
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f303re/nxlines/defconfig b/configs/nucleo-f303re/nxlines/defconfig
index e8ef9851108..915d55fac96 100644
--- a/configs/nucleo-f303re/nxlines/defconfig
+++ b/configs/nucleo-f303re/nxlines/defconfig
@@ -19,7 +19,6 @@ CONFIG_ARCH_CHIP_STM32F303RE=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=6522
 CONFIG_CAN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NXLINES=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f303re/pwm/defconfig b/configs/nucleo-f303re/pwm/defconfig
index 9d1156156e3..4919a2749e7 100644
--- a/configs/nucleo-f303re/pwm/defconfig
+++ b/configs/nucleo-f303re/pwm/defconfig
@@ -19,7 +19,6 @@ CONFIG_ARCH_CHIP_STM32F303RE=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=6522
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_PWM=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f303re/scripts/ld.script b/configs/nucleo-f303re/scripts/ld.script
index 0176c0d1ade..ba3152136a6 100644
--- a/configs/nucleo-f303re/scripts/ld.script
+++ b/configs/nucleo-f303re/scripts/ld.script
@@ -54,67 +54,71 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/nucleo-f303re/serialrx/defconfig b/configs/nucleo-f303re/serialrx/defconfig
index cfcb6ed6fe8..40280d41336 100644
--- a/configs/nucleo-f303re/serialrx/defconfig
+++ b/configs/nucleo-f303re/serialrx/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_CHIP_STM32=y
 CONFIG_ARCH_CHIP_STM32F303RE=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=6522
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_SERIALRX=y
 CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
diff --git a/configs/nucleo-f303ze/adc/defconfig b/configs/nucleo-f303ze/adc/defconfig
index ec0938b2d2a..6de30250bd1 100644
--- a/configs/nucleo-f303ze/adc/defconfig
+++ b/configs/nucleo-f303ze/adc/defconfig
@@ -19,7 +19,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=6522
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_ADC=y
 CONFIG_EXAMPLES_ADC_GROUPSIZE=3
 CONFIG_EXAMPLES_ADC_SWTRIG=y
diff --git a/configs/nucleo-f303ze/include/board.h b/configs/nucleo-f303ze/include/board.h
index a6bcc5f9baa..9ecfa8d26dc 100644
--- a/configs/nucleo-f303ze/include/board.h
+++ b/configs/nucleo-f303ze/include/board.h
@@ -199,6 +199,17 @@
 #define GPIO_USART3_RX     GPIO_USART3_RX_3  /* PD9 */
 #define GPIO_USART3_TX     GPIO_USART3_TX_3  /* PD8 */
 
+/* I2C1 Use Nucleo I2C1 pins */
+
+#define GPIO_I2C1_SCL GPIO_I2C1_SCL_3 /* PB8 - D15 */
+#define GPIO_I2C1_SDA GPIO_I2C1_SDA_3 /* PB9 - D14 */
+
+/* I2C2 Use Nucleo I2C2 pins */
+
+#define GPIO_I2C2_SCL  GPIO_I2C2_SCL_2  /* PF1 - D69 */
+#define GPIO_I2C2_SDA  GPIO_I2C2_SDA_2  /* PF0 - D68 */
+#define GPIO_I2C2_SMBA GPIO_I2C2_SMBA_2 /* PF2 - D70 */
+
 /* DMA **********************************************************************/
 
 #define ADC1_DMA_CHAN DMACHAN_ADC1
diff --git a/configs/nucleo-f303ze/nsh/defconfig b/configs/nucleo-f303ze/nsh/defconfig
index fa5be0ebb87..bc800aa885a 100644
--- a/configs/nucleo-f303ze/nsh/defconfig
+++ b/configs/nucleo-f303ze/nsh/defconfig
@@ -16,7 +16,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=6522
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f303ze/nxlines_oled/defconfig b/configs/nucleo-f303ze/nxlines_oled/defconfig
new file mode 100644
index 00000000000..fce455db806
--- /dev/null
+++ b/configs/nucleo-f303ze/nxlines_oled/defconfig
@@ -0,0 +1,60 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_FPU is not set
+# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set
+# CONFIG_NX_DISABLE_1BPP is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="nucleo-f303ze"
+CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CHIP_STM32=y
+CONFIG_ARCH_CHIP_STM32F303ZE=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=6522
+CONFIG_BUILTIN=y
+CONFIG_EXAMPLES_NXLINES=y
+CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=1
+CONFIG_EXAMPLES_NXLINES_BPP=1
+CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xff
+CONFIG_EXAMPLES_NXLINES_LINEWIDTH=1
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LCD=y
+CONFIG_LCD_MAXCONTRAST=255
+CONFIG_LCD_SH1106_OLED_132=y
+CONFIG_LCD_SSD1306_I2C=y
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_MM_REGIONS=2
+CONFIG_MQ_MAXMSGSIZE=64
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NX=y
+CONFIG_NXFONT_MONO5X8=y
+CONFIG_NX_BLOCKING=y
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PREALLOC_WDOGS=8
+CONFIG_RAM_SIZE=65536
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_START_DAY=27
+CONFIG_START_YEAR=2013
+CONFIG_STM32_I2C1=y
+CONFIG_STM32_JTAG_SW_ENABLE=y
+CONFIG_STM32_USART3=y
+CONFIG_SYSLOG_NONE=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_USART3_SERIAL_CONSOLE=y
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_WDOG_INTRESERVE=1
diff --git a/configs/nucleo-f303ze/scripts/ld.script b/configs/nucleo-f303ze/scripts/ld.script
index c19cfbb010c..35e41a6860a 100644
--- a/configs/nucleo-f303ze/scripts/ld.script
+++ b/configs/nucleo-f303ze/scripts/ld.script
@@ -52,67 +52,71 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/nucleo-f303ze/src/Makefile b/configs/nucleo-f303ze/src/Makefile
index 9f6c5cb074a..7da547c2f8d 100644
--- a/configs/nucleo-f303ze/src/Makefile
+++ b/configs/nucleo-f303ze/src/Makefile
@@ -56,4 +56,8 @@ ifeq ($(CONFIG_ADC),y)
 CSRCS += stm32_adc.c
 endif
 
+ifeq ($(CONFIG_LCD_SSD1306),y)
+CSRCS += stm32_ssd1306.c
+endif
+
 include $(TOPDIR)/configs/Board.mk
diff --git a/configs/nucleo-f303ze/src/nucleo-f303ze.h b/configs/nucleo-f303ze/src/nucleo-f303ze.h
index 8e0f4cfa8f0..fd7fa80d151 100644
--- a/configs/nucleo-f303ze/src/nucleo-f303ze.h
+++ b/configs/nucleo-f303ze/src/nucleo-f303ze.h
@@ -84,6 +84,10 @@
 
 #define GPIO_BTN_USER  (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13)
 
+/* Oled configuration */
+
+#define OLED_I2C_PORT   1
+
 /****************************************************************************
  * Public Data
  ****************************************************************************/
diff --git a/configs/nucleo-f303ze/src/stm32_ssd1306.c b/configs/nucleo-f303ze/src/stm32_ssd1306.c
new file mode 100644
index 00000000000..133222c2440
--- /dev/null
+++ b/configs/nucleo-f303ze/src/stm32_ssd1306.c
@@ -0,0 +1,124 @@
+/****************************************************************************
+ * config/nucleo-f303ze/src/stm32_ssd1306.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "stm32.h"
+#include "nucleo-f303ze.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#ifndef CONFIG_LCD_MAXPOWER
+#  define CONFIG_LCD_MAXPOWER 1
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+FAR struct i2c_master_s *g_i2c;
+FAR struct lcd_dev_s    *g_lcddev;
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_lcd_initialize
+ ****************************************************************************/
+
+int board_lcd_initialize(void)
+{
+  /* Initialize I2C */
+
+  g_i2c = stm32_i2cbus_initialize(OLED_I2C_PORT);
+  if (!g_i2c)
+    {
+      lcderr("ERROR: Failed to initialize I2C port %d\n", OLED_I2C_PORT);
+      return -ENODEV;
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: board_lcd_getdev
+ ****************************************************************************/
+
+FAR struct lcd_dev_s *board_lcd_getdev(int devno)
+{
+  /* Bind the I2C port to the OLED */
+
+  g_lcddev = ssd1306_initialize(g_i2c, NULL, devno);
+  if (!g_lcddev)
+    {
+      lcderr("ERROR: Failed to bind I2C port 1 to OLED %d: %d\n", devno);
+    }
+  else
+    {
+      lcdinfo("Bound I2C port %d to OLED %d\n", OLED_I2C_PORT, devno);
+
+      /* And turn the OLED on */
+
+      (void)g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER);
+      return g_lcddev;
+    }
+
+  return NULL;
+}
+
+/****************************************************************************
+ * Name: board_lcd_uninitialize
+ ****************************************************************************/
+
+void board_lcd_uninitialize(void)
+{
+  /* TO-FIX */
+}
diff --git a/configs/nucleo-f334r8/adc/defconfig b/configs/nucleo-f334r8/adc/defconfig
index 97973aecd0a..18a2b122b7a 100644
--- a/configs/nucleo-f334r8/adc/defconfig
+++ b/configs/nucleo-f334r8/adc/defconfig
@@ -23,10 +23,8 @@ CONFIG_BUILTIN=y
 CONFIG_BUILTIN_PROXY_STACKSIZE=512
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_EXAMPLES_ADC=y
 CONFIG_EXAMPLES_ADC_GROUPSIZE=3
 CONFIG_EXAMPLES_ADC_SWTRIG=y
diff --git a/configs/nucleo-f334r8/highpri/defconfig b/configs/nucleo-f334r8/highpri/defconfig
index df415beb8cb..5e4cdf5646a 100644
--- a/configs/nucleo-f334r8/highpri/defconfig
+++ b/configs/nucleo-f334r8/highpri/defconfig
@@ -21,7 +21,6 @@ CONFIG_BUILTIN=y
 CONFIG_BUILTIN_PROXY_STACKSIZE=512
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_FDCLONE_STDIO=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f334r8/include/board.h b/configs/nucleo-f334r8/include/board.h
index 227d6e93136..99c7def0bbb 100644
--- a/configs/nucleo-f334r8/include/board.h
+++ b/configs/nucleo-f334r8/include/board.h
@@ -284,8 +284,6 @@
 
 /* TIM1 PWM configuration ***************************************************/
 
-#    define PWM_TIM1_NCHANNELS 4
-
 #    define GPIO_TIM1_CH1OUT   GPIO_TIM1_CH1OUT_1 /* TIM1 CH1  - PA8 */
 #    define GPIO_TIM1_CH1NOUT  GPIO_TIM1_CH1N_3   /* TIM1 CH1N - PA7 */
                                                   /* TIM1 CH2  - PA9 */
diff --git a/configs/nucleo-f334r8/nsh/defconfig b/configs/nucleo-f334r8/nsh/defconfig
index 295f6dfdd0d..ddbd6506583 100644
--- a/configs/nucleo-f334r8/nsh/defconfig
+++ b/configs/nucleo-f334r8/nsh/defconfig
@@ -23,10 +23,8 @@ CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_FDCLONE_STDIO=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f334r8/scripts/ld.script b/configs/nucleo-f334r8/scripts/ld.script
index 0cc2f4d7171..00656794e3a 100644
--- a/configs/nucleo-f334r8/scripts/ld.script
+++ b/configs/nucleo-f334r8/scripts/ld.script
@@ -52,73 +52,77 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The RAM vector table (if present) should lie at the beginning of SRAM */
+        /* The RAM vector table (if present) should lie at the beginning of SRAM */
 
-	.ram_vectors : {
-		*(.ram_vectors)
-	} > sram
+        .ram_vectors : {
+                *(.ram_vectors)
+        } > sram
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/nucleo-f334r8/spwm1/defconfig b/configs/nucleo-f334r8/spwm1/defconfig
index 3c8fb58f479..d38b97c44ab 100644
--- a/configs/nucleo-f334r8/spwm1/defconfig
+++ b/configs/nucleo-f334r8/spwm1/defconfig
@@ -21,7 +21,6 @@ CONFIG_BUILTIN=y
 CONFIG_BUILTIN_PROXY_STACKSIZE=512
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_FDCLONE_STDIO=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f334r8/spwm2/defconfig b/configs/nucleo-f334r8/spwm2/defconfig
index 49806ed1f05..910ea6f28cd 100644
--- a/configs/nucleo-f334r8/spwm2/defconfig
+++ b/configs/nucleo-f334r8/spwm2/defconfig
@@ -23,7 +23,6 @@ CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_FDCLONE_STDIO=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f334r8/src/stm32_highpri.c b/configs/nucleo-f334r8/src/stm32_highpri.c
index c3c041b0cf6..b1af05426e4 100644
--- a/configs/nucleo-f334r8/src/stm32_highpri.c
+++ b/configs/nucleo-f334r8/src/stm32_highpri.c
@@ -441,9 +441,9 @@ int highpri_main(int argc, char *argv[])
 
   PWM_CCR_UPDATE(pwm1, 1, 0x0f00);
 
-  /* Enable TIM1 CHAN1 */
+  /* Enable TIM1 OUT1 */
 
-  PWM_OUTPUTS_ENABLE(pwm1, STM32_CHAN1, true);
+  PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true);
 #else
 #  error T1CC1 only supported for now
 #endif
diff --git a/configs/nucleo-f410rb/nsh/defconfig b/configs/nucleo-f410rb/nsh/defconfig
index 815b98ccb47..6ee10cdf0ef 100644
--- a/configs/nucleo-f410rb/nsh/defconfig
+++ b/configs/nucleo-f410rb/nsh/defconfig
@@ -23,7 +23,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=8499
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/nucleo-f446re/nsh/defconfig b/configs/nucleo-f446re/nsh/defconfig
index 7daffa6acd5..b33427b4c82 100644
--- a/configs/nucleo-f446re/nsh/defconfig
+++ b/configs/nucleo-f446re/nsh/defconfig
@@ -23,7 +23,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
 CONFIG_BOARD_LOOPSPERMSEC=8499
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f446re/src/stm32_ajoystick.c b/configs/nucleo-f446re/src/stm32_ajoystick.c
index 04fa8e6e9a3..6e51d0f0531 100644
--- a/configs/nucleo-f446re/src/stm32_ajoystick.c
+++ b/configs/nucleo-f446re/src/stm32_ajoystick.c
@@ -51,7 +51,7 @@
 
 #include "stm32_gpio.h"
 #include "stm32_adc.h"
-#include "chip/stm32_adc.h"
+#include "hardware/stm32_adc.h"
 #include "nucleo-f446re.h"
 
 /****************************************************************************
diff --git a/configs/nucleo-f4x1re/f401-nsh/defconfig b/configs/nucleo-f4x1re/f401-nsh/defconfig
index 2e404215fa5..3b2b848e686 100644
--- a/configs/nucleo-f4x1re/f401-nsh/defconfig
+++ b/configs/nucleo-f4x1re/f401-nsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
 CONFIG_BOARD_LOOPSPERMSEC=8499
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f4x1re/f411-nsh/defconfig b/configs/nucleo-f4x1re/f411-nsh/defconfig
index 944f5959dd0..a92b91de72c 100644
--- a/configs/nucleo-f4x1re/f411-nsh/defconfig
+++ b/configs/nucleo-f4x1re/f411-nsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
 CONFIG_BOARD_LOOPSPERMSEC=8499
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/nucleo-f4x1re/src/Makefile b/configs/nucleo-f4x1re/src/Makefile
index a836bb63702..7ebb7a823db 100644
--- a/configs/nucleo-f4x1re/src/Makefile
+++ b/configs/nucleo-f4x1re/src/Makefile
@@ -1,7 +1,7 @@
 ############################################################################
 # configs/nucleo-f4x1re/src/Makefile
 #
-#   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2014, 2019 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt 
 #
 # Redistribution and use in source and binary forms, with or without
@@ -36,7 +36,7 @@
 -include $(TOPDIR)/Make.defs
 
 ASRCS =
-CSRCS = stm32_boot.c stm32_spi.c
+CSRCS = stm32_boot.c stm32_spi.c stm32_bringup.c
 
 ifeq ($(CONFIG_ARCH_LEDS),y)
 CSRCS += stm32_autoleds.c
@@ -59,7 +59,7 @@ ifeq ($(CONFIG_SENSORS_QENCODER),y)
 CSRCS += stm32_qencoder.c
 endif
 
-ifeq ($(CONFIG_NSH_LIBRARY),y)
+ifeq ($(CONFIG_LIB_BOARDCTL),y)
 CSRCS += stm32_appinit.c
 endif
 
diff --git a/configs/nucleo-f4x1re/src/nucleo-f4x1re.h b/configs/nucleo-f4x1re/src/nucleo-f4x1re.h
index 59d96c0604e..b5f476333c9 100644
--- a/configs/nucleo-f4x1re/src/nucleo-f4x1re.h
+++ b/configs/nucleo-f4x1re/src/nucleo-f4x1re.h
@@ -227,6 +227,26 @@ extern struct sdio_dev_s *g_sdio;
  * Public Functions
  ************************************************************************************/
 
+/****************************************************************************
+ * Name: stm32_bringup
+ *
+ * Description:
+ *   Perform architecture specific initialization
+ *
+ *   CONFIG_LIB_BOARDCTL=y:
+ *     If CONFIG_NSH_ARCHINITIALIZE=y:
+ *       Called from the NSH library (or other application)
+ *     Otherwise, assumed to be called from some other application.
+ *
+ *   Otherwise CONFIG_BOARD_LATE_INITIALIZE=y:
+ *     Called from board_late_initialize().
+ *
+ *   Otherise, bad news:  Never called
+ *
+ ****************************************************************************/
+
+int stm32_bringup(void);
+
 /************************************************************************************
  * Name: stm32_spidev_initialize
  *
diff --git a/configs/nucleo-f4x1re/src/stm32_ajoystick.c b/configs/nucleo-f4x1re/src/stm32_ajoystick.c
index fe4a1ade251..42fdc973318 100644
--- a/configs/nucleo-f4x1re/src/stm32_ajoystick.c
+++ b/configs/nucleo-f4x1re/src/stm32_ajoystick.c
@@ -51,7 +51,7 @@
 
 #include "stm32_gpio.h"
 #include "stm32_adc.h"
-#include "chip/stm32_adc.h"
+#include "hardware/stm32_adc.h"
 #include "nucleo-f4x1re.h"
 
 /****************************************************************************
diff --git a/configs/nucleo-f4x1re/src/stm32_appinit.c b/configs/nucleo-f4x1re/src/stm32_appinit.c
index 7028c55a213..fe724d05c3c 100644
--- a/configs/nucleo-f4x1re/src/stm32_appinit.c
+++ b/configs/nucleo-f4x1re/src/stm32_appinit.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * configs/nucleo-f4x1re/src/stm32_appinit.c
  *
- *   Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2014, 2016, 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -39,19 +39,9 @@
 
 #include 
 
-#include 
-#include 
-#include 
+#include 
 
-#include 
 #include 
-#include 
-#include 
-
-#include 
-#include 
-
-#include 
 
 #include "nucleo-f4x1re.h"
 
@@ -71,7 +61,7 @@
  *   arg - The boardctl() argument is passed to the board_app_initialize()
  *         implementation without modification.  The argument has no
  *         meaning to NuttX; the meaning of the argument is a contract
- *         between the board-specific initalization logic and the
+ *         between the board-specific initialization logic and the
  *         matching application logic.  The value cold be such things as a
  *         mode enumeration value, a set of DIP switch switch settings, a
  *         pointer to configuration data read from a file or serial FLASH,
@@ -86,74 +76,7 @@
 
 int board_app_initialize(uintptr_t arg)
 {
-  int ret = OK;
+  /* Perform board initialization here */
 
-#ifdef HAVE_MMCSD
-  /* First, get an instance of the SDIO interface */
-
-  g_sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO);
-  if (!g_sdio)
-    {
-      syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n",
-             CONFIG_NSH_MMCSDSLOTNO);
-      return -ENODEV;
-    }
-
-  /* Now bind the SDIO interface to the MMC/SD driver */
-
-  ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdio);
-  if (ret != OK)
-    {
-      syslog(LOG_ERR,
-             "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n",
-             ret);
-      return ret;
-    }
-
-  /* Then let's guess and say that there is a card in the slot. There is no
-   * card detect GPIO.
-   */
-
-  sdio_mediachange(g_sdio, true);
-
-  syslog(LOG_INFO, "[boot] Initialized SDIO\n");
-#endif
-
-#ifdef CONFIG_ADC
-  /* Initialize ADC and register the ADC driver. */
-
-  ret = stm32_adc_setup();
-  if (ret < 0)
-    {
-      syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret);
-    }
-#endif
-
-#ifdef CONFIG_SENSORS_QENCODER
-  /* Initialize and register the qencoder driver */
-
-  ret = stm32_qencoder_initialize("/dev/qe0", CONFIG_NUCLEO_F401RE_QETIMER);
-  if (ret != OK)
-    {
-      syslog(LOG_ERR,
-             "ERROR: Failed to register the qencoder: %d\n",
-             ret);
-      return ret;
-    }
-#endif
-
-#ifdef CONFIG_AJOYSTICK
-  /* Initialize and register the joystick driver */
-
-  ret = board_ajoy_initialize();
-  if (ret != OK)
-    {
-      syslog(LOG_ERR,
-             "ERROR: Failed to register the joystick driver: %d\n",
-             ret);
-      return ret;
-    }
-#endif
-
-  return ret;
+  return stm32_bringup();
 }
diff --git a/configs/nucleo-f4x1re/src/stm32_boot.c b/configs/nucleo-f4x1re/src/stm32_boot.c
index a60931ba967..8c1328b5060 100644
--- a/configs/nucleo-f4x1re/src/stm32_boot.c
+++ b/configs/nucleo-f4x1re/src/stm32_boot.c
@@ -51,14 +51,6 @@
 #include "up_arch.h"
 #include "nucleo-f4x1re.h"
 
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Private Data
- ************************************************************************************/
-
 /************************************************************************************
  * Public Functions
  ************************************************************************************/
@@ -99,29 +91,26 @@ void stm32_boardinitialize(void)
 #endif
 }
 
-/****************************************************************************
+/************************************************************************************
  * Name: board_late_initialize
  *
  * Description:
- *   If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
- *   initialization call will be performed in the boot-up sequence to a
- *   function called board_late_initialize().  board_late_initialize() will be
- *   called immediately after up_intiialize() is called and just before the
- *   initial application is started.  This additional initialization phase
- *   may be used, for example, to initialize board-specific device drivers.
+ *   If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional initialization
+ *   call will be performed in the boot-up sequence to a function called
+ *   board_late_initialize().  board_late_initialize() will be called immediately
+ *   after up_initialize() is called and just before the initial application is
+ *   started.  This additional initialization phase may be used, for example, to
+ *   initialize board-specific device drivers.
  *
- ****************************************************************************/
+ ************************************************************************************/
 
 #ifdef CONFIG_BOARD_LATE_INITIALIZE
 void board_late_initialize(void)
 {
-  /* Perform NSH initialization here instead of from the NSH.  This
-   * alternative NSH initialization is necessary when NSH is ran in user-space
-   * but the initialization function must run in kernel space.
-   */
+#ifndef CONFIG_LIB_BOARDCTL
+  /* Perform board initialization here instead of from the board_app_initialize(). */
 
-#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL)
-  board_app_initialize(0);
+  (void)stm32_bringup();
 #endif
 }
 #endif
diff --git a/configs/nucleo-f4x1re/src/stm32_bringup.c b/configs/nucleo-f4x1re/src/stm32_bringup.c
new file mode 100644
index 00000000000..d973cafd5f7
--- /dev/null
+++ b/configs/nucleo-f4x1re/src/stm32_bringup.c
@@ -0,0 +1,148 @@
+/****************************************************************************
+ * configs/nucleo-f4x1re/src/stm32_bringup.c
+ *
+ *   Copyright (C) 2014, 2016, 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+
+#include "nucleo-f4x1re.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y :
+ *     Called from board_late_initialize().
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
+ *     Called from the NSH library
+ *
+ ****************************************************************************/
+
+int stm32_bringup(void)
+{
+  int ret = OK;
+
+#ifdef HAVE_MMCSD
+  /* First, get an instance of the SDIO interface */
+
+  g_sdio = sdio_initialize(CONFIG_NSH_MMCSDSLOTNO);
+  if (!g_sdio)
+    {
+      syslog(LOG_ERR, "ERROR: Failed to initialize SDIO slot %d\n",
+             CONFIG_NSH_MMCSDSLOTNO);
+      return -ENODEV;
+    }
+
+  /* Now bind the SDIO interface to the MMC/SD driver */
+
+  ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_sdio);
+  if (ret != OK)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n",
+             ret);
+      return ret;
+    }
+
+  /* Then let's guess and say that there is a card in the slot. There is no
+   * card detect GPIO.
+   */
+
+  sdio_mediachange(g_sdio, true);
+
+  syslog(LOG_INFO, "[boot] Initialized SDIO\n");
+#endif
+
+#ifdef CONFIG_ADC
+  /* Initialize ADC and register the ADC driver. */
+
+  ret = stm32_adc_setup();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret);
+    }
+#endif
+
+#ifdef CONFIG_SENSORS_QENCODER
+  /* Initialize and register the qencoder driver */
+
+  ret = stm32_qencoder_initialize("/dev/qe0", CONFIG_NUCLEO_F401RE_QETIMER);
+  if (ret != OK)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to register the qencoder: %d\n",
+             ret);
+      return ret;
+    }
+#endif
+
+#ifdef CONFIG_AJOYSTICK
+  /* Initialize and register the joystick driver */
+
+  ret = board_ajoy_initialize();
+  if (ret != OK)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to register the joystick driver: %d\n",
+             ret);
+      return ret;
+    }
+#endif
+
+  return ret;
+}
diff --git a/configs/nucleo-g071rb/Kconfig b/configs/nucleo-g071rb/Kconfig
new file mode 100644
index 00000000000..332b9450499
--- /dev/null
+++ b/configs/nucleo-g071rb/Kconfig
@@ -0,0 +1,8 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_NUCLEO_G071RB
+
+endif
diff --git a/configs/nucleo-g071rb/README.txt b/configs/nucleo-g071rb/README.txt
new file mode 100644
index 00000000000..0779c0f2883
--- /dev/null
+++ b/configs/nucleo-g071rb/README.txt
@@ -0,0 +1,34 @@
+Nucleo-64 Boards
+================
+
+The Nucleo-G071RB is a member of the Nucleo-64 board family.  The Nucleo-64
+is a standard board for use with several STM32 parts in the LQFP64 package.
+Variants include
+
+  Order code    Targeted STM32
+  ------------- --------------
+  NUCLEO-F030R8 STM32F030R8T6
+  NUCLEO-F070RB STM32F070RBT6
+  NUCLEO-F072RB STM32F072RBT6
+  NUCLEO-F091RC STM32F091RCT6
+  NUCLEO-F103RB STM32F103RBT6
+  NUCLEO-F302R8 STM32F302R8T6
+  NUCLEO-F303RE STM32F303RET6
+  NUCLEO-F334R8 STM32F334R8T6
+  NUCLEO-F401RE STM32F401RET6
+  NUCLEO-F410RB STM32F410RBT6
+  NUCLEO-F411RE STM32F411RET6
+  NUCLEO-F446RE STM32F446RET6
+  NUCLEO-L053R8 STM32L053R8T6
+  NUCLEO-L073RZ STM32L073RZT6
+  NUCLEO-L152RE STM32L152RET6
+  NUCLEO-L452RE STM32L452RET6
+  NUCLEO-L476RG STM32L476RGT6
+
+STATUS
+======
+
+  2019-05-27: Brings in initial WIP support for the STM32 G0.
+              Not tested on hardware.
+
+  2019-05-30: The basic NSH configuration is now functional.
diff --git a/configs/nucleo-g071rb/include/board.h b/configs/nucleo-g071rb/include/board.h
new file mode 100644
index 00000000000..b6675868212
--- /dev/null
+++ b/configs/nucleo-g071rb/include/board.h
@@ -0,0 +1,222 @@
+/****************************************************************************
+ * configs/nucleo-g071rb/include/board.h
+ * include/arch/board/board.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __CONFIG_NUCLEO_G071RB_INCLUDE_BOARD_H
+#define __CONFIG_NUCLEO_G071RB_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#ifndef __ASSEMBLY__
+#  include 
+#  include 
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking *****************************************************************/
+
+/* HSI - Internal 16 MHz RC Oscillator
+ * LSI - 32 KHz RC
+ * HSE - 8 MHz from MCO output of ST-LINK (disabled by default)
+ * LSE - 32.768 kHz
+ */
+
+#define STM32_BOARD_XTAL        8000000ul
+
+#define STM32_HSI_FREQUENCY     16000000ul
+#define STM32_LSI_FREQUENCY     32000            /* Between 30kHz and 60kHz */
+#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY     32768            /* X2 on board */
+
+/* Main PLL Configuration.
+ *
+ * PLL source is HSI = 16,000,000
+ *
+ * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN
+ * Subject to:
+ *
+ *     1 <= PLLM <= 8
+ *     8 <= PLLN <= 86
+ *   4 MHz <= PLL_IN <= 16MHz
+ *   64 MHz <= PLL_VCO <= 344MHz
+ * SYSCLK  = PLLRCLK = PLL_VCO / PLLR
+ *
+ */
+
+/* PLL source is HSI, PLLN=50, PLLM=4
+ * PLLP enable, PLLQ enable, PLLR enable
+ *
+ *   2 <= PLLP <= 32
+ *   2 <= PLLQ <= 8
+ *   2 <= PLLR <= 8
+ *
+ *   PLLR <= 64MHz
+ *   PLLQ <= 128MHz
+ *   PLLP <= 128MHz
+ *
+ *   PLL_VCO = (16,000,000 / 4) * 50 = 200 MHz
+ *
+ *   PLLP = PLL_VCO/4 = 200 MHz / 4 = 40 MHz
+ *   PLLQ = PLL_VCO/4 = 200 MHz / 4 = 40 MHz
+ *   PLLR = PLL_VCO/4 = 200 MHz / 4 = 40 MHz
+ */
+
+#define STM32_PLLCFG_PLLSRC     RCC_PLLCFG_PLLSRC_HSI
+#define STM32_PLLCFG_PLLCFG     (RCC_PLLCFG_PLLPEN | \
+                                 RCC_PLLCFG_PLLQEN | \
+                                 RCC_PLLCFG_PLLREN)
+
+#define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(4)
+#define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(50)
+#define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP(4)
+#define STM32_PLLCFG_PLLQ       RCC_PLLCFG_PLLQ(4)
+#define STM32_PLLCFG_PLLR       RCC_PLLCFG_PLLR(4)
+
+#define STM32_VCO_FREQUENCY     ((STM32_HSE_FREQUENCY / 2) * 50)
+#define STM32_PLLP_FREQUENCY    (STM32_VCO_FREQUENCY / 4)
+#define STM32_PLLQ_FREQUENCY    (STM32_VCO_FREQUENCY / 4)
+#define STM32_PLLR_FREQUENCY    (STM32_VCO_FREQUENCY / 4)
+
+/* Use the PLL and set the SYSCLK source to be the PLLR (40MHz) */
+
+#define STM32_SYSCLK_SW         RCC_CFGR_SW_PLL
+#define STM32_SYSCLK_SWS        RCC_CFGR_SWS_PLL
+#define STM32_SYSCLK_FREQUENCY  (STM32_PLLR_FREQUENCY)
+
+/* AHB clock (HCLK) is SYSCLK (40MHz) */
+
+#define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK
+#define STM32_HCLK_FREQUENCY    STM32_SYSCLK_FREQUENCY
+#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY
+
+/* APB1 clock (PCLK1) is HCLK/2 (20MHz) */
+
+#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd2
+#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
+
+/* TODO: timers */
+
+/* LED definitions **********************************************************/
+/* The Nucleo LO73RZ board has three LEDs.  Two of these are controlled by
+ * logic on the board and are not available for software control:
+ *
+ * LD1 COM:  LD1 default status is red.  LD1 turns to green to indicate that
+ *           communications are in progress between the PC and the
+ *           ST-LINK/V2-1.
+ * LD3 PWR:  red LED indicates that the board is powered.
+ *
+ * And one can be controlled by software:
+ *
+ * User LD2: green LED is a user LED connected to the I/O PA5 of the
+ *           STM32LO73RZ.
+ *
+ * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in
+ * any way.  The following definition is used to access the LED.
+ */
+
+/* LED index values for use with board_userled() */
+
+#define BOARD_LED1       0 /* User LD2 */
+#define BOARD_NLEDS      1
+
+/* LED bits for use with board_userled_all() */
+
+#define BOARD_LED1_BIT   (1 << BOARD_LED1)
+
+/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board
+ * the Nucleo LO73RZ.  The following definitions describe how NuttX controls
+ * the LED:
+ *
+ *   SYMBOL              Meaning                  LED1 state
+ *   ------------------  -----------------------  ----------
+ *   LED_STARTED         NuttX has been started   OFF
+ *   LED_HEAPALLOCATE    Heap has been allocated  OFF
+ *   LED_IRQSENABLED     Interrupts enabled       OFF
+ *   LED_STACKCREATED    Idle stack created       ON
+ *   LED_INIRQ           In an interrupt          No change
+ *   LED_SIGNAL          In a signal handler      No change
+ *   LED_ASSERTION       An assertion failed      No change
+ *   LED_PANIC           The system has crashed   Blinking
+ *   LED_IDLE            STM32 is is sleep mode   Not used
+ */
+
+#define LED_STARTED      0
+#define LED_HEAPALLOCATE 0
+#define LED_IRQSENABLED  0
+#define LED_STACKCREATED 1
+#define LED_INIRQ        2
+#define LED_SIGNAL       2
+#define LED_ASSERTION    2
+#define LED_PANIC        1
+
+/* Button definitions *******************************************************/
+/* The Nucleo LO73RZ supports two buttons; only one button is controllable
+ * by software:
+ *
+ *   B1 USER:  user button connected to the I/O PC13 of the STM32LO73RZ.
+ *   B2 RESET: push button connected to NRST is used to RESET the
+ *             STM32LO73RZ.
+ */
+
+#define BUTTON_USER      0
+#define NUM_BUTTONS      1
+
+#define BUTTON_USER_BIT  (1 << BUTTON_USER)
+
+/* Alternate function pin selections ****************************************/
+
+/* USART */
+
+/* By default the USART2 is connected to STLINK Virtual COM Port:
+ * USART2_RX - PA3
+ * USART2_TX - PA2
+ */
+
+#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */
+#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */
+
+/* DMA channels *************************************************************/
+/* ADC */
+
+#define ADC1_DMA_CHAN DMACHAN_ADC1     /* DMA1_CH1 */
+
+#endif /* __CONFIG_NUCLEO_LO73RZ_INCLUDE_BOARD_H */
diff --git a/configs/nucleo-g071rb/nsh/defconfig b/configs/nucleo-g071rb/nsh/defconfig
new file mode 100644
index 00000000000..377db0e6794
--- /dev/null
+++ b/configs/nucleo-g071rb/nsh/defconfig
@@ -0,0 +1,57 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_LIBC_LONG_LONG is not set
+# CONFIG_NSH_ARGCAT is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="nucleo-g071rb"
+CONFIG_ARCH_BOARD_NUCLEO_G071RB=y
+CONFIG_ARCH_CHIP_STM32G071RB=y
+CONFIG_ARCH_CHIP_STM32G0=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=2796
+CONFIG_BUILTIN=y
+CONFIG_DISABLE_ENVIRON=y
+CONFIG_DISABLE_MOUNTPOINT=y
+CONFIG_DISABLE_MQUEUE=y
+CONFIG_DISABLE_POLL=y
+CONFIG_DISABLE_POSIX_TIMERS=y
+CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
+CONFIG_EXAMPLES_HELLO=y
+CONFIG_INTELHEX_BINARY=y
+CONFIG_MAX_TASKS=8
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_NFILE_DESCRIPTORS=6
+CONFIG_NFILE_STREAMS=6
+CONFIG_NPTHREAD_KEYS=0
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=64
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_NUNGET_CHARS=0
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_PTHREAD_MUTEX_UNSAFE=y
+CONFIG_PTHREAD_STACK_DEFAULT=1536
+CONFIG_RAM_SIZE=20480
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_START_DAY=19
+CONFIG_START_MONTH=5
+CONFIG_START_YEAR=2013
+CONFIG_STDIO_DISABLE_BUFFERING=y
+CONFIG_STM32F0L0G0_USART2=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
+CONFIG_USART2_SERIAL_CONSOLE=y
+CONFIG_USERMAIN_STACKSIZE=1536
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_WDOG_INTRESERVE=0
diff --git a/configs/nucleo-g071rb/scripts/Make.defs b/configs/nucleo-g071rb/scripts/Make.defs
new file mode 100644
index 00000000000..38d96d46319
--- /dev/null
+++ b/configs/nucleo-g071rb/scripts/Make.defs
@@ -0,0 +1,114 @@
+############################################################################
+# configs/nucleo-g071rb/scripts/Make.defs
+#
+#   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt 
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv6-m/Toolchain.defs
+
+LDSCRIPT = ld.script
+
+ifeq ($(WINTOOL),y)
+  # Windows-native toolchains
+  DIRLINK = $(TOPDIR)/tools/copydir.sh
+  DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+  MKDEP = $(TOPDIR)/tools/mkwindeps.sh
+  ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+  ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+  # Linux/Cygwin-native toolchain
+  MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+  ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+  ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+STRIP = $(CROSSDEV)strip --strip-unneeded
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+  ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+  LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  LDFLAGS += -g
+endif
+
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =
+
diff --git a/configs/nucleo-g071rb/scripts/ld.script b/configs/nucleo-g071rb/scripts/ld.script
new file mode 100644
index 00000000000..9572c27ed4e
--- /dev/null
+++ b/configs/nucleo-g071rb/scripts/ld.script
@@ -0,0 +1,128 @@
+/****************************************************************************
+ * configs/nucleo-g071rb/scripts/ld.script
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The STM32GO71RB has 128Kb of FLASH beginning at address 0x0800:0000.
+ * 32Kb/36Kb of SRAM
+ *
+ * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
+ * where the code expects to begin execution by jumping to the entry point in
+ * the 0x0800:0000 address range.
+ */
+
+MEMORY
+{
+    flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+    sram (rwx) : ORIGIN = 0x20000000, LENGTH = 36K
+}
+
+OUTPUT_ARCH(arm)
+EXTERN(_vectors)
+ENTRY(_stext)
+SECTIONS
+{
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
+
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
+
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
+
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
+
+        _eronly = ABSOLUTE(.);
+
+        /* The RAM vector table (if present) should lie at the beginning of SRAM */
+
+        .ram_vectors : {
+                *(.ram_vectors)
+        } > sram
+
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
+
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
+
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/configs/nucleo-g071rb/src/Makefile b/configs/nucleo-g071rb/src/Makefile
new file mode 100644
index 00000000000..89159f28f8b
--- /dev/null
+++ b/configs/nucleo-g071rb/src/Makefile
@@ -0,0 +1,55 @@
+############################################################################
+# configs/nucleo-g071rb/src/Makefile
+#
+#   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+#   Author: Mateusz Szafoni 
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+
+ASRCS =
+CSRCS = stm32_boot.c stm32_bringup.c
+
+ifeq ($(CONFIG_ARCH_LEDS),y)
+CSRCS += stm32_autoleds.c
+else
+CSRCS += stm32_userleds.c
+endif
+
+ifeq ($(CONFIG_ARCH_BUTTONS),y)
+CSRCS += stm32_buttons.c
+endif
+
+ifeq ($(CONFIG_LIB_BOARDCTL),y)
+CSRCS += stm32_appinit.c
+endif
+
+include $(TOPDIR)/configs/Board.mk
diff --git a/configs/nucleo-g071rb/src/nucleo-g071rb.h b/configs/nucleo-g071rb/src/nucleo-g071rb.h
new file mode 100644
index 00000000000..6def8bfa9da
--- /dev/null
+++ b/configs/nucleo-g071rb/src/nucleo-g071rb.h
@@ -0,0 +1,114 @@
+/****************************************************************************
+ * configs/nucleo-g071rb/src/nucleo-g071rb.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Authors: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __CONFIGS_NUCLEO_G071RB_SRC_NUCLEO_G071RB_H
+#define __CONFIGS_NUCLEO_G071RB_SRC_NUCLEO_G071RB_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* LED definitions **********************************************************/
+/* The Nucleo G071RB board has three LEDs.  Two of these are controlled by
+ * logic on the board and are not available for software control:
+ *
+ * LD1 COM:  LD1 default status is red.  LD1 turns to green to indicate that
+ *           communications are in progress between the PC and the
+ *           ST-LINK/V2-1.
+ * LD3 PWR:  red LED indicates that the board is powered.
+ *
+ * And one can be controlled by software:
+ *
+ * User LD2: green LED is a user LED connected to the I/O PA5 of the
+ *           STM32G071RBT6.
+ *
+ * If CONFIG_ARCH_LEDS is not defined, then the user can control the LED in
+ * any way.  The following definition is used to access the LED.
+ */
+
+#define GPIO_LED1      (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_HIGH | \
+                        GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN5)
+
+#define LED_DRIVER_PATH "/dev/userleds"
+
+/* Button definitions *******************************************************/
+/* The Nucleo G071RB supports two buttons; only one button is controllable
+ * by software:
+ *
+ *   B1 USER:  user button connected to the I/O PC13 of the STM32G071RBT6.
+ *   B2 RESET: push button connected to NRST is used to RESET the
+ *             STM32G071RBT6.
+ *
+ * NOTE that EXTI interrupts are configured.
+ */
+
+#define MIN_IRQBUTTON  BUTTON_USER
+#define MAX_IRQBUTTON  BUTTON_USER
+#define NUM_IRQBUTTONS 1
+
+#define GPIO_BTN_USER  (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | \
+                        GPIO_PIN13)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Name: stm32_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y :
+ *     Called from board_late_initialize().
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
+ *     Called from the NSH library
+ *
+ ************************************************************************************/
+
+int stm32_bringup(void);
+
+#endif /* __CONFIGS_NUCLEO_G071RB_SRC_NUCLEO_G071RB_H */
diff --git a/configs/nucleo-g071rb/src/stm32_appinit.c b/configs/nucleo-g071rb/src/stm32_appinit.c
new file mode 100644
index 00000000000..3fe5aa499ac
--- /dev/null
+++ b/configs/nucleo-g071rb/src/stm32_appinit.c
@@ -0,0 +1,90 @@
+/****************************************************************************
+ * configs/nucleo-g071rb/src/stm32_appinitialize.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Authors: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+
+#include "nucleo-g071rb.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ *   Perform application specific initialization.  This function is never
+ *   called directly from application code, but only indirectly via the
+ *   (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ *   arg - The boardctl() argument is passed to the board_app_initialize()
+ *         implementation without modification.  The argument has no
+ *         meaning to NuttX; the meaning of the argument is a contract
+ *         between the board-specific initalization logic and the
+ *         matching application logic.  The value cold be such things as a
+ *         mode enumeration value, a set of DIP switch switch settings, a
+ *         pointer to configuration data read from a file or serial FLASH,
+ *         or whatever you would like to do with it.  Every implementation
+ *         should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int board_app_initialize(uintptr_t arg)
+{
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+  /* Board initialization already performed by board_late_initialize() */
+
+  return OK;
+#else
+  /* Perform board-specific initialization */
+
+  return stm32_bringup();
+#endif
+}
diff --git a/configs/nucleo-g071rb/src/stm32_autoleds.c b/configs/nucleo-g071rb/src/stm32_autoleds.c
new file mode 100644
index 00000000000..9249a40e319
--- /dev/null
+++ b/configs/nucleo-g071rb/src/stm32_autoleds.c
@@ -0,0 +1,94 @@
+/****************************************************************************
+ * configs/nucleo-g071rb/src/stm32_autoleds.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Authors: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+#include "stm32_gpio.h"
+#include "nucleo-g071rb.h"
+
+#include 
+
+#ifdef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_autoled_initialize
+ ****************************************************************************/
+
+void board_autoled_initialize(void)
+{
+  /* Configure LED1 GPIO for output */
+
+  stm32_configgpio(GPIO_LED1);
+}
+
+/****************************************************************************
+ * Name: board_autoled_on
+ ****************************************************************************/
+
+void board_autoled_on(int led)
+{
+  if (led == BOARD_LED1)
+    {
+      stm32_gpiowrite(GPIO_LED1, true);
+    }
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
+
+void board_autoled_off(int led)
+{
+  if (led == BOARD_LED1)
+    {
+      stm32_gpiowrite(GPIO_LED1, false);
+    }
+}
+
+#endif /* CONFIG_ARCH_LEDS */
diff --git a/configs/nucleo-g071rb/src/stm32_boot.c b/configs/nucleo-g071rb/src/stm32_boot.c
new file mode 100644
index 00000000000..b524411536b
--- /dev/null
+++ b/configs/nucleo-g071rb/src/stm32_boot.c
@@ -0,0 +1,99 @@
+/****************************************************************************
+ * configs/nucleo-g071rb/src/stm32_boot.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Authors: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+
+#include "nucleo-g071rb.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_boardinitialize
+ *
+ * Description:
+ *   All STM32 architectures must provide the following entry point.  This
+ *   entry point is called early in the intitialization -- after all memory
+ *   has been configured and mapped but before any devices have been
+ *   initialized.
+ *
+ ****************************************************************************/
+
+void stm32_boardinitialize(void)
+{
+#ifdef CONFIG_ARCH_LEDS
+  /* Configure on-board LEDs if LED support has been selected. */
+
+  board_autoled_initialize();
+#endif
+
+#ifdef CONFIG_STM32F0L0G0_SPI
+  /* Configure SPI chip selects */
+
+  stm32_spidev_initialize();
+#endif
+}
+
+/************************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ *   If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional initialization call
+ *   will be performed in the boot-up sequence to a function called
+ *   board_late_initialize().  board_late_initialize() will be called immediately after
+ *   up_initialize() is called and just before the initial application is started.
+ *   This additional initialization phase may be used, for example, to initialize
+ *   board-specific device drivers.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL)
+  /* Perform board bring-up here instead of from the board_app_initialize(). */
+
+  (void)stm32_bringup();
+#endif
+}
+#endif
diff --git a/configs/nucleo-g071rb/src/stm32_bringup.c b/configs/nucleo-g071rb/src/stm32_bringup.c
new file mode 100644
index 00000000000..3f82da88315
--- /dev/null
+++ b/configs/nucleo-g071rb/src/stm32_bringup.c
@@ -0,0 +1,164 @@
+/****************************************************************************
+ * configs/nucleo-g071rb/src/stm32_bringup.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Authors: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+
+#include "nucleo-g071rb.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#undef HAVE_LEDS
+#undef HAVE_DAC
+
+#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER)
+#  define HAVE_LEDS 1
+#endif
+
+#if defined(CONFIG_DAC)
+#  define HAVE_DAC1 1
+#  define HAVE_DAC2 1
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+/****************************************************************************
+ * Name: stm32_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y :
+ *     Called from board_late_initialize().
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y && CONFIG_NSH_ARCHINIT:
+ *     Called from the NSH library
+ *
+ ****************************************************************************/
+
+int stm32_bringup(void)
+{
+  int ret;
+
+#ifdef HAVE_LEDS
+  /* Register the LED driver */
+
+  ret = userled_lower_initialize(LED_DRIVER_PATH);
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
+      return ret;
+    }
+#endif
+
+#ifdef CONFIG_ADC
+  /* Initialize ADC and register the ADC driver. */
+
+  ret = stm32_adc_setup();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret);
+    }
+#endif
+
+#ifdef CONFIG_DAC
+  /* Initialize DAC and register the DAC driver. */
+
+  ret = stm32_dac_setup();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret);
+    }
+#endif
+
+#ifdef CONFIG_COMP
+  /* Initialize COMP and register the COMP driver. */
+
+  ret = stm32_comp_setup();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: stm32_comp_setup failed: %d\n", ret);
+    }
+#endif
+
+#ifdef CONFIG_OPAMP
+  /* Initialize OPAMP and register the OPAMP driver. */
+
+  ret = stm32_opamp_setup();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret);
+    }
+#endif
+
+#ifdef CONFIG_WL_NRF24L01
+  ret = stm32_wlinitialize();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", ret);
+    }
+#endif  /* CONFIG_WL_NRF24L01 */
+
+#ifdef CONFIG_LPWAN_SX127X
+  ret = stm32_lpwaninitialize();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", ret);
+    }
+#endif  /* CONFIG_LPWAN_SX127X */
+
+#ifdef CONFIG_CL_MFRC522
+  ret = stm32_mfrc522initialize("/dev/rfid0");
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: stm32_mfrc522initialize() failed: %d\n", ret);
+    }
+#endif  /* CONFIG_CL_MFRC522 */
+
+  UNUSED(ret);
+  return OK;
+}
diff --git a/configs/nucleo-g071rb/src/stm32_buttons.c b/configs/nucleo-g071rb/src/stm32_buttons.c
new file mode 100644
index 00000000000..29a3a6beba5
--- /dev/null
+++ b/configs/nucleo-g071rb/src/stm32_buttons.c
@@ -0,0 +1,129 @@
+/****************************************************************************
+ * configs/nucleo-g071rb/src/stm32_buttons.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Authors: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "stm32_gpio.h"
+#include "nucleo-g071rb.h"
+
+#include 
+
+#ifdef CONFIG_ARCH_BUTTONS
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_button_initialize
+ *
+ * Description:
+ *   board_button_initialize() must be called to initialize button resources.
+ *   After that, board_buttons() may be called to collect the current state
+ *   of all buttons or board_button_irq() may be called to register button
+ *   interrupt handlers.
+ *
+ ****************************************************************************/
+
+void board_button_initialize(void)
+{
+  /* Configure the single button as an input.  NOTE that EXTI interrupts are
+   * also configured for the pin.
+   */
+
+  stm32_configgpio(GPIO_BTN_USER);
+}
+
+/****************************************************************************
+ * Name: board_buttons
+ ****************************************************************************/
+
+uint32_t board_buttons(void)
+{
+  /* Check that state of each USER button. A LOW value means that the key is
+   * pressed.
+   */
+
+  bool released = stm32_gpioread(GPIO_BTN_USER);
+  return !released;
+}
+
+/************************************************************************************
+ * Button support.
+ *
+ * Description:
+ *   board_button_initialize() must be called to initialize button resources.  After
+ *   that, board_buttons() may be called to collect the current state of all
+ *   buttons or board_button_irq() may be called to register button interrupt
+ *   handlers.
+ *
+ *   After board_button_initialize() has been called, board_buttons() may be called to
+ *   collect the state of all buttons.  board_buttons() returns an 32-bit bit set
+ *   with each bit associated with a button.  See the BUTTON_*_BIT
+ *   definitions in board.h for the meaning of each bit.
+ *
+ *   board_button_irq() may be called to register an interrupt handler that will
+ *   be called when a button is depressed or released.  The ID value is a
+ *   button enumeration value that uniquely identifies a button resource. See the
+ *   BUTTON_* definitions in board.h for the meaning of enumeration
+ *   value.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_ARCH_IRQBUTTONS
+int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
+{
+  int ret = -EINVAL;
+
+  if (id == BUTTON_USER)
+    {
+      ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg);
+    }
+
+  return ret;
+}
+#endif
+#endif /* CONFIG_ARCH_BUTTONS */
diff --git a/configs/nucleo-h743zi/include/board.h b/configs/nucleo-h743zi/include/board.h
index 95d445fe9e5..e0faca428db 100644
--- a/configs/nucleo-h743zi/include/board.h
+++ b/configs/nucleo-h743zi/include/board.h
@@ -1,7 +1,7 @@
 /************************************************************************************
  * configs/nucleo-h743zi/include/board.h
  *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2018, 2019 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt 
  *            Simon Laube 
  *            Mateusz Szafoni 
@@ -199,6 +199,28 @@
 #define STM32_RCC_D3CFGR_D3PPRE   RCC_D3CFGR_D3PPRE_HCLKd4       /* PCLK4 = HCLK / 4 */
 #define STM32_PCLK4_FREQUENCY     (STM32_HCLK_FREQUENCY/4)
 
+/* Timer clock frequencies */
+
+/* Timers driven from APB1 will be twice PCLK1 */
+
+#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM12_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM13_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM14_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+
+/* Timers driven from APB2 will be twice PCLK2 */
+
+#define STM32_APB2_TIM1_CLKIN   (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN   (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM15_CLKIN  (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM16_CLKIN  (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM17_CLKIN  (2*STM32_PCLK2_FREQUENCY)
+
 /* Kernel Clock Configuration
  *
  * Note: look at Table 54 in ST Manual
@@ -250,6 +272,25 @@
 
 #define BOARD_FLASH_WAITSTATES 4
 
+/* SDMMC definitions ****************************************************************/
+
+/* Init 400kHz, PLL1Q/(2*250) */
+
+#define STM32_SDMMC_INIT_CLKDIV     (250 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+
+/* Just set these to 25 MHz for now, PLL1Q/(2*4), for default speed 12.5MB/s */
+
+#define STM32_SDMMC_MMCXFR_CLKDIV   (4 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#define STM32_SDMMC_SDXFR_CLKDIV    (4 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+
+#define STM32_SDMMC_CLKCR_EDGE      STM32_SDMMC_CLKCR_NEGEDGE
+
+/* Ethernet definitions ****************************************************************/
+
+#define GPIO_ETH_RMII_TXD0    GPIO_ETH_RMII_TXD0_2    /* PG13 */
+#define GPIO_ETH_RMII_TXD1    GPIO_ETH_RMII_TXD1_1    /* PB 13 */
+#define GPIO_ETH_RMII_TX_EN   GPIO_ETH_RMII_TX_EN_2
+
 /* LED definitions ******************************************************************/
 /* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a Blue
  * LED and LD3 a Red LED, that can be controlled by software. The following
@@ -321,10 +362,16 @@
 #define GPIO_USART6_RX     GPIO_USART6_RX_2  /* PG9 */
 #define GPIO_USART6_TX     GPIO_USART6_TX_2  /* PG14 */
 
-/* I2C1 Use Nucleo I2C pins */
+/* I2C1 Use Nucleo I2C1 pins */
 
-#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 /* PB8 */
-#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 /* PB9 */
+#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 /* PB8 - D15 */
+#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 /* PB9 - D14 */
+
+/* I2C2 Use Nucleo I2C2 pins */
+
+#define GPIO_I2C2_SCL  GPIO_I2C2_SCL_2  /* PF1 - D69 */
+#define GPIO_I2C2_SDA  GPIO_I2C2_SDA_2  /* PF0 - D68 */
+#define GPIO_I2C2_SMBA GPIO_I2C2_SMBA_2 /* PF2 - D70 */
 
 /* SPI3 */
 
@@ -333,6 +380,16 @@
 #define GPIO_SPI3_SCK  GPIO_SPI3_SCK_1  /* PB3 */
 #define GPIO_SPI3_NSS  GPIO_SPI3_NSS_2  /* PA4 */
 
+/* TIM1 */
+
+#define GPIO_TIM1_CH1OUT  GPIO_TIM1_CH1OUT_2  /* PE9  - D6 */
+#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1NOUT_3 /* PE8  - D42 */
+#define GPIO_TIM1_CH2OUT  GPIO_TIM1_CH2OUT_2  /* PE11 - D5 */
+#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2NOUT_3 /* PE10 - D40 */
+#define GPIO_TIM1_CH3OUT  GPIO_TIM1_CH3OUT_2  /* PE13 - D3 */
+#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3NOUT_3 /* PE12 - D39 */
+#define GPIO_TIM1_CH4OUT  GPIO_TIM1_CH4OUT_2  /* PE14 - D38 */
+
 /* DMA ******************************************************************************/
 
 #define DMAMAP_SPI3_RX DMAMAP_DMA12_SPI3RX_0 /* DMA1 */
diff --git a/configs/nucleo-h743zi/kernel/stm32_userspace.c b/configs/nucleo-h743zi/kernel/stm32_userspace.c
index f52bd91ac6a..8044e3a9ea5 100644
--- a/configs/nucleo-h743zi/kernel/stm32_userspace.c
+++ b/configs/nucleo-h743zi/kernel/stm32_userspace.c
@@ -115,9 +115,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/nucleo-h743zi/nsh/defconfig b/configs/nucleo-h743zi/nsh/defconfig
index a622d0d942f..23f050f31d6 100644
--- a/configs/nucleo-h743zi/nsh/defconfig
+++ b/configs/nucleo-h743zi/nsh/defconfig
@@ -5,7 +5,6 @@
 # You can then do "make savedefconfig" to generate a new defconfig file that includes your
 # modifications.
 #
-# CONFIG_ARCH_FPU is not set
 # CONFIG_NSH_DISABLE_IFCONFIG is not set
 # CONFIG_NSH_DISABLE_PS is not set
 # CONFIG_STANDARD_SERIAL is not set
@@ -22,7 +21,6 @@ CONFIG_ARMV7M_ICACHE=y
 CONFIG_BOARD_LOOPSPERMSEC=43103
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
 CONFIG_EXPERIMENTAL=y
diff --git a/configs/nucleo-h743zi/nxlines_oled/defconfig b/configs/nucleo-h743zi/nxlines_oled/defconfig
new file mode 100644
index 00000000000..a763083dfc9
--- /dev/null
+++ b/configs/nucleo-h743zi/nxlines_oled/defconfig
@@ -0,0 +1,75 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_FPU is not set
+# CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS is not set
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_NX_DISABLE_1BPP is not set
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="nucleo-h743zi"
+CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y
+CONFIG_ARCH_CHIP_STM32H743ZI=y
+CONFIG_ARCH_CHIP_STM32H7=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_DTCM=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_BOARD_LOOPSPERMSEC=43103
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_NOOPT=y
+CONFIG_EXAMPLES_NXLINES=y
+CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=1
+CONFIG_EXAMPLES_NXLINES_BPP=1
+CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xff
+CONFIG_EXAMPLES_NXLINES_LINEWIDTH=1
+CONFIG_EXPERIMENTAL=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LCD=y
+CONFIG_LCD_MAXCONTRAST=255
+CONFIG_LCD_SH1106_OLED_132=y
+CONFIG_LCD_SSD1306_I2C=y
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_MM_REGIONS=3
+CONFIG_MQ_MAXMSGSIZE=128
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_READLINE=y
+CONFIG_NX=y
+CONFIG_NXFONTS_DISABLE_1BPP=y
+CONFIG_NXFONT_MONO5X8=y
+CONFIG_NX_BLOCKING=y
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_RAM_SIZE=245760
+CONFIG_RAM_START=0x20010000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_START_DAY=6
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2011
+CONFIG_STM32H7_I2C2=y
+CONFIG_STM32H7_USART3=y
+CONFIG_SYSLOG_NONE=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_USART3_SERIAL_CONSOLE=y
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_WDOG_INTRESERVE=0
diff --git a/configs/nucleo-h743zi/src/Makefile b/configs/nucleo-h743zi/src/Makefile
index 3d08897b276..dc896ccd7ac 100644
--- a/configs/nucleo-h743zi/src/Makefile
+++ b/configs/nucleo-h743zi/src/Makefile
@@ -60,10 +60,22 @@ ifeq ($(CONFIG_SENSORS_LSM6DSL),y)
 CSRCS += stm32_lsm6dsl.c
 endif
 
+ifeq ($(CONFIG_SENSORS_LSM9DS1),y)
+CSRCS += stm32_lsm9ds1.c
+endif
+
 ifeq ($(CONFIG_SENSORS_LSM303AGR),y)
 CSRCS += stm32_lsm303agr.c
 endif
 
+ifeq ($(CONFIG_PCA9635PW),y)
+CSRCS += stm32_pca9635.c
+endif
+
+ifeq ($(CONFIG_LCD_SSD1306),y)
+CSRCS += stm32_ssd1306.c
+endif
+
 ifeq ($(CONFIG_LIB_BOARDCTL),y)
 CSRCS += stm32_appinitialize.c
 endif
diff --git a/configs/nucleo-h743zi/src/nucleo-h743zi.h b/configs/nucleo-h743zi/src/nucleo-h743zi.h
index e57bd96f860..afe775daf50 100644
--- a/configs/nucleo-h743zi/src/nucleo-h743zi.h
+++ b/configs/nucleo-h743zi/src/nucleo-h743zi.h
@@ -133,6 +133,19 @@
                             GPIO_OUTPUT_CLEAR | GPIO_PORTF | GPIO_PIN12)
 #define GPIO_NRF24L01_IRQ  (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTD | GPIO_PIN15)
 
+/* LMS9DS1 configuration */
+
+#define LMS9DS1_I2CBUS 1
+
+/* PCA9635 configuration */
+
+#define PCA9635_I2CBUS  1
+#define PCA9635_I2CADDR 0x40
+
+/* Oled configuration */
+
+#define OLED_I2C_PORT   2
+
 /************************************************************************************
  * Public Functions
  ************************************************************************************/
@@ -197,6 +210,7 @@ void stm32_usbinitialize(void);
  *
  * Description:
  *   Initialize I2C-based LSM6DSL.
+ *
  ****************************************************************************/
 
 #ifdef CONFIG_SENSORS_LSM303AGR
@@ -208,6 +222,7 @@ int stm32_lsm6dsl_initialize(char *devpath);
  *
  * Description:
  *   Initialize I2C-based LSM303AGR.
+ *
  ****************************************************************************/
 
 #ifdef CONFIG_SENSORS_LSM6DSL
@@ -225,4 +240,26 @@ int stm32_lsm303agr_initialize(char *devpath);
 int stm32_wlinitialize(void);
 #endif
 
+/*****************************************************************************
+ * Name: stm32_lsm9ds1_initialize
+ *
+ * Description:
+ *   Initialize I2C-based LSM9DS1.
+ ****************************************************************************/
+
+#ifdef CONFIG_SENSORS_LSM9DS1
+int stm32_lsm9ds1_initialize(char *devpath);
+#endif
+
+/****************************************************************************
+ * Name: stm32_pca9635_initialize
+ *
+ * Description:
+ *   Initialize I2C-based PCA9635PW LED driver.
+ ****************************************************************************/
+
+#ifdef CONFIG_PCA9635PW
+int stm32_pca9635_initialize(void);
+#endif
+
 #endif /* __CONFIGS_NUCLEO_H743ZI_SRC_NUCLEO_H743ZI_H */
diff --git a/configs/nucleo-h743zi/src/stm32_bringup.c b/configs/nucleo-h743zi/src/stm32_bringup.c
index 36e571030b1..6aa9fec9b7d 100644
--- a/configs/nucleo-h743zi/src/stm32_bringup.c
+++ b/configs/nucleo-h743zi/src/stm32_bringup.c
@@ -50,6 +50,68 @@
 #  include 
 #endif
 
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_i2c_register
+ *
+ * Description:
+ *   Register one I2C drivers for the I2C tool.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL)
+static void stm32_i2c_register(int bus)
+{
+  FAR struct i2c_master_s *i2c;
+  int ret;
+
+  i2c = stm32_i2cbus_initialize(bus);
+  if (i2c == NULL)
+    {
+      syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus);
+    }
+  else
+    {
+      ret = i2c_register(i2c, bus);
+      if (ret < 0)
+        {
+          syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n",
+                 bus, ret);
+          stm32_i2cbus_uninitialize(i2c);
+        }
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_i2ctool
+ *
+ * Description:
+ *   Register I2C drivers for the I2C tool.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL)
+static void stm32_i2ctool(void)
+{
+#ifdef CONFIG_STM32H7_I2C1
+  stm32_i2c_register(1);
+#endif
+#ifdef CONFIG_STM32H7_I2C2
+  stm32_i2c_register(2);
+#endif
+#ifdef CONFIG_STM32H7_I2C3
+  stm32_i2c_register(3);
+#endif
+#ifdef CONFIG_STM32H7_I2C4
+  stm32_i2c_register(4);
+#endif
+}
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -74,6 +136,10 @@ int stm32_bringup(void)
 
   UNUSED(ret);
 
+#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL)
+  stm32_i2ctool();
+#endif
+
 #ifdef CONFIG_FS_PROCFS
 #ifdef CONFIG_STM32_CCM_PROCFS
   /* Register the CCM procfs entry.  This must be done before the procfs is
@@ -122,6 +188,14 @@ int stm32_bringup(void)
     }
 #endif  /* CONFIG_SENSORS_LSM6DSL */
 
+#ifdef CONFIG_SENSORS_LSM9DS1
+  ret = stm32_lsm9ds1_initialize();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: Failed to initialize LSM9DS1 driver: %d\n", ret);
+    }
+#endif  /* CONFIG_SENSORS_LSM6DSL */
+
 #ifdef CONFIG_SENSORS_LSM303AGR
   ret = stm32_lsm303agr_initialize("/dev/lsm303mag0");
   if (ret < 0)
@@ -130,6 +204,16 @@ int stm32_bringup(void)
     }
 #endif  /* CONFIG_SENSORS_LSM303AGR */
 
+#ifdef CONFIG_PCA9635PW
+  /* Initialize the PCA9635 chip */
+
+  ret = stm32_pca9635_initialize();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: stm32_pca9635_initialize failed: %d\n", ret);
+    }
+#endif
+
 #ifdef CONFIG_WL_NRF24L01
   ret = stm32_wlinitialize();
   if (ret < 0)
diff --git a/configs/nucleo-h743zi/src/stm32_lsm6dsl.c b/configs/nucleo-h743zi/src/stm32_lsm6dsl.c
index 826695c6dd6..c23c6ece596 100644
--- a/configs/nucleo-h743zi/src/stm32_lsm6dsl.c
+++ b/configs/nucleo-h743zi/src/stm32_lsm6dsl.c
@@ -86,7 +86,7 @@ int stm32_lsm6dsl_initialize(char *devpath)
 
   sninfo("INFO: Initializing LMS6DSL accelero-gyro sensor over I2C%d\n", ret);
 
-  ret = lsm6dsl_sensor_register("/dev/lsm6dsl0", i2c, LSM6DSLACCEL_ADDR1);
+  ret = lsm6dsl_sensor_register(devpath, i2c, LSM6DSLACCEL_ADDR1);
   if (ret < 0)
     {
       snerr("ERROR: Failed to initialize LMS6DSL accelero-gyro driver %s\n", devpath);
diff --git a/configs/nucleo-h743zi/src/stm32_lsm9ds1.c b/configs/nucleo-h743zi/src/stm32_lsm9ds1.c
new file mode 100644
index 00000000000..b4ca3155ed0
--- /dev/null
+++ b/configs/nucleo-h743zi/src/stm32_lsm9ds1.c
@@ -0,0 +1,114 @@
+/*****************************************************************************
+ * configs/nucleo-h743zi/src/stm32_lsm9ds1.c
+ *
+ *   Copyright (C) 2019 Greg Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+#include "stm32.h"
+#include 
+#include 
+
+/*****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_STM32H7_I2C1
+#  error "LSM9DS1 driver requires CONFIG_STM32H7_I2C1 to be enabled"
+#endif
+
+#define LSM9DS1MAG_DEVPATH "/dev/lsm9ds1mag0"
+#define LSM9DS1ACC_DEVPATH "/dev/lsm9ds1acc0"
+#define LSM9DS1GYR_DEVPATH "/dev/lsm9ds1gyr0"
+
+/*****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Name: stm32_lsm9ds1_initialize
+ *
+ * Description:
+ *   Initialize I2C-based LSM9DS1.
+ ****************************************************************************/
+
+int stm32_lsm9ds1_initialize(void)
+{
+  FAR struct i2c_master_s *i2c;
+  int ret = OK;
+
+  sninfo("Initializing LMS9DS1!\n");
+
+#if defined(CONFIG_STM32H7_I2C1)
+  i2c = stm32_i2cbus_initialize(LMS9DS1_I2CBUS);
+  if (i2c == NULL)
+    {
+      return -ENODEV;
+    }
+
+  sninfo("INFO: Initializing LMS9DS1 9DoF sensor over I2C%d\n", LMS9DS1_I2CBUS);
+
+  ret = lsm9ds1mag_register(LSM9DS1MAG_DEVPATH, i2c, LSM9DS1MAG_ADDR1);
+  if (ret < 0)
+    {
+      snerr("ERROR: Failed to initialize LMS9DS1 mag driver %s\n", LSM9DS1MAG_DEVPATH);
+      return -ENODEV;
+    }
+
+  ret = lsm9ds1gyro_register(LSM9DS1GYR_DEVPATH, i2c, LSM9DS1GYRO_ADDR1);
+  if (ret < 0)
+    {
+      snerr("ERROR: Failed to initialize LMS9DS1 gyro driver %s\n", LSM9DS1MAG_DEVPATH);
+      return -ENODEV;
+    }
+
+  ret = lsm9ds1accel_register(LSM9DS1ACC_DEVPATH, i2c, LSM9DS1ACCEL_ADDR1);
+  if (ret < 0)
+    {
+      snerr("ERROR: Failed to initialize LMS9DS1 accel driver %s\n", LSM9DS1MAG_DEVPATH);
+      return -ENODEV;
+    }
+
+  sninfo("INFO: LMS9DS1 sensor has been initialized successfully\n");
+#endif
+
+  return ret;
+}
diff --git a/configs/nucleo-h743zi/src/stm32_pca9635.c b/configs/nucleo-h743zi/src/stm32_pca9635.c
new file mode 100644
index 00000000000..1d415a394d4
--- /dev/null
+++ b/configs/nucleo-h743zi/src/stm32_pca9635.c
@@ -0,0 +1,97 @@
+/************************************************************************************
+ * configs/nucleo-h743zi/src/stm32_pca9635.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+
+#include "stm32.h"
+#include "nucleo-h743zi.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_pca9635_initialize
+ *
+ * Description:
+ *   This function is called by board initialization logic to configure the
+ *   LED PWM chip.  This function will register the driver as /dev/leddrv0.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero is returned on success.  Otherwise, a negated errno value is
+ *   returned to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int stm32_pca9635_initialize(void)
+{
+  FAR struct i2c_master_s *i2c;
+  int ret;
+
+  /* Get the I2C driver that interfaces with the pca9635 */
+
+  i2c = stm32_i2cbus_initialize(PCA9635_I2CBUS);
+  if (!i2c)
+    {
+      i2cerr("ERROR: Failed to initialize I2C%d\n", PCA9635_I2CBUS);
+      return -1;
+    }
+
+  ret = pca9635pw_register("/dev/leddrv0", i2c, PCA9635_I2CADDR);
+  if (ret < 0)
+    {
+      snerr("ERROR: Failed to register PCA9635 driver: %d\n", ret);
+      return ret;
+    }
+
+  return OK;
+}
diff --git a/configs/nucleo-h743zi/src/stm32_ssd1306.c b/configs/nucleo-h743zi/src/stm32_ssd1306.c
new file mode 100644
index 00000000000..cd52bc3c049
--- /dev/null
+++ b/configs/nucleo-h743zi/src/stm32_ssd1306.c
@@ -0,0 +1,124 @@
+/****************************************************************************
+ * config/nucleo-h743zi/src/stm32_ssd1306.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "stm32.h"
+#include "nucleo-h743zi.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#ifndef CONFIG_LCD_MAXPOWER
+#  define CONFIG_LCD_MAXPOWER 1
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+FAR struct i2c_master_s *g_i2c;
+FAR struct lcd_dev_s    *g_lcddev;
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_lcd_initialize
+ ****************************************************************************/
+
+int board_lcd_initialize(void)
+{
+  /* Initialize I2C */
+
+  g_i2c = stm32_i2cbus_initialize(OLED_I2C_PORT);
+  if (!g_i2c)
+    {
+      lcderr("ERROR: Failed to initialize I2C port %d\n", OLED_I2C_PORT);
+      return -ENODEV;
+    }
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name: board_lcd_getdev
+ ****************************************************************************/
+
+FAR struct lcd_dev_s *board_lcd_getdev(int devno)
+{
+  /* Bind the I2C port to the OLED */
+
+  g_lcddev = ssd1306_initialize(g_i2c, NULL, devno);
+  if (!g_lcddev)
+    {
+      lcderr("ERROR: Failed to bind I2C port 1 to OLED %d: %d\n", devno);
+    }
+  else
+    {
+      lcdinfo("Bound I2C port %d to OLED %d\n", OLED_I2C_PORT, devno);
+
+      /* And turn the OLED on */
+
+      (void)g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER);
+      return g_lcddev;
+    }
+
+  return NULL;
+}
+
+/****************************************************************************
+ * Name: board_lcd_uninitialize
+ ****************************************************************************/
+
+void board_lcd_uninitialize(void)
+{
+  /* TO-FIX */
+}
diff --git a/configs/nucleo-l073rz/include/board.h b/configs/nucleo-l073rz/include/board.h
index 62d0e6fc09e..844e2373f93 100644
--- a/configs/nucleo-l073rz/include/board.h
+++ b/configs/nucleo-l073rz/include/board.h
@@ -99,6 +99,14 @@
 #define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd2
 #define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
 
+/* 48MHz clock configuration */
+
+#if defined(CONFIG_STM32F0L0G0_USB) || defined(CONFIG_STM32F0L0G0_RNG)
+#  define STM32_USE_CLK48       1
+#  define STM32_CLK48_SEL       RCC_CCIPR_CLK48SEL_HSI48
+#  define STM32_HSI48_SYNCSRC   SYNCSRC_NONE
+#endif
+
 /* TODO: timers */
 
 /* LED definitions **********************************************************/
diff --git a/configs/nucleo-l073rz/nsh/defconfig b/configs/nucleo-l073rz/nsh/defconfig
index 9538d685844..eb2a814fe4c 100644
--- a/configs/nucleo-l073rz/nsh/defconfig
+++ b/configs/nucleo-l073rz/nsh/defconfig
@@ -18,7 +18,6 @@ CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 CONFIG_EXAMPLES_HELLO=y
@@ -48,8 +47,8 @@ CONFIG_START_DAY=19
 CONFIG_START_MONTH=5
 CONFIG_START_YEAR=2013
 CONFIG_STDIO_DISABLE_BUFFERING=y
-CONFIG_STM32F0L0_PWR=y
-CONFIG_STM32F0L0_USART2=y
+CONFIG_STM32F0L0G0_PWR=y
+CONFIG_STM32F0L0G0_USART2=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_TASK_NAME_SIZE=0
 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
diff --git a/configs/nucleo-l073rz/scripts/ld.script b/configs/nucleo-l073rz/scripts/ld.script
index 9848160d2c1..be88db993f8 100644
--- a/configs/nucleo-l073rz/scripts/ld.script
+++ b/configs/nucleo-l073rz/scripts/ld.script
@@ -52,73 +52,77 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The RAM vector table (if present) should lie at the beginning of SRAM */
+        /* The RAM vector table (if present) should lie at the beginning of SRAM */
 
-	.ram_vectors : {
-		*(.ram_vectors)
-	} > sram
+        .ram_vectors : {
+                *(.ram_vectors)
+        } > sram
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/nucleo-l073rz/src/Makefile b/configs/nucleo-l073rz/src/Makefile
index eb04a71a456..908bf72df8d 100644
--- a/configs/nucleo-l073rz/src/Makefile
+++ b/configs/nucleo-l073rz/src/Makefile
@@ -48,7 +48,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
 CSRCS += stm32_buttons.c
 endif
 
-ifeq ($(CONFIG_STM32F0L0_SPI),y)
+ifeq ($(CONFIG_STM32F0L0G0_SPI),y)
 CSRCS += stm32_spi.c
 endif
 
diff --git a/configs/nucleo-l073rz/src/nucleo-l073rz.h b/configs/nucleo-l073rz/src/nucleo-l073rz.h
index c770ad0c506..92506d51243 100644
--- a/configs/nucleo-l073rz/src/nucleo-l073rz.h
+++ b/configs/nucleo-l073rz/src/nucleo-l073rz.h
@@ -153,7 +153,7 @@ int stm32_bringup(void);
  *
  ****************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI
+#ifdef CONFIG_STM32F0L0G0_SPI
 void stm32_spidev_initialize(void);
 #endif
 
diff --git a/configs/nucleo-l073rz/src/stm32_boot.c b/configs/nucleo-l073rz/src/stm32_boot.c
index 55b39892327..5ba03724316 100644
--- a/configs/nucleo-l073rz/src/stm32_boot.c
+++ b/configs/nucleo-l073rz/src/stm32_boot.c
@@ -83,7 +83,7 @@ void stm32_boardinitialize(void)
   board_autoled_initialize();
 #endif
 
-#ifdef CONFIG_STM32F0L0_SPI
+#ifdef CONFIG_STM32F0L0G0_SPI
   /* Configure SPI chip selects */
 
   stm32_spidev_initialize();
diff --git a/configs/nucleo-l073rz/src/stm32_mfrc522.c b/configs/nucleo-l073rz/src/stm32_mfrc522.c
index e6ccb66807b..97c13d9d7f5 100644
--- a/configs/nucleo-l073rz/src/stm32_mfrc522.c
+++ b/configs/nucleo-l073rz/src/stm32_mfrc522.c
@@ -49,7 +49,7 @@
 #include "stm32_spi.h"
 #include "nucleo-l073rz.h"
 
-#if defined(CONFIG_SPI) && defined(CONFIG_STM32F0L0_SPI2) && defined(CONFIG_CL_MFRC522)
+#if defined(CONFIG_SPI) && defined(CONFIG_STM32F0L0G0_SPI2) && defined(CONFIG_CL_MFRC522)
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/configs/nucleo-l073rz/src/stm32_spi.c b/configs/nucleo-l073rz/src/stm32_spi.c
index de68edcdfae..5fec5218b67 100644
--- a/configs/nucleo-l073rz/src/stm32_spi.c
+++ b/configs/nucleo-l073rz/src/stm32_spi.c
@@ -54,7 +54,7 @@
 #include "nucleo-l073rz.h"
 #include 
 
-#ifdef CONFIG_STM32F0L0_SPI
+#ifdef CONFIG_STM32F0L0G0_SPI
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -92,7 +92,7 @@ void stm32_spidev_initialize(void)
    *       architecture.
    */
 
-#ifdef CONFIG_STM32F0L0_SPI1
+#ifdef CONFIG_STM32F0L0G0_SPI1
 
 #  ifdef CONFIG_WL_NRF24L01
   /* Configure the SPI-based NRF24L01 chip select GPIO */
@@ -112,16 +112,16 @@ void stm32_spidev_initialize(void)
   stm32_gpiowrite(GPIO_SX127X_CS, true);
 #  endif
 
-#endif  /*  CONFIG_STM32F0L0_SPI1 */
+#endif  /*  CONFIG_STM32F0L0G0_SPI1 */
 
-#ifdef CONFIG_STM32F0L0_SPI2
+#ifdef CONFIG_STM32F0L0G0_SPI2
   /* Configure the SPI-based MFRC522 chip select GPIO */
 
 #  ifdef CONFIG_CL_MFRC522
   (void)stm32_configgpio(GPIO_MFRC522_CS);
 #  endif
 
-#endif  /* CONFIG_STM32F0L0_SPI2 */
+#endif  /* CONFIG_STM32F0L0G0_SPI2 */
 }
 
 /****************************************************************************
@@ -150,7 +150,7 @@ void stm32_spidev_initialize(void)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_STM32F0L0_SPI1
+#ifdef CONFIG_STM32F0L0G0_SPI1
 void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
 {
   spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
@@ -215,9 +215,9 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
 
   return status;
 }
-#endif  /* CONFIG_STM32F0L0_SPI1 */
+#endif  /* CONFIG_STM32F0L0G0_SPI1 */
 
-#ifdef CONFIG_STM32F0L0_SPI2
+#ifdef CONFIG_STM32F0L0G0_SPI2
 void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid,
                       bool selected)
 {
@@ -259,6 +259,6 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid)
 
   return status;
 }
-#endif  /* CONFIG_STM32F0L0_SPI2 */
+#endif  /* CONFIG_STM32F0L0G0_SPI2 */
 
 #endif
diff --git a/configs/nucleo-l073rz/sx127x/defconfig b/configs/nucleo-l073rz/sx127x/defconfig
index ca56a11c4e8..2ce7ee17382 100644
--- a/configs/nucleo-l073rz/sx127x/defconfig
+++ b/configs/nucleo-l073rz/sx127x/defconfig
@@ -20,7 +20,6 @@ CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 CONFIG_DRIVERS_LPWAN=y
@@ -59,9 +58,9 @@ CONFIG_START_DAY=19
 CONFIG_START_MONTH=5
 CONFIG_START_YEAR=2013
 CONFIG_STDIO_DISABLE_BUFFERING=y
-CONFIG_STM32F0L0_PWR=y
-CONFIG_STM32F0L0_SPI1=y
-CONFIG_STM32F0L0_USART2=y
+CONFIG_STM32F0L0G0_PWR=y
+CONFIG_STM32F0L0G0_SPI1=y
+CONFIG_STM32F0L0G0_USART2=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_TASK_NAME_SIZE=0
 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
diff --git a/configs/nucleo-l152re/nsh/defconfig b/configs/nucleo-l152re/nsh/defconfig
index 524e1cef72e..7358d104bb1 100644
--- a/configs/nucleo-l152re/nsh/defconfig
+++ b/configs/nucleo-l152re/nsh/defconfig
@@ -20,7 +20,6 @@ CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
 CONFIG_EXAMPLES_HELLO=y
diff --git a/configs/nucleo-l152re/scripts/ld.script b/configs/nucleo-l152re/scripts/ld.script
index e65d6be3e18..392ebf1ce1e 100644
--- a/configs/nucleo-l152re/scripts/ld.script
+++ b/configs/nucleo-l152re/scripts/ld.script
@@ -52,73 +52,77 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The RAM vector table (if present) should lie at the beginning of SRAM */
+        /* The RAM vector table (if present) should lie at the beginning of SRAM */
 
-	.ram_vectors : {
-		*(.ram_vectors)
-	} > sram
+        .ram_vectors : {
+                *(.ram_vectors)
+        } > sram
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/nucleo-l432kc/include/board.h b/configs/nucleo-l432kc/include/board.h
index af99458cfda..b7143bcb55e 100644
--- a/configs/nucleo-l432kc/include/board.h
+++ b/configs/nucleo-l432kc/include/board.h
@@ -64,7 +64,7 @@
  * is we set aside more DMA channels/streams.
  */
 
-/* Values defined in arch/arm/src/stm32l4/chip/stm32l4x3xx_dma.h */
+/* Values defined in arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h */
 
 #define DMACHAN_SPI1_RX DMACHAN_SPI1_RX_1 /* 2 choices */
 #define DMACHAN_SPI1_TX DMACHAN_SPI1_TX_1 /* 2 choices */
diff --git a/configs/nucleo-l432kc/include/nucleo-l432kc.h b/configs/nucleo-l432kc/include/nucleo-l432kc.h
index 1dbbe4fe55f..1100a2348c1 100644
--- a/configs/nucleo-l432kc/include/nucleo-l432kc.h
+++ b/configs/nucleo-l432kc/include/nucleo-l432kc.h
@@ -255,8 +255,11 @@
 
 /* CLK48 will come from PLLSAI1 (implicitly Q) */
 
-#define STM32L4_USE_CLK48
-#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG)
+#  define STM32L4_USE_CLK48       1
+#  define STM32L4_CLK48_SEL       RCC_CCIPR_CLK48SEL_PLLSAI1
+#  define STM32L4_HSI48_SYNCSRC   SYNCSRC_NONE
+#endif
 
 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */
 
@@ -348,8 +351,11 @@
 
 /* Enable CLK48; get it from PLLSAI1 */
 
-#define STM32L4_USE_CLK48
-#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG)
+#  define STM32L4_USE_CLK48       1
+#  define STM32L4_CLK48_SEL       RCC_CCIPR_CLK48SEL_PLLSAI1
+#  define STM32L4_HSI48_SYNCSRC   SYNCSRC_NONE
+#endif
 
 /* Enable LSE (for the RTC) */
 
@@ -440,8 +446,11 @@
 
 /* Enable CLK48; get it from PLLSAI1 */
 
-#define STM32L4_USE_CLK48
-#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG)
+#  define STM32L4_USE_CLK48       1
+#  define STM32L4_CLK48_SEL       RCC_CCIPR_CLK48SEL_PLLSAI1
+#  define STM32L4_HSI48_SYNCSRC   SYNCSRC_NONE
+#endif
 
 /* Enable LSE (for the RTC) */
 
diff --git a/configs/nucleo-l432kc/nsh/defconfig b/configs/nucleo-l432kc/nsh/defconfig
index 2d563bf90f9..98eb2acbc92 100644
--- a/configs/nucleo-l432kc/nsh/defconfig
+++ b/configs/nucleo-l432kc/nsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
 CONFIG_BOARD_LOOPSPERMSEC=8499
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_ALARM=y
 CONFIG_EXAMPLES_RANDOM=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/nucleo-l432kc/src/stm32_dac7571.c b/configs/nucleo-l432kc/src/stm32_dac7571.c
index 2eb48366e88..c51cec7d420 100644
--- a/configs/nucleo-l432kc/src/stm32_dac7571.c
+++ b/configs/nucleo-l432kc/src/stm32_dac7571.c
@@ -1,129 +1,129 @@
-/************************************************************************************
- * configs/nucleo-l432kc/src/stm32_dac7571.c
- *
- *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt 
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ************************************************************************************/
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include 
-
-#include 
-#include 
-#include 
-#include 
-
-#include 
-#include 
-#include 
-
-#include 
-#include 
-
-#if defined(CONFIG_I2C) && defined(CONFIG_STM32L4_I2C1) && defined(CONFIG_DAC7571) 
-
-/************************************************************************************
- * Preprocessor definitions
- ************************************************************************************/
-
-#if !defined(CONFIG_DAC7571_ADDR)
-#  define CONFIG_DAC7571_ADDR 0x4C  /* A0 tied to ground */
-#endif
-
-/************************************************************************************
- * Private Data
- ************************************************************************************/
-
-static struct dac_dev_s *g_dac;
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Name: stm32_dac7571initialize
- *
- * Description:
- *   Initialize and register the DAC7571 DAC driver.
- *
- * Input Parameters:
- *   devpath - The full path to the driver to register. E.g., "/dev/dac0"
- *
- * Returned Value:
- *   Zero (OK) on success; a negated errno value on failure.
- *
- ************************************************************************************/
-
-int stm32_dac7571initialize(FAR const char *devpath)
-{
-  FAR struct i2c_master_s *i2c;
-  int ret;
-
-  /* Configure D4(PA5) and D5(PA6) as input floating */
-
-  stm32l4_configgpio(GPIO_I2C1_D4);
-  stm32l4_configgpio(GPIO_I2C1_D5);
-
-  /* Get an instance of the I2C1 interface */
-
-  i2c =  stm32l4_i2cbus_initialize(1);
-  if (!i2c)
-    {
-      return -ENODEV;
-    }
-
-  /* Then initialize and register DAC7571 */
-
-  g_dac = dac7571_initialize(i2c, CONFIG_DAC7571_ADDR);
-  if (!g_dac)
-    {
-      ret = -ENODEV;
-      goto error;
-    }
-
-  ret = dac_register(devpath, g_dac);
-  if (ret < 0)
-    {
-      aerr("ERROR: dac_register failed: %d\n", ret);
-      goto error;
-    }
-
-  return OK;
-
-error:
-  (void)stm32l4_i2cbus_uninitialize(i2c);
-  return ret;
-}
-
-#endif /* defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) && defined(CONFIG_DAC7571) */
+/************************************************************************************
+ * configs/nucleo-l432kc/src/stm32_dac7571.c
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "chip.h"
+#include 
+
+#if defined(CONFIG_I2C) && defined(CONFIG_STM32L4_I2C1) && defined(CONFIG_DAC7571) 
+
+/************************************************************************************
+ * Preprocessor definitions
+ ************************************************************************************/
+
+#if !defined(CONFIG_DAC7571_ADDR)
+#  define CONFIG_DAC7571_ADDR 0x4C  /* A0 tied to ground */
+#endif
+
+/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+
+static struct dac_dev_s *g_dac;
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_dac7571initialize
+ *
+ * Description:
+ *   Initialize and register the DAC7571 DAC driver.
+ *
+ * Input Parameters:
+ *   devpath - The full path to the driver to register. E.g., "/dev/dac0"
+ *
+ * Returned Value:
+ *   Zero (OK) on success; a negated errno value on failure.
+ *
+ ************************************************************************************/
+
+int stm32_dac7571initialize(FAR const char *devpath)
+{
+  FAR struct i2c_master_s *i2c;
+  int ret;
+
+  /* Configure D4(PA5) and D5(PA6) as input floating */
+
+  stm32l4_configgpio(GPIO_I2C1_D4);
+  stm32l4_configgpio(GPIO_I2C1_D5);
+
+  /* Get an instance of the I2C1 interface */
+
+  i2c =  stm32l4_i2cbus_initialize(1);
+  if (!i2c)
+    {
+      return -ENODEV;
+    }
+
+  /* Then initialize and register DAC7571 */
+
+  g_dac = dac7571_initialize(i2c, CONFIG_DAC7571_ADDR);
+  if (!g_dac)
+    {
+      ret = -ENODEV;
+      goto error;
+    }
+
+  ret = dac_register(devpath, g_dac);
+  if (ret < 0)
+    {
+      aerr("ERROR: dac_register failed: %d\n", ret);
+      goto error;
+    }
+
+  return OK;
+
+error:
+  (void)stm32l4_i2cbus_uninitialize(i2c);
+  return ret;
+}
+
+#endif /* defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) && defined(CONFIG_DAC7571) */
diff --git a/configs/nucleo-l432kc/src/stm32_ina226.c b/configs/nucleo-l432kc/src/stm32_ina226.c
index f008017b476..263acf8a04e 100644
--- a/configs/nucleo-l432kc/src/stm32_ina226.c
+++ b/configs/nucleo-l432kc/src/stm32_ina226.c
@@ -48,7 +48,7 @@
 #include 
 #include 
 
-#include 
+#include "chip.h"
 #include 
 
 #if defined(CONFIG_I2C) && defined(CONFIG_STM32L4_I2C1) && defined(CONFIG_SENSORS_INA226) 
diff --git a/configs/nucleo-l432kc/src/stm32_spi.c b/configs/nucleo-l432kc/src/stm32_spi.c
index 77599af8141..396735148da 100644
--- a/configs/nucleo-l432kc/src/stm32_spi.c
+++ b/configs/nucleo-l432kc/src/stm32_spi.c
@@ -48,7 +48,7 @@
 #include 
 
 #include 
-#include 
+#include "chip.h"
 #include 
 
 #include "nucleo-l432kc.h"
diff --git a/configs/nucleo-l452re/include/board.h b/configs/nucleo-l452re/include/board.h
index 2fa0c52f7c0..f617e885e18 100644
--- a/configs/nucleo-l452re/include/board.h
+++ b/configs/nucleo-l452re/include/board.h
@@ -60,7 +60,7 @@
  * is we set aside more DMA channels/streams.
  */
 
-/* Values defined in arch/arm/src/stm32l4/chip/stm32l4x3xx_dma.h */
+/* Values defined in arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h */
 
 #define DMACHAN_SDMMC DMACHAN_SDMMC_1     /* 2 choices */
 
diff --git a/configs/nucleo-l452re/include/nucleo-l452re.h b/configs/nucleo-l452re/include/nucleo-l452re.h
index 834f745ac69..f1799b9107d 100644
--- a/configs/nucleo-l452re/include/nucleo-l452re.h
+++ b/configs/nucleo-l452re/include/nucleo-l452re.h
@@ -49,19 +49,8 @@
  * Pre-processor Definitions
  ************************************************************************************/
 
-#if 1
-#  define HSI_CLOCK_CONFIG          /* HSI-16 clock configuration */
-#elif 0
-/* Make sure you installed one! */
-
-#  define HSE_CLOCK_CONFIG          /* HSE with 8 MHz xtal */
-#else
-#  define MSI_CLOCK_CONFIG          /* MSI @ 4 MHz autotrimmed via LSE */
-#endif
-
 /* Clocking *************************************************************************/
 
-#if defined(HSI_CLOCK_CONFIG)
 /* The NUCLEOL452RE supports both HSE and LSE crystals (X2 and X3).  However, as
  * shipped, the X3 crystal is not populated.  Therefore the Nucleo-L452RE
  * will need to run off the 16MHz HSI clock, or the 32khz-synced MSI.
@@ -97,6 +86,18 @@
 #define STM32L4_LSI_FREQUENCY     32000
 #define STM32L4_LSE_FREQUENCY     32768
 
+#if 1
+#  define HSI_CLOCK_CONFIG          /* HSI-16 clock configuration */
+#elif 0
+/* Make sure you installed one! */
+
+#  define HSE_CLOCK_CONFIG          /* HSE with 8 MHz xtal */
+#else
+#  define MSI_CLOCK_CONFIG          /* MSI @ 4 MHz autotrimmed via LSE */
+#endif
+
+#if defined(HSI_CLOCK_CONFIG)
+
 #define STM32L4_BOARD_USEHSI      1
 
 /* XXX sysclk mux = pllclk */
@@ -223,23 +224,13 @@
 #define STM32L4_PLLCFG_PLLR             RCC_PLLCFG_PLLR(2)
 #define STM32L4_PLLCFG_PLLR_ENABLED
 
-/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't
- * do that with the main PLL's N value.  We set N = 12, and enable
- * the Q output (ultimately for CLK48) with /4.  So,
- * 16 MHz / 1 * 12 / 4 = 48 MHz
- *
- * XXX NOTE:  currently the SAIPLL /must/ be explicitly selected in the
- * menuconfig, or else all this is a moot point, and the various 48 MHz
- * peripherals will not work (RNG at present).  I would suggest removing
- * that option from Kconfig altogether, and simply making it an option
- * that is selected via a #define here, like all these other params.
- */
+/* 'SAIPLL1' is not used in this application */
 
 #define STM32L4_PLLSAI1CFG_PLLN         RCC_PLLSAI1CFG_PLLN(12)
 #define STM32L4_PLLSAI1CFG_PLLP         0
 #undef  STM32L4_PLLSAI1CFG_PLLP_ENABLED
-#define STM32L4_PLLSAI1CFG_PLLQ         RCC_PLLSAI1CFG_PLLQ_4
-#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLQ         0
+#undef  STM32L4_PLLSAI1CFG_PLLQ_ENABLED
 #define STM32L4_PLLSAI1CFG_PLLR         0
 #undef  STM32L4_PLLSAI1CFG_PLLR_ENABLED
 
@@ -253,10 +244,13 @@
 
 #define STM32L4_SYSCLK_FREQUENCY  80000000ul
 
-/* CLK48 will come from PLLSAI1 (implicitly Q) */
+/* CLK48 will come from HSI48 */
 
-#define STM32L4_USE_CLK48
-#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG)
+#  define STM32L4_USE_CLK48       1
+#  define STM32L4_CLK48_SEL       RCC_CCIPR_CLK48SEL_HSI48
+#  define STM32L4_HSI48_SYNCSRC   SYNCSRC_NONE
+#endif
 
 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */
 
@@ -351,8 +345,11 @@
 
 /* Enable CLK48; get it from PLLSAI1 */
 
-#define STM32L4_USE_CLK48
-#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG)
+#  define STM32L4_USE_CLK48       1
+#  define STM32L4_CLK48_SEL       RCC_CCIPR_CLK48SEL_PLLSAI1
+#  define STM32L4_HSI48_SYNCSRC   SYNCSRC_NONE
+#endif
 
 /* Enable LSE (for the RTC) */
 
@@ -410,13 +407,13 @@
 #define STM32L4_PLLCFG_PLLR             RCC_PLLCFG_PLLR_2
 #define STM32L4_PLLCFG_PLLR_ENABLED
 
-/* 'SAIPLL1' is used to generate the 48 MHz clock */
+/* 'SAIPLL1' is not used in this application */
 
 #define STM32L4_PLLSAI1CFG_PLLN         RCC_PLLSAI1CFG_PLLN(24)
 #define STM32L4_PLLSAI1CFG_PLLP         0
 #undef  STM32L4_PLLSAI1CFG_PLLP_ENABLED
-#define STM32L4_PLLSAI1CFG_PLLQ         RCC_PLLSAI1CFG_PLLQ_2
-#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLQ         0
+#undef STM32L4_PLLSAI1CFG_PLLQ_ENABLED
 #define STM32L4_PLLSAI1CFG_PLLR         0
 #undef  STM32L4_PLLSAI1CFG_PLLR_ENABLED
 
@@ -430,10 +427,13 @@
 
 #define STM32L4_SYSCLK_FREQUENCY  80000000ul
 
-/* Enable CLK48; get it from PLLSAI1 */
+/* Enable CLK48; get it from HSI48 */
 
-#define STM32L4_USE_CLK48
-#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG)
+#  define STM32L4_USE_CLK48       1
+#  define STM32L4_CLK48_SEL       RCC_CCIPR_CLK48SEL_HSI48
+#  define STM32L4_HSI48_SYNCSRC   SYNCSRC_NONE
+#endif
 
 /* Enable LSE (for the RTC) */
 
diff --git a/configs/nucleo-l452re/src/stm32_spi.c b/configs/nucleo-l452re/src/stm32_spi.c
index 70c06424522..2748508730b 100644
--- a/configs/nucleo-l452re/src/stm32_spi.c
+++ b/configs/nucleo-l452re/src/stm32_spi.c
@@ -47,7 +47,7 @@
 #include 
 
 #include 
-#include 
+#include "chip.h"
 #include 
 
 #include "nucleo-l452re.h"
diff --git a/configs/nucleo-l476rg/include/board.h b/configs/nucleo-l476rg/include/board.h
index a9fa9bc1ac8..41937ff21d8 100644
--- a/configs/nucleo-l476rg/include/board.h
+++ b/configs/nucleo-l476rg/include/board.h
@@ -62,7 +62,7 @@
  * is we set aside more DMA channels/streams.
  */
 
-/* Values defined in arch/arm/src/stm32l4/chip/stm32l4x6xx_dma.h */
+/* Values defined in arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h */
 
 #define DMACHAN_SDMMC DMACHAN_SDMMC_1     /* 2 choices */
 
diff --git a/configs/nucleo-l476rg/nsh/defconfig b/configs/nucleo-l476rg/nsh/defconfig
index 2159bffd620..eca703604b2 100644
--- a/configs/nucleo-l476rg/nsh/defconfig
+++ b/configs/nucleo-l476rg/nsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
 CONFIG_BOARD_LOOPSPERMSEC=8499
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_ALARM=y
 CONFIG_EXAMPLES_RANDOM=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/nucleo-l476rg/nxdemo/defconfig b/configs/nucleo-l476rg/nxdemo/defconfig
index 86d013f8a64..f0fdf6ce4b7 100644
--- a/configs/nucleo-l476rg/nxdemo/defconfig
+++ b/configs/nucleo-l476rg/nxdemo/defconfig
@@ -23,7 +23,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
 CONFIG_BOARD_LOOPSPERMSEC=8499
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NXHELLO=y
 CONFIG_EXAMPLES_NXHELLO_BPP=1
 CONFIG_HAVE_CXX=y
diff --git a/configs/nucleo-l476rg/src/Makefile b/configs/nucleo-l476rg/src/Makefile
index d06c4871429..19c2d1f952c 100644
--- a/configs/nucleo-l476rg/src/Makefile
+++ b/configs/nucleo-l476rg/src/Makefile
@@ -93,6 +93,14 @@ ifeq ($(CONFIG_SENSORS_LSM303AGR),y)
 CSRCS += stm32_lsm303agr.c
 endif
 
+ifeq ($(CONFIG_SENSORS_AS726X),y)
+CSRCS += stm32_as726x.c
+endif
+
+ifeq ($(CONFIG_SENSORS_BMP180),y)
+CSRCS += stm32_bmp180.c
+endif
+
 ifeq ($(CONFIG_PWM),y)
 CSRCS += stm32_pwm.c
 endif
diff --git a/configs/nucleo-l476rg/src/nucleo-l476rg.h b/configs/nucleo-l476rg/src/nucleo-l476rg.h
index 344235ac8eb..eef6e74480a 100644
--- a/configs/nucleo-l476rg/src/nucleo-l476rg.h
+++ b/configs/nucleo-l476rg/src/nucleo-l476rg.h
@@ -312,7 +312,7 @@ void stm32l4_spiinitialize(void);
 void stm32l4_usbinitialize(void);
 
 /****************************************************************************
- * Name: stm32_gpio_initialize
+ * Name: stm32l4_gpio_initialize
  *
  * Description:
  *   Initialize GPIO drivers for use with /apps/examples/gpio
@@ -410,7 +410,7 @@ int stm32l4_qencoder_initialize(FAR const char *devpath, int timer);
 #endif
 
 /****************************************************************************
- * Name: stm32_cc1101_initialize
+ * Name: stm32l4_cc1101_initialize
  *
  * Description:
  *   Initialize and register the cc1101 radio driver
@@ -418,7 +418,31 @@ int stm32l4_qencoder_initialize(FAR const char *devpath, int timer);
  ****************************************************************************/
 
 #ifdef CONFIG_WL_CC1101
-int stm32_cc1101_initialize(void);
+int stm32l4_cc1101_initialize(void);
+#endif
+
+/****************************************************************************
+ * Name: stm32_as726xinitialize
+ *
+ * Description:
+ * Called to configure an I2C and to register AS726X.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SENSORS_AS726X
+int stm32_as726xinitialize(FAR const char *devpath);
+#endif
+
+/****************************************************************************
+ * Name: stm32_bmp180initialize
+ *
+ * Description:
+ * Called to configure an I2C and to register BMP180.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SENSORS_BMP180
+int stm32_bmp180initialize(FAR const char *devpath);
 #endif
 
 #endif /* __CONFIGS_NUCLEO_L476RG_SRC_NUCLEO_L476RG_H */
diff --git a/configs/nucleo-l476rg/src/stm32_ajoystick.c b/configs/nucleo-l476rg/src/stm32_ajoystick.c
index 2daeaf01db6..e1f825fae40 100644
--- a/configs/nucleo-l476rg/src/stm32_ajoystick.c
+++ b/configs/nucleo-l476rg/src/stm32_ajoystick.c
@@ -50,7 +50,7 @@
 
 #include "stm32l4_gpio.h"
 #include "stm32l4_adc.h"
-#include "chip/stm32l4_adc.h"
+#include "hardware/stm32l4_adc.h"
 #include "nucleo-l476rg.h"
 
 /****************************************************************************
diff --git a/configs/nucleo-l476rg/src/stm32_appinit.c b/configs/nucleo-l476rg/src/stm32_appinit.c
index a1e04c5dc43..4bbd25771f5 100644
--- a/configs/nucleo-l476rg/src/stm32_appinit.c
+++ b/configs/nucleo-l476rg/src/stm32_appinit.c
@@ -82,6 +82,59 @@
 #  define MMCSD_MINOR       0
 #endif
 
+/****************************************************************************
+ * Name: stm32_i2c_register
+ *
+ * Description:
+ *   Register one I2C drivers for the I2C tool.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL)
+static void stm32_i2c_register(int bus)
+{
+  FAR struct i2c_master_s *i2c;
+  int ret;
+
+  i2c = stm32l4_i2cbus_initialize(bus);
+  if (i2c == NULL)
+  {
+    syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus);
+  }
+  else
+  {
+    ret = i2c_register(i2c, bus);
+    if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n",
+             bus, ret);
+      stm32l4_i2cbus_uninitialize(i2c);
+    }
+  }
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_i2ctool
+ *
+ * Description:
+ *   Register I2C drivers for the I2C tool.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL)
+static void stm32_i2ctool(void)
+{
+  stm32_i2c_register(1);
+#if 0
+  stm32_i2c_register(1);
+  stm32_i2c_register(2);
+#endif
+}
+#else
+#  define stm32_i2ctool()
+#endif
+
 /****************************************************************************
  * Name: board_app_initialize
  *
@@ -112,6 +165,11 @@ int board_app_initialize(uintptr_t arg)
 #ifdef HAVE_RTC_DRIVER
   FAR struct rtc_lowerhalf_s *rtclower;
 #endif
+
+#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL)
+  stm32_i2ctool();
+#endif
+
 #ifdef CONFIG_SENSORS_QENCODER
   int index;
   char buf[9];
@@ -190,6 +248,24 @@ int board_app_initialize(uintptr_t arg)
   syslog(LOG_INFO, "[boot] Initialized SDIO\n");
 #endif
 
+#ifdef CONFIG_SENSORS_AS726X
+  ret = stm32_as726xinitialize("/dev/spectr0");
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "Failed to initialize AS726X, error %d\n", ret);
+      return ret;
+    }
+#endif
+
+#ifdef CONFIG_SENSORS_BMP180
+  ret = stm32_bmp180initialize("/dev/press0");
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "Failed to initialize BMP180, error %d\n", ret);
+      return ret;
+    }
+#endif
+
 #ifdef CONFIG_PWM
   /* Initialize PWM and register the PWM device. */
 
@@ -370,11 +446,11 @@ int board_app_initialize(uintptr_t arg)
 #ifdef CONFIG_WL_CC1101
   /* Initialize and register the cc1101 radio */
 
-  ret = stm32_cc1101_initialize();
+  ret = stm32l4_cc1101_initialize();
   if (ret < 0)
     {
       syslog(LOG_ERR,
-             "ERROR: stm32_cc1101_initialize failed: %d\n",
+             "ERROR: stm32l4_cc1101_initialize failed: %d\n",
              ret);
       return ret;
     }
diff --git a/configs/nucleo-l476rg/src/stm32_as726x.c b/configs/nucleo-l476rg/src/stm32_as726x.c
new file mode 100644
index 00000000000..da398608b43
--- /dev/null
+++ b/configs/nucleo-l476rg/src/stm32_as726x.c
@@ -0,0 +1,103 @@
+/************************************************************************************
+ * configs/nucleo-l476rg/src/stm32_as726x.c
+ *
+ *   Copyright (C) 2019 Fabian Justi. All rights reserved.
+ *   Author: Fabian Justi 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+
+#include "stm32l4.h"
+#include "stm32l4_i2c.h"
+#include "nucleo-l476rg.h"
+
+#if defined(CONFIG_I2C) && defined(CONFIG_SENSORS_AS726X)
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_as726xinitialize
+ *
+ * Description:
+ *   Initialize and register the AS726X Spectral sensor.
+ *
+ * Input Parameters:
+ *   devpath - The full path to the driver to register. E.g., "/dev/spectr0"
+ *
+ * Returned Value:
+ *   Zero (OK) on success; a negated errno value on failure.
+ *
+ ************************************************************************************/
+
+int stm32_as726xinitialize(FAR const char *devpath)
+{
+  FAR struct i2c_master_s *i2c;
+  int ret;
+
+  sninfo("Initializing AS726X!\n");
+
+  /* Initialize I2C */
+
+  i2c = stm32l4_i2cbus_initialize(AS726X_I2C_PORTNO);
+
+  if (!i2c)
+    {
+      return -ENODEV;
+    }
+
+  /* Then register the light sensor */
+
+  ret = as726x_register(devpath, i2c);
+  if (ret < 0)
+    {
+      snerr("ERROR: Error registering AS726X\n");
+    }
+
+  return ret;
+}
+
+#endif /* CONFIG_I2C && CONFIG_SENSORS_AS726X && CONFIG_STM32_I2C1 */
diff --git a/configs/nucleo-l476rg/src/stm32_bmp180.c b/configs/nucleo-l476rg/src/stm32_bmp180.c
new file mode 100644
index 00000000000..2b1131354b0
--- /dev/null
+++ b/configs/nucleo-l476rg/src/stm32_bmp180.c
@@ -0,0 +1,99 @@
+/************************************************************************************
+ * configs/nucleo-l476rg/src/stm32_bmp180.c
+ *
+ *   Copyright (C) 2015 Alan Carvalho de Assis. All rights reserved.
+ *   Author: Alan Carvalho de Assis 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+
+#include "stm32l4.h"
+#include "stm32l4_i2c.h"
+#include "nucleo-l476rg.h"
+
+#if defined(CONFIG_I2C) && defined(CONFIG_SENSORS_BMP180)
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32_bmp180initialize
+ *
+ * Description:
+ *   Initialize and register the MPL115A Pressure Sensor driver.
+ *
+ * Input Parameters:
+ *   devpath - The full path to the driver to register. E.g., "/dev/press0"
+ *
+ * Returned Value:
+ *   Zero (OK) on success; a negated errno value on failure.
+ *
+ ************************************************************************************/
+
+int stm32_bmp180initialize(FAR const char *devpath)
+{
+  FAR struct i2c_master_s *i2c;
+  int ret;
+
+  sninfo("Initializing BMP180!\n");
+
+  /* Initialize I2C */
+
+  i2c = stm32l4_i2cbus_initialize(BMP180_I2C_PORTNO);
+
+  if (!i2c)
+    {
+      return -ENODEV;
+    }
+
+  /* Then register the barometer sensor */
+
+  ret = bmp180_register(devpath, i2c);
+  if (ret < 0)
+    {
+      snerr("ERROR: Error registering BM180\n");
+    }
+
+  return ret;
+}
+
+#endif /* CONFIG_I2C && CONFIG_SENSORS_BMP180 */
diff --git a/configs/nucleo-l476rg/src/stm32_can.c b/configs/nucleo-l476rg/src/stm32_can.c
index c1a1948b315..d2d608f7d1e 100644
--- a/configs/nucleo-l476rg/src/stm32_can.c
+++ b/configs/nucleo-l476rg/src/stm32_can.c
@@ -69,7 +69,7 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Name: stm32_can_setup
+ * Name: stm32l4_can_setup
  *
  * Description:
  *  Initialize CAN and register the CAN device
@@ -82,7 +82,7 @@ int stm32l4_can_setup(void)
   struct can_dev_s *can;
   int ret;
 
-  /* Call stm32_caninitialize() to get an instance of the CAN interface */
+  /* Call stm32l4can_initialize() to get an instance of the CAN interface */
 
   can = stm32l4can_initialize(CAN_PORT);
   if (can == NULL)
diff --git a/configs/nucleo-l476rg/src/stm32_cc1101.c b/configs/nucleo-l476rg/src/stm32_cc1101.c
index fd929239f54..c48110c979c 100644
--- a/configs/nucleo-l476rg/src/stm32_cc1101.c
+++ b/configs/nucleo-l476rg/src/stm32_cc1101.c
@@ -108,14 +108,14 @@ static void cc1101_pwr(FAR struct cc1101_dev_s *dev, bool enable)
  ****************************************************************************/
 
 /****************************************************************************
- * Name: stm32_cc1101_initialize
+ * Name: stm32l4_cc1101_initialize
  *
  * Description:
  *   Initialize and register the cc1101 radio driver
  *
  ****************************************************************************/
 
-int stm32_cc1101_initialize(void)
+int stm32l4_cc1101_initialize(void)
 {
   FAR struct spi_dev_s *spi    = NULL;
   FAR struct cc1101_dev_s *dev = NULL;
diff --git a/configs/nucleo-l476rg/src/stm32_gpio.c b/configs/nucleo-l476rg/src/stm32_gpio.c
index 9813e9405ca..d79e28ba5c2 100644
--- a/configs/nucleo-l476rg/src/stm32_gpio.c
+++ b/configs/nucleo-l476rg/src/stm32_gpio.c
@@ -264,7 +264,7 @@ static int gpint_enable(FAR struct gpio_dev_s *dev, bool enable)
  ****************************************************************************/
 
 /****************************************************************************
- * Name: stm32_gpio_initialize
+ * Name: stm32l4_gpio_initialize
  *
  * Description:
  *   Initialize GPIO drivers for use with /apps/examples/gpio
diff --git a/configs/nucleo-l476rg/src/stm32_lsm303agr.c b/configs/nucleo-l476rg/src/stm32_lsm303agr.c
index 6c44e02b914..63a64ff3b04 100644
--- a/configs/nucleo-l476rg/src/stm32_lsm303agr.c
+++ b/configs/nucleo-l476rg/src/stm32_lsm303agr.c
@@ -60,7 +60,7 @@
  ****************************************************************************/
 
 /*****************************************************************************
- * Name: stm32_lsm303agr_initialize
+ * Name: stm32l4_lsm303agr_initialize
  *
  * Description:
  *   Initialize I2C-based LSM303AGR.
diff --git a/configs/nucleo-l476rg/src/stm32_lsm6dsl.c b/configs/nucleo-l476rg/src/stm32_lsm6dsl.c
index c70424b18a4..06b894d44ae 100644
--- a/configs/nucleo-l476rg/src/stm32_lsm6dsl.c
+++ b/configs/nucleo-l476rg/src/stm32_lsm6dsl.c
@@ -1,5 +1,5 @@
 /*****************************************************************************
- * configs/stm32l476rg/src/stm32_lsm6dsl.c
+ * configs/nucleo-l476rg/src/stm32_lsm6dsl.c
  *
  *   Copyright (C) 2018 Greg Nutt. All rights reserved.
  *   Author: Alan Carvalho de Assis 
@@ -60,7 +60,7 @@
  ****************************************************************************/
 
 /*****************************************************************************
- * Name: stm32_lsm6dsl_initialize
+ * Name: stm32l4_lsm6dsl_initialize
  *
  * Description:
  *   Initialize I2C-based LSM6DSL.
diff --git a/configs/nucleo-l476rg/src/stm32_pwm.c b/configs/nucleo-l476rg/src/stm32_pwm.c
index 3db43caacf9..f0e1aa709df 100644
--- a/configs/nucleo-l476rg/src/stm32_pwm.c
+++ b/configs/nucleo-l476rg/src/stm32_pwm.c
@@ -73,14 +73,14 @@
  ************************************************************************************/
 
 /************************************************************************************
- * Name: stm32_pwm_setup
+ * Name: stm32l4_pwm_setup
  *
  * Description:
  *   Initialize PWM and register the PWM device.
  *
  ************************************************************************************/
 
-int stm32_pwm_setup(void)
+int stm32l4_pwm_setup(void)
 {
   static bool initialized = false;
   struct pwm_lowerhalf_s *pwm;
diff --git a/configs/nucleo-l476rg/src/stm32_spi.c b/configs/nucleo-l476rg/src/stm32_spi.c
index 48e90e9f3d5..205104b105b 100644
--- a/configs/nucleo-l476rg/src/stm32_spi.c
+++ b/configs/nucleo-l476rg/src/stm32_spi.c
@@ -48,7 +48,7 @@
 #include 
 
 #include 
-#include 
+#include "chip.h"
 #include 
 
 #include "nucleo-l476rg.h"
diff --git a/configs/nucleo-l476rg/src/stm32_spimmcsd.c b/configs/nucleo-l476rg/src/stm32_spimmcsd.c
index 19216ce24e2..f822a02195a 100644
--- a/configs/nucleo-l476rg/src/stm32_spimmcsd.c
+++ b/configs/nucleo-l476rg/src/stm32_spimmcsd.c
@@ -1,5 +1,5 @@
 /*****************************************************************************
- * configs/stm32f103-minimum/src/stm32_mmcsd.c
+ * configs/nucleo-l476rg/src/stm32_spimmcsd.c
  *
  *   Copyright (C) 2018 Greg Nutt. All rights reserved.
  *   Author: Alan Carvalho de Assis 
@@ -81,24 +81,26 @@ static const int SD_SLOT_NO  = 0; /* There is only one SD slot */
  ****************************************************************************/
 
 /*****************************************************************************
- * Name: stm32_spi1register
+ * Name: stm32l4_spi1register
  *
  * Description:
  *   Registers media change callback
+ *
  ****************************************************************************/
 
 int stm32l4_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback,
-                       void *arg)
+                         void *arg)
 {
   spiinfo("INFO: Registering spi1 device\n");
   return OK;
 }
 
 /*****************************************************************************
- * Name: stm32_mmcsd_initialize
+ * Name: stm32l4_mmcsd_initialize
  *
  * Description:
  *   Initialize SPI-based SD card and card detect thread.
+ *
  ****************************************************************************/
 
 int stm32l4_mmcsd_initialize(int minor)
diff --git a/configs/nucleo-l476rg/src/stm32_timer.c b/configs/nucleo-l476rg/src/stm32_timer.c
index 9f578b5bc6b..1381f0d0894 100644
--- a/configs/nucleo-l476rg/src/stm32_timer.c
+++ b/configs/nucleo-l476rg/src/stm32_timer.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * config/nucleo-l476rg/src/stm32_timer.c
+ * configs/nucleo-l476rg/src/stm32_timer.c
  *
  *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
diff --git a/configs/nucleo-l476rg/src/stm32_userleds.c b/configs/nucleo-l476rg/src/stm32_userleds.c
index 9464a6ad341..4661e2caff6 100644
--- a/configs/nucleo-l476rg/src/stm32_userleds.c
+++ b/configs/nucleo-l476rg/src/stm32_userleds.c
@@ -197,11 +197,11 @@ void board_userled_all(uint8_t ledset)
 }
 
 /****************************************************************************
- * Name: stm32_led_pminitialize
+ * Name: stm32l4_led_pminitialize
  ****************************************************************************/
 
 #ifdef CONFIG_PM
-void stm32_led_pminitialize(void)
+void stm32l4_led_pminitialize(void)
 {
   /* Register to receive power management callbacks */
 
diff --git a/configs/nucleo-l496zg/include/board.h b/configs/nucleo-l496zg/include/board.h
index 38af59e5be9..f3292a1c166 100644
--- a/configs/nucleo-l496zg/include/board.h
+++ b/configs/nucleo-l496zg/include/board.h
@@ -137,8 +137,11 @@
 
 /* CLK48 will come from PLLSAI1 (implicitly Q) */
 
-#define STM32L4_USE_CLK48         1
-#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG)
+#  define STM32L4_USE_CLK48       1
+#  define STM32L4_CLK48_SEL       RCC_CCIPR_CLK48SEL_PLLSAI1
+#  define STM32L4_HSI48_SYNCSRC   SYNCSRC_NONE
+#endif
 
 /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
 
@@ -241,8 +244,11 @@
 
 /* CLK48 will come from PLLSAI1 (implicitly Q) */
 
-#define STM32L4_USE_CLK48         1
-#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG)
+#  define STM32L4_USE_CLK48       1
+#  define STM32L4_CLK48_SEL       RCC_CCIPR_CLK48SEL_PLLSAI1
+#  define STM32L4_HSI48_SYNCSRC   SYNCSRC_NONE
+#endif
 
 /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
 
@@ -346,8 +352,11 @@
 
 /* CLK48 will come from PLLSAI1 (implicitly Q) */
 
-#define STM32L4_USE_CLK48         1
-#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG)
+#  define STM32L4_USE_CLK48       1
+#  define STM32L4_CLK48_SEL       RCC_CCIPR_CLK48SEL_PLLSAI1
+#  define STM32L4_HSI48_SYNCSRC   SYNCSRC_NONE
+#endif
 
 /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
 
diff --git a/configs/nucleo-l496zg/nsh/defconfig b/configs/nucleo-l496zg/nsh/defconfig
index 27ce7f91d79..af593f83a19 100644
--- a/configs/nucleo-l496zg/nsh/defconfig
+++ b/configs/nucleo-l496zg/nsh/defconfig
@@ -23,7 +23,6 @@ CONFIG_ARMV7M_STACKCHECK=y
 CONFIG_BOARD_LOOPSPERMSEC=8499
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_ADC=y
 CONFIG_EXAMPLES_ADC_SWTRIG=y
 CONFIG_EXAMPLES_ALARM=y
diff --git a/configs/nutiny-nuc120/nsh/defconfig b/configs/nutiny-nuc120/nsh/defconfig
index 896693939e9..6fefbe3a5d1 100644
--- a/configs/nutiny-nuc120/nsh/defconfig
+++ b/configs/nutiny-nuc120/nsh/defconfig
@@ -24,7 +24,6 @@ CONFIG_BOARD_LOOPSPERMSEC=2988
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_MAX_TASKS=8
diff --git a/configs/olimex-efm32g880f128-stk/include/board.h b/configs/olimex-efm32g880f128-stk/include/board.h
index f9c0a2c4ceb..41d3fb6b5b4 100644
--- a/configs/olimex-efm32g880f128-stk/include/board.h
+++ b/configs/olimex-efm32g880f128-stk/include/board.h
@@ -44,8 +44,8 @@
 
 #include 
 
-#include "chip/efm32_cmu.h"
-#include "chip/efm32_usart.h"
+#include "hardware/efm32_cmu.h"
+#include "hardware/efm32_usart.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/configs/olimex-efm32g880f128-stk/nsh/defconfig b/configs/olimex-efm32g880f128-stk/nsh/defconfig
index d5281c1927c..a69a1451502 100644
--- a/configs/olimex-efm32g880f128-stk/nsh/defconfig
+++ b/configs/olimex-efm32g880f128-stk/nsh/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=2662
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EFM32_GPIO_IRQ=y
 CONFIG_EFM32_LEUART1=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/olimex-efm32g880f128-stk/scripts/ld.script b/configs/olimex-efm32g880f128-stk/scripts/ld.script
index 1f934815c5c..5a29f2281ac 100644
--- a/configs/olimex-efm32g880f128-stk/scripts/ld.script
+++ b/configs/olimex-efm32g880f128-stk/scripts/ld.script
@@ -44,67 +44,71 @@ ENTRY(_stext)
 
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/olimex-lpc-h3131/nsh/defconfig b/configs/olimex-lpc-h3131/nsh/defconfig
index d7478e2318b..d64b04504fd 100644
--- a/configs/olimex-lpc-h3131/nsh/defconfig
+++ b/configs/olimex-lpc-h3131/nsh/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARM_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=4287
 CONFIG_BOOT_RUNFROMISRAM=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/olimex-lpc-h3131/scripts/ld.script b/configs/olimex-lpc-h3131/scripts/ld.script
index 3efc2fdcde1..aaf4fcf0626 100644
--- a/configs/olimex-lpc-h3131/scripts/ld.script
+++ b/configs/olimex-lpc-h3131/scripts/ld.script
@@ -48,67 +48,71 @@ OUTPUT_ARCH(arm)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > isram
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > isram
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > isram
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > isram
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > isram
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > isram
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > isram
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > isram
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > isram
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > isram
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > isram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > isram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/olimex-lpc1766stk/ftpc/defconfig b/configs/olimex-lpc1766stk/ftpc/defconfig
index 6209d93fcb9..f779ff9188e 100644
--- a/configs/olimex-lpc1766stk/ftpc/defconfig
+++ b/configs/olimex-lpc1766stk/ftpc/defconfig
@@ -38,6 +38,7 @@ CONFIG_MM_REGIONS=2
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSCLIENT_ENTRIES=4
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_FTPC=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
@@ -58,7 +59,6 @@ CONFIG_NSH_DISABLE_PUT=y
 CONFIG_NSH_DISABLE_WGET=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=16
 CONFIG_NXFLAT=y
diff --git a/configs/olimex-lpc1766stk/hidmouse/defconfig b/configs/olimex-lpc1766stk/hidmouse/defconfig
index a7484900083..ec6e0a65542 100644
--- a/configs/olimex-lpc1766stk/hidmouse/defconfig
+++ b/configs/olimex-lpc1766stk/hidmouse/defconfig
@@ -35,6 +35,7 @@ CONFIG_MM_REGIONS=2
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
@@ -43,7 +44,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=8
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCP_SPLIT=y
 CONFIG_NET_UDP=y
@@ -54,7 +54,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NXFLAT=y
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/olimex-lpc1766stk/nettest/defconfig b/configs/olimex-lpc1766stk/nettest/defconfig
index ee895da9c38..1b9148575fe 100644
--- a/configs/olimex-lpc1766stk/nettest/defconfig
+++ b/configs/olimex-lpc1766stk/nettest/defconfig
@@ -18,7 +18,6 @@ CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_ETH0_PHY_KS8721=y
 CONFIG_EXAMPLES_NETTEST=y
diff --git a/configs/olimex-lpc1766stk/nsh/defconfig b/configs/olimex-lpc1766stk/nsh/defconfig
index 76348338522..f10cf27e109 100644
--- a/configs/olimex-lpc1766stk/nsh/defconfig
+++ b/configs/olimex-lpc1766stk/nsh/defconfig
@@ -43,6 +43,7 @@ CONFIG_MM_REGIONS=2
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
@@ -51,7 +52,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=8
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCP_SPLIT=y
 CONFIG_NET_UDP=y
@@ -63,7 +63,6 @@ CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
 CONFIG_NSH_MMCSDSPIPORTNO=1
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NXFLAT=y
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/olimex-lpc1766stk/scripts/ld.script b/configs/olimex-lpc1766stk/scripts/ld.script
index 3c29cf8bf17..5aeb1630d05 100644
--- a/configs/olimex-lpc1766stk/scripts/ld.script
+++ b/configs/olimex-lpc1766stk/scripts/ld.script
@@ -51,68 +51,72 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
+        /* Stabs debugging sections. */
 
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/olimex-lpc1766stk/usbmsc/defconfig b/configs/olimex-lpc1766stk/usbmsc/defconfig
index b26230276da..8b78c29702f 100644
--- a/configs/olimex-lpc1766stk/usbmsc/defconfig
+++ b/configs/olimex-lpc1766stk/usbmsc/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_CHIP_LPC17XX=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=8111
-CONFIG_DISABLE_POLL=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_LIB_BOARDCTL=y
 CONFIG_LPC17_SSP1=y
diff --git a/configs/olimex-lpc1766stk/usbserial/defconfig b/configs/olimex-lpc1766stk/usbserial/defconfig
index e2893f59a0a..8d243f95d5c 100644
--- a/configs/olimex-lpc1766stk/usbserial/defconfig
+++ b/configs/olimex-lpc1766stk/usbserial/defconfig
@@ -15,7 +15,6 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=8111
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_USBSERIAL=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_LIB_BOARDCTL=y
diff --git a/configs/olimex-lpc1766stk/zmodem/defconfig b/configs/olimex-lpc1766stk/zmodem/defconfig
index 1dde3a973ef..ce5bffe5360 100644
--- a/configs/olimex-lpc1766stk/zmodem/defconfig
+++ b/configs/olimex-lpc1766stk/zmodem/defconfig
@@ -42,13 +42,13 @@ CONFIG_MM_REGIONS=2
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=8
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCP_SPLIT=y
 CONFIG_NET_UDP=y
@@ -60,7 +60,6 @@ CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
 CONFIG_NSH_MMCSDSPIPORTNO=1
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NXFLAT=y
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/olimex-lpc2378/nsh/defconfig b/configs/olimex-lpc2378/nsh/defconfig
index 0ad8aeb8342..9a7be8cf1c2 100644
--- a/configs/olimex-lpc2378/nsh/defconfig
+++ b/configs/olimex-lpc2378/nsh/defconfig
@@ -14,7 +14,6 @@ CONFIG_ARCH_CHIP_LPC2378=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARM_TOOLCHAIN_CODESOURCERYL=y
 CONFIG_BOARD_LOOPSPERMSEC=3270
-CONFIG_DISABLE_POLL=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_LPC2378_UART0=y
 CONFIG_LPC2378_UART2=y
diff --git a/configs/olimex-lpc2378/scripts/ld.script b/configs/olimex-lpc2378/scripts/ld.script
index 8434249b6e9..731bf6ccee4 100644
--- a/configs/olimex-lpc2378/scripts/ld.script
+++ b/configs/olimex-lpc2378/scripts/ld.script
@@ -39,127 +39,131 @@
  ****************************************************************************/
 MEMORY
 {
-  ROM (rx) : ORIGIN = 0x00000000, LENGTH = (512k-8k)	/* Flash: 512k - boot code */
-  RAM (rw) : ORIGIN = 0x40000000, LENGTH = (32k-32)	/* SRAM: 32k - IAP work */
-  URAM (rw) : ORIGIN = 0x7FD00000, LENGTH = (8k)		/* USB RAM: 8k */
-  ERAM (rw) : ORIGIN = 0x7FE00000, LENGTH = (16k)	/* Ethernet RAM: 16k */
-  BRAM (rw) : ORIGIN = 0xE0084000, LENGTH = (2k)		/* Battery RAM: 2k */
+  ROM (rx) : ORIGIN = 0x00000000, LENGTH = (512k-8k)    /* Flash: 512k - boot code */
+  RAM (rw) : ORIGIN = 0x40000000, LENGTH = (32k-32)     /* SRAM: 32k - IAP work */
+  URAM (rw) : ORIGIN = 0x7FD00000, LENGTH = (8k)                /* USB RAM: 8k */
+  ERAM (rw) : ORIGIN = 0x7FE00000, LENGTH = (16k)       /* Ethernet RAM: 16k */
+  BRAM (rw) : ORIGIN = 0xE0084000, LENGTH = (2k)                /* Battery RAM: 2k */
 }
 
 OUTPUT_ARCH(arm)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > ROM
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > ROM
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > ROM
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > ROM
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > ROM
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > ROM
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > ROM
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > ROM
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data :
-	{
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > RAM AT > ROM
+        . = ALIGN(4);
+        .data :
+        {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > RAM AT > ROM
 
 /* .bss section which is initialized by 0 */
   /* This section will be filled with zero by startup code */
   .bss (NOLOAD) :
   {
-	_sbss = ABSOLUTE(.) ;
-	*(.bss)
-	*(.bss.*)
-	*(.gnu.linkonce.b*)
-	*(COMMON)
-	_ebss = ABSOLUTE(.);
+        _sbss = ABSOLUTE(.) ;
+        *(.bss)
+        *(.bss.*)
+        *(.gnu.linkonce.b*)
+        *(COMMON)
+        _ebss = ABSOLUTE(.);
   } > RAM
 
   .usbram (NOLOAD) :
   {
-	__usbram_start = . ;
-	__usbram_start__ = . ;
-	*(.usbram)
-	. = ALIGN(4);
+        __usbram_start = . ;
+        __usbram_start__ = . ;
+        *(.usbram)
+        . = ALIGN(4);
   } > URAM
 
   .etherram (NOLOAD) :
   {
-	__etherram_start = . ;
-	__etherram_start__ = . ;
-	*(.etherram)
-	. = ALIGN(4);
+        __etherram_start = . ;
+        __etherram_start__ = . ;
+        *(.etherram)
+        . = ALIGN(4);
   } > ERAM
 
   .batteryram (NOLOAD) :
   {
-	__batteryram_start = . ;
-	__batteryram_start__ = . ;
-	*(.batteryram)
-	. = ALIGN(4);
+        __batteryram_start = . ;
+        __batteryram_start__ = . ;
+        *(.batteryram)
+        . = ALIGN(4);
   } > BRAM
 
-	/* Stabs debugging sections.	*/
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	/* DWARF debug sections.
-	Symbols in the DWARF debugging sections are relative to the beginning
-	of the section so we begin them at 0.  */
-	/* DWARF 1 */
-	.debug          0 : { *(.debug) }
-	.line           0 : { *(.line) }
-	/* GNU DWARF 1 extensions */
-	.debug_srcinfo  0 : { *(.debug_srcinfo) }
-	.debug_sfnames  0 : { *(.debug_sfnames) }
-	/* DWARF 1.1 and DWARF 2 */
-	.debug_aranges  0 : { *(.debug_aranges) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	/* DWARF 2 */
-	.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
-	.debug_abbrev   0 : { *(.debug_abbrev) }
-	.debug_line     0 : { *(.debug_line) }
-	.debug_frame    0 : { *(.debug_frame) }
-	.debug_str      0 : { *(.debug_str) }
-	.debug_loc      0 : { *(.debug_loc) }
-	.debug_macinfo  0 : { *(.debug_macinfo) }
-	/* SGI/MIPS DWARF 2 extensions */
-	.debug_weaknames 0 : { *(.debug_weaknames) }
-	.debug_funcnames 0 : { *(.debug_funcnames) }
-	.debug_typenames 0 : { *(.debug_typenames) }
-	.debug_varnames  0 : { *(.debug_varnames) }
+        /* Stabs debugging sections.    */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        /* DWARF debug sections.
+        Symbols in the DWARF debugging sections are relative to the beginning
+        of the section so we begin them at 0.  */
+        /* DWARF 1 */
+        .debug          0 : { *(.debug) }
+        .line           0 : { *(.line) }
+        /* GNU DWARF 1 extensions */
+        .debug_srcinfo  0 : { *(.debug_srcinfo) }
+        .debug_sfnames  0 : { *(.debug_sfnames) }
+        /* DWARF 1.1 and DWARF 2 */
+        .debug_aranges  0 : { *(.debug_aranges) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        /* DWARF 2 */
+        .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+        .debug_abbrev   0 : { *(.debug_abbrev) }
+        .debug_line     0 : { *(.debug_line) }
+        .debug_frame    0 : { *(.debug_frame) }
+        .debug_str      0 : { *(.debug_str) }
+        .debug_loc      0 : { *(.debug_loc) }
+        .debug_macinfo  0 : { *(.debug_macinfo) }
+        /* SGI/MIPS DWARF 2 extensions */
+        .debug_weaknames 0 : { *(.debug_weaknames) }
+        .debug_funcnames 0 : { *(.debug_funcnames) }
+        .debug_typenames 0 : { *(.debug_typenames) }
+        .debug_varnames  0 : { *(.debug_varnames) }
 }
diff --git a/configs/olimex-stm32-e407/netnsh/defconfig b/configs/olimex-stm32-e407/netnsh/defconfig
index b339006468d..30f49e50372 100644
--- a/configs/olimex-stm32-e407/netnsh/defconfig
+++ b/configs/olimex-stm32-e407/netnsh/defconfig
@@ -27,6 +27,9 @@ CONFIG_MAX_WDOGPARMS=2
 CONFIG_MM_REGIONS=2
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
+CONFIG_NETINIT_DHCPC=y
+CONFIG_NETINIT_DRIPADDR=0xc0a80101
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_DISCOVER=y
 CONFIG_NETUTILS_TELNETD=y
@@ -46,9 +49,6 @@ CONFIG_NET_UDP_CHECKSUMS=y
 CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_BUILTIN_APPS=y
-CONFIG_NSH_DHCPC=y
-CONFIG_NSH_DRIPADDR=0xc0a80101
-CONFIG_NSH_NOMAC=y
 CONFIG_NSOCKET_DESCRIPTORS=10
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/olimex-stm32-e407/nsh/defconfig b/configs/olimex-stm32-e407/nsh/defconfig
index 6261489ebb0..94c6e0b5d39 100644
--- a/configs/olimex-stm32-e407/nsh/defconfig
+++ b/configs/olimex-stm32-e407/nsh/defconfig
@@ -18,7 +18,6 @@ CONFIG_ARCH_CHIP_STM32F407ZG=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_EXAMPLES_HELLOXX=y
 CONFIG_FS_PROCFS=y
diff --git a/configs/olimex-stm32-e407/scripts/ld.script b/configs/olimex-stm32-e407/scripts/ld.script
index d3b3e6e71b1..349ef3ac73d 100644
--- a/configs/olimex-stm32-e407/scripts/ld.script
+++ b/configs/olimex-stm32-e407/scripts/ld.script
@@ -48,8 +48,8 @@
 
 MEMORY
 {
-	flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
-	sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K
+        flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+        sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K
 }
 
 OUTPUT_ARCH(arm)
@@ -57,67 +57,71 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/olimex-stm32-e407/src/olimex-stm32-e407.h b/configs/olimex-stm32-e407/src/olimex-stm32-e407.h
index 8b939a63b25..5c966588e7d 100644
--- a/configs/olimex-stm32-e407/src/olimex-stm32-e407.h
+++ b/configs/olimex-stm32-e407/src/olimex-stm32-e407.h
@@ -94,8 +94,7 @@
 #endif
 
 #if !defined(CONFIG_NSH_NETINIT_THREAD) || !defined(CONFIG_ARCH_PHY_INTERRUPT) || \
-    !defined(CONFIG_NETDEV_PHY_IOCTL) || !defined(CONFIG_NET_UDP) || \
-     defined(CONFIG_DISABLE_SIGNALS)
+    !defined(CONFIG_NETDEV_PHY_IOCTL) || !defined(CONFIG_NET_UDP)
 #  undef HAVE_NETMONITOR
 #endif
 
diff --git a/configs/olimex-stm32-e407/usbnsh/defconfig b/configs/olimex-stm32-e407/usbnsh/defconfig
index 988aa423855..a0046046e68 100644
--- a/configs/olimex-stm32-e407/usbnsh/defconfig
+++ b/configs/olimex-stm32-e407/usbnsh/defconfig
@@ -21,7 +21,6 @@ CONFIG_CDCACM=y
 CONFIG_CDCACM_CONSOLE=y
 CONFIG_CDCACM_RXBUFSIZE=256
 CONFIG_CDCACM_TXBUFSIZE=256
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_EXAMPLES_HELLOXX=y
 CONFIG_FS_PROCFS=y
diff --git a/configs/olimex-stm32-h405/scripts/ld.script b/configs/olimex-stm32-h405/scripts/ld.script
index 29f64825392..92d83fbbaad 100644
--- a/configs/olimex-stm32-h405/scripts/ld.script
+++ b/configs/olimex-stm32-h405/scripts/ld.script
@@ -57,67 +57,71 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/olimex-stm32-h405/usbnsh/defconfig b/configs/olimex-stm32-h405/usbnsh/defconfig
index 0b27c16af02..6eb6a77a741 100644
--- a/configs/olimex-stm32-h405/usbnsh/defconfig
+++ b/configs/olimex-stm32-h405/usbnsh/defconfig
@@ -29,7 +29,6 @@ CONFIG_CDCACM_CONSOLE=y
 CONFIG_CDCACM_RXBUFSIZE=256
 CONFIG_CDCACM_TXBUFSIZE=256
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_ADC=y
 CONFIG_EXAMPLES_CAN=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/olimex-stm32-h407/nsh/defconfig b/configs/olimex-stm32-h407/nsh/defconfig
index 2a62d082fdc..f9284285092 100644
--- a/configs/olimex-stm32-h407/nsh/defconfig
+++ b/configs/olimex-stm32-h407/nsh/defconfig
@@ -21,7 +21,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
diff --git a/configs/olimex-stm32-h407/nsh_uext/defconfig b/configs/olimex-stm32-h407/nsh_uext/defconfig
index 89eb0c0ce32..0bd3b9e2535 100644
--- a/configs/olimex-stm32-h407/nsh_uext/defconfig
+++ b/configs/olimex-stm32-h407/nsh_uext/defconfig
@@ -21,7 +21,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/olimex-stm32-h407/scripts/ld.script b/configs/olimex-stm32-h407/scripts/ld.script
index a476753cf29..25ee301f6cc 100644
--- a/configs/olimex-stm32-h407/scripts/ld.script
+++ b/configs/olimex-stm32-h407/scripts/ld.script
@@ -48,75 +48,79 @@
 
 MEMORY
 {
-	flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
-	sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K
+        flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+        sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K
 }
 
 OUTPUT_ARCH(arm)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/olimex-stm32-p107/nsh/defconfig b/configs/olimex-stm32-p107/nsh/defconfig
index 6f562d210c7..5c2e9039517 100644
--- a/configs/olimex-stm32-p107/nsh/defconfig
+++ b/configs/olimex-stm32-p107/nsh/defconfig
@@ -29,22 +29,21 @@ CONFIG_MMCSD=y
 CONFIG_MTD=y
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
+CONFIG_NETINIT_DRIPADDR=0xc0a80201
+CONFIG_NETINIT_IPADDR=0xc0a80232
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
 CONFIG_NET_ETH_PKTSIZE=650
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=40
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCP_CONNS=40
 CONFIG_NET_UDP=y
 CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_BUILTIN_APPS=y
-CONFIG_NSH_DRIPADDR=0xc0a80201
-CONFIG_NSH_IPADDR=0xc0a80232
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=10
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/olimex-stm32-p107/scripts/ld.script b/configs/olimex-stm32-p107/scripts/ld.script
index bf648f198cc..0a38d5e0164 100644
--- a/configs/olimex-stm32-p107/scripts/ld.script
+++ b/configs/olimex-stm32-p107/scripts/ld.script
@@ -35,8 +35,8 @@
 
 MEMORY
 {
-	flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K
-	sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+        flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+        sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
 
 }
 
@@ -45,69 +45,73 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The STM32F107VC has 64Kb of SRAM beginning at the following address */
+        /* The STM32F107VC has 64Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/olimex-stm32-p107/scripts/ld.script.dfu b/configs/olimex-stm32-p107/scripts/ld.script.dfu
index ff87e2eb635..62221c9c5f8 100644
--- a/configs/olimex-stm32-p107/scripts/ld.script.dfu
+++ b/configs/olimex-stm32-p107/scripts/ld.script.dfu
@@ -45,69 +45,73 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The STM32F103Z has 64Kb of SRAM beginning at the following address */
+        /* The STM32F103Z has 64Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/olimex-stm32-p207/nsh/defconfig b/configs/olimex-stm32-p207/nsh/defconfig
index c1cbf571cb2..0dba0851aad 100644
--- a/configs/olimex-stm32-p207/nsh/defconfig
+++ b/configs/olimex-stm32-p207/nsh/defconfig
@@ -35,6 +35,9 @@ CONFIG_MAX_WDOGPARMS=2
 CONFIG_MM_REGIONS=2
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
+CONFIG_NETINIT_DRIPADDR=0xa0000001
+CONFIG_NETINIT_IPADDR=0xa0000002
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_SOCKOPTS=y
@@ -47,11 +50,8 @@ CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_DISABLE_GET=y
 CONFIG_NSH_DISABLE_PUT=y
 CONFIG_NSH_DISABLE_WGET=y
-CONFIG_NSH_DRIPADDR=0xa0000001
 CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_IPADDR=0xa0000002
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/olimex-stm32-p207/scripts/ld.script b/configs/olimex-stm32-p207/scripts/ld.script
index ccaf2f05ea9..f0ef8e63ae2 100644
--- a/configs/olimex-stm32-p207/scripts/ld.script
+++ b/configs/olimex-stm32-p207/scripts/ld.script
@@ -56,67 +56,71 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/olimex-stm32-p407/dhtxx/defconfig b/configs/olimex-stm32-p407/dhtxx/defconfig
index 9b03f795dad..c36a7a1cc72 100644
--- a/configs/olimex-stm32-p407/dhtxx/defconfig
+++ b/configs/olimex-stm32-p407/dhtxx/defconfig
@@ -19,7 +19,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_CDCACM=y
 CONFIG_CDCACM_CONSOLE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_DHTXX=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
diff --git a/configs/olimex-stm32-p407/hidkbd/defconfig b/configs/olimex-stm32-p407/hidkbd/defconfig
index 5ac2a590020..bd87bef0426 100644
--- a/configs/olimex-stm32-p407/hidkbd/defconfig
+++ b/configs/olimex-stm32-p407/hidkbd/defconfig
@@ -16,7 +16,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HIDKBD=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
diff --git a/configs/olimex-stm32-p407/kernel/stm32_userspace.c b/configs/olimex-stm32-p407/kernel/stm32_userspace.c
index 36306ccd660..a5a4f113413 100644
--- a/configs/olimex-stm32-p407/kernel/stm32_userspace.c
+++ b/configs/olimex-stm32-p407/kernel/stm32_userspace.c
@@ -115,9 +115,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/olimex-stm32-p407/knsh/defconfig b/configs/olimex-stm32-p407/knsh/defconfig
index bcaf2391aaa..fb830ad66dc 100644
--- a/configs/olimex-stm32-p407/knsh/defconfig
+++ b/configs/olimex-stm32-p407/knsh/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARM_MPU=y
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILD_PROTECTED=y
-CONFIG_DISABLE_POLL=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
 CONFIG_FS_PROCFS=y
diff --git a/configs/olimex-stm32-p407/module/defconfig b/configs/olimex-stm32-p407/module/defconfig
index 3998024532d..30243ad32af 100644
--- a/configs/olimex-stm32-p407/module/defconfig
+++ b/configs/olimex-stm32-p407/module/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_USEBASEPRI=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_MODULE=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
diff --git a/configs/olimex-stm32-p407/nsh/defconfig b/configs/olimex-stm32-p407/nsh/defconfig
index 0e9f5750265..88be22f286c 100644
--- a/configs/olimex-stm32-p407/nsh/defconfig
+++ b/configs/olimex-stm32-p407/nsh/defconfig
@@ -16,7 +16,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/olimex-stm32-p407/src/stm32_sram.c b/configs/olimex-stm32-p407/src/stm32_sram.c
index 3350c467af4..ba2f00f1023 100644
--- a/configs/olimex-stm32-p407/src/stm32_sram.c
+++ b/configs/olimex-stm32-p407/src/stm32_sram.c
@@ -143,25 +143,6 @@ static const uint32_t g_sramconfig[] =
  * Private Functions
  ************************************************************************************/
 
-/************************************************************************************
- * Name: stm32_enablefsmc
- *
- * Description:
- *   Enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-static void stm32_enablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Enable AHB clocking to the FSMC */
-
-  regval  = getreg32( STM32_RCC_AHB3ENR);
-  regval |= RCC_AHB3ENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHB3ENR);
-}
-
 /************************************************************************************
  * Name: stm32_sramgpios
  *
@@ -220,7 +201,7 @@ void stm32_stram_configure(void)
 
   /* Enable AHB clocking to the FSMC */
 
-  stm32_enablefsmc();
+  stm32_fsmc_enable();
 
   /* Bank1 NOR/SRAM control register configuration
    *
diff --git a/configs/olimex-stm32-p407/zmodem/defconfig b/configs/olimex-stm32-p407/zmodem/defconfig
index ca11661b661..3f5af40b769 100644
--- a/configs/olimex-stm32-p407/zmodem/defconfig
+++ b/configs/olimex-stm32-p407/zmodem/defconfig
@@ -16,7 +16,6 @@ CONFIG_ARCH_CHIP_STM32F407ZG=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/olimex-strp711/nettest/defconfig b/configs/olimex-strp711/nettest/defconfig
index 35e518d36f6..f6b19b0df8a 100644
--- a/configs/olimex-strp711/nettest/defconfig
+++ b/configs/olimex-strp711/nettest/defconfig
@@ -17,7 +17,6 @@ CONFIG_BOARD_LOOPSPERMSEC=1431
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_ENC28J60=y
 CONFIG_EXAMPLES_NETTEST=y
 CONFIG_EXAMPLES_NETTEST_NOMAC=y
diff --git a/configs/olimex-strp711/nsh/defconfig b/configs/olimex-strp711/nsh/defconfig
index e6fddeb8828..14285aaa674 100644
--- a/configs/olimex-strp711/nsh/defconfig
+++ b/configs/olimex-strp711/nsh/defconfig
@@ -16,7 +16,6 @@ CONFIG_ARCH_CHIP_STR71X=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARM_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=1431
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_FAT=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_MAX_TASKS=16
diff --git a/configs/olimex-strp711/scripts/ld.script b/configs/olimex-strp711/scripts/ld.script
index 2717592dc72..d9735024d91 100644
--- a/configs/olimex-strp711/scripts/ld.script
+++ b/configs/olimex-strp711/scripts/ld.script
@@ -57,67 +57,71 @@ OUTPUT_ARCH(arm)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections.	*/
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections.    */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/olimexino-stm32/scripts/ld.script b/configs/olimexino-stm32/scripts/ld.script
index 0b3661058a3..777b9cf56e0 100644
--- a/configs/olimexino-stm32/scripts/ld.script
+++ b/configs/olimexino-stm32/scripts/ld.script
@@ -51,67 +51,71 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/olimexino-stm32/scripts/ld.script.dfu b/configs/olimexino-stm32/scripts/ld.script.dfu
index 3f6c09b5d53..0f344ba7959 100644
--- a/configs/olimexino-stm32/scripts/ld.script.dfu
+++ b/configs/olimexino-stm32/scripts/ld.script.dfu
@@ -45,69 +45,73 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The STM32F103Z has 64Kb of SRAM beginning at the following address */
+        /* The STM32F103Z has 64Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/omnibusf4/kernel/stm32_userspace.c b/configs/omnibusf4/kernel/stm32_userspace.c
index 25ac24bc6cb..9fb4fe0211f 100644
--- a/configs/omnibusf4/kernel/stm32_userspace.c
+++ b/configs/omnibusf4/kernel/stm32_userspace.c
@@ -118,9 +118,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/omnibusf4/nsh/defconfig b/configs/omnibusf4/nsh/defconfig
index 65c48146a31..ff55b7c456e 100644
--- a/configs/omnibusf4/nsh/defconfig
+++ b/configs/omnibusf4/nsh/defconfig
@@ -32,7 +32,6 @@ CONFIG_DEBUG_WARN=y
 CONFIG_DEV_GPIO=y
 CONFIG_DEV_URANDOM=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_VIDEO=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_EXAMPLES_HELLOXX=y
diff --git a/configs/omnibusf4/scripts/ld.script b/configs/omnibusf4/scripts/ld.script
index eb3ae13725d..3867568a72b 100644
--- a/configs/omnibusf4/scripts/ld.script
+++ b/configs/omnibusf4/scripts/ld.script
@@ -57,67 +57,71 @@ ENTRY(_stext)
 EXTERN(_vectors)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/omnibusf4/scripts/memory.ld b/configs/omnibusf4/scripts/memory.ld
index ea90262f57f..cdd73958b2c 100644
--- a/configs/omnibusf4/scripts/memory.ld
+++ b/configs/omnibusf4/scripts/memory.ld
@@ -54,7 +54,7 @@
  * Alignment of the user space FLASH partition is also a critical factor:
  * The user space FLASH partition will be spanned with a single region of
  * size 2**n bytes.  The alignment of the user-space region must be the same.
- * As a consequence, as the user-space increases in size, the alignmment
+ * As a consequence, as the user-space increases in size, the alignment
  * requirement also increases.
  *
  * This alignment requirement means that the largest user space FLASH region
diff --git a/configs/omnibusf4/src/stm32_bringup.c b/configs/omnibusf4/src/stm32_bringup.c
index bf608cbfd64..5801a21cf2d 100644
--- a/configs/omnibusf4/src/stm32_bringup.c
+++ b/configs/omnibusf4/src/stm32_bringup.c
@@ -306,16 +306,16 @@ int stm32_bringup(void)
     }
 #endif
 
-#if defined(CONFIG_RNDIS) && defined(CONFIG_NSH_MACADDR)
+#if defined(CONFIG_RNDIS) && defined(CONFIG_NETINIT_MACADDR)
   /* Set up a MAC address for the RNDIS device. */
 
   uint8_t mac[6];
   mac[0] = 0xa0; /* TODO */
-  mac[1] = (CONFIG_NSH_MACADDR >> (8 * 4)) & 0xff;
-  mac[2] = (CONFIG_NSH_MACADDR >> (8 * 3)) & 0xff;
-  mac[3] = (CONFIG_NSH_MACADDR >> (8 * 2)) & 0xff;
-  mac[4] = (CONFIG_NSH_MACADDR >> (8 * 1)) & 0xff;
-  mac[5] = (CONFIG_NSH_MACADDR >> (8 * 0)) & 0xff;
+  mac[1] = (CONFIG_NETINIT_MACADDR >> (8 * 4)) & 0xff;
+  mac[2] = (CONFIG_NETINIT_MACADDR >> (8 * 3)) & 0xff;
+  mac[3] = (CONFIG_NETINIT_MACADDR >> (8 * 2)) & 0xff;
+  mac[4] = (CONFIG_NETINIT_MACADDR >> (8 * 1)) & 0xff;
+  mac[5] = (CONFIG_NETINIT_MACADDR >> (8 * 0)) & 0xff;
   usbdev_rndis_initialize(mac);
 #endif
 
diff --git a/configs/omnibusf4/src/stm32_ostest.c b/configs/omnibusf4/src/stm32_ostest.c
index a0e6517af5f..6b4351270b2 100644
--- a/configs/omnibusf4/src/stm32_ostest.c
+++ b/configs/omnibusf4/src/stm32_ostest.c
@@ -61,8 +61,7 @@
 #if defined(CONFIG_ARCH_FPU) && \
     !defined(CONFIG_TESTING_OSTEST_FPUTESTDISABLE) && \
     defined(CONFIG_TESTING_OSTEST_FPUSIZE) && \
-    defined(CONFIG_SCHED_WAITPID) && \
-    !defined(CONFIG_DISABLE_SIGNALS)
+    defined(CONFIG_SCHED_WAITPID)
 #    define HAVE_FPU 1
 #endif
 
diff --git a/configs/open1788/README.txt b/configs/open1788/README.txt
index 95184cd942d..72cf09c1bd6 100644
--- a/configs/open1788/README.txt
+++ b/configs/open1788/README.txt
@@ -468,9 +468,6 @@ Configuration Directories
             CONFIG_LPC17_GPIOIRQ=y            : GPIO interrupt support
             CONFIG_LPC17_SSP1=y               : Enable support for SSP1
 
-          RTOS Features:
-            CONFIG_DISABLE_SIGNALS=n          : Signals are required
-
           Library Support:
             CONFIG_SCHED_WORKQUEUE=y          : Work queue support required
 
diff --git a/configs/open1788/kernel/lpc17_userspace.c b/configs/open1788/kernel/lpc17_userspace.c
index 8747acba6fd..b108b824ca4 100644
--- a/configs/open1788/kernel/lpc17_userspace.c
+++ b/configs/open1788/kernel/lpc17_userspace.c
@@ -114,9 +114,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/open1788/knsh/defconfig b/configs/open1788/knsh/defconfig
index 283be9733e2..b675ffc1ac3 100644
--- a/configs/open1788/knsh/defconfig
+++ b/configs/open1788/knsh/defconfig
@@ -23,7 +23,6 @@ CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=11934
 CONFIG_BUILD_PROTECTED=y
 CONFIG_DEV_LOOP=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/open1788/scripts/ld.script b/configs/open1788/scripts/ld.script
index 4634e03590a..016b29341ae 100644
--- a/configs/open1788/scripts/ld.script
+++ b/configs/open1788/scripts/ld.script
@@ -74,6 +74,7 @@ SECTIONS
         _etext = ABSOLUTE(.);
     } > FLASH
 
+    . = ALIGN(4);
     .init_section : {
         _sinit = ABSOLUTE(.);
         *(.init_array .init_array.*)
@@ -84,6 +85,7 @@ SECTIONS
         *(.ARM.extab*)
     } > FLASH
 
+    . = ALIGN(4);
     __exidx_start = ABSOLUTE(.);
     .ARM.exidx : {
         *(.ARM.exidx*)
@@ -93,6 +95,7 @@ SECTIONS
 
     _eronly = ABSOLUTE(.);
 
+    . = ALIGN(4);
     .data : {
         _sdata = ABSOLUTE(.);
         *(.data .data.*)
diff --git a/configs/open1788/scripts/memory.ld b/configs/open1788/scripts/memory.ld
index bf075975a8f..efbaf6d10d0 100644
--- a/configs/open1788/scripts/memory.ld
+++ b/configs/open1788/scripts/memory.ld
@@ -48,7 +48,7 @@
  * Alignment of the user space FLASH partition is a critical factor: The
  * user space FLASH partition will be spanned with a single region of size
  * 2**n bytes.  The alignment of the user-space region must be the same.  As
- * a consequence, as the user-space increases in size, the alignmment
+ * a consequence, as the user-space increases in size, the alignment
  * requirement also increases.
  *
  * This alignment requirement means that the largest user space FLASH region
diff --git a/configs/open1788/src/lpc17_sdraminitialize.c b/configs/open1788/src/lpc17_sdraminitialize.c
index e81cda735da..9a8c772223b 100644
--- a/configs/open1788/src/lpc17_sdraminitialize.c
+++ b/configs/open1788/src/lpc17_sdraminitialize.c
@@ -47,7 +47,7 @@
 
 #include "up_arch.h"
 #include "up_internal.h"
-#include "chip/lpc17_syscon.h"
+#include "hardware/lpc17_syscon.h"
 #include "lpc17_emc.h"
 
 #include "open1788.h"
diff --git a/configs/or1k/nsh/defconfig b/configs/or1k/nsh/defconfig
index 4d26be7a93d..327cbb6ee11 100644
--- a/configs/or1k/nsh/defconfig
+++ b/configs/or1k/nsh/defconfig
@@ -63,7 +63,6 @@ CONFIG_DEBUG_TIMER_WARN=y
 CONFIG_DEBUG_WARN=y
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_FS_PROCFS=y
diff --git a/configs/p112/README.txt b/configs/p112/README.txt
index 0d5e8ea29d8..c3bfae96a33 100644
--- a/configs/p112/README.txt
+++ b/configs/p112/README.txt
@@ -137,17 +137,32 @@ that connects to the P112 via the Z85230 ESCC channel A.
 Status
 ======
 
-2014-8-22:  After some time idling away, I tried rebuilding with Windows 8, the latest MinGW
-and the latest SDCC.  I fixed a few things but there a still a few issues.  The last "show
-stopper" before I gave up for now was during building dependencies:
+2014-8-22:  After some time idling away, I tried rebuilding with Windows 8,
+  the latest MinGW and the latest SDCC.  I fixed a few things but there a
+  still a few issues.  The last "show stopper" before I gave up for now was
+  during building dependencies:
 
-ASlink-Error- : "bin/mm_initialize.rel"
+  ASlink-Error- : "bin/mm_initialize.rel"
 
-Clearly there is something wrong with the command line options given to SDCC because it is
-trying to compile and link when we really only want dependencies.  I did not spend very much
-time trying to solve the problem; I assume that it is not too difficult.
+  Clearly there is something wrong with the command line options given to
+  SDCC because it is trying to compile and link when we really only want
+  dependencies.  I did not spend very much time trying to solve the problem;
+  I assume that it is not too difficult.
 
-2014-9-15: There has been a lot of change to the address environment APIs with the inegration
-of address environments on the Cortex-A.  It is likely that there is some breakage due to
-incompatibilities with the Z180's mini-MMU.
+2014-9-15: There has been a lot of change to the address environment APIs
+  with the integration of address environments on the Cortex-A.  It is
+  likely that there is some breakage due to incompatibilities with the
+  Z180's mini-MMU.
+
+Known compilation problems with SDCC:
+
+Known compilation problems:
+
+    CC:  stdlib/lib_strtof.c
+    stdlib/lib_strtof.c:62:6: warning: #warning "Size of exponent is unknown"
+    stdlib/lib_strtof.c:76: error 122: dividing by ZERO
+    stdlib/lib_strtof.c:102: error 122: dividing by ZERO
+    stdlib/lib_strtof.c:76: error 122: dividing by ZERO
+
+  Workaround: Remove lib_strtof.c from libs/libc/stdlib/Make.defs
 
diff --git a/configs/p112/ostest/defconfig b/configs/p112/ostest/defconfig
index cc379b37b86..ef7e9c0906a 100644
--- a/configs/p112/ostest/defconfig
+++ b/configs/p112/ostest/defconfig
@@ -17,7 +17,6 @@ CONFIG_BOARD_LOOPSPERMSEC=100
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_GRAN=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/p112/src/.gitignore b/configs/p112/src/.gitignore
index 726d936e1e3..101a8721005 100644
--- a/configs/p112/src/.gitignore
+++ b/configs/p112/src/.gitignore
@@ -1,2 +1,16 @@
-/.depend
 /Make.dep
+/.depend
+/up_mem.h
+/*.sym
+/*.asm
+/*.rel
+/*.lst
+/*.adb
+/*.rst
+/*.lib
+/*.lnk
+/*.map
+/*.mem
+/*.ihx
+/*.hex
+
diff --git a/configs/pcduino-a10/include/board.h b/configs/pcduino-a10/include/board.h
index 8d70982ba08..8aa18bbcdc6 100644
--- a/configs/pcduino-a10/include/board.h
+++ b/configs/pcduino-a10/include/board.h
@@ -42,7 +42,7 @@
 
 #include 
 
-#include "chip/a1x_piocfg.h"
+#include "hardware/a1x_piocfg.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/configs/pcduino-a10/nsh/defconfig b/configs/pcduino-a10/nsh/defconfig
index 9c103db7450..e82208c72ee 100644
--- a/configs/pcduino-a10/nsh/defconfig
+++ b/configs/pcduino-a10/nsh/defconfig
@@ -23,7 +23,6 @@ CONFIG_BOARD_LOOPSPERMSEC=49341
 CONFIG_BOOT_RUNFROMSDRAM=y
 CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/photon/nsh/defconfig b/configs/photon/nsh/defconfig
index d50ceaef84e..a4f999023e0 100644
--- a/configs/photon/nsh/defconfig
+++ b/configs/photon/nsh/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_CHIP_STM32F205RG=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
diff --git a/configs/photon/rgbled/defconfig b/configs/photon/rgbled/defconfig
index 2670b39d899..d50f8bd8ffd 100644
--- a/configs/photon/rgbled/defconfig
+++ b/configs/photon/rgbled/defconfig
@@ -21,7 +21,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_CDCACM=y
 CONFIG_CDCACM_CONSOLE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_RGBLED=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/photon/usbnsh/defconfig b/configs/photon/usbnsh/defconfig
index 972f4036811..5dc024de084 100644
--- a/configs/photon/usbnsh/defconfig
+++ b/configs/photon/usbnsh/defconfig
@@ -20,7 +20,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_CDCACM=y
 CONFIG_CDCACM_CONSOLE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/photon/wlan/defconfig b/configs/photon/wlan/defconfig
index fe2b9aff01c..d3402186891 100644
--- a/configs/photon/wlan/defconfig
+++ b/configs/photon/wlan/defconfig
@@ -44,6 +44,8 @@ CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDEVICES=y
 CONFIG_NETDEV_LATEINIT=y
 CONFIG_NETDEV_WIRELESS_IOCTL=y
+CONFIG_NETINIT_DHCPC=y
+CONFIG_NETINIT_DRIPADDR=0xc0a80001
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NET_BROADCAST=y
@@ -59,8 +61,6 @@ CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
-CONFIG_NSH_DHCPC=y
-CONFIG_NSH_DRIPADDR=0xc0a80001
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
 CONFIG_NSH_READLINE=y
diff --git a/configs/pic32mx-starterkit/README.txt b/configs/pic32mx-starterkit/README.txt
index 24ce663821d..bdde1a7b32c 100644
--- a/configs/pic32mx-starterkit/README.txt
+++ b/configs/pic32mx-starterkit/README.txt
@@ -1081,7 +1081,6 @@ Where  is one of the following:
        c. This example can support an FTP server.  In order to build in FTP server
           support simply add the following to the Nuttx configuration file:
 
-         CONFIG_DISABLE_POLL=n
          CONFIG_NETUTILS_FTPD=y
          CONFIG_EXAMPLES_FTPD=y
 
diff --git a/configs/pic32mx-starterkit/nsh/defconfig b/configs/pic32mx-starterkit/nsh/defconfig
index 3d6088b8514..cde2b9111b6 100644
--- a/configs/pic32mx-starterkit/nsh/defconfig
+++ b/configs/pic32mx-starterkit/nsh/defconfig
@@ -18,7 +18,6 @@ CONFIG_ARCH_MIPS=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=7245
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/pic32mx7mmb/README.txt b/configs/pic32mx7mmb/README.txt
index 85a028279e9..7e9981d83cd 100644
--- a/configs/pic32mx7mmb/README.txt
+++ b/configs/pic32mx7mmb/README.txt
@@ -708,10 +708,6 @@ Where  is one of the following:
          CONFIG_NETUTILS_FTPD=y
          CONFIG_SYSTEM_FTPD=y
 
-          And enable poll() support in the NuttX configuration file:
-
-          CONFIG_DISABLE_POLL=n
-
     6. Using a RAM disk and the USB MSC device to the nsh configuration
 
        Here is an experimental change to examples/nsh that will create a RAM
diff --git a/configs/pic32mx7mmb/src/pic32_touchscreen.c b/configs/pic32mx7mmb/src/pic32_touchscreen.c
index 83f6d21eb17..29ae6d1f851 100644
--- a/configs/pic32mx7mmb/src/pic32_touchscreen.c
+++ b/configs/pic32mx7mmb/src/pic32_touchscreen.c
@@ -211,9 +211,7 @@ struct tc_dev_s
    * retained in the f_priv field of the 'struct file'.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_TOUCHSCREEN_NPOLLWAITERS];
-#endif
 };
 
 /************************************************************************************
@@ -241,9 +239,7 @@ static int tc_open(FAR struct file *filep);
 static int tc_close(FAR struct file *filep);
 static ssize_t tc_read(FAR struct file *filep, FAR char *buffer, size_t len);
 static int tc_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int tc_poll(FAR struct file *filep, struct pollfd *fds, bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -258,10 +254,8 @@ static const struct file_operations tc_fops =
   tc_read,    /* read */
   0,          /* write */
   0,          /* seek */
-  tc_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , tc_poll   /* poll */
-#endif
+  tc_ioctl,   /* ioctl */
+  tc_poll     /* poll */
 };
 
 /* If only a single touchscreen device is supported, then the driver state
@@ -479,9 +473,7 @@ static inline bool tc_valid_sample(uint16_t sample)
 
 static void tc_notify(FAR struct tc_dev_s *priv)
 {
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   /* If there are threads waiting for read data, then signal one of them
    * that the read data is available.
@@ -502,7 +494,6 @@ static void tc_notify(FAR struct tc_dev_s *priv)
    * then some make end up blocking after all.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   for (i = 0; i < CONFIG_TOUCHSCREEN_NPOLLWAITERS; i++)
     {
       struct pollfd *fds = priv->fds[i];
@@ -513,7 +504,6 @@ static void tc_notify(FAR struct tc_dev_s *priv)
           nxsem_post(fds->sem);
         }
     }
-#endif
 }
 
 /****************************************************************************
@@ -1248,7 +1238,6 @@ static int tc_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: tc_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int tc_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup)
 {
@@ -1336,7 +1325,6 @@ errout:
   nxsem_post(&priv->devsem);
   return ret;
 }
-#endif
 
 /************************************************************************************
  * Public Functions
diff --git a/configs/pic32mz-starterkit/nsh/defconfig b/configs/pic32mz-starterkit/nsh/defconfig
index a7bca1a145d..8e7cc1ad8f3 100644
--- a/configs/pic32mz-starterkit/nsh/defconfig
+++ b/configs/pic32mz-starterkit/nsh/defconfig
@@ -18,7 +18,6 @@ CONFIG_ARCH_MIPS=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=7245
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/qemu-i486/nsh/defconfig b/configs/qemu-i486/nsh/defconfig
index 712a1ef1621..99945251048 100644
--- a/configs/qemu-i486/nsh/defconfig
+++ b/configs/qemu-i486/nsh/defconfig
@@ -24,7 +24,6 @@ CONFIG_ARCH_X86=y
 CONFIG_ARCH="x86"
 CONFIG_BOARD_LOOPSPERMSEC=999
 CONFIG_BOOT_RUNFROMEXTSRAM=y
-CONFIG_DISABLE_POLL=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_FS_FAT=y
 CONFIG_FS_ROMFS=y
diff --git a/configs/qemu-i486/ostest/defconfig b/configs/qemu-i486/ostest/defconfig
index 2f41d89f5f9..f1b58a34bab 100644
--- a/configs/qemu-i486/ostest/defconfig
+++ b/configs/qemu-i486/ostest/defconfig
@@ -14,7 +14,6 @@ CONFIG_ARCH_X86=y
 CONFIG_BOARD_LOOPSPERMSEC=999
 CONFIG_BOOT_RUNFROMEXTSRAM=y
 CONFIG_DEV_LOWCONSOLE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_FAT=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_MAX_TASKS=64
diff --git a/configs/sabre-6quad/README.txt b/configs/sabre-6quad/README.txt
index bf82c5183dd..22c8de745c1 100644
--- a/configs/sabre-6quad/README.txt
+++ b/configs/sabre-6quad/README.txt
@@ -4,6 +4,12 @@ README.txt
 This directory holds a port of NuttX to the NXP/Freescale Sabre board
 featuring the iMX 6Quad CPU.
 
+This is a minimal port, used primarily for verifying SMP operation.  More
+recently, a port to the i.MX RT was added.  This port has gotten more
+support since it is better aligned with usage in embedded systems.  The
+i.MX6 and the i.MX6 share IOMUXing and some peripherals.  It ought to be
+a simple matter to backport some of the common drivers from i.MXRT to i.MX6.
+
 Contents
 ========
 
@@ -163,12 +169,36 @@ Status
   configuration, you will see a crash due to memory corruption consistently,
   specially in the nested signal test (apps/examples/ostest/signest.c).
 
-2018-06-20:  There is a problem with the Interrupt Stack for SMP in
+2018-06-20:  There was a problem with the Interrupt Stack for SMP in
   arch/arm/src/armv7-a/arm_vectors.S:  There is only one interrupt stack for
   all CPUs!  A fix for this was put in place on 2018-06-21.  Big Improvement!
-  Bit this does not completely eliminate instabilities which seem to be
+  But this does not completely eliminate instabilities which seem to be
   related to memory corruption -- mm_mallinfo() asserts.
 
+CORTEX-A GIC SGI INTERRUPT MASKING (From the top-level TODO list)
+-----------------------------------------------------------------
+In the ARMv7-A GICv2 architecture, the inter-processor interrupts (SGIs) are
+non maskable and will occur even if interrupts are disabled.  This adds a
+lot of complexity to the ARMV7-A critical section design.
+
+Masayuki Ishikawa has suggested the use of the GICv2 ICCMPR register to
+control SGI interrupts.  This register (much like the ARMv7-M BASEPRI
+register) can be used to mask interrupts by interrupt priority.  Since SGIs
+may be assigned priorities the ICCMPR should be able to block execution of
+SGIs as well.
+
+Such an implementation would be very similar to the BASEPRI (vs PRIMASK)
+implementation for the ARMv7-M:  (1) The up_irq_save() and up_irq_restore()
+registers would have to set/restore the ICCMPR register, (2) register setup
+logic in arch/arm/src/armv7-a for task start-up and signal dispatch would
+have to set the ICCMPR correctly, and (3) the 'xcp' structure would have to
+be extended to hold the ICCMPR register;  logic would have to added be
+save/restore the ICCMPR register in the 'xcp' structure on each interrupt
+and context switch.
+
+This would also be an essential part of a high priority, nested interrupt
+implementation (unrelated feature).
+
 Platform Features
 =================
 
diff --git a/configs/sam3u-ek/README.txt b/configs/sam3u-ek/README.txt
index 8be852a2919..5d07eef6abe 100644
--- a/configs/sam3u-ek/README.txt
+++ b/configs/sam3u-ek/README.txt
@@ -397,9 +397,6 @@ Configurations
             CONFIG_SAM34_GPIO_IRQ=y           : GPIO interrupt support
             CONFIG_SAM34_GPIOA_IRQ=y          : Enable GPIO interrupts from port A
 
-          RTOS Features:
-            CONFIG_DISABLE_SIGNALS=n          : Signals are required
-
           Library Support:
             CONFIG_SCHED_WORKQUEUE=y          : Work queue support required
 
diff --git a/configs/sam3u-ek/kernel/sam_userspace.c b/configs/sam3u-ek/kernel/sam_userspace.c
index 9ca96b12308..073a1dbac6c 100644
--- a/configs/sam3u-ek/kernel/sam_userspace.c
+++ b/configs/sam3u-ek/kernel/sam_userspace.c
@@ -114,9 +114,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/sam3u-ek/knsh/defconfig b/configs/sam3u-ek/knsh/defconfig
index 2ae2c592155..4933db214d8 100644
--- a/configs/sam3u-ek/knsh/defconfig
+++ b/configs/sam3u-ek/knsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_ARM_MPU=y
 CONFIG_BOARD_LOOPSPERMSEC=8720
 CONFIG_BUILD_PROTECTED=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_FAT=y
 CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
diff --git a/configs/sam3u-ek/nsh/defconfig b/configs/sam3u-ek/nsh/defconfig
index 7564faca742..0aca5df9fe6 100644
--- a/configs/sam3u-ek/nsh/defconfig
+++ b/configs/sam3u-ek/nsh/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=8720
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_FAT=y
 CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
diff --git a/configs/sam3u-ek/nx/defconfig b/configs/sam3u-ek/nx/defconfig
index cbe419320c9..6db162e85d0 100644
--- a/configs/sam3u-ek/nx/defconfig
+++ b/configs/sam3u-ek/nx/defconfig
@@ -25,7 +25,6 @@ CONFIG_ARMV7M_USEBASEPRI=y
 CONFIG_BOARD_LOOPSPERMSEC=8720
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NX_BGCOLOR=0x7b5d
diff --git a/configs/sam3u-ek/nxwm/defconfig b/configs/sam3u-ek/nxwm/defconfig
index 70005582218..fac2374c036 100644
--- a/configs/sam3u-ek/nxwm/defconfig
+++ b/configs/sam3u-ek/nxwm/defconfig
@@ -27,7 +27,6 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=8720
 CONFIG_CXX_NEWLONG=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_INPUT=y
diff --git a/configs/sam3u-ek/scripts/ld.script b/configs/sam3u-ek/scripts/ld.script
index 64766f8cdad..da26bbd9ec3 100644
--- a/configs/sam3u-ek/scripts/ld.script
+++ b/configs/sam3u-ek/scripts/ld.script
@@ -53,67 +53,71 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram1 AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram1 AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram1
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram1
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/sam3u-ek/scripts/memory.ld b/configs/sam3u-ek/scripts/memory.ld
index 70369776b4b..5f40295e950 100644
--- a/configs/sam3u-ek/scripts/memory.ld
+++ b/configs/sam3u-ek/scripts/memory.ld
@@ -47,7 +47,7 @@
  * Alignment of the user space FLASH partition is a critical factor: The
  * user space FLASH partition will be spanned with a single region of size
  * 2**n bytes.  The alignment of the user-space region must be the same.  As
- * a consequence, as the user-space increases in size, the alignmment
+ * a consequence, as the user-space increases in size, the alignment
  * requirement also increases.
  *
  * This alignment requirement means that the largest user space FLASH region
diff --git a/configs/sam3u-ek/src/sam3u-ek.h b/configs/sam3u-ek/src/sam3u-ek.h
index 87119e417d4..1c3e0f971d6 100644
--- a/configs/sam3u-ek/src/sam3u-ek.h
+++ b/configs/sam3u-ek/src/sam3u-ek.h
@@ -48,7 +48,7 @@
 #include 
 #include 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/configs/sam3u-ek/src/sam_lcd.c b/configs/sam3u-ek/src/sam_lcd.c
index 25aa1822ae6..d08df5dd3fc 100644
--- a/configs/sam3u-ek/src/sam_lcd.c
+++ b/configs/sam3u-ek/src/sam_lcd.c
@@ -126,8 +126,8 @@
 
 #include "up_arch.h"
 #include "sam_gpio.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_smc.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_smc.h"
 #include "sam3u-ek.h"
 
 /**************************************************************************************
diff --git a/configs/sam4cmp-db/nsh/defconfig b/configs/sam4cmp-db/nsh/defconfig
index ce900a2bda6..20874ec873a 100644
--- a/configs/sam4cmp-db/nsh/defconfig
+++ b/configs/sam4cmp-db/nsh/defconfig
@@ -16,7 +16,6 @@ CONFIG_BOARD_LOOPSPERMSEC=6124
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_NFILE_DESCRIPTORS=8
diff --git a/configs/sam4cmp-db/src/sam4cmp-db.h b/configs/sam4cmp-db/src/sam4cmp-db.h
index ab9a1733c65..6989cc25455 100644
--- a/configs/sam4cmp-db/src/sam4cmp-db.h
+++ b/configs/sam4cmp-db/src/sam4cmp-db.h
@@ -48,7 +48,7 @@
 #include 
 #include 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 
 /************************************************************************************
  * Public Types
diff --git a/configs/sam4e-ek/README.txt b/configs/sam4e-ek/README.txt
index 1706a5b27ef..9913d592247 100644
--- a/configs/sam4e-ek/README.txt
+++ b/configs/sam4e-ek/README.txt
@@ -738,9 +738,6 @@ Touchscreen
       CONFIG_SAM34_GPIO_IRQ=y               : GPIO interrupt support
       CONFIG_SAM34_GPIOA_IRQ=y              : Enable GPIO interrupts from port A
 
-    RTOS Features:
-      CONFIG_DISABLE_SIGNALS=n              : Signals are required
-
     Library Support:
       CONFIG_SCHED_WORKQUEUE=y              : Work queue support required
 
@@ -1221,9 +1218,6 @@ Configurations
          CONFIG_SAM34_GPIO_IRQ=y           : GPIO interrupt support
          CONFIG_SAM34_GPIOA_IRQ=y          : Enable GPIO interrupts from port A
 
-       RTOS Features:
-         CONFIG_DISABLE_SIGNALS=n          : Signals are required
-
        Library Support:
          CONFIG_SCHED_WORKQUEUE=y          : Work queue support required
 
diff --git a/configs/sam4e-ek/nsh/defconfig b/configs/sam4e-ek/nsh/defconfig
index 57d54b28fae..2cc209ec9b0 100644
--- a/configs/sam4e-ek/nsh/defconfig
+++ b/configs/sam4e-ek/nsh/defconfig
@@ -33,6 +33,7 @@ CONFIG_MTD_AT25=y
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -41,7 +42,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=16
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
 CONFIG_NET_TCP_CONNS=16
@@ -54,7 +54,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig
index 05020514e27..72d96e26580 100644
--- a/configs/sam4e-ek/nxwm/defconfig
+++ b/configs/sam4e-ek/nxwm/defconfig
@@ -49,6 +49,7 @@ CONFIG_MTD_AT25=y
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -69,7 +70,6 @@ CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LIBRARY=y
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NX=y
 CONFIG_NXFONT_SANS22X29B=y
diff --git a/configs/sam4e-ek/src/sam4e-ek.h b/configs/sam4e-ek/src/sam4e-ek.h
index dacbe510986..aa5abaa0937 100644
--- a/configs/sam4e-ek/src/sam4e-ek.h
+++ b/configs/sam4e-ek/src/sam4e-ek.h
@@ -48,7 +48,7 @@
 #include 
 #include 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/configs/sam4e-ek/src/sam_ili9325.c b/configs/sam4e-ek/src/sam_ili9325.c
index 19c00ebd2d6..e0736353368 100644
--- a/configs/sam4e-ek/src/sam_ili9325.c
+++ b/configs/sam4e-ek/src/sam_ili9325.c
@@ -136,8 +136,8 @@
 #include "up_arch.h"
 #include "sam_gpio.h"
 #include "sam_periphclks.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_smc.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_smc.h"
 #include "sam4e-ek.h"
 
 #ifdef CONFIG_LCD
diff --git a/configs/sam4e-ek/src/sam_ili9341.c b/configs/sam4e-ek/src/sam_ili9341.c
index 8b689123896..906384c4703 100644
--- a/configs/sam4e-ek/src/sam_ili9341.c
+++ b/configs/sam4e-ek/src/sam_ili9341.c
@@ -136,8 +136,8 @@
 #include "up_arch.h"
 #include "sam_gpio.h"
 #include "sam_periphclks.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_smc.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_smc.h"
 #include "sam4e-ek.h"
 
 #ifdef CONFIG_LCD
diff --git a/configs/sam4e-ek/usbnsh/defconfig b/configs/sam4e-ek/usbnsh/defconfig
index 14177d76384..dde99cd5fd9 100644
--- a/configs/sam4e-ek/usbnsh/defconfig
+++ b/configs/sam4e-ek/usbnsh/defconfig
@@ -41,6 +41,7 @@ CONFIG_MTD_AT25=y
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -48,7 +49,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=16
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
 CONFIG_NET_TCP_CONNS=16
@@ -60,7 +60,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/sam4l-xplained/nsh/defconfig b/configs/sam4l-xplained/nsh/defconfig
index d0af770654a..7ffd107d11d 100644
--- a/configs/sam4l-xplained/nsh/defconfig
+++ b/configs/sam4l-xplained/nsh/defconfig
@@ -21,7 +21,6 @@ CONFIG_BOARD_LOOPSPERMSEC=3410
 CONFIG_BUILTIN=y
 CONFIG_CXX_NEWLONG=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/sam4l-xplained/src/sam4l-xplained.h b/configs/sam4l-xplained/src/sam4l-xplained.h
index 263b6fc8d1f..e4c310a0d82 100644
--- a/configs/sam4l-xplained/src/sam4l-xplained.h
+++ b/configs/sam4l-xplained/src/sam4l-xplained.h
@@ -48,7 +48,7 @@
 #include 
 #include 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/configs/sam4l-xplained/src/sam_slcd.c b/configs/sam4l-xplained/src/sam_slcd.c
index c627356dd40..9275f1f8417 100644
--- a/configs/sam4l-xplained/src/sam_slcd.c
+++ b/configs/sam4l-xplained/src/sam_slcd.c
@@ -61,7 +61,7 @@
 #include "up_arch.h"
 #include "sam_gpio.h"
 #include "sam4l_periphclks.h"
-#include "chip/sam4l_lcdca.h"
+#include "hardware/sam4l_lcdca.h"
 
 #include "sam4l-xplained.h"
 
@@ -298,9 +298,7 @@ static void slcd_action(enum slcdcode_e code, uint8_t count);
 static ssize_t slcd_read(FAR struct file *, FAR char *, size_t);
 static ssize_t slcd_write(FAR struct file *, FAR const char *, size_t);
 static int slcd_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int slcd_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -315,10 +313,8 @@ static const struct file_operations g_slcdops =
   slcd_read,     /* read */
   slcd_write,    /* write */
   0,             /* seek */
-  slcd_ioctl     /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , slcd_poll    /* poll */
-#endif
+  slcd_ioctl,    /* ioctl */
+  slcd_poll      /* poll */
 };
 
 /* LCD state data */
@@ -1131,7 +1127,6 @@ static int slcd_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: slcd_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int slcd_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup)
 {
@@ -1148,7 +1143,6 @@ static int slcd_poll(FAR struct file *filep, FAR struct pollfd *fds,
 
   return OK;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/configs/sam4s-xplained-pro/nsh/defconfig b/configs/sam4s-xplained-pro/nsh/defconfig
index 2184bec93af..12003e48e55 100644
--- a/configs/sam4s-xplained-pro/nsh/defconfig
+++ b/configs/sam4s-xplained-pro/nsh/defconfig
@@ -30,7 +30,6 @@ CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEV_ZERO=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_CPUHOG=y
 CONFIG_EXAMPLES_SERIALBLASTER=y
 CONFIG_EXAMPLES_SERIALRX=y
diff --git a/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h b/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h
index e6baf02f1de..9529a601573 100644
--- a/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h
+++ b/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h
@@ -49,7 +49,7 @@
 #include 
 #include 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/configs/sam4s-xplained/nsh/defconfig b/configs/sam4s-xplained/nsh/defconfig
index d56585a7b9b..00ac86c634d 100644
--- a/configs/sam4s-xplained/nsh/defconfig
+++ b/configs/sam4s-xplained/nsh/defconfig
@@ -23,7 +23,6 @@ CONFIG_BUILTIN=y
 CONFIG_CXX_NEWLONG=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/sam4s-xplained/src/sam4s-xplained.h b/configs/sam4s-xplained/src/sam4s-xplained.h
index 9e96a89072a..0ee5a092abc 100644
--- a/configs/sam4s-xplained/src/sam4s-xplained.h
+++ b/configs/sam4s-xplained/src/sam4s-xplained.h
@@ -48,7 +48,7 @@
 #include 
 #include 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/configs/sam4s-xplained/src/sam_sram.c b/configs/sam4s-xplained/src/sam_sram.c
index 28e9ae7ec22..90209799795 100644
--- a/configs/sam4s-xplained/src/sam_sram.c
+++ b/configs/sam4s-xplained/src/sam_sram.c
@@ -43,7 +43,7 @@
 
 #include "up_arch.h"
 #include "sam4s_periphclks.h"
-#include "chip/sam_smc.h"
+#include "hardware/sam_smc.h"
 #include "sam4s-xplained.h"
 
 #ifdef CONFIG_SAM34_EXTSRAM0
diff --git a/configs/sama5d2-xult/src/sama5d2-xult.h b/configs/sama5d2-xult/src/sama5d2-xult.h
index 59875ae36b9..3f23eaf96bc 100644
--- a/configs/sama5d2-xult/src/sama5d2-xult.h
+++ b/configs/sama5d2-xult/src/sama5d2-xult.h
@@ -49,7 +49,7 @@
 #include 
 #include 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/configs/sama5d3-xplained/README.txt b/configs/sama5d3-xplained/README.txt
index 402a82216d4..446f2d0db57 100644
--- a/configs/sama5d3-xplained/README.txt
+++ b/configs/sama5d3-xplained/README.txt
@@ -978,8 +978,7 @@ Networking
       that it supports arch_phy_irq().  This logic can be found at
       nuttx/configs/sama5d3-xplained/src/sam_ethernet.c.
 
-    - And a few other things: UDP support is required (CONFIG_NET_UDP) and
-      signals must not be disabled (CONFIG_DISABLE_SIGNALS).
+    - One other thing: UDP support is required (CONFIG_NET_UDP).
 
   Given those prerequisites, the newtork monitor can be selected with these additional settings.
 
diff --git a/configs/sama5d3-xplained/nsh/defconfig b/configs/sama5d3-xplained/nsh/defconfig
index 008a9f15c97..b8911549093 100644
--- a/configs/sama5d3-xplained/nsh/defconfig
+++ b/configs/sama5d3-xplained/nsh/defconfig
@@ -23,7 +23,6 @@ CONFIG_BOARD_LOOPSPERMSEC=65775
 CONFIG_BOOT_RUNFROMSDRAM=y
 CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/sama5d3-xplained/src/sam_ajoystick.c b/configs/sama5d3-xplained/src/sam_ajoystick.c
index f5347ae8197..f49a9be1246 100644
--- a/configs/sama5d3-xplained/src/sam_ajoystick.c
+++ b/configs/sama5d3-xplained/src/sam_ajoystick.c
@@ -51,7 +51,7 @@
 
 #include "sam_pio.h"
 #include "sam_adc.h"
-#include "chip/sam_adc.h"
+#include "hardware/sam_adc.h"
 #include "sama5d3-xplained.h"
 
 /****************************************************************************
diff --git a/configs/sama5d3-xplained/src/sam_nandflash.c b/configs/sama5d3-xplained/src/sam_nandflash.c
index f53fa352d9f..7e9a1619db4 100644
--- a/configs/sama5d3-xplained/src/sam_nandflash.c
+++ b/configs/sama5d3-xplained/src/sam_nandflash.c
@@ -59,8 +59,8 @@
 #include "sam_periphclks.h"
 #include "sam_pio.h"
 #include "sam_nand.h"
-#include "chip/sam_hsmc.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_hsmc.h"
+#include "hardware/sam_pinmap.h"
 
 #include "sama5d3-xplained.h"
 
diff --git a/configs/sama5d3-xplained/src/sam_ostest.c b/configs/sama5d3-xplained/src/sam_ostest.c
index fcd3fcd720f..ed2e433efc9 100644
--- a/configs/sama5d3-xplained/src/sam_ostest.c
+++ b/configs/sama5d3-xplained/src/sam_ostest.c
@@ -58,8 +58,7 @@
 
 #undef HAVE_FPU
 #if defined(CONFIG_ARCH_FPU) && !defined(CONFIG_TESTING_OSTEST_FPUTESTDISABLE) && \
-    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID) && \
-    !defined(CONFIG_DISABLE_SIGNALS)
+    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID)
 #    define HAVE_FPU 1
 #endif
 
diff --git a/configs/sama5d3-xplained/src/sam_sdram.c b/configs/sama5d3-xplained/src/sam_sdram.c
index abd75d66641..2768332d8ff 100644
--- a/configs/sama5d3-xplained/src/sam_sdram.c
+++ b/configs/sama5d3-xplained/src/sam_sdram.c
@@ -51,10 +51,10 @@
 #include "up_arch.h"
 
 #include "sam_periphclks.h"
-#include "chip/sam_memorymap.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_sfr.h"
-#include "chip/sam_mpddrc.h"
+#include "hardware/sam_memorymap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_sfr.h"
+#include "hardware/sam_mpddrc.h"
 
 #include "sama5d3-xplained.h"
 
diff --git a/configs/sama5d3-xplained/src/sam_usb.c b/configs/sama5d3-xplained/src/sam_usb.c
index 8abe5f5493e..d6534cd64be 100644
--- a/configs/sama5d3-xplained/src/sam_usb.c
+++ b/configs/sama5d3-xplained/src/sam_usb.c
@@ -56,7 +56,7 @@
 #include "up_arch.h"
 #include "sam_pio.h"
 #include "sam_usbhost.h"
-#include "chip/sam_ohci.h"
+#include "hardware/sam_ohci.h"
 #include "sama5d3-xplained.h"
 
 #if defined(CONFIG_SAMA5_UHPHS) || defined(CONFIG_SAMA5_UDPHS)
diff --git a/configs/sama5d3-xplained/src/sama5d3-xplained.h b/configs/sama5d3-xplained/src/sama5d3-xplained.h
index 40de794377d..fae72db6a00 100644
--- a/configs/sama5d3-xplained/src/sama5d3-xplained.h
+++ b/configs/sama5d3-xplained/src/sama5d3-xplained.h
@@ -48,7 +48,7 @@
 #include 
 #include 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/configs/sama5d3x-ek/README.txt b/configs/sama5d3x-ek/README.txt
index b9508357398..3bd73dc2ed2 100644
--- a/configs/sama5d3x-ek/README.txt
+++ b/configs/sama5d3x-ek/README.txt
@@ -1147,8 +1147,7 @@ Networking
       that it supports arch_phy_irq().  This logic can be found at
       nuttx/configs/sama5d3x-ek/src/sam_ethernet.c.
 
-    - And a few other things: UDP support is required (CONFIG_NET_UDP) and
-      signals must not be disabled (CONFIG_DISABLE_SIGNALS).
+    - One other thing: UDP support is required (CONFIG_NET_UDP).
 
   Given those prerequisites, the newtork monitor can be selected with these additional settings.
 
diff --git a/configs/sama5d3x-ek/demo/defconfig b/configs/sama5d3x-ek/demo/defconfig
index 1213ef60494..3843961ba91 100644
--- a/configs/sama5d3x-ek/demo/defconfig
+++ b/configs/sama5d3x-ek/demo/defconfig
@@ -21,7 +21,6 @@ CONFIG_AT25_SPIFREQUENCY=10000000
 CONFIG_BOARD_LOOPSPERMSEC=49341
 CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FLASH_SIZE=134217728
diff --git a/configs/sama5d3x-ek/hello/defconfig b/configs/sama5d3x-ek/hello/defconfig
index ff3256263ea..a8423089faa 100644
--- a/configs/sama5d3x-ek/hello/defconfig
+++ b/configs/sama5d3x-ek/hello/defconfig
@@ -19,7 +19,6 @@ CONFIG_BOOT_RUNFROMISRAM=y
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/sama5d3x-ek/norboot/defconfig b/configs/sama5d3x-ek/norboot/defconfig
index 3f060723878..1c1b33bda52 100644
--- a/configs/sama5d3x-ek/norboot/defconfig
+++ b/configs/sama5d3x-ek/norboot/defconfig
@@ -19,7 +19,6 @@ CONFIG_BOOT_RUNFROMISRAM=y
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/sama5d3x-ek/nsh/defconfig b/configs/sama5d3x-ek/nsh/defconfig
index 941197fb0bd..2ddb2a57424 100644
--- a/configs/sama5d3x-ek/nsh/defconfig
+++ b/configs/sama5d3x-ek/nsh/defconfig
@@ -21,7 +21,6 @@ CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=49341
 CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FLASH_SIZE=134217728
diff --git a/configs/sama5d3x-ek/nx/defconfig b/configs/sama5d3x-ek/nx/defconfig
index 6fc92ea0197..9a3968295bc 100644
--- a/configs/sama5d3x-ek/nx/defconfig
+++ b/configs/sama5d3x-ek/nx/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=49341
 CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NX_BPP=16
 CONFIG_FLASH_SIZE=134217728
diff --git a/configs/sama5d3x-ek/nxplayer/defconfig b/configs/sama5d3x-ek/nxplayer/defconfig
index 1eeb385f2cc..6085c36c481 100644
--- a/configs/sama5d3x-ek/nxplayer/defconfig
+++ b/configs/sama5d3x-ek/nxplayer/defconfig
@@ -25,7 +25,6 @@ CONFIG_AUDIO_WM8904=y
 CONFIG_BOARD_LOOPSPERMSEC=49341
 CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_AUDIO=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
diff --git a/configs/sama5d3x-ek/nxwm/defconfig b/configs/sama5d3x-ek/nxwm/defconfig
index cab645464ee..c7724006776 100644
--- a/configs/sama5d3x-ek/nxwm/defconfig
+++ b/configs/sama5d3x-ek/nxwm/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7A_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=49341
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FLASH_SIZE=134217728
 CONFIG_FLASH_START=0x10000000
 CONFIG_FLASH_VSTART=0x10000000
diff --git a/configs/sama5d3x-ek/ov2640/defconfig b/configs/sama5d3x-ek/ov2640/defconfig
index fe7b5974fab..b671f5c923f 100644
--- a/configs/sama5d3x-ek/ov2640/defconfig
+++ b/configs/sama5d3x-ek/ov2640/defconfig
@@ -19,7 +19,6 @@ CONFIG_BOARD_LOOPSPERMSEC=49341
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_VIDEO=y
 CONFIG_FLASH_SIZE=134217728
 CONFIG_FLASH_START=0x10000000
diff --git a/configs/sama5d3x-ek/src/nor_main.c b/configs/sama5d3x-ek/src/nor_main.c
index 14c86e787ea..609bae0071b 100644
--- a/configs/sama5d3x-ek/src/nor_main.c
+++ b/configs/sama5d3x-ek/src/nor_main.c
@@ -50,9 +50,9 @@
 #include "cp15_cacheops.h"
 
 #include "sam_periphclks.h"
-#include "chip/sam_hsmc.h"
-#include "chip/sam_matrix.h"
-#include "chip/sam_aximx.h"
+#include "hardware/sam_hsmc.h"
+#include "hardware/sam_matrix.h"
+#include "hardware/sam_aximx.h"
 
 #include "sama5d3x-ek.h"
 
diff --git a/configs/sama5d3x-ek/src/sam_nandflash.c b/configs/sama5d3x-ek/src/sam_nandflash.c
index e212a7f2749..8dc559d8341 100644
--- a/configs/sama5d3x-ek/src/sam_nandflash.c
+++ b/configs/sama5d3x-ek/src/sam_nandflash.c
@@ -59,8 +59,8 @@
 #include "sam_periphclks.h"
 #include "sam_pio.h"
 #include "sam_nand.h"
-#include "chip/sam_hsmc.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_hsmc.h"
+#include "hardware/sam_pinmap.h"
 
 #include "sama5d3x-ek.h"
 
diff --git a/configs/sama5d3x-ek/src/sam_norflash.c b/configs/sama5d3x-ek/src/sam_norflash.c
index 1b4ff0c3fb5..13412d068fb 100644
--- a/configs/sama5d3x-ek/src/sam_norflash.c
+++ b/configs/sama5d3x-ek/src/sam_norflash.c
@@ -50,7 +50,7 @@
 
 #include "up_arch.h"
 #include "sam_periphclks.h"
-#include "chip/sam_hsmc.h"
+#include "hardware/sam_hsmc.h"
 
 #include "sama5d3x-ek.h"
 
diff --git a/configs/sama5d3x-ek/src/sam_ostest.c b/configs/sama5d3x-ek/src/sam_ostest.c
index 79ad5e1f8c2..5c7ad3af3a3 100644
--- a/configs/sama5d3x-ek/src/sam_ostest.c
+++ b/configs/sama5d3x-ek/src/sam_ostest.c
@@ -58,8 +58,7 @@
 
 #undef HAVE_FPU
 #if defined(CONFIG_ARCH_FPU) && !defined(CONFIG_TESTING_OSTEST_FPUTESTDISABLE) && \
-    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID) && \
-    !defined(CONFIG_DISABLE_SIGNALS)
+    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID)
 #    define HAVE_FPU 1
 #endif
 
diff --git a/configs/sama5d3x-ek/src/sam_ov2640.c b/configs/sama5d3x-ek/src/sam_ov2640.c
index dfaf2dbfc10..71b2700c620 100644
--- a/configs/sama5d3x-ek/src/sam_ov2640.c
+++ b/configs/sama5d3x-ek/src/sam_ov2640.c
@@ -53,7 +53,7 @@
 #include "sam_pck.h"
 #include "sam_twi.h"
 #include "sam_pio.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 
 #include "sama5d3x-ek.h"
 
diff --git a/configs/sama5d3x-ek/src/sam_sdram.c b/configs/sama5d3x-ek/src/sam_sdram.c
index 184c5cbda4b..f0c9d62ad8c 100644
--- a/configs/sama5d3x-ek/src/sam_sdram.c
+++ b/configs/sama5d3x-ek/src/sam_sdram.c
@@ -51,10 +51,10 @@
 #include "up_arch.h"
 
 #include "sam_periphclks.h"
-#include "chip/sam_memorymap.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_sfr.h"
-#include "chip/sam_mpddrc.h"
+#include "hardware/sam_memorymap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_sfr.h"
+#include "hardware/sam_mpddrc.h"
 
 #include "sama5d3x-ek.h"
 
diff --git a/configs/sama5d3x-ek/src/sam_usb.c b/configs/sama5d3x-ek/src/sam_usb.c
index 614b6c31e24..91d12b0ecb8 100644
--- a/configs/sama5d3x-ek/src/sam_usb.c
+++ b/configs/sama5d3x-ek/src/sam_usb.c
@@ -56,7 +56,7 @@
 #include "up_arch.h"
 #include "sam_pio.h"
 #include "sam_usbhost.h"
-#include "chip/sam_ohci.h"
+#include "hardware/sam_ohci.h"
 #include "sama5d3x-ek.h"
 
 #if defined(CONFIG_SAMA5_UHPHS) || defined(CONFIG_SAMA5_UDPHS)
diff --git a/configs/sama5d3x-ek/src/sama5d3x-ek.h b/configs/sama5d3x-ek/src/sama5d3x-ek.h
index c6dd625998a..f475580340d 100644
--- a/configs/sama5d3x-ek/src/sama5d3x-ek.h
+++ b/configs/sama5d3x-ek/src/sama5d3x-ek.h
@@ -48,7 +48,7 @@
 #include 
 #include 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/configs/sama5d4-ek/README.txt b/configs/sama5d4-ek/README.txt
index 749c0ebb363..9726ed388db 100644
--- a/configs/sama5d4-ek/README.txt
+++ b/configs/sama5d4-ek/README.txt
@@ -1509,8 +1509,7 @@ Networking
       that it supports arch_phy_irq().  This logic can be found at
       nuttx/configs/sama5d4-ek/src/sam_ethernet.c.
 
-    - And a few other things: UDP support is required (CONFIG_NET_UDP) and
-      signals must not be disabled (CONFIG_DISABLE_SIGNALS).
+    - One other thing: UDP support is required (CONFIG_NET_UDP).
 
   Given those prerequisites, the network monitor can be selected with these
   additional settings.
diff --git a/configs/sama5d4-ek/at25boot/defconfig b/configs/sama5d4-ek/at25boot/defconfig
index b3b58c15591..3df3179f4db 100644
--- a/configs/sama5d4-ek/at25boot/defconfig
+++ b/configs/sama5d4-ek/at25boot/defconfig
@@ -19,7 +19,6 @@ CONFIG_BOARD_LOOPSPERMSEC=65775
 CONFIG_BOOT_RUNFROMISRAM=y
 CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/sama5d4-ek/dramboot/defconfig b/configs/sama5d4-ek/dramboot/defconfig
index eca850a1376..7e8c31d4ede 100644
--- a/configs/sama5d4-ek/dramboot/defconfig
+++ b/configs/sama5d4-ek/dramboot/defconfig
@@ -19,7 +19,6 @@ CONFIG_BOARD_LOOPSPERMSEC=65775
 CONFIG_BOOT_RUNFROMISRAM=y
 CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig
index 0a034d513f1..4a43a414676 100644
--- a/configs/sama5d4-ek/ipv6/defconfig
+++ b/configs/sama5d4-ek/ipv6/defconfig
@@ -60,6 +60,9 @@ CONFIG_MMCSD_MULTIBLOCK_DISABLE=y
 CONFIG_MMCSD_SDIO=y
 CONFIG_MQ_MAXMSGSIZE=64
 CONFIG_NET=y
+CONFIG_NETINIT_IPv6NETMASK_8=0xff80
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_ETH_PKTSIZE=590
 CONFIG_NET_ICMPv6=y
@@ -78,9 +81,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_ARCHROMFS=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_IPv6NETMASK_8=0xff80
-CONFIG_NSH_NETINIT_THREAD=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSH_ROMFSETC=y
 CONFIG_NX=y
diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig
index 3b393e0af02..b9eacb76392 100644
--- a/configs/sama5d4-ek/nsh/defconfig
+++ b/configs/sama5d4-ek/nsh/defconfig
@@ -62,6 +62,8 @@ CONFIG_MQ_MAXMSGSIZE=64
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -69,7 +71,6 @@ CONFIG_NET_ARP_SEND=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -81,8 +82,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_ARCHROMFS=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_NETINIT_THREAD=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSH_ROMFSETC=y
 CONFIG_NX=y
diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig
index 574ee42dc8d..dbcc971c5ba 100644
--- a/configs/sama5d4-ek/nxwm/defconfig
+++ b/configs/sama5d4-ek/nxwm/defconfig
@@ -64,6 +64,8 @@ CONFIG_MQ_MAXMSGSIZE=64
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -83,8 +85,6 @@ CONFIG_NSH_ARCHROMFS=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LIBRARY=y
-CONFIG_NSH_NETINIT_THREAD=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSH_ROMFSETC=y
 CONFIG_NX=y
diff --git a/configs/sama5d4-ek/ramtest/defconfig b/configs/sama5d4-ek/ramtest/defconfig
index 92bf04009a8..b1afd472d7b 100644
--- a/configs/sama5d4-ek/ramtest/defconfig
+++ b/configs/sama5d4-ek/ramtest/defconfig
@@ -21,7 +21,6 @@ CONFIG_BOARD_LOOPSPERMSEC=65775
 CONFIG_BOOT_RUNFROMISRAM=y
 CONFIG_BUILTIN=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/sama5d4-ek/src/sam_nandflash.c b/configs/sama5d4-ek/src/sam_nandflash.c
index 467ac8b106f..81a7ff86010 100644
--- a/configs/sama5d4-ek/src/sam_nandflash.c
+++ b/configs/sama5d4-ek/src/sam_nandflash.c
@@ -59,8 +59,8 @@
 #include "sam_periphclks.h"
 #include "sam_pio.h"
 #include "sam_nand.h"
-#include "chip/sam_hsmc.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_hsmc.h"
+#include "hardware/sam_pinmap.h"
 
 #include "sama5d4-ek.h"
 
diff --git a/configs/sama5d4-ek/src/sam_ostest.c b/configs/sama5d4-ek/src/sam_ostest.c
index 1cb9443ad5f..0f464a324c5 100644
--- a/configs/sama5d4-ek/src/sam_ostest.c
+++ b/configs/sama5d4-ek/src/sam_ostest.c
@@ -58,8 +58,7 @@
 
 #undef HAVE_FPU
 #if defined(CONFIG_ARCH_FPU) && !defined(CONFIG_TESTING_OSTEST_FPUTESTDISABLE) && \
-    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID) && \
-    !defined(CONFIG_DISABLE_SIGNALS)
+    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID)
 #    define HAVE_FPU 1
 #endif
 
diff --git a/configs/sama5d4-ek/src/sam_sdram.c b/configs/sama5d4-ek/src/sam_sdram.c
index a868d670911..c199e8ddabe 100644
--- a/configs/sama5d4-ek/src/sam_sdram.c
+++ b/configs/sama5d4-ek/src/sam_sdram.c
@@ -147,11 +147,11 @@
 #include "up_arch.h"
 
 #include "sam_periphclks.h"
-#include "chip/sam_memorymap.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_sfr.h"
-#include "chip/sam_matrix.h"
-#include "chip/sam_mpddrc.h"
+#include "hardware/sam_memorymap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_sfr.h"
+#include "hardware/sam_matrix.h"
+#include "hardware/sam_mpddrc.h"
 
 #include "sama5d4-ek.h"
 
diff --git a/configs/sama5d4-ek/src/sam_usb.c b/configs/sama5d4-ek/src/sam_usb.c
index 081197a7fad..51f69fb030d 100644
--- a/configs/sama5d4-ek/src/sam_usb.c
+++ b/configs/sama5d4-ek/src/sam_usb.c
@@ -56,7 +56,7 @@
 #include "up_arch.h"
 #include "sam_pio.h"
 #include "sam_usbhost.h"
-#include "chip/sam_ohci.h"
+#include "hardware/sam_ohci.h"
 #include "sama5d4-ek.h"
 
 #if defined(CONFIG_SAMA5_UHPHS) || defined(CONFIG_SAMA5_UDPHS)
diff --git a/configs/sama5d4-ek/src/sama5d4-ek.h b/configs/sama5d4-ek/src/sama5d4-ek.h
index 848a7d5caf0..9a3710d9e8e 100644
--- a/configs/sama5d4-ek/src/sama5d4-ek.h
+++ b/configs/sama5d4-ek/src/sama5d4-ek.h
@@ -49,7 +49,7 @@
 #include 
 #include 
 
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pinmap.h"
 
 /************************************************************************************
  * Pre-processor Definitions
diff --git a/configs/samd20-xplained/nsh/defconfig b/configs/samd20-xplained/nsh/defconfig
index aeed1d5f505..6826271ec66 100644
--- a/configs/samd20-xplained/nsh/defconfig
+++ b/configs/samd20-xplained/nsh/defconfig
@@ -35,7 +35,6 @@ CONFIG_ARMV6M_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=3410
 CONFIG_BUILTIN=y
 CONFIG_DEFAULT_SMALL=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/samd21-xplained/nsh/defconfig b/configs/samd21-xplained/nsh/defconfig
index a13995d611a..eacbb81a3de 100644
--- a/configs/samd21-xplained/nsh/defconfig
+++ b/configs/samd21-xplained/nsh/defconfig
@@ -35,7 +35,6 @@ CONFIG_ARMV6M_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=3410
 CONFIG_BUILTIN=y
 CONFIG_DEFAULT_SMALL=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/same70-xplained/README.txt b/configs/same70-xplained/README.txt
index e0c7f67d152..ac0e4583aea 100644
--- a/configs/same70-xplained/README.txt
+++ b/configs/same70-xplained/README.txt
@@ -583,8 +583,7 @@ Pre-requisites:
     that it supports arch_phy_irq().  This logic can be found at
     nuttx/configs/same70-xplained/src/sam_ethernet.c.
 
-  - And a few other things: UDP support is required (CONFIG_NET_UDP) and
-    signals must not be disabled (CONFIG_DISABLE_SIGNALS).
+  - One other thing: UDP support is required.
 
 Given those prerequisites, the network monitor can be selected with these
 additional settings.
@@ -1654,3 +1653,45 @@ Configuration sub-directories
     STATUS:
     2015-03-28: HSMCI TX DMA is disabled.  There are some issues with the TX
       DMA that need to be corrected.
+
+  twm4nx:
+
+    This configuration exercises the port of TWM to NuttX.  A description of
+    that port is available at apps/graphics/twm4nx/README.txt.  This
+    configuration uses the NuttX VNC server to provide a remote desktop for
+    use with VNC client on a PC.  No display, mouse, or keyboard devices are
+    needed.
+
+    NOTES:
+
+    1. Network configuration:  IP address 10.0.0.2.  The is easily changed
+       via 'make menuconfig'.  The VNC server address is 10.0.0.2:5900.
+
+    2. The default (local) framebuffer configuration is 800x600 with 16-bit
+       RGB color.
+
+    3. There are complicated interactions between VNC and the network
+       configuration.  The CONFIG_VNCSERVER_UPDATE_BUFSIZE determines the
+       size of update messages.  That is 1024 bytes in that configuration
+       (the full message with the header will be a little larger).  The
+       CONFIG_NET_ETH_PKTSIZE is set to 590 so that a full update will
+       require several packets.
+
+       Write buffering also effects network performance.  This will break
+       up the large updates into small (196 byte) groups.  When we run out
+       of read-ahead buffers, then partial updates may be sent causing a
+       loss of synchronization.
+
+    STATUS:
+      2019-04-28:  Configuration created.  Not verified.
+      2019-05-04:  Only partially functional.  VNC is a difficult way to
+         debug Twm4Nx because it has its own level of complexities due to
+         networking, mysterious VNC client behavior, and fragile VNC
+         configurations.  I am setting this on the shelf for the time
+         being.  I will stabilize Twm4Nx on another platform first.  Just
+         too many degrees of freedom.
+      2019-05-04:  Testing on hardware reveals that VNC is the source of
+         most of the issues.  Things look good on real, local hardware
+         (see configs/lpcxpresso-lpc54628/twm4nx).  VNC is just not mature
+         enough for this kind of usage at this time.
+
diff --git a/configs/same70-xplained/kernel/sam_userspace.c b/configs/same70-xplained/kernel/sam_userspace.c
index f4c7e40a734..e8e9e628412 100644
--- a/configs/same70-xplained/kernel/sam_userspace.c
+++ b/configs/same70-xplained/kernel/sam_userspace.c
@@ -114,9 +114,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/same70-xplained/mrf24j40-starhub/defconfig b/configs/same70-xplained/mrf24j40-starhub/defconfig
index c02c5f70734..dcd9789f301 100644
--- a/configs/same70-xplained/mrf24j40-starhub/defconfig
+++ b/configs/same70-xplained/mrf24j40-starhub/defconfig
@@ -64,6 +64,8 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y
 CONFIG_NETDEV_PHY_IOCTL=y
 CONFIG_NETDEV_STATISTICS=y
 CONFIG_NETDEV_WIRELESS_IOCTL=y
+CONFIG_NETINIT_MACADDR_2=0x00fade00
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_WEBCLIENT=y
 CONFIG_NET_6LOWPAN=y
@@ -73,7 +75,6 @@ CONFIG_NET_ICMPv6=y
 CONFIG_NET_ICMPv6_NEIGHBOR=y
 CONFIG_NET_ICMPv6_SOCKET=y
 CONFIG_NET_IPv6=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STAR=y
 CONFIG_NET_STARHUB=y
 CONFIG_NET_STATISTICS=y
@@ -90,8 +91,6 @@ CONFIG_NSH_DISABLE_PUT=y
 CONFIG_NSH_DISABLE_WGET=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_MACADDR=0x00fade00deadbeef
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig
index fc07fa453ff..db42f435d5e 100644
--- a/configs/same70-xplained/netnsh/defconfig
+++ b/configs/same70-xplained/netnsh/defconfig
@@ -54,6 +54,8 @@ CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
 CONFIG_NETDEV_PHY_IOCTL=y
 CONFIG_NETDEV_STATISTICS=y
+CONFIG_NETINIT_MONITOR=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -61,7 +63,6 @@ CONFIG_NET_ARP_SEND=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -73,8 +74,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETINIT_MONITOR=y
-CONFIG_NSH_NETINIT_THREAD=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/same70-xplained/nsh/defconfig b/configs/same70-xplained/nsh/defconfig
index 80d99c5653f..99e65d646fd 100644
--- a/configs/same70-xplained/nsh/defconfig
+++ b/configs/same70-xplained/nsh/defconfig
@@ -33,7 +33,6 @@ CONFIG_AT24XX_EXTSIZE=160
 CONFIG_AT24XX_SIZE=2
 CONFIG_BOARD_LOOPSPERMSEC=51262
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/same70-xplained/src/sam_buttons.c b/configs/same70-xplained/src/sam_buttons.c
index ab7dfeb8cfc..cae6df88ccc 100644
--- a/configs/same70-xplained/src/sam_buttons.c
+++ b/configs/same70-xplained/src/sam_buttons.c
@@ -51,7 +51,7 @@
 
 #include "up_arch.h"
 #include "sam_gpio.h"
-#include "chip/sam_matrix.h"
+#include "hardware/sam_matrix.h"
 #include "same70-xplained.h"
 
 #ifdef CONFIG_ARCH_BUTTONS
diff --git a/configs/same70-xplained/src/sam_sdram.c b/configs/same70-xplained/src/sam_sdram.c
index e8a6e65a195..89671c5a2e9 100644
--- a/configs/same70-xplained/src/sam_sdram.c
+++ b/configs/same70-xplained/src/sam_sdram.c
@@ -54,11 +54,11 @@
 #include "up_arch.h"
 
 #include "sam_periphclks.h"
-#include "chip/sam_memorymap.h"
-#include "chip/sam_pinmap.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_matrix.h"
-#include "chip/sam_sdramc.h"
+#include "hardware/sam_memorymap.h"
+#include "hardware/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_matrix.h"
+#include "hardware/sam_sdramc.h"
 
 #include "same70-xplained.h"
 
diff --git a/configs/same70-xplained/twm4nx/defconfig b/configs/same70-xplained/twm4nx/defconfig
new file mode 100644
index 00000000000..09fdcfc91b1
--- /dev/null
+++ b/configs/same70-xplained/twm4nx/defconfig
@@ -0,0 +1,129 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_RAMFUNCS is not set
+# CONFIG_MMCSD_MMCSUPPORT is not set
+# CONFIG_MMCSD_SPI is not set
+# CONFIG_NX_DISABLE_8BPP is not set
+# CONFIG_SAMV7_UART0 is not set
+# CONFIG_SAMV7_UART2 is not set
+# CONFIG_SAMV7_UART4 is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="same70-xplained"
+CONFIG_ARCH_BOARD_SAME70_XPLAINED=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CHIP_SAME70=y
+CONFIG_ARCH_CHIP_SAME70Q21=y
+CONFIG_ARCH_CHIP_SAME70Q=y
+CONFIG_ARCH_CHIP_SAMV7=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_IRQBUTTONS=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_STDARG_H=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_ARMV7M_LAZYFPU=y
+CONFIG_AT24XX_ADDR=0x57
+CONFIG_AT24XX_EXTENDED=y
+CONFIG_AT24XX_EXTSIZE=160
+CONFIG_AT24XX_SIZE=2
+CONFIG_BOARD_LOOPSPERMSEC=51262
+CONFIG_ETH0_PHY_KSZ8081=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_FS_PROCFS=y
+CONFIG_GRAPHICS_TWM4NX=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_I2C_DRIVER=y
+CONFIG_IOB_NBUFFERS=24
+CONFIG_LIB_HOSTNAME="SAME70-Xplained"
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_MMCSD_MULTIBLOCK_DISABLE=y
+CONFIG_MMCSD_SDIO=y
+CONFIG_MM_REGIONS=2
+CONFIG_MQ_MAXMSGSIZE=64
+CONFIG_MTD=y
+CONFIG_MTD_AT24XX=y
+CONFIG_MTD_AT25=y
+CONFIG_MTD_CONFIG=y
+CONFIG_NET=y
+CONFIG_NETDB_DNSCLIENT=y
+CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETDEV_PHY_IOCTL=y
+CONFIG_NETDEV_STATISTICS=y
+CONFIG_NETUTILS_TELNETD=y
+CONFIG_NET_ARP_SEND=y
+CONFIG_NET_BROADCAST=y
+CONFIG_NET_ETH_PKTSIZE=870
+CONFIG_NET_ICMP=y
+CONFIG_NET_ICMP_SOCKET=y
+CONFIG_NET_SOCKOPTS=y
+CONFIG_NET_STATISTICS=y
+CONFIG_NET_TCP=y
+CONFIG_NET_TCPBACKLOG=y
+CONFIG_NET_TCP_WRITE_BUFFERS=y
+CONFIG_NET_UDP=y
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NX=y
+CONFIG_NXFONT_SANS22X29B=y
+CONFIG_NXFONT_SANS23X27=y
+CONFIG_NXTERM=y
+CONFIG_NXTERM_CACHESIZE=32
+CONFIG_NXTERM_CURSORCHAR=95
+CONFIG_NXTERM_MXCHARS=325
+CONFIG_NXTERM_NXKBDIN=y
+CONFIG_NXWIDGETS_BPP=8
+CONFIG_NXWIDGETS_SIZEOFCHAR=1
+CONFIG_NX_BLOCKING=y
+CONFIG_NX_KBD=y
+CONFIG_NX_SWCURSOR=y
+CONFIG_NX_XYINPUT_TOUCHSCREEN=y
+CONFIG_PREALLOC_MQ_MSGS=64
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PREALLOC_WDOGS=8
+CONFIG_RAM_SIZE=393216
+CONFIG_RAM_START=0x20400000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SAMV7_EMAC0=y
+CONFIG_SAMV7_EMAC0_PHYSR=30
+CONFIG_SAMV7_EMAC0_PHYSR_100FD=0x6
+CONFIG_SAMV7_EMAC0_PHYSR_100HD=0x2
+CONFIG_SAMV7_EMAC0_PHYSR_10FD=0x5
+CONFIG_SAMV7_EMAC0_PHYSR_10HD=0x1
+CONFIG_SAMV7_EMAC0_PHYSR_ALTCONFIG=y
+CONFIG_SAMV7_EMAC0_PHYSR_ALTMODE=0x7
+CONFIG_SAMV7_EMAC0_RMII=y
+CONFIG_SAMV7_GPIOA_IRQ=y
+CONFIG_SAMV7_GPIOC_IRQ=y
+CONFIG_SAMV7_GPIO_IRQ=y
+CONFIG_SAMV7_HSMCI0=y
+CONFIG_SAMV7_SDRAMC=y
+CONFIG_SAMV7_SDRAMSIZE=2097152
+CONFIG_SAMV7_TWIHS0=y
+CONFIG_SAMV7_USART1=y
+CONFIG_SAMV7_XDMAC=y
+CONFIG_SCHED_HPWORK=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_SDIO_BLOCKSETUP=y
+CONFIG_START_DAY=28
+CONFIG_START_MONTH=4
+CONFIG_START_YEAR=2019
+CONFIG_SYSTEM_PING=y
+CONFIG_TWM4NX_ARCHINIT=y
+CONFIG_USART1_SERIAL_CONSOLE=y
+CONFIG_USER_ENTRYPOINT="twm4nx_main"
+CONFIG_VNCSERVER=y
+CONFIG_VNCSERVER_COLORFMT_RGB8=y
+CONFIG_VNCSERVER_PRIO=120
+CONFIG_VNCSERVER_SCREENHEIGHT=600
+CONFIG_VNCSERVER_SCREENWIDTH=800
+CONFIG_VNCSERVER_UPDATER_PRIO=120
+CONFIG_VNCSERVER_UPDATE_BUFSIZE=800
diff --git a/configs/saml21-xplained/nsh/defconfig b/configs/saml21-xplained/nsh/defconfig
index 88b29b98ae8..9c891b87747 100644
--- a/configs/saml21-xplained/nsh/defconfig
+++ b/configs/saml21-xplained/nsh/defconfig
@@ -35,7 +35,6 @@ CONFIG_ARMV6M_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=4356
 CONFIG_BUILTIN=y
 CONFIG_DEFAULT_SMALL=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/samv71-xult/README.txt b/configs/samv71-xult/README.txt
index f7bf184902d..d0cb10a89a4 100644
--- a/configs/samv71-xult/README.txt
+++ b/configs/samv71-xult/README.txt
@@ -912,8 +912,7 @@ Pre-requisites:
     that it supports arch_phy_irq().  This logic can be found at
     nuttx/configs/samv71-xult/src/sam_ethernet.c.
 
-  - And a few other things: UDP support is required (CONFIG_NET_UDP) and
-    signals must not be disabled (CONFIG_DISABLE_SIGNALS).
+  - One other thing: UDP support is required.
 
 Given those prerequisites, the network monitor can be selected with these
 additional settings.
diff --git a/configs/samv71-xult/kernel/sam_userspace.c b/configs/samv71-xult/kernel/sam_userspace.c
index 2de79a215df..19ef21ae189 100644
--- a/configs/samv71-xult/kernel/sam_userspace.c
+++ b/configs/samv71-xult/kernel/sam_userspace.c
@@ -114,9 +114,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/samv71-xult/knsh/defconfig b/configs/samv71-xult/knsh/defconfig
index f6deefbd64e..3fc6b47fd12 100644
--- a/configs/samv71-xult/knsh/defconfig
+++ b/configs/samv71-xult/knsh/defconfig
@@ -33,7 +33,6 @@ CONFIG_AT24XX_EXTSIZE=160
 CONFIG_AT24XX_SIZE=2
 CONFIG_BOARD_LOOPSPERMSEC=51262
 CONFIG_BUILD_PROTECTED=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/samv71-xult/module/defconfig b/configs/samv71-xult/module/defconfig
index 137722d8a52..73a541f412d 100644
--- a/configs/samv71-xult/module/defconfig
+++ b/configs/samv71-xult/module/defconfig
@@ -27,7 +27,6 @@ CONFIG_ARMV7M_LAZYFPU=y
 CONFIG_ARMV7M_USEBASEPRI=y
 CONFIG_BOARD_LOOPSPERMSEC=51262
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_MODULE=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_FAT_LCNAMES=y
diff --git a/configs/samv71-xult/mrf24j40-starhub/defconfig b/configs/samv71-xult/mrf24j40-starhub/defconfig
index 68be290ba09..72cd732df5b 100644
--- a/configs/samv71-xult/mrf24j40-starhub/defconfig
+++ b/configs/samv71-xult/mrf24j40-starhub/defconfig
@@ -65,6 +65,8 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y
 CONFIG_NETDEV_PHY_IOCTL=y
 CONFIG_NETDEV_STATISTICS=y
 CONFIG_NETDEV_WIRELESS_IOCTL=y
+CONFIG_NETINIT_MACADDR_2=0x00fade00
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -75,7 +77,6 @@ CONFIG_NET_ICMPv6=y
 CONFIG_NET_ICMPv6_NEIGHBOR=y
 CONFIG_NET_ICMPv6_SOCKET=y
 CONFIG_NET_IPv6=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STAR=y
 CONFIG_NET_STARHUB=y
 CONFIG_NET_STATISTICS=y
@@ -93,8 +94,6 @@ CONFIG_NSH_DISABLE_TELNETD=y
 CONFIG_NSH_DISABLE_WGET=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_MACADDR=0x00fade00deadbeef
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/samv71-xult/mxtxplnd/defconfig b/configs/samv71-xult/mxtxplnd/defconfig
index e56d9e8a8c9..b0f87a2e404 100644
--- a/configs/samv71-xult/mxtxplnd/defconfig
+++ b/configs/samv71-xult/mxtxplnd/defconfig
@@ -33,7 +33,6 @@ CONFIG_AT24XX_EXTSIZE=160
 CONFIG_AT24XX_SIZE=2
 CONFIG_BOARD_LOOPSPERMSEC=51262
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NXLINES=y
 CONFIG_EXAMPLES_NXLINES_BPP=16
 CONFIG_EXAMPLES_TOUCHSCREEN=y
diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig
index 09538662280..e9564a9ba1c 100644
--- a/configs/samv71-xult/netnsh/defconfig
+++ b/configs/samv71-xult/netnsh/defconfig
@@ -52,6 +52,8 @@ CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDEV_PHY_IOCTL=y
 CONFIG_NETDEV_STATISTICS=y
+CONFIG_NETINIT_MONITOR=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -59,7 +61,6 @@ CONFIG_NET_ARP_SEND=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -71,8 +72,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETINIT_MONITOR=y
-CONFIG_NSH_NETINIT_THREAD=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/samv71-xult/nsh/defconfig b/configs/samv71-xult/nsh/defconfig
index e662bc68b61..d5a07a1185f 100644
--- a/configs/samv71-xult/nsh/defconfig
+++ b/configs/samv71-xult/nsh/defconfig
@@ -32,7 +32,6 @@ CONFIG_AT24XX_EXTSIZE=160
 CONFIG_AT24XX_SIZE=2
 CONFIG_BOARD_LOOPSPERMSEC=51262
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/samv71-xult/nxwm/defconfig b/configs/samv71-xult/nxwm/defconfig
index 7cf3be2183b..0533b4e02bb 100644
--- a/configs/samv71-xult/nxwm/defconfig
+++ b/configs/samv71-xult/nxwm/defconfig
@@ -35,7 +35,6 @@ CONFIG_AT24XX_EXTSIZE=160
 CONFIG_AT24XX_SIZE=2
 CONFIG_BOARD_LOOPSPERMSEC=51262
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/samv71-xult/src/sam_buttons.c b/configs/samv71-xult/src/sam_buttons.c
index b78265a7788..6c1d0389494 100644
--- a/configs/samv71-xult/src/sam_buttons.c
+++ b/configs/samv71-xult/src/sam_buttons.c
@@ -51,7 +51,7 @@
 
 #include "up_arch.h"
 #include "sam_gpio.h"
-#include "chip/sam_matrix.h"
+#include "hardware/sam_matrix.h"
 #include "samv71-xult.h"
 
 #ifdef CONFIG_ARCH_BUTTONS
diff --git a/configs/samv71-xult/src/sam_ili9488.c b/configs/samv71-xult/src/sam_ili9488.c
index 3e1db9af55e..e4be9e27705 100644
--- a/configs/samv71-xult/src/sam_ili9488.c
+++ b/configs/samv71-xult/src/sam_ili9488.c
@@ -143,9 +143,9 @@
 #include "sam_gpio.h"
 #include "sam_periphclks.h"
 #include "sam_xdmac.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_smc.h"
-#include "chip/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_smc.h"
+#include "hardware/sam_pinmap.h"
 
 #include "samv71-xult.h"
 #include "atmxt-xpro.h"
diff --git a/configs/samv71-xult/src/sam_sdram.c b/configs/samv71-xult/src/sam_sdram.c
index b43a306f88b..7523a2c13f7 100644
--- a/configs/samv71-xult/src/sam_sdram.c
+++ b/configs/samv71-xult/src/sam_sdram.c
@@ -54,11 +54,11 @@
 #include "up_arch.h"
 
 #include "sam_periphclks.h"
-#include "chip/sam_memorymap.h"
-#include "chip/sam_pinmap.h"
-#include "chip/sam_pmc.h"
-#include "chip/sam_matrix.h"
-#include "chip/sam_sdramc.h"
+#include "hardware/sam_memorymap.h"
+#include "hardware/sam_pinmap.h"
+#include "hardware/sam_pmc.h"
+#include "hardware/sam_matrix.h"
+#include "hardware/sam_sdramc.h"
 
 #include "samv71-xult.h"
 
diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig
index f3095f01f71..fee9bb918c8 100644
--- a/configs/samv71-xult/vnc/defconfig
+++ b/configs/samv71-xult/vnc/defconfig
@@ -58,12 +58,12 @@ CONFIG_MTD_CONFIG=y
 CONFIG_NET=y
 CONFIG_NETDEV_PHY_IOCTL=y
 CONFIG_NETDEV_STATISTICS=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_WEBCLIENT=y
 CONFIG_NET_ARP_SEND=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -76,7 +76,6 @@ CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
 CONFIG_NSH_MOTD=y
 CONFIG_NSH_MOTD_STRING="VNC Server at 10.0.0.2:5900"
-CONFIG_NSH_NETINIT_THREAD=y
 CONFIG_NSH_READLINE=y
 CONFIG_NX=y
 CONFIG_NXFONT_SANS28X37=y
diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig
index 4e58c907b1b..784c14807bd 100644
--- a/configs/samv71-xult/vnxwm/defconfig
+++ b/configs/samv71-xult/vnxwm/defconfig
@@ -60,6 +60,7 @@ CONFIG_MTD_CONFIG=y
 CONFIG_NET=y
 CONFIG_NETDEV_PHY_IOCTL=y
 CONFIG_NETDEV_STATISTICS=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_WEBCLIENT=y
 CONFIG_NET_ARP_SEND=y
@@ -78,7 +79,6 @@ CONFIG_NSH_LIBRARY=y
 CONFIG_NSH_LINELEN=64
 CONFIG_NSH_MOTD=y
 CONFIG_NSH_MOTD_STRING="VNC Server at 10.0.0.2:5900"
-CONFIG_NSH_NETINIT_THREAD=y
 CONFIG_NSH_READLINE=y
 CONFIG_NX=y
 CONFIG_NXFONT_SANS22X29B=y
diff --git a/configs/shenzhou/nsh/defconfig b/configs/shenzhou/nsh/defconfig
index 7b7352568e2..3309873af42 100644
--- a/configs/shenzhou/nsh/defconfig
+++ b/configs/shenzhou/nsh/defconfig
@@ -29,13 +29,13 @@ CONFIG_MMCSD_SPICLOCK=12500000
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=40
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -49,7 +49,6 @@ CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
 CONFIG_NSH_MMCSDSPIPORTNO=1
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=10
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig
index 50d2bd47f53..78c22e81089 100644
--- a/configs/shenzhou/nxwm/defconfig
+++ b/configs/shenzhou/nxwm/defconfig
@@ -42,6 +42,7 @@ CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSCLIENT_ENTRIES=4
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -60,7 +61,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LIBRARY=y
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSH_TELNETD_CLIENTSTACKSIZE=1596
 CONFIG_NSH_TELNETD_DAEMONSTACKSIZE=1596
diff --git a/configs/shenzhou/scripts/ld.script b/configs/shenzhou/scripts/ld.script
index 8a92168c3e8..6077427b9cf 100644
--- a/configs/shenzhou/scripts/ld.script
+++ b/configs/shenzhou/scripts/ld.script
@@ -39,8 +39,8 @@
 
 MEMORY
 {
-	flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K
-	sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+        flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+        sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
 }
 
 OUTPUT_ARCH(arm)
@@ -48,69 +48,73 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The STM32F107VC has 64Kb of SRAM beginning at the following address */
+        /* The STM32F107VC has 64Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/shenzhou/scripts/ld.script.dfu b/configs/shenzhou/scripts/ld.script.dfu
index d5e9dbe95aa..4484a21d0b0 100644
--- a/configs/shenzhou/scripts/ld.script.dfu
+++ b/configs/shenzhou/scripts/ld.script.dfu
@@ -41,8 +41,8 @@
 
 MEMORY
 {
-	flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K
-	sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+        flash (rx) : ORIGIN = 0x08003000, LENGTH = 208K
+        sram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
 }
 
 OUTPUT_ARCH(arm)
@@ -50,69 +50,73 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The STM32F107VC has 64Kb of SRAM beginning at the following address */
+        /* The STM32F107VC has 64Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/shenzhou/thttpd/defconfig b/configs/shenzhou/thttpd/defconfig
index 480200f6f20..bd300baf14e 100644
--- a/configs/shenzhou/thttpd/defconfig
+++ b/configs/shenzhou/thttpd/defconfig
@@ -31,6 +31,9 @@ CONFIG_MTD_W25=y
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_DRIPADDR=0xc0a80001
+CONFIG_NETINIT_IPADDR=0xc0a80032
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_THTTPD=y
@@ -40,7 +43,6 @@ CONFIG_NET_ETH_PKTSIZE=768
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=40
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -51,11 +53,8 @@ CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
-CONFIG_NSH_DRIPADDR=0xc0a80001
 CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_IPADDR=0xc0a80032
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=16
 CONFIG_NXFLAT=y
diff --git a/configs/sim/README.txt b/configs/sim/README.txt
index e90d3cc5f78..cbdfddacae4 100644
--- a/configs/sim/README.txt
+++ b/configs/sim/README.txt
@@ -672,6 +672,9 @@ nsh2
      may not even be usable in all of those environments without some "tweaking"
      See discussion below under the nx11 configuration).
 
+     For examples, it expects to be able to include X11/Xlib.h.  That currently
+     fails on my Linux box.
+
 nx
 
   Configures to use apps/examples/nx.
@@ -849,7 +852,12 @@ nxwm
      the serial console.  So I do not believe that problem exists and
      I think that the above workaround should no longer be necessary.
      However, I will leave the above text in place until I get then
-     oppotunity to verify that the new UART simulation fixes the problem.
+     opportunity to verify that the new UART simulation fixes the problem.
+
+  2019-05-04:  Something has changed.  Today this configuration failed
+    to build because is requires CONFIG_NX_XYINPUT=y in the configuration.
+    That indicates mouse or touchscreen support.  Apparently, the current
+    NxWM will not build without this support.
 
 ostest
 
diff --git a/configs/sim/bas/defconfig b/configs/sim/bas/defconfig
index dc3d5e1a1fb..e1054199529 100644
--- a/configs/sim/bas/defconfig
+++ b/configs/sim/bas/defconfig
@@ -14,7 +14,6 @@ CONFIG_BOARD_LOOPSPERMSEC=0
 CONFIG_BOOT_RUNFROMEXTSRAM=y
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/sim/bluetooth/defconfig b/configs/sim/bluetooth/defconfig
index 6b6bc133eb8..7d160f192fb 100644
--- a/configs/sim/bluetooth/defconfig
+++ b/configs/sim/bluetooth/defconfig
@@ -9,7 +9,6 @@
 # CONFIG_NET_IPv4 is not set
 # CONFIG_NSH_CMDOPT_HEXDUMP is not set
 # CONFIG_NSH_DISABLE_DATE is not set
-# CONFIG_NSH_DISABLE_TELNETD is not set
 CONFIG_ARCH="sim"
 CONFIG_ARCH_BOARD="sim"
 CONFIG_ARCH_BOARD_SIM=y
@@ -25,7 +24,6 @@ CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEV_LOOP=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_BLUETOOTH=y
 CONFIG_DRIVERS_WIRELESS=y
 CONFIG_EXAMPLES_HELLO=y
@@ -46,6 +44,7 @@ CONFIG_NET=y
 CONFIG_NETDEVICES=y
 CONFIG_NETDEV_LATEINIT=y
 CONFIG_NETDEV_WIRELESS_IOCTL=y
+CONFIG_NETINIT_NETLOCAL=y
 CONFIG_NET_BLUETOOTH=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NFILE_DESCRIPTORS=32
@@ -54,7 +53,6 @@ CONFIG_NSH_ARCHROMFS=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FATDEVNO=2
 CONFIG_NSH_FILE_APPS=y
-CONFIG_NSH_NETLOCAL=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSH_ROMFSDEVNO=1
 CONFIG_NSH_ROMFSETC=y
diff --git a/configs/sim/configdata/defconfig b/configs/sim/configdata/defconfig
index a013be3988d..4a42be965a0 100644
--- a/configs/sim/configdata/defconfig
+++ b/configs/sim/configdata/defconfig
@@ -11,10 +11,8 @@ CONFIG_ARCH_BOARD_SIM=y
 CONFIG_ARCH_SIM=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_EXAMPLES_CONFIGDATA=y
 CONFIG_EXAMPLES_CONFIGDATA_NLOOPS=10000
 CONFIG_EXAMPLES_CONFIGDATA_SILENT=y
diff --git a/configs/sim/cxxtest/defconfig b/configs/sim/cxxtest/defconfig
index 82832a510f9..7e1cac59569 100644
--- a/configs/sim/cxxtest/defconfig
+++ b/configs/sim/cxxtest/defconfig
@@ -12,7 +12,6 @@ CONFIG_ARCH_BOARD_SIM=y
 CONFIG_ARCH_FLOAT_H=y
 CONFIG_ARCH_SIM=y
 CONFIG_BOARD_LOOPSPERMSEC=100
-CONFIG_DISABLE_POLL=y
 CONFIG_TESTING_CXXTEST=y
 CONFIG_HAVE_CXX=y
 CONFIG_IDLETHREAD_STACKSIZE=4096
diff --git a/configs/sim/dsptest/defconfig b/configs/sim/dsptest/defconfig
index be3a9c793ed..edaaf90db97 100644
--- a/configs/sim/dsptest/defconfig
+++ b/configs/sim/dsptest/defconfig
@@ -13,7 +13,6 @@ CONFIG_BUILTIN=y
 CONFIG_DEBUG_ASSERTIONS=y
 CONFIG_DEBUG_FEATURES=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_EXAMPLES_DSPTEST=y
 CONFIG_IDLETHREAD_STACKSIZE=4096
diff --git a/configs/sim/fb/defconfig b/configs/sim/fb/defconfig
index 24496626048..be7df91e84c 100644
--- a/configs/sim/fb/defconfig
+++ b/configs/sim/fb/defconfig
@@ -13,7 +13,6 @@ CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DRIVERS_VIDEO=y
 CONFIG_EXAMPLES_FB=y
diff --git a/configs/sim/ipforward/defconfig b/configs/sim/ipforward/defconfig
index cbe5c56ddf7..a393225c00b 100644
--- a/configs/sim/ipforward/defconfig
+++ b/configs/sim/ipforward/defconfig
@@ -22,7 +22,6 @@ CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEV_LOOP=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_IPFORWARD=y
 CONFIG_EXAMPLES_IPFORWARD_STACKSIZE=8192
 CONFIG_FAT_LCNAMES=y
diff --git a/configs/sim/minibasic/defconfig b/configs/sim/minibasic/defconfig
index 2db3ec59229..d17a3f81298 100644
--- a/configs/sim/minibasic/defconfig
+++ b/configs/sim/minibasic/defconfig
@@ -18,7 +18,6 @@ CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEV_LOOP=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_EXAMPLES_HELLO_STACKSIZE=8192
 CONFIG_FAT_LCNAMES=y
diff --git a/configs/sim/mount/defconfig b/configs/sim/mount/defconfig
index c43f4bc2801..634474ebf07 100644
--- a/configs/sim/mount/defconfig
+++ b/configs/sim/mount/defconfig
@@ -10,7 +10,6 @@ CONFIG_ARCH_BOARD="sim"
 CONFIG_ARCH_BOARD_SIM=y
 CONFIG_ARCH_SIM=y
 CONFIG_BOOT_RUNFROMSDRAM=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_MOUNT=y
 CONFIG_EXAMPLES_MOUNT_BLOCKDEVICE=y
 CONFIG_EXAMPLES_MOUNT_DEVNAME="/dev/ram0"
diff --git a/configs/sim/mtdpart/defconfig b/configs/sim/mtdpart/defconfig
index 267a5332551..347701a5ef7 100644
--- a/configs/sim/mtdpart/defconfig
+++ b/configs/sim/mtdpart/defconfig
@@ -11,10 +11,8 @@ CONFIG_ARCH_BOARD_SIM=y
 CONFIG_ARCH_SIM=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_EXAMPLES_MTDPART=y
 CONFIG_FS_FAT=y
 CONFIG_IDLETHREAD_STACKSIZE=4096
diff --git a/configs/sim/mtdrwb/defconfig b/configs/sim/mtdrwb/defconfig
index 9de22b388c8..81418d45e72 100644
--- a/configs/sim/mtdrwb/defconfig
+++ b/configs/sim/mtdrwb/defconfig
@@ -11,7 +11,6 @@ CONFIG_ARCH_BOARD_SIM=y
 CONFIG_ARCH_SIM=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DRVR_READAHEAD=y
 CONFIG_DRVR_WRITEBUFFER=y
diff --git a/configs/sim/nettest/defconfig b/configs/sim/nettest/defconfig
index 7b01ed75568..ccf5a1daa60 100644
--- a/configs/sim/nettest/defconfig
+++ b/configs/sim/nettest/defconfig
@@ -9,7 +9,6 @@ CONFIG_ARCH="sim"
 CONFIG_ARCH_BOARD="sim"
 CONFIG_ARCH_BOARD_SIM=y
 CONFIG_ARCH_SIM=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NETTEST=y
 CONFIG_EXAMPLES_NETTEST_DRIPADDR=0xc0a80001
 CONFIG_EXAMPLES_NETTEST_IPADDR=0xc0a80080
diff --git a/configs/sim/nsh/defconfig b/configs/sim/nsh/defconfig
index 531b0d09551..1b4ab4d8be6 100644
--- a/configs/sim/nsh/defconfig
+++ b/configs/sim/nsh/defconfig
@@ -19,7 +19,6 @@ CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEV_LOOP=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_EXAMPLES_HELLO_STACKSIZE=8192
 CONFIG_FAT_LCNAMES=y
diff --git a/configs/sim/nsh2/defconfig b/configs/sim/nsh2/defconfig
index 99d4a6e7fd9..ee5f3e02bcf 100644
--- a/configs/sim/nsh2/defconfig
+++ b/configs/sim/nsh2/defconfig
@@ -14,7 +14,6 @@ CONFIG_ARCH_BOARD_SIM=y
 CONFIG_ARCH_SIM=y
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NXHELLO=y
diff --git a/configs/sim/nx/defconfig b/configs/sim/nx/defconfig
index 755ebfa789f..3eb4e63087e 100644
--- a/configs/sim/nx/defconfig
+++ b/configs/sim/nx/defconfig
@@ -13,7 +13,6 @@ CONFIG_ARCH_BOARD_SIM=y
 CONFIG_ARCH_SIM=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NX_BPP=8
diff --git a/configs/sim/nx11/defconfig b/configs/sim/nx11/defconfig
index e532024e7e1..97615969b86 100644
--- a/configs/sim/nx11/defconfig
+++ b/configs/sim/nx11/defconfig
@@ -13,7 +13,6 @@ CONFIG_ARCH_BOARD_SIM=y
 CONFIG_ARCH_SIM=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_IDLETHREAD_STACKSIZE=4096
diff --git a/configs/sim/nxffs/defconfig b/configs/sim/nxffs/defconfig
index 6c0e10ffe3f..43a7bce0689 100644
--- a/configs/sim/nxffs/defconfig
+++ b/configs/sim/nxffs/defconfig
@@ -11,10 +11,8 @@ CONFIG_ARCH_BOARD_SIM=y
 CONFIG_ARCH_SIM=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_TESTING_NXFFS=y
 CONFIG_FS_FAT=y
 CONFIG_FS_NXFFS=y
diff --git a/configs/sim/nxlines/defconfig b/configs/sim/nxlines/defconfig
index 27c3f51b8cc..eb39feaca82 100644
--- a/configs/sim/nxlines/defconfig
+++ b/configs/sim/nxlines/defconfig
@@ -15,7 +15,6 @@ CONFIG_ARCH_BOARD_SIM=y
 CONFIG_ARCH_SIM=y
 CONFIG_BOARD_LOOPSPERMSEC=0
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_EXAMPLES_NXLINES=y
 CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x00006400
diff --git a/configs/sim/nxwm/defconfig b/configs/sim/nxwm/defconfig
index aa50fe3bb7f..78d030f614b 100644
--- a/configs/sim/nxwm/defconfig
+++ b/configs/sim/nxwm/defconfig
@@ -13,7 +13,6 @@ CONFIG_ARCH_BOARD="sim"
 CONFIG_ARCH_BOARD_SIM=y
 CONFIG_ARCH_SIM=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
diff --git a/configs/sim/ostest/defconfig b/configs/sim/ostest/defconfig
index 0d492ece2a0..c4ba181a6d1 100644
--- a/configs/sim/ostest/defconfig
+++ b/configs/sim/ostest/defconfig
@@ -11,7 +11,6 @@ CONFIG_ARCH_BOARD_SIM=y
 CONFIG_ARCH_SIM=y
 CONFIG_BOARD_LOOPSPERMSEC=100
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_NAMED_SEMAPHORES=y
 CONFIG_IDLETHREAD_STACKSIZE=4096
 CONFIG_MAX_TASKS=64
diff --git a/configs/sim/pashello/defconfig b/configs/sim/pashello/defconfig
index f0c8462c09e..97ca2b22857 100644
--- a/configs/sim/pashello/defconfig
+++ b/configs/sim/pashello/defconfig
@@ -9,7 +9,6 @@ CONFIG_ARCH="sim"
 CONFIG_ARCH_BOARD="sim"
 CONFIG_ARCH_BOARD_SIM=y
 CONFIG_ARCH_SIM=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_PASHELLO=y
 CONFIG_FS_FAT=y
 CONFIG_IDLETHREAD_STACKSIZE=4096
diff --git a/configs/sim/pf_ieee802154/defconfig b/configs/sim/pf_ieee802154/defconfig
index 3749516a42c..68f252e5d7b 100644
--- a/configs/sim/pf_ieee802154/defconfig
+++ b/configs/sim/pf_ieee802154/defconfig
@@ -24,7 +24,6 @@ CONFIG_BOARD_LOOPSPERMSEC=51262
 CONFIG_BUILTIN=y
 CONFIG_BUILTIN_PROXY_STACKSIZE=2048
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_WIRELESS=y
 CONFIG_EXAMPLES_PFIEEE802154=y
 CONFIG_EXAMPLES_PFIEEE802154_STACKSIZE1=8192
@@ -51,6 +50,7 @@ CONFIG_NET=y
 CONFIG_NETDEVICES=y
 CONFIG_NETDEV_PHY_IOCTL=y
 CONFIG_NETDEV_STATISTICS=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NET_IEEE802154=y
 CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
@@ -60,7 +60,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/sim/pktradio/defconfig b/configs/sim/pktradio/defconfig
index 30f901e9e74..3ad31c6ffd0 100644
--- a/configs/sim/pktradio/defconfig
+++ b/configs/sim/pktradio/defconfig
@@ -25,7 +25,6 @@ CONFIG_BOARD_LOOPSPERMSEC=51262
 CONFIG_BUILTIN=y
 CONFIG_BUILTIN_PROXY_STACKSIZE=2048
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_WIRELESS=y
 CONFIG_EXAMPLES_NETTEST=y
 CONFIG_EXAMPLES_NETTEST_DAEMON_STACKSIZE=4096
@@ -69,6 +68,7 @@ CONFIG_NETDEVICES=y
 CONFIG_NETDEV_PHY_IOCTL=y
 CONFIG_NETDEV_STATISTICS=y
 CONFIG_NETDEV_TELNET=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NET_6LOWPAN=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_IPv6=y
@@ -84,7 +84,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PKTRADIO_LOOPBACK=y
 CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048
diff --git a/configs/sim/sixlowpan/defconfig b/configs/sim/sixlowpan/defconfig
index 6d61eebca4c..f23488c967f 100644
--- a/configs/sim/sixlowpan/defconfig
+++ b/configs/sim/sixlowpan/defconfig
@@ -25,7 +25,6 @@ CONFIG_BOARD_LOOPSPERMSEC=51262
 CONFIG_BUILTIN=y
 CONFIG_BUILTIN_PROXY_STACKSIZE=2048
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_WIRELESS=y
 CONFIG_EXAMPLES_NETTEST=y
 CONFIG_EXAMPLES_NETTEST_DAEMON_STACKSIZE=4096
@@ -71,6 +70,7 @@ CONFIG_NETDEVICES=y
 CONFIG_NETDEV_PHY_IOCTL=y
 CONFIG_NETDEV_STATISTICS=y
 CONFIG_NETDEV_TELNET=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NET_6LOWPAN=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_IPv6=y
@@ -86,7 +86,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=2048
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/sim/spiffs/defconfig b/configs/sim/spiffs/defconfig
index 3174a5065ec..5beddd8e3f6 100644
--- a/configs/sim/spiffs/defconfig
+++ b/configs/sim/spiffs/defconfig
@@ -14,10 +14,8 @@ CONFIG_DEBUG_ASSERTIONS=y
 CONFIG_DEBUG_FEATURES=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_TESTING_FSTEST=y
 CONFIG_TESTING_FSTEST_MOUNTPT="/mnt/spiffs"
 CONFIG_TESTING_FSTEST_NLOOPS=10
diff --git a/configs/sim/touchscreen/defconfig b/configs/sim/touchscreen/defconfig
index 81a379929f5..8416da8b237 100644
--- a/configs/sim/touchscreen/defconfig
+++ b/configs/sim/touchscreen/defconfig
@@ -13,7 +13,6 @@ CONFIG_ARCH_BOARD_SIM=y
 CONFIG_ARCH_SIM=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_EXAMPLES_TOUCHSCREEN=y
 CONFIG_EXAMPLES_TOUCHSCREEN_NSAMPLES=25
diff --git a/configs/sim/traveler/defconfig b/configs/sim/traveler/defconfig
index 21c116df107..ddbf11d08b3 100644
--- a/configs/sim/traveler/defconfig
+++ b/configs/sim/traveler/defconfig
@@ -14,7 +14,6 @@ CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_ENVIRON=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DRIVERS_VIDEO=y
 CONFIG_FS_ROMFS=y
diff --git a/configs/sim/udgram/defconfig b/configs/sim/udgram/defconfig
index 2b566a4fcd0..2b43680c30a 100644
--- a/configs/sim/udgram/defconfig
+++ b/configs/sim/udgram/defconfig
@@ -17,7 +17,6 @@ CONFIG_BOARD_LOOPSPERMSEC=0
 CONFIG_BOOT_RUNFROMEXTSRAM=y
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_EXAMPLES_UDGRAM=y
 CONFIG_EXAMPLES_UDGRAM_CLIENT_STACKSIZE=8192
diff --git a/configs/sim/unionfs/defconfig b/configs/sim/unionfs/defconfig
index 9bcf5b0bbf6..f2ba849595c 100644
--- a/configs/sim/unionfs/defconfig
+++ b/configs/sim/unionfs/defconfig
@@ -14,7 +14,6 @@ CONFIG_BOARD_LOOPSPERMSEC=0
 CONFIG_BOOT_RUNFROMEXTSRAM=y
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_UNIONFS=y
 CONFIG_EXAMPLES_UNIONFS_RAMDEVNO_A=4
 CONFIG_EXAMPLES_UNIONFS_RAMDEVNO_B=5
diff --git a/configs/sim/userfs/defconfig b/configs/sim/userfs/defconfig
index d5a2cdb5988..b37b04a3599 100644
--- a/configs/sim/userfs/defconfig
+++ b/configs/sim/userfs/defconfig
@@ -20,7 +20,6 @@ CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEV_LOOP=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_EXAMPLES_USERFS=y
 CONFIG_EXAMPLES_USERFS_STACKSIZE=8192
diff --git a/configs/sim/ustream/defconfig b/configs/sim/ustream/defconfig
index 7bd45c38b9f..adf57457a08 100644
--- a/configs/sim/ustream/defconfig
+++ b/configs/sim/ustream/defconfig
@@ -18,7 +18,6 @@ CONFIG_BOARD_LOOPSPERMSEC=0
 CONFIG_BOOT_RUNFROMEXTSRAM=y
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_EXAMPLES_USTREAM=y
 CONFIG_FAT_LCNAMES=y
diff --git a/configs/skp16c26/ostest/defconfig b/configs/skp16c26/ostest/defconfig
index ea48170e34b..a8672fd2a8e 100644
--- a/configs/skp16c26/ostest/defconfig
+++ b/configs/skp16c26/ostest/defconfig
@@ -18,7 +18,6 @@ CONFIG_DEFAULT_SMALL=y
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_ENDIAN_BIG=y
 CONFIG_IDLETHREAD_STACKSIZE=256
 CONFIG_MAX_TASKS=8
diff --git a/configs/spresense/Kconfig b/configs/spresense/Kconfig
new file mode 100644
index 00000000000..5244102f5ca
--- /dev/null
+++ b/configs/spresense/Kconfig
@@ -0,0 +1,8 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_SPRESENSE
+
+endif
diff --git a/configs/spresense/README.txt b/configs/spresense/README.txt
new file mode 100644
index 00000000000..ec9fcaee054
--- /dev/null
+++ b/configs/spresense/README.txt
@@ -0,0 +1,20 @@
+README
+======
+
+Spresense is a compact development board based on Sony’s power-efficient
+multicore microcontroller CXD5602. It allows developers to create IoT
+applications in a very short time and is supported by the Arduino IDE as well
+as the more advanced NuttX based SDK.
+
+- Integrated GPS
+  The embedded GNSS with support for GPS, QZSS and GLONASS enables applications
+  where tracking is required.
+- Hi-res audio output and multi mic inputs
+  Advanced 192kHz/24 bit audio codec and amplifier for audio output, and
+  support for up to 8 mic input channels.
+- Multicore microcontroller
+  Spresense is powered by Sony's CXD5602 microcontroller (ARM® Cortex®-M4F × 6
+  cores), with a clock speed of 156 MHz.
+
+Refer to https://developer.sony.com/develop/spresense/ for further information
+about this board.
diff --git a/configs/spresense/include/board.h b/configs/spresense/include/board.h
new file mode 100644
index 00000000000..29ee204be28
--- /dev/null
+++ b/configs/spresense/include/board.h
@@ -0,0 +1,248 @@
+/****************************************************************************
+ * configs/spresense/include/board.h
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef _CONFIGS_SPRESENSE_INCLUDE_BOARD_H
+#define _CONFIGS_SPRESENSE_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+#include 
+#include 
+#include 
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking ****************************************************************/
+
+#define BOARD_XTAL_FREQUENCY        (26000000)  /* XTAL oscillator frequency */
+#define BOARD_RTCCLK_FREQUENCY      (32768)     /* RTC oscillator frequency */
+#define BOARD_INTRCOSC_FREQUENCY    (8192000)   /* Internal RC oscillator frequency */
+
+#ifdef CONFIG_CXD56_80MHz
+#  define BOARD_FCLKOUT_FREQUENCY   (80000000)
+#else
+#  define BOARD_FCLKOUT_FREQUENCY   (97500000)
+#endif
+
+#define CXD56_CCLK                  BOARD_FCLKOUT_FREQUENCY
+
+/* USB0 ********************************************************************/
+
+#define BOARD_USB0_CLKSRC           PLL0USB_CLKSEL_XTAL
+#define BOARD_USB0_MDIV             0x06167ffa /* Table 149 datsheet, valid for 12Mhz Fclkin */
+#define BOARD_USB0_NP_DIV           0x00302062 /* Table 149 datsheet, valid for 12Mhz Fclkin */
+
+/* SPIFI clocking **********************************************************/
+
+/* The SPIFI will receive clocking from a divider per the settings provided
+ * in this file.  The NuttX code will configure PLL1 as the input clock
+ * for the selected divider
+ */
+
+#undef  BOARD_SPIFI_PLL1                        /* No division */
+#undef  BOARD_SPIFI_DIVA                        /* Supports division by 1-4 */
+#undef  BOARD_SPIFI_DIVB                        /* Supports division by 1-16 */
+#undef  BOARD_SPIFI_DIVC                        /* Supports division by 1-16 */
+#undef  BOARD_SPIFI_DIVD                        /* Supports division by 1-16 */
+#undef  BOARD_SPIFI_DIVE                        /* Supports division by 1-256 */
+
+#if BOARD_FCLKOUT_FREQUENCY < 20000000
+#  define BOARD_SPIFI_PLL1          1           /* Use PLL1 directly */
+#else
+#  define BOARD_SPIFI_DIVB          1           /* Use IDIVB */
+#endif
+
+/* We need to configure the divider so that its output is as close to the
+ * desired SCLK value.  The peak data transfer rate will be about half of
+ * this frequency in bytes per second.
+ */
+
+#if BOARD_FCLKOUT_FREQUENCY < 20000000
+#  define BOARD_SPIFI_FREQUENCY     BOARD_FCLKOUT_FREQUENCY  /* 72Mhz? */
+#else
+#  define BOARD_SPIFI_DIVIDER       (14)        /* 204MHz / 14 = 14.57MHz */
+#  define BOARD_SPIFI_FREQUENCY     (102000000) /* 204MHz / 14 = 14.57MHz */
+#endif
+
+/* UART clocking ***********************************************************/
+
+/* Configure all UARTs to use the XTAL input frequency */
+
+#define BOARD_UART0_BASEFREQ        BOARD_XTAL_FREQUENCY
+#define BOARD_UART1_BASEFREQ        48750000
+#define BOARD_UART2_BASEFREQ        BOARD_XTAL_FREQUENCY
+
+/* LED definitions *********************************************************/
+
+#define BOARD_LED1          (0)
+#define BOARD_LED2          (1)
+#define BOARD_NLEDS         (2)
+
+/* LED bits for use with board_userled_all() */
+
+#define BOARD_LED1_BIT      (1 << BOARD_LED1)
+#define BOARD_LED2_BIT      (1 << BOARD_LED2)
+
+/* LED pattern for use with board_autoled_on() and board_autoled_off()
+ *           ON            OFF
+ *       LED1   LED2   LED1   LED2
+ * PTN0: OFF    OFF     -      -
+ * PTN1: ON     OFF     -      -
+ * PTN2: -      ON      -      OFF
+ *
+ */
+
+#define LED_AUTOLED_PTN0    (0)
+#define LED_AUTOLED_PTN1    (1)
+#define LED_AUTOLED_PTN2    (2)
+
+#define LED_STARTED         (LED_AUTOLED_PTN0)
+#define LED_HEAPALLOCATE    (LED_AUTOLED_PTN1)
+#define LED_IRQSENABLED     (LED_AUTOLED_PTN1)
+#define LED_STACKCREATED    (LED_AUTOLED_PTN1)
+#define LED_INIRQ           (LED_AUTOLED_PTN2)
+#define LED_SIGNAL          (LED_AUTOLED_PTN2)
+#define LED_ASSERTION       (LED_AUTOLED_PTN2)
+#define LED_PANIC           (LED_AUTOLED_PTN2)
+
+/* Buttons definitions *****************************************************/
+
+#define BOARD_NUM_BUTTONS   (2)
+
+/* Power Control definitions ***********************************************/
+
+/*     Switch    Device
+ *     --------- -------------------------------
+ *     LSW2      AcaPulco Audio Digital VDD
+ *     LSW3      SPI-Flash & TCXO
+ *     LSW4      GNSS LNA
+ *     GPO0      AcaPulco Audio Analog VDD
+ *     GPO1      Sensor 1.8V
+ *     GPO2      Sensor 3.3V
+ *     GPO3      Bluetooth/Bluetooth Low Energy
+ *     GPO4      Image Sensor 1.2V
+ *     GPO5      Image Sensor 3.3V
+ *     GPO6      eMMC 3.3V/1.8V
+ *     GPO7      Image Sensor 1.8V
+ *
+ */
+
+#define PMIC_NONE           (0)
+#define PMIC_TYPE_LSW       (1u << 8)
+#define PMIC_TYPE_GPO       (1u << 9)
+#define PMIC_TYPE_DDCLDO    (1u << 10)
+#define PMIC_GET_TYPE(v)    ((v) & 0xff00)
+#define PMIC_GET_CH(v)      ((v) & 0x00ff)
+#define PMIC_LSW(n)         (PMIC_TYPE_LSW | (1u << (n)))
+#define PMIC_GPO(n)         (PMIC_TYPE_GPO | (1u << (n)))
+#define PMIC_DDCLDO(n)      (PMIC_TYPE_DDCLDO | (1u << (n)))
+
+enum board_power_device
+{
+  /* DDC/LDO */
+
+  POWER_DDC_IO          = PMIC_DDCLDO(0),
+  POWER_LDO_EMMC        = PMIC_DDCLDO(1),
+  POWER_DDC_ANA         = PMIC_DDCLDO(2),
+  POWER_LDO_ANA         = PMIC_DDCLDO(3),
+  POWER_DDC_CORE        = PMIC_DDCLDO(4),
+  POWER_LDO_PERI        = PMIC_DDCLDO(5),
+
+  /* Load Switch */
+
+  POWER_AUDIO_DVDD      = PMIC_LSW(2),
+  POWER_FLASH           = PMIC_LSW(3),
+  POWER_TCXO            = PMIC_LSW(3),
+  POWER_LNA             = PMIC_LSW(4),
+
+  /* GPO */
+
+  POWER_AUDIO_AVDD      = PMIC_GPO(0),
+  POWER_SENSOR_18V      = PMIC_GPO(1),
+  POWER_SENSOR_33V      = PMIC_GPO(2),
+  POWER_BMI160          = POWER_SENSOR_18V,
+  POWER_SENSOR          = POWER_SENSOR_18V | POWER_SENSOR_33V,
+  POWER_BTBLE           = PMIC_GPO(3),
+  POWER_EINK            = PMIC_NONE,
+  POWER_EMMC            = PMIC_GPO(6),
+  POWER_LFOUR           = PMIC_NONE,
+  POWER_LTE             = PMIC_NONE,
+  POWER_IMAGE_SENSOR    = PMIC_GPO(4) | PMIC_GPO(5) | PMIC_GPO(7),
+};
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_boardinitialize
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_boardinitialize(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif  /* _CONFIGS_SPRESENSE_INCLUDE_BOARD_H */
diff --git a/configs/spresense/nsh/.gdbinit b/configs/spresense/nsh/.gdbinit
new file mode 100644
index 00000000000..c5fe8ea3b5e
--- /dev/null
+++ b/configs/spresense/nsh/.gdbinit
@@ -0,0 +1,15 @@
+define hookpost-load
+
+ if &g_readytorun != 0
+  eval "monitor nuttx.pid_offset %d", &((struct tcb_s *)(0))->pid
+  eval "monitor nuttx.xcpreg_offset %d", &((struct tcb_s *)(0))->xcp.regs
+  eval "monitor nuttx.state_offset %d", &((struct tcb_s *)(0))->task_state
+  eval "monitor nuttx.name_offset %d", &((struct tcb_s *)(0))->name
+  eval "monitor nuttx.name_size %d", sizeof(((struct tcb_s *)(0))->name)
+ end
+
+end
+
+define connect
+  target remote | openocd -f interface/cmsis-dap.cfg -f cxd5602.cfg -c "gdb_port pipe; log_output openocd.log"
+end
diff --git a/configs/spresense/nsh/defconfig b/configs/spresense/nsh/defconfig
new file mode 100644
index 00000000000..7160448d7f1
--- /dev/null
+++ b/configs/spresense/nsh/defconfig
@@ -0,0 +1,48 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="spresense"
+CONFIG_ARCH_BOARD_SPRESENSE=y
+CONFIG_ARCH_CHIP_CXD56XX=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_USEBASEPRI=y
+CONFIG_BOARD_LOOPSPERMSEC=5434
+CONFIG_BOOT_RUNFROMISRAM=y
+CONFIG_BUILTIN=y
+CONFIG_CLOCK_MONOTONIC=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_FS_PROCFS=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_I2C=y
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PREALLOC_WDOGS=16
+CONFIG_RAM_SIZE=1572864
+CONFIG_RAM_START=0x0d000000
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_SPI=y
+CONFIG_START_DAY=6
+CONFIG_START_MONTH=12
+CONFIG_START_YEAR=2011
+CONFIG_SYSTEM_CLE=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
+CONFIG_UART1_SERIAL_CONSOLE=y
+CONFIG_USER_ENTRYPOINT="nsh_main"
diff --git a/configs/spresense/scripts/Make.defs b/configs/spresense/scripts/Make.defs
new file mode 100644
index 00000000000..35c89687616
--- /dev/null
+++ b/configs/spresense/scripts/Make.defs
@@ -0,0 +1,150 @@
+############################################################################
+# configs/cxd56evb/nsh/Make.defs
+#
+#   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt 
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
+
+# Setup for the kind of memory that we are executing from
+
+LDSCRIPT = ramconfig.ld
+
+ifeq ($(WINTOOL),y)
+  # Windows-native toolchains
+  DIRLINK = $(TOPDIR)/tools/copydir.sh
+  DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+  MKDEP = $(TOPDIR)/tools/mkwindeps.sh
+  ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+  ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+  # Linux/Cygwin-native toolchain
+  MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+  ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+  ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+STRIP = $(CROSSDEV)strip
+
+MKNXFLAT = mknxflat
+LDNXFLAT = ldnxflat
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+  ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin -mabi=aapcs
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti -std=c++98
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+# Loadable module definitions
+
+CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs
+
+LDMODULEFLAGS = -r -e module_initialize
+ifeq ($(WINTOOL),y)
+  LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/sched/module/gnu-elf.ld}"
+else
+  LDMODULEFLAGS += -T $(TOPDIR)/sched/module/gnu-elf.ld
+endif
+
+# ELF module definitions
+
+CELFFLAGS = $(CFLAGS)
+CXXELFFLAGS = $(CXXFLAGS)
+
+LDELFFLAGS = -r -e main
+ifeq ($(WINTOOL),y)
+  LDELFFLAGS += -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/gnu-elf.ld}"
+else
+  LDELFFLAGS += -T $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/gnu-elf.ld
+endif
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+  LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  CFLAGS += -gdwarf-3
+  CXXFLAGS += -gdwarf-3
+  LDFLAGS += -g
+endif
+
+# Output map file with cross reference table
+
+ifeq ($(WINTOOL),y)
+  LDFLAGS += -Map="${shell cygpath -w $(TOPDIR)/nuttx.map}" --cref
+else
+  LDFLAGS += -Map=$(TOPDIR)/nuttx.map --cref
+endif
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =
diff --git a/configs/spresense/scripts/ramconfig.ld b/configs/spresense/scripts/ramconfig.ld
new file mode 100644
index 00000000000..5f1ef754fe1
--- /dev/null
+++ b/configs/spresense/scripts/ramconfig.ld
@@ -0,0 +1,119 @@
+/****************************************************************************
+ * configs/cxd56evb/scripts/ramconfig.ld
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+MEMORY
+{
+	ram (rwx)  : ORIGIN = 0x0d000000, LENGTH = 1536K
+}
+
+OUTPUT_ARCH(arm)
+ENTRY(__start)         /* Treat __start as the anchor for dead code stripping */
+EXTERN(_vectors)       /* Force the vectors to be included in the output */
+EXTERN(__stack)        /* Force the __stack to be included in the output */
+SECTIONS
+{
+	.text : {
+		_stext = ABSOLUTE(.);
+		*(.vectors)
+		*(.text .text.*)
+		*(.fixup)
+		*(.gnu.warning)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.t.*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.got)
+		*(.gcc_except_table)
+		*(.gnu.linkonce.r.*)
+		Image$$MODLIST$$Base = .;
+		KEEP(*(.modulelist))
+		Image$$MODLIST$$Limit = .;
+		_etext = ABSOLUTE(.);
+	} > ram
+
+	.init_section : {
+		_sinit = ABSOLUTE(.);
+		KEEP(*(.init_array .init_array.*))
+		_einit = ABSOLUTE(.);
+	} > ram
+
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} > ram
+
+	__exidx_start = ABSOLUTE(.);
+	.ARM.exidx : {
+		*(.ARM.exidx*)
+	} > ram
+	__exidx_end = ABSOLUTE(.);
+
+	_eronly = ABSOLUTE(.);
+
+	.data : {
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		CONSTRUCTORS
+		_edata = ABSOLUTE(.);
+	} > ram
+
+	.bss : {			/* BSS				*/
+		_sbss = ABSOLUTE(.);
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		_ebss = ABSOLUTE(.);
+	} > ram
+
+	/* __stack symbol is referred from mkspk tool
+	 * and means the end address of heap region */
+	PROVIDE(__stack = ORIGIN(ram) + LENGTH(ram));
+
+					/* Stabs debugging sections.	*/
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}
diff --git a/configs/spresense/src/.gitignore b/configs/spresense/src/.gitignore
new file mode 100644
index 00000000000..726d936e1e3
--- /dev/null
+++ b/configs/spresense/src/.gitignore
@@ -0,0 +1,2 @@
+/.depend
+/Make.dep
diff --git a/configs/spresense/src/Makefile b/configs/spresense/src/Makefile
new file mode 100644
index 00000000000..c7feedc0d16
--- /dev/null
+++ b/configs/spresense/src/Makefile
@@ -0,0 +1,58 @@
+############################################################################
+# configs/spresense/src/Makefile
+#
+#   Copyright 2018 Sony Semiconductor Solutions Corporation
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+
+DEPPATH = --dep-path .
+
+ASRCS =
+CSRCS = cxd56_boot.c cxd56_bringup.c
+
+ifeq ($(CONFIG_LIB_BOARDCTL),y)
+CSRCS += cxd56_appinit.c
+endif
+
+ifeq ($(CONFIG_BOARDCTL_IOCTL),y)
+CSRCS += cxd56_ioctl.c
+endif
+
+ifeq ($(CONFIG_ARCH_FPU),y)
+CSRCS += cxd56_ostest.c
+endif
+
+ifeq ($(CONFIG_ARCH_LEDS),y)
+CSRCS += cxd56_leds.c
+endif
+
+include $(TOPDIR)/configs/Board.mk
diff --git a/configs/spresense/src/cxd56_appinit.c b/configs/spresense/src/cxd56_appinit.c
new file mode 100644
index 00000000000..f699bb7ca55
--- /dev/null
+++ b/configs/spresense/src/cxd56_appinit.c
@@ -0,0 +1,94 @@
+/****************************************************************************
+ * configs/spresense/src/cxd56_appinit.c
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include "spresense.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef OK
+#  define OK 0
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ *   Perform application specific initialization.  This function is never
+ *   called directly from application code, but only indirectly via the
+ *   (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ *   arg - The boardctl() argument is passed to the board_app_initialize()
+ *         implementation without modification.  The argument has no
+ *         meaning to NuttX; the meaning of the argument is a contract
+ *         between the board-specific initialization logic and the
+ *         matching application logic.  The value cold be such things as a
+ *         mode enumeration value, a set of DIP switch switch settings, a
+ *         pointer to configuration data read from a file or serial FLASH,
+ *         or whatever you would like to do with it.  Every implementation
+ *         should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int board_app_initialize(uintptr_t arg)
+{
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+  /* Board initialization already performed by board_late_initialize() */
+
+  return OK;
+#else
+  /* Perform board-specific initialization */
+
+  return cxd56_bringup();
+#endif
+}
diff --git a/configs/spresense/src/cxd56_boot.c b/configs/spresense/src/cxd56_boot.c
new file mode 100644
index 00000000000..289071a5ff5
--- /dev/null
+++ b/configs/spresense/src/cxd56_boot.c
@@ -0,0 +1,96 @@
+/****************************************************************************
+ * configs/spresense/src/cxd56_boot.c
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include 
+#include 
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "spresense.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_boardinitialize
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void cxd56_boardinitialize(void)
+{
+}
+
+
+/****************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ *   If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
+ *   initialization call will be performed in the boot-up sequence to a
+ *   function called board_late_initialize().  board_late_initialize() will be
+ *   called immediately after up_initialize() is called and just before the
+ *   initial application is started.  This additional initialization phase
+ *   may be used, for example, to initialize board-specific device drivers.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+  /* Perform board-specific initialization */
+
+  (void)cxd56_bringup();
+}
+#endif
diff --git a/configs/spresense/src/cxd56_bringup.c b/configs/spresense/src/cxd56_bringup.c
new file mode 100644
index 00000000000..0c229d9022f
--- /dev/null
+++ b/configs/spresense/src/cxd56_bringup.c
@@ -0,0 +1,98 @@
+/****************************************************************************
+ * configs/spresense/src/cxd56_bringup.c
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "spresense.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* procfs File System */
+
+#ifdef CONFIG_FS_PROCFS
+#  ifdef CONFIG_NSH_PROC_MOUNTPOINT
+#    define CXD56_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT
+#  else
+#    define CXD56_PROCFS_MOUNTPOINT "/proc"
+#  endif
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y :
+ *     Called from board_late_initialize().
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
+ *     Called from the NSH library
+ *
+ ****************************************************************************/
+
+int cxd56_bringup(void)
+{
+  int ret;
+
+  (void) ret;
+
+#ifdef CONFIG_FS_PROCFS
+  ret = mount(NULL, CXD56_PROCFS_MOUNTPOINT, "procfs", 0, NULL);
+  if (ret < 0)
+    {
+      serr("ERROR: Failed to mount the procfs: %d\n", errno);
+    }
+#endif
+
+  return OK;
+}
diff --git a/configs/spresense/src/cxd56_ioctl.c b/configs/spresense/src/cxd56_ioctl.c
new file mode 100644
index 00000000000..1f6a0e13c5e
--- /dev/null
+++ b/configs/spresense/src/cxd56_ioctl.c
@@ -0,0 +1,117 @@
+/****************************************************************************
+ * configs/spresense/src/cxd56_ioctl.c
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "chip.h"
+#include "cxd56_uart.h"
+
+#ifdef CONFIG_BOARDCTL_IOCTL
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: boardctl
+ *
+ * Description:
+ *   In a small embedded system, there will typically be a much greater
+ *   interaction between application and low-level board features.  The
+ *   canonically correct to implement such interactions is by implementing a
+ *   character driver and performing the interactions via low level ioctl
+ *   calls.  This, however, may not be practical in many cases and will lead
+ *   to "correct" but awkward implementations.
+ *
+ *   boardctl() is non-standard OS interface to alleviate the problem.  It
+ *   basically circumvents the normal device driver ioctl interlace and allows
+ *   the application to perform direct IOCTL-like calls to the board-specific
+ *   logic.  It is especially useful for setting up board operational and
+ *   test configurations.
+ *
+ * Input Parameters:
+ *   cmd - Identifies the board command to be executed
+ *   arg - The argument that accompanies the command.  The nature of the
+ *         argument is determined by the specific command.
+ *
+ * Returned Value:
+ *   On success zero (OK) is returned; -1 (ERROR) is returned on failure
+ *   with the errno variable to to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int board_ioctl(unsigned int cmd, uintptr_t arg)
+{
+  int ret = -ENOTTY;  /* The correct return for the case of an unrecognized
+                       * command. */
+
+  switch (cmd)
+    {
+#ifdef CONFIG_USBDEV
+      /* CMD:           BOARDIOC_USBDEV_SETNOTIFYSIG
+       * DESCRIPTION:   Set signal id for notify USB device connection status
+       *                and supply current value.
+       * ARG:           None
+       * CONFIGURATION: CONFIG_LIB_BOARDCTL
+       * DEPENDENCIES:  Board logic must provide board_app_initialization
+       */
+
+      case BOARDIOC_USBDEV_SETNOTIFYSIG:
+        {
+          ret = cxd56_usbdev_setsigno((int)arg);
+        }
+        break;
+#endif
+      default:
+        break;
+    }
+
+  /* Any failure errno value will be set in boardctl() */
+
+  return ret;
+}
+#endif
diff --git a/configs/spresense/src/cxd56_leds.c b/configs/spresense/src/cxd56_leds.c
new file mode 100644
index 00000000000..0c3bcf001d1
--- /dev/null
+++ b/configs/spresense/src/cxd56_leds.c
@@ -0,0 +1,79 @@
+/****************************************************************************
+ * configs/spresense/src/cxd56_leds.c
+ *
+ *   Copyright 2018 Sony Semiconductor Solutions Corporation
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name of Sony Semiconductor Solutions Corporation nor
+ *    the names of its contributors may be used to endorse or promote
+ *    products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#ifdef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_autoled_initialize
+ ****************************************************************************/
+
+void board_autoled_initialize(void)
+{
+}
+
+/****************************************************************************
+ * Name: board_autoled_on
+ ****************************************************************************/
+
+void board_autoled_on(int led)
+{
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
+
+void board_autoled_off(int led)
+{
+}
+
+#endif /* CONFIG_ARCH_LEDS */
diff --git a/configs/spresense/src/cxd56_ostest.c b/configs/spresense/src/cxd56_ostest.c
new file mode 100644
index 00000000000..77cd95f4bb1
--- /dev/null
+++ b/configs/spresense/src/cxd56_ostest.c
@@ -0,0 +1,113 @@
+/****************************************************************************
+ * configs/spresense/src/cxd56_ostest.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#undef HAVE_FPU
+#if defined(CONFIG_ARCH_FPU) && defined(CONFIG_EXAMPLES_OSTEST_FPUSIZE) && \
+    defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_ARMV7M_CMNVECTOR)
+#    define HAVE_FPU 1
+#endif
+
+#ifdef HAVE_FPU
+
+#if CONFIG_EXAMPLES_OSTEST_FPUSIZE != (4*SW_FPU_REGS)
+#  error "CONFIG_EXAMPLES_OSTEST_FPUSIZE has the wrong size"
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint32_t g_saveregs[XCPTCONTEXT_REGS];
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/* Given an array of size CONFIG_EXAMPLES_OSTEST_FPUSIZE, this function will
+ * return the current FPU registers.
+ */
+
+void arch_getfpu(FAR uint32_t *fpusave)
+{
+  irqstate_t flags;
+
+  /* Take a snapshot of the thread context right now */
+
+  flags = enter_critical_section();
+  up_saveusercontext(g_saveregs);
+
+  /* Return only the floating register values */
+
+  memcpy(fpusave, &g_saveregs[REG_S0], (4*SW_FPU_REGS));
+  leave_critical_section(flags);
+}
+
+/* Given two arrays of size CONFIG_EXAMPLES_OSTEST_FPUSIZE this function
+ * will compare them and return true if they are identical.
+ */
+
+bool arch_cmpfpu(FAR const uint32_t *fpusave1, FAR const uint32_t *fpusave2)
+{
+  return memcmp(fpusave1, fpusave2, (4*SW_FPU_REGS)) == 0;
+}
+
+#endif /* HAVE_FPU */
diff --git a/configs/spresense/src/spresense.h b/configs/spresense/src/spresense.h
new file mode 100644
index 00000000000..e8b9b4f3e66
--- /dev/null
+++ b/configs/spresense/src/spresense.h
@@ -0,0 +1,80 @@
+/****************************************************************************
+ * configs/spresense/src/spresense.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __CONFIGS_SPRESENSE_SRC_SPRESENSE_H
+#define __CONFIGS_SPRESENSE_SRC_SPRESENSE_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: cxd56_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y :
+ *     Called from board_late_initialize().
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
+ *     Called from the NSH library
+ *
+ ****************************************************************************/
+
+int cxd56_bringup(void);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __CONFIGS_SPRESENSE_SRC_SPRESENSE_H */
diff --git a/configs/stm3210e-eval/README.txt b/configs/stm3210e-eval/README.txt
index 43a32719b9c..8bf188b20c4 100644
--- a/configs/stm3210e-eval/README.txt
+++ b/configs/stm3210e-eval/README.txt
@@ -235,7 +235,7 @@ SRAM3.  This memory will appear at address 0x68000000.
 The on-board SRAM can be configured by setting
 
   CONFIG_STM32_FSMC=y                         : Enables the FSMC
-  CONFIG_STM32_FSMC_SRAM=y                    : Enable external SRAM support
+  CONFIG_STM32_EXTERNAL_RAM=y                 : Enable external SRAM support
   CONFIG_HEAP2_BASE=0x68000000                : SRAM will be located at 0x680000000
   CONFIG_HEAP2_SIZE=1048576                   : The size of the SRAM is 1Mbyte
   CONFIG_MM_REGIONS=2                         : There will be two memory regions
@@ -716,7 +716,6 @@ Where  is one of the following:
 
           Pre-requisites:
 
-            CONFIG_DISABLE_POLL=n      # Don't disable poll()
             CONFIG_BUILTIN=y           # Enable support for built-in applications
             CONFIG_NSH_BUILTIN_APPS=y  # Enable NSH built-in applications
 
diff --git a/configs/stm3210e-eval/composite/defconfig b/configs/stm3210e-eval/composite/defconfig
index cb702759b6e..79ccdf2f3ba 100644
--- a/configs/stm3210e-eval/composite/defconfig
+++ b/configs/stm3210e-eval/composite/defconfig
@@ -25,7 +25,6 @@ CONFIG_COMPOSITE_PRODUCTID=0x2022
 CONFIG_COMPOSITE_PRODUCTSTR="Composite Device"
 CONFIG_COMPOSITE_SERIALSTR="12345"
 CONFIG_COMPOSITE_VENDORID=0x03eb
-CONFIG_DISABLE_POLL=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_LIB_BOARDCTL=y
diff --git a/configs/stm3210e-eval/nsh/defconfig b/configs/stm3210e-eval/nsh/defconfig
index 1ffe2736e46..5ec39d7c06e 100644
--- a/configs/stm3210e-eval/nsh/defconfig
+++ b/configs/stm3210e-eval/nsh/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_CHIP_STM32F103ZE=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=5483
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FS_FAT=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/stm3210e-eval/nsh2/defconfig b/configs/stm3210e-eval/nsh2/defconfig
index 34e8faba197..b7b3318cbe4 100644
--- a/configs/stm3210e-eval/nsh2/defconfig
+++ b/configs/stm3210e-eval/nsh2/defconfig
@@ -27,7 +27,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=5483
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NXHELLO=y
 CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011
diff --git a/configs/stm3210e-eval/nx/defconfig b/configs/stm3210e-eval/nx/defconfig
index b5d32706dbe..c491ae71fbd 100644
--- a/configs/stm3210e-eval/nx/defconfig
+++ b/configs/stm3210e-eval/nx/defconfig
@@ -23,7 +23,6 @@ CONFIG_BOARD_LOOPSPERMSEC=5483
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NX_BGCOLOR=0x0011
diff --git a/configs/stm3210e-eval/nxterm/defconfig b/configs/stm3210e-eval/nxterm/defconfig
index 330184a8434..16ac4bcd9ff 100644
--- a/configs/stm3210e-eval/nxterm/defconfig
+++ b/configs/stm3210e-eval/nxterm/defconfig
@@ -21,7 +21,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=5483
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NXTERM=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/stm3210e-eval/pm/defconfig b/configs/stm3210e-eval/pm/defconfig
index a1fcdde9d6b..e78ce440304 100644
--- a/configs/stm3210e-eval/pm/defconfig
+++ b/configs/stm3210e-eval/pm/defconfig
@@ -29,7 +29,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=5483
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NXHELLO=y
 CONFIG_EXAMPLES_NXHELLO_BGCOLOR=0x0011
diff --git a/configs/stm3210e-eval/scripts/ld.script b/configs/stm3210e-eval/scripts/ld.script
index 5444c56ab34..4db5e1d90e8 100644
--- a/configs/stm3210e-eval/scripts/ld.script
+++ b/configs/stm3210e-eval/scripts/ld.script
@@ -51,69 +51,73 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The STM32F103Z has 64Kb of SRAM beginning at the following address */
+        /* The STM32F103Z has 64Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/stm3210e-eval/scripts/ld.script.dfu b/configs/stm3210e-eval/scripts/ld.script.dfu
index 09e3ab875f5..5c6bbac1632 100644
--- a/configs/stm3210e-eval/scripts/ld.script.dfu
+++ b/configs/stm3210e-eval/scripts/ld.script.dfu
@@ -50,69 +50,73 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The STM32F103Z has 64Kb of SRAM beginning at the following address */
+        /* The STM32F103Z has 64Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/stm3210e-eval/src/stm3210e-eval.h b/configs/stm3210e-eval/src/stm3210e-eval.h
index 7083195f778..94ef3ee1d45 100644
--- a/configs/stm3210e-eval/src/stm3210e-eval.h
+++ b/configs/stm3210e-eval/src/stm3210e-eval.h
@@ -268,26 +268,6 @@ void stm32_extcontextrestore(struct extmem_save_s *restore);
 
 void stm32_extmemgpios(const uint16_t *gpios, int ngpios);
 
-/************************************************************************************
- * Name: stm32_enablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-void stm32_enablefsmc(void);
-
-/************************************************************************************
- * Name: stm32_disablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-void stm32_disablefsmc(void);
-
 /************************************************************************************
  * Name: stm32_selectnor
  *
diff --git a/configs/stm3210e-eval/src/stm32_boot.c b/configs/stm3210e-eval/src/stm32_boot.c
index da7371612f1..e03c3fa6160 100644
--- a/configs/stm3210e-eval/src/stm32_boot.c
+++ b/configs/stm3210e-eval/src/stm32_boot.c
@@ -71,9 +71,9 @@
 
 void stm32_boardinitialize(void)
 {
-  /* If the FSMC and FSMC_SRAM are selected, then enable SRAM access */
+  /* If the FSMC and external RAM are selected, then enable SRAM access */
 
-#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_FSMC_SRAM)
+#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_EXTERNAL_RAM)
   stm32_selectsram();
 #endif
 
diff --git a/configs/stm3210e-eval/src/stm32_deselectlcd.c b/configs/stm3210e-eval/src/stm32_deselectlcd.c
index b9c155e3db7..10d5819d96e 100644
--- a/configs/stm3210e-eval/src/stm32_deselectlcd.c
+++ b/configs/stm3210e-eval/src/stm32_deselectlcd.c
@@ -42,7 +42,7 @@
 #include 
 
 #include "up_arch.h"
-#include "stm32_fsmc.h"
+#include "stm32.h"
 #include "stm3210e-eval.h"
 
 #ifdef CONFIG_STM32_FSMC
@@ -87,7 +87,7 @@ void stm32_deselectlcd(void)
 
   /* Disable AHB clocking to the FSMC */
 
-  stm32_disablefsmc();
+  stm32_fsmc_disable();
 }
 
 #endif /* CONFIG_STM32_FSMC */
diff --git a/configs/stm3210e-eval/src/stm32_deselectnor.c b/configs/stm3210e-eval/src/stm32_deselectnor.c
index a46fb9bde2f..949493bd04c 100644
--- a/configs/stm3210e-eval/src/stm32_deselectnor.c
+++ b/configs/stm3210e-eval/src/stm32_deselectnor.c
@@ -42,7 +42,7 @@
 #include 
 
 #include "up_arch.h"
-#include "stm32_fsmc.h"
+#include "stm32.h"
 #include "stm3210e-eval.h"
 
 #ifdef CONFIG_STM32_FSMC
@@ -87,7 +87,7 @@ void stm32_deselectnor(void)
 
   /* Disable AHB clocking to the FSMC */
 
-  stm32_disablefsmc();
+  stm32_fsmc_disable();
 }
 
 #endif /* CONFIG_STM32_FSMC */
diff --git a/configs/stm3210e-eval/src/stm32_deselectsram.c b/configs/stm3210e-eval/src/stm32_deselectsram.c
index a57cab1f6ac..974351f350a 100644
--- a/configs/stm3210e-eval/src/stm32_deselectsram.c
+++ b/configs/stm3210e-eval/src/stm32_deselectsram.c
@@ -42,7 +42,7 @@
 #include 
 
 #include "up_arch.h"
-#include "stm32_fsmc.h"
+#include "stm32.h"
 #include "stm3210e-eval.h"
 
 #ifdef CONFIG_STM32_FSMC
@@ -87,10 +87,7 @@ void stm32_deselectsram(void)
 
   /* Disable AHB clocking to the FSMC */
 
-  stm32_disablefsmc();
+  stm32_fsmc_disable();
 }
 
 #endif /* CONFIG_STM32_FSMC */
-
-
-
diff --git a/configs/stm3210e-eval/src/stm32_extmem.c b/configs/stm3210e-eval/src/stm32_extmem.c
index 27602797b3e..24d2b3ae059 100644
--- a/configs/stm3210e-eval/src/stm32_extmem.c
+++ b/configs/stm3210e-eval/src/stm32_extmem.c
@@ -48,7 +48,6 @@
 #include "chip.h"
 #include "up_arch.h"
 
-#include "stm32_fsmc.h"
 #include "stm32_gpio.h"
 #include "stm32.h"
 #include "stm3210e-eval.h"
@@ -150,41 +149,3 @@ void stm32_extmemgpios(const uint16_t *gpios, int ngpios)
       stm32_configgpio(gpios[i]);
     }
 }
-
-/************************************************************************************
- * Name: stm32_enablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-void stm32_enablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Enable AHB clocking to the FSMC */
-
-  regval  = getreg32( STM32_RCC_AHBENR);
-  regval |= RCC_AHBENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHBENR);
-}
-
-/************************************************************************************
- * Name: stm32_disablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-void stm32_disablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Enable AHB clocking to the FSMC */
-
-  regval  = getreg32( STM32_RCC_AHBENR);
-  regval &= ~RCC_AHBENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHBENR);
-}
diff --git a/configs/stm3210e-eval/src/stm32_selectlcd.c b/configs/stm3210e-eval/src/stm32_selectlcd.c
index cead59ae571..607981c89ef 100644
--- a/configs/stm3210e-eval/src/stm32_selectlcd.c
+++ b/configs/stm3210e-eval/src/stm32_selectlcd.c
@@ -122,7 +122,7 @@ void stm32_selectlcd(void)
 
   /* Enable AHB clocking to the FSMC */
 
-  stm32_enablefsmc();
+  stm32_fsmc_enable();
 
   /* Bank4 NOR/SRAM control register configuration */
 
diff --git a/configs/stm3210e-eval/src/stm32_selectnor.c b/configs/stm3210e-eval/src/stm32_selectnor.c
index 3d16203c073..b4e6161d998 100644
--- a/configs/stm3210e-eval/src/stm32_selectnor.c
+++ b/configs/stm3210e-eval/src/stm32_selectnor.c
@@ -119,7 +119,7 @@ void stm32_selectnor(void)
 
   /* Enable AHB clocking to the FSMC */
 
-  stm32_enablefsmc();
+  stm32_fsmc_enable();
 
   /* Bank1 NOR/SRAM control register configuration */
 
diff --git a/configs/stm3210e-eval/src/stm32_selectsram.c b/configs/stm3210e-eval/src/stm32_selectsram.c
index 305f29e8eb1..30dde10d705 100644
--- a/configs/stm3210e-eval/src/stm32_selectsram.c
+++ b/configs/stm3210e-eval/src/stm32_selectsram.c
@@ -122,7 +122,7 @@ void stm32_selectsram(void)
 
   /* Enable AHB clocking to the FSMC */
 
-  stm32_enablefsmc();
+  stm32_fsmc_enable();
 
   /* Bank1 NOR/SRAM control register configuration */
 
diff --git a/configs/stm3210e-eval/usbmsc/defconfig b/configs/stm3210e-eval/usbmsc/defconfig
index db825e80ed1..6abb054ae66 100644
--- a/configs/stm3210e-eval/usbmsc/defconfig
+++ b/configs/stm3210e-eval/usbmsc/defconfig
@@ -15,7 +15,6 @@ CONFIG_ARCH_CHIP_STM32F103ZE=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=5483
-CONFIG_DISABLE_POLL=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_LIB_BOARDCTL=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/stm3210e-eval/usbserial/defconfig b/configs/stm3210e-eval/usbserial/defconfig
index da0b768e4ae..6ef50d80ebd 100644
--- a/configs/stm3210e-eval/usbserial/defconfig
+++ b/configs/stm3210e-eval/usbserial/defconfig
@@ -15,7 +15,6 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=5483
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_USBSERIAL=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_LIB_BOARDCTL=y
diff --git a/configs/stm3220g-eval/README.txt b/configs/stm3220g-eval/README.txt
index 68b4859cd6a..9e259d9cd2e 100644
--- a/configs/stm3220g-eval/README.txt
+++ b/configs/stm3220g-eval/README.txt
@@ -163,7 +163,7 @@ select CAN1 or CAN2 if fitted; neither if not fitted.
 The on-board SRAM can be configured by setting
 
   CONFIG_STM32_FSMC=y
-  CONFIG_STM32_FSMC_SRAM=y
+  CONFIG_STM32_EXTERNAL_RAM=y
   CONFIG_HEAP2_BASE=0x64000000
   CONFIG_HEAP2_SIZE=2097152
   CONFIG_MM_REGIONS=2
@@ -176,15 +176,15 @@ to internal SRAM, SRAM may also be available through the FSMC.  In order to
 use FSMC SRAM, the following additional things need to be present in the
 NuttX configuration file:
 
-  CONFIG_STM32_FSMC=y        : Enables the FSMC
-  CONFIG_STM32_FSMC_SRAM=y   : Indicates that SRAM is available via the
-                               FSMC (as opposed to an LCD or FLASH).
-  CONFIG_HEAP2_BASE          : The base address of the SRAM in the FSMC
-                               address space
-  CONFIG_HEAP2_SIZE          : The size of the SRAM in the FSMC
-                               address space
-  CONFIG_MM_REGIONS          : Must be set to a large enough value to
-                               include the FSMC SRAM
+  CONFIG_STM32_FSMC=y         : Enables the FSMC
+  CONFIG_STM32_EXTERNAL_RAM=y : Indicates that SRAM is available via the
+                                FSMC (as opposed to an LCD or FLASH).
+  CONFIG_HEAP2_BASE           : The base address of the SRAM in the FSMC
+                                address space
+  CONFIG_HEAP2_SIZE           : The size of the SRAM in the FSMC
+                                address space
+  CONFIG_MM_REGIONS           : Must be set to a large enough value to
+                                include the FSMC SRAM
 
 SRAM Configurations
 -------------------
@@ -194,7 +194,7 @@ There are 2 possible SRAM configurations:
                    CONFIG_MM_REGIONS == 1
   Configuration 2. System SRAM and FSMC SRAM
                    CONFIG_MM_REGIONS == 2
-                   CONFIG_STM32_FSMC_SRAM defined
+                   CONFIG_STM32_EXTERNAL_RAM defined
 
 I/O Expanders
 =============
@@ -285,7 +285,7 @@ STM3220G-EVAL-specific Configuration Options
     In order to use FSMC SRAM, the following additional things need to be
     present in the NuttX configuration file:
 
-    CONFIG_STM32_FSMC_SRAM - Indicates that SRAM is available via the
+    CONFIG_STM32_EXTERNAL_RAM - Indicates that SRAM is available via the
       FSMC (as opposed to an LCD or FLASH).
 
     CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space (hex)
@@ -668,10 +668,6 @@ Where  is one of the following:
        CONFIG_NETUTILS_FTPD=y
        CONFIG_EXAMPLES_FTPD=y
 
-       And enable poll() support in the NuttX configuration file:
-
-       CONFIG_DISABLE_POLL=n
-
     8. This example supports the watchdog timer test (apps/examples/watchdog)
        but this must be manually enabled by selecting:
 
diff --git a/configs/stm3220g-eval/dhcpd/defconfig b/configs/stm3220g-eval/dhcpd/defconfig
index c5e4075fe51..dbd423fe051 100644
--- a/configs/stm3220g-eval/dhcpd/defconfig
+++ b/configs/stm3220g-eval/dhcpd/defconfig
@@ -17,7 +17,6 @@ CONFIG_BOARD_LOOPSPERMSEC=10926
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_ETH0_PHY_DP83848C=y
 CONFIG_EXAMPLES_DHCPD=y
diff --git a/configs/stm3220g-eval/nettest/defconfig b/configs/stm3220g-eval/nettest/defconfig
index 2f743c8e2d7..7fdaf0e4130 100644
--- a/configs/stm3220g-eval/nettest/defconfig
+++ b/configs/stm3220g-eval/nettest/defconfig
@@ -17,7 +17,6 @@ CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_ETH0_PHY_DP83848C=y
 CONFIG_EXAMPLES_NETTEST=y
diff --git a/configs/stm3220g-eval/nsh2/defconfig b/configs/stm3220g-eval/nsh2/defconfig
index 87c5511e248..23b8942591c 100644
--- a/configs/stm3220g-eval/nsh2/defconfig
+++ b/configs/stm3220g-eval/nsh2/defconfig
@@ -42,6 +42,7 @@ CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSCLIENT_ENTRIES=4
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -49,7 +50,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=40
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -62,7 +62,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=10
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig
index a9d0a47fd8e..fe51ea578d5 100644
--- a/configs/stm3220g-eval/nxwm/defconfig
+++ b/configs/stm3220g-eval/nxwm/defconfig
@@ -43,13 +43,13 @@ CONFIG_MMCSD=y
 CONFIG_MMCSD_MULTIBLOCK_DISABLE=y
 CONFIG_MQ_MAXMSGSIZE=64
 CONFIG_NET=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=40
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -61,7 +61,6 @@ CONFIG_NFILE_STREAMS=12
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LIBRARY=y
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=10
 CONFIG_NX=y
diff --git a/configs/stm3220g-eval/scripts/ld.script b/configs/stm3220g-eval/scripts/ld.script
index 93440169d2e..8e780c4b532 100644
--- a/configs/stm3220g-eval/scripts/ld.script
+++ b/configs/stm3220g-eval/scripts/ld.script
@@ -56,67 +56,71 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/stm3220g-eval/src/stm3220g-eval.h b/configs/stm3220g-eval/src/stm3220g-eval.h
index 95e603fd17a..df8b87f9b4b 100644
--- a/configs/stm3220g-eval/src/stm3220g-eval.h
+++ b/configs/stm3220g-eval/src/stm3220g-eval.h
@@ -341,30 +341,6 @@ void stm32_extmemaddr(int naddrs);
 void stm32_extmemdata(int ndata);
 #endif
 
-/****************************************************************************************************
- * Name: stm32_enablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ****************************************************************************************************/
-
-#ifdef CONFIG_STM32_FSMC
-void stm32_enablefsmc(void);
-#endif
-
-/****************************************************************************************************
- * Name: stm32_disablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ****************************************************************************************************/
-
-#ifdef CONFIG_STM32_FSMC
-void stm32_disablefsmc(void);
-#endif
-
 /****************************************************************************************************
  * Name: stm32_selectsram
  *
diff --git a/configs/stm3220g-eval/src/stm32_deselectlcd.c b/configs/stm3220g-eval/src/stm32_deselectlcd.c
index 56d86cf242b..abe237207db 100644
--- a/configs/stm3220g-eval/src/stm32_deselectlcd.c
+++ b/configs/stm3220g-eval/src/stm32_deselectlcd.c
@@ -43,7 +43,7 @@
 #include 
 
 #include "up_arch.h"
-#include "stm32_fsmc.h"
+#include "stm32.h"
 #include "stm3220g-eval.h"
 
 #ifdef CONFIG_STM32_FSMC
@@ -88,7 +88,7 @@ void stm32_deselectlcd(void)
 
   /* Disable AHB clocking to the FSMC */
 
-  stm32_disablefsmc();
+  stm32_fsmc_disable();
 }
 
 #endif /* CONFIG_STM32_FSMC */
diff --git a/configs/stm3220g-eval/src/stm32_deselectsram.c b/configs/stm3220g-eval/src/stm32_deselectsram.c
index de5027f2c25..1114dd2aaed 100644
--- a/configs/stm3220g-eval/src/stm32_deselectsram.c
+++ b/configs/stm3220g-eval/src/stm32_deselectsram.c
@@ -42,7 +42,7 @@
 #include 
 
 #include "up_arch.h"
-#include "stm32_fsmc.h"
+#include "stm32.h"
 #include "stm3220g-eval.h"
 
 #ifdef CONFIG_STM32_FSMC
@@ -87,7 +87,7 @@ void stm32_deselectsram(void)
 
   /* Disable AHB clocking to the FSMC */
 
-  stm32_disablefsmc();
+  stm32_fsmc_disable();
 }
 
 #endif /* CONFIG_STM32_FSMC */
diff --git a/configs/stm3220g-eval/src/stm32_extmem.c b/configs/stm3220g-eval/src/stm32_extmem.c
index f6dd8a5a19e..0ec8d1c7604 100644
--- a/configs/stm3220g-eval/src/stm32_extmem.c
+++ b/configs/stm3220g-eval/src/stm32_extmem.c
@@ -48,7 +48,6 @@
 #include "chip.h"
 #include "up_arch.h"
 
-#include "stm32_fsmc.h"
 #include "stm32_gpio.h"
 #include "stm32.h"
 #include "stm3220g-eval.h"
@@ -147,41 +146,3 @@ void stm32_extmemdata(int ndata)
 {
   stm32_extmemgpios(g_dataconfig, ndata);
 }
-
-/************************************************************************************
- * Name: stm32_enablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-void stm32_enablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Enable AHB clocking to the FSMC */
-
-  regval  = getreg32( STM32_RCC_AHB3ENR);
-  regval |= RCC_AHB3ENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHB3ENR);
-}
-
-/************************************************************************************
- * Name: stm32_disablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-void stm32_disablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Disable AHB clocking to the FSMC */
-
-  regval  = getreg32(STM32_RCC_AHB3ENR);
-  regval &= ~RCC_AHB3ENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHB3ENR);
-}
diff --git a/configs/stm3220g-eval/src/stm32_selectlcd.c b/configs/stm3220g-eval/src/stm32_selectlcd.c
index 8c5193994dc..927cf00bbf8 100644
--- a/configs/stm3220g-eval/src/stm32_selectlcd.c
+++ b/configs/stm3220g-eval/src/stm32_selectlcd.c
@@ -135,7 +135,7 @@ void stm32_selectlcd(void)
 
   /* Enable AHB clocking to the FSMC */
 
-  stm32_enablefsmc();
+  stm32_fsmc_enable();
 
   /* Color LCD configuration (LCD configured as follow):
    *
diff --git a/configs/stm3220g-eval/src/stm32_selectsram.c b/configs/stm3220g-eval/src/stm32_selectsram.c
index 1cdcffa1b39..9022ddb2a28 100644
--- a/configs/stm3220g-eval/src/stm32_selectsram.c
+++ b/configs/stm3220g-eval/src/stm32_selectsram.c
@@ -149,7 +149,7 @@ void stm32_selectsram(void)
 
   /* Enable AHB clocking to the FSMC */
 
-  stm32_enablefsmc();
+  stm32_fsmc_enable();
 
   /* Bank1 NOR/SRAM control register configuration
    *
diff --git a/configs/stm3220g-eval/telnetd/defconfig b/configs/stm3220g-eval/telnetd/defconfig
index 7bf2e0ed303..598987dca59 100644
--- a/configs/stm3220g-eval/telnetd/defconfig
+++ b/configs/stm3220g-eval/telnetd/defconfig
@@ -17,7 +17,6 @@ CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_ETH0_PHY_DP83848C=y
 CONFIG_EXAMPLES_TELNETD=y
diff --git a/configs/stm3240g-eval/README.txt b/configs/stm3240g-eval/README.txt
index 750acce0ec8..369d2473682 100644
--- a/configs/stm3240g-eval/README.txt
+++ b/configs/stm3240g-eval/README.txt
@@ -233,7 +233,7 @@ select CAN1 or CAN2 if fitted; neither if not fitted.
 The on-board SRAM can be configured by setting
 
   CONFIG_STM32_FSMC=y
-  CONFIG_STM32_FSMC_SRAM=y
+  CONFIG_STM32_EXTERNAL_RAM=y
   CONFIG_HEAP2_BASE=0x64000000
   CONFIG_HEAP2_SIZE=2097152
   CONFIG_MM_REGIONS=2 (or =3, see below)
@@ -251,15 +251,15 @@ In addition to internal SRAM, SRAM may also be available through the FSMC.
 In order to use FSMC SRAM, the following additional things need to be
 present in the NuttX configuration file:
 
-  CONFIG_STM32_FSMC=y        : Enables the FSMC
-  CONFIG_STM32_FSMC_SRAM=y   : Indicates that SRAM is available via the
-                               FSMC (as opposed to an LCD or FLASH).
-  CONFIG_HEAP2_BASE          : The base address of the SRAM in the FSMC
+  CONFIG_STM32_FSMC=y         : Enables the FSMC
+  CONFIG_STM32_EXTERNAL_RAM=y : Indicates that SRAM is available via the
+                                FSMC (as opposed to an LCD or FLASH).
+  CONFIG_HEAP2_BASE           : The base address of the SRAM in the FSMC
                                address space
-  CONFIG_HEAP2_SIZE          : The size of the SRAM in the FSMC
-                               address space
-  CONFIG_MM_REGIONS          : Must be set to a large enough value to
-                               include the FSMC SRAM
+  CONFIG_HEAP2_SIZE           : The size of the SRAM in the FSMC
+                                address space
+  CONFIG_MM_REGIONS           : Must be set to a large enough value to
+                                include the FSMC SRAM
 
 SRAM Configurations
 -------------------
@@ -267,19 +267,19 @@ There are 4 possible SRAM configurations:
 
   Configuration 1. System SRAM (only)
                    CONFIG_MM_REGIONS == 1
-                   CONFIG_STM32_FSMC_SRAM NOT defined
+                   CONFIG_STM32_EXTERNAL_RAM NOT defined
                    CONFIG_STM32_CCMEXCLUDE defined
   Configuration 2. System SRAM and CCM SRAM
                    CONFIG_MM_REGIONS == 2
-                   CONFIG_STM32_FSMC_SRAM NOT defined
+                   CONFIG_STM32_EXTERNAL_RAM NOT defined
                    CONFIG_STM32_CCMEXCLUDE NOT defined
   Configuration 3. System SRAM and FSMC SRAM
                    CONFIG_MM_REGIONS == 2
-                   CONFIG_STM32_FSMC_SRAM defined
+                   CONFIG_STM32_EXTERNAL_RAM defined
                    CONFIG_STM32_CCMEXCLUDE defined
   Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM
                    CONFIG_MM_REGIONS == 3
-                   CONFIG_STM32_FSMC_SRAM defined
+                   CONFIG_STM32_ETXERNAL_RAM defined
                    CONFIG_STM32_CCMEXCLUDE NOT defined
 I/O Expanders
 =============
@@ -372,7 +372,7 @@ STM3240G-EVAL-specific Configuration Options
     In order to use FSMC SRAM, the following additional things need to be
     present in the NuttX configuration file:
 
-    CONFIG_STM32_FSMC_SRAM - Indicates that SRAM is available via the
+    CONFIG_STM32_EXTERNAL_RAM - Indicates that SRAM is available via the
       FSMC (as opposed to an LCD or FLASH).
 
     CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space (hex)
@@ -976,10 +976,6 @@ Where  is one of the following:
        CONFIG_NETUTILS_FTPD=y
        CONFIG_EXAMPLES_FTPD=y
 
-       And enable poll() support in the NuttX configuration file:
-
-       CONFIG_DISABLE_POLL=n
-
     8. This example supports the watchdog timer test (apps/examples/watchdog)
        but this must be manually enabled by selecting:
 
diff --git a/configs/stm3240g-eval/dhcpd/defconfig b/configs/stm3240g-eval/dhcpd/defconfig
index 864b5ee59a9..baee10f8564 100644
--- a/configs/stm3240g-eval/dhcpd/defconfig
+++ b/configs/stm3240g-eval/dhcpd/defconfig
@@ -18,7 +18,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_ETH0_PHY_DP83848C=y
 CONFIG_EXAMPLES_DHCPD=y
diff --git a/configs/stm3240g-eval/fb/defconfig b/configs/stm3240g-eval/fb/defconfig
index 468327e02ae..03219db0ee5 100644
--- a/configs/stm3240g-eval/fb/defconfig
+++ b/configs/stm3240g-eval/fb/defconfig
@@ -15,7 +15,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_VIDEO=y
 CONFIG_EXAMPLES_FB=y
 CONFIG_EXAMPLES_PDCURSES=y
@@ -65,7 +64,7 @@ CONFIG_SDCLONE_DISABLE=y
 CONFIG_START_DAY=17
 CONFIG_START_MONTH=9
 CONFIG_STM32_FSMC=y
-CONFIG_STM32_FSMC_SRAM=y
+CONFIG_STM32_EXTERNAL_RAM=y
 CONFIG_STM32_I2C1=y
 CONFIG_STM32_JTAG_FULL_ENABLE=y
 CONFIG_STM32_PWR=y
diff --git a/configs/stm3240g-eval/include/board.h b/configs/stm3240g-eval/include/board.h
index ab14d860414..8901fb8773b 100644
--- a/configs/stm3240g-eval/include/board.h
+++ b/configs/stm3240g-eval/include/board.h
@@ -285,7 +285,7 @@
  * select CAN1 or CAN2 if fitted; neither if not fitted.
  */
 
-#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_FSMC_SRAM)
+#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_EXTERNAL_RAM)
 #  if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)
 #    error "The STM3240G-EVAL cannot support both CAN and FSMC SRAM"
 #  endif
diff --git a/configs/stm3240g-eval/kernel/stm32_userspace.c b/configs/stm3240g-eval/kernel/stm32_userspace.c
index faca2fb74e0..fe856980847 100644
--- a/configs/stm3240g-eval/kernel/stm32_userspace.c
+++ b/configs/stm3240g-eval/kernel/stm32_userspace.c
@@ -114,9 +114,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/stm3240g-eval/knxwm/defconfig b/configs/stm3240g-eval/knxwm/defconfig
index b8114e21022..605d49daf57 100644
--- a/configs/stm3240g-eval/knxwm/defconfig
+++ b/configs/stm3240g-eval/knxwm/defconfig
@@ -23,7 +23,6 @@ CONFIG_ARM_MPU=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILD_PROTECTED=y
 CONFIG_CXX_NEWLONG=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/stm3240g-eval/nettest/defconfig b/configs/stm3240g-eval/nettest/defconfig
index d3790a2e32b..2f57f463656 100644
--- a/configs/stm3240g-eval/nettest/defconfig
+++ b/configs/stm3240g-eval/nettest/defconfig
@@ -18,7 +18,6 @@ CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_ETH0_PHY_DP83848C=y
 CONFIG_EXAMPLES_NETTEST=y
diff --git a/configs/stm3240g-eval/nsh/defconfig b/configs/stm3240g-eval/nsh/defconfig
index e29cde202d3..5b31e17a783 100644
--- a/configs/stm3240g-eval/nsh/defconfig
+++ b/configs/stm3240g-eval/nsh/defconfig
@@ -36,6 +36,7 @@ CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSCLIENT_ENTRIES=4
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -43,7 +44,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=40
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -55,7 +55,6 @@ CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=10
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/stm3240g-eval/nsh2/defconfig b/configs/stm3240g-eval/nsh2/defconfig
index f0e6c295e31..72310ff3d46 100644
--- a/configs/stm3240g-eval/nsh2/defconfig
+++ b/configs/stm3240g-eval/nsh2/defconfig
@@ -43,6 +43,7 @@ CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSCLIENT_ENTRIES=4
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -50,7 +51,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=40
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -63,7 +63,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=10
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig
index a5b9ff99847..b83f12239fd 100644
--- a/configs/stm3240g-eval/nxterm/defconfig
+++ b/configs/stm3240g-eval/nxterm/defconfig
@@ -45,6 +45,7 @@ CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSCLIENT_ENTRIES=4
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -64,7 +65,6 @@ CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LIBRARY=y
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=10
 CONFIG_NX=y
@@ -92,7 +92,7 @@ CONFIG_SDCLONE_DISABLE=y
 CONFIG_STM32_DFU=y
 CONFIG_STM32_ETHMAC=y
 CONFIG_STM32_FSMC=y
-CONFIG_STM32_FSMC_SRAM=y
+CONFIG_STM32_EXTERNAL_RAM=y
 CONFIG_STM32_I2C1=y
 CONFIG_STM32_JTAG_FULL_ENABLE=y
 CONFIG_STM32_MII=y
diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig
index 5eb1272204c..7893c0bdf03 100644
--- a/configs/stm3240g-eval/nxwm/defconfig
+++ b/configs/stm3240g-eval/nxwm/defconfig
@@ -43,13 +43,13 @@ CONFIG_MQ_MAXMSGSIZE=64
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=40
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -61,7 +61,6 @@ CONFIG_NFILE_STREAMS=12
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LIBRARY=y
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=10
 CONFIG_NX=y
diff --git a/configs/stm3240g-eval/scripts/ld.script b/configs/stm3240g-eval/scripts/ld.script
index 5a2dceafcdc..56a7aaf1489 100644
--- a/configs/stm3240g-eval/scripts/ld.script
+++ b/configs/stm3240g-eval/scripts/ld.script
@@ -57,67 +57,71 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/stm3240g-eval/scripts/memory.ld b/configs/stm3240g-eval/scripts/memory.ld
index a1b347ccb4f..585bce95595 100644
--- a/configs/stm3240g-eval/scripts/memory.ld
+++ b/configs/stm3240g-eval/scripts/memory.ld
@@ -54,7 +54,7 @@
  * Alignment of the user space FLASH partition is also a critical factor:
  * The user space FLASH partition will be spanned with a single region of
  * size 2**n bytes.  The alignment of the user-space region must be the same.
- * As a consequence, as the user-space increases in size, the alignmment
+ * As a consequence, as the user-space increases in size, the alignment
  * requirement also increases.
  *
  * This alignment requirement means that the largest user space FLASH region
diff --git a/configs/stm3240g-eval/src/stm3240g-eval.h b/configs/stm3240g-eval/src/stm3240g-eval.h
index 4a6bee4ef0e..e9da66245c4 100644
--- a/configs/stm3240g-eval/src/stm3240g-eval.h
+++ b/configs/stm3240g-eval/src/stm3240g-eval.h
@@ -370,30 +370,6 @@ void stm32_extmemaddr(int naddrs);
 void stm32_extmemdata(int ndata);
 #endif
 
-/****************************************************************************************************
- * Name: stm32_enablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ****************************************************************************************************/
-
-#ifdef CONFIG_STM32_FSMC
-void stm32_enablefsmc(void);
-#endif
-
-/****************************************************************************************************
- * Name: stm32_disablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ****************************************************************************************************/
-
-#ifdef CONFIG_STM32_FSMC
-void stm32_disablefsmc(void);
-#endif
-
 /****************************************************************************************************
  * Name: stm32_selectsram
  *
diff --git a/configs/stm3240g-eval/src/stm32_deselectlcd.c b/configs/stm3240g-eval/src/stm32_deselectlcd.c
index 76a6108ae17..88ee82a337e 100644
--- a/configs/stm3240g-eval/src/stm32_deselectlcd.c
+++ b/configs/stm3240g-eval/src/stm32_deselectlcd.c
@@ -43,7 +43,7 @@
 #include 
 
 #include "up_arch.h"
-#include "stm32_fsmc.h"
+#include "stm32.h"
 #include "stm3240g-eval.h"
 
 #ifdef CONFIG_STM32_FSMC
@@ -88,7 +88,7 @@ void stm32_deselectlcd(void)
 
   /* Disable AHB clocking to the FSMC */
 
-  stm32_disablefsmc();
+  stm32_fsmc_disable();
 }
 
 #endif /* CONFIG_STM32_FSMC */
diff --git a/configs/stm3240g-eval/src/stm32_deselectsram.c b/configs/stm3240g-eval/src/stm32_deselectsram.c
index bf38b924c15..cc48f7cf9d5 100644
--- a/configs/stm3240g-eval/src/stm32_deselectsram.c
+++ b/configs/stm3240g-eval/src/stm32_deselectsram.c
@@ -42,7 +42,7 @@
 #include 
 
 #include "up_arch.h"
-#include "stm32_fsmc.h"
+#include "stm32.h"
 #include "stm3240g-eval.h"
 
 #ifdef CONFIG_STM32_FSMC
@@ -87,10 +87,7 @@ void stm32_deselectsram(void)
 
   /* Disable AHB clocking to the FSMC */
 
-  stm32_disablefsmc();
+  stm32_fsmc_disable();
 }
 
 #endif /* CONFIG_STM32_FSMC */
-
-
-
diff --git a/configs/stm3240g-eval/src/stm32_extmem.c b/configs/stm3240g-eval/src/stm32_extmem.c
index 42b7a1e156a..7fe70097b7f 100644
--- a/configs/stm3240g-eval/src/stm32_extmem.c
+++ b/configs/stm3240g-eval/src/stm32_extmem.c
@@ -48,7 +48,6 @@
 #include "chip.h"
 #include "up_arch.h"
 
-#include "stm32_fsmc.h"
 #include "stm32_gpio.h"
 #include "stm32.h"
 #include "stm3240g-eval.h"
@@ -147,41 +146,3 @@ void stm32_extmemdata(int ndata)
 {
   stm32_extmemgpios(g_dataconfig, ndata);
 }
-
-/************************************************************************************
- * Name: stm32_enablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-void stm32_enablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Enable AHB clocking to the FSMC */
-
-  regval  = getreg32( STM32_RCC_AHB3ENR);
-  regval |= RCC_AHB3ENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHB3ENR);
-}
-
-/************************************************************************************
- * Name: stm32_disablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-void stm32_disablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Disable AHB clocking to the FSMC */
-
-  regval  = getreg32(STM32_RCC_AHB3ENR);
-  regval &= ~RCC_AHB3ENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHB3ENR);
-}
diff --git a/configs/stm3240g-eval/src/stm32_ostest.c b/configs/stm3240g-eval/src/stm32_ostest.c
index 267e1ab8bc0..6d96de08f33 100644
--- a/configs/stm3240g-eval/src/stm32_ostest.c
+++ b/configs/stm3240g-eval/src/stm32_ostest.c
@@ -58,7 +58,7 @@
 
 #undef HAVE_FPU
 #if defined(CONFIG_ARCH_FPU) && defined(CONFIG_TESTING_OSTEST_FPUSIZE) && \
-    defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_DISABLE_SIGNALS)
+    defined(CONFIG_SCHED_WAITPID)
 #    define HAVE_FPU 1
 #endif
 
diff --git a/configs/stm3240g-eval/src/stm32_selectlcd.c b/configs/stm3240g-eval/src/stm32_selectlcd.c
index d418a5fadb4..fac8aee33a3 100644
--- a/configs/stm3240g-eval/src/stm32_selectlcd.c
+++ b/configs/stm3240g-eval/src/stm32_selectlcd.c
@@ -135,7 +135,7 @@ void stm32_selectlcd(void)
 
   /* Enable AHB clocking to the FSMC */
 
-  stm32_enablefsmc();
+  stm32_fsmc_enable();
 
   /* Color LCD configuration (LCD configured as follow):
    *
diff --git a/configs/stm3240g-eval/src/stm32_selectsram.c b/configs/stm3240g-eval/src/stm32_selectsram.c
index fcbef4d9c81..1b2f754b39d 100644
--- a/configs/stm3240g-eval/src/stm32_selectsram.c
+++ b/configs/stm3240g-eval/src/stm32_selectsram.c
@@ -149,7 +149,7 @@ void stm32_selectsram(void)
 
   /* Enable AHB clocking to the FSMC */
 
-  stm32_enablefsmc();
+  stm32_fsmc_enable();
 
   /* Bank1 NOR/SRAM control register configuration
    *
diff --git a/configs/stm3240g-eval/telnetd/defconfig b/configs/stm3240g-eval/telnetd/defconfig
index 223ca0e794c..9ca06d139d1 100644
--- a/configs/stm3240g-eval/telnetd/defconfig
+++ b/configs/stm3240g-eval/telnetd/defconfig
@@ -18,7 +18,6 @@ CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_ETH0_PHY_DP83848C=y
 CONFIG_EXAMPLES_TELNETD=y
diff --git a/configs/stm3240g-eval/webserver/defconfig b/configs/stm3240g-eval/webserver/defconfig
index cc3df7b4238..1849d9c9db5 100644
--- a/configs/stm3240g-eval/webserver/defconfig
+++ b/configs/stm3240g-eval/webserver/defconfig
@@ -33,6 +33,7 @@ CONFIG_MAX_WDOGPARMS=2
 CONFIG_MM_REGIONS=2
 CONFIG_MTD=y
 CONFIG_NET=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_WEBSERVER=y
 CONFIG_NET_ICMP=y
@@ -50,7 +51,6 @@ CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LIBRARY=y
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=10
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/stm32_tiny/scripts/ld.script b/configs/stm32_tiny/scripts/ld.script
index a97be1a2fe6..4cfbff2a3e7 100644
--- a/configs/stm32_tiny/scripts/ld.script
+++ b/configs/stm32_tiny/scripts/ld.script
@@ -52,69 +52,73 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */
+        /* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/stm32_tiny/usbnsh/defconfig b/configs/stm32_tiny/usbnsh/defconfig
index 5cdbb1f1f08..837ac3fc3f0 100644
--- a/configs/stm32_tiny/usbnsh/defconfig
+++ b/configs/stm32_tiny/usbnsh/defconfig
@@ -33,7 +33,6 @@ CONFIG_CDCACM_CONSOLE=y
 CONFIG_CDCACM_RXBUFSIZE=256
 CONFIG_CDCACM_TXBUFSIZE=256
 CONFIG_DEFAULT_SMALL=y
-CONFIG_DISABLE_POLL=y
 CONFIG_LIB_BOARDCTL=y
 CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
diff --git a/configs/stm32butterfly2/nshnet/defconfig b/configs/stm32butterfly2/nshnet/defconfig
index 654dc20ee29..9176e71ac84 100644
--- a/configs/stm32butterfly2/nshnet/defconfig
+++ b/configs/stm32butterfly2/nshnet/defconfig
@@ -43,6 +43,9 @@ CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_MMCSD=y
 CONFIG_NET=y
+CONFIG_NETINIT_DRIPADDR=0x0a010101
+CONFIG_NETINIT_IPADDR=0x0a010163
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NET_ARP_IPIN=y
 CONFIG_NET_ETH_PKTSIZE=1500
 CONFIG_NET_ICMP=y
@@ -55,11 +58,8 @@ CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
-CONFIG_NSH_DRIPADDR=0x0a010101
-CONFIG_NSH_IPADDR=0x0a010163
 CONFIG_NSH_MOTD=y
 CONFIG_NSH_MOTD_STRING="stm32butterfly2 welcoms you"
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSH_STRERROR=y
 CONFIG_PL2303=y
diff --git a/configs/stm32butterfly2/src/stm32_adc.c b/configs/stm32butterfly2/src/stm32_adc.c
index eaac1722e71..6526338c22e 100644
--- a/configs/stm32butterfly2/src/stm32_adc.c
+++ b/configs/stm32butterfly2/src/stm32_adc.c
@@ -36,10 +36,10 @@
  * Included Files
  ****************************************************************************/
 
-#include 
 #include 
 #include 
 
+#include "chip.h"
 #include "stm32_adc.h"
 
 /*****************************************************************************
diff --git a/configs/stm32f051-discovery/include/board.h b/configs/stm32f051-discovery/include/board.h
index 7db6f4b8a0a..543c1181808 100644
--- a/configs/stm32f051-discovery/include/board.h
+++ b/configs/stm32f051-discovery/include/board.h
@@ -113,7 +113,7 @@
 
 #define STM32_CFGR_PLLSRC        RCC_CFGR_PLLSRC_HSId2       /* Source is HSI/2 */
 #define STM32_PLLSRC_FREQUENCY   (STM32_HSI_FREQUENCY/2)     /* 8MHz / 2 = 4MHz */
-#ifdef CONFIG_STM32F0L0_USB
+#ifdef CONFIG_STM32F0L0G0_USB
 #  undef  STM32_CFGR2_PREDIV                                 /* Not used with source HSI/2 */
 #  define STM32_CFGR_PLLMUL      RCC_CFGR_PLLMUL_CLKx12      /* PLLMUL = 12 */
 #  define STM32_PLL_FREQUENCY    (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
@@ -129,7 +129,7 @@
 
 #define STM32_SYSCLK_SW          RCC_CFGR_SW_PLL     /* Use the PLL as the SYSCLK */
 #define STM32_SYSCLK_SWS         RCC_CFGR_SWS_PLL
-#ifdef CONFIG_STM32F0L0_USB
+#ifdef CONFIG_STM32F0L0G0_USB
 #  define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
 #else
 #  define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
diff --git a/configs/stm32f051-discovery/nsh/defconfig b/configs/stm32f051-discovery/nsh/defconfig
index 5608d8d7d2f..4ee63b9a0be 100644
--- a/configs/stm32f051-discovery/nsh/defconfig
+++ b/configs/stm32f051-discovery/nsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_BOARD_LOOPSPERMSEC=2796
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_MAX_TASKS=8
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_MM_SMALL=y
@@ -51,8 +50,8 @@ CONFIG_START_DAY=19
 CONFIG_START_MONTH=5
 CONFIG_START_YEAR=2013
 CONFIG_STDIO_DISABLE_BUFFERING=y
-CONFIG_STM32F0L0_PWR=y
-CONFIG_STM32F0L0_USART1=y
+CONFIG_STM32F0L0G0_PWR=y
+CONFIG_STM32F0L0G0_USART1=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_TASK_NAME_SIZE=0
 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
diff --git a/configs/stm32f051-discovery/src/Makefile b/configs/stm32f051-discovery/src/Makefile
index 564a6e714fc..ffc5bc3aef7 100644
--- a/configs/stm32f051-discovery/src/Makefile
+++ b/configs/stm32f051-discovery/src/Makefile
@@ -49,7 +49,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
 CSRCS += stm32_buttons.c
 endif
 
-ifeq ($(CONFIG_STM32F0L0_SPI),y)
+ifeq ($(CONFIG_STM32F0L0G0_SPI),y)
 CSRCS += stm32_spi.c
 endif
 
diff --git a/configs/stm32f051-discovery/src/stm32f051-discovery.h b/configs/stm32f051-discovery/src/stm32f051-discovery.h
index 22691e03fee..7dc94065dcb 100644
--- a/configs/stm32f051-discovery/src/stm32f051-discovery.h
+++ b/configs/stm32f051-discovery/src/stm32f051-discovery.h
@@ -55,14 +55,14 @@
 /* How many SPI modules does this chip support? */
 
 #if STM32_NSPI < 1
-#  undef CONFIG_STM32F0L0_SPI1
-#  undef CONFIG_STM32F0L0_SPI2
-#  undef CONFIG_STM32F0L0_SPI3
+#  undef CONFIG_STM32F0L0G0_SPI1
+#  undef CONFIG_STM32F0L0G0_SPI2
+#  undef CONFIG_STM32F0L0G0_SPI3
 #elif STM32_NSPI < 2
-#  undef CONFIG_STM32F0L0_SPI2
-#  undef CONFIG_STM32F0L0_SPI3
+#  undef CONFIG_STM32F0L0G0_SPI2
+#  undef CONFIG_STM32F0L0G0_SPI3
 #elif STM32_NSPI < 3
-#  undef CONFIG_STM32F0L0_SPI3
+#  undef CONFIG_STM32F0L0G0_SPI3
 #endif
 
 /* STM32F0Discovery GPIOs ***************************************************************************/
diff --git a/configs/stm32f072-discovery/include/board.h b/configs/stm32f072-discovery/include/board.h
index ad5032af40d..2ebd0d251fa 100644
--- a/configs/stm32f072-discovery/include/board.h
+++ b/configs/stm32f072-discovery/include/board.h
@@ -113,7 +113,7 @@
 
 #define STM32_CFGR_PLLSRC        RCC_CFGR_PLLSRC_HSId2         /* Source is HSI/2 */
 #define STM32_PLLSRC_FREQUENCY   (STM32_HSI_FREQUENCY/2)     /* 8MHz / 2 = 4MHz */
-#ifdef CONFIG_STM32F0L0_USB
+#ifdef CONFIG_STM32F0L0G0_USB
 #  undef  STM32_CFGR2_PREDIV                                   /* Not used with source HSI/2 */
 #  define STM32_CFGR_PLLMUL      RCC_CFGR_PLLMUL_CLKx12        /* PLLMUL = 12 */
 #  define STM32_PLL_FREQUENCY    (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
@@ -129,7 +129,7 @@
 
 #define STM32_SYSCLK_SW          RCC_CFGR_SW_PLL       /* Use the PLL as the SYSCLK */
 #define STM32_SYSCLK_SWS         RCC_CFGR_SWS_PLL
-#ifdef CONFIG_STM32F0L0_USB
+#ifdef CONFIG_STM32F0L0G0_USB
 #  define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
 #else
 #  define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
diff --git a/configs/stm32f072-discovery/nsh/defconfig b/configs/stm32f072-discovery/nsh/defconfig
index 37a0ebf5765..3ea96369405 100644
--- a/configs/stm32f072-discovery/nsh/defconfig
+++ b/configs/stm32f072-discovery/nsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_BOARD_LOOPSPERMSEC=2796
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_MAX_TASKS=8
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_MM_SMALL=y
@@ -51,8 +50,8 @@ CONFIG_START_DAY=19
 CONFIG_START_MONTH=5
 CONFIG_START_YEAR=2013
 CONFIG_STDIO_DISABLE_BUFFERING=y
-CONFIG_STM32F0L0_PWR=y
-CONFIG_STM32F0L0_USART1=y
+CONFIG_STM32F0L0G0_PWR=y
+CONFIG_STM32F0L0G0_USART1=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_TASK_NAME_SIZE=0
 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536
diff --git a/configs/stm32f072-discovery/src/Makefile b/configs/stm32f072-discovery/src/Makefile
index e6bb4efaf24..550288851ab 100644
--- a/configs/stm32f072-discovery/src/Makefile
+++ b/configs/stm32f072-discovery/src/Makefile
@@ -49,7 +49,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
 CSRCS += stm32_buttons.c
 endif
 
-ifeq ($(CONFIG_STM32F0L0_SPI),y)
+ifeq ($(CONFIG_STM32F0L0G0_SPI),y)
 CSRCS += stm32_spi.c
 endif
 
diff --git a/configs/stm32f072-discovery/src/stm32f072-discovery.h b/configs/stm32f072-discovery/src/stm32f072-discovery.h
index 3d834708a2e..4c527a1b676 100644
--- a/configs/stm32f072-discovery/src/stm32f072-discovery.h
+++ b/configs/stm32f072-discovery/src/stm32f072-discovery.h
@@ -55,14 +55,14 @@
 /* How many SPI modules does this chip support? */
 
 #if STM32_NSPI < 1
-#  undef CONFIG_STM32F0L0_SPI1
-#  undef CONFIG_STM32F0L0_SPI2
-#  undef CONFIG_STM32F0L0_SPI3
+#  undef CONFIG_STM32F0L0G0_SPI1
+#  undef CONFIG_STM32F0L0G0_SPI2
+#  undef CONFIG_STM32F0L0G0_SPI3
 #elif STM32_NSPI < 2
-#  undef CONFIG_STM32F0L0_SPI2
-#  undef CONFIG_STM32F0L0_SPI3
+#  undef CONFIG_STM32F0L0G0_SPI2
+#  undef CONFIG_STM32F0L0G0_SPI3
 #elif STM32_NSPI < 3
-#  undef CONFIG_STM32F0L0_SPI3
+#  undef CONFIG_STM32F0L0G0_SPI3
 #endif
 
 /* STM32F0Discovery GPIOs ***************************************************************************/
diff --git a/configs/stm32f103-minimum/hello/defconfig b/configs/stm32f103-minimum/hello/defconfig
index d5b3c383e78..6bd51df709d 100644
--- a/configs/stm32f103-minimum/hello/defconfig
+++ b/configs/stm32f103-minimum/hello/defconfig
@@ -25,9 +25,7 @@ CONFIG_BOARD_LOOPSPERMSEC=5483
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_FDCLONE_STDIO=y
diff --git a/configs/stm32f103-minimum/mcp2515/defconfig b/configs/stm32f103-minimum/mcp2515/defconfig
index e2bde444f33..e27510b0aa1 100644
--- a/configs/stm32f103-minimum/mcp2515/defconfig
+++ b/configs/stm32f103-minimum/mcp2515/defconfig
@@ -30,7 +30,6 @@ CONFIG_CANUTILS_CANLIB=y
 CONFIG_CAN_MCP2515=y
 CONFIG_CAN_TXREADY=y
 CONFIG_DEFAULT_SMALL=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_CAN=y
 CONFIG_EXAMPLES_CAN_READ=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/stm32f103-minimum/scripts/ld.script b/configs/stm32f103-minimum/scripts/ld.script
index ec15a978f86..04ef2c8792e 100644
--- a/configs/stm32f103-minimum/scripts/ld.script
+++ b/configs/stm32f103-minimum/scripts/ld.script
@@ -57,69 +57,73 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */
+        /* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/stm32f103-minimum/scripts/ld.script.dfu b/configs/stm32f103-minimum/scripts/ld.script.dfu
index 9c9b0e6f4e8..fab175e98eb 100644
--- a/configs/stm32f103-minimum/scripts/ld.script.dfu
+++ b/configs/stm32f103-minimum/scripts/ld.script.dfu
@@ -51,69 +51,73 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */
+        /* The STM32F103C8T6 has 20Kb of SRAM beginning at the following address */
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/stm32f103-minimum/src/stm32_bringup.c b/configs/stm32f103-minimum/src/stm32_bringup.c
index 8b1d25bc241..da884476ee1 100644
--- a/configs/stm32f103-minimum/src/stm32_bringup.c
+++ b/configs/stm32f103-minimum/src/stm32_bringup.c
@@ -206,6 +206,17 @@ int stm32_bringup(void)
     }
 #endif
 
+#ifdef CONFIG_FS_PROCFS
+  /* Mount the procfs file system */
+
+  ret = mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL);
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n",
+             STM32_PROCFS_MOUNTPOINT, ret);
+    }
+#endif
+
 #ifdef HAVE_AT24
   /* Initialize the AT24 driver */
 
diff --git a/configs/stm32f103-minimum/src/stm32_mcp2515.c b/configs/stm32f103-minimum/src/stm32_mcp2515.c
index d6e4b554777..6fc3977238e 100644
--- a/configs/stm32f103-minimum/src/stm32_mcp2515.c
+++ b/configs/stm32f103-minimum/src/stm32_mcp2515.c
@@ -107,9 +107,15 @@ static struct stm32_mcp2515config_s g_mcp2515config =
 {
   .config =
   {
+    .spi        = NULL,
+    .baud       = 0,     /* REVISIT.  Proably broken by commit eb7373cedfa */
+    .btp        = 0,     /* REVISIT.  Proably broken by commit eb7373cedfa */
     .devid      = 0,
+    .mode       = 0,     /* REVISIT.  Proably broken by commit eb7373cedfa */
     .nfilters   = 6,
-    .ntxbuffers = 3,
+#ifdef MCP2515_LOOPBACK
+    .loopback   = false;
+#endif
     .attach     = mcp2515_attach,
   },
 };
@@ -140,7 +146,7 @@ int mcp2515_interrupt(int irq, FAR void *context, FAR void *arg)
 }
 
 static int mcp2515_attach(FAR struct mcp2515_config_s *state,
-                           mcp2515_handler_t handler, FAR void *arg)
+                          mcp2515_handler_t handler, FAR void *arg)
 {
   FAR struct stm32_mcp2515config_s *priv =
              (FAR struct stm32_mcp2515config_s *)state;
diff --git a/configs/stm32f103-minimum/src/stm32_ssd1306.c b/configs/stm32f103-minimum/src/stm32_ssd1306.c
index da1048cdfac..24eb5edc1cc 100644
--- a/configs/stm32f103-minimum/src/stm32_ssd1306.c
+++ b/configs/stm32f103-minimum/src/stm32_ssd1306.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * config/stm32f103-minimum/src/sam_ug2832hsweg04.c
+ * config/stm32f103-minimum/src/stm32_ssd1306.c
  *
  *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -105,7 +105,7 @@ FAR struct lcd_dev_s *board_lcd_getdev(int devno)
   g_lcddev = ssd1306_initialize(g_i2c, NULL, devno);
   if (!g_lcddev)
     {
-      lcderr("ERROR: Failed to bind SPI port 1 to OLED %d: %d\n", devno);
+      lcderr("ERROR: Failed to bind I2C port 1 to OLED %d: %d\n", devno);
     }
   else
     {
diff --git a/configs/stm32f103-minimum/src/stm32_veml6070.c b/configs/stm32f103-minimum/src/stm32_veml6070.c
index 8a84517f2f7..52eca585784 100644
--- a/configs/stm32f103-minimum/src/stm32_veml6070.c
+++ b/configs/stm32f103-minimum/src/stm32_veml6070.c
@@ -96,7 +96,7 @@ int stm32_veml6070initialize(FAR const char *devpath)
   ret = veml6070_register(devpath, i2c, VEML6070_I2C_DATA_LSB_CMD_ADDR);
   if (ret < 0)
     {
-      snerr("ERROR: Error registering BM180\n");
+      snerr("ERROR: Error registering VEML6070\n");
     }
 
   return ret;
diff --git a/configs/stm32f103-minimum/src/stm32f103_minimum.h b/configs/stm32f103-minimum/src/stm32f103_minimum.h
index 813e433d668..a13ad9e4f88 100644
--- a/configs/stm32f103-minimum/src/stm32f103_minimum.h
+++ b/configs/stm32f103-minimum/src/stm32f103_minimum.h
@@ -70,6 +70,16 @@
 #  undef HAVE_AT24
 #endif
 
+/* procfs File System */
+
+#ifdef CONFIG_FS_PROCFS
+#  ifdef CONFIG_NSH_PROC_MOUNTPOINT
+#    define STM32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT
+#  else
+#    define STM32_PROCFS_MOUNTPOINT "/proc"
+#  endif
+#endif
+
 /* If we are going to mount the AT24, then they user must also have told
  * us what to do with it by setting one of these.
  */
diff --git a/configs/stm32f103-minimum/usbnsh/defconfig b/configs/stm32f103-minimum/usbnsh/defconfig
index 01cd80390ca..1d9708bd893 100644
--- a/configs/stm32f103-minimum/usbnsh/defconfig
+++ b/configs/stm32f103-minimum/usbnsh/defconfig
@@ -33,7 +33,6 @@ CONFIG_CDCACM_CONSOLE=y
 CONFIG_CDCACM_RXBUFSIZE=256
 CONFIG_CDCACM_TXBUFSIZE=256
 CONFIG_DEFAULT_SMALL=y
-CONFIG_DISABLE_POLL=y
 CONFIG_LIB_BOARDCTL=y
 CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
diff --git a/configs/stm32f334-disco/buckboost/defconfig b/configs/stm32f334-disco/buckboost/defconfig
index b4977792960..0d95315cc12 100644
--- a/configs/stm32f334-disco/buckboost/defconfig
+++ b/configs/stm32f334-disco/buckboost/defconfig
@@ -24,7 +24,6 @@ CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_DRIVERS_SMPS=y
diff --git a/configs/stm32f334-disco/nsh/defconfig b/configs/stm32f334-disco/nsh/defconfig
index b7b97be42a2..3cbe9cfaecd 100644
--- a/configs/stm32f334-disco/nsh/defconfig
+++ b/configs/stm32f334-disco/nsh/defconfig
@@ -25,10 +25,8 @@ CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_FDCLONE_STDIO=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/stm32f334-disco/powerled/defconfig b/configs/stm32f334-disco/powerled/defconfig
index a3137090381..77ec271c749 100644
--- a/configs/stm32f334-disco/powerled/defconfig
+++ b/configs/stm32f334-disco/powerled/defconfig
@@ -27,7 +27,6 @@ CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_DRIVERS_POWERLED=y
 CONFIG_EXAMPLES_POWERLED=y
diff --git a/configs/stm32f334-disco/scripts/ld.script b/configs/stm32f334-disco/scripts/ld.script
index 72b8731eaa1..fa76abafd1b 100644
--- a/configs/stm32f334-disco/scripts/ld.script
+++ b/configs/stm32f334-disco/scripts/ld.script
@@ -52,73 +52,77 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The RAM vector table (if present) should lie at the beginning of SRAM */
+        /* The RAM vector table (if present) should lie at the beginning of SRAM */
 
-	.ram_vectors : {
-		*(.ram_vectors)
-	} > sram
+        .ram_vectors : {
+                *(.ram_vectors)
+        } > sram
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/stm32f3discovery/nsh/defconfig b/configs/stm32f3discovery/nsh/defconfig
index 925ff9d15e9..afa6534be04 100644
--- a/configs/stm32f3discovery/nsh/defconfig
+++ b/configs/stm32f3discovery/nsh/defconfig
@@ -21,7 +21,6 @@ CONFIG_BUILTIN=y
 CONFIG_CDCACM=y
 CONFIG_CDCACM_RXBUFSIZE=256
 CONFIG_CDCACM_TXBUFSIZE=256
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/stm32f3discovery/scripts/ld.script b/configs/stm32f3discovery/scripts/ld.script
index b4e38e8845e..181c9b02513 100644
--- a/configs/stm32f3discovery/scripts/ld.script
+++ b/configs/stm32f3discovery/scripts/ld.script
@@ -52,67 +52,71 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/stm32f3discovery/usbnsh/defconfig b/configs/stm32f3discovery/usbnsh/defconfig
index f84f1139fdb..948e817163a 100644
--- a/configs/stm32f3discovery/usbnsh/defconfig
+++ b/configs/stm32f3discovery/usbnsh/defconfig
@@ -24,7 +24,6 @@ CONFIG_CDCACM=y
 CONFIG_CDCACM_CONSOLE=y
 CONFIG_CDCACM_RXBUFSIZE=256
 CONFIG_CDCACM_TXBUFSIZE=256
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/stm32f411e-disco/nsh/defconfig b/configs/stm32f411e-disco/nsh/defconfig
index dee8b201fb2..1fcd18edcbc 100644
--- a/configs/stm32f411e-disco/nsh/defconfig
+++ b/configs/stm32f411e-disco/nsh/defconfig
@@ -23,7 +23,6 @@ CONFIG_ARCH_INTERRUPTSTACK=2048
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=8499
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/stm32f429i-disco/README.txt b/configs/stm32f429i-disco/README.txt
index 8131434c786..2c4f9108de5 100644
--- a/configs/stm32f429i-disco/README.txt
+++ b/configs/stm32f429i-disco/README.txt
@@ -41,7 +41,7 @@ Contents
   - Ser
   - Timer Inputs/Outputs
   - FPU
-  - FSMC SRAM
+  - FMC SDRAM
   - STM32F429I-DISCO-specific Configuration Options
   - Configurations
 
@@ -323,7 +323,7 @@ FMC SDRAM
 On-board SDRAM
 --------------
 The STM32F429I-DISCO has 8 MBytes on-board SDRAM connected to the MCU's
-SDRAM Bank 2 connections (Bank 6 of the FSMC).  This means the 8 MBytes
+SDRAM Bank 2 connections (Bank 6 of the FMC).  This means the 8 MiB
 (when enabled) is mapped to address 0xD0000000-0xD07FFFFF.  The port for
 the STM32F429I-DISCO board includes support for using the onboard 8M SDRAM.
 
@@ -336,20 +336,20 @@ to exclude CCM SRAM from the heap:
 
   CONFIG_STM32_CCMEXCLUDE    : Exclude CCM SRAM from the HEAP
 
-In addition to internal SRAM, SRAM may also be available through the FSMC.
-In order to use FSMC SRAM, the following additional things need to be
+In addition to internal SRAM, SRAM may also be available through the FMC.
+In order to use FMC SDRAM, the following additional things need to be
 present in the NuttX configuration file:
 
-  CONFIG_STM32_FSMC=y        : Enables the FSMC and the 8MByte SDRAM
-  CONFIG_STM32_FSMC_SRAM=y   : Indicates that SRAM is available via the
-                               FSMC (as opposed to an LCD or FLASH).
-  CONFIG_HEAP2_BASE          : The base address of the SRAM in the FSMC
-                               address space.  This should be 0xD0000000.
-  CONFIG_HEAP2_SIZE          : The size of the SRAM in the FSMC
-                               address space.  This should be 8388608.
-  CONFIG_MM_REGIONS          : Must be set to a large enough value to
-                               include the FSMC SDRAM (1, 2 or 3 depending
-                               if the CCM RAM and/or FSCM SDRAM are enabled).
+  CONFIG_STM32_FMC=y          : Enables the FMC and the 8MiB SDRAM
+  CONFIG_STM32_EXTERNAL_RAM=y : Indicates that RAM is available via the
+                                FMC (as opposed to an LCD or FLASH).
+  CONFIG_HEAP2_BASE           : The base address of the RAM in the FMC
+                                address space.  This should be 0xD0000000.
+  CONFIG_HEAP2_SIZE           : The size of the RAM in the FMC
+                                address space.  This should be 8388608.
+  CONFIG_MM_REGIONS           : Must be set to a large enough value to
+                                include the FMC SDRAM (1, 2 or 3 depending
+                                if the CCM RAM and/or FMC SDRAM are enabled).
 
 SRAM Configurations
 --------------------
@@ -357,19 +357,19 @@ There are 4 possible SRAM configurations:
 
   Configuration 1. System SRAM (only)
                    CONFIG_MM_REGIONS == 1
-                   CONFIG_STM32_FSMC_SRAM NOT defined
+                   CONFIG_STM32_EXTERNAL_RAM NOT defined
                    CONFIG_STM32_CCMEXCLUDE defined
   Configuration 2. System SRAM and CCM SRAM
                    CONFIG_MM_REGIONS == 2
-                   CONFIG_STM32_FSMC_SRAM NOT defined
+                   CONFIG_STM32_EXTERNAL_RAM NOT defined
                    CONFIG_STM32_CCMEXCLUDE NOT defined
-  Configuration 3. System SRAM and FSMC SRAM
+  Configuration 3. System SRAM and FMC SDRAM
                    CONFIG_MM_REGIONS == 2
-                   CONFIG_STM32_FSMC_SRAM defined
+                   CONFIG_STM32_EXTERNAL_RAM defined
                    CONFIG_STM32_CCMEXCLUDE defined
-  Configuration 4. System SRAM, CCM SRAM, and FSMC SRAM
+  Configuration 4. System SRAM, CCM SRAM, and FMC SDRAM
                    CONFIG_MM_REGIONS == 3
-                   CONFIG_STM32_FSMC_SRAM defined
+                   CONFIG_STM32_EXTERNAL_RAM defined
                    CONFIG_STM32_CCMEXCLUDE NOT defined
 
 STM32F429I-DISCO-specific Configuration Options
@@ -427,16 +427,16 @@ STM32F429I-DISCO-specific Configuration Options
 
     CONFIG_STM32_CCMEXCLUDE - Exclude CCM SRAM from the HEAP
 
-    In addition to internal SRAM, SRAM may also be available through the FSMC.
-    In order to use FSMC SRAM, the following additional things need to be
+    In addition to internal SRAM, SDRAM may also be available through the FMC.
+    In order to use FMC SDRAM, the following additional things need to be
     present in the NuttX configuration file:
 
-    CONFIG_STM32_FSMC_SRAM - Indicates that SRAM is available via the
-      FSMC (as opposed to an LCD or FLASH).
+    CONFIG_STM32_EXTERNAL_RAM - Indicates that SDRAM is available via the
+      FMC (as opposed to an LCD or FLASH).
 
-    CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space (hex)
+    CONFIG_HEAP2_BASE - The base address of the SDRAM in the FMC address space (hex)
 
-    CONFIG_HEAP2_SIZE - The size of the SRAM in the FSMC address space (decimal)
+    CONFIG_HEAP2_SIZE - The size of the SDRAM in the FMC address space (decimal)
 
     CONFIG_ARCH_FPU - The STM32F429I-DISCO supports a floating point unit (FPU)
 
@@ -476,7 +476,7 @@ STM32F429I-DISCO-specific Configuration Options
 
     AHB3
     ----
-    CONFIG_STM32_FSMC
+    CONFIG_STM32_FMC
 
     APB1
     ----
diff --git a/configs/stm32f429i-disco/adc/defconfig b/configs/stm32f429i-disco/adc/defconfig
index a2032bff417..39452d7c623 100644
--- a/configs/stm32f429i-disco/adc/defconfig
+++ b/configs/stm32f429i-disco/adc/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_ADC=y
 CONFIG_EXAMPLES_ADC_GROUPSIZE=3
 CONFIG_FS_PROCFS=y
@@ -57,8 +56,8 @@ CONFIG_STM32_ADC3=y
 CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
 CONFIG_STM32_DMA1=y
 CONFIG_STM32_DMA2=y
-CONFIG_STM32_FSMC=y
-CONFIG_STM32_FSMC_SRAM=y
+CONFIG_STM32_FMC=y
+CONFIG_STM32_EXTERNAL_RAM=y
 CONFIG_STM32_JTAG_SW_ENABLE=y
 CONFIG_STM32_PWR=y
 CONFIG_STM32_TIM1=y
diff --git a/configs/stm32f429i-disco/extflash/defconfig b/configs/stm32f429i-disco/extflash/defconfig
index 41d10e5e4d4..ea8b529b465 100644
--- a/configs/stm32f429i-disco/extflash/defconfig
+++ b/configs/stm32f429i-disco/extflash/defconfig
@@ -18,7 +18,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
@@ -59,8 +58,8 @@ CONFIG_STM32F429I_DISCO_FLASH_PART=y
 CONFIG_STM32F429I_DISCO_RAMMTD=y
 CONFIG_STM32F429I_DISCO_RAMMTD_SIZE=256
 CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
-CONFIG_STM32_FSMC=y
-CONFIG_STM32_FSMC_SRAM=y
+CONFIG_STM32_FMC=y
+CONFIG_STM32_EXTERNAL_RAM=y
 CONFIG_STM32_JTAG_SW_ENABLE=y
 CONFIG_STM32_PWR=y
 CONFIG_STM32_RNG=y
diff --git a/configs/stm32f429i-disco/fb/defconfig b/configs/stm32f429i-disco/fb/defconfig
index 66a0ea98461..f77940446ce 100644
--- a/configs/stm32f429i-disco/fb/defconfig
+++ b/configs/stm32f429i-disco/fb/defconfig
@@ -18,7 +18,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_VIDEO=y
 CONFIG_EXAMPLES_FB=y
 CONFIG_EXAMPLES_FBOVERLAY=y
@@ -67,8 +66,8 @@ CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000
 CONFIG_STM32_DMA2D_FB_SIZE=307200
 CONFIG_STM32_DMA2D_LAYER_PPLINE=240
 CONFIG_STM32_DMA2D_NLAYERS=2
-CONFIG_STM32_FSMC=y
-CONFIG_STM32_FSMC_SRAM=y
+CONFIG_STM32_FMC=y
+CONFIG_STM32_EXTERNAL_RAM=y
 CONFIG_STM32_I2C3=y
 CONFIG_STM32_JTAG_SW_ENABLE=y
 CONFIG_STM32_LTDC=y
diff --git a/configs/stm32f429i-disco/highpri/defconfig b/configs/stm32f429i-disco/highpri/defconfig
index 70221024899..0db601c6d80 100644
--- a/configs/stm32f429i-disco/highpri/defconfig
+++ b/configs/stm32f429i-disco/highpri/defconfig
@@ -19,7 +19,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_NOOPT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HEAP2_BASE=0xD0000000
 CONFIG_HEAP2_SIZE=8388608
@@ -54,8 +53,8 @@ CONFIG_STM32_ADC_NOIRQ=y
 CONFIG_STM32_CCMEXCLUDE=y
 CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
 CONFIG_STM32_DMA2=y
-CONFIG_STM32_FSMC=y
-CONFIG_STM32_FSMC_SRAM=y
+CONFIG_STM32_FMC=y
+CONFIG_STM32_EXTERNAL_RAM=y
 CONFIG_STM32_JTAG_SW_ENABLE=y
 CONFIG_STM32_PWM_LL_OPS=y
 CONFIG_STM32_PWR=y
diff --git a/configs/stm32f429i-disco/include/board.h b/configs/stm32f429i-disco/include/board.h
index 956aebb818e..2654bce169c 100644
--- a/configs/stm32f429i-disco/include/board.h
+++ b/configs/stm32f429i-disco/include/board.h
@@ -248,11 +248,11 @@
 #define GPIO_SPI4_MOSI GPIO_SPI4_MOSI_1
 #define GPIO_SPI4_SCK  GPIO_SPI4_SCK_1
 
-/* FSMC - SDRAM */
+/* FMC - SDRAM */
 
-#define GPIO_FSMC_SDCKE1 GPIO_FSMC_SDCKE1_1
-#define GPIO_FSMC_SDNE1  GPIO_FSMC_SDNE1_1
-#define GPIO_FSMC_SDNWE  GPIO_FSMC_SDNWE_1
+#define GPIO_FMC_SDCKE1 GPIO_FMC_SDCKE1_1
+#define GPIO_FMC_SDNE1  GPIO_FMC_SDNE1_1
+#define GPIO_FMC_SDNWE  GPIO_FMC_SDNWE_1
 
 /* Timer Inputs/Outputs (see the README.txt file for options) */
 
diff --git a/configs/stm32f429i-disco/lcd/defconfig b/configs/stm32f429i-disco/lcd/defconfig
index 925be131eaf..568f8da42e3 100644
--- a/configs/stm32f429i-disco/lcd/defconfig
+++ b/configs/stm32f429i-disco/lcd/defconfig
@@ -22,7 +22,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_CUSTOMOPT=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NX_BPP=16
 CONFIG_FS_PROCFS=y
@@ -63,8 +62,8 @@ CONFIG_STM32F429I_DISCO_ILI9341=y
 CONFIG_STM32F429I_DISCO_ILI9341_SPIBITS16=y
 CONFIG_STM32F429I_DISCO_ILI9341_SPIFREQUENCY=20000000
 CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
-CONFIG_STM32_FSMC=y
-CONFIG_STM32_FSMC_SRAM=y
+CONFIG_STM32_FMC=y
+CONFIG_STM32_EXTERNAL_RAM=y
 CONFIG_STM32_JTAG_SW_ENABLE=y
 CONFIG_STM32_PWR=y
 CONFIG_STM32_USART1=y
diff --git a/configs/stm32f429i-disco/lvgl/defconfig b/configs/stm32f429i-disco/lvgl/defconfig
index ecfa089a0fb..7a51804f57d 100644
--- a/configs/stm32f429i-disco/lvgl/defconfig
+++ b/configs/stm32f429i-disco/lvgl/defconfig
@@ -20,7 +20,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_CUSTOMOPT=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_VIDEO=y
 CONFIG_EXAMPLES_FB=y
 CONFIG_EXAMPLES_LVGLDEMO=y
@@ -65,8 +64,8 @@ CONFIG_START_YEAR=2017
 CONFIG_STM32F429I_DISCO_ILI9341=y
 CONFIG_STM32_CCMEXCLUDE=y
 CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
-CONFIG_STM32_FSMC=y
-CONFIG_STM32_FSMC_SRAM=y
+CONFIG_STM32_FMC=y
+CONFIG_STM32_EXTERNAL_RAM=y
 CONFIG_STM32_I2C3=y
 CONFIG_STM32_JTAG_SW_ENABLE=y
 CONFIG_STM32_LTDC=y
diff --git a/configs/stm32f429i-disco/nsh/defconfig b/configs/stm32f429i-disco/nsh/defconfig
index 132b5556f70..0f78d68b930 100644
--- a/configs/stm32f429i-disco/nsh/defconfig
+++ b/configs/stm32f429i-disco/nsh/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
@@ -47,8 +46,8 @@ CONFIG_START_DAY=6
 CONFIG_START_MONTH=12
 CONFIG_START_YEAR=2011
 CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
-CONFIG_STM32_FSMC=y
-CONFIG_STM32_FSMC_SRAM=y
+CONFIG_STM32_FMC=y
+CONFIG_STM32_EXTERNAL_RAM=y
 CONFIG_STM32_JTAG_SW_ENABLE=y
 CONFIG_STM32_PWR=y
 CONFIG_STM32_USART1=y
diff --git a/configs/stm32f429i-disco/nxhello/defconfig b/configs/stm32f429i-disco/nxhello/defconfig
index d8e4316205c..e499232c447 100644
--- a/configs/stm32f429i-disco/nxhello/defconfig
+++ b/configs/stm32f429i-disco/nxhello/defconfig
@@ -21,7 +21,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEV_LOOP=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_VIDEO=y
 CONFIG_EXAMPLES_NXHELLO=y
 CONFIG_EXAMPLES_NXHELLO_BPP=16
@@ -68,8 +67,8 @@ CONFIG_STM32_DMA2D_FB_BASE=0xD07B5000
 CONFIG_STM32_DMA2D_FB_SIZE=307200
 CONFIG_STM32_DMA2D_LAYER_PPLINE=240
 CONFIG_STM32_DMA2D_NLAYERS=2
-CONFIG_STM32_FSMC=y
-CONFIG_STM32_FSMC_SRAM=y
+CONFIG_STM32_FMC=y
+CONFIG_STM32_EXTERNAL_RAM=y
 CONFIG_STM32_JTAG_SW_ENABLE=y
 CONFIG_STM32_LTDC=y
 CONFIG_STM32_LTDC_FB_BASE=0xD076A000
diff --git a/configs/stm32f429i-disco/nxwm/defconfig b/configs/stm32f429i-disco/nxwm/defconfig
index 542aa6a3ef7..79ac042be1b 100644
--- a/configs/stm32f429i-disco/nxwm/defconfig
+++ b/configs/stm32f429i-disco/nxwm/defconfig
@@ -23,7 +23,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_CUSTOMOPT=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_VIDEO=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
@@ -99,8 +98,8 @@ CONFIG_START_MONTH=11
 CONFIG_STM32F429I_DISCO_ILI9341=y
 CONFIG_STM32_CCMEXCLUDE=y
 CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
-CONFIG_STM32_FSMC=y
-CONFIG_STM32_FSMC_SRAM=y
+CONFIG_STM32_FMC=y
+CONFIG_STM32_EXTERNAL_RAM=y
 CONFIG_STM32_I2C3=y
 CONFIG_STM32_JTAG_SW_ENABLE=y
 CONFIG_STM32_LTDC=y
diff --git a/configs/stm32f429i-disco/scripts/ld.script b/configs/stm32f429i-disco/scripts/ld.script
index 17e0ac2929a..583feebc34b 100644
--- a/configs/stm32f429i-disco/scripts/ld.script
+++ b/configs/stm32f429i-disco/scripts/ld.script
@@ -60,73 +60,77 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	/* The RAM vector table (if present) should lie at the beginning of SRAM */
+        /* The RAM vector table (if present) should lie at the beginning of SRAM */
 
-	.ram_vectors : {
-		*(.ram_vectors)
-	} > sram
+        .ram_vectors : {
+                *(.ram_vectors)
+        } > sram
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/stm32f429i-disco/scripts/memory.ld b/configs/stm32f429i-disco/scripts/memory.ld
index df11b9e3d60..da7bb9c1229 100644
--- a/configs/stm32f429i-disco/scripts/memory.ld
+++ b/configs/stm32f429i-disco/scripts/memory.ld
@@ -55,7 +55,7 @@
  * Alignment of the user space FLASH partition is also a critical factor:
  * The user space FLASH partition will be spanned with a single region of
  * size 2**n bytes.  The alignment of the user-space region must be the same.
- * As a consequence, as the user-space increases in size, the alignmment
+ * As a consequence, as the user-space increases in size, the alignment
  * requirement also increases.
  *
  * This alignment requirement means that the largest user space FLASH region
diff --git a/configs/stm32f429i-disco/src/Makefile b/configs/stm32f429i-disco/src/Makefile
index 3eec3d8eb3e..2f8631009fb 100644
--- a/configs/stm32f429i-disco/src/Makefile
+++ b/configs/stm32f429i-disco/src/Makefile
@@ -56,7 +56,7 @@ ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
 CSRCS += stm32_idle.c
 endif
 
-ifeq ($(CONFIG_STM32_FSMC),y)
+ifeq ($(CONFIG_STM32_FMC),y)
 CSRCS += stm32_extmem.c
 endif
 
diff --git a/configs/stm32f429i-disco/src/stm32_boot.c b/configs/stm32f429i-disco/src/stm32_boot.c
index 72e67fc825b..fa45f776757 100644
--- a/configs/stm32f429i-disco/src/stm32_boot.c
+++ b/configs/stm32f429i-disco/src/stm32_boot.c
@@ -96,8 +96,8 @@ void stm32_boardinitialize(void)
   board_autoled_initialize();
 #endif
 
-#ifdef CONFIG_STM32_FSMC
-  stm32_enablefsmc();
+#ifdef CONFIG_STM32_FMC
+  stm32_sdram_initialize();
 #endif
 
 #ifdef HAVE_CCM_HEAP
diff --git a/configs/stm32f429i-disco/src/stm32_extmem.c b/configs/stm32f429i-disco/src/stm32_extmem.c
index 135f68e4e37..c8f73b9cf54 100644
--- a/configs/stm32f429i-disco/src/stm32_extmem.c
+++ b/configs/stm32f429i-disco/src/stm32_extmem.c
@@ -43,69 +43,67 @@
 #include 
 #include 
 
+#include 
+
 #include "chip.h"
 #include "up_arch.h"
 
-#include "stm32_fsmc.h"
-#include "stm32_gpio.h"
 #include "stm32.h"
 #include "stm32f429i-disco.h"
 
-#include 
-
 /************************************************************************************
  * Pre-processor Definitions
  ************************************************************************************/
 
-#ifndef CONFIG_STM32_FSMC
-#  warning "FSMC is not enabled"
+#ifndef CONFIG_STM32_FMC
+#warning "FMC is not enabled"
 #endif
 
 #if STM32_NGPIO_PORTS < 6
-#  error "Required GPIO ports not enabled"
+#error "Required GPIO ports not enabled"
 #endif
 
-#define STM32_FSMC_NADDRCONFIGS 22
-#define STM32_FSMC_NDATACONFIGS 16
+#define STM32_SDRAM_CLKEN     FMC_SDCMR_CMD_CLK_ENABLE | FMC_SDCMR_BANK_2
 
-#define STM32_SDRAM_CLKEN     FSMC_SDRAM_MODE_CMD_CLK_ENABLE | FSMC_SDRAM_CMD_BANK_2
-#define STM32_SDRAM_PALL      FSMC_SDRAM_MODE_CMD_PALL | FSMC_SDRAM_CMD_BANK_2
-#define STM32_SDRAM_REFRESH   FSMC_SDRAM_MODE_CMD_AUTO_REFRESH | FSMC_SDRAM_CMD_BANK_2 |\
-                                (3 << FSMC_SDRAM_AUTO_REFRESH_SHIFT)
-#define STM32_SDRAM_MODEREG   FSMC_SDRAM_MODE_CMD_LOAD_MODE | FSMC_SDRAM_CMD_BANK_2 |\
-                                FSMC_SDRAM_MODEREG_BURST_LENGTH_2 | \
-                                FSMC_SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
-                                FSMC_SDRAM_MODEREG_CAS_LATENCY_3 |\
-                                FSMC_SDRAM_MODEREG_WRITEBURST_MODE_SINGLE
+#define STM32_SDRAM_PALL      FMC_SDCMR_CMD_PALL | FMC_SDCMR_BANK_2
 
+#define STM32_SDRAM_REFRESH   FMC_SDCMR_CMD_AUTO_REFRESH | FMC_SDCMR_BANK_2 |\
+                                FMC_SDCMR_NRFS(4)
+
+#define STM32_SDRAM_MODEREG   FMC_SDCMR_CMD_LOAD_MODE | FMC_SDCMR_BANK_2 |\
+                                FMC_SDCMR_MDR_BURST_LENGTH_2 | \
+                                FMC_SDCMR_MDR_BURST_TYPE_SEQUENTIAL |\
+                                FMC_SDCMR_MDR_CAS_LATENCY_3 |\
+                                FMC_SDCMR_MDR_WBL_SINGLE
 
 /************************************************************************************
  * Public Data
  ************************************************************************************/
 
-/* GPIO configurations common to most external memories */
-
-static const uint32_t g_addressconfig[STM32_FSMC_NADDRCONFIGS] =
-{
-  GPIO_FSMC_A0,  GPIO_FSMC_A1 , GPIO_FSMC_A2,  GPIO_FSMC_A3,  GPIO_FSMC_A4 , GPIO_FSMC_A5,
-  GPIO_FSMC_A6,  GPIO_FSMC_A7,  GPIO_FSMC_A8,  GPIO_FSMC_A9,  GPIO_FSMC_A10, GPIO_FSMC_A11,
-
-  GPIO_FSMC_SDCKE1, GPIO_FSMC_SDNE1, GPIO_FSMC_SDNWE, GPIO_FSMC_NBL0,
-  GPIO_FSMC_SDNRAS, GPIO_FSMC_NBL1,  GPIO_FSMC_BA0,   GPIO_FSMC_BA1,
-  GPIO_FSMC_SDCLK,  GPIO_FSMC_SDNCAS
-};
-
-static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] =
-{
-  GPIO_FSMC_D0,  GPIO_FSMC_D1 , GPIO_FSMC_D2,  GPIO_FSMC_D3,  GPIO_FSMC_D4 , GPIO_FSMC_D5,
-  GPIO_FSMC_D6,  GPIO_FSMC_D7,  GPIO_FSMC_D8,  GPIO_FSMC_D9,  GPIO_FSMC_D10, GPIO_FSMC_D11,
-  GPIO_FSMC_D12, GPIO_FSMC_D13, GPIO_FSMC_D14, GPIO_FSMC_D15
-};
-
 /************************************************************************************
  * Private Data
  ************************************************************************************/
 
+/* GPIO configurations common to most external memories */
+
+static const uint32_t g_sdram_config[] = {
+  /* 16 data lines */
+  GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3,
+  GPIO_FMC_D4, GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7,
+  GPIO_FMC_D8, GPIO_FMC_D9, GPIO_FMC_D10, GPIO_FMC_D11,
+  GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14, GPIO_FMC_D15,
+  /* 12 address lines */
+  GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3,
+  GPIO_FMC_A4, GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7,
+  GPIO_FMC_A8, GPIO_FMC_A9, GPIO_FMC_A10, GPIO_FMC_A11,
+  /* control lines */
+  GPIO_FMC_SDCKE1, GPIO_FMC_SDNE1, GPIO_FMC_SDNWE, GPIO_FMC_NBL0,
+  GPIO_FMC_SDNRAS, GPIO_FMC_NBL1, GPIO_FMC_BA0, GPIO_FMC_BA1,
+  GPIO_FMC_SDCLK, GPIO_FMC_SDNCAS,
+};
+
+#define NUM_SDRAM_GPIOS (sizeof(g_sdram_config) / sizeof(uint32_t))
+
 /************************************************************************************
  * Private Functions
  ************************************************************************************/
@@ -115,75 +113,27 @@ static const uint32_t g_dataconfig[STM32_FSMC_NDATACONFIGS] =
  ************************************************************************************/
 
 /************************************************************************************
- * Name: stm32_extmemgpios
+ * Name: stm32_sdram_initialize
  *
  * Description:
- *   Initialize GPIOs for external memory usage
+ *   Called from stm32_bringup to initialize external SDRAM access.
  *
  ************************************************************************************/
 
-static void stm32_extmemgpios(const uint32_t *gpios, int ngpios)
+void stm32_sdram_initialize(void)
 {
+  uint32_t val;
   int i;
-
-  /* Configure GPIOs */
-
-  for (i = 0; i < ngpios; i++)
-    {
-      stm32_configgpio(gpios[i]);
-    }
-}
-
-/************************************************************************************
- * Name: stm32_sdramcommand
- *
- * Description:
- *   Initialize data line GPIOs for external memory access
- *
- ************************************************************************************/
-
-static void stm32_sdramcommand(uint32_t command)
-{
-  uint32_t  regval;
-  volatile  uint32_t timeout = 0xFFFF;
-
-  regval = getreg32( STM32_FSMC_SDSR ) & 0x00000020;
-  while ((regval != 0) && timeout-- > 0)
-    {
-      regval = getreg32( STM32_FSMC_SDSR ) & 0x00000020;
-    }
-  putreg32(command, STM32_FSMC_SDCMR);
-  timeout = 0xFFFF;
-  regval = getreg32( STM32_FSMC_SDSR ) & 0x00000020;
-  while ((regval != 0) && timeout-- > 0)
-    {
-      regval = getreg32( STM32_FSMC_SDSR ) & 0x00000020;
-    }
-}
-
-/************************************************************************************
- * Name: stm32_enablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-void stm32_enablefsmc(void)
-{
-  uint32_t regval;
   volatile int count;
 
-  /* Enable GPIOs as FSMC / memory pins */
+  /* Enable GPIOs as FMC / memory pins */
+  for (i = 0; i < NUM_SDRAM_GPIOS; i++)
+    {
+      stm32_configgpio(g_sdram_config[i]);
+    }
 
-  stm32_extmemgpios(g_addressconfig, STM32_FSMC_NADDRCONFIGS);
-  stm32_extmemgpios(g_dataconfig, STM32_FSMC_NDATACONFIGS);
-
-  /* Enable AHB clocking to the FSMC */
-
-  regval  = getreg32( STM32_RCC_AHB3ENR);
-  regval |= RCC_AHB3ENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHB3ENR);
+  /* Enable AHB clocking to the FMC */
+  stm32_fmc_enable();
 
   /* Configure and enable the SDRAM bank1
    *
@@ -191,41 +141,31 @@ void stm32_enablefsmc(void)
    *   90MHz = 11,11 ns
    *   All timings from the datasheet for Speedgrade -7 (=7ns)
    */
+  val = FMC_SDCR_RPIPE_1 |      /* rpipe = 1 hclk */
+    FMC_SDCR_SDCLK_2X |         /* sdclk = 2 hclk */
+    FMC_SDCR_CAS_LATENCY_3 |    /* cas latency = 3 cycles */
+    FMC_SDCR_NBANKS_4 |         /* 4 internal banks */
+    FMC_SDCR_WIDTH_16 |         /* width = 16 bits */
+    FMC_SDCR_ROWS_12 |          /* numrows = 12 */
+    FMC_SDCR_COLS_8;            /* numcols = 8 bits */
+  stm32_fmc_sdram_set_control(1, val);
+  stm32_fmc_sdram_set_control(2, val);
 
-  putreg32(FSMC_SDRAM_CR_RPIPE_1 |
-           FSMC_SDRAM_CR_SDCLK_2X |
-           FSMC_SDRAM_CR_CASLAT_3 |
-           FSMC_SDRAM_CR_BANKS_4 |
-           FSMC_SDRAM_CR_WIDTH_16 |
-           FSMC_SDRAM_CR_ROWBITS_12 |
-           FSMC_SDRAM_CR_COLBITS_8,
-      STM32_FSMC_SDCR1);
-
-  putreg32(FSMC_SDRAM_CR_RPIPE_1 |
-           FSMC_SDRAM_CR_SDCLK_2X |
-           FSMC_SDRAM_CR_CASLAT_3 |
-           FSMC_SDRAM_CR_BANKS_4 |
-           FSMC_SDRAM_CR_WIDTH_16 |
-           FSMC_SDRAM_CR_ROWBITS_12 |
-           FSMC_SDRAM_CR_COLBITS_8,
-      STM32_FSMC_SDCR2);
-
-  putreg32((2 << FSMC_SDRAM_TR_TRCD_SHIFT) |  /* tRCD min = 15ns */
-           (2 << FSMC_SDRAM_TR_TRP_SHIFT) |   /* tRP  min = 15ns */
-           (2 << FSMC_SDRAM_TR_TWR_SHIFT) |   /* tWR      = 2CLK */
-           (7 << FSMC_SDRAM_TR_TRC_SHIFT) |   /* tRC  min = 63ns */
-           (4 << FSMC_SDRAM_TR_TRAS_SHIFT) |  /* tRAS min = 42ns */
-           (7 << FSMC_SDRAM_TR_TXSR_SHIFT) |  /* tXSR min = 70ns */
-           (2 << FSMC_SDRAM_TR_TMRD_SHIFT),   /* tMRD     = 2CLK */
-      STM32_FSMC_SDTR2);
+  val = FMC_SDTR_TRCD(3) |      /* tRCD min = 15ns */
+    FMC_SDTR_TRP(3) |           /* tRP  min = 15ns */
+    FMC_SDTR_TWR(3) |           /* tWR      = 2CLK */
+    FMC_SDTR_TRC(8) |           /* tRC  min = 63ns */
+    FMC_SDTR_TRAS(5) |          /* tRAS min = 42ns */
+    FMC_SDTR_TXSR(8) |          /* tXSR min = 70ns */
+    FMC_SDTR_TMRD(3);           /* tMRD     = 2CLK */
+  stm32_fmc_sdram_set_timing(2, val);
 
   /* SDRAM Initialization sequence */
-
-  stm32_sdramcommand(STM32_SDRAM_CLKEN);      /* Clock enable command */
-  for (count = 0; count < 10000; count++) ;    /* Delay */
-  stm32_sdramcommand(STM32_SDRAM_PALL);       /* Precharge ALL command */
-  stm32_sdramcommand(STM32_SDRAM_REFRESH);    /* Auto refresh command */
-  stm32_sdramcommand(STM32_SDRAM_MODEREG);    /* Mode Register program */
+  stm32_fmc_sdram_command(STM32_SDRAM_CLKEN);   /* Clock enable command */
+  for (count = 0; count < 10000; count++);      /* Delay */
+  stm32_fmc_sdram_command(STM32_SDRAM_PALL);    /* Precharge ALL command */
+  stm32_fmc_sdram_command(STM32_SDRAM_REFRESH); /* Auto refresh command */
+  stm32_fmc_sdram_command(STM32_SDRAM_MODEREG); /* Mode Register program */
 
   /* Set refresh count
    *
@@ -233,30 +173,8 @@ void stm32_enablefsmc(void)
    * Refresh_Rate = 7.81us
    * Counter = (FMC_CLK * Refresh_Rate) - 20
    */
-
-  putreg32(683 << 1, STM32_FSMC_SDRTR);
+  stm32_fmc_sdram_set_refresh_rate(683);
 
   /* Disable write protection */
-
-//  regval = getreg32(STM32_FSMC_SDCR2);
-//  putreg32(regval & 0xFFFFFDFF, STM32_FSMC_SDCR2);
-}
-
-/************************************************************************************
- * Name: stm32_disablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-void stm32_disablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Disable AHB clocking to the FSMC */
-
-  regval  = getreg32(STM32_RCC_AHB3ENR);
-  regval &= ~RCC_AHB3ENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHB3ENR);
+  // stm32_fmc_sdram_write_protect(2, false);
 }
diff --git a/configs/stm32f429i-disco/src/stm32_highpri.c b/configs/stm32f429i-disco/src/stm32_highpri.c
index 434a643e0c7..30fe72c3147 100644
--- a/configs/stm32f429i-disco/src/stm32_highpri.c
+++ b/configs/stm32f429i-disco/src/stm32_highpri.c
@@ -389,9 +389,9 @@ int highpri_main(int argc, char *argv[])
 
   PWM_CCR_UPDATE(pwm1, 1, 0x0f00);
 
-  /* Enable TIM1 CHAN1 */
+  /* Enable TIM1 OUT1 */
 
-  PWM_OUTPUTS_ENABLE(pwm1, STM32_CHAN1, true);
+  PWM_OUTPUTS_ENABLE(pwm1, STM32_PWM_OUT1, true);
 #else
 #  error T1CC1 only supported for now
 #endif
diff --git a/configs/stm32f429i-disco/src/stm32_ostest.c b/configs/stm32f429i-disco/src/stm32_ostest.c
index 65c0fa0e5e6..9cfe0f050c0 100644
--- a/configs/stm32f429i-disco/src/stm32_ostest.c
+++ b/configs/stm32f429i-disco/src/stm32_ostest.c
@@ -58,8 +58,7 @@
 
 #undef HAVE_FPU
 #if defined(CONFIG_ARCH_FPU) && !defined(CONFIG_TESTING_OSTEST_FPUTESTDISABLE) && \
-    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID) && \
-    !defined(CONFIG_DISABLE_SIGNALS)
+    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID)
 #    define HAVE_FPU 1
 #endif
 
diff --git a/configs/stm32f429i-disco/src/stm32f429i-disco.h b/configs/stm32f429i-disco/src/stm32f429i-disco.h
index 61e486df4ae..a1fd456b640 100644
--- a/configs/stm32f429i-disco/src/stm32f429i-disco.h
+++ b/configs/stm32f429i-disco/src/stm32f429i-disco.h
@@ -274,30 +274,16 @@ int stm32_usbhost_initialize(void);
 int stm32_tsc_setup(int minor);
 #endif
 
-/****************************************************************************
-
- * Name: stm32_enablefsmc
+/************************************************************************************
+ * Name: stm32_sdram_initialize
  *
  * Description:
- *  enable clocking to the FSMC module
+ *   Called from stm32_bringup to initialize external SDRAM access.
  *
- ****************************************************************************/
+ ************************************************************************************/
 
-#ifdef CONFIG_STM32_FSMC
-void stm32_enablefsmc(void);
-#endif
-
-/****************************************************************************
-
- * Name: stm32_disablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ****************************************************************************/
-
-#ifdef CONFIG_STM32_FSMC
-void stm32_disablefsmc(void);
+#ifdef CONFIG_STM32_FMC
+void stm32_sdram_initialize(void);
 #endif
 
 /****************************************************************************
diff --git a/configs/stm32f429i-disco/usbmsc/defconfig b/configs/stm32f429i-disco/usbmsc/defconfig
index fdddc6850ef..b4681447ae1 100644
--- a/configs/stm32f429i-disco/usbmsc/defconfig
+++ b/configs/stm32f429i-disco/usbmsc/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_FAT=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
@@ -51,8 +50,8 @@ CONFIG_START_DAY=6
 CONFIG_START_MONTH=12
 CONFIG_START_YEAR=2011
 CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
-CONFIG_STM32_FSMC=y
-CONFIG_STM32_FSMC_SRAM=y
+CONFIG_STM32_FMC=y
+CONFIG_STM32_EXTERNAL_RAM=y
 CONFIG_STM32_JTAG_SW_ENABLE=y
 CONFIG_STM32_OTGHS=y
 CONFIG_STM32_PWR=y
diff --git a/configs/stm32f429i-disco/usbnsh/defconfig b/configs/stm32f429i-disco/usbnsh/defconfig
index c31631400a3..133e39a6121 100644
--- a/configs/stm32f429i-disco/usbnsh/defconfig
+++ b/configs/stm32f429i-disco/usbnsh/defconfig
@@ -23,7 +23,6 @@ CONFIG_CDCACM_RXBUFSIZE=256
 CONFIG_CDCACM_TXBUFSIZE=256
 CONFIG_DEV_LOOP=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_FAT=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
@@ -58,8 +57,8 @@ CONFIG_START_DAY=6
 CONFIG_START_MONTH=12
 CONFIG_START_YEAR=2011
 CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
-CONFIG_STM32_FSMC=y
-CONFIG_STM32_FSMC_SRAM=y
+CONFIG_STM32_FMC=y
+CONFIG_STM32_EXTERNAL_RAM=y
 CONFIG_STM32_JTAG_SW_ENABLE=y
 CONFIG_STM32_OTGHS=y
 CONFIG_STM32_PWR=y
diff --git a/configs/stm32f4discovery/audio/defconfig b/configs/stm32f4discovery/audio/defconfig
index 6cd87eb4f8f..6ca1a8d1f00 100644
--- a/configs/stm32f4discovery/audio/defconfig
+++ b/configs/stm32f4discovery/audio/defconfig
@@ -23,7 +23,6 @@ CONFIG_AUDIO_EXCLUDE_TONE=y
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_AUDIO=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
diff --git a/configs/stm32f4discovery/cxxtest/defconfig b/configs/stm32f4discovery/cxxtest/defconfig
index dff815947d0..0c9e4bd373e 100644
--- a/configs/stm32f4discovery/cxxtest/defconfig
+++ b/configs/stm32f4discovery/cxxtest/defconfig
@@ -18,7 +18,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_C99_BOOL8=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_TESTING_CXXTEST=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
diff --git a/configs/stm32f4discovery/ipv6/defconfig b/configs/stm32f4discovery/ipv6/defconfig
index 20ca114da91..1403120a71e 100644
--- a/configs/stm32f4discovery/ipv6/defconfig
+++ b/configs/stm32f4discovery/ipv6/defconfig
@@ -38,6 +38,8 @@ CONFIG_MMCSD=y
 CONFIG_MMCSD_MULTIBLOCK_DISABLE=y
 CONFIG_MMCSD_SDIO=y
 CONFIG_NET=y
+CONFIG_NETINIT_IPv6NETMASK_8=0xff80
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_ETH_PKTSIZE=590
 CONFIG_NET_ICMPv6=y
@@ -55,9 +57,7 @@ CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_IPv6NETMASK_8=0xff80
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/stm32f4discovery/kernel/stm32_userspace.c b/configs/stm32f4discovery/kernel/stm32_userspace.c
index 1dac94c6fce..df0ef9487ba 100644
--- a/configs/stm32f4discovery/kernel/stm32_userspace.c
+++ b/configs/stm32f4discovery/kernel/stm32_userspace.c
@@ -115,9 +115,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/stm32f4discovery/kostest/defconfig b/configs/stm32f4discovery/kostest/defconfig
index 08b87a17c1b..f4af2dd33ae 100644
--- a/configs/stm32f4discovery/kostest/defconfig
+++ b/configs/stm32f4discovery/kostest/defconfig
@@ -19,7 +19,6 @@ CONFIG_BUILD_PROTECTED=y
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/stm32f4discovery/max31855/defconfig b/configs/stm32f4discovery/max31855/defconfig
index 213f6179d7c..f0ddff5a262 100644
--- a/configs/stm32f4discovery/max31855/defconfig
+++ b/configs/stm32f4discovery/max31855/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_MAX31855=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/stm32f4discovery/module/defconfig b/configs/stm32f4discovery/module/defconfig
index 952201db737..885108645b0 100644
--- a/configs/stm32f4discovery/module/defconfig
+++ b/configs/stm32f4discovery/module/defconfig
@@ -18,7 +18,6 @@ CONFIG_ARCH_CHIP_STM32F407VG=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_MODULE=y
 CONFIG_FS_PROCFS=y
 CONFIG_FS_ROMFS=y
diff --git a/configs/stm32f4discovery/netnsh/defconfig b/configs/stm32f4discovery/netnsh/defconfig
index c308b897708..74cc42edb11 100644
--- a/configs/stm32f4discovery/netnsh/defconfig
+++ b/configs/stm32f4discovery/netnsh/defconfig
@@ -41,6 +41,8 @@ CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
 CONFIG_NETDEV_PHY_IOCTL=y
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -48,7 +50,6 @@ CONFIG_NET_ARP_SEND=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_SOLINGER=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -61,8 +62,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETINIT_THREAD=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/stm32f4discovery/nsh/defconfig b/configs/stm32f4discovery/nsh/defconfig
index f1aab852071..1b973d2ef60 100644
--- a/configs/stm32f4discovery/nsh/defconfig
+++ b/configs/stm32f4discovery/nsh/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/stm32f4discovery/nxlines/defconfig b/configs/stm32f4discovery/nxlines/defconfig
index 8162940fe5b..410a678e9e7 100644
--- a/configs/stm32f4discovery/nxlines/defconfig
+++ b/configs/stm32f4discovery/nxlines/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARCH_CHIP_STM32F407VG=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NXLINES=y
 CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0320
 CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xffe0
diff --git a/configs/stm32f4discovery/pm/defconfig b/configs/stm32f4discovery/pm/defconfig
index 087de6a4017..eaab60f6a0d 100644
--- a/configs/stm32f4discovery/pm/defconfig
+++ b/configs/stm32f4discovery/pm/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
diff --git a/configs/stm32f4discovery/rgbled/defconfig b/configs/stm32f4discovery/rgbled/defconfig
index e96e274b157..a9d73ab8cdd 100644
--- a/configs/stm32f4discovery/rgbled/defconfig
+++ b/configs/stm32f4discovery/rgbled/defconfig
@@ -19,7 +19,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
 CONFIG_EXAMPLES_RGBLED=y
diff --git a/configs/stm32f4discovery/rndis/defconfig b/configs/stm32f4discovery/rndis/defconfig
index 9521f819db2..f7a60d80123 100644
--- a/configs/stm32f4discovery/rndis/defconfig
+++ b/configs/stm32f4discovery/rndis/defconfig
@@ -23,7 +23,6 @@ CONFIG_BOARDCTL_USBDEVCTRL=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILD_LOADABLE=y
 CONFIG_BUILTIN=y
-CONFIG_SYMTAB_ORDEREDBYNAME=y
 CONFIG_CLOCK_MONOTONIC=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
@@ -37,15 +36,20 @@ CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_INTELHEX_BINARY=y
-CONFIG_MAX_TASKS=16
-CONFIG_MAX_WDOGPARMS=2
 CONFIG_LIBC_EXECFUNCS=y
 CONFIG_LIB_ENVPATH=y
-CONFIG_PATH_INITIAL="/mnt/nfs/bin"
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0
 CONFIG_NETDEVICES=y
+CONFIG_NETINIT_DHCPC=y
+CONFIG_NETINIT_DRIPADDR=0x0
+CONFIG_NETINIT_MACADDR_1=0xdeadcafe
+CONFIG_NETINIT_NETMASK=0x0
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -54,7 +58,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_LOOPBACK=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCP_WRITE_BUFFERS=y
@@ -65,17 +68,12 @@ CONFIG_NFS=y
 CONFIG_NFS_STATISTICS=y
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
-CONFIG_NSH_DHCPC=y
-CONFIG_NSH_DRIPADDR=0x0
-CONFIG_NSH_FILE_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_FILE_APPS=y
 CONFIG_NSH_LINELEN=128
-CONFIG_NSH_MACADDR=0x00e0deadcafe
-CONFIG_NSH_NETINIT_THREAD=y
-CONFIG_NSH_NETMASK=0x0
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSH_TELNETD_CLIENTSTACKSIZE=3072
+CONFIG_PATH_INITIAL="/mnt/nfs/bin"
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
 CONFIG_PREALLOC_WDOGS=16
@@ -98,11 +96,12 @@ CONFIG_STM32_OTGFS=y
 CONFIG_STM32_PWR=y
 CONFIG_STM32_SPI1=y
 CONFIG_STM32_USART2=y
+CONFIG_SYMTAB_ORDEREDBYNAME=y
 CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
 CONFIG_SYSTEM_NSH_SYMTAB=y
 CONFIG_SYSTEM_NSH_SYMTAB_ARRAYNAME="g_symtab"
 CONFIG_SYSTEM_NSH_SYMTAB_COUNTNAME="g_nsymbols"
-CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
 CONFIG_SYSTEM_PING=y
 CONFIG_USART2_SERIAL_CONSOLE=y
 CONFIG_USBDEV=y
diff --git a/configs/stm32f4discovery/scripts/ld.script b/configs/stm32f4discovery/scripts/ld.script
index 0c3c1edda4c..35b35e1b8af 100644
--- a/configs/stm32f4discovery/scripts/ld.script
+++ b/configs/stm32f4discovery/scripts/ld.script
@@ -57,67 +57,71 @@ ENTRY(_stext)
 EXTERN(_vectors)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                KEEP(*(.init_array .init_array.*))
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/stm32f4discovery/scripts/memory.ld b/configs/stm32f4discovery/scripts/memory.ld
index 3a7480d8714..f81320551a5 100644
--- a/configs/stm32f4discovery/scripts/memory.ld
+++ b/configs/stm32f4discovery/scripts/memory.ld
@@ -54,7 +54,7 @@
  * Alignment of the user space FLASH partition is also a critical factor:
  * The user space FLASH partition will be spanned with a single region of
  * size 2**n bytes.  The alignment of the user-space region must be the same.
- * As a consequence, as the user-space increases in size, the alignmment
+ * As a consequence, as the user-space increases in size, the alignment
  * requirement also increases.
  *
  * This alignment requirement means that the largest user space FLASH region
diff --git a/configs/stm32f4discovery/src/stm32_appinit.c b/configs/stm32f4discovery/src/stm32_appinit.c
index c0c0924a836..a6e91745067 100644
--- a/configs/stm32f4discovery/src/stm32_appinit.c
+++ b/configs/stm32f4discovery/src/stm32_appinit.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * config/stm32f4discovery/src/stm32_appinit.c
  *
- *   Copyright (C) 2012, 2014, 2016, 20018 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2012, 2014, 2016, 2018 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/configs/stm32f4discovery/src/stm32_bringup.c b/configs/stm32f4discovery/src/stm32_bringup.c
index 90f482f4537..f9ff25c940a 100644
--- a/configs/stm32f4discovery/src/stm32_bringup.c
+++ b/configs/stm32f4discovery/src/stm32_bringup.c
@@ -427,14 +427,14 @@ int stm32_bringup(void)
     }
 #endif
 
-#if defined(CONFIG_RNDIS) && defined(CONFIG_NSH_MACADDR)
+#if defined(CONFIG_RNDIS) && defined(CONFIG_NETINIT_MACADDR)
   uint8_t mac[6];
   mac[0] = 0xa0; /* TODO */
-  mac[1] = (CONFIG_NSH_MACADDR >> (8 * 4)) & 0xff;
-  mac[2] = (CONFIG_NSH_MACADDR >> (8 * 3)) & 0xff;
-  mac[3] = (CONFIG_NSH_MACADDR >> (8 * 2)) & 0xff;
-  mac[4] = (CONFIG_NSH_MACADDR >> (8 * 1)) & 0xff;
-  mac[5] = (CONFIG_NSH_MACADDR >> (8 * 0)) & 0xff;
+  mac[1] = (CONFIG_NETINIT_MACADDR >> (8 * 4)) & 0xff;
+  mac[2] = (CONFIG_NETINIT_MACADDR >> (8 * 3)) & 0xff;
+  mac[3] = (CONFIG_NETINIT_MACADDR >> (8 * 2)) & 0xff;
+  mac[4] = (CONFIG_NETINIT_MACADDR >> (8 * 1)) & 0xff;
+  mac[5] = (CONFIG_NETINIT_MACADDR >> (8 * 0)) & 0xff;
   usbdev_rndis_initialize(mac);
 #endif
 
diff --git a/configs/stm32f4discovery/src/stm32_extmem.c b/configs/stm32f4discovery/src/stm32_extmem.c
index f5f531e0680..912d2b2c135 100644
--- a/configs/stm32f4discovery/src/stm32_extmem.c
+++ b/configs/stm32f4discovery/src/stm32_extmem.c
@@ -145,41 +145,3 @@ void stm32_extmemdata(int ndata)
 {
   stm32_extmemgpios(g_dataconfig, ndata);
 }
-
-/************************************************************************************
- * Name: stm32_enablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-void stm32_enablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Enable AHB clocking to the FSMC */
-
-  regval  = getreg32( STM32_RCC_AHB3ENR);
-  regval |= RCC_AHB3ENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHB3ENR);
-}
-
-/************************************************************************************
- * Name: stm32_disablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-void stm32_disablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Disable AHB clocking to the FSMC */
-
-  regval  = getreg32(STM32_RCC_AHB3ENR);
-  regval &= ~RCC_AHB3ENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHB3ENR);
-}
diff --git a/configs/stm32f4discovery/src/stm32_ostest.c b/configs/stm32f4discovery/src/stm32_ostest.c
index 742caf9aed8..79fdba5a53c 100644
--- a/configs/stm32f4discovery/src/stm32_ostest.c
+++ b/configs/stm32f4discovery/src/stm32_ostest.c
@@ -59,8 +59,7 @@
 
 #undef HAVE_FPU
 #if defined(CONFIG_ARCH_FPU) && !defined(CONFIG_TESTING_OSTEST_FPUTESTDISABLE) && \
-    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID) && \
-    !defined(CONFIG_DISABLE_SIGNALS)
+    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID)
 #    define HAVE_FPU 1
 #endif
 
diff --git a/configs/stm32f4discovery/src/stm32_ssd1289.c b/configs/stm32f4discovery/src/stm32_ssd1289.c
index 488316763cc..a5abfe2149a 100644
--- a/configs/stm32f4discovery/src/stm32_ssd1289.c
+++ b/configs/stm32f4discovery/src/stm32_ssd1289.c
@@ -280,7 +280,7 @@ void stm32_selectlcd(void)
 
   /* Enable AHB clocking to the FSMC */
 
-  stm32_enablefsmc();
+  stm32_fsmc_enable();
 
   /* Color LCD configuration (LCD configured as follow):
    *
diff --git a/configs/stm32f4discovery/src/stm32f4discovery.h b/configs/stm32f4discovery/src/stm32f4discovery.h
index 2d6be6268ae..dc99c9c71ff 100644
--- a/configs/stm32f4discovery/src/stm32f4discovery.h
+++ b/configs/stm32f4discovery/src/stm32f4discovery.h
@@ -171,8 +171,7 @@
 #endif
 
 #if !defined(CONFIG_NSH_NETINIT_THREAD) || !defined(CONFIG_ARCH_PHY_INTERRUPT) || \
-    !defined(CONFIG_NETDEV_PHY_IOCTL) || !defined(CONFIG_NET_UDP) || \
-     defined(CONFIG_DISABLE_SIGNALS)
+    !defined(CONFIG_NETDEV_PHY_IOCTL) || !defined(CONFIG_NET_UDP)
 #  undef HAVE_NETMONITOR
 #endif
 
@@ -595,30 +594,6 @@ void stm32_extmemaddr(int naddrs);
 void stm32_extmemdata(int ndata);
 #endif
 
-/****************************************************************************
- * Name: stm32_enablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ****************************************************************************/
-
-#ifdef CONFIG_STM32_FSMC
-void stm32_enablefsmc(void);
-#endif
-
-/****************************************************************************
- * Name: stm32_disablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ****************************************************************************/
-
-#ifdef CONFIG_STM32_FSMC
-void stm32_disablefsmc(void);
-#endif
-
 /****************************************************************************
  * Name: stm32_led_pminitialize
  *
diff --git a/configs/stm32f4discovery/testlibcxx/defconfig b/configs/stm32f4discovery/testlibcxx/defconfig
index 5ce688f88a5..c7da07e0f45 100644
--- a/configs/stm32f4discovery/testlibcxx/defconfig
+++ b/configs/stm32f4discovery/testlibcxx/defconfig
@@ -18,7 +18,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_C99_BOOL8=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_HELLOXX=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
diff --git a/configs/stm32f4discovery/usbmsc/defconfig b/configs/stm32f4discovery/usbmsc/defconfig
index e07845b9999..51ae6800618 100644
--- a/configs/stm32f4discovery/usbmsc/defconfig
+++ b/configs/stm32f4discovery/usbmsc/defconfig
@@ -16,7 +16,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/stm32f4discovery/usbnsh/defconfig b/configs/stm32f4discovery/usbnsh/defconfig
index 90b48c5dc4f..ecf5bafa149 100644
--- a/configs/stm32f4discovery/usbnsh/defconfig
+++ b/configs/stm32f4discovery/usbnsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_CDCACM=y
 CONFIG_CDCACM_CONSOLE=y
 CONFIG_CDCACM_RXBUFSIZE=256
 CONFIG_CDCACM_TXBUFSIZE=256
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
diff --git a/configs/stm32f4discovery/winbuild/defconfig b/configs/stm32f4discovery/winbuild/defconfig
index f0e9bb094f6..255c78e0c4f 100644
--- a/configs/stm32f4discovery/winbuild/defconfig
+++ b/configs/stm32f4discovery/winbuild/defconfig
@@ -17,7 +17,6 @@ CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_MAX_TASKS=16
diff --git a/configs/stm32f4discovery/xen1210/defconfig b/configs/stm32f4discovery/xen1210/defconfig
index 0c6e82c9939..2e3bd98344c 100644
--- a/configs/stm32f4discovery/xen1210/defconfig
+++ b/configs/stm32f4discovery/xen1210/defconfig
@@ -19,7 +19,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LATE_INITIALIZE=y
 CONFIG_BOARD_LOOPSPERMSEC=16717
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
diff --git a/configs/stm32f746g-disco/fb/defconfig b/configs/stm32f746g-disco/fb/defconfig
index f2c75063226..ac05810325b 100644
--- a/configs/stm32f746g-disco/fb/defconfig
+++ b/configs/stm32f746g-disco/fb/defconfig
@@ -27,7 +27,6 @@ CONFIG_BOARD_LOOPSPERMSEC=43103
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_VIDEO=y
 CONFIG_EXAMPLES_FB=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/stm32f746g-disco/include/board.h b/configs/stm32f746g-disco/include/board.h
index 0a71112f34d..0903e13bcbb 100644
--- a/configs/stm32f746g-disco/include/board.h
+++ b/configs/stm32f746g-disco/include/board.h
@@ -348,6 +348,13 @@
 #define GPIO_USART1_RX GPIO_USART1_RX_2
 #define GPIO_USART1_TX GPIO_USART1_TX_1
 
+/* I2C1 - the I2C1 bus is shared by audio (Cirrus WM8994),
+ * camera (DCMI SDA/SCL) and external connectors CN2 & Arduino D14/D15.
+ */
+
+#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
+#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2
+
 /* I2C - There is a FT5336 TouchPanel on I2C3 using these pins: */
 
 #define GPIO_I2C3_SCL GPIO_I2C3_SCL_2
diff --git a/configs/stm32f746g-disco/kernel/stm32_userspace.c b/configs/stm32f746g-disco/kernel/stm32_userspace.c
index 427a763e4ab..f74776751d2 100644
--- a/configs/stm32f746g-disco/kernel/stm32_userspace.c
+++ b/configs/stm32f746g-disco/kernel/stm32_userspace.c
@@ -115,9 +115,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/stm32f746g-disco/lvgl/defconfig b/configs/stm32f746g-disco/lvgl/defconfig
index e08dceccf43..5f78e63d5eb 100644
--- a/configs/stm32f746g-disco/lvgl/defconfig
+++ b/configs/stm32f746g-disco/lvgl/defconfig
@@ -26,7 +26,6 @@ CONFIG_BOARD_LOOPSPERMSEC=43103
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_VIDEO=y
 CONFIG_EXAMPLES_FB=y
 CONFIG_EXAMPLES_LVGLDEMO=y
diff --git a/configs/stm32f746g-disco/netnsh/defconfig b/configs/stm32f746g-disco/netnsh/defconfig
index 7dfaa413ad6..54e21b1dc26 100644
--- a/configs/stm32f746g-disco/netnsh/defconfig
+++ b/configs/stm32f746g-disco/netnsh/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARMV7M_ICACHE=y
 CONFIG_BOARD_LOOPSPERMSEC=43103
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_ETH0_PHY_LAN8742A=y
 CONFIG_FS_PROCFS=y
 CONFIG_FS_PROCFS_REGISTER=y
@@ -33,6 +32,9 @@ CONFIG_MAX_WDOGPARMS=2
 CONFIG_MM_REGIONS=3
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
+CONFIG_NETINIT_DHCPC=y
+CONFIG_NETINIT_NETMASK=0xfffffe00
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_DISCOVER=y
 CONFIG_NET_ARP_IPIN=y
@@ -50,12 +52,9 @@ CONFIG_NET_UDP_CHECKSUMS=y
 CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_BUILTIN_APPS=y
-CONFIG_NSH_DHCPC=y
 CONFIG_NSH_DISABLE_IFUPDOWN=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETMASK=0xfffffe00
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PIPES=y
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/stm32f746g-disco/nsh/defconfig b/configs/stm32f746g-disco/nsh/defconfig
index bb806551179..3883df989b8 100644
--- a/configs/stm32f746g-disco/nsh/defconfig
+++ b/configs/stm32f746g-disco/nsh/defconfig
@@ -23,7 +23,6 @@ CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y
 CONFIG_BOARD_LOOPSPERMSEC=43103
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/stm32f746g-disco/nxdemo/defconfig b/configs/stm32f746g-disco/nxdemo/defconfig
index 8dce97060c8..57e7186abba 100644
--- a/configs/stm32f746g-disco/nxdemo/defconfig
+++ b/configs/stm32f746g-disco/nxdemo/defconfig
@@ -27,7 +27,6 @@ CONFIG_BOARD_LOOPSPERMSEC=43103
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_VIDEO=y
 CONFIG_EXAMPLES_NX=y
 CONFIG_EXAMPLES_NXDEMO=y
diff --git a/configs/stm32f746g-disco/nxterm/defconfig b/configs/stm32f746g-disco/nxterm/defconfig
index 01a107ad7cf..7c7d6ab3633 100644
--- a/configs/stm32f746g-disco/nxterm/defconfig
+++ b/configs/stm32f746g-disco/nxterm/defconfig
@@ -28,7 +28,6 @@ CONFIG_BOARD_LOOPSPERMSEC=43103
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DRIVERS_VIDEO=y
 CONFIG_EXAMPLES_NXTERM=y
 CONFIG_HAVE_CXX=y
diff --git a/configs/stm32f746g-disco/src/stm32_ostest.c b/configs/stm32f746g-disco/src/stm32_ostest.c
index f6c91b22f61..4ce5dff67e0 100644
--- a/configs/stm32f746g-disco/src/stm32_ostest.c
+++ b/configs/stm32f746g-disco/src/stm32_ostest.c
@@ -58,8 +58,7 @@
 
 #undef HAVE_FPU
 #if defined(CONFIG_ARCH_FPU) && !defined(CONFIG_TESTING_OSTEST_FPUTESTDISABLE) && \
-    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID) && \
-    !defined(CONFIG_DISABLE_SIGNALS)
+    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID)
 #    define HAVE_FPU 1
 #endif
 
diff --git a/configs/stm32f769i-disco/kernel/stm32_userspace.c b/configs/stm32f769i-disco/kernel/stm32_userspace.c
index d0fd835c82a..73a4b44c499 100644
--- a/configs/stm32f769i-disco/kernel/stm32_userspace.c
+++ b/configs/stm32f769i-disco/kernel/stm32_userspace.c
@@ -115,9 +115,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/stm32f769i-disco/nsh/defconfig b/configs/stm32f769i-disco/nsh/defconfig
index 46bb4e81ca0..56b84cd890e 100644
--- a/configs/stm32f769i-disco/nsh/defconfig
+++ b/configs/stm32f769i-disco/nsh/defconfig
@@ -21,7 +21,6 @@ CONFIG_ARMV7M_ICACHE=y
 CONFIG_ARMV7M_LAZYFPU=y
 CONFIG_BOARD_LOOPSPERMSEC=43103
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/stm32f769i-disco/src/stm32_ostest.c b/configs/stm32f769i-disco/src/stm32_ostest.c
index b7829a814f9..3d676820549 100644
--- a/configs/stm32f769i-disco/src/stm32_ostest.c
+++ b/configs/stm32f769i-disco/src/stm32_ostest.c
@@ -58,8 +58,7 @@
 
 #undef HAVE_FPU
 #if defined(CONFIG_ARCH_FPU) && !defined(CONFIG_TESTING_OSTEST_FPUTESTDISABLE) && \
-    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID) && \
-    !defined(CONFIG_DISABLE_SIGNALS)
+    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID)
 #    define HAVE_FPU 1
 #endif
 
diff --git a/configs/stm32l476-mdk/nsh/defconfig b/configs/stm32l476-mdk/nsh/defconfig
index 51e790b2a12..e3f68a7ed8a 100644
--- a/configs/stm32l476-mdk/nsh/defconfig
+++ b/configs/stm32l476-mdk/nsh/defconfig
@@ -24,7 +24,6 @@ CONFIG_BOARD_LOOPSPERMSEC=8499
 CONFIG_BUILTIN=y
 CONFIG_DEV_LOOP=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_FS_PROCFS_REGISTER=y
 CONFIG_FS_ROMFS=y
diff --git a/configs/stm32l476-mdk/src/stm32_spi.c b/configs/stm32l476-mdk/src/stm32_spi.c
index ae13e9e59d7..d40b8ad381b 100644
--- a/configs/stm32l476-mdk/src/stm32_spi.c
+++ b/configs/stm32l476-mdk/src/stm32_spi.c
@@ -48,7 +48,7 @@
 #include 
 
 #include 
-#include 
+#include "chip.h"
 #include 
 
 #include "stm32l476-mdk.h"
diff --git a/configs/stm32l476vg-disco/include/board.h b/configs/stm32l476vg-disco/include/board.h
index 5713b402e8b..4765a663dd6 100644
--- a/configs/stm32l476vg-disco/include/board.h
+++ b/configs/stm32l476vg-disco/include/board.h
@@ -60,7 +60,7 @@
  * is we set aside more DMA channels/streams.
  */
 
-/* Values defined in arch/arm/src/stm32l4/chip/stm32l4x6xx_dma.h */
+/* Values defined in arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h */
 
 /* XXX are these used on disco? */
 
diff --git a/configs/stm32l476vg-disco/kernel/stm32l4_userspace.c b/configs/stm32l476vg-disco/kernel/stm32l4_userspace.c
index b5c3a0f6b7a..296836a7929 100644
--- a/configs/stm32l476vg-disco/kernel/stm32l4_userspace.c
+++ b/configs/stm32l476vg-disco/kernel/stm32l4_userspace.c
@@ -115,9 +115,7 @@ const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
 
   /* Signal handler trampoline */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   .signal_handler   = up_signal_handler,
-#endif
 
   /* User-space work queue support (declared in include/nuttx/wqueue.h) */
 
diff --git a/configs/stm32l476vg-disco/knsh/defconfig b/configs/stm32l476vg-disco/knsh/defconfig
index c8f8cf349d8..ad90afdc964 100644
--- a/configs/stm32l476vg-disco/knsh/defconfig
+++ b/configs/stm32l476vg-disco/knsh/defconfig
@@ -26,7 +26,6 @@ CONFIG_BOARD_LOOPSPERMSEC=8499
 CONFIG_BUILD_PROTECTED=y
 CONFIG_DEV_LOOP=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_PROCFS=y
 CONFIG_FS_PROCFS_REGISTER=y
 CONFIG_FS_TMPFS=y
@@ -46,7 +45,7 @@ CONFIG_NSH_DISABLE_DD=y
 CONFIG_NSH_DISABLE_IFUPDOWN=y
 CONFIG_NSH_DISABLE_MKRD=y
 CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_LINELEN=64
+CONFIG_NSH_LINELEN=80
 CONFIG_NSH_READLINE=y
 CONFIG_NUTTX_USERSPACE=0x08020000
 CONFIG_PASS1_BUILDIR="configs/stm32l476vg-disco/kernel"
diff --git a/configs/stm32l476vg-disco/nsh/defconfig b/configs/stm32l476vg-disco/nsh/defconfig
index 9e58b08aed1..52988a44d15 100644
--- a/configs/stm32l476vg-disco/nsh/defconfig
+++ b/configs/stm32l476vg-disco/nsh/defconfig
@@ -25,7 +25,6 @@ CONFIG_BOARD_LOOPSPERMSEC=8499
 CONFIG_BUILTIN=y
 CONFIG_DEV_LOOP=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_ALARM=y
 CONFIG_EXAMPLES_MEDIA=y
 CONFIG_FS_PROCFS=y
@@ -48,7 +47,7 @@ CONFIG_NSH_ARCHROMFS=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_DISABLE_IFUPDOWN=y
 CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_LINELEN=64
+CONFIG_NSH_LINELEN=80
 CONFIG_NSH_READLINE=y
 CONFIG_NSH_ROMFSETC=y
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/stm32l476vg-disco/scripts/memory.ld b/configs/stm32l476vg-disco/scripts/memory.ld
index 7dbe1317eb9..3c3ba9d54b3 100644
--- a/configs/stm32l476vg-disco/scripts/memory.ld
+++ b/configs/stm32l476vg-disco/scripts/memory.ld
@@ -1,5 +1,5 @@
 /****************************************************************************
- * configs/stm32f4discovery/scripts/memory.ld
+ * configs/stm32l476vg-disco/scripts/memory.ld
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
@@ -47,14 +47,14 @@
  * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of
  * FLASH and 4Kb of SRAM.  That is an excessive amount for the kernel which
  * should fit into 64KB and, of course, can be optimized as needed (See
- * also configs/stm32f4discovery/scripts/kernel-space.ld).  Allowing the
+ * also configs/stm32l476vg-disco/scripts/kernel-space.ld).  Allowing the
  * additional does permit addition debug instrumentation to be added to the
  * kernel space without overflowing the partition.
  *
  * Alignment of the user space FLASH partition is also a critical factor:
  * The user space FLASH partition will be spanned with a single region of
  * size 2**n bytes.  The alignment of the user-space region must be the same.
- * As a consequence, as the user-space increases in size, the alignmment
+ * As a consequence, as the user-space increases in size, the alignment
  * requirement also increases.
  *
  * This alignment requirement means that the largest user space FLASH region
@@ -95,6 +95,6 @@ MEMORY
     /* 96Kb of contiguous SRAM */
 
     ksram (rwx)      : ORIGIN = 0x20000000, LENGTH = 8K
-    usram (rwx)      : ORIGIN = 0x20001000, LENGTH = 8K
-    xsram (rwx)      : ORIGIN = 0x20002000, LENGTH = 80K
+    usram (rwx)      : ORIGIN = 0x20002000, LENGTH = 8K
+    xsram (rwx)      : ORIGIN = 0x20004000, LENGTH = 80K
 }
diff --git a/configs/stm32l476vg-disco/src/stm32_spi.c b/configs/stm32l476vg-disco/src/stm32_spi.c
index 38c71247a9d..096615102b1 100644
--- a/configs/stm32l476vg-disco/src/stm32_spi.c
+++ b/configs/stm32l476vg-disco/src/stm32_spi.c
@@ -48,7 +48,7 @@
 #include 
 
 #include 
-#include 
+#include "chip.h"
 #include 
 
 #include "stm32l476vg-disco.h"
diff --git a/configs/stm32l4r9ai-disco/include/board.h b/configs/stm32l4r9ai-disco/include/board.h
index 4aecf071f70..c1c845734af 100644
--- a/configs/stm32l4r9ai-disco/include/board.h
+++ b/configs/stm32l4r9ai-disco/include/board.h
@@ -59,7 +59,7 @@
  * is we set aside more DMA channels/streams.
  */
 
-/* Values defined in arch/arm/src/stm32l4/chip/stm32l4x6xx_dma.h */
+/* Values defined in arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h */
 
 /* XXX are these used on disco? */
 
@@ -77,11 +77,14 @@
 #endif
 
 /* ADC measurements
- * Default is ADC1_IN9 (PA4) connected to STMod+ connector CN1 pin 13.
+ *
+ * Some of the choices are:
+ *   ADC1_IN9 (PA4) connected to STMod+ connector CN1 pin 13.
+ *   ADC1_IN12 (PA7) connected to Arduino A0.
  */
 
-#define ADC1_MEASURE_CHANNEL     9
-#define GPIO_MEASURE_ADC         (GPIO_ADC1_IN9)
+#define ADC1_MEASURE_CHANNEL     12
+#define GPIO_MEASURE_ADC         (GPIO_ADC1_IN12)
 
 /* Alternate function pin selections ************************************************/
 
@@ -119,7 +122,7 @@
 
 /* I2C
  *
- * The optional _GPIO configurations allow the I2C driver to manually
+ * The optional GPIO configurations allow the I2C driver to manually
  * reset the bus to clear stuck slaves.  They match the pin configuration,
  * but are normally-high GPIOs.
  *
@@ -131,24 +134,24 @@
  */
 
 #define GPIO_I2C1_SCL    (GPIO_I2C1_SCL_1|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET)
-#define GPIO_I2C1_SDA    (GPIO_I2C1_SDA_1|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET)
+#define GPIO_I2C1_SDA    (GPIO_I2C1_SDA_3|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET)
 #define GPIO_I2C1_SCL_GPIO \
    (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN6)
 #define GPIO_I2C1_SDA_GPIO \
-   (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN7)
+   (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN13)
 
 /* XXX Is I2C2 used on Disco? */
 
-#if 0
+/* I2C3 connects to Arduino Uno V3 connector pins D15 (I2C3_SCL) and D14 (I2C3_SDA). */
 
-#define GPIO_I2C2_SCL    (GPIO_I2C2_SCL_1|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET)
-#define GPIO_I2C2_SDA    (GPIO_I2C2_SDA_1|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET)
-#define GPIO_I2C2_SCL_GPIO \
-   (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10)
-#define GPIO_I2C2_SDA_GPIO \
-   (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_I2C3_SCL    (GPIO_I2C3_SCL_2|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET)
+#define GPIO_I2C3_SDA    (GPIO_I2C3_SDA_2|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET)
+#define GPIO_I2C3_SCL_GPIO \
+   (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN7)
+#define GPIO_I2C3_SDA_GPIO \
+   (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN8)
 
-#endif
+/* XXX Is I2C4 used on Disco? */
 
 /* SPI */
 
@@ -158,11 +161,35 @@
 #define GPIO_SPI1_MOSI   GPIO_SPI1_MOSI_1
 #define GPIO_SPI1_SCK    GPIO_SPI1_SCK_1
 
-/* XXX is SPI2 used on Disco? */
+/* SPI2 connects to Arduino Uno V3 connector pins D10-D13,
+ * also to DSI display.
+ */
 
-#define GPIO_SPI2_MISO   GPIO_SPI2_MISO_3
-#define GPIO_SPI2_MOSI   GPIO_SPI2_MOSI_3
-#define GPIO_SPI2_SCK    GPIO_SPI2_SCK_3
+#define GPIO_SPI2_MISO   GPIO_SPI2_MISO_1
+#define GPIO_SPI2_MOSI   GPIO_SPI2_MOSI_1
+#define GPIO_SPI2_SCK    GPIO_SPI2_SCK_1
+
+/* XXX is SPI3 used on Disco? */
+
+#if 0
+#define GPIO_SPI3_MISO   GPIO_SPI3_MISO_3
+#define GPIO_SPI3_MOSI   GPIO_SPI3_MOSI_3
+#define GPIO_SPI3_SCK    GPIO_SPI3_SCK_3
+#endif
+
+/* DFSDM1
+ *
+ * DFSDM is connected to two MEMS microphones (MP34DT01) by default.
+ *   PC2  -> CKOUT
+ *   PB12 -> DATIN1
+ *   PH2  -> MIC_VDD GPIO
+ */
+
+#define GPIO_DFSDM_DATIN1   GPIO_DFSDM_DATIN1_1
+#define GPIO_DFSDM_CKOUT    GPIO_DFSDM_CKOUT_1
+
+#define GPIO_MIC_VDD       (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | \
+                            GPIO_OUTPUT_CLEAR | GPIO_PORTH | GPIO_PIN2)
 
 /* LEDs
  *
diff --git a/configs/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h b/configs/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h
index a8e07f76350..265d1138c27 100644
--- a/configs/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h
+++ b/configs/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h
@@ -145,13 +145,20 @@
 
 /* CLK48 will come from PLLSAI1 (implicitly Q) */
 
-#define STM32L4_USE_CLK48         1
-#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG)
+#  define STM32L4_USE_CLK48       1
+#  define STM32L4_CLK48_SEL       RCC_CCIPR_CLK48SEL_PLLSAI1
+#  define STM32L4_HSI48_SYNCSRC   SYNCSRC_NONE
+#endif
 
 /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
 
 #define STM32L4_USE_LSE           1
 
+/* HSI16 used as I2C clock */
+
+#define STM32L4_I2C_USE_HSI16     1
+
 /* AHB clock (HCLK) is SYSCLK (120 MHz) */
 
 #define STM32L4_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
@@ -248,13 +255,20 @@
 
 /* Enable CLK48; get it from PLLSAI1 */
 
-#define STM32L4_USE_CLK48         1
-#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG)
+#  define STM32L4_USE_CLK48       1
+#  define STM32L4_CLK48_SEL       RCC_CCIPR_CLK48SEL_PLLSAI1
+#  define STM32L4_HSI48_SYNCSRC   SYNCSRC_NONE
+#endif
 
 /* Enable LSE (for the RTC) */
 
 #define STM32L4_USE_LSE           1
 
+/* HSI16 used as I2C clock */
+
+#define STM32L4_I2C_USE_HSI16     1
+
 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
 
 #define STM32L4_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
@@ -338,13 +352,20 @@
 
 /* Enable CLK48; get it from PLLSAI1 */
 
-#define STM32L4_USE_CLK48         1
-#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG)
+#  define STM32L4_USE_CLK48       1
+#  define STM32L4_CLK48_SEL       RCC_CCIPR_CLK48SEL_PLLSAI1
+#  define STM32L4_HSI48_SYNCSRC   SYNCSRC_NONE
+#endif
 
 /* Enable LSE (for the RTC) */
 
 #define STM32L4_USE_LSE           1
 
+/* HSI16 used as I2C clock */
+
+#define STM32L4_I2C_USE_HSI16     1
+
 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
 
 #define STM32L4_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
diff --git a/configs/stm32l4r9ai-disco/kernel/.gitignore b/configs/stm32l4r9ai-disco/kernel/.gitignore
new file mode 100644
index 00000000000..7bacd5aee3e
--- /dev/null
+++ b/configs/stm32l4r9ai-disco/kernel/.gitignore
@@ -0,0 +1,2 @@
+/nuttx_user.elf
+
diff --git a/configs/stm32l4r9ai-disco/kernel/Makefile b/configs/stm32l4r9ai-disco/kernel/Makefile
new file mode 100644
index 00000000000..103b2c60dd0
--- /dev/null
+++ b/configs/stm32l4r9ai-disco/kernel/Makefile
@@ -0,0 +1,122 @@
+############################################################################
+# configs/stm32l4r9ai-disco/kernel/Makefile
+#
+#   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt 
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+
+# This is the directory for the board-specific header files
+
+BOARD_INCLUDE = $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)include
+
+# The entry point name (if none is provided in the .config file)
+
+CONFIG_USER_ENTRYPOINT ?= user_start
+ENTRYPT = $(patsubst "%",%,$(CONFIG_USER_ENTRYPOINT))
+
+# Get the paths to the libraries and the links script path in format that
+# is appropriate for the host OS
+
+ifeq ($(WINTOOL),y)
+  # Windows-native toolchains
+  USER_LIBPATHS = ${shell for path in $(USERLIBS); do dir=`dirname $(TOPDIR)$(DELIM)$$path`;echo "-L\"`cygpath -w $$dir`\"";done}
+  USER_LDSCRIPT = -T "${shell cygpath -w $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)memory.ld}"
+  USER_LDSCRIPT += -T "${shell cygpath -w $(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)user-space.ld}"
+  USER_HEXFILE += "${shell cygpath -w $(TOPDIR)$(DELIM)nuttx_user.hex}"
+  USER_SRECFILE += "${shell cygpath -w $(TOPDIR)$(DELIM)nuttx_user.srec}"
+  USER_BINFILE += "${shell cygpath -w $(TOPDIR)$(DELIM)nuttx_user.bin}"
+else
+  # Linux/Cygwin-native toolchain
+  USER_LIBPATHS = $(addprefix -L$(TOPDIR)$(DELIM),$(dir $(USERLIBS)))
+  USER_LDSCRIPT = -T$(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)memory.ld
+  USER_LDSCRIPT += -T$(TOPDIR)$(DELIM)configs$(DELIM)$(CONFIG_ARCH_BOARD)$(DELIM)scripts$(DELIM)user-space.ld
+  USER_HEXFILE += "$(TOPDIR)$(DELIM)nuttx_user.hex"
+  USER_SRECFILE += "$(TOPDIR)$(DELIM)nuttx_user.srec"
+  USER_BINFILE += "$(TOPDIR)$(DELIM)nuttx_user.bin"
+endif
+
+USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT)
+USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS))))
+USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}"
+
+# Source files
+
+CSRCS = stm32l4_userspace.c
+COBJS = $(CSRCS:.c=$(OBJEXT))
+OBJS  = $(COBJS)
+
+# Targets:
+
+all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map
+.PHONY: nuttx_user.elf depend clean distclean
+
+$(COBJS): %$(OBJEXT): %.c
+	$(call COMPILE, $<, $@)
+
+# Create the nuttx_user.elf file containing all of the user-mode code
+
+nuttx_user.elf: $(OBJS)
+	$(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC)
+
+$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf
+	@echo "LD: nuttx_user.elf"
+	$(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf
+ifeq ($(CONFIG_INTELHEX_BINARY),y)
+	@echo "CP: nuttx_user.hex"
+	$(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE)
+endif
+ifeq ($(CONFIG_MOTOROLA_SREC),y)
+	@echo "CP: nuttx_user.srec"
+	$(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE)
+endif
+ifeq ($(CONFIG_RAW_BINARY),y)
+	@echo "CP: nuttx_user.bin"
+	$(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE)
+endif
+
+$(TOPDIR)$(DELIM)User.map: nuttx_user.elf
+	@echo "MK: User.map"
+	$(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map
+	$(Q) $(CROSSDEV)size nuttx_user.elf
+
+.depend:
+
+depend: .depend
+
+clean:
+	$(call DELFILE, nuttx_user.elf)
+	$(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*")
+	$(call DELFILE, "$(TOPDIR)$(DELIM)User.map")
+	$(call CLEAN)
+
+distclean: clean
diff --git a/configs/stm32l4r9ai-disco/kernel/stm32l4_userspace.c b/configs/stm32l4r9ai-disco/kernel/stm32l4_userspace.c
new file mode 100644
index 00000000000..3b723e1e3cf
--- /dev/null
+++ b/configs/stm32l4r9ai-disco/kernel/stm32l4_userspace.c
@@ -0,0 +1,132 @@
+/****************************************************************************
+ * configs/stm32l4r9ai-disco/kernel/stm32l4_userspace.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#ifndef CONFIG_NUTTX_USERSPACE
+#  error "CONFIG_NUTTX_USERSPACE not defined"
+#endif
+
+#if CONFIG_NUTTX_USERSPACE != 0x08020000
+#  error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld"
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* These 'addresses' of these values are setup by the linker script.  They
+ * are not actual uint32_t storage locations!  They are only used
+ * meaningfully in the following way:
+ *
+ *  - The linker script defines, for example, the symbol_sdata.
+ *  - The declaration extern uint32_t _sdata; makes C happy.  C will believe
+ *    that the value _sdata is the address of a uint32_t variable _data (it is
+ *    not!).
+ *  - We can recover the linker value then by simply taking the address of
+ *    of _data.  like:  uint32_t *pdata = &_sdata;
+ */
+
+extern uint32_t _stext;           /* Start of .text */
+extern uint32_t _etext;           /* End_1 of .text + .rodata */
+extern const uint32_t _eronly;    /* End+1 of read only section (.text + .rodata) */
+extern uint32_t _sdata;           /* Start of .data */
+extern uint32_t _edata;           /* End+1 of .data */
+extern uint32_t _sbss;            /* Start of .bss */
+extern uint32_t _ebss;            /* End+1 of .bss */
+
+/* This is the user space entry point */
+
+int CONFIG_USER_ENTRYPOINT(int argc, char *argv[]);
+
+const struct userspace_s userspace __attribute__ ((section (".userspace"))) =
+{
+  /* General memory map */
+
+  .us_entrypoint    = (main_t)CONFIG_USER_ENTRYPOINT,
+  .us_textstart     = (uintptr_t)&_stext,
+  .us_textend       = (uintptr_t)&_etext,
+  .us_datasource    = (uintptr_t)&_eronly,
+  .us_datastart     = (uintptr_t)&_sdata,
+  .us_dataend       = (uintptr_t)&_edata,
+  .us_bssstart      = (uintptr_t)&_sbss,
+  .us_bssend        = (uintptr_t)&_ebss,
+
+  /* Memory manager heap structure */
+
+  .us_heap          = &g_mmheap,
+
+  /* Task/thread startup routines */
+
+  .task_startup     = task_startup,
+#ifndef CONFIG_DISABLE_PTHREAD
+  .pthread_startup  = pthread_startup,
+#endif
+
+  /* Signal handler trampoline */
+
+  .signal_handler   = up_signal_handler,
+
+  /* User-space work queue support (declared in include/nuttx/wqueue.h) */
+
+#ifdef CONFIG_LIB_USRWORK
+  .work_usrstart    = work_usrstart,
+#endif
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */
diff --git a/configs/stm32l4r9ai-disco/knsh/Make.defs b/configs/stm32l4r9ai-disco/knsh/Make.defs
new file mode 100644
index 00000000000..f586181e7aa
--- /dev/null
+++ b/configs/stm32l4r9ai-disco/knsh/Make.defs
@@ -0,0 +1,119 @@
+############################################################################
+# configs/stm32l4r9ai-disco/knsh/Make.defs
+#
+#   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt 
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
+
+LDSCRIPT1 = memory.ld
+LDSCRIPT2 = kernel-space.ld
+
+ifeq ($(WINTOOL),y)
+  # Windows-native toolchains
+  DIRLINK = $(TOPDIR)/tools/copydir.sh
+  DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+  MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+  ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+  ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT1)}"
+  ARCHSCRIPT += -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT2)}"
+else
+  # Linux/Cygwin-native toolchain
+  MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+  ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+  ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT1)
+  ARCHSCRIPT += -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT2)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+STRIP = $(CROSSDEV)strip --strip-unneeded
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+  ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+  LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  LDFLAGS += -g
+endif
+
+#LDFLAGS += -Map=${TOPDIR}/nuttx.map
+#CFLAGS += -Wa,-adhln
+#CXXFLAGS += -Wa,-adhln
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =
diff --git a/configs/stm32l4r9ai-disco/knsh/defconfig b/configs/stm32l4r9ai-disco/knsh/defconfig
new file mode 100644
index 00000000000..1bb7c379706
--- /dev/null
+++ b/configs/stm32l4r9ai-disco/knsh/defconfig
@@ -0,0 +1,88 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_FPU is not set
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDPARMS is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="stm32l4r9ai-disco"
+CONFIG_ARCH_BOARD_STM32L4R9AI_DISCO=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CHIP_STM32L4=y
+CONFIG_ARCH_CHIP_STM32L4R9AI=y
+CONFIG_ARCH_INTERRUPTSTACK=2048
+CONFIG_ARCH_IRQBUTTONS=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARM_MPU=y
+CONFIG_BOARDCTL_IOCTL=y
+CONFIG_BOARDCTL_UNIQUEID=y
+CONFIG_BOARDCTL_UNIQUEID_SIZE=12
+CONFIG_BOARD_LOOPSPERMSEC=9234
+CONFIG_BUILD_PROTECTED=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEV_LOOP=y
+CONFIG_DEV_ZERO=y
+CONFIG_FS_PROCFS=y
+CONFIG_FS_PROCFS_REGISTER=y
+CONFIG_FS_TMPFS=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_I2C=y
+CONFIG_I2C_DRIVER=y
+CONFIG_INTELHEX_BINARY=y
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_MM_REGIONS=3
+CONFIG_MTD=y
+CONFIG_MTD_PARTITION=y
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_DISABLE_DD=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_DISABLE_MKRD=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_NUTTX_USERSPACE=0x08020000
+CONFIG_PASS1_BUILDIR="configs/stm32l4r9ai-disco/kernel"
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_PREALLOC_WDOGS=8
+CONFIG_RAM_SIZE=98304
+CONFIG_RAM_START=0x20000000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_RTC_ALARM=y
+CONFIG_RTC_DATETIME=y
+CONFIG_RTC_DRIVER=y
+CONFIG_RTC_IOCTL=y
+CONFIG_RTC_NALARMS=2
+CONFIG_SCHED_WAITPID=y
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_SPI_DRIVER=y
+CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
+CONFIG_STM32L4_I2C1=y
+CONFIG_STM32L4_I2C3=y
+CONFIG_STM32L4_PWR=y
+CONFIG_STM32L4_RNG=y
+CONFIG_STM32L4_RTC=y
+CONFIG_STM32L4_SAI1PLL=y
+CONFIG_STM32L4_SPI2=y
+CONFIG_STM32L4_SRAM2_HEAP=y
+CONFIG_STM32L4_UART4=y
+CONFIG_STM32L4_USART2=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
+CONFIG_SYS_RESERVED=8
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_UART4_BAUD=2000000
+CONFIG_UART4_RXBUFSIZE=512
+CONFIG_UART4_SERIAL_CONSOLE=y
+CONFIG_USERMAIN_STACKSIZE=3072
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_WDOG_INTRESERVE=1
diff --git a/configs/stm32l4r9ai-disco/nsh/defconfig b/configs/stm32l4r9ai-disco/nsh/defconfig
index 32caebfefdf..8c551c0e259 100644
--- a/configs/stm32l4r9ai-disco/nsh/defconfig
+++ b/configs/stm32l4r9ai-disco/nsh/defconfig
@@ -7,7 +7,6 @@
 #
 # CONFIG_ARCH_FPU is not set
 # CONFIG_NSH_ARGCAT is not set
-# CONFIG_NSH_CMDOPT_HEXDUMP is not set
 # CONFIG_NSH_CMDPARMS is not set
 CONFIG_ARCH="arm"
 CONFIG_ARCH_BOARD="stm32l4r9ai-disco"
@@ -25,15 +24,17 @@ CONFIG_BOARD_LOOPSPERMSEC=9234
 CONFIG_BUILTIN=y
 CONFIG_DEV_LOOP=y
 CONFIG_DEV_ZERO=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_ALARM=y
 CONFIG_EXAMPLES_MEDIA=y
+CONFIG_EXAMPLES_RANDOM=y
 CONFIG_FS_PROCFS=y
 CONFIG_FS_PROCFS_REGISTER=y
 CONFIG_FS_ROMFS=y
 CONFIG_FS_TMPFS=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_I2C=y
+CONFIG_I2C_DRIVER=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
@@ -47,7 +48,6 @@ CONFIG_NSH_ARCHROMFS=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_DISABLE_IFUPDOWN=y
 CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_LINELEN=64
 CONFIG_NSH_READLINE=y
 CONFIG_NSH_ROMFSETC=y
 CONFIG_PREALLOC_MQ_MSGS=4
@@ -64,12 +64,15 @@ CONFIG_RTC_IOCTL=y
 CONFIG_RTC_NALARMS=2
 CONFIG_SCHED_WAITPID=y
 CONFIG_SDCLONE_DISABLE=y
-CONFIG_SPI=y
+CONFIG_SPI_DRIVER=y
 CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
+CONFIG_STM32L4_I2C1=y
+CONFIG_STM32L4_I2C3=y
 CONFIG_STM32L4_PWR=y
 CONFIG_STM32L4_RNG=y
 CONFIG_STM32L4_RTC=y
 CONFIG_STM32L4_SAI1PLL=y
+CONFIG_STM32L4_SPI2=y
 CONFIG_STM32L4_SRAM2_HEAP=y
 CONFIG_STM32L4_UART4=y
 CONFIG_STM32L4_USART2=y
diff --git a/configs/stm32l4r9ai-disco/scripts/memory.ld b/configs/stm32l4r9ai-disco/scripts/memory.ld
index 3351176ff11..18904dc888f 100644
--- a/configs/stm32l4r9ai-disco/scripts/memory.ld
+++ b/configs/stm32l4r9ai-disco/scripts/memory.ld
@@ -46,16 +46,16 @@
  * 0x0800:0000 address range.
  *
  * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of
- * FLASH and 4Kb of SRAM.  That is an excessive amount for the kernel which
+ * FLASH and 16Kb of SRAM.  That is an excessive amount for the kernel which
  * should fit into 64KB and, of course, can be optimized as needed (See
- * also configs/stm32f4discovery/scripts/kernel-space.ld).  Allowing the
+ * also configs/stm32l4r9ai-disco/scripts/kernel-space.ld).  Allowing the
  * additional does permit addition debug instrumentation to be added to the
  * kernel space without overflowing the partition.
  *
  * Alignment of the user space FLASH partition is also a critical factor:
  * The user space FLASH partition will be spanned with a single region of
  * size 2**n bytes.  The alignment of the user-space region must be the same.
- * As a consequence, as the user-space increases in size, the alignmment
+ * As a consequence, as the user-space increases in size, the alignment
  * requirement also increases.
  *
  * This alignment requirement means that the largest user space FLASH region
@@ -63,39 +63,21 @@
  * 0x08800000.  If you change this address, don't forget to change the
  * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify
  * the check in kernel/userspace.c.
- *
- * For the same reasons, the maximum size of the SRAM mapping is limited to
- * 4KB.  Both of these alignment limitations could be reduced by using
- * multiple regions to map the FLASH/SDRAM range or perhaps with some
- * clever use of subregions.
- *
- * A detailed memory map for the 96KB SRAM region is as follows:
- *
- *   0x20000 0000:  Kernel .data region.  Typical size: 0.1KB
- *   ------- ----   Kernel .bss  region.  Typical size: 1.8KB
- *   0x20000 0800:  Kernel IDLE thread stack (approximate).  Size is
- *                  determined by CONFIG_IDLETHREAD_STACKSIZE and
- *                  adjustments for alignment.  Typical is 1KB.
- *   ------- ----   Padded to 4KB
- *   0x20000 2000:  User .data region.  Size is variable.
- *   ------- ----   User .bss region  Size is variable.
- *   0x20000 4000:  Beginning of kernel heap.  Size determined by
- *                  CONFIG_MM_KERNEL_HEAPSIZE.
- *   ------- ----   Beginning of user heap.  Can vary with other settings.
- *   0x20001 8000:  End+1 of CPU RAM
  */
 
 MEMORY
 {
-    /* 1024Kb FLASH */
+    /* 2048Kb FLASH */
 
     kflash (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
     uflash (rx)      : ORIGIN = 0x08020000, LENGTH = 128K
-    xflash (rx)      : ORIGIN = 0x08040000, LENGTH = 768K
+    xflash (rx)      : ORIGIN = 0x08040000, LENGTH = 1792K
 
-    /* 96Kb of contiguous SRAM */
+    /* 640Kb of contiguous SRAM */
 
-    ksram (rwx)      : ORIGIN = 0x20000000, LENGTH = 8K
-    usram (rwx)      : ORIGIN = 0x20001000, LENGTH = 8K
-    xsram (rwx)      : ORIGIN = 0x20002000, LENGTH = 80K
+    ksram (rwx)      : ORIGIN = 0x20000000, LENGTH = 16K
+    usram (rwx)      : ORIGIN = 0x20004000, LENGTH = 16K
+    xsram (rwx)      : ORIGIN = 0x20008000, LENGTH = 192K + 64K - 32K
+
+    sram3 (rwx)      : ORIGIN = 0x20040000, LENGTH = 384K
 }
diff --git a/configs/stm32l4r9ai-disco/src/Makefile b/configs/stm32l4r9ai-disco/src/Makefile
index 8828e6e117f..a809ba6ee01 100644
--- a/configs/stm32l4r9ai-disco/src/Makefile
+++ b/configs/stm32l4r9ai-disco/src/Makefile
@@ -36,16 +36,12 @@
 -include $(TOPDIR)/Make.defs
 
 ASRCS =
-CSRCS = stm32_boot.c stm32_spi.c
+CSRCS = stm32_boot.c
 
 ifeq ($(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG),y)
 CSRCS += stm32_clockconfig.c
 endif
 
-ifeq ($(CONFIG_STM32L4_OTGFS),y)
-CSRCS += stm32_usb.c
-endif
-
 ifeq ($(CONFIG_ARCH_LEDS),y)
 CSRCS += stm32_autoleds.c
 else
@@ -57,13 +53,26 @@ CSRCS += stm32_buttons.c
 endif
 
 ifeq ($(CONFIG_ADC),y)
+ifeq ($(CONFIG_STM32L4_ADC),y)
 CSRCS += stm32_adc.c
 endif
+ifeq ($(CONFIG_STM32L4_DFSDM),y)
+CSRCS += stm32_dfsdm.c
+endif
+endif
 
 ifeq ($(CONFIG_DAC),y)
 CSRCS += stm32_dac.c
 endif
 
+ifeq ($(CONFIG_STM32L4_SPI),y)
+CSRCS += stm32_spi.c
+endif
+
+ifeq ($(CONFIG_STM32L4_OTGFS),y)
+CSRCS += stm32_usb.c
+endif
+
 ifeq ($(CONFIG_LIB_BOARDCTL),y)
 CSRCS += stm32_appinit.c
 endif
diff --git a/configs/stm32l4r9ai-disco/src/stm32_appinit.c b/configs/stm32l4r9ai-disco/src/stm32_appinit.c
index 8feee3384c8..d84f09fbe7b 100644
--- a/configs/stm32l4r9ai-disco/src/stm32_appinit.c
+++ b/configs/stm32l4r9ai-disco/src/stm32_appinit.c
@@ -78,6 +78,15 @@
  * Private Data
  ****************************************************************************/
 
+#ifdef CONFIG_I2C
+#  ifdef CONFIG_STM32L4_I2C1
+static struct i2c_master_s* g_i2c1;
+#  endif
+#  ifdef CONFIG_STM32L4_I2C3
+static struct i2c_master_s* g_i2c3;
+#  endif
+#endif
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -156,6 +165,23 @@ int board_app_initialize(uintptr_t arg)
     }
 #endif
 
+#ifdef CONFIG_I2C
+  i2cinfo("Initializing I2C buses\n");
+#ifdef CONFIG_STM32L4_I2C1
+  g_i2c1 = stm32l4_i2cbus_initialize(1);
+#ifdef CONFIG_I2C_DRIVER
+  i2c_register(g_i2c1, 1);
+#endif
+#endif
+
+#ifdef CONFIG_STM32L4_I2C3
+  g_i2c3 = stm32l4_i2cbus_initialize(3);
+#ifdef CONFIG_I2C_DRIVER
+  i2c_register(g_i2c3, 3);
+#endif
+#endif
+#endif /* CONFIG_I2C */
+
 #ifdef HAVE_USBHOST
   /* Initialize USB host operation.  stm32l4_usbhost_initialize() starts a
    * thread that will monitor for USB connection and disconnection events.
@@ -184,7 +210,16 @@ int board_app_initialize(uintptr_t arg)
   ainfo("Initializing ADC\n");
 
   (void)stm32l4_adc_setup();
+#ifdef CONFIG_STM32L4_DFSDM
+  /* Initialize DFSDM and register its filters as additional ADC devices. */
+
+  ret = stm32_dfsdm_setup();
+  if (ret < 0)
+    {
+      aerr("ERROR: Failed to start DFSDM: %d\n", ret);
+    }
 #endif
+#endif /* CONFIG_ADC */
 
 #ifdef CONFIG_DAC
   ainfo("Initializing DAC\n");
diff --git a/configs/stm32l4r9ai-disco/src/stm32_boot.c b/configs/stm32l4r9ai-disco/src/stm32_boot.c
index 4a573add40a..125a8c68bd1 100644
--- a/configs/stm32l4r9ai-disco/src/stm32_boot.c
+++ b/configs/stm32l4r9ai-disco/src/stm32_boot.c
@@ -73,8 +73,8 @@ void stm32l4_board_initialize(void)
    * stm32_spiinitialize() has been brought into the link.
    */
 
-#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3)
-  stm32l4_spiinitialize();
+#ifdef CONFIG_STM32L4_SPI
+  stm32_spiinitialize();
 #endif
 
 #ifdef CONFIG_STM32L4_OTGFS
diff --git a/configs/stm32l4r9ai-disco/src/stm32_dfsdm.c b/configs/stm32l4r9ai-disco/src/stm32_dfsdm.c
new file mode 100644
index 00000000000..ab381fa810c
--- /dev/null
+++ b/configs/stm32l4r9ai-disco/src/stm32_dfsdm.c
@@ -0,0 +1,146 @@
+/****************************************************************************
+ * configs/stm32l4r9ai-disco/src/stm32_dfsdm.c
+ *
+ *   Copyright (C) 2019 Haltian Ltd. All rights reserved.
+ *   Authors: Juha Niskanen 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+
+#include "stm32l4_gpio.h"
+#include "stm32l4_dfsdm.h"
+#include "stm32l4r9ai-disco.h"
+
+#include 
+
+#if defined(CONFIG_ADC) && defined(CONFIG_STM32L4_DFSDM)
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_dfsdm_setup
+ ****************************************************************************/
+
+int stm32_dfsdm_setup(void)
+{
+  static bool initialized = false;
+
+  if (!initialized)
+    {
+      int ret;
+      struct adc_dev_s *adc;
+
+      ainfo("Initializing DFSDM\n");
+
+      /* TODO: just some arbitrary channels selected, missing input pin
+       * configuration and DFSDM mode selection: SPI/Manchester or internal
+       * parallel inputs (CPU/DMA/ADC).
+       */
+
+#ifdef CONFIG_STM32L4_DFSDM1_FLT0
+      adc = stm32l4_dfsdm_initialize(0, (const uint8_t[1]){0}, 1);
+      if (adc == NULL)
+        {
+          aerr("Failed to get DFSDM FLT0 interface\n");
+          return -ENODEV;
+        }
+
+      ret = adc_register("/dev/adc_flt0", adc);
+      if (ret < 0)
+        {
+          aerr("adc_register failed: %d\n", ret);
+          return ret;
+        }
+#endif
+#ifdef CONFIG_STM32L4_DFSDM1_FLT1
+      adc = stm32l4_dfsdm_initialize(1, (const uint8_t[2]){0,1}, 2);
+      if (adc == NULL)
+        {
+          aerr("Failed to get DFSDM FLT1 interface\n");
+          return -ENODEV;
+        }
+
+      ret = adc_register("/dev/adc_flt1", adc);
+      if (ret < 0)
+        {
+          aerr("adc_register failed: %d\n", ret);
+          return ret;
+        }
+#endif
+#ifdef CONFIG_STM32L4_DFSDM1_FLT2
+      adc = stm32l4_dfsdm_initialize(2, (const uint8_t[8]){0,1,2,3,4,5,6,7}, 8);
+      if (adc == NULL)
+        {
+          aerr("Failed to get DFSDM FLT2 interface\n");
+          return -ENODEV;
+        }
+
+      ret = adc_register("/dev/adc_flt2", adc);
+      if (ret < 0)
+        {
+          aerr("adc_register failed: %d\n", ret);
+          return ret;
+        }
+#endif
+#ifdef CONFIG_STM32L4_DFSDM1_FLT3
+      adc = stm32l4_dfsdm_initialize(3, (const uint8_t[4]){6,5,4,3}, 4);
+      if (adc == NULL)
+        {
+          aerr("Failed to get DFSDM FLT3 interface\n");
+          return -ENODEV;
+        }
+
+      ret = adc_register("/dev/adc_flt3", adc);
+      if (ret < 0)
+        {
+          aerr("adc_register failed: %d\n", ret);
+          return ret;
+        }
+#endif
+
+      initialized = true;
+    }
+
+  return OK;
+}
+#endif /* CONFIG_ADC && CONFIG_STM32L4_DFSDM */
diff --git a/configs/stm32l4r9ai-disco/src/stm32_spi.c b/configs/stm32l4r9ai-disco/src/stm32_spi.c
index bb62454e775..dbf3720c01c 100644
--- a/configs/stm32l4r9ai-disco/src/stm32_spi.c
+++ b/configs/stm32l4r9ai-disco/src/stm32_spi.c
@@ -45,28 +45,29 @@
 #include 
 
 #include 
+#include 
 #include 
 
 #include 
-#include 
+#include "chip.h"
 #include 
 
 #include "stm32l4r9ai-disco.h"
 
-#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3)
+#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3)
 
 /************************************************************************************
  * Public Data
  ************************************************************************************/
 /* Global driver instances */
 
-#ifdef CONFIG_STM32_SPI1
+#ifdef CONFIG_STM32L4_SPI1
 struct spi_dev_s *g_spi1;
 #endif
-#ifdef CONFIG_STM32_SPI2
+#ifdef CONFIG_STM32L4_SPI2
 struct spi_dev_s *g_spi2;
 #endif
-#ifdef CONFIG_STM32_SPI3
+#ifdef CONFIG_STM32L4_SPI3
 struct spi_dev_s *g_spi3;
 #endif
 
@@ -84,53 +85,62 @@ struct spi_dev_s *g_spi3;
 
 void weak_function stm32_spiinitialize(void)
 {
-#ifdef CONFIG_STM32_SPI1
+#ifdef CONFIG_STM32L4_SPI1
   /* Configure SPI-based devices on SPI1 */
 
-  g_spi1 = up_spiinitialize(1);
+  g_spi1 = stm32l4_spibus_initialize(1);
   if (!g_spi1)
     {
       spierr("ERROR: [boot] FAILED to initialize SPI port 1\n");
     }
+#ifdef CONFIG_SPI_DRIVER
+  spi_register(g_spi1, 1);
+#endif
 
 #ifdef HAVE_MMCSD
-  stm32_configgpio(GPIO_SPI_CS_SD_CARD);
+  stm32l4_configgpio(GPIO_SPI_CS_SD_CARD);
 #endif
 #endif
 
-#ifdef CONFIG_STM32_SPI2
+#ifdef CONFIG_STM32L4_SPI2
   /* Configure SPI-based devices on SPI2 */
 
-  g_spi2 = up_spiinitialize(2);
+  g_spi2 = stm32l4_spibus_initialize(2);
   if (!g_spi2)
     {
       spierr("ERROR: [boot] FAILED to initialize SPI port 2\n");
     }
+#ifdef CONFIG_SPI_DRIVER
+  spi_register(g_spi2, 2);
+#endif
 
 #warning No devices specified on SPI2
 #endif
 
-#ifdef CONFIG_STM32_SPI2
+#ifdef CONFIG_STM32L4_SPI3
   /* Configure SPI-based devices on SPI3 */
 
-  g_spi2 = up_spiinitialize(3);
-  if (!g_spi2)
+  g_spi3 = stm32l4_spibus_initialize(3);
+  if (!g_spi3)
     {
       spierr("ERROR: [boot] FAILED to initialize SPI port 3\n");
     }
+#ifdef CONFIG_SPI_DRIVER
+  spi_register(g_spi3, 3);
+#endif
 
 #warning No devices specified on SPI3
 #endif
 }
 
 /****************************************************************************
- * Name:  stm32_spi1/2/3select and stm32_spi1/2/3status
+ * Name:  stm32l4_spi1/2/3select and stm32l4_spi1/2/3status
  *
  * Description:
  *   The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be
  *   provided by board-specific logic.  They are implementations of the select
  *   and status methods of the SPI interface defined by struct spi_ops_s (see
- *   include/nuttx/spi/spi.h). All other methods (including up_spiinitialize())
+ *   include/nuttx/spi/spi.h). All other methods (including stm32l4_spibus_initialize())
  *   are provided by common STM32 logic.  To use this common SPI logic on your
  *   board:
  *
@@ -139,60 +149,60 @@ void weak_function stm32_spiinitialize(void)
  *   2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your
  *      board-specific logic.  These functions will perform chip selection and
  *      status operations using GPIOs in the way your board is configured.
- *   3. Add a calls to up_spiinitialize() in your low level application
+ *   3. Add a calls to stm32l4_spibus_initialize() in your low level application
  *      initialization logic
- *   4. The handle returned by up_spiinitialize() may then be used to bind the
+ *   4. The handle returned by stm32l4_spibus_initialize() may then be used to bind the
  *      SPI driver to higher level logic (e.g., calling
  *      mmcsd_spislotinitialize(), for example, will bind the SPI driver to
  *      the SPI MMC/SD driver).
  *
  ****************************************************************************/
 
-#ifdef CONFIG_STM32_SPI1
-void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
+#ifdef CONFIG_STM32L4_SPI1
+void stm32l4_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
 {
   spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
 
 #ifdef HAVE_MMCSD
   if (devid == SPIDEV_MMCSD(0))
     {
-      stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected);
+      stm32l4_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected);
     }
 #endif
 }
 
-uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
+uint8_t stm32l4_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
 {
   return 0;
 }
 #endif
 
-#ifdef CONFIG_STM32_SPI2
-void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
+#ifdef CONFIG_STM32L4_SPI2
+void stm32l4_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
 {
   spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
 }
 
-uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid)
+uint8_t stm32l4_spi2status(FAR struct spi_dev_s *dev, uint32_t devid)
 {
   return 0;
 }
 #endif
 
-#ifdef CONFIG_STM32_SPI3
-void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
+#ifdef CONFIG_STM32L4_SPI3
+void stm32l4_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
 
   spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
 }
 
-uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid)
+uint8_t stm32l4_spi3status(FAR struct spi_dev_s *dev, uint32_t devid)
 {
   return 0;
 }
 #endif
 
 /****************************************************************************
- * Name: stm32_spi1cmddata
+ * Name: stm32l4_spi1/2/3cmddata
  *
  * Description:
  *   Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true)
@@ -215,26 +225,26 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid)
  ****************************************************************************/
 
 #ifdef CONFIG_SPI_CMDDATA
-#ifdef CONFIG_STM32_SPI1
-int stm32_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
+#ifdef CONFIG_STM32L4_SPI1
+int stm32l4_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
 {
   return OK;
 }
 #endif
 
-#ifdef CONFIG_STM32_SPI2
-int stm32_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
+#ifdef CONFIG_STM32L4_SPI2
+int stm32l4_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
 {
   return OK;
 }
 #endif
 
-#ifdef CONFIG_STM32_SPI3
-int stm32_spi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
+#ifdef CONFIG_STM32L4_SPI3
+int stm32l4_spi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
 {
   return OK;
 }
 #endif
 #endif /* CONFIG_SPI_CMDDATA */
 
-#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */
+#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */
diff --git a/configs/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h b/configs/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h
index 20ab622e0cb..1d9dec3d2a1 100644
--- a/configs/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h
+++ b/configs/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h
@@ -190,10 +190,10 @@
 
 /* Global driver instances */
 
-#ifdef CONFIG_STM32_SPI1
+#ifdef CONFIG_STM32L4_SPI1
 extern struct spi_dev_s *g_spi1;
 #endif
-#ifdef CONFIG_STM32_SPI2
+#ifdef CONFIG_STM32L4_SPI2
 extern struct spi_dev_s *g_spi2;
 #endif
 
@@ -231,6 +231,18 @@ int stm32l4_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, uint32_t *ve
 
 int stm32l4_dac_setup(void);
 
+/************************************************************************************
+ * Name: stm32_dfsdm_setup
+ *
+ * Description:
+ *   Initialize DFSDM and register the ADC drivers for DFSDM filters.
+ *
+ ************************************************************************************/
+
+#if defined(CONFIG_ADC) && defined(CONFIG_STM32L4_DFSDM)
+int stm32_dfsdm_setup(void);
+#endif
+
 /************************************************************************************
  * Name: stm32_spiinitialize
  *
diff --git a/configs/stm32ldiscovery/nsh/defconfig b/configs/stm32ldiscovery/nsh/defconfig
index b405c87b8fb..df07c8941ed 100644
--- a/configs/stm32ldiscovery/nsh/defconfig
+++ b/configs/stm32ldiscovery/nsh/defconfig
@@ -23,7 +23,6 @@ CONFIG_BOARD_LOOPSPERMSEC=2796
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_MAX_TASKS=8
diff --git a/configs/stm32ldiscovery/src/Makefile b/configs/stm32ldiscovery/src/Makefile
index 0bfb618418d..41f069ac701 100644
--- a/configs/stm32ldiscovery/src/Makefile
+++ b/configs/stm32ldiscovery/src/Makefile
@@ -36,7 +36,7 @@
 -include $(TOPDIR)/Make.defs
 
 ASRCS =
-CSRCS = stm32_boot.c stm32_spi.c
+CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c
 
 ifeq ($(CONFIG_ARCH_LEDS),y)
 CSRCS += stm32_autoleds.c
diff --git a/configs/stm32ldiscovery/src/stm32_appinit.c b/configs/stm32ldiscovery/src/stm32_appinit.c
index 394caf5bc75..b580dc334eb 100644
--- a/configs/stm32ldiscovery/src/stm32_appinit.c
+++ b/configs/stm32ldiscovery/src/stm32_appinit.c
@@ -1,8 +1,7 @@
 /****************************************************************************
  * config/stm32ldiscovery/src/stm32_appinit.c
- * arch/arm/src/board/stm32_appinit.c
  *
- *   Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013, 2016, 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -63,7 +62,7 @@
  *   arg - The boardctl() argument is passed to the board_app_initialize()
  *         implementation without modification.  The argument has no
  *         meaning to NuttX; the meaning of the argument is a contract
- *         between the board-specific initalization logic and the
+ *         between the board-specific initialization logic and the
  *         matching application logic.  The value cold be such things as a
  *         mode enumeration value, a set of DIP switch switch settings, a
  *         pointer to configuration data read from a file or serial FLASH,
@@ -78,40 +77,7 @@
 
 int board_app_initialize(uintptr_t arg)
 {
-  int ret = OK;
+  /* Perform board initialization here */
 
-#ifdef CONFIG_STM32_LCD
-  /* Initialize the SLCD and register the SLCD device as /dev/slcd0 */
-
-  ret = stm32_slcd_initialize();
-  if (ret != OK)
-    {
-      syslog(LOG_ERR, "ERROR: stm32_slcd_initialize failed: %d\n", ret);
-      return ret;
-    }
-#endif
-
-#ifdef CONFIG_PWM
-  /* Initialize PWM and register the PWM device. */
-
-  ret = stm32_pwm_setup();
-  if (ret < 0)
-    {
-      syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret);
-    }
-#endif
-
-#ifdef CONFIG_SENSORS_QENCODER
-  /* Initialize and register the qencoder driver */
-
-  ret = stm32_qencoder_initialize("/dev/qe0", CONFIG_STM32LDISCO_QETIMER);
-  if (ret != OK)
-    {
-      syslog(LOG_ERR,
-             "ERROR: Failed to register the qencoder: %d\n",
-             ret);
-    }
-#endif
-
-  return ret;
+  return stm32_bringup();
 }
diff --git a/configs/stm32ldiscovery/src/stm32_boot.c b/configs/stm32ldiscovery/src/stm32_boot.c
index df34cb340a2..eab817f265e 100644
--- a/configs/stm32ldiscovery/src/stm32_boot.c
+++ b/configs/stm32ldiscovery/src/stm32_boot.c
@@ -1,7 +1,7 @@
 /************************************************************************************
  * configs/stm32ldiscovery/src/stm32_boot.c
  *
- *   Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013, 2015, 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -88,3 +88,27 @@ void stm32_boardinitialize(void)
   board_autoled_initialize();
 #endif
 }
+
+/************************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ *   If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional initialization call
+ *   will be performed in the boot-up sequence to a function called
+ *   board_late_initialize().  board_late_initialize() will be called immediately after
+ *   up_initialize() is called and just before the initial application is started.
+ *   This additional initialization phase may be used, for example, to initialize
+ *   board-specific device drivers.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+#ifndef CONFIG_LIB_BOARDCTL
+  /* Perform board initialization here instead of from the board_app_initialize(). */
+
+  (void)stm32_bringup();
+#endif
+}
+#endif
diff --git a/configs/stm32ldiscovery/src/stm32_bringup.c b/configs/stm32ldiscovery/src/stm32_bringup.c
new file mode 100644
index 00000000000..fc2d5b8bf61
--- /dev/null
+++ b/configs/stm32ldiscovery/src/stm32_bringup.c
@@ -0,0 +1,105 @@
+/****************************************************************************
+ * config/stm32ldiscovery/src/stm32_bringup.c
+ *
+ *   Copyright (C) 2013, 2016, 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include 
+#include 
+
+#include "stm32ldiscovery.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=y :
+ *     Called from board_late_initialize().
+ *
+ *   CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
+ *     Called from the NSH library
+ *
+ ****************************************************************************/
+
+int stm32_bringup(void)
+{
+  int ret = OK;
+
+#ifdef CONFIG_STM32_LCD
+  /* Initialize the SLCD and register the SLCD device as /dev/slcd0 */
+
+  ret = stm32_slcd_initialize();
+  if (ret != OK)
+    {
+      syslog(LOG_ERR, "ERROR: stm32_slcd_initialize failed: %d\n", ret);
+      return ret;
+    }
+#endif
+
+#ifdef CONFIG_PWM
+  /* Initialize PWM and register the PWM device. */
+
+  ret = stm32_pwm_setup();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret);
+    }
+#endif
+
+#ifdef CONFIG_SENSORS_QENCODER
+  /* Initialize and register the qencoder driver */
+
+  ret = stm32_qencoder_initialize("/dev/qe0", CONFIG_STM32LDISCO_QETIMER);
+  if (ret != OK)
+    {
+      syslog(LOG_ERR,
+             "ERROR: Failed to register the qencoder: %d\n",
+             ret);
+    }
+#endif
+
+  return ret;
+}
diff --git a/configs/stm32ldiscovery/src/stm32_lcd.c b/configs/stm32ldiscovery/src/stm32_lcd.c
index dd96b9dcafe..5ebffb35512 100644
--- a/configs/stm32ldiscovery/src/stm32_lcd.c
+++ b/configs/stm32ldiscovery/src/stm32_lcd.c
@@ -65,7 +65,7 @@
 #include "up_arch.h"
 #include "stm32_gpio.h"
 #include "stm32_rcc.h"
-#include "chip/stm32_lcd.h"
+#include "hardware/stm32_lcd.h"
 
 #include "stm32ldiscovery.h"
 
@@ -302,9 +302,7 @@ static void slcd_action(enum slcdcode_e code, uint8_t count);
 static ssize_t slcd_read(FAR struct file *, FAR char *, size_t);
 static ssize_t slcd_write(FAR struct file *, FAR const char *, size_t);
 static int slcd_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int slcd_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -319,10 +317,8 @@ static const struct file_operations g_slcdops =
   slcd_read,     /* read */
   slcd_write,    /* write */
   0,             /* seek */
-  slcd_ioctl     /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , slcd_poll    /* poll */
-#endif
+  slcd_ioctl,    /* ioctl */
+  slcd_poll      /* poll */
 };
 
 /* LCD state data */
@@ -1434,7 +1430,6 @@ static int slcd_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: slcd_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int slcd_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup)
 {
@@ -1451,7 +1446,6 @@ static int slcd_poll(FAR struct file *filep, FAR struct pollfd *fds,
 
   return OK;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/configs/stm32ldiscovery/src/stm32ldiscovery.h b/configs/stm32ldiscovery/src/stm32ldiscovery.h
index 161e3c6401e..69ee6afa5c5 100644
--- a/configs/stm32ldiscovery/src/stm32ldiscovery.h
+++ b/configs/stm32ldiscovery/src/stm32ldiscovery.h
@@ -233,6 +233,26 @@
  * Public Functions
  ****************************************************************************************************/
 
+/****************************************************************************
+ * Name: stm32_bringup
+ *
+ * Description:
+ *   Perform architecture specific initialization
+ *
+ *   CONFIG_LIB_BOARDCTL=y:
+ *     If CONFIG_NSH_ARCHINITIALIZE=y:
+ *       Called from the NSH library (or other application)
+ *     Otherwise, assumed to be called from some other application.
+ *
+ *   Otherwise CONFIG_BOARD_LATE_INITIALIZE=y:
+ *     Called from board_late_initialize().
+ *
+ *   Otherise, bad news:  Never called
+ *
+ ****************************************************************************/
+
+int stm32_bringup(void);
+
 /****************************************************************************************************
  * Name: stm32_spidev_initialize
  *
diff --git a/configs/stm32vldiscovery/nsh/defconfig b/configs/stm32vldiscovery/nsh/defconfig
index 69163678d95..c9ef28bd1f2 100644
--- a/configs/stm32vldiscovery/nsh/defconfig
+++ b/configs/stm32vldiscovery/nsh/defconfig
@@ -31,7 +31,6 @@ CONFIG_BUILTIN=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEFAULT_SMALL=y
-CONFIG_DISABLE_POLL=y
 CONFIG_IDLETHREAD_STACKSIZE=128
 CONFIG_INTELHEX_BINARY=y
 CONFIG_MAX_TASKS=4
diff --git a/configs/sure-pic32mx/nsh/defconfig b/configs/sure-pic32mx/nsh/defconfig
index e906e66a022..ae19f352e23 100644
--- a/configs/sure-pic32mx/nsh/defconfig
+++ b/configs/sure-pic32mx/nsh/defconfig
@@ -18,7 +18,6 @@ CONFIG_ARCH_MIPS=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=5580
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/sure-pic32mx/src/pic32mx_lcd1602.c b/configs/sure-pic32mx/src/pic32mx_lcd1602.c
index 35a05eade6f..02ff207fd90 100644
--- a/configs/sure-pic32mx/src/pic32mx_lcd1602.c
+++ b/configs/sure-pic32mx/src/pic32mx_lcd1602.c
@@ -184,9 +184,7 @@ static void lcd_action(enum slcdcode_e code, uint8_t count);
 static ssize_t lcd_read(FAR struct file *, FAR char *, size_t);
 static ssize_t lcd_write(FAR struct file *, FAR const char *, size_t);
 static int lcd_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int lcd_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -201,10 +199,8 @@ static const struct file_operations g_lcdops =
   lcd_read,      /* read */
   lcd_write,     /* write */
   0,             /* seek */
-  lcd_ioctl      /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , lcd_poll     /* poll */
-#endif
+  lcd_ioctl,     /* ioctl */
+  lcd_poll       /* poll */
 };
 
 /* This is the driver state structure */
@@ -1016,7 +1012,6 @@ static int lcd_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: lcd_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int lcd_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup)
 {
@@ -1032,7 +1027,6 @@ static int lcd_poll(FAR struct file *filep, FAR struct pollfd *fds,
     }
   return OK;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/configs/sure-pic32mx/usbnsh/defconfig b/configs/sure-pic32mx/usbnsh/defconfig
index 1f24a0db91f..a9bacb2466c 100644
--- a/configs/sure-pic32mx/usbnsh/defconfig
+++ b/configs/sure-pic32mx/usbnsh/defconfig
@@ -24,7 +24,6 @@ CONFIG_CDCACM=y
 CONFIG_CDCACM_CONSOLE=y
 CONFIG_CDCACM_RXBUFSIZE=256
 CONFIG_CDCACM_TXBUFSIZE=256
-CONFIG_DISABLE_POLL=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/teensy-2.0/hello/defconfig b/configs/teensy-2.0/hello/defconfig
index ef6301a5cef..e3fda2193e5 100644
--- a/configs/teensy-2.0/hello/defconfig
+++ b/configs/teensy-2.0/hello/defconfig
@@ -19,9 +19,7 @@ CONFIG_DEFAULT_SMALL=y
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_EXAMPLES_HELLO=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_IDLETHREAD_STACKSIZE=512
diff --git a/configs/teensy-2.0/nsh/defconfig b/configs/teensy-2.0/nsh/defconfig
index ad4a0f5590e..1fd3906492b 100644
--- a/configs/teensy-2.0/nsh/defconfig
+++ b/configs/teensy-2.0/nsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_BOARD_LOOPSPERMSEC=864
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_IDLETHREAD_STACKSIZE=512
diff --git a/configs/teensy-2.0/usbmsc/defconfig b/configs/teensy-2.0/usbmsc/defconfig
index d982bbcfe14..f04f47b0374 100644
--- a/configs/teensy-2.0/usbmsc/defconfig
+++ b/configs/teensy-2.0/usbmsc/defconfig
@@ -21,7 +21,6 @@ CONFIG_BOARD_LOOPSPERMSEC=864
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_IDLETHREAD_STACKSIZE=512
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/teensy-3.x/nsh/defconfig b/configs/teensy-3.x/nsh/defconfig
index 576437c1da4..9d0b8d19c9a 100644
--- a/configs/teensy-3.x/nsh/defconfig
+++ b/configs/teensy-3.x/nsh/defconfig
@@ -22,7 +22,6 @@ CONFIG_BOARD_LOOPSPERMSEC=6024
 CONFIG_BUILTIN=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_KINETIS_SERIALBRK_BSDCOMPAT=y
diff --git a/configs/teensy-3.x/src/k20_usbdev.c b/configs/teensy-3.x/src/k20_usbdev.c
index f5f20fbf246..a8382c7f776 100644
--- a/configs/teensy-3.x/src/k20_usbdev.c
+++ b/configs/teensy-3.x/src/k20_usbdev.c
@@ -50,7 +50,7 @@
 #include "up_arch.h"
 #include "kinetis.h"
 #include "kinetis_usbotg.h"
-#include "chip/kinetis_sim.h"
+#include "hardware/kinetis_sim.h"
 #include "teensy-3x.h"
 
 /************************************************************************************
diff --git a/configs/teensy-3.x/usbnsh/defconfig b/configs/teensy-3.x/usbnsh/defconfig
index 3e109353703..0b8510ac789 100644
--- a/configs/teensy-3.x/usbnsh/defconfig
+++ b/configs/teensy-3.x/usbnsh/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=6024
 CONFIG_BUILTIN=y
 CONFIG_CDCACM=y
-CONFIG_DISABLE_POLL=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_KINETIS_SERIALBRK_BSDCOMPAT=y
 CONFIG_KINETIS_UART0=y
diff --git a/configs/teensy-lc/nsh/defconfig b/configs/teensy-lc/nsh/defconfig
index 27792ac8139..caa4ce3f216 100644
--- a/configs/teensy-lc/nsh/defconfig
+++ b/configs/teensy-lc/nsh/defconfig
@@ -28,7 +28,6 @@ CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_HAVE_CXX=y
 CONFIG_HAVE_CXXINITIALIZE=y
 CONFIG_INTELHEX_BINARY=y
diff --git a/configs/teensy-lc/src/kl_boardinitialize.c b/configs/teensy-lc/src/kl_boardinitialize.c
index b4c23d63833..1f1cf656176 100644
--- a/configs/teensy-lc/src/kl_boardinitialize.c
+++ b/configs/teensy-lc/src/kl_boardinitialize.c
@@ -45,7 +45,7 @@
 #include 
 #include "chip.h"
 #include "kl_gpio.h"
-#include "chip/kl_pinmux.h"
+#include "hardware/kl_pinmux.h"
 
 #include "up_arch.h"
 #include "teensy-lc.h"
diff --git a/configs/tm4c123g-launchpad/nsh/defconfig b/configs/tm4c123g-launchpad/nsh/defconfig
index c00b76a6b0d..c379addfc34 100644
--- a/configs/tm4c123g-launchpad/nsh/defconfig
+++ b/configs/tm4c123g-launchpad/nsh/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=4531
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_NFILE_DESCRIPTORS=8
diff --git a/configs/tm4c1294-launchpad/ipv6/defconfig b/configs/tm4c1294-launchpad/ipv6/defconfig
index 791da698ecd..4a6c8c4c294 100644
--- a/configs/tm4c1294-launchpad/ipv6/defconfig
+++ b/configs/tm4c1294-launchpad/ipv6/defconfig
@@ -28,6 +28,10 @@ CONFIG_LIBM=y
 CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_NET=y
+CONFIG_NETINIT_IPv6NETMASK_4=0x0000
+CONFIG_NETINIT_IPv6NETMASK_8=0xff80
+CONFIG_NETINIT_MONITOR=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_ETH_PKTSIZE=590
 CONFIG_NET_ICMPv6=y
@@ -45,11 +49,7 @@ CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_IPv6NETMASK_4=0x0000
-CONFIG_NSH_IPv6NETMASK_8=0xff80
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETINIT_MONITOR=y
-CONFIG_NSH_NETINIT_THREAD=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/tm4c1294-launchpad/nsh/defconfig b/configs/tm4c1294-launchpad/nsh/defconfig
index a8df042fabd..80f94b7b721 100644
--- a/configs/tm4c1294-launchpad/nsh/defconfig
+++ b/configs/tm4c1294-launchpad/nsh/defconfig
@@ -28,6 +28,8 @@ CONFIG_MAX_WDOGPARMS=2
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_MONITOR=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
 CONFIG_NETUTILS_WEBCLIENT=y
@@ -36,7 +38,6 @@ CONFIG_NET_ARP_SEND=y
 CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_SOLINGER=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
@@ -49,8 +50,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NETINIT_MONITOR=y
-CONFIG_NSH_NETINIT_THREAD=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/tm4c1294-launchpad/scripts/ld.script b/configs/tm4c1294-launchpad/scripts/ld.script
index 5b8232a2981..bf43e00efdb 100644
--- a/configs/tm4c1294-launchpad/scripts/ld.script
+++ b/configs/tm4c1294-launchpad/scripts/ld.script
@@ -49,68 +49,72 @@ ENTRY(_stext)
 
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
+        /* Stabs debugging sections. */
 
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/tms570ls31x-usb-kit/nsh/defconfig b/configs/tms570ls31x-usb-kit/nsh/defconfig
index 22e8728ce49..237942f9c22 100644
--- a/configs/tms570ls31x-usb-kit/nsh/defconfig
+++ b/configs/tms570ls31x-usb-kit/nsh/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_LOWVECTORS=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARCH="arm"
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_ELF=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_FAT_LCNAMES=y
diff --git a/configs/twr-k60n512/nsh/defconfig b/configs/twr-k60n512/nsh/defconfig
index d06ae5246ef..42e072a80ad 100644
--- a/configs/twr-k60n512/nsh/defconfig
+++ b/configs/twr-k60n512/nsh/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_STACKDUMP=y
 CONFIG_ARMV7M_OABI_TOOLCHAIN=y
 CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
 CONFIG_BOARD_LOOPSPERMSEC=9535
-CONFIG_DISABLE_POLL=y
 CONFIG_FS_FAT=y
 CONFIG_INTELHEX_BINARY=y
 CONFIG_KINETIS_UART3=y
diff --git a/configs/twr-k64f120m/README.txt b/configs/twr-k64f120m/README.txt
index fe9ed6e5830..8d8f54cd309 100644
--- a/configs/twr-k64f120m/README.txt
+++ b/configs/twr-k64f120m/README.txt
@@ -365,8 +365,7 @@ Networking Support
         CONFIG_ARCH_PHY_INTERRUPT in the board configuration file to
         advertise that it supports arch_phy_irq().
 
-        And a few other things: UDP support is required (CONFIG_NET_UDP) and
-        signals must not be disabled (CONFIG_DISABLE_SIGNALS).
+        One other thing: UDP support is required (CONFIG_NET_UDP).
 
   Given those prerequisites, the network monitor can be selected with these
   additional settings.
diff --git a/configs/twr-k64f120m/netnsh/defconfig b/configs/twr-k64f120m/netnsh/defconfig
index 87fee1710c8..8ba8c7d8128 100644
--- a/configs/twr-k64f120m/netnsh/defconfig
+++ b/configs/twr-k64f120m/netnsh/defconfig
@@ -30,6 +30,8 @@ CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_MMCSD=y
 CONFIG_MMCSD_SDIO=y
+CONFIG_NETINIT_DRIPADDR=0xc0a800fe
+CONFIG_NETINIT_IPADDR=0xc0a800e9
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NET_ARP_IPIN=y
 CONFIG_NET_ARP_SEND=y
@@ -43,9 +45,7 @@ CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_DISABLE_IFUPDOWN=y
-CONFIG_NSH_DRIPADDR=0xc0a800fe
 CONFIG_NSH_FILEIOSIZE=512
-CONFIG_NSH_IPADDR=0xc0a800e9
 CONFIG_NSH_LINELEN=64
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/twr-k64f120m/nsh/defconfig b/configs/twr-k64f120m/nsh/defconfig
index 9b9c70bd6be..bd8508fc052 100644
--- a/configs/twr-k64f120m/nsh/defconfig
+++ b/configs/twr-k64f120m/nsh/defconfig
@@ -14,7 +14,6 @@ CONFIG_ARCH_CHIP_KINETIS=y
 CONFIG_ARCH_CHIP_MK64FN1M0VMD12=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=9535
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_AUTOMOUNTER=y
 CONFIG_FS_FAT=y
diff --git a/configs/twr-k64f120m/scripts/ld.script b/configs/twr-k64f120m/scripts/ld.script
index e9dc2d42d1e..574c1da1cd1 100644
--- a/configs/twr-k64f120m/scripts/ld.script
+++ b/configs/twr-k64f120m/scripts/ld.script
@@ -48,10 +48,10 @@
 
 MEMORY
 {
-	vectflash (rx)  : ORIGIN = 0x00000000, LENGTH = 1K
-	cfmprotect (rx) : ORIGIN = 0x00000400, LENGTH = 16
-	progflash (rx)  : ORIGIN = 0x00000800, LENGTH = 1M - 2K
-	datasram (rwx)  : ORIGIN = 0x1fff0000, LENGTH = 256K
+        vectflash (rx)  : ORIGIN = 0x00000000, LENGTH = 1K
+        cfmprotect (rx) : ORIGIN = 0x00000400, LENGTH = 16
+        progflash (rx)  : ORIGIN = 0x00000800, LENGTH = 1M - 2K
+        datasram (rwx)  : ORIGIN = 0x1fff0000, LENGTH = 256K
 }
 
 OUTPUT_ARCH(arm)
@@ -60,84 +60,88 @@ ENTRY(_stext)
 EXTERN(__flashconfigbytes)
 SECTIONS
 {
-	.vectors : {
-		_svectors = ABSOLUTE(.);
-		*(.vectors)
-		_evectors = ABSOLUTE(.);
-	} > vectflash
+        .vectors : {
+                _svectors = ABSOLUTE(.);
+                *(.vectors)
+                _evectors = ABSOLUTE(.);
+        } > vectflash
 
-	.cfmprotect : {
-		KEEP(*(.cfmconfig))
-	} > cfmprotect
+        .cfmprotect : {
+                KEEP(*(.cfmconfig))
+        } > cfmprotect
 
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > progflash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > progflash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > progflash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > progflash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > progflash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > progflash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > progflash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > progflash
+        __exidx_end = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > datasram AT > progflash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > datasram AT > progflash
 
-	_eronly = LOADADDR(.data);
+        _eronly = LOADADDR(.data);
 
-	.ramfunc ALIGN(4): {
-		_sramfuncs = ABSOLUTE(.);
-		*(.ramfunc  .ramfunc.*)
-		_eramfuncs = ABSOLUTE(.);
-	} > datasram AT > progflash
+        .ramfunc ALIGN(4): {
+                _sramfuncs = ABSOLUTE(.);
+                *(.ramfunc  .ramfunc.*)
+                _eramfuncs = ABSOLUTE(.);
+        } > datasram AT > progflash
 
-	_framfuncs = LOADADDR(.ramfunc);
+        _framfuncs = LOADADDR(.ramfunc);
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > datasram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > datasram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/u-blox-c027/nsh/defconfig b/configs/u-blox-c027/nsh/defconfig
index 208a95184d9..47680775eff 100644
--- a/configs/u-blox-c027/nsh/defconfig
+++ b/configs/u-blox-c027/nsh/defconfig
@@ -59,6 +59,12 @@ CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
 CONFIG_NETDEV_LATEINIT=y
+CONFIG_NETINIT_DHCPC=y
+CONFIG_NETINIT_DRIPADDR=0xc0a80101
+CONFIG_NETINIT_MACADDR_1=0x55add7e5
+CONFIG_NETINIT_MACADDR_2=0xbada
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_PPPD_PAP=y
 CONFIG_NETUTILS_TELNETD=y
@@ -69,7 +75,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=8
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_STATISTICS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCPBACKLOG=y
@@ -80,12 +85,7 @@ CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
-CONFIG_NSH_DHCPC=y
-CONFIG_NSH_DRIPADDR=0xc0a80101
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_MACADDR=0xbada55add7e5
-CONFIG_NSH_NETINIT_THREAD=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSH_STRERROR=y
 CONFIG_NSH_TELNET_LOGIN=y
diff --git a/configs/ubw32/nsh/defconfig b/configs/ubw32/nsh/defconfig
index 480db1b85dc..af760c32909 100644
--- a/configs/ubw32/nsh/defconfig
+++ b/configs/ubw32/nsh/defconfig
@@ -20,7 +20,6 @@ CONFIG_ARCH_MIPS=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=8079
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/us7032evb1/nsh/defconfig b/configs/us7032evb1/nsh/defconfig
index 5e60bcfb909..e326a8625a9 100644
--- a/configs/us7032evb1/nsh/defconfig
+++ b/configs/us7032evb1/nsh/defconfig
@@ -17,10 +17,8 @@ CONFIG_ARCH="renesas"
 CONFIG_BOARD_LOOPSPERMSEC=572
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_ENDIAN_BIG=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_MAX_TASKS=8
diff --git a/configs/us7032evb1/ostest/defconfig b/configs/us7032evb1/ostest/defconfig
index 7315b475e20..bc9d077fdf6 100644
--- a/configs/us7032evb1/ostest/defconfig
+++ b/configs/us7032evb1/ostest/defconfig
@@ -17,7 +17,6 @@ CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_ENVIRON=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_POSIX_TIMERS=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_ENDIAN_BIG=y
diff --git a/configs/us7032evb1/ostest/ld.script b/configs/us7032evb1/ostest/ld.script
index 36c9b0d9a8d..a6d85c050f2 100644
--- a/configs/us7032evb1/ostest/ld.script
+++ b/configs/us7032evb1/ostest/ld.script
@@ -37,55 +37,56 @@ OUTPUT_ARCH(sh)
 ENTRY(_stext)
 SECTIONS
 {
-	/* The us7032evb1 has CMON in PROM beginning at address 0x00000000 and
-	 * either 64Kb or 256Kb of SRAM beginning at 0x0a000000.  Neither the
-	 * PROM nor the first 8Kb of SRAM are avaible to the devoleper as these
-	 * are used by CMON.  The next 1Kb of SRAM is dedicated to relocated
-	 * interrupt vectors.
-	 */
+        /* The us7032evb1 has CMON in PROM beginning at address 0x00000000 and
+         * either 64Kb or 256Kb of SRAM beginning at 0x0a000000.  Neither the
+         * PROM nor the first 8Kb of SRAM are avaible to the devoleper as these
+         * are used by CMON.  The next 1Kb of SRAM is dedicated to relocated
+         * interrupt vectors.
+         */
 
-	. = 0x0a002000;
-	.text : {
-		_svect = ABSOLUTE(.);
-		*(.vects);		/* Relocated interrupt vectors	*/
-		_evect = ABSOLUTE(.);
-		_stext = ABSOLUTE(.);
-		*(.reset)		/* Reset/IRQ code		*/
-		*(.text)		/* Code				*/
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata)		/* Read-only data		*/
-		*(.rodata.str1.4)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)			/* Global offset table		*/
-		_etext = ABSOLUTE(.);
-	}
+        . = 0x0a002000;
+        .text : {
+                _svect = ABSOLUTE(.);
+                *(.vects);              /* Relocated interrupt vectors  */
+                _evect = ABSOLUTE(.);
+                _stext = ABSOLUTE(.);
+                *(.reset)               /* Reset/IRQ code               */
+                *(.text)                /* Code                         */
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata)              /* Read-only data               */
+                *(.rodata.str1.4)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)                 /* Global offset table          */
+                _etext = ABSOLUTE(.);
+        }
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data)		/* Modifiable data		*/
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	}
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data)                /* Modifiable data              */
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        }
 
-	.bss : {			/* BSS				*/
-		_sbss = ABSOLUTE(.);
-		*(.bss)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	}
-					/* Stabs debugging sections.	*/
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        .bss : {                        /* BSS                          */
+                _sbss = ABSOLUTE(.);
+                *(.bss)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        }
+                                        /* Stabs debugging sections.    */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/viewtool-stm32f107/README.txt b/configs/viewtool-stm32f107/README.txt
index 2fa7dd48601..ac8234ae68b 100644
--- a/configs/viewtool-stm32f107/README.txt
+++ b/configs/viewtool-stm32f107/README.txt
@@ -1058,9 +1058,6 @@ Configurations
           System Type -> Peripherals:
             CONFIG_STM32_SPI2=y                : Enable support for SPI2
 
-          RTOS Features:
-            CONFIG_DISABLE_SIGNALS=n           : Signals are required
-
           Library Support:
             CONFIG_SCHED_WORKQUEUE=y           : Work queue support required
 
diff --git a/configs/viewtool-stm32f107/netnsh/defconfig b/configs/viewtool-stm32f107/netnsh/defconfig
index 60d6735dbfa..31744b5b0ca 100644
--- a/configs/viewtool-stm32f107/netnsh/defconfig
+++ b/configs/viewtool-stm32f107/netnsh/defconfig
@@ -28,6 +28,8 @@ CONFIG_MAX_WDOGPARMS=2
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
@@ -43,7 +45,6 @@ CONFIG_NET_ICMPv6_SOCKET=y
 CONFIG_NET_IPv6=y
 CONFIG_NET_MAX_LISTENPORTS=40
 CONFIG_NET_ROUTE=y
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCP_CONNS=40
 CONFIG_NET_TCP_WRITE_BUFFERS=y
@@ -52,8 +53,6 @@ CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
-CONFIG_NSH_NETINIT_THREAD=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=10
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/viewtool-stm32f107/src/stm32_max3421e.c b/configs/viewtool-stm32f107/src/stm32_max3421e.c
index 661381980df..12bd225268a 100644
--- a/configs/viewtool-stm32f107/src/stm32_max3421e.c
+++ b/configs/viewtool-stm32f107/src/stm32_max3421e.c
@@ -364,16 +364,16 @@ int stm32_max3421e_setup(void)
     }
 #endif
 
-#if defined(CONFIG_RNDIS) && defined(CONFIG_NSH_MACADDR)
+#if defined(CONFIG_RNDIS) && defined(CONFIG_NETINIT_MACADDR)
   {
     uint8_t mac[6];
 
     mac[0] = 0xa0; /* TODO */
-    mac[1] = (CONFIG_NSH_MACADDR >> (8 * 4)) & 0xff;
-    mac[2] = (CONFIG_NSH_MACADDR >> (8 * 3)) & 0xff;
-    mac[3] = (CONFIG_NSH_MACADDR >> (8 * 2)) & 0xff;
-    mac[4] = (CONFIG_NSH_MACADDR >> (8 * 1)) & 0xff;
-    mac[5] = (CONFIG_NSH_MACADDR >> (8 * 0)) & 0xff;
+    mac[1] = (CONFIG_NETINIT_MACADDR >> (8 * 4)) & 0xff;
+    mac[2] = (CONFIG_NETINIT_MACADDR >> (8 * 3)) & 0xff;
+    mac[3] = (CONFIG_NETINIT_MACADDR >> (8 * 2)) & 0xff;
+    mac[4] = (CONFIG_NETINIT_MACADDR >> (8 * 1)) & 0xff;
+    mac[5] = (CONFIG_NETINIT_MACADDR >> (8 * 0)) & 0xff;
 
     ret = usbdev_rndis_initialize(mac);
     if (ret < 0)
diff --git a/configs/viewtool-stm32f107/src/stm32_ssd1289.c b/configs/viewtool-stm32f107/src/stm32_ssd1289.c
index 0b7a152a2bd..17b1f2e49ee 100644
--- a/configs/viewtool-stm32f107/src/stm32_ssd1289.c
+++ b/configs/viewtool-stm32f107/src/stm32_ssd1289.c
@@ -102,7 +102,6 @@ static void stm32_write(FAR struct ssd1289_lcd_s *dev, uint16_t data);
 static void stm32_backlight(FAR struct ssd1289_lcd_s *dev, int power);
 
 static void stm32_extmemgpios(const uint16_t *gpios, int ngpios);
-static void stm32_enablefsmc(void);
 
 /**************************************************************************************
  * Private Data
@@ -435,7 +434,7 @@ static void stm32_selectlcd(void)
 
   /* Enable AHB clocking to the FSMC */
 
-  stm32_enablefsmc();
+  stm32_fsmc_enable();
 
   /* Bank1 NOR/SRAM control register configuration */
 
@@ -481,25 +480,6 @@ static void stm32_extmemgpios(const uint16_t *gpios, int ngpios)
   }
 }
 
-/************************************************************************************
- * Name: stm32_enablefsmc
- *
- * Description:
- *  enable clocking to the FSMC module
- *
- ************************************************************************************/
-
-static void stm32_enablefsmc(void)
-{
-  uint32_t regval;
-
-  /* Enable AHB clocking to the FSMC */
-
-  regval  = getreg32( STM32_RCC_AHBENR);
-  regval |= RCC_AHBENR_FSMCEN;
-  putreg32(regval, STM32_RCC_AHBENR);
-}
-
 /**************************************************************************************
  * Public Functions
  **************************************************************************************/
diff --git a/configs/viewtool-stm32f107/tcpblaster/defconfig b/configs/viewtool-stm32f107/tcpblaster/defconfig
index 1e92d83de4d..c380e359f19 100644
--- a/configs/viewtool-stm32f107/tcpblaster/defconfig
+++ b/configs/viewtool-stm32f107/tcpblaster/defconfig
@@ -26,6 +26,8 @@ CONFIG_LIB_HOSTNAME="Viewtool-STM32F107"
 CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
 CONFIG_NET=y
+CONFIG_NETINIT_NOMAC=y
+CONFIG_NETINIT_THREAD=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NET_ARP_SEND=y
 CONFIG_NET_ETH_PKTSIZE=1514
@@ -43,8 +45,6 @@ CONFIG_NFILE_DESCRIPTORS=8
 CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_BUILTIN_APPS=y
-CONFIG_NSH_NETINIT_THREAD=y
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NSOCKET_DESCRIPTORS=10
 CONFIG_PREALLOC_MQ_MSGS=4
diff --git a/configs/xmc4500-relax/nsh/defconfig b/configs/xmc4500-relax/nsh/defconfig
index ce7af819eb0..fd9a2f2d592 100644
--- a/configs/xmc4500-relax/nsh/defconfig
+++ b/configs/xmc4500-relax/nsh/defconfig
@@ -24,7 +24,6 @@ CONFIG_AT24XX_EXTSIZE=160
 CONFIG_AT24XX_SIZE=2
 CONFIG_BOARD_LOOPSPERMSEC=8000
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y
 CONFIG_FS_FAT=y
diff --git a/configs/xmc4500-relax/src/xmc4_ostest.c b/configs/xmc4500-relax/src/xmc4_ostest.c
index a3575d25552..8ce4a8eaf5d 100644
--- a/configs/xmc4500-relax/src/xmc4_ostest.c
+++ b/configs/xmc4500-relax/src/xmc4_ostest.c
@@ -59,8 +59,7 @@
 
 #undef HAVE_FPU
 #if defined(CONFIG_ARCH_FPU) && !defined(CONFIG_TESTING_OSTEST_FPUTESTDISABLE) && \
-    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID) && \
-    !defined(CONFIG_DISABLE_SIGNALS)
+    defined(CONFIG_TESTING_OSTEST_FPUSIZE) && defined(CONFIG_SCHED_WAITPID)
 #    define HAVE_FPU 1
 #endif
 
diff --git a/configs/xmc4500-relax/src/xmc4_spi.c b/configs/xmc4500-relax/src/xmc4_spi.c
index 1beb039238d..04c5a45be95 100644
--- a/configs/xmc4500-relax/src/xmc4_spi.c
+++ b/configs/xmc4500-relax/src/xmc4_spi.c
@@ -75,7 +75,7 @@ void weak_function xmc4_spidev_initialize(void)
 
   /* Configure SPI2 chip selects */
 
-#ifdef CONFIG_XMC4_SPI2  && defined(CONFIG_SENSORS_MAX6675)
+#if define(CONFIG_XMC4_SPI2) && defined(CONFIG_SENSORS_MAX6675)
   (void)xmc4_gpio_config(GPIO_CS_MAX6675);
 #endif
 
diff --git a/configs/z16f2800100zcog/README.txt b/configs/z16f2800100zcog/README.txt
index e3414462ab5..3f468664586 100644
--- a/configs/z16f2800100zcog/README.txt
+++ b/configs/z16f2800100zcog/README.txt
@@ -68,13 +68,47 @@ Version 5.0.1
   on a different platform, you will need to change the path in the ZDS binaries
   in those that file and your PATH environment variable.
 
+Version 5.2.1
+  On June 2, 2019, support for the 5.2.1 ZDS-II toolchain was added.
+  I started verification using 5.30 on June 2, 2019.  To use this toolchain,
+  I had to suppress the gmtime() and gmtimer() because these were causing an
+  internal compiler error:
+
+    time\lib_gmtimer.c
+    P2: Internal Error(0xB47E59):
+            Please contact Technical Support
+
+  This is the change to suppress building these files:
+
+    diff --git a/libs/libc/time/Make.defs b/libs/libc/time/Make.defs
+    index 5c9b746778..8327e287f4 100644
+    --- a/libs/libc/time/Make.defs
+    +++ b/libs/libc/time/Make.defs
+    @@ -44,7 +44,7 @@ ifdef CONFIG_LIBC_LOCALTIME
+     CSRCS += lib_localtime.c lib_asctime.c lib_asctimer.c lib_ctime.c
+     CSRCS += lib_ctimer.c
+     else
+    -CSRCS += lib_mktime.c lib_gmtime.c lib_gmtimer.c
+    +CSRCS += lib_mktime.c # lib_gmtime.c lib_gmtimer.c
+     ifdef CONFIG_TIME_EXTENDED
+     CSRCS += lib_dayofweek.c lib_asctime.c lib_asctimer.c lib_ctime.c
+     CSRCS += lib_ctimer.c
+
+  The consequence is, of course, that these interfaces will not be available
+  to applications.
+
+  Another issue is that the ZDS-II version of stdarg.h does not provide
+  va_copy().  This affects libs/libc/lib_sysloc.c.
+
+  There are a few outstanding build issues, but it seems close enough for
+  the time being.
+
 Other Versions
 
-  If you use any version of ZDS-II other than 5.0.1 or if you install ZDS-II
-  at any location other than the default location, you will have to modify
-  configs/z16f2800100zcog/*/Make.defs.  Simply edit that file, changing
-  5.0.1 to whatever.  Also make sure that your PATH environment variable
-  includes th correct path to the toolchain.
+  If you use any version of ZDS-II or if you install ZDS-II at any location
+  other than the default location, you will have to modify
+  arch/z16/src/z16f/Kconfig and configs/z16f2800100zcog/scripts/Make.defs.
+  Simply edit that file, changing 5.0.1 to whatever.
 
 Patches
 =======
diff --git a/configs/z16f2800100zcog/nsh/defconfig b/configs/z16f2800100zcog/nsh/defconfig
index 275e9291ab4..ee1a4cd6697 100644
--- a/configs/z16f2800100zcog/nsh/defconfig
+++ b/configs/z16f2800100zcog/nsh/defconfig
@@ -19,7 +19,6 @@ CONFIG_ARCH_Z16=y
 CONFIG_ARCH="z16"
 CONFIG_BOARD_LOOPSPERMSEC=1250
 CONFIG_BUILTIN=y
-CONFIG_DISABLE_POLL=y
 CONFIG_ENDIAN_BIG=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/z16f2800100zcog/ostest/defconfig b/configs/z16f2800100zcog/ostest/defconfig
index c0108b66306..583f7868f5a 100644
--- a/configs/z16f2800100zcog/ostest/defconfig
+++ b/configs/z16f2800100zcog/ostest/defconfig
@@ -13,7 +13,6 @@ CONFIG_ARCH_Z16=y
 CONFIG_ARCH="z16"
 CONFIG_BOARD_LOOPSPERMSEC=1250
 CONFIG_DEV_LOWCONSOLE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_ENDIAN_BIG=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_IDLETHREAD_STACKSIZE=4096
diff --git a/configs/z16f2800100zcog/pashello/defconfig b/configs/z16f2800100zcog/pashello/defconfig
index f1f0e5e984c..3e071ce5fa3 100644
--- a/configs/z16f2800100zcog/pashello/defconfig
+++ b/configs/z16f2800100zcog/pashello/defconfig
@@ -13,7 +13,6 @@ CONFIG_ARCH_Z16=y
 CONFIG_ARCH="z16"
 CONFIG_BOARD_LOOPSPERMSEC=1250
 CONFIG_DEV_LOWCONSOLE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_ENDIAN_BIG=y
 CONFIG_EXAMPLES_PASHELLO=y
 CONFIG_HOST_WINDOWS=y
diff --git a/configs/z16f2800100zcog/scripts/Make.defs b/configs/z16f2800100zcog/scripts/Make.defs
index e8f784ab4cf..71846c9e509 100644
--- a/configs/z16f2800100zcog/scripts/Make.defs
+++ b/configs/z16f2800100zcog/scripts/Make.defs
@@ -36,19 +36,28 @@
 include $(TOPDIR)/.config
 include $(TOPDIR)/tools/Config.mk
 
-# These are the directories where the ZDS-II toolchain is installed.  NOTE
-# that short 8.3 path names are used in order to avoid spaces.  On my machine
-# I have:
+# These are the default directories where the ZDS-II toolchain is installed.
+# NOTE that short 8.3 path names are used in order to avoid spaces.  On my
+# machine I have:
 #
-# C:\PROGRA~1\ = C:\Profram Files\
-# C:\PROGRA~2\ = C:\Program Files (x86)\
+# Versions 5.0.1
+#   C:\PROGRA~1\ = C:\Program Files\
+#   C:\PROGRA~2\ = C:\Program Files (x86)\
 #
 # Your PC may be configured differently.
+#
+# Version 5.2.1, the default install location is C:\ZiLOG
 
-ZDSVERSION = 5.0.1
+ifeq ($(CONFIG_Z16F_ZDSII_V511),y)
+INSTALLROOT = C:/PROGRA~2/ZiLOG
+ZDSVERSION := 5.0.1
+else ifeq ($(CONFIG_Z16F_ZDSII_V521),y)
+INSTALLROOT = C:/ZiLOG
+ZDSVERSION := 5.2.1
+endif
 
 ifeq ($(CONFIG_WINDOWS_NATIVE),y)
-  ZDSINSTALLDIR = C:/PROGRA~2/ZiLOG/ZDSII_ZNEO_$(ZDSVERSION)
+  ZDSINSTALLDIR = $(INSTALLROOT)/ZDSII_ZNEO_$(ZDSVERSION)
   INSTALLDIR = ${shell echo $(ZDSINSTALLDIR)| sed -e "s/\//\\/g"}
   ZDSBINDIR = $(INSTALLDIR)\bin
   ZDSSTDINCDIR = $(INSTALLDIR)\include\std
@@ -64,7 +73,7 @@ ifeq ($(CONFIG_WINDOWS_NATIVE),y)
   ARCHUSRINCLUDES = -usrinc:.
 else
   WINTOOL = y
-  ZDSINSTALLDIR = C:/PROGRA~2/ZiLOG/ZDSII_ZNEO_$(ZDSVERSION)
+  ZDSINSTALLDIR = $(INSTALLROOT)/ZDSII_ZNEO_$(ZDSVERSION)
   INSTALLDIR = ${shell cygpath -u "$(ZDSINSTALLDIR)"}
   ZDSBINDIR = $(INSTALLDIR)/bin
   ZDSSTDINCDIR = $(INSTALLDIR)/include/std
@@ -147,11 +156,11 @@ LINKCMDTEMPLATE = $(TOPDIR)$(DELIM)configs$(DELIM)z16f2800100zcog$(DELIM)scripts
 # Tool names/pathes
 
 CROSSDEV =
-CC = zneocc.exe
+CC = $(ZDSBINDIR)$(DELIM)zneocc.exe
 CPP = gcc -E
-LD = zneolink.exe
-AS = zneoasm.exe
-AR = zneolib.exe
+LD = $(ZDSBINDIR)$(DELIM)zneolink.exe
+AS = $(ZDSBINDIR)$(DELIM)zneoasm.exe
+AR = $(ZDSBINDIR)$(DELIM)zneolib.exe
 
 # File extensions
 
@@ -180,9 +189,8 @@ define ASSEMBLE
 endef
 
 define MOVEOBJ
-	$(Q) $(call MOVEFILE, "$1.obj", "$2$(DELIM)$1.obj")
-	$(Q) $(call MOVEFILE, "$1.lst", "$2$(DELIM)$1.lst")
-	-$(Q) $(call MOVEFILE, "$1.src", "$2$(DELIM)$1.src")
+	$(call MOVEFILE, "$1.obj", "$2$(DELIM)$1.obj")
+	$(call MOVEFILE, "$1.lst", "$2$(DELIM)$1.lst")
 endef
 
 define ARCHIVE
@@ -207,17 +215,16 @@ define PREPROCESS
 endef
 
 define COMPILE
-	$(Q) (wfile=`cygpath -w "$1"`; "$(CC)" $(CFLAGS) $$wfile)
+	$(Q) "$(CC)" $(CFLAGS) `cygpath -w "$1"`
 endef
 
 define ASSEMBLE
-	$(Q) (wfile=`cygpath -w "$1"`; "$(AS)" $(AFLAGS) $$wfile)
+	$(Q) "$(AS)" $(AFLAGS) `cygpath -w "$1"`
 endef
 
 define MOVEOBJ
-	$(Q) $(call MOVEFILE, "$1.obj", "$2$(DELIM)$1.obj")
-	$(Q) $(call MOVEFILE, "$1.lst", "$2$(DELIM)$1.lst")
-	-$(Q) $(call MOVEFILE, "$1.src", "$2$(DELIM)$1.src")
+	$(call MOVEFILE, "$1.obj", "$2$(DELIM)$1.obj")
+	$(call MOVEFILE, "$1.lst", "$2$(DELIM)$1.lst")
 endef
 
 define ARCHIVE
@@ -243,7 +250,8 @@ ifeq ($(CONFIG_WINDOWS_NATIVE),y)
 
   # Windows-native host tools
 
-  MKDEP = $(TOPDIR)\tools\mkdeps.exe --winnative
+  #MKDEP = $(TOPDIR)\tools\mkdeps.exe --winnative
+  MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mknulldeps.sh
 else
 
 # Linux/Cygwin host tool definitions
@@ -255,7 +263,7 @@ else
 
   # This is the tool to use for dependencies (i.e., none)
 
-  MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mkwindeps.sh
+  MKDEP = $(TOPDIR)$(DELIM)tools$(DELIM)mknulldeps.sh
 
   # ZDS-II cannot follow Cygwin soft links, so we will have to use directory copies
 
diff --git a/configs/z16f2800100zcog/src/z16f_lowinit.c b/configs/z16f2800100zcog/src/z16f_lowinit.c
index 081d2d50909..6c82bb0c54f 100644
--- a/configs/z16f2800100zcog/src/z16f_lowinit.c
+++ b/configs/z16f2800100zcog/src/z16f_lowinit.c
@@ -41,7 +41,7 @@
 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/configs/z80sim/README.txt b/configs/z80sim/README.txt
index 0d29568fc3a..8fdf9caa551 100644
--- a/configs/z80sim/README.txt
+++ b/configs/z80sim/README.txt
@@ -222,3 +222,15 @@ and install SDCC:
 
   sudo make install
 
+Known compilation problems:
+
+    CC:  stdlib/lib_strtof.c
+    stdlib/lib_strtof.c:62:6: warning: #warning "Size of exponent is unknown"
+    stdlib/lib_strtof.c:76: error 122: dividing by ZERO
+    stdlib/lib_strtof.c:102: error 122: dividing by ZERO
+    stdlib/lib_strtof.c:76: error 122: dividing by ZERO
+
+  Workaround: Remove lib_strtof.c from libs/libc/stdlib/Make.defs
+
+  In arch/z80/src/z180:  error 26: '_cbr' not a structure/union member
+
diff --git a/configs/z80sim/nsh/defconfig b/configs/z80sim/nsh/defconfig
index fbc6311dd55..3b436fb5e18 100644
--- a/configs/z80sim/nsh/defconfig
+++ b/configs/z80sim/nsh/defconfig
@@ -28,7 +28,6 @@ CONFIG_BOARD_LOOPSPERMSEC=100
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_SYSTEM_NSH=y
 CONFIG_MAX_TASKS=8
diff --git a/configs/z80sim/ostest/defconfig b/configs/z80sim/ostest/defconfig
index 64c0e7a0ff2..bbdf5a0d030 100644
--- a/configs/z80sim/ostest/defconfig
+++ b/configs/z80sim/ostest/defconfig
@@ -15,7 +15,6 @@ CONFIG_BOARD_LOOPSPERMSEC=100
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_MAX_TASKS=8
 CONFIG_MAX_WDOGPARMS=2
diff --git a/configs/z80sim/pashello/defconfig b/configs/z80sim/pashello/defconfig
index fa353a8e223..502dd596c30 100644
--- a/configs/z80sim/pashello/defconfig
+++ b/configs/z80sim/pashello/defconfig
@@ -16,9 +16,7 @@ CONFIG_DEFAULT_SMALL=y
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
-CONFIG_DISABLE_SIGNALS=y
 CONFIG_EXAMPLES_PASHELLO=y
 CONFIG_INTERPRETERS_PCODE=y
 CONFIG_MAX_TASKS=8
diff --git a/configs/z80sim/src/z80_serial.c b/configs/z80sim/src/z80_serial.c
index ee1f60570e6..abe80c38ec2 100644
--- a/configs/z80sim/src/z80_serial.c
+++ b/configs/z80sim/src/z80_serial.c
@@ -50,7 +50,6 @@
 #include 
 #include 
 #include 
-#include 
 
 #include "up_arch.h"
 #include "up_internal.h"
@@ -113,22 +112,24 @@ static uart_dev_t g_uartport =
   { 1 },                    /* closesem */
   { 0 },                    /* xmitsem */
   { 0 },                    /* recvsem */
+  { 0 },                    /* pollsem */
   {                         /* xmit */
     { 1 },                  /*   sem */
     0,                      /*   head */
     0,                      /*   tail */
     CONFIG_UART_TXBUFSIZE,  /*   size */
-    g_uarttxbuffer,         /*   buffer */
+    g_uarttxbuffer          /*   buffer */
   },
   {                         /* recv */
     { 1 },                  /*   sem */
     0,                      /*   head */
     0,                      /*   tail */
     CONFIG_UART_RXBUFSIZE,  /*   size */
-    g_uartrxbuffer,         /*   buffer */
+    g_uartrxbuffer          /*   buffer */
   },
   &g_uart_ops,              /* ops */
   NULL,                     /* priv */
+  NULL                      /* pollfds */
 };
 
 /****************************************************************************
diff --git a/configs/z8encore000zco/ostest/defconfig b/configs/z8encore000zco/ostest/defconfig
index c9a7048d232..cc8de5ea896 100644
--- a/configs/z8encore000zco/ostest/defconfig
+++ b/configs/z8encore000zco/ostest/defconfig
@@ -18,7 +18,6 @@ CONFIG_DEFAULT_SMALL=y
 CONFIG_DEV_LOWCONSOLE=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_IDLETHREAD_STACKSIZE=256
diff --git a/configs/z8encore000zco/src/z8_lowinit.c b/configs/z8encore000zco/src/z8_lowinit.c
index ec39b79670c..315b66da24a 100644
--- a/configs/z8encore000zco/src/z8_lowinit.c
+++ b/configs/z8encore000zco/src/z8_lowinit.c
@@ -41,7 +41,7 @@
 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/configs/z8f64200100kit/README.txt b/configs/z8f64200100kit/README.txt
index e0dbcee016f..71132c6fd57 100644
--- a/configs/z8f64200100kit/README.txt
+++ b/configs/z8f64200100kit/README.txt
@@ -44,6 +44,10 @@ Other Versions
   the configs/z8f64200100kit/*/Make.defs file and also your PATH environment
   variable.
 
+  It has been a long time since the z8 port has been used.  A lot has
+  changed so it would most likely require a modest effort to get the
+  compilation working again.
+
 Configuration Subdirectories
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
diff --git a/configs/z8f64200100kit/ostest/defconfig b/configs/z8f64200100kit/ostest/defconfig
index b1b15915d92..4d3f2c14af2 100644
--- a/configs/z8f64200100kit/ostest/defconfig
+++ b/configs/z8f64200100kit/ostest/defconfig
@@ -17,7 +17,6 @@ CONFIG_BOARD_LOOPSPERMSEC=1250
 CONFIG_DEFAULT_SMALL=y
 CONFIG_DISABLE_MOUNTPOINT=y
 CONFIG_DISABLE_MQUEUE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_DISABLE_PTHREAD=y
 CONFIG_HOST_WINDOWS=y
 CONFIG_IDLETHREAD_STACKSIZE=256
diff --git a/configs/z8f64200100kit/src/z8_lowinit.c b/configs/z8f64200100kit/src/z8_lowinit.c
index 0a56359e3f6..2250c6261ee 100644
--- a/configs/z8f64200100kit/src/z8_lowinit.c
+++ b/configs/z8f64200100kit/src/z8_lowinit.c
@@ -41,7 +41,7 @@
 
 #include 
 
-#include "chip/chip.h"
+#include "chip.h"
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/configs/zkit-arm-1769/nsh/defconfig b/configs/zkit-arm-1769/nsh/defconfig
index a5b4f62ab9d..524f500c05a 100644
--- a/configs/zkit-arm-1769/nsh/defconfig
+++ b/configs/zkit-arm-1769/nsh/defconfig
@@ -43,6 +43,7 @@ CONFIG_MM_REGIONS=2
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
@@ -51,7 +52,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=8
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCP_SPLIT=y
 CONFIG_NET_UDP=y
@@ -61,7 +61,6 @@ CONFIG_NFILE_STREAMS=8
 CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_PREALLOC_MQ_MSGS=4
 CONFIG_PREALLOC_TIMERS=4
diff --git a/configs/zkit-arm-1769/nxhello/defconfig b/configs/zkit-arm-1769/nxhello/defconfig
index 779b0d892f2..ba2777df63b 100644
--- a/configs/zkit-arm-1769/nxhello/defconfig
+++ b/configs/zkit-arm-1769/nxhello/defconfig
@@ -51,6 +51,7 @@ CONFIG_MQ_MAXMSGSIZE=64
 CONFIG_NET=y
 CONFIG_NETDB_DNSCLIENT=y
 CONFIG_NETDB_DNSSERVER_NOADDR=y
+CONFIG_NETINIT_NOMAC=y
 CONFIG_NETUTILS_DHCPC=y
 CONFIG_NETUTILS_TELNETD=y
 CONFIG_NETUTILS_TFTPC=y
@@ -59,7 +60,6 @@ CONFIG_NET_BROADCAST=y
 CONFIG_NET_ICMP=y
 CONFIG_NET_ICMP_SOCKET=y
 CONFIG_NET_MAX_LISTENPORTS=8
-CONFIG_NET_SOCKOPTS=y
 CONFIG_NET_TCP=y
 CONFIG_NET_TCP_SPLIT=y
 CONFIG_NET_UDP=y
@@ -70,7 +70,6 @@ CONFIG_NSH_ARCHINIT=y
 CONFIG_NSH_FILEIOSIZE=512
 CONFIG_NSH_LIBRARY=y
 CONFIG_NSH_LINELEN=64
-CONFIG_NSH_NOMAC=y
 CONFIG_NSH_READLINE=y
 CONFIG_NX=y
 CONFIG_NXFONT_SANS23X27=y
diff --git a/configs/zkit-arm-1769/scripts/ld.script b/configs/zkit-arm-1769/scripts/ld.script
index 030bcabf00b..35f8e1001a2 100644
--- a/configs/zkit-arm-1769/scripts/ld.script
+++ b/configs/zkit-arm-1769/scripts/ld.script
@@ -56,61 +56,64 @@ EXTERN(_vectors)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} >sram
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } >sram
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} >sram
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } >sram
+        __exidx_end = ABSOLUTE(.);
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections. */
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections. */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/configs/zp214xpa/nsh/defconfig b/configs/zp214xpa/nsh/defconfig
index 48f0e27dd92..8ed3b3b430a 100644
--- a/configs/zp214xpa/nsh/defconfig
+++ b/configs/zp214xpa/nsh/defconfig
@@ -14,7 +14,6 @@ CONFIG_ARCH_CHIP_LPC2148=y
 CONFIG_ARCH_CHIP_LPC214X=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=3270
-CONFIG_DISABLE_POLL=y
 CONFIG_IDLETHREAD_STACKSIZE=2048
 CONFIG_MAX_TASKS=16
 CONFIG_MAX_WDOGPARMS=2
diff --git a/configs/zp214xpa/nxlines/defconfig b/configs/zp214xpa/nxlines/defconfig
index 2e748bd4252..d17d20126e6 100644
--- a/configs/zp214xpa/nxlines/defconfig
+++ b/configs/zp214xpa/nxlines/defconfig
@@ -17,7 +17,6 @@ CONFIG_ARCH_CHIP_LPC214X=y
 CONFIG_ARCH_STACKDUMP=y
 CONFIG_BOARD_LOOPSPERMSEC=3270
 CONFIG_DEV_LOWCONSOLE=y
-CONFIG_DISABLE_POLL=y
 CONFIG_EXAMPLES_NXLINES=y
 CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0x01
 CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4
diff --git a/configs/zp214xpa/scripts/ld.script b/configs/zp214xpa/scripts/ld.script
index ba6ff8f2c16..b28dd9a0983 100644
--- a/configs/zp214xpa/scripts/ld.script
+++ b/configs/zp214xpa/scripts/ld.script
@@ -46,75 +46,79 @@
 
 MEMORY
 {
-	flash (rx) : ORIGIN = 0x00000000, LENGTH = 500K
-	sram  (rw) : ORIGIN = 0x40000000, LENGTH = 32K - 32
+        flash (rx) : ORIGIN = 0x00000000, LENGTH = 500K
+        sram  (rw) : ORIGIN = 0x40000000, LENGTH = 32K - 32
 }
 
 OUTPUT_ARCH(arm)
 ENTRY(_stext)
 SECTIONS
 {
-	.text : {
-		_stext = ABSOLUTE(.);
-		*(.vectors)
-		*(.text .text.*)
-		*(.fixup)
-		*(.gnu.warning)
-		*(.rodata .rodata.*)
-		*(.gnu.linkonce.t.*)
-		*(.glue_7)
-		*(.glue_7t)
-		*(.got)
-		*(.gcc_except_table)
-		*(.gnu.linkonce.r.*)
-		_etext = ABSOLUTE(.);
-	} > flash
+        .text : {
+                _stext = ABSOLUTE(.);
+                *(.vectors)
+                *(.text .text.*)
+                *(.fixup)
+                *(.gnu.warning)
+                *(.rodata .rodata.*)
+                *(.gnu.linkonce.t.*)
+                *(.glue_7)
+                *(.glue_7t)
+                *(.got)
+                *(.gcc_except_table)
+                *(.gnu.linkonce.r.*)
+                _etext = ABSOLUTE(.);
+        } > flash
 
-	.init_section : {
-		_sinit = ABSOLUTE(.);
-		*(.init_array .init_array.*)
-		_einit = ABSOLUTE(.);
-	} > flash
+        . = ALIGN(4);
+        .init_section : {
+                _sinit = ABSOLUTE(.);
+                *(.init_array .init_array.*)
+                _einit = ABSOLUTE(.);
+        } > flash
 
-	.ARM.extab : {
-		*(.ARM.extab*)
-	} > flash
+        . = ALIGN(4);
+        .ARM.extab : {
+                *(.ARM.extab*)
+        } > flash
 
-	__exidx_start = ABSOLUTE(.);
-	.ARM.exidx : {
-		*(.ARM.exidx*)
-	} > flash
-	__exidx_end = ABSOLUTE(.);
+        . = ALIGN(4);
+        __exidx_start = ABSOLUTE(.);
+        .ARM.exidx : {
+                *(.ARM.exidx*)
+        } > flash
+        __exidx_end = ABSOLUTE(.);
 
-	_eronly = ABSOLUTE(.);
+        _eronly = ABSOLUTE(.);
 
-	.data : {
-		_sdata = ABSOLUTE(.);
-		*(.data .data.*)
-		*(.gnu.linkonce.d.*)
-		CONSTRUCTORS
-		_edata = ABSOLUTE(.);
-	} > sram AT > flash
+        . = ALIGN(4);
+        .data : {
+                _sdata = ABSOLUTE(.);
+                *(.data .data.*)
+                *(.gnu.linkonce.d.*)
+                CONSTRUCTORS
+                _edata = ABSOLUTE(.);
+        } > sram AT > flash
 
-	.bss : {
-		_sbss = ABSOLUTE(.);
-		*(.bss .bss.*)
-		*(.gnu.linkonce.b.*)
-		*(COMMON)
-		_ebss = ABSOLUTE(.);
-	} > sram
+        .bss : {
+                _sbss = ABSOLUTE(.);
+                *(.bss .bss.*)
+                *(.gnu.linkonce.b.*)
+                *(COMMON)
+                _ebss = ABSOLUTE(.);
+        } > sram
 
-	/* Stabs debugging sections.	*/
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.stab.excl 0 : { *(.stab.excl) }
-	.stab.exclstr 0 : { *(.stab.exclstr) }
-	.stab.index 0 : { *(.stab.index) }
-	.stab.indexstr 0 : { *(.stab.indexstr) }
-	.comment 0 : { *(.comment) }
-	.debug_abbrev 0 : { *(.debug_abbrev) }
-	.debug_info 0 : { *(.debug_info) }
-	.debug_line 0 : { *(.debug_line) }
-	.debug_pubnames 0 : { *(.debug_pubnames) }
-	.debug_aranges 0 : { *(.debug_aranges) }
+        /* Stabs debugging sections.    */
+        .stab 0 : { *(.stab) }
+        .stabstr 0 : { *(.stabstr) }
+        .stab.excl 0 : { *(.stab.excl) }
+        .stab.exclstr 0 : { *(.stab.exclstr) }
+        .stab.index 0 : { *(.stab.index) }
+        .stab.indexstr 0 : { *(.stab.indexstr) }
+        .comment 0 : { *(.comment) }
+        .debug_abbrev 0 : { *(.debug_abbrev) }
+        .debug_info 0 : { *(.debug_info) }
+        .debug_line 0 : { *(.debug_line) }
+        .debug_pubnames 0 : { *(.debug_pubnames) }
+        .debug_aranges 0 : { *(.debug_aranges) }
 }
diff --git a/crypto/cryptodev.c b/crypto/cryptodev.c
index 97099227421..f70be00a487 100644
--- a/crypto/cryptodev.c
+++ b/crypto/cryptodev.c
@@ -80,17 +80,15 @@ static int cryptodev_ioctl(FAR struct file *filep, int cmd,
 
 static const struct file_operations g_cryptodevops =
 {
-  0,                  /* open   */
-  0,                  /* close  */
+  NULL,               /* open   */
+  NULL,               /* close  */
   cryptodev_read,     /* read   */
   cryptodev_write,    /* write  */
-  0,                  /* seek   */
-  cryptodev_ioctl     /* ioctl  */
-#ifndef CONFIG_DISABLE_POLL
-  , 0                 /* poll   */
-#endif
+  NULL,               /* seek   */
+  cryptodev_ioctl,    /* ioctl  */
+  NULL                /* poll   */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
-  , 0                 /* unlink */
+  , NULL              /* unlink */
 #endif
 };
 
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 71e813a3b17..8b695006534 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -3,17 +3,6 @@
 # see the file kconfig-language.txt in the NuttX tools repository.
 #
 
-config DISABLE_POLL
-	bool "Disable driver poll interfaces"
-	default n
-	---help---
-		The sizes of drivers can be reduced if the poll() method is not
-		supported.  If you do not use poll() or select(), then you can
-		select DISABLE_POLL to reduce the code footprint by a small amount.
-
-		This selection disables the poll() interface as well as interfaces
-		the derive from poll() such as select().
-
 config DEV_NULL
 	bool "Enable /dev/null"
 	default y
diff --git a/drivers/analog/Kconfig b/drivers/analog/Kconfig
index 6e5964c2594..7273ff9af71 100644
--- a/drivers/analog/Kconfig
+++ b/drivers/analog/Kconfig
@@ -36,7 +36,6 @@ config ADC_FIFOSIZE
 config ADC_NPOLLWAITERS
 	int "Number of poll waiters"
 	default 2
-	depends on !DISABLE_POLL
 	---help---
 		Maximum number of threads that can be waiting on poll.
 
diff --git a/drivers/analog/adc.c b/drivers/analog/adc.c
index a54be243015..85c965eb621 100644
--- a/drivers/analog/adc.c
+++ b/drivers/analog/adc.c
@@ -76,9 +76,7 @@ static int     adc_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
 static int     adc_receive(FAR struct adc_dev_s *dev, uint8_t ch,
                            int32_t data);
 static void    adc_notify(FAR struct adc_dev_s *dev);
-#ifndef CONFIG_DISABLE_POLL
 static int     adc_poll(FAR struct file *filep, struct pollfd *fds, bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -91,10 +89,8 @@ static const struct file_operations g_adc_fops =
   adc_read,     /* read */
   0,            /* write */
   0,            /* seek */
-  adc_ioctl     /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , adc_poll    /* poll */
-#endif
+  adc_ioctl,    /* ioctl */
+  adc_poll      /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL        /* unlink */
 #endif
@@ -461,7 +457,6 @@ static int adc_receive(FAR struct adc_dev_s *dev, uint8_t ch, int32_t data)
  * Name: adc_pollnotify
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static void adc_pollnotify(FAR struct adc_dev_s *dev, uint32_t type)
 {
   int i;
@@ -476,7 +471,6 @@ static void adc_pollnotify(FAR struct adc_dev_s *dev, uint32_t type)
         }
     }
 }
-#endif
 
 /****************************************************************************
  * Name: adc_notify
@@ -499,16 +493,13 @@ static void adc_notify(FAR struct adc_dev_s *dev)
    * then wake them up now.
    */
 
-#ifndef CONFIG_DISABLE_POLL
    adc_pollnotify(dev, POLLIN);
-#endif
 }
 
 /************************************************************************************
  * Name: adc_poll
  ************************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int adc_poll(FAR struct file *filep, struct pollfd *fds, bool setup)
 {
   FAR struct inode     *inode = filep->f_inode;
@@ -581,7 +572,6 @@ return_with_irqdisabled:
   leave_critical_section(flags);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/analog/ads1242.c b/drivers/analog/ads1242.c
index 018da51cf53..b75e6ccec80 100644
--- a/drivers/analog/ads1242.c
+++ b/drivers/analog/ads1242.c
@@ -122,10 +122,8 @@ static const struct file_operations g_ads1242_fops =
   ads1242_read,
   ads1242_write,
   NULL,
-  ads1242_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  ads1242_ioctl,
+  NULL
 };
 
 /****************************************************************************
diff --git a/drivers/analog/comp.c b/drivers/analog/comp.c
index cceaf4ee41c..9404bac0c0d 100644
--- a/drivers/analog/comp.c
+++ b/drivers/analog/comp.c
@@ -64,11 +64,9 @@ static int     comp_close(FAR struct file *filep);
 static ssize_t comp_read(FAR struct file *filep, FAR char *buffer,
                          size_t buflen);
 static int     comp_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int     comp_poll(FAR struct file *filep, FAR struct pollfd *fds,
                          bool setup);
 static int     comp_notify(FAR struct comp_dev_s *dev, uint8_t val);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -81,21 +79,17 @@ static const struct file_operations comp_fops =
   comp_read,                    /* read */
   NULL,                         /* write */
   NULL,                         /* seek */
-  comp_ioctl                    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , comp_poll                   /* poll */
-#endif
+  comp_ioctl,                   /* ioctl */
+  comp_poll                     /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL                        /* unlink */
 #endif
 };
 
-#ifndef CONFIG_DISABLE_POLL
 static const struct comp_callback_s g_comp_callback =
   {
     comp_notify   /* au_notify */
   };
-#endif
 
 /****************************************************************************
  * Private Functions
@@ -109,7 +103,6 @@ static const struct comp_callback_s g_comp_callback =
  *
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static void comp_pollnotify(FAR struct comp_dev_s *dev,
                             pollevent_t eventset)
 {
@@ -143,13 +136,11 @@ static void comp_pollnotify(FAR struct comp_dev_s *dev,
         }
     }
 }
-#endif
 
 /****************************************************************************
  * Name: comp_semtake
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static void comp_semtake(FAR sem_t *sem)
 {
  int ret;
@@ -168,13 +159,11 @@ static void comp_semtake(FAR sem_t *sem)
     }
   while (ret == -EINTR);
 }
-#endif
 
 /****************************************************************************
  * Name: comp_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int comp_poll(FAR struct file *filep, FAR struct pollfd *fds,
                      bool setup)
 {
@@ -239,7 +228,6 @@ static int comp_poll(FAR struct file *filep, FAR struct pollfd *fds,
   nxsem_post(&dev->ad_sem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Name: comp_notify
@@ -250,7 +238,6 @@ static int comp_poll(FAR struct file *filep, FAR struct pollfd *fds,
  *
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int comp_notify(FAR struct comp_dev_s *dev, uint8_t val)
 {
   /* TODO: store values in FIFO? */
@@ -262,7 +249,6 @@ static int comp_notify(FAR struct comp_dev_s *dev, uint8_t val)
 
   return 0;
 }
-#endif
 
 /****************************************************************************
  * Name: comp_open
@@ -382,16 +368,13 @@ static ssize_t comp_read(FAR struct file *filep, FAR char *buffer, size_t buflen
 
   /* If non-blocking read, read the value immediately and return. */
 
-#ifndef CONFIG_DISABLE_POLL
   if (filep->f_oflags & O_NONBLOCK)
-#endif
     {
       ret = dev->ad_ops->ao_read(dev);
       buffer[0] = (uint8_t)ret;
       return 1;
     }
 
-#ifndef CONFIG_DISABLE_POLL
   ret = nxsem_wait(&dev->ad_readsem);
   if (ret < 0)
     {
@@ -402,7 +385,6 @@ static ssize_t comp_read(FAR struct file *filep, FAR char *buffer, size_t buflen
   buffer[0] = dev->val;
 
   return 1;
-#endif
 }
 
 /****************************************************************************
@@ -447,7 +429,6 @@ int comp_register(FAR const char *path, FAR struct comp_dev_s *dev)
 
   DEBUGASSERT(dev->ad_ops != NULL);
 
-#ifndef CONFIG_DISABLE_POLL
   if (dev->ad_ops->ao_bind != NULL)
     {
       ret = dev->ad_ops->ao_bind(dev, &g_comp_callback);
@@ -457,7 +438,6 @@ int comp_register(FAR const char *path, FAR struct comp_dev_s *dev)
           return ret;
         }
     }
-#endif
 
   /* Register the COMP character driver */
 
diff --git a/drivers/analog/dac.c b/drivers/analog/dac.c
index 495095c73c8..b129c5bbc0b 100644
--- a/drivers/analog/dac.c
+++ b/drivers/analog/dac.c
@@ -92,11 +92,9 @@ static const struct file_operations dac_fops =
   dac_close,
   dac_read,
   dac_write,
-  0,
-  dac_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , 0
-#endif
+  NULL,
+  dac_ioctl,
+  NULL
 };
 
 /****************************************************************************
@@ -204,11 +202,7 @@ static int dac_close(FAR struct file *filep)
 
           while (dev->ad_xmit.af_head != dev->ad_xmit.af_tail)
             {
-#ifndef CONFIG_DISABLE_SIGNALS
                nxsig_usleep(HALF_SECOND_USEC);
-#else
-               up_mdelay(HALF_SECOND_MSEC);
-#endif
             }
 
           /* Free the IRQ and disable the DAC device */
diff --git a/drivers/analog/opamp.c b/drivers/analog/opamp.c
index 50e43d52c92..b9ad35974bb 100644
--- a/drivers/analog/opamp.c
+++ b/drivers/analog/opamp.c
@@ -73,10 +73,8 @@ static const struct file_operations opamp_fops =
   NULL,                          /* read */
   NULL,                          /* write */
   NULL,                          /* seek */
-  opamp_ioctl                    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL                         /* poll */
-#endif
+  opamp_ioctl,                   /* ioctl */
+  NULL                           /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL                         /* unlink */
 #endif
diff --git a/drivers/audio/tone.c b/drivers/audio/tone.c
index d0dfb4d33bd..9422f5e6c7e 100644
--- a/drivers/audio/tone.c
+++ b/drivers/audio/tone.c
@@ -180,13 +180,11 @@ static const struct file_operations g_toneops =
   tone_close,                   /* close */
   tone_read,                    /* read */
   tone_write,                   /* write */
-  0,                            /* seek */
-  0                             /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0                           /* poll */
-#endif
+  NULL,                         /* seek */
+  NULL,                         /* ioctl */
+  NULL                          /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
-  , 0                           /* unlink */
+  , NULL                        /* unlink */
 #endif
 };
 
diff --git a/drivers/bch/bchdev_driver.c b/drivers/bch/bchdev_driver.c
index f9b8181e6cd..8593899527f 100644
--- a/drivers/bch/bchdev_driver.c
+++ b/drivers/bch/bchdev_driver.c
@@ -75,10 +75,8 @@ static ssize_t bch_write(FAR struct file *filep, FAR const char *buffer,
                  size_t buflen);
 static int     bch_ioctl(FAR struct file *filep, int cmd,
                  unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int     bch_poll(FAR struct file *filep, FAR struct pollfd *fds,
                  bool setup);
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
 static int     bch_unlink(FAR struct inode *inode);
 #endif
@@ -94,10 +92,8 @@ const struct file_operations bch_fops =
   bch_read,    /* read */
   bch_write,   /* write */
   bch_seek,    /* seek */
-  bch_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , bch_poll   /* poll */
-#endif
+  bch_ioctl,   /* ioctl */
+  bch_poll     /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , bch_unlink /* unlink */
 #endif
@@ -111,7 +107,6 @@ const struct file_operations bch_fops =
  * Name: bch_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int bch_poll(FAR struct file *filep, FAR struct pollfd *fds,
                     bool setup)
 {
@@ -126,7 +121,6 @@ static int bch_poll(FAR struct file *filep, FAR struct pollfd *fds,
 
   return OK;
 }
-#endif
 
 /****************************************************************************
  * Name: bch_open
diff --git a/drivers/bch/bchdev_unregister.c b/drivers/bch/bchdev_unregister.c
index de636046706..a18a2264b73 100644
--- a/drivers/bch/bchdev_unregister.c
+++ b/drivers/bch/bchdev_unregister.c
@@ -73,7 +73,7 @@
 int bchdev_unregister(FAR const char *chardev)
 {
   FAR struct bchlib_s *bch;
-  FAR struct file filestruct;
+  struct file filestruct;
   int ret;
 
   /* Sanity check */
diff --git a/drivers/can/Kconfig b/drivers/can/Kconfig
index 32a1e0521d3..029ec72c549 100644
--- a/drivers/can/Kconfig
+++ b/drivers/can/Kconfig
@@ -119,7 +119,6 @@ config CAN_LOOPBACK
 config CAN_NPOLLWAITERS
 	int "Number of poll waiters"
 	default 2
-	depends on !DISABLE_POLL
 	---help---
 		The maximum number of threads that may be waiting on the
 		poll method.
@@ -175,5 +174,10 @@ config MCP2515_CLK_FREQUENCY
 	default 8000000
 	range 1 25000000
 
+config MCP2515_SPI_SCK_FREQUENCY
+	int "MCP2515 SPI SCK Frequency"
+	default 1000000
+	range 100000 10000000
+
 endif # CAN_MCP2515
 endif # CAN
diff --git a/drivers/can/can.c b/drivers/can/can.c
index 6232f70ee86..8cfb5d0d406 100644
--- a/drivers/can/can.c
+++ b/drivers/can/can.c
@@ -1,8 +1,8 @@
 /****************************************************************************
  * drivers/can/can.c
  *
- *   Copyright (C) 2008-2009, 2011-2012, 2014-2015, 2017 Gregory Nutt. All
- *     rights reserved.
+ *   Copyright (C) 2008-2009, 2011-2012, 2014-2015, 2017, 2019 Gregory Nutt.
+ *     All rights reserved.
  *   Author: Gregory Nutt 
  *
  *   Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
@@ -60,6 +60,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #ifdef CONFIG_CAN_TXREADY
 #  include 
@@ -72,6 +73,7 @@
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
+
 /* Configuration ************************************************************/
 
 #ifdef CONFIG_CAN_TXREADY
@@ -118,10 +120,8 @@ static int            can_takesem(FAR sem_t *sem);
 
 /* Poll helpers */
 
-#ifndef CONFIG_DISABLE_POLL
 static void           can_pollnotify(FAR struct can_dev_s *dev,
                                      pollevent_t eventset);
-#endif
 
 /* CAN helpers */
 
@@ -146,10 +146,8 @@ static inline ssize_t can_rtrread(FAR struct can_dev_s *dev,
                                   FAR struct canioc_rtr_s *rtr);
 static int            can_ioctl(FAR struct file *filep, int cmd,
                                 unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int            can_poll(FAR struct file *filep, FAR struct pollfd *fds,
                                bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -162,10 +160,8 @@ static const struct file_operations g_canops =
   can_read,  /* read */
   can_write, /* write */
   NULL,      /* seek */
-  can_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , can_poll /* poll */
-#endif
+  can_ioctl, /* ioctl */
+  can_poll   /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL     /* unlink */
 #endif
@@ -205,7 +201,6 @@ static int can_takesem(FAR sem_t *sem)
  * Name: can_pollnotify
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static void can_pollnotify(FAR struct can_dev_s *dev, pollevent_t eventset)
 {
   FAR struct pollfd *fds;
@@ -225,9 +220,6 @@ static void can_pollnotify(FAR struct can_dev_s *dev, pollevent_t eventset)
         }
     }
 }
-#else
-#  define can_pollnotify(dev, eventset)
-#endif
 
 /****************************************************************************
  * Name: can_dlc2bytes
@@ -256,16 +248,22 @@ static uint8_t can_dlc2bytes(uint8_t dlc)
         {
           case 9:
             return 12;
+
           case 10:
             return 16;
+
           case 11:
             return 20;
+
           case 12:
             return 24;
+
           case 13:
             return 32;
+
           case 14:
             return 48;
+
           default:
           case 15:
             return 64;
@@ -394,6 +392,20 @@ static void can_txready_work(FAR void *arg)
 }
 #endif
 
+static FAR struct can_reader_s *init_can_reader(FAR struct file *filep)
+{
+  FAR struct can_reader_s *reader = kmm_zalloc(sizeof(struct can_reader_s));
+  DEBUGASSERT(reader != NULL);
+
+  reader->fifo.rx_head  = 0;
+  reader->fifo.rx_tail  = 0;
+
+  nxsem_init(&reader->fifo.rx_sem, 0, 1);
+  reader->filep = filep;
+
+  return reader;
+}
+
 /****************************************************************************
  * Name: can_open
  *
@@ -448,8 +460,6 @@ static int can_open(FAR struct file *filep)
               dev->cd_xmit.tx_head  = 0;
               dev->cd_xmit.tx_queue = 0;
               dev->cd_xmit.tx_tail  = 0;
-              dev->cd_recv.rx_head  = 0;
-              dev->cd_recv.rx_tail  = 0;
 
               /* Finally, Enable the CAN RX interrupt */
 
@@ -458,6 +468,8 @@ static int can_open(FAR struct file *filep)
               /* Save the new open count only on success */
 
               dev->cd_ocount = 1;
+
+              list_initialize(&dev->cd_readers);
             }
 
           leave_critical_section(flags);
@@ -468,6 +480,12 @@ static int can_open(FAR struct file *filep)
 
           dev->cd_ocount = tmp;
         }
+
+    irqstate_t flags = enter_critical_section();
+    list_add_head(&dev->cd_readers,
+                  (FAR struct list_node *)init_can_reader(filep));
+
+    leave_critical_section(flags);
     }
 
   can_givesem(&dev->cd_closesem);
@@ -488,6 +506,8 @@ static int can_close(FAR struct file *filep)
   FAR struct inode     *inode = filep->f_inode;
   FAR struct can_dev_s *dev   = inode->i_private;
   irqstate_t            flags;
+  FAR struct list_node *node;
+  FAR struct list_node *tmp;
   int                   ret;
 
   caninfo("ocount: %d\n", dev->cd_ocount);
@@ -498,6 +518,16 @@ static int can_close(FAR struct file *filep)
       return ret;
     }
 
+  list_for_every_safe(&dev->cd_readers, node, tmp)
+    {
+      if (((FAR struct can_reader_s *)node)->filep == filep)
+        {
+          list_delete(node);
+          kmm_free(node);
+          break;
+        }
+    }
+
   /* Decrement the references to the driver.  If the reference count will
    * decrement to 0, then uninitialize the driver.
    */
@@ -520,22 +550,14 @@ static int can_close(FAR struct file *filep)
 
   while (dev->cd_xmit.tx_head != dev->cd_xmit.tx_tail)
     {
-#ifndef CONFIG_DISABLE_SIGNALS
        nxsig_usleep(HALF_SECOND_USEC);
-#else
-       up_mdelay(HALF_SECOND_MSEC);
-#endif
     }
 
   /* And wait for the TX hardware FIFO to drain */
 
   while (!dev_txempty(dev))
     {
-#ifndef CONFIG_DISABLE_SIGNALS
       nxsig_usleep(HALF_SECOND_USEC);
-#else
-      up_mdelay(HALF_SECOND_MSEC);
-#endif
     }
 
   /* Free the IRQ and disable the CAN device */
@@ -560,11 +582,14 @@ errout:
 static ssize_t can_read(FAR struct file *filep, FAR char *buffer,
                         size_t buflen)
 {
-  FAR struct inode     *inode = filep->f_inode;
-  FAR struct can_dev_s *dev   = inode->i_private;
-  size_t                nread;
-  irqstate_t            flags;
-  int                   ret   = 0;
+  FAR struct inode         *inode = filep->f_inode;
+  FAR struct can_dev_s     *dev = inode->i_private;
+  FAR struct can_reader_s  *reader = NULL;
+  FAR struct list_node     *node;
+  FAR struct can_rxfifo_s  *fifo;
+  size_t                    nread;
+  irqstate_t                flags;
+  int                       ret = 0;
 
   caninfo("buflen: %d\n", buflen);
 
@@ -616,7 +641,20 @@ static ssize_t can_read(FAR struct file *filep, FAR char *buffer,
         }
 #endif /* CONFIG_CAN_ERRORS */
 
-      while (dev->cd_recv.rx_head == dev->cd_recv.rx_tail)
+      list_for_every(&dev->cd_readers, node)
+        {
+          if (((FAR struct can_reader_s *) node)->filep == filep)
+            {
+              reader = (FAR struct can_reader_s *)node;
+              break;
+            }
+        }
+
+      DEBUGASSERT(reader != NULL);
+
+      fifo = &reader->fifo;
+
+      while (fifo->rx_head == fifo->rx_tail)
         {
           /* The receive FIFO is empty -- was non-blocking mode selected? */
 
@@ -630,8 +668,9 @@ static ssize_t can_read(FAR struct file *filep, FAR char *buffer,
 
           DEBUGASSERT(dev->cd_nrxwaiters < 255);
           dev->cd_nrxwaiters++;
-          ret = can_takesem(&dev->cd_recv.rx_sem);
+          ret = can_takesem(&fifo->rx_sem);
           dev->cd_nrxwaiters--;
+
           if (ret < 0)
             {
               goto return_with_irqdisabled;
@@ -642,33 +681,33 @@ static ssize_t can_read(FAR struct file *filep, FAR char *buffer,
        * in the user buffer.
        */
 
-      nread = 0;
-      do
-        {
-          /* Will the next message in the FIFO fit into the user buffer? */
+    nread = 0;
+    do
+      {
+        /* Will the next message in the FIFO fit into the user buffer? */
 
-          FAR struct can_msg_s *msg = &dev->cd_recv.rx_buffer[dev->cd_recv.rx_head];
-          int nbytes = can_dlc2bytes(msg->cm_hdr.ch_dlc);
-          int msglen = CAN_MSGLEN(nbytes);
+        FAR struct can_msg_s *msg = &fifo->rx_buffer[fifo->rx_head];
+        int nbytes = can_dlc2bytes(msg->cm_hdr.ch_dlc);
+        int msglen = CAN_MSGLEN(nbytes);
 
-          if (nread + msglen > buflen)
-            {
-              break;
-            }
+        if (nread + msglen > buflen)
+          {
+            break;
+          }
 
-          /* Copy the message to the user buffer */
+        /* Copy the message to the user buffer */
 
-          memcpy(&buffer[nread], msg, msglen);
-          nread += msglen;
+        memcpy(&buffer[nread], msg, msglen);
+        nread += msglen;
 
-          /* Increment the head of the circular message buffer */
+        /* Increment the head of the circular message buffer */
 
-          if (++dev->cd_recv.rx_head >= CONFIG_CAN_FIFOSIZE)
-            {
-              dev->cd_recv.rx_head = 0;
-            }
+        if (++fifo->rx_head >= CONFIG_CAN_FIFOSIZE)
+          {
+            fifo->rx_head = 0;
+          }
         }
-      while (dev->cd_recv.rx_head != dev->cd_recv.rx_tail);
+      while (fifo->rx_head != fifo->rx_tail);
 
       /* All on the messages have bee transferred.  Return the number of bytes
        * that were read.
@@ -721,7 +760,8 @@ static int can_xmit(FAR struct can_dev_s *dev)
 
   /* Check if we have already queued all of the data in the TX fifo.
    *
-   * tx_tail:  Incremented in can_write each time a message is queued in the FIFO
+   * tx_tail:  Incremented in can_write each time a message is queued in the
+   *           FIFO
    * tx_head:  Incremented in can_txdone each time a message completes
    * tx_queue: Incremented each time that a message is sent to the hardware.
    *
@@ -832,9 +872,9 @@ static ssize_t can_write(FAR struct file *filep, FAR const char *buffer,
               goto return_with_irqdisabled;
             }
 
-          /* If the TX hardware was inactive when we started, then we will have
-           * start the XMIT sequence generate the TX done interrupts needed
-           * to clear the FIFO.
+          /* If the TX hardware was inactive when we started, then we will
+           * have start the XMIT sequence generate the TX done interrupts
+           * needed to clear the FIFO.
            */
 
           if (inactive)
@@ -992,12 +1032,13 @@ static int can_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: can_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int can_poll(FAR struct file *filep, FAR struct pollfd *fds,
                     bool setup)
 {
-  FAR struct inode     *inode = (FAR struct inode *)filep->f_inode;
-  FAR struct can_dev_s *dev   = (FAR struct can_dev_s *)inode->i_private;
+  FAR struct inode *inode = (FAR struct inode *)filep->f_inode;
+  FAR struct can_dev_s *dev = (FAR struct can_dev_s *)inode->i_private;
+  FAR struct can_reader_s *reader = NULL;
+  FAR struct list_node *node;
   pollevent_t eventset;
   int ndx;
   int ret;
@@ -1012,6 +1053,17 @@ static int can_poll(FAR struct file *filep, FAR struct pollfd *fds,
     }
 #endif
 
+  list_for_every(&dev->cd_readers, node)
+    {
+      if (((FAR struct can_reader_s *)node)->filep == filep)
+        {
+          reader = (FAR struct can_reader_s *)node;
+          break;
+        }
+    }
+
+  DEBUGASSERT(reader != NULL);
+
   /* Get exclusive access to the poll structures */
 
   ret = can_takesem(&dev->cd_pollsem);
@@ -1096,17 +1148,17 @@ static int can_poll(FAR struct file *filep, FAR struct pollfd *fds,
       dev->cd_nrxwaiters++;
       do
         {
-          ret = can_takesem(&dev->cd_recv.rx_sem);
+          ret = can_takesem(&reader->fifo.rx_sem);
         }
       while (ret < 0);
       dev->cd_nrxwaiters--;
 
-      if (dev->cd_recv.rx_head != dev->cd_recv.rx_tail)
+      if (reader->fifo.rx_head != reader->fifo.rx_tail)
         {
           eventset |= fds->events & POLLIN;
         }
 
-      can_givesem(&dev->cd_recv.rx_sem);
+      can_givesem(&reader->fifo.rx_sem);
 
       if (eventset != 0)
         {
@@ -1117,7 +1169,7 @@ static int can_poll(FAR struct file *filep, FAR struct pollfd *fds,
     {
       /* This is a request to tear down the poll */
 
-      struct pollfd **slot = (struct pollfd **)fds->priv;
+      FAR struct pollfd **slot = (FAR struct pollfd **)fds->priv;
 
 #ifdef CONFIG_DEBUG_FEATURES
       if (slot == NULL)
@@ -1137,7 +1189,6 @@ errout:
   can_givesem(&dev->cd_pollsem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
@@ -1168,11 +1219,8 @@ int can_register(FAR const char *path, FAR struct can_dev_s *dev)
   /* Initialize semaphores */
 
   nxsem_init(&dev->cd_xmit.tx_sem, 0, 1);
-  nxsem_init(&dev->cd_recv.rx_sem, 0, 1);
   nxsem_init(&dev->cd_closesem,    0, 1);
-#ifndef CONFIG_DISABLE_POLL
   nxsem_init(&dev->cd_pollsem,     0, 1);
-#endif
 
   for (i = 0; i < CONFIG_CAN_NPENDINGRTR; i++)
     {
@@ -1217,8 +1265,10 @@ int can_register(FAR const char *path, FAR struct can_dev_s *dev)
 int can_receive(FAR struct can_dev_s *dev, FAR struct can_hdr_s *hdr,
                 FAR uint8_t *data)
 {
-  FAR struct can_rxfifo_s *fifo = &dev->cd_recv;
+  FAR struct can_rxfifo_s *fifo;
   FAR uint8_t             *dest;
+  FAR struct list_node    *node;
+  FAR struct list_node    *tmp;
   int                      nexttail;
   int                      errcode = -ENOMEM;
   int                      i;
@@ -1229,12 +1279,6 @@ int can_receive(FAR struct can_dev_s *dev, FAR struct can_hdr_s *hdr,
    * enqueue read data.
    */
 
-  nexttail = fifo->rx_tail + 1;
-  if (nexttail >= CONFIG_CAN_FIFOSIZE)
-    {
-      nexttail = 0;
-    }
-
   /* First, check if this response matches any RTR response that we may be
    * waiting for.
    */
@@ -1280,60 +1324,72 @@ int can_receive(FAR struct can_dev_s *dev, FAR struct can_hdr_s *hdr,
         }
     }
 
-  /* Refuse the new data if the FIFO is full */
-
-  if (nexttail != fifo->rx_head)
+  list_for_every_safe(&dev->cd_readers, node, tmp)
     {
-      int nbytes;
+      FAR struct can_reader_s *reader = (FAR struct can_reader_s *)node;
+      fifo = &reader->fifo;
 
-      /* Add the new, decoded CAN message at the tail of the FIFO.
-       *
-       * REVISIT:  In the CAN FD format, the coding of the DLC differs from
-       * the standard CAN format. The DLC codes 0 to 8 have the same coding
-       * as in standard CAN, the codes 9 to 15, which in standard CAN all
-       * code a data field of 8 bytes, are encoded:
-       *
-       *   9->12, 10->16, 11->20, 12->24, 13->32, 14->48, 15->64
-       */
-
-      memcpy(&fifo->rx_buffer[fifo->rx_tail].cm_hdr, hdr, sizeof(struct can_hdr_s));
-
-      nbytes = can_dlc2bytes(hdr->ch_dlc);
-      for (i = 0, dest = fifo->rx_buffer[fifo->rx_tail].cm_data; i < nbytes; i++)
+      nexttail = fifo->rx_tail + 1;
+      if (nexttail >= CONFIG_CAN_FIFOSIZE)
         {
-          *dest++ = *data++;
+          nexttail = 0;
         }
 
-      /* Increment the tail of the circular buffer */
+      /* Refuse the new data if the FIFO is full */
 
-      fifo->rx_tail = nexttail;
-
-      /* The increment the counting semaphore. The maximum value should be
-       * CONFIG_CAN_FIFOSIZE -- one possible count for each allocated
-       * message buffer.
-       */
-
-      if (dev->cd_nrxwaiters > 0)
+      if (nexttail != fifo->rx_head)
         {
-          can_givesem(&fifo->rx_sem);
+          int nbytes;
+          int sval;
+
+          /* Add the new, decoded CAN message at the tail of the FIFO.
+           *
+           * REVISIT:  In the CAN FD format, the coding of the DLC differs
+           * from the standard CAN format. The DLC codes 0 to 8 have the
+           * same coding as in standard CAN, the codes 9 to 15, which in
+           * standard CAN all code a data field of 8 bytes, are encoded:
+           *
+           *   9->12, 10->16, 11->20, 12->24, 13->32, 14->48, 15->64
+           */
+
+          memcpy(&fifo->rx_buffer[fifo->rx_tail].cm_hdr, hdr,
+                 sizeof(struct can_hdr_s));
+
+          nbytes = can_dlc2bytes(hdr->ch_dlc);
+          memcpy(fifo->rx_buffer[fifo->rx_tail].cm_data, data, nbytes);
+
+          /* Increment the tail of the circular buffer */
+
+          fifo->rx_tail = nexttail;
+
+          /* The increment the counting semaphore. The maximum value should be
+           * CONFIG_CAN_FIFOSIZE -- one possible count for each allocated
+           * message buffer.
+           */
+
+          sval = 0;
+          if (nxsem_getvalue(&fifo->rx_sem, &sval) <= 0)
+            {
+              can_givesem(&fifo->rx_sem);
+            }
+
+          errcode = OK;
+
+          /* Notify all poll/select waiters that they can read from the
+           * cd_recv buffer
+           */
+
+          can_pollnotify(dev, POLLIN);
         }
-
-      errcode = OK;
-
-      /* Notify all poll/select waiters that they can read from the
-       * cd_recv buffer
-       */
-
-      can_pollnotify(dev, POLLIN);
-    }
 #ifdef CONFIG_CAN_ERRORS
-  else
-    {
-      /* Report rx overflow error */
+      else
+        {
+          /* Report rx overflow error */
 
-      dev->cd_error |= CAN_ERROR5_RXOVERFLOW;
-    }
+          dev->cd_error |= CAN_ERROR5_RXOVERFLOW;
+        }
 #endif
+    }
 
   return errcode;
 }
@@ -1556,15 +1612,11 @@ int can_txready(FAR struct can_dev_s *dev)
   else
     {
       /* There should not be any threads waiting for space in the S/W TX
-       * FIFO is it is empty.
-       *
-       * REVISIT: Assertion can fire in certain race conditions, i.e, when
-       * all waiters have been awakened but have not yet had a chance to
-       * decrement cd_ntxwaiters.
+       * FIFO is it is empty.  However, an assertion would fire in certain
+       * race conditions, i.e, when all waiters have been awakened but
+       * have not yet had a chance to decrement cd_ntxwaiters.
        */
 
-      //DEBUGASSERT(dev->cd_ntxwaiters == 0);
-
 #if 0 /* REVISIT */
       /* When the H/W FIFO has been emptied, we can disable further TX
        * interrupts.
diff --git a/drivers/can/mcp2515.c b/drivers/can/mcp2515.c
index bcf1a316d54..e0db92e72a3 100644
--- a/drivers/can/mcp2515.c
+++ b/drivers/can/mcp2515.c
@@ -48,6 +48,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -68,6 +69,10 @@
 
 /* MCP2515 Configuration ****************************************************/
 
+#define CAN_FRAME_MAX_DATA_LEN 8
+#define SPI_TRANSFER_BUF_LEN   (6 + CAN_FRAME_MAX_DATA_LEN)
+#define MCP2515_NUM_TX_BUFFERS 3
+
 /* Bit timing */
 
 #define MCP2515_PROPSEG  CONFIG_MCP2515_PROPSEG
@@ -75,7 +80,7 @@
 #define MCP2515_PHSEG2   CONFIG_MCP2515_PHASESEG2
 #define MCP2515_TSEG1    (MCP2515_PROPSEG + MCP2515_PHSEG1)
 #define MCP2515_TSEG2    MCP2515_PHSEG2
-#define MCP2515_BRP      ((uint8_t)(((float) MCP2515_CANCLK_FREQUENCY / \
+#define MCP2515_BRP      ((uint8_t)(((float)(MCP2515_CANCLK_FREQUENCY) / \
                          ((float)(MCP2515_TSEG1 + MCP2515_TSEG2 + 1) * \
                          (float)(2 * CONFIG_MCP2515_BITRATE))) - 1))
 #define MCP2515_SJW      CONFIG_MCP2515_SJW
@@ -108,29 +113,29 @@
 
 /* MCP2515 Filters */
 
-#  ifndef CONFIG_MCP2515_NSTDFILTERS
-#    define CONFIG_MCP2515_NSTDFILTERS 0
-#  endif
+#ifndef CONFIG_MCP2515_NSTDFILTERS
+#  define CONFIG_MCP2515_NSTDFILTERS 0
+#endif
 
-#  if (CONFIG_MCP2515_NSTDFILTERS > 128)
-#    error Invalid MCP25150 number of Standard Filters
-#  endif
+#if (CONFIG_MCP2515_NSTDFILTERS > 128)
+#  error Invalid MCP25150 number of Standard Filters
+#endif
 
-#  ifndef CONFIG_MCP2515_NEXTFILTERS
-#    define CONFIG_MCP2515_NEXTFILTERS 0
-#  endif
+#ifndef CONFIG_MCP2515_NEXTFILTERS
+#  define CONFIG_MCP2515_NEXTFILTERS 0
+#endif
 
-#  if (CONFIG_MCP2515_NEXTFILTERS > 64)
-#    error Invalid MCP25150 number of Extended Filters
-#  endif
+#if (CONFIG_MCP2515_NEXTFILTERS > 64)
+#  error Invalid MCP25150 number of Extended Filters
+#endif
 
-#  define MCP2515_STDFILTER_BYTES \
-      MCP2515_ALIGN_UP(CONFIG_MCP2515_NSTDFILTERS << 2)
-#  define MCP2515_STDFILTER_WORDS (MCP2515_STDFILTER_BYTES >> 2)
+#define MCP2515_STDFILTER_BYTES \
+   MCP2515_ALIGN_UP(CONFIG_MCP2515_NSTDFILTERS << 2)
+#define MCP2515_STDFILTER_WORDS (MCP2515_STDFILTER_BYTES >> 2)
 
-#  define MCP2515_EXTFILTER_BYTES \
-      MCP2515_ALIGN_UP(CONFIG_MCP2515_NEXTFILTERS << 3)
-#  define MCP2515_EXTFILTER_WORDS (MCP2515_EXTFILTER_BYTES >> 2)
+#define MCP2515_EXTFILTER_BYTES \
+   MCP2515_ALIGN_UP(CONFIG_MCP2515_NEXTFILTERS << 3)
+#define MCP2515_EXTFILTER_WORDS (MCP2515_EXTFILTER_BYTES >> 2)
 
 /* MCP25150 TX buffer element size */
 
@@ -170,6 +175,10 @@
 
 #define MCP2515_TXBUFFER_INTS  (MCP2515_INT_TX0 | MCP2515_INT_TX1 | MCP2515_INT_TX2)
 
+/* Helpers ******************************************************************/
+
+#define TXREGVAL(reg) priv->spi_txbuf[reg - MCP2515_TXB0CTRL]
+
 /* Debug ********************************************************************/
 
 /* Debug configurations that may be enabled just for testing MCP2515 */
@@ -213,9 +222,10 @@ struct mcp2515_can_s
   uint32_t olderrors;       /* Used to detect the changes in error states */
 #endif
   uint8_t filters;          /* Standard/Extende filter bit allocator. */
-  uint8_t ntxbufs;          /* Number of allocated TX Buffers */
   uint8_t txbuffers;        /* TX Buffers bit allocator. */
 
+  FAR uint8_t *spi_txbuf;
+  FAR uint8_t *spi_rxbuf;
 #ifdef CONFIG_MCP2515_REGDEBUG
   uintptr_t regaddr;        /* Last register address read */
   uint32_t regval;          /* Last value read from the register */
@@ -309,6 +319,22 @@ static const struct can_ops_s g_mcp2515ops =
  * Private Functions
  ****************************************************************************/
 
+static void mcp2515_read_2regs(FAR struct mcp2515_can_s *priv, uint8_t reg,
+                               FAR uint8_t *v1, FAR uint8_t *v2)
+{
+  priv->spi_txbuf[0] = MCP2515_READ;
+  priv->spi_txbuf[1] = reg;
+
+  SPI_LOCK(priv->config->spi, true);
+  SPI_SELECT(priv->config->spi, SPIDEV_CANBUS(0), true);
+  SPI_EXCHANGE(priv->config->spi, priv->spi_txbuf, priv->spi_rxbuf, 4);
+  SPI_SELECT(priv->config->spi, SPIDEV_CANBUS(0), false);
+  SPI_LOCK(priv->config->spi, false);
+
+  *v1 = priv->spi_rxbuf[2];
+  *v2 = priv->spi_rxbuf[3];
+}
+
 /****************************************************************************
  * Name: mcp2515_readregs
  *
@@ -362,6 +388,29 @@ static void mcp2515_readregs(FAR struct mcp2515_can_s *priv, uint8_t regaddr,
 #endif
 }
 
+static void mcp2515_transfer(FAR struct mcp2515_can_s *priv, uint8_t len)
+{
+  FAR struct mcp2515_config_s *config = priv->config;
+
+  (void)SPI_LOCK(config->spi, true);
+
+  /* Select the MCP2515 */
+
+  SPI_SELECT(config->spi, SPIDEV_CANBUS(0), true);
+
+  /* Send the READ command */
+
+  SPI_EXCHANGE(config->spi, priv->spi_txbuf, priv->spi_rxbuf, len);
+
+  /* Deselect the MCP2515 */
+
+  SPI_SELECT(config->spi, SPIDEV_CANBUS(0), false);
+
+  /* Unlock bus */
+
+  (void)SPI_LOCK(config->spi, false);
+}
+
 /****************************************************************************
  * Name: mcp2515_writeregs
  *
@@ -435,6 +484,10 @@ static void mcp2515_modifyreg(FAR struct mcp2515_can_s *priv, uint8_t regaddr,
                               uint8_t mask, uint8_t value)
 {
   FAR struct mcp2515_config_s *config = priv->config;
+  uint8_t wr[4]=
+  {
+    MCP2515_BITMOD, regaddr, mask, value
+  };
 
   (void)SPI_LOCK(config->spi, true);
 
@@ -442,21 +495,7 @@ static void mcp2515_modifyreg(FAR struct mcp2515_can_s *priv, uint8_t regaddr,
 
   SPI_SELECT(config->spi, SPIDEV_CANBUS(0), true);
 
-  /* Send the Modify command */
-
-  (void)SPI_SEND(config->spi, MCP2515_BITMOD);
-
-  /* Send the register address */
-
-  (void)SPI_SEND(config->spi, regaddr);
-
-  /* Send the mask */
-
-  (void)SPI_SEND(config->spi, mask);
-
-  /* Send the value */
-
-  (void)SPI_SEND(config->spi, value);
+  SPI_SNDBLOCK(config->spi, wr, 4);
 
   /* Deselect the MCP2515 */
 
@@ -539,7 +578,7 @@ static void mcp2515_dev_lock(FAR struct mcp2515_can_s *priv)
 
 #ifdef CONFIG_CAN_EXTID
 static int mcp2515_add_extfilter(FAR struct mcp2515_can_s *priv,
-                              FAR struct canioc_extfilter_s *extconfig)
+                                 FAR struct canioc_extfilter_s *extconfig)
 {
   FAR struct mcp2515_config_s *config;
   uint8_t regval;
@@ -867,7 +906,7 @@ static int mcp2515_del_extfilter(FAR struct mcp2515_can_s *priv, int ndx)
  ****************************************************************************/
 
 static int mcp2515_add_stdfilter(FAR struct mcp2515_can_s *priv,
-                              FAR struct canioc_stdfilter_s *stdconfig)
+                                 FAR struct canioc_stdfilter_s *stdconfig)
 {
   FAR struct mcp2515_config_s *config;
   uint8_t regval;
@@ -948,7 +987,7 @@ static int mcp2515_add_stdfilter(FAR struct mcp2515_can_s *priv,
                 break;
 
               case CAN_FILTER_RANGE:
-                /* not supported */
+                /* Not supported */
 
                 break;
             }
@@ -987,7 +1026,7 @@ static int mcp2515_add_stdfilter(FAR struct mcp2515_can_s *priv,
 
               /* Setup the Filter */
 
-              regval = (uint8_t)(((stdconfig->sf_id1) & 0x7f8) >> 3);
+              regval = (uint8_t) (((stdconfig->sf_id1) & 0x7f8) >> 3);
               mcp2515_writeregs(priv, MCP2515_RXF0SIDH + offset +
                                 ((priv->nalloc - 1) * 4), ®val, 1);
               mcp2515_writeregs(priv, MCP2515_RXM0SIDH + offset, ®val, 1);
@@ -1166,7 +1205,8 @@ static void mcp2515_reset_lowlevel(FAR struct mcp2515_can_s *priv)
    */
 
   nxsem_destroy(&priv->txfsem);
-  nxsem_init(&priv->txfsem, 0, config->ntxbuffers);
+  nxsem_init(&priv->txfsem, 0, MCP2515_NUM_TX_BUFFERS);
+  priv->txbuffers = 0b111;
 
   /* Define the current state and unlock */
 
@@ -1303,7 +1343,6 @@ static void mcp2515_rxint(FAR struct can_dev_s *dev, bool enable)
   FAR struct mcp2515_can_s *priv;
   FAR struct mcp2515_config_s *config;
   irqstate_t flags;
-  uint8_t regval;
 
   DEBUGASSERT(dev);
   priv = dev->cd_priv;
@@ -1318,18 +1357,17 @@ static void mcp2515_rxint(FAR struct can_dev_s *dev, bool enable)
 
   flags = enter_critical_section();
 
-  mcp2515_readregs(priv, MCP2515_CANINTE, ®val, 1);
-
   if (enable)
     {
-      regval |= priv->rxints | MCP2515_ERROR_INTS;
+      mcp2515_modifyreg(priv, MCP2515_CANINTE,
+                        priv->rxints | MCP2515_ERROR_INTS,
+                        priv->rxints | MCP2515_ERROR_INTS);
     }
   else
     {
-      regval &= ~priv->rxints;
+      mcp2515_modifyreg(priv, MCP2515_CANINTE, priv->rxints, ~priv->rxints);
     }
 
-  mcp2515_writeregs(priv, MCP2515_CANINTE, ®val, 1);
   leave_critical_section(flags);
 }
 
@@ -1351,7 +1389,6 @@ static void mcp2515_txint(FAR struct can_dev_s *dev, bool enable)
 {
   FAR struct mcp2515_can_s *priv = dev->cd_priv;
   irqstate_t flags;
-  uint8_t regval;
 
   DEBUGASSERT(priv && priv->config);
 
@@ -1360,18 +1397,18 @@ static void mcp2515_txint(FAR struct can_dev_s *dev, bool enable)
   /* Enable/disable the receive interrupts */
 
   flags = enter_critical_section();
-  mcp2515_readregs(priv, MCP2515_CANINTE, ®val, 1);
 
   if (enable)
     {
-      regval |= priv->txints | MCP2515_ERROR_INTS;
+      mcp2515_modifyreg(priv, MCP2515_CANINTE,
+                        priv->txints | MCP2515_ERROR_INTS,
+                        priv->txints | MCP2515_ERROR_INTS);
     }
   else
     {
-      regval &= ~priv->txints;
+      mcp2515_modifyreg(priv, MCP2515_CANINTE, priv->txints, ~priv->txints);
     }
 
-  mcp2515_writeregs(priv, MCP2515_CANINTE, ®val, 1);
   leave_critical_section(flags);
 }
 
@@ -1425,18 +1462,18 @@ static int mcp2515_ioctl(FAR struct can_dev_s *dev, int cmd,
           DEBUGASSERT(bt != NULL);
 
           mcp2515_readregs(priv, MCP2515_CNF1, ®val, 1);
-          bt->bt_sjw   = ((regval & CNF1_SJW_MASK) >> CNF1_SJW_SHIFT) + 1;
-          brp          = (((regval & CNF1_BRP_MASK) >> CNF1_BRP_SHIFT) + 1) * 2;
+          bt->bt_sjw    = ((regval & CNF1_SJW_MASK) >> CNF1_SJW_SHIFT) + 1;
+          brp           = (((regval & CNF1_BRP_MASK) >> CNF1_BRP_SHIFT) + 1) * 2;
 
           mcp2515_readregs(priv, MCP2515_CNF2, ®val, 1);
-          bt->bt_tseg1 = ((regval & CNF2_PRSEG_MASK) >> CNF2_PRSEG_SHIFT) + 1;
+          bt->bt_tseg1  = ((regval & CNF2_PRSEG_MASK) >> CNF2_PRSEG_SHIFT) + 1;
           bt->bt_tseg1 += ((regval & CNF2_PHSEG1_MASK) >> CNF2_PHSEG1_SHIFT) + 1;
 
           mcp2515_readregs(priv, MCP2515_CNF3, ®val, 1);
-          bt->bt_tseg2 = ((regval & CNF3_PHSEG2_MASK) >> CNF3_PHSEG2_SHIFT) + 1;
+          bt->bt_tseg2  = ((regval & CNF3_PHSEG2_MASK) >> CNF3_PHSEG2_SHIFT) + 1;
 
-          bt->bt_baud  = MCP2515_CANCLK_FREQUENCY / brp /
-                         (bt->bt_tseg1 + bt->bt_tseg2 + 1);
+          bt->bt_baud   = MCP2515_CANCLK_FREQUENCY / brp /
+                          (bt->bt_tseg1 + bt->bt_tseg2 + 1);
           ret = OK;
         }
         break;
@@ -1683,9 +1720,8 @@ static int mcp2515_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
   FAR struct mcp2515_can_s *priv;
   FAR struct mcp2515_config_s *config;
   uint8_t regval;
-  uint8_t offset;
+  uint8_t txbuf;
   unsigned int nbytes;
-  unsigned int i;
 
   DEBUGASSERT(dev);
   priv = dev->cd_priv;
@@ -1697,46 +1733,20 @@ static int mcp2515_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
           config->devid, msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc);
   UNUSED(config);
 
-  /* That that FIFO elements were configured.
-   *
-   * REVISIT: Dedicated TX buffers are not used by this driver.
-   */
-
-  DEBUGASSERT(config->ntxbuffers > 0);
-
-  /* Select one empty transmit buffer */
-
-  mcp2515_readregs(priv, MCP2515_TXB0CTRL, ®val, 1);
-  if ((regval & TXBCTRL_TXREQ) == 0)
-    {
-      offset = MCP2515_TX0_OFFSET;
-    }
-  else
-    {
-      mcp2515_readregs(priv, MCP2515_TXB1CTRL, ®val, 1);
-      if ((regval & TXBCTRL_TXREQ) == 0)
-        {
-          offset = MCP2515_TX1_OFFSET;
-        }
-     else
-       {
-         mcp2515_readregs(priv, MCP2515_TXB2CTRL, ®val, 1);
-         if ((regval & TXBCTRL_TXREQ) == 0)
-           {
-              offset = MCP2515_TX2_OFFSET;
-           }
-         else
-           {
-             canerr("ERROR: No available transmit buffer!\n");
-             return -EBUSY;
-           }
-       }
-    }
-
   /* Get exclusive access to the MCP2515 peripheral */
 
   mcp2515_dev_lock(priv);
 
+  /* Acquire buffer */
+
+  nxsem_wait(&priv->txfsem);
+  DEBUGASSERT(priv->txbuffers != 0);
+
+  txbuf = ffs(priv->txbuffers) - 1;
+  priv->txbuffers &= ~(1 << txbuf);
+
+  /* Select one empty transmit buffer */
+
   /* Setup the MCP2515 TX Buffer with the message to send */
 
 #ifdef CONFIG_CAN_EXTID
@@ -1747,12 +1757,12 @@ static int mcp2515_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
       /* EID7 - EID0 */
 
       regval = (msg->cm_hdr.ch_id & 0xff);
-      mcp2515_writeregs(priv, MCP2515_TXB0EID0 + offset, ®val, 1);
+      TXREGVAL(MCP2515_TXB0EID0) = regval;
 
       /* EID15 - EID8 */
 
       regval = (msg->cm_hdr.ch_id & 0xff00) >> 8;
-      mcp2515_writeregs(priv, MCP2515_TXB0EID8 + offset, ®val, 1);
+      TXREGVAL(MCP2515_TXB0EID8) = regval;
 
       /* EID17 and EID16 */
 
@@ -1762,12 +1772,12 @@ static int mcp2515_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
       /* STD2 - STD0 */
 
       regval |= (msg->cm_hdr.ch_id & 0x1c0000) >> 18;
-      mcp2515_writeregs(priv, MCP2515_TXB0SIDL + offset, ®val, 1);
+      TXREGVAL(MCP2515_TXB0SIDL) = regval;
 
       /* STD10 - STD3 */
 
       regval  = (msg->cm_hdr.ch_id & 0x1fe00000) >> 21;
-      mcp2515_writeregs(priv, MCP2515_TXB0SIDH + offset, ®val, 1);
+      TXREGVAL(MCP2515_TXB0SIDH) = regval;
     }
   else
 #endif
@@ -1779,12 +1789,12 @@ static int mcp2515_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
       /* STD10 - STD3 */
 
       regval  = (msg->cm_hdr.ch_id & 0x7f8) >> 3;
-      mcp2515_writeregs(priv, MCP2515_TXB0SIDH + offset, ®val, 1);
+      TXREGVAL(MCP2515_TXB0SIDH) = regval;
 
       /* STD2 - STD0 */
 
       regval  = (msg->cm_hdr.ch_id & 0x007) << 5;
-      mcp2515_writeregs(priv, MCP2515_TXB0SIDL + offset, ®val, 1);
+      TXREGVAL(MCP2515_TXB0SIDL) = regval;
     }
 
   /* Setup the DLC */
@@ -1796,25 +1806,22 @@ static int mcp2515_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
       regval |= TXBDLC_RTR;
     }
 
-  mcp2515_writeregs(priv, MCP2515_TXB0DLC + offset, ®val, 1);
+  TXREGVAL(MCP2515_TXB0DLC) = regval;
 
   /* Fill the data buffer */
 
   nbytes = msg->cm_hdr.ch_dlc;
 
-  for (i = 0; i < nbytes; i++)
-    {
-      /* Little endian is assumed */
+  memcpy(&TXREGVAL(MCP2515_TXB0D0), msg->cm_data, nbytes);
 
-      regval = msg->cm_data[i];
-      mcp2515_writeregs(priv, MCP2515_TXB0D0 + offset + i, ®val, 1);
-    }
+  TXREGVAL(MCP2515_TXB0CTRL) = MCP2515_LOAD_TXB(txbuf);
 
-  /* And request to send the message */
+  mcp2515_transfer(priv, SPI_TRANSFER_BUF_LEN);
 
-  mcp2515_readregs(priv, MCP2515_TXB0CTRL, ®val, 1);
-  regval |= TXBCTRL_TXREQ;
-  mcp2515_writeregs(priv, MCP2515_TXB0CTRL, ®val, 1);
+  /* Request to send */
+
+  priv->spi_txbuf[0] = MCP2515_RTS(txbuf);
+  mcp2515_transfer(priv, 1);
 
   mcp2515_dev_unlock(priv);
 
@@ -1848,55 +1855,12 @@ static int mcp2515_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
 static bool mcp2515_txready(FAR struct can_dev_s *dev)
 {
   FAR struct mcp2515_can_s *priv;
-  uint8_t regval;
-  bool ready;
 
   DEBUGASSERT(dev);
   priv = dev->cd_priv;
   DEBUGASSERT(priv);
 
-  /* That that FIFO elements were configured.
-   *
-   * REVISIT: Dedicated TX buffers are not used by this driver.
-   */
-
-  DEBUGASSERT(priv->config->ntxbuffers > 0);
-
-  /* Get exclusive access to the MCP2515 peripheral */
-
-  mcp2515_dev_lock(priv);
-
-  /* Select one empty transmit buffer */
-
-  mcp2515_readregs(priv, MCP2515_TXB0CTRL, ®val, 1);
-  if ((regval & TXBCTRL_TXREQ) == 0)
-    {
-      ready = true;
-    }
-  else
-    {
-      mcp2515_readregs(priv, MCP2515_TXB1CTRL, ®val, 1);
-      if ((regval & TXBCTRL_TXREQ) == 0)
-        {
-          ready = true;
-        }
-     else
-       {
-         mcp2515_readregs(priv, MCP2515_TXB2CTRL, ®val, 1);
-         if ((regval & TXBCTRL_TXREQ) == 0)
-           {
-              ready = true;
-           }
-         else
-           {
-             ready = false;
-           }
-       }
-    }
-
-  mcp2515_dev_unlock(priv);
-
-  return ready;
+  return priv->txbuffers != 0;
 }
 
 /****************************************************************************
@@ -1920,55 +1884,12 @@ static bool mcp2515_txready(FAR struct can_dev_s *dev)
 static bool mcp2515_txempty(FAR struct can_dev_s *dev)
 {
   FAR struct mcp2515_can_s *priv;
-  uint8_t regval;
-  bool empty;
 
   DEBUGASSERT(dev);
   priv = dev->cd_priv;
   DEBUGASSERT(priv);
 
-  /* That that FIFO elements were configured.
-   *
-   * REVISIT: Dedicated TX buffers are not used by this driver.
-   */
-
-  DEBUGASSERT(priv->config->ntxbuffers > 0);
-
-  /* Get exclusive access to the MCP2515 peripheral */
-
-  mcp2515_dev_lock(priv);
-
-  /* Select one empty transmit buffer */
-
-  mcp2515_readregs(priv, MCP2515_TXB0CTRL, ®val, 1);
-  if ((regval & TXBCTRL_TXREQ) != 0)
-    {
-      empty = false;
-    }
-  else
-    {
-      mcp2515_readregs(priv, MCP2515_TXB1CTRL, ®val, 1);
-      if ((regval & TXBCTRL_TXREQ) != 0)
-        {
-          empty = false;
-        }
-     else
-       {
-         mcp2515_readregs(priv, MCP2515_TXB2CTRL, ®val, 1);
-         if ((regval & TXBCTRL_TXREQ) != 0)
-           {
-              empty = false;
-           }
-         else
-           {
-             empty = true;
-           }
-       }
-    }
-
-  mcp2515_dev_unlock(priv);
-
-  return empty;
+  return priv->txbuffers == (1 << MCP2515_NUM_TX_BUFFERS) - 1;
 }
 
 /****************************************************************************
@@ -2116,23 +2037,23 @@ static void mcp2515_error(FAR struct can_dev_s *dev, uint8_t status,
  *
  ****************************************************************************/
 
+#define RXREGVAL(reg) priv->spi_rxbuf[reg-MCP2515_RXB0CTRL]
+
 static void mcp2515_receive(FAR struct can_dev_s *dev, uint8_t offset)
 {
   FAR struct mcp2515_can_s *priv;
   struct can_hdr_s hdr;
   int ret;
   uint8_t regval;
-  uint8_t data[CAN_MAXDATALEN];
 
   DEBUGASSERT(dev);
   priv = dev->cd_priv;
   DEBUGASSERT(priv);
 
-  /* Format the CAN header */
+  mcp2515_readregs(priv, MCP2515_RXB0CTRL + offset, priv->spi_rxbuf,
+                   SPI_TRANSFER_BUF_LEN);
 
-  /* Get the CAN identifier. */
-
-  mcp2515_readregs(priv, MCP2515_RXB0SIDL + offset, ®val, 1);
+  regval = RXREGVAL(MCP2515_RXB0SIDL);
 
 #ifdef CONFIG_CAN_EXTID
   if ((regval & RXBSIDL_IDE) != 0)
@@ -2141,36 +2062,38 @@ static void mcp2515_receive(FAR struct can_dev_s *dev, uint8_t offset)
 
       /* EID7 - EID0 */
 
-      mcp2515_readregs(priv, MCP2515_RXB0EID0 + offset, ®val, 1);
-      hdr.ch_id    = regval ;
+      regval     = RXREGVAL(MCP2515_RXB0EID0);
+      hdr.ch_id  = regval ;
 
       /* EID15 - EID8 */
 
-      mcp2515_readregs(priv, MCP2515_RXB0EID8 + offset, ®val, 1);
-      hdr.ch_id    = hdr.ch_id | (regval << 8);
+      regval     = RXREGVAL(MCP2515_RXB0EID8);
+      hdr.ch_id  = hdr.ch_id | (regval << 8);
 
       /* EID17 and EID16 */
 
-      mcp2515_readregs(priv, MCP2515_RXB0SIDL + offset, ®val, 1);
-      hdr.ch_id    = hdr.ch_id | ((regval & RXBSIDL_EID_MASK) << 16);
+      regval     = RXREGVAL(MCP2515_RXB0SIDL);
+      hdr.ch_id  = hdr.ch_id | ((regval & RXBSIDL_EID_MASK) << 16);
 
       /* STD2 - STD0 */
 
-      hdr.ch_id = hdr.ch_id | ((regval >> 5) << 18);
+      hdr.ch_id  = hdr.ch_id | ((regval >> 5) << 18);
 
       /* STD10 - STD3 */
 
-      mcp2515_readregs(priv, MCP2515_RXB0SIDH + offset, ®val, 1);
-      hdr.ch_id = hdr.ch_id | (regval << 21);
+      regval     = RXREGVAL(MCP2515_RXB0SIDH);
+      hdr.ch_id  = hdr.ch_id | (regval << 21);
+
       hdr.ch_extid = true;
     }
   else
     {
       /* Save the standard ID of the newly received message */
 
-      mcp2515_readregs(priv, MCP2515_RXB0SIDH + offset, ®val, 1);
+      regval = RXREGVAL(MCP2515_RXB0SIDH);
       hdr.ch_id = regval;
-      mcp2515_readregs(priv, MCP2515_RXB0SIDL + offset, ®val, 1);
+
+      regval = RXREGVAL(MCP2515_RXB0SIDL);
       hdr.ch_id = (hdr.ch_id << 3) | (regval >> 5);
       hdr.ch_extid = false;
     }
@@ -2187,9 +2110,9 @@ static void mcp2515_receive(FAR struct can_dev_s *dev, uint8_t offset)
 
   /* Save the standard ID of the newly received message */
 
-  mcp2515_readregs(priv, MCP2515_RXB0SIDH + offset, ®val, 1);
+  regval    = RXREGVAL(MCP2515_RXB0SIDH);
   hdr.ch_id = regval;
-  mcp2515_readregs(priv, MCP2515_RXB0SIDL + offset, ®val, 1);
+  regval    = RXREGVAL(MCP2515_RXB0SIDL);
   hdr.ch_id = (hdr.ch_id << 3) | (regval >> 5);
 #endif
 
@@ -2200,19 +2123,17 @@ static void mcp2515_receive(FAR struct can_dev_s *dev, uint8_t offset)
 
   /* Extract the RTR bit */
 
-  mcp2515_readregs(priv, MCP2515_RXB0CTRL, ®val, 1);
+  regval = RXREGVAL(MCP2515_RXB0CTRL);
   hdr.ch_rtr = (regval & RXBCTRL_RXRTR) != 0;
 
   /* Get the DLC */
 
-  mcp2515_readregs(priv, MCP2515_RXB0DLC, ®val, 1);
+  regval = RXREGVAL(MCP2515_RXB0DLC);
   hdr.ch_dlc = (regval & RXBDLC_DLC_MASK) >> RXBDLC_DLC_SHIFT;
 
   /* Save the message data */
 
-  mcp2515_readregs(priv, MCP2515_RXB0D0, data, (uint8_t) hdr.ch_dlc);
-
-  ret = can_receive(dev, &hdr, (FAR uint8_t *) data);
+  ret = can_receive(dev, &hdr, (FAR uint8_t *) & RXREGVAL(MCP2515_RXB0D0));
 
   if (ret < 0)
     {
@@ -2242,7 +2163,8 @@ static int mcp2515_interrupt(FAR struct mcp2515_config_s *config,
   uint8_t ir;
   uint8_t ie;
   uint8_t pending;
-  bool    handled;
+  uint8_t clrmask;
+  bool handled;
 
   DEBUGASSERT(dev);
   priv = dev->cd_priv;
@@ -2255,11 +2177,16 @@ static int mcp2515_interrupt(FAR struct mcp2515_config_s *config,
     {
       /* Get the set of pending interrupts. */
 
-      mcp2515_readregs(priv, MCP2515_CANINTF, &ir, 1);
-      mcp2515_readregs(priv, MCP2515_CANINTE, &ie, 1);
+      mcp2515_read_2regs(priv, MCP2515_CANINTE, &ie, &ir);
 
       pending = (ir & ie);
       handled = false;
+      clrmask = 0;
+
+      if (pending == 0)
+        {
+          return OK;
+        }
 
       /* Check for any errors */
 
@@ -2267,8 +2194,8 @@ static int mcp2515_interrupt(FAR struct mcp2515_config_s *config,
         {
           /* Clear interrupt errors */
 
-          mcp2515_modifyreg(priv, MCP2515_CANINTF, MCP2515_ERROR_INTS,
-                            (uint8_t)~MCP2515_ERROR_INTS);
+          pending &= ~MCP2515_ERROR_INTS;
+          clrmask |= MCP2515_ERROR_INTS;
 
 #ifdef CONFIG_CAN_ERRORS
           /* Report errors */
@@ -2307,28 +2234,36 @@ static int mcp2515_interrupt(FAR struct mcp2515_config_s *config,
 
               /* Clear TX0 interrupt */
 
-              mcp2515_modifyreg(priv, MCP2515_CANINTF, MCP2515_INT_TX0,
-                                ~MCP2515_INT_TX0);
+              priv->txbuffers |= (1 << 0);
+              nxsem_post(&priv->txfsem);
+              pending &= ~MCP2515_INT_TX0;
+              clrmask |= MCP2515_INT_TX0;
             }
 
           if (pending & MCP2515_INT_TX1)
             {
               caninfo("TX1 is empty to transmit new message!\n");
 
+              priv->txbuffers |= (1 << 1);
+              nxsem_post(&priv->txfsem);
+
               /* Clear TX1 interrupt */
 
-              mcp2515_modifyreg(priv, MCP2515_CANINTF, MCP2515_INT_TX1,
-                                ~MCP2515_INT_TX1);
+              pending &= ~MCP2515_INT_TX1;
+              clrmask |= MCP2515_INT_TX1;
             }
 
           if (pending & MCP2515_INT_TX2)
             {
               caninfo("TX2 is empty to transmit new message!\n");
 
+              priv->txbuffers |= (1 << 2);
+              nxsem_post(&priv->txfsem);
+
               /* Clear TX2 interrupt */
 
-              mcp2515_modifyreg(priv, MCP2515_CANINTF, MCP2515_INT_TX2,
-                                ~MCP2515_INT_TX2);
+              pending &= ~MCP2515_INT_TX2;
+              clrmask |= MCP2515_INT_TX2;
             }
 
           handled = true;
@@ -2343,11 +2278,8 @@ static int mcp2515_interrupt(FAR struct mcp2515_config_s *config,
         }
       else if ((pending & priv->txints) != 0)
         {
-#if 0
           /* Clear unhandled TX events */
 
-          mcp2515_putreg(priv, MCP2515_IR_OFFSET, priv->txints);
-#endif
           handled = true;
         }
 
@@ -2366,8 +2298,8 @@ static int mcp2515_interrupt(FAR struct mcp2515_config_s *config,
 
               /* Clear RX0 interrupt */
 
-              mcp2515_modifyreg(priv, MCP2515_CANINTF, MCP2515_INT_RX0,
-                                ~MCP2515_INT_RX0);
+              pending &= ~MCP2515_INT_RX0;
+              clrmask |= MCP2515_INT_RX0;
             }
           else
             {
@@ -2377,8 +2309,8 @@ static int mcp2515_interrupt(FAR struct mcp2515_config_s *config,
 
                   /* Clear RX1 interrupt */
 
-                  mcp2515_modifyreg(priv, MCP2515_CANINTF, MCP2515_INT_RX1,
-                                    ~MCP2515_INT_RX1);
+                  pending &= ~MCP2515_INT_RX1;
+                  clrmask |= MCP2515_INT_RX1;
                 }
             }
 
@@ -2386,6 +2318,8 @@ static int mcp2515_interrupt(FAR struct mcp2515_config_s *config,
 
           handled = true;
         }
+
+      mcp2515_modifyreg(priv, MCP2515_CANINTF, clrmask, pending);
     }
   while (handled);
 
@@ -2545,7 +2479,7 @@ FAR struct mcp2515_can_s *
 
   /* Setup SPI frequency and mode */
 
-  SPI_SETFREQUENCY(config->spi, MCP2515_SPI_FREQUENCY);
+  SPI_SETFREQUENCY(config->spi, CONFIG_MCP2515_SPI_SCK_FREQUENCY);
   SPI_SETMODE(config->spi, MCP2515_SPI_MODE);
   SPI_SETBITS(config->spi, 8);
   (void)SPI_HWFEATURES(config->spi, 0);
@@ -2555,19 +2489,21 @@ FAR struct mcp2515_can_s *
   memset(priv, 0, sizeof(struct mcp2515_can_s));
   priv->config = config;
 
-#if 0
+  priv->spi_txbuf = kmm_zalloc(SPI_TRANSFER_BUF_LEN);
+  priv->spi_rxbuf = kmm_zalloc(SPI_TRANSFER_BUF_LEN);
+
   /* Set the initial bit timing.  This might change subsequently
    * due to IOCTL command processing.
    */
 
-  priv->btp    = config->btp;
-  priv->fbtp   = config->fbtp;
-#endif
-
   /* Initialize semaphores */
 
   nxsem_init(&priv->locksem, 0, 1);
-  nxsem_init(&priv->txfsem, 0, config->ntxbuffers);
+  nxsem_init(&priv->txfsem, 0, MCP2515_NUM_TX_BUFFERS);
+
+  /* Initialize bitmask */
+
+  priv->txbuffers = (1 << MCP2515_NUM_TX_BUFFERS)-1;
 
   /* And put the hardware in the initial state */
 
diff --git a/drivers/can/mcp2515.h b/drivers/can/mcp2515.h
index 67178c494d2..3fb2134800d 100644
--- a/drivers/can/mcp2515.h
+++ b/drivers/can/mcp2515.h
@@ -208,7 +208,6 @@
 
 #define TXBSIDH_SID_MASK     0xff     /* Standard Identifier bits <10:3> */
 
-
 /* TXBnSIDL – TRANSMIT BUFFER n STANDARD IDENTIFIER LOW */
 
 #define TXBSIDL_SID_SHIFT    (5)      /* Bits 5-7: Standard Identifier bits <2:0> */
@@ -217,7 +216,6 @@
 #define TXBSIDL_EID_SHIFT    (0)      /* Bits 0-1: Extended Identifier bits <17:16> */
 #define TXBSIDL_EID_MASK     (0x03 << TXBSIDL_EID_MASK)
 
-
 /* TXBnEID8 – TRANSMIT BUFFER n EXTENDED IDENTIFIER HIGH */
 
 #define TXBEID8_EID_MASK     0xff     /* Bits 0-7: Extended Identifier bits <15:8> */
@@ -260,8 +258,9 @@
                                       /* Bit 7: Not used */
 
 /* N.B.: In the datasheet DS21801D the file RXM of RXBnCTRL could to assume
-         the value 01 and 10 to receive only STD or EXT msgs respectively.
-         But in a more recent datasheet DS20001801H it was removed. */
+ *       the value 01 and 10 to receive only STD or EXT msgs respectively.
+ *       But in a more recent datasheet DS20001801H it was removed.
+ */
 
 /* RXB1CTRL – RECEIVE BUFFER 1 CONTROL */
 
@@ -421,9 +420,12 @@
 #define MCP2515_LOAD_TX0     0x40
 #define MCP2515_LOAD_TX1     0x42
 #define MCP2515_LOAD_TX2     0x44
+#define MCP2515_LOAD_TXB(n)  (0x40 + 2 * (n))
+#define MCP2515_READ_RXB(n)  (((n) == 0) ? 0x90 : 0x94)
 #define MCP2515_RTS_TX0      0x81
 #define MCP2515_RTS_TX1      0x82
 #define MCP2515_RTS_TX2      0x84
+#define MCP2515_RTS(x)       (0x81+x)
 #define MCP2515_RTS_ALL      0x87
 #define MCP2515_READ_STATUS  0xA0
 #define MCP2515_RX_STATUS    0xB0
diff --git a/drivers/contactless/mfrc522.c b/drivers/contactless/mfrc522.c
index 0721624e4c8..610551b1aa3 100644
--- a/drivers/contactless/mfrc522.c
+++ b/drivers/contactless/mfrc522.c
@@ -138,13 +138,11 @@ static const struct file_operations g_mfrc522fops =
   mfrc522_close,
   mfrc522_read,
   mfrc522_write,
-  0,
-  mfrc522_ioctl
-#ifndef CONFIG_DISABLE_POLL
-    , 0
-#endif
+  NULL,
+  mfrc522_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
-    , 0
+  , NULL
 #endif
 };
 
diff --git a/drivers/contactless/pn532.c b/drivers/contactless/pn532.c
index e7df69b2717..60bc2edeca6 100644
--- a/drivers/contactless/pn532.c
+++ b/drivers/contactless/pn532.c
@@ -137,13 +137,11 @@ static const struct file_operations g_pn532fops =
   _close,
   _read,
   _write,
-  0,
-  _ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , 0
-#endif
+  NULL,
+  _ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
-  , 0
+  , NULL
 #endif
 };
 
diff --git a/drivers/crypto/dev_urandom.c b/drivers/crypto/dev_urandom.c
index 1ee6fc13458..77778e70d5a 100644
--- a/drivers/crypto/dev_urandom.c
+++ b/drivers/crypto/dev_urandom.c
@@ -100,10 +100,8 @@ static ssize_t devurand_read(FAR struct file *filep, FAR char *buffer,
                              size_t buflen);
 static ssize_t devurand_write(FAR struct file *filep, FAR const char *buffer,
                               size_t buflen);
-#ifndef CONFIG_DISABLE_POLL
 static int devurand_poll(FAR struct file *filep, FAR struct pollfd *fds,
                          bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -116,10 +114,8 @@ static const struct file_operations g_urand_fops =
   devurand_read,                /* read */
   devurand_write,               /* write */
   NULL,                         /* seek */
-  NULL                          /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , devurand_poll               /* poll */
-#endif
+  NULL,                         /* ioctl */
+  devurand_poll                 /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL                        /* unlink */
 #endif
@@ -304,7 +300,6 @@ static ssize_t devurand_write(FAR struct file *filep, FAR const char *buffer,
  * Name: devurand_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int devurand_poll(FAR struct file *filep, FAR struct pollfd *fds,
                          bool setup)
 {
@@ -319,7 +314,6 @@ static int devurand_poll(FAR struct file *filep, FAR struct pollfd *fds,
 
   return OK;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/dev_null.c b/drivers/dev_null.c
index af882d49b65..d5aadc7262c 100644
--- a/drivers/dev_null.c
+++ b/drivers/dev_null.c
@@ -57,10 +57,8 @@ static ssize_t devnull_read(FAR struct file *filep, FAR char *buffer,
                  size_t buflen);
 static ssize_t devnull_write(FAR struct file *filep, FAR const char *buffer,
                  size_t buflen);
-#ifndef CONFIG_DISABLE_POLL
 static int     devnull_poll(FAR struct file *filep, FAR struct pollfd *fds,
                  bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -73,10 +71,8 @@ static const struct file_operations devnull_fops =
   devnull_read,  /* read */
   devnull_write, /* write */
   NULL,          /* seek */
-  NULL           /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , devnull_poll /* poll */
-#endif
+  NULL,          /* ioctl */
+  devnull_poll   /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL         /* unlink */
 #endif
@@ -108,7 +104,6 @@ static ssize_t devnull_write(FAR struct file *filep, FAR const char *buffer, siz
  * Name: devnull_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int devnull_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup)
 {
@@ -123,7 +118,6 @@ static int devnull_poll(FAR struct file *filep, FAR struct pollfd *fds,
 
   return OK;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/dev_zero.c b/drivers/dev_zero.c
index 5f836bb58e1..4fe39fb9dd8 100644
--- a/drivers/dev_zero.c
+++ b/drivers/dev_zero.c
@@ -57,10 +57,8 @@ static ssize_t devzero_read(FAR struct file *filep, FAR char *buffer,
                  size_t buflen);
 static ssize_t devzero_write(FAR struct file *filep, FAR const char *buffer,
                  size_t buflen);
-#ifndef CONFIG_DISABLE_POLL
 static int     devzero_poll(FAR struct file *filep, FAR struct pollfd *fds,
                  bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -73,10 +71,8 @@ static const struct file_operations devzero_fops =
   devzero_read,  /* read */
   devzero_write, /* write */
   NULL,          /* seek */
-  NULL           /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , devzero_poll /* poll */
-#endif
+  NULL,          /* ioctl */
+  devzero_poll   /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL         /* unlink */
 #endif
@@ -111,7 +107,6 @@ static ssize_t devzero_write(FAR struct file *filep, FAR const char *buffer,
  * Name: devzero_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int devzero_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup)
 {
@@ -125,7 +120,6 @@ static int devzero_poll(FAR struct file *filep, FAR struct pollfd *fds,
     }
   return OK;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/eeprom/i2c_xx24xx.c b/drivers/eeprom/i2c_xx24xx.c
index 23337379099..982bb7f89c9 100644
--- a/drivers/eeprom/i2c_xx24xx.c
+++ b/drivers/eeprom/i2c_xx24xx.c
@@ -206,10 +206,8 @@ static const struct file_operations ee24xx_fops =
   ee24xx_read,  /* read */
   ee24xx_write, /* write */
   ee24xx_seek,  /* seek */
-  ee24xx_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0           /* poll */
-#endif
+  ee24xx_ioctl, /* ioctl */
+  NULL          /* poll */
 };
 
 /****************************************************************************
diff --git a/drivers/eeprom/spi_xx25xx.c b/drivers/eeprom/spi_xx25xx.c
index 4b76d1a111e..3bbc74c8251 100644
--- a/drivers/eeprom/spi_xx25xx.c
+++ b/drivers/eeprom/spi_xx25xx.c
@@ -254,10 +254,8 @@ static const struct file_operations ee25xx_fops =
   ee25xx_read,  /* read */
   ee25xx_write, /* write */
   ee25xx_seek,  /* seek */
-  ee25xx_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0           /* poll */
-#endif
+  ee25xx_ioctl, /* ioctl */
+  NULL          /* poll */
 };
 
 /****************************************************************************
diff --git a/drivers/i2c/i2c_driver.c b/drivers/i2c/i2c_driver.c
index 9a3e659d9df..422b8651d48 100644
--- a/drivers/i2c/i2c_driver.c
+++ b/drivers/i2c/i2c_driver.c
@@ -106,16 +106,14 @@ static const struct file_operations i2cdrvr_fops =
   i2cdrvr_open,    /* open */
   i2cdrvr_close,   /* close */
 #else
-  0,               /* open */
-  0,               /* close */
+  NULL,            /* open */
+  NULL,            /* close */
 #endif
   i2cdrvr_read,    /* read */
   i2cdrvr_write,   /* write */
-  0,               /* seek */
-  i2cdrvr_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0              /* poll */
-#endif
+  NULL,            /* seek */
+  i2cdrvr_ioctl,   /* ioctl */
+  NULL             /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , i2cdrvr_unlink /* unlink */
 #endif
@@ -241,7 +239,7 @@ static int i2cdrvr_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
   FAR struct i2c_transfer_s *transfer;
   int ret;
 
-  i2cinfo("cmd=%d arg=%lu\n", cmd, arg);
+  i2cinfo("cmd=%x arg=%08x\n", cmd, arg);
 
   /* Get our private data structure */
 
diff --git a/drivers/i2s/i2schar.c b/drivers/i2s/i2schar.c
index d8031a215ce..21f37ac0552 100644
--- a/drivers/i2s/i2schar.c
+++ b/drivers/i2s/i2schar.c
@@ -117,9 +117,7 @@ static const struct file_operations i2schar_fops =
   i2schar_write,        /* write */
   NULL,                 /* seek  */
   i2schar_ioctl,        /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
   NULL,                 /* poll  */
-#endif
 };
 
 /****************************************************************************
diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig
index 645312fba21..090f4f52b46 100644
--- a/drivers/input/Kconfig
+++ b/drivers/input/Kconfig
@@ -51,7 +51,6 @@ config TSC2007_MULTIPLE
 config TSC2007_NPOLLWAITERS
 	int "Number TSC2007 poll waiters"
 	default 4
-	depends on !DISABLE_POLL
 	---help---
 		Maximum number of threads that can be waiting on poll()
 
@@ -125,7 +124,6 @@ endif # FT5X06_SINGLEPOINT
 config FT5X06_NPOLLWAITERS
 	int "Number FT5336/FT5x06 poll waiters"
 	default 4
-	depends on !DISABLE_POLL
 	---help---
 		Maximum number of threads that can be waiting on poll()
 
@@ -151,7 +149,6 @@ config ADS7843E_MULTIPLE
 config ADS7843E_NPOLLWAITERS
 	int "Number poll waiters"
 	default 4
-	depends on !DISABLE_POLL
 	---help---
 		Maximum number of threads that can be waiting on poll()
 
@@ -246,7 +243,6 @@ config MXT_THRESHY
 config MXT_NPOLLWAITERS
 	int "Number poll waiters"
 	default 4
-	depends on !DISABLE_POLL
 	---help---
 		Maximum number of threads that can be waiting on poll()
 
@@ -320,7 +316,6 @@ config STMPE811_MULTIPLE
 config STMPE811_NPOLLWAITERS
 	int "Number poll waiters"
 	default 4
-	depends on !DISABLE_POLL
 	---help---
 		Maximum number of threads that can be waiting on poll()
 
@@ -459,7 +454,6 @@ config BUTTONS_LOWER
 config BUTTONS_NPOLLWAITERS
 	int "Max Number of Poll Waiters"
 	default 2
-	depends on !DISABLE_POLL
 
 endif # BUTTONS
 
@@ -478,7 +472,6 @@ if DJOYSTICK
 config DJOYSTICK_NPOLLWAITERS
 	int "Max Number of Poll Waiters"
 	default 2
-	depends on !DISABLE_POLL
 
 endif # DJOYSTICK
 
@@ -497,7 +490,6 @@ if AJOYSTICK
 config AJOYSTICK_NPOLLWAITERS
 	int "Max Number of Poll Waiters"
 	default 2
-	depends on !DISABLE_POLL
 
 endif # AJOYSTICK
 
@@ -516,6 +508,5 @@ if INPUT_NUNCHUCK
 config NUNCHUCK_NPOLLWAITERS
 	int "Max Number of Poll Waiters"
 	default 2
-	depends on !DISABLE_POLL
 
 endif # INPUT_NUNCHUCK
diff --git a/drivers/input/ads7843e.c b/drivers/input/ads7843e.c
index f7c747f7aeb..eb25551eb2e 100644
--- a/drivers/input/ads7843e.c
+++ b/drivers/input/ads7843e.c
@@ -119,9 +119,7 @@ static int ads7843e_open(FAR struct file *filep);
 static int ads7843e_close(FAR struct file *filep);
 static ssize_t ads7843e_read(FAR struct file *filep, FAR char *buffer, size_t len);
 static int ads7843e_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int ads7843e_poll(FAR struct file *filep, struct pollfd *fds, bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -136,10 +134,8 @@ static const struct file_operations ads7843e_fops =
   ads7843e_read,    /* read */
   0,                /* write */
   0,                /* seek */
-  ads7843e_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , ads7843e_poll   /* poll */
-#endif
+  ads7843e_ioctl,   /* ioctl */
+  ads7843e_poll     /* poll */
 };
 
 /* If only a single ADS7843E device is supported, then the driver state
@@ -292,9 +288,7 @@ static uint16_t ads7843e_sendcmd(FAR struct ads7843e_dev_s *priv, uint8_t cmd)
 
 static void ads7843e_notify(FAR struct ads7843e_dev_s *priv)
 {
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   /* If there are threads waiting for read data, then signal one of them
    * that the read data is available.
@@ -315,7 +309,6 @@ static void ads7843e_notify(FAR struct ads7843e_dev_s *priv)
    * then some make end up blocking after all.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   for (i = 0; i < CONFIG_ADS7843E_NPOLLWAITERS; i++)
     {
       struct pollfd *fds = priv->fds[i];
@@ -326,7 +319,6 @@ static void ads7843e_notify(FAR struct ads7843e_dev_s *priv)
           nxsem_post(fds->sem);
         }
     }
-#endif
 }
 
 /****************************************************************************
@@ -1035,7 +1027,6 @@ static int ads7843e_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: ads7843e_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int ads7843e_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup)
 {
@@ -1121,11 +1112,6 @@ errout:
   nxsem_post(&priv->devsem);
   return ret;
 }
-#endif
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/input/ads7843e.h b/drivers/input/ads7843e.h
index 84e3169680d..e2f341dd61b 100644
--- a/drivers/input/ads7843e.h
+++ b/drivers/input/ads7843e.h
@@ -156,9 +156,7 @@ struct ads7843e_dev_s
    * retained in the f_priv field of the 'struct file'.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_ADS7843E_NPOLLWAITERS];
-#endif
 };
 
 /********************************************************************************************
diff --git a/drivers/input/ajoystick.c b/drivers/input/ajoystick.c
index bc83f0d2260..8a237adf72e 100644
--- a/drivers/input/ajoystick.c
+++ b/drivers/input/ajoystick.c
@@ -100,15 +100,12 @@ struct ajoy_open_s
 
   volatile bool ao_closing;
 
-#ifndef CONFIG_DISABLE_SIGNALS
   /* Joystick event notification information */
 
   pid_t ao_pid;
   struct ajoy_notify_s ao_notify;
   struct sigwork_s ao_work;
-#endif
 
-#ifndef CONFIG_DISABLE_POLL
   /* Poll event information */
 
   struct ajoy_pollevents_s ao_pollevents;
@@ -118,7 +115,6 @@ struct ajoy_open_s
    */
 
   FAR struct pollfd *ao_fds[CONFIG_AJOYSTICK_NPOLLWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -132,11 +128,9 @@ static inline int ajoy_takesem(sem_t *sem);
 
 /* Sampling and Interrupt handling */
 
-#if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
 static void    ajoy_enable(FAR struct ajoy_upperhalf_s *priv);
 static void    ajoy_interrupt(FAR const struct ajoy_lowerhalf_s *lower,
                               FAR void *arg);
-#endif
 
 /* Sampling */
 
@@ -150,10 +144,8 @@ static ssize_t ajoy_read(FAR struct file *filep, FAR char *buffer,
                          size_t buflen);
 static int     ajoy_ioctl(FAR struct file *filep, int cmd,
                           unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int     ajoy_poll(FAR struct file *filep, FAR struct pollfd *fds,
                          bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -166,10 +158,8 @@ static const struct file_operations ajoy_fops =
   ajoy_read,  /* read */
   0,          /* write */
   0,          /* seek */
-  ajoy_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , ajoy_poll /* poll */
-#endif
+  ajoy_ioctl, /* ioctl */
+  ajoy_poll   /* poll */
 };
 
 /****************************************************************************
@@ -200,7 +190,6 @@ static inline int ajoy_takesem(sem_t *sem)
  * Name: ajoy_enable
  ****************************************************************************/
 
-#if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
 static void ajoy_enable(FAR struct ajoy_upperhalf_s *priv)
 {
   FAR const struct ajoy_lowerhalf_s *lower;
@@ -208,9 +197,7 @@ static void ajoy_enable(FAR struct ajoy_upperhalf_s *priv)
   ajoy_buttonset_t press;
   ajoy_buttonset_t release;
   irqstate_t flags;
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   DEBUGASSERT(priv);
   lower = priv->au_lower;
@@ -229,7 +216,6 @@ static void ajoy_enable(FAR struct ajoy_upperhalf_s *priv)
 
   for (opriv = priv->au_open; opriv; opriv = opriv->ao_flink)
     {
-#ifndef CONFIG_DISABLE_POLL
       /* Are there any poll waiters? */
 
       for (i = 0; i < CONFIG_AJOYSTICK_NPOLLWAITERS; i++)
@@ -243,14 +229,11 @@ static void ajoy_enable(FAR struct ajoy_upperhalf_s *priv)
               break;
             }
         }
-#endif
 
-#ifndef CONFIG_DISABLE_SIGNALS
       /* OR in the signal events */
 
       press   |= opriv->ao_notify.an_press;
       release |= opriv->ao_notify.an_release;
-#endif
     }
 
   /* Enable/disable button interrupts */
@@ -272,13 +255,11 @@ static void ajoy_enable(FAR struct ajoy_upperhalf_s *priv)
 
   leave_critical_section(flags);
 }
-#endif
 
 /****************************************************************************
  * Name: ajoy_interrupt
  ****************************************************************************/
 
-#if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
 static void ajoy_interrupt(FAR const struct ajoy_lowerhalf_s *lower,
                            FAR void *arg)
 {
@@ -290,7 +271,6 @@ static void ajoy_interrupt(FAR const struct ajoy_lowerhalf_s *lower,
 
   ajoy_sample(priv);
 }
-#endif
 
 /****************************************************************************
  * Name: ajoy_sample
@@ -301,15 +281,11 @@ static void ajoy_sample(FAR struct ajoy_upperhalf_s *priv)
   FAR const struct ajoy_lowerhalf_s *lower;
   FAR struct ajoy_open_s *opriv;
   ajoy_buttonset_t sample;
-#if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
   ajoy_buttonset_t change;
   ajoy_buttonset_t press;
   ajoy_buttonset_t release;
-#endif
   irqstate_t flags;
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   DEBUGASSERT(priv);
   lower = priv->au_lower;
@@ -328,7 +304,6 @@ static void ajoy_sample(FAR struct ajoy_upperhalf_s *priv)
 
   add_ui_randomness(sample);
 
-#if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
   /* Determine which buttons have been newly pressed and which have been
    * newly released.
    */
@@ -343,7 +318,6 @@ static void ajoy_sample(FAR struct ajoy_upperhalf_s *priv)
 
   for (opriv = priv->au_open; opriv; opriv = opriv->ao_flink)
     {
-#ifndef CONFIG_DISABLE_POLL
       /* Have any poll events occurred? */
 
       if ((press & opriv->ao_pollevents.ap_press)     != 0 ||
@@ -365,9 +339,7 @@ static void ajoy_sample(FAR struct ajoy_upperhalf_s *priv)
                 }
             }
         }
-#endif
 
-#ifndef CONFIG_DISABLE_SIGNALS
       /* Have any signal events occurred? */
 
       if ((press & opriv->ao_notify.an_press)     != 0 ||
@@ -379,13 +351,11 @@ static void ajoy_sample(FAR struct ajoy_upperhalf_s *priv)
           nxsig_notification(opriv->ao_pid, &opriv->ao_notify.an_event,
                              SI_QUEUE, &opriv->ao_work);
         }
-#endif
     }
 
   /* Enable/disable interrupt handling */
 
   ajoy_enable(priv);
-#endif
 
   priv->au_sample = sample;
   leave_critical_section(flags);
@@ -400,10 +370,8 @@ static int ajoy_open(FAR struct file *filep)
   FAR struct inode *inode;
   FAR struct ajoy_upperhalf_s *priv;
   FAR struct ajoy_open_s *opriv;
-#ifndef CONFIG_DISABLE_POLL
   FAR const struct ajoy_lowerhalf_s *lower;
   ajoy_buttonset_t supported;
-#endif
   int ret;
 
   DEBUGASSERT(filep && filep->f_inode);
@@ -432,14 +400,12 @@ static int ajoy_open(FAR struct file *filep)
 
   /* Initialize the open structure */
 
-#ifndef CONFIG_DISABLE_POLL
   lower = priv->au_lower;
   DEBUGASSERT(lower && lower->al_supported);
   supported = lower->al_supported(lower);
 
   opriv->ao_pollevents.ap_press   = supported;
   opriv->ao_pollevents.ap_release = supported;
-#endif
 
   /* Attach the open structure to the device */
 
@@ -658,7 +624,6 @@ static int ajoy_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
       }
       break;
 
-#ifndef CONFIG_DISABLE_POLL
     /* Command:     AJOYIOC_POLLEVENTS
      * Description: Specify the set of button events that can cause a poll()
      *              to awaken.  The default is all button depressions and
@@ -688,9 +653,7 @@ static int ajoy_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
           }
       }
       break;
-#endif
 
-#ifndef CONFIG_DISABLE_SIGNALS
     /* Command:     AJOYIOC_REGISTER
      * Description: Register to receive a signal whenever there is a change
      *              in any of the joystick discrete inputs.  This feature,
@@ -723,7 +686,6 @@ static int ajoy_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
           }
       }
       break;
-#endif
 
     default:
       ierr("ERROR: Unrecognized command: %ld\n", cmd);
@@ -739,7 +701,6 @@ static int ajoy_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: ajoy_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int ajoy_poll(FAR struct file *filep, FAR struct pollfd *fds,
                      bool setup)
 {
@@ -819,7 +780,6 @@ errout_with_dusem:
   ajoy_givesem(&priv->au_exclsem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/input/button_upper.c b/drivers/input/button_upper.c
index 6e293fdac67..2c62ece45e5 100644
--- a/drivers/input/button_upper.c
+++ b/drivers/input/button_upper.c
@@ -96,15 +96,12 @@ struct btn_open_s
 
   volatile bool bo_closing;
 
-#ifndef CONFIG_DISABLE_SIGNALS
   /* Button event notification information */
 
   pid_t bo_pid;
   struct btn_notify_s bo_notify;
   struct sigwork_s bo_work;
-#endif
 
-#ifndef CONFIG_DISABLE_POLL
   /* Poll event information */
 
   struct btn_pollevents_s bo_pollevents;
@@ -114,7 +111,6 @@ struct btn_open_s
    */
 
   FAR struct pollfd *bo_fds[CONFIG_BUTTONS_NPOLLWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -128,11 +124,9 @@ static inline int btn_takesem(sem_t *sem);
 
 /* Sampling and Interrupt handling */
 
-#if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
 static void    btn_enable(FAR struct btn_upperhalf_s *priv);
 static void    btn_interrupt(FAR const struct btn_lowerhalf_s *lower,
                              FAR void *arg);
-#endif
 
 /* Sampling */
 
@@ -146,10 +140,8 @@ static ssize_t btn_read(FAR struct file *filep, FAR char *buffer,
                         size_t buflen);
 static int     btn_ioctl(FAR struct file *filep, int cmd,
                          unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int     btn_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -162,10 +154,8 @@ static const struct file_operations btn_fops =
   btn_read,  /* read */
   NULL,      /* write */
   NULL,      /* seek */
-  btn_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , btn_poll /* poll */
-#endif
+  btn_ioctl, /* ioctl */
+  btn_poll   /* poll */
 };
 
 /****************************************************************************
@@ -196,7 +186,6 @@ static inline int btn_takesem(sem_t *sem)
  * Name: btn_enable
  ****************************************************************************/
 
-#if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
 static void btn_enable(FAR struct btn_upperhalf_s *priv)
 {
   FAR const struct btn_lowerhalf_s *lower;
@@ -221,19 +210,15 @@ static void btn_enable(FAR struct btn_upperhalf_s *priv)
 
   for (opriv = priv->bu_open; opriv; opriv = opriv->bo_flink)
     {
-#ifndef CONFIG_DISABLE_POLL
       /* OR in the poll event buttons */
 
       press   |= opriv->bo_pollevents.bp_press;
       release |= opriv->bo_pollevents.bp_release;
-#endif
 
-#ifndef CONFIG_DISABLE_SIGNALS
       /* OR in the signal events */
 
       press   |= opriv->bo_notify.bn_press;
       release |= opriv->bo_notify.bn_release;
-#endif
     }
 
   /* Enable/disable button interrupts */
@@ -255,13 +240,11 @@ static void btn_enable(FAR struct btn_upperhalf_s *priv)
 
   leave_critical_section(flags);
 }
-#endif
 
 /****************************************************************************
  * Name: btn_interrupt
  ****************************************************************************/
 
-#if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
 static void btn_interrupt(FAR const struct btn_lowerhalf_s *lower,
                           FAR void *arg)
 {
@@ -273,7 +256,6 @@ static void btn_interrupt(FAR const struct btn_lowerhalf_s *lower,
 
   btn_sample(priv);
 }
-#endif
 
 /****************************************************************************
  * Name: btn_sample
@@ -284,15 +266,11 @@ static void btn_sample(FAR struct btn_upperhalf_s *priv)
   FAR const struct btn_lowerhalf_s *lower;
   FAR struct btn_open_s *opriv;
   btn_buttonset_t sample;
-#if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
   btn_buttonset_t change;
   btn_buttonset_t press;
   btn_buttonset_t release;
-#endif
   irqstate_t flags;
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   DEBUGASSERT(priv && priv->bu_lower);
   lower = priv->bu_lower;
@@ -310,7 +288,6 @@ static void btn_sample(FAR struct btn_upperhalf_s *priv)
 
   add_ui_randomness(sample);
 
-#if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
   /* Determine which buttons have been newly pressed and which have been
    * newly released.
    */
@@ -325,7 +302,6 @@ static void btn_sample(FAR struct btn_upperhalf_s *priv)
 
   for (opriv = priv->bu_open; opriv; opriv = opriv->bo_flink)
     {
-#ifndef CONFIG_DISABLE_POLL
       /* Have any poll events occurred? */
 
       if ((press & opriv->bo_pollevents.bp_press)     != 0 ||
@@ -347,9 +323,7 @@ static void btn_sample(FAR struct btn_upperhalf_s *priv)
                 }
             }
         }
-#endif
 
-#ifndef CONFIG_DISABLE_SIGNALS
       /* Have any signal events occurred? */
 
       if ((press & opriv->bo_notify.bn_press)     != 0 ||
@@ -361,13 +335,11 @@ static void btn_sample(FAR struct btn_upperhalf_s *priv)
           nxsig_notification(opriv->bo_pid, &opriv->bo_notify.bn_event,
                              SI_QUEUE, &opriv->bo_work);
         }
-#endif
     }
 
   /* Enable/disable interrupt handling */
 
   btn_enable(priv);
-#endif
 
   priv->bu_sample = sample;
   leave_critical_section(flags);
@@ -382,10 +354,8 @@ static int btn_open(FAR struct file *filep)
   FAR struct inode *inode;
   FAR struct btn_upperhalf_s *priv;
   FAR struct btn_open_s *opriv;
-#ifndef CONFIG_DISABLE_POLL
   FAR const struct btn_lowerhalf_s *lower;
   btn_buttonset_t supported;
-#endif
   int ret;
 
   DEBUGASSERT(filep && filep->f_inode);
@@ -414,14 +384,12 @@ static int btn_open(FAR struct file *filep)
 
   /* Initialize the open structure */
 
-#ifndef CONFIG_DISABLE_POLL
   lower = priv->bu_lower;
   DEBUGASSERT(lower && lower->bl_supported);
   supported = lower->bl_supported(lower);
 
   opriv->bo_pollevents.bp_press   = supported;
   opriv->bo_pollevents.bp_release = supported;
-#endif
 
   /* Attach the open structure to the device */
 
@@ -641,7 +609,6 @@ static int btn_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
       }
       break;
 
-#ifndef CONFIG_DISABLE_POLL
     /* Command:     BTNIOC_POLLEVENTS
      * Description: Specify the set of button events that can cause a poll()
      *              to awaken.  The default is all button depressions and
@@ -671,9 +638,7 @@ static int btn_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
           }
       }
       break;
-#endif
 
-#ifndef CONFIG_DISABLE_SIGNALS
     /* Command:     BTNIOC_REGISTER
      * Description: Register to receive a signal whenever there is a change
      *              in any of the discrete buttone inputs.  This feature,
@@ -706,7 +671,6 @@ static int btn_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
           }
       }
       break;
-#endif
 
     default:
       ierr("ERROR: Unrecognized command: %ld\n", cmd);
@@ -722,7 +686,6 @@ static int btn_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: btn_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int btn_poll(FAR struct file *filep, FAR struct pollfd *fds,
                     bool setup)
 {
@@ -803,7 +766,6 @@ errout_with_dusem:
   btn_givesem(&priv->bu_exclsem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/input/cypress_mbr3108.c b/drivers/input/cypress_mbr3108.c
index dc103b8c682..bebd408be38 100644
--- a/drivers/input/cypress_mbr3108.c
+++ b/drivers/input/cypress_mbr3108.c
@@ -210,9 +210,7 @@ struct mbr3108_dev_s
   struct mbr3108_debug_conf_s debug_conf;
   bool int_pending;
 
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_INPUT_CYPRESS_MBR3108_NPOLLWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -225,10 +223,8 @@ static ssize_t mbr3108_read(FAR struct file *filep, FAR char *buffer,
                             size_t buflen);
 static ssize_t mbr3108_write(FAR struct file *filep, FAR const char *buffer,
                              size_t buflen);
-#ifndef CONFIG_DISABLE_POLL
 static int mbr3108_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup);
-#endif
 
 /****************************************************************************
 * Private Data
@@ -240,11 +236,9 @@ static const struct file_operations g_mbr3108_fileops =
   mbr3108_close,  /* close */
   mbr3108_read,   /* read */
   mbr3108_write,  /* write */
-  0,              /* seek */
-  0               /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , mbr3108_poll  /* poll */
-#endif
+  NULL,           /* seek */
+  NULL,           /* ioctl */
+  mbr3108_poll    /* poll */
 };
 
 /****************************************************************************
@@ -1006,8 +1000,6 @@ static int mbr3108_close(FAR struct file *filep)
   return 0;
 }
 
-#ifndef CONFIG_DISABLE_POLL
-
 static void mbr3108_poll_notify(FAR struct mbr3108_dev_s *priv)
 {
   int i;
@@ -1108,8 +1100,6 @@ out:
   return ret;
 }
 
-#endif /* !CONFIG_DISABLE_POLL */
-
 static int mbr3108_isr_handler(int irq, FAR void *context, FAR void *arg)
 {
   FAR struct mbr3108_dev_s *priv = (FAR struct mbr3108_dev_s *)arg;
@@ -1121,9 +1111,7 @@ static int mbr3108_isr_handler(int irq, FAR void *context, FAR void *arg)
   priv->int_pending = true;
   leave_critical_section(flags);
 
-#ifndef CONFIG_DISABLE_POLL
   mbr3108_poll_notify(priv);
-#endif
   return 0;
 }
 
diff --git a/drivers/input/djoystick.c b/drivers/input/djoystick.c
index 7955fff5110..2d4d9687680 100644
--- a/drivers/input/djoystick.c
+++ b/drivers/input/djoystick.c
@@ -100,15 +100,12 @@ struct djoy_open_s
 
   volatile bool do_closing;
 
-#ifndef CONFIG_DISABLE_SIGNALS
   /* Joystick event notification information */
 
   pid_t do_pid;
   struct djoy_notify_s do_notify;
   struct sigwork_s do_work;
-#endif
 
-#ifndef CONFIG_DISABLE_POLL
   /* Poll event information */
 
   struct djoy_pollevents_s do_pollevents;
@@ -118,7 +115,6 @@ struct djoy_open_s
    */
 
   FAR struct pollfd *do_fds[CONFIG_DJOYSTICK_NPOLLWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -132,11 +128,9 @@ static inline int djoy_takesem(sem_t *sem);
 
 /* Sampling and Interrupt handling */
 
-#if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
 static void    djoy_enable(FAR struct djoy_upperhalf_s *priv);
 static void    djoy_interrupt(FAR const struct djoy_lowerhalf_s *lower,
                               FAR void *arg);
-#endif
 
 /* Sampling */
 
@@ -150,10 +144,8 @@ static ssize_t djoy_read(FAR struct file *filep, FAR char *buffer,
                          size_t buflen);
 static int     djoy_ioctl(FAR struct file *filep, int cmd,
                           unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int     djoy_poll(FAR struct file *filep, FAR struct pollfd *fds,
                          bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -166,10 +158,8 @@ static const struct file_operations djoy_fops =
   djoy_read,  /* read */
   0,          /* write */
   0,          /* seek */
-  djoy_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , djoy_poll /* poll */
-#endif
+  djoy_ioctl, /* ioctl */
+  djoy_poll   /* poll */
 };
 
 /****************************************************************************
@@ -200,7 +190,6 @@ static inline int djoy_takesem(sem_t *sem)
  * Name: djoy_enable
  ****************************************************************************/
 
-#if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
 static void djoy_enable(FAR struct djoy_upperhalf_s *priv)
 {
   FAR const struct djoy_lowerhalf_s *lower;
@@ -208,9 +197,7 @@ static void djoy_enable(FAR struct djoy_upperhalf_s *priv)
   djoy_buttonset_t press;
   djoy_buttonset_t release;
   irqstate_t flags;
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   DEBUGASSERT(priv);
   lower = priv->du_lower;
@@ -229,7 +216,6 @@ static void djoy_enable(FAR struct djoy_upperhalf_s *priv)
 
   for (opriv = priv->du_open; opriv; opriv = opriv->do_flink)
     {
-#ifndef CONFIG_DISABLE_POLL
       /* Are there any poll waiters? */
 
       for (i = 0; i < CONFIG_DJOYSTICK_NPOLLWAITERS; i++)
@@ -243,14 +229,11 @@ static void djoy_enable(FAR struct djoy_upperhalf_s *priv)
               break;
             }
         }
-#endif
 
-#ifndef CONFIG_DISABLE_SIGNALS
       /* OR in the signal events */
 
       press   |= opriv->do_notify.dn_press;
       release |= opriv->do_notify.dn_release;
-#endif
     }
 
   /* Enable/disable button interrupts */
@@ -272,13 +255,11 @@ static void djoy_enable(FAR struct djoy_upperhalf_s *priv)
 
   leave_critical_section(flags);
 }
-#endif
 
 /****************************************************************************
  * Name: djoy_interrupt
  ****************************************************************************/
 
-#if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
 static void djoy_interrupt(FAR const struct djoy_lowerhalf_s *lower,
                            FAR void *arg)
 {
@@ -290,7 +271,6 @@ static void djoy_interrupt(FAR const struct djoy_lowerhalf_s *lower,
 
   djoy_sample(priv);
 }
-#endif
 
 /****************************************************************************
  * Name: djoy_sample
@@ -301,15 +281,11 @@ static void djoy_sample(FAR struct djoy_upperhalf_s *priv)
   FAR const struct djoy_lowerhalf_s *lower;
   FAR struct djoy_open_s *opriv;
   djoy_buttonset_t sample;
-#if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
   djoy_buttonset_t change;
   djoy_buttonset_t press;
   djoy_buttonset_t release;
-#endif
   irqstate_t flags;
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   DEBUGASSERT(priv);
   lower = priv->du_lower;
@@ -328,7 +304,6 @@ static void djoy_sample(FAR struct djoy_upperhalf_s *priv)
 
   add_ui_randomness(sample);
 
-#if !defined(CONFIG_DISABLE_POLL) || !defined(CONFIG_DISABLE_SIGNALS)
   /* Determine which buttons have been newly pressed and which have been
    * newly released.
    */
@@ -343,7 +318,6 @@ static void djoy_sample(FAR struct djoy_upperhalf_s *priv)
 
   for (opriv = priv->du_open; opriv; opriv = opriv->do_flink)
     {
-#ifndef CONFIG_DISABLE_POLL
       /* Have any poll events occurred? */
 
       if ((press & opriv->do_pollevents.dp_press)     != 0 ||
@@ -365,9 +339,7 @@ static void djoy_sample(FAR struct djoy_upperhalf_s *priv)
                 }
             }
         }
-#endif
 
-#ifndef CONFIG_DISABLE_SIGNALS
       /* Have any signal events occurred? */
 
       if ((press & opriv->do_notify.dn_press)     != 0 ||
@@ -379,13 +351,11 @@ static void djoy_sample(FAR struct djoy_upperhalf_s *priv)
           nxsig_notification(opriv->do_pid, &opriv->do_notify.dn_event,
                              SI_QUEUE, &opriv->do_work);
         }
-#endif
     }
 
   /* Enable/disable interrupt handling */
 
   djoy_enable(priv);
-#endif
 
   priv->du_sample = sample;
   leave_critical_section(flags);
@@ -400,10 +370,8 @@ static int djoy_open(FAR struct file *filep)
   FAR struct inode *inode;
   FAR struct djoy_upperhalf_s *priv;
   FAR struct djoy_open_s *opriv;
-#ifndef CONFIG_DISABLE_POLL
   FAR const struct djoy_lowerhalf_s *lower;
   djoy_buttonset_t supported;
-#endif
   int ret;
 
   DEBUGASSERT(filep && filep->f_inode);
@@ -432,14 +400,12 @@ static int djoy_open(FAR struct file *filep)
 
   /* Initialize the open structure */
 
-#ifndef CONFIG_DISABLE_POLL
   lower = priv->du_lower;
   DEBUGASSERT(lower && lower->dl_supported);
   supported = lower->dl_supported(lower);
 
   opriv->do_pollevents.dp_press   = supported;
   opriv->do_pollevents.dp_release = supported;
-#endif
 
   /* Attach the open structure to the device */
 
@@ -654,7 +620,6 @@ static int djoy_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
       }
       break;
 
-#ifndef CONFIG_DISABLE_POLL
     /* Command:     DJOYIOC_POLLEVENTS
      * Description: Specify the set of button events that can cause a poll()
      *              to awaken.  The default is all button depressions and
@@ -684,9 +649,7 @@ static int djoy_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
           }
       }
       break;
-#endif
 
-#ifndef CONFIG_DISABLE_SIGNALS
     /* Command:     DJOYIOC_REGISTER
      * Description: Register to receive a signal whenever there is a change
      *              in any of the joystick discrete inputs.  This feature,
@@ -719,7 +682,6 @@ static int djoy_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
           }
       }
       break;
-#endif
 
     default:
       ierr("ERROR: Unrecognized command: %ld\n", cmd);
@@ -735,7 +697,6 @@ static int djoy_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: djoy_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int djoy_poll(FAR struct file *filep, FAR struct pollfd *fds,
                      bool setup)
 {
@@ -815,7 +776,6 @@ errout_with_dusem:
   djoy_givesem(&priv->du_exclsem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/input/ft5x06.c b/drivers/input/ft5x06.c
index 8afe629ae00..4c71a902ba3 100644
--- a/drivers/input/ft5x06.c
+++ b/drivers/input/ft5x06.c
@@ -144,14 +144,12 @@ struct ft5x06_dev_s
 #endif
   uint8_t touchbuf[FT5x06_TOUCH_DATA_LEN];  /* Raw touch data */
 
-#ifndef CONFIG_DISABLE_POLL
   /* The following is a list if poll structures of threads waiting for
    * driver events. The 'struct pollfd' reference for each open is also
    * retained in the f_priv field of the 'struct file'.
    */
 
   struct pollfd *fds[CONFIG_FT5X06_NPOLLWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -180,10 +178,8 @@ static ssize_t ft5x06_read(FAR struct file *filep, FAR char *buffer,
                            size_t len);
 static int  ft5x06_ioctl(FAR struct file *filep, int cmd,
                          unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int  ft5x06_poll(FAR struct file *filep, struct pollfd *fds,
                         bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -198,10 +194,8 @@ static const struct file_operations ft5x06_fops =
   ft5x06_read,    /* read */
   NULL,           /* write */
   NULL,           /* seek */
-  ft5x06_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , ft5x06_poll   /* poll */
-#endif
+  ft5x06_ioctl,   /* ioctl */
+  ft5x06_poll     /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL          /* unlink */
 #endif
@@ -227,9 +221,7 @@ static const uint8_t g_event_map[4] =
 
 static void ft5x06_notify(FAR struct ft5x06_dev_s *priv)
 {
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   /* If there are threads waiting for read data, then signal one of them
    * that the read data is available.
@@ -244,7 +236,6 @@ static void ft5x06_notify(FAR struct ft5x06_dev_s *priv)
       nxsem_post(&priv->waitsem);
     }
 
-#ifndef CONFIG_DISABLE_POLL
   /* If there are threads waiting on poll() for FT5x06 data to become available,
    * then wake them up now.  NOTE: we wake up all waiting threads because we
    * do not know that they are going to do.  If they all try to read the data,
@@ -261,7 +252,6 @@ static void ft5x06_notify(FAR struct ft5x06_dev_s *priv)
           nxsem_post(fds->sem);
         }
     }
-#endif
 }
 
 /****************************************************************************
@@ -1034,7 +1024,6 @@ static int ft5x06_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: ft5x06_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int ft5x06_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup)
 {
@@ -1055,7 +1044,7 @@ static int ft5x06_poll(FAR struct file *filep, FAR struct pollfd *fds,
   ret = nxsem_wait(&priv->devsem);
   if (ret < 0)
     {
-      /* This should only happen if the wait was cancelled by an signal */
+      /* This should only happen if the wait was canceled by an signal */
 
       ierr("ERROR: nxsem_wait failed: %d\n", ret);
       DEBUGASSERT(ret == -EINTR || ret == -ECANCELED);
@@ -1123,7 +1112,6 @@ errout:
   nxsem_post(&priv->devsem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
@@ -1177,7 +1165,7 @@ int ft5x06_register(FAR struct i2c_master_s *i2c,
   priv = (FAR struct ft5x06_dev_s *)kmm_zalloc(sizeof(struct ft5x06_dev_s));
   if (!priv)
     {
-      ierr("ERROR: kmm_malloc(%d) failed\n", sizeof(struct ft5x06_dev_s));
+      ierr("ERROR: kmm_zalloc(%d) failed\n", sizeof(struct ft5x06_dev_s));
       return -ENOMEM;
     }
 
diff --git a/drivers/input/max11802.c b/drivers/input/max11802.c
index 4033407c573..f9d4c8976d6 100644
--- a/drivers/input/max11802.c
+++ b/drivers/input/max11802.c
@@ -114,10 +114,8 @@ static ssize_t max11802_read(FAR struct file *filep, FAR char *buffer,
                              size_t len);
 static int max11802_ioctl(FAR struct file *filep, int cmd,
                           unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int max11802_poll(FAR struct file *filep, struct pollfd *fds,
                          bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -132,10 +130,8 @@ static const struct file_operations max11802_fops =
   max11802_read,    /* read */
   0,                /* write */
   0,                /* seek */
-  max11802_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , max11802_poll   /* poll */
-#endif
+  max11802_ioctl,   /* ioctl */
+  max11802_poll     /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , 0               /* unlink */
 #endif
@@ -256,9 +252,7 @@ static uint16_t max11802_sendcmd(FAR struct max11802_dev_s *priv,
 
 static void max11802_notify(FAR struct max11802_dev_s *priv)
 {
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   /* If there are threads waiting for read data, then signal one of them
    * that the read data is available.
@@ -279,7 +273,6 @@ static void max11802_notify(FAR struct max11802_dev_s *priv)
    * all try to read the data, then some make end up blocking after all.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   for (i = 0; i < CONFIG_MAX11802_NPOLLWAITERS; i++)
     {
       struct pollfd *fds = priv->fds[i];
@@ -290,7 +283,6 @@ static void max11802_notify(FAR struct max11802_dev_s *priv)
           nxsem_post(fds->sem);
         }
     }
-#endif
 }
 
 /****************************************************************************
@@ -1041,7 +1033,6 @@ static int max11802_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: max11802_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int max11802_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup)
 {
@@ -1127,7 +1118,6 @@ errout:
   nxsem_post(&priv->devsem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/input/max11802.h b/drivers/input/max11802.h
index 5c389f7f7f8..0610bb2a56c 100644
--- a/drivers/input/max11802.h
+++ b/drivers/input/max11802.h
@@ -148,9 +148,7 @@ struct max11802_dev_s
    * retained in the f_priv field of the 'struct file'.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_MAX11802_NPOLLWAITERS];
-#endif
 };
 
 /********************************************************************************************
diff --git a/drivers/input/mxt.c b/drivers/input/mxt.c
index 52e4a3582c2..b2a656518f0 100644
--- a/drivers/input/mxt.c
+++ b/drivers/input/mxt.c
@@ -214,9 +214,7 @@ struct mxt_dev_s
    * retained in the f_priv field of the 'struct file'.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_MXT_NPOLLWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -271,9 +269,7 @@ static int  mxt_close(FAR struct file *filep);
 static ssize_t mxt_read(FAR struct file *filep, FAR char *buffer,
               size_t len);
 static int  mxt_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int  mxt_poll(FAR struct file *filep, struct pollfd *fds, bool setup);
-#endif
 
 /* Initialization */
 
@@ -293,10 +289,8 @@ static const struct file_operations mxt_fops =
   mxt_read,    /* read */
   0,           /* write */
   0,           /* seek */
-  mxt_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , mxt_poll   /* poll */
-#endif
+  mxt_ioctl,   /* ioctl */
+  mxt_poll     /* poll */
 };
 
 /****************************************************************************
@@ -598,9 +592,7 @@ static int mxt_flushmsgs(FAR struct mxt_dev_s *priv)
 
 static void mxt_notify(FAR struct mxt_dev_s *priv)
 {
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   /* If there are threads waiting for read data, then signal one of them
    * that the read data is available.
@@ -621,7 +613,6 @@ static void mxt_notify(FAR struct mxt_dev_s *priv)
    * then some make end up blocking after all.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   for (i = 0; i < CONFIG_MXT_NPOLLWAITERS; i++)
     {
       struct pollfd *fds = priv->fds[i];
@@ -632,7 +623,6 @@ static void mxt_notify(FAR struct mxt_dev_s *priv)
           nxsem_post(fds->sem);
         }
     }
-#endif
 }
 
 /****************************************************************************
@@ -1560,7 +1550,6 @@ static int mxt_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: mxt_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int mxt_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup)
 {
@@ -1648,7 +1637,6 @@ errout:
   nxsem_post(&priv->devsem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Name: mxt_getinfo
diff --git a/drivers/input/nunchuck.c b/drivers/input/nunchuck.c
index b1b2df93f3e..92a94470298 100644
--- a/drivers/input/nunchuck.c
+++ b/drivers/input/nunchuck.c
@@ -133,10 +133,8 @@ static const struct file_operations nunchuck_fops =
   nunchuck_read,  /* read */
   NULL,           /* write */
   NULL,           /* seek */
-  nunchuck_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL          /* poll */
-#endif
+  nunchuck_ioctl, /* ioctl */
+  NULL            /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL          /* unlink */
 #endif
diff --git a/drivers/input/stmpe811.h b/drivers/input/stmpe811.h
index dea9f3a0a86..f44b64c504d 100644
--- a/drivers/input/stmpe811.h
+++ b/drivers/input/stmpe811.h
@@ -169,9 +169,7 @@ struct stmpe811_dev_s
    * retained in the f_priv field of the 'struct file'.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_STMPE811_NPOLLWAITERS];
-#endif
 #endif
 
   /* Fields that may be disabled to save size of GPIO support is not used */
diff --git a/drivers/input/stmpe811_tsc.c b/drivers/input/stmpe811_tsc.c
index b1f467ebe89..b9ededff8b4 100644
--- a/drivers/input/stmpe811_tsc.c
+++ b/drivers/input/stmpe811_tsc.c
@@ -125,10 +125,8 @@ static ssize_t  stmpe811_read(FAR struct file *filep, FAR char *buffer,
                   size_t len);
 static int      stmpe811_ioctl(FAR struct file *filep, int cmd,
                   unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int      stmpe811_poll(FAR struct file *filep, struct pollfd *fds,
                   bool setup);
-#endif
 
 /* Initialization logic */
 
@@ -145,12 +143,10 @@ static const struct file_operations g_stmpe811fops =
   stmpe811_open,    /* open */
   stmpe811_close,   /* close */
   stmpe811_read,    /* read */
-  0,               /* write */
-  0,               /* seek */
-  stmpe811_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , stmpe811_poll   /* poll */
-#endif
+  NULL,             /* write */
+  NULL,             /* seek */
+  stmpe811_ioctl,   /* ioctl */
+  stmpe811_poll     /* poll */
 };
 
 /****************************************************************************
@@ -167,9 +163,7 @@ static const struct file_operations g_stmpe811fops =
 
 static void stmpe811_notify(FAR struct stmpe811_dev_s *priv)
 {
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   /* If there are threads waiting for read data, then signal one of them
    * that the read data is available.
@@ -190,7 +184,6 @@ static void stmpe811_notify(FAR struct stmpe811_dev_s *priv)
    * then some make end up blocking after all.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   for (i = 0; i < CONFIG_STMPE811_NPOLLWAITERS; i++)
     {
       struct pollfd *fds = priv->fds[i];
@@ -201,7 +194,6 @@ static void stmpe811_notify(FAR struct stmpe811_dev_s *priv)
           nxsem_post(fds->sem);
         }
     }
-#endif
 }
 
 /****************************************************************************
@@ -644,7 +636,6 @@ static int stmpe811_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  *
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int stmpe811_poll(FAR struct file *filep, FAR struct pollfd *fds,
                          bool setup)
 {
@@ -733,7 +724,6 @@ errout:
   nxsem_post(&priv->exclsem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Name: stmpe811_timeoutworker
diff --git a/drivers/input/tsc2007.c b/drivers/input/tsc2007.c
index b6520626b45..d0cbd1c4e1a 100644
--- a/drivers/input/tsc2007.c
+++ b/drivers/input/tsc2007.c
@@ -177,9 +177,7 @@ struct tsc2007_dev_s
    * retained in the f_priv field of the 'struct file'.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_TSC2007_NPOLLWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -204,9 +202,7 @@ static int tsc2007_open(FAR struct file *filep);
 static int tsc2007_close(FAR struct file *filep);
 static ssize_t tsc2007_read(FAR struct file *filep, FAR char *buffer, size_t len);
 static int tsc2007_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int tsc2007_poll(FAR struct file *filep, struct pollfd *fds, bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -221,10 +217,8 @@ static const struct file_operations tsc2007_fops =
   tsc2007_read,    /* read */
   0,               /* write */
   0,               /* seek */
-  tsc2007_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , tsc2007_poll   /* poll */
-#endif
+  tsc2007_ioctl,   /* ioctl */
+  tsc2007_poll     /* poll */
 };
 
 /* If only a single TSC2007 device is supported, then the driver state
@@ -250,9 +244,7 @@ static struct tsc2007_dev_s *g_tsc2007list;
 
 static void tsc2007_notify(FAR struct tsc2007_dev_s *priv)
 {
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   /* If there are threads waiting for read data, then signal one of them
    * that the read data is available.
@@ -273,7 +265,6 @@ static void tsc2007_notify(FAR struct tsc2007_dev_s *priv)
    * then some make end up blocking after all.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   for (i = 0; i < CONFIG_TSC2007_NPOLLWAITERS; i++)
     {
       struct pollfd *fds = priv->fds[i];
@@ -284,7 +275,6 @@ static void tsc2007_notify(FAR struct tsc2007_dev_s *priv)
           nxsem_post(fds->sem);
         }
     }
-#endif
 }
 
 /****************************************************************************
@@ -1106,7 +1096,6 @@ static int tsc2007_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: tsc2007_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int tsc2007_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup)
 {
@@ -1195,11 +1184,6 @@ errout:
   nxsem_post(&priv->devsem);
   return ret;
 }
-#endif
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/ioexpander/gpio.c b/drivers/ioexpander/gpio.c
index 70ebcee20a3..654986cf049 100644
--- a/drivers/ioexpander/gpio.c
+++ b/drivers/ioexpander/gpio.c
@@ -73,17 +73,15 @@ static int     gpio_ioctl(FAR struct file *filep, int cmd,
 
 static const struct file_operations g_gpio_drvrops =
 {
-  gpio_open,  /* open */
-  gpio_close, /* close */
-  gpio_read,  /* read */
-  gpio_write, /* write */
-  gpio_seek,  /* seek */
-  gpio_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL      /* poll */
-#endif
+  gpio_open,   /* open */
+  gpio_close,  /* close */
+  gpio_read,   /* read */
+  gpio_write,  /* write */
+  gpio_seek,   /* seek */
+  gpio_ioctl,  /* ioctl */
+  NULL         /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
-  , NULL      /* unlink */
+  , NULL       /* unlink */
 #endif
 };
 
diff --git a/drivers/ioexpander/pca9555.h b/drivers/ioexpander/pca9555.h
index 815d92de237..dc8c13354ea 100644
--- a/drivers/ioexpander/pca9555.h
+++ b/drivers/ioexpander/pca9555.h
@@ -71,8 +71,6 @@
  *   CONFIG_IOEXPANDER
  *     Enables support for the PCA9555 I/O expander
  *
- * Other settings that effect the driver: CONFIG_DISABLE_POLL
- *
  * CONFIG_IOEXPANDER_PCA9555
  *   Enables support for the PCA9555 driver (Needs CONFIG_INPUT)
  * CONFIG_PCA9555_MULTIPLE
diff --git a/drivers/ioexpander/pcf8574.h b/drivers/ioexpander/pcf8574.h
index ec164908073..9ef09767296 100644
--- a/drivers/ioexpander/pcf8574.h
+++ b/drivers/ioexpander/pcf8574.h
@@ -67,8 +67,6 @@
  *   CONFIG_IOEXPANDER
  *     Enables I/O expander support
  *
- * Other settings that effect the driver: CONFIG_DISABLE_POLL
- *
  * CONFIG_IOEXPANDER_PCF8574
  *   Enables support for the PCF8574 driver (Needs CONFIG_INPUT)
  * CONFIG_PCF8574_MULTIPLE
diff --git a/drivers/ioexpander/tca64xx.h b/drivers/ioexpander/tca64xx.h
index dbe9557b455..c77ed6bc894 100644
--- a/drivers/ioexpander/tca64xx.h
+++ b/drivers/ioexpander/tca64xx.h
@@ -71,8 +71,6 @@
  *   CONFIG_IOEXPANDER
  *     Enables I/O expander support
  *
- * Other settings that effect the driver: CONFIG_DISABLE_POLL
- *
  * CONFIG_IOEXPANDER_TCA64XX
  *   Enables support for the TCA64XX driver (Needs CONFIG_INPUT)
  * CONFIG_TCA64XX_MULTIPLE
diff --git a/drivers/lcd/ft80x.c b/drivers/lcd/ft80x.c
index 337b1a4de7c..6850e200f1a 100644
--- a/drivers/lcd/ft80x.c
+++ b/drivers/lcd/ft80x.c
@@ -143,10 +143,8 @@ static const struct file_operations g_ft80x_fops =
   ft80x_read,    /* read */
   ft80x_write,   /* write */
   NULL,          /* seek */
-  ft80x_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL         /* poll */
-#endif
+  ft80x_ioctl,   /* ioctl */
+  NULL           /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , ft80x_unlink /* unlink */
 #endif
diff --git a/drivers/lcd/pcf8574_lcd_backpack.c b/drivers/lcd/pcf8574_lcd_backpack.c
index 9bc07aa8da9..8c93c54342a 100644
--- a/drivers/lcd/pcf8574_lcd_backpack.c
+++ b/drivers/lcd/pcf8574_lcd_backpack.c
@@ -119,10 +119,8 @@ static off_t pcf8574_lcd_seek(FAR struct file *filep, off_t offset,
                               int whence);
 static int pcf8574_lcd_ioctl(FAR struct file *filep, int cmd,
                              unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int pcf8574lcd_poll(FAR struct file *filep, FAR struct pollfd *fds,
                            bool setup);
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
 static int pcf8574_lcd_unlink(FAR struct inode *inode);
 #endif
@@ -139,9 +137,7 @@ static const struct file_operations g_pcf8574_lcd_fops =
   pcf8574_lcd_write,            /* write */
   pcf8574_lcd_seek,             /* seek */
   pcf8574_lcd_ioctl,            /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
   pcf8574lcd_poll,              /* poll */
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   pcf8574_lcd_unlink            /* unlink */
 #endif
@@ -1567,7 +1563,6 @@ static int pcf8574_lcd_ioctl(FAR struct file *filep, int cmd,
  * Name: pcf8574lcd_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int pcf8574lcd_poll(FAR struct file *filep, FAR struct pollfd *fds,
                            bool setup)
 {
@@ -1584,7 +1579,6 @@ static int pcf8574lcd_poll(FAR struct file *filep, FAR struct pollfd *fds,
 
   return OK;
 }
-#endif
 
 /****************************************************************************
  * Name: pcf8574_lcd_unlink
diff --git a/drivers/lcd/st7032.c b/drivers/lcd/st7032.c
index 16bc586fc2d..d73afcb3135 100644
--- a/drivers/lcd/st7032.c
+++ b/drivers/lcd/st7032.c
@@ -133,11 +133,9 @@ static const struct file_operations g_st7032fops =
   st7032_write,  /* write */
   st7032_seek,   /* seek */
   st7032_ioctl,  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  0,              /* poll */
-#endif
+  NULL,          /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
-  NULL            /* unlink */
+  NULL           /* unlink */
 #endif
 };
 
diff --git a/drivers/lcd/tda19988.c b/drivers/lcd/tda19988.c
index d3597130c16..d04695e82e5 100644
--- a/drivers/lcd/tda19988.c
+++ b/drivers/lcd/tda19988.c
@@ -162,10 +162,8 @@ static ssize_t tda19988_write(FAR struct file *filep, FAR const char *buffer,
                  size_t buflen);
 static off_t   tda19988_seek(FAR struct file *filep, off_t offset, int whence);
 static int     tda19988_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int     tda19988_poll(FAR struct file *filep, FAR struct pollfd *fds,
                  bool setup);
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
 static int     tda19988_unlink(FAR struct inode *inode);
 #endif
@@ -190,10 +188,8 @@ static const struct file_operations tda19988_fops =
   tda19988_read,     /* read */
   tda19988_write,    /* write */
   tda19988_seek,     /* seek */
-  tda19988_ioctl     /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , tda19988_poll    /* poll */
-#endif
+  tda19988_ioctl,    /* ioctl */
+  tda19988_poll      /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , tda19988_unlink  /* unlink */
 #endif
@@ -1176,7 +1172,6 @@ static int tda19988_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  *
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int tda19988_poll(FAR struct file *filep, FAR struct pollfd *fds,
                          bool setup)
 {
@@ -1212,7 +1207,6 @@ static int tda19988_poll(FAR struct file *filep, FAR struct pollfd *fds,
   nxsem_post(&priv->exclsem);
   return OK;
 }
-#endif
 
 /****************************************************************************
  * Name: tda19988_unlink
diff --git a/drivers/leds/apa102.c b/drivers/leds/apa102.c
index 4d8835e8acc..dd539c1aa9a 100644
--- a/drivers/leds/apa102.c
+++ b/drivers/leds/apa102.c
@@ -91,11 +91,9 @@ static const struct file_operations g_apa102fops =
   apa102_close,  /* close */
   apa102_read,   /* read */
   apa102_write,  /* write */
-  0,             /* seek */
-  0,             /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  0,             /* poll */
-#endif
+  NULL,          /* seek */
+  NULL,          /* ioctl */
+  NULL           /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL         /* unlink */
 #endif
diff --git a/drivers/leds/max7219.c b/drivers/leds/max7219.c
index c0cce2f4368..1f0367cc306 100644
--- a/drivers/leds/max7219.c
+++ b/drivers/leds/max7219.c
@@ -102,11 +102,9 @@ static const struct file_operations g_max7219fops =
   max7219_close,  /* close */
   max7219_read,   /* read */
   max7219_write,  /* write */
-  0,              /* seek */
-  0,              /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  0,              /* poll */
-#endif
+  NULL,           /* seek */
+  NULL,           /* ioctl */
+  NULL,           /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   NULL            /* unlink */
 #endif
diff --git a/drivers/leds/rgbled.c b/drivers/leds/rgbled.c
index 49c4cfc7064..d07a4355cf2 100644
--- a/drivers/leds/rgbled.c
+++ b/drivers/leds/rgbled.c
@@ -104,13 +104,11 @@ static const struct file_operations g_rgbledops =
   rgbled_close, /* close */
   rgbled_read,  /* read */
   rgbled_write, /* write */
-  0,            /* seek */
-  0             /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0           /* poll */
-#endif
+  NULL,         /* seek */
+  NULL,         /* ioctl */
+  NULL          /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
-  , 0           /* unlink */
+  , NULL        /* unlink */
 #endif
 };
 
diff --git a/drivers/leds/userled_upper.c b/drivers/leds/userled_upper.c
index efb2083733e..5826e36868b 100644
--- a/drivers/leds/userled_upper.c
+++ b/drivers/leds/userled_upper.c
@@ -117,17 +117,15 @@ static int     userled_ioctl(FAR struct file *filep, int cmd,
 
 static const struct file_operations userled_fops =
 {
-  userled_open,  /* open */
-  userled_close, /* close */
-  NULL,          /* read */
-  userled_write, /* write */
-  NULL,          /* seek */
-  userled_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL         /* poll */
-#endif
+  userled_open,   /* open */
+  userled_close,  /* close */
+  NULL,           /* read */
+  userled_write,  /* write */
+  NULL,           /* seek */
+  userled_ioctl,  /* ioctl */
+  NULL            /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
-  , NULL         /* unlink */
+  , NULL          /* unlink */
 #endif
 };
 
@@ -461,7 +459,7 @@ static int userled_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
 
         /* Verify that a valid LED set was provided */
 
-        if ((ledset & priv->lu_supported) == ledset)
+        if ((ledset & ~priv->lu_supported) == 0)
           {
             /* Update the LED state */
 
diff --git a/drivers/loop/loop.c b/drivers/loop/loop.c
index 4fa9bd18ce5..f4ed22d977f 100644
--- a/drivers/loop/loop.c
+++ b/drivers/loop/loop.c
@@ -65,15 +65,13 @@ static int     loop_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
 
 static const struct file_operations g_loop_fops =
 {
-  0,             /* open */
-  0,             /* close */
+  NULL,          /* open */
+  NULL,          /* close */
   loop_read,     /* read */
   loop_write,    /* write */
-  0,             /* seek */
-  loop_ioctl     /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0            /* poll */
-#endif
+  NULL,          /* seek */
+  loop_ioctl,    /* ioctl */
+  NULL           /* poll */
 };
 
 /****************************************************************************
diff --git a/drivers/mmcsd/mmcsd_sdio.c b/drivers/mmcsd/mmcsd_sdio.c
index be7fd548be3..74f7de76f34 100644
--- a/drivers/mmcsd/mmcsd_sdio.c
+++ b/drivers/mmcsd/mmcsd_sdio.c
@@ -97,7 +97,7 @@
 
 #define MMCSD_SCR_DATADELAY     (100)      /* Wait up to 100MS to get SCR */
 #define MMCSD_BLOCK_RDATADELAY  (100)      /* Wait up to 100MS to get one data block */
-#define MMCSD_BLOCK_WDATADELAY  (230)      /* Wait up to 230MS to write one data block */
+#define MMCSD_BLOCK_WDATADELAY  (260)      /* Wait up to 260MS to write one data block */
 
 #define IS_EMPTY(priv) (priv->type == MMCSD_CARDTYPE_UNKNOWN)
 
diff --git a/drivers/modem/u-blox.c b/drivers/modem/u-blox.c
index 3e1ac02a4dc..11c5db7066e 100644
--- a/drivers/modem/u-blox.c
+++ b/drivers/modem/u-blox.c
@@ -95,11 +95,9 @@ static int     ubxmdm_ioctl(FAR struct file* filep,
                             int cmd,
                             unsigned long arg);
 
-#ifndef CONFIG_DISABLE_POLL
 static int     ubxmdm_poll (FAR struct file* filep,
                             FAR struct pollfd* fds,
                             bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -113,9 +111,7 @@ static const struct file_operations ubxmdm_fops =
   ubxmdm_write, /* write */
   0,            /* seek */
   ubxmdm_ioctl, /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  ubxmdm_poll,  /* poll */
-#endif
+  ubxmdm_poll   /* poll */
 };
 
 /****************************************************************************
@@ -252,7 +248,6 @@ static int ubxmdm_ioctl(FAR struct file* filep,
   return ret;
 }
 
-#ifndef CONFIG_DISABLE_POLL
 static int ubxmdm_poll(FAR struct file* filep,
                        FAR struct pollfd* fds,
                        bool setup)
@@ -268,7 +263,6 @@ static int ubxmdm_poll(FAR struct file* filep,
 
   return OK;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/mtd/mtd_config.c b/drivers/mtd/mtd_config.c
index a57a16f183a..3d70dbe1aca 100644
--- a/drivers/mtd/mtd_config.c
+++ b/drivers/mtd/mtd_config.c
@@ -123,10 +123,8 @@ static ssize_t mtdconfig_read(FAR struct file *filep, FAR char *buffer,
                   size_t buflen);
 static int     mtdconfig_ioctl(FAR struct file *filep, int cmd,
                   unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int     mtdconfig_poll(FAR struct file *filep, FAR struct pollfd *fds,
                   bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -139,10 +137,8 @@ static const struct file_operations mtdconfig_fops =
   mtdconfig_read,  /* read */
   0,               /* write */
   0,               /* seek */
-  mtdconfig_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , mtdconfig_poll /* poll */
-#endif
+  mtdconfig_ioctl, /* ioctl */
+  mtdconfig_poll   /* poll */
 };
 
 /****************************************************************************
@@ -1661,7 +1657,6 @@ static int mtdconfig_ioctl(FAR struct file *filep, int cmd,
  * Name: mtdconfig_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int mtdconfig_poll(FAR struct file *filep, FAR struct pollfd *fds,
                           bool setup)
 {
@@ -1676,7 +1671,6 @@ static int mtdconfig_poll(FAR struct file *filep, FAR struct pollfd *fds,
 
   return OK;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/mtd/smart.c b/drivers/mtd/smart.c
index 840f496562c..12644d8041b 100644
--- a/drivers/mtd/smart.c
+++ b/drivers/mtd/smart.c
@@ -420,15 +420,13 @@ static const struct block_operations g_bops =
 #ifdef CONFIG_SMART_DEV_LOOP
 static const struct file_operations g_fops =
 {
-  0,                /* open */
-  0,                /* close */
+  NULL,             /* open */
+  NULL,             /* close */
   smart_loop_read,  /* read */
   smart_loop_write, /* write */
-  0,                /* seek */
-  smart_loop_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0               /* poll */
-#endif
+  NULL,             /* seek */
+  smart_loop_ioctl, /* ioctl */
+  NULL              /* poll */
 };
 #endif /* CONFIG_SMART_DEV_LOOP */
 
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 7125b06a2ac..28969a3f0bf 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -36,23 +36,39 @@ config TELNET_TXBUFFER_SIZE
 	int "Telnet TX buffer size"
 	default 256
 
-config TELNET_DUMPBUFFER
-	bool "Dump Telnet buffers"
-	default n
-	depends on DEBUG_NET
+config TELNET_MAXLCLIENTS
+	int "Maximum Telnet clients"
+	default 8
+	---help---
+		The maximum number of Telnet clients tasks is limited by this
+		number.  This limitation is somewhat artificial since it only
+		determines the size of a fixed-size, preallocated, internal array.
 
 config TELNET_CHARACTER_MODE
 	bool "Character mode"
 	default n
 	---help---
-		The Telnet daemon works in character mode. In this case, the deamon
+		The Telnet daemon works in character mode. In this case, the daemon
 		will echo a character which telnet client sent. By default, it works
 		in line mode.
 
+config TELNET_IOTHREAD_PRIORITY
+	int "I/O thread priority"
+	default 100
+
+config TELNET_IOTHREAD_STACKSIZE
+	int "I/O thread stack size"
+	default 1024
+
 config TELNET_SUPPORT_NAWS
 	bool "Support NAWS (Negotiate About Window Size)"
 	default n
 
+config TELNET_DUMPBUFFER
+	bool "Dump Telnet buffers"
+	default n
+	depends on DEBUG_NET
+
 endif # NETDEV_TELNET
 
 config ARCH_HAVE_NETDEV_STATISTICS
diff --git a/drivers/net/phy_notify.c b/drivers/net/phy_notify.c
index ef7dd3d9513..4ebcdd25f7d 100644
--- a/drivers/net/phy_notify.c
+++ b/drivers/net/phy_notify.c
@@ -329,7 +329,7 @@ int phy_notify_subscribe(FAR const char *intf, pid_t pid,
 
       client->pid   = pid;
       client->event = *event;
-      snprintf(client->intf, CONFIG_PHY_NOTIFICATION_MAXINTFLEN+1, intf);
+      strncpy(client->intf, intf, CONFIG_PHY_NOTIFICATION_MAXINTFLEN + 1);
       client->intf[CONFIG_PHY_NOTIFICATION_MAXINTFLEN] = '\0';
 
       /* Attach/re-attach the PHY interrupt */
diff --git a/drivers/net/telnet.c b/drivers/net/telnet.c
index d4622a6bb20..08209906949 100644
--- a/drivers/net/telnet.c
+++ b/drivers/net/telnet.c
@@ -5,8 +5,8 @@
  *     rights reserved.
  *   Author: Gregory Nutt 
  *
- * This is a leverage of similar logic from uIP which has a compatible BSD
- * license:
+ * This dervies remotely from some Telnet logic from uIP which has a
+ * compatible BSD license:
  *
  *   Author: Adam Dunkels 
  *   Copyright (c) 2003, Adam Dunkels.
@@ -61,6 +61,8 @@
 #include 
 #include 
 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -81,6 +83,23 @@
 #  define CONFIG_TELNET_TXBUFFER_SIZE 256
 #endif
 
+#ifndef CONFIG_TELNET_MAXLCLIENTS
+#  define CONFIG_TELNET_MAXLCLIENTS 8
+#endif
+
+#ifndef CONFIG_TELNET_IOTHREAD_PRIORITY
+#  define CONFIG_TELNET_IOTHREAD_PRIORITY 100
+#endif
+
+#ifndef CONFIG_TELNET_IOTHREAD_STACKSIZE
+#  define CONFIG_TELNET_IOTHREAD_STACKSIZE 1024
+#endif
+
+#undef HAVE_SIGNALS
+#if defined(CONFIG_TTY_SIGINT) || defined(CONFIG_TTY_SIGSTP)
+#  define HAVE_SIGNALS
+#endif
+
 /* Telnet protocol stuff ****************************************************/
 
 #define ISO_nl                0x0a
@@ -136,6 +155,7 @@ enum telnet_state_e
 struct telnet_dev_s
 {
   sem_t             td_exclsem;   /* Enforces mutually exclusive access */
+  sem_t             td_iosem;     /* I/O thread will notify that data is available */
   uint8_t           td_state;     /* (See telnet_state_e) */
   uint8_t           td_pending;   /* Number of valid, pending bytes in the rxbuffer */
   uint8_t           td_offset;    /* Offset to the valid, pending bytes in the rxbuffer */
@@ -146,6 +166,10 @@ struct telnet_dev_s
   uint16_t          td_cols;      /* Number of NAWS cols */
   int               td_sb_count;  /* Count of TELNET_SB bytes received */
 #endif
+#ifdef HAVE_SIGNALS
+  pid_t             pid;
+#endif
+  struct pollfd     fds;
   FAR struct socket td_psock;     /* A clone of the internal socket structure */
   char td_rxbuffer[CONFIG_TELNET_RXBUFFER_SIZE];
   char td_txbuffer[CONFIG_TELNET_TXBUFFER_SIZE];
@@ -182,6 +206,7 @@ static bool    telnet_putchar(FAR struct telnet_dev_s *priv, uint8_t ch,
                  int *nwritten);
 static void    telnet_sendopt(FAR struct telnet_dev_s *priv, uint8_t option,
                  uint8_t value);
+static int     telnet_io_main(int argc, char** argv);
 
 /* Telnet character driver methods */
 
@@ -191,10 +216,8 @@ static ssize_t telnet_read(FAR struct file *filep, FAR char *buffer,
                  size_t len);
 static ssize_t telnet_write(FAR struct file *filep, FAR const char *buffer,
                  size_t len);
-#ifndef CONFIG_DISABLE_POLL
 static int     telnet_poll(FAR struct file *filep, FAR struct pollfd *fds,
                  bool setup);
-#endif
 
 /* Telnet session creation */
 
@@ -220,10 +243,8 @@ static const struct file_operations g_telnet_fops =
   telnet_read,   /* read */
   telnet_write,  /* write */
   NULL,          /* seek */
-  common_ioctl   /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , telnet_poll  /* poll */
-#endif
+  common_ioctl,  /* ioctl */
+  telnet_poll    /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL         /* unlink */
 #endif
@@ -236,16 +257,14 @@ static const struct file_operations g_factory_fops =
   factory_read,  /* read */
   factory_write, /* write */
   NULL,          /* seek */
-  common_ioctl   /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , telnet_poll  /* poll */
-#endif
+  common_ioctl,  /* ioctl */
+  telnet_poll    /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL         /* unlink */
 #endif
 };
 
-/* Global information shared amongst telnet driver instanaces. */
+/* Global information shared amongst telnet driver instances. */
 
 static struct telnet_common_s g_telnet_common =
 {
@@ -253,6 +272,16 @@ static struct telnet_common_s g_telnet_common =
   0
 };
 
+/* This is an global data set of all of all active Telnet drivers.  This
+ * additional logic in included to handle killing of task via control
+ * characters received via Telenet (via Ctrl-C SIGINT, in particular).
+ */
+
+static pid_t                g_telnet_io_kthread;
+static struct telnet_dev_s *g_telnet_clients[CONFIG_TELNET_MAXLCLIENTS];
+static sem_t                g_iosem       = SEM_INITIALIZER(0);
+static sem_t                g_clients_sem = SEM_INITIALIZER(1);
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -278,6 +307,64 @@ static inline void telnet_dumpbuffer(FAR const char *msg,
 }
 #endif
 
+/****************************************************************************
+ * Name: telnet_check_ctrl_char
+ *
+ * Description:
+ *   Check if an incoming control character should generate a signal.
+ *
+ ****************************************************************************/
+
+#ifdef HAVE_SIGNALS
+static void telnet_check_ctrl_char (FAR struct telnet_dev_s *priv,
+                                    uint8_t ch)
+{
+  int signo = 0;
+
+#ifdef CONFIG_TTY_SIGINT
+  /* Is this the special character that will generate the SIGINT signal? */
+
+  if (priv->pid >= 0 && ch == CONFIG_TTY_SIGINT_CHAR)
+    {
+      /* Yes.. note that the kill is needed and do not put the character
+       * into the Rx buffer.  It should not be read as normal data.
+       */
+
+      signo = SIGINT;
+    }
+  else
+#endif
+#ifdef CONFIG_TTY_SIGSTP
+  /* Is this the special character that will generate the SIGSTP signal? */
+
+  if (priv->pid >= 0 && ch == CONFIG_TTY_SIGSTP_CHAR)
+    {
+#ifdef CONFIG_TTY_SIGINT
+      /* Give precedence to SIGINT */
+
+      if (signo == 0)
+#endif
+        {
+          /* Note that the kill is needed and do not put the character
+           * into the Rx buffer.  It should not be read as normal data.
+           */
+
+          signo = SIGSTP;
+        }
+    }
+#endif
+
+#if defined(CONFIG_TTY_SIGINT) || defined(CONFIG_TTY_SIGSTP)
+  /* Send the signal if necessary */
+
+  if (signo != 0)
+    {
+      kill(priv->pid, signo);
+    }
+#endif
+}
+#endif
+
 /****************************************************************************
  * Name: telnet_getchar
  *
@@ -449,7 +536,7 @@ static ssize_t telnet_receive(FAR struct telnet_dev_s *priv,
             break;
 
 #ifdef CONFIG_TELNET_SUPPORT_NAWS
-          /* Handle Telnet Sub negotation request */
+          /* Handle Telnet Sub negotiation request */
 
           case STATE_SB:
             switch (ch)
@@ -663,6 +750,7 @@ static int telnet_close(FAR struct file *filep)
   FAR struct telnet_dev_s *priv = inode->i_private;
   FAR char *devpath;
   int ret;
+  int i;
 
   ninfo("td_crefs: %d\n", priv->td_crefs);
 
@@ -721,6 +809,34 @@ static int telnet_close(FAR struct file *filep)
           free(devpath);
         }
 
+      /* Remove ourself from the clients list */
+
+      nxsem_wait(&g_clients_sem);
+      for (i = 0; i < CONFIG_TELNET_MAXLCLIENTS; i++)
+        {
+          if (g_telnet_clients[i] == priv)
+            {
+              g_telnet_clients[i] = 0;
+              break;
+            }
+        }
+
+      /* If the socket is still polling */
+
+      if (priv->fds.events)
+        {
+          /* Tear down the poll */
+
+          psock_poll(&priv->td_psock, &priv->fds, FALSE);
+          priv->fds.events = 0;
+        }
+
+      nxsem_post(&g_clients_sem);
+
+      /* Notify the I/O thread that a client was removed */
+
+      nxsem_post(&g_iosem);
+
       /* Close the socket */
 
       psock_close(&priv->td_psock);
@@ -768,56 +884,52 @@ static ssize_t telnet_read(FAR struct file *filep, FAR char *buffer,
   /* First, handle the case where there are still valid bytes left in the
    * I/O buffer from the last time that read was called.  NOTE:  Much of
    * what we read may be protocol stuff and may not correspond to user
-   * data.  Hence we need the loop and we need may need to call psock_recv()
+   * data.  Hence we need the loop and we need may need to wait for data
    * multiple times in order to get data that the client is interested in.
    */
 
   do
     {
-      if (priv->td_pending > 0)
+      FAR const char *src;
+
+      if (priv->td_pending == 0)
         {
-          /* Process the buffered telnet data */
-
-          FAR const char *src = &priv->td_rxbuffer[priv->td_offset];
-          ret = telnet_receive(priv, src, priv->td_pending, buffer, len);
-        }
-
-      /* Read a buffer of data from the telnet client */
-
-      else
-        {
-          /* Test for non-blocking read */
-
           if (filep->f_oflags & O_NONBLOCK)
             {
               return 0;
             }
 
-          ret = psock_recv(&priv->td_psock, priv->td_rxbuffer,
-                           CONFIG_TELNET_RXBUFFER_SIZE, 0);
-
-          /* Did we receive anything? */
-
-          if (ret > 0)
+          do
             {
-              /* Yes.. Process the newly received telnet data */
+              /* Wait for new data (or error) */
 
-              telnet_dumpbuffer("Received buffer", priv->td_rxbuffer, ret);
-              ret = telnet_receive(priv, priv->td_rxbuffer, ret, buffer, len);
-           }
+              ret = nxsem_wait(&priv->td_iosem);
+            }
+          while (ret == -EINTR);
 
-          /* Otherwise the peer closed the connection (ret == 0) or an error
-           * occurred (ret < 0).
-           */
+          /* poll fds.revents contains last poll status in case of error */
 
-          else
+          if ((priv->fds.revents & (POLLHUP | POLLERR)) != 0)
             {
-              break;
+              return -EPIPE;
             }
         }
+
+      /* Take exclusive access to data buffer */
+
+      (void)nxsem_wait(&priv->td_exclsem);
+
+      /* Process the buffered telnet data */
+
+      src = &priv->td_rxbuffer[priv->td_offset];
+      ret = telnet_receive(priv, src, priv->td_pending, buffer, len);
+
+      nxsem_post(&priv->td_exclsem);
     }
   while (ret == 0);
 
+  return ret;
+
   /* Returned Value:
    *
    * ret > 0:  The number of characters copied into the user buffer by
@@ -862,7 +974,7 @@ static ssize_t telnet_write(FAR struct file *filep, FAR const char *buffer,
        * next largest character sequence ("\r\n\0")?
        */
 
-      if (eol || ncopied > CONFIG_TELNET_TXBUFFER_SIZE-3)
+      if (eol || ncopied > CONFIG_TELNET_TXBUFFER_SIZE - 3)
         {
           /* Yes... send the data now */
 
@@ -926,10 +1038,11 @@ static int telnet_session(FAR struct telnet_session_s *session)
   struct stat statbuf;
   uint16_t start;
   int ret;
+  int i;
 
   /* Allocate instance data for this driver */
 
-  priv = (FAR struct telnet_dev_s *)malloc(sizeof(struct telnet_dev_s));
+  priv = (FAR struct telnet_dev_s *)zalloc(sizeof(struct telnet_dev_s));
   if (!priv)
     {
       nerr("ERROR: Failed to allocate the driver data structure\n");
@@ -939,11 +1052,21 @@ static int telnet_session(FAR struct telnet_session_s *session)
   /* Initialize the allocated driver instance */
 
   nxsem_init(&priv->td_exclsem, 0, 1);
+  nxsem_init(&priv->td_iosem, 0, 0);
+
+  /* td_iosem is used for signaling and, hence, must not participate in
+   * priority inheritance.
+   */
+
+  sem_setprotocol(&priv->td_iosem, SEM_PRIO_NONE);
 
   priv->td_state     = STATE_NORMAL;
   priv->td_crefs     = 0;
   priv->td_pending   = 0;
   priv->td_offset    = 0;
+#ifdef HAVE_SIGNALS
+  priv->pid          = -1;
+#endif
 #ifdef CONFIG_TELNET_SUPPORT_NAWS
   priv->td_rows      = 25;
   priv->td_cols      = 80;
@@ -1032,6 +1155,38 @@ static int telnet_session(FAR struct telnet_session_s *session)
   telnet_sendopt(priv, TELNET_DO, TELNET_NAWS);
 #endif
 
+  /* Has the I/O thread been started? */
+
+  if (g_telnet_io_kthread == (pid_t)0)
+    {
+      /* g_iosem is used for signaling and, hence, must not participate in
+       * priority inheritance.
+       */
+
+      sem_setprotocol(&g_iosem, SEM_PRIO_NONE);
+
+      /* Start the I/O thread */
+
+      g_telnet_io_kthread =
+        kthread_create("telnet_io", CONFIG_TELNET_IOTHREAD_PRIORITY,
+                       CONFIG_TELNET_IOTHREAD_STACKSIZE, telnet_io_main, 0);
+    }
+
+  /* Save ourself in the list of Telnet client threads */
+
+  nxsem_wait(&g_clients_sem);
+  for (i = 0; i < CONFIG_TELNET_MAXLCLIENTS; i++)
+    {
+      if (g_telnet_clients[i] == NULL)
+        {
+          g_telnet_clients[i] = priv;
+          break;
+        }
+    }
+
+  nxsem_post(&g_clients_sem);
+  nxsem_post(&g_iosem);
+
   /* Return the path to the new telnet driver */
 
   nxsem_post(&g_telnet_common.tc_exclsem);
@@ -1086,7 +1241,6 @@ static ssize_t factory_write(FAR struct file *filep, FAR const char *buffer,
  *
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int telnet_poll(FAR struct file *filep, FAR struct pollfd *fds,
                        bool setup)
 {
@@ -1120,7 +1274,122 @@ static int telnet_poll(FAR struct file *filep, FAR struct pollfd *fds,
 
   return psock_poll(psock, fds, setup);
 }
+
+/****************************************************************************
+ * Name: telnet_io_main
+ ****************************************************************************/
+
+static int telnet_io_main(int argc, FAR char** argv)
+{
+  FAR struct telnet_dev_s *priv;
+  FAR char *buffer;
+  int i;
+#ifdef HAVE_SIGNALS
+  int c;
 #endif
+  int ret;
+
+  while (1)
+    {
+      nxsem_reset(&g_iosem, 0);
+
+      /* Poll each client in the g_telnet_clients[] array. */
+
+      nxsem_wait(&g_clients_sem);
+      for (i = 0; i < CONFIG_TELNET_MAXLCLIENTS; i++)
+        {
+          if (g_telnet_clients[i] != 0)
+            {
+              priv              = g_telnet_clients[i];
+              priv->fds.sem     = &g_iosem;
+              priv->fds.events  = POLLIN | POLLHUP | POLLERR;
+              priv->fds.revents = 0;
+
+              (void)psock_poll(&priv->td_psock, &priv->fds, TRUE);
+            }
+        }
+
+      nxsem_post(&g_clients_sem);
+
+      /* Wait for any Telnet connect/disconnect events to
+       * to include/remove client sockets from polling
+       */
+
+      (void)nxsem_wait(&g_iosem);
+
+      /* Revisit each client in the g_telnet_clients[] array */
+
+      nxsem_wait(&g_clients_sem);
+      for (i = 0; i < CONFIG_TELNET_MAXLCLIENTS; i++)
+        {
+          if (g_telnet_clients[i] != 0)
+            {
+              /* Check for a pending poll() */
+
+              priv = g_telnet_clients[i];
+              if (priv->fds.revents & POLLIN)
+                {
+                  if (priv->td_pending < CONFIG_TELNET_RXBUFFER_SIZE)
+                    {
+                      /* Take exclusive access to data buffer */
+
+                      nxsem_wait(&priv->td_exclsem);
+                      buffer = priv->td_rxbuffer + priv->td_pending +
+                               priv->td_offset;
+
+                      ret = psock_recv(&priv->td_psock, buffer,
+                                       CONFIG_TELNET_RXBUFFER_SIZE -
+                                       priv->td_pending - priv->td_offset,
+                                       0);
+
+                      priv->td_pending += ret;
+                      nxsem_post(&priv->td_exclsem);
+
+                      /* Notify the client thread that data is available */
+
+                      nxsem_post(&priv->td_iosem);
+
+#ifdef HAVE_SIGNALS
+                      /* Check if any of the received characters is a
+                       * control that should generate a signal.
+                       */
+
+                      for (c = 0; c < ret; c++)
+                        {
+                          telnet_check_ctrl_char(priv, buffer[c]);
+                        }
+#endif
+                    }
+                }
+
+              /* If poll was setup previously (events != 0), tear it down */
+
+              if (priv->fds.events)
+                {
+                  psock_poll(&priv->td_psock, &priv->fds, FALSE);
+                  priv->fds.events = 0;
+                }
+
+              /* POLLHUP (or POLLERR) indicates that this session has
+               * terminated.
+               */
+
+              if (priv->fds.revents & (POLLHUP | POLLERR))
+                {
+                  g_telnet_clients[i] = 0;
+
+                  /* notify the client thread */
+
+                  nxsem_post(&priv->td_iosem);
+                }
+            }
+        }
+
+      nxsem_post(&g_clients_sem);
+    }
+
+  return 0;
+}
 
 /****************************************************************************
  * Name: common_ioctl
@@ -1128,10 +1397,9 @@ static int telnet_poll(FAR struct file *filep, FAR struct pollfd *fds,
 
 static int common_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
 {
-#ifdef CONFIG_TELNET_SUPPORT_NAWS
   FAR struct inode *inode = filep->f_inode;
   FAR struct telnet_dev_s *priv = inode->i_private;
-#endif
+
   int ret;
 
   switch (cmd)
@@ -1145,8 +1413,8 @@ static int common_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
 
     case SIOCTELNET:
       {
-         FAR struct telnet_session_s *session =
-           (FAR struct telnet_session_s *)((uintptr_t)arg);
+        FAR struct telnet_session_s *session =
+            (FAR struct telnet_session_s *)((uintptr_t) arg);
 
         if (session == NULL)
           {
@@ -1159,26 +1427,47 @@ static int common_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
       }
       break;
 
-#ifdef CONFIG_TELNET_SUPPORT_NAWS
-    case TIOCGWINSZ:
+#ifdef HAVE_SIGNALS
+      /* Make the given terminal the controlling terminal of the calling process */
+
+    case TIOCSCTTY:
       {
-         FAR struct winsize *pW = (FAR struct winsize *)((uintptr_t)arg);
+        /* Check if the ISIG flag is set in the termios c_lflag to enable
+         * this feature.  This flag is set automatically for a serial console
+         * device.
+         */
 
-         /* Get row/col from the private data */
+        /* Save the PID of the recipient of the SIGINT signal. */
 
-         pW->ws_row = priv->td_rows;
-         pW->ws_col = priv->td_cols;
+        priv->pid = (pid_t)arg;
+        DEBUGASSERT((unsigned long)(priv->pid) == arg);
 
-         ret = OK;
+        ret = OK;
       }
       break;
 #endif
 
+#ifdef CONFIG_TELNET_SUPPORT_NAWS
+      case TIOCGWINSZ:
+        {
+          FAR struct winsize *pw = (FAR struct winsize *)((uintptr_t)arg);
+
+          /* Get row/col from the private data */
+
+          pw->ws_row = priv->td_rows;
+          pw->ws_col = priv->td_cols;
+
+          ret = OK;
+        }
+      break;
+#endif
+
     default:
       ret = -ENOTTY;
       break;
     }
 
+  UNUSED(priv);  /* Avoid warning if not used */
   return ret;
 }
 
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index 5fc914204e9..43b8e61bd9c 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -47,10 +47,7 @@
 #include 
 #include 
 #include 
-
-#ifndef CONFIG_DISABLE_POLL
-#  include 
-#endif
+#include 
 
 #include 
 
@@ -139,13 +136,8 @@ struct tun_device_s
   bool              read_wait;
   WDOG_ID           txpoll;    /* TX poll timer */
   struct work_s     work;      /* For deferring poll work to the work queue */
-
   FAR struct file  *filep;
-
-#ifndef CONFIG_DISABLE_POLL
   FAR struct pollfd *poll_fds;
-#endif
-
   sem_t             waitsem;
   sem_t             read_wait_sem;
   size_t            read_d_len;
@@ -226,10 +218,8 @@ static ssize_t tun_read(FAR struct file *filep, FAR char *buffer,
 static ssize_t tun_write(FAR struct file *filep, FAR const char *buffer,
                          size_t buflen);
 static int tun_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int tun_poll(FAR struct file *filep, FAR struct pollfd *fds,
                     bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -244,13 +234,11 @@ static const struct file_operations g_tun_file_ops =
   tun_close,    /* close */
   tun_read,     /* read */
   tun_write,    /* write */
-  0,            /* seek */
+  NULL,         /* seek */
   tun_ioctl,    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
   tun_poll,     /* poll */
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
-  0,            /* unlink */
+  NULL,         /* unlink */
 #endif
 };
 
@@ -326,7 +314,6 @@ static void tun_unlock(FAR struct tun_device_s *priv)
  * Name: tun_pollnotify
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static void tun_pollnotify(FAR struct tun_device_s *priv,
                            pollevent_t eventset)
 {
@@ -345,9 +332,6 @@ static void tun_pollnotify(FAR struct tun_device_s *priv,
       nxsem_post(fds->sem);
     }
 }
-#else
-#  define tun_pollnotify(dev, event)
-#endif
 
 /****************************************************************************
  * Name: tun_fd_transmit
@@ -1399,7 +1383,6 @@ out:
  * Name: tun_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 int tun_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup)
 {
   FAR struct tun_device_s *priv = filep->f_priv;
@@ -1458,7 +1441,6 @@ errout:
 
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Name: tun_ioctl
diff --git a/drivers/pipes/fifo.c b/drivers/pipes/fifo.c
index 6a8905a6a20..9ece1f8865c 100644
--- a/drivers/pipes/fifo.c
+++ b/drivers/pipes/fifo.c
@@ -63,9 +63,7 @@ static const struct file_operations fifo_fops =
   pipecommon_write, /* write */
   0,                /* seek */
   pipecommon_ioctl, /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
   pipecommon_poll,  /* poll */
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   pipecommon_unlink /* unlink */
 #endif
diff --git a/drivers/pipes/pipe.c b/drivers/pipes/pipe.c
index 1cf395dc22f..4a82bdb9316 100644
--- a/drivers/pipes/pipe.c
+++ b/drivers/pipes/pipe.c
@@ -82,9 +82,7 @@ static const struct file_operations pipe_fops =
   pipecommon_write,  /* write */
   0,                 /* seek */
   pipecommon_ioctl,  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
   pipecommon_poll,   /* poll */
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   pipecommon_unlink  /* unlink */
 #endif
diff --git a/drivers/pipes/pipe_common.c b/drivers/pipes/pipe_common.c
index 610a3a18356..39b258014f0 100644
--- a/drivers/pipes/pipe_common.c
+++ b/drivers/pipes/pipe_common.c
@@ -117,7 +117,6 @@ static void pipecommon_semtake(FAR sem_t *sem)
  * Name: pipecommon_pollnotify
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static void pipecommon_pollnotify(FAR struct pipe_dev_s *dev,
                                   pollevent_t eventset)
 {
@@ -151,9 +150,6 @@ static void pipecommon_pollnotify(FAR struct pipe_dev_s *dev,
         }
     }
 }
-#else
-#  define pipecommon_pollnotify(dev,event)
-#endif
 
 /****************************************************************************
  * Public Functions
@@ -665,7 +661,6 @@ ssize_t pipecommon_write(FAR struct file *filep, FAR const char *buffer,
  * Name: pipecommon_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 int pipecommon_poll(FAR struct file *filep, FAR struct pollfd *fds,
                     bool setup)
 {
@@ -783,7 +778,6 @@ errout:
   nxsem_post(&dev->d_bfsem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Name: pipecommon_ioctl
diff --git a/drivers/pipes/pipe_common.h b/drivers/pipes/pipe_common.h
index 0986a27af17..3c4204a4cb9 100644
--- a/drivers/pipes/pipe_common.h
+++ b/drivers/pipes/pipe_common.h
@@ -147,9 +147,7 @@ struct pipe_dev_s
    * retained in the f_priv field of the 'struct file'.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *d_fds[CONFIG_DEV_PIPE_NPOLLWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -174,10 +172,8 @@ int     pipecommon_close(FAR struct file *filep);
 ssize_t pipecommon_read(FAR struct file *, FAR char *, size_t);
 ssize_t pipecommon_write(FAR struct file *, FAR const char *, size_t);
 int     pipecommon_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 int     pipecommon_poll(FAR struct file *filep, FAR struct pollfd *fds,
                                bool setup);
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
 int     pipecommon_unlink(FAR struct inode *priv);
 #endif
diff --git a/drivers/power/battery_charger.c b/drivers/power/battery_charger.c
index 70f707aa7b7..9f422a9b1b0 100644
--- a/drivers/power/battery_charger.c
+++ b/drivers/power/battery_charger.c
@@ -89,11 +89,9 @@ static const struct file_operations g_batteryops =
   bat_charger_close,
   bat_charger_read,
   bat_charger_write,
-  0,
-  bat_charger_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , 0
-#endif
+  NULL,
+  bat_charger_ioctl,
+  NULL
 };
 
 /****************************************************************************
diff --git a/drivers/power/battery_gauge.c b/drivers/power/battery_gauge.c
index 63b59092a97..f883a2a2697 100644
--- a/drivers/power/battery_gauge.c
+++ b/drivers/power/battery_gauge.c
@@ -41,20 +41,20 @@
 #include 
 
 #include 
-#include 
 #include 
 #include 
 
+#include 
 #include 
 #include 
 #include 
 
 /* This driver requires:
  *
- * CONFIG_BATTERY - Upper half battery driver support
+ * CONFIG_BATTERY_GAUGE - Upper half battery driver support
  */
 
-#if defined(CONFIG_BATTERY)
+#if defined(CONFIG_BATTERY_GAUGE)
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -72,7 +72,7 @@
 
 static int     bat_gauge_open(FAR struct file *filep);
 static int     bat_gauge_close(FAR struct file *filep);
-static ssize_t bat_gauge_read(FAR struct file *filep, FAR char *buflen,
+static ssize_t bat_gauge_read(FAR struct file *filep, FAR char *buffer,
                  size_t buflen);
 static ssize_t bat_gauge_write(FAR struct file *filep, FAR const char *buffer,
                  size_t buflen);
@@ -89,11 +89,9 @@ static const struct file_operations g_batteryops =
   bat_gauge_close,
   bat_gauge_read,
   bat_gauge_write,
-  0,
-  bat_gauge_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , 0
-#endif
+  NULL,
+  bat_gauge_ioctl,
+  NULL
 };
 
 /****************************************************************************
@@ -262,4 +260,4 @@ int battery_gauge_register(FAR const char *devpath,
 
   return ret;
 }
-#endif /* CONFIG_BATTERY */
+#endif /* CONFIG_BATTERY_GAUGE */
diff --git a/drivers/power/motor.c b/drivers/power/motor.c
index 76f6e7546a7..c7f1dc9f117 100644
--- a/drivers/power/motor.c
+++ b/drivers/power/motor.c
@@ -78,10 +78,8 @@ static const struct file_operations motor_fops =
   motor_read,                    /* read */
   motor_write,                   /* write */
   NULL,                          /* seek */
-  motor_ioctl                    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL                         /* poll */
-#endif
+  motor_ioctl,                   /* ioctl */
+  NULL                           /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL                         /* unlink */
 #endif
diff --git a/drivers/power/powerled.c b/drivers/power/powerled.c
index a915fc0a550..913f28cc28a 100644
--- a/drivers/power/powerled.c
+++ b/drivers/power/powerled.c
@@ -74,10 +74,8 @@ static const struct file_operations powerled_fops =
   NULL,                         /* read */
   NULL,                         /* write */
   NULL,                         /* seek */
-  powerled_ioctl                /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL                        /* poll */
-#endif
+  powerled_ioctl,               /* ioctl */
+  NULL                          /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL                        /* unlink */
 #endif
diff --git a/drivers/power/smps.c b/drivers/power/smps.c
index 3eb040fedc2..613598e0ea1 100644
--- a/drivers/power/smps.c
+++ b/drivers/power/smps.c
@@ -78,10 +78,8 @@ static const struct file_operations smps_fops =
   smps_read,                    /* read */
   smps_write,                   /* write */
   NULL,                         /* seek */
-  smps_ioctl                    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL                        /* poll */
-#endif
+  smps_ioctl,                   /* ioctl */
+  NULL                          /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL                        /* unlink */
 #endif
diff --git a/drivers/pwm/pwm.c b/drivers/pwm/pwm.c
index bb0c15da9e9..ee51e4ed5f0 100644
--- a/drivers/pwm/pwm.c
+++ b/drivers/pwm/pwm.c
@@ -109,11 +109,9 @@ static const struct file_operations g_pwmops =
   pwm_close, /* close */
   pwm_read,  /* read */
   pwm_write, /* write */
-  0,         /* seek */
-  pwm_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0        /* poll */
-#endif
+  NULL,      /* seek */
+  pwm_ioctl, /* ioctl */
+  NULL       /* poll */
 };
 
 /****************************************************************************
diff --git a/drivers/sensors/Kconfig b/drivers/sensors/Kconfig
index 6ebbeb7d914..1f93e7813a3 100644
--- a/drivers/sensors/Kconfig
+++ b/drivers/sensors/Kconfig
@@ -23,6 +23,13 @@ config SENSORS_AS5048B
 	---help---
 		Enable driver support for the AMS AS5048B magnetic rotary encoder.
 
+config SENSORS_AS726X
+	bool "AMS AS726X Spetral sensor support"
+	default n
+	select I2C
+	---help---
+		Enable driver support for the AS726X Spectral Sensor.
+
 config SENSORS_BH1750FVI
 	bool "Rohm BH1750FVI Ambient Light Sensor support"
 	default n
diff --git a/drivers/sensors/Make.defs b/drivers/sensors/Make.defs
index bd0f730a5fb..5cf0f1a6c6e 100644
--- a/drivers/sensors/Make.defs
+++ b/drivers/sensors/Make.defs
@@ -61,6 +61,10 @@ ifeq ($(CONFIG_SENSORS_AS5048B),y)
   CSRCS += as5048b.c
 endif
 
+ifeq ($(CONFIG_SENSORS_AS726X),y)
+  CSRCS += as726x.c
+endif
+
 ifeq ($(CONFIG_SENSORS_KXTJ9),y)
   CSRCS += kxtj9.c
 endif
diff --git a/drivers/sensors/adxl372.c b/drivers/sensors/adxl372.c
index f01dde1a2b1..c2f39aa0505 100644
--- a/drivers/sensors/adxl372.c
+++ b/drivers/sensors/adxl372.c
@@ -140,10 +140,8 @@ static const struct file_operations g_adxl372_fops =
   adxl372_read,
   adxl372_write,
   adxl372_seek,
-  adxl372_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  adxl372_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
diff --git a/drivers/sensors/apds9960.c b/drivers/sensors/apds9960.c
index 9eb10b82299..ff02308df17 100644
--- a/drivers/sensors/apds9960.c
+++ b/drivers/sensors/apds9960.c
@@ -144,10 +144,8 @@ static const struct file_operations g_apds9960_fops =
   apds9960_read,   /* read */
   apds9960_write,  /* write */
   NULL,            /* seek */
-  NULL             /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL           /* poll */
-#endif
+  NULL,            /* ioctl */
+  NULL             /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL           /* unlink */
 #endif
@@ -1251,7 +1249,7 @@ int apds9960_register(FAR const char *devpath,
   /* Initialize the APDS9960 device structure */
 
   FAR struct apds9960_dev_s *priv =
-    (FAR struct apds9960_dev_s *)kmm_malloc(sizeof(struct apds9960_dev_s));
+    (FAR struct apds9960_dev_s *)kmm_zalloc(sizeof(struct apds9960_dev_s));
 
   if (priv == NULL)
     {
@@ -1260,7 +1258,6 @@ int apds9960_register(FAR const char *devpath,
     }
 
   priv->config         = config;
-  priv->work.worker    = NULL;
   priv->gesture_motion = DIR_NONE;
   nxsem_init(&priv->sample_sem, 0, 0);
 
diff --git a/drivers/sensors/as726x.c b/drivers/sensors/as726x.c
new file mode 100644
index 00000000000..84bba4ccf53
--- /dev/null
+++ b/drivers/sensors/as726x.c
@@ -0,0 +1,514 @@
+/****************************************************************************
+ * drivers/sensors/as726x.c
+ * Character driver for the AS7263 6-Ch NIR Spectral Sensing Engine
+ * and AS7262 Consumer Grade Smart 6-Channel VIS Sensor
+ *
+ *   Copyright (C) 2019 Fabian Justi. All rights reserved.
+ *   Author: Fabian Justi  and
+ *           Andreas Kurz 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#if defined(CONFIG_I2C) && defined(CONFIG_SENSORS_AS726X)
+
+/****************************************************************************
+ * Pre-process Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_AS726X_I2C_FREQUENCY
+#  define CONFIG_AS726X_I2C_FREQUENCY 100000
+#endif
+
+#define AS726X_INTEGRATION_TIME 50
+#define AS726X_GAIN             0b01   /* Set gain to 64x */
+#define AS726X_MEASURMENT_MODE  0b10   /* One-shot reading of VBGYOR or RSTUVW */
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct as726x_dev_s
+{
+  FAR struct i2c_master_s *i2c; /* I2C interface */
+  uint8_t addr;                 /* I2C address */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static float as726x_getcalibrated(FAR struct as726x_dev_s *priv,
+                                  uint8_t regaddr);
+static int16_t as726x_getchannel(FAR struct as726x_dev_s *priv,
+                                 uint8_t regaddr);
+
+/* I2C Helpers */
+
+static uint8_t read_register(FAR struct as726x_dev_s *priv, uint8_t addr);
+static uint8_t as726x_read8(FAR struct as726x_dev_s *priv, uint8_t regval);
+static void write_register(FAR struct as726x_dev_s *priv, uint8_t addr,
+                          uint8_t val);
+static void as726x_write8(FAR struct as726x_dev_s *priv, uint8_t regaddr,
+                          uint8_t regval);
+
+/* Character driver methods */
+
+static int as726x_open(FAR struct file *filep);
+static int as726x_close(FAR struct file *filep);
+static ssize_t as726x_read(FAR struct file *filep, FAR char *buffer,
+                           size_t buflen);
+static ssize_t as726x_write(FAR struct file *filep,
+                            FAR const char *buffer, size_t buflen);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct file_operations g_as726x_fops =
+{
+  as726x_open,                  /* open */
+  as726x_close,                 /* close */
+  as726x_read,                  /* read */
+  as726x_write,                 /* write */
+  NULL,                         /* seek */
+  NULL,                         /* ioctl */
+  NULL                          /* poll */
+#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
+  , NULL                        /* unlink */
+#endif
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: as726x_getcalibrated
+ *
+ * Description:
+ *   Read calibrated value
+ *
+ ****************************************************************************/
+
+static float as726x_getcalibrated(FAR struct as726x_dev_s *priv,
+                                  uint8_t regaddr)
+{
+  uint8_t byte0 = as726x_read8(priv, regaddr + 0);
+  uint8_t byte1 = as726x_read8(priv, regaddr + 1);
+  uint8_t byte2 = as726x_read8(priv, regaddr + 2);
+  uint8_t byte3 = as726x_read8(priv, regaddr + 3);
+
+  uint32_t colourdata = ((uint32_t) byte0 << (8 * 3));
+  colourdata |= ((uint32_t) byte1 << (8 * 2));
+  colourdata |= ((uint32_t) byte2 << (8 * 1));
+  colourdata |= ((uint32_t) byte3 << (8 * 0));
+
+  return *((float *)(&colourdata));
+}
+
+/****************************************************************************
+ * Name: as726x_getchannel
+ *
+ * Description:
+ *   Read colour channel
+ *
+ ****************************************************************************/
+
+static int16_t as726x_getchannel(FAR struct as726x_dev_s *priv,
+                                 uint8_t regaddr)
+{
+  int16_t colourdata = as726x_read8(priv, regaddr) << 8;
+  colourdata |= as726x_read8(priv, regaddr + 1);
+  return colourdata;
+}
+
+/****************************************************************************
+ * Name: as726x_read8
+ *
+ * Description:
+ *   Read 8-bit register
+ *
+ ****************************************************************************/
+
+static uint8_t read_register(FAR struct as726x_dev_s *priv, uint8_t addr)
+{
+  struct i2c_config_s config;
+  uint8_t regval = 0;
+  int ret;
+
+  config.frequency = CONFIG_AS726X_I2C_FREQUENCY;
+  config.address = AS726X_I2C_ADDR;
+  config.addrlen = 7;
+
+  ret = i2c_write(priv->i2c, &config, &addr, 1);
+  if (ret < 0)
+    {
+      snerr("ERROR: i2c_write failed: %d\n", ret);
+      return ret;
+    }
+
+  ret = i2c_read(priv->i2c, &config, ®val, 1);
+  if (ret < 0)
+    {
+      snerr("ERROR: i2c_read failed: %d\n", ret);
+      return ret;
+    }
+
+  return regval;
+}
+
+static uint8_t as726x_read8(FAR struct as726x_dev_s *priv, uint8_t regaddr)
+{
+  uint8_t status;
+
+  status = read_register(priv, AS72XX_SLAVE_STATUS_REG);
+  if ((status & AS72XX_SLAVE_RX_VALID) != 0)
+    {
+      /* There is data to be read.
+       * Read the byte but do nothing with it.
+       */
+
+      (void)read_register(priv, AS72XX_SLAVE_READ_REG);
+    }
+
+  /* Wait for WRITE flag to clear */
+
+  while (1)
+    {
+      status = read_register(priv, AS72XX_SLAVE_STATUS_REG);
+      if ((status & AS72XX_SLAVE_TX_VALID) == 0)
+        {
+          break;  /* If TX bit is clear, it is ok to write */
+        }
+
+      usleep(AS726X_POLLING_DELAY);
+    }
+
+  /* Send the virtual register address (bit 7 should be 0 to indicate we are
+   * reading a register).
+   */
+
+  write_register(priv, AS72XX_SLAVE_WRITE_REG, regaddr);
+
+  /* Wait for READ flag to be set */
+
+  while (1)
+    {
+      status = read_register(priv, AS72XX_SLAVE_STATUS_REG);
+      if ((status & AS72XX_SLAVE_RX_VALID) != 0)
+        {
+          break;  /* Read data is ready. */
+        }
+
+      usleep(AS726X_POLLING_DELAY);
+    }
+
+  uint8_t incoming = read_register(priv, AS72XX_SLAVE_READ_REG);
+  return incoming;
+}
+
+/****************************************************************************
+ * Name: as726x_write8
+ *
+ * Description:
+ *   Write from an 8-bit register
+ *
+ ****************************************************************************/
+
+static void write_register(FAR struct as726x_dev_s *priv, uint8_t addr,
+                           uint8_t val)
+{
+  struct i2c_config_s config;
+  uint8_t msg[2] =
+  {
+    0
+  };
+  int ret;
+
+  config.frequency = CONFIG_AS726X_I2C_FREQUENCY;
+  config.address = AS726X_I2C_ADDR;
+  config.addrlen = 7;
+
+  msg[0] = addr;
+  msg[1] = val;
+
+  ret = i2c_write(priv->i2c, &config, msg, 2);
+  if (ret < 0)
+    {
+      snerr("ERROR: i2c_write failed: %d\n", ret);
+      return;
+    }
+}
+
+static void as726x_write8(FAR struct as726x_dev_s *priv, uint8_t regaddr,
+                          uint8_t regval)
+{
+  uint8_t status;
+
+  while (1)
+    {
+      status = read_register(priv, AS72XX_SLAVE_STATUS_REG);
+      if ((status & AS72XX_SLAVE_TX_VALID) == 0)
+        {
+         /* No inbound TX pending at slave. Okay to write now. */
+
+          break;
+        }
+
+      usleep(AS726X_POLLING_DELAY);
+    }
+
+  /* Send the virtual register address (setting bit 7 to indicate we are
+   * writing to a register).
+   */
+
+  write_register(priv, AS72XX_SLAVE_WRITE_REG, (regaddr | 0x80));
+
+  /* Wait for WRITE register to be empty */
+
+  while (1)
+    {
+      status = read_register(priv, AS72XX_SLAVE_STATUS_REG);
+      if ((status & AS72XX_SLAVE_TX_VALID) == 0)
+        {
+          /* No inbound TX pending at slave. Okay to write now. */
+
+          break;
+        }
+
+      usleep(AS726X_POLLING_DELAY);
+    }
+
+  /* Send the data to complete the operation. */
+
+  write_register(priv, AS72XX_SLAVE_WRITE_REG, regval);
+}
+
+/****************************************************************************
+ * Name: as726x_open
+ *
+ * Description:
+ *   This function is called whenever the AS726X device is opened.
+ *
+ ****************************************************************************/
+
+static int as726x_open(FAR struct file *filep)
+{
+  return OK;
+}
+
+/****************************************************************************
+ * Name: as726x_close
+ *
+ * Description:
+ *   This routine is called when the AS726X device is closed.
+ *
+ ****************************************************************************/
+
+static int as726x_close(FAR struct file *filep)
+{
+  return OK;
+}
+
+/****************************************************************************
+ * Name: as726x_read
+ ****************************************************************************/
+
+static ssize_t as726x_read(FAR struct file *filep, FAR char *buffer,
+                           size_t buflen)
+{
+  FAR struct inode *inode = filep->f_inode;
+  FAR struct as726x_dev_s *priv = inode->i_private;
+  FAR struct as726x_sensor_data_s *data =
+    (FAR struct as726x_sensor_data_s *)buffer;
+
+  /* Check if the user is reading the right size */
+
+  if (buflen < sizeof(FAR struct as726x_sensor_data_s))
+    {
+      snerr("ERROR: Not enough memory for reading all channels.\n");
+      return -ENOSYS;
+    }
+  else
+    {
+      data->v_r_value = as726x_getchannel(priv, AS726X_V_R);
+      data->b_s_value = as726x_getchannel(priv, AS726X_B_S);
+      data->g_t_value = as726x_getchannel(priv, AS726X_G_T);
+      data->y_u_value = as726x_getchannel(priv, AS726X_Y_U);
+      data->o_v_value = as726x_getchannel(priv, AS726X_O_V);
+      data->r_w_value = as726x_getchannel(priv, AS726X_R_W);
+    }
+
+  return buflen;
+}
+
+/****************************************************************************
+ * Name: as726x_write
+ ****************************************************************************/
+
+static ssize_t as726x_write(FAR struct file *filep,
+                            FAR const char *buffer, size_t buflen)
+{
+  return -ENOSYS;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: as726x_register
+ *
+ * Description:
+ *   Register the AS726X character device as 'devpath'
+ *
+ * Input Parameters:
+ *   devpath - The full path to the driver to register. E.g., "/dev/spectr0"
+ *   i2c - An instance of the I2C interface to use to communicate with AS726X
+ *   addr - The I2C address of the AS726X.
+ *
+ * Returned Value:
+ *   Zero (OK) on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int as726x_register(FAR const char *devpath, FAR struct i2c_master_s *i2c)
+{
+  uint8_t _sensor_version;
+  uint8_t value;
+  int ret;
+
+  /* Sanity check */
+
+  DEBUGASSERT(i2c != NULL);
+
+  /* Initialize the AS726X device structure */
+
+  FAR struct as726x_dev_s *priv =
+    (FAR struct as726x_dev_s *)kmm_malloc(sizeof(struct as726x_dev_s));
+
+  if (priv == NULL)
+    {
+      snerr("ERROR: Failed to allocate instance\n");
+      return -ENOMEM;
+    }
+
+  priv->i2c = i2c;
+  priv->addr = AS726X_I2C_ADDR;
+
+   /* Check HW version for AS7262 and AS7263 */
+
+  _sensor_version = as726x_read8(priv, AS726x_HW_VERSION);
+  if (_sensor_version != 0x3e && _sensor_version != 0x3f)
+    {
+      snerr("ID (should be 0x3e or 0x3f): 0x %d\n", ret);
+    }
+
+  /* Initialize the device
+   * Read the register value toggle and disable led
+   */
+
+  ret = as726x_read8(priv, AS726x_LED_CONTROL);
+  if (ret < 0)
+    {
+      snerr("ERROR: Failed to initialize the AS726X!\n");
+      return ret;
+    }
+
+  value  = ret;
+  value &= ~(1 << 0);           /* Clear the bit */
+
+  as726x_write8(priv, AS726x_LED_CONTROL, value);
+
+  /* If you use Mode 2 or 3 (all the colors) then integration time is double.
+   * 140*2 = 280ms between readings.
+   * 50 * 2.8ms = 140ms. 0 to 255 is valid.
+   */
+
+  as726x_write8(priv, AS726x_INT_T, AS726X_INTEGRATION_TIME);
+
+  ret = as726x_read8(priv, AS726x_CONTROL_SETUP);
+  if (ret < 0)
+    {
+      snerr("ERROR: Failed to initialize the AS726X!\n");
+      return ret;
+    }
+
+  value  = ret;
+  value &= 0 b11001111;         /* Clear GAIN bits */
+  value |= (AS726X_GAIN << 4);  /* Set GAIN bits with user's choice */
+
+  as726x_write8(priv, AS726x_CONTROL_SETUP, value);
+
+  ret = as726x_read8(priv, AS726x_CONTROL_SETUP);
+  if (ret < 0)
+    {
+      snerr("ERROR: Failed to initialize the AS726X!\n");
+      return ret;
+    }
+
+  value  = ret;
+  value &= 0 b11110011;                     /* Clear BANK bits */
+  value |= (AS726X_MEASURMENT_MODE << 2);   /* Set BANK bits with user's
+                                             * choice */
+
+  as726x_write8(priv, AS726x_CONTROL_SETUP, value);
+
+  /* Register the character driver */
+
+  ret = register_driver(devpath, &g_as726x_fops, 0666, priv);
+  if (ret < 0)
+    {
+      snerr("ERROR: Failed to register driver: %d\n", ret);
+      kmm_free(priv);
+    }
+
+  return ret;
+}
+
+#endif /* CONFIG_I2C && CONFIG_SENSORS_AS726X */
diff --git a/drivers/sensors/bh1750fvi.c b/drivers/sensors/bh1750fvi.c
index 2f90470bcc4..9ac16a873a3 100644
--- a/drivers/sensors/bh1750fvi.c
+++ b/drivers/sensors/bh1750fvi.c
@@ -106,10 +106,8 @@ static const struct file_operations g_bh1750fvi_fops =
   bh1750fvi_read,   /* read */
   bh1750fvi_write,  /* write */
   NULL,             /* seek */
-  bh1750fvi_ioctl   /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL            /* poll */
-#endif
+  bh1750fvi_ioctl,  /* ioctl */
+  NULL              /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL            /* unlink */
 #endif
diff --git a/drivers/sensors/bmg160.c b/drivers/sensors/bmg160.c
index f84b32592bb..a94a24ad167 100644
--- a/drivers/sensors/bmg160.c
+++ b/drivers/sensors/bmg160.c
@@ -117,10 +117,8 @@ static const struct file_operations g_bmg160_fops =
   bmg160_read,
   bmg160_write,
   NULL,
-  bmg160_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  bmg160_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
diff --git a/drivers/sensors/bmp180.c b/drivers/sensors/bmp180.c
index 5bfd1defa3b..63e0567cb62 100644
--- a/drivers/sensors/bmp180.c
+++ b/drivers/sensors/bmp180.c
@@ -164,10 +164,8 @@ static const struct file_operations g_bmp180fops =
   bmp180_read,                  /* read */
   bmp180_write,                 /* write */
   NULL,                         /* seek */
-  NULL                          /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL                        /* poll */
-#endif
+  NULL,                         /* ioctl */
+  NULL                          /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL                        /* unlink */
 #endif
diff --git a/drivers/sensors/dhtxx.c b/drivers/sensors/dhtxx.c
index c9b72bb2464..6e142055a10 100644
--- a/drivers/sensors/dhtxx.c
+++ b/drivers/sensors/dhtxx.c
@@ -133,10 +133,8 @@ static const struct file_operations g_dhtxxfops =
   dhtxx_read,   /* read */
   dhtxx_write,  /* write */
   NULL,         /* seek */
-  dhtxx_ioctl   /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL        /* poll */
-#endif
+  dhtxx_ioctl,  /* ioctl */
+  NULL          /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL        /* unlink */
 #endif
diff --git a/drivers/sensors/hc_sr04.c b/drivers/sensors/hc_sr04.c
index 9865da7dbf4..815c594ffe4 100644
--- a/drivers/sensors/hc_sr04.c
+++ b/drivers/sensors/hc_sr04.c
@@ -72,10 +72,8 @@ static ssize_t hcsr04_read(FAR struct file *filep, FAR char *buffer,
 static ssize_t hcsr04_write(FAR struct file *filep, FAR const char *buffer,
                             size_t buflen);
 static int hcsr04_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int hcsr04_poll(FAR struct file *filep, FAR struct pollfd *fds,
                        bool setup);
-#endif
 
 /****************************************************************************
  * Private Types
@@ -89,9 +87,7 @@ struct hcsr04_dev_s
   int time_start_pulse;
   int time_finish_pulse;
   volatile bool rising;
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_HCSR04_NPOLLWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -105,10 +101,8 @@ static const struct file_operations g_hcsr04ops =
   hcsr04_read,   /* read */
   hcsr04_write,  /* write */
   NULL,          /* seek */
-  hcsr04_ioctl   /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , hcsr04_poll  /* poll */
-#endif
+  hcsr04_ioctl,  /* ioctl */
+  hcsr04_poll    /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL         /* unlink */
 #endif
@@ -316,7 +310,6 @@ static int hcsr04_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
   return ret;
 }
 
-#ifndef CONFIG_DISABLE_POLL
 static bool hcsr04_sample(FAR struct hcsr04_dev_s *priv)
 {
   int done;
@@ -439,7 +432,6 @@ out:
   nxsem_post(&priv->devsem);
   return ret;
 }
-#endif /* !CONFIG_DISABLE_POLL */
 
 static int hcsr04_int_handler(int irq, FAR void *context, FAR void *arg)
 {
@@ -477,9 +469,7 @@ static int hcsr04_int_handler(int irq, FAR void *context, FAR void *arg)
     }
 
   hcsr04_dbg("HC-SR04 interrupt\n");
-#ifndef CONFIG_DISABLE_POLL
   hcsr04_notify(priv);
-#endif
 
   return OK;
 }
diff --git a/drivers/sensors/hts221.c b/drivers/sensors/hts221.c
index 6541d4291f3..8fd4c17c270 100644
--- a/drivers/sensors/hts221.c
+++ b/drivers/sensors/hts221.c
@@ -126,10 +126,8 @@ static ssize_t hts221_read(FAR struct file *filep, FAR char *buffer,
 static ssize_t hts221_write(FAR struct file *filep, FAR const char *buffer,
                             size_t buflen);
 static int hts221_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int hts221_poll(FAR struct file *filep, FAR struct pollfd *fds,
                        bool setup);
-#endif
 
 /****************************************************************************
 * Private Types
@@ -142,9 +140,7 @@ struct hts221_dev_s
   hts221_config_t *config;
   sem_t devsem;
   volatile bool int_pending;
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_HTS221_NPOLLWAITERS];
-#endif
   struct
   {
     int16_t t0_out;
@@ -169,10 +165,8 @@ static const struct file_operations g_humidityops =
   hts221_read,   /* read */
   hts221_write,  /* write */
   NULL,          /* seek */
-  hts221_ioctl   /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , hts221_poll  /* poll */
-#endif
+  hts221_ioctl,  /* ioctl */
+  hts221_poll    /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL         /* unlink */
 #endif
@@ -1056,7 +1050,6 @@ static int hts221_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
   return ret;
 }
 
-#ifndef CONFIG_DISABLE_POLL
 static bool hts221_sample(FAR struct hts221_dev_s *priv)
 {
   int ret;
@@ -1188,7 +1181,6 @@ out:
   nxsem_post(&priv->devsem);
   return ret;
 }
-#endif /* !CONFIG_DISABLE_POLL */
 
 static int hts221_int_handler(int irq, FAR void *context, FAR void *arg)
 {
@@ -1198,9 +1190,7 @@ static int hts221_int_handler(int irq, FAR void *context, FAR void *arg)
 
   priv->int_pending = true;
   hts221_dbg("Hts221 interrupt\n");
-#ifndef CONFIG_DISABLE_POLL
   hts221_notify(priv);
-#endif
 
   return OK;
 }
diff --git a/drivers/sensors/ina219.c b/drivers/sensors/ina219.c
index 6c322dce798..762f3978051 100644
--- a/drivers/sensors/ina219.c
+++ b/drivers/sensors/ina219.c
@@ -132,10 +132,8 @@ static const struct file_operations g_ina219fops =
   ina219_read,
   ina219_write,
   NULL,
-  ina219_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  ina219_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
diff --git a/drivers/sensors/ina226.c b/drivers/sensors/ina226.c
index 83aa991a1d1..e076b5723c4 100644
--- a/drivers/sensors/ina226.c
+++ b/drivers/sensors/ina226.c
@@ -115,10 +115,8 @@ static const struct file_operations g_ina226fops =
   ina226_read,
   ina226_write,
   NULL,
-  ina226_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  ina226_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
diff --git a/drivers/sensors/ina3221.c b/drivers/sensors/ina3221.c
index 2adb6c4dc5c..9ef6b4119a3 100644
--- a/drivers/sensors/ina3221.c
+++ b/drivers/sensors/ina3221.c
@@ -142,10 +142,8 @@ static const struct file_operations g_ina3221fops =
   ina3221_read,
   ina3221_write,
   NULL,
-  ina3221_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  ina3221_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
diff --git a/drivers/sensors/kxtj9.c b/drivers/sensors/kxtj9.c
index ed50d6260fa..1c6235ad0c0 100644
--- a/drivers/sensors/kxtj9.c
+++ b/drivers/sensors/kxtj9.c
@@ -181,9 +181,7 @@ static const struct file_operations g_fops =
   kxtj9_write,
   NULL,
   kxtj9_ioctl,
-#ifndef CONFIG_DISABLE_POLL
   NULL,
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   NULL,
 #endif
diff --git a/drivers/sensors/l3gd20.c b/drivers/sensors/l3gd20.c
index c7c7add92c2..0a21416d518 100644
--- a/drivers/sensors/l3gd20.c
+++ b/drivers/sensors/l3gd20.c
@@ -123,10 +123,8 @@ static const struct file_operations g_l3gd20_fops =
   l3gd20_read,
   l3gd20_write,
   NULL,
-  l3gd20_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  l3gd20_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
diff --git a/drivers/sensors/lis2dh.c b/drivers/sensors/lis2dh.c
index 64de6dc899f..e5e30f240c2 100644
--- a/drivers/sensors/lis2dh.c
+++ b/drivers/sensors/lis2dh.c
@@ -114,9 +114,7 @@ struct lis2dh_dev_s
 #else
   volatile bool              int_pending; /* Interrupt received but data not read, yet */
 #endif
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd              *fds[CONFIG_LIS2DH_NPOLLWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -136,11 +134,9 @@ static int            lis2dh_get_reading(FAR struct lis2dh_dev_s *dev,
                         FAR struct lis2dh_vector_s *res, bool force_read);
 static int            lis2dh_powerdown(FAR struct lis2dh_dev_s *dev);
 static int            lis2dh_reboot(FAR struct lis2dh_dev_s *dev);
-#ifndef CONFIG_DISABLE_POLL
 static int            lis2dh_poll(FAR struct file *filep,
                         FAR struct pollfd *fds, bool setup);
 static void           lis2dh_notify(FAR struct lis2dh_dev_s *priv);
-#endif
 static int            lis2dh_int_handler(int irq, FAR void *context,
                         FAR void *arg);
 static int            lis2dh_setup(FAR struct lis2dh_dev_s *dev,
@@ -174,10 +170,8 @@ static const struct file_operations g_lis2dhops =
   lis2dh_read,   /* read */
   lis2dh_write,  /* write */
   NULL,          /* seek */
-  lis2dh_ioctl   /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , lis2dh_poll  /* poll */
-#endif
+  lis2dh_ioctl,  /* ioctl */
+  lis2dh_poll    /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL         /* unlink */
 #endif
@@ -457,10 +451,7 @@ static ssize_t lis2dh_read(FAR struct file *filep, FAR char *buffer,
           priv->int_pending = true;
 #endif
 
-#ifndef CONFIG_DISABLE_POLL
           lis2dh_notify(priv);
-#endif
-
           leave_critical_section(flags);
         }
       else if (fifo_mode != LIS2DH_STREAM_MODE && priv->fifo_stopped)
@@ -675,7 +666,6 @@ static int lis2dh_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  *
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int lis2dh_poll(FAR struct file *filep, FAR struct pollfd *fds,
                        bool setup)
 {
@@ -777,7 +767,6 @@ static void lis2dh_notify(FAR struct lis2dh_dev_s *priv)
         }
     }
 }
-#endif /* !CONFIG_DISABLE_POLL */
 
 /****************************************************************************
  * Name: lis2dh_callback
@@ -802,10 +791,7 @@ static int lis2dh_int_handler(int irq, FAR void *context, FAR void *arg)
   priv->int_pending = true;
 #endif
 
-#ifndef CONFIG_DISABLE_POLL
   lis2dh_notify(priv);
-#endif
-
   leave_critical_section(flags);
 
   return OK;
diff --git a/drivers/sensors/lis3dh.c b/drivers/sensors/lis3dh.c
index af66ceec4da..845731830eb 100644
--- a/drivers/sensors/lis3dh.c
+++ b/drivers/sensors/lis3dh.c
@@ -124,10 +124,8 @@ static const struct file_operations g_lis3dh_fops =
   lis3dh_read,
   lis3dh_write,
   NULL,
-  lis3dh_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  lis3dh_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
diff --git a/drivers/sensors/lis3dsh.c b/drivers/sensors/lis3dsh.c
index aa94b1c3bfa..f93a2a0d1db 100644
--- a/drivers/sensors/lis3dsh.c
+++ b/drivers/sensors/lis3dsh.c
@@ -119,10 +119,8 @@ static const struct file_operations g_lis3dsh_fops =
   lis3dsh_read,
   lis3dsh_write,
   NULL,
-  lis3dsh_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  lis3dsh_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
diff --git a/drivers/sensors/lis3mdl.c b/drivers/sensors/lis3mdl.c
index 99d2b2b2d3f..9dccc1f98ad 100644
--- a/drivers/sensors/lis3mdl.c
+++ b/drivers/sensors/lis3mdl.c
@@ -119,10 +119,8 @@ static const struct file_operations g_lis3mdl_fops =
   lis3mdl_read,
   lis3mdl_write,
   NULL,
-  lis3mdl_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  lis3mdl_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
diff --git a/drivers/sensors/lm75.c b/drivers/sensors/lm75.c
index f5f4ce6fa78..113f368ff83 100644
--- a/drivers/sensors/lm75.c
+++ b/drivers/sensors/lm75.c
@@ -115,10 +115,8 @@ static const struct file_operations g_lm75fops =
   lm75_read,
   lm75_write,
   NULL,
-  lm75_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  lm75_ioctl,
+  NULL
 };
 
 /****************************************************************************
@@ -449,7 +447,7 @@ static int lm75_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
         }
         break;
 
-      /* Wrtie to the configuration register. Arg:  uint8_t value */
+      /* Write to the configuration register. Arg:  uint8_t value */
 
       case SNIOC_WRITECONF:
         ret = lm75_writeconf(priv, (uint8_t)arg);
diff --git a/drivers/sensors/lm92.c b/drivers/sensors/lm92.c
index cd2aa13b350..791131ae533 100644
--- a/drivers/sensors/lm92.c
+++ b/drivers/sensors/lm92.c
@@ -117,10 +117,8 @@ static const struct file_operations g_lm92fops =
   lm92_read,
   lm92_write,
   NULL,
-  lm92_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  lm92_ioctl,
+  NULL
 };
 
 /****************************************************************************
diff --git a/drivers/sensors/lps25h.c b/drivers/sensors/lps25h.c
index dd47fd84284..d3e0630c3a5 100644
--- a/drivers/sensors/lps25h.c
+++ b/drivers/sensors/lps25h.c
@@ -225,10 +225,8 @@ static const struct file_operations g_lps25hops =
   lps25h_read,   /* read */
   lps25h_write,  /* write */
   NULL,          /* seek */
-  lps25h_ioctl   /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL         /* poll */
-#endif
+  lps25h_ioctl,  /* ioctl */
+  NULL           /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL         /* unlink */
  #endif
diff --git a/drivers/sensors/lsm303agr.c b/drivers/sensors/lsm303agr.c
index 7a2b3340bb5..1adeabfe256 100644
--- a/drivers/sensors/lsm303agr.c
+++ b/drivers/sensors/lsm303agr.c
@@ -133,10 +133,8 @@ static const struct file_operations g_fops =
   lsm303agr_read,
   lsm303agr_write,
   NULL,
-  lsm303agr_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  lsm303agr_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
diff --git a/drivers/sensors/lsm330_spi.c b/drivers/sensors/lsm330_spi.c
index a99c28a951b..27b3cc253b6 100644
--- a/drivers/sensors/lsm330_spi.c
+++ b/drivers/sensors/lsm330_spi.c
@@ -165,10 +165,8 @@ static const struct file_operations g_lsm330a_fops =
   lsm330acl_read,
   lsm330acl_write,
   lsm330acl_seek,
-  lsm330_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  lsm330_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
@@ -181,10 +179,8 @@ static const struct file_operations g_lsm330g_fops =
   lsm330gyro_read,
   lsm330gyro_write,
   lsm330gyro_seek,
-  lsm330_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  lsm330_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
diff --git a/drivers/sensors/lsm6dsl.c b/drivers/sensors/lsm6dsl.c
index d0458b97348..6880aa1ef4f 100644
--- a/drivers/sensors/lsm6dsl.c
+++ b/drivers/sensors/lsm6dsl.c
@@ -132,10 +132,8 @@ static const struct file_operations g_fops =
   lsm6dsl_read,
   lsm6dsl_write,
   NULL,
-  lsm6dsl_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  lsm6dsl_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #  endif
diff --git a/drivers/sensors/lsm9ds1.c b/drivers/sensors/lsm9ds1.c
index 65276cf0faa..f60a2fbb41e 100644
--- a/drivers/sensors/lsm9ds1.c
+++ b/drivers/sensors/lsm9ds1.c
@@ -592,9 +592,7 @@ static const struct file_operations g_fops =
   lsm9ds1_write,
   NULL,
   lsm9ds1_ioctl,
-#ifndef CONFIG_DISABLE_POLL
   NULL,
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   NULL,
 #endif
diff --git a/drivers/sensors/ltc4151.c b/drivers/sensors/ltc4151.c
index 81eb772afbb..897df65335c 100644
--- a/drivers/sensors/ltc4151.c
+++ b/drivers/sensors/ltc4151.c
@@ -105,10 +105,8 @@ static const struct file_operations g_ltc4151fops =
   ltc4151_read,
   ltc4151_write,
   NULL,
-  ltc4151_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  ltc4151_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
diff --git a/drivers/sensors/max31855.c b/drivers/sensors/max31855.c
index fe2cbf0c7b9..93688c91fca 100644
--- a/drivers/sensors/max31855.c
+++ b/drivers/sensors/max31855.c
@@ -107,10 +107,8 @@ static const struct file_operations g_max31855fops =
   max31855_read,
   max31855_write,
   NULL,
+  NULL,
   NULL
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
 };
 
 /****************************************************************************
diff --git a/drivers/sensors/max44009.c b/drivers/sensors/max44009.c
index 569f6509ebf..3990ed9cfa9 100644
--- a/drivers/sensors/max44009.c
+++ b/drivers/sensors/max44009.c
@@ -93,9 +93,7 @@ struct max44009_dev_s
   uint8_t addr;
   uint8_t cref;
   bool int_pending;
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_MAX44009_NPOLLWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -109,10 +107,8 @@ static ssize_t max44009_read(FAR struct file *filep, FAR char *buffer,
 static ssize_t max44009_write(FAR struct file *filep, FAR const char *buffer,
                               size_t buflen);
 static int max44009_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int max44009_poll(FAR struct file *filep, FAR struct pollfd *fds,
                          bool setup);
-#endif
 
 static int max44009_read_data(FAR struct max44009_dev_s *priv,
                               FAR struct max44009_data_s *data);
@@ -128,10 +124,8 @@ static const struct file_operations g_alsops =
   max44009_read,   /* read */
   max44009_write,  /* write */
   NULL,            /* seek */
-  max44009_ioctl   /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , max44009_poll  /* poll */
-#endif
+  max44009_ioctl,  /* ioctl */
+  max44009_poll    /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL           /* unlink */
 #endif
@@ -794,7 +788,6 @@ static int max44009_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
   return ret;
 }
 
-#ifndef CONFIG_DISABLE_POLL
 static void max44009_notify(FAR struct max44009_dev_s *priv)
 {
   DEBUGASSERT(priv != NULL);
@@ -900,7 +893,6 @@ out:
   nxsem_post(&priv->dev_sem);
   return ret;
 }
-#endif /* !CONFIG_DISABLE_POLL */
 
 static int max44009_int_handler(int irq, FAR void *context, FAR void *arg)
 {
@@ -912,9 +904,7 @@ static int max44009_int_handler(int irq, FAR void *context, FAR void *arg)
   flags = enter_critical_section();
   priv->int_pending = true;
   leave_critical_section(flags);
-#ifndef CONFIG_DISABLE_POLL
   max44009_notify(priv);
-#endif
   max44009_dbg("MAX44009 interrupt\n");
 
   return OK;
diff --git a/drivers/sensors/max6675.c b/drivers/sensors/max6675.c
index 9d6c944536b..e804ae6b573 100644
--- a/drivers/sensors/max6675.c
+++ b/drivers/sensors/max6675.c
@@ -103,10 +103,8 @@ static const struct file_operations g_max6675fops =
   max6675_read,
   max6675_write,
   NULL,
+  NULL,
   NULL
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
 };
 
 /****************************************************************************
diff --git a/drivers/sensors/mb7040.c b/drivers/sensors/mb7040.c
index bba31620234..2981ac82aee 100644
--- a/drivers/sensors/mb7040.c
+++ b/drivers/sensors/mb7040.c
@@ -105,10 +105,8 @@ static const struct file_operations g_fops =
   mb7040_read,
   mb7040_write,
   NULL,
-  mb7040_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  mb7040_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
diff --git a/drivers/sensors/mcp9844.c b/drivers/sensors/mcp9844.c
index 22f9057fac9..f1b124069c3 100644
--- a/drivers/sensors/mcp9844.c
+++ b/drivers/sensors/mcp9844.c
@@ -105,10 +105,8 @@ static const struct file_operations g_mcp9844_fops =
   mcp9844_read,
   mcp9844_write,
   NULL,
-  mcp9844_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  mcp9844_ioctl,
+  NULL
 };
 
 /****************************************************************************
diff --git a/drivers/sensors/mlx90393.c b/drivers/sensors/mlx90393.c
index 299fd84e10d..08dc16838c7 100644
--- a/drivers/sensors/mlx90393.c
+++ b/drivers/sensors/mlx90393.c
@@ -118,10 +118,8 @@ static const struct file_operations g_mlx90393_fops =
   mlx90393_read,
   mlx90393_write,
   NULL,
-  mlx90393_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  mlx90393_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
diff --git a/drivers/sensors/mlx90614.c b/drivers/sensors/mlx90614.c
index 0948b774b4e..61e2a2ef2b9 100644
--- a/drivers/sensors/mlx90614.c
+++ b/drivers/sensors/mlx90614.c
@@ -104,11 +104,9 @@ static const struct file_operations g_mlx90614_fops =
   mlx90614_close,  /* close */
   mlx90614_read,   /* read */
   mlx90614_write,  /* write */
-  NULL,             /* seek */
-  mlx90614_ioctl   /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL            /* poll */
-#endif
+  NULL,            /* seek */
+  mlx90614_ioctl,  /* ioctl */
+  NULL             /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL            /* unlink */
 #endif
diff --git a/drivers/sensors/mpl115a.c b/drivers/sensors/mpl115a.c
index c4ea87de60e..1299f7a408e 100644
--- a/drivers/sensors/mpl115a.c
+++ b/drivers/sensors/mpl115a.c
@@ -102,12 +102,12 @@ static const struct file_operations g_mpl115afops =
   mpl115a_close,  /* close */
   mpl115a_read,   /* read */
   mpl115a_write,  /* write */
-  0,              /* seek */
-  0,              /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  0,              /* poll */
+  NULL,           /* seek */
+  NULL,           /* ioctl */
+  NULL,           /* poll */
+#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
+  NULL            /* unlink */
 #endif
-  0               /* unlink */
 };
 
 /****************************************************************************
diff --git a/drivers/sensors/mpu60x0.c b/drivers/sensors/mpu60x0.c
index 39bcd9db2eb..59addb345c3 100644
--- a/drivers/sensors/mpu60x0.c
+++ b/drivers/sensors/mpu60x0.c
@@ -281,12 +281,10 @@ static const struct file_operations g_mpu_fops =
   mpu_read,
   mpu_write,
   mpu_seek,
-  mpu_ioctl
-#ifndef CONFIG_DISABLE_POLL
-    , NULL
-#endif
+  mpu_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
-    , NULL
+  , NULL
 #endif
 };
 
diff --git a/drivers/sensors/ms58xx.c b/drivers/sensors/ms58xx.c
index d36b5865f69..cc3af19cc7a 100644
--- a/drivers/sensors/ms58xx.c
+++ b/drivers/sensors/ms58xx.c
@@ -180,10 +180,8 @@ static const struct file_operations g_fops =
   ms58xx_read,
   ms58xx_write,
   NULL,
-  ms58xx_ioctl
-#ifndef CONFIG_DISABLE_POLL
-  , NULL
-#endif
+  ms58xx_ioctl,
+  NULL
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL
 #endif
diff --git a/drivers/sensors/qencoder.c b/drivers/sensors/qencoder.c
index 6649bf0ab39..385d3ad8c33 100644
--- a/drivers/sensors/qencoder.c
+++ b/drivers/sensors/qencoder.c
@@ -98,11 +98,9 @@ static const struct file_operations g_qeops =
   qe_close, /* close */
   qe_read,  /* read */
   qe_write, /* write */
-  0,         /* seek */
-  qe_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0        /* poll */
-#endif
+  NULL,     /* seek */
+  qe_ioctl, /* ioctl */
+  NULL      /* poll */
 };
 
 /****************************************************************************
diff --git a/drivers/sensors/scd30.c b/drivers/sensors/scd30.c
index a1e13ce4f4a..65918c71210 100644
--- a/drivers/sensors/scd30.c
+++ b/drivers/sensors/scd30.c
@@ -193,10 +193,8 @@ static const struct file_operations g_scd30fops =
   scd30_read,     /* read */
   scd30_write,    /* write */
   NULL,           /* seek */
-  scd30_ioctl     /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL          /* poll */
-#endif
+  scd30_ioctl,    /* ioctl */
+  NULL            /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , scd30_unlink /* unlink */
 #endif
diff --git a/drivers/sensors/sgp30.c b/drivers/sensors/sgp30.c
index dc89eb5878e..282e4472f64 100644
--- a/drivers/sensors/sgp30.c
+++ b/drivers/sensors/sgp30.c
@@ -166,10 +166,8 @@ static const struct file_operations g_sgp30fops =
   sgp30_read,     /* read */
   sgp30_write,    /* write */
   NULL,           /* seek */
-  sgp30_ioctl     /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL          /* poll */
-#endif
+  sgp30_ioctl,    /* ioctl */
+  NULL            /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , sgp30_unlink /* unlink */
 #endif
diff --git a/drivers/sensors/sht21.c b/drivers/sensors/sht21.c
index 7a16714b10e..ad3c5ffdee5 100644
--- a/drivers/sensors/sht21.c
+++ b/drivers/sensors/sht21.c
@@ -143,10 +143,8 @@ static const struct file_operations g_sht21fops =
   sht21_read,     /* read */
   sht21_write,    /* write */
   NULL,           /* seek */
-  sht21_ioctl     /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL          /* poll */
-#endif
+  sht21_ioctl,    /* ioctl */
+  NULL            /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , sht21_unlink /* unlink */
 #endif
diff --git a/drivers/sensors/sps30.c b/drivers/sensors/sps30.c
index 63fd644f28e..53bddd3ffad 100644
--- a/drivers/sensors/sps30.c
+++ b/drivers/sensors/sps30.c
@@ -187,10 +187,8 @@ static const struct file_operations g_sps30fops =
   sps30_read,     /* read */
   sps30_write,    /* write */
   NULL,           /* seek */
-  sps30_ioctl     /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL          /* poll */
-#endif
+  sps30_ioctl,    /* ioctl */
+  NULL            /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , sps30_unlink /* unlink */
 #endif
diff --git a/drivers/sensors/t67xx.c b/drivers/sensors/t67xx.c
index da827b3faf0..1a73b68bbfc 100644
--- a/drivers/sensors/t67xx.c
+++ b/drivers/sensors/t67xx.c
@@ -178,10 +178,8 @@ static const struct file_operations g_t67xxfops =
   t67xx_read,     /* read */
   t67xx_write,    /* write */
   NULL,           /* seek */
-  t67xx_ioctl     /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL          /* poll */
-#endif
+  t67xx_ioctl,    /* ioctl */
+  NULL            /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL          /* unlink */
 #endif
diff --git a/drivers/sensors/veml6070.c b/drivers/sensors/veml6070.c
index 2255f0618a9..2009f8512f1 100644
--- a/drivers/sensors/veml6070.c
+++ b/drivers/sensors/veml6070.c
@@ -102,10 +102,8 @@ static const struct file_operations g_veml6070_fops =
   veml6070_read,   /* read */
   veml6070_write,  /* write */
   NULL,            /* seek */
-  NULL             /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL           /* poll */
-#endif
+  NULL,            /* ioctl */
+  NULL             /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL           /* unlink */
 #endif
diff --git a/drivers/sensors/xen1210.c b/drivers/sensors/xen1210.c
index e29cf8fb0c2..32602425409 100644
--- a/drivers/sensors/xen1210.c
+++ b/drivers/sensors/xen1210.c
@@ -79,10 +79,8 @@ static const struct file_operations g_xen1210fops =
   xen1210_read,    /* read */
   NULL,            /* write */
   NULL,            /* seek */
-  NULL             /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL           /* poll */
-#endif
+  NULL,            /* ioctl */
+  NULL             /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL           /* unlink */
 #endif
diff --git a/drivers/sensors/zerocross.c b/drivers/sensors/zerocross.c
index 611187f04d2..8e04ea550ce 100644
--- a/drivers/sensors/zerocross.c
+++ b/drivers/sensors/zerocross.c
@@ -61,14 +61,6 @@
 
 #ifdef CONFIG_SENSORS_ZEROCROSS
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#ifdef CONFIG_DISABLE_SIGNALS
-#  error "This driver needs SIGNAL support, remove CONFIG_DISABLE_SIGNALS"
-#endif
-
 /****************************************************************************
  * Private Type Definitions
  ****************************************************************************/
@@ -133,11 +125,9 @@ static const struct file_operations g_zcops =
   zc_close,  /* close */
   zc_read,   /* read */
   zc_write,  /* write */
-  0,         /* seek */
-  zc_ioctl   /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0        /* poll */
-#endif
+  NULL,      /* seek */
+  zc_ioctl,  /* ioctl */
+  NULL       /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , 0        /* unlink */
 #endif
@@ -433,36 +423,34 @@ static int zc_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
   ret = -EINVAL;
   switch (cmd)
     {
-#ifndef CONFIG_DISABLE_SIGNALS
-    /* Command:     ZCIOC_REGISTER
-     * Description: Register to receive a signal whenever there is zero
-     *              cross detection interrupt.
-     * Argument:    A read-only pointer to an instance of struct
-     *              zc_notify_s
-     * Return:      Zero (OK) on success.  Minus one will be returned on
-     *              failure with the errno value set appropriately.
-     */
+      /* Command:     ZCIOC_REGISTER
+       * Description: Register to receive a signal whenever there is zero
+       *              cross detection interrupt.
+       * Argument:    A read-only pointer to an instance of struct
+       *              zc_notify_s
+       * Return:      Zero (OK) on success.  Minus one will be returned on
+       *              failure with the errno value set appropriately.
+       */
 
-    case ZCIOC_REGISTER:
-      {
-        FAR struct sigevent *event =
-          (FAR struct sigevent *)((uintptr_t)arg);
+      case ZCIOC_REGISTER:
+        {
+          FAR struct sigevent *event =
+            (FAR struct sigevent *)((uintptr_t)arg);
 
-        if (event)
-          {
-            /* Save the notification events */
+          if (event)
+            {
+              /* Save the notification events */
 
-            opriv->do_event = *event;
-            opriv->do_pid   = getpid();
+              opriv->do_event = *event;
+              opriv->do_pid   = getpid();
 
-            /* Enable/disable interrupt handling */
+              /* Enable/disable interrupt handling */
 
-            zerocross_enable(priv);
-            ret = OK;
-          }
-      }
-      break;
-#endif
+              zerocross_enable(priv);
+              ret = OK;
+            }
+        }
+        break;
 
       default:
         {
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 448e7aef727..2aa8311d97c 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -6,8 +6,7 @@
 config DEV_LOWCONSOLE
 	bool "Low-level console support"
 	default n
-	depends on ARCH_LOWPUTC
-	depends on DEV_CONSOLE
+	depends on ARCH_LOWPUTC && DEV_CONSOLE
 	---help---
 		Use the simple, low-level, write-only serial console driver (minimal support)
 
@@ -72,7 +71,7 @@ config STANDARD_SERIAL
 config SERIAL_NPOLLWAITERS
 	int "Number of poll threads"
 	default 2
-	depends on !DISABLE_POLL && STANDARD_SERIAL
+	depends on STANDARD_SERIAL
 	---help---
 		Maximum number of threads than can be waiting for POLL events.
 		Default: 2
@@ -81,11 +80,21 @@ config SERIAL_IFLOWCONTROL
 	bool
 	default n
 
+config SERIAL_RS485CONTROL
+	bool
+	default n
+	---help---
+		Use RTS pin to control RS485 direction (Asserted while transmitting).
+
 config SERIAL_OFLOWCONTROL
 	bool
 	default n
 
-config SERIAL_DMA
+config SERIAL_TXDMA
+	bool
+	default n
+
+config SERIAL_RXDMA
 	bool
 	default n
 
@@ -152,7 +161,7 @@ config TTY_SIGINT
 	bool "Support SIGINT"
 	default n
 	select SIG_SIGKILL_ACTION
-	depends on !DISABLE_SIGNALS && SERIAL_TERMIOS
+	depends on SERIAL_TERMIOS
 	---help---
 		Whether support Ctrl-c/x event.  Enabled automatically for console
 		devices.  May be enabled for other serial devices using the ISIG bit
@@ -197,7 +206,7 @@ config TTY_SIGSTP
 	bool "Support SIGSTP"
 	default n
 	select CONFIG_SIG_SIGSTOP_ACTION
-	depends on !DISABLE_SIGNALS && SERIAL_TERMIOS
+	depends on SERIAL_TERMIOS
 	---help---
 		Whether support Ctrl-z event.  Enabled automatically for console
 		devices.  May be enabled for other serial devices using the ISIG bit
@@ -466,10 +475,17 @@ config UART_OFLOWCONTROL
 	---help---
 		Enable UART CTS flow control
 
-config UART_DMA
-	bool "UART DMA support"
+config UART_TXDMA
+	bool "UART Tx DMA support"
 	default n
-	select SERIAL_DMA
+	select SERIAL_TXDMA
+	---help---
+		Enable DMA transfers on UART
+
+config UART_RXDMA
+	bool "UART Rx DMA support"
+	default n
+	select SERIAL_RXDMA
 	---help---
 		Enable DMA transfers on UART
 
diff --git a/drivers/serial/Kconfig-lpuart b/drivers/serial/Kconfig-lpuart
index f700f9886b0..1ad57f6f5d1 100644
--- a/drivers/serial/Kconfig-lpuart
+++ b/drivers/serial/Kconfig-lpuart
@@ -53,6 +53,8 @@ config LPUART8_SERIALDRIVER
 	default n
 	select MCU_SERIAL
 
+#####################################################################################
+
 menu "LPUART0 Configuration"
 	depends on LPUART0_SERIALDRIVER
 
@@ -84,40 +86,64 @@ config LPUART0_BITS
 
 config LPUART0_PARITY
 	int "Parity setting"
-	range 0 2
 	default 0
+	range 0 2
 	---help---
 		0=no parity, 1=odd parity, 2=even parity
 
 config LPUART0_2STOP
-	int "use 2 stop bits"
+	int "Uses 2 stop bits"
 	default 0
 	---help---
 		1=Two stop bits
+choice
+	prompt "IFLOW Control"
+	default LPUART0_NOIFLOWCONTROL
+
+config LPUART0_NOIFLOWCONTROL
+	bool "No IFLOW control"
+	---help---
+		No IFLOW control
+
+config LPUART0_RS485RTSCONTROL
+	bool "RTS for RS485 Direction"
+	select SERIAL_RS485CONTROL
+	---help---
+		 Use RTS pin for RS485 direction switching
 
 config LPUART0_IFLOWCONTROL
-	bool "LPUART0 RTS flow control"
-	default n
+	bool "RTS for IFLOW control"
 	select SERIAL_IFLOWCONTROL
 	---help---
-		Enable LPUART0 RTS flow control
+		Enable RTS flow control
+endchoice
+
+config LPUART0_INVERTIFLOWCONTROL
+	depends on LPUART0_RS485RTSCONTROL || LPUART0_IFLOWCONTROL
+	bool "Invert sense of RTS bit"
+	default n
+	---help---
+		Make RTS bit active high rather than active low
 
 config LPUART0_OFLOWCONTROL
-	bool "LPUART0 CTS flow control"
+	depends on !LPUART0_RS485RTSCONTROL
+	bool "CTS OFLOW control"
 	default n
 	select SERIAL_OFLOWCONTROL
 	---help---
-		Enable LPUART0 CTS flow control
+		Enable CTS flow control
 
 config LPUART0_DMA
 	bool "LPUART0 DMA support"
 	default n
 	select SERIAL_DMA
 	---help---
-		Enable DMA transfers on LPUART0
+		Enable DMA transfers
 
 endmenu
 
+#####################################################################################
+
 menu "LPUART1 Configuration"
 	depends on LPUART1_SERIALDRIVER
 
@@ -159,30 +185,56 @@ config LPUART1_2STOP
 	default 0
 	---help---
 		1=Two stop bits
+choice
+	prompt "IFLOW Control"
+	default LPUART1_NOIFLOWCONTROL
+
+config LPUART1_NOIFLOWCONTROL
+	bool "No IFLOW control"
+	---help---
+		No IFLOW control
+
+config LPUART1_RS485RTSCONTROL
+	bool "RTS for RS485 Direction"
+	select SERIAL_RS485CONTROL
+	---help---
+		 Use RTS pin for RS485 direction switching
 
 config LPUART1_IFLOWCONTROL
-	bool "LPUART1 RTS flow control"
-	default n
+	bool "RTS for IFLOW control"
 	select SERIAL_IFLOWCONTROL
 	---help---
-		Enable LPUART1 RTS flow control
+		Enable RTS flow control
+endchoice
+
+config LPUART1_INVERTIFLOWCONTROL
+	depends on LPUART1_RS485RTSCONTROL || LPUART1_IFLOWCONTROL
+	bool "Invert sense of RTS bit"
+	default n
+	---help---
+		Make RTS bit active high rather than active low
 
 config LPUART1_OFLOWCONTROL
-	bool "LPUART1 CTS flow control"
+	depends on !LPUART1_RS485RTSCONTROL
+	bool "CTS OFLOW control"
 	default n
 	select SERIAL_OFLOWCONTROL
 	---help---
-		Enable LPUART1 CTS flow control
+		Enable CTS flow control
 
 config LPUART1_DMA
 	bool "LPUART1 DMA support"
 	default n
 	select SERIAL_DMA
 	---help---
-		Enable DMA transfers on LPUART1
+		Enable DMA transfers
 
 endmenu
 
+#####################################################################################
+
+#####################################################################################
+
 menu "LPUART2 Configuration"
 	depends on LPUART2_SERIALDRIVER
 
@@ -224,30 +276,54 @@ config LPUART2_2STOP
 	default 0
 	---help---
 		1=Two stop bits
+choice
+	prompt "IFLOW Control"
+	default LPUART2_NOIFLOWCONTROL
+
+config LPUART2_NOIFLOWCONTROL
+	bool "No IFLOW control"
+	---help---
+		No IFLOW control
+
+config LPUART2_RS485RTSCONTROL
+	bool "RTS for RS485 Direction"
+	select SERIAL_RS485CONTROL
+	---help---
+		 Use RTS pin for RS485 direction switching
 
 config LPUART2_IFLOWCONTROL
-	bool "LPUART2 RTS flow control"
-	default n
+	bool "RTS for IFLOW control"
 	select SERIAL_IFLOWCONTROL
 	---help---
-		Enable LPUART2 RTS flow control
+		Enable RTS flow control
+endchoice
+
+config LPUART2_INVERTIFLOWCONTROL
+	depends on LPUART2_RS485RTSCONTROL || LPUART2_IFLOWCONTROL
+	bool "Invert sense of RTS bit"
+	default n
+	---help---
+		Make RTS bit active high rather than active low
 
 config LPUART2_OFLOWCONTROL
-	bool "LPUART2 CTS flow control"
+	depends on !LPUART2_RS485RTSCONTROL
+	bool "CTS OFLOW control"
 	default n
 	select SERIAL_OFLOWCONTROL
 	---help---
-		Enable LPUART2 CTS flow control
+		Enable CTS flow control
 
 config LPUART2_DMA
 	bool "LPUART2 DMA support"
 	default n
 	select SERIAL_DMA
 	---help---
-		Enable DMA transfers on LPUART2
+		Enable DMA transfers
 
 endmenu
 
+#####################################################################################
+
 menu "LPUART3 Configuration"
 	depends on LPUART3_SERIALDRIVER
 
@@ -289,30 +365,54 @@ config LPUART3_2STOP
 	default 0
 	---help---
 		1=Two stop bits
+choice
+	prompt "IFLOW Control"
+	default LPUART3_NOIFLOWCONTROL
+
+config LPUART3_NOIFLOWCONTROL
+	bool "No IFLOW control"
+	---help---
+		No IFLOW control
+
+config LPUART3_RS485RTSCONTROL
+	bool "RTS for RS485 Direction"
+	select SERIAL_RS485CONTROL
+	---help---
+		 Use RTS pin for RS485 direction switching
 
 config LPUART3_IFLOWCONTROL
-	bool "LPUART3 RTS flow control"
-	default n
+	bool "RTS for IFLOW control"
 	select SERIAL_IFLOWCONTROL
 	---help---
-		Enable LPUART3 RTS flow control
+		Enable RTS flow control
+endchoice
+
+config LPUART3_INVERTIFLOWCONTROL
+	depends on LPUART3_RS485RTSCONTROL || LPUART3_IFLOWCONTROL
+	bool "Invert sense of RTS bit"
+	default n
+	---help---
+		Make RTS bit active high rather than active low
 
 config LPUART3_OFLOWCONTROL
-	bool "LPUART3 CTS flow control"
+	depends on !LPUART3_RS485RTSCONTROL
+	bool "CTS OFLOW control"
 	default n
 	select SERIAL_OFLOWCONTROL
 	---help---
-		Enable LPUART3 CTS flow control
+		Enable CTS flow control
 
 config LPUART3_DMA
 	bool "LPUART3 DMA support"
 	default n
 	select SERIAL_DMA
 	---help---
-		Enable DMA transfers on LPUART3
+		Enable DMA transfers
 
 endmenu
 
+#####################################################################################
+
 menu "LPUART4 Configuration"
 	depends on LPUART4_SERIALDRIVER
 
@@ -354,30 +454,54 @@ config LPUART4_2STOP
 	default 0
 	---help---
 		1=Two stop bits
+choice
+	prompt "IFLOW Control"
+	default LPUART4_NOIFLOWCONTROL
+
+config LPUART4_NOIFLOWCONTROL
+	bool "No IFLOW control"
+	---help---
+		No IFLOW control
+
+config LPUART4_RS485RTSCONTROL
+	bool "RTS for RS485 Direction"
+	select SERIAL_RS485CONTROL
+	---help---
+		 Use RTS pin for RS485 direction switching
 
 config LPUART4_IFLOWCONTROL
-	bool "LPUART4 RTS flow control"
-	default n
+	bool "RTS for IFLOW control"
 	select SERIAL_IFLOWCONTROL
 	---help---
-		Enable LPUART4 RTS flow control
+		Enable RTS flow control
+endchoice
+
+config LPUART4_INVERTIFLOWCONTROL
+	depends on LPUART4_RS485RTSCONTROL || LPUART4_IFLOWCONTROL
+	bool "Invert sense of RTS bit"
+	default n
+	---help---
+		Make RTS bit active high rather than active low
 
 config LPUART4_OFLOWCONTROL
-	bool "LPUART4 CTS flow control"
+	depends on !LPUART4_RS485RTSCONTROL
+	bool "CTS OFLOW control"
 	default n
 	select SERIAL_OFLOWCONTROL
 	---help---
-		Enable LPUART4 CTS flow control
+		Enable CTS flow control
 
 config LPUART4_DMA
 	bool "LPUART4 DMA support"
 	default n
 	select SERIAL_DMA
 	---help---
-		Enable DMA transfers on LPUART4
+		Enable DMA transfers
 
 endmenu
 
+#####################################################################################
+
 menu "LPUART5 Configuration"
 	depends on LPUART5_SERIALDRIVER
 
@@ -419,30 +543,54 @@ config LPUART5_2STOP
 	default 0
 	---help---
 		1=Two stop bits
+choice
+	prompt "IFLOW Control"
+	default LPUART5_NOIFLOWCONTROL
+
+config LPUART5_NOIFLOWCONTROL
+	bool "No IFLOW control"
+	---help---
+		No IFLOW control
+
+config LPUART5_RS485RTSCONTROL
+	bool "RTS for RS485 Direction"
+	select SERIAL_RS485CONTROL
+	---help---
+		 Use RTS pin for RS485 direction switching
 
 config LPUART5_IFLOWCONTROL
-	bool "LPUART5 RTS flow control"
-	default n
+	bool "RTS for IFLOW control"
 	select SERIAL_IFLOWCONTROL
 	---help---
-		Enable LPUART5 RTS flow control
+		Enable RTS flow control
+endchoice
+
+config LPUART5_INVERTIFLOWCONTROL
+	depends on LPUART5_RS485RTSCONTROL || LPUART5_IFLOWCONTROL
+	bool "Invert sense of RTS bit"
+	default n
+	---help---
+		Make RTS bit active high rather than active low
 
 config LPUART5_OFLOWCONTROL
-	bool "LPUART5 CTS flow control"
+	depends on !LPUART5_RS485RTSCONTROL
+	bool "CTS OFLOW control"
 	default n
 	select SERIAL_OFLOWCONTROL
 	---help---
-		Enable LPUART5 CTS flow control
+		Enable CTS flow control
 
 config LPUART5_DMA
 	bool "LPUART5 DMA support"
 	default n
 	select SERIAL_DMA
 	---help---
-		Enable DMA transfers on LPUART5
+		Enable DMA transfers
 
 endmenu
 
+#####################################################################################
+
 menu "LPUART6 Configuration"
 	depends on LPUART6_SERIALDRIVER
 
@@ -484,30 +632,54 @@ config LPUART6_2STOP
 	default 0
 	---help---
 		1=Two stop bits
+choice
+	prompt "IFLOW Control"
+	default LPUART6_NOIFLOWCONTROL
+
+config LPUART6_NOIFLOWCONTROL
+	bool "No IFLOW control"
+	---help---
+		No IFLOW control
+
+config LPUART6_RS485RTSCONTROL
+	bool "RTS for RS485 Direction"
+	select SERIAL_RS485CONTROL
+	---help---
+		 Use RTS pin for RS485 direction switching
 
 config LPUART6_IFLOWCONTROL
-	bool "LPUART6 RTS flow control"
-	default n
+	bool "RTS for IFLOW control"
 	select SERIAL_IFLOWCONTROL
 	---help---
-		Enable LPUART6 RTS flow control
+		Enable RTS flow control
+endchoice
+
+config LPUART6_INVERTIFLOWCONTROL
+	depends on LPUART6_RS485RTSCONTROL || LPUART6_IFLOWCONTROL
+	bool "Invert sense of RTS bit"
+	default n
+	---help---
+		Make RTS bit active high rather than active low
 
 config LPUART6_OFLOWCONTROL
-	bool "LPUART6 CTS flow control"
+	depends on !LPUART6_RS485RTSCONTROL
+	bool "CTS OFLOW control"
 	default n
 	select SERIAL_OFLOWCONTROL
 	---help---
-		Enable LPUART6 CTS flow control
+		Enable CTS flow control
 
 config LPUART6_DMA
 	bool "LPUART6 DMA support"
 	default n
 	select SERIAL_DMA
 	---help---
-		Enable DMA transfers on LPUART6
+		Enable DMA transfers
 
 endmenu
 
+#####################################################################################
+
 menu "LPUART7 Configuration"
 	depends on LPUART7_SERIALDRIVER
 
@@ -549,30 +721,54 @@ config LPUART7_2STOP
 	default 0
 	---help---
 		1=Two stop bits
+choice
+	prompt "IFLOW Control"
+	default LPUART7_NOIFLOWCONTROL
+
+config LPUART7_NOIFLOWCONTROL
+	bool "No IFLOW control"
+	---help---
+		No IFLOW control
+
+config LPUART7_RS485RTSCONTROL
+	bool "RTS for RS485 Direction"
+	select SERIAL_RS485CONTROL
+	---help---
+		 Use RTS pin for RS485 direction switching
 
 config LPUART7_IFLOWCONTROL
-	bool "LPUART7 RTS flow control"
-	default n
+	bool "RTS for IFLOW control"
 	select SERIAL_IFLOWCONTROL
 	---help---
-		Enable LPUART7 RTS flow control
+		Enable RTS flow control
+endchoice
+
+config LPUART7_INVERTIFLOWCONTROL
+	depends on LPUART7_RS485RTSCONTROL || LPUART7_IFLOWCONTROL
+	bool "Invert sense of RTS bit"
+	default n
+	---help---
+		Make RTS bit active high rather than active low
 
 config LPUART7_OFLOWCONTROL
-	bool "LPUART7 CTS flow control"
+	depends on !LPUART7_RS485RTSCONTROL
+	bool "CTS OFLOW control"
 	default n
 	select SERIAL_OFLOWCONTROL
 	---help---
-		Enable LPUART7 CTS flow control
+		Enable CTS flow control
 
 config LPUART7_DMA
 	bool "LPUART7 DMA support"
 	default n
 	select SERIAL_DMA
 	---help---
-		Enable DMA transfers on LPUART7
+		Enable DMA transfers
 
 endmenu
 
+#####################################################################################
+
 menu "LPUART8 Configuration"
 	depends on LPUART8_SERIALDRIVER
 
@@ -614,26 +810,48 @@ config LPUART8_2STOP
 	default 0
 	---help---
 		1=Two stop bits
+choice
+	prompt "IFLOW Control"
+	default LPUART8_NOIFLOWCONTROL
+
+config LPUART8_NOIFLOWCONTROL
+	bool "No IFLOW control"
+	---help---
+		No IFLOW control
+
+config LPUART8_RS485RTSCONTROL
+	bool "RTS for RS485 Direction"
+	select SERIAL_RS485CONTROL
+	---help---
+		 Use RTS pin for RS485 direction switching
 
 config LPUART8_IFLOWCONTROL
-	bool "LPUART8 RTS flow control"
-	default n
+	bool "RTS for IFLOW control"
 	select SERIAL_IFLOWCONTROL
 	---help---
-		Enable LPUART8 RTS flow control
+		Enable RTS flow control
+endchoice
+
+config LPUART8_INVERTIFLOWCONTROL
+	depends on LPUART8_RS485RTSCONTROL || LPUART8_IFLOWCONTROL
+	bool "Invert sense of RTS bit"
+	default n
+	---help---
+		Make RTS bit active high rather than active low
 
 config LPUART8_OFLOWCONTROL
-	bool "LPUART8 CTS flow control"
+	depends on !LPUART8_RS485RTSCONTROL
+	bool "CTS OFLOW control"
 	default n
 	select SERIAL_OFLOWCONTROL
 	---help---
-		Enable LPUART8 CTS flow control
+		Enable CTS flow control
 
 config LPUART8_DMA
 	bool "LPUART8 DMA support"
 	default n
 	select SERIAL_DMA
 	---help---
-		Enable DMA transfers on LPUART8
+		Enable DMA transfers
 
 endmenu
diff --git a/drivers/serial/Make.defs b/drivers/serial/Make.defs
index 5d1b7c11c30..5789c226080 100644
--- a/drivers/serial/Make.defs
+++ b/drivers/serial/Make.defs
@@ -37,7 +37,9 @@
 
 CSRCS += serial.c serial_io.c lowconsole.c
 
-ifeq ($(CONFIG_SERIAL_DMA),y)
+ifeq ($(CONFIG_SERIAL_RXDMA),y)
+  CSRCS += serial_dma.c
+else ifeq ($(CONFIG_SERIAL_TXDMA),y)
   CSRCS += serial_dma.c
 endif
 
diff --git a/drivers/serial/lowconsole.c b/drivers/serial/lowconsole.c
index c3be8596619..6e02ea78c6f 100644
--- a/drivers/serial/lowconsole.c
+++ b/drivers/serial/lowconsole.c
@@ -75,10 +75,8 @@ static const struct file_operations g_consoleops =
   lowconsole_read,  /* read */
   lowconsole_write, /* write */
   NULL,             /* seek */
-  lowconsole_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL            /* poll */
-#endif
+  lowconsole_ioctl, /* ioctl */
+  NULL              /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL            /* unlink */
 #endif
diff --git a/drivers/serial/ptmx.c b/drivers/serial/ptmx.c
index dc4a48352ed..f8559ac9bdc 100644
--- a/drivers/serial/ptmx.c
+++ b/drivers/serial/ptmx.c
@@ -103,10 +103,8 @@ static const struct file_operations g_ptmx_fops =
   ptmx_read,     /* read */
   ptmx_write,    /* write */
   NULL,          /* seek */
-  NULL           /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL         /* poll */
-#endif
+  NULL,          /* ioctl */
+  NULL           /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL         /* unlink */
 #endif
diff --git a/drivers/serial/pty.c b/drivers/serial/pty.c
index f8e316e0d39..fcff8435d6f 100644
--- a/drivers/serial/pty.c
+++ b/drivers/serial/pty.c
@@ -145,9 +145,7 @@ struct pty_dev_s
   tcflag_t pd_oflag;            /* Terminal output modes */
 #endif
 
-#ifndef CONFIG_DISABLE_POLL
   struct pty_poll_s pd_poll[CONFIG_DEV_PTY_NPOLLWAITERS];
-#endif
 };
 
 /* This structure describes the pipe pair */
@@ -185,10 +183,8 @@ static ssize_t pty_read(FAR struct file *filep, FAR char *buffer,
 static ssize_t pty_write(FAR struct file *filep, FAR const char *buffer,
                  size_t buflen);
 static int     pty_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int     pty_poll(FAR struct file *filep, FAR struct pollfd *fds,
                  bool setup);
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
 static int     pty_unlink(FAR struct inode *inode);
 #endif
@@ -209,10 +205,8 @@ static const struct file_operations g_pty_fops =
   pty_read,      /* read */
   pty_write,     /* write */
   NULL,          /* seek */
-  pty_ioctl      /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , pty_poll     /* poll */
-#endif
+  pty_ioctl,     /* ioctl */
+  pty_poll       /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , pty_unlink   /* unlink */
 #endif
@@ -934,7 +928,6 @@ static int pty_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: pty_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int pty_poll(FAR struct file *filep, FAR struct pollfd *fds,
                     bool setup)
 {
@@ -1017,7 +1010,6 @@ errout:
   pty_semgive(devpair);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Name: pty_unlink
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 981847a0976..15789ebf44d 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -82,7 +82,6 @@
 
 /* Timing */
 
-#define POLL_DELAY_MSEC 1
 #define POLL_DELAY_USEC 1000
 
 /************************************************************************************
@@ -94,9 +93,7 @@
  ************************************************************************************/
 
 static int     uart_takesem(FAR sem_t *sem, bool errout);
-#ifndef CONFIG_DISABLE_POLL
 static void    uart_pollnotify(FAR uart_dev_t *dev, pollevent_t eventset);
-#endif
 
 /* Write support */
 
@@ -112,9 +109,7 @@ static int     uart_close(FAR struct file *filep);
 static ssize_t uart_read(FAR struct file *filep, FAR char *buffer, size_t buflen);
 static ssize_t uart_write(FAR struct file *filep, FAR const char *buffer, size_t buflen);
 static int     uart_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int     uart_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup);
-#endif
 
 /************************************************************************************
  * Private Data
@@ -127,10 +122,8 @@ static const struct file_operations g_serialops =
   uart_read,  /* read */
   uart_write, /* write */
   0,          /* seek */
-  uart_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , uart_poll /* poll */
-#endif
+  uart_ioctl, /* ioctl */
+  uart_poll   /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL      /* unlink */
 #endif
@@ -186,7 +179,6 @@ static int uart_takesem(FAR sem_t *sem, bool errout)
  * Name: uart_pollnotify
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static void uart_pollnotify(FAR uart_dev_t *dev, pollevent_t eventset)
 {
   int i;
@@ -209,9 +201,6 @@ static void uart_pollnotify(FAR uart_dev_t *dev, pollevent_t eventset)
         }
     }
 }
-#else
-#  define uart_pollnotify(dev,event)
-#endif
 
 /************************************************************************************
  * Name: uart_putxmitchar
@@ -302,7 +291,7 @@ static int uart_putxmitchar(FAR uart_dev_t *dev, int ch, bool oktoblock)
                * the semaphore.
                */
 
-#ifdef CONFIG_SERIAL_DMA
+#ifdef CONFIG_SERIAL_TXDMA
               uart_dmatxavail(dev);
 #endif
               uart_enabletxint(dev);
@@ -485,7 +474,7 @@ static int uart_tcdrain(FAR uart_dev_t *dev, clock_t timeout)
                * the semaphore.
                */
 
-#ifdef CONFIG_SERIAL_DMA
+#ifdef CONFIG_SERIAL_TXDMA
               uart_dmatxavail(dev);
 #endif
               uart_enabletxint(dev);
@@ -516,11 +505,7 @@ static int uart_tcdrain(FAR uart_dev_t *dev, clock_t timeout)
             {
               clock_t elapsed;
 
-#ifndef CONFIG_DISABLE_SIGNALS
               nxsig_usleep(POLL_DELAY_USEC);
-#else
-              up_mdelay(POLL_DELAY_MSEC);
-#endif
 
               /* Check for a timeout */
 
@@ -624,7 +609,7 @@ static int uart_open(FAR struct file *filep)
            goto errout_with_sem;
         }
 
-#ifdef CONFIG_SERIAL_DMA
+#ifdef CONFIG_SERIAL_RXDMA
       /* Notify DMA that there is free space in the RX buffer */
 
       uart_dmarxfree(dev);
@@ -887,7 +872,7 @@ static ssize_t uart_read(FAR struct file *filep, FAR char *buffer, size_t buflen
 
       else
         {
-#ifdef CONFIG_SERIAL_DMA
+#ifdef CONFIG_SERIAL_RXDMA
           /* Disable all interrupts and test again...
            * uart_disablerxint() is insufficient for the check in DMA mode.
            */
@@ -910,7 +895,7 @@ static ssize_t uart_read(FAR struct file *filep, FAR char *buffer, size_t buflen
                * additional data to be received.
                */
 
-#ifdef CONFIG_SERIAL_DMA
+#ifdef CONFIG_SERIAL_RXDMA
               /* Notify DMA that there is free space in the RX buffer */
 
               uart_dmarxfree(dev);
@@ -991,7 +976,7 @@ static ssize_t uart_read(FAR struct file *filep, FAR char *buffer, size_t buflen
                * the loop.
                */
 
-#ifdef CONFIG_SERIAL_DMA
+#ifdef CONFIG_SERIAL_RXDMA
               leave_critical_section(flags);
 #else
               uart_enablerxint(dev);
@@ -1000,7 +985,7 @@ static ssize_t uart_read(FAR struct file *filep, FAR char *buffer, size_t buflen
         }
     }
 
-#ifdef CONFIG_SERIAL_DMA
+#ifdef CONFIG_SERIAL_RXDMA
   /* Notify DMA that there is free space in the RX buffer */
 
   flags = enter_critical_section();
@@ -1008,7 +993,7 @@ static ssize_t uart_read(FAR struct file *filep, FAR char *buffer, size_t buflen
   leave_critical_section(flags);
 #endif
 
-#ifndef CONFIG_SERIAL_DMA
+#ifndef CONFIG_SERIAL_RXDMA
   /* RX interrupt could be disabled by RX buffer overflow. Enable it now. */
 
   uart_enablerxint(dev);
@@ -1224,7 +1209,7 @@ static ssize_t uart_write(FAR struct file *filep, FAR const char *buffer,
 
   if (dev->xmit.head != dev->xmit.tail)
     {
-#ifdef CONFIG_SERIAL_DMA
+#ifdef CONFIG_SERIAL_TXDMA
       uart_dmatxavail(dev);
 #endif
       uart_enabletxint(dev);
@@ -1459,7 +1444,6 @@ static int uart_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: uart_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int uart_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup)
 {
   FAR struct inode *inode = filep->f_inode;
@@ -1472,7 +1456,7 @@ static int uart_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup)
   /* Some sanity checking */
 
 #ifdef CONFIG_DEBUG_FEATURES
-  if (!dev || !fds)
+  if (dev == NULL || fds == NULL)
     {
       return -ENODEV;
     }
@@ -1571,11 +1555,11 @@ static int uart_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup)
         }
 
     }
-  else if (fds->priv)
+  else if (fds->priv != NULL)
     {
       /* This is a request to tear down the poll. */
 
-      struct pollfd **slot = (struct pollfd **)fds->priv;
+      FAR struct pollfd **slot = (FAR struct pollfd **)fds->priv;
 
 #ifdef CONFIG_DEBUG_FEATURES
       if (!slot)
@@ -1595,7 +1579,6 @@ errout:
   uart_givesem(&dev->pollsem);
   return ret;
 }
-#endif
 
 /************************************************************************************
  * Public Functions
@@ -1639,9 +1622,7 @@ int uart_register(FAR const char *path, FAR uart_dev_t *dev)
   nxsem_init(&dev->closesem, 0, 1);
   nxsem_init(&dev->xmitsem,  0, 0);
   nxsem_init(&dev->recvsem,  0, 0);
-#ifndef CONFIG_DISABLE_POLL
   nxsem_init(&dev->pollsem,  0, 1);
-#endif
 
   /* The recvsem and xmitsem are used for signaling and, hence, should not have
    * priority inheritance enabled.
@@ -1802,7 +1783,6 @@ void uart_reset_sem(FAR uart_dev_t *dev)
   nxsem_reset(&dev->recvsem,  0);
   nxsem_reset(&dev->xmit.sem, 1);
   nxsem_reset(&dev->recv.sem, 1);
-#ifndef CONFIG_DISABLE_POLL
   nxsem_reset(&dev->pollsem,  1);
-#endif
 }
+
diff --git a/drivers/serial/serial_dma.c b/drivers/serial/serial_dma.c
index 9559a4dcd4d..17c453a79a4 100644
--- a/drivers/serial/serial_dma.c
+++ b/drivers/serial/serial_dma.c
@@ -46,7 +46,7 @@
 
 #include 
 
-#ifdef CONFIG_SERIAL_DMA
+#if defined(CONFIG_SERIAL_TXDMA) || defined(CONFIG_SERIAL_RXDMA)
 
 /************************************************************************************
  * Private Functions
@@ -105,7 +105,8 @@ static int uart_check_signo(const char *buf, size_t size)
  *
  ************************************************************************************/
 
-#if defined(CONFIG_TTY_SIGINT) || defined(CONFIG_TTY_SIGSTP)
+#if defined(CONFIG_SERIAL_RXDMA) && \
+   (defined(CONFIG_TTY_SIGINT) || defined(CONFIG_TTY_SIGSTP))
 static int uart_recvchars_signo(FAR uart_dev_t *dev)
 {
   FAR struct uart_dmaxfer_s *xfer = &dev->dmarx;
@@ -144,6 +145,7 @@ static int uart_recvchars_signo(FAR uart_dev_t *dev)
  *
  ************************************************************************************/
 
+#ifdef CONFIG_SERIAL_TXDMA
 void uart_xmitchars_dma(FAR uart_dev_t *dev)
 {
   FAR struct uart_dmaxfer_s *xfer = &dev->dmatx;
@@ -172,6 +174,7 @@ void uart_xmitchars_dma(FAR uart_dev_t *dev)
 
   uart_dmasend(dev);
 }
+#endif
 
 /************************************************************************************
  * Name: uart_xmitchars_done
@@ -183,6 +186,7 @@ void uart_xmitchars_dma(FAR uart_dev_t *dev)
  *
  ************************************************************************************/
 
+#ifdef CONFIG_SERIAL_TXDMA
 void uart_xmitchars_done(FAR uart_dev_t *dev)
 {
   FAR struct uart_dmaxfer_s *xfer = &dev->dmatx;
@@ -204,6 +208,7 @@ void uart_xmitchars_done(FAR uart_dev_t *dev)
       uart_datasent(dev);
     }
 }
+#endif
 
 /************************************************************************************
  * Name: uart_recvchars_dma
@@ -213,6 +218,7 @@ void uart_xmitchars_done(FAR uart_dev_t *dev)
  *
  ************************************************************************************/
 
+#ifdef CONFIG_SERIAL_RXDMA
 void uart_recvchars_dma(FAR uart_dev_t *dev)
 {
   FAR struct uart_dmaxfer_s *xfer = &dev->dmarx;
@@ -331,6 +337,7 @@ void uart_recvchars_dma(FAR uart_dev_t *dev)
 
   uart_dmareceive(dev);
 }
+#endif
 
 /************************************************************************************
  * Name: uart_recvchars_done
@@ -342,6 +349,7 @@ void uart_recvchars_dma(FAR uart_dev_t *dev)
  *
  ************************************************************************************/
 
+#ifdef CONFIG_SERIAL_RXDMA
 void uart_recvchars_done(FAR uart_dev_t *dev)
 {
   FAR struct uart_dmaxfer_s *xfer = &dev->dmarx;
@@ -383,5 +391,6 @@ void uart_recvchars_done(FAR uart_dev_t *dev)
     }
 #endif
 }
+#endif
 
-#endif /* CONFIG_SERIAL_DMA */
+#endif /* CONFIG_SERIAL_TXDMA || CONFIG_SERIAL_RXDMA */
diff --git a/drivers/serial/uart_16550.c b/drivers/serial/uart_16550.c
index a2f8a9216f2..9d421c03b17 100644
--- a/drivers/serial/uart_16550.c
+++ b/drivers/serial/uart_16550.c
@@ -103,11 +103,13 @@ static bool u16550_rxavailable(FAR struct uart_dev_s *dev);
 static bool u16550_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered,
                                  bool upper);
 #endif
-#ifdef CONFIG_SERIAL_DMA
+#ifdef CONFIG_SERIAL_TXDMA
 static void u16550_dmasend(FAR struct uart_dev_s *dev);
+static void u16550_dmatxavail(FAR struct uart_dev_s *dev);
+#endif
+#ifdef CONFIG_SERIAL_RXDMA
 static void u16550_dmareceive(FAR struct uart_dev_s *dev);
 static void u16550_dmarxfree(FAR struct uart_dev_s *dev);
-static void u16550_dmatxavail(FAR struct uart_dev_s *dev);
 #endif
 static void u16550_send(FAR struct uart_dev_s *dev, int ch);
 static void u16550_txint(FAR struct uart_dev_s *dev, bool enable);
@@ -131,10 +133,14 @@ static const struct uart_ops_s g_uart_ops =
 #ifdef CONFIG_SERIAL_IFLOWCONTROL
   .rxflowcontrol  = u16550_rxflowcontrol,
 #endif
-#ifdef CONFIG_SERIAL_DMA
+#ifdef CONFIG_SERIAL_TXDMA
   .dmasend        = u16550_dmasend,
+#endif
+#ifdef CONFIG_SERIAL_RXDMA
   .dmareceive     = u16550_dmareceive,
   .dmarxfree      = u16550_dmarxfree,
+#endif
+#ifdef CONFIG_SERIAL_TXDMA
   .dmatxavail     = u16550_dmatxavail,
 #endif
   .send           = u16550_send,
@@ -1164,11 +1170,13 @@ static bool u16550_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered,
  *
  ****************************************************************************/
 
-#ifdef CONFIG_SERIAL_DMA
+#ifdef CONFIG_SERIAL_TXDMA
 static void u16550_dmasend(FAR struct uart_dev_s *dev)
 {
 }
+#endif
 
+#ifdef CONFIG_SERIAL_RXDMA
 static void u16550_dmareceive(FAR struct uart_dev_s *dev)
 {
 }
@@ -1176,7 +1184,9 @@ static void u16550_dmareceive(FAR struct uart_dev_s *dev)
 static void u16550_dmarxfree(FAR struct uart_dev_s *dev)
 {
 }
+#endif
 
+#ifdef CONFIG_SERIAL_TXDMA
 static void u16550_dmatxavail(FAR struct uart_dev_s *dev)
 {
 }
diff --git a/drivers/spi/spi_driver.c b/drivers/spi/spi_driver.c
index 56236e56546..5f930b62dfa 100644
--- a/drivers/spi/spi_driver.c
+++ b/drivers/spi/spi_driver.c
@@ -106,16 +106,14 @@ static const struct file_operations spidrvr_fops =
   spidrvr_open,    /* open */
   spidrvr_close,   /* close */
 #else
-  0,               /* open */
-  0,               /* close */
+  NULL,            /* open */
+  NULL,            /* close */
 #endif
   spidrvr_read,    /* read */
   spidrvr_write,   /* write */
-  0,               /* seek */
-  spidrvr_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0              /* poll */
-#endif
+  NULL,            /* seek */
+  spidrvr_ioctl,   /* ioctl */
+  NULL             /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , spidrvr_unlink /* unlink */
 #endif
diff --git a/drivers/syslog/Kconfig b/drivers/syslog/Kconfig
index a7556570ca8..8e9e179c2d0 100644
--- a/drivers/syslog/Kconfig
+++ b/drivers/syslog/Kconfig
@@ -67,7 +67,6 @@ config RAMLOG_NONBLOCKING
 config RAMLOG_NPOLLWAITERS
 	int "RAMLOG number of poll waiters"
 	default 4
-	depends on !DISABLE_POLL
 	---help---
 		The maximum number of threads that may be waiting on the poll method.
 
diff --git a/drivers/syslog/README.txt b/drivers/syslog/README.txt
index 024e4ce4344..93cd1709f8f 100644
--- a/drivers/syslog/README.txt
+++ b/drivers/syslog/README.txt
@@ -16,7 +16,7 @@ SYSLOG Interfaces
   Prototypes:
 
     int syslog(int priority, FAR const IPTR char *format, ...);
-    int vsyslog(int priority, FAR const IPTR char *src, va_list ap);
+    void vsyslog(int priority, FAR const IPTR char *src, va_list ap);
 
   Description:
 
diff --git a/drivers/syslog/note_driver.c b/drivers/syslog/note_driver.c
index db8b81705ab..d075cfe637c 100644
--- a/drivers/syslog/note_driver.c
+++ b/drivers/syslog/note_driver.c
@@ -63,15 +63,13 @@ static ssize_t note_read(FAR struct file *filep, FAR char *buffer,
 
 static const struct file_operations note_fops =
 {
-  0,             /* open */
-  0,             /* close */
+  NULL,          /* open */
+  NULL,          /* close */
   note_read,     /* read */
-  0,             /* write */
-  0,             /* seek */
-  0              /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0            /* poll */
-#endif
+  NULL,          /* write */
+  NULL,          /* seek */
+  NULL,          /* ioctl */
+  NULL           /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , 0            /* unlink */
 #endif
@@ -166,4 +164,4 @@ int note_register(void)
   return register_driver("/dev/note", ¬e_fops, 0666, NULL);
 }
 
-#endif /* CONFIG_SCHED_INSTRUMENTATION_BUFFER && CONFIG_DRIVER_NOTE */
\ No newline at end of file
+#endif /* CONFIG_SCHED_INSTRUMENTATION_BUFFER && CONFIG_DRIVER_NOTE */
diff --git a/drivers/syslog/ramlog.c b/drivers/syslog/ramlog.c
index 80228d49fe7..b72f05a5eaa 100644
--- a/drivers/syslog/ramlog.c
+++ b/drivers/syslog/ramlog.c
@@ -86,9 +86,7 @@ struct ramlog_dev_s
    * retained in the f_priv field of the 'struct file'.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   FAR struct pollfd *rl_fds[CONFIG_RAMLOG_NPOLLWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -103,10 +101,8 @@ static int ramlog_flush(void);
 
 /* Helper functions */
 
-#ifndef CONFIG_DISABLE_POLL
 static void ramlog_pollnotify(FAR struct ramlog_dev_s *priv,
                               pollevent_t eventset);
-#endif
 static ssize_t ramlog_addchar(FAR struct ramlog_dev_s *priv, char ch);
 
 /* Character driver methods */
@@ -115,10 +111,8 @@ static ssize_t ramlog_read(FAR struct file *filep, FAR char *buffer,
                            size_t buflen);
 static ssize_t ramlog_write(FAR struct file *filep, FAR const char *buffer,
                             size_t buflen);
-#ifndef CONFIG_DISABLE_POLL
 static int     ramlog_poll(FAR struct file *filep, FAR struct pollfd *fds,
                            bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -144,10 +138,8 @@ static const struct file_operations g_ramlogfops =
   ramlog_read,  /* read */
   ramlog_write, /* write */
   NULL,         /* seek */
-  NULL          /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , ramlog_poll /* poll */
-#endif
+  NULL,         /* ioctl */
+  ramlog_poll   /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL        /* unlink */
 #endif
@@ -200,7 +192,6 @@ static int ramlog_flush(void)
  * Name: ramlog_pollnotify
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static void ramlog_pollnotify(FAR struct ramlog_dev_s *priv,
                               pollevent_t eventset)
 {
@@ -225,9 +216,6 @@ static void ramlog_pollnotify(FAR struct ramlog_dev_s *priv,
       leave_critical_section(flags);
     }
 }
-#else
-#  define ramlog_pollnotify(priv,event)
-#endif
 
 /****************************************************************************
  * Name: ramlog_addchar
@@ -426,12 +414,10 @@ static ssize_t ramlog_read(FAR struct file *filep, FAR char *buffer, size_t len)
 errout_without_sem:
 #endif
 
-#ifndef CONFIG_DISABLE_POLL
   if (nread > 0)
     {
       ramlog_pollnotify(priv, POLLOUT);
     }
-#endif
 
   /* Return the number of characters actually read */
 
@@ -511,7 +497,6 @@ static ssize_t ramlog_write(FAR struct file *filep, FAR const char *buffer, size
 
   /* Was anything written? */
 
-#if !defined(CONFIG_RAMLOG_NONBLOCKING) || !defined(CONFIG_DISABLE_POLL)
   if (nwritten > 0)
     {
       irqstate_t flags;
@@ -536,7 +521,6 @@ static ssize_t ramlog_write(FAR struct file *filep, FAR const char *buffer, size
       ramlog_pollnotify(priv, POLLIN);
       leave_critical_section(flags);
     }
-#endif
 
   /* We always have to return the number of bytes requested and NOT the
    * number of bytes that were actually written.  Otherwise, callers
@@ -550,7 +534,6 @@ static ssize_t ramlog_write(FAR struct file *filep, FAR const char *buffer, size
  * Name: ramlog_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 int ramlog_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup)
 {
   FAR struct inode *inode = filep->f_inode;
@@ -656,7 +639,6 @@ errout:
   nxsem_post(&priv->rl_exclsem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/syslog/syslog_chardev.c b/drivers/syslog/syslog_chardev.c
index bbb1194be67..e39d6722ea2 100644
--- a/drivers/syslog/syslog_chardev.c
+++ b/drivers/syslog/syslog_chardev.c
@@ -70,10 +70,8 @@ static const struct file_operations syslog_fops =
   NULL,          /* read */
   syslog_chardev_write, /* write */
   NULL,          /* seek */
-  NULL           /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL         /* poll */
-#endif
+  NULL,          /* ioctl */
+  NULL           /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL         /* unlink */
 #endif
diff --git a/drivers/syslog/syslog_console.c b/drivers/syslog/syslog_console.c
index 422e16a166c..eb8de226b70 100644
--- a/drivers/syslog/syslog_console.c
+++ b/drivers/syslog/syslog_console.c
@@ -66,15 +66,13 @@ static int     syslog_console_ioctl(FAR struct file *filep, int cmd,
 
 static const struct file_operations g_consoleops =
 {
-  0,                    /* open */
-  0,                    /* close */
+  NULL,                 /* open */
+  NULL,                 /* close */
   syslog_console_read,  /* read */
   syslog_console_write, /* write */
-  0,                    /* seek */
-  syslog_console_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0                   /* poll */
-#endif
+  NULL,                 /* seek */
+  syslog_console_ioctl, /* ioctl */
+  NULL                  /* poll */
 };
 
 /****************************************************************************
diff --git a/drivers/timers/oneshot.c b/drivers/timers/oneshot.c
index 2772013afd4..eb95ce0fd51 100644
--- a/drivers/timers/oneshot.c
+++ b/drivers/timers/oneshot.c
@@ -54,14 +54,6 @@
 
 #ifdef CONFIG_ONESHOT
 
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#ifdef CONFIG_DISABLE_SIGNALS
-#  error "This driver needs SIGNAL support, remove CONFIG_DISABLE_SIGNALS"
-#endif
-
 /****************************************************************************
  * Private Type Definitions
  ****************************************************************************/
@@ -106,13 +98,11 @@ static const struct file_operations g_oneshot_ops =
   oneshot_close, /* close */
   oneshot_read,  /* read */
   oneshot_write, /* write */
-  0,             /* seek */
-  oneshot_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0            /* poll */
-#endif
+  NULL,          /* seek */
+  oneshot_ioctl, /* ioctl */
+  NULL           /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
-  , 0            /* unlink */
+  , NULL         /* unlink */
 #endif
 };
 
diff --git a/drivers/timers/rtc.c b/drivers/timers/rtc.c
index e6338aae4e9..01c7a6285a8 100644
--- a/drivers/timers/rtc.c
+++ b/drivers/timers/rtc.c
@@ -135,16 +135,14 @@ static const struct file_operations rtc_fops =
   rtc_open,      /* open */
   rtc_close,     /* close */
 #else
-  0,             /* open */
-  0,             /* close */
+  NULL,          /* open */
+  NULL,          /* close */
 #endif
   rtc_read,      /* read */
   rtc_write,     /* write */
-  0,             /* seek */
+  NULL,          /* seek */
   rtc_ioctl,     /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  0,             /* poll */
-#endif
+  NULL,          /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   rtc_unlink     /* unlink */
 #endif
diff --git a/drivers/timers/timer.c b/drivers/timers/timer.c
index fc61075ab39..7dc6c1197e6 100644
--- a/drivers/timers/timer.c
+++ b/drivers/timers/timer.c
@@ -105,10 +105,8 @@ static const struct file_operations g_timerops =
   timer_read,  /* read */
   timer_write, /* write */
   NULL,        /* seek */
-  timer_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL       /* poll */
-#endif
+  timer_ioctl, /* ioctl */
+  NULL         /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL       /* unlink */
 #endif
diff --git a/drivers/timers/watchdog.c b/drivers/timers/watchdog.c
index 7433e5ef56f..9eff36d2ac0 100644
--- a/drivers/timers/watchdog.c
+++ b/drivers/timers/watchdog.c
@@ -119,11 +119,9 @@ static const struct file_operations g_wdogops =
   wdog_close, /* close */
   wdog_read,  /* read */
   wdog_write, /* write */
-  0,          /* seek */
-  wdog_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , 0         /* poll */
-#endif
+  NULL,       /* seek */
+  wdog_ioctl, /* ioctl */
+  NULL        /* poll */
 };
 
 /****************************************************************************
diff --git a/drivers/usbdev/Kconfig b/drivers/usbdev/Kconfig
index adaff6bddaf..d0d9c178f04 100644
--- a/drivers/usbdev/Kconfig
+++ b/drivers/usbdev/Kconfig
@@ -128,6 +128,52 @@ config USBDEV_TRACE_INITIALIDSET
 
 endif # USBDEV_TRACE
 
+menuconfig USBDEV_CUSTOM_TXFIFO_SIZE
+	bool "Custom TX Fifo size"
+	default n
+	---help---
+		Enables custom TX Fifo size
+
+if USBDEV_CUSTOM_TXFIFO_SIZE
+
+config USBDEV_EP0_TXFIFO_SIZE
+	int "USBDEV_EP0_TXFIFO_SIZE"
+	default 64
+
+config USBDEV_EP1_TXFIFO_SIZE
+	int "USBDEV_EP1_TXFIFO_SIZE"
+	default 0
+
+config USBDEV_EP2_TXFIFO_SIZE
+	int "USBDEV_EP2_TXFIFO_SIZE"
+	default 0
+
+config USBDEV_EP3_TXFIFO_SIZE
+	int "USBDEV_EP3_TXFIFO_SIZE"
+	default 0
+
+config USBDEV_EP4_TXFIFO_SIZE
+	int "USBDEV_EP4_TXFIFO_SIZE"
+	default 0
+
+config USBDEV_EP5_TXFIFO_SIZE
+	int "USBDEV_EP5_TXFIFO_SIZE"
+	default 0
+
+config USBDEV_EP6_TXFIFO_SIZE
+	int "USBDEV_EP6_TXFIFO_SIZE"
+	default 0
+
+config USBDEV_EP7_TXFIFO_SIZE
+	int "USBDEV_EP7_TXFIFO_SIZE"
+	default 0
+
+config USBDEV_EP8_TXFIFO_SIZE
+	int "USBDEV_EP8_TXFIFO_SIZE"
+	default 0
+
+endif # USBDEV_CUSTOM_TXFIFO_SIZE
+
 comment "USB Device Class Driver Options"
 
 menuconfig USBDEV_COMPOSITE
@@ -691,12 +737,12 @@ menuconfig RNDIS
 if RNDIS
 
 config RNDIS_COMPOSITE
-    bool "RNDIS composite support"
-    default n
-    depends on USBDEV_COMPOSITE
-    ---help---
-        Configure the RNDIS driver as part of a composite driver
-        (only if USBDEV_COMPOSITE is also defined)
+	bool "RNDIS composite support"
+	default n
+	depends on USBDEV_COMPOSITE
+	---help---
+		Configure the RNDIS driver as part of a composite driver
+		(only if USBDEV_COMPOSITE is also defined)
 
 if !RNDIS_COMPOSITE
 
diff --git a/drivers/usbdev/cdcacm.c b/drivers/usbdev/cdcacm.c
index f28b540f9b8..f91d4fb09d2 100644
--- a/drivers/usbdev/cdcacm.c
+++ b/drivers/usbdev/cdcacm.c
@@ -281,10 +281,14 @@ static const struct uart_ops_s g_uartops =
 #ifdef CONFIG_SERIAL_IFLOWCONTROL
   cdcuart_rxflowcontrol, /* rxflowcontrol */
 #endif
-#ifdef CONFIG_SERIAL_DMA
+#ifdef CONFIG_SERIAL_TXDMA
   NULL,                  /* dmasend */
+#endif
+#ifdef CONFIG_SERIAL_RXDMA
   NULL,                  /* dmareceive */
   NULL,                  /* dmarxfree */
+#endif
+#ifdef CONFIG_SERIAL_TXDMA
   NULL,                  /* dmatxavail */
 #endif
   NULL,                  /* send */
diff --git a/drivers/usbhost/Kconfig b/drivers/usbhost/Kconfig
index 9829051f6c9..07e695b02f4 100644
--- a/drivers/usbhost/Kconfig
+++ b/drivers/usbhost/Kconfig
@@ -260,7 +260,7 @@ config USBHOST_HIDKBD
 	depends on !INT_DISABLE
 	---help---
 		Enable support for the keyboard class driver.  This also depends on
-		SCHED_WORKQUEUE && !DISABLE_SIGNALS
+		SCHED_WORKQUEUE
 
 if  USBHOST_HIDKBD
 
@@ -291,7 +291,6 @@ config HIDKBD_BUFSIZE
 config HIDKBD_NPOLLWAITERS
 	int "Max Number of Waiters for Poll Event"
 	default 2
-	depends on !DISABLE_POLL
 	---help---
 		If the poll() method is enabled, this defines the maximum number
 		of threads that can be waiting for keyboard events.  Default: 2.
@@ -339,7 +338,7 @@ config USBHOST_HIDMOUSE
 	select MOUSE
 	---help---
 		Enable support for the mouse class driver.  This also depends on
-		SCHED_WORKQUEUE && !DISABLE_SIGNALS
+		SCHED_WORKQUEUE
 
 		NOTE:  This driver checks out on a Labtec and an AOpen mouse, but
 		does not work correctly on a Microsoft mouse.  A little more work
@@ -384,7 +383,6 @@ config HIDMOUSE_BUFSIZE
 config HIDMOUSE_NPOLLWAITERS
 	int "Max Number of Waiters for Poll Event"
 	default 2
-	depends on !DISABLE_POLL
 	---help---
 		If the poll() method is enabled, this defines the maximum number
 		of threads that can be waiting for mouse events.  Default: 2.
@@ -546,7 +544,6 @@ config XBOXCONTROLLER_STACKSIZE
 config XBOXCONTROLLER_NPOLLWAITERS
 	int "Max Number of Waiters for Poll Event"
 	default 2
-	depends on !DISABLE_POLL
 	---help---
 		If the poll() method is enabled, this defines the maximum number
 		of threads that can be waiting for mouse events.  Default: 2.
diff --git a/drivers/usbhost/usbhost_hidkbd.c b/drivers/usbhost/usbhost_hidkbd.c
index 96588341cb6..84e954b9413 100644
--- a/drivers/usbhost/usbhost_hidkbd.c
+++ b/drivers/usbhost/usbhost_hidkbd.c
@@ -80,7 +80,9 @@
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
+
 /* Configuration ************************************************************/
+
 /* This determines how often the USB keyboard will be polled in units of
  * of microseconds.  The default is 100MS.
  */
@@ -97,14 +99,6 @@
 #  warning "Worker thread support is required (CONFIG_SCHED_WORKQUEUE)"
 #endif
 
-/* Signals must not be disabled as they are needed by nxsig_usleep.  Need to have
- * CONFIG_DISABLE_SIGNALS=n
- */
-
-#ifdef CONFIG_DISABLE_SIGNALS
-#  warning "Signal support is required (CONFIG_DISABLE_SIGNALS)"
-#endif
-
 /* Provide some default values for other configuration settings */
 
 #ifndef CONFIG_HIDKBD_DEFPRIO
@@ -154,6 +148,7 @@
 #endif
 
 /* Driver support ***********************************************************/
+
 /* This format is used to construct the /dev/kbd[n] device driver path.  It
  * defined here so that it will be used consistently in all places.
  */
@@ -172,6 +167,7 @@
 #define USBHOST_MAX_CREFS   0x7fff
 
 /* Debug ********************************************************************/
+
 /* Both CONFIG_DEBUG_INPUT and CONFIG_DEBUG_USB could apply to this file.
  * We assume here that CONFIG_DEBUG_INPUT might be enabled separately, but
  * CONFIG_DEBUG_USB implies both.
@@ -234,9 +230,7 @@ struct usbhost_state_s
    * retained in the f_priv field of the 'struct file'.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_HIDKBD_NPOLLWAITERS];
-#endif
 
   /* Buffer used to collect and buffer incoming keyboard characters */
 
@@ -266,11 +260,7 @@ static void usbhost_takesem(sem_t *sem);
 
 /* Polling support */
 
-#ifndef CONFIG_DISABLE_POLL
 static void usbhost_pollnotify(FAR struct usbhost_state_s *dev);
-#else
-#  define usbhost_pollnotify(dev)
-#endif
 
 /* Memory allocation services */
 
@@ -337,10 +327,8 @@ static ssize_t usbhost_read(FAR struct file *filep,
                             FAR char *buffer, size_t len);
 static ssize_t usbhost_write(FAR struct file *filep,
                              FAR const char *buffer, size_t len);
-#ifndef CONFIG_DISABLE_POLL
 static int usbhost_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -364,23 +352,21 @@ static const struct usbhost_id_s g_hidkbd_id =
 
 static struct usbhost_registry_s g_hidkbd =
 {
-  NULL,                    /* flink     */
-  usbhost_create,          /* create    */
-  1,                       /* nids      */
-  &g_hidkbd_id             /* id[]      */
+  NULL,                     /* flink     */
+  usbhost_create,           /* create    */
+  1,                        /* nids      */
+  &g_hidkbd_id              /* id[]      */
 };
 
 static const struct file_operations g_hidkbd_fops =
 {
-  usbhost_open,            /* open      */
-  usbhost_close,           /* close     */
-  usbhost_read,            /* read      */
-  usbhost_write,           /* write     */
-  0,                       /* seek      */
-  0                        /* ioctl     */
-#ifndef CONFIG_DISABLE_POLL
-  , usbhost_poll           /* poll      */
-#endif
+  usbhost_open,             /* open      */
+  usbhost_close,            /* close     */
+  usbhost_read,             /* read      */
+  usbhost_write,            /* write     */
+  NULL,                     /* seek      */
+  NULL,                     /* ioctl     */
+  usbhost_poll              /* poll      */
 };
 
 /* This is a bitmap that is used to allocate device names /dev/kbda-z. */
@@ -621,7 +607,6 @@ static void usbhost_takesem(sem_t *sem)
  * Name: usbhost_pollnotify
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static void usbhost_pollnotify(FAR struct usbhost_state_s *priv)
 {
   int i;
@@ -640,7 +625,6 @@ static void usbhost_pollnotify(FAR struct usbhost_state_s *priv)
         }
     }
 }
-#endif
 
 /****************************************************************************
  * Name: usbhost_allocclass
@@ -2322,7 +2306,6 @@ static ssize_t usbhost_write(FAR struct file *filep, FAR const char *buffer,
  *
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int usbhost_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup)
 {
@@ -2407,7 +2390,6 @@ errout:
   nxsem_post(&priv->exclsem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/usbhost/usbhost_hidmouse.c b/drivers/usbhost/usbhost_hidmouse.c
index 1b4ddac1764..17f95a586bf 100644
--- a/drivers/usbhost/usbhost_hidmouse.c
+++ b/drivers/usbhost/usbhost_hidmouse.c
@@ -78,7 +78,9 @@
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
+
 /* Configuration ************************************************************/
+
 /* Worker thread is needed, unfortunately, to handle some cornercase failure
  * conditions.  This is kind of wasteful and begs for a re-design.
  */
@@ -87,14 +89,6 @@
 #  warning "Worker thread support is required (CONFIG_SCHED_WORKQUEUE)"
 #endif
 
-/* Signals must not be disabled as they are needed for nxsig_kill.  Need to
- * have CONFIG_DISABLE_SIGNALS=n
- */
-
-#ifdef CONFIG_DISABLE_SIGNALS
-#  warning "Signal support is required (CONFIG_DISABLE_SIGNALS)"
-#endif
-
 /* Provide some default values for other configuration settings */
 
 #ifndef CONFIG_HIDMOUSE_XMAX
@@ -172,6 +166,7 @@
 #define INVALID_POSITION_B16 (0x7fffffff)
 
 /* Driver support ***********************************************************/
+
 /* This format is used to construct the /dev/mouse[n] device driver path.  It
  * defined here so that it will be used consistently in all places.
  */
@@ -193,6 +188,7 @@
 #define USBHOST_MAX_CREFS   0x7fff
 
 /* Debug ********************************************************************/
+
 /* Both CONFIG_DEBUG_INPUT and CONFIG_DEBUG_USB could apply to this file.
  * We assume here that CONFIG_DEBUG_INPUT might be enabled separately, but
  * CONFIG_DEBUG_USB implies both.
@@ -297,9 +293,7 @@ struct usbhost_state_s
    * retained in the f_priv field of the 'struct file'.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_HIDMOUSE_NPOLLWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -313,11 +307,7 @@ static void usbhost_takesem(sem_t *sem);
 
 /* Polling support */
 
-#ifndef CONFIG_DISABLE_POLL
 static void usbhost_pollnotify(FAR struct usbhost_state_s *dev);
-#else
-#  define usbhost_pollnotify(dev)
-#endif
 
 /* Memory allocation services */
 
@@ -389,10 +379,8 @@ static ssize_t usbhost_read(FAR struct file *filep,
                             FAR char *buffer, size_t len);
 static ssize_t usbhost_write(FAR struct file *filep,
                              FAR const char *buffer, size_t len);
-#ifndef CONFIG_DISABLE_POLL
 static int usbhost_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -428,11 +416,9 @@ static const struct file_operations g_hidmouse_fops =
   usbhost_close,           /* close     */
   usbhost_read,            /* read      */
   usbhost_write,           /* write     */
-  0,                       /* seek      */
-  0                        /* ioctl     */
-#ifndef CONFIG_DISABLE_POLL
-  , usbhost_poll           /* poll      */
-#endif
+  NULL,                    /* seek      */
+  NULL,                    /* ioctl     */
+  usbhost_poll             /* poll      */
 };
 
 /* This is a bitmap that is used to allocate device names /dev/mouse0-31. */
@@ -481,7 +467,6 @@ static void usbhost_takesem(sem_t *sem)
  * Name: usbhost_pollnotify
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static void usbhost_pollnotify(FAR struct usbhost_state_s *priv)
 {
   int i;
@@ -500,7 +485,6 @@ static void usbhost_pollnotify(FAR struct usbhost_state_s *priv)
         }
     }
 }
-#endif
 
 /****************************************************************************
  * Name: usbhost_allocclass
@@ -686,9 +670,7 @@ static void usbhost_destroy(FAR void *arg)
 
 static void usbhost_notify(FAR struct usbhost_state_s *priv)
 {
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   /* If there are threads waiting for read data, then signal one of them
    * that the read data is available.
@@ -705,7 +687,6 @@ static void usbhost_notify(FAR struct usbhost_state_s *priv)
    * then some make end up blocking after all.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   for (i = 0; i < CONFIG_HIDMOUSE_NPOLLWAITERS; i++)
     {
       struct pollfd *fds = priv->fds[i];
@@ -716,7 +697,6 @@ static void usbhost_notify(FAR struct usbhost_state_s *priv)
           nxsem_post(fds->sem);
         }
     }
-#endif
 }
 
 /****************************************************************************
@@ -2451,7 +2431,6 @@ static ssize_t usbhost_write(FAR struct file *filep, FAR const char *buffer,
  *
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int usbhost_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup)
 {
@@ -2536,7 +2515,6 @@ errout:
   nxsem_post(&priv->exclsem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/usbhost/usbhost_storage.c b/drivers/usbhost/usbhost_storage.c
index 58dd6bd439d..d2691f9f63a 100644
--- a/drivers/usbhost/usbhost_storage.c
+++ b/drivers/usbhost/usbhost_storage.c
@@ -261,7 +261,7 @@ static int usbhost_ioctl(FAR struct inode *inode, int cmd,
  * device.
  */
 
-static const const struct usbhost_id_s g_id =
+static const struct usbhost_id_s g_id =
 {
   USB_CLASS_MASS_STORAGE, /* base     */
   USBMSC_SUBCLASS_SCSI,  /* subclass */
diff --git a/drivers/usbhost/usbhost_xboxcontroller.c b/drivers/usbhost/usbhost_xboxcontroller.c
index 20a29c83eaa..5b06ab90460 100644
--- a/drivers/usbhost/usbhost_xboxcontroller.c
+++ b/drivers/usbhost/usbhost_xboxcontroller.c
@@ -84,6 +84,7 @@
 #endif
 
 /* Driver support ***********************************************************/
+
 /* This format is used to construct the /dev/xbox[n] device driver path.  It
  * defined here so that it will be used consistently in all places.
  */
@@ -254,10 +255,8 @@ static ssize_t usbhost_read(FAR struct file *filep,
 static ssize_t usbhost_write(FAR struct file *filep,
                              FAR const char *buffer, size_t len);
 static int usbhost_ioctl(FAR struct file* filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int usbhost_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -274,16 +273,18 @@ static const const struct usbhost_id_s g_xboxcontroller_id[] =
     USB_CLASS_VENDOR_SPEC,  /* base -- Must be one of the USB_CLASS_* definitions in usb.h */
     0x0047,  /* subclass -- depends on the device */
     0x00d0,  /* proto -- depends on the device    */
-    0x045E,  /* vid      */
-    0x02DD   /* pid      */
+    0x045e,  /* vid      */
+    0x02dd   /* pid      */
   },
+
   /* XBox One S controller */
+
   {
     USB_CLASS_VENDOR_SPEC,  /* base -- Must be one of the USB_CLASS_* definitions in usb.h */
     0x0047,  /* subclass -- depends on the device */
     0x00d0,  /* proto -- depends on the device    */
-    0x045E,  /* vid      */
-    0x02EA   /* pid      */
+    0x045e,  /* vid      */
+    0x02ea   /* pid      */
   }
 };
 
@@ -305,11 +306,9 @@ static const struct file_operations g_xboxcontroller_fops =
   usbhost_close,           /* close     */
   usbhost_read,            /* read      */
   usbhost_write,           /* write     */
-  0,                       /* seek      */
-  usbhost_ioctl            /* ioctl     */
-#ifndef CONFIG_DISABLE_POLL
-  , usbhost_poll           /* poll      */
-#endif
+  NULL,                    /* seek      */
+  usbhost_ioctl,           /* ioctl     */
+  usbhost_poll             /* poll      */
 };
 
 /* This is a bitmap that is used to allocate device names /dev/xboxa-z. */
@@ -544,9 +543,7 @@ static void usbhost_destroy(FAR void *arg)
 
 static void usbhost_notify(FAR struct usbhost_state_s *priv)
 {
-#ifndef CONFIG_DISABLE_POLL
   int i;
-#endif
 
   /* If there are threads waiting for read data, then signal one of them
    * that the read data is available.
@@ -563,7 +560,6 @@ static void usbhost_notify(FAR struct usbhost_state_s *priv)
    * then some make end up blocking after all.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   for (i = 0; i < CONFIG_XBOXCONTROLLER_NPOLLWAITERS; i++)
     {
       FAR struct pollfd *fds = priv->fds[i];
@@ -574,7 +570,6 @@ static void usbhost_notify(FAR struct usbhost_state_s *priv)
           nxsem_post(fds->sem);
         }
     }
-#endif
 }
 
 /****************************************************************************
@@ -2107,7 +2102,6 @@ errout:
  *
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int usbhost_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup)
 {
@@ -2191,7 +2185,6 @@ errout:
   nxsem_post(&priv->exclsem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/drivers/usbmisc/Kconfig b/drivers/usbmisc/Kconfig
index 66690612833..cf2fca823c2 100644
--- a/drivers/usbmisc/Kconfig
+++ b/drivers/usbmisc/Kconfig
@@ -6,11 +6,11 @@
 comment "USB Miscellaneous drivers"
 
 config FUSB301
-	bool "Fairchild FUSB301 USB type-C controller support"
+	bool "On Semiconductor FUSB301 USB Type-C controller support"
 	default n
 	select I2C
 	---help---
-		Enable device driver for Fairchild USB type-C controller
+		Enable device driver for Fairchild/On Semiconductor USB Type-C controller
 
 if FUSB301
 
@@ -32,3 +32,31 @@ config FUSB301_NPOLLWAITERS
 		Maximum number of threads that can be waiting on poll()
 
 endif
+
+config FUSB303
+	bool "On Semiconductor FUSB303 USB Type-C controller support"
+	default n
+	select I2C
+	---help---
+		Enable device driver for Fairchild/On Semiconductor USB Type-C controller
+
+if FUSB303
+
+config FUSB303_I2C_FREQUENCY
+	int "FUSB303 I2C frequency"
+	default 400000
+	range 1 400000
+
+config DEBUG_FUSB303
+	bool "Enable debug support for the FUSB303"
+	default n
+	---help---
+		Enables debug support for the FUSB303
+
+config FUSB303_NPOLLWAITERS
+	int "Number of waiters to poll"
+	default 2
+	---help---
+		Maximum number of threads that can be waiting on poll()
+
+endif
diff --git a/drivers/usbmisc/Make.defs b/drivers/usbmisc/Make.defs
index fd9dd6af37e..a3d6a57b532 100644
--- a/drivers/usbmisc/Make.defs
+++ b/drivers/usbmisc/Make.defs
@@ -41,6 +41,10 @@ ifeq ($(CONFIG_FUSB301),y)
   CSRCS += fusb301.c
 endif
 
+ifeq ($(CONFIG_FUSB303),y)
+  CSRCS += fusb303.c
+endif
+
 # Include USB miscellaneous build support
 
 DEPPATH += --dep-path usbmisc
diff --git a/drivers/usbmisc/fusb301.c b/drivers/usbmisc/fusb301.c
index 98da77b5964..bd46ae5d965 100644
--- a/drivers/usbmisc/fusb301.c
+++ b/drivers/usbmisc/fusb301.c
@@ -82,9 +82,7 @@ struct fusb301_dev_s
   volatile bool int_pending;            /* Interrupt received but handled */
   sem_t devsem;                         /* Manages exclusive access */
   FAR struct fusb301_config_s *config;  /* Platform specific configuration */
-#ifndef CONFIG_DISABLE_POLL
   FAR struct pollfd *fds[CONFIG_FUSB301_NPOLLWAITERS];
-#endif
 };
 
 /****************************************************************************
@@ -97,11 +95,9 @@ static ssize_t fusb301_read(FAR struct file *, FAR char *, size_t);
 static ssize_t fusb301_write(FAR struct file *filep, FAR const char *buffer,
                              size_t buflen);
 static int fusb301_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int fusb301_poll(FAR struct file *filep, FAR struct pollfd *fds,
                         bool setup);
 static void fusb301_notify(FAR struct fusb301_dev_s *priv);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -114,13 +110,11 @@ static const struct file_operations g_fusb301ops =
   fusb301_read,  /* read */
   fusb301_write, /* write */
   NULL,          /* seek */
-  fusb301_ioctl  /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , fusb301_poll /* poll */
-#endif
+  fusb301_ioctl, /* ioctl */
+  fusb301_poll   /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL         /* unlink */
- #endif
+#endif
 };
 
 /****************************************************************************
@@ -410,7 +404,7 @@ static int fusb301_set_state(FAR struct fusb301_dev_s *priv,
  * Name: fusb301_read_status
  *
  * Description:
- *   Clear read status register
+ *   Read status register
  *
  ****************************************************************************/
 
@@ -666,7 +660,6 @@ static int fusb301_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  *   This routine is called during FUSB301 device poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int fusb301_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup)
 {
   FAR struct inode *inode;
@@ -779,7 +772,6 @@ static void fusb301_notify(FAR struct fusb301_dev_s *priv)
         }
     }
 }
-#endif /* !CONFIG_DISABLE_POLL */
 
 /****************************************************************************
  * Name: fusb301_callback
@@ -799,9 +791,7 @@ static int fusb301_int_handler(int irq, FAR void *context, FAR void *arg)
   flags = enter_critical_section();
   priv->int_pending = true;
 
-#ifndef CONFIG_DISABLE_POLL
   fusb301_notify(priv);
-#endif
   leave_critical_section(flags);
 
   return OK;
@@ -848,7 +838,11 @@ int fusb301_register(FAR const char *devpath, FAR struct i2c_master_s *i2c,
 
   /* Prepare interrupt line and handler. */
 
-  priv->config->irq_clear(config);
+  if (priv->config->irq_clear)
+    {
+      priv->config->irq_clear(config);
+    }
+
   priv->config->irq_attach(config, fusb301_int_handler, priv);
   priv->config->irq_enable(config, false);
 
diff --git a/drivers/usbmisc/fusb303.c b/drivers/usbmisc/fusb303.c
new file mode 100644
index 00000000000..b66432fe34f
--- /dev/null
+++ b/drivers/usbmisc/fusb303.c
@@ -0,0 +1,1106 @@
+/****************************************************************************
+ * drivers/usbmisc/fusb303.c
+ *
+ * FUSB303 USB-C controller driver
+ *
+ *   Copyright (C) 2019 Haltian Ltd. All rights reserved.
+ *   Authors: Harri Luhtala 
+ *            Juha Niskanen 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_FUSB303
+#  define fusb303_err(x, ...)        _err(x, ##__VA_ARGS__)
+#  define fusb303_info(x, ...)       _info(x, ##__VA_ARGS__)
+#else
+#  define fusb303_err(x, ...)        uerr(x, ##__VA_ARGS__)
+#  define fusb303_info(x, ...)       uinfo(x, ##__VA_ARGS__)
+#endif
+
+#ifndef CONFIG_FUSB303_I2C_FREQUENCY
+#  define CONFIG_FUSB303_I2C_FREQUENCY 400000
+#endif
+
+/* Other macros */
+
+#define FUSB303_I2C_RETRIES  10
+
+#define FUSB303_ALL_INTR     (INTERRUPT_ATTACH | INTERRUPT_DETACH | \
+                              INTERRUPT_BC_LVL | INTERRUPT_AUTOSNK | \
+                              INTERRUPT_VBUS_CHG | INTERRUPT_FAULT | \
+                              INTERRUPT_ORIENT)
+
+#define FUSB303_ALL_INTR1    (INTERRUPT1_REMEDY | INTERRUPT1_FRC_SUCC | \
+                              INTERRUPT1_FRC_FAIL | INTERRUPT1_REM_FAIL | \
+                              INTERRUPT1_REM_VBON | INTERRUPT1_REM_VBOFF)
+
+/* Debug */
+
+#ifdef CONFIG_DEBUG_FUSB303
+#  define DUMPREG(priv, x) \
+    do \
+      { \
+        int ret = fusb303_getreg((priv), (x)); \
+        if (ret < 0) \
+          { \
+            fusb303_err("ERROR: Failed to read %s(0x%02X)\n", #x, (x)); \
+          } \
+        else \
+          { \
+            fusb303_info("%s(0x%02X): 0x%02X\n", #x, (x), ret); \
+          } \
+      } \
+    while(0)
+#endif
+
+/****************************************************************************
+ * Private Data Types
+ ****************************************************************************/
+
+struct fusb303_dev_s
+{
+  FAR struct i2c_master_s *i2c;         /* I2C interface */
+  uint8_t addr;                         /* I2C address */
+  volatile bool int_pending;            /* Interrupt received but handled */
+  sem_t devsem;                         /* Manages exclusive access */
+  FAR struct fusb303_config_s *config;  /* Platform specific configuration */
+  FAR struct pollfd *fds[CONFIG_FUSB303_NPOLLWAITERS];
+};
+
+/****************************************************************************
+ * Private Function prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_FUSB303
+static int fusb303_dumpregs(FAR const char *funcname,
+                            FAR struct fusb303_dev_s *priv);
+#endif
+static int fusb303_open(FAR struct file *filep);
+static int fusb303_close(FAR struct file *filep);
+static ssize_t fusb303_read(FAR struct file *, FAR char *, size_t);
+static ssize_t fusb303_write(FAR struct file *filep, FAR const char *buffer,
+                             size_t buflen);
+static int fusb303_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
+static int fusb303_poll(FAR struct file *filep, FAR struct pollfd *fds,
+                        bool setup);
+static void fusb303_notify(FAR struct fusb303_dev_s *priv);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct file_operations g_fusb303ops =
+{
+  fusb303_open,  /* open */
+  fusb303_close, /* close */
+  fusb303_read,  /* read */
+  fusb303_write, /* write */
+  NULL,          /* seek */
+  fusb303_ioctl, /* ioctl */
+  fusb303_poll   /* poll */
+#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
+  , NULL         /* unlink */
+#endif
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: fusb303_getreg
+ *
+ * Description:
+ *   Read from an 8-bit FUSB303 register
+ *
+ * Input Parameters:
+ *   priv   - pointer to FUSB303 Private Structure
+ *   reg    - register to read
+ *
+ * Returned Value:
+ *   Returns positive register value in case of success, otherwise ERROR
+ *
+ ****************************************************************************/
+
+static int fusb303_getreg(FAR struct fusb303_dev_s *priv, uint8_t reg)
+{
+  int ret = -EIO;
+  int retries;
+  uint8_t regval;
+  struct i2c_msg_s msg[2];
+
+  DEBUGASSERT(priv);
+
+  msg[0].frequency = CONFIG_FUSB303_I2C_FREQUENCY;
+  msg[0].addr      = priv->addr;
+  msg[0].flags     = 0;
+  msg[0].buffer    = ®
+  msg[0].length    = 1;
+
+  msg[1].frequency = CONFIG_FUSB303_I2C_FREQUENCY;
+  msg[1].addr      = priv->addr;
+  msg[1].flags     = I2C_M_READ;
+  msg[1].buffer    = ®val;
+  msg[1].length    = 1;
+
+  /* Perform the transfer */
+
+  for (retries = 0; retries < FUSB303_I2C_RETRIES; retries++)
+    {
+      ret = I2C_TRANSFER(priv->i2c, msg, 2);
+      if (ret >= 0)
+        {
+          fusb303_info("reg:%02X, value:%02X\n", reg, regval);
+          return regval;
+        }
+      else
+        {
+          /* Some error. Try to reset I2C bus and keep trying. */
+
+#ifdef CONFIG_I2C_RESET
+          if (retries == FUSB303_I2C_RETRIES - 1)
+            {
+              break;
+            }
+
+          ret = I2C_RESET(priv->i2c);
+          if (ret < 0)
+            {
+              fusb303_err("ERROR: I2C_RESET failed: %d\n", ret);
+              return ret;
+            }
+#endif
+        }
+    }
+
+  fusb303_info("reg:%02X, error:%d\n", reg, ret);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: fusb303_putreg
+ *
+ * Description:
+ *   Write a value to an 8-bit FUSB303 register
+ *
+ * Input Parameters:
+ *   priv    - pointer to FUSB303 Private Structure
+ *   regaddr - register to read
+ *   regval  - value to be written
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static int fusb303_putreg(FAR struct fusb303_dev_s *priv, uint8_t regaddr,
+                          uint8_t regval)
+{
+  int ret = -EIO;
+  int retries;
+  struct i2c_msg_s msg;
+  uint8_t txbuffer[2];
+
+  /* Setup to the data to be transferred (register address and data). */
+
+  txbuffer[0]   = regaddr;
+  txbuffer[1]   = regval;
+
+  /* Setup 8-bit FUSB303 address write message */
+
+  msg.frequency = CONFIG_FUSB303_I2C_FREQUENCY;
+  msg.addr      = priv->addr;
+  msg.flags     = 0;
+  msg.buffer    = txbuffer;
+  msg.length    = 2;
+
+  /* Perform the transfer */
+
+  for (retries = 0; retries < FUSB303_I2C_RETRIES; retries++)
+    {
+      ret = I2C_TRANSFER(priv->i2c, &msg, 1);
+      if (ret == OK)
+        {
+          fusb303_info("reg:%02X, value:%02X\n", regaddr, regval);
+
+          return OK;
+        }
+      else
+        {
+          /* Some error. Try to reset I2C bus and keep trying. */
+
+#ifdef CONFIG_I2C_RESET
+          if (retries == FUSB303_I2C_RETRIES - 1)
+            {
+              break;
+            }
+
+          ret = I2C_RESET(priv->i2c);
+          if (ret < 0)
+            {
+              fusb303_err("ERROR: I2C_RESET failed: %d\n", ret);
+              return ret;
+            }
+#endif
+        }
+    }
+
+  fusb303_err("ERROR: failed reg:%02X, value:%02X, error:%d\n",
+              regaddr, regval, ret);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: fusb303_dumpregs
+ *
+ * Description:
+ *   Dump FUSB303 registers
+ *
+ * Input Parameters:
+ *   priv    - pointer to FUSB303 Private Structure
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_FUSB303
+static int noinline_function fusb303_dumpregs(FAR const char *funcname,
+                                              FAR struct fusb303_dev_s *priv)
+{
+  fusb303_info("'%s':\n", funcname);
+  DUMPREG(priv, FUSB303_DEV_ID_REG);
+  DUMPREG(priv, FUSB303_DEV_TYPE_REG);
+  DUMPREG(priv, FUSB303_PORTROLE_REG);
+  DUMPREG(priv, FUSB303_CONTROL_REG);
+  DUMPREG(priv, FUSB303_CONTROL1_REG);
+  DUMPREG(priv, FUSB303_MANUAL_REG);
+  DUMPREG(priv, FUSB303_RESET_REG);
+  DUMPREG(priv, FUSB303_MASK_REG);
+  DUMPREG(priv, FUSB303_MASK1_REG);
+  DUMPREG(priv, FUSB303_STATUS_REG);
+  DUMPREG(priv, FUSB303_STATUS1_REG);
+  DUMPREG(priv, FUSB303_TYPE_REG);
+  DUMPREG(priv, FUSB303_INTERRUPT_REG);
+  DUMPREG(priv, FUSB303_INTERRUPT1_REG);
+  return OK;
+}
+#endif /* CONFIG_DEBUG_FUSB303 */
+
+/****************************************************************************
+ * Name: fusb303_read_device_id
+ *
+ * Description:
+ *   Read device version, revision ID and type.
+ *
+ ****************************************************************************/
+
+static int fusb303_read_device_id(FAR struct fusb303_dev_s *priv,
+                                  FAR uint8_t *dev_id, FAR uint8_t *dev_type)
+{
+  int ret;
+
+  ret = fusb303_getreg(priv, FUSB303_DEV_ID_REG);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to read device ID\n");
+      return -EIO;
+    }
+
+  if (dev_id != NULL)
+    {
+      *dev_id = ret;
+    }
+
+  ret = fusb303_getreg(priv, FUSB303_DEV_TYPE_REG);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to read device type\n");
+      return -EIO;
+    }
+
+  if (dev_type != NULL)
+    {
+      *dev_type = ret;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: fusb303_clear_interrupts
+ *
+ * Description:
+ *   Clear interrupts from FUSB303 chip
+ *
+ ****************************************************************************/
+
+static int fusb303_clear_interrupts(FAR struct fusb303_dev_s *priv)
+{
+  int ret;
+
+  ret = fusb303_putreg(priv, FUSB303_INTERRUPT_REG, FUSB303_ALL_INTR);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to clear interrupts\n");
+      return -EIO;
+    }
+
+  ret = fusb303_putreg(priv, FUSB303_INTERRUPT1_REG, FUSB303_ALL_INTR1);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to clear interrupts\n");
+      return -EIO;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: fusb303_setup
+ *
+ * Description:
+ *   Setup FUSB303 chip
+ *
+ ****************************************************************************/
+
+static int fusb303_setup(FAR struct fusb303_dev_s *priv,
+                         struct fusb303_setup_s *setup)
+{
+  int ret = OK;
+  uint8_t regval;
+
+  fusb303_info("drp_tgl:%02X, host_curr:%02X\n"
+               "dcable_en: %d, remedy_en: %d, auto_snk_en: %d\n"
+               "global_int: %d, mask: %02X, mask1: %02X\n",
+               setup->drp_toggle_timing, setup->host_current,
+               (int)setup->dcable_en, (int)setup->remedy_en,
+               (int)setup->auto_snk_en, (int)setup->global_int_mask,
+               setup->int_mask, setup->int_mask1);
+
+  /* Enable chip in I2C mode. */
+
+  ret = fusb303_getreg(priv, FUSB303_CONTROL1_REG);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to enable chip\n");
+      goto err_out;
+    }
+
+  /* TODO: no way to change AUTO_SNK_TH or TCCDEB at the moment. */
+
+  regval = (uint8_t)ret | CONTROL1_ENABLE;
+  if (setup->auto_snk_en)
+    {
+      regval |= CONTROL1_AUTO_SNK_EN;
+    }
+  else
+    {
+      regval &= ~CONTROL1_AUTO_SNK_EN;
+    }
+
+  if (setup->remedy_en)
+    {
+      regval |= CONTROL1_REMEDY_EN;
+    }
+  else
+    {
+      regval &= ~CONTROL1_REMEDY_EN;
+    }
+
+  ret = fusb303_putreg(priv, FUSB303_CONTROL1_REG, regval);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to enable chip\n");
+      goto err_out;
+    }
+
+  /* Setup the interrupt masks and remaining settings. */
+
+  ret = fusb303_putreg(priv, FUSB303_MASK_REG, setup->int_mask);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to write mask register\n");
+      goto err_out;
+    }
+
+  ret = fusb303_putreg(priv, FUSB303_MASK1_REG, setup->int_mask1);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to write mask register\n");
+      goto err_out;
+    }
+
+  /* Interrupts can happen only after unmasking global_int_mask */
+
+  regval = setup->drp_toggle_timing | setup->host_current |
+           setup->global_int_mask;
+  if (setup->dcable_en)
+    {
+      regval |= CONTROL_DCABLE_EN;
+    }
+
+  ret = fusb303_putreg(priv, FUSB303_CONTROL_REG, regval);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to write control register\n");
+      goto err_out;
+    }
+
+err_out:
+#ifdef CONFIG_DEBUG_FUSB303
+  fusb303_dumpregs("fusb303_setup", priv);
+#endif
+  return ret;
+}
+
+/****************************************************************************
+ * Name: fusb303_toggle_control1_enable
+ *
+ * Description:
+ *   Switch enable flag off and then on.
+ *
+ ****************************************************************************/
+
+static int fusb303_toggle_control1_enable(FAR struct fusb303_dev_s *priv)
+{
+  int regval;
+  int ret;
+
+  regval = fusb303_getreg(priv, FUSB303_CONTROL1_REG);
+  if (regval < 0)
+    {
+      fusb303_err("ERROR: Failed to read CONTROL1 register\n");
+      return -1;
+    }
+
+  if (!(regval & CONTROL1_ENABLE))
+    {
+      /* Not enabled, skip toggling. */
+
+      return 0;
+    }
+
+  ret = fusb303_putreg(priv, FUSB303_CONTROL1_REG,
+                       regval & ~CONTROL1_ENABLE);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to write CONTROL1 register\n");
+      return -1;
+    }
+
+  ret = fusb303_putreg(priv, FUSB303_CONTROL1_REG, regval);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to write CONTROL1 register\n");
+      return -1;
+    }
+
+  return 0;
+}
+
+/****************************************************************************
+ * Name: fusb303_set_mode
+ *
+ * Description:
+ *   Configure supported device modes (sink, source, DRP, accessory)
+ *
+ ****************************************************************************/
+
+static int fusb303_set_mode(FAR struct fusb303_dev_s *priv,
+                            enum fusb303_mode_e mode)
+{
+  int ret;
+
+  if (mode > MODE_ORIENTDEB)
+    {
+      return -EINVAL;
+    }
+
+  ret = fusb303_putreg(priv, FUSB303_PORTROLE_REG, mode);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to set portrole\n");
+      ret = -EIO;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: fusb303_set_state
+ *
+ * Description:
+ *   Force device in specified state
+ *
+ ****************************************************************************/
+
+static int fusb303_set_state(FAR struct fusb303_dev_s *priv,
+                             enum fusb303_manual_e state)
+{
+  int ret;
+
+  if (state > MANUAL_FORCE_SRC)
+    {
+      return -EINVAL;
+    }
+
+  ret = fusb303_putreg(priv, FUSB303_MANUAL_REG, state);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to set state\n");
+      ret = -EIO;
+    }
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: fusb303_read_status
+ *
+ * Description:
+ *   Read status register
+ *
+ ****************************************************************************/
+
+static int fusb303_read_status(FAR struct fusb303_dev_s *priv,
+                               FAR uint8_t *arg)
+{
+  int ret;
+
+  ret = fusb303_getreg(priv, FUSB303_STATUS_REG);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to read status\n");
+      return -EIO;
+    }
+
+  *arg = ret;
+  return OK;
+}
+
+/****************************************************************************
+ * Name: fusb303_read_devtype
+ *
+ * Description:
+ *   Read type of attached device
+ *
+ ****************************************************************************/
+
+static int fusb303_read_devtype(FAR struct fusb303_dev_s *priv,
+                                FAR uint8_t *arg)
+{
+  int ret;
+
+  ret = fusb303_getreg(priv, FUSB303_TYPE_REG);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to read type\n");
+      return -EIO;
+    }
+
+  *arg = ret;
+  return OK;
+}
+
+/****************************************************************************
+ * Name: fusb303_reset
+ *
+ * Description:
+ *   Reset FUSB303 HW and clear I2C registers
+ *
+ ****************************************************************************/
+
+static int fusb303_reset(FAR struct fusb303_dev_s *priv)
+{
+  int ret;
+
+  ret = fusb303_putreg(priv, FUSB303_RESET_REG, RESET_SW_RES);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to reset chip\n");
+      ret = -EIO;
+    }
+
+  /* tRESET max 100 ms. */
+
+  up_mdelay(100);
+
+  return ret;
+}
+
+/****************************************************************************
+ * Name: fusb303_open
+ *
+ * Description:
+ *   This function is called whenever the FUSB303 device is opened.
+ *
+ ****************************************************************************/
+
+static int fusb303_open(FAR struct file *filep)
+{
+  FAR struct inode *inode = filep->f_inode;
+  FAR struct fusb303_dev_s *priv = inode->i_private;
+  uint8_t dev_id;
+  uint8_t dev_type;
+  int ret;
+
+  ret = nxsem_wait(&priv->devsem);
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+  /* Probe device */
+
+  ret = fusb303_read_device_id(priv, &dev_id, &dev_type);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: No response at given address 0x%02X\n", priv->addr);
+      ret = -EFAULT;
+    }
+  else
+    {
+      fusb303_info("device id: 0x%02X type: 0x%02X\n", dev_id, dev_type);
+
+      (void)fusb303_clear_interrupts(priv);
+      priv->config->irq_enable(priv->config, true);
+    }
+
+  nxsem_post(&priv->devsem);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: fusb303_close
+ *
+ * Description:
+ *   This routine is called when the FUSB303 device is closed.
+ *
+ ****************************************************************************/
+
+static int fusb303_close(FAR struct file *filep)
+{
+  FAR struct inode *inode = filep->f_inode;
+  FAR struct fusb303_dev_s *priv = inode->i_private;
+  int ret;
+
+  ret = nxsem_wait(&priv->devsem);
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+  priv->config->irq_enable(priv->config, false);
+
+  nxsem_post(&priv->devsem);
+  return OK;
+}
+
+/****************************************************************************
+ * Name: fusb303_read
+ *
+ * Description:
+ *   This routine is called when the FUSB303 device is read.
+ *
+ ****************************************************************************/
+
+static ssize_t fusb303_read(FAR struct file *filep, FAR char *buffer,
+                            size_t buflen)
+{
+  FAR struct inode *inode = filep->f_inode;
+  FAR struct fusb303_dev_s *priv = inode->i_private;
+  FAR struct fusb303_result_s *ptr;
+  irqstate_t flags;
+  int ret;
+
+  if (buflen < sizeof(struct fusb303_result_s))
+    {
+      return 0;
+    }
+
+  ptr = (struct fusb303_result_s *)buffer;
+
+  ret = nxsem_wait(&priv->devsem);
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+  ptr->status = fusb303_getreg(priv, FUSB303_STATUS_REG);
+  ptr->status1 = fusb303_getreg(priv, FUSB303_STATUS1_REG);
+  ptr->dev_type = fusb303_getreg(priv, FUSB303_TYPE_REG);
+
+#ifdef CONFIG_DEBUG_FUSB303
+  fusb303_dumpregs("fusb303_read", priv);
+#endif
+
+  if (!(ptr->status & STATUS_ATTACH) ||
+      (ptr->status & STATUS_BC_LVL_3000) == STATUS_BC_LVL_UNATT)
+    {
+      /* Toggle enable bit when USB is not attached. This is needed to
+       * enable attach interrupt when orientation of USB-C cable changes.
+       */
+
+      (void)fusb303_toggle_control1_enable(priv);
+
+      up_mdelay(1); /* Wait for initial interrupt. */
+    }
+
+  flags = enter_critical_section();
+  priv->int_pending = false;
+  leave_critical_section(flags);
+
+  (void)fusb303_clear_interrupts(priv);
+
+  nxsem_post(&priv->devsem);
+  return sizeof(struct fusb303_result_s);
+}
+
+/****************************************************************************
+ * Name: fusb303_write
+ *
+ * Description:
+ *   This routine is called when the FUSB303 device is written to.
+ *
+ ****************************************************************************/
+
+static ssize_t fusb303_write(FAR struct file *filep, FAR const char *buffer,
+                             size_t buflen)
+{
+  ssize_t length = 0;
+
+  return length;
+}
+
+/****************************************************************************
+ * Name: fusb303_ioctl
+ *
+ * Description:
+ *   This routine is called when ioctl function call is performed for
+ *   the FUSB303 device.
+ *
+ ****************************************************************************/
+
+static int fusb303_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
+{
+  FAR struct inode *inode = filep->f_inode;
+  FAR struct fusb303_dev_s *priv = inode->i_private;
+  int ret;
+
+  ret = nxsem_wait(&priv->devsem);
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+  fusb303_info("cmd: 0x%02X, arg:%lu\n", cmd, arg);
+
+  switch (cmd)
+  {
+  case USBCIOC_READ_DEVID:
+    {
+      ret = fusb303_read_device_id(priv, (uint8_t *)arg, NULL);
+    }
+    break;
+
+  case USBCIOC_SETUP:
+    {
+      ret = fusb303_setup(priv, (struct fusb303_setup_s *)arg);
+    }
+    break;
+
+  case USBCIOC_SET_MODE:
+    {
+      ret = fusb303_set_mode(priv, (uint8_t)arg);
+    }
+    break;
+
+  case USBCIOC_SET_STATE:
+    {
+      ret = fusb303_set_state(priv, (uint8_t)arg);
+    }
+    break;
+
+  case USBCIOC_READ_STATUS:
+    {
+      ret = fusb303_read_status(priv, (uint8_t *)arg);
+    }
+    break;
+
+  case USBCIOC_READ_DEVTYPE:
+    {
+      ret = fusb303_read_devtype(priv, (uint8_t *)arg);
+    }
+    break;
+
+  case USBCIOC_RESET:
+    {
+      ret = fusb303_reset(priv);
+    }
+    break;
+
+  default:
+    {
+      fusb303_err("ERROR: Unrecognized cmd: %d\n", cmd);
+      ret = -ENOTTY;
+    }
+    break;
+  }
+
+  nxsem_post(&priv->devsem);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: fusb303_poll
+ *
+ * Description:
+ *   This routine is called during FUSB303 device poll
+ *
+ ****************************************************************************/
+
+static int fusb303_poll(FAR struct file *filep, FAR struct pollfd *fds,
+                        bool setup)
+{
+  FAR struct inode *inode;
+  FAR struct fusb303_dev_s *priv;
+  irqstate_t flags;
+  int ret = OK;
+  int i;
+
+  DEBUGASSERT(filep && fds);
+  inode = filep->f_inode;
+
+  DEBUGASSERT(inode && inode->i_private);
+  priv = (FAR struct fusb303_dev_s *)inode->i_private;
+
+  ret = nxsem_wait(&priv->devsem);
+  if (ret < 0)
+    {
+      return ret;
+    }
+
+  if (setup)
+    {
+      /* Ignore waits that do not include POLLIN */
+
+      if ((fds->events & POLLIN) == 0)
+        {
+          ret = -EDEADLK;
+          goto out;
+        }
+
+      /* This is a request to set up the poll. Find an available
+       * slot for the poll structure reference.
+       */
+
+      for (i = 0; i < CONFIG_FUSB303_NPOLLWAITERS; i++)
+        {
+          /* Find an available slot */
+
+          if (!priv->fds[i])
+            {
+              /* Bind the poll structure and this slot */
+
+              priv->fds[i] = fds;
+              fds->priv = &priv->fds[i];
+              break;
+            }
+        }
+
+      if (i >= CONFIG_FUSB303_NPOLLWAITERS)
+        {
+          fds->priv = NULL;
+          ret = -EBUSY;
+          goto out;
+        }
+
+      flags = enter_critical_section();
+      if (priv->int_pending)
+        {
+          fusb303_notify(priv);
+        }
+
+      leave_critical_section(flags);
+    }
+  else if (fds->priv)
+    {
+      /* This is a request to tear down the poll. */
+
+      struct pollfd **slot = (struct pollfd **)fds->priv;
+      DEBUGASSERT(slot != NULL);
+
+      /* Remove all memory of the poll setup */
+
+      *slot = NULL;
+      fds->priv = NULL;
+    }
+
+out:
+  nxsem_post(&priv->devsem);
+  return ret;
+}
+
+/****************************************************************************
+ * Name: fusb303_notify
+ *
+ * Description:
+ *   Notify thread about data to be available
+ *
+ ****************************************************************************/
+
+static void fusb303_notify(FAR struct fusb303_dev_s *priv)
+{
+  int i;
+
+  DEBUGASSERT(priv != NULL);
+
+  /* If there are threads waiting on poll() for FUSB303 data to become
+   * available, then wake them up now.  NOTE: we wake up all waiting threads
+   * because we do not know that they are going to do.  If they all try to
+   * read the data, then some make end up blocking after all.
+   */
+
+  for (i = 0; i < CONFIG_FUSB303_NPOLLWAITERS; i++)
+    {
+      struct pollfd *fds = priv->fds[i];
+      if (fds)
+        {
+          fds->revents |= POLLIN;
+          fusb303_info("Report events: %02x\n", fds->revents);
+          nxsem_post(fds->sem);
+        }
+    }
+}
+
+/****************************************************************************
+ * Name: fusb303_callback
+ *
+ * Description:
+ *   FUSB303 interrupt handler
+ *
+ ****************************************************************************/
+
+static int fusb303_int_handler(int irq, FAR void *context, FAR void *arg)
+{
+  FAR struct fusb303_dev_s *priv = (FAR struct fusb303_dev_s *)arg;
+  irqstate_t flags;
+
+  DEBUGASSERT(priv != NULL);
+
+  flags = enter_critical_section();
+  priv->int_pending = true;
+
+  fusb303_notify(priv);
+  leave_critical_section(flags);
+
+  return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+int fusb303_register(FAR const char *devpath, FAR struct i2c_master_s *i2c,
+                     uint8_t addr, FAR struct fusb303_config_s *config)
+{
+  FAR struct fusb303_dev_s *priv;
+  int ret;
+
+  DEBUGASSERT(devpath != NULL && i2c != NULL && config != NULL);
+
+  /* Initialize the FUSB303 device structure */
+
+  priv = (FAR struct fusb303_dev_s *)kmm_zalloc(sizeof(struct fusb303_dev_s));
+  if (!priv)
+    {
+      fusb303_err("ERROR: Failed to allocate instance\n");
+      return -ENOMEM;
+    }
+
+  /* Initialize device structure semaphore */
+
+  nxsem_init(&priv->devsem, 0, 1);
+
+  priv->int_pending = false;
+  priv->i2c         = i2c;
+  priv->addr        = addr;
+  priv->config      = config;
+
+  /* Register the character driver */
+
+  ret = register_driver(devpath, &g_fusb303ops, 0666, priv);
+  if (ret < 0)
+    {
+      fusb303_err("ERROR: Failed to register driver: %d\n", ret);
+      goto errout_with_priv;
+    }
+
+  /* Prepare interrupt line and handler. */
+
+  if (priv->config->irq_clear)
+    {
+      priv->config->irq_clear(config);
+    }
+
+  priv->config->irq_attach(config, fusb303_int_handler, priv);
+  priv->config->irq_enable(config, false);
+
+  return OK;
+
+errout_with_priv:
+  nxsem_destroy(&priv->devsem);
+  kmm_free(priv);
+
+  return ret;
+}
diff --git a/drivers/video/fb.c b/drivers/video/fb.c
index 53ff4c9124d..2caac78749b 100644
--- a/drivers/video/fb.c
+++ b/drivers/video/fb.c
@@ -96,10 +96,8 @@ static const struct file_operations fb_fops =
   fb_read,       /* read */
   fb_write,      /* write */
   fb_seek,       /* seek */
-  fb_ioctl       /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , NULL         /* poll */
-#endif
+  fb_ioctl,      /* ioctl */
+  NULL           /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL         /* unlink */
 #endif
diff --git a/drivers/video/max7456.c b/drivers/video/max7456.c
index 7f82ca9916b..7bff2315616 100644
--- a/drivers/video/max7456.c
+++ b/drivers/video/max7456.c
@@ -353,9 +353,7 @@ static ssize_t mx7_debug_write(FAR struct file *filep,
 
 static const struct file_operations g_mx7_fops =
 {
-#ifndef CONFIG_DISABLE_POLL
   .poll   = NULL,
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   .unlink = NULL,
 #endif
@@ -372,9 +370,7 @@ static const struct file_operations g_mx7_fops =
 
 static const struct file_operations g_mx7_debug_fops =
 {
-#ifndef CONFIG_DISABLE_POLL
   .poll   = NULL,
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   .unlink = NULL,
 #endif
diff --git a/drivers/wireless/cc1101.c b/drivers/wireless/cc1101.c
index ba995ddc1c2..44d5618cb86 100644
--- a/drivers/wireless/cc1101.c
+++ b/drivers/wireless/cc1101.c
@@ -300,10 +300,8 @@ static ssize_t cc1101_file_read(FAR struct file *filep, FAR char *buffer,
                                 size_t buflen);
 static ssize_t cc1101_file_write(FAR struct file *filep, FAR const char *buffer,
                                  size_t buflen);
-#ifndef CONFIG_DISABLE_POLL
 static int cc1101_file_poll(FAR struct file *filep, FAR struct pollfd *fds,
                             bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -316,11 +314,8 @@ static const struct file_operations g_cc1101ops =
   cc1101_file_read,  /* read */
   cc1101_file_write, /* write */
   NULL,              /* seek */
-  NULL               /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  ,
+  NULL,              /* ioctl */
   cc1101_file_poll   /* poll */
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   ,
   NULL               /* unlink */
@@ -630,7 +625,6 @@ static ssize_t cc1101_file_read(FAR struct file *filep, FAR char *buffer,
  *
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int cc1101_file_poll(FAR struct file *filep, FAR struct pollfd *fds,
                             bool setup)
 {
@@ -704,7 +698,6 @@ errout:
   nxsem_post(&dev->devsem);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Name: cc1101_access_begin
@@ -1580,14 +1573,12 @@ void cc1101_isr_process(FAR void *arg)
           fifo_put(dev, buf, len);
           nxsem_post(&dev->sem_rx);
 
-#ifndef CONFIG_DISABLE_POLL
           if (dev->pfd)
             {
               dev->pfd->revents |= POLLIN; /* Data available for input */
               wlinfo("Wake up polled fd\n");
               nxsem_post(dev->pfd->sem);
             }
-#endif
         }
         break;
 
diff --git a/drivers/wireless/ieee802154/xbee/xbee_netdev.c b/drivers/wireless/ieee802154/xbee/xbee_netdev.c
index f6406218741..be01ea7b9a4 100644
--- a/drivers/wireless/ieee802154/xbee/xbee_netdev.c
+++ b/drivers/wireless/ieee802154/xbee/xbee_netdev.c
@@ -159,14 +159,12 @@ struct xbeenet_driver_s
   sem_t xd_eventsem;                /* Signaling semaphore for waiting get event */
   sq_queue_t primitive_queue;       /* For holding primitives to pass along */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   /* MAC Service notification information */
 
   bool    xd_notify_registered;
   pid_t   xd_notify_pid;
   struct sigevent xd_notify_event;
   struct sigwork_s xd_notify_work;
-#endif
 };
 
 /****************************************************************************
@@ -442,14 +440,12 @@ static int xbeenet_notify(FAR struct xbee_maccb_s *maccb,
           nxsem_post(&priv->xd_eventsem);
         }
 
-#ifndef CONFIG_DISABLE_SIGNALS
       if (priv->xd_notify_registered)
         {
           priv->xd_notify_event.sigev_value.sival_int = primitive->type;
           nxsig_notification(priv->xd_notify_pid, &priv->xd_notify_event,
                              SI_QUEUE, &priv->xd_notify_work);
         }
-#endif
 
       nxsem_post(&priv->xd_exclsem);
       return OK;
@@ -1034,7 +1030,6 @@ static int xbeenet_ioctl(FAR struct net_driver_s *dev, int cmd,
 
           switch (cmd)
             {
-        #ifndef CONFIG_DISABLE_SIGNALS
               /* Command:     MAC802154IOC_NOTIFY_REGISTER
                * Description: Register to receive a signal whenever there is a
                *              event primitive sent from the MAC layer.
@@ -1054,7 +1049,7 @@ static int xbeenet_ioctl(FAR struct net_driver_s *dev, int cmd,
                   ret = OK;
                 }
                 break;
-        #endif
+
               case MAC802154IOC_GET_EVENT:
                 {
                   FAR struct ieee802154_primitive_s *primitive;
diff --git a/drivers/wireless/lpwan/sx127x/sx127x.c b/drivers/wireless/lpwan/sx127x/sx127x.c
index ce10210d1fd..a60271e03f9 100644
--- a/drivers/wireless/lpwan/sx127x/sx127x.c
+++ b/drivers/wireless/lpwan/sx127x/sx127x.c
@@ -303,9 +303,7 @@ struct sx127x_dev_s
 
   uint8_t nopens;                 /* Number of times the device has been opened */
   sem_t   dev_sem;                /* Ensures exclusive access to this structure */
-#ifndef CONFIG_DISABLE_POLL
   FAR struct pollfd *pfd;         /* Polled file descr  (or NULL if any) */
-#endif
 };
 
 /****************************************************************************
@@ -445,10 +443,8 @@ static ssize_t sx127x_read(FAR struct file *filep, FAR char *buffer,
 static ssize_t sx127x_write(FAR struct file *filep, FAR const char *buffer,
                             size_t buflen);
 static int sx127x_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int sx127x_poll(FAR struct file *filep, FAR struct pollfd *fds,
                        bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -467,10 +463,8 @@ static const struct file_operations sx127x_fops =
   sx127x_read,    /* read */
   sx127x_write,   /* write */
   NULL,           /* seek */
-  sx127x_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , sx127x_poll   /* poll */
-#endif
+  sx127x_ioctl,   /* ioctl */
+  sx127x_poll     /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL          /* unlink */
 #endif
@@ -1205,7 +1199,6 @@ static int sx127x_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  *
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int sx127x_poll(FAR struct file *filep, FAR struct pollfd *fds,
                        bool setup)
 {
@@ -1285,7 +1278,6 @@ errout:
   return ret;
 #endif
 }
-#endif
 
 /****************************************************************************
  * Name: sx127x_lora_isr0_process
@@ -1350,7 +1342,6 @@ static int sx127x_lora_isr0_process(FAR struct sx127x_dev_s *dev)
               ret = sx127x_lora_rxhandle(dev);
               if (ret > 0)
                 {
-#ifndef CONFIG_DISABLE_POLL
                   if (dev->pfd)
                     {
                       /* Data available for input */
@@ -1360,7 +1351,6 @@ static int sx127x_lora_isr0_process(FAR struct sx127x_dev_s *dev)
                       wlinfo("Wake up polled fd\n");
                       nxsem_post(dev->pfd->sem);
                     }
-#endif  /* CONFIG_DISABLE_POLL */
 
                   /* Wake-up any thread waiting in recv */
 
@@ -1487,7 +1477,6 @@ static int sx127x_fskook_isr0_process(FAR struct sx127x_dev_s *dev)
               ret = sx127x_fskook_rxhandle(dev);
               if (ret > 0)
                 {
-#ifndef CONFIG_DISABLE_POLL
                   if (dev->pfd)
                     {
                       /* Data available for input */
@@ -1497,7 +1486,6 @@ static int sx127x_fskook_isr0_process(FAR struct sx127x_dev_s *dev)
                       wlinfo("Wake up polled fd\n");
                       nxsem_post(dev->pfd->sem);
                     }
-#endif  /* CONFIG_DISABLE_POLL */
 
                   /* Wake-up any thread waiting in recv */
 
@@ -4587,9 +4575,7 @@ int sx127x_register(FAR struct spi_dev_s *spi,
 
   /* Polled file decr */
 
-#ifndef CONFIG_DISABLE_POLL
   dev->pfd        = NULL;
-#endif
 
   /* Initialize sem */
 
diff --git a/drivers/wireless/nrf24l01.c b/drivers/wireless/nrf24l01.c
index 06da78d77a4..ef7bfaa4dad 100644
--- a/drivers/wireless/nrf24l01.c
+++ b/drivers/wireless/nrf24l01.c
@@ -36,7 +36,8 @@
 /* Features:
  *   - Fixed length and dynamically sized payloads  (1 - 32 bytes)
  *   - Management of the 6 receiver pipes
- *   - Configuration of each pipe: address, packet length, auto-acknowledge, etc.
+ *   - Configuration of each pipe: address, packet length, auto-acknowledge,
+ *     etc.
  *   - Use a FIFO buffer to store the received packets
  *
  * Todo:
@@ -58,6 +59,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -143,6 +145,7 @@ struct nrf24l01_dev_s
 
   nrf24l01_state_t state;   /* Current state of the nRF24L01 */
 
+  bool tx_payload_noack;    /* TX without waiting for ACK */
   uint8_t en_aa;            /* Cache EN_AA register value */
   uint8_t en_pipes;         /* Cache EN_RXADDR register value */
   bool ce_enabled;          /* Cache the value of CE pin */
@@ -170,9 +173,7 @@ struct nrf24l01_dev_s
 
   uint8_t nopens;           /* Number of times the device has been opened */
   sem_t devsem;             /* Ensures exclusive access to this structure */
-#ifndef CONFIG_DISABLE_POLL
   FAR struct pollfd *pfd;   /* Polled file descr  (or NULL if any) */
-#endif
 };
 
 /****************************************************************************
@@ -186,7 +187,7 @@ static void nrf24l01_lock(FAR struct spi_dev_s *spi);
 static void nrf24l01_unlock(FAR struct spi_dev_s *spi);
 
 static uint8_t nrf24l01_access(FAR struct nrf24l01_dev_s *dev,
-             nrf24l01_access_mode_t mode, uint8_t cmd, uint8_t *buf,
+             nrf24l01_access_mode_t mode, uint8_t cmd, FAR uint8_t *buf,
              int length);
 static uint8_t nrf24l01_flush_rx(FAR struct nrf24l01_dev_s *dev);
 static uint8_t nrf24l01_flush_tx(FAR struct nrf24l01_dev_s *dev);
@@ -215,15 +216,16 @@ static int dosend(FAR struct nrf24l01_dev_s *dev, FAR const uint8_t *data,
 static int nrf24l01_unregister(FAR struct nrf24l01_dev_s *dev);
 
 #ifdef CONFIG_WL_NRF24L01_RXSUPPORT
-static void fifoput(struct nrf24l01_dev_s *dev, uint8_t pipeno,
+static void fifoput(FAR struct nrf24l01_dev_s *dev, uint8_t pipeno,
              FAR uint8_t *buffer, uint8_t buflen);
-static uint8_t fifoget(struct nrf24l01_dev_s *dev, FAR uint8_t *buffer,
+static uint8_t fifoget(FAR struct nrf24l01_dev_s *dev, FAR uint8_t *buffer,
              uint8_t buflen, FAR uint8_t *pipeno);
 static void nrf24l01_worker(FAR void *arg);
 #endif
 
 #ifdef CONFIG_DEBUG_WIRELESS
-static void binarycvt(char *deststr, const uint8_t *srcbin, size_t srclen);
+static void binarycvt(FAR char *deststr, FAR const uint8_t *srcbin,
+                      size_t srclen);
 #endif
 
 /* POSIX API */
@@ -236,10 +238,8 @@ static ssize_t nrf24l01_write(FAR struct file *filep,
              FAR const char *buffer, size_t buflen);
 static int nrf24l01_ioctl(FAR struct file *filep, int cmd,
              unsigned long arg);
-#ifndef CONFIG_DISABLE_POLL
 static int nrf24l01_poll(FAR struct file *filep, FAR struct pollfd *fds,
              bool setup);
-#endif
 
 /****************************************************************************
  * Private Data
@@ -252,10 +252,8 @@ static const struct file_operations nrf24l01_fops =
   nrf24l01_read,    /* read */
   nrf24l01_write,   /* write */
   NULL,             /* seek */
-  nrf24l01_ioctl    /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  , nrf24l01_poll   /* poll */
-#endif
+  nrf24l01_ioctl,   /* ioctl */
+  nrf24l01_poll     /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   , NULL            /* unlink */
 #endif
@@ -400,7 +398,7 @@ static uint8_t nrf24l01_access(FAR struct nrf24l01_dev_s *dev,
  * Name: nrf24l01_flush_rx
  ****************************************************************************/
 
-static inline uint8_t nrf24l01_flush_rx(struct nrf24l01_dev_s *dev)
+static inline uint8_t nrf24l01_flush_rx(FAR struct nrf24l01_dev_s *dev)
 {
   return nrf24l01_access(dev, MODE_WRITE, NRF24L01_FLUSH_RX, NULL, 0);
 }
@@ -409,7 +407,7 @@ static inline uint8_t nrf24l01_flush_rx(struct nrf24l01_dev_s *dev)
  * Name: nrf24l01_flush_tx
  ****************************************************************************/
 
-static inline uint8_t nrf24l01_flush_tx(struct nrf24l01_dev_s *dev)
+static inline uint8_t nrf24l01_flush_tx(FAR struct nrf24l01_dev_s *dev)
 {
   return nrf24l01_access(dev, MODE_WRITE, NRF24L01_FLUSH_TX, NULL, 0);
 }
@@ -422,7 +420,7 @@ static inline uint8_t nrf24l01_flush_tx(struct nrf24l01_dev_s *dev)
  *
  ****************************************************************************/
 
-static inline uint8_t nrf24l01_readreg(struct nrf24l01_dev_s *dev,
+static inline uint8_t nrf24l01_readreg(FAR struct nrf24l01_dev_s *dev,
                                        uint8_t reg, FAR uint8_t *value,
                                        int len)
 {
@@ -438,7 +436,7 @@ static inline uint8_t nrf24l01_readreg(struct nrf24l01_dev_s *dev,
  *
  ****************************************************************************/
 
-static inline uint8_t nrf24l01_readregbyte(struct nrf24l01_dev_s *dev,
+static inline uint8_t nrf24l01_readregbyte(FAR struct nrf24l01_dev_s *dev,
                                            uint8_t reg)
 {
   uint8_t val;
@@ -518,7 +516,8 @@ static void fifoput(FAR struct nrf24l01_dev_s *dev, uint8_t pipeno,
 
       int skiplen = FIFO_PKTLEN(dev) + 1;
 
-      dev->nxt_read = (dev->nxt_read + skiplen) % CONFIG_WL_NRF24L01_RXFIFO_LEN;
+      dev->nxt_read  = (dev->nxt_read + skiplen) %
+                       CONFIG_WL_NRF24L01_RXFIFO_LEN;
       dev->fifo_len -= skiplen;
     }
 
@@ -542,7 +541,7 @@ static void fifoput(FAR struct nrf24l01_dev_s *dev, uint8_t pipeno,
  ****************************************************************************/
 
 static uint8_t fifoget(FAR struct nrf24l01_dev_s *dev, FAR uint8_t *buffer,
-                       uint8_t buflen, uint8_t *pipeno)
+                       uint8_t buflen, FAR uint8_t *pipeno)
 {
   uint8_t pktlen;
   uint8_t i;
@@ -570,12 +569,14 @@ static uint8_t fifoget(FAR struct nrf24l01_dev_s *dev, FAR uint8_t *buffer,
   for (i = 0; i < pktlen && i < buflen; i++)
     {
       *(buffer++) = dev->rx_fifo[dev->nxt_read];
-      dev->nxt_read = (dev->nxt_read + 1) % CONFIG_WL_NRF24L01_RXFIFO_LEN;
+      dev->nxt_read = (dev->nxt_read + 1) %
+                      CONFIG_WL_NRF24L01_RXFIFO_LEN;
     }
 
   if (i < pktlen)
     {
-      dev->nxt_read = (dev->nxt_read + pktlen - i) % CONFIG_WL_NRF24L01_RXFIFO_LEN;
+      dev->nxt_read = (dev->nxt_read + pktlen - i) %
+                      CONFIG_WL_NRF24L01_RXFIFO_LEN;
     }
 
   /* Adjust fifo bytes count */
@@ -619,8 +620,8 @@ static int nrf24l01_irqhandler(int irq, FAR void *context, FAR void *arg)
  *
  ****************************************************************************/
 
-static inline int nrf24l01_attachirq(FAR struct nrf24l01_dev_s *dev, xcpt_t isr,
-                                     FAR void *arg)
+static inline int nrf24l01_attachirq(FAR struct nrf24l01_dev_s *dev,
+                                     xcpt_t isr, FAR void *arg)
 {
   return dev->config->irqattach(isr, arg);
 }
@@ -664,9 +665,7 @@ static void nrf24l01_worker(FAR void *arg)
       /* Put CE low */
 
       bool ce = nrf24l01_chipenable(dev, false);
-#ifndef CONFIG_DISABLE_POLL
       bool has_data = false;
-#endif
 
       wlinfo("RX_DR is set!\n");
 
@@ -699,7 +698,8 @@ static void nrf24l01_worker(FAR void *arg)
                * to get actual length.
                */
 
-              nrf24l01_access(dev, MODE_READ, NRF24L01_R_RX_PL_WID, &pktlen, 1);
+              nrf24l01_access(dev, MODE_READ, NRF24L01_R_RX_PL_WID, &pktlen,
+                              1);
             }
 
           if (pktlen > NRF24L01_MAX_PAYLOAD_LEN) /* bad length */
@@ -714,19 +714,17 @@ static void nrf24l01_worker(FAR void *arg)
           nrf24l01_access(dev, MODE_READ, NRF24L01_R_RX_PAYLOAD, buf, pktlen);
 
           fifoput(dev, pipeno, buf, pktlen);
-#ifndef CONFIG_DISABLE_POLL
           has_data = true;
-#endif
           nxsem_post(&dev->sem_rx);  /* Wake-up any thread waiting in recv */
 
-          status = nrf24l01_readreg(dev, NRF24L01_FIFO_STATUS, &fifo_status, 1);
+          status = nrf24l01_readreg(dev, NRF24L01_FIFO_STATUS, &fifo_status,
+                                    1);
 
           wlinfo("FIFO_STATUS=%02x\n", fifo_status);
           wlinfo("STATUS=%02x\n", status);
         }
       while ((fifo_status & NRF24L01_RX_EMPTY) == 0);
 
-#ifndef CONFIG_DISABLE_POLL
       if (dev->pfd && has_data)
         {
           dev->pfd->revents |= POLLIN;  /* Data available for input */
@@ -734,7 +732,6 @@ static void nrf24l01_worker(FAR void *arg)
           wlinfo("Wake up polled fd\n");
           nxsem_post(dev->pfd->sem);
         }
-#endif
 
       /* Clear interrupt sources */
 
@@ -774,7 +771,7 @@ static void nrf24l01_worker(FAR void *arg)
  * Name: nrf24l01_tostate
  ****************************************************************************/
 
-static void nrf24l01_tostate(struct nrf24l01_dev_s *dev,
+static void nrf24l01_tostate(FAR struct nrf24l01_dev_s *dev,
                              nrf24l01_state_t state)
 {
   nrf24l01_state_t oldstate = dev->state;
@@ -829,6 +826,7 @@ static int dosend(FAR struct nrf24l01_dev_s *dev, FAR const uint8_t *data,
 {
   uint8_t status;
   uint8_t obsvalue;
+  uint8_t cmd;
   int ret;
 
   /* Store the current lifecycle state in order to restore it after transmit
@@ -843,10 +841,11 @@ static int dosend(FAR struct nrf24l01_dev_s *dev, FAR const uint8_t *data,
 
   nrf24l01_flush_tx(dev);
 
-  /* Write payload */
+  /* Write payload - use different command depending on ACK setting */
 
-  nrf24l01_access(dev, MODE_WRITE, NRF24L01_W_TX_PAYLOAD,
-                  (FAR uint8_t *)data, datalen);
+  cmd = dev->tx_payload_noack ? NRF24L01_W_TX_PAYLOAD_NOACK :
+        NRF24L01_W_TX_PAYLOAD;
+  nrf24l01_access(dev, MODE_WRITE, cmd, (FAR uint8_t *)data, datalen);
 
   dev->tx_pending = true;
 
@@ -911,7 +910,8 @@ out:
 
   /* Clear interrupt sources */
 
-  nrf24l01_writeregbyte(dev, NRF24L01_STATUS, NRF24L01_TX_DS | NRF24L01_MAX_RT);
+  nrf24l01_writeregbyte(dev, NRF24L01_STATUS, NRF24L01_TX_DS |
+                             NRF24L01_MAX_RT);
 
   /* Clear fifo */
 
@@ -928,16 +928,17 @@ out:
  ****************************************************************************/
 
 #ifdef CONFIG_DEBUG_WIRELESS
-static void binarycvt(char *deststr, const uint8_t *srcbin, size_t srclen)
+static void binarycvt(FAR char *deststr, FAR const uint8_t *srcbin,
+                      size_t srclen)
 {
   int i = 0;
   while (i < srclen)
     {
-      sprintf(deststr + i*2, "%02x", srcbin[i]);
+      sprintf(deststr + i * 2, "%02x", srcbin[i]);
       ++i;
     }
 
-  *(deststr + i*2) = '\0';
+  *(deststr + i * 2) = '\0';
 }
 #endif
 
@@ -1057,7 +1058,28 @@ static ssize_t nrf24l01_read(FAR struct file *filep, FAR char *buffer,
       return ret;
     }
 
+  if (filep->f_oflags & O_NONBLOCK)
+    {
+      int packet_count;
+
+      /* Test if data is ready */
+
+      ret = nxsem_getvalue(&dev->sem_rx, &packet_count);
+      if (ret)
+        {
+          goto errout; /* getvalue failed */
+        }
+
+      if (!packet_count)
+        {
+          ret = -EWOULDBLOCK; /* don't wait for packets */
+          goto errout;
+        }
+    }
+
   ret = nrf24l01_recv(dev, (uint8_t *)buffer, buflen, &dev->last_recvpipeno);
+
+errout:
   nxsem_post(&dev->devsem);
   return ret;
 #endif
@@ -1199,7 +1221,8 @@ static int nrf24l01_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
       case NRF24L01IOC_SETPIPESCFG:
         {
           int i;
-          FAR nrf24l01_pipecfg_t **cfg_array = (FAR nrf24l01_pipecfg_t **)(arg);
+          FAR nrf24l01_pipecfg_t **cfg_array =
+            (FAR nrf24l01_pipecfg_t **)(arg);
 
           DEBUGASSERT(cfg_array != NULL);
           for (i = 0; i < NRF24L01_PIPE_COUNT; i++)
@@ -1215,7 +1238,8 @@ static int nrf24l01_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
       case NRF24L01IOC_GETPIPESCFG:
         {
           int i;
-          FAR nrf24l01_pipecfg_t **cfg_array = (FAR nrf24l01_pipecfg_t **)(arg);
+          FAR nrf24l01_pipecfg_t **cfg_array =
+            (FAR nrf24l01_pipecfg_t **)(arg);
 
           DEBUGASSERT(cfg_array != NULL);
           for (i = 0; i < NRF24L01_PIPE_COUNT; i++)
@@ -1323,6 +1347,24 @@ static int nrf24l01_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
           break;
         }
 
+      case NRF24L01IOC_SETTXPAYLOADNOACK:
+        {
+          FAR uint32_t *tx_payload_noack = (FAR uint32_t *)(arg);
+          DEBUGASSERT(tx_payload_noack != NULL);
+
+          dev->tx_payload_noack = (*tx_payload_noack) > 0;
+          break;
+        }
+
+      case NRF24L01IOC_GETTXPAYLOADNOACK:
+        {
+          FAR uint32_t *tx_payload_noack = (FAR uint32_t *)(arg);
+          DEBUGASSERT(tx_payload_noack != NULL);
+
+          *tx_payload_noack = dev->tx_payload_noack ? 1 : 0;
+          break;
+        }
+
       default:
         ret = -ENOTTY;
         break;
@@ -1336,7 +1378,6 @@ static int nrf24l01_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
  * Name: nrf24l01_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 static int nrf24l01_poll(FAR struct file *filep, FAR struct pollfd *fds,
                          bool setup)
 {
@@ -1416,7 +1457,6 @@ errout:
   return ret;
 #endif
 }
-#endif
 
 /****************************************************************************
  * Name: nrf24l01_unregister
@@ -1455,12 +1495,12 @@ int nrf24l01_register(FAR struct spi_dev_s *spi,
   int ret = OK;
 
 #ifdef CONFIG_WL_NRF24L01_RXSUPPORT
-  uint8_t *rx_fifo;
+  FAR uint8_t *rx_fifo;
 #endif
 
   DEBUGASSERT((spi != NULL) & (cfg != NULL));
 
-  if ((dev = kmm_malloc(sizeof(struct nrf24l01_dev_s))) == NULL)
+  if ((dev = kmm_zalloc(sizeof(struct nrf24l01_dev_s))) == NULL)
     {
       return -ENOMEM;
     }
@@ -1469,16 +1509,9 @@ int nrf24l01_register(FAR struct spi_dev_s *spi,
   dev->config     = cfg;
 
   dev->state      = ST_UNKNOWN;
-  dev->en_aa      = 0;
   dev->ce_enabled = false;
 
   nxsem_init(&(dev->devsem), 0, 1);
-  dev->nopens     = 0;
-
-#ifndef CONFIG_DISABLE_POLL
-  dev->pfd        = NULL;
-#endif
-
   nxsem_init(&dev->sem_tx, 0, 0);
   nxsem_setprotocol(&dev->sem_tx, SEM_PRIO_NONE);
 
@@ -1490,10 +1523,6 @@ int nrf24l01_register(FAR struct spi_dev_s *spi,
     }
 
   dev->rx_fifo         = rx_fifo;
-  dev->nxt_read        = 0;
-  dev->nxt_write       = 0;
-  dev->fifo_len        = 0;
-  dev->irq_work.worker = 0;
 
   nxsem_init(&(dev->sem_fifo), 0, 1);
   nxsem_init(&(dev->sem_rx), 0, 0);
@@ -1538,9 +1567,12 @@ int nrf24l01_init(FAR struct nrf24l01_dev_s *dev)
 
   nrf24l01_configspi(dev->spi);
 
-  /* Enable features. */
+  /* Enable features in hardware: dynamic payload length + sending without
+   * expecting ACK
+   */
 
-  nrf24l01_writeregbyte(dev, NRF24L01_FEATURE, NRF24L01_EN_DPL);
+  nrf24l01_writeregbyte(dev, NRF24L01_FEATURE, NRF24L01_EN_DPL |
+                             NRF24L01_EN_DYN_ACK);
   features = nrf24l01_readregbyte(dev, NRF24L01_FEATURE);
   if (0 == features)
     {
@@ -1684,11 +1716,13 @@ int nrf24l01_getpipeconfig(FAR struct nrf24l01_dev_s *dev,
 
   /* Auto ack */
 
-  pipecfg->en_aa = ((nrf24l01_readregbyte(dev, NRF24L01_EN_AA) & (1 << pipeno)) != 0);
+  pipecfg->en_aa =
+    ((nrf24l01_readregbyte(dev, NRF24L01_EN_AA) & (1 << pipeno)) != 0);
 
   /* Payload config */
 
-  dynlength = ((nrf24l01_readregbyte(dev, NRF24L01_DYNPD) & (1 << pipeno)) != 0);
+  dynlength =
+    ((nrf24l01_readregbyte(dev, NRF24L01_DYNPD) & (1 << pipeno)) != 0);
 
   if (dynlength)
     {
@@ -1696,7 +1730,8 @@ int nrf24l01_getpipeconfig(FAR struct nrf24l01_dev_s *dev,
     }
   else
     {
-      pipecfg->payload_length = nrf24l01_readregbyte(dev, NRF24L01_RX_PW_P0 + pipeno);
+      pipecfg->payload_length =
+        nrf24l01_readregbyte(dev, NRF24L01_RX_PW_P0 + pipeno);
     }
 
   nrf24l01_unlock(dev->spi);
@@ -1939,7 +1974,7 @@ int nrf24l01_setaddrwidth(FAR struct nrf24l01_dev_s *dev, uint32_t width)
              width >= NRF24L01_MIN_ADDR_LEN);
 
   nrf24l01_lock(dev->spi);
-  nrf24l01_writeregbyte(dev, NRF24L01_SETUP_AW, width-2);
+  nrf24l01_writeregbyte(dev, NRF24L01_SETUP_AW, width - 2);
   nrf24l01_unlock(dev->spi);
   dev->addrlen = width;
   return OK;
@@ -1949,7 +1984,8 @@ int nrf24l01_setaddrwidth(FAR struct nrf24l01_dev_s *dev, uint32_t width)
  * Name: nrf24l01_changestate
  ****************************************************************************/
 
-int nrf24l01_changestate(FAR struct nrf24l01_dev_s *dev, nrf24l01_state_t state)
+int nrf24l01_changestate(FAR struct nrf24l01_dev_s *dev,
+                         nrf24l01_state_t state)
 {
   nrf24l01_lock(dev->spi);
   nrf24l01_tostate(dev, state);
@@ -2030,8 +2066,8 @@ int nrf24l01_lastxmitcount(FAR struct nrf24l01_dev_s *dev)
  ****************************************************************************/
 
 #ifdef CONFIG_WL_NRF24L01_RXSUPPORT
-ssize_t nrf24l01_recv(struct nrf24l01_dev_s *dev, uint8_t *buffer,
-                      size_t buflen, uint8_t *recvpipe)
+ssize_t nrf24l01_recv(FAR struct nrf24l01_dev_s *dev, FAR uint8_t *buffer,
+                      size_t buflen, FAR uint8_t *recvpipe)
 {
   int ret = nxsem_wait(&dev->sem_rx);
   if (ret < 0)
@@ -2051,7 +2087,7 @@ ssize_t nrf24l01_recv(struct nrf24l01_dev_s *dev, uint8_t *buffer,
  ****************************************************************************/
 
 #ifdef CONFIG_DEBUG_WIRELESS
-void nrf24l01_dumpregs(struct nrf24l01_dev_s *dev)
+void nrf24l01_dumpregs(FAR struct nrf24l01_dev_s *dev)
 {
   uint8_t addr[NRF24L01_MAX_ADDR_LEN];
   char addrstr[NRF24L01_MAX_ADDR_LEN * 2 +1];
@@ -2109,7 +2145,7 @@ void nrf24l01_dumpregs(struct nrf24l01_dev_s *dev)
  ****************************************************************************/
 
 #if defined(CONFIG_DEBUG_WIRELESS) && defined(CONFIG_WL_NRF24L01_RXSUPPORT)
-void nrf24l01_dumprxfifo(struct nrf24l01_dev_s *dev)
+void nrf24l01_dumprxfifo(FAR struct nrf24l01_dev_s *dev)
 {
   syslog(LOG_INFO, "bytes count: %d\n", dev->fifo_len);
   syslog(LOG_INFO, "next read:   %d,  next write: %d\n",
diff --git a/fs/nxffs/nxffs_dump.c b/fs/nxffs/nxffs_dump.c
index fb290479f39..024f42aaa3c 100644
--- a/fs/nxffs/nxffs_dump.c
+++ b/fs/nxffs/nxffs_dump.c
@@ -76,8 +76,10 @@ struct nxffs_blkinfo_s
  * Private Data
  ****************************************************************************/
 
+#if defined(CONFIG_DEBUG_FEATURES) && defined(CONFIG_DEBUG_FS)
 static const char g_hdrformat[] = "  BLOCK:OFFS  TYPE  STATE   LENGTH\n";
 static const char g_format[]    = "  %5d:%-5d %s %s %5d\n";
+#endif
 
 /****************************************************************************
  * Private Functions
@@ -351,7 +353,7 @@ static inline void nxffs_analyze(FAR struct nxffs_blkinfo_s *blkinfo)
              blkinfo->geo.blocksize);
     }
 
-  /* Serach for Inode and data block headers.  */
+  /* Search for Inode and data block headers.  */
 
   inndx = 0;
   datndx = 0;
diff --git a/fs/procfs/fs_procfs.c b/fs/procfs/fs_procfs.c
index 121e61c2991..4db3f51a295 100644
--- a/fs/procfs/fs_procfs.c
+++ b/fs/procfs/fs_procfs.c
@@ -188,13 +188,13 @@ static const struct procfs_entry_s g_procfs_entries[] =
 
 #ifdef CONFIG_FS_PROCFS_REGISTER
 static const uint8_t g_base_entrycount = sizeof(g_base_entries) /
-                                        sizeof(struct procfs_entry_s);
+                                         sizeof(struct procfs_entry_s);
 
 static FAR struct procfs_entry_s *g_procfs_entries;
 static uint8_t g_procfs_entrycount;
 #else
 static const uint8_t g_procfs_entrycount = sizeof(g_procfs_entries) /
-                                          sizeof(struct procfs_entry_s);
+                                           sizeof(struct procfs_entry_s);
 #endif
 
 /****************************************************************************
@@ -244,15 +244,9 @@ static int     procfs_stat(FAR struct inode *mountpt,
 /* Initialization */
 
 #ifdef CONFIG_FS_PROCFS_REGISTER
-int procfs_initialize(void);
-#else
-#  define procfs_initialize()
+static int     procfs_initialize(void);
 #endif
 
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
 /****************************************************************************
  * Public Data
  ****************************************************************************/
@@ -616,12 +610,14 @@ static int procfs_opendir(FAR struct inode *mountpt, FAR const char *relpath,
 
           if (match(g_procfs_entries[x].pathpattern, relpath))
             {
-              /* Match found!  Call the handler's opendir routine.  If successful,
-               * this opendir routine will create an entry derived from struct
-               * procfs_dir_priv_s as dir->u.procfs.
+              /* Match found!  Call the handler's opendir routine.  If
+               * successful, this opendir routine will create an entry
+               * derived from struct procfs_dir_priv_s as dir->u.procfs.
                */
 
-              DEBUGASSERT(g_procfs_entries[x].ops && g_procfs_entries[x].ops->opendir);
+              DEBUGASSERT(g_procfs_entries[x].ops != NULL &&
+                          g_procfs_entries[x].ops->opendir != NULL);
+
               ret = g_procfs_entries[x].ops->opendir(relpath, dir);
 
               if (ret == OK)
@@ -639,14 +635,15 @@ static int procfs_opendir(FAR struct inode *mountpt, FAR const char *relpath,
 
             /* Test for a sub-string match (e.g. "ls /proc/fs") */
 
-          else if (strncmp(g_procfs_entries[x].pathpattern, relpath, len) == 0)
+          else if (strncmp(g_procfs_entries[x].pathpattern, relpath,
+                           len) == 0)
             {
               FAR struct procfs_level1_s *level1;
 
               /* Doing an intermediate directory search */
 
-              /* The path refers to the top level directory.  Allocate the level1
-               * dirent structure.
+              /* The path refers to the top level directory.  Allocate
+               * the level1 dirent structure.
                */
 
               level1 = (FAR struct procfs_level1_s *)
@@ -654,7 +651,8 @@ static int procfs_opendir(FAR struct inode *mountpt, FAR const char *relpath,
 
               if (!level1)
                 {
-                  ferr("ERROR: Failed to allocate the level0 directory structure\n");
+                  ferr("ERROR: Failed to allocate the level0 directory "
+                       "structure\n");
                   return -ENOMEM;
                 }
 
@@ -850,8 +848,8 @@ static int procfs_readdir(struct inode *mountpt, struct fs_dirent_s *dir)
           dir->fd_dir.d_type = DTYPE_DIRECTORY;
           snprintf(dir->fd_dir.d_name, NAME_MAX + 1, "%d", (int)pid);
 
-          /* Set up the next directory entry offset.  NOTE that we could use the
-           * standard f_pos instead of our own private index.
+          /* Set up the next directory entry offset.  NOTE that we could use
+           * the standard f_pos instead of our own private index.
            */
 
           level0->base.index = index + 1;
@@ -959,8 +957,8 @@ static int procfs_rewinddir(struct inode *mountpt, struct fs_dirent_s *dir)
  *
  * Description: This implements a portion of the mount operation. This
  *  function allocates and initializes the mountpoint private data and
- *  binds the blockdriver inode to the filesystem private data.  The final
- *  binding of the private data (containing the blockdriver) to the
+ *  binds the block driver inode to the filesystem private data.  The final
+ *  binding of the private data (containing the block driver) to the
  *  mountpoint is performed by mount().
  *
  ****************************************************************************/
@@ -968,9 +966,12 @@ static int procfs_rewinddir(struct inode *mountpt, struct fs_dirent_s *dir)
 static int procfs_bind(FAR struct inode *blkdriver, const void *data,
                        void **handle)
 {
+#ifdef CONFIG_FS_PROCFS_REGISTER
   /* Make sure that we are properly initialized */
 
   procfs_initialize();
+#endif
+
   return OK;
 }
 
@@ -1063,7 +1064,8 @@ static int procfs_stat(struct inode *mountpt, const char *relpath,
 
           /* Test for an internal subdirectory stat */
 
-          else if (strncmp(g_procfs_entries[x].pathpattern, relpath, len) == 0)
+          else if (strncmp(g_procfs_entries[x].pathpattern, relpath,
+                           len) == 0)
             {
               /* It's an internal subdirectory */
 
@@ -1098,7 +1100,7 @@ int procfs_initialize(void)
 
   if (g_procfs_entries == NULL)
     {
-      /* No.. allocate a modifyable list of entries */
+      /* No.. allocate a modifiable list of entries */
 
       g_procfs_entries = (FAR struct procfs_entry_s *)
         kmm_malloc(sizeof(g_base_entries));
@@ -1168,7 +1170,9 @@ int procfs_register(FAR const struct procfs_entry_s *entry)
   newsize  = newcount * sizeof(struct procfs_entry_s);
 
   sched_lock();
-  newtable = (FAR struct procfs_entry_s *)kmm_realloc(g_procfs_entries, newsize);
+  newtable = (FAR struct procfs_entry_s *)
+    kmm_realloc(g_procfs_entries, newsize);
+
   if (newtable == NULL)
     {
       /* Reallocation failed! */
@@ -1179,7 +1183,8 @@ int procfs_register(FAR const struct procfs_entry_s *entry)
     {
       /* Copy the new entry at the end of the reallocated table */
 
-      memcpy(&newtable[g_procfs_entrycount], entry, sizeof(struct procfs_entry_s));
+      memcpy(&newtable[g_procfs_entrycount], entry,
+             sizeof(struct procfs_entry_s));
 
       /* Instantiate the reallocated table */
 
diff --git a/fs/procfs/fs_procfsproc.c b/fs/procfs/fs_procfsproc.c
index 76dc0d4145b..3fbf1e6ffb5 100644
--- a/fs/procfs/fs_procfsproc.c
+++ b/fs/procfs/fs_procfsproc.c
@@ -386,10 +386,8 @@ static FAR const char *g_statenames[] =
 #endif
   "Running",
   "Inactive",
-  "Waiting,Semaphore"
-#ifndef CONFIG_DISABLE_SIGNALS
-  , "Waiting,Signal"
-#endif
+  "Waiting,Semaphore",
+  "Waiting,Signal"
 #ifndef CONFIG_DISABLE_MQUEUE
   , "Waiting,MQ empty"
   , "Waiting,MQ full"
@@ -628,14 +626,11 @@ static ssize_t proc_status(FAR struct proc_file_s *procfile,
 
   /* Show the signal mask */
 
-#ifndef CONFIG_DISABLE_SIGNALS
   linesize = snprintf(procfile->line, STATUS_LINELEN, "%-12s%08x\n", "SigMask:",
                       tcb->sigprocmask);
   copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, &offset);
 
   totalsize += copysize;
-#endif
-
   return totalsize;
 }
 
diff --git a/fs/vfs/fs_epoll.c b/fs/vfs/fs_epoll.c
index ca9a6bfdccd..1aece415e25 100644
--- a/fs/vfs/fs_epoll.c
+++ b/fs/vfs/fs_epoll.c
@@ -49,8 +49,6 @@
 
 #include 
 
-#ifndef CONFIG_DISABLE_POLL
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -235,4 +233,3 @@ int epoll_wait(int epfd, FAR struct epoll_event *evs, int maxevents,
   return i;
 }
 
-#endif /* CONFIG_DISABLE_POLL */
diff --git a/fs/vfs/fs_poll.c b/fs/vfs/fs_poll.c
index 6319ad96a5a..0e59edf53b4 100644
--- a/fs/vfs/fs_poll.c
+++ b/fs/vfs/fs_poll.c
@@ -56,8 +56,6 @@
 
 #include "inode/inode.h"
 
-#ifndef CONFIG_DISABLE_POLL
-
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
@@ -130,7 +128,8 @@ static int poll_fdsetup(int fd, FAR struct pollfd *fds, bool setup)
  *
  ****************************************************************************/
 
-static inline int poll_setup(FAR struct pollfd *fds, nfds_t nfds, sem_t *sem)
+static inline int poll_setup(FAR struct pollfd *fds, nfds_t nfds,
+                             FAR sem_t *sem)
 {
   unsigned int i;
   unsigned int j;
@@ -542,4 +541,3 @@ int poll(FAR struct pollfd *fds, nfds_t nfds, int timeout)
   return count;
 }
 
-#endif /* CONFIG_DISABLE_POLL */
diff --git a/fs/vfs/fs_select.c b/fs/vfs/fs_select.c
index f473b57fbb0..1acd40d0fe0 100644
--- a/fs/vfs/fs_select.c
+++ b/fs/vfs/fs_select.c
@@ -54,16 +54,6 @@
 
 #include "inode/inode.h"
 
-#ifndef CONFIG_DISABLE_POLL
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -295,4 +285,3 @@ errout:
   return ERROR;
 }
 
-#endif /* CONFIG_DISABLE_POLL */
diff --git a/graphics/Kconfig b/graphics/Kconfig
index c763bb10b28..f8154a23d4d 100644
--- a/graphics/Kconfig
+++ b/graphics/Kconfig
@@ -62,7 +62,17 @@ config NX_RAMBACKED
 
 		Redraw requests in other cases are also suppressed:  Changes to window
 		position, size, etc.  As a consequence, some manual updates will be
-		required when certain events occurr (like removing a toolbar from a
+		required when certain events occur (like removing a toolbar from a
+		window).
+
+		An exception is the case when the window is resized to a wider and/or
+		taller size.  In that case, the redraw callback will till occur.
+		It is necessary in that case to provide new graphic content for the
+		extended window area.
+
+		Redraw requests in other cases are also suppressed:  Changes to window
+		position, size, etc.  As a consequence, some manual updates will be
+		required when certain events occur (like removing a toolbar from a
 		window).
 
 		NOTE:  A significant amount of RAM, usually external SDRAM, may be
@@ -77,11 +87,31 @@ config NX_NOCURSOR
 
 config NX_SWCURSOR
 	bool "Software cursor support"
-	depends on NX_RAMBACKED && EXPERIMENTAL
+	depends on !NX_LCDDRIVER && NX_DISABLE_1BPP && NX_DISABLE_2BPP && NX_DISABLE_4BPP && !BUILD_KERNEL
+	---help---
+		Software cursor support has several dependencies are due to un-
+		implemented cursor capabilities.  This assumes the following:
+
+		  1. You are using a framebuffer hardware interface.  This is
+		     because the logic to implement this feature on top of the LCD
+		     interface has not been implemented.
+		  2. The pixel depth is greater then or equal to 8-bits (8-bpp,
+		     16-bpp, 24/32/-bpp).  This is because the logic to handle
+		     pixels smaller than 1-byte has not been implemented,
+		  3. For FLAT and PROTECTED builds only.  In those builds, the
+		     cursor image resides in the common application space and is
+		     assumed to pesist as long as needed.  But with the KERNEL
+		     build, the image will lie in a process space and will not be
+		     generally available.  In that case, we could keep the image in
+		     a shared memory region or perhaps copy the image into a kernel
+		     internal buffer.  Neither of  those are implemented.
 
 config NX_HWCURSOR
 	bool "Software cursor support"
 	depends on (FB_HWCURSOR || LCD_HWCURSOR) && EXPERIMENTAL
+	---help---
+		Hardware cursor support has not been implemented, hence the
+		EXPERIMENTAL dependency.
 
 endchoice # Cursor support
 
@@ -403,6 +433,21 @@ config NXTERM_NXKBDIN
 		by window callback functions so that keyboard input *only* goes to the
 		top window.
 
+		NOTE: nxterm_kdbin() is an internal OS API.  It can be accessed by
+		applications via the boardctl(BOARDIOC_NXTERM) interface.
+
+		The logic path is complex in this case:  (1) The keyboard input is
+		received by an application listener thread and injected into NX via
+		nx_kbdin().  NX sends (2) the keyboard input to single the NX window
+		that has focus.  That window then (3) gives the keyboard input to the
+		single NxTerm associated with the window via boardctl(BOARDIOC_NXTERM).
+
+		NOTE:  If CONFIG_NXTERM_NXKBDIN not defined, then NxTerm input coming
+		directly from /dev/console.  That works well if there is only a single
+		NxTerm window.  But if there are multiple NxTerm windows, then it is
+		anyone's guess which will receive the keyboard input.  That does not
+		work well in such cases.
+
 config NXTERM_KBDBUFSIZE
 	int "Keyboard Input Buffer Size"
 	default 16
diff --git a/graphics/Makefile b/graphics/Makefile
index d70491f41bd..2e4d9d1fae8 100644
--- a/graphics/Makefile
+++ b/graphics/Makefile
@@ -1,7 +1,8 @@
 ############################################################################
 # graphics/Makefile
 #
-#   Copyright (C) 2008-2009, 2011-2012, 2016 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2008-2009, 2011-2012, 2016, 2019 Gregory Nutt. All
+#     rights reserved.
 #   Author: Gregory Nutt 
 #
 # Redistribution and use in source and binary forms, with or without
@@ -87,24 +88,36 @@ gen8bppsource:
 ifeq ($(CONFIG_NX_RAMBACKED),y)
 	$(Q) $(MAKE) -C nxglib -f Makefile.pwfb TOPDIR=$(TOPDIR) NXGLIB_BITSPERPIXEL=8 EXTRADEFINES=$(EXTRADEFINES)
 endif
+ifeq ($(CONFIG_NX_SWCURSOR),y)
+	$(Q) $(MAKE) -C nxglib -f Makefile.cursor TOPDIR=$(TOPDIR) NXGLIB_BITSPERPIXEL=8 EXTRADEFINES=$(EXTRADEFINES)
+endif
 
 gen16bppsource:
 	$(Q) $(MAKE) -C nxglib -f Makefile.devblit TOPDIR=$(TOPDIR) NXGLIB_BITSPERPIXEL=16 EXTRADEFINES=$(EXTRADEFINES)
 ifeq ($(CONFIG_NX_RAMBACKED),y)
 	$(Q) $(MAKE) -C nxglib -f Makefile.pwfb TOPDIR=$(TOPDIR) NXGLIB_BITSPERPIXEL=16 EXTRADEFINES=$(EXTRADEFINES)
 endif
+ifeq ($(CONFIG_NX_SWCURSOR),y)
+	$(Q) $(MAKE) -C nxglib -f Makefile.cursor TOPDIR=$(TOPDIR) NXGLIB_BITSPERPIXEL=16 EXTRADEFINES=$(EXTRADEFINES)
+endif
 
 gen24bppsource:
 	$(Q) $(MAKE) -C nxglib -f Makefile.devblit TOPDIR=$(TOPDIR) NXGLIB_BITSPERPIXEL=24 EXTRADEFINES=$(EXTRADEFINES)
 ifeq ($(CONFIG_NX_RAMBACKED),y)
 	$(Q) $(MAKE) -C nxglib -f Makefile.pwfb TOPDIR=$(TOPDIR) NXGLIB_BITSPERPIXEL=24 EXTRADEFINES=$(EXTRADEFINES)
 endif
+ifeq ($(CONFIG_NX_SWCURSOR),y)
+	$(Q) $(MAKE) -C nxglib -f Makefile.cursor TOPDIR=$(TOPDIR) NXGLIB_BITSPERPIXEL=24 EXTRADEFINES=$(EXTRADEFINES)
+endif
 
 gen32bppsources:
 	$(Q) $(MAKE) -C nxglib -f Makefile.devblit TOPDIR=$(TOPDIR) NXGLIB_BITSPERPIXEL=32 EXTRADEFINES=$(EXTRADEFINES)
 ifeq ($(CONFIG_NX_RAMBACKED),y)
 	$(Q) $(MAKE) -C nxglib -f Makefile.pwfb TOPDIR=$(TOPDIR) NXGLIB_BITSPERPIXEL=32 EXTRADEFINES=$(EXTRADEFINES)
 endif
+ifeq ($(CONFIG_NX_SWCURSOR),y)
+	$(Q) $(MAKE) -C nxglib -f Makefile.cursor TOPDIR=$(TOPDIR) NXGLIB_BITSPERPIXEL=32 EXTRADEFINES=$(EXTRADEFINES)
+endif
 
 gensources: gen1bppsources gen2bppsource gen4bppsource gen8bppsource gen16bppsource gen24bppsource gen32bppsources
 
@@ -130,14 +143,15 @@ context: gensources
 clean:
 	$(Q) $(MAKE) -C nxglib -f Makefile.devblit clean TOPDIR=$(TOPDIR) EXTRADEFINES=$(EXTRADEFINES)
 	$(Q) $(MAKE) -C nxglib -f Makefile.pwfb clean TOPDIR=$(TOPDIR) EXTRADEFINES=$(EXTRADEFINES)
+	$(Q) $(MAKE) -C nxglib -f Makefile.cursor clean TOPDIR=$(TOPDIR) EXTRADEFINES=$(EXTRADEFINES)
 	$(call DELFILE, $(BIN))
 	$(call CLEAN)
 
 distclean: clean
 	$(Q) $(MAKE) -C nxglib -f Makefile.devblit distclean TOPDIR=$(TOPDIR) EXTRADEFINES=$(EXTRADEFINES)
 	$(Q) $(MAKE) -C nxglib -f Makefile.pwfb distclean TOPDIR=$(TOPDIR) EXTRADEFINES=$(EXTRADEFINES)
+	$(Q) $(MAKE) -C nxglib -f Makefile.cursor distclean TOPDIR=$(TOPDIR) EXTRADEFINES=$(EXTRADEFINES)
 	$(call DELFILE, Make.dep)
 	$(call DELFILE, .depend)
 
 -include Make.dep
-
diff --git a/graphics/nxbe/Make.defs b/graphics/nxbe/Make.defs
index ee57af88348..fb3efd413b2 100644
--- a/graphics/nxbe/Make.defs
+++ b/graphics/nxbe/Make.defs
@@ -37,16 +37,16 @@ CSRCS += nxbe_bitmap.c nxbe_configure.c nxbe_colormap.c nxbe_clipper.c
 CSRCS += nxbe_closewindow.c nxbe_redraw.c nxbe_redrawbelow.c
 CSRCS += nxbe_setposition.c nxbe_move.c nxbe_getrectangle.c
 CSRCS += nxbe_fill.c nxbe_filltrapezoid.c nxbe_setpixel.c
-CSRCS += nxbe_lower.c nxbe_raise.c nxbe_modal.c
-CSRCS += nxbe_setsize.c nxbe_visible.c
+CSRCS += nxbe_lower.c nxbe_raise.c nxbe_modal.c nxbe_isvisible.c
+CSRCS += nxbe_setsize.c nxbe_setvisibility.c
 
 ifeq ($(CONFIG_NX_RAMBACKED),y)
 CSRCS += nxbe_flush.c
 endif
 
-ifeq ($(CONFIG_NX_HWCURSOR),y)
-CSRCS += nxbe_cursor.c
-else ifeq ($(CONFIG_NX_SWCURSOR),y)
+ifeq ($(CONFIG_NX_SWCURSOR),y)
+CSRCS += nxbe_cursor.c nxbe_cursor_backupdraw.c
+else ifeq ($(CONFIG_NX_HWCURSOR),y)
 CSRCS += nxbe_cursor.c
 endif
 
diff --git a/graphics/nxbe/nxbe.h b/graphics/nxbe/nxbe.h
index 8e5476be09b..a7dc1e88e26 100644
--- a/graphics/nxbe/nxbe.h
+++ b/graphics/nxbe/nxbe.h
@@ -48,6 +48,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 /****************************************************************************
@@ -64,7 +65,7 @@
 
 /* Server flags and helper macros:
  *
- * NXBE_STATE_MODAL     - One window is in a focused, modal state
+ * NXBE_STATE_MODAL  - One window is in a focused, modal state
  */
 
 #define NXBE_STATE_MODAL     (1 << 0) /* Bit 0: One window is in a focused,
@@ -146,20 +147,46 @@ struct nxbe_pwfb_vtable_s
 };
 #endif
 
+#ifdef CONFIG_NX_SWCURSOR
+/* A vtable of raster operation function pointers.  The types of the
+ * function points must match the cursor rasterizer types exported by
+ * nxglib.
+ */
+
+struct nxbe_cursorops_s
+{
+  CODE void (*draw)(FAR struct nxbe_state_s *be,
+                    FAR const struct nxgl_rect_s *bounds,
+                    int planeno);
+  CODE void (*erase)(FAR struct nxbe_state_s *be,
+                     FAR const struct nxgl_rect_s *bounds,
+                     int planeno);
+  CODE void (*backup)(FAR struct nxbe_state_s *be,
+                      FAR const struct nxgl_rect_s *bounds,
+                      int planeno);
+};
+#endif
+
 /* Encapsulates everything needed support window rasterization commands. */
 
 struct nxbe_plane_s
 {
-  /* Raster device operation callbacks */
+  /* Raster device operations */
 
   struct nxbe_dev_vtable_s dev;
 
 #ifdef CONFIG_NX_RAMBACKED
-  /* Raster per-window framebuffer operation callbacks */
+  /* Raster per-window framebuffer operations */
 
   struct nxbe_pwfb_vtable_s pwfb;
 #endif
 
+#ifdef CONFIG_NX_SWCURSOR
+  /* Cursor device operations */
+
+  struct nxbe_cursorops_s cursor;
+#endif
+
   /* Framebuffer plane info describing destination video plane */
 
   NX_PLANEINFOTYPE pinfo;
@@ -173,15 +200,39 @@ struct nxbe_plane_s
 
 struct nxbe_clipops_s
 {
-  void (*visible)(FAR struct nxbe_clipops_s *cops,
-                  FAR struct nxbe_plane_s *plane,
-                  FAR const struct nxgl_rect_s *rect);
+  CODE void (*visible)(FAR struct nxbe_clipops_s *cops,
+                       FAR struct nxbe_plane_s *plane,
+                       FAR const struct nxgl_rect_s *rect);
 
-  void (*obscured)(FAR struct nxbe_clipops_s *cops,
-                   FAR struct nxbe_plane_s *plane,
-                   FAR const struct nxgl_rect_s *rect);
+  CODE void (*obscured)(FAR struct nxbe_clipops_s *cops,
+                        FAR struct nxbe_plane_s *plane,
+                        FAR const struct nxgl_rect_s *rect);
 };
 
+/* Cursor *******************************************************************/
+
+/* Cursor state structure */
+
+#if defined(CONFIG_NX_SWCURSOR)
+struct nxbe_cursor_s
+{
+  bool visible;                    /* True: the cursor is visible */
+  struct nxgl_rect_s bounds;       /* Cursor image bounding box */
+  nxgl_mxpixel_t color1[CONFIG_NX_NPLANES]; /* Color1 is main color of the cursor */
+  nxgl_mxpixel_t color2[CONFIG_NX_NPLANES]; /* Color2 is color of any border */
+  nxgl_mxpixel_t color3[CONFIG_NX_NPLANES]; /* Color3 is the blended color */
+  size_t allocsize;                /* Size of the background allocation */
+  FAR const uint8_t *image;        /* Cursor image at 2-bits/pixel */
+  FAR nxgl_mxpixel_t *bkgd;        /* Cursor background in device pixels */
+};
+#elif defined(CONFIG_NX_HWCURSOR)
+struct nxbe_cursor_s
+{
+  bool visible;                    /* True: the cursor is visible */
+  struct nxgl_point_s pos;         /* The current cursor position */
+};
+#endif
+
 /* Back-end state ***********************************************************/
 
 /* This structure describes the overall back-end window state */
@@ -193,14 +244,7 @@ struct nxbe_state_s
 #if defined(CONFIG_NX_SWCURSOR) || defined(CONFIG_NX_HWCURSOR)
   /* Cursor support */
 
-  struct
-  {
-    bool visible;                    /* True: the cursor is visible */
-    struct cursor_pos_s pos;         /* The current cursor position */
-#ifdef CONFIG_NX_SWCURSOR
-    FAR struct cursor_image_s image; /* Cursor image */
-#endif
-  } cursor;
+  struct nxbe_cursor_s cursor;       /* Cursor support */
 #endif
 
   /* The window list (with the background window always at the bottom) */
@@ -291,11 +335,17 @@ void nxbe_cursor_enable(FAR struct nxbe_state_s *be, bool enable);
  * Description:
  *   Set the cursor image
  *
+ *   The image is provided a a 2-bits-per-pixel image.  The two bit incoding
+ *   is as followings:
+ *
+ *   00 - The transparent background
+ *   01 - Color1:  The main color of the cursor
+ *   10 - Color2:  The color of any border
+ *   11 - Color3:  A blend color for better imaging (fake anti-aliasing).
+ *
  * Input Parameters:
  *   be  - The back-end state structure instance
- *   image - Describes the cursor image in the expected format.  For a
- *           software cursor, this is the format used with the display.  The
- *           format may be different if a hardware cursor is used.
+ *   image - Describes the cursor image in the expected format.
  *
  * Returned Value:
  *   None
@@ -304,11 +354,11 @@ void nxbe_cursor_enable(FAR struct nxbe_state_s *be, bool enable);
 
 #if defined(CONFIG_NX_HWCURSORIMAGE) || defined(CONFIG_NX_SWCURSOR)
 void nxbe_cursor_setimage(FAR struct nxbe_state_s *be,
-                          FAR struct cursor_image_s *image);
+                          FAR struct nx_cursorimage_s *image);
 #endif
 
 /****************************************************************************
- * Name: nxcursor_setposition
+ * Name: nxbe_cursor_setposition
  *
  * Description:
  *   Move the cursor to the specified position
@@ -322,10 +372,63 @@ void nxbe_cursor_setimage(FAR struct nxbe_state_s *be,
  *
  ****************************************************************************/
 
-void nxcursor_setposition(FAR struct nxbe_state_s *be,
-                          FAR const struct cursor_pos_s *pos);
+void nxbe_cursor_setposition(FAR struct nxbe_state_s *be,
+                             FAR const struct nxgl_point_s *pos);
+
 #endif /* CONFIG_NX_SWCURSOR || CONFIG_NX_HWCURSOR */
 
+#ifdef CONFIG_NX_SWCURSOR
+/****************************************************************************
+ * Name: nxbe_cursor_backupdraw and nxbe_cursor_backupdraw_dev
+ *
+ * Description:
+ *   Called after any modification to the display (in window coordinate
+ *   frame) to perform the backup-draw operation on one color plane.
+ *
+ * Input Parameters:
+ *   be    - The back-end state structure instance, or
+ *   wnd   - Window state structure
+ *   rect  - The modified region of the window.  In windows coordinates for
+ *           nxbe_cursor_backupdraw(); in graphics device corrdinates for
+ *           nxbe_cursor_backupdraw_dev().
+ *   plane - The plane number to use.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void nxbe_cursor_backupdraw(FAR struct nxbe_window_s *wnd,
+                            FAR const struct nxgl_rect_s *rect, int plane);
+void nxbe_cursor_backupdraw_dev(FAR struct nxbe_state_s *be,
+                                FAR const struct nxgl_rect_s *rect,
+                                int plane);
+
+/****************************************************************************
+ * Name: nxbe_cursor_backupdraw_all and nxbe_cursor_backupdraw_devall
+ *
+ * Description:
+ *   Called after any modification to the display to perform the backup-draw
+ *   operation on all color planes.
+ *
+ * Input Parameters:
+ *   be    - The back-end state structure instance, or
+ *   wnd   - Window state structure
+ *   rect  - The modified region of the window.  In windows coordinates for
+ *           nxbe_cursor_backupdraw(); in graphics device corrdinates for
+ *           nxbe_cursor_backupdraw_dev().
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void nxbe_cursor_backupdraw_all(FAR struct nxbe_window_s *wnd,
+                                FAR const struct nxgl_rect_s *rect);
+void nxbe_cursor_backupdraw_devall(FAR struct nxbe_state_s *be,
+                                   FAR const struct nxgl_rect_s *rect);
+#endif /*  */
+
 /****************************************************************************
  * Name: nxbe_closewindow
  *
@@ -397,6 +500,25 @@ void nxbe_lower(FAR struct nxbe_window_s *wnd);
 
 void nxbe_modal(FAR struct nxbe_window_s *wnd, bool enable);
 
+/****************************************************************************
+ * Name: nxbe_setvisibility
+ *
+ * Description:
+ *   Select if the window is visible or hidden.  A hidden window is still
+ *   present will will update normally, but will be on the visiable on the
+ *   display until it is unhidden.
+ *
+ * Input Parameters:
+ *   wnd  - The window to be modified
+ *   hide - True: Window will be hidden; false: Window will be visible
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void nxbe_setvisibility(FAR struct nxbe_window_s *wnd, bool hide);
+
 /****************************************************************************
  * Name: nxbe_setpixel
  *
@@ -517,7 +639,7 @@ void nxbe_move(FAR struct nxbe_window_s *wnd,
  * Input Parameters:
  *   wnd    - The window that will receive the bitmap image
  *   dest   - Describes the rectangular region on the display that will
- *            receive the the bit map.
+ *            receive the the bit map (window coordinate frame).
  *   src    - The start of the source image.
  *   origin - The origin of the upper, left-most corner of the full bitmap.
  *            Both dest and origin are in window coordinates, however, origin
@@ -548,7 +670,7 @@ void nxbe_bitmap_dev(FAR struct nxbe_window_s *wnd,
  * Input Parameters:
  *   wnd    - The window that will receive the bitmap image
  *   dest   - Describes the rectangular region on the display that will
- *            receive the the bit map.
+ *            receive the the bit map (window coordinate frame).
  *   src    - The start of the source image.
  *   origin - The origin of the upper, left-most corner of the full bitmap.
  *            Both dest and origin are in window coordinates, however, origin
@@ -566,33 +688,6 @@ void nxbe_bitmap(FAR struct nxbe_window_s *wnd,
                  FAR const struct nxgl_point_s *origin,
                  unsigned int stride);
 
-/****************************************************************************
- * Name: nxbe_sprite_refresh
- *
- * Description:
- *   Prior to calling nxbe_bitmap_dev(), update any "sprites" tht need to
- *   be overlaid on the per-window frambuffer.  This could include such
- *   things as OSD functionality, a software cursor, selection boxes, etc.
- *
- * Input Parameters (same as for nxbe_bitmap_dev):
- *   wnd    - The window that will receive the bitmap image
- *   dest   - Describes the rectangular region on the display that was
- *            modified (in device coordinates)
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#ifdef CONFIG_NX_RAMBACKED
-#if 0 /* There are none yet */
-void nxbe_sprite_refresh(FAR struct nxbe_window_s *wnd,
-                         FAR const struct nxgl_rect_s *dest);
-#else
-#  define nxbe_sprite_refresh(wnd, dest)
-#endif
-#endif
-
 /****************************************************************************
  * Name: nxbe_flush
  *
@@ -601,23 +696,22 @@ void nxbe_sprite_refresh(FAR struct nxbe_window_s *wnd,
  *   be written to device graphics memory.  That function is managed by this
  *   simple function.  It does the following:
  *
- *   1) It calls nxbe_sprite_refresh() to update any "sprite" graphics on top
- *      of the RAM framebuffer.   This could include such things as OSD
- *      functionality, a software cursor, selection boxes, etc.
- *   2) Then it calls nxbe_bitmap_dev() to copy the modified per-window
- *      frambuffer into device memory.
- *
- *   This the "sprite" image is always on top of the device display, this
- *   supports flicker-free software sprites.
+ *   1) It calls nxbe_bitmap_dev() to copy the modified per-window
+ *      framebuffer into device graphics memory.
+ *   2) If CONFIG_NX_SWCURSOR is enabled, it calls the cursor "draw"
+ *      renderer to update re-draw the currsor image if any portion of
+ *      graphics display update overwrote the cursor.  Since these
+ *      operations are performed back-to-back, any resulting flicker
+ *      should be minimized.
  *
  * Input Parameters (same as for nxbe_bitmap_dev):
  *   wnd    - The window that will receive the bitmap image
- *   dest   - Describes the rectangular region on the display that will
- *            receive the the bit map.
+ *   dest   - Describes the rectangular region in the window that will
+ *            receive the the bit map (window coordinate frame).
  *   src    - The start of the source image.
  *   origin - The origin of the upper, left-most corner of the full bitmap.
- *            Both dest and origin are in window coordinates, however, origin
- *            may lie outside of the display.
+ *            Both dest and origin are in window coordinates, however,
+ *            origin may lie outside of the display.
  *   stride - The width of the full source image in bytes.
  *
  * Returned Value:
@@ -662,7 +756,7 @@ void nxbe_redrawbelow(FAR struct nxbe_state_s *be,
                       FAR const struct nxgl_rect_s *rect);
 
 /****************************************************************************
- * Name: nxbe_visible
+ * Name: nxbe_isvisible
  *
  * Description:
  *   Return true if the point, pt, in window wnd is visible.  pt is in
@@ -670,8 +764,8 @@ void nxbe_redrawbelow(FAR struct nxbe_state_s *be,
  *
  ****************************************************************************/
 
-bool nxbe_visible(FAR struct nxbe_window_s *wnd,
-                  FAR const struct nxgl_point_s *pos);
+bool nxbe_isvisible(FAR struct nxbe_window_s *wnd,
+                    FAR const struct nxgl_point_s *pos);
 
 /****************************************************************************
  * Name: nxbe_clipper
diff --git a/graphics/nxbe/nxbe_bitmap.c b/graphics/nxbe/nxbe_bitmap.c
index 3029723a0f9..b93899e5f71 100644
--- a/graphics/nxbe/nxbe_bitmap.c
+++ b/graphics/nxbe/nxbe_bitmap.c
@@ -100,7 +100,7 @@ static void bitmap_clipcopy(FAR struct nxbe_clipops_s *cops,
  * Input Parameters:
  *   wnd   - The window that will receive the bitmap image
  *   dest   - Describes the rectangular on the display that will receive the
- *            the bit map.
+ *            the bit map (window coordinate frame).
  *   src    - The start of the source image.
  *   origin - The origin of the upper, left-most corner of the full bitmap.
  *            Both dest and origin are in window coordinates, however, origin
@@ -193,7 +193,7 @@ static inline void nxbe_bitmap_pwfb(FAR struct nxbe_window_s *wnd,
  * Input Parameters:
  *   wnd    - The window that will receive the bitmap image
  *   dest   - Describes the rectangular region on the display that will
- *            receive the the bit map.
+ *            receive the the bit map (window coordinate frame).
  *   src    - The start of the source image.
  *   origin - The origin of the upper, left-most corner of the full bitmap.
  *            Both dest and origin are in window coordinates, however, origin
@@ -221,6 +221,13 @@ void nxbe_bitmap_dev(FAR struct nxbe_window_s *wnd,
   DEBUGASSERT(wnd != NULL && dest != NULL && src != NULL && origin != NULL);
   DEBUGASSERT(wnd->be != NULL && wnd->be->plane != NULL);
 
+  /* Don't update hidden windows */
+
+  if (NXBE_ISHIDDEN(wnd))
+    {
+      return;
+    }
+
   /* Verify that the destination rectangle begins "below" and to the "right"
    * of the origin
    */
@@ -293,7 +300,7 @@ void nxbe_bitmap_dev(FAR struct nxbe_window_s *wnd,
  * Input Parameters:
  *   wnd    - The window that will receive the bitmap image
  *   dest   - Describes the rectangular region on the display that will
- *            receive the the bit map.
+ *            receive the the bit map (window coordinate frame).
  *   src    - The start of the source image.
  *   origin - The origin of the upper, left-most corner of the full bitmap.
  *            Both dest and origin are in window coordinates, however, origin
@@ -321,14 +328,23 @@ void nxbe_bitmap(FAR struct nxbe_window_s *wnd,
       /* Update the per-window framebuffer */
 
       nxbe_bitmap_pwfb(wnd, dest, src, origin, stride);
-
-      /* Overlay any update any sprites on the per-window frambuffer */
-
-      nxbe_sprite_refresh(wnd, dest);
     }
 #endif
 
-  /* Rend the bitmap directly to the graphics device in any case */
+  /* Don't update hidden windows */
 
-  nxbe_bitmap_dev(wnd, dest, src, origin, stride);
+  if (!NXBE_ISHIDDEN(wnd))
+    {
+      /* Rend the bitmap directly to the graphics device */
+
+      nxbe_bitmap_dev(wnd, dest, src, origin, stride);
+
+#ifdef CONFIG_NX_SWCURSOR
+      /* Update cursor backup memory and redraw the cursor in the modified window
+       * region.
+       */
+
+      nxbe_cursor_backupdraw_all(wnd, dest);
+#endif
+    }
 }
diff --git a/graphics/nxbe/nxbe_closewindow.c b/graphics/nxbe/nxbe_closewindow.c
index b05bd003761..4648b958a5b 100644
--- a/graphics/nxbe/nxbe_closewindow.c
+++ b/graphics/nxbe/nxbe_closewindow.c
@@ -89,7 +89,7 @@ void nxbe_closewindow(FAR struct nxbe_window_s *wnd)
        * indicate the modal state.
        */
 
-      DEBUGASSERT(wnd->above == NULL & NXBE_STATE_ISMODAL(be));
+      DEBUGASSERT(wnd->above == NULL && NXBE_STATE_ISMODAL(be));
 
       /* Leave the modal state */
 
@@ -97,36 +97,41 @@ void nxbe_closewindow(FAR struct nxbe_window_s *wnd)
       NXBE_STATE_CLRMODAL(be);
     }
 
-  /* Is there a window above the one being closed? */
+  /* A hidden window does not exist in the hiearchy */
 
-  if (wnd->above != NULL)
+  if (!NXBE_ISHIDDEN(wnd))
     {
-      /* Yes, now the window below that one is the window below
-       * the one being closed.
+      /* Is there a window above the one being closed? */
+
+      if (wnd->above != NULL)
+        {
+          /* Yes, now the window below that one is the window below
+           * the one being closed.
+           */
+
+          wnd->above->below = wnd->below;
+        }
+      else
+        {
+          /* No, then the top window is the one below this (which
+           * can never be NULL because the background window is
+           * always at the true bottom of the list
+           */
+
+          be->topwnd = wnd->below;
+        }
+
+      /* There is always a window below the one being closed (because
+       * the background is never closed.  Now, the window above that
+       * is the window above the one that is being closed.
        */
 
-      wnd->above->below = wnd->below;
+      wnd->below->above = wnd->above;
+
+      /* Redraw the windows that were below us (and may now be exposed) */
+
+      nxbe_redrawbelow(be, wnd->below, &wnd->bounds);
     }
-  else
-    {
-      /* No, then the top window is the one below this (which
-       * can never be NULL because the background window is
-       * always at the true bottom of the list
-       */
-
-      be->topwnd = wnd->below;
-    }
-
-  /* There is always a window below the one being closed (because
-   * the background is never closed.  Now, the window above that
-   * is the window above the one that is being closed.
-   */
-
-  wnd->below->above = wnd->above;
-
-  /* Redraw the windows that were below us (and may now be exposed) */
-
-  nxbe_redrawbelow(be, wnd->below, &wnd->bounds);
 
 #ifdef CONFIG_NX_RAMBACKED
   /* Free any allocated, per-window framebuffer */
diff --git a/graphics/nxbe/nxbe_configure.c b/graphics/nxbe/nxbe_configure.c
index 0eff716788e..5178e817621 100644
--- a/graphics/nxbe/nxbe_configure.c
+++ b/graphics/nxbe/nxbe_configure.c
@@ -43,6 +43,7 @@
 #include 
 #include 
 
+#include "nxglib.h"
 #include "nxbe.h"
 
 /****************************************************************************
@@ -212,6 +213,12 @@ int nxbe_configure(FAR NX_DRIVERTYPE *dev, FAR struct nxbe_state_s *be)
           be->plane[i].pwfb.moverectangle = pwfb_moverectangle_8bpp;
           be->plane[i].pwfb.copyrectangle = pwfb_copyrectangle_8bpp;
 #endif
+
+#ifdef CONFIG_NX_SWCURSOR
+          be->plane[i].cursor.draw        = nxglib_cursor_draw_8bpp;
+          be->plane[i].cursor.erase       = nxglib_cursor_erase_8bpp;
+          be->plane[i].cursor.backup      = nxglib_cursor_backup_8bpp;
+#endif
         }
       else
 #endif
@@ -233,6 +240,12 @@ int nxbe_configure(FAR NX_DRIVERTYPE *dev, FAR struct nxbe_state_s *be)
           be->plane[i].pwfb.moverectangle = pwfb_moverectangle_16bpp;
           be->plane[i].pwfb.copyrectangle = pwfb_copyrectangle_16bpp;
 #endif
+
+#ifdef CONFIG_NX_SWCURSOR
+          be->plane[i].cursor.draw        = nxglib_cursor_draw_16bpp;
+          be->plane[i].cursor.erase       = nxglib_cursor_erase_16bpp;
+          be->plane[i].cursor.backup      = nxglib_cursor_backup_16bpp;
+#endif
         }
       else
 #endif
@@ -254,6 +267,12 @@ int nxbe_configure(FAR NX_DRIVERTYPE *dev, FAR struct nxbe_state_s *be)
           be->plane[i].pwfb.moverectangle = pwfb_moverectangle_24bpp;
           be->plane[i].pwfb.copyrectangle = pwfb_copyrectangle_24bpp;
 #endif
+
+#ifdef CONFIG_NX_SWCURSOR
+          be->plane[i].cursor.draw        = nxglib_cursor_draw_24bpp;
+          be->plane[i].cursor.erase       = nxglib_cursor_erase_24bpp;
+          be->plane[i].cursor.backup      = nxglib_cursor_backup_24bpp;
+#endif
         }
       else
 #endif
@@ -275,6 +294,12 @@ int nxbe_configure(FAR NX_DRIVERTYPE *dev, FAR struct nxbe_state_s *be)
           be->plane[i].pwfb.moverectangle = pwfb_moverectangle_32bpp;
           be->plane[i].pwfb.copyrectangle = pwfb_copyrectangle_32bpp;
 #endif
+
+#ifdef CONFIG_NX_SWCURSOR
+          be->plane[i].cursor.draw        = nxglib_cursor_draw_32bpp;
+          be->plane[i].cursor.erase       = nxglib_cursor_erase_32bpp;
+          be->plane[i].cursor.backup      = nxglib_cursor_backup_32bpp;
+#endif
         }
       else
 #endif
diff --git a/graphics/nxbe/nxbe_cursor.c b/graphics/nxbe/nxbe_cursor.c
index 0b201c845b7..9e3b667a36c 100644
--- a/graphics/nxbe/nxbe_cursor.c
+++ b/graphics/nxbe/nxbe_cursor.c
@@ -41,13 +41,17 @@
 
 #include 
 
+#include 
+
+#include "nxglib.h"
 #include "nxbe.h"
 
+#if defined(CONFIG_NX_SWCURSOR) || defined(CONFIG_NX_HWCURSOR)
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
 
-#if defined(CONFIG_NX_SWCURSOR) || defined(CONFIG_NX_HWCURSOR)
 /****************************************************************************
  * Name: nxbe_cursor_enable
  *
@@ -65,20 +69,109 @@
 
 void nxbe_cursor_enable(FAR struct nxbe_state_s *be, bool enable)
 {
-#warning Missing logic
+  /* Are we enabling the cursor?  Don't allow the cursor to be enabled if no
+   * image has been assigned to the cursor.
+   */
+
+  ginfo("enable=%d visible=%u\n", enable, be->cursor.visible);
+
+  if (enable && !be->cursor.visible)
+    {
+#ifdef CONFIG_NX_SWCURSOR
+      /* Don't allow the cursor to be enabled if no image has been assigned
+       * to the cursor
+       */
+
+      if (be->cursor.image != NULL)
+        {
+          struct nxgl_rect_s bounds;
+
+          DEBUGASSERT(be->cursor.bkgd != NULL);
+
+          /* Handle the case where some or all of the cursor is off the
+           * display.
+           */
+
+          nxgl_rectintersect(&bounds, &be->cursor.bounds, &be->bkgd.bounds);
+          if (!nxgl_nullrect(&bounds))
+            {
+              /* Save the cursor background image */
+
+              be->plane[0].cursor.backup(be, &bounds, 0);
+
+              /* Write the new cursor image to device memory */
+
+              be->plane[0].cursor.draw(be, &bounds, 0);
+            }
+
+          /* Mark the cursor visible */
+
+          be->cursor.visible = true;
+        }
+#else
+      /* Mark the cursor visible */
+
+      be->cursor.visible = true;
+
+      /* For a hardware cursor, this would require some interaction with the
+       * grahics device.
+       */
+
+#  error Missing logic
+#endif
+    }
+
+  /* Are we disabling the cursor ? */
+
+  else if (!enable && be->cursor.visible)
+    {
+      struct nxgl_rect_s bounds;
+
+      /* Mark the cursor not visible */
+
+      be->cursor.visible = false;
+
+#ifdef CONFIG_NX_SWCURSOR
+      DEBUGASSERT(be->cursor.bkgd != NULL);
+
+      /* Handle the case where some or all of the cursor is off the display. */
+
+      nxgl_rectintersect(&bounds, &be->cursor.bounds, &be->bkgd.bounds);
+      if (!nxgl_nullrect(&bounds))
+        {
+          /* Erase the old cursor image by writing the saved background
+           * image.
+           */
+
+          be->plane[0].cursor.erase(be, &bounds, 0);
+        }
+#else
+      /* For a hardware cursor, this would require some interaction with the
+       * grahics device.
+       */
+
+#  error Missing logic
+#endif
+    }
 }
 
 /****************************************************************************
  * Name: nxbe_cursor_setimage
  *
  * Description:
- *   Set the cursor image
+ *   Set the cursor image.
+ *
+ *   The image is provided a a 2-bits-per-pixel image.  The two bit encoding
+ *   is as follows:
+ *
+ *   00 - The transparent background
+ *   01 - Color1:  The main color of the cursor
+ *   10 - Color2:  The color of any border
+ *   11 - Color3:  A blend color for better imaging (fake anti-aliasing).
  *
  * Input Parameters:
- *   be  - The back-end state structure instance
- *   image - Describes the cursor image in the expected format.  For a
- *           software cursor, this is the format used with the display.  The
- *           format may be different if a hardware cursor is used.
+ *   be    - The back-end state structure instance
+ *   image - Describes the cursor image in the expected format.
  *
  * Returned Value:
  *   None
@@ -87,14 +180,120 @@ void nxbe_cursor_enable(FAR struct nxbe_state_s *be, bool enable)
 
 #if defined(CONFIG_NX_HWCURSORIMAGE) || defined(CONFIG_NX_SWCURSOR)
 void nxbe_cursor_setimage(FAR struct nxbe_state_s *be,
-                          FAR struct cursor_image_s *image);
+                          FAR struct nx_cursorimage_s *image)
 {
-#warning Missing logic
+#ifdef CONFIG_NX_SWCURSOR
+  struct nxgl_size_s oldsize;
+  struct nxgl_rect_s bounds;
+  size_t allocsize;
+  unsigned int bpp;
+
+  ginfo("image=%p\n", image);
+
+  /* If the cursor is visible, then we need to erase the old cursor from the
+   * device graphics memory.
+   */
+
+  if (be->cursor.visible)
+    {
+      /* Handle the case where some or all of the cursor is off the display. */
+
+      nxgl_rectintersect(&bounds, &be->cursor.bounds, &be->bkgd.bounds);
+      if (!nxgl_nullrect(&bounds))
+        {
+          /* Erase the old cursor image by writing the saved background
+           * image.
+           */
+
+          DEBUGASSERT(be->cursor.bkgd != NULL);
+          be->plane[0].cursor.erase(be, &bounds, 0);
+        }
+    }
+
+  /* Has the cursor changed size? */
+
+  oldsize.w = be->cursor.bounds.pt2.x - be->cursor.bounds.pt2.y + 1;
+  oldsize.h = be->cursor.bounds.pt2.y - be->cursor.bounds.pt2.y + 1;
+
+  if (image->size.w != oldsize.w || image->size.h != oldsize.h)
+    {
+      /* Check the size of the allocation we need to hold the backup image. */
+
+      bpp       = be->plane[0].pinfo.bpp;
+      allocsize = (image->size.w * image->size.h * bpp + 7) >> 3;
+
+      /* Reallocate the buffer only if a larger one is needed */
+
+      if (allocsize > be->cursor.allocsize)
+        {
+          FAR void *tmp = kmm_realloc(be->cursor.bkgd, allocsize);
+          if (tmp == NULL)
+            {
+              goto errout_with_erase;
+            }
+
+          /* Save the new allocation information */
+
+          be->cursor.allocsize = allocsize;
+          be->cursor.bkgd      = (FAR nxgl_mxpixel_t *)tmp;
+        }
+
+      /* Calculate the new image bounds.  The position (pt1), does not
+       * change.
+       */
+
+      be->cursor.bounds.pt2.x = be->cursor.bounds.pt1.x + image->size.w - 1;
+      be->cursor.bounds.pt2.y = be->cursor.bounds.pt1.y + image->size.h - 1;
+
+      /* Read in the new background image */
+
+      be->plane[0].cursor.backup(be, &be->cursor.bounds, 0);
+    }
+
+  /* Save the new colors */
+
+  nxgl_colorcopy(be->cursor.color1, image->color1);
+  nxgl_colorcopy(be->cursor.color2, image->color2);
+  nxgl_colorcopy(be->cursor.color3, image->color3);
+
+  /* Save the new image.  This is a reference to an image in user space.
+   * which we assume will persist while we use it.
+   *
+   * REVISIT:  There is an issue in KERNEL build mode. For FLAT and
+   * PROTECTED builds, the cursor image resides in the common application
+   * space and is assumed to pesist as long as needed.  But with the KERNEL
+   * build, the image will lie in a process space and will not be generally
+   * available.  In that case, we could keep the image in a shared memory
+   * region or perhaps copy the image into a kernel internal buffer.
+   * Neither of those are implemented.
+   */
+
+  be->cursor.image = image->image;
+
+errout_with_erase:
+  /* If the cursor is visible, then put write the new cursor image into
+   * device graphics memory now.
+   */
+
+  if (be->cursor.visible)
+    {
+      /* Write the new cursor image to the device graphics memory. */
+
+      be->plane[0].cursor.draw(be, &be->cursor.bounds, 0);
+    }
+
+#else
+  /* For a hardware cursor, this would require some interaction with the
+   * grahics device.
+   */
+
+#  error Missing logic
+#endif
 }
 #endif
 
 /****************************************************************************
- * Name: nxcursor_setposition
+ * Name: nxbe_cursor_setposition
  *
  * Description:
  *   Move the cursor to the specified position
@@ -108,10 +307,65 @@ void nxbe_cursor_setimage(FAR struct nxbe_state_s *be,
  *
  ****************************************************************************/
 
-void nxcursor_setposition(FAR struct nxbe_state_s *be,
-                          FAR const struct cursor_pos_s *pos)
+void nxbe_cursor_setposition(FAR struct nxbe_state_s *be,
+                             FAR const struct nxgl_point_s *pos)
 {
-#warning Missing logic
+#ifdef CONFIG_NX_SWCURSOR
+  nxgl_coord_t dx;
+  nxgl_coord_t dy;
+
+  ginfo("pos=(%d,%d)\n", pos->x, pos->y);
+
+  /* If the cursor is visible, then we need to erase the cursor from the
+   * old position in device graphics memory.
+   */
+
+  if (be->cursor.visible)
+    {
+      /* Erase the old cursor image by writing the saved background image. */
+
+      be->plane[0].cursor.erase(be, &be->cursor.bounds, 0);
+    }
+
+  /* Calculate the cursor movement */
+
+  dx = pos->x - be->cursor.bounds.pt1.x;
+  dy = pos->y - be->cursor.bounds.pt1.y;
+
+  /* Calculate the new image bounds. */
+
+  nxgl_rectoffset(&be->cursor.bounds, &be->cursor.bounds, dx, dy);
+
+  /* If the cursor is visible, then put write the new cursor image into
+   * device graphics memory now.
+   */
+
+  if (be->cursor.visible)
+    {
+      struct nxgl_rect_s bounds;
+
+      /* Handle the case where some or all of the cursor is off the display. */
+
+      nxgl_rectintersect(&bounds, &be->cursor.bounds, &be->bkgd.bounds);
+      if (!nxgl_nullrect(&bounds))
+        {
+          /* Read in the new background image at this offset */
+
+          be->plane[0].cursor.backup(be, &bounds, 0);
+
+          /* Write the new cursor image to the device graphics memory. */
+
+          be->plane[0].cursor.draw(be, &bounds, 0);
+        }
+    }
+
+#else
+  /* For a hardware cursor, this would require some interaction with the
+   * grahics device.
+   */
+
+#  error Missing logic
+#endif
 }
 
 #endif /* CONFIG_NX_SWCURSOR || CONFIG_NX_HWCURSOR */
diff --git a/graphics/nxbe/nxbe_cursor_backupdraw.c b/graphics/nxbe/nxbe_cursor_backupdraw.c
new file mode 100644
index 00000000000..e8dbe4f21f6
--- /dev/null
+++ b/graphics/nxbe/nxbe_cursor_backupdraw.c
@@ -0,0 +1,224 @@
+/****************************************************************************
+ * graphics/nxbe/nxbe_cursor_backupdraw.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include "nxglib.h"
+#include "nxbe.h"
+
+#ifdef CONFIG_NX_SWCURSOR
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _nxbe_cursor_backupdraw_dev
+ *
+ * Description:
+ *   Called after any modification to the display to backup and redraw one
+ *   color plane
+ *
+ * Input Parameters:
+ *   be    - The back-end state structure instance
+ *   rect  - The modified region of the display, in device coordinates
+ *   plane - The plane number to use.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+static inline void _nxbe_cursor_backupdraw_dev(FAR struct nxbe_state_s *be,
+                                               FAR const struct nxgl_rect_s *rect,
+                                               int plane)
+{
+  /* Save the modified cursor background region. */
+
+  be->plane[plane].cursor.backup(be, rect, plane);
+
+  /* Restore the software cursor in the region that was modified. */
+
+  be->plane[plane].cursor.draw(be, rect, plane);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nxbe_cursor_backupdraw
+ *
+ * Description:
+ *   Called after any modification to the display (in window coordinate
+ *   frame) to perform the backup-draw operation on one color plane.
+ *
+ * Input Parameters:
+ *   be    - The back-end state structure instance, or
+ *   wnd   - Window state structure
+ *   rect  - The modified region of the window, in windows coordinates
+ *   plane - The plane number to use.
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void nxbe_cursor_backupdraw_dev(FAR struct nxbe_state_s *be,
+                                FAR const struct nxgl_rect_s *rect,
+                                int plane)
+{
+  struct nxgl_rect_s bounds;
+
+  /* Update the software cursor if it is visible */
+
+  if (be->cursor.visible)
+    {
+      /* Clip to the limits of the display */
+
+      nxgl_rectintersect(&bounds, rect, &be->bkgd.bounds);
+      if (!nxgl_nullrect(&bounds))
+        {
+          _nxbe_cursor_backupdraw_dev(be, &bounds, plane);
+        }
+    }
+}
+
+void nxbe_cursor_backupdraw(FAR struct nxbe_window_s *wnd,
+                            FAR const struct nxgl_rect_s *rect,
+                            int plane)
+{
+  struct nxgl_rect_s bounds;
+
+  /* Update the software cursor if it is visible */
+
+  if (wnd->be->cursor.visible)
+    {
+      /* Offset the rectangle to convert to device coordinates */
+
+      nxgl_rectoffset(&bounds, rect, wnd->bounds.pt1.x, wnd->bounds.pt1.y);
+
+      /* Clip to the limits of the window */
+
+      nxgl_rectintersect(&bounds, &bounds, &wnd->bounds);
+
+      /* Let nxbe_cursor_backupdraw_dev() do the rest */
+
+      nxbe_cursor_backupdraw_dev(wnd->be, &bounds, plane);
+    }
+}
+
+/****************************************************************************
+ * Name: nxbe_cursor_backupdraw_all and nxbe_cursor_backupdraw_devall
+ *
+ * Description:
+ *   Called after any modification to the display to perform the backup-draw
+ *   operation on all color planes.
+ *
+ * Input Parameters:
+ *   be    - The back-end state structure instance, or
+ *   wnd   - Window state structure
+ *   rect  - The modified region of the window.  In windows coordinates for
+ *           nxbe_cursor_backupdraw(); in graphics device corrdinates for
+ *           nxbe_cursor_backupdraw_dev().
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void nxbe_cursor_backupdraw_devall(FAR struct nxbe_state_s *be,
+                                   FAR const struct nxgl_rect_s *rect)
+{
+#if CONFIG_NX_NPLANES > 1
+  struct nxgl_rect_s bounds;
+  int plane;
+
+  /* Update the software cursor if it is visible */
+
+  if (be->cursor.visible)
+    {
+      /* Clip to the limits of the display */
+
+      nxgl_rectintersect(&bounds, &bounds, &be->bkgd.bounds);
+      if (!nxgl_nullrect(&bounds))
+        {
+          /* Perform the backup-draw operation on all color planes */
+
+          for (plane = 0; plane < CONFIG_NX_NPLANES; plane++)
+            {
+              _nxbe_cursor_backupdraw_dev(be, &bounds, plane);
+            }
+        }
+    }
+#else
+  nxbe_cursor_backupdraw_dev(be, rect, 0);
+#endif
+}
+
+void nxbe_cursor_backupdraw_all(FAR struct nxbe_window_s *wnd,
+                                FAR const struct nxgl_rect_s *rect)
+{
+#if CONFIG_NX_NPLANES > 1
+  struct nxgl_rect_s bounds;
+
+  /* Update the software cursor if it is visible */
+
+  if (wnd->be->cursor.visible)
+    {
+      /* Offset the rectangle to convert it to device coordinates */
+
+      nxgl_rectoffset(&bounds, rect, wnd->bounds.pt1.x, wnd->bounds.pt1.y);
+
+      /* Clip to the limits of the window */
+
+      nxgl_rectintersect(&bounds, &bounds, &wnd->bounds);
+
+      /* And then let nxbe_cursor_backupdraw_devall() do the rest */
+
+      nxbe_cursor_backupdraw_all(wnd, &bounds);
+    }
+#else
+  nxbe_cursor_backupdraw(wnd, rect, 0);
+#endif
+}
+
+#endif /* CONFIG_NX_SWCURSOR */
diff --git a/graphics/nxbe/nxbe_fill.c b/graphics/nxbe/nxbe_fill.c
index fb612caf5a7..5cd7566c535 100644
--- a/graphics/nxbe/nxbe_fill.c
+++ b/graphics/nxbe/nxbe_fill.c
@@ -71,8 +71,8 @@ struct nxbe_fill_s
  ****************************************************************************/
 
 static void nxbe_clipfill(FAR struct nxbe_clipops_s *cops,
-                        FAR struct nxbe_plane_s *plane,
-                        FAR const struct nxgl_rect_s *rect)
+                          FAR struct nxbe_plane_s *plane,
+                          FAR const struct nxgl_rect_s *rect)
 {
   struct nxbe_fill_s *fillinfo = (struct nxbe_fill_s *)cops;
 
@@ -119,12 +119,26 @@ static inline void nxbe_fill_dev(FAR struct nxbe_window_s *wnd,
     {
       DEBUGASSERT(wnd->be->plane[i].dev.fillrectangle != NULL);
 
+      /* Fill the visible part of the rectangle */
+
       info.cops.visible  = nxbe_clipfill;
       info.cops.obscured = nxbe_clipnull;
       info.color         = color[i];
 
       nxbe_clipper(wnd->above, rect, NX_CLIPORDER_DEFAULT,
                    &info.cops, &wnd->be->plane[i]);
+
+#ifdef CONFIG_NX_SWCURSOR
+      /* Backup and redraw the cursor in the affected region.
+       *
+       * REVISIT:  This and the following logic belongs in the function
+       * nxbe_clipfill().  It is here only because the struct nxbe_state_s
+       * (wnd->be) is not available at that point.  This may result in an
+       * excessive number of cursor updates.
+       */
+
+      nxbe_cursor_backupdraw_dev(wnd->be, rect, i);
+#endif
     }
 }
 
@@ -223,8 +237,13 @@ void nxbe_fill(FAR struct nxbe_window_s *wnd,
         }
 #endif
 
-      /* Rend the bitmap directly to the graphics device in any case */
+      /* Don't update hidden windows */
 
-      nxbe_fill_dev(wnd, &remaining, color);
+      if (!NXBE_ISHIDDEN(wnd))
+        {
+          /* Rend the bitmap directly to the graphics device */
+
+          nxbe_fill_dev(wnd, &remaining, color);
+        }
     }
 }
diff --git a/graphics/nxbe/nxbe_filltrapezoid.c b/graphics/nxbe/nxbe_filltrapezoid.c
index 8c50058064d..44c68f60b70 100644
--- a/graphics/nxbe/nxbe_filltrapezoid.c
+++ b/graphics/nxbe/nxbe_filltrapezoid.c
@@ -150,9 +150,25 @@ static inline void nxbe_filltrapezoid_dev(FAR struct nxbe_window_s *wnd,
   i = 0;
 #endif
     {
+      /* Rend any part of the trapezoid that is not occluded by a window
+       * higher in the hiearchy.
+       */
+
       info.color = color[i];
       nxbe_clipper(wnd->above, bounds, NX_CLIPORDER_DEFAULT,
                    &info.cops, &wnd->be->plane[i]);
+
+#ifdef CONFIG_NX_SWCURSOR
+      /* Backup and redraw the cursor in the modified region.
+       *
+       * REVISIT:  This and the following logic belongs in the function
+       * nxbe_clipfill().  It is here only because the struct nxbe_state_s
+       * (wnd->be) is not available at that point.  This may result in an
+       * excessive number of cursor updates.
+       */
+
+      nxbe_cursor_backupdraw_dev(wnd->be, bounds, i);
+#endif
     }
 }
 
@@ -324,6 +340,9 @@ void nxbe_filltrapezoid(FAR struct nxbe_window_s *wnd,
         }
       else
 #endif
+      /* Don't update hidden windows */
+
+      if (!NXBE_ISHIDDEN(wnd))
         {
           /* Update only the graphics device memory. */
 
diff --git a/graphics/nxbe/nxbe_flush.c b/graphics/nxbe/nxbe_flush.c
index 45bcea5bea2..e19c6bed94c 100644
--- a/graphics/nxbe/nxbe_flush.c
+++ b/graphics/nxbe/nxbe_flush.c
@@ -53,32 +53,6 @@
  * Public Functions
  ****************************************************************************/
 
-/****************************************************************************
- * Name: nxbe_sprite_refresh
- *
- * Description:
- *   Prior to calling nxbe_bitmap_dev(), update any "sprites" tht need to
- *   be overlaid on the per-window frambuffer.  This could include such
- *   things as OSD functionality, a software cursor, selection boxes, etc.
- *
- * Input Parameters (same as for nxbe_flush):
- *   wnd    - The window that will receive the bitmap image
- *   dest   - Describes the rectangular region on the display that was
- *            modified (in device coordinates)
- *
- * Returned Value:
- *   None
- *
- ****************************************************************************/
-
-#if 0 /* There are none yet */
-void nxbe_sprite_refresh(FAR struct nxbe_window_s *wnd,
-                        FAR const struct nxgl_rect_s *dest)
-{
-  /* Sprite support has not yet been implemented */
-}
-#endif
-
 /****************************************************************************
  * Name: nxbe_flush
  *
@@ -87,19 +61,18 @@ void nxbe_sprite_refresh(FAR struct nxbe_window_s *wnd,
  *   be written to device graphics memory.  That function is managed by this
  *   simple function.  It does the following:
  *
- *   1) It calls nxbe_sprite_refresh() to update any "sprite" graphics on top
- *      of the RAM framebuffer.   This could include such things as OSD
- *      functionality, a software cursor, selection boxes, etc.
- *   2) Then it calls nxbe_bitmap_dev() to copy the modified per-window
- *      frambuffer into device memory.
- *
- *   This the "sprite" image is always on top of the device display, this
- *   supports flicker-free software sprites.
+ *   1) It calls nxbe_bitmap_dev() to copy the modified per-window
+ *      framebuffer into device graphics memory.
+ *   2) If CONFIG_NX_SWCURSOR is enabled, it calls the cursor "draw"
+ *      renderer to update re-draw the currsor image if any portion of
+ *      graphics display update overwrote the cursor.  Since these
+ *      operations are performed back-to-back, any resulting flicker
+ *      should be minimized.
  *
  * Input Parameters (same as for nxbe_flush):
  *   wnd    - The window that will receive the bitmap image
- *   dest   - Describes the rectangular on the display that will receive the
- *            the bit map.
+ *   dest   - Describes the rectangular region in the window that will
+ *            receive the the bit map (window coordinate frame).
  *   src    - The start of the source image.
  *   origin - The origin of the upper, left-most corner of the full bitmap.
  *            Both dest and origin are in window coordinates, however, origin
@@ -117,18 +90,22 @@ void nxbe_flush(FAR struct nxbe_window_s *wnd,
                 FAR const struct nxgl_point_s *origin,
                 unsigned int stride)
 {
-  /* Update any "sprite" graphics on top of the display.  These may have been
-   * damaged by the preceding framebuffer update.
-   */
+  /* Don't update hidden windows */
 
-  nxbe_sprite_refresh(wnd, dest);
+  if (!NXBE_ISHIDDEN(wnd))
+    {
+      /* Copy the modified per-window frambuffer into device memory. */
 
-  /* Copy the modified per-window frambuffer into device memory.  Since the
-   * "sprite" graphics were refreshed after the update, then should be no
-   * flicker as you see with a direct update of the device graphics memory.
-   */
+      nxbe_bitmap_dev(wnd, dest, src, origin, stride);
 
-  nxbe_bitmap_dev(wnd, dest, src, origin, stride);
+#ifdef CONFIG_NX_SWCURSOR
+      /* Update cursor backup memory and redraw the cursor in the modified
+       * window region.
+       */
+
+      nxbe_cursor_backupdraw_all(wnd, dest);
+#endif
+    }
 }
 
 #endif  /* CONFIG_NX_RAMBACKED */
diff --git a/graphics/nxbe/nxbe_getrectangle.c b/graphics/nxbe/nxbe_getrectangle.c
index eeac3081fca..b9f5d06b528 100644
--- a/graphics/nxbe/nxbe_getrectangle.c
+++ b/graphics/nxbe/nxbe_getrectangle.c
@@ -104,7 +104,7 @@ static inline void nxbe_getrectangle_dev(FAR struct nxbe_window_s *wnd,
  *
  * Input Parameters:
  *   wnd  - The window structure reference
- *   rect - The location to be copied
+ *   rect - The location to be copied (in device coordinates, clipped)
  *   plane - Specifies the color plane to get from.
  *   dest - The location to copy the memory region
  *   deststride - The width, in bytes, of the dest memory
@@ -126,8 +126,8 @@ static inline void nxbe_getrectangle_pwfb(FAR struct nxbe_window_s *wnd,
 
   DEBUGASSERT(pplane != NULL && pplane->pwfb.getrectangle != NULL);
 
-  /* The rectangle that we receive here is in abolute device coordinates.  We
-   * need to restore this to windows relative coordinates.
+  /* The rectangle that we receive here is in abolute device coordinates.
+   * We need to restore this to windows relative coordinates.
    */
 
   nxgl_rectoffset(&relrect, rect, -wnd->bounds.pt1.x, -wnd->bounds.pt1.y);
@@ -153,7 +153,7 @@ static inline void nxbe_getrectangle_pwfb(FAR struct nxbe_window_s *wnd,
  *
  * Input Parameters:
  *   wnd  - The window structure reference
- *   rect - The location to be copied
+ *   rect - The location to be copied (in window-relative coordinates)
  *   plane - Specifies the color plane to get from.
  *   dest - The location to copy the memory region
  *   deststride - The width, in bytes, of the dest memory
@@ -174,7 +174,7 @@ void nxbe_getrectangle(FAR struct nxbe_window_s *wnd,
   DEBUGASSERT(plane < wnd->be->vinfo.nplanes);
 
   /* Offset the rectangle by the window origin to convert it into a
-   * bounding box
+   * bounding box in device coordinates
    */
 
   nxgl_rectoffset(&remaining, rect, wnd->bounds.pt1.x, wnd->bounds.pt1.y);
@@ -197,18 +197,47 @@ void nxbe_getrectangle(FAR struct nxbe_window_s *wnd,
 
       if (NXBE_ISRAMBACKED(wnd))
         {
-          nxbe_getrectangle_pwfb(wnd, rect, plane, dest, deststride);
+          nxbe_getrectangle_pwfb(wnd, &remaining, plane, dest, deststride);
         }
       else
 #endif
+      /* If the window is hidden, then there is no available data source */
+
+      if (!NXBE_ISHIDDEN(wnd))
         {
+#ifdef CONFIG_NX_SWCURSOR
+          /* Is the software cursor visible? */
+
+          if (wnd->be->cursor.visible)
+            {
+              /* Erase any portion of the cursor that may be above this
+               * region.
+               * REVISIT:  Only a single color plane is supported
+               */
+
+              wnd->be->plane[0].cursor.erase(wnd->be, &remaining, 0);
+            }
+#endif
           /* Get the rectangle from the graphics device memory.
            * NOTE: Since raw graphic memory is returned, the returned memory
            * content may be the memory of windows above this one and may
            * not necessarily belong to this window.
            */
 
-           nxbe_getrectangle_dev(wnd, rect, plane, dest, deststride);
+           nxbe_getrectangle_dev(wnd, &remaining, plane, dest, deststride);
+
+#ifdef CONFIG_NX_SWCURSOR
+          /* Was the software cursor visible? */
+
+          if (wnd->be->cursor.visible)
+            {
+              /* Restore the software cursor if any part of the cursor was
+               * erased above.
+               */
+
+              wnd->be->plane[0].cursor.draw(wnd->be, &remaining, 0);
+            }
+#endif
         }
     }
 }
diff --git a/graphics/nxbe/nxbe_visible.c b/graphics/nxbe/nxbe_isvisible.c
similarity index 87%
rename from graphics/nxbe/nxbe_visible.c
rename to graphics/nxbe/nxbe_isvisible.c
index 9fc5612f263..5b8ea229849 100644
--- a/graphics/nxbe/nxbe_visible.c
+++ b/graphics/nxbe/nxbe_isvisible.c
@@ -1,7 +1,7 @@
 /****************************************************************************
- * graphics/nxbe/nxbe_redraw.c
+ * graphics/nxbe/nxbe_isvisible.c
  *
- *   Copyright (C) 2008-2009, 2011 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2008-2009, 2011, 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -52,7 +52,7 @@
  * Private Types
  ****************************************************************************/
 
-struct nxbe_visible_s
+struct nxbe_setvisibility_s
 {
   struct nxbe_clipops_s cops;
   bool visible;
@@ -70,7 +70,7 @@ static void nxbe_clipvisible(FAR struct nxbe_clipops_s *cops,
                              FAR struct nxbe_plane_s *plane,
                              FAR const struct nxgl_rect_s *rect)
 {
-  FAR struct nxbe_visible_s *info = (FAR struct nxbe_visible_s *)cops;
+  FAR struct nxbe_setvisibility_s *info = (FAR struct nxbe_setvisibility_s *)cops;
   info->visible = true;
 }
 
@@ -79,7 +79,7 @@ static void nxbe_clipvisible(FAR struct nxbe_clipops_s *cops,
  ****************************************************************************/
 
 /****************************************************************************
- * Name: nxbe_visible
+ * Name: nxbe_isvisible
  *
  * Description:
  *   Return true if the point, pt, in window wnd is visible.  pt is in
@@ -87,10 +87,17 @@ static void nxbe_clipvisible(FAR struct nxbe_clipops_s *cops,
  *
  ****************************************************************************/
 
-bool nxbe_visible(FAR struct nxbe_window_s *wnd,
-                  FAR const struct nxgl_point_s *pos)
+bool nxbe_isvisible(FAR struct nxbe_window_s *wnd,
+                    FAR const struct nxgl_point_s *pos)
 {
-  struct nxbe_visible_s info;
+  struct nxbe_setvisibility_s info;
+
+  /* Hidden windows are never visible */
+
+  if (NXBE_ISHIDDEN(wnd))
+    {
+      return false;
+    }
 
   /* Check if the absolute position lies within the window */
 
@@ -99,7 +106,7 @@ bool nxbe_visible(FAR struct nxbe_window_s *wnd,
       return false;
     }
 
-  /* If this is the top window, then the psition is visible */
+  /* If this is the top window, then the position is visible */
 
   if (!wnd->above)
     {
@@ -120,3 +127,4 @@ bool nxbe_visible(FAR struct nxbe_window_s *wnd,
 
   return info.visible;
 }
+
diff --git a/graphics/nxbe/nxbe_lower.c b/graphics/nxbe/nxbe_lower.c
index 77bbbba4612..8e93ab00612 100644
--- a/graphics/nxbe/nxbe_lower.c
+++ b/graphics/nxbe/nxbe_lower.c
@@ -64,9 +64,12 @@ void nxbe_lower(FAR struct nxbe_window_s *wnd)
 
   /* If the window is already at the bottom, then there is nothing to do.
    * Refuse to lower the background window; Refuse to lower a modal window.
+   * It is impossible to lower a hidden window because it does not exist
+   * in the hiearchy.
    */
 
-  if (wnd->below == NULL || wnd->below == &be->bkgd || NXBE_ISMODAL(wnd))
+  if (wnd->below == NULL || wnd->below == &be->bkgd ||
+      NXBE_ISMODAL(wnd) || NXBE_ISHIDDEN(wnd))
     {
       return;
     }
@@ -95,7 +98,9 @@ void nxbe_lower(FAR struct nxbe_window_s *wnd)
 
   below = wnd->below;
 
-  /* Then put the lowered window at the bottom (just above the background window) */
+  /* Then put the lowered window at the bottom (just above the background
+   * window).
+   */
 
   wnd->below     = &be->bkgd;
   wnd->above     = be->bkgd.above;
diff --git a/graphics/nxbe/nxbe_move.c b/graphics/nxbe/nxbe_move.c
index 292cb9be7d8..7075ddba722 100644
--- a/graphics/nxbe/nxbe_move.c
+++ b/graphics/nxbe/nxbe_move.c
@@ -131,7 +131,7 @@ static void nxbe_clipmoveobscured(FAR struct nxbe_clipops_s *cops,
   struct nxgl_rect_s dst;
 
   nxgl_rectoffset(&dst, rect, info->offset.x, info->offset.y);
-  nxmu_redrawreq(info->wnd, &dst);
+  nxmu_redraw(info->wnd, &dst);
 }
 
 /****************************************************************************
@@ -168,7 +168,7 @@ static void nxbe_clipmovedest(FAR struct nxbe_clipops_s *cops,
     {
       if (!nxgl_nullrect(&nonintersecting[i]))
         {
-          nxmu_redrawreq(dstdata->wnd, &nonintersecting[i]);
+          nxmu_redraw(dstdata->wnd, &nonintersecting[i]);
         }
     }
 
@@ -180,6 +180,8 @@ static void nxbe_clipmovedest(FAR struct nxbe_clipops_s *cops,
     {
       struct nxbe_move_s srcinfo;
 
+      /* Move the visible part of window */
+
       srcinfo.cops.visible  = nxbe_clipmovesrc;
       srcinfo.cops.obscured = nxbe_clipmoveobscured;
       srcinfo.offset        = offset;
@@ -198,7 +200,8 @@ static void nxbe_clipmovedest(FAR struct nxbe_clipops_s *cops,
  *
  * Input Parameters:
  *   wnd    - The window within which the move is to be done
- *   rect   - Describes the rectangular region to move (absolute positions)
+ *   rect   - Describes the rectangular region to move (absolute device
+ *            positions)
  *   offset - The offset to move the region
  *
  * Returned Value:
@@ -211,6 +214,9 @@ static inline void nxbe_move_dev(FAR struct nxbe_window_s *wnd,
                                  FAR const struct nxgl_point_s *offset)
 {
   struct nxbe_move_s info;
+#ifdef CONFIG_NX_SWCURSOR
+  struct nxgl_rect_s dest;
+#endif
   int i;
 
   info.cops.visible  = nxbe_clipmovedest;
@@ -260,6 +266,12 @@ static inline void nxbe_move_dev(FAR struct nxbe_window_s *wnd,
         }
     }
 
+#ifdef CONFIG_NX_SWCURSOR
+  /* Apply the offsets to the source window to get the destination window */
+
+  nxgl_rectoffset(&dest, rect, offset->x, offset->y);
+#endif
+
   /* Then perform the move */
 
 #if CONFIG_NX_NPLANES > 1
@@ -268,8 +280,31 @@ static inline void nxbe_move_dev(FAR struct nxbe_window_s *wnd,
   i = 0;
 #endif
     {
+#ifdef CONFIG_NX_SWCURSOR
+      /* Is the cursor visible? */
+
+      if (wnd->be->cursor.visible)
+        {
+          /* Remove the cursor from the source region */
+
+          wnd->be->plane[i].cursor.erase(wnd->be, rect, i);
+        }
+#endif
+
       nxbe_clipper(wnd->above, &info.srcrect, info.order,
                    &info.cops, &wnd->be->plane[i]);
+
+#ifdef CONFIG_NX_SWCURSOR
+      /* Backup and redraw the cursor in the modified region.
+       *
+       * REVISIT:  This and the following logic belongs in the function
+       * nxbe_clipfill().  It is here only because the struct nxbe_state_s
+       * (wnd->be) is not available at that point.  This may result in an
+       * excessive number of cursor updates.
+       */
+
+      nxbe_cursor_backupdraw_dev(wnd->be, &dest, i);
+#endif
     }
 }
 
@@ -430,6 +465,9 @@ void nxbe_move(FAR struct nxbe_window_s *wnd,
             }
           else
 #endif
+          /* Don't update hidden windows */
+
+          if (!NXBE_ISHIDDEN(wnd))
             {
               /* Update only the graphics device memory. */
 
diff --git a/graphics/nxbe/nxbe_raise.c b/graphics/nxbe/nxbe_raise.c
index f9792e0460d..25e4e3a93da 100644
--- a/graphics/nxbe/nxbe_raise.c
+++ b/graphics/nxbe/nxbe_raise.c
@@ -78,10 +78,10 @@ void nxbe_raise(FAR struct nxbe_window_s *wnd)
 
   /* If this window is already at the top of the display, then do nothing
    * (this covers modal window which must always be at the top).  Don't
-   * raise the background window.
+   * raise the background window and don't raise hidden windows.
    */
 
-  if (wnd->above == NULL || wnd->below == NULL)
+  if (wnd->above == NULL || wnd->below == NULL || NXBE_ISHIDDEN(wnd))
     {
       return;
     }
@@ -110,14 +110,28 @@ void nxbe_raise(FAR struct nxbe_window_s *wnd)
 
   if (NXBE_STATE_ISMODAL(be) && be->topwnd->below != NULL)
     {
+      FAR struct nxbe_window_s *above;
+      FAR struct nxbe_window_s *below;
+
       /* We are in a modal state.  The topwnd is not the background and it
        * has focus.
        */
 
-      wnd->above        = be->topwnd;
-      wnd->below        = be->topwnd->below;
+      above             = be->topwnd;
+      below             = be->topwnd->below;
 
-      be->topwnd->below = wnd;
+      wnd->above        = above;
+      wnd->below        = below;
+
+      above->below      = wnd;
+      below->above      = wnd;
+
+      /* Then redraw this window AND all windows below it. Having moved the
+       * window, we may have exposed previously obscured portions of windows
+       * below this one.
+       */
+
+      nxbe_redrawbelow(be, wnd, &wnd->bounds);
     }
   else
     {
@@ -128,11 +142,11 @@ void nxbe_raise(FAR struct nxbe_window_s *wnd)
 
       be->topwnd->above = wnd;
       be->topwnd        = wnd;
+
+      /* This window is now at the top of the display, we know, therefore,
+       * that it is not obscured by another window
+       */
+
+      nxmu_redraw(wnd, &wnd->bounds);
     }
-
-  /* This window is now at the top of the display, we know, therefore, that
-   * it is not obscured by another window
-   */
-
-  nxmu_redrawreq(wnd, &wnd->bounds);
 }
diff --git a/graphics/nxbe/nxbe_redraw.c b/graphics/nxbe/nxbe_redraw.c
index bc4f400a27f..d8df90b1ca4 100644
--- a/graphics/nxbe/nxbe_redraw.c
+++ b/graphics/nxbe/nxbe_redraw.c
@@ -66,13 +66,13 @@ struct nxbe_redraw_s
  ****************************************************************************/
 
 static void nxbe_clipredraw(FAR struct nxbe_clipops_s *cops,
-                           FAR struct nxbe_plane_s *plane,
-                           FAR const struct nxgl_rect_s *rect)
+                            FAR struct nxbe_plane_s *plane,
+                            FAR const struct nxgl_rect_s *rect)
 {
   FAR struct nxbe_window_s *wnd = ((struct nxbe_redraw_s *)cops)->wnd;
   if (wnd)
     {
-      nxmu_redrawreq(wnd, rect);
+      nxmu_redraw(wnd, rect);
     }
 }
 
diff --git a/graphics/nxbe/nxbe_setpixel.c b/graphics/nxbe/nxbe_setpixel.c
index 24cc2cb49b9..97562b93bcf 100644
--- a/graphics/nxbe/nxbe_setpixel.c
+++ b/graphics/nxbe/nxbe_setpixel.c
@@ -86,10 +86,6 @@ static void nxbe_clipfill(FAR struct nxbe_clipops_s *cops,
 #endif
 }
 
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
 /****************************************************************************
  * Name: nxbe_setpixel
  *
@@ -106,22 +102,20 @@ static void nxbe_clipfill(FAR struct nxbe_clipops_s *cops,
  *
  ****************************************************************************/
 
-void nxbe_setpixel(FAR struct nxbe_window_s *wnd,
-                   FAR const struct nxgl_point_s *pos,
-                   nxgl_mxpixel_t color[CONFIG_NX_NPLANES])
+static void nxbe_setpixel_dev(FAR struct nxbe_window_s *wnd,
+                              FAR const struct nxgl_point_s *pos,
+                              nxgl_mxpixel_t color[CONFIG_NX_NPLANES])
 {
   struct nxbe_setpixel_s info;
   struct nxgl_rect_s rect;
   int i;
 
-  DEBUGASSERT(wnd != NULL && pos != NULL);
-
   /* Offset the position by the window origin */
 
   nxgl_vectoradd(&rect.pt1, pos, &wnd->bounds.pt1);
 
   /* Make sure that the point is within the limits of the window
-   * and of the background screen
+   * and of the background screen.
    */
 
   if (!nxgl_rectinside(&wnd->bounds, &rect.pt1) ||
@@ -147,7 +141,73 @@ void nxbe_setpixel(FAR struct nxbe_window_s *wnd,
       info.cops.obscured = nxbe_clipnull;
       info.color         = color[i];
 
+      /* Draw the point (if it is visible) */
+
       nxbe_clipper(wnd->above, &rect, NX_CLIPORDER_DEFAULT,
                    &info.cops, &wnd->be->plane[i]);
+
+#ifdef CONFIG_NX_SWCURSOR
+      /* Update cursor backup memory and redraw the cursor in the modified
+       * window region.
+       *
+       * REVISIT:  This and the following logic belongs in the function
+       * nxbe_clipfill().  It is here only because the struct
+       * nxbe_state_s (wnd->be) is not available at that point.
+       */
+
+      nxbe_cursor_backupdraw_dev(wnd->be, &rect, i);
+#endif
+    }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nxbe_setpixel
+ *
+ * Description:
+ *  Fill the specified rectangle in the window with the specified color
+ *
+ * Input Parameters:
+ *   wnd  - The window structure reference
+ *   rect - The location to be filled
+ *   col  - The color to use in the fill
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void nxbe_setpixel(FAR struct nxbe_window_s *wnd,
+                   FAR const struct nxgl_point_s *pos,
+                   nxgl_mxpixel_t color[CONFIG_NX_NPLANES])
+{
+  DEBUGASSERT(wnd != NULL && pos != NULL);
+
+#ifdef CONFIG_NX_RAMBACKED
+  /* If this window supports a pre-window frame buffer then shadow the full,
+   * unclipped bitmap in that framebuffer.
+   * REVISIT:  The logic to set a pixel in the per-window frame buffer is missing
+   */
+
+  DEBUGASSERT(!NXBE_ISRAMBACKED(wnd));
+#endif
+
+  /* Don't update hidden windows */
+
+  if (!NXBE_ISHIDDEN(wnd))
+    {
+      nxbe_setpixel_dev(wnd, pos, color);
+
+#ifdef CONFIG_NX_SWCURSOR
+      /* Was the software cursor visible?
+       * REVISIT: Missing logic for the case where the update clobbers a
+       * single pixel in the cursor image
+       */
+
+      DEBUGASSERT(!wnd->be->cursor.visible);
+#endif
     }
 }
diff --git a/graphics/nxbe/nxbe_setposition.c b/graphics/nxbe/nxbe_setposition.c
index c4a4239dbce..7db92e9296b 100644
--- a/graphics/nxbe/nxbe_setposition.c
+++ b/graphics/nxbe/nxbe_setposition.c
@@ -88,7 +88,7 @@ void nxbe_setposition(FAR struct nxbe_window_s *wnd,
   nxmu_reportposition(wnd);
 
   /* Then redraw this window AND all windows below it. Having moved the
-   * window, we may have exposed previoulsy obscured portions of windows
+   * window, we may have exposed previously obscured portions of windows
    * below this one.
    */
 
diff --git a/graphics/nxbe/nxbe_setsize.c b/graphics/nxbe/nxbe_setsize.c
index 295593a398c..4f46fd5edc8 100644
--- a/graphics/nxbe/nxbe_setsize.c
+++ b/graphics/nxbe/nxbe_setsize.c
@@ -64,6 +64,10 @@
 #  define MIN(a,b) ((a < b) ? a : b)
 #endif
 
+#ifndef MAX
+#  define MAX(a,b) ((a > b) ? a : b)
+#endif
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -88,9 +92,11 @@ static void nxbe_realloc(FAR struct nxbe_window_s *wnd,
   FAR nxgl_mxpixel_t *newfb;
   FAR uint8_t *src;
   FAR uint8_t *dest;
+  struct nxgl_rect_s bounds;
   nxgl_coord_t minheight;
   nxgl_coord_t newwidth;
   nxgl_coord_t newheight;
+  nxgl_coord_t oldwidth;
   nxgl_coord_t oldheight;
   nxgl_coord_t row;
   size_t newfbsize;
@@ -112,10 +118,12 @@ static void nxbe_realloc(FAR struct nxbe_window_s *wnd,
 
   if (NXBE_ISRAMBACKED(wnd))
     {
+      oldwidth        = oldbounds->pt2.x - oldbounds->pt1.x + 1;
       oldheight       = oldbounds->pt2.y - oldbounds->pt1.y + 1;
 
       newwidth        = wnd->bounds.pt2.x - wnd->bounds.pt1.x + 1;
       newheight       = wnd->bounds.pt2.y - wnd->bounds.pt1.y + 1;
+
       bpp             = wnd->be->plane[0].pinfo.bpp;
       newstride       = (bpp * newwidth + 7) >> 3;
       newfbsize       = newstride * newheight;
@@ -205,6 +213,42 @@ static void nxbe_realloc(FAR struct nxbe_window_s *wnd,
 #endif
       wnd->stride = newstride;
       wnd->fbmem  = newfb;
+
+      /* If the window became wider, then send a message requesting an update
+       * of the new territory on the right.
+       */
+
+      if (oldwidth < newwidth)
+        {
+          /* Get a bounding box in device coordinates */
+
+          bounds.pt1.x = wnd->bounds.pt1.x + oldwidth;
+          bounds.pt1.y = wnd->bounds.pt1.y;
+          bounds.pt2.x = wnd->bounds.pt2.x;
+          bounds.pt2.y = wnd->bounds.pt2.y + MIN(oldheight, newheight) - 1;
+
+          /* Send the redraw request */
+
+          nxmu_redrawreq(wnd, &bounds);
+        }
+
+      /* If the window became taller, then send a message requesting an update
+       * of the new territory at the bottom.
+       */
+
+      if (oldheight < newheight)
+        {
+          /* Get a bounding box in device coordinates */
+
+          bounds.pt1.x = wnd->bounds.pt1.x;
+          bounds.pt1.y = wnd->bounds.pt1.y + oldheight;
+          bounds.pt2.x = wnd->bounds.pt2.x;
+          bounds.pt2.y = wnd->bounds.pt2.y;
+
+          /* Send the redraw request */
+
+          nxmu_redrawreq(wnd, &bounds);
+        }
     }
 }
 #else
@@ -246,6 +290,12 @@ void nxbe_setsize(FAR struct nxbe_window_s *wnd,
 
   nxgl_rectintersect(&wnd->bounds, &wnd->bounds, &wnd->be->bkgd.bounds);
 
+  /* Report the new size/position.  The application needs to know the new
+   * size before getting redraw requests.
+   */
+
+  nxmu_reportposition(wnd);
+
   /* Re-allocate the per-window framebuffer memory for the new window size. */
 
   nxbe_realloc(wnd, &bounds);
@@ -257,10 +307,6 @@ void nxbe_setsize(FAR struct nxbe_window_s *wnd,
 
   nxgl_rectunion(&bounds, &bounds, &wnd->bounds);
 
-  /* Report the new size/position */
-
-  nxmu_reportposition(wnd);
-
   /* Then redraw this window AND all windows below it. Having resized the
    * window, we may have exposed previoulsy obscured portions of windows
    * below this one.
diff --git a/graphics/nxbe/nxbe_setvisibility.c b/graphics/nxbe/nxbe_setvisibility.c
new file mode 100644
index 00000000000..7cd3b4eacee
--- /dev/null
+++ b/graphics/nxbe/nxbe_setvisibility.c
@@ -0,0 +1,206 @@
+/****************************************************************************
+ * graphics/nxbe/nxbe_setvisibility.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include 
+
+#include "nxbe.h"
+#include "nxmu.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nxbe_show_window
+ *
+ * Description:
+ *   Make a hidden window visible.
+ *
+ * Input Parameters:
+ *   wnd  - The window to be shown
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void nxbe_show_window(FAR struct nxbe_window_s *wnd)
+{
+  FAR struct nxbe_state_s *be = wnd->be;
+
+  /* Mark the window no longer hidden */
+
+  NXBE_CLRHIDDEN(wnd);
+
+  /* Restore the window to the top of the hierarchy.  Exception:  If the top
+   * window is a modal window, then only raise it to second highest.
+   */
+
+  if (NXBE_STATE_ISMODAL(be) && be->topwnd->below != NULL)
+    {
+      /* We are in a modal state.  The topwnd is not the background and it
+       * has focus.
+       */
+
+      wnd->above        = be->topwnd;
+      wnd->below        = be->topwnd->below;
+
+      be->topwnd->below = wnd;
+
+     /* Redraw this window and the other that are below us */
+
+      nxbe_redrawbelow(be, wnd, &wnd->bounds);
+    }
+  else
+    {
+      /* Otherwise re-insert the window at the top on the display. */
+
+      wnd->above        = NULL;
+      wnd->below        = be->topwnd;
+
+      be->topwnd->above = wnd;
+      be->topwnd        = wnd;
+
+      /* This window is now at the top of the display, we know, therefore,
+       * that it is not obscured by another window.  Just redraw it.
+       */
+
+      nxmu_redraw(wnd, &wnd->bounds);
+    }
+}
+
+/****************************************************************************
+ * Name: nxbe_hide_window
+ *
+ * Description:
+ *   Hide a visible window.
+ *
+ * Input Parameters:
+ *   wnd  - The window to be modified
+ *   hide - True: Window will be hidden; false: Window will be visible
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void nxbe_hide_window(FAR struct nxbe_window_s *wnd)
+{
+  FAR struct nxbe_state_s *be = wnd->be;
+
+  /* The background window should never be hidden */
+
+  DEBUGASSERT(wnd != &be->bkgd);
+
+  /* Remove this window from the hiearachy */
+
+  /* Is there a window above the one being hidden? */
+
+  if (wnd->above != NULL)
+    {
+      /* Yes, now the window below that one is the window below
+       * the one being hidden.
+       */
+
+      wnd->above->below = wnd->below;
+    }
+  else
+    {
+      /* No, then the top window is the one below this (which
+       * can never be NULL because the background window is
+       * always at the true bottom of the list
+       */
+
+      be->topwnd = wnd->below;
+    }
+
+  /* There is always a window below the one being closed (because
+   * the background is never closed.  Now, the window above that
+   * is the window above the one that is being closed.
+   */
+
+  wnd->below->above = wnd->above;
+
+  /* Redraw the windows that were below us (and may now be exposed) */
+
+  nxbe_redrawbelow(be, wnd->below, &wnd->bounds);
+
+  /* And mark the window as hidden */
+
+  NXBE_SETHIDDEN(wnd);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nxbe_setvisibility
+ *
+ * Description:
+ *   Select if the window is visible or hidden.  A hidden window is still
+ *   present will will update normally, but will be on the visiable on the
+ *   display until it is unhidden.
+ *
+ * Input Parameters:
+ *   wnd  - The window to be modified
+ *   hide - True: Window will be hidden; false: Window will be visible
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void nxbe_setvisibility(FAR struct nxbe_window_s *wnd, bool hide)
+{
+  /* Are we showing the window?  Or hiding it? */
+
+  if (hide && !NXBE_ISHIDDEN(wnd))
+    {
+      nxbe_hide_window(wnd);
+    }
+  else if (!hide && NXBE_ISHIDDEN(wnd))
+    {
+      nxbe_show_window(wnd);
+    }
+}
diff --git a/graphics/nxglib/.gitignore b/graphics/nxglib/.gitignore
index d49f40d897e..861a0270ac7 100644
--- a/graphics/nxglib/.gitignore
+++ b/graphics/nxglib/.gitignore
@@ -10,4 +10,6 @@
 /pwfb_filltrapezoid_*bpp.c
 /pwfb_moverectangle_*bpp.c
 /pwfb_copyrectangle_*bpp.c
-
+/nxglib_cursor_draw_*bpp.c
+/nxglib_cursor_erase_*bpp.c
+/nxglib_cursor_backup_*bpp.c
\ No newline at end of file
diff --git a/graphics/nxglib/Make.defs b/graphics/nxglib/Make.defs
index 634ac014632..db252c4ba81 100644
--- a/graphics/nxglib/Make.defs
+++ b/graphics/nxglib/Make.defs
@@ -97,6 +97,19 @@ CSRCS += pwfb_copyrectangle_32bpp.c
 
 endif
 
+ifeq ($(CONFIG_NX_SWCURSOR),y)
+
+CSRCS += nxglib_cursor_draw_8bpp.c nxglib_cursor_draw_16bpp.c
+CSRCS += nxglib_cursor_draw_24bpp.c nxglib_cursor_draw_32bpp.c
+
+CSRCS += nxglib_cursor_erase_8bpp.c nxglib_cursor_erase_16bpp.c
+CSRCS += nxglib_cursor_erase_24bpp.c nxglib_cursor_erase_32bpp.c
+
+CSRCS += nxglib_cursor_backup_8bpp.c nxglib_cursor_backup_16bpp.c
+CSRCS += nxglib_cursor_backup_24bpp.c nxglib_cursor_backup_32bpp.c
+
+endif
+
 DEPPATH += --dep-path nxglib
 CFLAGS += ${shell $(INCDIR) $(INCDIROPT) "$(CC)" $(TOPDIR)/graphics/nxglib}
 #VPATH += :nxglib
diff --git a/graphics/nxglib/Makefile.cursor b/graphics/nxglib/Makefile.cursor
new file mode 100644
index 00000000000..4544dd93379
--- /dev/null
+++ b/graphics/nxglib/Makefile.cursor
@@ -0,0 +1,105 @@
+############################################################################
+# graphics/nxglib/Makefile.cursor
+#
+#   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt 
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+
+ifeq ($(NXGLIB_BITSPERPIXEL),8)
+NXGLIB_SUFFIX := _8bpp
+DRAW_CSRC     := nxglib_cursor_draw_8bpp.c
+ERASE_CSRC    := nxglib_cursor_erase_8bpp.c
+BACKUP_CSRC   := nxglib_cursor_backup_8bpp.c
+endif
+ifeq ($(NXGLIB_BITSPERPIXEL),16)
+NXGLIB_SUFFIX := _16bpp
+DRAW_CSRC     := nxglib_cursor_draw_16bpp.c
+ERASE_CSRC    := nxglib_cursor_erase_16bpp.c
+BACKUP_CSRC   := nxglib_cursor_backup_16bpp.c
+endif
+ifeq ($(NXGLIB_BITSPERPIXEL),24)
+NXGLIB_SUFFIX := _24bpp
+DRAW_CSRC     := nxglib_cursor_draw_24bpp.c
+ERASE_CSRC    := nxglib_cursor_erase_24bpp.c
+BACKUP_CSRC   := nxglib_cursor_backup_24bpp.c
+endif
+ifeq ($(NXGLIB_BITSPERPIXEL),32)
+NXGLIB_SUFFIX := _32bpp
+DRAW_CSRC     := nxglib_cursor_draw_32bpp.c
+ERASE_CSRC    := nxglib_cursor_erase_32bpp.c
+BACKUP_CSRC   := nxglib_cursor_backup_32bpp.c
+endif
+
+CPPFLAGS      += -DNXGLIB_BITSPERPIXEL=$(NXGLIB_BITSPERPIXEL)
+CPPFLAGS      += -DNXGLIB_SUFFIX=$(NXGLIB_SUFFIX)
+
+DRAW_TMP       = $(DRAW_CSRC:.c=.i)
+ERASE_TMP      = $(ERASE_CSRC:.c=.i)
+BACKUP_TMP     = $(BACKUP_CSRC:.c=.i)
+
+GEN_CSRCS      = $(DRAW_CSRC) $(ERASE_CSRC) $(BACKUP_CSRC)
+
+BLITDIR        = cursor
+
+all:    $(GEN_CSRCS)
+.PHONY : clean distclean
+
+$(DRAW_CSRC) : $(BLITDIR)/nxglib_cursor_draw.c nxglib_bitblit.h
+ifneq ($(NXGLIB_BITSPERPIXEL),)
+	$(call PREPROCESS, $(BLITDIR)/nxglib_cursor_draw.c, $(DRAW_TMP))
+	$(Q) cat $(DRAW_TMP) | sed -e "/^#/d" >$@
+	$(Q) rm -f  $(DRAW_TMP)
+endif
+
+$(ERASE_CSRC) : $(BLITDIR)/nxglib_cursor_erase.c nxglib_bitblit.h
+ifneq ($(NXGLIB_BITSPERPIXEL),)
+	$(call PREPROCESS, $(BLITDIR)/nxglib_cursor_erase.c, $(ERASE_TMP))
+	$(Q) cat $(ERASE_TMP) | sed -e "/^#/d" >$@
+	$(Q) rm -f  $(ERASE_TMP)
+endif
+
+$(BACKUP_CSRC) : $(BLITDIR)/nxglib_cursor_backup.c nxglib_bitblit.h
+ifneq ($(NXGLIB_BITSPERPIXEL),)
+	$(call PREPROCESS, $(BLITDIR)/nxglib_cursor_backup.c, $(BACKUP_TMP))
+	$(Q) cat $(BACKUP_TMP) | sed -e "/^#/d" >$@
+	$(Q) rm -f  $(BACKUP_TMP)
+endif
+
+clean:
+	$(call DELFILE, *.i)
+	$(call CLEAN)
+
+distclean: clean
+	$(call DELFILE, nxglib_cursor_draw_*bpp.c)
+	$(call DELFILE, nxglib_cursor_erase_*bpp.c)
+	$(call DELFILE, nxglib_cursor_backup_*bpp.c)
diff --git a/graphics/nxglib/cursor/nxglib_cursor_backup.c b/graphics/nxglib/cursor/nxglib_cursor_backup.c
new file mode 100644
index 00000000000..814903076c2
--- /dev/null
+++ b/graphics/nxglib/cursor/nxglib_cursor_backup.c
@@ -0,0 +1,152 @@
+/****************************************************************************
+ * graphics/nxglib/nxglib_cursor_backup.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include 
+
+#include "nxglib_bitblit.h"
+#include "../nxbe/nxbe.h"
+#include "nxglib.h"
+
+#ifdef CONFIG_NX_SWCURSOR
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nxglib_cursor_backup
+ *
+ * Description:
+ *   Saved the cursor background data from the device graphics memory into an
+ *   internal save area.  This saved image will be used to "erase" the cursor
+ *   when necessary.
+ *
+ * Input Parameters:
+ *   be      - The back-end state structure instance
+ *   bounds  - The region of the display that has been modified.
+ *   planeno - The color plane being drawn
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void NXGL_FUNCNAME(nxglib_cursor_backup, NXGLIB_SUFFIX)
+(FAR struct nxbe_state_s *be, FAR const struct nxgl_rect_s *bounds, int planeno)
+{
+  struct nxgl_rect_s intersection;
+  struct nxgl_point_s origin;
+  FAR struct nxbe_plane_s *plane;
+  FAR uint8_t *fbmem;
+  FAR const uint8_t *sline;
+  FAR uint8_t *dline;
+  FAR const FAR NXGL_PIXEL_T *src;
+  FAR FAR NXGL_PIXEL_T *dest;
+  nxgl_coord_t width;
+  nxgl_coord_t height;
+  nxgl_coord_t sstride;
+  nxgl_coord_t dwidth;
+  nxgl_coord_t dstride;
+  int row;
+  int col;
+
+  /* Handle the case some or all of the backup image is off of the display. */
+
+  nxgl_rectintersect(&intersection, &be->cursor.bounds, &be->bkgd.bounds);
+
+  /* Check if there is anything in the modified region that we need to handle. */
+
+  nxgl_rectintersect(&intersection, &intersection, bounds);
+  if (!nxgl_nullrect(&intersection))
+    {
+      /* Get the width and the height of the images to copy in pixels/rows */
+
+      width   = intersection.pt2.x - intersection.pt1.x + 1;
+      height  = intersection.pt2.y - intersection.pt1.y + 1;
+
+      /* Get the width of the images in bytes. */
+
+      plane   = &be->plane[planeno];
+      sstride = plane->pinfo.stride;
+
+      dwidth  = be->cursor.bounds.pt2.x - be->cursor.bounds.pt1.x + 1;
+      dstride = NXGL_SCALEX(dwidth);
+
+      /* Get the origin position in the background image */
+
+      nxgl_vectsubtract(&origin, &intersection.pt1, &be->cursor.bounds.pt1);
+
+      /* Get the source and destination addresses */
+
+      fbmem  = (FAR uint8_t *)plane->pinfo.fbmem;
+      sline  = (FAR uint8_t *)fbmem + sstride * intersection.pt1.y +
+                NXGL_SCALEX(intersection.pt1.x);
+      dline  = (FAR uint8_t *)be->cursor.bkgd + dstride * origin.y +
+                NXGL_SCALEX(origin.x);
+
+      /* Save the cursor background by copying the device graphics memory */
+
+      /* Loop for each row */
+
+      for (row = 0; row < height; row++)
+        {
+          /* Reset to the beginning of the line */
+
+          src  = (FAR NXGL_PIXEL_T *)sline;
+          dest = (FAR NXGL_PIXEL_T *)dline;
+
+          /* Loop for each column */
+
+          for (col = 0; col < width; col++)
+            {
+              *dest++ = *src++;
+            }
+
+          /* Update the row addresses to the next row */
+
+          sline += sstride;
+          dline += dstride;
+       }
+    }
+}
+#endif /* CONFIG_NX_SWCURSOR */
diff --git a/graphics/nxglib/cursor/nxglib_cursor_draw.c b/graphics/nxglib/cursor/nxglib_cursor_draw.c
new file mode 100644
index 00000000000..000dc5bfc27
--- /dev/null
+++ b/graphics/nxglib/cursor/nxglib_cursor_draw.c
@@ -0,0 +1,235 @@
+/****************************************************************************
+ * graphics/nxglib/nxglib_cursor_draw.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include 
+
+#include "nxglib_bitblit.h"
+#include "../nxbe/nxbe.h"
+#include "nxglib.h"
+
+#ifdef CONFIG_NX_SWCURSOR
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nxbe_map_color
+ *
+ * Description:
+ *   Map a 2-bit cursor pixel value to a device pixel value
+ *
+ *   REVISIT:  If we really were to support multiple displays (or planes)
+ *   with differing pixel depth, then the cursor.color1,2,3 would be
+ *   insufficient:  There would have to be multiple color sets for each
+ *   plane.
+ *
+ * Input Parameters:
+ *   be   - The back-end state structure instance
+ *   pixel - Pixel to be mapped
+ *
+ * Returned Value:
+ *   The mapped pixel.
+ *
+ ****************************************************************************/
+
+static NXGL_PIXEL_T nxbe_map_color(FAR struct nxbe_state_s *be, int plane,
+                                   uint8_t pixel)
+{
+  switch (pixel)
+    {
+      case 0:
+      default:
+        return 0;  /* Should not happen */
+
+      case 1:
+        return be->cursor.color1[plane];
+
+      case 2:
+        return be->cursor.color2[plane];
+
+      case 3:
+        return be->cursor.color3[plane];
+    }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nxglib_cursor_draw
+ *
+ * Description:
+ *   Update the cursor region by drawing directly in device memory.
+ *
+ * Input Parameters:
+ *   be      - The back-end state structure instance
+ *   bounds  - The region of the display that has been modified.
+ *   planeno - The color plane being drawn
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void NXGL_FUNCNAME(nxglib_cursor_draw, NXGLIB_SUFFIX)
+(FAR struct nxbe_state_s *be, FAR const struct nxgl_rect_s *bounds, int planeno)
+{
+  struct nxgl_rect_s intersection;
+  struct nxgl_point_s origin;
+  FAR struct nxbe_plane_s *plane;
+  FAR uint8_t *fbmem;
+  FAR const uint8_t *src;
+  FAR const uint8_t *sline;
+  FAR uint8_t *dline;
+  FAR NXGL_PIXEL_T *dest;
+  nxgl_coord_t width;
+  nxgl_coord_t height;
+  nxgl_coord_t swidth;
+  nxgl_coord_t sstride;
+  nxgl_coord_t dstride;
+  nxgl_coord_t sshift;
+  int shift;
+  int row;
+  int col;
+
+  /* Handle the case some or all of the cursor image is off of the display. */
+
+  nxgl_rectintersect(&intersection, &be->cursor.bounds, &be->bkgd.bounds);
+
+  /* Check if there is anything in the modified region that we need to handle. */
+
+  nxgl_rectintersect(&intersection, &intersection, bounds);
+  if (!nxgl_nullrect(&intersection))
+    {
+      /* Get the width and the height of the images to copy in pixels/rows */
+
+      width   = intersection.pt2.x - intersection.pt1.x + 1;
+      height  = intersection.pt2.y - intersection.pt1.y + 1;
+
+      /* Get the width of the images in bytes. */
+
+      swidth  = be->cursor.bounds.pt2.x - be->cursor.bounds.pt1.x + 1;
+      sstride = (swidth + 3) >> 2;  /* 2 bits per pixel, 4 pixels per byte */
+
+      plane   = &be->plane[planeno];
+      dstride = plane->pinfo.stride;
+
+      /* Get the origin position in the cursor image */
+
+      nxgl_vectsubtract(&origin, &intersection.pt1, &be->cursor.bounds.pt1);
+
+      /* Update any cursor graphics on top of the device display to include
+       * the modified cursor.
+       *
+       * REVISIT:  This will only work for a single plane and for bits per
+       * pixel greater than or equal to 8.
+       */
+
+      fbmem  = (FAR uint8_t *)plane->pinfo.fbmem;
+      sline  = be->cursor.image + sstride * origin.y + (origin.x >> 2);
+      dline  = (FAR uint8_t *)fbmem + dstride * intersection.pt1.y +
+                NXGL_SCALEX(intersection.pt1.x);
+
+      sshift = (3 - (origin.y & 3)) << 1;    /* MS first {0, 2, 4, 6} */
+
+      /* Loop for each row */
+
+      for (row = 0; row < height; row++)
+        {
+          /* Reset to the beginning of the line */
+
+          src   = sline;
+          dest  = (FAR NXGL_PIXEL_T *)dline;
+          shift = sshift;
+
+          /* Loop for each column */
+
+          for (col = 0; col < width; col++)
+            {
+              /* Extract the 2-bit pixel.  Data is always packed MS first.
+               * Shift for first pixel=6, shift for last pixel=0
+               */
+
+              uint8_t pixel = (*src >> shift) & 3;
+
+              /* Skip over invisible pixels */
+
+              if (pixel != 0)
+                {
+                  *dest = nxbe_map_color(be, 0, pixel);
+                }
+
+              dest++;
+
+              /* Was that the last pixel in the byte? */
+
+              if (shift == 0)
+                {
+                  /* Update source column addresses and reset the shift
+                   * value
+                   */
+
+                  src++;
+                  shift = 6;
+                }
+              else
+                {
+                  /* The shift value is one of {2, 4, 6}.  Update the shift
+                   * value following this order: 6, 4, 2, 0
+                   */
+
+                  shift = (shift - 2) & 6;
+                }
+            }
+
+          /* Update the row addresses to the next row */
+
+          sline += sstride;
+          dline += dstride;
+       }
+    }
+}
+
+#endif /* CONFIG_NX_SWCURSOR */
diff --git a/graphics/nxglib/cursor/nxglib_cursor_erase.c b/graphics/nxglib/cursor/nxglib_cursor_erase.c
new file mode 100644
index 00000000000..1970e896b9a
--- /dev/null
+++ b/graphics/nxglib/cursor/nxglib_cursor_erase.c
@@ -0,0 +1,152 @@
+/****************************************************************************
+ * graphics/nxglib/nxglib_cursor_erase.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+
+#include 
+
+#include "nxglib_bitblit.h"
+#include "../nxbe/nxbe.h"
+#include "nxglib.h"
+
+#ifdef CONFIG_NX_SWCURSOR
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nxglib_cursor_erase
+ *
+ * Description:
+ *   Erase the cursor region by writing the saved background to the graphics
+ *   device memory.
+ *
+ * Input Parameters:
+ *   be      - The back-end state structure instance
+ *   bounds  - The region of the display that has been modified.
+ *   planeno - The color plane being drawn
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+void NXGL_FUNCNAME(nxglib_cursor_erase, NXGLIB_SUFFIX)
+(FAR struct nxbe_state_s *be, FAR const struct nxgl_rect_s *bounds, int planeno)
+{
+  struct nxgl_rect_s intersection;
+  struct nxgl_point_s origin;
+  FAR struct nxbe_plane_s *plane;
+  FAR uint8_t *fbmem;
+  FAR const uint8_t *sline;
+  FAR uint8_t *dline;
+  FAR const NXGL_PIXEL_T *src;
+  FAR NXGL_PIXEL_T *dest;
+  nxgl_coord_t width;
+  nxgl_coord_t height;
+  nxgl_coord_t swidth;
+  nxgl_coord_t sstride;
+  nxgl_coord_t dstride;
+  int row;
+  int col;
+
+  /* Handle the case some or all of the cursor image is off of the display. */
+
+  nxgl_rectintersect(&intersection, &be->cursor.bounds, &be->bkgd.bounds);
+
+  /* Check if there is anything in the modified region that we need to handle. */
+
+  nxgl_rectintersect(&intersection, &intersection, bounds);
+  if (!nxgl_nullrect(&intersection))
+    {
+      /* Get the width and the height of the images to copy in pixels/rows */
+
+      width   = intersection.pt2.x - intersection.pt1.x + 1;
+      height  = intersection.pt2.y - intersection.pt1.y + 1;
+
+      /* Get the width of the images in bytes. */
+
+      swidth  = be->cursor.bounds.pt2.x - be->cursor.bounds.pt1.x + 1;
+      sstride = NXGL_SCALEX(swidth);
+
+      plane   = &be->plane[planeno];
+      dstride = plane->pinfo.stride;
+
+      /* Get the origin position in the background image */
+
+      nxgl_vectsubtract(&origin, &intersection.pt1, &be->cursor.bounds.pt1);
+
+      /* Get the source and destination addresses */
+
+      fbmem  = (FAR uint8_t *)plane->pinfo.fbmem;
+      sline  = (FAR uint8_t *)be->cursor.bkgd + sstride * origin.y +
+                NXGL_SCALEX(origin.x);
+      dline  = (FAR uint8_t *)fbmem + dstride * intersection.pt1.y +
+                NXGL_SCALEX(intersection.pt1.x);
+
+      /* Erase the old cursor position by copying the previous content */
+
+      /* Loop for each row */
+
+      for (row = 0; row < height; row++)
+        {
+          /* Reset to the beginning of the line */
+
+          src  = (FAR NXGL_PIXEL_T *)sline;
+          dest = (FAR NXGL_PIXEL_T *)dline;
+
+          /* Loop for each column */
+
+          for (col = 0; col < width; col++)
+            {
+              *dest++ = *src++;
+            }
+
+          /* Update the row addresses to the next row */
+
+          sline += sstride;
+          dline += dstride;
+       }
+    }
+}
+
+#endif /* CONFIG_NX_SWCURSOR */
diff --git a/graphics/nxglib/nxglib.h b/graphics/nxglib/nxglib.h
new file mode 100644
index 00000000000..03e781def4f
--- /dev/null
+++ b/graphics/nxglib/nxglib.h
@@ -0,0 +1,534 @@
+/****************************************************************************
+ * graphics/nxglib/nx/nxglib.h
+ *
+ *   Copyright (C) 2008-2011, 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __GRAPHICS_NXGLIB_NXBLIC_H
+#define __GRAPHICS_NXGLIB_NXBLIC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+
+#include 
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+# define EXTERN extern "C"
+extern "C"
+{
+#else
+# define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/* Rasterizers **************************************************************/
+
+/****************************************************************************
+ * Name: nxgl_setpixel_*bpp / pwfb_setpixel_*bpp
+ *
+ * Description:
+ *   Draw a single pixel in graphics memory at the given position and
+ *   with the given color.  This is equivalent to nxgl_fillrectangle_*bpp()
+ *   with a 1x1 rectangle but is more efficient.
+ *
+ ****************************************************************************/
+
+struct nxbe_window_s; /* Forward reference.  See include/nuttx/nx/nxbe.h */
+
+/* For direct access to graphics device memory */
+
+void nxgl_setpixel_1bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                        FAR const struct nxgl_point_s *pos, uint8_t color);
+void nxgl_setpixel_2bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                        FAR const struct nxgl_point_s *pos, uint8_t color);
+void nxgl_setpixel_4bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                        FAR const struct nxgl_point_s *pos, uint8_t color);
+void nxgl_setpixel_8bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                        FAR const struct nxgl_point_s *pos, uint8_t color);
+void nxgl_setpixel_16bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                         FAR const struct nxgl_point_s *pos, uint16_t color);
+void nxgl_setpixel_24bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                         FAR const struct nxgl_point_s *pos, uint32_t color);
+void nxgl_setpixel_32bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                         FAR const struct nxgl_point_s *pos, uint32_t color);
+
+#ifdef CONFIG_NX_RAMBACKED
+/* For access to per-window framebuffer memory */
+
+void pwfb_setpixel_1bpp(FAR struct nxbe_window_s *bwnd,
+                        FAR const struct nxgl_point_s *pos, uint8_t color);
+void pwfb_setpixel_2bpp(FAR struct nxbe_window_s *bwnd,
+                        FAR const struct nxgl_point_s *pos, uint8_t color);
+void pwfb_setpixel_4bpp(FAR struct nxbe_window_s *bwnd,
+                        FAR const struct nxgl_point_s *pos, uint8_t color);
+void pwfb_setpixel_8bpp(FAR struct nxbe_window_s *bwnd,
+                        FAR const struct nxgl_point_s *pos, uint8_t color);
+void pwfb_setpixel_16bpp(FAR struct nxbe_window_s *bwnd,
+                         FAR const struct nxgl_point_s *pos, uint16_t color);
+void pwfb_setpixel_24bpp(FAR struct nxbe_window_s *bwnd,
+                         FAR const struct nxgl_point_s *pos, uint32_t color);
+void pwfb_setpixel_32bpp(FAR struct nxbe_window_s *bwnd,
+                         FAR const struct nxgl_point_s *pos, uint32_t color);
+#endif
+
+/****************************************************************************
+ * Name: nxgl_fillrectangle_*bpp / pwfb_fillrectangle_*bpp
+ *
+ * Description:
+ *   Fill a rectangle region in the graphics memory with a fixed color
+ *
+ ****************************************************************************/
+
+/* For direct access to graphics device memory */
+
+void nxgl_fillrectangle_1bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_rect_s *rect,
+                             uint8_t color);
+void nxgl_fillrectangle_2bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_rect_s *rect,
+                             uint8_t color);
+void nxgl_fillrectangle_4bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_rect_s *rect,
+                             uint8_t color);
+void nxgl_fillrectangle_8bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_rect_s *rect,
+                             uint8_t color);
+void nxgl_fillrectangle_16bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                              FAR const struct nxgl_rect_s *rect,
+                              uint16_t color);
+void nxgl_fillrectangle_24bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                              FAR const struct nxgl_rect_s *rect,
+                              uint32_t color);
+void nxgl_fillrectangle_32bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                              FAR const struct nxgl_rect_s *rect,
+                              uint32_t color);
+
+#ifdef CONFIG_NX_RAMBACKED
+/* For access to per-window framebuffer memory */
+
+void pwfb_fillrectangle_1bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_rect_s *rect,
+                             uint8_t color);
+void pwfb_fillrectangle_2bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_rect_s *rect,
+                             uint8_t color);
+void pwfb_fillrectangle_4bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_rect_s *rect,
+                             uint8_t color);
+void pwfb_fillrectangle_8bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_rect_s *rect,
+                             uint8_t color);
+void pwfb_fillrectangle_16bpp(FAR struct nxbe_window_s *bwnd,
+                              FAR const struct nxgl_rect_s *rect,
+                              uint16_t color);
+void pwfb_fillrectangle_24bpp(FAR struct nxbe_window_s *bwnd,
+                              FAR const struct nxgl_rect_s *rect,
+                              uint32_t color);
+void pwfb_fillrectangle_32bpp(FAR struct nxbe_window_s *bwnd,
+                              FAR const struct nxgl_rect_s *rect,
+                              uint32_t color);
+#endif
+
+/****************************************************************************
+ * Name: nxgl_getrectangle_*bpp / pwfb_getrectangle_*bpp
+ *
+ * Description:
+ *   Fetch a rectangular region from graphics memory.  The source is
+ *   expressed as a rectangle.
+ *
+ ****************************************************************************/
+
+/* For direct access to graphics device memory */
+
+void nxgl_getrectangle_1bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                            FAR const struct nxgl_rect_s *rect,
+                            FAR void *dest, unsigned int deststride);
+void nxgl_getrectangle_2bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                            FAR const struct nxgl_rect_s *rect,
+                            FAR void *dest, unsigned int deststride);
+void nxgl_getrectangle_4bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                            FAR const struct nxgl_rect_s *rect,
+                            FAR void *dest, unsigned int deststride);
+void nxgl_getrectangle_8bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                            FAR const struct nxgl_rect_s *rect,
+                            FAR void *dest, unsigned int deststride);
+void nxgl_getrectangle_16bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_rect_s *rect,
+                             FAR void *dest, unsigned int deststride);
+void nxgl_getrectangle_24bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_rect_s *rect,
+                             FAR void *dest, unsigned int deststride);
+void nxgl_getrectangle_32bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_rect_s *rect,
+                             FAR void *dest, unsigned int deststride);
+
+#ifdef CONFIG_NX_RAMBACKED
+/* For access to per-window framebuffer memory */
+
+void pwfb_getrectangle_1bpp(FAR struct nxbe_window_s *bwnd,
+                            FAR const struct nxgl_rect_s *rect,
+                            FAR void *dest, unsigned int deststride);
+void pwfb_getrectangle_2bpp(FAR struct nxbe_window_s *bwnd,
+                            FAR const struct nxgl_rect_s *rect,
+                            FAR void *dest, unsigned int deststride);
+void pwfb_getrectangle_4bpp(FAR struct nxbe_window_s *bwnd,
+                            FAR const struct nxgl_rect_s *rect,
+                            FAR void *dest, unsigned int deststride);
+void pwfb_getrectangle_8bpp(FAR struct nxbe_window_s *bwnd,
+                            FAR const struct nxgl_rect_s *rect,
+                            FAR void *dest, unsigned int deststride);
+void pwfb_getrectangle_16bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_rect_s *rect,
+                             FAR void *dest, unsigned int deststride);
+void pwfb_getrectangle_24bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_rect_s *rect,
+                             FAR void *dest, unsigned int deststride);
+void pwfb_getrectangle_32bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_rect_s *rect,
+                             FAR void *dest, unsigned int deststride);
+#endif
+
+/****************************************************************************
+ * Name: nxglib_filltrapezoid_*bpp / pwfb_filltrapezoid_*bpp
+ *
+ * Description:
+ *   Fill a trapezoidal region in the graphics memory with a fixed color.
+ *   Clip the trapezoid to lie within a bounding box.  This is useful for
+ *   drawing complex shapes that can be broken into a set of trapezoids.
+ *
+ ****************************************************************************/
+
+/* For direct access to graphics device memory */
+
+void nxgl_filltrapezoid_1bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_trapezoid_s *trap,
+                             FAR const struct nxgl_rect_s *bounds,
+                             uint8_t color);
+void nxgl_filltrapezoid_2bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_trapezoid_s *trap,
+                             FAR const struct nxgl_rect_s *bounds,
+                             uint8_t color);
+void nxgl_filltrapezoid_4bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_trapezoid_s *trap,
+                             FAR const struct nxgl_rect_s *bounds,
+                             uint8_t color);
+void nxgl_filltrapezoid_8bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_trapezoid_s *trap,
+                             FAR const struct nxgl_rect_s *bounds,
+                             uint8_t color);
+void nxgl_filltrapezoid_16bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                              FAR const struct nxgl_trapezoid_s *trap,
+                              FAR const struct nxgl_rect_s *bounds,
+                              uint16_t color);
+void nxgl_filltrapezoid_24bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                              FAR const struct nxgl_trapezoid_s *trap,
+                              FAR const struct nxgl_rect_s *bounds,
+                              uint32_t color);
+void nxgl_filltrapezoid_32bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                              FAR const struct nxgl_trapezoid_s *trap,
+                              FAR const struct nxgl_rect_s *bounds,
+                              uint32_t color);
+
+#ifdef CONFIG_NX_RAMBACKED
+/* For access to per-window framebuffer memory */
+
+void pwfb_filltrapezoid_1bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_trapezoid_s *trap,
+                             FAR const struct nxgl_rect_s *bounds,
+                             uint8_t color);
+void pwfb_filltrapezoid_2bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_trapezoid_s *trap,
+                             FAR const struct nxgl_rect_s *bounds,
+                             uint8_t color);
+void pwfb_filltrapezoid_4bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_trapezoid_s *trap,
+                             FAR const struct nxgl_rect_s *bounds,
+                             uint8_t color);
+void pwfb_filltrapezoid_8bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_trapezoid_s *trap,
+                             FAR const struct nxgl_rect_s *bounds,
+                             uint8_t color);
+void pwfb_filltrapezoid_16bpp(FAR struct nxbe_window_s *bwnd,
+                              FAR const struct nxgl_trapezoid_s *trap,
+                              FAR const struct nxgl_rect_s *bounds,
+                              uint16_t color);
+void pwfb_filltrapezoid_24bpp(FAR struct nxbe_window_s *bwnd,
+                              FAR const struct nxgl_trapezoid_s *trap,
+                              FAR const struct nxgl_rect_s *bounds,
+                              uint32_t color);
+void pwfb_filltrapezoid_32bpp(FAR struct nxbe_window_s *bwnd,
+                              FAR const struct nxgl_trapezoid_s *trap,
+                              FAR const struct nxgl_rect_s *bounds,
+                              uint32_t color);
+#endif
+
+/****************************************************************************
+ * Name: nxgl_moverectangle_*bpp / pwfb_moverectangle_*bpp
+ *
+ * Description:
+ *   Move a rectangular region from location to another in the
+ *   framebuffer/LCD memory.  The source is expressed as a rectangle; the
+ *   destination position is expressed as a point corresponding to the
+ *   translation of the upper, left-hand corner.
+ *
+ ****************************************************************************/
+
+/* For direct access to graphics device memory */
+
+void nxgl_moverectangle_1bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_rect_s *rect,
+                             FAR struct nxgl_point_s *offset);
+void nxgl_moverectangle_2bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_rect_s *rect,
+                             FAR struct nxgl_point_s *offset);
+void nxgl_moverectangle_4bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_rect_s *rect,
+                             FAR struct nxgl_point_s *offset);
+void nxgl_moverectangle_8bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_rect_s *rect,
+                             FAR struct nxgl_point_s *offset);
+void nxgl_moverectangle_16bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                              FAR const struct nxgl_rect_s *rect,
+                              FAR struct nxgl_point_s *offset);
+void nxgl_moverectangle_24bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                              FAR const struct nxgl_rect_s *rect,
+                              FAR struct nxgl_point_s *offset);
+void nxgl_moverectangle_32bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                              FAR const struct nxgl_rect_s *rect,
+                              FAR struct nxgl_point_s *offset);
+
+#ifdef CONFIG_NX_RAMBACKED
+/* For access to per-window framebuffer memory */
+
+void pwfb_moverectangle_1bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_rect_s *rect,
+                             FAR struct nxgl_point_s *offset);
+void pwfb_moverectangle_2bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_rect_s *rect,
+                             FAR struct nxgl_point_s *offset);
+void pwfb_moverectangle_4bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_rect_s *rect,
+                             FAR struct nxgl_point_s *offset);
+void pwfb_moverectangle_8bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_rect_s *rect,
+                             FAR struct nxgl_point_s *offset);
+void pwfb_moverectangle_16bpp(FAR struct nxbe_window_s *bwnd,
+                              FAR const struct nxgl_rect_s *rect,
+                              FAR struct nxgl_point_s *offset);
+void pwfb_moverectangle_24bpp(FAR struct nxbe_window_s *bwnd,
+                              FAR const struct nxgl_rect_s *rect,
+                              FAR struct nxgl_point_s *offset);
+void pwfb_moverectangle_32bpp(FAR struct nxbe_window_s *bwnd,
+                              FAR const struct nxgl_rect_s *rect,
+                              FAR struct nxgl_point_s *offset);
+#endif
+
+/****************************************************************************
+ * Name: nxgl_copyrectangle_*bpp / pwfb_copyrectangle_*bpp
+ *
+ * Description:
+ *   Copy a rectangular bitmap image into the specific position in the
+ *   graphics memory.
+ *
+ ****************************************************************************/
+
+/* For direct access to graphics device memory */
+
+void nxgl_copyrectangle_1bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_rect_s *dest,
+                             FAR const void *src,
+                             FAR const struct nxgl_point_s *origin,
+                             unsigned int srcstride);
+void nxgl_copyrectangle_2bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_rect_s *dest,
+                             FAR const void *src,
+                             FAR const struct nxgl_point_s *origin,
+                             unsigned int srcstride);
+void nxgl_copyrectangle_4bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_rect_s *dest,
+                             FAR const void *src,
+                             FAR const struct nxgl_point_s *origin,
+                             unsigned int srcstride);
+void nxgl_copyrectangle_8bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                             FAR const struct nxgl_rect_s *dest,
+                             FAR const void *src,
+                             FAR const struct nxgl_point_s *origin,
+                             unsigned int srcstride);
+void nxgl_copyrectangle_16bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                              FAR const struct nxgl_rect_s *dest,
+                              FAR const void *src,
+                              FAR const struct nxgl_point_s *origin,
+                              unsigned int srcstride);
+void nxgl_copyrectangle_24bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                              FAR const struct nxgl_rect_s *dest,
+                              FAR const void *src,
+                              FAR const struct nxgl_point_s *origin,
+                              unsigned int srcstride);
+void nxgl_copyrectangle_32bpp(FAR NX_PLANEINFOTYPE *pinfo,
+                              FAR const struct nxgl_rect_s *dest,
+                              FAR const void *src,
+                              FAR const struct nxgl_point_s *origin,
+                              unsigned int srcstride);
+
+#ifdef CONFIG_NX_RAMBACKED
+/* For access to per-window framebuffer memory */
+
+void pwfb_copyrectangle_1bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_rect_s *dest,
+                             FAR const void *src,
+                             FAR const struct nxgl_point_s *origin,
+                             unsigned int srcstride);
+void pwfb_copyrectangle_2bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_rect_s *dest,
+                             FAR const void *src,
+                             FAR const struct nxgl_point_s *origin,
+                             unsigned int srcstride);
+void pwfb_copyrectangle_4bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_rect_s *dest,
+                             FAR const void *src,
+                             FAR const struct nxgl_point_s *origin,
+                             unsigned int srcstride);
+void pwfb_copyrectangle_8bpp(FAR struct nxbe_window_s *bwnd,
+                             FAR const struct nxgl_rect_s *dest,
+                             FAR const void *src,
+                             FAR const struct nxgl_point_s *origin,
+                             unsigned int srcstride);
+void pwfb_copyrectangle_16bpp(FAR struct nxbe_window_s *bwnd,
+                              FAR const struct nxgl_rect_s *dest,
+                              FAR const void *src,
+                              FAR const struct nxgl_point_s *origin,
+                              unsigned int srcstride);
+void pwfb_copyrectangle_24bpp(FAR struct nxbe_window_s *bwnd,
+                              FAR const struct nxgl_rect_s *dest,
+                              FAR const void *src,
+                              FAR const struct nxgl_point_s *origin,
+                              unsigned int srcstride);
+void pwfb_copyrectangle_32bpp(FAR struct nxbe_window_s *bwnd,
+                              FAR const struct nxgl_rect_s *dest,
+                              FAR const void *src,
+                              FAR const struct nxgl_point_s *origin,
+                              unsigned int srcstride);
+#endif
+
+/****************************************************************************
+ * Name: nxgl_cursor_draw_*bpp
+ *
+ * Description:
+ *   Draw the cursor image into the specified position in the graphics memory.
+ *
+ ****************************************************************************/
+
+struct nxbe_state_s;    /* Forward reference */
+
+#ifdef CONFIG_NX_SWCURSOR
+void nxglib_cursor_draw_8bpp(FAR struct nxbe_state_s *be,
+                             FAR const struct nxgl_rect_s *bounds,
+                             int planeno);
+void nxglib_cursor_draw_16bpp(FAR struct nxbe_state_s *be,
+                              FAR const struct nxgl_rect_s *bounds,
+                              int planeno);
+void nxglib_cursor_draw_24bpp(FAR struct nxbe_state_s *be,
+                              FAR const struct nxgl_rect_s *bounds,
+                              int planeno);
+void nxglib_cursor_draw_32bpp(FAR struct nxbe_state_s *be,
+                              FAR const struct nxgl_rect_s *bounds,
+                              int planeno);
+#endif
+
+/****************************************************************************
+ * Name: nxgl_cursor_erase_*bpp
+ *
+ * Description:
+ *   Erase the cursor by copying the saved background image into the graphics
+ *   memory.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NX_SWCURSOR
+void nxglib_cursor_erase_8bpp(FAR struct nxbe_state_s *be,
+                              FAR const struct nxgl_rect_s *bounds,
+                              int planeno);
+void nxglib_cursor_erase_16bpp(FAR struct nxbe_state_s *be,
+                               FAR const struct nxgl_rect_s *bounds,
+                               int planeno);
+void nxglib_cursor_erase_24bpp(FAR struct nxbe_state_s *be,
+                               FAR const struct nxgl_rect_s *bounds,
+                               int planeno);
+void nxglib_cursor_erase_32bpp(FAR struct nxbe_state_s *be,
+                               FAR const struct nxgl_rect_s *bounds,
+                               int planeno);
+#endif
+
+/****************************************************************************
+ * Name: nxgl_cursor_backup_*bpp
+ *
+ * Description:
+ *   Save the backgroud image for subsequent use to erase the cursor from the
+ *   device graphics memory.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NX_SWCURSOR
+void nxglib_cursor_backup_8bpp(FAR struct nxbe_state_s *be,
+                               FAR const struct nxgl_rect_s *bounds,
+                               int planeno);
+void nxglib_cursor_backup_16bpp(FAR struct nxbe_state_s *be,
+                                FAR const struct nxgl_rect_s *bounds,
+                                int planeno);
+void nxglib_cursor_backup_24bpp(FAR struct nxbe_state_s *be,
+                                FAR const struct nxgl_rect_s *bounds,
+                                int planeno);
+void nxglib_cursor_backup_32bpp(FAR struct nxbe_state_s *be,
+                                FAR const struct nxgl_rect_s *bounds,
+                                int planeno);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __GRAPHICS_NXGLIB_NXBLIC_H */
diff --git a/graphics/nxmu/Make.defs b/graphics/nxmu/Make.defs
index 21feb883bb1..a45e664e78d 100644
--- a/graphics/nxmu/Make.defs
+++ b/graphics/nxmu/Make.defs
@@ -33,7 +33,7 @@
 #
 ############################################################################
 
-CSRCS += nxmu_kbdin.c nxmu_mouse.c nxmu_openwindow.c nxmu_redrawreq.c
+CSRCS += nxmu_kbdin.c nxmu_mouse.c nxmu_openwindow.c nxmu_redraw.c
 CSRCS += nxmu_releasebkgd.c nxmu_requestbkgd.c nxmu_reportposition.c
 CSRCS += nxmu_sendclient.c nxmu_sendclientwindow.c nxmu_server.c
 CSRCS += nxmu_start.c
diff --git a/graphics/nxmu/nxmu.h b/graphics/nxmu/nxmu.h
index f5a8bb36158..7440af48eaf 100644
--- a/graphics/nxmu/nxmu.h
+++ b/graphics/nxmu/nxmu.h
@@ -205,13 +205,28 @@ void nxmu_reportposition(FAR struct nxbe_window_s *wnd);
  * Name: nxmu_redrawreq
  *
  * Description:
- *   Request the client that has this window to redraw the rectangular region.
+ *  Send a message to the client requesting that it to redraw the rectangular
+ *  region in the window.
  *
  ****************************************************************************/
 
 void nxmu_redrawreq(FAR struct nxbe_window_s *wnd,
                     FAR const struct nxgl_rect_s *rect);
 
+/****************************************************************************
+ * Name: nxmu_redraw
+ *
+ * Description:
+ *   Redraw client window data.  This may involve either sending a message
+ *   to the client requesting that it redraw a region of the window.  Or, in
+ *   the base that the window supports a per-window framebuffer, this might
+ *   amount to an immediate redraw from the framebuffer.
+ *
+ ****************************************************************************/
+
+void nxmu_redraw(FAR struct nxbe_window_s *wnd,
+                 FAR const struct nxgl_rect_s *rect);
+
 /****************************************************************************
  * Name: nxmu_mouseinit
  *
diff --git a/graphics/nxmu/nxmu_mouse.c b/graphics/nxmu/nxmu_mouse.c
index 83b074c3669..58e642b6d82 100644
--- a/graphics/nxmu/nxmu_mouse.c
+++ b/graphics/nxmu/nxmu_mouse.c
@@ -54,6 +54,10 @@
  * Private Data
  ****************************************************************************/
 
+/* REVISIT:  These globals will prevent this code from being used in an
+ * environment with more than one display.  FIX ME!
+ */
+
 static struct nxgl_point_s       g_mpos;
 static struct nxgl_point_s       g_mrange;
 static uint8_t                   g_mbutton;
@@ -138,7 +142,7 @@ int nxmu_mousereport(struct nxbe_window_s *wnd)
     {
       /* Yes.. Is the mouse position visible in this window? */
 
-      if (nxbe_visible(wnd, &g_mpos))
+      if (nxbe_isvisible(wnd, &g_mpos))
         {
           /* Yes... Convert the mouse position to window relative
            * coordinates and send it to the client
@@ -198,7 +202,7 @@ int nxmu_mousein(FAR struct nxmu_state_s *nxmu,
       y = g_mrange.y - 1;
     }
 
-  /* Look any change in values */
+  /* Look for any change in values */
 
   if (x != g_mpos.x || y != g_mpos.y || buttons != g_mbutton)
     {
@@ -211,13 +215,13 @@ int nxmu_mousein(FAR struct nxmu_state_s *nxmu,
 
       /* If a button is already down, regard this as part of a mouse drag
        * event. Pass all the following events to the window where the drag
-       * started in.
+       * started in, including the final button release event.
        */
 
-      if (oldbuttons)
+      if (oldbuttons != 0)
         {
           g_mwnd = nxmu_revalidate_g_mwnd(nxmu->be.topwnd);
-          if (g_mwnd && g_mwnd->cb->mousein)
+          if (g_mwnd != NULL && g_mwnd->cb->mousein)
             {
               struct nxclimsg_mousein_s outmsg;
               outmsg.msgid   = NX_CLIMSG_MOUSEIN;
diff --git a/graphics/nxmu/nxmu_openwindow.c b/graphics/nxmu/nxmu_openwindow.c
index a914b13fd6d..a0bfb2ba10c 100644
--- a/graphics/nxmu/nxmu_openwindow.c
+++ b/graphics/nxmu/nxmu_openwindow.c
@@ -160,32 +160,37 @@ void nxmu_openwindow(FAR struct nxbe_state_s *be, FAR struct nxbe_window_s *wnd)
     }
 #endif
 
-  /* Now, insert the new window at the correct position in the hierarchy.
-   * topwnd is never NULL (it may point only at the background window,
-   * however).  If we are in a modal state, then we cannot insert the
-   * window at the top of the display.
-   */
+  /* Is the window being created in the hidden state? */
 
-  if (NXBE_STATE_ISMODAL(be) && be->topwnd->below != NULL)
+  if (!NXBE_ISHIDDEN(wnd))
     {
-      /* We are in a modal state.  The topwnd is not the background and it
-       * has focus.
+      /* No.. Insert the new window at the correct position in the
+       * hierarchy.  topwnd is never NULL (it may point only at the
+       * background window, however).  If we are in a modal state, then we
+       * cannot insert the window at the top of the display.
        */
 
-      wnd->above        = be->topwnd;
-      wnd->below        = be->topwnd->below;
+      if (NXBE_STATE_ISMODAL(be) && be->topwnd->below != NULL)
+        {
+          /* We are in a modal state.  The topwnd is not the background and
+           * it has focus.
+           */
 
-      be->topwnd->below = wnd;
-    }
-  else
-    {
-      /* Otherwise insert the new window at the top on the display. */
+          wnd->above        = be->topwnd;
+          wnd->below        = be->topwnd->below;
 
-      wnd->above        = NULL;
-      wnd->below        = be->topwnd;
+          be->topwnd->below = wnd;
+        }
+      else
+        {
+          /* Otherwise insert the new window at the top on the display. */
 
-      be->topwnd->above = wnd;
-      be->topwnd        = wnd;
+          wnd->above        = NULL;
+          wnd->below        = be->topwnd;
+
+          be->topwnd->above = wnd;
+          be->topwnd        = wnd;
+        }
     }
 
   /* Report the initial size/position of the window to the client */
diff --git a/graphics/nxmu/nxmu_redraw.c b/graphics/nxmu/nxmu_redraw.c
new file mode 100644
index 00000000000..22917847372
--- /dev/null
+++ b/graphics/nxmu/nxmu_redraw.c
@@ -0,0 +1,195 @@
+/****************************************************************************
+ * graphics/nxmu/nxmu_redraw.c
+ *
+ *   Copyright (C) 2008-2009, 2011-2012, 2019 Gregory Nutt. All rights
+ *     reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include "nxmu.h"
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nxmu_redraw_pwfb
+ *
+ * Description:
+ *   Redraw into the per-window framebuffer
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NX_RAMBACKED
+static inline void nxmu_redraw_pwfb(FAR struct nxbe_window_s *wnd,
+                                    FAR const struct nxgl_rect_s *rect)
+{
+  FAR const void *src[CONFIG_NX_NPLANES];
+  struct nxgl_rect_s wndrect;
+  struct nxgl_point_s origin;
+  unsigned int bpp;
+
+  /* Put the rectangle back relative to the window */
+
+  nxgl_rectoffset(&wndrect, rect,
+                  -wnd->bounds.pt1.x, -wnd->bounds.pt1.y);
+
+  /* Get the source of address of the rectangle in the framebuffer. */
+
+  bpp    = wnd->be->plane[0].pinfo.bpp;
+  src[0] = (FAR const void *)((FAR uint8_t *)wnd->fbmem +
+                               wndrect.pt1.y * wnd->stride +
+                               ((bpp * wndrect.pt1.x) >> 3));
+
+  /* For resolutions less than 8-bits, the starting pixel will be contained
+   * in the byte pointed to by src[0]but may not be properly aligned for the
+   * transfer.  We fix this by modifying the origin.
+   */
+
+  origin.x = wndrect.pt1.x;
+  origin.y = wndrect.pt1.y;
+
+  switch (bpp)
+    {
+#ifndef CONFIG_NX_DISABLE_1BPP
+      case 1:  /* 1 bit per pixel */
+        {
+          origin.x &= ~7;
+        }
+        break;
+#endif
+
+#ifndef CONFIG_NX_DISABLE_2BPP
+      case 2:  /* 2 bits per pixel */
+        {
+          origin.x &= ~3;
+        }
+        break;
+#endif
+
+#ifndef CONFIG_NX_DISABLE_4BPP
+      case 4:  /* 4 bits per pixel */
+        {
+          origin.x &= ~1;
+        }
+        break;
+#endif
+
+      default:
+        break;
+    }
+
+  /* And render the bitmap into device graphics memory */
+
+  nxbe_flush(wnd, &wndrect, src, &origin, wnd->stride);
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nxmu_redrawreq
+ *
+ * Description:
+ *  Send a message to the client requesting that it to redraw the rectangular
+ *  region in the window.
+ *
+ ****************************************************************************/
+
+void nxmu_redrawreq(FAR struct nxbe_window_s *wnd,
+                    FAR const struct nxgl_rect_s *rect)
+{
+  struct nxclimsg_redraw_s outmsg;
+
+  /* Send the client redraw message */
+
+  outmsg.msgid = NX_CLIMSG_REDRAW;
+  outmsg.wnd   = wnd;
+  outmsg.more  = false;
+  nxgl_rectoffset(&outmsg.rect, rect,
+                  -wnd->bounds.pt1.x, -wnd->bounds.pt1.y);
+
+  (void)nxmu_sendclientwindow(wnd, &outmsg,
+                              sizeof(struct nxclimsg_redraw_s));
+}
+
+/****************************************************************************
+ * Name: nxmu_redraw
+ *
+ * Description:
+ *   Redraw client window data.  This may involve either sending a message
+ *   to the client requesting that it redraw a region of the window.  Or, in
+ *   the base that the window supports a per-window framebuffer, this might
+ *   amount to an immediate redraw from the framebuffer.
+ *
+ ****************************************************************************/
+
+void nxmu_redraw(FAR struct nxbe_window_s *wnd,
+                 FAR const struct nxgl_rect_s *rect)
+{
+  /* Don't update hidden windows */
+
+  if (!NXBE_ISHIDDEN(wnd))
+    {
+#ifdef CONFIG_NX_RAMBACKED
+      /* If this window supports a pre-window frame buffer, then we can just
+       * update the device content from that framebuffer.
+       */
+
+      if (NXBE_ISRAMBACKED(wnd))
+        {
+          nxmu_redraw_pwfb(wnd, rect);
+        }
+
+      /* Otherwise, send a message to the client requesting an update of the
+       * affected region in the window.
+       */
+
+      else
+#endif
+        {
+          nxmu_redrawreq(wnd, rect);
+        }
+    }
+}
diff --git a/graphics/nxmu/nxmu_redrawreq.c b/graphics/nxmu/nxmu_redrawreq.c
deleted file mode 100644
index 48032bcb205..00000000000
--- a/graphics/nxmu/nxmu_redrawreq.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/****************************************************************************
- * graphics/nxmu/nxmu_redrawreq.c
- *
- *   Copyright (C) 2008-2009, 2011-2012, 2019 Gregory Nutt. All rights
- *     reserved.
- *   Author: Gregory Nutt 
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include 
-
-#include 
-#include 
-#include 
-
-#include 
-#include "nxmu.h"
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: nxmu_redrawreq
- *
- * Description:
- *   Request the client that has this window to redraw the rectangular region.
- *
- ****************************************************************************/
-
-void nxmu_redrawreq(FAR struct nxbe_window_s *wnd,
-                    FAR const struct nxgl_rect_s *rect)
-{
-#ifdef CONFIG_NX_RAMBACKED
-  /* If this window supports a pre-window frame buffer, then we can just
-   * update the device content from that framebuffer.
-   */
-
-  if (NXBE_ISRAMBACKED(wnd))
-    {
-      FAR const void *src[CONFIG_NX_NPLANES];
-      struct nxgl_rect_s wndrect;
-      struct nxgl_point_s origin;
-      unsigned int bpp;
-
-      /* Put the rectangle back relative to the window */
-
-      nxgl_rectoffset(&wndrect, rect,
-                      -wnd->bounds.pt1.x, -wnd->bounds.pt1.y);
-
-      /* Get the source of address of the rectangle in the framebuffer. */
-
-      bpp    = wnd->be->plane[0].pinfo.bpp;
-      src[0] = (FAR const void *)
-               ((FAR uint8_t *)wnd->fbmem +
-                wndrect.pt1.y * wnd->stride +
-               ((bpp * wndrect.pt1.x) >> 3));
-
-      /* For resolutions less than 8-bits, the starting pixel will be
-       * contained in the byte pointed to by src[0]but may not be properly
-       * aligned for the transfer.  We fix this by modifying the origin.
-       */
-
-      origin.x = wndrect.pt1.x;
-      origin.y = wndrect.pt1.y;
-
-      switch (bpp)
-        {
-#ifndef CONFIG_NX_DISABLE_1BPP
-          case 1:  /* 1 bit per pixel */
-            {
-              origin.x &= ~7;
-            }
-            break;
-#endif
-
-#ifndef CONFIG_NX_DISABLE_2BPP
-          case 2:  /* 2 bits per pixel */
-            {
-              origin.x &= ~3;
-            }
-            break;
-#endif
-
-#ifndef CONFIG_NX_DISABLE_4BPP
-          case 4:  /* 4 bits per pixel */
-            {
-              origin.x &= ~1;
-            }
-            break;
-#endif
-
-          default:
-            break;
-        }
-
-      /* And render the bitmap into device graphics memory */
-
-      nxbe_flush(wnd, &wndrect, src, &origin, wnd->stride);
-    }
-  else
-#endif
-    {
-      struct nxclimsg_redraw_s outmsg;
-
-      /* Send the client redraw message */
-
-      outmsg.msgid = NX_CLIMSG_REDRAW;
-      outmsg.wnd   = wnd;
-      outmsg.more  = false;
-      nxgl_rectoffset(&outmsg.rect, rect,
-                      -wnd->bounds.pt1.x, -wnd->bounds.pt1.y);
-
-      (void)nxmu_sendclientwindow(wnd, &outmsg,
-                                  sizeof(struct nxclimsg_redraw_s));
-    }
-}
diff --git a/graphics/nxmu/nxmu_releasebkgd.c b/graphics/nxmu/nxmu_releasebkgd.c
index e2209f3a9e6..618d9a17679 100644
--- a/graphics/nxmu/nxmu_releasebkgd.c
+++ b/graphics/nxmu/nxmu_releasebkgd.c
@@ -80,5 +80,5 @@ void nxmu_releasebkgd(FAR struct nxmu_state_s *nxmu)
 
   /* Redraw the background window */
 
-  nxmu_redrawreq(&be->bkgd, &be->bkgd.bounds);
+  nxmu_redraw(&be->bkgd, &be->bkgd.bounds);
 }
diff --git a/graphics/nxmu/nxmu_requestbkgd.c b/graphics/nxmu/nxmu_requestbkgd.c
index 4c1cd97a85b..8b19021882c 100644
--- a/graphics/nxmu/nxmu_requestbkgd.c
+++ b/graphics/nxmu/nxmu_requestbkgd.c
@@ -89,7 +89,7 @@ void nxmu_requestbkgd(FAR struct nxmu_conn_s *conn,
 
   /* Redraw the background window */
 
-  nxmu_redrawreq(&be->bkgd, &be->bkgd.bounds);
+  nxmu_redraw(&be->bkgd, &be->bkgd.bounds);
 
 #ifdef CONFIG_NX_XYINPUT
   /* Provide the mouse settings */
diff --git a/graphics/nxmu/nxmu_server.c b/graphics/nxmu/nxmu_server.c
index daf556d3550..50985277725 100644
--- a/graphics/nxmu/nxmu_server.c
+++ b/graphics/nxmu/nxmu_server.c
@@ -380,7 +380,7 @@ int nx_runinstance(FAR const char *mqname, FAR NX_DRIVERTYPE *dev)
          case NX_SVRMSG_CURSOR_ENABLE: /* Enable/disable cursor */
            {
              FAR struct nxsvrmsg_curenable_s *enabmsg = (FAR struct nxsvrmsg_curenable_s *)buffer;
-             nxbe_cursor_enable(&nxwm.be, enabmsg->enable);
+             nxbe_cursor_enable(&nxmu.be, enabmsg->enable);
            }
            break;
 
@@ -388,14 +388,14 @@ int nx_runinstance(FAR const char *mqname, FAR NX_DRIVERTYPE *dev)
          case NX_SVRMSG_CURSOR_IMAGE: /* Set cursor image */
            {
              FAR struct nxsvrmsg_curimage_s *imgmsg = (FAR struct nxsvrmsg_curimage_s *)buffer;
-             nxbe_cursor_setimage(&nxwm.be, imgmsg->image);
+             nxbe_cursor_setimage(&nxmu.be, &imgmsg->image);
            }
            break;
 #endif
          case NX_SVRMSG_CURSOR_SETPOS: /* Set cursor position */
            {
              FAR struct nxsvrmsg_curpos_s *posmsg = (FAR struct nxsvrmsg_curpos_s *)buffer;
-             nxbe_cursor_setposition(&nxwm.be, &posmsg->pos);
+             nxbe_cursor_setposition(&nxmu.be, &posmsg->pos);
            }
            break;
 #endif
@@ -455,6 +455,14 @@ int nx_runinstance(FAR const char *mqname, FAR NX_DRIVERTYPE *dev)
            }
            break;
 
+         case NX_SVRMSG_SETVISIBILITY: /* Show or hide a window */
+           {
+             FAR struct nxsvrmsg_setvisibility_s *vismsg =
+               (FAR struct nxsvrmsg_setvisibility_s *)buffer;
+             nxbe_setvisibility(vismsg->wnd, vismsg->hide);
+           }
+           break;
+
          case NX_SVRMSG_SETPIXEL: /* Set a single pixel in the window with a color */
            {
              FAR struct nxsvrmsg_setpixel_s *setmsg = (FAR struct nxsvrmsg_setpixel_s *)buffer;
@@ -543,7 +551,7 @@ int nx_runinstance(FAR const char *mqname, FAR NX_DRIVERTYPE *dev)
          case NX_SVRMSG_REDRAWREQ: /* Request re-drawing of rectangular region */
            {
              FAR struct nxsvrmsg_redrawreq_s *redrawmsg = (FAR struct nxsvrmsg_redrawreq_s *)buffer;
-             nxmu_redrawreq(redrawmsg->wnd, &redrawmsg->rect);
+             nxmu_redraw(redrawmsg->wnd, &redrawmsg->rect);
            }
            break;
 
diff --git a/graphics/nxterm/Make.defs b/graphics/nxterm/Make.defs
index 24673b2a726..58d78edd170 100644
--- a/graphics/nxterm/Make.defs
+++ b/graphics/nxterm/Make.defs
@@ -1,7 +1,7 @@
 ############################################################################
 # graphics/nxterm/Make.defs
 #
-#   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+#   Copyright (C) 2012, 2019 Gregory Nutt. All rights reserved.
 #   Author: Gregory Nutt 
 #
 # Redistribution and use in source and binary forms, with or without
@@ -36,7 +36,7 @@
 ifeq ($(CONFIG_NXTERM),y)
 
 CSRCS += nx_register.c nxterm_driver.c nxterm_font.c nxterm_putc.c
-CSRCS += nxterm_redraw.c nxterm_register.c nxterm_scroll.c
+CSRCS += nxterm_redraw.c nxterm_resize.c nxterm_register.c nxterm_scroll.c
 CSRCS += nxterm_vt100.c nxtk_register.c nxtool_register.c nxterm_clear.c
 
 ifneq ($(CONFIG_DISABLE_PSEUDOFS_OPERATIONS),y)
diff --git a/graphics/nxterm/nxterm.h b/graphics/nxterm/nxterm.h
index 02bea4b09c3..27f6011c322 100644
--- a/graphics/nxterm/nxterm.h
+++ b/graphics/nxterm/nxterm.h
@@ -173,9 +173,7 @@ struct nxterm_state_s
    * retained in the f_priv field of the 'struct file'.
    */
 
-#ifndef CONFIG_DISABLE_POLL
   struct pollfd *fds[CONFIG_NXTERM_NPOLLWAITERS];
-#endif
 #endif /* CONFIG_NXTERM_NXKBDIN */
 };
 
@@ -210,12 +208,21 @@ FAR struct nxterm_state_s *nxterm_register(NXTERM handle,
 void nxterm_unregister(FAR struct nxterm_state_s *priv);
 #endif
 
+/* Driver methods */
+
 #ifdef CONFIG_NXTERM_NXKBDIN
 ssize_t nxterm_read(FAR struct file *filep, FAR char *buffer, size_t len);
-#ifndef CONFIG_DISABLE_POLL
 int nxterm_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup);
 #endif
+
+/* IOCTL handlers */
+
+void nxterm_redraw(NXTERM handle, FAR const struct nxgl_rect_s *rect,
+                   bool more);
+#ifdef CONFIG_NXTERM_NXKBDIN
+void nxterm_kbdin(NXTERM handle, FAR const uint8_t *buffer, uint8_t buflen);
 #endif
+int nxterm_resize(NXTERM handle, FAR const struct nxgl_size_s *size);
 
 /* VT100 Terminal emulation */
 
diff --git a/graphics/nxterm/nxterm_driver.c b/graphics/nxterm/nxterm_driver.c
index a2abf2a2b92..81874c0e071 100644
--- a/graphics/nxterm/nxterm_driver.c
+++ b/graphics/nxterm/nxterm_driver.c
@@ -59,6 +59,8 @@ static int     nxterm_open(FAR struct file *filep);
 static int     nxterm_close(FAR struct file *filep);
 static ssize_t nxterm_write(FAR struct file *filep, FAR const char *buffer,
                  size_t buflen);
+static int     nxterm_ioctl(FAR struct file *filep, int cmd,
+                            unsigned long arg);
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
 static int     nxterm_unlink(FAR struct inode *inode);
 #endif
@@ -77,12 +79,9 @@ const struct file_operations g_nxterm_drvrops =
   nxterm_close, /* close */
   nxterm_read,  /* read */
   nxterm_write, /* write */
-  0,            /* seek */
-  0             /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  ,
+  NULL,         /* seek */
+  nxterm_ioctl, /* ioctl */
   nxterm_poll   /* poll */
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   ,
   nxterm_unlink /* unlink */
@@ -95,14 +94,11 @@ const struct file_operations g_nxterm_drvrops =
 {
   nxterm_open,  /* open */
   nxterm_close, /* close */
-  0,            /* read */
+  NULL,         /* read */
   nxterm_write, /* write */
-  0,            /* seek */
-  0             /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
-  ,
-  0             /* poll */
-#endif
+  NULL,         /* seek */
+  nxterm_ioctl, /* ioctl */
+  NULL          /* poll */
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   ,
   nxterm_unlink /* unlink */
@@ -315,6 +311,23 @@ static ssize_t nxterm_write(FAR struct file *filep, FAR const char *buffer,
   return (ssize_t)buflen;
 }
 
+/****************************************************************************
+ * Name: nxterm_ioctl
+ ****************************************************************************/
+
+static int nxterm_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
+{
+  /* NOTE:  We don't need driver context here because the NXTERM handle
+   * provided within each of the NXTERM IOCTL command data.  Mutual
+   * exclusion is similar managed by the IOCTL cmmand hendler.
+   *
+   * This permits the IOCTL to be called in abnormal context (such as
+   * from boardctl())
+   */
+
+  return nxterm_ioctl_tap(cmd, arg);
+}
+
 /****************************************************************************
  * Name: nxterm_unlink
  ****************************************************************************/
@@ -362,3 +375,87 @@ static int nxterm_unlink(FAR struct inode *inode)
  * Public Functions
  ****************************************************************************/
 
+/****************************************************************************
+ * Name: nxterm_ioctl_tap
+ *
+ * Description:
+ *   Execute an NXTERM IOCTL command from an external caller.
+ *
+ * NOTE:  We don't need driver context here because the NXTERM handle
+ * provided within each of the NXTERM IOCTL command data.  Mutual
+ * exclusion is similar managed by the IOCTL cmmand hendler.
+ *
+ * This permits the IOCTL to be called in abnormal context (such as
+ * from boardctl())
+ *
+ ****************************************************************************/
+
+int nxterm_ioctl_tap(int cmd, uintptr_t arg)
+{
+  int ret;
+
+  switch (cmd)
+    {
+      /* CMD:           NXTERMIOC_NXTERM_REDRAW
+       * DESCRIPTION:   Re-draw a portion of the NX console.  This function
+       *                should be called from the appropriate window callback
+       *                logic.
+       * ARG:           A reference readable instance of struct
+       *                nxtermioc_redraw_s
+       * CONFIGURATION: CONFIG_NXTERM
+       */
+
+       case NXTERMIOC_NXTERM_REDRAW:
+         {
+           FAR struct nxtermioc_redraw_s *redraw =
+             (FAR struct nxtermioc_redraw_s *)((uintptr_t)arg);
+
+           nxterm_redraw(redraw->handle, &redraw->rect, redraw->more);
+           ret = OK;
+         }
+         break;
+
+      /* CMD:           NXTERMIOC_NXTERM_KBDIN
+       * DESCRIPTION:   Provide NxTerm keyboard input to NX.
+       * ARG:           A reference readable instance of struct
+       *                nxtermioc_kbdin_s
+       * CONFIGURATION: CONFIG_NXTERM_NXKBDIN
+       */
+
+       case NXTERMIOC_NXTERM_KBDIN:
+         {
+#ifdef CONFIG_NXTERM_NXKBDIN
+           FAR struct nxtermioc_kbdin_s *kbdin =
+             (FAR struct nxtermioc_kbdin_s *)((uintptr_t)arg);
+
+           nxterm_kbdin(kbdin->handle, kbdin->buffer, kbdin->buflen);
+           ret = OK;
+#else
+           ret = -ENOSYS;
+#endif
+         }
+         break;
+
+      /* CMD:           NXTERMIOC_NXTERM_RESIZE
+       * DESCRIPTION:   Inform NxTerm keyboard the the size of the window has
+       *                changed
+       * ARG:           A reference readable instance of struct nxtermioc_resize_s
+       * CONFIGURATION: CONFIG_NXTERM
+       */
+
+       case NXTERMIOC_NXTERM_RESIZE:
+         {
+           FAR struct nxtermioc_resize_s *resize =
+             (FAR struct nxtermioc_resize_s *)((uintptr_t)arg);
+
+           ret = nxterm_resize(resize->handle, &resize->size);
+         }
+         break;
+
+      default:
+        ret = -ENOTTY;
+        break;
+    }
+
+  return ret;
+}
diff --git a/graphics/nxterm/nxterm_kbdin.c b/graphics/nxterm/nxterm_kbdin.c
index 00cccb1d506..bff320e652d 100644
--- a/graphics/nxterm/nxterm_kbdin.c
+++ b/graphics/nxterm/nxterm_kbdin.c
@@ -60,8 +60,8 @@
  * Name: nxterm_pollnotify
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
-static void nxterm_pollnotify(FAR struct nxterm_state_s *priv, pollevent_t eventset)
+static void nxterm_pollnotify(FAR struct nxterm_state_s *priv,
+                              pollevent_t eventset)
 {
   FAR struct pollfd *fds;
   irqstate_t flags;
@@ -85,9 +85,6 @@ static void nxterm_pollnotify(FAR struct nxterm_state_s *priv, pollevent_t event
       leave_critical_section(flags);
     }
 }
-#else
-#  define nxterm_pollnotify(priv,event)
-#endif
 
 /****************************************************************************
  * Public Functions
@@ -240,12 +237,10 @@ ssize_t nxterm_read(FAR struct file *filep, FAR char *buffer, size_t len)
 
 errout_without_sem:
 
-#ifndef CONFIG_DISABLE_POLL
   if (nread > 0)
     {
       nxterm_pollnotify(priv, POLLOUT);
     }
-#endif
 
   /* Return the number of characters actually read */
 
@@ -256,7 +251,6 @@ errout_without_sem:
  * Name: nxterm_poll
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_POLL
 int nxterm_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup)
 {
   FAR struct inode *inode = filep->f_inode;
@@ -355,7 +349,6 @@ errout:
   nxterm_sempost(priv);
   return ret;
 }
-#endif
 
 /****************************************************************************
  * Name: nxterm_kbdin
@@ -464,11 +457,9 @@ void nxterm_kbdin(NXTERM handle, FAR const uint8_t *buffer, uint8_t buflen)
           nxsem_post(&priv->waitsem);
         }
 
-      /* Notify all poll/select waiters that they can write to the FIFO */
+      /* Notify all poll/select waiters that they can read from the FIFO */
 
-#ifndef CONFIG_DISABLE_POLL
       nxterm_pollnotify(priv, POLLIN);
-#endif
       sched_unlock();
     }
 
diff --git a/graphics/nxterm/nxterm_redraw.c b/graphics/nxterm/nxterm_redraw.c
index 5d76d1c1d6e..22aaafa87e8 100644
--- a/graphics/nxterm/nxterm_redraw.c
+++ b/graphics/nxterm/nxterm_redraw.c
@@ -1,5 +1,5 @@
 /****************************************************************************
- * nuttx/graphics/nxterm/nxterm_bkgd.c
+ * nuttx/graphics/nxterm/nxterm_redraw.c
  *
  *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt 
diff --git a/graphics/nxterm/nxterm_resize.c b/graphics/nxterm/nxterm_resize.c
new file mode 100644
index 00000000000..c4730fa4139
--- /dev/null
+++ b/graphics/nxterm/nxterm_resize.c
@@ -0,0 +1,108 @@
+/****************************************************************************
+ * nuttx/graphics/nxterm/nxterm_resize.c
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt 
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#include "nxterm.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nxterm_resize
+ *
+ * Description:
+ *   This function handles the IOCTL resize command.  It indicates that the
+ *   size of the NxTerm window has changed and needs to be updated.
+ *
+ * Input Parameters:
+ *   handle - A handle previously returned by nx_register, nxtk_register, or
+ *     nxtool_register.
+ *   size   - The new window size
+ *
+ * Returned Value:
+ *   None
+ *
+ ****************************************************************************/
+
+int nxterm_resize(NXTERM handle, FAR const struct nxgl_size_s *size)
+{
+  FAR struct nxterm_state_s *priv;
+  int ret;
+
+  DEBUGASSERT(handle != NULL && size != NULL);
+  ginfo("size={%d,%d)\n", size->w, size->h);
+
+  /* Recover our private state structure */
+
+  priv = (FAR struct nxterm_state_s *)handle;
+
+  /* Get exclusive access to the state structure */
+
+  ret = nxterm_semwait(priv);
+  if (ret < 0)
+    {
+      /* The only expected error is if the wait failed because of it was
+       * interrupted by a signal or if the thread was canceled.
+       */
+
+      DEBUGASSERT(ret == -EINTR || ret == -ECANCELED);
+      return ret;
+    }
+
+  /* Set the new window size.
+   * REVISIT:  Should other things be reset as well?
+   */
+
+  priv->wndo.wsize.w = size->w;
+  priv->wndo.wsize.h = size->h;
+
+  (void)nxterm_sempost(priv);
+  return true;
+}
diff --git a/graphics/nxterm/nxterm_sem.c b/graphics/nxterm/nxterm_sem.c
index c54bed93f0b..9b1a70560f1 100644
--- a/graphics/nxterm/nxterm_sem.c
+++ b/graphics/nxterm/nxterm_sem.c
@@ -98,11 +98,9 @@ int nxterm_semwait(FAR struct nxterm_state_s *priv)
 
 int nxterm_sempost(FAR struct nxterm_state_s *priv)
 {
-  pid_t me = getpid();
-
   /* Make sure that I really hold the semaphore */
 
-  DEBUGASSERT(priv->holder == me);
+  DEBUGASSERT(priv->holder == getpid());
 
   /* Then let go of it */
 
diff --git a/graphics/vnc/server/Kconfig b/graphics/vnc/server/Kconfig
index bb96d3f9889..cf7fca29b32 100644
--- a/graphics/vnc/server/Kconfig
+++ b/graphics/vnc/server/Kconfig
@@ -112,8 +112,25 @@ config VNCSERVER_UPDATE_BUFSIZE
 		example, an update buffers of 32 pixels at 8-bits per pixel and
 		32-rows would yield a buffer size of 1024!
 
-		Ideally, this buffer should fit in one network packet to avoid
-		accessive re-assembly of partial TCP packets.
+		There is a very strong interaction with this setting and the network MTU.
+		Ideally, this buffer should fit in one network packet to avoid accessive
+		re-assembly of partial TCP packets.
+
+		REVISIT:  In fact, if the buffer does not fit in one network packet,
+		then there appears to be reliability issues in the connection.  I am
+		not sure why that is; TCP is a stream so it should not matter how
+		many packets are in a transfer.
+
+		Example:  Negotiated pixel depth = 8 BPP, window width = 800 pixels.
+		CONFIG_VNCSERVER_UPDATE_BUFSIZE needs to be the payload size (MSS)
+		of the transfer or 800 bytes.  The MTU is then:
+
+		  MSS = MTU - sizeof(IP Header) - sizeof(VNC FramebufferUpdate Header)
+
+		For IPv4, the IP Header is 20 bytes; 40 bytes for IPv6.  The
+		FramebufferUpdate header is 16 bytes so.  The desired MSS is 800 bytes
+		so MTU = 836 or 856.  For Ethernet, this is a total packet size of 870
+		bytes.
 
 config VNCSERVER_KBDENCODE
 	bool "Encode keyboard input"
diff --git a/graphics/vnc/server/vnc_color.c b/graphics/vnc/server/vnc_color.c
index 8543cf7866e..517f58de59c 100644
--- a/graphics/vnc/server/vnc_color.c
+++ b/graphics/vnc/server/vnc_color.c
@@ -155,7 +155,7 @@ uint8_t vnc_convert_rgb8_332(lfb_color_t rgb)
    *          RRRGGGBB
    */
 
-  return (uint8_t)(((rgb >> 8) & 0x0070)  |
+  return (uint8_t)(((rgb >> 8) & 0x00e0)  |
                    ((rgb >> 6) & 0x001c)  |
                    ((rgb >> 3) & 0x0003));
 }
diff --git a/graphics/vnc/server/vnc_fbdev.c b/graphics/vnc/server/vnc_fbdev.c
index 999b40f0b65..407b1f1592f 100644
--- a/graphics/vnc/server/vnc_fbdev.c
+++ b/graphics/vnc/server/vnc_fbdev.c
@@ -132,12 +132,12 @@ static int up_setcursor(FAR struct fb_vtable_s *vtable,
 /* Current cursor position */
 
 #ifdef CONFIG_FB_HWCURSOR
-static struct cursor_pos_s g_cpos;
+static struct fb_cursorpos_s g_cpos;
 
 /* Current cursor size */
 
 #ifdef CONFIG_FB_HWCURSORSIZE
-static struct cursor_size_s g_csize;
+static struct fb_cursorsize_s g_csize;
 #endif
 #endif
 
@@ -871,7 +871,7 @@ void nx_notify_rectangle(FAR NX_PLANEINFOTYPE *pinfo,
 
   DEBUGASSERT(pinfo != NULL && rect != NULL);
 
-  /* Recover the session informatin from the display number in the planeinfo
+  /* Recover the session information from the display number in the planeinfo
    * structure.
    */
 
diff --git a/graphics/vnc/server/vnc_keymap.c b/graphics/vnc/server/vnc_keymap.c
index 6914fde0f15..5e828d8da1c 100644
--- a/graphics/vnc/server/vnc_keymap.c
+++ b/graphics/vnc/server/vnc_keymap.c
@@ -651,4 +651,4 @@ void vnc_kbdout(FAR void *arg, uint8_t nch, FAR const uint8_t *ch)
   (void)nx_kbdin((NXHANDLE)arg, nch, ch);
 }
 
-#endif /* CONFIG_NX_KBD */
\ No newline at end of file
+#endif /* CONFIG_NX_KBD */
diff --git a/graphics/vnc/server/vnc_raw.c b/graphics/vnc/server/vnc_raw.c
index 383849fd818..acd195d989e 100644
--- a/graphics/vnc/server/vnc_raw.c
+++ b/graphics/vnc/server/vnc_raw.c
@@ -164,7 +164,8 @@ static size_t vnc_copy16(FAR struct vnc_session_s *session,
 
   /* Source rectangle start address (left/top)*/
 
-  srcleft = (FAR lfb_color_t *)(session->fb + RFB_STRIDE * row + RFB_BYTESPERPIXEL * col);
+  srcleft = (FAR lfb_color_t *)
+    (session->fb + RFB_STRIDE * row + RFB_BYTESPERPIXEL * col);
 
   /* Transfer each row from the source buffer into the update buffer */
 
@@ -235,7 +236,8 @@ static size_t vnc_copy32(FAR struct vnc_session_s *session,
 
   /* Source rectangle start address (left/top)*/
 
-  srcleft = (FAR lfb_color_t *)(session->fb + RFB_STRIDE * row + RFB_BYTESPERPIXEL * col);
+  srcleft = (FAR lfb_color_t *)
+    (session->fb + RFB_STRIDE * row + RFB_BYTESPERPIXEL * col);
 
   /* Transfer each row from the source buffer into the update buffer */
 
@@ -405,7 +407,7 @@ int vnc_raw(FAR struct vnc_session_s *session, FAR struct nxgl_rect_s *rect)
           updheight = srcheight;
         }
 
-      /* Loop until this horizontal swath has sent to the VNC client.
+      /* Loop until this horizontal swath has been sent to the VNC client.
        * Start with the leftmost pixel and transfer rectangles
        * horizontally with width of destwidth until all srcwidth
        * columns have been transferred (the last rectangle may be
@@ -504,4 +506,4 @@ int vnc_raw(FAR struct vnc_session_s *session, FAR struct nxgl_rect_s *rect)
     }
 
   return OK;
-}
\ No newline at end of file
+}
diff --git a/graphics/vnc/server/vnc_receiver.c b/graphics/vnc/server/vnc_receiver.c
index efa97283dd5..6d8e452e914 100644
--- a/graphics/vnc/server/vnc_receiver.c
+++ b/graphics/vnc/server/vnc_receiver.c
@@ -280,7 +280,7 @@ int vnc_receiver(FAR struct vnc_session_s *session)
 
               ginfo("Received FramebufferUpdateRequest\n");
 
-              /* Read the rest of the SetPixelFormat message */
+              /* Read the rest of the FramebufferUpdateRequest message */
 
               ret = vnc_read_remainder(session,
                                        sizeof(struct rfb_fbupdatereq_s) - 1,
diff --git a/graphics/vnc/server/vnc_rre.c b/graphics/vnc/server/vnc_rre.c
index f33b0921ac0..172c5ae47ed 100644
--- a/graphics/vnc/server/vnc_rre.c
+++ b/graphics/vnc/server/vnc_rre.c
@@ -196,8 +196,8 @@ ssize_t vnc_rre32(FAR struct vnc_session_s *session,
  *   rect  - Describes the rectangle in the local framebuffer.
  *
  * Returned Value:
- *   Zero is returned if RRE coding was not performed (but not error was)
- *   encountered.  Otherwise, the size of the framebuffer update message
+ *   Zero is returned if RRE coding was not performed (but no error was
+ *   encountered).  Otherwise, the size of the framebuffer update message
  *   is returned on success or a negated errno value is returned on failure
  *   that indicates the nature of the failure.  A failure is only
  *   returned in cases of a network failure and unexpected internal failures.
@@ -315,4 +315,4 @@ int vnc_rre(FAR struct vnc_session_s *session, FAR struct nxgl_rect_s *rect)
     }
 
   return 0;
-}
\ No newline at end of file
+}
diff --git a/graphics/vnc/server/vnc_updater.c b/graphics/vnc/server/vnc_updater.c
index 439a952aff3..f12badcd6bc 100644
--- a/graphics/vnc/server/vnc_updater.c
+++ b/graphics/vnc/server/vnc_updater.c
@@ -653,7 +653,7 @@ int vnc_update_rectangle(FAR struct vnc_session_s *session,
           update->whupd = whupd;
           nxgl_rectcopy(&update->rect, &intersection);
 
-          /* Add the upate to the end of the update queue. */
+          /* Add the update to the end of the update queue. */
 
           vnc_add_queue(session, update);
 
@@ -665,7 +665,7 @@ int vnc_update_rectangle(FAR struct vnc_session_s *session,
       sched_unlock();
     }
 
-  /* Since we ignore bad rectangles and wait for updata structures, there is
+  /* Since we ignore bad rectangles and wait for update structures, there is
    * really no way a failure can occur.
    */
 
diff --git a/include/cxx/cstdlib b/include/cxx/cstdlib
index ec632ed054a..714319e4154 100644
--- a/include/cxx/cstdlib
+++ b/include/cxx/cstdlib
@@ -53,6 +53,7 @@ namespace std
 
   using ::srand;
   using ::rand;
+  using ::random;
 
 #ifndef CONFIG_DISABLE_ENVIRON
   // Environment variable support
diff --git a/include/nuttx/addrenv.h b/include/nuttx/addrenv.h
index 0cb854376f2..fdedef20a2e 100644
--- a/include/nuttx/addrenv.h
+++ b/include/nuttx/addrenv.h
@@ -247,7 +247,6 @@
  */
 
 #ifdef CONFIG_BUILD_KERNEL
-#ifndef CONFIG_DISABLE_SIGNALS
 /* This is the type of the signal handler trampoline routine.  This
  * trampoline is called directly from kernel logic.  It simply forwards the
  * signal information to the real signal handler.  When the signal handler
@@ -257,15 +256,12 @@
 
 typedef void (*addrenv_sigtramp_t)(_sa_sigaction_t sighand, int signo,
                                    FAR siginfo_t *info, FAR void *ucontext);
-#endif
 
 /* This structure describes the format of the .bss/.data reserved area */
 
 struct addrenv_reserve_s
 {
-#ifndef CONFIG_DISABLE_SIGNALS
   addrenv_sigtramp_t ar_sigtramp;  /* Signal trampoline */
-#endif
   struct mm_heap_s   ar_usrheap;   /* User space heap structure */
 };
 
diff --git a/include/nuttx/analog/adc.h b/include/nuttx/analog/adc.h
index c54bbc4e8f2..8826c760fb8 100644
--- a/include/nuttx/analog/adc.h
+++ b/include/nuttx/analog/adc.h
@@ -195,10 +195,7 @@ struct adc_dev_s
    * retained in the f_priv field of the 'struct file'.
    */
 
-#if !defined(CONFIG_DISABLE_POLL)
   struct pollfd *fds[CONFIG_ADC_NPOLLWAITERS];
-#endif
-
 #endif /* CONFIG_ADC */
 
   /* Fields provided by lower half ADC logic */
diff --git a/include/nuttx/analog/comp.h b/include/nuttx/analog/comp.h
index 10e3f3b5f51..4b22da721f2 100644
--- a/include/nuttx/analog/comp.h
+++ b/include/nuttx/analog/comp.h
@@ -114,14 +114,13 @@ struct comp_dev_s
   /* Fields managed by common upper half COMP logic */
 
   uint8_t ad_ocount;            /* The number of times the device has been opened */
+  uint8_t val;                 /* Comparator value after output transition event */
   sem_t   ad_sem;               /* Used to serialize access  */
   sem_t   ad_readsem;           /* Blocking read */
 
-#ifndef CONFIG_DISABLE_POLL
-  struct pollfd *d_fds[CONFIG_DEV_COMP_NPOLLWAITERS]; /* pollfds for output transition events */
-  uint8_t        val;           /* Comparator value after output transition event */
-#endif
+  /* pollfd's for output transition events */
 
+  struct pollfd *d_fds[CONFIG_DEV_COMP_NPOLLWAITERS];
 #endif
 
   /* Fields provided by lower half COMP logic */
diff --git a/include/nuttx/arch.h b/include/nuttx/arch.h
index fb7b957da8b..d30d7385ac8 100644
--- a/include/nuttx/arch.h
+++ b/include/nuttx/arch.h
@@ -523,9 +523,7 @@ void up_reprioritize_rtr(FAR struct tcb_s *tcb, uint8_t priority);
  *
  ****************************************************************************/
 
-#ifndef CONFIG_DISABLE_SIGNALS
 void up_schedule_sigaction(FAR struct tcb_s *tcb, sig_deliver_t sigdeliver);
-#endif
 
 /****************************************************************************
  * Name: up_task_start
@@ -617,7 +615,7 @@ void up_pthread_start(pthread_startroutine_t entrypt, pthread_addr_t arg)
  ****************************************************************************/
 
 #if (defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
-     defined(CONFIG_BUILD_KERNEL) && !defined(CONFIG_DISABLE_SIGNALS)
+     defined(CONFIG_BUILD_KERNEL)
 void up_signal_dispatch(_sa_sigaction_t sighand, int signo,
                         FAR siginfo_t *info, FAR void *ucontext);
 #endif
@@ -641,8 +639,7 @@ void up_signal_dispatch(_sa_sigaction_t sighand, int signo,
  *
  ****************************************************************************/
 
-#if (defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__)) && \
-    !defined(CONFIG_DISABLE_SIGNALS)
+#if (defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__))
 void up_signal_handler(_sa_sigaction_t sighand, int signo,
                        FAR siginfo_t *info, FAR void *ucontext)
        noreturn_function;
diff --git a/include/nuttx/can/can.h b/include/nuttx/can/can.h
index e66e0e76981..69f37470f1e 100644
--- a/include/nuttx/can/can.h
+++ b/include/nuttx/can/can.h
@@ -1,7 +1,8 @@
 /************************************************************************************
  * include/nuttx/can/can.h
  *
- *   Copyright (C) 2008, 2009, 2011-2012, 2015-2017 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2008, 2009, 2011-2012, 2015-2017, 2019 Gregory Nutt. All rights
+ *     reserved.
  *   Author: Gregory Nutt 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -48,6 +49,7 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
 
@@ -62,6 +64,7 @@
  ************************************************************************************/
 
 /* Configuration ********************************************************************/
+
 /* CONFIG_CAN - Enables CAN support (MCU-specific selections are also required.  For
  *   STM32, as an example, one or both of CONFIG_STM32_CAN1 or CONFIG_STM32_CAN2
  *   must also be defined)
@@ -106,6 +109,7 @@
 #endif
 
 /* Ioctl Commands *******************************************************************/
+
 /* Ioctl commands supported by the upper half CAN driver.
  *
  * CANIOC_RTR:
@@ -360,6 +364,7 @@
 #endif /* CONFIG_CAN_ERRORS */
 
 /* CAN filter support ***************************************************************/
+
 /* Some CAN hardware supports a notion of prioritizing messages that match filters.
  * Only two priority levels are currently supported and are encoded as defined
  * below:
@@ -377,6 +382,7 @@
 /************************************************************************************
  * Public Types
  ************************************************************************************/
+
 /* CAN-message Format (without Extended ID support)
  *
  *   One based CAN-message is represented with a maximum of 10 bytes.  A message is
@@ -431,6 +437,7 @@ begin_packed_struct struct can_hdr_s
   uint8_t      ch_extid  : 1; /* Extended ID indication */
   uint8_t      ch_unused : 1; /* Unused */
 } end_packed_struct;
+
 #else
 begin_packed_struct struct can_hdr_s
 {
@@ -550,21 +557,27 @@ struct can_ops_s
  * The common logic will initialize all semaphores.
  */
 
+struct can_reader_s
+{
+  struct list_node     list;
+  sem_t                read_sem;
+  FAR struct file     *filep;
+  struct can_rxfifo_s  fifo;             /* Describes receive FIFO */
+};
+
 struct can_dev_s
 {
   uint8_t              cd_ocount;        /* The number of times the device has been opened */
   uint8_t              cd_npendrtr;      /* Number of pending RTR messages */
   volatile uint8_t     cd_ntxwaiters;    /* Number of threads waiting to enqueue a message */
   volatile uint8_t     cd_nrxwaiters;    /* Number of threads waiting to receive a message */
+  struct list_node     cd_readers;       /* Number of readers */
 #ifdef CONFIG_CAN_ERRORS
   uint8_t              cd_error;         /* Flags to indicate internal device errors */
 #endif
   sem_t                cd_closesem;      /* Locks out new opens while close is in progress */
-#ifndef CONFIG_DISABLE_POLL
   sem_t                cd_pollsem;       /* Manages exclusive access to cd_fds[] */
-#endif
   struct can_txfifo_s  cd_xmit;          /* Describes transmit FIFO */
-  struct can_rxfifo_s  cd_recv;          /* Describes receive FIFO */
 #ifdef CONFIG_CAN_TXREADY
   struct work_s        cd_work;          /* Use to manage can_txready() work */
 #endif
@@ -573,9 +586,7 @@ struct can_dev_s
   FAR const struct can_ops_s *cd_ops;    /* Arch-specific operations */
   FAR void            *cd_priv;          /* Used by the arch-specific logic */
 
-#ifndef CONFIG_DISABLE_POLL
   FAR struct pollfd   *cd_fds[CONFIG_CAN_NPOLLWAITERS];
-#endif
 };
 
 /* Structures used with ioctl calls */
diff --git a/include/nuttx/can/mcp2515.h b/include/nuttx/can/mcp2515.h
index 5689f76f1f7..dde0ac67a14 100644
--- a/include/nuttx/can/mcp2515.h
+++ b/include/nuttx/can/mcp2515.h
@@ -54,7 +54,6 @@
 
 /* SPI BUS PARAMETERS *******************************************************/
 
-#define MCP2515_SPI_FREQUENCY    (1000000)        /* 1 MHz */
 #define MCP2515_SPI_MODE         (SPIDEV_MODE0)   /* Device uses SPI Mode 0: CPOL=0, CPHA=0 */
 
 /****************************************************************************
@@ -86,10 +85,6 @@ struct mcp2515_config_s
   uint8_t devid;            /* MCP2515 device ID */
   uint8_t mode;             /* See enum mcp2515_canmod_e */
   uint8_t nfilters;         /* Number of standard/extended filters */
-  uint8_t ntxbuffers;       /* Number of TX Buffer available */
-  uint8_t txbuf0[10];       /* Transmit Buffer 0 */
-  uint8_t txbuf1[10];       /* Transmit Buffer 1 */
-  uint8_t txbuf2[10];       /* Transmit Buffer 2 */
 #ifdef MCP2515_LOOPBACK
   bool loopback;            /* True: Loopback mode */
 #endif
diff --git a/include/nuttx/fs/fs.h b/include/nuttx/fs/fs.h
index fcfc27ca32f..c394650f9e8 100644
--- a/include/nuttx/fs/fs.h
+++ b/include/nuttx/fs/fs.h
@@ -240,9 +240,7 @@ struct file_operations
 
   /* The two structures need not be common after this point */
 
-#ifndef CONFIG_DISABLE_POLL
   int     (*poll)(FAR struct file *filep, struct pollfd *fds, bool setup);
-#endif
 #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
   int     (*unlink)(FAR struct inode *inode);
 #endif
diff --git a/include/nuttx/fs/ioctl.h b/include/nuttx/fs/ioctl.h
index 0e517350ade..8bb12b60d05 100644
--- a/include/nuttx/fs/ioctl.h
+++ b/include/nuttx/fs/ioctl.h
@@ -93,6 +93,7 @@
 #define _MAC802154BASE  (0x2600) /* 802.15.4 MAC ioctl commands */
 #define _PWRBASE        (0x2700) /* Power-related ioctl commands */
 #define _FBIOCBASE      (0x2800) /* Frame buffer character driver ioctl commands */
+#define _NXTERMBASE     (0x2900) /* NxTerm character driver ioctl commands */
 
 /* boardctl() commands share the same number space */
 
@@ -467,8 +468,13 @@
 
 /* Frame buffer character drivers *******************************************/
 
-#define _FBIOCVALID(c)   (_IOC_TYPE(c)==_FBIOCBASE)
-#define _FBIOC(nr)       _IOC(_FBIOCBASE,nr)
+#define _FBIOCVALID(c)    (_IOC_TYPE(c)==_FBIOCBASE)
+#define _FBIOC(nr)        _IOC(_FBIOCBASE,nr)
+
+/* NxTerm character drivers *************************************************/
+
+#define _NXTERMVALID(c)   (_IOC_TYPE(c)==_NXTERMBASE)
+#define _NXTERMIOC(nr)    _IOC(_NXTERMBASE,nr)
 
 /* boardctl() command definitions *******************************************/
 
diff --git a/include/nuttx/input/ads7843e.h b/include/nuttx/input/ads7843e.h
index 3b14507228f..868fcc8a730 100644
--- a/include/nuttx/input/ads7843e.h
+++ b/include/nuttx/input/ads7843e.h
@@ -84,10 +84,6 @@
  * in getting the right configuration.
  */
 
-#ifdef CONFIG_DISABLE_SIGNALS
-#  error "Signals are required.  CONFIG_DISABLE_SIGNALS must not be selected."
-#endif
-
 #ifndef CONFIG_SCHED_WORKQUEUE
 #  error "Work queue support required.  CONFIG_SCHED_WORKQUEUE must be selected."
 #endif
diff --git a/include/nuttx/input/ft5x06.h b/include/nuttx/input/ft5x06.h
index 791f13ee105..90f6946d800 100644
--- a/include/nuttx/input/ft5x06.h
+++ b/include/nuttx/input/ft5x06.h
@@ -74,10 +74,6 @@
  * in getting the right configuration.
  */
 
-#ifdef CONFIG_DISABLE_SIGNALS
-#  error "Signals are required.  CONFIG_DISABLE_SIGNALS must not be selected."
-#endif
-
 #ifndef CONFIG_SCHED_WORKQUEUE
 #  error "Work queue support required.  CONFIG_SCHED_WORKQUEUE must be selected."
 #endif
diff --git a/include/nuttx/input/max11802.h b/include/nuttx/input/max11802.h
index 318c83b7085..f411e8245e0 100644
--- a/include/nuttx/input/max11802.h
+++ b/include/nuttx/input/max11802.h
@@ -86,10 +86,6 @@
  * in getting the right configuration.
  */
 
-#ifdef CONFIG_DISABLE_SIGNALS
-#  error "Signals are required.  CONFIG_DISABLE_SIGNALS must not be selected."
-#endif
-
 #ifndef CONFIG_SCHED_WORKQUEUE
 #  error "Work queue support required.  CONFIG_SCHED_WORKQUEUE must be selected."
 #endif
diff --git a/include/nuttx/input/mxt.h b/include/nuttx/input/mxt.h
index 0923b57a531..5e6296952fd 100644
--- a/include/nuttx/input/mxt.h
+++ b/include/nuttx/input/mxt.h
@@ -87,10 +87,6 @@
  * in getting the right configuration.
  */
 
-#ifdef CONFIG_DISABLE_SIGNALS
-#  error "Signals are required.  CONFIG_DISABLE_SIGNALS must not be selected."
-#endif
-
 #ifndef CONFIG_SCHED_WORKQUEUE
 #  error "Work queue support required.  CONFIG_SCHED_WORKQUEUE must be selected."
 #endif
diff --git a/include/nuttx/input/stmpe811.h b/include/nuttx/input/stmpe811.h
index 9e0b98ada7c..c92dbe3f63f 100644
--- a/include/nuttx/input/stmpe811.h
+++ b/include/nuttx/input/stmpe811.h
@@ -58,7 +58,6 @@
  ********************************************************************************************/
 /* Configuration ****************************************************************************/
 /* Prerequisites:  CONFIG_INPUT=y
- * Other settings that effect the driver: CONFIG_DISABLE_POLL
  *
  * CONFIG_INPUT_STMPE811
  *   Enables support for the STMPE811 driver (Needs CONFIG_INPUT)
@@ -69,8 +68,7 @@
  * CONFIG_STMPE811_MULTIPLE
  *   Can be defined to support multiple STMPE811 devices on board.
  * CONFIG_STMPE811_NPOLLWAITERS
- *   Maximum number of threads that can be waiting on poll() (ignored if
- *   CONFIG_DISABLE_POLL is set).
+ *   Maximum number of threads that can be waiting on poll()
  * CONFIG_STMPE811_TSC_DISABLE
  *   Disable driver touchscreen functionality.
  * CONFIG_STMPE811_ADC_DISABLE
@@ -123,10 +121,6 @@
 #  endif
 #endif
 
-#ifdef CONFIG_DISABLE_SIGNALS
-#  error "Signals are required.  CONFIG_DISABLE_SIGNALS must not be selected."
-#endif
-
 #ifndef CONFIG_SCHED_WORKQUEUE
 #  error "Work queue support required.  CONFIG_SCHED_WORKQUEUE must be selected."
 #endif
diff --git a/include/nuttx/input/tsc2007.h b/include/nuttx/input/tsc2007.h
index 20a832f8707..2a1b5142b26 100644
--- a/include/nuttx/input/tsc2007.h
+++ b/include/nuttx/input/tsc2007.h
@@ -69,10 +69,6 @@
  * in getting the right configuration.
  */
 
-#ifdef CONFIG_DISABLE_SIGNALS
-#  error "Signals are required.  CONFIG_DISABLE_SIGNALS must not be selected."
-#endif
-
 #ifndef CONFIG_SCHED_WORKQUEUE
 #  error "Work queue support required.  CONFIG_SCHED_WORKQUEUE must be selected."
 #endif
diff --git a/include/nuttx/lcd/ft80x.h b/include/nuttx/lcd/ft80x.h
index b0153446b0f..d37d89fdef0 100644
--- a/include/nuttx/lcd/ft80x.h
+++ b/include/nuttx/lcd/ft80x.h
@@ -65,11 +65,8 @@
 /********************************************************************************************
  * Pre-processor Definitions
  ********************************************************************************************/
-/* Configuration ****************************************************************************/
 
-#ifdef CONFIG_DISABLE_SIGNALS
-#  error Signal support is required by this driver
-#endif
+/* Configuration ****************************************************************************/
 
 #if defined(CONFIG_LCD_FT80X_WQVGA)
 #  define FT80X_DISPLAY_WIDTH   480
diff --git a/include/nuttx/lib/float.h b/include/nuttx/lib/float.h
index 2ff2b4252c6..a3ef2d297b7 100644
--- a/include/nuttx/lib/float.h
+++ b/include/nuttx/lib/float.h
@@ -59,18 +59,24 @@
 
 /* Number of base-FLT_RADIX digits in the floating-point significand, p. */
 
-#define FLT_MANT_DIG 24
-
-#ifdef CONFIG_HAVE_DOUBLE
-#  define DBL_MANT_DIG 53
-#else
-#  define DBL_MANT_DIG FLT_MANT_DIG
+#ifndef FLT_MANT_DIG  /* May be defined in a toolchain header */
+#  define FLT_MANT_DIG 24
 #endif
 
-#ifdef CONFIG_HAVE_LONG_DOUBLE
-#  define LDBL_MANT_DIG DBL_MANT_DIG /* FIX ME */
-#else
-#  define LDBL_MANT_DIG DBL_MANT_DIG
+#ifndef DBL_MANT_DIG  /* May be defined in a toolchain header */
+#  ifdef CONFIG_HAVE_DOUBLE
+#    define DBL_MANT_DIG 53
+#  else
+#    define DBL_MANT_DIG FLT_MANT_DIG
+#  endif
+#endif
+
+#ifndef LDBL_MANT_DIG  /* May be defined in a toolchain header */
+#  ifdef CONFIG_HAVE_LONG_DOUBLE
+#    define LDBL_MANT_DIG DBL_MANT_DIG /* FIX ME */
+#  else
+#    define LDBL_MANT_DIG DBL_MANT_DIG
+#  endif
 #endif
 
 /* Number of decimal digits, n, such that any floating-point number in the
@@ -86,140 +92,188 @@
  * b digits and back again without change to the q decimal digits.
  */
 
-#define FLT_DIG 6
-
-#ifdef CONFIG_HAVE_DOUBLE
-#  define DBL_DIG 15  /* 10 */
-#else
-#  define DBL_DIG FLT_DIG
+#ifndef FLT_DIG  /* May be defined in a toolchain header */
+#  define FLT_DIG 6
 #endif
 
-#ifdef CONFIG_HAVE_LONG_DOUBLE
-#  define LDBL_DIG DBL_DIG  /* FIX ME */
-#else
-#  define LDBL_DIG DBL_DIG
+#ifndef DBL_DIG  /* May be defined in a toolchain header */
+#  ifdef CONFIG_HAVE_DOUBLE
+#    define DBL_DIG 15  /* 10 */
+#  else
+#    define DBL_DIG FLT_DIG
+#  endif
+#endif
+
+#ifndef LDBL_DIG  /* May be defined in a toolchain header */
+# ifdef CONFIG_HAVE_LONG_DOUBLE
+#    define LDBL_DIG DBL_DIG  /* FIX ME */
+#  else
+#    define LDBL_DIG DBL_DIG
+#  endif
 #endif
 
 /* Minimum negative integer such that FLT_RADIX raised to that power minus
  * 1 is a normalized floating-point number, emin.
  */
 
-#define FLT_MIN_EXP (-125)
-
-#ifdef CONFIG_HAVE_DOUBLE
-#  define DBL_MIN_EXP (-1021)
-#else
-#  define DBL_MIN_EXP FLT_MIN_EXP
+#ifndef FLT_MIN_EXP  /* May be defined in a toolchain header */
+#  define FLT_MIN_EXP (-125)
 #endif
 
-#ifdef CONFIG_HAVE_LONG_DOUBLE
-#  define LDBL_MIN_EXP DBL_MIN_EXP /* FIX ME */
-#else
-#  define LDBL_MIN_EXP DBL_MIN_EXP
+#ifndef DBL_MIN_EXP  /* May be defined in a toolchain header */
+#  ifdef CONFIG_HAVE_DOUBLE
+#    define DBL_MIN_EXP (-1021)
+#  else
+#    define DBL_MIN_EXP FLT_MIN_EXP
+#  endif
 #endif
 
-/* inimum negative integer such that 10 raised to that power is in the range
+#ifndef LDBL_MIN_EXP  /* May be defined in a toolchain header */
+#  ifdef CONFIG_HAVE_LONG_DOUBLE
+#    define LDBL_MIN_EXP DBL_MIN_EXP /* FIX ME */
+#  else
+#    define LDBL_MIN_EXP DBL_MIN_EXP
+#  endif
+#endif
+
+/* Minimum negative integer such that 10 raised to that power is in the range
  * of normalized floating-point numbers.
  */
 
-#define FLT_MIN_10_EXP (-37)
-
-#ifdef CONFIG_HAVE_DOUBLE
-#  define DBL_MIN_10_EXP (-307)  /* -37 */
-#else
-#  define DBL_MIN_10_EXP FLT_MIN_10_EXP
+#ifndef FLT_MIN_10_EXP  /* May be defined in a toolchain header */
+#  define FLT_MIN_10_EXP (-37)
 #endif
 
-#ifdef CONFIG_HAVE_LONG_DOUBLE
-#  define LDBL_MIN_10_EXP DBL_MIN_10_EXP  /* FIX ME */
-#else
-#  define LDBL_MIN_10_EXP DBL_MIN_10_EXP
+#ifndef DBL_MIN_10_EXP  /* May be defined in a toolchain header */
+#  ifdef CONFIG_HAVE_DOUBLE
+#    define DBL_MIN_10_EXP (-307)  /* -37 */
+#  else
+#    define DBL_MIN_10_EXP FLT_MIN_10_EXP
+#  endif
+#endif
+
+#ifndef LDBL_MIN_10_EXP  /* May be defined in a toolchain header */
+#  ifdef CONFIG_HAVE_LONG_DOUBLE
+#    define LDBL_MIN_10_EXP DBL_MIN_10_EXP  /* FIX ME */
+#  else
+#    define LDBL_MIN_10_EXP DBL_MIN_10_EXP
+#  endif
 #endif
 
 /* Maximum integer such that FLT_RADIX raised to that power minus 1 is a
  * representable finite floating-point number, emax.
  */
 
-#define FLT_MAX_EXP 128
-
-#ifdef CONFIG_HAVE_DOUBLE
-#  define DBL_MAX_EXP 1024
-#else
-#  define DBL_MAX_EXP FLT_MAX_EXP
+#ifndef FLT_MAX_EXP  /* May be defined in a toolchain header */
+#  define FLT_MAX_EXP 128
 #endif
 
-#ifdef CONFIG_HAVE_LONG_DOUBLE
-#  define LDBL_MAX_EXP DBL_MAX_EXP /* FIX ME */
-#else
-#  define LDBL_MAX_EXP DBL_MAX_EXP
+#ifndef DBL_MAX_EXP  /* May be defined in a toolchain header */
+#  ifdef CONFIG_HAVE_DOUBLE
+#    define DBL_MAX_EXP 1024
+#  else
+#    define DBL_MAX_EXP FLT_MAX_EXP
+#  endif
+#endif
+
+#ifndef LDBL_MAX_EXP  /* May be defined in a toolchain header */
+#  ifdef CONFIG_HAVE_LONG_DOUBLE
+#    define LDBL_MAX_EXP DBL_MAX_EXP /* FIX ME */
+#  else
+#    define LDBL_MAX_EXP DBL_MAX_EXP
+#  endif
 #endif
 
 /* Maximum integer such that 10 raised to that power is in the range of
  * representable finite floating-point numbers.
  */
 
-#define FLT_MAX_10_EXP 38  /* 37 */
-
-#ifdef CONFIG_HAVE_DOUBLE
-#  define DBL_MAX_10_EXP 308  /* 37 */
-#else
-#  define DBL_MAX_10_EXP FLT_MAX_10_EXP
+#ifndef FLT_MAX_10_EXP       /* May be defined in toolchain header */
+#  define FLT_MAX_10_EXP 38  /* 37 */
 #endif
 
-#ifdef CONFIG_HAVE_LONG_DOUBLE
-#  define LDBL_MAX_10_EXP DBL_MAX_10_EXP  /* FIX ME */
-#else
-#  define LDBL_MAX_10_EXP DBL_MAX_10_EXP
+#ifndef DBL_MAX_10_EXP          /* May be defined in toolchain header */
+#  ifdef CONFIG_HAVE_DOUBLE
+#    define DBL_MAX_10_EXP 308  /* 37 */
+#  else
+#    define DBL_MAX_10_EXP FLT_MAX_10_EXP
+#  endif
+#endif
+
+#ifndef LDBL_MAX_10_EXP      /* May be defined in toolchain header */
+#  ifdef CONFIG_HAVE_LONG_DOUBLE
+#    define LDBL_MAX_10_EXP DBL_MAX_10_EXP  /* FIX ME */
+#  else
+#    define LDBL_MAX_10_EXP DBL_MAX_10_EXP
+#  endif
 #endif
 
 /* Maximum representable finite floating-point number. */
 
-#define FLT_MAX 3.40282347e+38F  /* 1E+37 */
-
-#ifdef CONFIG_HAVE_DOUBLE
-#  define DBL_MAX 1.7976931348623157e+308  /* 1E+37 */
-#else
-#  define DBL_MAX FLT_MAX
+#ifndef FLT_MAX                    /* May be defined in toolchain header */
+#  define FLT_MAX 3.40282347e+38F  /* 1E+37 */
 #endif
 
-#ifdef CONFIG_HAVE_LONG_DOUBLE
-#  define LDBL_MAX DBL_MAX  /* FIX ME */
-#else
-#  define LDBL_MAX DBL_MAX
+#ifndef DBL_MAX                    /* May be defined in toolchain header */
+#  ifdef CONFIG_HAVE_DOUBLE
+#    define DBL_MAX 1.7976931348623157e+308  /* 1E+37 */
+#  else
+#    define DBL_MAX FLT_MAX
+#  endif
+#endif
+
+#ifndef LDBL_MAX                   /* May be defined in toolchain header */
+#  ifdef CONFIG_HAVE_LONG_DOUBLE
+#    define LDBL_MAX DBL_MAX       /* FIX ME */
+#  else
+#    define LDBL_MAX DBL_MAX
+#  endif
 #endif
 
 /* The difference between 1 and the least value greater than 1 that is
  * representable in the given floating-point type, b1-p.
  */
 
-#define FLT_EPSILON 1.1920929e-07F  /* 1E-5 */
-
-#ifdef CONFIG_HAVE_DOUBLE
-#  define DBL_EPSILON 2.2204460492503131e-16  /* 1E-9 */
-#else
-#  define DBL_EPSILON FLT_EPSILON
+#ifndef FLT_EPSILON                  /* May be defined in toolchain header */
+#  define FLT_EPSILON 1.1920929e-07F /* 1E-5 */
 #endif
 
-#ifdef CONFIG_HAVE_LONG_DOUBLE
-#  define LDBL_EPSILON DBL_EPSILON /* FIX ME */
-#else
-#  define LDBL_EPSILON DBL_EPSILON
+#ifndef DBL_EPSILON                  /* May be defined in toolchain header */
+#  ifdef CONFIG_HAVE_DOUBLE
+#    define DBL_EPSILON 2.2204460492503131e-16  /* 1E-9 */
+#  else
+#    define DBL_EPSILON FLT_EPSILON
+#  endif
+#endif
+
+#ifndef LDBL_EPSILON                 /* May be defined in toolchain header */
+#  ifdef CONFIG_HAVE_LONG_DOUBLE
+#    define LDBL_EPSILON DBL_EPSILON /* FIX ME */
+#  else
+#    define LDBL_EPSILON DBL_EPSILON
+#  endif
 #endif
 
 /* Minimum normalized positive floating-point number, bemin -1. */
 
-#define FLT_MIN 1.17549435e-38F  /* 1E-37 */
-
-#ifdef CONFIG_HAVE_DOUBLE
-#define DBL_MIN 2.2250738585072014e-308  /* 1E-37 */
-#else
-#  define DBL_MIN FLT_MIN
+#ifndef FLT_MIN                    /* May be defined in toolchain header */
+#  define FLT_MIN 1.17549435e-38F  /* 1E-37 */
 #endif
 
-#ifdef CONFIG_HAVE_LONG_DOUBLE
-#  define LDBL_MIN DBL_MIN /* FIX ME */
-#else
-#  define LDBL_MIN DBL_MIN
+#ifndef DBL_MIN                    /* May be defined in toolchain header */
+#  ifdef CONFIG_HAVE_DOUBLE
+#    define DBL_MIN 2.2250738585072014e-308  /* 1E-37 */
+#  else
+#    define DBL_MIN FLT_MIN
+#  endif
+#endif
+
+#ifndef LDBL_MIN                    /* May be defined in toolchain header */
+#  ifdef CONFIG_HAVE_LONG_DOUBLE
+#    define LDBL_MIN DBL_MIN        /* FIX ME */
+#  else
+#    define LDBL_MIN DBL_MIN
+#  endif
 #endif
 
 #endif /* __INCLUDE_NUTTX_LIB_FLOAT_H */
diff --git a/include/nuttx/mqueue.h b/include/nuttx/mqueue.h
index f3f514608a2..f7a838335e7 100644
--- a/include/nuttx/mqueue.h
+++ b/include/nuttx/mqueue.h
@@ -113,12 +113,10 @@ struct mqueue_inode_s
 #else
   uint16_t maxmsgsize;        /* Max size of message in message queue */
 #endif
-#ifndef CONFIG_DISABLE_SIGNALS
   FAR struct mq_des *ntmqdes; /* Notification: Owning mqdes (NULL if none) */
   pid_t ntpid;                /* Notification: Receiving Task's PID */
   struct sigevent ntevent;    /* Notification description */
   struct sigwork_s ntwork;    /* Notification work */
-#endif
 };
 
 /* This describes the message queue descriptor that is held in the
diff --git a/include/nuttx/net/bluetooth.h b/include/nuttx/net/bluetooth.h
index 20ec48d03e6..1fe370b25a9 100644
--- a/include/nuttx/net/bluetooth.h
+++ b/include/nuttx/net/bluetooth.h
@@ -40,8 +40,11 @@
  * Public Function Prototypes
  ****************************************************************************/
 
+#include 
 #include 
 
+#ifdef CONFIG_NET_BLUETOOTH
+
 /****************************************************************************
  * Public Function Prototypes
  ****************************************************************************/
@@ -144,4 +147,5 @@ int bluetooth_input(FAR struct radio_driver_s *radio,
                      FAR struct iob_s *framelist,
                      FAR struct bluetooth_frame_meta_s *meta);
 
+#endif /* CONFIG_NET_BLUETOOTH */
 #endif /*  __INCLUDE_NUTTX_NET_BLUETOOTH_H */
diff --git a/include/nuttx/net/mii.h b/include/nuttx/net/mii.h
index e4e915e70cf..c7cb4f1f9cf 100644
--- a/include/nuttx/net/mii.h
+++ b/include/nuttx/net/mii.h
@@ -1,7 +1,8 @@
 /****************************************************************************
  * include/nuttx/net/mii.h
  *
- *   Copyright (C) 2008-2010, 2012-2015 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2008-2010, 2012-2015, 2019 Gregory Nutt. All rights
+ *     reserved.
  *   Author: Gregory Nutt 
  *
  * Redistribution and use in source and binary forms, with or without
@@ -369,6 +370,24 @@
 #define MII_LAN8720_SPSCR_ANEGDONE   (1 << 12) /* Bit 12: Autonegotiation complete */
                                                /* Bits 13-15: Reserved */
 
+/* SMSC LAN8720 MODES register bits */
+
+#define MII_LAN8720_MODES_PHYAD_SHIFT (0)      /* Bits 0-4: Phy Address */
+#define MII_LAN8720_MODES_PHYAD_MASK  (0x1f << MII_LAN8720_MODES_PHYAD_SHIFT)
+#define MII_LAN8720_MODES_PHYAD(n)    ((n<