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arm64/qemu_boot: add the pcie cfg address for arm64

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1. Extend the arm64 address to 48bit;
2. Add pci cfg address to the mmu map table;

Signed-off-by: yangshuyong <yangshuyong@xiaomi.com>
This commit is contained in:
yangshuyong
2024-09-10 14:34:31 +08:00
committed by Xiang Xiao
parent f69a62583c
commit 6a09037efd
3 changed files with 21 additions and 14 deletions
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arch/arm64/include/qemu/chip.h
+14 -11
View File
@@ -41,29 +41,32 @@
#if CONFIG_ARM64_GIC_VERSION == 2
#define CONFIG_GICD_BASE 0x8000000
#define CONFIG_GICR_BASE 0x8010000
#define CONFIG_GICD_BASE 0x8000000
#define CONFIG_GICR_BASE 0x8010000
#elif CONFIG_ARM64_GIC_VERSION == 3 || CONFIG_ARM64_GIC_VERSION == 4
#define CONFIG_GICD_BASE 0x8000000
#define CONFIG_GICR_BASE 0x80a0000
#define CONFIG_GICR_OFFSET 0x20000
#define CONFIG_GICD_BASE 0x8000000
#define CONFIG_GICR_BASE 0x80a0000
#define CONFIG_GICR_OFFSET 0x20000
#else
#error CONFIG_ARM64_GIC_VERSION should be 2, 3 or 4
#endif /* CONFIG_ARM64_GIC_VERSION */
#define CONFIG_RAMBANK1_ADDR 0x40000000
#define CONFIG_RAMBANK1_SIZE MB(128)
#define CONFIG_RAMBANK1_ADDR 0x40000000
#define CONFIG_RAMBANK1_SIZE MB(128)
#define CONFIG_DEVICEIO_BASEADDR 0x7000000
#define CONFIG_DEVICEIO_SIZE MB(512)
#define CONFIG_DEVICEIO_BASEADDR 0x7000000
#define CONFIG_DEVICEIO_SIZE MB(512)
#define CONFIG_LOAD_BASE 0x40280000
#define CONFIG_DEVICEPCIE_BASEADDR 0x4010000000
#define CONFIG_DEVICEPCIE_SIZE MB(256)
#define MPID_TO_CLUSTER_ID(mpid) ((mpid) & ~0xff)
#define CONFIG_LOAD_BASE 0x40280000
#define MPID_TO_CLUSTER_ID(mpid) ((mpid) & ~0xff)
#endif
arch/arm64/src/common/arm64_arch.h
+2 -3
View File
@@ -273,15 +273,14 @@
* The choice could be: 32, 36, 42, 48
*/
#define CONFIG_ARM64_VA_BITS 36
#define CONFIG_ARM64_VA_BITS 48
/* Physical address space size
* Choose the maximum physical address range that the kernel will support.
*
* The choice could be: 32, 36, 42, 48
*/
#define CONFIG_ARM64_PA_BITS 36
#define CONFIG_ARM64_PA_BITS 48
#define L1_CACHE_SHIFT (6)
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
arch/arm64/src/qemu/qemu_boot.c
+5
View File
@@ -62,6 +62,11 @@ static const struct arm_mmu_region g_mmu_regions[] =
MMU_REGION_FLAT_ENTRY("DRAM0_S0",
CONFIG_RAMBANK1_ADDR, CONFIG_RAMBANK1_SIZE,
MT_NORMAL | MT_RW | MT_SECURE),
MMU_REGION_FLAT_ENTRY("PCI-E",
CONFIG_DEVICEPCIE_BASEADDR,
CONFIG_DEVICEPCIE_SIZE,
MT_NORMAL | MT_RW | MT_SECURE),
};
const struct arm_mmu_config g_mmu_config =