From 6a09037efd2970c787be1d614d27078d5e65bf3f Mon Sep 17 00:00:00 2001
From: yangshuyong <yangshuyong@xiaomi.com>
Date: Tue, 14 Nov 2023 16:47:54 +0800
Subject: [PATCH] arm64/qemu_boot: add the pcie cfg address for arm64

1. Extend the arm64 address to 48bit;
2. Add pci cfg address to the mmu map table;

Signed-off-by: yangshuyong <yangshuyong@xiaomi.com>
---
 arch/arm64/include/qemu/chip.h     | 25 ++++++++++++++-----------
 arch/arm64/src/common/arm64_arch.h |  5 ++---
 arch/arm64/src/qemu/qemu_boot.c    |  5 +++++
 3 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/include/qemu/chip.h b/arch/arm64/include/qemu/chip.h
index 27208cdf7ea..bc7bc2d7a00 100644
--- a/arch/arm64/include/qemu/chip.h
+++ b/arch/arm64/include/qemu/chip.h
@@ -41,29 +41,32 @@
 
 #if CONFIG_ARM64_GIC_VERSION == 2
 
-#define CONFIG_GICD_BASE          0x8000000
-#define CONFIG_GICR_BASE          0x8010000
+#define CONFIG_GICD_BASE           0x8000000
+#define CONFIG_GICR_BASE           0x8010000
 
 #elif CONFIG_ARM64_GIC_VERSION == 3 || CONFIG_ARM64_GIC_VERSION == 4
 
-#define CONFIG_GICD_BASE          0x8000000
-#define CONFIG_GICR_BASE          0x80a0000
-#define CONFIG_GICR_OFFSET        0x20000
+#define CONFIG_GICD_BASE           0x8000000
+#define CONFIG_GICR_BASE           0x80a0000
+#define CONFIG_GICR_OFFSET         0x20000
 #else
 
 #error CONFIG_ARM64_GIC_VERSION should be 2, 3 or 4
 
 #endif /* CONFIG_ARM64_GIC_VERSION */
 
-#define CONFIG_RAMBANK1_ADDR      0x40000000
-#define CONFIG_RAMBANK1_SIZE      MB(128)
+#define CONFIG_RAMBANK1_ADDR       0x40000000
+#define CONFIG_RAMBANK1_SIZE       MB(128)
 
-#define CONFIG_DEVICEIO_BASEADDR  0x7000000
-#define CONFIG_DEVICEIO_SIZE      MB(512)
+#define CONFIG_DEVICEIO_BASEADDR   0x7000000
+#define CONFIG_DEVICEIO_SIZE       MB(512)
 
-#define CONFIG_LOAD_BASE          0x40280000
+#define CONFIG_DEVICEPCIE_BASEADDR 0x4010000000
+#define CONFIG_DEVICEPCIE_SIZE     MB(256)
 
-#define MPID_TO_CLUSTER_ID(mpid)  ((mpid) & ~0xff)
+#define CONFIG_LOAD_BASE           0x40280000
+
+#define MPID_TO_CLUSTER_ID(mpid)   ((mpid) & ~0xff)
 
 #endif
 
diff --git a/arch/arm64/src/common/arm64_arch.h b/arch/arm64/src/common/arm64_arch.h
index facf2da475b..32d40dc747f 100644
--- a/arch/arm64/src/common/arm64_arch.h
+++ b/arch/arm64/src/common/arm64_arch.h
@@ -273,15 +273,14 @@
  * The choice could be: 32, 36, 42, 48
  */
 
-#define CONFIG_ARM64_VA_BITS        36
-
+#define CONFIG_ARM64_VA_BITS        48
 /* Physical address space size
  * Choose the maximum physical address range that the kernel will support.
  *
  * The choice could be: 32, 36, 42, 48
  */
 
-#define CONFIG_ARM64_PA_BITS        36
+#define CONFIG_ARM64_PA_BITS        48
 
 #define L1_CACHE_SHIFT              (6)
 #define L1_CACHE_BYTES              BIT(L1_CACHE_SHIFT)
diff --git a/arch/arm64/src/qemu/qemu_boot.c b/arch/arm64/src/qemu/qemu_boot.c
index 364f93d2c34..fdcd1d0f59a 100644
--- a/arch/arm64/src/qemu/qemu_boot.c
+++ b/arch/arm64/src/qemu/qemu_boot.c
@@ -62,6 +62,11 @@ static const struct arm_mmu_region g_mmu_regions[] =
   MMU_REGION_FLAT_ENTRY("DRAM0_S0",
                         CONFIG_RAMBANK1_ADDR, CONFIG_RAMBANK1_SIZE,
                         MT_NORMAL | MT_RW | MT_SECURE),
+
+  MMU_REGION_FLAT_ENTRY("PCI-E",
+                        CONFIG_DEVICEPCIE_BASEADDR,
+                        CONFIG_DEVICEPCIE_SIZE,
+                        MT_NORMAL | MT_RW | MT_SECURE),
 };
 
 const struct arm_mmu_config g_mmu_config =