arch/arm:use UP_DSB, UP_DMB, UP_ISB as barrier standard API

Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>

arch/arm/include/armv6-m/barriers.h

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv6-m/barriers.h
+ * arch/arm/include/armv6-m/barriers.h
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,8 +20,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_ARMV6_M_BARRIERS_H
-#define __ARCH_ARM_SRC_ARMV6_M_BARRIERS_H
+#ifndef __ARCH_ARM_INCLUDE_ARMV6_M_BARRIERS_H
+#define __ARCH_ARM_INCLUDE_ARMV6_M_BARRIERS_H
 
 /****************************************************************************
  * Included Files
@@ -37,8 +37,8 @@
 #define arm_isb()  __asm__ __volatile__ ("isb " : : : "memory")
 #define arm_dmb()  __asm__ __volatile__ ("dmb " : : : "memory")
 
-#define ARM_DSB()  arm_dsb()
-#define ARM_ISB()  arm_isb()
-#define ARM_DMB()  arm_dmb()
+#define UP_DSB()  arm_dsb()
+#define UP_ISB()  arm_isb()
+#define UP_DMB()  arm_dmb()
 
-#endif /* __ARCH_ARM_SRC_ARMV6_M_BARRIERS_H */
+#endif /* __ARCH_ARM_INCLUDE_ARMV6_M_BARRIERS_H */

arch/arm/include/armv7-a/barriers.h

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv7-a/barriers.h
+ * arch/arm/include/armv7-a/barriers.h
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,8 +20,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_ARMV7_A_BARRIERS_H
-#define __ARCH_ARM_SRC_ARMV7_A_BARRIERS_H
+#ifndef __ARCH_ARM_INCLUDE_ARMV7_A_BARRIERS_H
+#define __ARCH_ARM_INCLUDE_ARMV7_A_BARRIERS_H
 
 /****************************************************************************
  * Included Files
@@ -39,10 +39,10 @@
 #define arm_nop()  __asm__ __volatile__ ("nop\n")
 #define arm_sev()  __asm__ __volatile__ ("sev\n")
 
-#define ARM_DSB()  arm_dsb(15)
-#define ARM_DMB()  arm_dmb(15)
-#define ARM_ISB()  arm_isb()
-#define ARM_NOP()  arm_nop()
-#define ARM_SEV()  arm_sev()
+#define UP_DSB()  arm_dsb(15)
+#define UP_DMB()  arm_dmb(15)
+#define UP_ISB()  arm_isb()
+#define UP_NOP()  arm_nop()
+#define UP_SEV()  arm_sev()
 
-#endif /* __ARCH_ARM_SRC_ARMV7_A_BARRIERS_H */
+#endif /* __ARCH_ARM_INCLUDE_ARMV7_A_BARRIERS_H */

arch/arm/include/armv7-m/barriers.h

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv7-m/barriers.h
+ * arch/arm/include/armv7-m/barriers.h
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,8 +20,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_ARMV7_M_BARRIERS_H
-#define __ARCH_ARM_SRC_ARMV7_M_BARRIERS_H
+#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_BARRIERS_H
+#define __ARCH_ARM_INCLUDE_ARMV7_M_BARRIERS_H
 
 /****************************************************************************
  * Included Files
@@ -37,8 +37,8 @@
 #define arm_isb()  __asm__ __volatile__ ("isb " : : : "memory")
 #define arm_dmb()  __asm__ __volatile__ ("dmb " : : : "memory")
 
-#define ARM_DSB()  arm_dsb()
-#define ARM_ISB()  arm_isb()
-#define ARM_DMB()  arm_dmb()
+#define UP_DSB()  arm_dsb()
+#define UP_ISB()  arm_isb()
+#define UP_DMB()  arm_dmb()
 
-#endif /* __ARCH_ARM_SRC_ARMV7_M_BARRIERS_H */
+#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_BARRIERS_H */

arch/arm/include/armv7-r/barriers.h

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv7-r/barriers.h
+ * arch/arm/include/armv7-r/barriers.h
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,8 +20,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_ARMV7_R_BARRIERS_H
-#define __ARCH_ARM_SRC_ARMV7_R_BARRIERS_H
+#ifndef __ARCH_ARM_INCLUDE_ARMV7_R_BARRIERS_H
+#define __ARCH_ARM_INCLUDE_ARMV7_R_BARRIERS_H
 
 /****************************************************************************
  * Included Files
@@ -39,10 +39,10 @@
 #define arm_nop()  __asm__ __volatile__ ("nop\n")
 #define arm_sev()  __asm__ __volatile__ ("sev\n")
 
-#define ARM_DSB()  arm_dsb(15)
-#define ARM_DMB()  arm_dmb(15)
-#define ARM_ISB()  arm_isb()
-#define ARM_NOP()  arm_nop()
-#define ARM_SEV()  arm_sev()
+#define UP_DSB()  arm_dsb(15)
+#define UP_DMB()  arm_dmb(15)
+#define UP_ISB()  arm_isb()
+#define UP_NOP()  arm_nop()
+#define UP_SEV()  arm_sev()
 
-#endif /* __ARCH_ARM_SRC_ARMV7_R_BARRIERS_H */
+#endif /* __ARCH_ARM_INCLUDE_ARMV7_R_BARRIERS_H */

arch/arm/include/armv8-m/barriers.h

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv8-m/barriers.h
+ * arch/arm/include/armv8-m/barriers.h
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,8 +20,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_ARMV8_M_BARRIERS_H
-#define __ARCH_ARM_SRC_ARMV8_M_BARRIERS_H
+#ifndef __ARCH_ARM_INCLUDE_ARMV8_M_BARRIERS_H
+#define __ARCH_ARM_INCLUDE_ARMV8_M_BARRIERS_H
 
 /****************************************************************************
  * Included Files
@@ -37,8 +37,8 @@
 #define arm_dmb()  __asm__ __volatile__ ("dmb " : : : "memory")
 #define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
 
-#define ARM_ISB()  arm_isb()
-#define ARM_DMB()  arm_dmb()
-#define ARM_DSB()  arm_dsb(15)
+#define UP_ISB()  arm_isb()
+#define UP_DMB()  arm_dmb()
+#define UP_DSB()  arm_dsb(15)
 
-#endif /* __ARCH_ARM_SRC_ARMV8_M_BARRIERS_H */
+#endif /* __ARCH_ARM_INCLUDE_ARMV8_M_BARRIERS_H */

arch/arm/include/armv8-r/barriers.h

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/armv8-r/barriers.h
+ * arch/arm/include/armv8-r/barriers.h
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,8 +20,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_ARMV8_R_BARRIERS_H
-#define __ARCH_ARM_SRC_ARMV8_R_BARRIERS_H
+#ifndef __ARCH_ARM_INCLUDE_ARMV8_R_BARRIERS_H
+#define __ARCH_ARM_INCLUDE_ARMV8_R_BARRIERS_H
 
 /****************************************************************************
  * Included Files
@@ -39,10 +39,10 @@
 #define arm_nop()  __asm__ __volatile__ ("nop\n")
 #define arm_sev()  __asm__ __volatile__ ("sev\n")
 
-#define ARM_DSB()  arm_dsb(15)
-#define ARM_DMB()  arm_dmb(15)
-#define ARM_ISB()  arm_isb()
-#define ARM_NOP()  arm_nop()
-#define ARM_SEV()  arm_sev()
+#define UP_DSB()  arm_dsb(15)
+#define UP_DMB()  arm_dmb(15)
+#define UP_ISB()  arm_isb()
+#define UP_NOP()  arm_nop()
+#define UP_SEV()  arm_sev()
 
-#endif /* __ARCH_ARM_SRC_ARMV8_R_BARRIERS_H */
+#endif /* __ARCH_ARM_INCLUDE_ARMV8_R_BARRIERS_H */

arch/arm/include/barriers.h

@@ -0,0 +1,52 @@
+/****************************************************************************
+ * arch/arm/include/barriers.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_BARRIERS_H
+#define __ARCH_ARM_INCLUDE_BARRIERS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#if defined(CONFIG_ARCH_ARMV7A)
+#  include <arch/armv7-a/barriers.h>
+#elif defined(CONFIG_ARCH_ARMV7R)
+#  include <arch/armv7-r/barriers.h>
+#elif defined(CONFIG_ARCH_ARMV8R)
+#  include <arch/armv8-r/barriers.h>
+#elif defined(CONFIG_ARCH_ARMV7M)
+#  include <arch/armv7-m/barriers.h>
+#elif defined(CONFIG_ARCH_ARMV8M)
+#  include <arch/armv8-m/barriers.h>
+#elif defined(CONFIG_ARCH_ARMV6M)
+#  include <arch/armv6-m/barriers.h>
+#else
+#  include <arch/arm/barriers.h>
+#endif
+
+#define UP_MB() \
+  do            \
+    {           \
+      UP_DSB(); \
+      UP_ISB(); \
+    }           \
+  while (0)
+
+#endif /* __ARCH_ARM_INCLUDE_BARRIERS_H */

arch/arm/include/spinlock.h

@@ -31,6 +31,8 @@
 #  include <stdint.h>
 #endif /* __ASSEMBLY__ */
 
+#include <arch/barriers.h>
+
 /****************************************************************************
  * Pre-processor Prototypes
  ****************************************************************************/

arch/arm/src/armv7-a/arm_cache.c

@@ -28,9 +28,9 @@
 #include <nuttx/cache.h>
 #include <nuttx/irq.h>
 #include <sys/param.h>
+#include <arch/barriers.h>
 
 #include "cp15_cacheops.h"
-#include "barriers.h"
 #include "l2cc.h"
 
 /****************************************************************************

arch/arm/src/armv7-a/arm_l2cc_pl310.c

@@ -40,8 +40,8 @@
 #include <nuttx/irq.h>
 #include <nuttx/spinlock.h>
 
+#include <arch/barriers.h>
 #include "arm_internal.h"
-#include "barriers.h"
 #include "l2cc.h"
 #include "l2cc_pl310.h"
 
@@ -292,8 +292,7 @@ static void l2cc_disable_nolock(void)
   /* Disable the L2CC-P310 L2 cache by clearing the Control Register (CR) */
 
   putreg32(0, L2CC_CR);
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 
 /****************************************************************************
@@ -457,8 +456,7 @@ void arm_l2ccinitialize(void)
 
       l2cc_invalidate_all();
       putreg32(L2CC_CR_L2CEN, L2CC_CR);
-      ARM_DSB();
-      ARM_ISB();
+      UP_MB();
     }
 
   sinfo("(%d ways) * (%d bytes/way) = %d bytes\n",
@@ -533,8 +531,7 @@ void l2cc_enable(void)
 
   l2cc_invalidate_all_nolock();
   putreg32(L2CC_CR_L2CEN, L2CC_CR);
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
   spin_unlock_irqrestore(&g_l2cc_lock, flags);
 }
 

arch/arm/src/armv7-a/arm_scu.c

@@ -28,12 +28,12 @@
 
 #include <stdint.h>
 
+#include <arch/barriers.h>
 #include <arch/irq.h>
 #include <sched/sched.h>
 
 #include "arm_internal.h"
 #include "cp15_cacheops.h"
-#include "barriers.h"
 #include "sctlr.h"
 #include "scu.h"
 
@@ -83,7 +83,7 @@ void arm_enable_smp(int cpu)
        */
 
       cp15_invalidate_dcache_all();
-      ARM_DSB();
+      UP_DSB();
 
       /* Invalidate the L2C-310 -- Missing logic. */
 
@@ -95,7 +95,7 @@ void arm_enable_smp(int cpu)
 
       /* Initialize done, kick other cpus which waiting on __start */
 
-      ARM_SEV();
+      UP_SEV();
     }
 
   /* Actions for other CPUs */
@@ -107,7 +107,7 @@ void arm_enable_smp(int cpu)
        */
 
       cp15_dcache_op_level(0, CP15_CACHE_INVALIDATE);
-      ARM_DSB();
+      UP_DSB();
 
       /* Wait for the SCU to be enabled by the primary processor -- should
        * not be necessary.

arch/arm/src/armv7-a/arm_timer.c

@@ -29,10 +29,10 @@
 #include <nuttx/irq.h>
 #include <nuttx/kmalloc.h>
 
+#include <arch/barriers.h>
 #include <arch/irq.h>
 
 #include "arm_timer.h"
-#include "barriers.h"
 #include "gic.h"
 
 /****************************************************************************
@@ -98,49 +98,49 @@ static const struct oneshot_operations_s g_arm_timer_ops =
 static inline void arm_timer_set_freq(uint32_t freq)
 {
   CP15_SET(CNTFRQ, freq);
-  ARM_ISB();
+  UP_ISB();
 }
 
 static inline uint64_t arm_timer_get_count(void)
 {
-  ARM_ISB();
+  UP_ISB();
   return CP15_GET64(CNTPCT);
 }
 
 static inline uint32_t arm_timer_get_ctrl(void)
 {
-  ARM_ISB();
+  UP_ISB();
   return CP15_GET(CNTP_CTL);
 }
 
 static inline void arm_timer_set_ctrl(uint32_t ctrl)
 {
   CP15_SET(CNTP_CTL, ctrl);
-  ARM_ISB();
+  UP_ISB();
 }
 
 static inline uint32_t arm_timer_get_tval(void)
 {
-  ARM_ISB();
+  UP_ISB();
   return CP15_GET(CNTP_TVAL);
 }
 
 static inline void arm_timer_set_tval(uint32_t tval)
 {
   CP15_SET(CNTP_TVAL, tval);
-  ARM_ISB();
+  UP_ISB();
 }
 
 static inline uint64_t arm_timer_get_cval(void)
 {
-  ARM_ISB();
+  UP_ISB();
   return CP15_GET64(CNTP_CVAL);
 }
 
 static inline void arm_timer_set_cval(uint64_t cval)
 {
   CP15_SET64(CNTP_CVAL, cval);
-  ARM_ISB();
+  UP_ISB();
 }
 
 static inline uint64_t nsec_from_count(uint64_t count, uint32_t freq)
@@ -288,7 +288,7 @@ static int arm_timer_interrupt(int irq, void *context, void *arg)
 
 uint32_t arm_timer_get_freq(void)
 {
-  ARM_ISB();
+  UP_ISB();
   return CP15_GET(CNTFRQ);
 }
 

arch/arm/src/armv7-a/cp15_cacheops.c

@@ -113,7 +113,7 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
 
   line = cp15_dcache_linesize();
 
-  ARM_DSB();
+  UP_DSB();
 
   if ((start & (line - 1)) != 0)
     {
@@ -152,7 +152,7 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
       start += line;
     }
 
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -181,7 +181,7 @@ void cp15_dcache_op_level(uint32_t level, int op)
   way_shift = 32 - ilog2(ways);
   set_shift = ilog2(line);
 
-  ARM_DSB();
+  UP_DSB();
 
   /* A: Log2(ways)
    * B: L+S
@@ -220,7 +220,7 @@ void cp15_dcache_op_level(uint32_t level, int op)
         }
     }
 
-  ARM_ISB();
+  UP_ISB();
 }
 
 void cp15_invalidate_icache(uintptr_t start, uintptr_t end)
@@ -230,7 +230,7 @@ void cp15_invalidate_icache(uintptr_t start, uintptr_t end)
   line = cp15_icache_linesize();
   start &= ~(line - 1);
 
-  ARM_DSB();
+  UP_DSB();
 
   while (start < end)
     {
@@ -238,7 +238,7 @@ void cp15_invalidate_icache(uintptr_t start, uintptr_t end)
       start += line;
     }
 
-  ARM_ISB();
+  UP_ISB();
 }
 
 void cp15_coherent_dcache(uintptr_t start, uintptr_t end)

arch/arm/src/armv7-a/cp15_cacheops.h

@@ -587,7 +587,7 @@ static inline void cp15_enable_dcache(void)
   sctlr = CP15_GET(SCTLR);
   sctlr |= SCTLR_C;
   CP15_SET(SCTLR, sctlr);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -611,7 +611,7 @@ static inline void cp15_disable_dcache(void)
   sctlr = CP15_GET(SCTLR);
   sctlr &= ~SCTLR_C;
   CP15_SET(SCTLR, sctlr);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -635,7 +635,7 @@ static inline void cp15_enable_icache(void)
   sctlr = CP15_GET(SCTLR);
   sctlr |= SCTLR_I;
   CP15_SET(SCTLR, sctlr);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -659,7 +659,7 @@ static inline void cp15_disable_icache(void)
   sctlr = CP15_GET(SCTLR);
   sctlr &= ~SCTLR_I;
   CP15_SET(SCTLR, sctlr);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -679,7 +679,7 @@ static inline void cp15_disable_icache(void)
 static inline void cp15_invalidate_icache_inner_sharable(void)
 {
   CP15_SET(ICIALLUIS, 0);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -699,7 +699,7 @@ static inline void cp15_invalidate_icache_inner_sharable(void)
 static inline void cp15_invalidate_btb_inner_sharable(void)
 {
   CP15_SET(BPIALLIS, 0);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -720,7 +720,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void)
 static inline void cp15_invalidate_icache_all(void)
 {
   CP15_SET(ICIALLU, 0);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -740,7 +740,7 @@ static inline void cp15_invalidate_icache_all(void)
 static inline void cp15_invalidate_icache_bymva(unsigned int va)
 {
   CP15_SET(ICIMVAU, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -760,7 +760,7 @@ static inline void cp15_invalidate_icache_bymva(unsigned int va)
 static inline void cp15_flush_btb(void)
 {
   CP15_SET(BPIALL, 0);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -780,7 +780,7 @@ static inline void cp15_flush_btb(void)
 static inline void cp15_flush_btb_bymva(unsigned int va)
 {
   CP15_SET(BPIMVA, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -802,7 +802,7 @@ static inline void cp15_flush_btb_bymva(unsigned int va)
 static inline void cp15_invalidate_dcacheline_bymva(unsigned int va)
 {
   CP15_SET(DCIMVAC, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -824,7 +824,7 @@ static inline void cp15_invalidate_dcacheline_bymva(unsigned int va)
 static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway)
 {
   CP15_SET(DCISW, setway);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -846,7 +846,7 @@ static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway)
 static inline void cp15_clean_dcache_bymva(unsigned int va)
 {
   CP15_SET(DCCMVAC, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -866,7 +866,7 @@ static inline void cp15_clean_dcache_bymva(unsigned int va)
 static inline void cp15_clean_dcache_bysetway(unsigned int setway)
 {
   CP15_SET(DCCSW, setway);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -886,7 +886,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway)
 static inline void cp15_clean_ucache_bymva(unsigned int va)
 {
   CP15_SET(DCCMVAU, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -906,7 +906,7 @@ static inline void cp15_clean_ucache_bymva(unsigned int va)
 static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va)
 {
   CP15_SET(DCCIMVAC, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -926,7 +926,7 @@ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va)
 static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway)
 {
   CP15_SET(DCCISW, setway);
-  ARM_ISB();
+  UP_ISB();
 }
 
 #endif /* __ASSEMBLY__ */

arch/arm/src/armv7-a/mmu.h

@@ -37,12 +37,12 @@
 
 #include <nuttx/config.h>
 #include <sys/types.h>
+#include <arch/barriers.h>
 #include "sctlr.h"
 
 #ifndef __ASSEMBLY__
 #  include <stdint.h>
 #  include "chip.h"
-#  include "barriers.h"
 #endif /* __ASSEMBLY__ */
 
 /****************************************************************************
@@ -1250,7 +1250,7 @@ static inline void cp15_disable_mmu(void)
 
 static inline void cp15_invalidate_tlbs(void)
 {
-  ARM_DSB();
+  UP_DSB();
 #ifdef CONFIG_ARM_HAVE_MPCORE
   CP15_SET(TLBIALLIS, 0);
   CP15_SET(BPIALLIS, 0);
@@ -1258,8 +1258,7 @@ static inline void cp15_invalidate_tlbs(void)
   CP15_SET2(TLBIALL, c7, 0);
   CP15_SET(BPIALL, 0);
 #endif
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 
 /****************************************************************************
@@ -1275,7 +1274,7 @@ static inline void cp15_invalidate_tlbs(void)
 
 static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
 {
-  ARM_DSB();
+  UP_DSB();
 #ifdef CONFIG_ARM_HAVE_MPCORE
   CP15_SET(TLBIMVAAIS, vaddr);
   CP15_SET(BPIALLIS, 0);
@@ -1283,8 +1282,7 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
   CP15_SET2(TLBIMVA, c7, vaddr);
   CP15_SET(BPIALL, 0);
 #endif
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 
 /****************************************************************************
@@ -1301,14 +1299,14 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
 static inline void cp15_wrdacr(unsigned int dacr)
 {
   CP15_SET(DACR, dacr);
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
 }
 
 /****************************************************************************
@@ -1329,14 +1327,14 @@ static inline void cp15_wrdacr(unsigned int dacr)
 static inline void cp15_wrttb(unsigned int ttb)
 {
   CP15_SET(TTBR0, ttb);
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
   CP15_SET(TTBCR, 0);
 }
 

arch/arm/src/armv7-a/sctlr.h

@@ -36,10 +36,9 @@
  * Included Files
  ****************************************************************************/
 
+#include <arch/barriers.h>
 #include <arch/irq.h>
 
-#include "barriers.h"
-
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
@@ -460,14 +459,14 @@ static inline unsigned int cp15_rdsctlr(void)
 static inline void cp15_wrsctlr(unsigned int sctlr)
 {
   CP15_SET(SCTLR, sctlr);
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
 }
 
 /* Read/write the vector base address register (VBAR) */

arch/arm/src/armv7-m/arm_cache.c

@@ -42,9 +42,9 @@
 
 #include <nuttx/config.h>
 #include <nuttx/cache.h>
+#include <arch/barriers.h>
 
 #include "arm_internal.h"
-#include "barriers.h"
 #include "nvic.h"
 
 /****************************************************************************
@@ -268,8 +268,7 @@ void up_enable_icache(void)
 {
   uint32_t regval;
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 
   /* Invalidate the entire I-Cache */
 
@@ -281,8 +280,7 @@ void up_enable_icache(void)
   regval |= NVIC_CFGCON_IC;
   putreg32(regval, NVIC_CFGCON);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif
 
@@ -305,8 +303,7 @@ void up_disable_icache(void)
 {
   uint32_t regval;
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 
   /* Disable the I-Cache */
 
@@ -318,8 +315,7 @@ void up_disable_icache(void)
 
   putreg32(0, NVIC_ICIALLU);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif
 
@@ -350,7 +346,7 @@ void up_invalidate_icache(uintptr_t start, uintptr_t end)
    *   (ssize - 1)  = 0x007f : Mask of the set field
    */
 
-  ARM_DSB();
+  UP_DSB();
 
   if ((start & (ssize - 1)) != 0)
     {
@@ -380,8 +376,7 @@ void up_invalidate_icache(uintptr_t start, uintptr_t end)
       putreg32(start, NVIC_ICIMVAU);
     }
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif /* CONFIG_ARMV7M_ICACHE */
 
@@ -402,15 +397,13 @@ void up_invalidate_icache(uintptr_t start, uintptr_t end)
 #ifdef CONFIG_ARMV7M_ICACHE
 void up_invalidate_icache_all(void)
 {
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 
   /* Invalidate the entire I-Cache */
 
   putreg32(0, NVIC_ICIALLU);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif
 
@@ -523,7 +516,7 @@ void up_enable_dcache(void)
 
   /* Invalidate the entire D-Cache */
 
-  ARM_DSB();
+  UP_DSB();
   do
     {
       int32_t tmpways = ways;
@@ -537,7 +530,7 @@ void up_enable_dcache(void)
     }
   while (sets--);
 
-  ARM_DSB();
+  UP_DSB();
 
 #ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
   ccr = getreg32(NVIC_CACR);
@@ -551,8 +544,7 @@ void up_enable_dcache(void)
   ccr |= NVIC_CFGCON_DC;
   putreg32(ccr, NVIC_CFGCON);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif /* CONFIG_ARMV7M_DCACHE */
 
@@ -601,7 +593,7 @@ void up_disable_dcache(void)
 
   wshift = arm_clz(ways) & 0x1f;
 
-  ARM_DSB();
+  UP_DSB();
 
   /* Disable the D-Cache */
 
@@ -624,8 +616,7 @@ void up_disable_dcache(void)
     }
   while (sets--);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif /* CONFIG_ARMV7M_DCACHE */
 
@@ -665,7 +656,7 @@ void up_invalidate_dcache(uintptr_t start, uintptr_t end)
    *   (ssize - 1)  = 0x007f : Mask of the set field
    */
 
-  ARM_DSB();
+  UP_DSB();
 
   if ((start & (ssize - 1)) != 0)
     {
@@ -695,8 +686,7 @@ void up_invalidate_dcache(uintptr_t start, uintptr_t end)
       putreg32(start, NVIC_DCCIMVAC);
     }
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif /* CONFIG_ARMV7M_DCACHE */
 
@@ -744,7 +734,7 @@ void up_invalidate_dcache_all(void)
 
   wshift = arm_clz(ways) & 0x1f;
 
-  ARM_DSB();
+  UP_DSB();
 
   /* Invalidate the entire D-Cache */
 
@@ -761,8 +751,7 @@ void up_invalidate_dcache_all(void)
     }
   while (sets--);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif /* CONFIG_ARMV7M_DCACHE */
 
@@ -819,7 +808,7 @@ void up_clean_dcache(uintptr_t start, uintptr_t end)
 #endif
 
   start &= ~(ssize - 1);
-  ARM_DSB();
+  UP_DSB();
 
   do
     {
@@ -839,8 +828,7 @@ void up_clean_dcache(uintptr_t start, uintptr_t end)
   while (start < end);
 #endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif /* CONFIG_ARMV7M_DCACHE */
 
@@ -898,7 +886,7 @@ void up_clean_dcache_all(void)
 
   wshift = arm_clz(ways) & 0x1f;
 
-  ARM_DSB();
+  UP_DSB();
 
   /* Clean the entire D-Cache */
 
@@ -916,8 +904,7 @@ void up_clean_dcache_all(void)
   while (sets--);
 #endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif /* CONFIG_ARMV7M_DCACHE */
 
@@ -974,7 +961,7 @@ void up_flush_dcache(uintptr_t start, uintptr_t end)
 #endif
 
   start &= ~(ssize - 1);
-  ARM_DSB();
+  UP_DSB();
 
   do
     {
@@ -993,8 +980,7 @@ void up_flush_dcache(uintptr_t start, uintptr_t end)
     }
   while (start < end);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 #else
   up_invalidate_dcache(start, end);
 #endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */
@@ -1054,7 +1040,7 @@ void up_flush_dcache_all(void)
 
   wshift = arm_clz(ways) & 0x1f;
 
-  ARM_DSB();
+  UP_DSB();
 
   /* Clean and invalidate the entire D-Cache */
 
@@ -1071,8 +1057,7 @@ void up_flush_dcache_all(void)
     }
   while (sets--);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 #else
   up_invalidate_dcache_all();
 #endif /* !CONFIG_ARMV7M_DCACHE_WRITETHROUGH */

arch/arm/src/armv7-m/arm_mpu.c

@@ -30,9 +30,10 @@
 #include <assert.h>
 #include <debug.h>
 
+#include <arch/barriers.h>
+
 #include "mpu.h"
 #include "arm_internal.h"
-#include "barriers.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -226,8 +227,7 @@ static void mpu_reset_internal(void)
 
   putreg32(0, MPU_CTRL);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif
 
@@ -284,8 +284,7 @@ void mpu_freeregion(unsigned int region)
   putreg32(0, MPU_RASR);
   putreg32(0, MPU_RBAR);
   g_mpu_region &= ~(1 << region);
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 
 /****************************************************************************
@@ -450,8 +449,7 @@ void mpu_control(bool enable, bool hfnmiena, bool privdefena)
 
   /* Ensure MPU setting take effects */
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 
 /****************************************************************************
@@ -524,8 +522,7 @@ void mpu_modify_region(unsigned int region, uintptr_t base, size_t size,
 
   /* Ensure MPU setting take effects */
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 
 /****************************************************************************

arch/arm/src/armv7-r/arm_cache.c

@@ -28,9 +28,9 @@
 #include <nuttx/cache.h>
 #include <nuttx/irq.h>
 #include <sys/param.h>
+#include <arch/barriers.h>
 
 #include "cp15_cacheops.h"
-#include "barriers.h"
 #include "l2cc.h"
 
 /****************************************************************************

arch/arm/src/armv7-r/arm_l2cc_pl310.c

@@ -39,9 +39,9 @@
 
 #include <nuttx/irq.h>
 #include <nuttx/spinlock.h>
+#include <arch/barriers.h>
 
 #include "arm_internal.h"
-#include "barriers.h"
 #include "l2cc.h"
 #include "l2cc_pl310.h"
 
@@ -292,8 +292,7 @@ static void l2cc_disable_nolock(void)
   /* Disable the L2CC-P310 L2 cache by clearing the Control Register (CR) */
 
   putreg32(0, L2CC_CR);
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 
 /****************************************************************************
@@ -457,8 +456,7 @@ void arm_l2ccinitialize(void)
 
       l2cc_invalidate_all();
       putreg32(L2CC_CR_L2CEN, L2CC_CR);
-      ARM_DSB();
-      ARM_ISB();
+      UP_MB();
     }
 
   sinfo("(%d ways) * (%d bytes/way) = %d bytes\n",
@@ -533,8 +531,7 @@ void l2cc_enable(void)
 
   l2cc_invalidate_all_nolock();
   putreg32(L2CC_CR_L2CEN, L2CC_CR);
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
   spin_unlock_irqrestore(&g_l2cc_lock, flags);
 }
 

arch/arm/src/armv7-r/arm_mpu.c

@@ -281,8 +281,7 @@ void mpu_freeregion(unsigned int region)
   mpu_set_dracr(0);
   mpu_set_drsr(0);
   g_mpu_region &= ~(1 << region);
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 
 /****************************************************************************

arch/arm/src/armv7-r/arm_scu.c

@@ -28,12 +28,12 @@
 
 #include <stdint.h>
 
+#include <arch/barriers.h>
 #include <arch/irq.h>
 #include <sched/sched.h>
 
 #include "arm_internal.h"
 #include "cp15_cacheops.h"
-#include "barriers.h"
 #include "sctlr.h"
 #include "scu.h"
 
@@ -85,7 +85,7 @@ void arm_enable_smp(int cpu)
        */
 
       cp15_invalidate_dcache_all();
-      ARM_DSB();
+      UP_DSB();
 
       /* Invalidate the L2C-310 -- Missing logic. */
 
@@ -97,7 +97,7 @@ void arm_enable_smp(int cpu)
 
       /* Initialize done, kick other cpus which waiting on __start */
 
-      ARM_SEV();
+      UP_SEV();
     }
 
   /* Actions for other CPUs */
@@ -109,7 +109,7 @@ void arm_enable_smp(int cpu)
        */
 
       cp15_dcache_op_level(0, CP15_CACHE_INVALIDATE);
-      ARM_DSB();
+      UP_DSB();
 
       /* Wait for the SCU to be enabled by the primary processor -- should
        * not be necessary.

arch/arm/src/armv7-r/arm_timer.c

@@ -28,9 +28,9 @@
 #include <nuttx/arch.h>
 #include <nuttx/irq.h>
 #include <nuttx/kmalloc.h>
+#include <arch/barriers.h>
 
 #include "arm_timer.h"
-#include "barriers.h"
 #include "gic.h"
 
 /****************************************************************************
@@ -96,49 +96,49 @@ static const struct oneshot_operations_s g_arm_timer_ops =
 static inline void arm_timer_set_freq(uint32_t freq)
 {
   CP15_SET(CNTFRQ, freq);
-  ARM_ISB();
+  UP_ISB();
 }
 
 static inline uint64_t arm_timer_get_count(void)
 {
-  ARM_ISB();
+  UP_ISB();
   return CP15_GET64(CNTPCT);
 }
 
 static inline uint32_t arm_timer_get_ctrl(void)
 {
-  ARM_ISB();
+  UP_ISB();
   return CP15_GET(CNTP_CTL);
 }
 
 static inline void arm_timer_set_ctrl(uint32_t ctrl)
 {
   CP15_SET(CNTP_CTL, ctrl);
-  ARM_ISB();
+  UP_ISB();
 }
 
 static inline uint32_t arm_timer_get_tval(void)
 {
-  ARM_ISB();
+  UP_ISB();
   return CP15_GET(CNTP_TVAL);
 }
 
 static inline void arm_timer_set_tval(uint32_t tval)
 {
   CP15_SET(CNTP_TVAL, tval);
-  ARM_ISB();
+  UP_ISB();
 }
 
 static inline uint64_t arm_timer_get_cval(void)
 {
-  ARM_ISB();
+  UP_ISB();
   return CP15_GET64(CNTP_CVAL);
 }
 
 static inline void arm_timer_set_cval(uint64_t cval)
 {
   CP15_SET64(CNTP_CVAL, cval);
-  ARM_ISB();
+  UP_ISB();
 }
 
 static inline uint64_t nsec_from_count(uint64_t count, uint32_t freq)
@@ -286,7 +286,7 @@ static int arm_timer_interrupt(int irq, void *context, void *arg)
 
 uint32_t arm_timer_get_freq(void)
 {
-  ARM_ISB();
+  UP_ISB();
   return CP15_GET(CNTFRQ);
 }
 

arch/arm/src/armv7-r/cp15_cacheops.c

@@ -113,7 +113,7 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
 
   line = cp15_dcache_linesize();
 
-  ARM_DSB();
+  UP_DSB();
 
   if ((start & (line - 1)) != 0)
     {
@@ -152,7 +152,7 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
       start += line;
     }
 
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -181,7 +181,7 @@ void cp15_dcache_op_level(uint32_t level, int op)
   way_shift = 32 - ilog2(ways);
   set_shift = ilog2(line);
 
-  ARM_DSB();
+  UP_DSB();
 
   /* A: Log2(ways)
    * B: L+S
@@ -220,7 +220,7 @@ void cp15_dcache_op_level(uint32_t level, int op)
         }
     }
 
-  ARM_ISB();
+  UP_ISB();
 }
 
 void cp15_invalidate_icache(uintptr_t start, uintptr_t end)
@@ -230,7 +230,7 @@ void cp15_invalidate_icache(uintptr_t start, uintptr_t end)
   line = cp15_icache_linesize();
   start &= ~(line - 1);
 
-  ARM_DSB();
+  UP_DSB();
 
   while (start < end)
     {
@@ -238,7 +238,7 @@ void cp15_invalidate_icache(uintptr_t start, uintptr_t end)
       start += line;
     }
 
-  ARM_ISB();
+  UP_ISB();
 }
 
 void cp15_coherent_dcache(uintptr_t start, uintptr_t end)

arch/arm/src/armv7-r/cp15_cacheops.h

@@ -594,7 +594,7 @@ static inline void cp15_enable_dcache(void)
   sctlr = CP15_GET(SCTLR);
   sctlr |= SCTLR_C;
   CP15_SET(SCTLR, sctlr);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -618,7 +618,7 @@ static inline void cp15_disable_dcache(void)
   sctlr = CP15_GET(SCTLR);
   sctlr &= ~SCTLR_C;
   CP15_SET(SCTLR, sctlr);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -642,7 +642,7 @@ static inline void cp15_enable_icache(void)
   sctlr = CP15_GET(SCTLR);
   sctlr |= SCTLR_I;
   CP15_SET(SCTLR, sctlr);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -666,7 +666,7 @@ static inline void cp15_disable_icache(void)
   sctlr = CP15_GET(SCTLR);
   sctlr &= ~SCTLR_I;
   CP15_SET(SCTLR, sctlr);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -686,7 +686,7 @@ static inline void cp15_disable_icache(void)
 static inline void cp15_invalidate_icache_inner_sharable(void)
 {
   CP15_SET(ICIALLUIS, 0);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -706,7 +706,7 @@ static inline void cp15_invalidate_icache_inner_sharable(void)
 static inline void cp15_invalidate_btb_inner_sharable(void)
 {
   CP15_SET(BPIALLIS, 0);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -727,7 +727,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void)
 static inline void cp15_invalidate_icache_all(void)
 {
   CP15_SET(ICIALLU, 0);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -747,7 +747,7 @@ static inline void cp15_invalidate_icache_all(void)
 static inline void cp15_invalidate_icache_bymva(unsigned int va)
 {
   CP15_SET(ICIMVAU, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -767,7 +767,7 @@ static inline void cp15_invalidate_icache_bymva(unsigned int va)
 static inline void cp15_flush_btb(void)
 {
   CP15_SET(BPIALL, 0);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -787,7 +787,7 @@ static inline void cp15_flush_btb(void)
 static inline void cp15_flush_btb_bymva(unsigned int va)
 {
   CP15_SET(BPIMVA, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -809,7 +809,7 @@ static inline void cp15_flush_btb_bymva(unsigned int va)
 static inline void cp15_invalidate_dcacheline_bymva(unsigned int va)
 {
   CP15_SET(DCIMVAC, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -831,7 +831,7 @@ static inline void cp15_invalidate_dcacheline_bymva(unsigned int va)
 static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway)
 {
   CP15_SET(DCISW, setway);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -853,7 +853,7 @@ static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway)
 static inline void cp15_clean_dcache_bymva(unsigned int va)
 {
   CP15_SET(DCCMVAC, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -873,7 +873,7 @@ static inline void cp15_clean_dcache_bymva(unsigned int va)
 static inline void cp15_clean_dcache_bysetway(unsigned int setway)
 {
   CP15_SET(DCCSW, setway);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -893,7 +893,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway)
 static inline void cp15_clean_ucache_bymva(unsigned int va)
 {
   CP15_SET(DCCMVAU, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -913,7 +913,7 @@ static inline void cp15_clean_ucache_bymva(unsigned int va)
 static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va)
 {
   CP15_SET(DCCIMVAC, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -933,7 +933,7 @@ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va)
 static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway)
 {
   CP15_SET(DCCISW, setway);
-  ARM_ISB();
+  UP_ISB();
 }
 
 #endif /* __ASSEMBLY__ */

arch/arm/src/armv7-r/sctlr.h

@@ -34,10 +34,9 @@
  * Included Files
  ****************************************************************************/
 
+#include <arch/barriers.h>
 #include <arch/irq.h>
 
-#include "barriers.h"
-
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
@@ -524,14 +523,14 @@ static inline unsigned int cp15_rdsctlr(void)
 static inline void cp15_wrsctlr(unsigned int sctlr)
 {
   CP15_SET(SCTLR, sctlr);
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
 }
 
 /* Read/write the vector base address register (VBAR) */

arch/arm/src/armv8-m/arm_cache.c

@@ -42,9 +42,9 @@
 
 #include <nuttx/config.h>
 #include <nuttx/cache.h>
+#include <arch/barriers.h>
 
 #include "arm_internal.h"
-#include "barriers.h"
 #include "nvic.h"
 
 /****************************************************************************
@@ -268,8 +268,7 @@ void up_enable_icache(void)
 {
   uint32_t regval;
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 
   /* Invalidate the entire I-Cache */
 
@@ -281,8 +280,7 @@ void up_enable_icache(void)
   regval |= NVIC_CFGCON_IC;
   putreg32(regval, NVIC_CFGCON);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif
 
@@ -305,8 +303,7 @@ void up_disable_icache(void)
 {
   uint32_t regval;
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 
   /* Disable the I-Cache */
 
@@ -318,8 +315,7 @@ void up_disable_icache(void)
 
   putreg32(0, NVIC_ICIALLU);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif
 
@@ -350,7 +346,7 @@ void up_invalidate_icache(uintptr_t start, uintptr_t end)
    *   (ssize - 1)  = 0x007f : Mask of the set field
    */
 
-  ARM_DSB();
+  UP_DSB();
 
   if ((start & (ssize - 1)) != 0)
     {
@@ -380,8 +376,7 @@ void up_invalidate_icache(uintptr_t start, uintptr_t end)
       putreg32(start, NVIC_ICIMVAU);
     }
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif /* CONFIG_ARMV8M_ICACHE */
 
@@ -402,15 +397,13 @@ void up_invalidate_icache(uintptr_t start, uintptr_t end)
 #ifdef CONFIG_ARMV8M_ICACHE
 void up_invalidate_icache_all(void)
 {
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 
   /* Invalidate the entire I-Cache */
 
   putreg32(0, NVIC_ICIALLU);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif
 
@@ -523,7 +516,7 @@ void up_enable_dcache(void)
 
   /* Invalidate the entire D-Cache */
 
-  ARM_DSB();
+  UP_DSB();
   do
     {
       int32_t tmpways = ways;
@@ -537,7 +530,7 @@ void up_enable_dcache(void)
     }
   while (sets--);
 
-  ARM_DSB();
+  UP_DSB();
 
 #ifdef CONFIG_ARMV8M_DCACHE_WRITETHROUGH
   ccr = getreg32(NVIC_CACR);
@@ -551,8 +544,7 @@ void up_enable_dcache(void)
   ccr |= NVIC_CFGCON_DC;
   putreg32(ccr, NVIC_CFGCON);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif /* CONFIG_ARMV8M_DCACHE */
 
@@ -601,7 +593,7 @@ void up_disable_dcache(void)
 
   wshift = arm_clz(ways) & 0x1f;
 
-  ARM_DSB();
+  UP_DSB();
 
   /* Disable the D-Cache */
 
@@ -624,8 +616,7 @@ void up_disable_dcache(void)
     }
   while (sets--);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif /* CONFIG_ARMV8M_DCACHE */
 
@@ -665,7 +656,7 @@ void up_invalidate_dcache(uintptr_t start, uintptr_t end)
    *   (ssize - 1)  = 0x007f : Mask of the set field
    */
 
-  ARM_DSB();
+  UP_DSB();
 
   if ((start & (ssize - 1)) != 0)
     {
@@ -695,8 +686,7 @@ void up_invalidate_dcache(uintptr_t start, uintptr_t end)
       putreg32(start, NVIC_DCCIMVAC);
     }
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif /* CONFIG_ARMV8M_DCACHE */
 
@@ -744,7 +734,7 @@ void up_invalidate_dcache_all(void)
 
   wshift = arm_clz(ways) & 0x1f;
 
-  ARM_DSB();
+  UP_DSB();
 
   /* Invalidate the entire D-Cache */
 
@@ -761,8 +751,7 @@ void up_invalidate_dcache_all(void)
     }
   while (sets--);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif /* CONFIG_ARMV8M_DCACHE */
 
@@ -819,7 +808,7 @@ void up_clean_dcache(uintptr_t start, uintptr_t end)
 #endif
 
   start &= ~(ssize - 1);
-  ARM_DSB();
+  UP_DSB();
 
   do
     {
@@ -839,8 +828,7 @@ void up_clean_dcache(uintptr_t start, uintptr_t end)
   while (start < end);
 #endif /* !CONFIG_ARMV8M_DCACHE_WRITETHROUGH */
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif /* CONFIG_ARMV8M_DCACHE */
 
@@ -898,7 +886,7 @@ void up_clean_dcache_all(void)
 
   wshift = arm_clz(ways) & 0x1f;
 
-  ARM_DSB();
+  UP_DSB();
 
   /* Clean the entire D-Cache */
 
@@ -916,8 +904,7 @@ void up_clean_dcache_all(void)
   while (sets--);
 #endif /* !CONFIG_ARMV8M_DCACHE_WRITETHROUGH */
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif /* CONFIG_ARMV8M_DCACHE */
 
@@ -974,7 +961,7 @@ void up_flush_dcache(uintptr_t start, uintptr_t end)
 #endif
 
   start &= ~(ssize - 1);
-  ARM_DSB();
+  UP_DSB();
 
   do
     {
@@ -993,8 +980,7 @@ void up_flush_dcache(uintptr_t start, uintptr_t end)
     }
   while (start < end);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 #else
   up_invalidate_dcache(start, end);
 #endif /* !CONFIG_ARMV8M_DCACHE_WRITETHROUGH */
@@ -1054,7 +1040,7 @@ void up_flush_dcache_all(void)
 
   wshift = arm_clz(ways) & 0x1f;
 
-  ARM_DSB();
+  UP_DSB();
 
   /* Clean and invalidate the entire D-Cache */
 
@@ -1071,8 +1057,7 @@ void up_flush_dcache_all(void)
     }
   while (sets--);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 #else
   up_invalidate_dcache_all();
 #endif /* !CONFIG_ARMV8M_DCACHE_WRITETHROUGH */

arch/arm/src/armv8-m/arm_mpu.c

@@ -30,10 +30,10 @@
 #include <assert.h>
 #include <debug.h>
 #include <sys/param.h>
+#include <arch/barriers.h>
 
 #include "mpu.h"
 #include "arm_internal.h"
-#include "barriers.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -88,8 +88,7 @@ static void mpu_reset_internal(void)
 
   putreg32(0, MPU_CTRL);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 #endif
 
@@ -146,8 +145,7 @@ void mpu_freeregion(unsigned int region)
   putreg32(0, MPU_RLAR);
   putreg32(0, MPU_RBAR);
   g_mpu_region &= ~(1 << region);
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 
 /****************************************************************************
@@ -200,8 +198,7 @@ void mpu_control(bool enable, bool hfnmiena, bool privdefena)
 
   /* Ensure MPU setting take effects */
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 
 /****************************************************************************
@@ -254,8 +251,7 @@ void mpu_modify_region(unsigned int region, uintptr_t base, size_t size,
 
   /* Ensure MPU setting take effects */
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 
 /****************************************************************************

arch/arm/src/armv8-r/arm_arch_timer.c

@@ -30,12 +30,12 @@
 #include <stdio.h>
 
 #include <nuttx/arch.h>
+#include <arch/barriers.h>
 #include <arch/irq.h>
 #include <arch/chip/chip.h>
 #include <nuttx/spinlock.h>
 #include <nuttx/timers/arch_alarm.h>
 
-#include "barriers.h"
 #include "arm_gic.h"
 #include "arm_arch_timer.h"
 

arch/arm/src/armv8-r/arm_cache.c

@@ -28,9 +28,9 @@
 #include <nuttx/cache.h>
 #include <nuttx/irq.h>
 #include <sys/param.h>
+#include <arch/barriers.h>
 
 #include "cp15_cacheops.h"
-#include "barriers.h"
 #include "l2cc.h"
 
 /****************************************************************************

arch/arm/src/armv8-r/arm_gicv3.c

@@ -29,12 +29,12 @@
 #include <assert.h>
 
 #include <nuttx/arch.h>
+#include <arch/barriers.h>
 #include <arch/irq.h>
 #include <arch/chip/chip.h>
 #include <sched/sched.h>
 
 #include "arm_internal.h"
-#include "barriers.h"
 #include "arm_gic.h"
 
 /***************************************************************************
@@ -333,7 +333,7 @@ static void arm_gic_eoi_group0(unsigned int intid)
    * DEVICE nGnRnE attribute.
    */
 
-  ARM_DSB();
+  UP_DSB();
 
   /* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case
    * Write a Group 0 interrupt completion
@@ -367,7 +367,7 @@ void arm_gic_eoi(unsigned int intid)
    * DEVICE nGnRnE attribute.
    */
 
-  ARM_DSB();
+  UP_DSB();
 
   /* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case */
 
@@ -393,9 +393,9 @@ static int arm_gic_send_sgi(unsigned int sgi_id, uint64_t target_aff,
   sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id, SGIR_IRM_TO_AFF,
                              target_list);
 
-  ARM_DSB();
+  UP_DSB();
   CP15_SET64(ICC_SGI1R, sgi_val);
-  ARM_ISB();
+  UP_ISB();
 
   return 0;
 }

arch/arm/src/armv8-r/arm_l2cc_pl310.c

@@ -39,9 +39,9 @@
 
 #include <nuttx/irq.h>
 #include <nuttx/spinlock.h>
+#include <arch/barriers.h>
 
 #include "arm_internal.h"
-#include "barriers.h"
 #include "l2cc.h"
 #include "l2cc_pl310.h"
 
@@ -292,8 +292,7 @@ static void l2cc_disable_nolock(void)
   /* Disable the L2CC-P310 L2 cache by clearing the Control Register (CR) */
 
   putreg32(0, L2CC_CR);
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 
 /****************************************************************************
@@ -457,8 +456,7 @@ void arm_l2ccinitialize(void)
 
       l2cc_invalidate_all();
       putreg32(L2CC_CR_L2CEN, L2CC_CR);
-      ARM_DSB();
-      ARM_ISB();
+      UP_MB();
     }
 
   sinfo("(%d ways) * (%d bytes/way) = %d bytes\n",
@@ -533,8 +531,7 @@ void l2cc_enable(void)
 
   l2cc_invalidate_all_nolock();
   putreg32(L2CC_CR_L2CEN, L2CC_CR);
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
   spin_unlock_irqrestore(&g_l2cc_lock, flags);
 }
 

arch/arm/src/armv8-r/cp15_cacheops.c

@@ -113,7 +113,7 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
 
   line = cp15_dcache_linesize();
 
-  ARM_DSB();
+  UP_DSB();
 
   if ((start & (line - 1)) != 0)
     {
@@ -152,7 +152,7 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
       start += line;
     }
 
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -181,7 +181,7 @@ void cp15_dcache_op_level(uint32_t level, int op)
   way_shift = 32 - ilog2(ways);
   set_shift = ilog2(line);
 
-  ARM_DSB();
+  UP_DSB();
 
   /* A: Log2(ways)
    * B: L+S
@@ -220,7 +220,7 @@ void cp15_dcache_op_level(uint32_t level, int op)
         }
     }
 
-  ARM_ISB();
+  UP_ISB();
 }
 
 void cp15_invalidate_icache(uintptr_t start, uintptr_t end)
@@ -230,7 +230,7 @@ void cp15_invalidate_icache(uintptr_t start, uintptr_t end)
   line = cp15_icache_linesize();
   start &= ~(line - 1);
 
-  ARM_DSB();
+  UP_DSB();
 
   while (start < end)
     {
@@ -238,7 +238,7 @@ void cp15_invalidate_icache(uintptr_t start, uintptr_t end)
       start += line;
     }
 
-  ARM_ISB();
+  UP_ISB();
 }
 
 void cp15_coherent_dcache(uintptr_t start, uintptr_t end)

arch/arm/src/armv8-r/cp15_cacheops.h

@@ -594,7 +594,7 @@ static inline void cp15_enable_dcache(void)
   sctlr = CP15_GET(SCTLR);
   sctlr |= SCTLR_C;
   CP15_SET(SCTLR, sctlr);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -618,7 +618,7 @@ static inline void cp15_disable_dcache(void)
   sctlr = CP15_GET(SCTLR);
   sctlr &= ~SCTLR_C;
   CP15_SET(SCTLR, sctlr);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -642,7 +642,7 @@ static inline void cp15_enable_icache(void)
   sctlr = CP15_GET(SCTLR);
   sctlr |= SCTLR_I;
   CP15_SET(SCTLR, sctlr);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -666,7 +666,7 @@ static inline void cp15_disable_icache(void)
   sctlr = CP15_GET(SCTLR);
   sctlr &= ~SCTLR_I;
   CP15_SET(SCTLR, sctlr);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -686,7 +686,7 @@ static inline void cp15_disable_icache(void)
 static inline void cp15_invalidate_icache_inner_sharable(void)
 {
   CP15_SET(ICIALLUIS, 0);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -706,7 +706,7 @@ static inline void cp15_invalidate_icache_inner_sharable(void)
 static inline void cp15_invalidate_btb_inner_sharable(void)
 {
   CP15_SET(BPIALLIS, 0);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -727,7 +727,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void)
 static inline void cp15_invalidate_icache_all(void)
 {
   CP15_SET(ICIALLU, 0);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -747,7 +747,7 @@ static inline void cp15_invalidate_icache_all(void)
 static inline void cp15_invalidate_icache_bymva(unsigned int va)
 {
   CP15_SET(ICIMVAU, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -767,7 +767,7 @@ static inline void cp15_invalidate_icache_bymva(unsigned int va)
 static inline void cp15_flush_btb(void)
 {
   CP15_SET(BPIALL, 0);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -787,7 +787,7 @@ static inline void cp15_flush_btb(void)
 static inline void cp15_flush_btb_bymva(unsigned int va)
 {
   CP15_SET(BPIMVA, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -809,7 +809,7 @@ static inline void cp15_flush_btb_bymva(unsigned int va)
 static inline void cp15_invalidate_dcacheline_bymva(unsigned int va)
 {
   CP15_SET(DCIMVAC, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -831,7 +831,7 @@ static inline void cp15_invalidate_dcacheline_bymva(unsigned int va)
 static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway)
 {
   CP15_SET(DCISW, setway);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -853,7 +853,7 @@ static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway)
 static inline void cp15_clean_dcache_bymva(unsigned int va)
 {
   CP15_SET(DCCMVAC, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -873,7 +873,7 @@ static inline void cp15_clean_dcache_bymva(unsigned int va)
 static inline void cp15_clean_dcache_bysetway(unsigned int setway)
 {
   CP15_SET(DCCSW, setway);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -893,7 +893,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway)
 static inline void cp15_clean_ucache_bymva(unsigned int va)
 {
   CP15_SET(DCCMVAU, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -913,7 +913,7 @@ static inline void cp15_clean_ucache_bymva(unsigned int va)
 static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va)
 {
   CP15_SET(DCCIMVAC, va);
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************
@@ -933,7 +933,7 @@ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va)
 static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway)
 {
   CP15_SET(DCCISW, setway);
-  ARM_ISB();
+  UP_ISB();
 }
 
 #endif /* __ASSEMBLY__ */

arch/arm/src/armv8-r/sctlr.h

@@ -34,10 +34,9 @@
  * Included Files
  ****************************************************************************/
 
+#include <arch/barriers.h>
 #include <arch/irq.h>
 
-#include "barriers.h"
-
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
@@ -543,14 +542,14 @@ static inline unsigned int cp15_rdsctlr(void)
 static inline void cp15_wrsctlr(unsigned int sctlr)
 {
   CP15_SET(SCTLR, sctlr);
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
-  ARM_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
+  UP_NOP();
 }
 
 /* Read/write the vector base address register (VBAR) */

arch/arm/src/fvp-v8r-aarch32/fvp_boot.c

@@ -30,12 +30,12 @@
 #include <assert.h>
 #include <debug.h>
 
+#include <arch/barriers.h>
 #include <arch/irq.h>
 #include <arch/chip/chip.h>
 
 #include "arm_internal.h"
 
-#include "barriers.h"
 #include "arm_gic.h"
 #include "chip.h"
 #include "fvp_boot.h"
@@ -69,7 +69,7 @@ void arm_el_init(void)
   CP15_SET(ICC_HSRE, ICC_SRE_ELX_SRE_BIT | ICC_SRE_ELX_DFB_BIT |
                      ICC_SRE_ELX_DIB_BIT | ICC_SRE_EL3_EN_BIT);
 
-  ARM_ISB();
+  UP_ISB();
 }
 
 /****************************************************************************

arch/arm/src/imx6/imx_cpuboot.c

@@ -31,6 +31,7 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/sched.h>
+#include <arch/barriers.h>
 #include <arch/irq.h>
 
 #include "arm_internal.h"
@@ -40,7 +41,6 @@
 #include "scu.h"
 #include "gic.h"
 #include "mmu.h"
-#include "barriers.h"
 
 #ifdef CONFIG_SMP
 
@@ -209,7 +209,7 @@ void imx_cpu_enable(void)
 
       memcpy((uint32_t *)(PGTABLE_BASE_VADDR + PGTABLE_SIZE * cpu),
              (uint32_t *)PGTABLE_BASE_VADDR, PGTABLE_SIZE);
-      ARM_DSB();
+      UP_DSB();
 #endif
 
       /* Set the start up address */

arch/arm/src/imx9/imx9_clockconfig.c

@@ -34,8 +34,7 @@
 #include <sys/types.h>
 
 #include <arch/board/board.h>
-
-#include "barriers.h"
+#include <arch/barriers.h>
 
 #include "arm_internal.h"
 #include "hardware/imx9_gpc.h"
@@ -52,16 +51,6 @@
 
 #define ROOT_CLOCK_OFFSET 41
 
-/* Common barrier */
-
-#define mb()                                                                  \
-  do                                                                          \
-    {                                                                         \
-      ARM_DSB();                                                              \
-      ARM_ISB();                                                              \
-    }                                                                         \
-  while (0)
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/

arch/arm/src/imx9/imx9_mpuinit.c

@@ -32,8 +32,9 @@
 
 #include <nuttx/userspace.h>
 
+#include <arch/barriers.h>
+
 #include "mpu.h"
-#include "barriers.h"
 
 #include "hardware/imx9_memorymap.h"
 
@@ -104,7 +105,7 @@ void imx9_mpu_initialize(void)
 #ifdef CONFIG_ARMV7M_DCACHE
   /* Memory barrier */
 
-  ARM_DMB();
+  UP_DMB();
 #endif
 
 #ifdef CONFIG_BUILD_PROTECTED

arch/arm/src/imx9/imx9_start.c

@@ -34,9 +34,9 @@
 #include <nuttx/cache.h>
 #include <nuttx/init.h>
 #include <arch/board/board.h>
+#include <arch/barriers.h>
 
 #include "arm_internal.h"
-#include "barriers.h"
 #include "nvic.h"
 #include "mpu.h"
 
@@ -107,8 +107,7 @@ static inline void imx9_tcmenable(void)
 {
   uint32_t regval;
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 
   /* Enabled/disabled ITCM */
 
@@ -130,8 +129,7 @@ static inline void imx9_tcmenable(void)
 #endif
   putreg32(regval, NVIC_DTCMCR);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 
 /****************************************************************************

arch/arm/src/imxrt/imxrt106x_flash.c

@@ -31,14 +31,13 @@
 #include <nuttx/config.h>
 #include <nuttx/arch.h>
 #include <nuttx/mutex.h>
+#include <arch/barriers.h>
 #include <debug.h>
 
 #include <stdbool.h>
 #include <assert.h>
 #include <errno.h>
 
-#include "barriers.h"
-
 #include "hardware/rt106x/imxrt106x_memorymap.h"
 #include "arm_internal.h"
 

arch/arm/src/imxrt/imxrt_enet.c

@@ -35,7 +35,6 @@
 #include <assert.h>
 #include <debug.h>
 #include <errno.h>
-#include <barriers.h>
 #include <endian.h>
 
 #include <arpa/inet.h>
@@ -55,6 +54,7 @@
 #  include <nuttx/net/pkt.h>
 #endif
 
+#include <arch/barriers.h>
 #include <arch/board/board.h>
 
 #include "arm_internal.h"
@@ -778,7 +778,7 @@ static int imxrt_transmit(struct imxrt_driver_s *priv)
 #ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
   /* Make sure that descriptors are flushed */
 
-  ARM_DSB();
+  UP_DSB();
 #else
   up_clean_dcache((uintptr_t)txdesc,
                   (uintptr_t)txdesc + sizeof(struct enet_desc_s));
@@ -1033,7 +1033,7 @@ static void imxrt_receive(struct imxrt_driver_s *priv)
           rxdesc->status1 |= RXDESC_E;
 
 #ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
-          ARM_DSB();
+          UP_DSB();
 #else
           up_clean_dcache((uintptr_t)rxdesc,
                           (uintptr_t)rxdesc + sizeof(struct enet_desc_s));
@@ -1473,7 +1473,7 @@ static int imxrt_ifup_action(struct net_driver_s *dev, bool resetphy)
 #ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
   /* Make sure that descriptors are flushed */
 
-  ARM_DSB();
+  UP_DSB();
 #endif
 
   /* Indicate that there have been empty receive buffers produced */

arch/arm/src/imxrt/imxrt_flexio.c

@@ -35,6 +35,7 @@
 #include <assert.h>
 #include <debug.h>
 
+#include <arch/barriers.h>
 #include <arch/board/board.h>
 
 #include <nuttx/arch.h>
@@ -44,7 +45,6 @@
 #include <nuttx/mutex.h>
 
 #include "arm_internal.h"
-#include "barriers.h"
 
 #include "imxrt_gpio.h"
 #include "imxrt_periphclks.h"

arch/arm/src/imxrt/imxrt_flexspi.c

@@ -35,6 +35,7 @@
 #include <assert.h>
 #include <debug.h>
 
+#include <arch/barriers.h>
 #include <arch/board/board.h>
 
 #include <nuttx/arch.h>
@@ -44,7 +45,6 @@
 #include <nuttx/mutex.h>
 
 #include "arm_internal.h"
-#include "barriers.h"
 
 #include "imxrt_gpio.h"
 #include "imxrt_periphclks.h"

arch/arm/src/imxrt/imxrt_mpuinit.c

@@ -30,9 +30,9 @@
 #include <sys/param.h>
 
 #include <nuttx/userspace.h>
+#include <arch/barriers.h>
 
 #include "mpu.h"
-#include "barriers.h"
 
 #include "hardware/imxrt_memorymap.h"
 
@@ -101,7 +101,7 @@ void imxrt_mpu_initialize(void)
 #ifdef CONFIG_ARMV7M_DCACHE
   /* Memory barrier */
 
-  ARM_DMB();
+  UP_DMB();
 
 #ifdef CONFIG_IMXFT_QSPI
   /* Make QSPI memory region strongly ordered */

arch/arm/src/imxrt/imxrt_periphclks.c

@@ -28,8 +28,9 @@
 
 #include <stdint.h>
 
+#include <arch/barriers.h>
+
 #include "arm_internal.h"
-#include "barriers.h"
 #include "imxrt_periphclks.h"
 
 /****************************************************************************
@@ -72,8 +73,7 @@ void imxrt_periphclk_configure(unsigned int index, unsigned int value)
 
       putreg32(regval, IMXRT_CCM_LPCG_DIR(index));
 
-      ARM_DSB();
-      ARM_ISB();
+      UP_MB();
 
       /* Ensure the clock setting is written and active before we return */
 
@@ -105,8 +105,7 @@ void imxrt_periphclk_configure(uintptr_t regaddr, unsigned int index,
                                unsigned int value)
 {
   modifyreg32(regaddr, CCM_CCGRX_CG_MASK(index), CCM_CCGRX_CG(index, value));
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 
 #endif

arch/arm/src/imxrt/imxrt_start.c

@@ -32,10 +32,10 @@
 
 #include <nuttx/cache.h>
 #include <nuttx/init.h>
+#include <arch/barriers.h>
 #include <arch/board/board.h>
 
 #include "arm_internal.h"
-#include "barriers.h"
 #include "nvic.h"
 
 #include "imxrt_clockconfig.h"
@@ -101,8 +101,7 @@ static inline void imxrt_tcmenable(void)
 {
   uint32_t regval;
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 
   /* Enabled/disabled ITCM */
 
@@ -124,8 +123,7 @@ static inline void imxrt_tcmenable(void)
 #endif
   putreg32(regval, NVIC_DTCMCR);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 
 #ifdef CONFIG_ARMV7M_ITCM
   /* Copy TCM code from flash to ITCM */

arch/arm/src/mps/mps_start.c

@@ -28,10 +28,10 @@
 
 #include <nuttx/cache.h>
 #include <nuttx/init.h>
+#include <arch/barriers.h>
 #include <arch/board/board.h>
 
 #include "arm_internal.h"
-#include "barriers.h"
 #include "nvic.h"
 #include "mps_irq.h"
 #include "mps_userspace.h"
@@ -76,8 +76,7 @@ static inline void mps_tcmenable(void)
 {
   uint32_t regval;
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 
   /* Enabled/disabled ITCM */
 
@@ -99,8 +98,7 @@ static inline void mps_tcmenable(void)
 #endif
   putreg32(regval, NVIC_DTCMCR);
 
-  ARM_DSB();
-  ARM_ISB();
+  UP_MB();
 }
 
 /****************************************************************************
@@ -164,7 +162,7 @@ void __start(void)
 #ifdef CONFIG_ARMV7M_DCACHE
   /* Memory barrier */
 
-  ARM_DMB();
+  UP_DMB();
 
 #endif
 

arch/arm/src/mps/mps_userspace.c

@@ -30,9 +30,9 @@
 #include <assert.h>
 #include <sys/param.h>
 #include <nuttx/userspace.h>
+#include <arch/barriers.h>
 
 #include "mpu.h"
-#include "barriers.h"
 #include "arm_internal.h"
 #include "mps_userspace.h"
 

arch/arm/src/nrf52/nrf52_nvmc.c

@@ -43,8 +43,9 @@
 #include <nuttx/config.h>
 #include <stdbool.h>
 
+#include <arch/barriers.h>
+
 #include "arm_internal.h"
-#include "barriers.h"
 
 #include "hardware/nrf52_ficr.h"
 #include "hardware/nrf52_nvmc.h"
@@ -99,8 +100,7 @@ static inline void wait_for_flash_ready(void)
 
 static inline void nrf_mem_barrier(void)
 {
-  ARM_ISB();
-  ARM_DSB();
+  UP_MB();
 }
 
 /****************************************************************************