arch/riscv: use UP_DSB, UP_DMB, UP_ISB as barrier standard API

Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>

arch/risc-v/include/barriers.h

@@ -27,16 +27,16 @@
 
 #define __FENCE(p, s) __asm__ __volatile__ ("fence "#p", "#s  ::: "memory")
 
-/* __DMB() is used to flush local data caches (memory) */
+/* UP_DMB() is used to flush local data caches (memory) */
 
-#define __DMB()       __FENCE(rw, rw)
+#define UP_DMB()       __FENCE(rw, rw)
 
-/* __MB() is a full memory barrier */
+/* UP_DSB() is a full memory barrier */
 
-#define __MB()        __FENCE(iorw, iorw)
+#define UP_DSB()       __FENCE(iorw, iorw)
 
-/* __ISB() is used to synchronize the instruction and data streams */
+/* UP_ISB() is used to synchronize the instruction and data streams */
 
-#define __ISB()       __asm__ __volatile__ ("fence.i" ::: "memory")
+#define UP_ISB()       __asm__ __volatile__ ("fence.i" ::: "memory")
 
 #endif /* __ARCH_RISCV_INCLUDE_BARRIERS_H */

arch/risc-v/include/spinlock.h

@@ -31,6 +31,8 @@
 #  include <stdint.h>
 #endif /* __ASSEMBLY__ */
 
+#include <arch/barriers.h>
+
 /* Include RISC-V architecture-specific IRQ definitions (including register
  * save structure and up_irq_save()/up_irq_restore() functions)
  */
@@ -61,9 +63,6 @@
  *
  */
 
-#define UP_DSB() __asm__ __volatile__ ("fence")
-#define UP_DMB() __asm__ __volatile__ ("fence")
-
 /****************************************************************************
  * Public Types
  ****************************************************************************/

arch/risc-v/src/common/riscv_addrenv.c

@@ -176,7 +176,7 @@ static int create_spgtables(arch_addrenv_t *addrenv)
 
   /* Flush the data cache, so the changes are committed to memory */
 
-  __DMB();
+  UP_DMB();
 
   return i;
 }
@@ -312,7 +312,7 @@ static int create_region(arch_addrenv_t *addrenv, uintptr_t vaddr,
 
   /* Flush the data cache, so the changes are committed to memory */
 
-  __DMB();
+  UP_DMB();
 
   return npages;
 }
@@ -486,8 +486,8 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
 
   /* When all is set and done, flush the data caches */
 
-  __ISB();
-  __DMB();
+  UP_ISB();
+  UP_DMB();
 
   return OK;
 
@@ -528,8 +528,8 @@ int up_addrenv_destroy(arch_addrenv_t *addrenv)
 
   /* Make sure the caches are flushed before doing this */
 
-  __ISB();
-  __DMB();
+  UP_ISB();
+  UP_DMB();
 
   /* Things start from the beginning of the user virtual memory */
 
@@ -583,8 +583,8 @@ int up_addrenv_destroy(arch_addrenv_t *addrenv)
 
   /* When all is set and done, flush the caches */
 
-  __ISB();
-  __DMB();
+  UP_ISB();
+  UP_DMB();
 
   memset(addrenv, 0, sizeof(arch_addrenv_t));
   return OK;

arch/risc-v/src/common/riscv_addrenv_perms.c

@@ -97,8 +97,8 @@ static int modify_region(uintptr_t vstart, uintptr_t vend, uintptr_t setmask)
 
   /* When all is set and done, flush the data caches */
 
-  __ISB();
-  __DMB();
+  UP_ISB();
+  UP_DMB();
 
   return OK;
 }

arch/risc-v/src/common/riscv_addrenv_pgmap.c

@@ -215,7 +215,7 @@ int up_addrenv_kmap_init(void)
 
   /* When all is set and done, flush the data caches */
 
-  __DMB();
+  UP_DMB();
 
   return OK;
 }

arch/risc-v/src/common/riscv_addrenv_utils.c

@@ -108,7 +108,7 @@ uintptr_t riscv_get_pgtable(arch_addrenv_t *addrenv, uintptr_t vaddr)
 
   /* Flush the data cache, so the changes are committed to memory */
 
-  __DMB();
+  UP_DMB();
 
   return paddr;
 }
@@ -164,7 +164,7 @@ int riscv_map_pages(arch_addrenv_t *addrenv, uintptr_t *pages,
 
   /* Flush the data cache, so the changes are committed to memory */
 
-  __DMB();
+  UP_DMB();
 
   return OK;
 }
@@ -225,7 +225,7 @@ int riscv_unmap_pages(arch_addrenv_t *addrenv, uintptr_t vaddr,
 
   /* Flush the data cache, so the changes are committed to memory */
 
-  __DMB();
+  UP_DMB();
 
   return OK;
 }

arch/risc-v/src/common/riscv_mtimer.c

@@ -128,7 +128,7 @@ static void riscv_mtimer_set_mtimecmp(struct riscv_mtimer_lowerhalf_s *priv,
 
   /* Make sure it sticks */
 
-  __MB();
+  UP_DSB();
 }
 #else
 

arch/risc-v/src/common/riscv_percpu.c

@@ -154,7 +154,7 @@ void riscv_percpu_add_hart(uintptr_t hartid)
 
   /* Make sure it sticks */
 
-  __MB();
+  UP_DSB();
 }
 
 /****************************************************************************

arch/risc-v/src/common/riscv_pgalloc.c

@@ -158,7 +158,7 @@ uintptr_t pgalloc(uintptr_t brkaddr, unsigned int npages)
 
   /* Flush the data cache, so the changes are committed to memory */
 
-  __DMB();
+  UP_DMB();
 
   return brkaddr;
 }

arch/risc-v/src/mpfs/mpfs_gpio.c

@@ -102,7 +102,7 @@ static struct gpio_callback_s g_mss_gpio_callbacks[GPIO_BANK0_NUM_PINS +
 static void mpfs_gpio_irq_clear(int bank, int pin)
 {
   putreg32(1 << pin, g_gpio_base[bank] + MPFS_GPIO_INTR_OFFSET);
-  __MB();
+  UP_DSB();
 }
 
 /****************************************************************************

arch/risc-v/src/nuttsbi/sbi_mscratch.c

@@ -83,5 +83,5 @@ void sbi_mscratch_assign(uintptr_t hartid)
 
   /* Make sure mscratch is updated before continuing */
 
-  __MB();
+  UP_DSB();
 }

arch/risc-v/src/nuttsbi/sbi_mtimer.c

@@ -99,5 +99,5 @@ void sbi_set_mtimecmp(uint64_t value)
 
   /* Make sure it sticks */
 
-  __MB();
+  UP_DSB();
 }

libs/libc/machine/risc-v/arch_elf.c

@@ -130,7 +130,7 @@ static void _set_val(uint16_t *addr, uint32_t val)
 
   /* NOTE: Ensure relocation before execution */
 
-  __ISB();
+  UP_ISB();
 }
 
 static void _add_val(uint16_t *addr, uint32_t val)