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arch: arm: tiva: fix nxstyle errors

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Fix nxstyle errors to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea
2021-03-24 09:37:30 +01:00
committed by Xiang Xiao
parent fa0dd46c6c
commit 648b2669d1
112 changed files with 2703 additions and 1974 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/tiva/cc13xx/cc13x0_rom.c
+261 -186
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File diff suppressed because it is too large Load Diff
arch/arm/src/tiva/cc13xx/cc13x0_rom.h
+31 -24
View File
@@ -1,10 +1,11 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x0_rom.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* This is a port of TI's setup_rom.h file which has a fully compatible BSD license:
* This is a port of TI's setup_rom.h file which has a fully compatible
* BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,26 +37,26 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13X0_ROM_H
#define __ARCH_ARM_SRC_TIVA_CC13XX_CC13X0_ROM_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <stdint.h>
#include <nuttx/irq.h>
#include "hardware/tiva_aux_smph.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Start address of the ROM hard API access table (located after the ROM FW rev
* field)
/* Start address of the ROM hard API access table
* (located after the ROM FW rev field)
*/
#define ROM_HAPI_TABLE_ADDR 0x10000048
@@ -605,9 +606,9 @@
#define AUX_WUC_POWER_DOWN 0x00000002
#define AUX_WUC_POWER_ACTIVE 0x00000004
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/* ROM Hard-API function interface types */
@@ -659,7 +660,9 @@ typedef void (*fptr_adccompbin_t) (uint8_t /* signal */);
typedef void (*fptr_compbref_t) (uint8_t /* signal */);
/* Types used in the "Safe" interfaces taken from the TI DriverLib hw_types.h */
/* Types used in the "Safe" interfaces taken from the TI DriverLib
* hw_types.h
*/
typedef void (*fptr_void_void_t) (void);
typedef void (*fptr_void_uint8_t) (uint8_t);
@@ -691,9 +694,9 @@ struct hard_api_s
typedef struct hard_api_s hard_api_t;
/************************************************************************************
/****************************************************************************
* Global Function Prototypes
************************************************************************************/
****************************************************************************/
/* ROM functions implemented in FLASH */
@@ -708,26 +711,29 @@ uint32_t rom_setup_get_trim_xosc_hfibiastherm(void);
uint32_t rom_setup_get_trim_ampcompth1(void);
uint32_t rom_setup_get_trim_ampcompth2(void);
uint32_t rom_setup_get_trim_ampcompctrl(uint32_t fcfg1_revision);
uint32_t rom_setup_get_trim_dblrloopfilter_resetvoltage(uint32_t fcfg1_revision);
uint32_t
rom_setup_get_trim_dblrloopfilter_resetvoltage(uint32_t fcfg1_revision);
uint32_t rom_setup_get_trim_adcshmodeen(uint32_t fcfg1_revision);
uint32_t rom_setup_get_trim_adcshvbufen(uint32_t fcfg1_revision);
uint32_t rom_setup_get_trim_xosc_hfctrl(uint32_t fcfg1_revision);
uint32_t rom_setup_get_trim_xosc_hffaststart(void);
uint32_t rom_setup_get_trim_radc_extcfg(uint32_t fcfg1_revision);
uint32_t rom_setup_get_trim_rcosc_lfibiastrim(uint32_t fcfg1_revision);
uint32_t rom_setup_get_trim_lfregulator_cmirrwr_ratio(uint32_t fcfg1_revision);
uint32_t
rom_setup_get_trim_lfregulator_cmirrwr_ratio(uint32_t fcfg1_revision);
void rom_setup_cachemode(void);
void rom_setup_aonrtc_subsecinc(uint32_t subsecinc);
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: rom_signextend_vddrtrim
*
* Description:
* Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21)
* Sign extend the VDDR_TRIM setting
* (special format ranging from -10 to +21)
*
* Input Parameters
* vddrtrim - VDDR_TRIM setting
@@ -735,7 +741,7 @@ void rom_setup_aonrtc_subsecinc(uint32_t subsecinc);
* Returned Value:
* Returns sign extended VDDR_TRIM setting.
*
************************************************************************************/
****************************************************************************/
static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim)
{
@@ -752,7 +758,7 @@ static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim)
return signed_vaddrtrim;
}
/************************************************************************************
/****************************************************************************
* Name: rom_hapi_void and rom_hapi_auxadiselect
*
* Description:
@@ -765,7 +771,7 @@ static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim)
* Returned Value:
* None
*
************************************************************************************/
****************************************************************************/
inline static void rom_hapi_void(fptr_void_void_t fptr)
{
@@ -779,7 +785,8 @@ inline static void rom_hapi_void(fptr_void_void_t fptr)
leave_critical_section(flags);
}
inline static void rom_hapi_auxadiselect(fptr_void_uint8_t fptr, uint8_t signal)
inline static void rom_hapi_auxadiselect(fptr_void_uint8_t fptr,
uint8_t signal)
{
irqstate_t flags = enter_critical_section();
while (getreg32(TIVA_AUX_SMPH_SMPH0) == 0)
arch/arm/src/tiva/cc13xx/cc13x0_trim.c
+62 -58
View File
@@ -10,37 +10,38 @@
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 2) Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3) Neither the name NuttX nor the names of its contributors may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
* 3) Neither the name NuttX nor the names of its contributors may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
****************************************************************************/
/******************************************************************************
/****************************************************************************
* Included Files
******************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -59,11 +60,11 @@
#include "cc13xx/cc13x0_rom.h"
/******************************************************************************
/****************************************************************************
* Private Functions
******************************************************************************/
****************************************************************************/
/******************************************************************************
/****************************************************************************
* Name: trim_wakeup_frompowerdown
*
* Description:
@@ -73,14 +74,14 @@
* Returned Value:
* None
*
******************************************************************************/
****************************************************************************/
static void trim_wakeup_frompowerdown(void)
{
/* Currently no specific trim for Powerdown */
}
/******************************************************************************
/****************************************************************************
* Name: trim_wakeup_fromshutdown
*
* Description:
@@ -93,7 +94,7 @@ static void trim_wakeup_frompowerdown(void)
* Returned Value:
* None
*
******************************************************************************/
****************************************************************************/
static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
{
@@ -126,14 +127,16 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
{
/* ADI3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19]
* (=ALT_DCDC_DITHER_EN) ADI3_REFSYS:DCDCCTL5[2:0](=IPEAK ) =
* CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) Using a single 4-bit masked
* write since layout is equal for both source and destination
* CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK )
* Using a single 4-bit masked write since layout is equal for
* both source and destination
*/
regval = getreg32(TIVA_CCFG_MODE_CONF_1);
regval = (0xf0 | (regval >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_SHIFT));
putreg8((uint8_t)regval,
TIVA_ADI3_REFSYS_MASK4B + (TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET * 2));
TIVA_ADI3_REFSYS_MASK4B +
(TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET * 2));
}
/* Enable for JTAG to be powered down. The JTAG domain is automatically
@@ -167,7 +170,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
rom_setup_coldreset_from_shutdown_cfg2(fcfg1_revision, ccfg_modeconf);
/* Increased margin between digital supply voltage and VDD BOD during
* standby. VTRIM_UDIG: signed 4 bits value to be incremented by 2 (max = 7)
* standby.
* VTRIM_UDIG: signed 4 bits value to be incremented by 2 (max = 7)
* VTRIM_BOD: unsigned 4 bits value to be decremented by 1 (min = 0) This
* applies to chips with mp1rev < 542 for cc13x0 and for mp1rev < 527 for
* cc26x0
@@ -239,7 +243,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
putreg32(regval, TIVA_FLASH_CFG);
}
/******************************************************************************
/****************************************************************************
* Name: trim_coldreset
*
* Description:
@@ -248,28 +252,28 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
* Returned Value:
* None
*
******************************************************************************/
****************************************************************************/
static void trim_coldreset(void)
{
/* Currently no specific trim for Cold Reset */
}
/******************************************************************************
/****************************************************************************
* Public Functions
******************************************************************************/
****************************************************************************/
/******************************************************************************
/****************************************************************************
* Name: cc13xx_trim_device
*
* Description:
* Perform the necessary trim of the device which is not done in boot code
*
* This function should only execute coming from ROM boot. The current
* implementation does not take soft reset into account. However, it does no
* damage to execute it again. It only consumes time.
* implementation does not take soft reset into account. However, it does
* no damage to execute it again. It only consumes time.
*
******************************************************************************/
****************************************************************************/
void cc13xx_trim_device(void)
{
@@ -303,11 +307,11 @@ void cc13xx_trim_device(void)
putreg32(AUX_WUC_MODCLKEN1_SMPH, TIVA_AUX_WUC_MODCLKEN1);
/* Warm resets on CC13x0 and CC26x0 complicates software design because much
* of our software expect that initialization is done from a full system
* reset. This includes RTC setup, oscillator configuration and AUX setup. To
* ensure a full reset of the device is done when customers get e.g. a
* Watchdog reset, the following is set here:
/* Warm resets on CC13x0 and CC26x0 complicates software design because
* much of our software expect that initialization is done from a full
* system reset. This includes RTC setup, oscillator configuration and
* AUX setup. To ensure a full reset of the device is done when customers
* get e.g. a Watchdog reset, the following is set here:
*/
regval = getreg32(TIVA_PRCM_WARMRESET);
@@ -338,11 +342,11 @@ void cc13xx_trim_device(void)
trim_wakeup_frompowerdown();
}
/* Check for shutdown. When device is going to shutdown the hardware will
* automatically clear the SLEEPDIS bit in the SLEEP register in the
* AON_SYSCTL module. It is left for the application to assert this bit when
* waking back up, but not before the desired IO configuration has been
* re-established.
/* Check for shutdown.
* When device is going to shutdown the hardware will automatically clear
* the SLEEPDIS bit in the SLEEP register in the AON_SYSCTL module.
* It is left for the application to assert this bit when waking back
* up, but not before the desired IO configuration has been re-established.
*/
else if ((getreg32(TIVA_AON_SYSCTL_SLEEPCTL) &
@@ -358,8 +362,8 @@ void cc13xx_trim_device(void)
}
else
{
/* Consider adding a check for soft reset to allow debugging to skip this
* section!!! NB. This should be calling a ROM implementation of
/* Consider adding a check for soft reset to allow debugging to skip
* this section!!! NB. This should be calling a ROM implementation of
* required trim and compensation e.g. trim_coldreset() -->
* trim_wakeup_fromshutdown() --> trim_wakeup_frompowerdown()
*/
@@ -375,8 +379,8 @@ void cc13xx_trim_device(void)
putreg32(0, TIVA_PRCM_PDCTL1VIMS);
/* Configure optimal wait time for flash FSM in cases where flash pump wakes
* up from sleep
/* Configure optimal wait time for flash FSM in cases where flash pump
* wakes up from sleep
*/
regval = getreg32(TIVA_FLASH_FPAC1);
@@ -385,8 +389,8 @@ void cc13xx_trim_device(void)
putreg32(regval, TIVA_FLASH_FPAC1);
/* And finally at the end of the flash boot process: SET BOOT_DET bits in
* AON_SYSCTL to 3 if already found to be 1 Note: The BOOT_DET_x_CLR/SET bits
* must be manually cleared
* AON_SYSCTL to 3 if already found to be 1 Note: The BOOT_DET_x_CLR/SET
* bits must be manually cleared
*/
if ((getreg32(TIVA_AON_SYSCTL_RESETCTL) &
arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.c
+6 -6
View File
@@ -91,7 +91,7 @@ void rom_setup_stepvaddrtrimto(uint32_t tocode)
putreg32(pmctl_regsetctrl & ~AON_PMCTL_RESETCTL_VDDR_LOSS_EN,
TIVA_AON_PMCTL_RESETCTL);
/* Wait for VDDR_LOSS_EN setting to propagate */
/* Wait for VDDR_LOSS_EN setting to propagate */
getreg32(TIVA_AON_RTC_SYNC);
}
@@ -135,7 +135,7 @@ void rom_setup_stepvaddrtrimto(uint32_t tocode)
putreg32(pmctl_regsetctrl, TIVA_AON_PMCTL_RESETCTL);
/* And finally wait for VDDR_LOSS_EN setting to propagate */
/* And finally wait for VDDR_LOSS_EN setting to propagate */
getreg32(TIVA_AON_RTC_SYNC);
}
@@ -160,8 +160,8 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf)
{
/* Set VDDS_BOD trim - using masked write {MASK8:DATA8} - TRIM_VDDS_BOD
* is bits[7:3] of ADI3..REFSYSCTL1 - Needs a positive transition on
* BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to latch new VDDS BOD. Set to 0
* first to guarantee a positive transition.
* BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to latch new VDDS BOD.
* Set to 0 first to guarantee a positive transition.
*/
putreg8(ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN,
@@ -219,8 +219,8 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf)
setbits |= AON_PMCTL_PWRCTL_DCDC_EN;
}
/* Set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE Note: Inverse
* polarity
/* Set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE
* Note: Inverse polarity
*/
if ((ccfg_modeconf & CCFG_MODE_CONF_DCDC_ACTIVE) != 0)
arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h
+20 -18
View File
@@ -1,10 +1,11 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* This is a port of TI's rom.h file which has a fully compatible BSD license:
* This is a port of TI's rom.h file which has a fully compatible
* BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,17 +37,17 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_CC26X2_V1_ROM_H
#define __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_CC26X2_V1_ROM_H
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Start address of the ROM hard API access table (located after the ROM FW rev
* field)
/* Start address of the ROM hard API access table (located after the ROM FW
* rev field)
*/
#define ROM_HAPI_TABLE_ADDR 0x10000048
@@ -812,9 +813,9 @@
((void (*)(uint32_t powerconfig)) \
ROM_API_PWR_CTRL_TABLE[0])
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/* ROM Hard-API function interface types */
@@ -830,8 +831,8 @@ typedef uint32_t (*fptr_reserved1_t) (uint32_t);
typedef uint32_t (*fptr_reserved2_t) (void);
typedef uint32_t (*fptr_reserved3_t) (uint8_t *,\
uint32_t,\
typedef uint32_t (*fptr_reserved3_t) (uint8_t *, \
uint32_t, \
uint32_t);
typedef void (*fptr_resetdev_t) (void);
@@ -893,15 +894,16 @@ struct hard_api_s
typedef struct hard_api_s hard_api_t;
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: rom_signextend_vddrtrim
*
* Description:
* Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21)
* Sign extend the VDDR_TRIM setting
* (special format ranging from -10 to +21)
*
* Input Parameters
* vddrtrim - VDDR_TRIM setting
@@ -909,7 +911,7 @@ typedef struct hard_api_s hard_api_t;
* Returned Value:
* Returns sign extended VDDR_TRIM setting.
*
************************************************************************************/
****************************************************************************/
static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim)
{
@@ -926,9 +928,9 @@ static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim)
return signed_vaddrtrim;
}
/************************************************************************************
/****************************************************************************
* Global Function Prototypes
************************************************************************************/
****************************************************************************/
/* ROM functions implemented in FLASH */
arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h
+16 -14
View File
@@ -1,10 +1,11 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* This is a port of TI's rom.h file which has a fully compatible BSD license:
* This is a port of TI's rom.h file which has a fully compatible BSD
* license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,17 +37,17 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_CC26X2_V2_ROM_H
#define __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_CC26X2_V2_ROM_H
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Start address of the ROM hard API access table (located after the ROM FW rev
* field)
/* Start address of the ROM hard API access table
* (located after the ROM FW rev field)
*/
#define ROM_HAPI_TABLE_ADDR 0x10000048
@@ -968,9 +969,9 @@
((uint32_t (*)(uint32_t irqFlags)) \
ROM_API_SHA2_TABLE[5])
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/* ROM Hard-API function interface types */
@@ -1049,15 +1050,16 @@ struct hard_api_s
typedef struct hard_api_s hard_api_t;
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: rom_signextend_vddrtrim
*
* Description:
* Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21)
* Sign extend the VDDR_TRIM setting
* (special format ranging from -10 to +21)
*
* Input Parameters
* vddrtrim - VDDR_TRIM setting
@@ -1065,7 +1067,7 @@ typedef struct hard_api_s hard_api_t;
* Returned Value:
* Returns sign extended VDDR_TRIM setting.
*
************************************************************************************/
****************************************************************************/
static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim)
{
arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c
+28 -25
View File
@@ -25,17 +25,17 @@
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
@@ -224,8 +224,9 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
{
/* ADI3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19]
* (=ALT_DCDC_DITHER_EN) ADI3_REFSYS:DCDCCTL5[2:0](=IPEAK ) =
* CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) Using a single 4-bit masked
* write since layout is equal for both source and destination
* CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) Using a single 4-bit
* masked write since layout is equal for both source and
* destination
*/
regval = getreg32(TIVA_CCFG_MODE_CONF_1);
@@ -237,8 +238,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
/* TBD - Temporarily removed for CC13x2 / CC26x2 */
/* Force DCDC to use RCOSC before starting up XOSC. Clock loss detector does
* not use XOSC until SCLK_HF actually switches and thus DCDC is not
/* Force DCDC to use RCOSC before starting up XOSC. Clock loss detector
* does not use XOSC until SCLK_HF actually switches and thus DCDC is not
* protected from clock loss on XOSC in that time frame. The force must be
* released when the switch to XOSC has happened. This is done in
* OSCHfSourceSwitch().
@@ -292,7 +293,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
(((fusedata & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_MASK) >>
FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_SHIFT) <<
ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT));
putreg8(regval8, TIVA_ADI2_REFSYS_DIR + TIVA_ADI2_REFSYS_SOCLDOCTL1_OFFSET);
putreg8(regval8,
TIVA_ADI2_REFSYS_DIR + TIVA_ADI2_REFSYS_SOCLDOCTL1_OFFSET);
/* Write to register CTLSOCREFSYS0 (addr offset 0) bits[4:0] (TRIMIREF) in
* ADI2_REFSYS. Avoid using masked write access since bit field spans
@@ -303,7 +305,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
regval8 = (((fusedata & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_MASK) >>
FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_SHIFT) <<
ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT);
putreg8(regval8, TIVA_ADI2_REFSYS_DIR + TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET);
putreg8(regval8,
TIVA_ADI2_REFSYS_DIR + TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET);
/* Write to register CTLSOCREFSYS2 (addr offset 4) bits[7:4] (TRIMMAG) in
* ADI3_REFSYS
@@ -485,8 +488,8 @@ static void trim_coldreset(void)
* Perform the necessary trim of the device which is not done in boot code
*
* This function should only execute coming from ROM boot. The current
* implementation does not take soft reset into account. However, it does no
* damage to execute it again. It only consumes time.
* implementation does not take soft reset into account. However, it does
* no damage to execute it again. It only consumes time.
*
****************************************************************************/
@@ -577,8 +580,8 @@ void cc13xx_trim_device(void)
putreg32(0, TIVA_PRCM_PDCTL1VIMS);
/* Configure optimal wait time for flash FSM in cases where flash pump wakes
* up from sleep
/* Configure optimal wait time for flash FSM in cases where flash pump
* wakes up from sleep
*/
regval = getreg32(TIVA_FLASH_FPAC1);
@@ -587,8 +590,8 @@ void cc13xx_trim_device(void)
putreg32(regval, TIVA_FLASH_FPAC1);
/* And finally at the end of the flash boot process: SET BOOT_DET bits in
* AON_PMCTL to 3 if already found to be 1 Note: The BOOT_DET_x_CLR/SET bits
* must be manually cleared
* AON_PMCTL to 3 if already found to be 1 Note: The BOOT_DET_x_CLR/SET
* bits must be manually cleared
*/
if ((getreg32(TIVA_AON_PMCTL_RESETCTL) &
@@ -608,8 +611,8 @@ void cc13xx_trim_device(void)
}
/* Make sure there are no ongoing VIMS mode change when leaving
* cc13x2_cc26x2_trim_device() (There should typically be no wait time here,
* but need to be sure)
* cc13x2_cc26x2_trim_device() (There should typically be no wait time
* here, but need to be sure)
*/
while ((getreg32(TIVA_VIMS_STAT) & VIMS_STAT_MODE_CHANGING) != 0)
arch/arm/src/tiva/cc13xx/cc13xx_chipinfo.c
+42 -36
View File
@@ -1,4 +1,4 @@
/*****************************************************************************
/****************************************************************************
* arch/arm/src/tiva/cc13xx/cc13xx_chipinfo.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
@@ -37,11 +37,11 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
****************************************************************************/
/*****************************************************************************
/****************************************************************************
* Included Files
*****************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -51,11 +51,11 @@
#include "hardware/tiva_prcm.h"
#include "tiva_chipinfo.h"
/*****************************************************************************
/****************************************************************************
* Public Functions
*****************************************************************************/
****************************************************************************/
/*****************************************************************************
/****************************************************************************
* Name: chipinfo_protocols
*
* Description:
@@ -64,18 +64,19 @@
* Returned Value:
* Returns a bit set indicating supported protocols.
*
*****************************************************************************/
****************************************************************************/
enum cc13xx_protocol_e chipinfo_protocols(void)
{
/* Return allowed RTC modes.
* REVISIT: Per fcfg1 header file, the allowed RGC modes are in bits 0-2. */
* REVISIT: Per fcfg1 header file, the allowed RGC modes are in bits 0-2.
*/
uint32_t regval = getreg32(TIVA_PRCM_RFCMODEHWOPT);
return (enum cc13xx_protocol_e)(regval & 0x0e);
uint32_t regval = getreg32(TIVA_PRCM_RFCMODEHWOPT);
return (enum cc13xx_protocol_e)(regval & 0x0e);
}
/*****************************************************************************
/****************************************************************************
* Name: chipinfo_packagetype
*
* Description:
@@ -84,7 +85,7 @@ enum cc13xx_protocol_e chipinfo_protocols(void)
* Returned Value:
* Returns an enumeration value indicating the package type.
*
*****************************************************************************/
****************************************************************************/
enum cc13xx_package_e chipinfo_packagetype(void)
{
@@ -102,7 +103,7 @@ enum cc13xx_package_e chipinfo_packagetype(void)
return pkgtype;
}
/*****************************************************************************
/****************************************************************************
* Name: chipinfo_chiptype
*
* Description:
@@ -111,7 +112,7 @@ enum cc13xx_package_e chipinfo_packagetype(void)
* Returned Value:
* Returns an enumeration value indicating the chip type
*
*****************************************************************************/
****************************************************************************/
enum cc13xx_chiptype_e chipinfo_chiptype(void)
{
@@ -147,13 +148,13 @@ enum cc13xx_chiptype_e chipinfo_chiptype(void)
#elif defined(CONFIG_ARCH_CHIP_CC13X2)
cc13 = ((userid & FCFG1_USER_ID_CC13) != 0); /* CC13xx device type (vs CC26xx) */
pa = ((userid & FCFG1_USER_ID_PA) != 0); /* Supports 20dBM PA */
cc13 = ((userid & FCFG1_USER_ID_CC13) != 0); /* CC13xx device type (vs CC26xx) */
pa = ((userid & FCFG1_USER_ID_PA) != 0); /* Supports 20dBM PA */
if (chipfamily == FAMILY_CC13x2_CC26x2)
{
switch (protocol)
{
if (chipfamily == FAMILY_CC13x2_CC26x2)
{
switch (protocol)
{
case 0xf:
if (cc13)
{
@@ -195,7 +196,7 @@ enum cc13xx_chiptype_e chipinfo_chiptype(void)
return chiptype;
}
/*****************************************************************************
/****************************************************************************
* Name: chipinfo_chipfamily
*
* Description:
@@ -204,7 +205,7 @@ enum cc13xx_chiptype_e chipinfo_chiptype(void)
* Returned Value:
* Returns an enumeration value indicating the chip family
*
*****************************************************************************/
****************************************************************************/
enum cc13xx_chipfamily_e chipinfo_chipfamily(void)
{
@@ -220,28 +221,30 @@ enum cc13xx_chipfamily_e chipinfo_chipfamily(void)
if (waferid == 0xb9be)
{
chipfamily = FAMILY_CC13x0;
}
}
#elif defined(CONFIG_ARCH_CHIP_CC13X2)
if (waferid == 0xbb41)
{
chipfamily = FAMILY_CC13x2_CC26x2;
}
}
#endif
return chipfamily;
return chipfamily;
}
/*****************************************************************************
/****************************************************************************
* Name: chipinfo_hwrevision
*
* Description:
* Returns an enumeration value indicating the hardware revision of the chip
* Returns an enumeration value indicating the hardware revision of the
* chip
*
* Returned Value:
* Returns an enumeration value indicating the hardware revision of the chip
* Returns an enumeration value indicating the hardware revision of the
* chip
*
*****************************************************************************/
****************************************************************************/
enum cc13xx_revision_e chipinfo_hwrevision(void)
{
@@ -265,7 +268,8 @@ enum cc13xx_revision_e chipinfo_hwrevision(void)
break;
case 2: /* CC13x0 PG2.0 (or later) */
hwrev = (enum cc13xx_revision_e)(((uint32_t)HWREV_2_0) + hwminorrev);
hwrev = (enum cc13xx_revision_e)(((uint32_t)HWREV_2_0) +
hwminorrev);
break;
}
}
@@ -281,21 +285,23 @@ enum cc13xx_revision_e chipinfo_hwrevision(void)
break;
case 2: /* CC13x2, CC26x2 - PG1.1 (or later) */
hwrev = (enum cc13xx_revision_e)(((uint32_t)HWREV_1_1) + hwminorrev);
hwrev = (enum cc13xx_revision_e)(((uint32_t)HWREV_1_1) +
hwminorrev);
break;
case 3: /* CC13x2, CC26x2 - PG2.1 (or later) */
hwrev = (enum cc13xx_revision_e)(((uint32_t)HWREV_2_1) + hwminorrev);
hwrev = (enum cc13xx_revision_e)(((uint32_t)HWREV_2_1) +
hwminorrev);
break;
}
}
#endif
return hwrev;
return hwrev;
}
/*****************************************************************************
/****************************************************************************
* Name: chipinfo_verify
*
* Description:
@@ -305,7 +311,7 @@ enum cc13xx_revision_e chipinfo_hwrevision(void)
* Returned Value:
* None
*
*****************************************************************************/
****************************************************************************/
#ifdef CONFIG_DEBUG_ASSERTIONS
void chipinfo_verify(void)
arch/arm/src/tiva/cc13xx/cc13xx_enableclks.h
+12 -12
View File
@@ -1,4 +1,4 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/cc13xx/cc13xx_enableclks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_ENABLECLKS_H
#define __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_ENABLECLKS_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "cc13xx/cc13xx_prcm.h"
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
****************************************************************************/
#define CC13XX_RUNMODE_CLOCK (1 << 0)
#define CC13XX_SLEEPMODE_CLOCK (1 << 1)
@@ -218,27 +218,27 @@
#define tiva_trng_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_TRNG, CC13XX_ALLMODE_CLOCKS)
#define tiva_trng_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_TRNG, CC13XX_ALLMODE_CLOCKS)
/****************************************************************************************************
/****************************************************************************
* Public Function Prototypes
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
/****************************************************************************
* Name: cc13xx_periph_enableclks
*
* Description:
* Enable clocking in the selected modes for this peripheral.
*
****************************************************************************************************/
****************************************************************************/
void cc13xx_periph_enableclk(uint32_t peripheral, uint32_t modeset);
/****************************************************************************************************
/****************************************************************************
* Name: cc13xx_periph_disableclk
*
* Description:
* Disable clocking in the selected modes for this peripheral.
*
****************************************************************************************************/
****************************************************************************/
void cc13xx_periph_disableclk(uint32_t peripheral, uint32_t modeset);
arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.h
+16 -15
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_ENABLEPWR_H
#define __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_ENABLEPWR_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "cc13xx/cc13xx_prcm.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* CC13xx Power Domains:
*
* 1) PRCM_DOMAIN_RFCORE : RF Core
* 2) PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0
* 3) PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1
* 3) PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1,
* I2S, DMA, UART1
* 4) PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM
* 5) PRCM_DOMAIN_SYSBUS
* 6) PRCM_DOMAIN_CPU
@@ -121,28 +122,28 @@
#define tiva_trng_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_TRNG)
#define tiva_trng_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_TRNG)
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: cc13xx_periph_enablepwr
*
* Description:
* Enable the power domain associated with the peripheral.
*
************************************************************************************/
****************************************************************************/
void cc13xx_periph_enablepwr(uint32_t peripheral);
/************************************************************************************
/****************************************************************************
* Name: cc13xx_periph_disablepwr
*
* Description:
* Disable the power domain associated with the peripheral if and only if all
* peripherals using that power domain no longer need power.
* Disable the power domain associated with the peripheral if and only if
* all peripherals using that power domain no longer need power.
*
************************************************************************************/
****************************************************************************/
void cc13xx_periph_disablepwr(uint32_t peripheral);
arch/arm/src/tiva/chip.h
+9 -9
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_CHIP_H
#define __ARCH_ARM_SRC_TIVA_CHIP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <arch/tiva/chip.h>
@@ -43,13 +43,13 @@
#include "hardware/tiva_timer.h" /* Timer */
#include "hardware/tiva_adc.h" /* ADC */
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Provide the required number of peripheral interrupt vector definitions as well.
* The definition TIVA_IRQ_NEXTINT simply comes from the chip-specific IRQ header
* file included by arch/tiva/irq.h.
/* Provide the required number of peripheral interrupt vector definitions as
* well. The definition TIVA_IRQ_NEXTINT simply comes from the chip-specific
* IRQ header file included by arch/tiva/irq.h.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS TIVA_IRQ_NEXTINT
arch/arm/src/tiva/common/lmxx_tm4c_enableclks.h
+8 -8
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/common/lmxx_tm4c_enableclks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_COMMON_LMXX_TM4C_ENABLECLKS_H
#define __ARCH_ARM_SRC_TIVA_COMMON_LMXX_TM4C_ENABLECLKS_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,12 +31,12 @@
#include "chip.h"
#include "hardware/tiva_sysctrl.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Clocks are enabled or disabled by setting or clearing a bit (b) in a system
* control register (a))
/* Clocks are enabled or disabled by setting or clearing a bit (b) in a
* system control register (a))
*/
#define tiva_enableclk(a,b) modifyreg32((a),0,(b))
arch/arm/src/tiva/common/lmxx_tm4c_enablepwr.h
+8 -8
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/common/lmxx_tm4c_enablepwr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_COMMON_LMXX_TM4C_ENABLEPWR_H
#define __ARCH_ARM_SRC_TIVA_COMMON_LMXX_TM4C_ENABLEPWR_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,12 +31,12 @@
#include "chip.h"
#include "hardware/tiva_sysctrl.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Power control is enabled or disabled by setting or clearing a bit (b) in a system
* control register (a))
/* Power control is enabled or disabled by setting or clearing a bit (b) in
* a system control register (a))
*/
#define tiva_enablepwr(a, b) modifyreg32((a), 0, (b))
arch/arm/src/tiva/common/tiva_i2c.c
+151 -119
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/tiva/common/tiva_pwm.c
+64 -44
View File
@@ -1,11 +1,11 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/common/tiva_pwm.c
*
* Copyright (C) 2016 Young Mu. All rights reserved.
* Author: Young Mu <young.mu@aliyun.com>
*
* The basic structure of this driver derives in spirit (if nothing more) from the
* NuttX SAM PWM driver which has:
* The basic structure of this driver derives in spirit (if nothing more)
* from the NuttX SAM PWM driver which has:
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -37,11 +37,11 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -61,9 +61,9 @@
#include "hardware/tiva_pinmap.h"
#include "hardware/tiva_memorymap.h"
/************************************************************************************
/****************************************************************************
* Private Types
************************************************************************************/
****************************************************************************/
uint32_t g_pwm_pinset[] =
{
@@ -94,24 +94,28 @@ struct tiva_pwm_chan_s
#endif
};
/************************************************************************************
/****************************************************************************
* Private Function Prototypes
************************************************************************************/
****************************************************************************/
#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN0)
static int tiva_pwm_gen0_interrupt(int irq, FAR void *context, FAR void *arg);
static int tiva_pwm_gen0_interrupt(int irq,
FAR void *context, FAR void *arg);
#endif
#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN2)
static int tiva_pwm_gen1_interrupt(int irq, FAR void *context, FAR void *arg);
static int tiva_pwm_gen1_interrupt(int irq,
FAR void *context, FAR void *arg);
#endif
#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN4)
static int tiva_pwm_gen2_interrupt(int irq, FAR void *context, FAR void *arg);
static int tiva_pwm_gen2_interrupt(int irq,
FAR void *context, FAR void *arg);
#endif
#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN6)
static int tiva_pwm_gen3_interrupt(int irq, FAR void *context, FAR void *arg);
static int tiva_pwm_gen3_interrupt(int irq,
FAR void *context, FAR void *arg);
#endif
#if defined(CONFIG_PWM_PULSECOUNT) && \
@@ -131,7 +135,8 @@ static int tiva_pwm_setup(FAR struct pwm_lowerhalf_s *dev);
static int tiva_pwm_shutdown(FAR struct pwm_lowerhalf_s *dev);
#ifdef CONFIG_PWM_PULSECOUNT
static int tiva_pwm_start(FAR struct pwm_lowerhalf_s *dev,
FAR const struct pwm_info_s *info, FAR void *handle);
FAR const struct pwm_info_s *info,
FAR void *handle);
#else
static int tiva_pwm_start(FAR struct pwm_lowerhalf_s *dev,
FAR const struct pwm_info_s *info);
@@ -140,9 +145,9 @@ static int tiva_pwm_stop(FAR struct pwm_lowerhalf_s *dev);
static int tiva_pwm_ioctl(FAR struct pwm_lowerhalf_s *dev,
int cmd, unsigned long arg);
/************************************************************************************
/****************************************************************************
* Private Data
************************************************************************************/
****************************************************************************/
static uint32_t g_pwm_freq = 1875000;
static uint32_t g_pwm_counter = (1 << 16);
@@ -163,7 +168,8 @@ static struct tiva_pwm_chan_s g_pwm_chan0 =
.controller_id = 0,
.controller_base = TIVA_PWM0_BASE,
.generator_id = 0,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 0,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE +
TIVA_PWMn_INTERVAL * 0,
.channel_id = 0,
#ifdef CONFIG_PWM_PULSECOUNT
.inited = false,
@@ -182,7 +188,8 @@ static struct tiva_pwm_chan_s g_pwm_chan1 =
.controller_id = 0,
.controller_base = TIVA_PWM0_BASE,
.generator_id = 0,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 0,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE +
TIVA_PWMn_INTERVAL * 0,
.channel_id = 1,
#ifdef CONFIG_PWM_PULSECOUNT
.inited = false,
@@ -201,7 +208,8 @@ static struct tiva_pwm_chan_s g_pwm_chan2 =
.controller_id = 0,
.controller_base = TIVA_PWM0_BASE,
.generator_id = 1,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 1,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE +
TIVA_PWMn_INTERVAL * 1,
.channel_id = 2,
#ifdef CONFIG_PWM_PULSECOUNT
.inited = false,
@@ -220,7 +228,8 @@ static struct tiva_pwm_chan_s g_pwm_chan3 =
.controller_id = 0,
.controller_base = TIVA_PWM0_BASE,
.generator_id = 1,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 1,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE +
TIVA_PWMn_INTERVAL * 1,
.channel_id = 3,
#ifdef CONFIG_PWM_PULSECOUNT
.inited = false,
@@ -239,7 +248,8 @@ static struct tiva_pwm_chan_s g_pwm_chan4 =
.controller_id = 0,
.controller_base = TIVA_PWM0_BASE,
.generator_id = 2,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 2,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE +
TIVA_PWMn_INTERVAL * 2,
.channel_id = 4,
#ifdef CONFIG_PWM_PULSECOUNT
.inited = false,
@@ -258,7 +268,8 @@ static struct tiva_pwm_chan_s g_pwm_chan5 =
.controller_id = 0,
.controller_base = TIVA_PWM0_BASE,
.generator_id = 2,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 2,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE +
TIVA_PWMn_INTERVAL * 2,
.channel_id = 5,
#ifdef CONFIG_PWM_PULSECOUNT
.inited = false,
@@ -277,7 +288,8 @@ static struct tiva_pwm_chan_s g_pwm_chan6 =
.controller_id = 0,
.controller_base = TIVA_PWM0_BASE,
.generator_id = 3,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 3,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE +
TIVA_PWMn_INTERVAL * 3,
.channel_id = 6,
#ifdef CONFIG_PWM_PULSECOUNT
.inited = false,
@@ -296,7 +308,8 @@ static struct tiva_pwm_chan_s g_pwm_chan7 =
.controller_id = 0,
.controller_base = TIVA_PWM0_BASE,
.generator_id = 3,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 3,
.generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE +
TIVA_PWMn_INTERVAL * 3,
.channel_id = 7,
#ifdef CONFIG_PWM_PULSECOUNT
.inited = false,
@@ -308,17 +321,17 @@ static struct tiva_pwm_chan_s g_pwm_chan7 =
};
#endif
/************************************************************************************
/****************************************************************************
* Private Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: tiva_pwm_gen[n]_interrupt
*
* Description:
* Pulse count interrupt handlers for PWM[n]
*
************************************************************************************/
****************************************************************************/
#if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN0)
static int tiva_pwm_gen0_interrupt(int irq, FAR void *context, FAR void *arg)
@@ -348,13 +361,13 @@ static int tiva_pwm_gen3_interrupt(int irq, FAR void *context, FAR void *arg)
}
#endif
/************************************************************************************
/****************************************************************************
* Name: tiva_pwm_interrupt
*
* Description:
* Common pulse count interrupt handler.
*
************************************************************************************/
****************************************************************************/
#if defined(CONFIG_PWM_PULSECOUNT) && \
(defined(CONFIG_TIVA_PWM0_CHAN0) || defined(CONFIG_TIVA_PWM0_CHAN2) || \
@@ -373,7 +386,8 @@ static int tiva_pwm_interrupt(struct tiva_pwm_chan_s *chan)
if (chan->cur_count == 0)
{
tiva_pwm_putreg(chan, TIVA_PWMn_CTL_OFFSET, CTL_DISABLE << TIVA_PWMn_CTL_ENABLE);
tiva_pwm_putreg(chan, TIVA_PWMn_CTL_OFFSET,
CTL_DISABLE << TIVA_PWMn_CTL_ENABLE);
chan->cur_count = chan->count;
pwm_expired(chan->handle);
}
@@ -382,28 +396,28 @@ static int tiva_pwm_interrupt(struct tiva_pwm_chan_s *chan)
}
#endif
/************************************************************************************
/****************************************************************************
* Name: tiva_pwm_getreg
*
* Description:
* Get a 32-bit register value by offset
*
************************************************************************************/
****************************************************************************/
static inline uint32_t tiva_pwm_getreg(struct tiva_pwm_chan_s *chan,
unsigned int offset)
{
uintptr_t regaddr = chan->generator_base + offset;
return getreg32(regaddr);
uintptr_t regaddr = chan->generator_base + offset;
return getreg32(regaddr);
}
/************************************************************************************
/****************************************************************************
* Name: tiva_pwm_putreg
*
* Description:
* Put a 32-bit register value by offset
*
************************************************************************************/
****************************************************************************/
static inline void tiva_pwm_putreg(struct tiva_pwm_chan_s *chan,
unsigned int offset, uint32_t regval)
@@ -500,7 +514,8 @@ static int tiva_pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
#ifdef CONFIG_PWM_PULSECOUNT
static int tiva_pwm_start(FAR struct pwm_lowerhalf_s *dev,
FAR const struct pwm_info_s *info, FAR void *handle)
FAR const struct pwm_info_s *info,
FAR void *handle)
{
FAR struct tiva_pwm_chan_s *chan = (FAR struct tiva_pwm_chan_s *)dev;
pwminfo("start PWM for channel %d\n", chan->channel_id);
@@ -533,7 +548,8 @@ static int tiva_pwm_start(FAR struct pwm_lowerhalf_s *dev,
/* Disable interrupt */
uint32_t enable = getreg32(chan->controller_base + TIVA_PWM_INTEN_OFFSET);
uint32_t enable = getreg32(chan->controller_base +
TIVA_PWM_INTEN_OFFSET);
enable &= ~(INT_ENABLE << chan->generator_id);
putreg32(enable, chan->controller_base + TIVA_PWM_INTEN_OFFSET);
}
@@ -541,7 +557,8 @@ static int tiva_pwm_start(FAR struct pwm_lowerhalf_s *dev,
{
/* Enable interrupt */
uint32_t enable = getreg32(chan->controller_base + TIVA_PWM_INTEN_OFFSET);
uint32_t enable = getreg32(chan->controller_base +
TIVA_PWM_INTEN_OFFSET);
enable |= (INT_ENABLE << chan->generator_id);
putreg32(enable, chan->controller_base + TIVA_PWM_INTEN_OFFSET);
}
@@ -642,7 +659,9 @@ static inline int tiva_pwm_timer(FAR struct tiva_pwm_chan_s *chan,
/* Enable the PWM generator (refer to TM4C1294NCPDT 23.4.10) */
tiva_pwm_putreg(chan, TIVA_PWMn_CTL_OFFSET, CTL_ENABLE << TIVA_PWMn_CTL_ENABLE);
tiva_pwm_putreg(chan,
TIVA_PWMn_CTL_OFFSET,
CTL_ENABLE << TIVA_PWMn_CTL_ENABLE);
/* Enable PWM channel (refer to TM4C1294NCPDT 23.4.11) */
@@ -817,7 +836,8 @@ FAR struct pwm_lowerhalf_s *tiva_pwm_initialize(int channel)
* TODO: need an algorithm to choose the best divider and load value combo.
*/
putreg32(CC_USEPWM << TIVA_PWM_CC_USEPWM | CC_PWMDIV_64 << TIVA_PWM_CC_PWMDIV,
putreg32(CC_USEPWM << TIVA_PWM_CC_USEPWM |
CC_PWMDIV_64 << TIVA_PWM_CC_PWMDIV,
chan->controller_base + TIVA_PWM_CC);
#ifdef CONFIG_PWM_PULSECOUNT
@@ -826,7 +846,7 @@ FAR struct pwm_lowerhalf_s *tiva_pwm_initialize(int channel)
tiva_pwm_putreg(chan, TIVA_PWMn_INTEN_OFFSET, INT_SET << INTCMPAD);
/* Attach IRQ handler and enable interrupt*/
/* Attach IRQ handler and enable interrupt */
switch (chan->channel_id)
{
arch/arm/src/tiva/common/tiva_timerlib.c
+189 -98
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h
+14 -11
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,24 +37,24 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI2_REFSYS_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI2_REFSYS_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
#include "hardware/tiva_ddi.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* ADI2 REFSYS Register Offsets *************************************************************************************/
/* ADI2 REFSYS Register Offsets *********************************************/
#define TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET 0x0000
#define TIVA_ADI2_REFSYS_SOCLDOCTL0_OFFSET 0x0002
@@ -66,7 +67,7 @@
#define TIVA_ADI2_REFSYS_HPOSCCTL1_OFFSET 0x000b
#define TIVA_ADI2_REFSYS_HPOSCCTL2_OFFSET 0x000c
/* ADI2 REFSYS Register Addresses ***********************************************************************************/
/* ADI2 REFSYS Register Addresses *******************************************/
#define TIVA_ADI2_REFSYS_REFSYSCTL0 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET)
#define TIVA_ADI2_REFSYS_SOCLDOCTL0 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL0_OFFSET)
@@ -79,7 +80,9 @@
#define TIVA_ADI2_REFSYS_HPOSCCTL1 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL1_OFFSET)
#define TIVA_ADI2_REFSYS_HPOSCCTL2 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL2_OFFSET)
/* Offsets may also be used in conjunction with access as described in cc13x0_ddi.h */
/* Offsets may also be used in conjunction with access as described in
* cc13x0_ddi.h
*/
#define TIVA_ADI2_REFSYS_DIR (TIVA_ADI2_BASE + TIVA_DDI_DIR_OFFSET)
#define TIVA_ADI2_REFSYS_SET (TIVA_ADI2_BASE + TIVA_DDI_SET_OFFSET)
@@ -88,7 +91,7 @@
#define TIVA_ADI2_REFSYS_MASK8B (TIVA_ADI2_BASE + TIVA_DDI_MASK8B_OFFSET)
#define TIVA_ADI2_REFSYS_MASK16B (TIVA_ADI2_BASE + TIVA_DDI_MASK16B_OFFSET)
/* ADI2 REFSYS Bitfield Definitions *********************************************************************************/
/* ADI2 REFSYS Bitfield Definitions *****************************************/
/* TIVA_ADI2_REFSYS_REFSYSCTL0 */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h
+17 -11
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,24 +37,24 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI3_REFSYS_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI3_REFSYS_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
#include "hardware/tiva_ddi.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* ADI3 REFSYS Register Offsets *************************************************************************************/
/* ADI3 REFSYS Register Offsets *********************************************/
#define TIVA_ADI3_REFSYS_SPARE0_OFFSET 0x0001 /* Analog Test Control */
#define TIVA_ADI3_REFSYS_REFSYSCTL0_OFFSET 0x0002
@@ -67,7 +68,7 @@
#define TIVA_ADI3_REFSYS_DCDCCTL4_OFFSET 0x000a
#define TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET 0x000b
/* ADI3 REFSYS Register Addresses ***********************************************************************************/
/* ADI3 REFSYS Register Addresses *******************************************/
#define TIVA_ADI3_REFSYS_SPARE0 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_SPARE0_OFFSET)
#define TIVA_ADI3_REFSYS_REFSYSCTL0 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_REFSYSCTL0_OFFSET)
@@ -81,7 +82,9 @@
#define TIVA_ADI3_REFSYS_DCDCCTL4 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL4_OFFSET)
#define TIVA_ADI3_REFSYS_DCDCCTL5 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET)
/* Offsets may also be used in conjunction with access as described in cc13x0_ddi.h */
/* Offsets may also be used in conjunction with access as described in
* cc13x0_ddi.h
*/
#define TIVA_ADI3_REFSYS_DIR (TIVA_ADI3_BASE + TIVA_DDI_DIR_OFFSET)
#define TIVA_ADI3_REFSYS_SET (TIVA_ADI3_BASE + TIVA_DDI_SET_OFFSET)
@@ -90,7 +93,7 @@
#define TIVA_ADI3_REFSYS_MASK8B (TIVA_ADI3_BASE + TIVA_DDI_MASK8B_OFFSET)
#define TIVA_ADI3_REFSYS_MASK16B (TIVA_ADI3_BASE + TIVA_DDI_MASK16B_OFFSET)
/* ADI3 REFSYS Bitfield Definitions *********************************************************************************/
/* ADI3 REFSYS Bitfield Definitions *****************************************/
/* TIVA_ADI3_REFSYS_SPARE0 */
@@ -182,6 +185,7 @@
# define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_TYPICAL (5 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Typical voltage after trim voltage 1.71V */
# define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MAX (21 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Max voltage 1.96V */
# define ADI3_REFS */YS_DCDCCTL0_VDDR_TRIM_MIN (22 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Min voltage 1.47V */
#define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT (5) /* Bits 5-7: Set charge and re-charge current level */
/* 2's complement encoding */
#define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_MASK (7 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT)
@@ -200,6 +204,7 @@
# define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_TYPICAL (nn << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) /* Typical voltage after trim voltage 1.52V */
# define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_MAX (nn << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) /* Max voltage 1.96V */
# define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_MIN (nn << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) /* Min voltage 1.47V */
#define ADI3_REFSYS_DCDCCTL1_VDDR_OK_HYST (1 << 5) /* Bit 5: Increase the hysteresis for when VDDR is considered ok */
/* 0: Hysteresis = 60mV; 1: Hysteresis = 70mV */
#define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT (6) /* Bits 6-7: Trim GLDO bias current */
@@ -221,6 +226,7 @@
# define ADI3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE (2 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* Pass transistor gate voltage connected to test bus */
# define ADI3_REFSYS_DCDCCTL2_TESTSEL_IB1U (4 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* 1uA bias current connected to test bus */
# define ADI3_REFSYS_DCDCCTL2_TESTSEL_VDDROK (8 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* VDDR_OK connected to test bus */
#define ADI3_REFSYS_DCDCCTL2_BIAS_DIS (1 << 4) /* Bit 4: Disable dummy bias current */
#define ADI3_REFSYS_DCDCCTL2_TEST_VDDR (1 << 5) /* Bit 5: Connect VDDR to ATEST bus */
#define ADI3_REFSYS_DCDCCTL2_TURNON_EA_SW (1 << 6) /* Bit 6: Turns on GLDO error amp switch */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_batmon.h
+11 -10
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_batmon.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a compatible
* BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_BATMON_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_BATMON_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* AON BATMON Register Offsets **************************************************************************************/
/* AON BATMON Register Offsets **********************************************/
#define TIVA_AON_BATMON_CTL_OFFSET 0x0000
#define TIVA_AON_BATMON_MEASCFG_OFFSET 0x0004
@@ -68,7 +69,7 @@
#define TIVA_AON_BATMON_TEMP_OFFSET 0x0030 /* Temperature */
#define TIVA_AON_BATMON_TEMPUPD_OFFSET 0x0034 /* Temperature Update */
/* AON BATMON Register Addresses ************************************************************************************/
/* AON BATMON Register Addresses ********************************************/
#define TIVA_AON_BATMON_CTL (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_CTL_OFFSET)
#define TIVA_AON_BATMON_MEASCFG (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_MEASCFG_OFFSET)
@@ -84,7 +85,7 @@
#define TIVA_AON_BATMON_TEMP (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMP_OFFSET)
#define TIVA_AON_BATMON_TEMPUPD (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPUPD_OFFSET)
/* AON BATMON Register Bitfield Definitions *************************************************************************/
/* AON BATMON Register Bitfield Definitions *********************************/
/* AON_BATMON_CTL */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_ioc.h
+11 -10
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_ioc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_IOC_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_IOC_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* AON IOC Register Offsets *****************************************************************************************/
/* AON IOC Register Offsets *************************************************/
#define TIVA_AON_IOC_IOSTRMIN_OFFSET 0x0000
#define TIVA_AON_IOC_IOSTRMED_OFFSET 0x0004
@@ -61,7 +62,7 @@
#define TIVA_AON_IOC_CLK32KCTL_OFFSET 0x0010 /* SCLK_LF External Output Control */
#define TIVA_AON_IOC_TCKCTL_OFFSET 0x0014 /* TCK IO Pin Control */
/* AON IOC Register Addresses ***************************************************************************************/
/* AON IOC Register Addresses ***********************************************/
#define TIVA_AON_IOC_IOSTRMIN (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMIN_OFFSET)
#define TIVA_AON_IOC_IOSTRMED (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMED_OFFSET)
@@ -69,7 +70,7 @@
#define TIVA_AON_IOC_IOCLATCH (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOCLATCH_OFFSET)
#define TIVA_AON_IOC_CLK32KCTL (TIVA_AON_IOC_BASE + TIVA_AON_IOC_CLK32KCTL_OFFSET)
/* AON IOC Bitfield Definitions *************************************************************************************/
/* AON IOC Bitfield Definitions *********************************************/
/* TIVA_AON_IOC_IOSTRMIN */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_rtc.h
+19 -10
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_rtc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_RTC_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_RTC_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* AON RTC Register Offsets *****************************************************************************************/
/* AON RTC Register Offsets *************************************************/
#define TIVA_AON_RTC_CTL_OFFSET 0x0000 /* Control */
#define TIVA_AON_RTC_EVFLAGS_OFFSET 0x0004 /* Event Flags, RTC Status */
@@ -67,7 +68,7 @@
#define TIVA_AON_RTC_CH1CAPT_OFFSET 0x0028 /* Channel 1 Capture Value */
#define TIVA_AON_RTC_SYNC_OFFSET 0x002c /* AON Synchronization */
/* AON RTC Register Addresses ***************************************************************************************/
/* AON RTC Register Addresses ***********************************************/
#define TIVA_AON_RTC_CTL (TIVA_AON_RTC_BASE + TIVA_AON_RTC_CTL_OFFSET)
#define TIVA_AON_RTC_EVFLAGS (TIVA_AON_RTC_BASE + TIVA_AON_RTC_EVFLAGS_OFFSET)
@@ -82,7 +83,7 @@
#define TIVA_AON_RTC_CH1CAPT (TIVA_AON_RTC_BASE + TIVA_AON_RTC_CH1CAPT_OFFSET)
#define TIVA_AON_RTC_SYNC (TIVA_AON_RTC_BASE + TIVA_AON_RTC_SYNC_OFFSET)
/* AON RTC Bitfield Definitions *************************************************************************************/
/* AON RTC Bitfield Definitions *********************************************/
/* TIVA_AON_RTC_CTL */
@@ -106,6 +107,7 @@
# define AON_RTC_CTL_EV_DELAY_D112 (11 << AON_RTC_CTL_EV_DELAY_SHIFT) /* Delay by 112 clock cycles */
# define AON_RTC_CTL_EV_DELAY_D128 (12 << AON_RTC_CTL_EV_DELAY_SHIFT) /* Delay by 128 clock cycles */
# define AON_RTC_CTL_EV_DELAY_D144 (13 << AON_RTC_CTL_EV_DELAY_SHIFT) /* Delay by 144 clock cycles */
#define AON_RTC_CTL_COMB_EV_MASK_SHIFT (16) /* Bits 16-18: Select how delayed event form combined events */
#define AON_RTC_CTL_COMB_EV_MASK_MASK (7 << AON_RTC_CTL_COMB_EV_MASK_SHIFT)
# define AON_RTC_CTL_COMB_EV_MASK_NONE (0 << AON_RTC_CTL_COMB_EV_MASK_SHIFT) /* No event for combined event */
@@ -120,7 +122,9 @@
#define AON_RTC_EVFLAGS_CH2 (1 << 16) /* Bit 16: Channel 2 event flag */
/* TIVA_AON_RTC_SEC (32-bit value, units of seconds) */
/* TIVA_AON_RTC_SUBSEC (32-bit value, b32 fractional seconds) */
/* TIVA_AON_RTC_SUBSECINC (32-bit value) */
/* TIVA_AON_RTC_CHCTL */
@@ -128,14 +132,19 @@
#define AON_RTC_CHCTL_CH0_EN (1 << 0) /* Bit 0: RTC Channel 0 enable */
#define AON_RTC_CHCTL_CH1_EN (1 << 8) /* Bit 8: RTC Channel 1 enable */
#define AON_RTC_CHCTL_CH1_CAPT_EN (1 << 9) /* Bit 9: Channel 1 mode */
# define AON_RTC_CHCTL_CH1_CAPT_CMP (0) /* Compare mode */
# define AON_RTC_CHCTL_CH1_CAPT_CAPT AON_RTC_CHCTL_CH1_CAPT_EN /* Capture mode */
#define AON_RTC_CHCTL_CH2_EN (1 << 16) /* Bit 16: RTC Channel 2 Enable */
#define AON_RTC_CHCTL_CH2_CONT_EN (1 << 18) /* Bit 18: Enable Channel 2 Continuous Operation */
/* TIVA_AON_RTC_CH0CMP (32-bit value) */
/* TIVA_AON_RTC_CH1CMP (32-bit value) */
/* TIVA_AON_RTC_CH2CMP (32-bit value) */
/* TIVA_AON_RTC_CH2CMPINC (32-bit value) */
/* TIVA_AON_RTC_CH1CAPT */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_sysctl.h
+11 -10
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_sysctl.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,35 +37,35 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_SYSCTL_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_SYSCTL_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* AON SYSCTL Register Offsets **************************************************************************************/
/* AON SYSCTL Register Offsets **********************************************/
#define TIVA_AON_SYSCTL_PWRCTL_OFFSET 0x0000 /* Power Management */
#define TIVA_AON_SYSCTL_RESETCTL_OFFSET 0x0004 /* Reset Management */
#define TIVA_AON_SYSCTL_SLEEPCTL_OFFSET 0x0008 /* Sleep Mode */
/* AON SYSCTL Register Addresses ************************************************************************************/
/* AON SYSCTL Register Addresses ********************************************/
#define TIVA_AON_SYSCTL_PWRCTL (TIVA_AON_SYSCTL_BASE + TIVA_AON_SYSCTL_PWRCTL_OFFSET)
#define TIVA_AON_SYSCTL_RESETCTL (TIVA_AON_SYSCTL_BASE + TIVA_AON_SYSCTL_RESETCTL_OFFSET)
#define TIVA_AON_SYSCTL_SLEEPCTL (TIVA_AON_SYSCTL_BASE + TIVA_AON_SYSCTL_SLEEPCTL_OFFSET)
/* AON SYSCTL Register Bitfield Definitions *************************************************************************/
/* AON SYSCTL Register Bitfield Definitions *********************************/
/* AON_SYSCTL_PWRCTL */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_wuc.h
+11 -10
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_wuc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_WUC_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_WUC_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* AON SYSCTL Register Offsets **************************************************************************************/
/* AON SYSCTL Register Offsets **********************************************/
#define TIVA_AON_WUC_MCUCLK_OFFSET 0x0000 /* MCU Clock Management */
#define TIVA_AON_WUC_AUXCLK_OFFSET 0x0004 /* AUX Clock Management */
@@ -69,7 +70,7 @@
#define TIVA_AON_WUC_JTAGCFG_OFFSET 0x0040 /* JTAG Configuration */
#define TIVA_AON_WUC_JTAGUSERCODE_OFFSET 0x0044 /* JTAG USERCODE */
/* AON SYSCTL Register Addresses ************************************************************************************/
/* AON SYSCTL Register Addresses ********************************************/
#define TIVA_AON_WUC_MCUCLK (TIVA_AON_WUC_BASE + TIVA_AON_WUC_MCUCLK_OFFSET)
#define TIVA_AON_WUC_AUXCLK (TIVA_AON_WUC_BASE + TIVA_AON_WUC_AUXCLK_OFFSET)
@@ -86,7 +87,7 @@
#define TIVA_AON_WUC_JTAGCFG (TIVA_AON_WUC_BASE + TIVA_AON_WUC_JTAGCFG_OFFSET)
#define TIVA_AON_WUC_JTAGUSERCODE (TIVA_AON_WUC_BASE + TIVA_AON_WUC_JTAGUSERCODE_OFFSET)
/* AON SYSCTL Register Bitfield Definitions *************************************************************************/
/* AON SYSCTL Register Bitfield Definitions *********************************/
/* AON_WUC_MCUCLK */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_wuc.h
+11 -10
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_wuc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AUX_WUC_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AUX_WUC_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* AUX WUC Register Offsets *****************************************************************************************/
/* AUX WUC Register Offsets *************************************************/
#define TIVA_AUX_WUC_MODCLKEN0_OFFSET 0x0000 /* Module Clock Enable */
#define TIVA_AUX_WUC_PWROFFREQ_OFFSET 0x0004 /* Power Off Request */
@@ -74,7 +75,7 @@
#define TIVA_AUX_WUC_AUXIOLATCH_OFFSET 0x0054 /* AUX Input Output Latch */
#define TIVA_AUX_WUC_MODCLKEN1_OFFSET 0x005c /* Module Clock Enable 1 */
/* AUX WUC Register Addresses ***************************************************************************************/
/* AUX WUC Register Addresses ***********************************************/
#define TIVA_AUX_WUC_MODCLKEN0 (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_MODCLKEN0_OFFSET)
#define TIVA_AUX_WUC_PWROFFREQ (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_PWROFFREQ_OFFSET)
@@ -96,7 +97,7 @@
#define TIVA_AUX_WUC_AUXIOLATCH (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_AUXIOLATCH_OFFSET)
#define TIVA_AUX_WUC_MODCLKEN1 (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_MODCLKEN1_OFFSET)
/* AUX WUC Register Bitfield Definitions ****************************************************************************/
/* AUX WUC Register Bitfield Definitions ************************************/
/* AUX_WUC_MODCLKEN0 */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_ccfg.h
+9 -9
View File
@@ -1,4 +1,4 @@
/************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_ccfg.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
@@ -37,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_CCFG_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_CCFG_H
/************************************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************************************/
****************************************************************************/
/* CCFG Register Offsets ************************************************************************************/
/* CCFG Register Offsets ****************************************************/
#define TIVA_CCFG_EXT_LF_CLK_OFFSET 0x0fa8 /* Extern LF clock configuration */
#define TIVA_CCFG_MODE_CONF_1_OFFSET 0x0fac /* Mode Configuration 1 */
@@ -78,7 +78,7 @@
#define TIVA_CCFG_CCFG_PROT_95_64_OFFSET 0x0ff8 /* Protect Sectors 64-95 */
#define TIVA_CCFG_CCFG_PROT_127_96_OFFSET 0x0ffc /* Protect Sectors 96-127 */
/* CCFG Register Addresses **********************************************************************************/
/* CCFG Register Addresses **************************************************/
#define TIVA_CCFG_EXT_LF_CLK (TIVA_CCFG_BASE + TIVA_CCFG_EXT_LF_CLK_OFFSET)
#define TIVA_CCFG_MODE_CONF_1 (TIVA_CCFG_BASE + TIVA_CCFG_MODE_CONF_1_OFFSET)
@@ -103,7 +103,7 @@
#define TIVA_CCFG_CCFG_PROT_95_64 (TIVA_CCFG_BASE + TIVA_CCFG_CCFG_PROT_95_64_OFFSET)
#define TIVA_CCFG_CCFG_PROT_127_96 (TIVA_CCFG_BASE + TIVA_CCFG_CCFG_PROT_127_96_OFFSET)
/* CCFG Bifield Definitions *********************************************************************************/
/* CCFG Bifield Definitions *************************************************/
/* TIVA_CCFG_EXT_LF_CLK */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h
+26 -11
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,24 +37,24 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_DDI0_OSC_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_DDI0_OSC_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
#include "hardware/tiva_ddi.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* DDI0 OSC Register Offsets ****************************************************************************************/
/* DDI0 OSC Register Offsets ************************************************/
#define TIVA_DDI0_OSC_CTL0_OFFSET 0x0000 /* Control 0 */
#define TIVA_DDI0_OSC_CTL1_OFFSET 0x0004 /* Control 1 */
@@ -72,7 +73,8 @@
#define TIVA_DDI0_OSC_STAT1_OFFSET 0x0038 /* Status 1 */
#define TIVA_DDI0_OSC_STAT2_OFFSET 0x003c /* Status 2 */
/* DDI0 OSC Register Addresses **************************************************************************************/
/* DDI0 OSC Register Addresses **********************************************/
/* Direct access */
#define TIVA_DDI0_OSC_CTL0 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_CTL0_OFFSET)
@@ -92,7 +94,9 @@
#define TIVA_DDI0_OSC_STAT1 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_STAT1_OFFSET)
#define TIVA_DDI0_OSC_STAT2 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_STAT2_OFFSET)
/* Offsets may also be used in conjunction with access as described in cc13x0_ddi.h */
/* Offsets may also be used in conjunction with access as described in
* cc13x0_ddi.h
*/
#define TIVA_DDI0_OSC_DIR (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_DIR_OFFSET)
#define TIVA_DDI0_OSC_SET (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET)
@@ -101,17 +105,20 @@
#define TIVA_DDI0_OSC_MASK8B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK8B_OFFSET)
#define TIVA_DDI0_OSC_MASK16B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK16B_OFFSET)
/* DDI0 OSC Bitfield Definitions ************************************************************************************/
/* DDI0 OSC Bitfield Definitions ********************************************/
/* DDI0_OSC_CTL0 */
#define DDI0_OSC_CTL0_SCLK_HF_SRC_SEL (1 << 0) /* Bit 0: Source select for sclk_hf */
# define DDI0_OSC_CTL0_SCLK_HF_SRC_RCOSC (0) /* High frequency RCOSC clock */
# define DDI0_OSC_CTL0_SCLK_HF_SRC_XOSC DDI0_OSC_CTL0_SCLK_HF_SRC_SEL /* High frequency XOSC clock */
#define DDI0_OSC_CTL0_SCLK_MF_SRC_SEL (1 << 1) /* Bit 1 */
# define DDI0_OSC_CTL0_SCLK_MF_SRC_SEL_RCOSCHFDMF 0
# define DDI0_OSC_CTL0_SCLK_MF_SRC_SEL_XCOSCHFDMF DDI0_OSC_CTL0_SCLK_MF_SRC_SEL /* Medium frequency clock derived
* from high frequency XOSC */
#define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT (2) /* Bits 2-3: Source select for sclk_lf */
#define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_MASK (3 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT)
# define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF (1 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency clock derived
@@ -120,26 +127,31 @@
* from High Frequency RCOSC */
# define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF (2 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency RCOSC */
# define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF (3 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency XOSC */
#define DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT (5) /* Bits 5-6: Source select for aclk_ref */
#define DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_MASK (3 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT)
# define DDI0_OSC_CTL0_ACLK_REF_SRC_RCOSCHF (0 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* RCOSC_HF derived (31.25kHz) */
# define DDI0_OSC_CTL0_ACLK_REF_SRC_XOSCHF (1 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* XOSC_HF derived (31.25kHz) */
# define DDI0_OSC_CTL0_ACLK_REF_SRC_RCOSCLF (2 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* RCOSC_LF (32kHz) */
# define DDI0_OSC_CTL0_ACLK_REF_SRC_XOSCLF (3 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* XOSC_LF (32.768kHz) */
#define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT (7) /* Bits 7-8: ource select for aclk_tdc */
#define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_MASK (3 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT)
# define DDI0_OSC_CTL0_ACLK_TDC_SRC_RCOSCHF48 (0 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* RCOSC_HF (48MHz) */
# define DDI0_OSC_CTL0_ACLK_TDC_SRC_RCOSCHF24 (1 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* RCOSC_HF (24MHz) */
# define DDI0_OSC_CTL0_ACLK_TDC_SRC_XOSCHF24 (2 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* XOSC_HF (24MHz) */
#define DDI0_OSC_CTL0_CLK_LOSS_EN (1 << 9) /* Bit 9: Enable SCLK_HF, SCLK_MF and SCLK_LF clock
* loss detection and indicators to the system
* controller */
#define DDI0_OSC_CTL0_XOSC_LF_DIG_BYPASS (1 << 10) /* Bit 10: Bypass XOSC_LF and use the digital
* input clock from AON for the xosc_lf */
# define DDI0_OSC_CTL0_XOSC_LF_DIG_32KHZ (0) /* Use 32kHz XOSC as xosc_lf
* clock source */
# define DDI0_OSC_CTL0_XOSC_LF_DIG_DIGINPUT DDI0_OSC_CTL0_XOSC_LF_DIG_BYPASS /* Use digital input (from AON)
* as xosc_lf clock source */
#define DDI0_OSC_CTL0_XOSC_HF_POWER_MODE (1 << 11) /* Bit 11 */
#define DDI0_OSC_CTL0_RCOSC_LF_TRIMMED (1 << 12) /* Bit 12 */
#define DDI0_OSC_CTL0_HPOSC_MODE_EN (1 << 14) /* Bit 14 */
@@ -326,8 +338,11 @@
#define DDI0_OSC_STAT0_RCOSC_LF_EN (1 << 21) /* Bit 21: RCOSC_LF enable */
#define DDI0_OSC_STAT0_RCOSC_HF_EN (1 << 22) /* Bit 22: RSOSC_HF enable */
#define DDI0_OSC_STAT0_SCLK_HF_SRC (1 << 28) /* Bit 28: Indicates source for sclk_hf */
# define DDI0_OSC_STAT0_SCLK_HF_SRC_RCOSC (0) /* High frequency RCOSC clock */
# define DDI0_OSC_STAT0_SCLK_HF_SRC_XOSC DDI0_OSC_STAT0_SCLK_HF_SRC /* High frequency XOSC */
#define DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT (29) /* Bits 29-30: Indicates source for the sclk_lf */
#define DDI0_OSC_STAT0_SCLK_LF_SRC_MASK (3 << DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT)
# define DDI0_OSC_STAT0_SCLK_LF_SRC(n) ((uint32_t)(n) << DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT)
arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h
+49 -22
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_FCFG1_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_FCFG1_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* FCFG1 Register Offsets *******************************************************************************************/
/* FCFG1 Register Offsets ***************************************************/
#define TIVA_FCFG1_MISC_CONF_1_OFFSET 0x00a0 /* Misc configurations */
#define TIVA_FCFG1_MISC_CONF_2_OFFSET 0x00a4
@@ -137,7 +138,7 @@
#define TIVA_FCFG1_PWD_CURR_110C_OFFSET 0x03b4 /* Power Down Current Control 110C */
#define TIVA_FCFG1_PWD_CURR_125C_OFFSET 0x03b8 /* Power Down Current Control 125C */
/* FCFG1 Register Register Addresses ********************************************************************************/
/* FCFG1 Register Register Addresses ****************************************/
#define TIVA_FCFG1_MISC_CONF_1 (TIVA_FCFG1_BASE + TIVA_FCFG1_MISC_CONF_1_OFFSET)
#define TIVA_FCFG1_MISC_CONF_2 (TIVA_FCFG1_BASE + TIVA_FCFG1_MISC_CONF_2_OFFSET)
@@ -222,7 +223,7 @@
#define TIVA_FCFG1_PWD_CURR_110C (TIVA_FCFG1_BASE + TIVA_FCFG1_PWD_CURR_110C_OFFSET)
#define TIVA_FCFG1_PWD_CURR_125C (TIVA_FCFG1_BASE + TIVA_FCFG1_PWD_CURR_125C_OFFSET)
/* FCFG1 Bitfield Definitions ***************************************************************************************/
/* FCFG1 Bitfield Definitions ***********************************************/
/* TIVA_FCFG1_MISC_CONF_1 */
@@ -512,10 +513,21 @@
#define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_MASK (15 << FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_SHIFT)
# define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM(n) ((uint32_t)(n) << FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_SHIFT)
/* TIVA_FCFG1_SHDW_DIE_ID_0 (32-bit value, Shadow of the DIE_ID_0 register in eFuse row number 3) */
/* TIVA_FCFG1_SHDW_DIE_ID_1 (32-bit value, Shadow of the DIE_ID_1 register in eFuse row number 4) */
/* TIVA_FCFG1_SHDW_DIE_ID_2 (32-bit value, Shadow of the DIE_ID_2 register in eFuse row number 5) */
/* TIVA_FCFG1_SHDW_DIE_ID_3 (32-bit value, Shadow of the DIE_ID_3 register in eFuse row number 6) */
/* TIVA_FCFG1_SHDW_DIE_ID_0 (32-bit value,
* Shadow of the DIE_ID_0 register in eFuse row number 3)
*/
/* TIVA_FCFG1_SHDW_DIE_ID_1 (32-bit value,
* Shadow of the DIE_ID_1 register in eFuse row number 4)
*/
/* TIVA_FCFG1_SHDW_DIE_ID_2 (32-bit value,
* Shadow of the DIE_ID_2 register in eFuse row number 5)
*/
/* TIVA_FCFG1_SHDW_DIE_ID_3 (32-bit value,
* Shadow of the DIE_ID_3 register in eFuse row number 6)
*/
/* TIVA_FCFG1_SHDW_OSC_BIAS_LDO_TRIM */
@@ -716,6 +728,7 @@
# define FCFG1_USER_ID_PROTOCOL_RF4CE (2 << FCFG1_USER_ID_PROTOCOL_SHIFT) /* RF4CE */
# define FCFG1_USER_ID_PROTOCOL_802154 (4 << FCFG1_USER_ID_PROTOCOL_SHIFT) /* Zigbee/6lowpan */
# define FCFG1_USER_ID_PROTOCOL_PROP (8 << FCFG1_USER_ID_PROTOCOL_SHIFT) /* Proprietary */
#define FCFG1_USER_ID_PKG_SHIFT (16) /* Bits 16-18: Package type */
#define FCFG1_USER_ID_PKG_MASK (7 << FCFG1_USER_ID_PKG_SHIFT)
# define FCFG1_USER_ID_PKG_RHG (0 << FCFG1_USER_ID_PKG_SHIFT) /* 4x4mm QFN (RHB) package */
@@ -723,6 +736,7 @@
# define FCFG1_USER_ID_PKG_RGZ (2 << FCFG1_USER_ID_PKG_SHIFT) /* 7x7mm QFN (RGZ) package */
# define FCFG1_USER_ID_PKG_WSP (3 << FCFG1_USER_ID_PKG_SHIFT) /* Wafer sale package (naked die) */
# define FCFG1_USER_ID_PKG_QFNWF (5 << FCFG1_USER_ID_PKG_SHIFT) /* 7x7mm QFN package with Wettable Flanks */
#define FCFG1_USER_ID_SEQUENCE_SHIFT (19) /* Bits 19-22: Sequence */
#define FCFG1_USER_ID_SEQUENCE_MASK (15 << FCFG1_USER_ID_SEQUENCE_SHIFT)
# define FCFG1_USER_ID_SEQUENCE(n) ((uint32_t)(n) << FCFG1_USER_ID_SEQUENCE_SHIFT)
@@ -812,10 +826,21 @@
#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_MASK (15 << FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_SHIFT)
# define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD(n) ((uint32_t)(n) << FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_SHIFT)
/* TIVA_FCFG1_MAC_BLE_0 (32-bit value, The first 32-bits of the 64-bit MAC BLE address) */
/* TIVA_FCFG1_MAC_BLE_1 (32-bit value, The last 32-bits of the 64-bit MAC BLE address) */
/* TIVA_FCFG1_MAC_15_4_0 (32-bit value, The first 32-bits of the 64-bit MAC 15.4 address) */
/* TIVA_FCFG1_MAC_15_4_1 (32-bit value, The last 32-bits of the 64-bit MAC 15.4 address) */
/* TIVA_FCFG1_MAC_BLE_0
* (32-bit value, The first 32-bits of the 64-bit MAC BLE address)
*/
/* TIVA_FCFG1_MAC_BLE_1
* (32-bit value, The last 32-bits of the 64-bit MAC BLE address)
*/
/* TIVA_FCFG1_MAC_15_4_0
* (32-bit value, The first 32-bits of the 64-bit MAC 15.4 address)
*/
/* TIVA_FCFG1_MAC_15_4_1
* (32-bit value, The last 32-bits of the 64-bit MAC 15.4 address)
*/
/* TIVA_FCFG1_FLASH_OTP_DATA4 */
@@ -858,8 +883,8 @@
/* TIVA_FCFG1_MISC_TRIM */
#define FCFG1_MISC_TRIM_TEMPVSLOPE_SHIFT (0) /* Bits 0-7: TEMP slope with battery voltage, in
degrees C */
#define FCFG1_MISC_TRIM_TEMPVSLOPE_SHIFT (0) /* Bits 0-7: TEMP slope with battery voltage,
* degrees in C */
#define FCFG1_MISC_TRIM_TEMPVSLOPE_MASK (0xff << FCFG1_MISC_TRIM_TEMPVSLOPE_SHIFT)
# define FCFG1_MISC_TRIM_TEMPVSLOPE(n) ((uint32_t)(n) << FCFG1_MISC_TRIM_TEMPVSLOPE_SHIFT)
@@ -899,7 +924,9 @@ degrees C */
#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_MASK (15 << FCFG1_ICEPICK_DEVICE_ID_PG_REV_SHIFT)
# define FCFG1_ICEPICK_DEVICE_ID_PG_REV(n) ((uint32_t)(n) << FCFG1_ICEPICK_DEVICE_ID_PG_REV_SHIFT)
/* TIVA_FCFG1_FCFG1_REVISION (32-bit value, The revision number of the FCFG1 layout) */
/* TIVA_FCFG1_FCFG1_REVISION
* (32-bit value, The revision number of the FCFG1 layout)
*/
/* TIVA_FCFG1_MISC_OTP_DATA */
@@ -1100,7 +1127,7 @@ degrees C */
#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N (1 << 17) /* Bit 17 */
#define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_SHIFT (18) /* Bits 18-21 */
#define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_MASK (15 << FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_SHIFT)
# define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM(n) ((uint32_t)(n) << FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_SHIFT)
# define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM(n) ((uint32_t)(n) << FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_SHIFT)
/* TIVA_FCFG1_VOLT_TRIM */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_flash.h
+24 -10
View File
@@ -1,10 +1,11 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_flash.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_FLASH_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_FLASH_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
****************************************************************************/
/* FLASH Register Offsets ***************************************************************************/
/* FLASH Register Offsets ***************************************************/
#define TIVA_FLASH_STAT_OFFSET 0x001c /* FMC and Efuse Status */
#define TIVA_FLASH_CFG_OFFSET 0x0024
@@ -178,7 +179,7 @@
#define TIVA_FLASH_FCFG_B7_START_OFFSET 0x242c
#define TIVA_FLASH_FCFG_B0_SSIZE0_OFFSET 0x2430
/* FLASH Register Addresses *************************************************************************/
/* FLASH Register Addresses *************************************************/
#define TIVA_FLASH_STAT (TIVA_FLASH_BASE + TIVA_FLASH_STAT_OFFSET)
#define TIVA_FLASH_CFG (TIVA_FLASH_BASE + TIVA_FLASH_CFG_OFFSET)
@@ -304,7 +305,7 @@
#define TIVA_FLASH_FCFG_B7_START (TIVA_FLASH_BASE + TIVA_FLASH_FCFG_B7_START_OFFSET)
#define TIVA_FLASH_FCFG_B0_SSIZE0 (TIVA_FLASH_BASE + TIVA_FLASH_FCFG_B0_SSIZE0_OFFSET)
/* FLASH Bitfield Definitions ***********************************************************************/
/* FLASH Bitfield Definitions ***********************************************/
/* TIVA_FLASH_STAT */
@@ -494,6 +495,7 @@
#define FLASH_TWOBIT_FROMN_MASK (0x7fffffff << FLASH_TWOBIT_FROMN_SHIFT)
/* TIVA_FLASH_SELFTESTCYC (32-bit value) */
/* TIVA_FLASH_SELFTESTSIGN (32-bit value) */
/* TIVA_FLASH_FRDCTL */
@@ -726,12 +728,19 @@
#define FLASH_FTCTL_WDATA_BLK_CLR (1 << 16) /* Bit 16 */
/* TIVA_FLASH_FWPWRITE0 (32-bit value) */
/* TIVA_FLASH_FWPWRITE1 (32-bit value) */
/* TIVA_FLASH_FWPWRITE2 (32-bit value) */
/* TIVA_FLASH_FWPWRITE3 (32-bit value) */
/* TIVA_FLASH_FWPWRITE4 (32-bit value) */
/* TIVA_FLASH_FWPWRITE5 (32-bit value) */
/* TIVA_FLASH_FWPWRITE6 (32-bit value) */
/* TIVA_FLASH_FWPWRITE7 (32-bit value) */
/* TIVA_FLASH_FWPWRITE_ECC */
@@ -991,10 +1000,15 @@
#define FLASH_FSM_EXECUTE_SUSPEND_NOW_MASK (15 << FLASH_FSM_EXECUTE_SUSPEND_NOW_SHIFT)
/* TIVA_FLASH_FSM_SECTOR1 (32-bit value) */
/* TIVA_FLASH_FSM_SECTOR2 (32-bit value) */
/* TIVA_FLASH_FSM_BSLE0 (32-bit value) */
/* TIVA_FLASH_FSM_BSLE1 (32-bit value) */
/* TIVA_FLASH_FSM_BSLP0 (32-bit value) */
/* TIVA_FLASH_FSM_BSLP1 (32-bit value) */
/* TIVA_FLASH_FCFG_BANK */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_gpio.h
+17 -16
View File
@@ -1,10 +1,11 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_gpio.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a compatible
* BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_GPIO_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_GPIO_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* GPIO Register Offsets ************************************************************/
/* GPIO Register Offsets ****************************************************/
#define TIVA_GPIO_DOUT_PIN_OFFSET(n) ((n) & ~3)
# define TIVA_GPIO_DOUT_PIN3_0_OFFSET 0x0000 /* Data Out 0 to 3 */
@@ -71,7 +72,7 @@
#define TIVA_GPIO_DOE_OFFSET 0x00d0 /* Data Output Enable for DIO 0 to 31 */
#define TIVA_GPIO_EVFLAGS_OFFSET 0x00e0 /* Event Register for DIO 0 to 31 */
/* GPIO Register Addresses **********************************************************/
/* GPIO Register Addresses **************************************************/
#define TIVA_GPIO_DOUT_PIN_BASE(n) (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN_OFFSET(n))
# define TIVA_GPIO_DOUT_PIN3_0 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN3_0_OFFSET)
@@ -90,7 +91,7 @@
#define TIVA_GPIO_DOE (TIVA_GPIO_BASE + TIVA_GPIO_DOE_OFFSET)
#define TIVA_GPIO_EVFLAGS (TIVA_GPIO_BASE + TIVA_GPIO_EVFLAGS_OFFSET)
/* GPIO Register Bitfield Definitions ***********************************************/
/* GPIO Register Bitfield Definitions ***************************************/
/* Data Out n to n + 3 */
@@ -125,16 +126,16 @@
#define GPIO_EVFLAGS(n) (1 << (n))
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_GPIO_H */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_i2c.h
+9 -8
View File
@@ -1,10 +1,11 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_i2c.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,16 +37,16 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_I2C_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_I2C_H
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* I2C register offsets *********************************************************************/
/* I2C register offsets *****************************************************/
#define TIVA_I2C_SOAR_OFFSET 0x0000 /* Slave Own Address */
#define TIVA_I2C_SSTAT_OFFSET 0x0004 /* Slave Status */
@@ -67,7 +68,7 @@
#define TIVA_I2C_MICR_OFFSET 0x081c /* Master Interrupt Clear */
#define TIVA_I2C_MCR_OFFSET 0x0820 /* Master Configuration */
/* I2C register addresses *******************************************************************/
/* I2C register addresses ***************************************************/
#define TIVA_I2C0_SOAR (TIVA_I2C0_BASE + TIVA_I2C_SOAR_OFFSET)
#define TIVA_I2C0_SSTAT (TIVA_I2C0_BASE + TIVA_I2C_SSTAT_OFFSET)
@@ -89,7 +90,7 @@
#define TIVA_I2C0_MICR (TIVA_I2C0_BASE + TIVA_I2C_MICR_OFFSET)
#define TIVA_I2C0_MCR (TIVA_I2C0_BASE + TIVA_I2C_MCR_OFFSET)
/* I2C bitfield definitions *****************************************************************/
/* I2C bitfield definitions *************************************************/
/* Slave Own Address */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_ioc.h
+25 -17
View File
@@ -1,10 +1,11 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_ioc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a compatible
* BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,25 +37,25 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2IOC_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2IOC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <arch/chip/chip.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#define TIVA_NDIO 32 /* DIO0-31 */
/* IOC register offsets ************************************************************/
/* IOC register offsets *****************************************************/
#define TIVA_IOC_IOCFG_OFFSET(n) ((n) << 2)
# define TIVA_IOC_IOCFG0_OFFSET 0x0000 /* Configuration of DIO0 */
@@ -90,7 +91,7 @@
# define TIVA_IOC_IOCFG30_OFFSET 0x0078 /* Configuration of DIO30 */
# define TIVA_IOC_IOCFG31_OFFSET 0x007c /* Configuration of DIO31 */
/* IOC register addresses **********************************************************/
/* IOC register addresses ***************************************************/
#define TIVA_IOC_IOCFG(n) (TIVA_IOC_BASE + TIVA_IOC_IOCFG_OFFSET(n))
# define TIVA_IOC_IOCFG0 (TIVA_IOC_BASE + TIVA_IOC_IOCFG0_OFFSET)
@@ -126,36 +127,41 @@
# define TIVA_IOC_IOCFG30 (TIVA_IOC_BASE + TIVA_IOC_IOCFG30_OFFSET)
# define TIVA_IOC_IOCFG31 (TIVA_IOC_BASE + TIVA_IOC_IOCFG31_OFFSET)
/* IOC register bit settings *******************************************************/
/* IOC register bit settings ************************************************/
/* Common bitfield for all DIO configuration registers */
#define IOC_IOCFG_PORTID_SHIFT (0) /* Bits 0-5: Selects DIO usage */
#define IOC_IOCFG_PORTID_MASK (0x3f << IOC_IOCFG_PORTID_SHIFT)
# define IOC_IOCFG_PORTID(n) ((uint32_t)(n) << IOC_IOCFG_PORTID_SHIFT) /* See PORT ID definitions */
#define IOC_IOCFG_IOSTR_SHIFT (8) /* Bits 8-9: I/O drive strength */
#define IOC_IOCFG_IOSTR_MASK (3 << IOC_IOCFG_IOSTR_SHIFT)
# define IOC_IOCFG_IOSTR_AUTO (0 << IOC_IOCFG_IOSTR_SHIFT) /* Automatic drive strength */
# define IOC_IOCFG_IOSTR_MIN (1 << IOC_IOCFG_IOSTR_SHIFT) /* Minimum drive strength */
# define IOC_IOCFG_IOSTR_MED (2 << IOC_IOCFG_IOSTR_SHIFT) /* Medium drive strength */
# define IOC_IOCFG_IOSTR_MAX (3 << IOC_IOCFG_IOSTR_SHIFT) /* Maximum drive strength */
#define IOC_IOCFG_IOCURR_SHIFT (10) /* Bits 10-11: I/O current mode */
#define IOC_IOCFG_IOCURR_MASK (3 << IOC_IOCFG_IOCURR_SHIFT)
# define IOC_IOCFG_IOCURR_2MA (0 << IOC_IOCFG_IOCURR_SHIFT) /* Extended-Current (EC) mode */
# define IOC_IOCFG_IOCURR_4MA (1 << IOC_IOCFG_IOCURR_SHIFT) /* High-Current (HC) mode */
# define IOC_IOCFG_IOCURR_8MA (2 << IOC_IOCFG_IOCURR_SHIFT) /* Low-Current (LC) mode */
#define IOC_IOCFG_SLEW_RED (1 << 12) /* Bit 12: Reduces output slew rate */
#define IOC_IOCFG_PULLCTL_SHIFT (13) /* Bits 13-14: Pull Control */
#define IOC_IOCFG_PULLCTL_MASK (3 << IOC_IOCFG_PULLCTL_SHIFT)
# define IOC_IOCFG_PULLCTL_DIS (3 << IOC_IOCFG_PULLCTL_SHIFT) /* No pull */
# define IOC_IOCFG_PULLCTL_DWN (1 << IOC_IOCFG_PULLCTL_SHIFT) /* Pull down */
# define IOC_IOCFG_PULLCTL_UP (2 << IOC_IOCFG_PULLCTL_SHIFT) /* Pull up */
#define IOC_IOCFG_EDGEDET_SHIFT (16) /* Bits 16-17: Enable edge events generation */
#define IOC_IOCFG_EDGEDET_MASK (3 << IOC_IOCFG_EDGEDET_SHIFT)
# define IOC_IOCFG_EDGEDET_NONE (0 << IOC_IOCFG_EDGEDET_SHIFT) /* No edge detection */
# define IOC_IOCFG_EDGEDET_NEG (1 << IOC_IOCFG_EDGEDET_SHIFT) /* Negative edge detection */
# define IOC_IOCFG_EDGEDET_POS (2 << IOC_IOCFG_EDGEDET_SHIFT) /* Positive edge detection */
# define IOC_IOCFG_EDGEDET_BOTH (3 << IOC_IOCFG_EDGEDET_SHIFT) /* Both edge detection */
#define IOC_IOCFG_EDGE_IRQEN (1 << 18) /* Bit 18: Enable interrupt generation */
#define IOC_IOCFG_IOMODE_SHIFT (24) /* Bits 24-26: I/O Mode */
#define IOC_IOCFG_IOMODE_MASK (7 << IOC_IOCFG_IOMODE_SHIFT)
@@ -165,12 +171,14 @@
# define IOC_IOCFG_IOMODE_OPENDRINV (5 << IOC_IOCFG_IOMODE_SHIFT) /* Open drain, inverted I/O */
# define IOC_IOCFG_IOMODE_OPENSRC (6 << IOC_IOCFG_IOMODE_SHIFT) /* Open source */
# define IOC_IOCFG_IOMODE_OPENSRCINV (7 << IOC_IOCFG_IOMODE_SHIFT) /* Open source, inverted I/O */
#define IOC_IOCFG_WUCFG_SHIFT (27) /* Bits 27-28: Wakeup Configuration */
#define IOC_IOCFG_WUCFG_MASK (3 << IOC_IOCFG_WUCFG_SHIFT)
# define IOC_IOCFG_WUCFG_NONE (0 << IOC_IOCFG_WUCFG_SHIFT) /* 0, 1: Wakeup disabled */
# define IOC_IOCFG_WUCFG_ENABLE (2 << IOC_IOCFG_WUCFG_SHIFT) /* 2, 3: Wakeup enabled */
# define IOC_IOCFG_WUCFG_WAKEUPL (2 << IOC_IOCFG_WUCFG_SHIFT) /* 2: Wakeup on transition low */
# define IOC_IOCFG_WUCFG_WEKUPH (3 << IOC_IOCFG_WUCFG_SHIFT) /* 3: Wakeup on transition high */
#define IOC_IOCFG_IE (1 << 29) /* Bit 29: Input enable */
#define IOC_IOCFG_HYSTEN (1 << 30) /* Bit 30: Input hysteresis enable */
@@ -219,16 +227,16 @@
#define IOC_IOCFG_PORTID_RFC_SMI_CLOUT 0x37
#define IOC_IOCFG_PORTID_RFC_SMI_CLIN 0x38
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2IOC_H */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_prcm.h
+18 -16
View File
@@ -1,10 +1,11 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_prcm.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_PRCM_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_PRCM_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
****************************************************************************/
/* PRCM Register Offsets ****************************************************************************/
/* PRCM Register Offsets ****************************************************/
#define TIVA_PRCM_INFRCLKDIVR_OFFSET 0x0000 /* Infrastructure Clock Division Factor For Run Mode */
#define TIVA_PRCM_INFRCLKDIVS_OFFSET 0x0004 /* Infrastructure Clock Division Factor For Sleep Mode */
@@ -114,7 +115,7 @@
#define TIVA_PRCM_PWRPROFSTAT_OFFSET 0x01e0 /* Power Profiler Register */
#define TIVA_PRCM_RAMRETEN_OFFSET 0x0224 /* Memory Retention Control */
/* PRCM Register Addresses *************************************************************************/
/* PRCM Register Addresses **************************************************/
#define TIVA_PRCM_INFRCLKDIVR (TIVA_PRCM_BASE + TIVA_PRCM_INFRCLKDIVR_OFFSET)
#define TIVA_PRCM_INFRCLKDIVS (TIVA_PRCM_BASE + TIVA_PRCM_INFRCLKDIVS_OFFSET)
@@ -176,7 +177,7 @@
#define TIVA_PRCM_PWRPROFSTAT (TIVA_PRCM_BASE + TIVA_PRCM_PWRPROFSTAT_OFFSET)
#define TIVA_PRCM_RAMRETEN (TIVA_PRCM_BASE + TIVA_PRCM_RAMRETEN_OFFSET)
/* PRCM Register Bitfield Definitions **************************************************************/
/* PRCM Register Bitfield Definitions ***************************************/
/* Infrastructure Clock Division Factor For Run Mode */
@@ -322,6 +323,7 @@
# define PRCM_I2SCLKCTL_WCLKPHASE_SINGLE (0 << PRCM_I2SCLKCTL_WCLKPHASE_SHIFT) /* Single phase */
# define PRCM_I2SCLKCTL_WCLKPHASE_DUAL (1 << PRCM_I2SCLKCTL_WCLKPHASE_SHIFT) /* Dual phase */
# define PRCM_I2SCLKCTL_WCLKPHASE_USER (2 << PRCM_I2SCLKCTL_WCLKPHASE_SHIFT) /* User Defined */
#define PRCM_I2SCLKCTL_POSEDGE (1 << 3) /* Bit 3: Sample/clock on positive edge */
# define PRCM_I2SCLKCTL_NEGEDGE (0) /* Sample/clock on negative edge */
@@ -475,16 +477,16 @@
# define PRCM_RAMRETEN_VIMS_CRAM (2 << PRCM_RAMRETEN_VIMS_SHIFT)
#define PRCM_RAMRETEN_RFC (1 << 2) /* Bit 2: RFC SRAM retention enabled */
/****************************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
/****************************************************************************
* Public Function Prototypes
****************************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_PRCM_H */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_timer.h
+17 -16
View File
@@ -1,10 +1,11 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_timer.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a compatible
* BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,37 +37,37 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_TIMER_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_TIMER_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* TIMER Register Offsets ***********************************************************/
/* TIMER Register Offsets ***************************************************/
/* TIMER Register Addresses *********************************************************/
/* TIMER Register Addresses *************************************************/
/* TIMER Register Bitfield Definitions **********************************************/
/* TIMER Register Bitfield Definitions **************************************/
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_TIMER_H */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_uart.h
+15 -14
View File
@@ -1,10 +1,11 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_uart.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a compatible
* BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_UART_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_UART_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <arch/chip/chip.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* UART register offsets ************************************************************/
/* UART register offsets ****************************************************/
#define TIVA_UART_DR_OFFSET 0x0000 /* UART Data */
#define TIVA_UART_RSR_OFFSET 0x0004 /* UART Receive Status */
@@ -82,7 +83,7 @@
#define TIVA_UART_PCELLID2_OFFSET 0x0ff8 /* UART PrimeCell Identification 2 */
#define TIVA_UART_PCELLID3_OFFSET 0x0ffc /* UART PrimeCell Identification 3 */
/* UART register addresses **********************************************************/
/* UART register addresses **************************************************/
#define TIVA_UART_BASE(n) (TIVA_UART0_BASE + (n)*0x01000)
@@ -118,7 +119,7 @@
# define TIVA_UART0_DMACTL (TIVA_UART0_BASE + TIVA_UART_DMACTL_OFFSET)
#endif
/* UART register bit settings *******************************************************/
/* UART register bit settings ***********************************************/
/* UART Data (DR) */
@@ -255,12 +256,12 @@
#define UART_DMACTL_TXDMAE (1 << 1) /* Bit 1: Transmit DMA Enable */
#define UART_DMACTL_DMAERR (1 << 2) /* Bit 2: DMA on Error */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_UART_H */
arch/arm/src/tiva/hardware/cc13x0/cc13x0_vims.h
+13 -10
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_vims.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,33 +37,33 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_VIMS_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_VIMS_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* VIMS Register Offsets ********************************************************************************************/
/* VIMS Register Offsets ****************************************************/
#define TIVA_VIMS_STAT_OFFSET 0x0000 /* Status */
#define TIVA_VIMS_CTL_OFFSET 0x0004 /* Control */
/* VIMS Register Addresses ******************************************************************************************/
/* VIMS Register Addresses **************************************************/
#define TIVA_VIMS_STAT (TIVA_VIMS_BASE + TIVA_VIMS_STAT_OFFSET)
#define TIVA_VIMS_CTL (TIVA_VIMS_BASE + TIVA_VIMS_CTL_OFFSET)
/* VIMS Bitfield Definitions ****************************************************************************************/
/* VIMS Bitfield Definitions ************************************************/
/* VIMS_STAT */
@@ -71,6 +72,7 @@
# define VIMS_STAT_MODE_GPRAM (0 << VIMS_STAT_MODE_SHIFT) /* VIMS GPRAM mode */
# define VIMS_STAT_MODE_CACHE (1 << VIMS_STAT_MODE_SHIFT) /* VIMS Cache mode */
# define VIMS_STAT_MODE_OFF (3 << VIMS_STAT_MODE_SHIFT) /* VIMS Off mode */
#define VIMS_STAT_INV (1 << 2) /* Bit 2: Invalidation of caching memory in-progress */
#define VIMS_STAT_MODE_CHANGING (1 << 3) /* Bit 3: VIMS mode change status */
#define VIMS_STAT_SYSBUS_LB_DIS (1 << 4) /* Bit 4: Sysbus flash line buffer control */
@@ -83,6 +85,7 @@
# define VIMS_CTL_MODE_GPRAM (0 << VIMS_CTL_MODE_SHIFT) /* VIMS GPRAM mode */
# define VIMS_CTL_MODE_CACHE (1 << VIMS_CTL_MODE_SHIFT) /* VIMS Cache mode */
# define VIMS_CTL_MODE_OFF (3 << VIMS_CTL_MODE_SHIFT) /* VIMS Off mode */
#define VIMS_CTL_PREF_EN (1 << 2) /* Bit 2: Tag prefetch control */
#define VIMS_CTL_ARB_CFG (1 << 3) /* Bit 3: Icode/Dcode and sysbus arbitation scheme */
# define VIMS_CTL_ARB_STATIC (0)
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h
+14 -11
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,24 +37,24 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_ADI2_REFSYS_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_ADI2_REFSYS_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
#include "hardware/tiva_ddi.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* ADI2 REFSYS Register Offsets *************************************************************************************/
/* ADI2 REFSYS Register Offsets *********************************************/
#define TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET 0x0000
#define TIVA_ADI2_REFSYS_SOCLDOCTL0_OFFSET 0x0002
@@ -66,7 +67,7 @@
#define TIVA_ADI2_REFSYS_HPOSCCTL1_OFFSET 0x000b
#define TIVA_ADI2_REFSYS_HPOSCCTL2_OFFSET 0x000c
/* ADI2 REFSYS Register Addresses ***********************************************************************************/
/* ADI2 REFSYS Register Addresses *******************************************/
#define TIVA_ADI2_REFSYS_REFSYSCTL0 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET)
#define TIVA_ADI2_REFSYS_SOCLDOCTL0 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL0_OFFSET)
@@ -79,7 +80,9 @@
#define TIVA_ADI2_REFSYS_HPOSCCTL1 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL1_OFFSET)
#define TIVA_ADI2_REFSYS_HPOSCCTL2 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL2_OFFSET)
/* Offsets may also be used in conjunction with access as described in cc13x2_cc26x2_ddi.h */
/* Offsets may also be used in conjunction with access as described in
* cc13x2_cc26x2_ddi.h
*/
#define TIVA_ADI2_REFSYS_DIR (TIVA_ADI2_BASE + TIVA_DDI_DIR_OFFSET)
#define TIVA_ADI2_REFSYS_SET (TIVA_ADI2_BASE + TIVA_DDI_SET_OFFSET)
@@ -88,7 +91,7 @@
#define TIVA_ADI2_REFSYS_MASK8B (TIVA_ADI2_BASE + TIVA_DDI_MASK8B_OFFSET)
#define TIVA_ADI2_REFSYS_MASK16B (TIVA_ADI2_BASE + TIVA_DDI_MASK16B_OFFSET)
/* ADI2 REFSYS Bitfield Definitions *********************************************************************************/
/* ADI2 REFSYS Bitfield Definitions *****************************************/
/* TIVA_ADI2_REFSYS_REFSYSCTL0 */
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_batmon.h
+11 -10
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_batmon.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AON_BATMON_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AON_BATMON_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* AON BATMON Register Offsets **************************************************************************************/
/* AON BATMON Register Offsets **********************************************/
#define TIVA_AON_BATMON_CTL_OFFSET 0x0000
#define TIVA_AON_BATMON_MEASCFG_OFFSET 0x0004
@@ -74,7 +75,7 @@
#define TIVA_AON_BATMON_TEMPUL_OFFSET 0x0058 /* Temperature Upper Limit */
#define TIVA_AON_BATMON_TEMPLL_OFFSET 0x005c /* Temperature Lower Limit */
/* AON BATMON Register Addresses ************************************************************************************/
/* AON BATMON Register Addresses ********************************************/
#define TIVA_AON_BATMON_CTL (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_CTL_OFFSET)
#define TIVA_AON_BATMON_MEASCFG (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_MEASCFG_OFFSET)
@@ -96,7 +97,7 @@
#define TIVA_AON_BATMON_TEMPUL (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPUL_OFFSET)
#define TIVA_AON_BATMON_TEMPLL (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPLL_OFFSET)
/* AON BATMON Register Bitfield Definitions *************************************************************************/
/* AON BATMON Register Bitfield Definitions *********************************/
/* AON_BATMON_CTL */
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_ioc.h
+11 -10
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_ioc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a compatible
* BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AON_IOC_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AON_IOC_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* AON IOC Register Offsets *****************************************************************************************/
/* AON IOC Register Offsets *************************************************/
#define TIVA_AON_IOC_IOSTRMIN_OFFSET 0x0000
#define TIVA_AON_IOC_IOSTRMED_OFFSET 0x0004
@@ -61,7 +62,7 @@
#define TIVA_AON_IOC_CLK32KCTL_OFFSET 0x0010 /* SCLK_LF External Output Control */
#define TIVA_AON_IOC_TCKCTL_OFFSET 0x0014 /* TCK IO Pin Control */
/* AON IOC Register Addresses ***************************************************************************************/
/* AON IOC Register Addresses ***********************************************/
#define TIVA_AON_IOC_IOSTRMIN (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMIN_OFFSET)
#define TIVA_AON_IOC_IOSTRMED (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMED_OFFSET)
@@ -70,7 +71,7 @@
#define TIVA_AON_IOC_CLK32KCTL (TIVA_AON_IOC_BASE + TIVA_AON_IOC_CLK32KCTL_OFFSET)
#define TIVA_AON_IOC_TCKCTL (TIVA_AON_IOC_BASE + TIVA_AON_IOC_TCKCTL_OFFSET)
/* AON IOC Bitfield Definitions *************************************************************************************/
/* AON IOC Bitfield Definitions *********************************************/
/* TIVA_AON_IOC_IOSTRMIN */
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_sysif.h
+11 -10
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_sysif.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AUX_SYSIF_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AUX_SYSIF_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* AUX SYSIF Register Offsets ***************************************************************************************/
/* AUX SYSIF Register Offsets ***********************************************/
#define TIVA_AUX_SYSIF_OPMODEREQ_OFFSET 0x0000 /* Operational Mode Request */
#define TIVA_AUX_SYSIF_OPMODEACK_OFFSET 0x0004 /* Operational Mode Acknowledgement */
@@ -96,7 +97,7 @@
#define TIVA_AUX_SYSIF_TIMER2BRIDGE_OFFSET 0x00b0 /* AUX_TIMER2 Bridge */
#define TIVA_AUX_SYSIF_SWPWRPROF_OFFSET 0x00b4 /* Software Power Profiler */
/* AUX SYSIF Register Addresses *************************************************************************************/
/* AUX SYSIF Register Addresses *********************************************/
#define TIVA_AUX_SYSIF_OPMODEREQ (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_OPMODEREQ_OFFSET)
#define TIVA_AUX_SYSIF_OPMODEACK (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_OPMODEACK_OFFSET)
@@ -140,7 +141,7 @@
#define TIVA_AUX_SYSIF_TIMER2BRIDGE (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_TIMER2BRIDGE_OFFSET)
#define TIVA_AUX_SYSIF_SWPWRPROF (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_SWPWRPROF_OFFSET)
/* AUX SYSIF Register Bifield Definitions ***************************************************************************/
/* AUX SYSIF Register Bifield Definitions ***********************************/
/* AUX_SYSIF_OPMODEREQ */
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h
+31 -11
View File
@@ -1,10 +1,11 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,24 +37,24 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_DDI0_OSC_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_DDI0_OSC_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
#include "hardware/tiva_ddi.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* DDI0 OSC Register Offsets ****************************************************************************************/
/* DDI0 OSC Register Offsets ************************************************/
#define TIVA_DDI0_OSC_CTL0_OFFSET 0x0000 /* Control 0 */
#define TIVA_DDI0_OSC_CTL1_OFFSET 0x0004 /* Control 1 */
@@ -73,7 +74,8 @@
#define TIVA_DDI0_OSC_STAT1_OFFSET 0x0040 /* Status 1 */
#define TIVA_DDI0_OSC_STAT2_OFFSET 0x0044 /* Status 2 */
/* DDI0 OSC Register Addresses **************************************************************************************/
/* DDI0 OSC Register Addresses **********************************************/
/* Direct access */
#define TIVA_DDI0_OSC_CTL0 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_CTL0_OFFSET)
@@ -94,7 +96,9 @@
#define TIVA_DDI0_OSC_STAT1 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_STAT1_OFFSET)
#define TIVA_DDI0_OSC_STAT2 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_STAT2_OFFSET)
/* Offsets may also be used in conjunction with access as described in cc13x2_cc26x2_ddi.h */
/* Offsets may also be used in conjunction with access as described in
* cc13x2_cc26x2_ddi.h
*/
#define TIVA_DDI0_OSC_DIR (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_DIR_OFFSET)
#define TIVA_DDI0_OSC_SET (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET)
@@ -103,13 +107,15 @@
#define TIVA_DDI0_OSC_MASK8B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK8B_OFFSET)
#define TIVA_DDI0_OSC_MASK16B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK16B_OFFSET)
/* DDI0 OSC Bitfield Definitions ************************************************************************************/
/* DDI0 OSC Bitfield Definitions ********************************************/
/* DDI0_OSC_CTL0 */
#define DDI0_OSC_CTL0_SCLK_HF_SRC_SEL (1 << 0) /* Bit 0: Source select for sclk_hf */
# define DDI0_OSC_CTL0_SCLK_HF_SRC_RCOSC (0) /* High frequency RCOSC clock */
# define DDI0_OSC_CTL0_SCLK_HF_SRC_XOSC DDI0_OSC_CTL0_SCLK_HF_SRC_SEL /* High frequency XOSC clock */
#define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT (2) /* Bits 2-3: Source select for sclk_lf */
#define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_MASK (3 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT)
# define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF (1 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency clock derived
@@ -118,6 +124,7 @@
* from High Frequency RCOSC */
# define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF (2 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency RCOSC */
# define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF (3 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency XOSC */
#define DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT (4) /* Bits 4-6: Source select for aclk_ref */
#define DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_MASK (7 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT)
# define DDI0_OSC_CTL0_ACLK_REF_SRC_RCOSCHF (0 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* RCOSC_HF derived (31.25kHz) */
@@ -125,20 +132,25 @@
# define DDI0_OSC_CTL0_ACLK_REF_SRC_RCOSCLF (2 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* RCOSC_LF (32kHz) */
# define DDI0_OSC_CTL0_ACLK_REF_SRC_XOSCLF (3 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* XOSC_LF (32.768kHz) */
# define DDI0_OSC_CTL0_ACLK_REF_SRC_RCOSCMF (4 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* RCOSC_MF (2MHz) */
#define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT (7) /* Bits 7-8: ource select for aclk_tdc */
#define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_MASK (3 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT)
# define DDI0_OSC_CTL0_ACLK_TDC_SRC_RCOSCHF48 (0 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* RCOSC_HF (48MHz) */
# define DDI0_OSC_CTL0_ACLK_TDC_SRC_RCOSCHF24 (1 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* RCOSC_HF (24MHz) */
# define DDI0_OSC_CTL0_ACLK_TDC_SRC_XOSCHF24 (2 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* XOSC_HF (24MHz) */
#define DDI0_OSC_CTL0_CLK_LOSS_EN (1 << 9) /* Bit 9: Enable SCLK_HF, SCLK_MF and SCLK_LF clock
* loss detection and indicators to the system
* controller */
#define DDI0_OSC_CTL0_XOSC_LF_DIG_BYPASS (1 << 10) /* Bit 10: Bypass XOSC_LF and use the digital
* input clock from AON for the xosc_lf */
# define DDI0_OSC_CTL0_XOSC_LF_DIG_32KHZ (0) /* Use 32kHz XOSC as xosc_lf
* clock source */
# define DDI0_OSC_CTL0_XOSC_LF_DIG_DIGINPUT DDI0_OSC_CTL0_XOSC_LF_DIG_BYPASS /* Use digital input (from AON)
* as xosc_lf clock source */
#define DDI0_OSC_CTL0_XOSC_HF_POWER_MODE (1 << 11) /* Bit 11 */
#define DDI0_OSC_CTL0_RCOSC_LF_TRIMMED (1 << 12) /* Bit 12 */
#define DDI0_OSC_CTL0_HPOSC_MODE_EN (1 << 14) /* Bit 14 */
@@ -264,6 +276,7 @@
# define DDI0_OSC_ATESTCTL_ATEST_RCOSCMF_BIAS (3 << DDI0_OSC_ATESTCTL_ATEST_RCOSCMF_SHIFT) /* ATEST enabled, bias current connected,
* ATEST internal to RCOSC_MF enabled
* to send out 2MHz clock. */
#define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT (14) /* Bits 14-15: Test mode control for RCOSC_MF */
#define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_MASK (3 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT)
# define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_DISABLE (0 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT) /* Test modes disabled */
@@ -273,6 +286,7 @@
# define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_BOOSTDIS (3 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT) /* Boosted bias current into self
* biased inverter + clock qualification
* disabled */
#define DDI0_OSC_ATESTCTL_SCLK_LF_AUX_EN (1 << 31) /* Bit 31: Enable 32 kHz clock to AUX_COMPB */
/* DDI0_OSC_ADCDOUBLERNANOAMPCTL */
@@ -332,6 +346,7 @@
# define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_MIN (8 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_SHIFT) /* minimum current */
# define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_DEFAULT (0 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_SHIFT) /* default current */
# define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_MAX (7 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_SHIFT) /* maximum current */
#define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_SHIFT (4) /* Bits 4-5: Select fine resistor for frequency adjustment */
#define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_MASK (3 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_SHIFT)
# define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_11K (0 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_SHIFT) /* 11kohms, minimum resistance,
@@ -340,6 +355,7 @@
# define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_16K (2 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_SHIFT) /* 16kohms */
# define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_20K (3 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_SHIFT) /* 20kohms, max resistance,
* min freq */
#define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_SHIFT (6) /* Bits 6-7: Select coarse resistor for frequency adjustment */
#define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_MASK (3 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_SHIFT)
# define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_DEFAULT (0 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_SHIFT) /* 400kohms, default */
@@ -349,6 +365,7 @@
# define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_400KOHM (0 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_SHIFT) /* 400kohms */
# define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_500KOHM (3 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_SHIFT) /* 500kohms */
# define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_600KOHM (2 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_SHIFT) /* 600kohms */
#define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL (1 << 8) /* Bit 8: Select alternate regulator type */
#define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_SHIFT (9) /* Bits 9-15: Adjust RCOSC_MF capacitor array */
#define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_MASK (0x7f << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_SHIFT)
@@ -382,8 +399,11 @@
#define DDI0_OSC_STAT0_RCOSC_LF_EN (1 << 21) /* Bit 21: RCOSC_LF enable */
#define DDI0_OSC_STAT0_RCOSC_HF_EN (1 << 22) /* Bit 22: RSOSC_HF enable */
#define DDI0_OSC_STAT0_SCLK_HF_SRC (1 << 28) /* Bit 28: Indicates source for sclk_hf */
# define DDI0_OSC_STAT0_SCLK_HF_SRC_RCOSC (0) /* High frequency RCOSC clock */
# define DDI0_OSC_STAT0_SCLK_HF_SRC_XOSC DDI0_OSC_STAT0_SCLK_HF_SRC /* High frequency XOSC */
#define DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT (29) /* Bits 29-30: Indicates source for the sclk_lf */
#define DDI0_OSC_STAT0_SCLK_LF_SRC_MASK (3 << DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT)
# define DDI0_OSC_STAT0_SCLK_LF_SRC(n) ((uint32_t)(n) << DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT)
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_gpio.h
+17 -16
View File
@@ -1,10 +1,11 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_gpio.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a compatible
* BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_GPIO_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_GPIO_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* GPIO Register Offsets ************************************************************/
/* GPIO Register Offsets ****************************************************/
#define TIVA_GPIO_DOUT_PIN_OFFSET(n) ((n) & ~3)
# define TIVA_GPIO_DOUT_PIN3_0_OFFSET 0x0000 /* Data Out 0 to 3 */
@@ -71,7 +72,7 @@
#define TIVA_GPIO_DOE_OFFSET 0x00d0 /* Data Output Enable for DIO 0 to 31 */
#define TIVA_GPIO_EVFLAGS_OFFSET 0x00e0 /* Event Register for DIO 0 to 31 */
/* GPIO Register Addresses **********************************************************/
/* GPIO Register Addresses **************************************************/
#define TIVA_GPIO_DOUT_PIN_BASE(n) (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN_OFFSET(n))
# define TIVA_GPIO_DOUT_PIN3_0 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN3_0_OFFSET)
@@ -90,7 +91,7 @@
#define TIVA_GPIO_DOE (TIVA_GPIO_BASE + TIVA_GPIO_DOE_OFFSET)
#define TIVA_GPIO_EVFLAGS (TIVA_GPIO_BASE + TIVA_GPIO_EVFLAGS_OFFSET)
/* GPIO Register Bitfield Definitions ***********************************************/
/* GPIO Register Bitfield Definitions ***************************************/
/* Data Out n to n + 3 */
@@ -125,16 +126,16 @@
#define GPIO_EVFLAGS(n) (1 << (n))
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_GPIO_H */
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_i2c.h
+9 -8
View File
@@ -1,10 +1,11 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_i2c.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a compatible
* BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,16 +37,16 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_I2C_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_I2C_H
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* I2C register offsets *********************************************************************/
/* I2C register offsets *****************************************************/
#define TIVA_I2C_SOAR_OFFSET 0x0000 /* Slave Own Address */
#define TIVA_I2C_SSTAT_OFFSET 0x0004 /* Slave Status */
@@ -67,7 +68,7 @@
#define TIVA_I2C_MICR_OFFSET 0x081c /* Master Interrupt Clear */
#define TIVA_I2C_MCR_OFFSET 0x0820 /* Master Configuration */
/* I2C register addresses *******************************************************************/
/* I2C register addresses ***************************************************/
#define TIVA_I2C0_SOAR (TIVA_I2C0_BASE + TIVA_I2C_SOAR_OFFSET)
#define TIVA_I2C0_SSTAT (TIVA_I2C0_BASE + TIVA_I2C_SSTAT_OFFSET)
@@ -89,7 +90,7 @@
#define TIVA_I2C0_MICR (TIVA_I2C0_BASE + TIVA_I2C_MICR_OFFSET)
#define TIVA_I2C0_MCR (TIVA_I2C0_BASE + TIVA_I2C_MCR_OFFSET)
/* I2C bitfield definitions *****************************************************************/
/* I2C bitfield definitions *************************************************/
/* Slave Own Address */
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ioc.h
+25 -17
View File
@@ -1,10 +1,11 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ioc.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a compatible
* BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,25 +37,25 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2IOC_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2IOC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#define TIVA_NDIO 32 /* DIO0-31 */
/* IOC register offsets ************************************************************/
/* IOC register offsets *****************************************************/
#define TIVA_IOC_IOCFG_OFFSET(n) ((n) << 2)
# define TIVA_IOC_IOCFG0_OFFSET 0x0000 /* Configuration of DIO0 */
@@ -90,7 +91,7 @@
# define TIVA_IOC_IOCFG30_OFFSET 0x0078 /* Configuration of DIO30 */
# define TIVA_IOC_IOCFG31_OFFSET 0x007c /* Configuration of DIO31 */
/* IOC register addresses **********************************************************/
/* IOC register addresses ***************************************************/
#define TIVA_IOC_IOCFG(n) (TIVA_IOC_BASE + TIVA_IOC_IOCFG_OFFSET(n))
# define TIVA_IOC_IOCFG0 (TIVA_IOC_BASE + TIVA_IOC_IOCFG0_OFFSET)
@@ -126,11 +127,12 @@
# define TIVA_IOC_IOCFG30 (TIVA_IOC_BASE + TIVA_IOC_IOCFG30_OFFSET)
# define TIVA_IOC_IOCFG31 (TIVA_IOC_BASE + TIVA_IOC_IOCFG31_OFFSET)
/* IOC register bit settings *******************************************************/
/* IOC register bit settings ************************************************/
#define IOC_IOCFG_PORTID_SHIFT (0) /* Bits 0-5: Selects DIO usage */
#define IOC_IOCFG_PORTID_MASK (0x3f << IOC_IOCFG_PORTID_SHIFT)
# define IOC_IOCFG_PORTID(n) ((uint32_t)(n) << IOC_IOCFG_PORTID_SHIFT) /* See PORT ID definitions */
#define IOC_IOCFG_IOEV_MCU_WUEN (1 << 6) /* Bit 6: Input edge asserts MCU_WU event */
#define IOC_IOCFG_IOEV_RTCEN (1 << 7) /* Bit 7: Input edge asserts RTC event */
#define IOC_IOCFG_IOSTR_SHIFT (8) /* Bits 8-9: I/O drive strength */
@@ -139,23 +141,27 @@
# define IOC_IOCFG_IOSTR_MIN (1 << IOC_IOCFG_IOSTR_SHIFT) /* Minimum drive strength */
# define IOC_IOCFG_IOSTR_MED (2 << IOC_IOCFG_IOSTR_SHIFT) /* Medium drive strength */
# define IOC_IOCFG_IOSTR_MAX (3 << IOC_IOCFG_IOSTR_SHIFT) /* Maximum drive strength */
#define IOC_IOCFG_IOCURR_SHIFT (10) /* Bits 10-11: I/O current mode */
#define IOC_IOCFG_IOCURR_MASK (3 << IOC_IOCFG_IOCURR_SHIFT)
# define IOC_IOCFG_IOCURR_2MA (0 << IOC_IOCFG_IOCURR_SHIFT) /* Extended-Current (EC) mode */
# define IOC_IOCFG_IOCURR_4MA (1 << IOC_IOCFG_IOCURR_SHIFT) /* High-Current (HC) mode */
# define IOC_IOCFG_IOCURR_8MA (2 << IOC_IOCFG_IOCURR_SHIFT) /* Low-Current (LC) mode */
#define IOC_IOCFG_SLEW_RED (1 << 12) /* Bit 12: Reduces output slew rate */
#define IOC_IOCFG_PULLCTL_SHIFT (13) /* Bits 13-14: Pull Control */
#define IOC_IOCFG_PULLCTL_MASK (3 << IOC_IOCFG_PULLCTL_SHIFT)
# define IOC_IOCFG_PULLCTL_DIS (3 << IOC_IOCFG_PULLCTL_SHIFT) /* No pull */
# define IOC_IOCFG_PULLCTL_DWN (1 << IOC_IOCFG_PULLCTL_SHIFT) /* Pull down */
# define IOC_IOCFG_PULLCTL_UP (2 << IOC_IOCFG_PULLCTL_SHIFT) /* Pull up */
#define IOC_IOCFG_EDGEDET_SHIFT (16) /* Bits 16-17: Enable edge events generation */
#define IOC_IOCFG_EDGEDET_MASK (3 << IOC_IOCFG_EDGEDET_SHIFT)
# define IOC_IOCFG_EDGEDET_NONE (0 << IOC_IOCFG_EDGEDET_SHIFT) /* No edge detection */
# define IOC_IOCFG_EDGEDET_NEG (1 << IOC_IOCFG_EDGEDET_SHIFT) /* Negative edge detection */
# define IOC_IOCFG_EDGEDET_POS (2 << IOC_IOCFG_EDGEDET_SHIFT) /* Positive edge detection */
# define IOC_IOCFG_EDGEDET_BOTH (3 << IOC_IOCFG_EDGEDET_SHIFT) /* Both edge detection */
#define IOC_IOCFG_EDGE_IRQEN (1 << 18) /* Bit 18: Enable interrupt generation */
#define IOC_IOCFG_IOEV_AON_PROG0 (1 << 21) /* Bit 21: Input edge asserts AON_PROG0 */
#define IOC_IOCFG_IOEV_AON_PROG1 (1 << 22) /* Bit 22: Input edge asserts AON_PROG1 */
@@ -168,12 +174,14 @@
# define IOC_IOCFG_IOMODE_OPENDRINV (5 << IOC_IOCFG_IOMODE_SHIFT) /* Open drain, inverted I/O */
# define IOC_IOCFG_IOMODE_OPENSRC (6 << IOC_IOCFG_IOMODE_SHIFT) /* Open source */
# define IOC_IOCFG_IOMODE_OPENSRCINV (7 << IOC_IOCFG_IOMODE_SHIFT) /* Open source, inverted I/O */
#define IOC_IOCFG_WUCFG_SHIFT (27) /* Bits 27-28: Wakeup Configuration */
#define IOC_IOCFG_WUCFG_MASK (3 << IOC_IOCFG_WUCFG_SHIFT)
# define IOC_IOCFG_WUCFG_NONE (0 << IOC_IOCFG_WUCFG_SHIFT) /* 0, 1: Wakeup disabled */
# define IOC_IOCFG_WUCFG_ENABLE (2 << IOC_IOCFG_WUCFG_SHIFT) /* 2, 3: Wakeup enabled */
# define IOC_IOCFG_WUCFG_WAKEUPL (2 << IOC_IOCFG_WUCFG_SHIFT) /* 2: Wakeup on transition low */
# define IOC_IOCFG_WUCFG_WEKUPH (3 << IOC_IOCFG_WUCFG_SHIFT) /* 3: Wakeup on transition high */
#define IOC_IOCFG_IE (1 << 29) /* Bit 29: Input enable */
#define IOC_IOCFG_HYSTEN (1 << 30) /* Bit 30: Input hysteresis enable */
@@ -226,16 +234,16 @@
#define IOC_IOCFG_PORTID_RFC_SMI_CLOUT 0x37
#define IOC_IOCFG_PORTID_RFC_SMI_CLIN 0x38
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2IOC_H */
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_timer.h
+17 -16
View File
@@ -1,10 +1,11 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_timer.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a compatible
* BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,38 +37,38 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_TIMER_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_TIMER_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* TIMER Register Offsets ***********************************************************/
/* TIMER Register Offsets ***************************************************/
/* TIMER Register Addresses *********************************************************/
/* TIMER Register Addresses *************************************************/
/* TIMER Register Bitfield Definitions **********************************************/
/* TIMER Register Bitfield Definitions **************************************/
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_TIMER_H */
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_uart.h
+15 -14
View File
@@ -1,10 +1,11 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_uart.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
* Technical content derives from a TI header file that has a compatible
* BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
@@ -36,23 +37,23 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_UART_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_UART_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/tiva_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* UART register offsets ************************************************************/
/* UART register offsets ****************************************************/
#define TIVA_UART_DR_OFFSET 0x0000 /* UART Data */
#define TIVA_UART_RSR_OFFSET 0x0004 /* UART Receive Status */
@@ -69,7 +70,7 @@
#define TIVA_UART_ICR_OFFSET 0x0044 /* UART Interrupt Clear */
#define TIVA_UART_DMACTL_OFFSET 0x0048 /* UART DMA Control */
/* UART register addresses **********************************************************/
/* UART register addresses **************************************************/
#define TIVA_UART_BASE(n) (TIVA_UART0_BASE + (n)*0x01000)
@@ -122,7 +123,7 @@
# define TIVA_UART1_DMACTL (TIVA_UART1_BASE + TIVA_UART_DMACTL_OFFSET)
#endif
/* UART register bit settings *******************************************************/
/* UART register bit settings ***********************************************/
/* UART Data (DR) */
@@ -264,12 +265,12 @@
#define UART_DMACTL_TXDMAE (1 << 1) /* Bit 1: Transmit DMA Enable */
#define UART_DMACTL_DMAERR (1 << 2) /* Bit 2: DMA on Error */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_UART_H */
arch/arm/src/tiva/hardware/lm/lm3s_ethernet.h
+18 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/lm/lm3s_ethernet.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_ETHERNET_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_ETHERNET_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/net/mii.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Ethernet Controller Register Offsets *********************************************/
/* Ethernet Controller Register Offsets *************************************/
/* Ethernet MAC Register Offsets */
@@ -59,7 +59,7 @@
/* MII Management Register Offsets (see include/nuttx/net/mii.h) */
/* Ethernet Controller Register Addresses *******************************************/
/* Ethernet Controller Register Addresses ***********************************/
#define TIVA_MAC_RIS (TIVA_ETHCON_BASE + TIVA_MAC_RIS_OFFSET)
#define TIVA_MAC_IACK (TIVA_ETHCON_BASE + TIVA_MAC_IACK_OFFSET)
@@ -96,9 +96,11 @@
#define MAC_MII_LEDCONFIG (TIVA_ETHCON_BASE + MII_TIVA_LEDCONFIG)
#define MAC_MII_MDICONTROL (TIVA_ETHCON_BASE + MII_TIVA_MDICONTROL)
/* Ethernet Controller Register Bit Definitions *************************************/
/* Ethernet Controller Register Bit Definitions *****************************/
/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */
/* Ethernet MAC Raw Interrupt Status/Acknowledge
* (MACRIS/MACIACK), offset 0x000
*/
#define MAC_RIS_RXINT (1 << 0) /* Bit 0: Packet Received */
#define MAC_RIS_TXER (1 << 1) /* Bit 1: Transmit Error */
@@ -173,16 +175,16 @@
#define MAC_TR_NEWTX (1 << 0) /* Bit 0: New Transmission */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_ETHERNET_H */
arch/arm/src/tiva/hardware/lm/lm3s_flash.h
+26 -26
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/lm/lm3s_flash.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_FLASH_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_FLASH_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* FLASH dimensions ****************************************************************/
/* FLASH dimensions *********************************************************/
#if defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM4F120) || \
defined(CONFIG_ARCH_CHIP_LM3S8962) || defined(CONFIG_ARCH_CHIP_LM3S9B96) || \
@@ -39,8 +39,8 @@
defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || defined(CONFIG_ARCH_CHIP_TM4C123GH6PM) || \
defined(CONFIG_ARCH_CHIP_TM4C123AH6PM)
/* These parts all support a 1KiB erase page size and a total FLASH memory size
* of 256Kib or 256 pages.
/* These parts all support a 1KiB erase page size and a total FLASH memory
* size of 256Kib or 256 pages.
*/
# define TIVA_FLASH_NPAGES 256
@@ -49,10 +49,10 @@
#define TIVA_FLASH_SIZE (TIVA_FLASH_NPAGES * TIVA_FLASH_PAGESIZE)
/* FLASH register offsets ***********************************************************/
/* FLASH register offsets ***************************************************/
/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
* control base address of TIVA_FLASHCON_BASE.
/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the
* Flash control base address of TIVA_FLASHCON_BASE.
*/
#define TIVA_FLASH_FMA_OFFSET 0x000 /* Flash memory address */
@@ -62,8 +62,8 @@
#define TIVA_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */
#define TIVA_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */
/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
* System Control base address of TIVA_SYSCON_BASE
/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative
* to the System Control base address of TIVA_SYSCON_BASE
*/
#define TIVA_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */
@@ -81,10 +81,10 @@
#define TIVA_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */
#define TIVA_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */
/* FLASH register addresses *********************************************************/
/* FLASH register addresses *************************************************/
/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
* control base address of TIVA_FLASHCON_BASE.
/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the
* Flash control base address of TIVA_FLASHCON_BASE.
*/
#define TIVA_FLASH_FMA (TIVA_FLASHCON_BASE + TIVA_FLASH_FMA_OFFSET)
@@ -94,8 +94,8 @@
#define TIVA_FLASH_FCIM (TIVA_FLASHCON_BASE + TIVA_FLASH_FCIM_OFFSET)
#define TIVA_FLASH_FCMISC (TIVA_FLASHCON_BASE + TIVA_FLASH_FCMISC_OFFSET)
/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
* System Control base address of TIVA_SYSCON_BASE
/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative
* to the System Control base address of TIVA_SYSCON_BASE
*/
#define TIVA_FLASH_FMPRE (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE_OFFSET)
@@ -113,7 +113,7 @@
#define TIVA_FLASH_FMPPE2 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE2_OFFSET)
#define TIVA_FLASH_FMPPE3 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE3_OFFSET)
/* FLASH register bit definitions ***************************************************/
/* FLASH register bit definitions *******************************************/
#define FLASH_FMA_OFFSET_SHIFT 0 /* Bits 17-0: Address Offset */
#define FLASH_FMA_OFFSET_MASK (0x0003ffff << FLASH_FMA_OFFSET_SHIFT)
@@ -132,16 +132,16 @@
#define FLASH_FMC_WRKEY_MASK (0xffff << FLASH_FMC_WRKEY_SHIFT)
#define FLASH_FMC_WRKEY (0xa442 << FLASH_FMC_WRKEY_SHIFT) /* Magic write key */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_FLASH_H */
arch/arm/src/tiva/hardware/lm/lm3s_gpio.h
+16 -15
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/lm/lm3s_gpio.h
*
* Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
@@ -32,20 +32,21 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_GPIO_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_GPIO_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* REVISIT: Why do we not use the AHB aperture for all GPIO accesses? */
#define TIVA_GPIOK_BASE TIVA_GPIOKAHB_BASE
@@ -58,7 +59,7 @@
#define TIVA_GPIOS_BASE TIVA_GPIOSAHB_BASE
#define TIVA_GPIOT_BASE TIVA_GPIOTAHB_BASE
/* GPIO Register Offsets ************************************************************/
/* GPIO Register Offsets ****************************************************/
#define TIVA_GPIO_DATA_OFFSET 0x0000 /* GPIO Data */
#define TIVA_GPIO_DIR_OFFSET 0x0400 /* GPIO Direction */
@@ -98,7 +99,7 @@
#define TIVA_GPIO_PCELLID2_OFFSET 0x0ff8 /* GPIO PrimeCell Identification 2 */
#define TIVA_GPIO_PCELLID3_OFFSET 0x0ffc /* GPIO PrimeCell Identification 3*/
/* GPIO Register Addresses **********************************************************/
/* GPIO Register Addresses **************************************************/
#if TIVA_NPORTS > 0
@@ -457,7 +458,7 @@
# define TIVA_GPIOJ_PCELLID3 (TIVA_GPIOJ_BASE + TIVA_GPIO_PCELLID3_OFFSET)
#endif
/* GPIO Register Bitfield Definitions ***********************************************/
/* GPIO Register Bitfield Definitions ***************************************/
/* GPIO Lock */
@@ -488,16 +489,16 @@
# define GPIO_PCTL_PMC7_MASK (15 << GPIO_PCTL_PMC7_SHIFT)
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_GPIO_H */
arch/arm/src/tiva/hardware/lm/lm3s_memorymap.h
+26 -19
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/lm/lm3s_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,22 +16,22 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_MEMORYMAP_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Memory map ***********************************************************************/
/* Memory map ***************************************************************/
#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \
defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962)
@@ -68,7 +68,7 @@
# define TIVA_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
# define TIVA_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
# define TIVA_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
/* -0xe000dfff: Reserved */
/* -0xe000dfff: Reserved */
# define TIVA_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
/* -0xe003ffff: Reserved */
# define TIVA_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
@@ -77,11 +77,13 @@
# error "Memory map not specified for this LM3S chip"
#endif
/* Peripheral base addresses ********************************************************/
/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few different
* peripheral modules. They could probably be combined into one peripheral memory
* map. However, keeping them separate does also provide so early, compile-time
* error detection that makes the duplication worthwhile.
/* Peripheral base addresses ************************************************/
/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few
* different peripheral modules. They could probably be combined into one
* peripheral memory map. However, keeping them separate does also provide
* so early, compile-time error detection that makes the duplication
* worthwhile.
*/
#if defined(CONFIG_ARCH_CHIP_LM3S6918)
@@ -99,6 +101,7 @@
# define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
/* -0x1ffff: Reserved */
/* Peripheral Base Addresses */
# define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x20fff: I2C0 */
@@ -138,6 +141,7 @@
# define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
/* -0x1ffff: Reserved */
/* Peripheral Base Addresses */
# define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x20fff: I2C0 */
@@ -178,6 +182,7 @@
# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
# define TIVA_UART2_BASE (TIVA_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
/* -0x1ffff: Reserved */
/* Peripheral Base Addresses */
# define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x20fff: I2C0 */
@@ -221,6 +226,7 @@
# define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
/* -0x1ffff: Reserved */
/* Peripheral Base Addresses */
# define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x20fff: I2C0 */
@@ -267,6 +273,7 @@
# define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
# define TIVA_UART2_BASE (TIVA_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
/* -0x1ffff: Reserved */
/* Peripheral Base Addresses */
# define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x207ff: I2C0 */
@@ -322,16 +329,16 @@
# error "Peripheral base addresses not specified for this Stellaris chip"
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_MEMORYMAP_H */
arch/arm/src/tiva/hardware/lm/lm3s_pinmap.h
+13 -13
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/tiva/hardware/lm/lm3s_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_PINMAP_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_PINMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* The following lists the input value to tiva_configgpio to setup the alternate,
* hardware function for each pin.
/* The following lists the input value to tiva_configgpio to setup the
* alternate, hardware function for each pin.
*/
#if defined(CONFIG_ARCH_CHIP_LM3S6918)
@@ -261,18 +261,18 @@
# define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PF1: QEI module 1 index. ) */
# define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */
# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PG1:PWM Generator 0, PWM1 */
# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PG1:PWM Generator 0, PWM1 */
#else
# error "Unknown Stellaris chip"
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/****************************************************************************
* Public Function Prototypes

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