diff --git a/arch/arm/src/tiva/cc13xx/cc13x0_rom.c b/arch/arm/src/tiva/cc13xx/cc13x0_rom.c index f0d0ae034e4..5800d22368f 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x0_rom.c +++ b/arch/arm/src/tiva/cc13xx/cc13x0_rom.c @@ -1,10 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/cc13xx/cc13x0_rom.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * This is a port of TI's setup_rom.c file which has a fully compatible BSD license: + * This is a port of TI's setup_rom.c file which has a fully compatible BSD + * license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,11 +37,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -60,13 +61,13 @@ #include "cc13xx/cc13x0_rom.h" -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: rom_set_vddr_level - ************************************************************************************/ + ****************************************************************************/ static void rom_set_vddr_level(uint32_t ccfg_modeconf) { @@ -77,7 +78,8 @@ static void rom_set_vddr_level(uint32_t ccfg_modeconf) uint16_t regval16; /* VDDS_BOD_LEVEL = 1 means that boost mode is selected - Step up VDDR_TRIM - * to FCFG1..VDDR_TRIM_HH */ + * to FCFG1..VDDR_TRIM_HH + */ rawtrim = ((getreg32(TIVA_FCFG1_VOLT_TRIM) & FCFG1_VOLT_TRIM_VDDR_TRIM_HH_MASK) >> @@ -117,7 +119,8 @@ static void rom_set_vddr_level(uint32_t ccfg_modeconf) ((currenttrim << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) & ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MASK); putreg16(regval16, - TIVA_ADI3_REFSYS_MASK8B + (TIVA_ADI3_REFSYS_DCDCCTL0_OFFSET * 2)); + TIVA_ADI3_REFSYS_MASK8B + + (TIVA_ADI3_REFSYS_DCDCCTL0_OFFSET * 2)); /* Force SCLK_LF period wait on next read */ @@ -131,23 +134,23 @@ static void rom_set_vddr_level(uint32_t ccfg_modeconf) putreg32(1, TIVA_AON_RTC_SYNC); getreg32(TIVA_AON_RTC_SYNC); /* Wait one more SCLK_LF period - * before re-enabling VDDR BOD */ + * before re-enabling VDDR BOD */ modifyreg32(TIVA_AON_SYSCTL_RESETCTL, 0, AON_SYSCTL_RESETCTL_VDDR_LOSS_EN); getreg32(TIVA_AON_RTC_SYNC); /* And finally wait for - * VDDR_LOSS_EN setting to - * propagate */ + * VDDR_LOSS_EN setting to + * propagate */ } } -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_coldreset_from_shutdown_cfg1 - ************************************************************************************/ + ****************************************************************************/ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf) { @@ -158,15 +161,19 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf) uint16_t regval16; /* Check for CC13xx boost mode The combination VDDR_EXT_LOAD=0 and - * VDDS_BOD_LEVEL=1 is defined to select boost mode */ + * VDDS_BOD_LEVEL=1 is defined to select boost mode + */ if (((ccfg_modeconf & CCFG_MODE_CONF_1_VDDR_EXT_LOAD) == 0) && ((ccfg_modeconf & CCFG_MODE_CONF_1_VDDS_BOD_LEVEL) != 0)) { - /* Set VDDS_BOD trim - using masked write {MASK8:DATA8} - TRIM_VDDS_BOD - * is bits[7:3] of ADI3..REFSYSCTL1 - Needs a positive transition on - * BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to latch new VDDS BOD. Set to 0 - * first to guarantee a positive transition. */ + /* Set VDDS_BOD trim - using masked write {MASK8:DATA8} + * + * - TRIM_VDDS_BOD is bits[7:3] of ADI3..REFSYSCTL1 + * - Needs a positive transition on BOD_BG_TRIM_EN + * (bit[7] of REFSYSCTL3) to latch new VDDS BOD. + * Set to 0 first to guarantee a positive transition. + */ putreg8(ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN, TIVA_ADI3_REFSYS_CLR + TIVA_ADI3_REFSYS_REFSYSCTL3_OFFSET); @@ -177,7 +184,8 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf) putreg16((ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_MASK << 8) | (ADI3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31), - TIVA_ADI3_REFSYS_MASK8B + (TIVA_ADI3_REFSYS_REFSYSCTL1_OFFSET * 2)); + TIVA_ADI3_REFSYS_MASK8B + + (TIVA_ADI3_REFSYS_REFSYSCTL1_OFFSET * 2)); putreg8(ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN, TIVA_ADI3_REFSYS_SET + TIVA_ADI3_REFSYS_REFSYSCTL3_OFFSET); @@ -185,27 +193,29 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf) vddr_sleeptrim = rom_signextend_vddrtrim((getreg32(TIVA_FCFG1_VOLT_TRIM) & - FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_MASK) >> - FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_SHIFT); + FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_MASK) >> + FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_SHIFT); } else { vddr_sleeptrim = rom_signextend_vddrtrim((getreg32(TIVA_FCFG1_LDO_TRIM) & - FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_MASK) >> - FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_SHIFT); + FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_MASK) >> + FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_SHIFT); } /* Adjust the VDDR_TRIM_SLEEP value with value adjustable by customer - * (CCFG_MODE_CONF_1_VDDR_TRIM_SLEEP_DELTA) Read and sign extend VddrSleepDelta - * (in range -8 to +7) */ + * (CCFG_MODE_CONF_1_VDDR_TRIM_SLEEP_DELTA) + * Read and sign extend VddrSleepDelta (in range -8 to +7) + */ vddr_sleepdelta = (((int32_t) (ccfg_modeconf << (32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_WIDTH - - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_SHIFT))) >> (32 - - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_WIDTH)); + CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_SHIFT))) >> + (32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_WIDTH)); + /* Calculate new VDDR sleep trim */ vddr_sleeptrim = (vddr_sleeptrim + vddr_sleepdelta + 1); @@ -222,7 +232,8 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf) /* Write adjusted value using MASKED write (MASK8) */ regval16 = ((ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_MASK << 8) | - ((vddr_sleeptrim << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) & + ((vddr_sleeptrim << + ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) & ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_MASK)); putreg16(regval16, TIVA_ADI3_REFSYS_MASK8B + (TIVA_ADI3_REFSYS_DCDCCTL1_OFFSET * 2)); @@ -262,8 +273,8 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf) setbits |= AON_SYSCTL_PWRCTL_DCDC_EN; } - /* Set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE Note: Inverse - * polarity + /* Set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE + * Note: Inverse polarity */ if ((ccfg_modeconf & CCFG_MODE_CONF_1_DCDC_ACTIVE) != 0) @@ -278,9 +289,9 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf) modifyreg32(TIVA_AON_SYSCTL_PWRCTL, clrbits, setbits); } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_coldreset_from_shutdown_cfg2 - ************************************************************************************/ + ****************************************************************************/ void rom_setup_coldreset_from_shutdown_cfg2(uint32_t fcfg1_revision, uint32_t ccfg_modeconf) @@ -289,40 +300,52 @@ void rom_setup_coldreset_from_shutdown_cfg2(uint32_t fcfg1_revision, /* Following sequence is required for using XOSCHF, if not included devices * crashes when trying to switch to XOSCHF. Trim CAP settings. Get and set - * trim value for the ANABYPASS_VALUE1 register */ + * trim value for the ANABYPASS_VALUE1 register + */ trim = rom_setup_get_trim_anabypass_value1(ccfg_modeconf); - rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0_OSC_ANABYPASSVAL1_OFFSET, trim); + rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, + TIVA_DDI0_OSC_ANABYPASSVAL1_OFFSET, trim); /* Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and - * RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register. */ + * RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register. + */ trim = rom_setup_get_trim_rcosc_lfrtunectuntrim(); - rom_ddi_bitfield_write16(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0_OSC_LFOSCCTL_OFFSET, - (DDI0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM | - DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM), - DDI0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_SHIFT, trim); + rom_ddi_bitfield_write16(TIVA_AUX_DDI0_OSC_BASE, + TIVA_DDI0_OSC_LFOSCCTL_OFFSET, + (DDI0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM | + DDI0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM), + DDI0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_SHIFT, trim); - /* Trim XOSCHF IBIAS THERM. Get and set trim value for the XOSCHF IBIAS THERM - * bit field in the ANABYPASS_VALUE2 register. Other register bit fields are - * set to 0. */ + /* Trim XOSCHF IBIAS THERM. + * Get and set trim value for the XOSCHF IBIAS THERM bit field in the + * ANABYPASS_VALUE2 register. + * Other register bit fields are set to 0. + */ trim = rom_setup_get_trim_xosc_hfibiastherm(); - rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0_OSC_ANABYPASSVAL2_OFFSET, + rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, + TIVA_DDI0_OSC_ANABYPASSVAL2_OFFSET, trim << DDI0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_SHIFT); /* Trim AMPCOMP settings required before switch to XOSCHF */ trim = rom_setup_get_trim_ampcompth2(); - rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0_OSC_AMPCOMPTH2_OFFSET, trim); + rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, + TIVA_DDI0_OSC_AMPCOMPTH2_OFFSET, trim); trim = rom_setup_get_trim_ampcompth1(); - rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0_OSC_AMPCOMPTH1_OFFSET, trim); + rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, + TIVA_DDI0_OSC_AMPCOMPTH1_OFFSET, trim); trim = rom_setup_get_trim_ampcompctrl(fcfg1_revision); - rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0_OSC_AMPCOMPCTL_OFFSET, trim); + rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, + TIVA_DDI0_OSC_AMPCOMPCTL_OFFSET, trim); /* Set trim for DDI0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN in accordance - * to FCFG1 setting This is bit[5] in the TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL - * register Using MASK4 write + 1 => writing to bits[7:4] */ + * to FCFG1 setting + * This is bit[5] in the TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL + * register Using MASK4 write + 1 => writing to bits[7:4] + */ trim = rom_setup_get_trim_adcshmodeen(fcfg1_revision); putreg8((0x20 | (trim << 1), @@ -330,26 +353,32 @@ void rom_setup_coldreset_from_shutdown_cfg2(uint32_t fcfg1_revision, (TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL_OFFSET * 2) + 1)); /* Set trim for DDI0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in accordance - * to FCFG1 setting This is bit[4] in the TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL - * register Using MASK4 write + 1 => writing to bits[7:4] */ + * to FCFG1 setting + * This is bit[4] in the TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL + * register Using MASK4 write + 1 => writing to bits[7:4] + */ trim = rom_setup_get_trim_adcshvbufen(fcfg1_revision); putreg8(0x10 | trim, TIVA_AUX_DDI0_OSC_BASE + TIVA_DI_MASK4B_OFFSET + (TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL_OFFSET * 2) + 1); - /* Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields - * in the TIVA_DDI0_OSC_XOSCHFCTL register in accordance to FCFG1 setting. - * Remaining register bit fields are set to their reset values of 0. */ + /* Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit + * fields in the TIVA_DDI0_OSC_XOSCHFCTL register in accordance to FCFG1 + * setting. + * Remaining register bit fields are set to their reset values of 0. + */ trim = rom_setup_get_trim_xosc_hfctrl(fcfg1_revision); - rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0_OSC_XOSCHFCTL_OFFSET, trim); + rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, + TIVA_DDI0_OSC_XOSCHFCTL_OFFSET, trim); - /* Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting - * (This is bits [18:17] in TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL) (Using MASK4 - * write + 4 => writing to bits[19:16] => (4*4)) (Assuming: - * DDI0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_SHIFT = 17 and - * that DDI0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_MASK = + /* Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 + * setting (This is bits [18:17] in TIVA_DDI0_OSC_ADCDOUBLERNANOAMPCTL) + * (Using MASK4 write + 4 => writing to bits[19:16] => (4*4)) (Assuming: + * DDI0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_SHIFT = 17 + * and that + * DDI0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_MASK = * 0x00060000) */ @@ -360,8 +389,8 @@ void rom_setup_coldreset_from_shutdown_cfg2(uint32_t fcfg1_revision, /* Update DDI0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from * FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM This is TIVA_DDI0_OSC_ATESTCTL - * bit[7] ( TIVA_DDI0_OSC_ATESTCTL is currently hidden (but=0x00000020)) Using - * MASK4 write + 1 => writing to bits[7:4] + * bit[7] ( TIVA_DDI0_OSC_ATESTCTL is currently hidden (but=0x00000020)) + * Using MASK4 write + 1 => writing to bits[7:4] */ trim = rom_setup_get_trim_rcosc_lfibiastrim(fcfg1_revision); @@ -371,8 +400,8 @@ void rom_setup_coldreset_from_shutdown_cfg2(uint32_t fcfg1_revision, /* Update DDI0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and * DDI0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write This can be - * simplified since the registers are packed together in the same order both - * in FCFG1 and in the HW register. This spans TIVA_DDI0_OSC_LFOSCCTL + * simplified since the registers are packed together in the same order + * both in FCFG1 and in the HW register. This spans TIVA_DDI0_OSC_LFOSCCTL * bits[23:18] Using MASK8 write + 4 => writing to bits[23:16] */ @@ -383,22 +412,26 @@ void rom_setup_coldreset_from_shutdown_cfg2(uint32_t fcfg1_revision, /* Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit * fields in the TIVA_DDI0_OSC_RADCEXTCFG register in accordance to FCFG1 - * setting. Remaining register bit fields are set to their reset values of 0. */ + * setting. + * Remaining register bit fields are set to their reset values of 0. + */ trim = rom_setup_get_trim_radc_extcfg(fcfg1_revision); - rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, TIVA_DDI0_OSC_RADCEXTCFG_OFFSET, trim); + rom_ddi_write32(TIVA_AUX_DDI0_OSC_BASE, + TIVA_DDI0_OSC_RADCEXTCFG_OFFSET, trim); - /* Setting FORCE_KICKSTART_EN (ref. CC26_V1_BUG00261). Should also be done - * for PG2 (This is bit 22 in TIVA_DDI0_OSC_CTL0) */ + /* Setting FORCE_KICKSTART_EN (ref. CC26_V1_BUG00261). + * Should also be done for PG2 (This is bit 22 in TIVA_DDI0_OSC_CTL0) + */ putreg32(DDI0_OSC_CTL0_FORCE_KICKSTART_EN, TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET + TIVA_DDI0_OSC_CTL0_OFFSET); } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_coldreset_from_shutdown_cfg13 - ************************************************************************************/ + ****************************************************************************/ void rom_setup_coldreset_from_shutdown_cfg3(uint32_t ccfg_modeconf) { @@ -409,15 +442,18 @@ void rom_setup_coldreset_from_shutdown_cfg3(uint32_t ccfg_modeconf) uint32_t regval; uint8_t regval8; - /* Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz - * XOSC */ + /* Examine the XOSC_FREQ field to select + * 0x1=HPOSC, + * 0x2=48MHz XOSC, + * 0x3=24MHz XOSC + */ switch ((ccfg_modeconf & CCFG_MODE_CONF_1_XOSC_FREQ_MASK) >> CCFG_MODE_CONF_1_XOSC_FREQ_SHIFT) { case 2: - /* XOSC source is a 48 MHz crystal Do nothing (since this is the reset - * setting) + /* XOSC source is a 48 MHz crystal Do nothing + * (since this is the reset setting) */ break; @@ -431,8 +467,10 @@ void rom_setup_coldreset_from_shutdown_cfg3(uint32_t ccfg_modeconf) if ((fcfg1_oscconf & FCFG1_OSC_CONF_HPOSC_OPTION) == 0) { - /* This is a HPOSC chip, apply HPOSC settings Set bit - * DDI0_OSC_CTL0_HPOSC_MODE_EN (this is bit 14 in TIVA_DDI0_OSC_CTL0) */ + /* This is a HPOSC chip, + * apply HPOSC settings Set bit DDI0_OSC_CTL0_HPOSC_MODE_EN + * (this is bit 14 in TIVA_DDI0_OSC_CTL0) + */ putreg32(DDI0_OSC_CTL0_HPOSC_MODE_EN, TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET + @@ -450,7 +488,8 @@ void rom_setup_coldreset_from_shutdown_cfg3(uint32_t ccfg_modeconf) * ADI2_REFSYS_HPOSCCTL0_SERIES_CAP = * FCFG1_OSC_CONF_HPOSC_SERIES_CAP (2 bits) * ADI2_REFSYS_HPOSCCTL0_DIV3_BYPASS = - * FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit) */ + * FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit) + */ regval = ((getreg32(TIVA_ADI2_REFSYS_HPOSCCTL2) & ~(ADI2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN | @@ -502,11 +541,13 @@ void rom_setup_coldreset_from_shutdown_cfg3(uint32_t ccfg_modeconf) putreg32(regval, TIVA_ADI2_REFSYS_HPOSCCTL0); break; } + /* Not a HPOSC chip - fall through to default */ default: /* XOSC source is a 24 MHz crystal (default) Set bit - * DDI0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in TIVA_DDI0_OSC_CTL0) */ + * DDI0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in TIVA_DDI0_OSC_CTL0) + */ putreg32(DDI0_OSC_CTL0_XTAL_IS_24M, TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET + @@ -514,20 +555,24 @@ void rom_setup_coldreset_from_shutdown_cfg3(uint32_t ccfg_modeconf) break; } - /* Set XOSC_HF in bypass mode if CCFG is configured for external TCXO Please - * note that it is up to the customer to make sure that the external clock - * source is up and running before XOSC_HF can be used. */ + /* Set XOSC_HF in bypass mode if CCFG is configured for external TCXO + * Please note that it is up to the customer to make sure that the external + * clock source is up and running before XOSC_HF can be used. + */ if ((getreg32(TIVA_CCFG_SIZE_AND_DIS_FLAGS) & CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO) == 0) { putreg32(DDI0_OSC_XOSCHFCTL_BYPASS, - TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET + TIVA_DDI0_OSC_XOSCHFCTL_OFFSET); + TIVA_AUX_DDI0_OSC_BASE + + TIVA_DDI_SET_OFFSET + + TIVA_DDI0_OSC_XOSCHFCTL_OFFSET); } - /* Clear DDI0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). This is bit 9 - * in TIVA_DDI0_OSC_CTL0. This is typically already 0 except on Lizard where it - * is set in ROM-boot */ + /* Clear DDI0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). + * This is bit 9 in TIVA_DDI0_OSC_CTL0. + * This is typically already 0 except on Lizard where it is set in ROM-boot + */ putreg32(DDI0_OSC_CTL0_CLK_LOSS_EN, TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_CLR_OFFSET + @@ -547,36 +592,42 @@ void rom_setup_coldreset_from_shutdown_cfg3(uint32_t ccfg_modeconf) switch ((ccfg_modeconf & CCFG_MODE_CONF_1_SCLK_LF_OPTION_MASK) >> CCFG_MODE_CONF_1_SCLK_LF_OPTION_SHIFT) { - case 0: /* XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 - * Hz) */ + case 0: /* XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF + * (=31250Hz) */ rom_osc_set_clocksource(OSC_SRC_CLK_LF, OSC_XOSC_HF); - rom_setup_aonrtc_subsecinc(0x8637bd); /* RTC_INCREMENT = 2^38 / + rom_setup_aonrtc_subsecinc(0x8637bd); /* RTC_INCREMENT = 2^38 / * frequency */ break; - case 1: /* EXTERNAL signal -> SCLK_LF - * (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT) - * * Set SCLK_LF to use the same source as SCLK_HF - * * Can be simplified a bit since possible return - * values for HF matches LF settings */ + case 1: /* EXTERNAL signal -> SCLK_LF + * (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT) + * * Set SCLK_LF to use the same source as SCLK_HF + * * Can be simplified a bit since possible return + * values for HF matches LF settings + */ current_hfclock = rom_osc_get_clocksource(OSC_SRC_CLK_HF); rom_osc_set_clocksource(OSC_SRC_CLK_LF, current_hfclock); while (rom_osc_get_clocksource(OSC_SRC_CLK_LF) != current_hfclock) { /* Wait until switched */ - } + ccfg_extlfclk = getreg32(TIVA_CCFG_EXT_LF_CLK); - rom_setup_aonrtc_subsecinc((ccfg_extlfclk & CCFG_EXT_LF_CLK_RTC_INCREMENT_MASK) - >> CCFG_EXT_LF_CLK_RTC_INCREMENT_SHIFT); + rom_setup_aonrtc_subsecinc((ccfg_extlfclk & + CCFG_EXT_LF_CLK_RTC_INCREMENT_MASK) >> + CCFG_EXT_LF_CLK_RTC_INCREMENT_SHIFT); /* Route external clock to AON IOC w/hysteresis. Set XOSC_LF in * bypass mode to allow external 32 kHz clock */ - rom_iocport_set_configuration((ccfg_extlfclk & CCFG_EXT_LF_CLK_DIO_MASK) >> CCFG_EXT_LF_CLK_DIO_SHIFT, IOC_PORT_AON_CLK32K, IOC_STD_INPUT | IOC_HYST_ENABLE); + rom_iocport_set_configuration((ccfg_extlfclk & + CCFG_EXT_LF_CLK_DIO_MASK) >> + CCFG_EXT_LF_CLK_DIO_SHIFT, + IOC_PORT_AON_CLK32K, + IOC_STD_INPUT | IOC_HYST_ENABLE); putreg32(DDI0_OSC_CTL0_XOSC_LF_DIG_BYPASS, TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET + @@ -597,8 +648,8 @@ void rom_setup_coldreset_from_shutdown_cfg3(uint32_t ccfg_modeconf) /* Update ADI4_AUX_ADCREF1_VTRIM with value from FCFG1 */ regval8 = (((getreg32(TIVA_FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT) >> - FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_SHIFT) - << ADI4_AUX_ADCREF1_VTRIM_SHIFT) & ADI4_AUX_ADCREF1_VTRIM_MASK); + FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_SHIFT) + << ADI4_AUX_ADCREF1_VTRIM_SHIFT) & ADI4_AUX_ADCREF1_VTRIM_MASK); putreg8(regval8, TIVA_ADI4_AUX_ADCREF1); /* Sync with AON */ @@ -606,9 +657,9 @@ void rom_setup_coldreset_from_shutdown_cfg3(uint32_t ccfg_modeconf) SysCtrlAonSync(); } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_get_trim_anabypass_value1 - ************************************************************************************/ + ****************************************************************************/ uint32_t rom_setup_get_trim_anabypass_value1(uint32_t ccfg_modeconf) { @@ -617,9 +668,10 @@ uint32_t rom_setup_get_trim_anabypass_value1(uint32_t ccfg_modeconf) uint32_t xosc_hf_col; uint32_t trimval; - /* Use device specific trim values located in factory configuration area for - * the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in the - * ANABYPASS_VALUE1 register. Value for the other bit fields are set to 0. */ + /* Use device specific trim values located in factory configuration area + * for the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in the + * ANABYPASS_VALUE1 register. Value for the other bit fields are set to 0. + */ fcfg1val = getreg32(TIVA_FCFG1_CONFIG_OSC_TOP); xosc_hf_row = ((fcfg1val & @@ -633,36 +685,38 @@ uint32_t rom_setup_get_trim_anabypass_value1(uint32_t ccfg_modeconf) { /* XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply * compensation XOSC_CAPARRAY_DELTA is located in bit[15:8] of - * ccfg_modeconf Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is - * not given by a define and sign extension must therefore be hard coded. - * ( A small test program is created verifying the code lines below: Ref.: - * ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c) */ + * ccfg_modeconf Note: HW_REV_DEPENDENT_IMPLEMENTATION. + * Field width is not given by a define and sign extension must + * therefore be hard coded.( A small test program is created + * verifying the code lines below: Ref.: + * ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c) + */ int32_t customer_delta_adjust = (((int32_t) (ccfg_modeconf << (32 - CCFG_MODE_CONF_1_XOSC_CAPARRAY_DELTA_WIDTH - - CCFG_MODE_CONF_1_XOSC_CAPARRAY_DELTA_SHIFT))) >> (32 - - CCFG_MODE_CONF_1_XOSC_CAPARRAY_DELTA_WIDTH)); + CCFG_MODE_CONF_1_XOSC_CAPARRAY_DELTA_SHIFT))) >> + (32 - CCFG_MODE_CONF_1_XOSC_CAPARRAY_DELTA_WIDTH)); while (customer_delta_adjust < 0) { xosc_hf_col >>= 1; /* COL 1 step down */ + /* if COL below minimum */ + if (xosc_hf_col == 0) - { /* if COL below minimum */ - + { xosc_hf_col = 0xffff; /* Set COL to maximum */ - xosc_hf_row >>= 1; /* ROW 1 step down */ - if (xosc_hf_row == 0) - { /* if ROW below minimum */ + /* if ROW below minimum */ + if (xosc_hf_row == 0) + { xosc_hf_row = 1; /* Set both ROW and COL */ xosc_hf_col = 1; /* to minimum */ - } } @@ -673,22 +727,24 @@ uint32_t rom_setup_get_trim_anabypass_value1(uint32_t ccfg_modeconf) { xosc_hf_col = (xosc_hf_col << 1) | 1; /* COL 1 step up */ - if (xosc_hf_col > 0xffff) - { /* if COL above maximum */ + /* if COL above maximum */ + if (xosc_hf_col > 0xffff) + { xosc_hf_col = 1; /* Set COL to minimum */ xosc_hf_row = (xosc_hf_row << 1) | 1; /* ROW 1 step up */ - if (xosc_hf_row > 0xf) - { /* if ROW above maximum */ + /* if ROW above maximum */ + if (xosc_hf_row > 0xf) + { xosc_hf_row = 0xf; /* Set both ROW and COL */ xosc_hf_col = 0xffff; /* to maximum */ - } } + customer_delta_adjust--; } } @@ -700,9 +756,9 @@ uint32_t rom_setup_get_trim_anabypass_value1(uint32_t ccfg_modeconf) return trimval; } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_get_trim_rcosc_lfrtunectuntrim - ************************************************************************************/ + ****************************************************************************/ uint32_t rom_setup_get_trim_rcosc_lfrtunectuntrim(void) { @@ -725,9 +781,9 @@ uint32_t rom_setup_get_trim_rcosc_lfrtunectuntrim(void) return trimval; } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_get_trim_xosc_hfibiastherm - ************************************************************************************/ + ****************************************************************************/ uint32_t rom_setup_get_trim_xosc_hfibiastherm(void) { @@ -743,18 +799,19 @@ uint32_t rom_setup_get_trim_xosc_hfibiastherm(void) return trimval; } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_get_trim_ampcompth2 - ************************************************************************************/ + ****************************************************************************/ uint32_t rom_setup_get_trim_ampcompth2(void) { uint32_t trimval; uint32_t fcfg1val; - /* Use device specific trim value located in factory configuration area. All - * defined register bit fields have corresponding trim value in the factory - * configuration area */ + /* Use device specific trim value located in factory configuration area. + * All defined register bit fields have corresponding trim value in the + * factory configuration area + */ fcfg1val = getreg32(TIVA_FCFG1_AMPCOMP_TH2); trimval = ((fcfg1val & @@ -777,18 +834,19 @@ uint32_t rom_setup_get_trim_ampcompth2(void) return trimval; } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_get_trim_ampcompth1 - ************************************************************************************/ + ****************************************************************************/ uint32_t rom_setup_get_trim_ampcompth1(void) { uint32_t trimval; uint32_t fcfg1val; - /* Use device specific trim values located in factory configuration area. All - * defined register bit fields have a corresponding trim value in the factory - * configuration area */ + /* Use device specific trim values located in factory configuration area. + * All defined register bit fields have a corresponding trim value in the + * factory configuration area + */ fcfg1val = getreg32(TIVA_FCFG1_AMPCOMP_TH1); trimval = (((fcfg1val & @@ -811,9 +869,9 @@ uint32_t rom_setup_get_trim_ampcompth1(void) return trimval; } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_get_trim_ampcompctrl - ************************************************************************************/ + ****************************************************************************/ uint32_t rom_setup_get_trim_ampcompctrl(uint32_t fcfg1_revision) { @@ -825,8 +883,9 @@ uint32_t rom_setup_get_trim_ampcompctrl(uint32_t fcfg1_revision) int32_t delta_adjust; /* Use device specific trim values located in factory configuration area. - * Register bit fields without trim values in the factory configuration area - * will be set to the value of 0. */ + * Register bit fields without trim values in the factory configuration + * area will be set to the value of 0. + */ fcfg1val = getreg32(TIVA_FCFG1_AMPCOMP_CTRL1); @@ -840,12 +899,15 @@ uint32_t rom_setup_get_trim_ampcompctrl(uint32_t fcfg1_revision) if ((getreg32(TIVA_CCFG_SIZE_AND_DIS_FLAGS) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR) == 0) { - /* Adjust with TIVA_DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG */ + /* Adjust with TIVA_DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT + * from CCFG + */ mode_conf1 = getreg32(TIVA_CCFG_MODE_CONF_1); - /* Both fields are signed 4-bit values. This is an assumption when doing - * the sign extension. */ + /* Both fields are signed 4-bit values. This is an assumption + * when doing the sign extension. + */ delta_adjust = (((int32_t) @@ -858,6 +920,7 @@ uint32_t rom_setup_get_trim_ampcompctrl(uint32_t fcfg1_revision) { delta_adjust = 0; } + if (delta_adjust > (DDI0_OSC_AMPCOMPCTL_IBIAS_OFFSET_MASK >> DDI0_OSC_AMPCOMPCTL_IBIAS_OFFSET_SHIFT)) @@ -866,19 +929,21 @@ uint32_t rom_setup_get_trim_ampcompctrl(uint32_t fcfg1_revision) (DDI0_OSC_AMPCOMPCTL_IBIAS_OFFSET_MASK >> DDI0_OSC_AMPCOMPCTL_IBIAS_OFFSET_SHIFT); } + ibias_offset = (uint32_t) delta_adjust; delta_adjust = (((int32_t) (mode_conf1 << (32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_WIDTH - - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_SHIFT))) >> (32 - - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_WIDTH)); + CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_SHIFT))) >> + (32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_WIDTH)); delta_adjust += (int32_t)ibias_init; if (delta_adjust < 0) { delta_adjust = 0; } + if (delta_adjust > (DDI0_OSC_AMPCOMPCTL_IBIAS_INIT_MASK >> DDI0_OSC_AMPCOMPCTL_IBIAS_INIT_SHIFT)) @@ -887,6 +952,7 @@ uint32_t rom_setup_get_trim_ampcompctrl(uint32_t fcfg1_revision) (DDI0_OSC_AMPCOMPCTL_IBIAS_INIT_MASK >> DDI0_OSC_AMPCOMPCTL_IBIAS_INIT_SHIFT); } + ibias_init = (uint32_t) delta_adjust; } @@ -921,11 +987,12 @@ uint32_t rom_setup_get_trim_ampcompctrl(uint32_t fcfg1_revision) return trimval; } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_get_trim_dblrloopfilter_resetvoltage - ************************************************************************************/ + ****************************************************************************/ -uint32_t rom_setup_get_trim_dblrloopfilter_resetvoltage(uint32_t fcfg1_revision) +uint32_t +rom_setup_get_trim_dblrloopfilter_resetvoltage(uint32_t fcfg1_revision) { uint32_t dblrLoopFilterResetVoltageValue = 0; /* Reset value */ @@ -940,9 +1007,9 @@ uint32_t rom_setup_get_trim_dblrloopfilter_resetvoltage(uint32_t fcfg1_revision) return (dblrLoopFilterResetVoltageValue); } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_get_trim_adcshmodeen - ************************************************************************************/ + ****************************************************************************/ uint32_t rom_setup_get_trim_adcshmodeen(uint32_t fcfg1_revision) { @@ -950,7 +1017,8 @@ uint32_t rom_setup_get_trim_adcshmodeen(uint32_t fcfg1_revision) if (fcfg1_revision >= 0x00000022) { - if ((getreg32(TIVA_FCFG1_OSC_CONF) & FCFG1_OSC_CONF_ADC_SH_MODE_EN) == 0) + if ((getreg32(TIVA_FCFG1_OSC_CONF) & + FCFG1_OSC_CONF_ADC_SH_MODE_EN) == 0) { fcfg1_adcsh_modeen = 0; } @@ -959,9 +1027,9 @@ uint32_t rom_setup_get_trim_adcshmodeen(uint32_t fcfg1_revision) return fcfg1_adcsh_modeen; } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_get_trim_adcshvbufen - ************************************************************************************/ + ****************************************************************************/ uint32_t rom_setup_get_trim_adcshvbufen(uint32_t fcfg1_revision) { @@ -969,7 +1037,8 @@ uint32_t rom_setup_get_trim_adcshvbufen(uint32_t fcfg1_revision) if (fcfg1_revision >= 0x00000022) { - if ((getreg32(TIVA_FCFG1_OSC_CONF) & FCFG1_OSC_CONF_ADC_SH_VBUF_EN) == 0) + if ((getreg32(TIVA_FCFG1_OSC_CONF) & + FCFG1_OSC_CONF_ADC_SH_VBUF_EN) == 0) { trim_adcshvbufen = 0; } @@ -978,9 +1047,9 @@ uint32_t rom_setup_get_trim_adcshvbufen(uint32_t fcfg1_revision) return trim_adcshvbufen; } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_get_trim_xosc_hfctrl - ************************************************************************************/ + ****************************************************************************/ uint32_t rom_setup_get_trim_xosc_hfctrl(uint32_t fcfg1_revision) { @@ -1010,9 +1079,9 @@ uint32_t rom_setup_get_trim_xosc_hfctrl(uint32_t fcfg1_revision) return (getTrimForXoschfCtlValue); } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_get_trim_xosc_hffaststart - ************************************************************************************/ + ****************************************************************************/ uint32_t rom_setup_get_trim_xosc_hffaststart(void) { @@ -1027,9 +1096,9 @@ uint32_t rom_setup_get_trim_xosc_hffaststart(void) return (ui32XoscHfFastStartValue); } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_get_trim_radc_extcfg - ************************************************************************************/ + ****************************************************************************/ uint32_t rom_setup_get_trim_radc_extcfg(uint32_t fcfg1_revision) { @@ -1060,9 +1129,9 @@ uint32_t rom_setup_get_trim_radc_extcfg(uint32_t fcfg1_revision) return (getTrimForRadcExtCfgValue); } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_get_trim_rcosc_lfibiastrim - ************************************************************************************/ + ****************************************************************************/ uint32_t rom_setup_get_trim_rcosc_lfibiastrim(uint32_t fcfg1_revision) { @@ -1070,7 +1139,8 @@ uint32_t rom_setup_get_trim_rcosc_lfibiastrim(uint32_t fcfg1_revision) if (fcfg1_revision >= 0x00000022) { - if ((getreg32(TIVA_FCFG1_OSC_CONF) & FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM) != 0) + if ((getreg32(TIVA_FCFG1_OSC_CONF) & + FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM) != 0) { trim_rcosc_lfibaistrim = 1; } @@ -1079,11 +1149,12 @@ uint32_t rom_setup_get_trim_rcosc_lfibiastrim(uint32_t fcfg1_revision) return trim_rcosc_lfibaistrim; } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_get_trim_lfregulator_cmirrwr_ratio - ************************************************************************************/ + ****************************************************************************/ -uint32_t rom_setup_get_trim_lfregulator_cmirrwr_ratio(uint32_t fcfg1_revision) +uint32_t +rom_setup_get_trim_lfregulator_cmirrwr_ratio(uint32_t fcfg1_revision) { /* Default value for both fields */ @@ -1101,18 +1172,18 @@ uint32_t rom_setup_get_trim_lfregulator_cmirrwr_ratio(uint32_t fcfg1_revision) return (trimForXoscLfRegulatorAndCmirrwrRatioValue); } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_cachemode - ************************************************************************************/ + ****************************************************************************/ void rom_setup_cachemode(void) { - /* - Make sure to enable aggressive VIMS clock gating for power optimization + /* Make sure to enable aggressive VIMS clock gating for power optimization * Only for PG2 devices. - Enable cache prefetch enable as default setting * (Slightly higher power consumption, but higher CPU performance) - IF ( - * CCFG_..._DIS_GPRAM == 1 ) then: Enable cache (set cache mode = 1), even if - * set by ROM boot code (This is done because it's not set by boot code when - * running inside a debugger supporting the Halt In Boot (HIB) + * CCFG_..._DIS_GPRAM == 1 ) then: Enable cache (set cache mode = 1), even + * if set by ROM boot code (This is done because it's not set by boot code + * when running inside a debugger supporting the Halt In Boot (HIB) * functionality). else: Set MODE_GPRAM if not already set (see inline * comments as well) */ @@ -1143,15 +1214,16 @@ void rom_setup_cachemode(void) VIMS_STAT_MODE_GPRAM) { /* GPRAM is enabled in CCFG but not selected Note: It is recommended to - * go via MODE_OFF when switching to MODE_GPRAM */ + * go via MODE_OFF when switching to MODE_GPRAM + */ putreg32((vims_ctlmode0 | VIMS_CTL_MODE_OFF), TIVA_VIMS_CTL); while ((getreg32(TIVA_VIMS_STAT) & VIMS_STAT_MODE_MASK) != VIMS_STAT_MODE_OFF) { /* Do nothing - wait for an eventual mode change to complete (This - * goes fast). */ - + * goes fast). + */ } putreg32(vims_ctlmode0, TIVA_VIMS_CTL); @@ -1164,17 +1236,19 @@ void rom_setup_cachemode(void) } } -/************************************************************************************ +/**************************************************************************** * Name: rom_setup_aonrtc_subsecinc - ************************************************************************************/ + ****************************************************************************/ void rom_setup_aonrtc_subsecinc(uint32_t subsecinc) { - /* Loading a new RTCSUBSECINC value is done in 5 steps: 1. Write bit[15:0] of - * new SUBSECINC value to TIVA_AUX_WUC_RTCSUBSECINC0 2. Write bit[23:16] of new - * SUBSECINC value to TIVA_AUX_WUC_RTCSUBSECINC1 3. Set - * AUX_WUC_RTCSUBSECINCCTL_UPD_REQ 4. Wait for - * AUX_WUC_RTCSUBSECINCCTL_UPD_ACK 5. Clear AUX_WUC_RTCSUBSECINCCTL_UPD_REQ */ + /* Loading a new RTCSUBSECINC value is done in 5 steps: + * 1. Write bit[15:0] of new SUBSECINC value to TIVA_AUX_WUC_RTCSUBSECINC0 + * 2. Write bit[23:16] of new SUBSECINC value to TIVA_AUX_WUC_RTCSUBSECINC1 + * 3. Set AUX_WUC_RTCSUBSECINCCTL_UPD_REQ + * 4. Wait forAUX_WUC_RTCSUBSECINCCTL_UPD_ACK + * 5. Clear AUX_WUC_RTCSUBSECINCCTL_UPD_REQ + */ putreg32(((subsecinc) & AUX_WUC_RTCSUBSECINC0_INC15_0_MASK), TIVA_AUX_WUC_RTCSUBSECINC0); @@ -1182,7 +1256,8 @@ void rom_setup_aonrtc_subsecinc(uint32_t subsecinc) TIVA_AUX_WUC_RTCSUBSECINC1); putreg32(AUX_WUC_RTCSUBSECINCCTL_UPD_REQ, TIVA_AUX_WUC_RTCSUBSECINCCTL); - while ((getreg32(TIVA_AUX_WUC_RTCSUBSECINCCTL) & AUX_WUC_RTCSUBSECINCCTL_UPD_ACK) == 0) + while ((getreg32(TIVA_AUX_WUC_RTCSUBSECINCCTL) & + AUX_WUC_RTCSUBSECINCCTL_UPD_ACK) == 0) { } diff --git a/arch/arm/src/tiva/cc13xx/cc13x0_rom.h b/arch/arm/src/tiva/cc13xx/cc13x0_rom.h index b75853b54e4..2b5bf851e72 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x0_rom.h +++ b/arch/arm/src/tiva/cc13xx/cc13x0_rom.h @@ -1,10 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/cc13xx/cc13x0_rom.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * This is a port of TI's setup_rom.h file which has a fully compatible BSD license: + * This is a port of TI's setup_rom.h file which has a fully compatible + * BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,26 +37,26 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13X0_ROM_H #define __ARCH_ARM_SRC_TIVA_CC13XX_CC13X0_ROM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include "hardware/tiva_aux_smph.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Start address of the ROM hard API access table (located after the ROM FW rev - * field) +/* Start address of the ROM hard API access table + * (located after the ROM FW rev field) */ #define ROM_HAPI_TABLE_ADDR 0x10000048 @@ -605,9 +606,9 @@ #define AUX_WUC_POWER_DOWN 0x00000002 #define AUX_WUC_POWER_ACTIVE 0x00000004 -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* ROM Hard-API function interface types */ @@ -659,7 +660,9 @@ typedef void (*fptr_adccompbin_t) (uint8_t /* signal */); typedef void (*fptr_compbref_t) (uint8_t /* signal */); -/* Types used in the "Safe" interfaces taken from the TI DriverLib hw_types.h */ +/* Types used in the "Safe" interfaces taken from the TI DriverLib + * hw_types.h + */ typedef void (*fptr_void_void_t) (void); typedef void (*fptr_void_uint8_t) (uint8_t); @@ -691,9 +694,9 @@ struct hard_api_s typedef struct hard_api_s hard_api_t; -/************************************************************************************ +/**************************************************************************** * Global Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /* ROM functions implemented in FLASH */ @@ -708,26 +711,29 @@ uint32_t rom_setup_get_trim_xosc_hfibiastherm(void); uint32_t rom_setup_get_trim_ampcompth1(void); uint32_t rom_setup_get_trim_ampcompth2(void); uint32_t rom_setup_get_trim_ampcompctrl(uint32_t fcfg1_revision); -uint32_t rom_setup_get_trim_dblrloopfilter_resetvoltage(uint32_t fcfg1_revision); +uint32_t +rom_setup_get_trim_dblrloopfilter_resetvoltage(uint32_t fcfg1_revision); uint32_t rom_setup_get_trim_adcshmodeen(uint32_t fcfg1_revision); uint32_t rom_setup_get_trim_adcshvbufen(uint32_t fcfg1_revision); uint32_t rom_setup_get_trim_xosc_hfctrl(uint32_t fcfg1_revision); uint32_t rom_setup_get_trim_xosc_hffaststart(void); uint32_t rom_setup_get_trim_radc_extcfg(uint32_t fcfg1_revision); uint32_t rom_setup_get_trim_rcosc_lfibiastrim(uint32_t fcfg1_revision); -uint32_t rom_setup_get_trim_lfregulator_cmirrwr_ratio(uint32_t fcfg1_revision); +uint32_t +rom_setup_get_trim_lfregulator_cmirrwr_ratio(uint32_t fcfg1_revision); void rom_setup_cachemode(void); void rom_setup_aonrtc_subsecinc(uint32_t subsecinc); -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: rom_signextend_vddrtrim * * Description: - * Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21) + * Sign extend the VDDR_TRIM setting + * (special format ranging from -10 to +21) * * Input Parameters * vddrtrim - VDDR_TRIM setting @@ -735,7 +741,7 @@ void rom_setup_aonrtc_subsecinc(uint32_t subsecinc); * Returned Value: * Returns sign extended VDDR_TRIM setting. * - ************************************************************************************/ + ****************************************************************************/ static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim) { @@ -752,7 +758,7 @@ static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim) return signed_vaddrtrim; } -/************************************************************************************ +/**************************************************************************** * Name: rom_hapi_void and rom_hapi_auxadiselect * * Description: @@ -765,7 +771,7 @@ static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ inline static void rom_hapi_void(fptr_void_void_t fptr) { @@ -779,7 +785,8 @@ inline static void rom_hapi_void(fptr_void_void_t fptr) leave_critical_section(flags); } -inline static void rom_hapi_auxadiselect(fptr_void_uint8_t fptr, uint8_t signal) +inline static void rom_hapi_auxadiselect(fptr_void_uint8_t fptr, + uint8_t signal) { irqstate_t flags = enter_critical_section(); while (getreg32(TIVA_AUX_SMPH_SMPH0) == 0) diff --git a/arch/arm/src/tiva/cc13xx/cc13x0_trim.c b/arch/arm/src/tiva/cc13xx/cc13x0_trim.c index 94999a76345..a2fd19525e1 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x0_trim.c +++ b/arch/arm/src/tiva/cc13xx/cc13x0_trim.c @@ -10,37 +10,38 @@ * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: * - * 1) Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. * - * 2) Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. + * 2) Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3) Neither the name NuttX nor the names of its contributors may be used to - * endorse or promote products derived from this software without specific - * prior written permission. + * 3) Neither the name NuttX nor the names of its contributors may be used to + * endorse or promote products derived from this software without specific + * prior written permission. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ******************************************************************************/ + ****************************************************************************/ -/****************************************************************************** +/**************************************************************************** * Included Files - ******************************************************************************/ + ****************************************************************************/ #include @@ -59,11 +60,11 @@ #include "cc13xx/cc13x0_rom.h" -/****************************************************************************** +/**************************************************************************** * Private Functions - ******************************************************************************/ + ****************************************************************************/ -/****************************************************************************** +/**************************************************************************** * Name: trim_wakeup_frompowerdown * * Description: @@ -73,14 +74,14 @@ * Returned Value: * None * - ******************************************************************************/ + ****************************************************************************/ static void trim_wakeup_frompowerdown(void) { /* Currently no specific trim for Powerdown */ } -/****************************************************************************** +/**************************************************************************** * Name: trim_wakeup_fromshutdown * * Description: @@ -93,7 +94,7 @@ static void trim_wakeup_frompowerdown(void) * Returned Value: * None * - ******************************************************************************/ + ****************************************************************************/ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) { @@ -126,14 +127,16 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) { /* ADI3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19] * (=ALT_DCDC_DITHER_EN) ADI3_REFSYS:DCDCCTL5[2:0](=IPEAK ) = - * CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) Using a single 4-bit masked - * write since layout is equal for both source and destination + * CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) + * Using a single 4-bit masked write since layout is equal for + * both source and destination */ regval = getreg32(TIVA_CCFG_MODE_CONF_1); regval = (0xf0 | (regval >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_SHIFT)); putreg8((uint8_t)regval, - TIVA_ADI3_REFSYS_MASK4B + (TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET * 2)); + TIVA_ADI3_REFSYS_MASK4B + + (TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET * 2)); } /* Enable for JTAG to be powered down. The JTAG domain is automatically @@ -167,7 +170,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) rom_setup_coldreset_from_shutdown_cfg2(fcfg1_revision, ccfg_modeconf); /* Increased margin between digital supply voltage and VDD BOD during - * standby. VTRIM_UDIG: signed 4 bits value to be incremented by 2 (max = 7) + * standby. + * VTRIM_UDIG: signed 4 bits value to be incremented by 2 (max = 7) * VTRIM_BOD: unsigned 4 bits value to be decremented by 1 (min = 0) This * applies to chips with mp1rev < 542 for cc13x0 and for mp1rev < 527 for * cc26x0 @@ -239,7 +243,7 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) putreg32(regval, TIVA_FLASH_CFG); } -/****************************************************************************** +/**************************************************************************** * Name: trim_coldreset * * Description: @@ -248,28 +252,28 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) * Returned Value: * None * - ******************************************************************************/ + ****************************************************************************/ static void trim_coldreset(void) { /* Currently no specific trim for Cold Reset */ } -/****************************************************************************** +/**************************************************************************** * Public Functions - ******************************************************************************/ + ****************************************************************************/ -/****************************************************************************** +/**************************************************************************** * Name: cc13xx_trim_device * * Description: * Perform the necessary trim of the device which is not done in boot code * * This function should only execute coming from ROM boot. The current - * implementation does not take soft reset into account. However, it does no - * damage to execute it again. It only consumes time. + * implementation does not take soft reset into account. However, it does + * no damage to execute it again. It only consumes time. * - ******************************************************************************/ + ****************************************************************************/ void cc13xx_trim_device(void) { @@ -303,11 +307,11 @@ void cc13xx_trim_device(void) putreg32(AUX_WUC_MODCLKEN1_SMPH, TIVA_AUX_WUC_MODCLKEN1); - /* Warm resets on CC13x0 and CC26x0 complicates software design because much - * of our software expect that initialization is done from a full system - * reset. This includes RTC setup, oscillator configuration and AUX setup. To - * ensure a full reset of the device is done when customers get e.g. a - * Watchdog reset, the following is set here: + /* Warm resets on CC13x0 and CC26x0 complicates software design because + * much of our software expect that initialization is done from a full + * system reset. This includes RTC setup, oscillator configuration and + * AUX setup. To ensure a full reset of the device is done when customers + * get e.g. a Watchdog reset, the following is set here: */ regval = getreg32(TIVA_PRCM_WARMRESET); @@ -338,11 +342,11 @@ void cc13xx_trim_device(void) trim_wakeup_frompowerdown(); } - /* Check for shutdown. When device is going to shutdown the hardware will - * automatically clear the SLEEPDIS bit in the SLEEP register in the - * AON_SYSCTL module. It is left for the application to assert this bit when - * waking back up, but not before the desired IO configuration has been - * re-established. + /* Check for shutdown. + * When device is going to shutdown the hardware will automatically clear + * the SLEEPDIS bit in the SLEEP register in the AON_SYSCTL module. + * It is left for the application to assert this bit when waking back + * up, but not before the desired IO configuration has been re-established. */ else if ((getreg32(TIVA_AON_SYSCTL_SLEEPCTL) & @@ -358,8 +362,8 @@ void cc13xx_trim_device(void) } else { - /* Consider adding a check for soft reset to allow debugging to skip this - * section!!! NB. This should be calling a ROM implementation of + /* Consider adding a check for soft reset to allow debugging to skip + * this section!!! NB. This should be calling a ROM implementation of * required trim and compensation e.g. trim_coldreset() --> * trim_wakeup_fromshutdown() --> trim_wakeup_frompowerdown() */ @@ -375,8 +379,8 @@ void cc13xx_trim_device(void) putreg32(0, TIVA_PRCM_PDCTL1VIMS); - /* Configure optimal wait time for flash FSM in cases where flash pump wakes - * up from sleep + /* Configure optimal wait time for flash FSM in cases where flash pump + * wakes up from sleep */ regval = getreg32(TIVA_FLASH_FPAC1); @@ -385,8 +389,8 @@ void cc13xx_trim_device(void) putreg32(regval, TIVA_FLASH_FPAC1); /* And finally at the end of the flash boot process: SET BOOT_DET bits in - * AON_SYSCTL to 3 if already found to be 1 Note: The BOOT_DET_x_CLR/SET bits - * must be manually cleared + * AON_SYSCTL to 3 if already found to be 1 Note: The BOOT_DET_x_CLR/SET + * bits must be manually cleared */ if ((getreg32(TIVA_AON_SYSCTL_RESETCTL) & diff --git a/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.c b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.c index 44ecd884dd7..e7b4c7499f9 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.c +++ b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.c @@ -91,7 +91,7 @@ void rom_setup_stepvaddrtrimto(uint32_t tocode) putreg32(pmctl_regsetctrl & ~AON_PMCTL_RESETCTL_VDDR_LOSS_EN, TIVA_AON_PMCTL_RESETCTL); - /* Wait for VDDR_LOSS_EN setting to propagate */ + /* Wait for VDDR_LOSS_EN setting to propagate */ getreg32(TIVA_AON_RTC_SYNC); } @@ -135,7 +135,7 @@ void rom_setup_stepvaddrtrimto(uint32_t tocode) putreg32(pmctl_regsetctrl, TIVA_AON_PMCTL_RESETCTL); - /* And finally wait for VDDR_LOSS_EN setting to propagate */ + /* And finally wait for VDDR_LOSS_EN setting to propagate */ getreg32(TIVA_AON_RTC_SYNC); } @@ -160,8 +160,8 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf) { /* Set VDDS_BOD trim - using masked write {MASK8:DATA8} - TRIM_VDDS_BOD * is bits[7:3] of ADI3..REFSYSCTL1 - Needs a positive transition on - * BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to latch new VDDS BOD. Set to 0 - * first to guarantee a positive transition. + * BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to latch new VDDS BOD. + * Set to 0 first to guarantee a positive transition. */ putreg8(ADI3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN, @@ -219,8 +219,8 @@ void rom_setup_coldreset_from_shutdown_cfg1(uint32_t ccfg_modeconf) setbits |= AON_PMCTL_PWRCTL_DCDC_EN; } - /* Set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE Note: Inverse - * polarity + /* Set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE + * Note: Inverse polarity */ if ((ccfg_modeconf & CCFG_MODE_CONF_DCDC_ACTIVE) != 0) diff --git a/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h index 8e59060fbaa..81eb3617c9f 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h +++ b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h @@ -1,10 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v1_rom.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * This is a port of TI's rom.h file which has a fully compatible BSD license: + * This is a port of TI's rom.h file which has a fully compatible + * BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,17 +37,17 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_CC26X2_V1_ROM_H #define __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_CC26X2_V1_ROM_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Start address of the ROM hard API access table (located after the ROM FW rev - * field) +/* Start address of the ROM hard API access table (located after the ROM FW + * rev field) */ #define ROM_HAPI_TABLE_ADDR 0x10000048 @@ -812,9 +813,9 @@ ((void (*)(uint32_t powerconfig)) \ ROM_API_PWR_CTRL_TABLE[0]) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* ROM Hard-API function interface types */ @@ -830,8 +831,8 @@ typedef uint32_t (*fptr_reserved1_t) (uint32_t); typedef uint32_t (*fptr_reserved2_t) (void); -typedef uint32_t (*fptr_reserved3_t) (uint8_t *,\ - uint32_t,\ +typedef uint32_t (*fptr_reserved3_t) (uint8_t *, \ + uint32_t, \ uint32_t); typedef void (*fptr_resetdev_t) (void); @@ -893,15 +894,16 @@ struct hard_api_s typedef struct hard_api_s hard_api_t; -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: rom_signextend_vddrtrim * * Description: - * Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21) + * Sign extend the VDDR_TRIM setting + * (special format ranging from -10 to +21) * * Input Parameters * vddrtrim - VDDR_TRIM setting @@ -909,7 +911,7 @@ typedef struct hard_api_s hard_api_t; * Returned Value: * Returns sign extended VDDR_TRIM setting. * - ************************************************************************************/ + ****************************************************************************/ static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim) { @@ -926,9 +928,9 @@ static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim) return signed_vaddrtrim; } -/************************************************************************************ +/**************************************************************************** * Global Function Prototypes - ************************************************************************************/ + ****************************************************************************/ /* ROM functions implemented in FLASH */ diff --git a/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h index 5f23978552d..5998e77835b 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h +++ b/arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h @@ -1,10 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/cc13xx/cc13x2_cc26x2_v2_rom.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * This is a port of TI's rom.h file which has a fully compatible BSD license: + * This is a port of TI's rom.h file which has a fully compatible BSD + * license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,17 +37,17 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_CC26X2_V2_ROM_H #define __ARCH_ARM_SRC_TIVA_CC13XX_CC13X2_CC26X2_V2_ROM_H -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Start address of the ROM hard API access table (located after the ROM FW rev - * field) +/* Start address of the ROM hard API access table + * (located after the ROM FW rev field) */ #define ROM_HAPI_TABLE_ADDR 0x10000048 @@ -968,9 +969,9 @@ ((uint32_t (*)(uint32_t irqFlags)) \ ROM_API_SHA2_TABLE[5]) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ /* ROM Hard-API function interface types */ @@ -1049,15 +1050,16 @@ struct hard_api_s typedef struct hard_api_s hard_api_t; -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: rom_signextend_vddrtrim * * Description: - * Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21) + * Sign extend the VDDR_TRIM setting + * (special format ranging from -10 to +21) * * Input Parameters * vddrtrim - VDDR_TRIM setting @@ -1065,7 +1067,7 @@ typedef struct hard_api_s hard_api_t; * Returned Value: * Returns sign extended VDDR_TRIM setting. * - ************************************************************************************/ + ****************************************************************************/ static inline int32_t rom_signextend_vddrtrim(uint32_t vddrtrim) { diff --git a/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c b/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c index 633c18add2b..c3bd1af8cce 100644 --- a/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c +++ b/arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c @@ -25,17 +25,17 @@ * to endorse or promote products derived from this software without * specific prior written permission. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************/ @@ -224,8 +224,9 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) { /* ADI3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19] * (=ALT_DCDC_DITHER_EN) ADI3_REFSYS:DCDCCTL5[2:0](=IPEAK ) = - * CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) Using a single 4-bit masked - * write since layout is equal for both source and destination + * CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) Using a single 4-bit + * masked write since layout is equal for both source and + * destination */ regval = getreg32(TIVA_CCFG_MODE_CONF_1); @@ -237,8 +238,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) /* TBD - Temporarily removed for CC13x2 / CC26x2 */ - /* Force DCDC to use RCOSC before starting up XOSC. Clock loss detector does - * not use XOSC until SCLK_HF actually switches and thus DCDC is not + /* Force DCDC to use RCOSC before starting up XOSC. Clock loss detector + * does not use XOSC until SCLK_HF actually switches and thus DCDC is not * protected from clock loss on XOSC in that time frame. The force must be * released when the switch to XOSC has happened. This is done in * OSCHfSourceSwitch(). @@ -292,7 +293,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) (((fusedata & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_MASK) >> FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_SHIFT) << ADI2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT)); - putreg8(regval8, TIVA_ADI2_REFSYS_DIR + TIVA_ADI2_REFSYS_SOCLDOCTL1_OFFSET); + putreg8(regval8, + TIVA_ADI2_REFSYS_DIR + TIVA_ADI2_REFSYS_SOCLDOCTL1_OFFSET); /* Write to register CTLSOCREFSYS0 (addr offset 0) bits[4:0] (TRIMIREF) in * ADI2_REFSYS. Avoid using masked write access since bit field spans @@ -303,7 +305,8 @@ static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision) regval8 = (((fusedata & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_MASK) >> FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_SHIFT) << ADI2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT); - putreg8(regval8, TIVA_ADI2_REFSYS_DIR + TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET); + putreg8(regval8, + TIVA_ADI2_REFSYS_DIR + TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET); /* Write to register CTLSOCREFSYS2 (addr offset 4) bits[7:4] (TRIMMAG) in * ADI3_REFSYS @@ -485,8 +488,8 @@ static void trim_coldreset(void) * Perform the necessary trim of the device which is not done in boot code * * This function should only execute coming from ROM boot. The current - * implementation does not take soft reset into account. However, it does no - * damage to execute it again. It only consumes time. + * implementation does not take soft reset into account. However, it does + * no damage to execute it again. It only consumes time. * ****************************************************************************/ @@ -577,8 +580,8 @@ void cc13xx_trim_device(void) putreg32(0, TIVA_PRCM_PDCTL1VIMS); - /* Configure optimal wait time for flash FSM in cases where flash pump wakes - * up from sleep + /* Configure optimal wait time for flash FSM in cases where flash pump + * wakes up from sleep */ regval = getreg32(TIVA_FLASH_FPAC1); @@ -587,8 +590,8 @@ void cc13xx_trim_device(void) putreg32(regval, TIVA_FLASH_FPAC1); /* And finally at the end of the flash boot process: SET BOOT_DET bits in - * AON_PMCTL to 3 if already found to be 1 Note: The BOOT_DET_x_CLR/SET bits - * must be manually cleared + * AON_PMCTL to 3 if already found to be 1 Note: The BOOT_DET_x_CLR/SET + * bits must be manually cleared */ if ((getreg32(TIVA_AON_PMCTL_RESETCTL) & @@ -608,8 +611,8 @@ void cc13xx_trim_device(void) } /* Make sure there are no ongoing VIMS mode change when leaving - * cc13x2_cc26x2_trim_device() (There should typically be no wait time here, - * but need to be sure) + * cc13x2_cc26x2_trim_device() (There should typically be no wait time + * here, but need to be sure) */ while ((getreg32(TIVA_VIMS_STAT) & VIMS_STAT_MODE_CHANGING) != 0) diff --git a/arch/arm/src/tiva/cc13xx/cc13xx_chipinfo.c b/arch/arm/src/tiva/cc13xx/cc13xx_chipinfo.c index ffc6c678d3b..7d61141f5c2 100644 --- a/arch/arm/src/tiva/cc13xx/cc13xx_chipinfo.c +++ b/arch/arm/src/tiva/cc13xx/cc13xx_chipinfo.c @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/cc13xx/cc13xx_chipinfo.c * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -37,11 +37,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include @@ -51,11 +51,11 @@ #include "hardware/tiva_prcm.h" #include "tiva_chipinfo.h" -/***************************************************************************** +/**************************************************************************** * Public Functions - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Name: chipinfo_protocols * * Description: @@ -64,18 +64,19 @@ * Returned Value: * Returns a bit set indicating supported protocols. * - *****************************************************************************/ + ****************************************************************************/ enum cc13xx_protocol_e chipinfo_protocols(void) { /* Return allowed RTC modes. - * REVISIT: Per fcfg1 header file, the allowed RGC modes are in bits 0-2. */ + * REVISIT: Per fcfg1 header file, the allowed RGC modes are in bits 0-2. + */ - uint32_t regval = getreg32(TIVA_PRCM_RFCMODEHWOPT); - return (enum cc13xx_protocol_e)(regval & 0x0e); + uint32_t regval = getreg32(TIVA_PRCM_RFCMODEHWOPT); + return (enum cc13xx_protocol_e)(regval & 0x0e); } -/***************************************************************************** +/**************************************************************************** * Name: chipinfo_packagetype * * Description: @@ -84,7 +85,7 @@ enum cc13xx_protocol_e chipinfo_protocols(void) * Returned Value: * Returns an enumeration value indicating the package type. * - *****************************************************************************/ + ****************************************************************************/ enum cc13xx_package_e chipinfo_packagetype(void) { @@ -102,7 +103,7 @@ enum cc13xx_package_e chipinfo_packagetype(void) return pkgtype; } -/***************************************************************************** +/**************************************************************************** * Name: chipinfo_chiptype * * Description: @@ -111,7 +112,7 @@ enum cc13xx_package_e chipinfo_packagetype(void) * Returned Value: * Returns an enumeration value indicating the chip type * - *****************************************************************************/ + ****************************************************************************/ enum cc13xx_chiptype_e chipinfo_chiptype(void) { @@ -147,13 +148,13 @@ enum cc13xx_chiptype_e chipinfo_chiptype(void) #elif defined(CONFIG_ARCH_CHIP_CC13X2) - cc13 = ((userid & FCFG1_USER_ID_CC13) != 0); /* CC13xx device type (vs CC26xx) */ - pa = ((userid & FCFG1_USER_ID_PA) != 0); /* Supports 20dBM PA */ + cc13 = ((userid & FCFG1_USER_ID_CC13) != 0); /* CC13xx device type (vs CC26xx) */ + pa = ((userid & FCFG1_USER_ID_PA) != 0); /* Supports 20dBM PA */ - if (chipfamily == FAMILY_CC13x2_CC26x2) - { - switch (protocol) - { + if (chipfamily == FAMILY_CC13x2_CC26x2) + { + switch (protocol) + { case 0xf: if (cc13) { @@ -195,7 +196,7 @@ enum cc13xx_chiptype_e chipinfo_chiptype(void) return chiptype; } -/***************************************************************************** +/**************************************************************************** * Name: chipinfo_chipfamily * * Description: @@ -204,7 +205,7 @@ enum cc13xx_chiptype_e chipinfo_chiptype(void) * Returned Value: * Returns an enumeration value indicating the chip family * - *****************************************************************************/ + ****************************************************************************/ enum cc13xx_chipfamily_e chipinfo_chipfamily(void) { @@ -220,28 +221,30 @@ enum cc13xx_chipfamily_e chipinfo_chipfamily(void) if (waferid == 0xb9be) { chipfamily = FAMILY_CC13x0; - } + } #elif defined(CONFIG_ARCH_CHIP_CC13X2) if (waferid == 0xbb41) { chipfamily = FAMILY_CC13x2_CC26x2; - } + } #endif - return chipfamily; + return chipfamily; } -/***************************************************************************** +/**************************************************************************** * Name: chipinfo_hwrevision * * Description: - * Returns an enumeration value indicating the hardware revision of the chip + * Returns an enumeration value indicating the hardware revision of the + * chip * * Returned Value: - * Returns an enumeration value indicating the hardware revision of the chip + * Returns an enumeration value indicating the hardware revision of the + * chip * - *****************************************************************************/ + ****************************************************************************/ enum cc13xx_revision_e chipinfo_hwrevision(void) { @@ -265,7 +268,8 @@ enum cc13xx_revision_e chipinfo_hwrevision(void) break; case 2: /* CC13x0 PG2.0 (or later) */ - hwrev = (enum cc13xx_revision_e)(((uint32_t)HWREV_2_0) + hwminorrev); + hwrev = (enum cc13xx_revision_e)(((uint32_t)HWREV_2_0) + + hwminorrev); break; } } @@ -281,21 +285,23 @@ enum cc13xx_revision_e chipinfo_hwrevision(void) break; case 2: /* CC13x2, CC26x2 - PG1.1 (or later) */ - hwrev = (enum cc13xx_revision_e)(((uint32_t)HWREV_1_1) + hwminorrev); + hwrev = (enum cc13xx_revision_e)(((uint32_t)HWREV_1_1) + + hwminorrev); break; case 3: /* CC13x2, CC26x2 - PG2.1 (or later) */ - hwrev = (enum cc13xx_revision_e)(((uint32_t)HWREV_2_1) + hwminorrev); + hwrev = (enum cc13xx_revision_e)(((uint32_t)HWREV_2_1) + + hwminorrev); break; } } #endif - return hwrev; + return hwrev; } -/***************************************************************************** +/**************************************************************************** * Name: chipinfo_verify * * Description: @@ -305,7 +311,7 @@ enum cc13xx_revision_e chipinfo_hwrevision(void) * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_ASSERTIONS void chipinfo_verify(void) diff --git a/arch/arm/src/tiva/cc13xx/cc13xx_enableclks.h b/arch/arm/src/tiva/cc13xx/cc13xx_enableclks.h index abbdd0b7924..a7f04d549db 100644 --- a/arch/arm/src/tiva/cc13xx/cc13xx_enableclks.h +++ b/arch/arm/src/tiva/cc13xx/cc13xx_enableclks.h @@ -1,4 +1,4 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/cc13xx/cc13xx_enableclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_ENABLECLKS_H #define __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_ENABLECLKS_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "cc13xx/cc13xx_prcm.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ #define CC13XX_RUNMODE_CLOCK (1 << 0) #define CC13XX_SLEEPMODE_CLOCK (1 << 1) @@ -218,27 +218,27 @@ #define tiva_trng_enableclk() cc13xx_periph_enableclk(PRCM_PERIPH_TRNG, CC13XX_ALLMODE_CLOCKS) #define tiva_trng_disableclk() cc13xx_periph_disableclk(PRCM_PERIPH_TRNG, CC13XX_ALLMODE_CLOCKS) -/**************************************************************************************************** +/**************************************************************************** * Public Function Prototypes - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** +/**************************************************************************** * Name: cc13xx_periph_enableclks * * Description: * Enable clocking in the selected modes for this peripheral. * - ****************************************************************************************************/ + ****************************************************************************/ void cc13xx_periph_enableclk(uint32_t peripheral, uint32_t modeset); -/**************************************************************************************************** +/**************************************************************************** * Name: cc13xx_periph_disableclk * * Description: * Disable clocking in the selected modes for this peripheral. * - ****************************************************************************************************/ + ****************************************************************************/ void cc13xx_periph_disableclk(uint32_t peripheral, uint32_t modeset); diff --git a/arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.h b/arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.h index 404b208d797..46e6f333007 100644 --- a/arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.h +++ b/arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,29 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_ENABLEPWR_H #define __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_ENABLEPWR_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "cc13xx/cc13xx_prcm.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* CC13xx Power Domains: * * 1) PRCM_DOMAIN_RFCORE : RF Core * 2) PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 - * 3) PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 + * 3) PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, + * I2S, DMA, UART1 * 4) PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM * 5) PRCM_DOMAIN_SYSBUS * 6) PRCM_DOMAIN_CPU @@ -121,28 +122,28 @@ #define tiva_trng_enablepwr() cc13xx_periph_enablepwr(PRCM_PERIPH_TRNG) #define tiva_trng_disablepwr() cc13xx_periph_disablepwr(PRCM_PERIPH_TRNG) -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: cc13xx_periph_enablepwr * * Description: * Enable the power domain associated with the peripheral. * - ************************************************************************************/ + ****************************************************************************/ void cc13xx_periph_enablepwr(uint32_t peripheral); -/************************************************************************************ +/**************************************************************************** * Name: cc13xx_periph_disablepwr * * Description: - * Disable the power domain associated with the peripheral if and only if all - * peripherals using that power domain no longer need power. + * Disable the power domain associated with the peripheral if and only if + * all peripherals using that power domain no longer need power. * - ************************************************************************************/ + ****************************************************************************/ void cc13xx_periph_disablepwr(uint32_t peripheral); diff --git a/arch/arm/src/tiva/chip.h b/arch/arm/src/tiva/chip.h index bfaf33de9ac..4d8b747ea6b 100644 --- a/arch/arm/src/tiva/chip.h +++ b/arch/arm/src/tiva/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/chip.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_CHIP_H #define __ARCH_ARM_SRC_TIVA_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -43,13 +43,13 @@ #include "hardware/tiva_timer.h" /* Timer */ #include "hardware/tiva_adc.h" /* ADC */ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Provide the required number of peripheral interrupt vector definitions as well. - * The definition TIVA_IRQ_NEXTINT simply comes from the chip-specific IRQ header - * file included by arch/tiva/irq.h. +/* Provide the required number of peripheral interrupt vector definitions as + * well. The definition TIVA_IRQ_NEXTINT simply comes from the chip-specific + * IRQ header file included by arch/tiva/irq.h. */ #define ARMV7M_PERIPHERAL_INTERRUPTS TIVA_IRQ_NEXTINT diff --git a/arch/arm/src/tiva/common/lmxx_tm4c_enableclks.h b/arch/arm/src/tiva/common/lmxx_tm4c_enableclks.h index 8fc4c55d0c1..e9c2c5a24ff 100644 --- a/arch/arm/src/tiva/common/lmxx_tm4c_enableclks.h +++ b/arch/arm/src/tiva/common/lmxx_tm4c_enableclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/common/lmxx_tm4c_enableclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_COMMON_LMXX_TM4C_ENABLECLKS_H #define __ARCH_ARM_SRC_TIVA_COMMON_LMXX_TM4C_ENABLECLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,12 +31,12 @@ #include "chip.h" #include "hardware/tiva_sysctrl.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Clocks are enabled or disabled by setting or clearing a bit (b) in a system - * control register (a)) +/* Clocks are enabled or disabled by setting or clearing a bit (b) in a + * system control register (a)) */ #define tiva_enableclk(a,b) modifyreg32((a),0,(b)) diff --git a/arch/arm/src/tiva/common/lmxx_tm4c_enablepwr.h b/arch/arm/src/tiva/common/lmxx_tm4c_enablepwr.h index 3f4be38a519..69261ff0894 100644 --- a/arch/arm/src/tiva/common/lmxx_tm4c_enablepwr.h +++ b/arch/arm/src/tiva/common/lmxx_tm4c_enablepwr.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/common/lmxx_tm4c_enablepwr.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_COMMON_LMXX_TM4C_ENABLEPWR_H #define __ARCH_ARM_SRC_TIVA_COMMON_LMXX_TM4C_ENABLEPWR_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,12 +31,12 @@ #include "chip.h" #include "hardware/tiva_sysctrl.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Power control is enabled or disabled by setting or clearing a bit (b) in a system - * control register (a)) +/* Power control is enabled or disabled by setting or clearing a bit (b) in + * a system control register (a)) */ #define tiva_enablepwr(a, b) modifyreg32((a), 0, (b)) diff --git a/arch/arm/src/tiva/common/tiva_i2c.c b/arch/arm/src/tiva/common/tiva_i2c.c index e472bc844f9..c40057b3429 100644 --- a/arch/arm/src/tiva/common/tiva_i2c.c +++ b/arch/arm/src/tiva/common/tiva_i2c.c @@ -1,11 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/common/tiva_i2c.c * * Copyright (C) 2014-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * The basic structure of this driver derives in spirit (if nothing more) from the - * NuttX STM32 I2C driver which has: + * The basic structure of this driver derives in spirit (if nothing more) + * from the NuttX STM32 I2C driver which has: * * Copyright (C) 2011 Uros Platise. All rights reserved. * Author: Uros Platise @@ -37,11 +37,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -80,14 +80,14 @@ defined(CONFIG_TIVA_I2C6) || defined(CONFIG_TIVA_I2C7) || \ defined(CONFIG_TIVA_I2C8) || defined(CONFIG_TIVA_I2C9) -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Configuration ********************************************************************/ +/* Configuration ************************************************************/ -/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. Instead, - * CPU-intensive polling will be used. +/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. + * Instead, CPU-intensive polling will be used. */ /* Interrupt wait timeout in seconds and milliseconds */ @@ -112,7 +112,7 @@ # define CONFIG_TIVA_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_TIVA_I2C_TIMEOTICKS) #endif -/* GPIO pins ************************************************************************/ +/* GPIO pins ****************************************************************/ /* Macros to convert a I2C pin to a GPIO output */ @@ -122,15 +122,16 @@ #define MKI2C_INPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_INPUT) #define MKI2C_OUTPUT(p) (((p) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | I2C_OUTPUT) -/* Debug ****************************************************************************/ +/* Debug ********************************************************************/ #ifndef CONFIG_DEBUG_I2C_INFO # undef CONFIG_TIVA_I2C_REGDEBUG #endif -/* I2C event trace logic. NOTE: trace uses the internal, non-standard, low-level - * debug interface syslog() but does not require that any other debug - * is enabled. +/* I2C event trace logic. + * NOTE: + * trace uses the internal, non-standard, low-level debug interface syslog() + * but does not require that any other debug is enabled. */ #ifndef CONFIG_I2C_TRACE @@ -144,9 +145,9 @@ # define CONFIG_I2C_NTRACE 32 #endif -/************************************************************************************ +/**************************************************************************** * Private Types - ************************************************************************************/ + ****************************************************************************/ /* Interrupt state */ @@ -253,15 +254,17 @@ struct tiva_i2c_priv_s #endif }; -/************************************************************************************ +/**************************************************************************** * Private Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_TIVA_I2C_REGDEBUG static bool tiva_i2c_checkreg(struct tiva_i2c_priv_s *priv, bool wr, uint32_t regval, uintptr_t regaddr); -static uint32_t tiva_i2c_getreg(struct tiva_i2c_priv_s *priv, unsigned int offset); -static void tiva_i2c_putreg(struct tiva_i2c_priv_s *priv, unsigned int offset, +static uint32_t tiva_i2c_getreg(struct tiva_i2c_priv_s *priv, + unsigned int offset); +static void tiva_i2c_putreg(struct tiva_i2c_priv_s *priv, + unsigned int offset, uint32_t value); #else static inline uint32_t tiva_i2c_getreg(struct tiva_i2c_priv_s *priv, @@ -295,18 +298,21 @@ static int tiva_i2c_process(struct tiva_i2c_priv_s * priv, uint32_t status); static int tiva_i2c_interrupt(int irq, void *context, FAR void *arg); #endif /* !CONFIG_I2C_POLLED */ -static int tiva_i2c_initialize(struct tiva_i2c_priv_s *priv, uint32_t frequency); +static int tiva_i2c_initialize(struct tiva_i2c_priv_s *priv, + uint32_t frequency); static int tiva_i2c_uninitialize(struct tiva_i2c_priv_s *priv); -static void tiva_i2c_setclock(struct tiva_i2c_priv_s *priv, uint32_t frequency); -static int tiva_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgv, +static void tiva_i2c_setclock(struct tiva_i2c_priv_s *priv, + uint32_t frequency); +static int tiva_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgv, int msgc); #ifdef CONFIG_I2C_RESET static int tiva_i2c_reset(FAR struct i2c_master_s *dev); #endif -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ /* I2C Interface */ @@ -528,11 +534,11 @@ static const struct tiva_i2c_config_s tiva_i2c9_config = static struct tiva_i2c_priv_s tiva_i2c9_priv; #endif -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: sam_checkreg * * Description: @@ -546,7 +552,7 @@ static struct tiva_i2c_priv_s tiva_i2c9_priv; * true: This is the first register access of this type. * flase: This is the same as the preceding register access. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_TIVA_I2C_REGDEBUG static bool tiva_i2c_checkreg(struct tiva_i2c_priv_s *priv, bool wr, @@ -586,16 +592,17 @@ static bool tiva_i2c_checkreg(struct tiva_i2c_priv_s *priv, bool wr, } #endif -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_getreg * * Description: * Get a 16-bit register value by offset * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_TIVA_I2C_REGDEBUG -static uint32_t tiva_i2c_getreg(struct tiva_i2c_priv_s *priv, unsigned int offset) +static uint32_t tiva_i2c_getreg(struct tiva_i2c_priv_s *priv, + unsigned int offset) { uintptr_t regaddr = priv->config->base + offset; uint32_t regval = getreg32(regaddr); @@ -615,16 +622,17 @@ static inline uint32_t tiva_i2c_getreg(struct tiva_i2c_priv_s *priv, } #endif -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_putreg * * Description: * Put a 16-bit register value by offset * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_TIVA_I2C_REGDEBUG -static void tiva_i2c_putreg(struct tiva_i2c_priv_s *priv, unsigned int offset, +static void tiva_i2c_putreg(struct tiva_i2c_priv_s *priv, + unsigned int offset, uint32_t regval) { uintptr_t regaddr = priv->config->base + offset; @@ -644,13 +652,14 @@ static inline void tiva_i2c_putreg(struct tiva_i2c_priv_s *priv, } #endif -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_tousecs * * Description: - * Return a micro-second delay based on the number of bytes left to be processed. + * Return a micro-second delay based on the number of bytes left to be + * processed. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_TIVA_I2C_DYNTIMEO static useconds_t tiva_i2c_tousecs(int msgc, struct i2c_msg_s *msgv) @@ -673,13 +682,13 @@ static useconds_t tiva_i2c_tousecs(int msgc, struct i2c_msg_s *msgv) } #endif -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_sem_waitdone * * Description: * Wait for a transfer to complete * - ************************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_I2C_POLLED static inline int tiva_i2c_sem_waitdone(struct tiva_i2c_priv_s *priv) @@ -690,16 +699,16 @@ static inline int tiva_i2c_sem_waitdone(struct tiva_i2c_priv_s *priv) flags = enter_critical_section(); - /* Enable the master interrupt. The I2C master module generates an interrupt when - * a transaction completes (either transmit or receive), when arbitration is lost, - * or when an error occurs during a transaction. + /* Enable the master interrupt. The I2C master module generates an + * interrupt when a transaction completes (either transmit or receive), + * when arbitration is lost, or when an error occurs during a transaction. */ tiva_i2c_putreg(priv, TIVA_I2CM_IMR_OFFSET, I2CM_IMR_MIM); - /* Signal the interrupt handler that we are waiting. NOTE: Interrupts - * are currently disabled but will be temporarily re-enabled below when - * nxsem_timedwait() sleeps. + /* Signal the interrupt handler that we are waiting. + * NOTE: Interrupts are currently disabled but will be temporarily + * re-enabled below when nxsem_timedwait() sleeps. */ do @@ -819,26 +828,26 @@ static inline int tiva_i2c_sem_waitdone(struct tiva_i2c_priv_s *priv) } #endif -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_sem_post * * Description: * Release the mutual exclusion semaphore * - ************************************************************************************/ + ****************************************************************************/ static inline void tiva_i2c_sem_post(struct tiva_i2c_priv_s *priv) { nxsem_post(&priv->exclsem); } -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_sem_init * * Description: * Initialize semaphores * - ************************************************************************************/ + ****************************************************************************/ static inline void tiva_i2c_sem_init(struct tiva_i2c_priv_s *priv) { @@ -854,13 +863,13 @@ static inline void tiva_i2c_sem_init(struct tiva_i2c_priv_s *priv) #endif } -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_sem_destroy * * Description: * Destroy semaphores. * - ************************************************************************************/ + ****************************************************************************/ static inline void tiva_i2c_sem_destroy(struct tiva_i2c_priv_s *priv) { @@ -870,13 +879,13 @@ static inline void tiva_i2c_sem_destroy(struct tiva_i2c_priv_s *priv) #endif } -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_trace * * Description: * I2C trace instrumentation * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_I2C_TRACE static void tiva_i2c_traceclear(struct tiva_i2c_priv_s *priv) @@ -913,11 +922,14 @@ static void tiva_i2c_tracenew(struct tiva_i2c_priv_s *priv, uint32_t status) if (trace->count != 0) { - /* Yes.. bump up the trace index (unless we are out of trace entries) */ + /* Yes.. bump up the trace index + * (unless we are out of trace entries) + */ if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) { - i2cerr("ERROR: I2C%d trace table overflow\n", priv->config->devno); + i2cerr("ERROR: I2C%d trace table overflow\n", + priv->config->devno); return; } @@ -966,7 +978,8 @@ static void tiva_i2c_traceevent(struct tiva_i2c_priv_s *priv, if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) { - i2cerr("ERROR: I2C%d trace table overflow\n", priv->config->devno); + i2cerr("ERROR: I2C%d trace table overflow\n", + priv->config->devno); return; } @@ -1005,13 +1018,13 @@ static void tiva_i2c_tracedump(struct tiva_i2c_priv_s *priv) } #endif /* CONFIG_I2C_TRACE */ -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_startxfr * * Description: * Send the START conditions/force Master mode * - ************************************************************************************/ + ****************************************************************************/ static void tiva_i2c_startxfr(struct tiva_i2c_priv_s *priv) { @@ -1043,30 +1056,32 @@ static void tiva_i2c_startxfr(struct tiva_i2c_priv_s *priv) tiva_i2c_nextxfr(priv, I2CM_CS_START); } -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_nextxfr * * Description: * Common Interrupt Service Routine * - ************************************************************************************/ + ****************************************************************************/ static void tiva_i2c_nextxfr(struct tiva_i2c_priv_s *priv, uint32_t cmd) { - /* Set up the basic command. The STOP bit should be set on the last byte transfer. + /* Set up the basic command. The STOP bit should be set on the last byte + * transfer. * - * - CASE 1: If this is the last message in the sequence, then the stop bit should - * always be set. + * - CASE 1: If this is the last message in the sequence, then the stop bit + * should always be set. * - CASE 2.1.1: The next message may be another read or write of the SAME - * direction (read or write) and to the SAME address WITHOUT repeated start, in - * which case this is really just a continuation of the message. No STOP is - * needed. - * - CASE 2.x.2: The next message may be to the SAME address WITH repeated start. - * Because the repeated start, a direction change is possible. This is still - * a continuation of the same message sequence and so no STOP is needed. - * - CASE 2.2.x: The next message may be a DIFFERENT address WITHOUT repeated - * start. This would be an error; The STOP will be sent, the next message will - * fail. + * direction (read or write) and to the SAME address WITHOUT repeated + * start, in which case this is really just a continuation of the + * message. No STOP is needed. + * - CASE 2.x.2: The next message may be to the SAME address WITH repeated + * start. Because the repeated start, a direction change is possible. + * This is still a continuation of the same message sequence and so no + * STOP is needed. + * - CASE 2.2.x: The next message may be a DIFFERENT address WITHOUT + * repeated start. This would be an error; The STOP will be sent, the + * next message will fail. */ cmd |= I2CM_CS_RUN; @@ -1111,7 +1126,9 @@ static void tiva_i2c_nextxfr(struct tiva_i2c_priv_s *priv, uint32_t cmd) cmd |= I2CM_CS_ACK; } - /* Write the command to the control register to receive the next byte. */ + /* Write the command to the control register to receive the next + * byte. + */ tiva_i2c_putreg(priv, TIVA_I2CM_CS_OFFSET, cmd); tiva_i2c_traceevent(priv, I2CEVENT_RECVSETUP, priv->mcnt); @@ -1120,13 +1137,15 @@ static void tiva_i2c_nextxfr(struct tiva_i2c_priv_s *priv, uint32_t cmd) { uint32_t dr; - /* We are sending data. Write the data to be sent to the DR register. */ + /* We are sending data. + * Write the data to be sent to the DR register. + */ dr = (uint32_t)*priv->mptr++; tiva_i2c_putreg(priv, TIVA_I2CM_DR_OFFSET, dr << I2CM_DR_SHIFT); - /* Write the command to the control register to send the byte in the DR - * register. + /* Write the command to the control register to send the byte in the + * DR register. */ tiva_i2c_putreg(priv, TIVA_I2CM_CS_OFFSET, cmd); @@ -1136,13 +1155,13 @@ static void tiva_i2c_nextxfr(struct tiva_i2c_priv_s *priv, uint32_t cmd) priv->intstate = INTSTATE_WAITING; } -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_process * * Description: * Common Interrupt Service Routine * - ************************************************************************************/ + ****************************************************************************/ static int tiva_i2c_process(struct tiva_i2c_priv_s *priv, uint32_t status) { @@ -1150,9 +1169,9 @@ static int tiva_i2c_process(struct tiva_i2c_priv_s *priv, uint32_t status) tiva_i2c_tracenew(priv, status); - /* Check for a master interrupt? The I2C master module generates an interrupt when - * a transaction completes (either transmit or receive), when arbitration is lost, - * or when an error occurs during a transaction. + /* Check for a master interrupt? The I2C master module generates an + * interrupt when a transaction completes (either transmit or receive), + * when arbitration is lost, or when an error occurs during a transaction. */ if ((status & I2CM_RIS_MRIS) != 0) @@ -1173,8 +1192,8 @@ static int tiva_i2c_process(struct tiva_i2c_priv_s *priv, uint32_t status) tiva_i2c_getreg(priv, TIVA_I2CM_MIS_OFFSET); #endif - /* We need look at the Master Control/Status register to determine the cause - * of the master interrupt. + /* We need look at the Master Control/Status register to determine + * the cause of the master interrupt. */ mcs = tiva_i2c_getreg(priv, TIVA_I2CM_CS_OFFSET); @@ -1247,7 +1266,9 @@ static int tiva_i2c_process(struct tiva_i2c_priv_s *priv, uint32_t status) if (priv->intstate == INTSTATE_WAITING) { - /* Data transfer completed. Are we sending or receiving data? */ + /* Data transfer completed. + * Are we sending or receiving data? + */ if ((priv->mflags & I2C_M_READ) != 0) { @@ -1287,7 +1308,8 @@ static int tiva_i2c_process(struct tiva_i2c_priv_s *priv, uint32_t status) * continue with or without the (repeated) start bit. */ - tiva_i2c_traceevent(priv, I2CEVENT_NEXTMSG, priv->msgc); + tiva_i2c_traceevent(priv, + I2CEVENT_NEXTMSG, priv->msgc); if ((priv->msgv->flags & I2C_M_NOSTART) != 0) { /* Just continue transferring data. In this case, @@ -1314,7 +1336,8 @@ static int tiva_i2c_process(struct tiva_i2c_priv_s *priv, uint32_t status) { /* No.. then we are finished */ - tiva_i2c_traceevent(priv, I2CEVENT_DONE, priv->intstate); + tiva_i2c_traceevent(priv, + I2CEVENT_DONE, priv->intstate); /* Disable further interrupts */ @@ -1361,13 +1384,13 @@ static int tiva_i2c_process(struct tiva_i2c_priv_s *priv, uint32_t status) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_interrupt * * Description: * Common I2C interrupt service routine * - ************************************************************************************/ + ****************************************************************************/ #ifndef CONFIG_I2C_POLLED static int tiva_i2c_interrupt(int irq, void *context, void *arg) @@ -1387,15 +1410,16 @@ static int tiva_i2c_interrupt(int irq, void *context, void *arg) } #endif -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_initialize * * Description: * Setup the I2C hardware, ready for operation with defaults * - ************************************************************************************/ + ****************************************************************************/ -static int tiva_i2c_initialize(struct tiva_i2c_priv_s *priv, uint32_t frequency) +static int tiva_i2c_initialize(struct tiva_i2c_priv_s *priv, + uint32_t frequency) { const struct tiva_i2c_config_s *config = priv->config; uint32_t regval; @@ -1494,13 +1518,13 @@ static int tiva_i2c_initialize(struct tiva_i2c_priv_s *priv, uint32_t frequency) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_uninitialize * * Description: * Shutdown the I2C hardware * - ************************************************************************************/ + ****************************************************************************/ static int tiva_i2c_uninitialize(struct tiva_i2c_priv_s *priv) { @@ -1537,15 +1561,16 @@ static int tiva_i2c_uninitialize(struct tiva_i2c_priv_s *priv) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_setclock * * Description: * Set the I2C frequency * - ************************************************************************************/ + ****************************************************************************/ -static void tiva_i2c_setclock(struct tiva_i2c_priv_s *priv, uint32_t frequency) +static void tiva_i2c_setclock(struct tiva_i2c_priv_s *priv, + uint32_t frequency) { uint32_t regval; uint32_t tmp; @@ -1557,8 +1582,8 @@ static void tiva_i2c_setclock(struct tiva_i2c_priv_s *priv, uint32_t frequency) if (frequency != priv->frequency) { - /* Calculate the clock divider that results in the highest frequency that - * is than or equal to the desired speed. + /* Calculate the clock divider that results in the highest frequency + * that is than or equal to the desired speed. */ tmp = 2 * 10 * frequency; @@ -1576,9 +1601,11 @@ static void tiva_i2c_setclock(struct tiva_i2c_priv_s *priv, uint32_t frequency) if ((regval & I2CSC_PC_HS) != 0) { tmp = (2 * 3 * 3400000); - regval = (((SYSCLK_FREQUENCY + tmp - 1) / tmp) - 1) << I2CM_TPR_SHIFT; + regval = (((SYSCLK_FREQUENCY + tmp - 1) / tmp) - 1) << + I2CM_TPR_SHIFT; - tiva_i2c_putreg(priv, TIVA_I2CM_TPR_OFFSET, I2CM_TPR_HS | regval); + tiva_i2c_putreg(priv, TIVA_I2CM_TPR_OFFSET, + I2CM_TPR_HS | regval); } #endif @@ -1588,15 +1615,16 @@ static void tiva_i2c_setclock(struct tiva_i2c_priv_s *priv, uint32_t frequency) } } -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_transfer * * Description: * Generic I2C transfer function * - ************************************************************************************/ + ****************************************************************************/ -static int tiva_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgv, +static int tiva_i2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgv, int msgc) { struct tiva_i2c_priv_s *priv = (struct tiva_i2c_priv_s *)dev; @@ -1652,7 +1680,8 @@ static int tiva_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgv, ret = -ETIMEDOUT; } #if 0 /* I2CM_CS_CLKTO */ - else if ((priv->mstatus & (I2CM_CS_ERROR | I2CM_CS_ARBLST | I2CM_CS_CLKTO)) != 0) + else if ((priv->mstatus & + (I2CM_CS_ERROR | I2CM_CS_ARBLST | I2CM_CS_CLKTO)) != 0) #else else if ((priv->mstatus & (I2CM_CS_ERROR | I2CM_CS_ARBLST)) != 0) #endif @@ -1688,9 +1717,10 @@ static int tiva_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgv, } } - /* This is not an error, but should not happen. The I2CM_CS_BUSBSY signal - * can hang, however. This normally indicates the STOP was never sent, - * possibly because some other error occurred. + /* This is not an error, but should not happen. + * The I2CM_CS_BUSBSY signal can hang, however. + * This normally indicates the STOP was never sent, possibly because some + * other error occurred. * * The status bits are not valid if BUSY is set. But in this context I * assume that busy bit stuck on would be a very bad situation, worthy @@ -1725,7 +1755,9 @@ static int tiva_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgv, tiva_i2c_tracedump(priv); - /* Ensure that no ISR happening after we finish can overwrite any user data */ + /* Ensure that no ISR happening after we finish can overwrite any user + * data + */ priv->mcnt = 0; priv->mptr = NULL; @@ -1734,7 +1766,7 @@ static int tiva_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgv, return ret; } -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2c_reset * * Description: @@ -1746,7 +1778,7 @@ static int tiva_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgv, * Returned Value: * Zero (OK) on success; a negated errno value on failure. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_I2C_RESET static int tiva_i2c_reset(FAR struct i2c_master_s * dev) @@ -1862,17 +1894,17 @@ out: } #endif /* CONFIG_I2C_RESET */ -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2cbus_initialize * * Description: * Initialize one I2C bus * - ************************************************************************************/ + ****************************************************************************/ struct i2c_master_s *tiva_i2cbus_initialize(int port) { @@ -1988,13 +2020,13 @@ struct i2c_master_s *tiva_i2cbus_initialize(int port) return (struct i2c_master_s *)priv; } -/************************************************************************************ +/**************************************************************************** * Name: tiva_i2cbus_uninitialize * * Description: * Uninitialize an I2C bus * - ************************************************************************************/ + ****************************************************************************/ int tiva_i2cbus_uninitialize(struct i2c_master_s *dev) { diff --git a/arch/arm/src/tiva/common/tiva_pwm.c b/arch/arm/src/tiva/common/tiva_pwm.c index 25f69d6b618..a84462ee71b 100644 --- a/arch/arm/src/tiva/common/tiva_pwm.c +++ b/arch/arm/src/tiva/common/tiva_pwm.c @@ -1,11 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/common/tiva_pwm.c * * Copyright (C) 2016 Young Mu. All rights reserved. * Author: Young Mu * - * The basic structure of this driver derives in spirit (if nothing more) from the - * NuttX SAM PWM driver which has: + * The basic structure of this driver derives in spirit (if nothing more) + * from the NuttX SAM PWM driver which has: * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -37,11 +37,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -61,9 +61,9 @@ #include "hardware/tiva_pinmap.h" #include "hardware/tiva_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Private Types - ************************************************************************************/ + ****************************************************************************/ uint32_t g_pwm_pinset[] = { @@ -94,24 +94,28 @@ struct tiva_pwm_chan_s #endif }; -/************************************************************************************ +/**************************************************************************** * Private Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN0) -static int tiva_pwm_gen0_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_pwm_gen0_interrupt(int irq, + FAR void *context, FAR void *arg); #endif #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN2) -static int tiva_pwm_gen1_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_pwm_gen1_interrupt(int irq, + FAR void *context, FAR void *arg); #endif #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN4) -static int tiva_pwm_gen2_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_pwm_gen2_interrupt(int irq, + FAR void *context, FAR void *arg); #endif #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN6) -static int tiva_pwm_gen3_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_pwm_gen3_interrupt(int irq, + FAR void *context, FAR void *arg); #endif #if defined(CONFIG_PWM_PULSECOUNT) && \ @@ -131,7 +135,8 @@ static int tiva_pwm_setup(FAR struct pwm_lowerhalf_s *dev); static int tiva_pwm_shutdown(FAR struct pwm_lowerhalf_s *dev); #ifdef CONFIG_PWM_PULSECOUNT static int tiva_pwm_start(FAR struct pwm_lowerhalf_s *dev, - FAR const struct pwm_info_s *info, FAR void *handle); + FAR const struct pwm_info_s *info, + FAR void *handle); #else static int tiva_pwm_start(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_s *info); @@ -140,9 +145,9 @@ static int tiva_pwm_stop(FAR struct pwm_lowerhalf_s *dev); static int tiva_pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg); -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ static uint32_t g_pwm_freq = 1875000; static uint32_t g_pwm_counter = (1 << 16); @@ -163,7 +168,8 @@ static struct tiva_pwm_chan_s g_pwm_chan0 = .controller_id = 0, .controller_base = TIVA_PWM0_BASE, .generator_id = 0, - .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 0, + .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + + TIVA_PWMn_INTERVAL * 0, .channel_id = 0, #ifdef CONFIG_PWM_PULSECOUNT .inited = false, @@ -182,7 +188,8 @@ static struct tiva_pwm_chan_s g_pwm_chan1 = .controller_id = 0, .controller_base = TIVA_PWM0_BASE, .generator_id = 0, - .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 0, + .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + + TIVA_PWMn_INTERVAL * 0, .channel_id = 1, #ifdef CONFIG_PWM_PULSECOUNT .inited = false, @@ -201,7 +208,8 @@ static struct tiva_pwm_chan_s g_pwm_chan2 = .controller_id = 0, .controller_base = TIVA_PWM0_BASE, .generator_id = 1, - .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 1, + .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + + TIVA_PWMn_INTERVAL * 1, .channel_id = 2, #ifdef CONFIG_PWM_PULSECOUNT .inited = false, @@ -220,7 +228,8 @@ static struct tiva_pwm_chan_s g_pwm_chan3 = .controller_id = 0, .controller_base = TIVA_PWM0_BASE, .generator_id = 1, - .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 1, + .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + + TIVA_PWMn_INTERVAL * 1, .channel_id = 3, #ifdef CONFIG_PWM_PULSECOUNT .inited = false, @@ -239,7 +248,8 @@ static struct tiva_pwm_chan_s g_pwm_chan4 = .controller_id = 0, .controller_base = TIVA_PWM0_BASE, .generator_id = 2, - .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 2, + .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + + TIVA_PWMn_INTERVAL * 2, .channel_id = 4, #ifdef CONFIG_PWM_PULSECOUNT .inited = false, @@ -258,7 +268,8 @@ static struct tiva_pwm_chan_s g_pwm_chan5 = .controller_id = 0, .controller_base = TIVA_PWM0_BASE, .generator_id = 2, - .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 2, + .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + + TIVA_PWMn_INTERVAL * 2, .channel_id = 5, #ifdef CONFIG_PWM_PULSECOUNT .inited = false, @@ -277,7 +288,8 @@ static struct tiva_pwm_chan_s g_pwm_chan6 = .controller_id = 0, .controller_base = TIVA_PWM0_BASE, .generator_id = 3, - .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 3, + .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + + TIVA_PWMn_INTERVAL * 3, .channel_id = 6, #ifdef CONFIG_PWM_PULSECOUNT .inited = false, @@ -296,7 +308,8 @@ static struct tiva_pwm_chan_s g_pwm_chan7 = .controller_id = 0, .controller_base = TIVA_PWM0_BASE, .generator_id = 3, - .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + TIVA_PWMn_INTERVAL * 3, + .generator_base = TIVA_PWM0_BASE + TIVA_PWMn_BASE + + TIVA_PWMn_INTERVAL * 3, .channel_id = 7, #ifdef CONFIG_PWM_PULSECOUNT .inited = false, @@ -308,17 +321,17 @@ static struct tiva_pwm_chan_s g_pwm_chan7 = }; #endif -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: tiva_pwm_gen[n]_interrupt * * Description: * Pulse count interrupt handlers for PWM[n] * - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_PWM_PULSECOUNT) && defined(CONFIG_TIVA_PWM0_CHAN0) static int tiva_pwm_gen0_interrupt(int irq, FAR void *context, FAR void *arg) @@ -348,13 +361,13 @@ static int tiva_pwm_gen3_interrupt(int irq, FAR void *context, FAR void *arg) } #endif -/************************************************************************************ +/**************************************************************************** * Name: tiva_pwm_interrupt * * Description: * Common pulse count interrupt handler. * - ************************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_PWM_PULSECOUNT) && \ (defined(CONFIG_TIVA_PWM0_CHAN0) || defined(CONFIG_TIVA_PWM0_CHAN2) || \ @@ -373,7 +386,8 @@ static int tiva_pwm_interrupt(struct tiva_pwm_chan_s *chan) if (chan->cur_count == 0) { - tiva_pwm_putreg(chan, TIVA_PWMn_CTL_OFFSET, CTL_DISABLE << TIVA_PWMn_CTL_ENABLE); + tiva_pwm_putreg(chan, TIVA_PWMn_CTL_OFFSET, + CTL_DISABLE << TIVA_PWMn_CTL_ENABLE); chan->cur_count = chan->count; pwm_expired(chan->handle); } @@ -382,28 +396,28 @@ static int tiva_pwm_interrupt(struct tiva_pwm_chan_s *chan) } #endif -/************************************************************************************ +/**************************************************************************** * Name: tiva_pwm_getreg * * Description: * Get a 32-bit register value by offset * - ************************************************************************************/ + ****************************************************************************/ static inline uint32_t tiva_pwm_getreg(struct tiva_pwm_chan_s *chan, unsigned int offset) { - uintptr_t regaddr = chan->generator_base + offset; - return getreg32(regaddr); + uintptr_t regaddr = chan->generator_base + offset; + return getreg32(regaddr); } -/************************************************************************************ +/**************************************************************************** * Name: tiva_pwm_putreg * * Description: * Put a 32-bit register value by offset * - ************************************************************************************/ + ****************************************************************************/ static inline void tiva_pwm_putreg(struct tiva_pwm_chan_s *chan, unsigned int offset, uint32_t regval) @@ -500,7 +514,8 @@ static int tiva_pwm_shutdown(FAR struct pwm_lowerhalf_s *dev) #ifdef CONFIG_PWM_PULSECOUNT static int tiva_pwm_start(FAR struct pwm_lowerhalf_s *dev, - FAR const struct pwm_info_s *info, FAR void *handle) + FAR const struct pwm_info_s *info, + FAR void *handle) { FAR struct tiva_pwm_chan_s *chan = (FAR struct tiva_pwm_chan_s *)dev; pwminfo("start PWM for channel %d\n", chan->channel_id); @@ -533,7 +548,8 @@ static int tiva_pwm_start(FAR struct pwm_lowerhalf_s *dev, /* Disable interrupt */ - uint32_t enable = getreg32(chan->controller_base + TIVA_PWM_INTEN_OFFSET); + uint32_t enable = getreg32(chan->controller_base + + TIVA_PWM_INTEN_OFFSET); enable &= ~(INT_ENABLE << chan->generator_id); putreg32(enable, chan->controller_base + TIVA_PWM_INTEN_OFFSET); } @@ -541,7 +557,8 @@ static int tiva_pwm_start(FAR struct pwm_lowerhalf_s *dev, { /* Enable interrupt */ - uint32_t enable = getreg32(chan->controller_base + TIVA_PWM_INTEN_OFFSET); + uint32_t enable = getreg32(chan->controller_base + + TIVA_PWM_INTEN_OFFSET); enable |= (INT_ENABLE << chan->generator_id); putreg32(enable, chan->controller_base + TIVA_PWM_INTEN_OFFSET); } @@ -642,7 +659,9 @@ static inline int tiva_pwm_timer(FAR struct tiva_pwm_chan_s *chan, /* Enable the PWM generator (refer to TM4C1294NCPDT 23.4.10) */ - tiva_pwm_putreg(chan, TIVA_PWMn_CTL_OFFSET, CTL_ENABLE << TIVA_PWMn_CTL_ENABLE); + tiva_pwm_putreg(chan, + TIVA_PWMn_CTL_OFFSET, + CTL_ENABLE << TIVA_PWMn_CTL_ENABLE); /* Enable PWM channel (refer to TM4C1294NCPDT 23.4.11) */ @@ -817,7 +836,8 @@ FAR struct pwm_lowerhalf_s *tiva_pwm_initialize(int channel) * TODO: need an algorithm to choose the best divider and load value combo. */ - putreg32(CC_USEPWM << TIVA_PWM_CC_USEPWM | CC_PWMDIV_64 << TIVA_PWM_CC_PWMDIV, + putreg32(CC_USEPWM << TIVA_PWM_CC_USEPWM | + CC_PWMDIV_64 << TIVA_PWM_CC_PWMDIV, chan->controller_base + TIVA_PWM_CC); #ifdef CONFIG_PWM_PULSECOUNT @@ -826,7 +846,7 @@ FAR struct pwm_lowerhalf_s *tiva_pwm_initialize(int channel) tiva_pwm_putreg(chan, TIVA_PWMn_INTEN_OFFSET, INT_SET << INTCMPAD); - /* Attach IRQ handler and enable interrupt*/ + /* Attach IRQ handler and enable interrupt */ switch (chan->channel_id) { diff --git a/arch/arm/src/tiva/common/tiva_timerlib.c b/arch/arm/src/tiva/common/tiva_timerlib.c index 83d7b863cf9..9e96b4e5e4f 100644 --- a/arch/arm/src/tiva/common/tiva_timerlib.c +++ b/arch/arm/src/tiva/common/tiva_timerlib.c @@ -55,6 +55,7 @@ /**************************************************************************** * Private Types ****************************************************************************/ + /* This structure retains the fixed, well-known attributes of a GPTM module */ struct tiva_gptmattr_s @@ -86,23 +87,25 @@ struct tiva_gptmstate_s #ifdef CONFIG_TIVA_TIMER_REGDEBUG /* Register level debug */ - bool wrlast; /* Last was a write */ - uintptr_t addrlast; /* Last address */ - uint32_t vallast; /* Last value */ - int ntimes; /* Number of times */ + bool wrlast; /* Last was a write */ + uintptr_t addrlast; /* Last address */ + uint32_t vallast; /* Last value */ + int ntimes; /* Number of times */ #endif }; /**************************************************************************** * Private Function Prototypes ****************************************************************************/ + /* Register Access */ #ifdef CONFIG_TIVA_TIMER_REGDEBUG static bool tiva_timer_checkreg(struct tiva_gptmstate_s *priv, bool wr, uint32_t regval, uintptr_t regaddr); #endif -static uint32_t tiva_getreg(struct tiva_gptmstate_s *priv, unsigned int offset); +static uint32_t tiva_getreg(struct tiva_gptmstate_s *priv, + unsigned int offset); static void tiva_putreg(struct tiva_gptmstate_s *priv, unsigned int offset, uint32_t regval); @@ -140,36 +143,52 @@ static int tiva_gptm7_interrupt(int irq, FAR void *context, FAR void *arg); static int tiva_timer16_interrupt(struct tiva_gptmstate_s *priv, int tmndx); #ifdef CONFIG_TIVA_TIMER0 -static int tiva_timer0a_interrupt(int irq, FAR void *context, FAR void *arg); -static int tiva_timer0b_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer0a_interrupt(int irq, FAR void *context, + FAR void *arg); +static int tiva_timer0b_interrupt(int irq, FAR void *context, + FAR void *arg); #endif #ifdef CONFIG_TIVA_TIMER1 -static int tiva_timer1a_interrupt(int irq, FAR void *context, FAR void *arg); -static int tiva_timer1b_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer1a_interrupt(int irq, FAR void *context, + FAR void *arg); +static int tiva_timer1b_interrupt(int irq, FAR void *context, + FAR void *arg); #endif #ifdef CONFIG_TIVA_TIMER2 -static int tiva_timer2a_interrupt(int irq, FAR void *context, FAR void *arg); -static int tiva_timer2b_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer2a_interrupt(int irq, FAR void *context, + FAR void *arg); +static int tiva_timer2b_interrupt(int irq, FAR void *context, + FAR void *arg); #endif #ifdef CONFIG_TIVA_TIMER3 -static int tiva_timer3a_interrupt(int irq, FAR void *context, FAR void *arg); -static int tiva_timer3b_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer3a_interrupt(int irq, FAR void *context, + FAR void *arg); +static int tiva_timer3b_interrupt(int irq, FAR void *context, + FAR void *arg); #endif #ifdef CONFIG_TIVA_TIMER4 -static int tiva_timer4a_interrupt(int irq, FAR void *context, FAR void *arg); -static int tiva_timer4b_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer4a_interrupt(int irq, FAR void *context, + FAR void *arg); +static int tiva_timer4b_interrupt(int irq, FAR void *context, + FAR void *arg); #endif #ifdef CONFIG_TIVA_TIMER5 -static int tiva_timer5a_interrupt(int irq, FAR void *context, FAR void *arg); -static int tiva_timer5b_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer5a_interrupt(int irq, FAR void *context, + FAR void *arg); +static int tiva_timer5b_interrupt(int irq, FAR void *context, + FAR void *arg); #endif #ifdef CONFIG_TIVA_TIMER6 -static int tiva_timer6a_interrupt(int irq, FAR void *context, FAR void *arg); -static int tiva_timer6b_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer6a_interrupt(int irq, FAR void *context, + FAR void *arg); +static int tiva_timer6b_interrupt(int irq, FAR void *context, + FAR void *arg); #endif #ifdef CONFIG_TIVA_TIMER7 -static int tiva_timer7a_interrupt(int irq, FAR void *context, FAR void *arg); -static int tiva_timer7b_interrupt(int irq, FAR void *context, FAR void *arg); +static int tiva_timer7a_interrupt(int irq, FAR void *context, + FAR void *arg); +static int tiva_timer7b_interrupt(int irq, FAR void *context, + FAR void *arg); #endif #endif /* CONFIG_TIVA_TIMER_16BIT */ @@ -196,9 +215,10 @@ static int tiva_input_time_mode16(struct tiva_gptmstate_s *priv, const struct tiva_timer16config_s *timer, int tmndx); #endif #ifdef CONFIG_TIVA_TIMER16_PWM -static uint32_t tiva_pwm16_sel_event(struct tiva_gptmstate_s *priv, - const struct tiva_timer16config_s *timer, - int tmndx); +static uint32_t +tiva_pwm16_sel_event(struct tiva_gptmstate_s *priv, + const struct tiva_timer16config_s *timer, + int tmndx); #endif #ifdef CONFIG_TIVA_TIMER16_PWM static int tiva_pwm_mode16(struct tiva_gptmstate_s *priv, @@ -222,12 +242,18 @@ static int tiva_timer16_configure(struct tiva_gptmstate_s *priv, static const struct tiva_gptmattr_s g_gptm0_attr = { .base = TIVA_TIMER0_BASE, - .irq = { TIVA_IRQ_TIMER0A, TIVA_IRQ_TIMER0B }, + .irq = + { + TIVA_IRQ_TIMER0A, TIVA_IRQ_TIMER0B + }, #ifdef CONFIG_TIVA_TIMER_32BIT .handler32 = tiva_gptm0_interrupt, #endif #ifdef CONFIG_TIVA_TIMER_16BIT - .handler16 = { tiva_timer0a_interrupt, tiva_timer0b_interrupt }, + .handler16 = + { + tiva_timer0a_interrupt, tiva_timer0b_interrupt + }, #endif }; @@ -238,12 +264,18 @@ static struct tiva_gptmstate_s g_gptm0_state; static const struct tiva_gptmattr_s g_gptm1_attr = { .base = TIVA_TIMER1_BASE, - .irq = { TIVA_IRQ_TIMER1A, TIVA_IRQ_TIMER1B }, + .irq = + { + TIVA_IRQ_TIMER1A, TIVA_IRQ_TIMER1B + }, #ifdef CONFIG_TIVA_TIMER_32BIT .handler32 = tiva_gptm1_interrupt, #endif #ifdef CONFIG_TIVA_TIMER_16BIT - .handler16 = { tiva_timer1a_interrupt, tiva_timer1b_interrupt }, + .handler16 = + { + tiva_timer1a_interrupt, tiva_timer1b_interrupt + }, #endif }; @@ -254,12 +286,18 @@ static struct tiva_gptmstate_s g_gptm1_state; static const struct tiva_gptmattr_s g_gptm2_attr = { .base = TIVA_TIMER2_BASE, - .irq = { TIVA_IRQ_TIMER2A, TIVA_IRQ_TIMER2B }, + .irq = + { + TIVA_IRQ_TIMER2A, TIVA_IRQ_TIMER2B + }, #ifdef CONFIG_TIVA_TIMER_32BIT .handler32 = tiva_gptm2_interrupt, #endif #ifdef CONFIG_TIVA_TIMER_16BIT - .handler16 = { tiva_timer2a_interrupt, tiva_timer2b_interrupt }, + .handler16 = + { + tiva_timer2a_interrupt, tiva_timer2b_interrupt + }, #endif }; @@ -270,12 +308,18 @@ static struct tiva_gptmstate_s g_gptm2_state; static const struct tiva_gptmattr_s g_gptm3_attr = { .base = TIVA_TIMER3_BASE, - .irq = { TIVA_IRQ_TIMER3A, TIVA_IRQ_TIMER3B }, + .irq = + { + TIVA_IRQ_TIMER3A, TIVA_IRQ_TIMER3B + }, #ifdef CONFIG_TIVA_TIMER_32BIT .handler32 = tiva_gptm3_interrupt, #endif #ifdef CONFIG_TIVA_TIMER_16BIT - .handler16 = { tiva_timer3a_interrupt, tiva_timer3b_interrupt }, + .handler16 = + { + tiva_timer3a_interrupt, tiva_timer3b_interrupt + }, #endif }; @@ -286,12 +330,18 @@ static struct tiva_gptmstate_s g_gptm3_state; static const struct tiva_gptmattr_s g_gptm4_attr = { .base = TIVA_TIMER4_BASE, - .irq = { TIVA_IRQ_TIMER4A, TIVA_IRQ_TIMER4B }, + .irq = + { + TIVA_IRQ_TIMER4A, TIVA_IRQ_TIMER4B + }, #ifdef CONFIG_TIVA_TIMER_32BIT .handler32 = tiva_gptm4_interrupt, #endif #ifdef CONFIG_TIVA_TIMER_16BIT - .handler16 = { tiva_timer4a_interrupt, tiva_timer4b_interrupt }, + .handler16 = + { + tiva_timer4a_interrupt, tiva_timer4b_interrupt + }, #endif }; @@ -302,12 +352,18 @@ static struct tiva_gptmstate_s g_gptm4_state; static const struct tiva_gptmattr_s g_gptm5_attr = { .base = TIVA_TIMER5_BASE, - .irq = { TIVA_IRQ_TIMER5A, TIVA_IRQ_TIMER5B }, + .irq = + { + TIVA_IRQ_TIMER5A, TIVA_IRQ_TIMER5B + }, #ifdef CONFIG_TIVA_TIMER_32BIT .handler32 = tiva_gptm5_interrupt, #endif #ifdef CONFIG_TIVA_TIMER_16BIT - .handler16 = { tiva_timer5a_interrupt, tiva_timer5b_interrupt }, + .handler16 = + { + tiva_timer5a_interrupt, tiva_timer5b_interrupt + }, #endif }; @@ -318,12 +374,18 @@ static struct tiva_gptmstate_s g_gptm5_state; static const struct tiva_gptmattr_s g_gptm6_attr = { .base = TIVA_TIMER6_BASE, - .irq = { TIVA_IRQ_TIMER6A, TIVA_IRQ_TIMER6B }, + .irq = + { + TIVA_IRQ_TIMER6A, TIVA_IRQ_TIMER6B + }, #ifdef CONFIG_TIVA_TIMER_32BIT .handler32 = tiva_gptm6_interrupt, #endif #ifdef CONFIG_TIVA_TIMER_16BIT - .handler16 = { tiva_timer6a_interrupt, tiva_timer6b_interrupt }, + .handler16 = + { + tiva_timer6a_interrupt, tiva_timer6b_interrupt + }, #endif }; @@ -334,12 +396,18 @@ static struct tiva_gptmstate_s g_gptm6_state; static const struct tiva_gptmattr_s g_gptm7_attr = { .base = TIVA_TIMER7_BASE, - .irq = { TIVA_IRQ_TIMER7A, TIVA_IRQ_TIMER7B }, + .irq = + { + TIVA_IRQ_TIMER7A, TIVA_IRQ_TIMER7B + }, #ifdef CONFIG_TIVA_TIMER_32BIT .handler32 = tiva_gptm7_interrupt, #endif #ifdef CONFIG_TIVA_TIMER_16BIT - .handler16 = { tiva_timer7a_interrupt, tiva_timer7b_interrupt }, + .handler16 = + { + tiva_timer7a_interrupt, tiva_timer7b_interrupt + }, #endif }; @@ -412,7 +480,8 @@ static bool tiva_timer_checkreg(struct tiva_gptmstate_s *priv, bool wr, * ****************************************************************************/ -static uint32_t tiva_getreg(struct tiva_gptmstate_s *priv, unsigned int offset) +static uint32_t tiva_getreg(struct tiva_gptmstate_s *priv, + unsigned int offset) { uintptr_t regaddr = priv->attr->base + offset; uint32_t regval = getreg32(regaddr); @@ -460,7 +529,8 @@ static void tiva_putreg(struct tiva_gptmstate_s *priv, unsigned int offset, * ****************************************************************************/ -static void tiva_modifyreg(struct tiva_gptmstate_s *priv, unsigned int offset, +static void tiva_modifyreg(struct tiva_gptmstate_s *priv, + unsigned int offset, uint32_t clrbits, uint32_t setbits) { #ifdef CONFIG_TIVA_TIMER_REGDEBUG @@ -623,7 +693,9 @@ static int tiva_timer16_interrupt(struct tiva_gptmstate_s *priv, int tmndx) DEBUGASSERT(priv && priv->attr && priv->config && (unsigned)tmndx < 2); - /* Read the masked interrupt status, masking out bits only for this timer. */ + /* Read the masked interrupt status, + * masking out bits only for this timer. + */ intmask = tmndx ? TIMERB_INTS : TIMERA_INTS; status = tiva_getreg(priv, TIVA_TIMER_MIS_OFFSET) & intmask; @@ -780,8 +852,9 @@ static int tiva_timer7b_interrupt(int irq, FAR void *context, FAR void *arg) ****************************************************************************/ #ifdef CONFIG_TIVA_TIMER32_PERIODIC -static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv, - const struct tiva_timer32config_s *timer) +static int +tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv, + const struct tiva_timer32config_s *timer) { uint32_t regval; @@ -798,7 +871,7 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv, * operation. */ - tiva_putreg(priv, TIVA_TIMER_CFG_OFFSET, TIMER_CFG_CFG_32); + tiva_putreg(priv, TIVA_TIMER_CFG_OFFSET, TIMER_CFG_CFG_32); /* 3. Configure the TAMR field in the GPTM Timer n Mode Register * (GPTMTAMR): @@ -864,15 +937,15 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv, /* Enable snapshot mode? * - * In periodic, snap-shot mode (TnMR field is 0x2 and the TnSNAPS bit is - * set in the GPTMTnMR register), the value of the timer at the time-out - * event is loaded into the GPTMTnR register and the value of the - * prescaler is loaded into the GPTMTnPS register. The free-running - * counter value is shown in the GPTMTnV register. In this manner, - * software can determine the time elapsed from the interrupt assertion - * to the ISR entry by examining the snapshot values and the current value - * of the free-running timer. Snapshot mode is not available when the - * timer is configured in one-shot mode. + * In periodic, snap-shot mode (TnMR field is 0x2 and the TnSNAPS bit is + * set in the GPTMTnMR register), the value of the timer at the time-out + * event is loaded into the GPTMTnR register and the value of the + * prescaler is loaded into the GPTMTnPS register. The free-running + * counter value is shown in the GPTMTnV register. In this manner, + * software can determine the time elapsed from the interrupt assertion + * to the ISR entry by examining the snapshot values and the current value + * of the free-running timer. Snapshot mode is not available when the + * timer is configured in one-shot mode. * * TODO: Not implemented */ @@ -894,6 +967,7 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv, tiva_putreg(priv, TIVA_TIMER_TAMR_OFFSET, regval); /* Enable and configure ADC trigger outputs */ + if (TIMER_ISADCTIMEOUT(timer) || TIMER_ISADCMATCH(timer)) { #ifdef CONFIG_ARCH_CHIP_TM4C129 @@ -988,9 +1062,10 @@ static int tiva_oneshot_periodic_mode32(struct tiva_gptmstate_s *priv, ****************************************************************************/ #ifdef CONFIG_TIVA_TIMER16_PERIODIC -static int tiva_oneshot_periodic_mode16(struct tiva_gptmstate_s *priv, - const struct tiva_timer16config_s *timer, - int tmndx) +static int +tiva_oneshot_periodic_mode16(struct tiva_gptmstate_s *priv, + const struct tiva_timer16config_s *timer, + int tmndx) { unsigned int regoffset; uint32_t regval; @@ -1047,10 +1122,11 @@ static int tiva_oneshot_periodic_mode16(struct tiva_gptmstate_s *priv, * register. If the timer prescaler is used, the prescaler * snapshot is loaded into the GPTM Timer A/B (GPTMTnPR). * TnWOT - GPTM Timer A/B Wait-on-Trigger - * 0: The 16-bit begins counting as soon as it is enabled (default). - * 1: If the 16-bit timer is enabled, it does not begin counting - * until it receives a trigger from the timer in the - * previous position in the daisy chain. + * 0: The 16-bit begins counting as soon as it is enabled + * (default). + * 1: If the 16-bit timer is enabled, it does not begin + * counting until it receives a trigger from the timer in + * the previous position in the daisy chain. * TnINTD - One-shot/Periodic Interrupt Disable * 0: Time-out interrupt functions as normal. * 1: Time-out interrupt are disabled (default). @@ -1078,9 +1154,9 @@ static int tiva_oneshot_periodic_mode16(struct tiva_gptmstate_s *priv, * prescaler is loaded into the GPTMTnPS register. The free-running * counter value is shown in the GPTMTnV register. In this manner, * software can determine the time elapsed from the interrupt assertion - * to the ISR entry by examining the snapshot values and the current value - * of the free-running timer. Snapshot mode is not available when the - * timer is configured in one-shot mode. + * to the ISR entry by examining the snapshot values and the current + * value of the free-running timer. Snapshot mode is not available when + * the timer is configured in one-shot mode. * * TODO: Not implemented */ @@ -1227,7 +1303,7 @@ static int tiva_rtc_mode32(struct tiva_gptmstate_s *priv, * the 32-bit RTC mode. */ - tiva_putreg(priv, TIVA_TIMER_CFG_OFFSET, TIMER_CFG_CFG_RTC); + tiva_putreg(priv, TIVA_TIMER_CFG_OFFSET, TIMER_CFG_CFG_RTC); /* 4. Write the match value to the GPTM Timer n Match Register * (GPTMTnMATCHR). @@ -1286,11 +1362,13 @@ static int tiva_rtc_mode32(struct tiva_gptmstate_s *priv, ****************************************************************************/ #ifdef CONFIG_TIVA_TIMER16_EDGECOUNT -static int tiva_input_edgecount_mode16(struct tiva_gptmstate_s *priv, - const struct tiva_timer16config_s *timer, - int tmndx) +static int +tiva_input_edgecount_mode16(struct tiva_gptmstate_s *priv, + const struct tiva_timer16config_s *timer, + int tmndx) { - /* A timer is configured to Input Edge-Count mode by the following sequence: + /* A timer is configured to Input Edge-Count mode by the following + * sequence: * * 1. Ensure the timer is disabled (the TnEN bit is cleared) before making * any changes. @@ -1457,9 +1535,10 @@ static int tiva_input_time_mode16(struct tiva_gptmstate_s *priv, ****************************************************************************/ #ifdef CONFIG_TIVA_TIMER16_PWM -static uint32_t tiva_pwm16_sel_event(struct tiva_gptmstate_s *priv, - const struct tiva_timer16config_s *timer, - int tmndx) +static uint32_t +tiva_pwm16_sel_event(struct tiva_gptmstate_s *priv, + const struct tiva_timer16config_s *timer, + int tmndx) { /* For PWM interrupt edge selection, we can interrupt on positive edge * (TIMER_CTL_TnEVENT_POS), negative edge (TIMER_CTL_TnEVENT_NEG), or both @@ -1473,6 +1552,7 @@ static uint32_t tiva_pwm16_sel_event(struct tiva_gptmstate_s *priv, /* When interrupting on both edges, it doesn't matter if PWM output * is inverted. */ + return tmndx ? TIMER_CTL_TBEVENT_BOTH : TIMER_CTL_TAEVENT_BOTH; } @@ -1557,7 +1637,8 @@ static int tiva_pwm_mode16(struct tiva_gptmstate_s *priv, regoffset = tmndx ? TIVA_TIMER_TBMR_OFFSET : TIVA_TIMER_TAMR_OFFSET; clrbits = TIMER_TnMR_TnMR_MASK | TIMER_TnMR_TnCMR | TIMER_TnMR_TnAMS; - setbits = TIMER_TnMR_TnMR_PERIODIC | TIMER_TnMR_TnCMR_EDGECOUNT | TIMER_TnMR_TnAMS_PWM; + setbits = TIMER_TnMR_TnMR_PERIODIC | TIMER_TnMR_TnCMR_EDGECOUNT | + TIMER_TnMR_TnAMS_PWM; tiva_modifyreg(priv, regoffset, clrbits, setbits); /* 4. Configure the output state of the PWM signal (whether or not it is @@ -1596,12 +1677,13 @@ static int tiva_pwm_mode16(struct tiva_gptmstate_s *priv, tiva_modifyreg(priv, regoffset, 0, TIMER_TnMR_TnPWMIE); /* 6. Set PWM period: This is a 24-bit value. Put the high byte (bits 16 - * through 23) in the prescaler register (TIVA_TIMER_TnPR_OFFSET). Put the - * low word (bits 0 through 15) in the interval load register + * through 23) in the prescaler register (TIVA_TIMER_TnPR_OFFSET). + * Put the low word (bits 0 through 15) in the interval load register * (TIVA_TIMER_TnILR_OFFSET). * - * NOTE: This is done when tiva_timer16pwm_setperiodduty() is called. - * That must be done by other logic, prior to starting the clock running. + * NOTE: + * This is done when tiva_timer16pwm_setperiodduty() is called. That + * must be done by other logic, prior to starting the clock running. * * The following note was here before implementation of this function * was written: @@ -1624,12 +1706,13 @@ static int tiva_pwm_mode16(struct tiva_gptmstate_s *priv, */ /* 7. Set PWM duty cycle: This is a 24-bit value. Put the high byte (bits - * 16 through 23) in the prescale match register (TIVA_TIMER_TnPMR_OFFSET). - * Put the low word (bits 0 through 16) in the match register - * (TIVA_TIMER_TnMATCHR_OFFSET). + * 16 through 23) in the prescale match register + * (TIVA_TIMER_TnPMR_OFFSET). Put the low word (bits 0 through 16) in + * the match register (TIVA_TIMER_TnMATCHR_OFFSET). * - * NOTE: This is done when tiva_timer16pwm_setperiodduty() is called. - * That must be done by other logic, prior to starting the clock running. + * NOTE: + * This is done when tiva_timer16pwm_setperiodduty() is called. That + * must be done by other logic, prior to starting the clock running. * Once the period and initial duty cycle are set, the duty cycle can * be changed at any time by calling tiva_timer16pwm_setduty(). */ @@ -1768,6 +1851,7 @@ TIMER_HANDLE tiva_gptm_configure(const struct tiva_gptmconfig_s *config) { #ifdef CONFIG_TIVA_TIMER0 case 0: + /* Enable GPTM0 clocking and power */ attr = &g_gptm0_attr; @@ -1903,8 +1987,9 @@ TIMER_HANDLE tiva_gptm_configure(const struct tiva_gptmconfig_s *config) priv->clkin = ALTCLK_FREQUENCY; #else - tmrinfo("tiva_gptm_configure: Error: alternate clock only available on TM4C129 devices\n"); - return (TIMER_HANDLE)NULL; + tmrinfo("tiva_gptm_configure:"); + tmrinfo(" Error: alternate clock only available on TM4C129 devices\n"); + return (TIMER_HANDLE)NULL; #endif /* CONFIG_ARCH_CHIP_TM4C129 */ } else @@ -1950,7 +2035,8 @@ TIMER_HANDLE tiva_gptm_configure(const struct tiva_gptmconfig_s *config) ret = irq_attach(attr->irq[TIMER16A], attr->handler16[TIMER16A], NULL); if (ret == OK) { - ret = irq_attach(attr->irq[TIMER16B], attr->handler16[TIMER16B], NULL); + ret = irq_attach(attr->irq[TIMER16B], + attr->handler16[TIMER16B], NULL); } if (ret == OK) @@ -2060,7 +2146,8 @@ void tiva_gptm_release(TIMER_HANDLE handle) * ****************************************************************************/ -void tiva_gptm_putreg(TIMER_HANDLE handle, unsigned int offset, uint32_t value) +void tiva_gptm_putreg(TIMER_HANDLE handle, + unsigned int offset, uint32_t value) { DEBUGASSERT(handle); tiva_putreg((struct tiva_gptmstate_s *)handle, offset, value); @@ -2079,8 +2166,8 @@ void tiva_gptm_putreg(TIMER_HANDLE handle, unsigned int offset, uint32_t value) * offset - The offset to the timer register to be written * * Returned Value: - * The 32-bit value read at the provided offset into the timer register base - * address. + * The 32-bit value read at the provided offset into the timer register + * base address. * ****************************************************************************/ @@ -2159,8 +2246,8 @@ void tiva_timer32_start(TIMER_HANDLE handle) * Name: tiva_timer16_start * * Description: - * After tiva_gptm_configure() has been called to configure 16-bit timer(s), - * this function must be called to start one 16-bit timer. + * After tiva_gptm_configure() has been called to configure 16-bit + * timer(s), this function must be called to start one 16-bit timer. * * Input Parameters: * handle - The handle value returned by tiva_gptm_configure() @@ -2363,9 +2450,10 @@ uint32_t tiva_timer16_counter(TIMER_HANDLE handle, int tmndx) } else { - /* We are counting down. The prescaler contains the least-significant - * bits of the count. Sample these registers until we are assured that - * there is no roll-over from the counter to the counter register. + /* We are counting down. + * The prescaler contains the least-significant bits of the count. + * Sample these registers until we are assured that there is no + * roll-over from the counter to the counter register. */ do @@ -2488,6 +2576,7 @@ void tiva_timer32_setinterval(TIMER_HANDLE handle, uint32_t interval) /* Clearing the TACINTD bit allows the time-out interrupt to be * generated as normal */ + moder = base + TIVA_TIMER_TAMR_OFFSET; modev1 = getreg32(moder); modev2 = modev1 & ~TIMER_TnMR_TnCINTD; @@ -2558,7 +2647,8 @@ void tiva_timer32_setinterval(TIMER_HANDLE handle, uint32_t interval) ****************************************************************************/ #ifdef CONFIG_TIVA_TIMER_16BIT -void tiva_timer16_setinterval(TIMER_HANDLE handle, uint16_t interval, int tmndx) +void tiva_timer16_setinterval(TIMER_HANDLE handle, + uint16_t interval, int tmndx) { struct tiva_gptmstate_s *priv = (struct tiva_gptmstate_s *)handle; const struct tiva_gptm16config_s *config; @@ -2739,7 +2829,8 @@ uint32_t tiva_timer32_remaining(TIMER_HANDLE handle) * timeout event (the value in the GPTMTAILR, the timer reloads * with zero. * - * Get the current timer interval value */ + * Get the current timer interval value + */ interval = tiva_getreg(priv, TIVA_TIMER_TAILR_OFFSET); @@ -2970,7 +3061,6 @@ void tiva_timer32_relmatch(TIMER_HANDLE handle, uint32_t relmatch) #endif /* CONFIG_ARCH_CHIP_TM4C129 */ tmrinfo("%08x<-%08x\n", base + TIVA_TIMER_IMR_OFFSET, priv->imr); #endif /* CONFIG_TIVA_TIMER_REGDEBUG */ - } #endif /* CONFIG_TIVA_TIMER32_PERIODIC */ @@ -3273,7 +3363,8 @@ void tiva_timer16pwm_setperiodduty(TIMER_HANDLE handle, uint32_t period, /* Enable the capture mode event interrupt at the timer peripheral. * The interrupt will not fire until enabled at the NVIC. That will be - * done when tiva_timer16_start() is called. */ + * done when tiva_timer16_start() is called. + */ if (toints) { diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h index 6aa143d9208..af04ad585a4 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi2_refsys.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,24 +37,24 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI2_REFSYS_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI2_REFSYS_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" #include "hardware/tiva_ddi.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* ADI2 REFSYS Register Offsets *************************************************************************************/ +/* ADI2 REFSYS Register Offsets *********************************************/ #define TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET 0x0000 #define TIVA_ADI2_REFSYS_SOCLDOCTL0_OFFSET 0x0002 @@ -66,7 +67,7 @@ #define TIVA_ADI2_REFSYS_HPOSCCTL1_OFFSET 0x000b #define TIVA_ADI2_REFSYS_HPOSCCTL2_OFFSET 0x000c -/* ADI2 REFSYS Register Addresses ***********************************************************************************/ +/* ADI2 REFSYS Register Addresses *******************************************/ #define TIVA_ADI2_REFSYS_REFSYSCTL0 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET) #define TIVA_ADI2_REFSYS_SOCLDOCTL0 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL0_OFFSET) @@ -79,7 +80,9 @@ #define TIVA_ADI2_REFSYS_HPOSCCTL1 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL1_OFFSET) #define TIVA_ADI2_REFSYS_HPOSCCTL2 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL2_OFFSET) -/* Offsets may also be used in conjunction with access as described in cc13x0_ddi.h */ +/* Offsets may also be used in conjunction with access as described in + * cc13x0_ddi.h + */ #define TIVA_ADI2_REFSYS_DIR (TIVA_ADI2_BASE + TIVA_DDI_DIR_OFFSET) #define TIVA_ADI2_REFSYS_SET (TIVA_ADI2_BASE + TIVA_DDI_SET_OFFSET) @@ -88,7 +91,7 @@ #define TIVA_ADI2_REFSYS_MASK8B (TIVA_ADI2_BASE + TIVA_DDI_MASK8B_OFFSET) #define TIVA_ADI2_REFSYS_MASK16B (TIVA_ADI2_BASE + TIVA_DDI_MASK16B_OFFSET) -/* ADI2 REFSYS Bitfield Definitions *********************************************************************************/ +/* ADI2 REFSYS Bitfield Definitions *****************************************/ /* TIVA_ADI2_REFSYS_REFSYSCTL0 */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h index 075f039347e..2a1a11246f2 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_adi3_refsys.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,24 +37,24 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI3_REFSYS_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_ADI3_REFSYS_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" #include "hardware/tiva_ddi.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* ADI3 REFSYS Register Offsets *************************************************************************************/ +/* ADI3 REFSYS Register Offsets *********************************************/ #define TIVA_ADI3_REFSYS_SPARE0_OFFSET 0x0001 /* Analog Test Control */ #define TIVA_ADI3_REFSYS_REFSYSCTL0_OFFSET 0x0002 @@ -67,7 +68,7 @@ #define TIVA_ADI3_REFSYS_DCDCCTL4_OFFSET 0x000a #define TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET 0x000b -/* ADI3 REFSYS Register Addresses ***********************************************************************************/ +/* ADI3 REFSYS Register Addresses *******************************************/ #define TIVA_ADI3_REFSYS_SPARE0 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_SPARE0_OFFSET) #define TIVA_ADI3_REFSYS_REFSYSCTL0 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_REFSYSCTL0_OFFSET) @@ -81,7 +82,9 @@ #define TIVA_ADI3_REFSYS_DCDCCTL4 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL4_OFFSET) #define TIVA_ADI3_REFSYS_DCDCCTL5 (TIVA_ADI3_BASE + TIVA_ADI3_REFSYS_DCDCCTL5_OFFSET) -/* Offsets may also be used in conjunction with access as described in cc13x0_ddi.h */ +/* Offsets may also be used in conjunction with access as described in + * cc13x0_ddi.h + */ #define TIVA_ADI3_REFSYS_DIR (TIVA_ADI3_BASE + TIVA_DDI_DIR_OFFSET) #define TIVA_ADI3_REFSYS_SET (TIVA_ADI3_BASE + TIVA_DDI_SET_OFFSET) @@ -90,7 +93,7 @@ #define TIVA_ADI3_REFSYS_MASK8B (TIVA_ADI3_BASE + TIVA_DDI_MASK8B_OFFSET) #define TIVA_ADI3_REFSYS_MASK16B (TIVA_ADI3_BASE + TIVA_DDI_MASK16B_OFFSET) -/* ADI3 REFSYS Bitfield Definitions *********************************************************************************/ +/* ADI3 REFSYS Bitfield Definitions *****************************************/ /* TIVA_ADI3_REFSYS_SPARE0 */ @@ -182,6 +185,7 @@ # define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_TYPICAL (5 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Typical voltage after trim voltage 1.71V */ # define ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_MAX (21 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Max voltage 1.96V */ # define ADI3_REFS */YS_DCDCCTL0_VDDR_TRIM_MIN (22 << ADI3_REFSYS_DCDCCTL0_VDDR_TRIM_SHIFT) /* Min voltage 1.47V */ + #define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT (5) /* Bits 5-7: Set charge and re-charge current level */ /* 2's complement encoding */ #define ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_MASK (7 << ADI3_REFSYS_DCDCCTL0_GLDO_ISRC_SHIFT) @@ -200,6 +204,7 @@ # define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_TYPICAL (nn << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) /* Typical voltage after trim voltage 1.52V */ # define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_MAX (nn << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) /* Max voltage 1.96V */ # define ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_MIN (nn << ADI3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_SHIFT) /* Min voltage 1.47V */ + #define ADI3_REFSYS_DCDCCTL1_VDDR_OK_HYST (1 << 5) /* Bit 5: Increase the hysteresis for when VDDR is considered ok */ /* 0: Hysteresis = 60mV; 1: Hysteresis = 70mV */ #define ADI3_REFSYS_DCDCCTL1_IPTAT_TRIM_SHIFT (6) /* Bits 6-7: Trim GLDO bias current */ @@ -221,6 +226,7 @@ # define ADI3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE (2 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* Pass transistor gate voltage connected to test bus */ # define ADI3_REFSYS_DCDCCTL2_TESTSEL_IB1U (4 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* 1uA bias current connected to test bus */ # define ADI3_REFSYS_DCDCCTL2_TESTSEL_VDDROK (8 << ADI3_REFSYS_DCDCCTL2_TESTSEL_SHIFT) /* VDDR_OK connected to test bus */ + #define ADI3_REFSYS_DCDCCTL2_BIAS_DIS (1 << 4) /* Bit 4: Disable dummy bias current */ #define ADI3_REFSYS_DCDCCTL2_TEST_VDDR (1 << 5) /* Bit 5: Connect VDDR to ATEST bus */ #define ADI3_REFSYS_DCDCCTL2_TURNON_EA_SW (1 << 6) /* Bit 6: Turns on GLDO error amp switch */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_batmon.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_batmon.h index cab60d4cd3e..3b8ef152284 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_batmon.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_batmon.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_batmon.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a compatible + * BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_BATMON_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_BATMON_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* AON BATMON Register Offsets **************************************************************************************/ +/* AON BATMON Register Offsets **********************************************/ #define TIVA_AON_BATMON_CTL_OFFSET 0x0000 #define TIVA_AON_BATMON_MEASCFG_OFFSET 0x0004 @@ -68,7 +69,7 @@ #define TIVA_AON_BATMON_TEMP_OFFSET 0x0030 /* Temperature */ #define TIVA_AON_BATMON_TEMPUPD_OFFSET 0x0034 /* Temperature Update */ -/* AON BATMON Register Addresses ************************************************************************************/ +/* AON BATMON Register Addresses ********************************************/ #define TIVA_AON_BATMON_CTL (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_CTL_OFFSET) #define TIVA_AON_BATMON_MEASCFG (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_MEASCFG_OFFSET) @@ -84,7 +85,7 @@ #define TIVA_AON_BATMON_TEMP (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMP_OFFSET) #define TIVA_AON_BATMON_TEMPUPD (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPUPD_OFFSET) -/* AON BATMON Register Bitfield Definitions *************************************************************************/ +/* AON BATMON Register Bitfield Definitions *********************************/ /* AON_BATMON_CTL */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_ioc.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_ioc.h index ba825a37839..6caca560609 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_ioc.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_ioc.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_ioc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_IOC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_IOC_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* AON IOC Register Offsets *****************************************************************************************/ +/* AON IOC Register Offsets *************************************************/ #define TIVA_AON_IOC_IOSTRMIN_OFFSET 0x0000 #define TIVA_AON_IOC_IOSTRMED_OFFSET 0x0004 @@ -61,7 +62,7 @@ #define TIVA_AON_IOC_CLK32KCTL_OFFSET 0x0010 /* SCLK_LF External Output Control */ #define TIVA_AON_IOC_TCKCTL_OFFSET 0x0014 /* TCK IO Pin Control */ -/* AON IOC Register Addresses ***************************************************************************************/ +/* AON IOC Register Addresses ***********************************************/ #define TIVA_AON_IOC_IOSTRMIN (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMIN_OFFSET) #define TIVA_AON_IOC_IOSTRMED (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMED_OFFSET) @@ -69,7 +70,7 @@ #define TIVA_AON_IOC_IOCLATCH (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOCLATCH_OFFSET) #define TIVA_AON_IOC_CLK32KCTL (TIVA_AON_IOC_BASE + TIVA_AON_IOC_CLK32KCTL_OFFSET) -/* AON IOC Bitfield Definitions *************************************************************************************/ +/* AON IOC Bitfield Definitions *********************************************/ /* TIVA_AON_IOC_IOSTRMIN */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_rtc.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_rtc.h index bd1c7f623b6..db68ac8e03c 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_rtc.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_rtc.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_rtc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_RTC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_RTC_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* AON RTC Register Offsets *****************************************************************************************/ +/* AON RTC Register Offsets *************************************************/ #define TIVA_AON_RTC_CTL_OFFSET 0x0000 /* Control */ #define TIVA_AON_RTC_EVFLAGS_OFFSET 0x0004 /* Event Flags, RTC Status */ @@ -67,7 +68,7 @@ #define TIVA_AON_RTC_CH1CAPT_OFFSET 0x0028 /* Channel 1 Capture Value */ #define TIVA_AON_RTC_SYNC_OFFSET 0x002c /* AON Synchronization */ -/* AON RTC Register Addresses ***************************************************************************************/ +/* AON RTC Register Addresses ***********************************************/ #define TIVA_AON_RTC_CTL (TIVA_AON_RTC_BASE + TIVA_AON_RTC_CTL_OFFSET) #define TIVA_AON_RTC_EVFLAGS (TIVA_AON_RTC_BASE + TIVA_AON_RTC_EVFLAGS_OFFSET) @@ -82,7 +83,7 @@ #define TIVA_AON_RTC_CH1CAPT (TIVA_AON_RTC_BASE + TIVA_AON_RTC_CH1CAPT_OFFSET) #define TIVA_AON_RTC_SYNC (TIVA_AON_RTC_BASE + TIVA_AON_RTC_SYNC_OFFSET) -/* AON RTC Bitfield Definitions *************************************************************************************/ +/* AON RTC Bitfield Definitions *********************************************/ /* TIVA_AON_RTC_CTL */ @@ -106,6 +107,7 @@ # define AON_RTC_CTL_EV_DELAY_D112 (11 << AON_RTC_CTL_EV_DELAY_SHIFT) /* Delay by 112 clock cycles */ # define AON_RTC_CTL_EV_DELAY_D128 (12 << AON_RTC_CTL_EV_DELAY_SHIFT) /* Delay by 128 clock cycles */ # define AON_RTC_CTL_EV_DELAY_D144 (13 << AON_RTC_CTL_EV_DELAY_SHIFT) /* Delay by 144 clock cycles */ + #define AON_RTC_CTL_COMB_EV_MASK_SHIFT (16) /* Bits 16-18: Select how delayed event form combined events */ #define AON_RTC_CTL_COMB_EV_MASK_MASK (7 << AON_RTC_CTL_COMB_EV_MASK_SHIFT) # define AON_RTC_CTL_COMB_EV_MASK_NONE (0 << AON_RTC_CTL_COMB_EV_MASK_SHIFT) /* No event for combined event */ @@ -120,7 +122,9 @@ #define AON_RTC_EVFLAGS_CH2 (1 << 16) /* Bit 16: Channel 2 event flag */ /* TIVA_AON_RTC_SEC (32-bit value, units of seconds) */ + /* TIVA_AON_RTC_SUBSEC (32-bit value, b32 fractional seconds) */ + /* TIVA_AON_RTC_SUBSECINC (32-bit value) */ /* TIVA_AON_RTC_CHCTL */ @@ -128,14 +132,19 @@ #define AON_RTC_CHCTL_CH0_EN (1 << 0) /* Bit 0: RTC Channel 0 enable */ #define AON_RTC_CHCTL_CH1_EN (1 << 8) /* Bit 8: RTC Channel 1 enable */ #define AON_RTC_CHCTL_CH1_CAPT_EN (1 << 9) /* Bit 9: Channel 1 mode */ + # define AON_RTC_CHCTL_CH1_CAPT_CMP (0) /* Compare mode */ # define AON_RTC_CHCTL_CH1_CAPT_CAPT AON_RTC_CHCTL_CH1_CAPT_EN /* Capture mode */ + #define AON_RTC_CHCTL_CH2_EN (1 << 16) /* Bit 16: RTC Channel 2 Enable */ #define AON_RTC_CHCTL_CH2_CONT_EN (1 << 18) /* Bit 18: Enable Channel 2 Continuous Operation */ /* TIVA_AON_RTC_CH0CMP (32-bit value) */ + /* TIVA_AON_RTC_CH1CMP (32-bit value) */ + /* TIVA_AON_RTC_CH2CMP (32-bit value) */ + /* TIVA_AON_RTC_CH2CMPINC (32-bit value) */ /* TIVA_AON_RTC_CH1CAPT */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_sysctl.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_sysctl.h index dc1c46c9adc..dd4e278288e 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_sysctl.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_sysctl.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_sysctl.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,35 +37,35 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_SYSCTL_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_SYSCTL_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* AON SYSCTL Register Offsets **************************************************************************************/ +/* AON SYSCTL Register Offsets **********************************************/ #define TIVA_AON_SYSCTL_PWRCTL_OFFSET 0x0000 /* Power Management */ #define TIVA_AON_SYSCTL_RESETCTL_OFFSET 0x0004 /* Reset Management */ #define TIVA_AON_SYSCTL_SLEEPCTL_OFFSET 0x0008 /* Sleep Mode */ -/* AON SYSCTL Register Addresses ************************************************************************************/ +/* AON SYSCTL Register Addresses ********************************************/ #define TIVA_AON_SYSCTL_PWRCTL (TIVA_AON_SYSCTL_BASE + TIVA_AON_SYSCTL_PWRCTL_OFFSET) #define TIVA_AON_SYSCTL_RESETCTL (TIVA_AON_SYSCTL_BASE + TIVA_AON_SYSCTL_RESETCTL_OFFSET) #define TIVA_AON_SYSCTL_SLEEPCTL (TIVA_AON_SYSCTL_BASE + TIVA_AON_SYSCTL_SLEEPCTL_OFFSET) -/* AON SYSCTL Register Bitfield Definitions *************************************************************************/ +/* AON SYSCTL Register Bitfield Definitions *********************************/ /* AON_SYSCTL_PWRCTL */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_wuc.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_wuc.h index 904ff3bc0ef..efdfb64cacc 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_wuc.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_wuc.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_aon_wuc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_WUC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AON_WUC_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* AON SYSCTL Register Offsets **************************************************************************************/ +/* AON SYSCTL Register Offsets **********************************************/ #define TIVA_AON_WUC_MCUCLK_OFFSET 0x0000 /* MCU Clock Management */ #define TIVA_AON_WUC_AUXCLK_OFFSET 0x0004 /* AUX Clock Management */ @@ -69,7 +70,7 @@ #define TIVA_AON_WUC_JTAGCFG_OFFSET 0x0040 /* JTAG Configuration */ #define TIVA_AON_WUC_JTAGUSERCODE_OFFSET 0x0044 /* JTAG USERCODE */ -/* AON SYSCTL Register Addresses ************************************************************************************/ +/* AON SYSCTL Register Addresses ********************************************/ #define TIVA_AON_WUC_MCUCLK (TIVA_AON_WUC_BASE + TIVA_AON_WUC_MCUCLK_OFFSET) #define TIVA_AON_WUC_AUXCLK (TIVA_AON_WUC_BASE + TIVA_AON_WUC_AUXCLK_OFFSET) @@ -86,7 +87,7 @@ #define TIVA_AON_WUC_JTAGCFG (TIVA_AON_WUC_BASE + TIVA_AON_WUC_JTAGCFG_OFFSET) #define TIVA_AON_WUC_JTAGUSERCODE (TIVA_AON_WUC_BASE + TIVA_AON_WUC_JTAGUSERCODE_OFFSET) -/* AON SYSCTL Register Bitfield Definitions *************************************************************************/ +/* AON SYSCTL Register Bitfield Definitions *********************************/ /* AON_WUC_MCUCLK */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_wuc.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_wuc.h index 4dc4cf64ede..cbedf16088c 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_wuc.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_wuc.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_aux_wuc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AUX_WUC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_AUX_WUC_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* AUX WUC Register Offsets *****************************************************************************************/ +/* AUX WUC Register Offsets *************************************************/ #define TIVA_AUX_WUC_MODCLKEN0_OFFSET 0x0000 /* Module Clock Enable */ #define TIVA_AUX_WUC_PWROFFREQ_OFFSET 0x0004 /* Power Off Request */ @@ -74,7 +75,7 @@ #define TIVA_AUX_WUC_AUXIOLATCH_OFFSET 0x0054 /* AUX Input Output Latch */ #define TIVA_AUX_WUC_MODCLKEN1_OFFSET 0x005c /* Module Clock Enable 1 */ -/* AUX WUC Register Addresses ***************************************************************************************/ +/* AUX WUC Register Addresses ***********************************************/ #define TIVA_AUX_WUC_MODCLKEN0 (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_MODCLKEN0_OFFSET) #define TIVA_AUX_WUC_PWROFFREQ (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_PWROFFREQ_OFFSET) @@ -96,7 +97,7 @@ #define TIVA_AUX_WUC_AUXIOLATCH (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_AUXIOLATCH_OFFSET) #define TIVA_AUX_WUC_MODCLKEN1 (TIVA_AUX_WUC_BASE + TIVA_AUX_WUC_MODCLKEN1_OFFSET) -/* AUX WUC Register Bitfield Definitions ****************************************************************************/ +/* AUX WUC Register Bitfield Definitions ************************************/ /* AUX_WUC_MODCLKEN0 */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ccfg.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ccfg.h index 0f6f08ea174..79f4e1617b1 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ccfg.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ccfg.h @@ -1,4 +1,4 @@ -/************************************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_ccfg.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -37,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_CCFG_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_CCFG_H -/************************************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/************************************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************************************/ + ****************************************************************************/ -/* CCFG Register Offsets ************************************************************************************/ +/* CCFG Register Offsets ****************************************************/ #define TIVA_CCFG_EXT_LF_CLK_OFFSET 0x0fa8 /* Extern LF clock configuration */ #define TIVA_CCFG_MODE_CONF_1_OFFSET 0x0fac /* Mode Configuration 1 */ @@ -78,7 +78,7 @@ #define TIVA_CCFG_CCFG_PROT_95_64_OFFSET 0x0ff8 /* Protect Sectors 64-95 */ #define TIVA_CCFG_CCFG_PROT_127_96_OFFSET 0x0ffc /* Protect Sectors 96-127 */ -/* CCFG Register Addresses **********************************************************************************/ +/* CCFG Register Addresses **************************************************/ #define TIVA_CCFG_EXT_LF_CLK (TIVA_CCFG_BASE + TIVA_CCFG_EXT_LF_CLK_OFFSET) #define TIVA_CCFG_MODE_CONF_1 (TIVA_CCFG_BASE + TIVA_CCFG_MODE_CONF_1_OFFSET) @@ -103,7 +103,7 @@ #define TIVA_CCFG_CCFG_PROT_95_64 (TIVA_CCFG_BASE + TIVA_CCFG_CCFG_PROT_95_64_OFFSET) #define TIVA_CCFG_CCFG_PROT_127_96 (TIVA_CCFG_BASE + TIVA_CCFG_CCFG_PROT_127_96_OFFSET) -/* CCFG Bifield Definitions *********************************************************************************/ +/* CCFG Bifield Definitions *************************************************/ /* TIVA_CCFG_EXT_LF_CLK */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h index b954dbc43e2..ea25a12576a 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_ddi0_osc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,24 +37,24 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_DDI0_OSC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_DDI0_OSC_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" #include "hardware/tiva_ddi.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* DDI0 OSC Register Offsets ****************************************************************************************/ +/* DDI0 OSC Register Offsets ************************************************/ #define TIVA_DDI0_OSC_CTL0_OFFSET 0x0000 /* Control 0 */ #define TIVA_DDI0_OSC_CTL1_OFFSET 0x0004 /* Control 1 */ @@ -72,7 +73,8 @@ #define TIVA_DDI0_OSC_STAT1_OFFSET 0x0038 /* Status 1 */ #define TIVA_DDI0_OSC_STAT2_OFFSET 0x003c /* Status 2 */ -/* DDI0 OSC Register Addresses **************************************************************************************/ +/* DDI0 OSC Register Addresses **********************************************/ + /* Direct access */ #define TIVA_DDI0_OSC_CTL0 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_CTL0_OFFSET) @@ -92,7 +94,9 @@ #define TIVA_DDI0_OSC_STAT1 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_STAT1_OFFSET) #define TIVA_DDI0_OSC_STAT2 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_STAT2_OFFSET) -/* Offsets may also be used in conjunction with access as described in cc13x0_ddi.h */ +/* Offsets may also be used in conjunction with access as described in + * cc13x0_ddi.h + */ #define TIVA_DDI0_OSC_DIR (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_DIR_OFFSET) #define TIVA_DDI0_OSC_SET (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET) @@ -101,17 +105,20 @@ #define TIVA_DDI0_OSC_MASK8B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK8B_OFFSET) #define TIVA_DDI0_OSC_MASK16B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK16B_OFFSET) -/* DDI0 OSC Bitfield Definitions ************************************************************************************/ +/* DDI0 OSC Bitfield Definitions ********************************************/ /* DDI0_OSC_CTL0 */ #define DDI0_OSC_CTL0_SCLK_HF_SRC_SEL (1 << 0) /* Bit 0: Source select for sclk_hf */ # define DDI0_OSC_CTL0_SCLK_HF_SRC_RCOSC (0) /* High frequency RCOSC clock */ + # define DDI0_OSC_CTL0_SCLK_HF_SRC_XOSC DDI0_OSC_CTL0_SCLK_HF_SRC_SEL /* High frequency XOSC clock */ + #define DDI0_OSC_CTL0_SCLK_MF_SRC_SEL (1 << 1) /* Bit 1 */ # define DDI0_OSC_CTL0_SCLK_MF_SRC_SEL_RCOSCHFDMF 0 # define DDI0_OSC_CTL0_SCLK_MF_SRC_SEL_XCOSCHFDMF DDI0_OSC_CTL0_SCLK_MF_SRC_SEL /* Medium frequency clock derived * from high frequency XOSC */ + #define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT (2) /* Bits 2-3: Source select for sclk_lf */ #define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_MASK (3 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) # define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF (1 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency clock derived @@ -120,26 +127,31 @@ * from High Frequency RCOSC */ # define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF (2 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency RCOSC */ # define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF (3 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency XOSC */ + #define DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT (5) /* Bits 5-6: Source select for aclk_ref */ #define DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_MASK (3 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) # define DDI0_OSC_CTL0_ACLK_REF_SRC_RCOSCHF (0 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* RCOSC_HF derived (31.25kHz) */ # define DDI0_OSC_CTL0_ACLK_REF_SRC_XOSCHF (1 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* XOSC_HF derived (31.25kHz) */ # define DDI0_OSC_CTL0_ACLK_REF_SRC_RCOSCLF (2 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* RCOSC_LF (32kHz) */ # define DDI0_OSC_CTL0_ACLK_REF_SRC_XOSCLF (3 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* XOSC_LF (32.768kHz) */ + #define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT (7) /* Bits 7-8: ource select for aclk_tdc */ #define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_MASK (3 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) # define DDI0_OSC_CTL0_ACLK_TDC_SRC_RCOSCHF48 (0 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* RCOSC_HF (48MHz) */ # define DDI0_OSC_CTL0_ACLK_TDC_SRC_RCOSCHF24 (1 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* RCOSC_HF (24MHz) */ # define DDI0_OSC_CTL0_ACLK_TDC_SRC_XOSCHF24 (2 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* XOSC_HF (24MHz) */ + #define DDI0_OSC_CTL0_CLK_LOSS_EN (1 << 9) /* Bit 9: Enable SCLK_HF, SCLK_MF and SCLK_LF clock * loss detection and indicators to the system * controller */ #define DDI0_OSC_CTL0_XOSC_LF_DIG_BYPASS (1 << 10) /* Bit 10: Bypass XOSC_LF and use the digital * input clock from AON for the xosc_lf */ + # define DDI0_OSC_CTL0_XOSC_LF_DIG_32KHZ (0) /* Use 32kHz XOSC as xosc_lf * clock source */ # define DDI0_OSC_CTL0_XOSC_LF_DIG_DIGINPUT DDI0_OSC_CTL0_XOSC_LF_DIG_BYPASS /* Use digital input (from AON) * as xosc_lf clock source */ + #define DDI0_OSC_CTL0_XOSC_HF_POWER_MODE (1 << 11) /* Bit 11 */ #define DDI0_OSC_CTL0_RCOSC_LF_TRIMMED (1 << 12) /* Bit 12 */ #define DDI0_OSC_CTL0_HPOSC_MODE_EN (1 << 14) /* Bit 14 */ @@ -326,8 +338,11 @@ #define DDI0_OSC_STAT0_RCOSC_LF_EN (1 << 21) /* Bit 21: RCOSC_LF enable */ #define DDI0_OSC_STAT0_RCOSC_HF_EN (1 << 22) /* Bit 22: RSOSC_HF enable */ #define DDI0_OSC_STAT0_SCLK_HF_SRC (1 << 28) /* Bit 28: Indicates source for sclk_hf */ + # define DDI0_OSC_STAT0_SCLK_HF_SRC_RCOSC (0) /* High frequency RCOSC clock */ + # define DDI0_OSC_STAT0_SCLK_HF_SRC_XOSC DDI0_OSC_STAT0_SCLK_HF_SRC /* High frequency XOSC */ + #define DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT (29) /* Bits 29-30: Indicates source for the sclk_lf */ #define DDI0_OSC_STAT0_SCLK_LF_SRC_MASK (3 << DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT) # define DDI0_OSC_STAT0_SCLK_LF_SRC(n) ((uint32_t)(n) << DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT) diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h index d034769ef63..fa51b85c6cd 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_fcfg1.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_FCFG1_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_FCFG1_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* FCFG1 Register Offsets *******************************************************************************************/ +/* FCFG1 Register Offsets ***************************************************/ #define TIVA_FCFG1_MISC_CONF_1_OFFSET 0x00a0 /* Misc configurations */ #define TIVA_FCFG1_MISC_CONF_2_OFFSET 0x00a4 @@ -137,7 +138,7 @@ #define TIVA_FCFG1_PWD_CURR_110C_OFFSET 0x03b4 /* Power Down Current Control 110C */ #define TIVA_FCFG1_PWD_CURR_125C_OFFSET 0x03b8 /* Power Down Current Control 125C */ -/* FCFG1 Register Register Addresses ********************************************************************************/ +/* FCFG1 Register Register Addresses ****************************************/ #define TIVA_FCFG1_MISC_CONF_1 (TIVA_FCFG1_BASE + TIVA_FCFG1_MISC_CONF_1_OFFSET) #define TIVA_FCFG1_MISC_CONF_2 (TIVA_FCFG1_BASE + TIVA_FCFG1_MISC_CONF_2_OFFSET) @@ -222,7 +223,7 @@ #define TIVA_FCFG1_PWD_CURR_110C (TIVA_FCFG1_BASE + TIVA_FCFG1_PWD_CURR_110C_OFFSET) #define TIVA_FCFG1_PWD_CURR_125C (TIVA_FCFG1_BASE + TIVA_FCFG1_PWD_CURR_125C_OFFSET) -/* FCFG1 Bitfield Definitions ***************************************************************************************/ +/* FCFG1 Bitfield Definitions ***********************************************/ /* TIVA_FCFG1_MISC_CONF_1 */ @@ -512,10 +513,21 @@ #define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_MASK (15 << FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_SHIFT) # define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM(n) ((uint32_t)(n) << FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_SHIFT) -/* TIVA_FCFG1_SHDW_DIE_ID_0 (32-bit value, Shadow of the DIE_ID_0 register in eFuse row number 3) */ -/* TIVA_FCFG1_SHDW_DIE_ID_1 (32-bit value, Shadow of the DIE_ID_1 register in eFuse row number 4) */ -/* TIVA_FCFG1_SHDW_DIE_ID_2 (32-bit value, Shadow of the DIE_ID_2 register in eFuse row number 5) */ -/* TIVA_FCFG1_SHDW_DIE_ID_3 (32-bit value, Shadow of the DIE_ID_3 register in eFuse row number 6) */ +/* TIVA_FCFG1_SHDW_DIE_ID_0 (32-bit value, + * Shadow of the DIE_ID_0 register in eFuse row number 3) + */ + +/* TIVA_FCFG1_SHDW_DIE_ID_1 (32-bit value, + * Shadow of the DIE_ID_1 register in eFuse row number 4) + */ + +/* TIVA_FCFG1_SHDW_DIE_ID_2 (32-bit value, + * Shadow of the DIE_ID_2 register in eFuse row number 5) + */ + +/* TIVA_FCFG1_SHDW_DIE_ID_3 (32-bit value, + * Shadow of the DIE_ID_3 register in eFuse row number 6) + */ /* TIVA_FCFG1_SHDW_OSC_BIAS_LDO_TRIM */ @@ -716,6 +728,7 @@ # define FCFG1_USER_ID_PROTOCOL_RF4CE (2 << FCFG1_USER_ID_PROTOCOL_SHIFT) /* RF4CE */ # define FCFG1_USER_ID_PROTOCOL_802154 (4 << FCFG1_USER_ID_PROTOCOL_SHIFT) /* Zigbee/6lowpan */ # define FCFG1_USER_ID_PROTOCOL_PROP (8 << FCFG1_USER_ID_PROTOCOL_SHIFT) /* Proprietary */ + #define FCFG1_USER_ID_PKG_SHIFT (16) /* Bits 16-18: Package type */ #define FCFG1_USER_ID_PKG_MASK (7 << FCFG1_USER_ID_PKG_SHIFT) # define FCFG1_USER_ID_PKG_RHG (0 << FCFG1_USER_ID_PKG_SHIFT) /* 4x4mm QFN (RHB) package */ @@ -723,6 +736,7 @@ # define FCFG1_USER_ID_PKG_RGZ (2 << FCFG1_USER_ID_PKG_SHIFT) /* 7x7mm QFN (RGZ) package */ # define FCFG1_USER_ID_PKG_WSP (3 << FCFG1_USER_ID_PKG_SHIFT) /* Wafer sale package (naked die) */ # define FCFG1_USER_ID_PKG_QFNWF (5 << FCFG1_USER_ID_PKG_SHIFT) /* 7x7mm QFN package with Wettable Flanks */ + #define FCFG1_USER_ID_SEQUENCE_SHIFT (19) /* Bits 19-22: Sequence */ #define FCFG1_USER_ID_SEQUENCE_MASK (15 << FCFG1_USER_ID_SEQUENCE_SHIFT) # define FCFG1_USER_ID_SEQUENCE(n) ((uint32_t)(n) << FCFG1_USER_ID_SEQUENCE_SHIFT) @@ -812,10 +826,21 @@ #define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_MASK (15 << FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_SHIFT) # define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD(n) ((uint32_t)(n) << FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_SHIFT) -/* TIVA_FCFG1_MAC_BLE_0 (32-bit value, The first 32-bits of the 64-bit MAC BLE address) */ -/* TIVA_FCFG1_MAC_BLE_1 (32-bit value, The last 32-bits of the 64-bit MAC BLE address) */ -/* TIVA_FCFG1_MAC_15_4_0 (32-bit value, The first 32-bits of the 64-bit MAC 15.4 address) */ -/* TIVA_FCFG1_MAC_15_4_1 (32-bit value, The last 32-bits of the 64-bit MAC 15.4 address) */ +/* TIVA_FCFG1_MAC_BLE_0 + * (32-bit value, The first 32-bits of the 64-bit MAC BLE address) + */ + +/* TIVA_FCFG1_MAC_BLE_1 + * (32-bit value, The last 32-bits of the 64-bit MAC BLE address) + */ + +/* TIVA_FCFG1_MAC_15_4_0 + * (32-bit value, The first 32-bits of the 64-bit MAC 15.4 address) + */ + +/* TIVA_FCFG1_MAC_15_4_1 + * (32-bit value, The last 32-bits of the 64-bit MAC 15.4 address) + */ /* TIVA_FCFG1_FLASH_OTP_DATA4 */ @@ -858,8 +883,8 @@ /* TIVA_FCFG1_MISC_TRIM */ -#define FCFG1_MISC_TRIM_TEMPVSLOPE_SHIFT (0) /* Bits 0-7: TEMP slope with battery voltage, in -degrees C */ +#define FCFG1_MISC_TRIM_TEMPVSLOPE_SHIFT (0) /* Bits 0-7: TEMP slope with battery voltage, + * degrees in C */ #define FCFG1_MISC_TRIM_TEMPVSLOPE_MASK (0xff << FCFG1_MISC_TRIM_TEMPVSLOPE_SHIFT) # define FCFG1_MISC_TRIM_TEMPVSLOPE(n) ((uint32_t)(n) << FCFG1_MISC_TRIM_TEMPVSLOPE_SHIFT) @@ -899,7 +924,9 @@ degrees C */ #define FCFG1_ICEPICK_DEVICE_ID_PG_REV_MASK (15 << FCFG1_ICEPICK_DEVICE_ID_PG_REV_SHIFT) # define FCFG1_ICEPICK_DEVICE_ID_PG_REV(n) ((uint32_t)(n) << FCFG1_ICEPICK_DEVICE_ID_PG_REV_SHIFT) -/* TIVA_FCFG1_FCFG1_REVISION (32-bit value, The revision number of the FCFG1 layout) */ +/* TIVA_FCFG1_FCFG1_REVISION + * (32-bit value, The revision number of the FCFG1 layout) + */ /* TIVA_FCFG1_MISC_OTP_DATA */ @@ -1100,7 +1127,7 @@ degrees C */ #define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N (1 << 17) /* Bit 17 */ #define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_SHIFT (18) /* Bits 18-21 */ #define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_MASK (15 << FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_SHIFT) -# define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM(n) ((uint32_t)(n) << FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_SHIFT) +# define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM(n) ((uint32_t)(n) << FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_SHIFT) /* TIVA_FCFG1_VOLT_TRIM */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_flash.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_flash.h index 79d7e8eb2e0..5280b41af18 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_flash.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_flash.h @@ -1,10 +1,11 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_flash.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_FLASH_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_FLASH_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* FLASH Register Offsets ***************************************************************************/ +/* FLASH Register Offsets ***************************************************/ #define TIVA_FLASH_STAT_OFFSET 0x001c /* FMC and Efuse Status */ #define TIVA_FLASH_CFG_OFFSET 0x0024 @@ -178,7 +179,7 @@ #define TIVA_FLASH_FCFG_B7_START_OFFSET 0x242c #define TIVA_FLASH_FCFG_B0_SSIZE0_OFFSET 0x2430 -/* FLASH Register Addresses *************************************************************************/ +/* FLASH Register Addresses *************************************************/ #define TIVA_FLASH_STAT (TIVA_FLASH_BASE + TIVA_FLASH_STAT_OFFSET) #define TIVA_FLASH_CFG (TIVA_FLASH_BASE + TIVA_FLASH_CFG_OFFSET) @@ -304,7 +305,7 @@ #define TIVA_FLASH_FCFG_B7_START (TIVA_FLASH_BASE + TIVA_FLASH_FCFG_B7_START_OFFSET) #define TIVA_FLASH_FCFG_B0_SSIZE0 (TIVA_FLASH_BASE + TIVA_FLASH_FCFG_B0_SSIZE0_OFFSET) -/* FLASH Bitfield Definitions ***********************************************************************/ +/* FLASH Bitfield Definitions ***********************************************/ /* TIVA_FLASH_STAT */ @@ -494,6 +495,7 @@ #define FLASH_TWOBIT_FROMN_MASK (0x7fffffff << FLASH_TWOBIT_FROMN_SHIFT) /* TIVA_FLASH_SELFTESTCYC (32-bit value) */ + /* TIVA_FLASH_SELFTESTSIGN (32-bit value) */ /* TIVA_FLASH_FRDCTL */ @@ -726,12 +728,19 @@ #define FLASH_FTCTL_WDATA_BLK_CLR (1 << 16) /* Bit 16 */ /* TIVA_FLASH_FWPWRITE0 (32-bit value) */ + /* TIVA_FLASH_FWPWRITE1 (32-bit value) */ + /* TIVA_FLASH_FWPWRITE2 (32-bit value) */ + /* TIVA_FLASH_FWPWRITE3 (32-bit value) */ + /* TIVA_FLASH_FWPWRITE4 (32-bit value) */ + /* TIVA_FLASH_FWPWRITE5 (32-bit value) */ + /* TIVA_FLASH_FWPWRITE6 (32-bit value) */ + /* TIVA_FLASH_FWPWRITE7 (32-bit value) */ /* TIVA_FLASH_FWPWRITE_ECC */ @@ -991,10 +1000,15 @@ #define FLASH_FSM_EXECUTE_SUSPEND_NOW_MASK (15 << FLASH_FSM_EXECUTE_SUSPEND_NOW_SHIFT) /* TIVA_FLASH_FSM_SECTOR1 (32-bit value) */ + /* TIVA_FLASH_FSM_SECTOR2 (32-bit value) */ + /* TIVA_FLASH_FSM_BSLE0 (32-bit value) */ + /* TIVA_FLASH_FSM_BSLE1 (32-bit value) */ + /* TIVA_FLASH_FSM_BSLP0 (32-bit value) */ + /* TIVA_FLASH_FSM_BSLP1 (32-bit value) */ /* TIVA_FLASH_FCFG_BANK */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_gpio.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_gpio.h index f3b4eae8039..e72ba755a04 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_gpio.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_gpio.h @@ -1,10 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_gpio.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a compatible + * BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_GPIO_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* GPIO Register Offsets ************************************************************/ +/* GPIO Register Offsets ****************************************************/ #define TIVA_GPIO_DOUT_PIN_OFFSET(n) ((n) & ~3) # define TIVA_GPIO_DOUT_PIN3_0_OFFSET 0x0000 /* Data Out 0 to 3 */ @@ -71,7 +72,7 @@ #define TIVA_GPIO_DOE_OFFSET 0x00d0 /* Data Output Enable for DIO 0 to 31 */ #define TIVA_GPIO_EVFLAGS_OFFSET 0x00e0 /* Event Register for DIO 0 to 31 */ -/* GPIO Register Addresses **********************************************************/ +/* GPIO Register Addresses **************************************************/ #define TIVA_GPIO_DOUT_PIN_BASE(n) (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN_OFFSET(n)) # define TIVA_GPIO_DOUT_PIN3_0 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN3_0_OFFSET) @@ -90,7 +91,7 @@ #define TIVA_GPIO_DOE (TIVA_GPIO_BASE + TIVA_GPIO_DOE_OFFSET) #define TIVA_GPIO_EVFLAGS (TIVA_GPIO_BASE + TIVA_GPIO_EVFLAGS_OFFSET) -/* GPIO Register Bitfield Definitions ***********************************************/ +/* GPIO Register Bitfield Definitions ***************************************/ /* Data Out n to n + 3 */ @@ -125,16 +126,16 @@ #define GPIO_EVFLAGS(n) (1 << (n)) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_GPIO_H */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_i2c.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_i2c.h index 4f086104162..9bae6c5f7ca 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_i2c.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_i2c.h @@ -1,10 +1,11 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_i2c.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,16 +37,16 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_I2C_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_I2C_H -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* I2C register offsets *********************************************************************/ +/* I2C register offsets *****************************************************/ #define TIVA_I2C_SOAR_OFFSET 0x0000 /* Slave Own Address */ #define TIVA_I2C_SSTAT_OFFSET 0x0004 /* Slave Status */ @@ -67,7 +68,7 @@ #define TIVA_I2C_MICR_OFFSET 0x081c /* Master Interrupt Clear */ #define TIVA_I2C_MCR_OFFSET 0x0820 /* Master Configuration */ -/* I2C register addresses *******************************************************************/ +/* I2C register addresses ***************************************************/ #define TIVA_I2C0_SOAR (TIVA_I2C0_BASE + TIVA_I2C_SOAR_OFFSET) #define TIVA_I2C0_SSTAT (TIVA_I2C0_BASE + TIVA_I2C_SSTAT_OFFSET) @@ -89,7 +90,7 @@ #define TIVA_I2C0_MICR (TIVA_I2C0_BASE + TIVA_I2C_MICR_OFFSET) #define TIVA_I2C0_MCR (TIVA_I2C0_BASE + TIVA_I2C_MCR_OFFSET) -/* I2C bitfield definitions *****************************************************************/ +/* I2C bitfield definitions *************************************************/ /* Slave Own Address */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ioc.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ioc.h index 58daf03f77c..a410d8168e9 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ioc.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ioc.h @@ -1,10 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_ioc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a compatible + * BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,25 +37,25 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2IOC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2IOC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define TIVA_NDIO 32 /* DIO0-31 */ -/* IOC register offsets ************************************************************/ +/* IOC register offsets *****************************************************/ #define TIVA_IOC_IOCFG_OFFSET(n) ((n) << 2) # define TIVA_IOC_IOCFG0_OFFSET 0x0000 /* Configuration of DIO0 */ @@ -90,7 +91,7 @@ # define TIVA_IOC_IOCFG30_OFFSET 0x0078 /* Configuration of DIO30 */ # define TIVA_IOC_IOCFG31_OFFSET 0x007c /* Configuration of DIO31 */ -/* IOC register addresses **********************************************************/ +/* IOC register addresses ***************************************************/ #define TIVA_IOC_IOCFG(n) (TIVA_IOC_BASE + TIVA_IOC_IOCFG_OFFSET(n)) # define TIVA_IOC_IOCFG0 (TIVA_IOC_BASE + TIVA_IOC_IOCFG0_OFFSET) @@ -126,36 +127,41 @@ # define TIVA_IOC_IOCFG30 (TIVA_IOC_BASE + TIVA_IOC_IOCFG30_OFFSET) # define TIVA_IOC_IOCFG31 (TIVA_IOC_BASE + TIVA_IOC_IOCFG31_OFFSET) -/* IOC register bit settings *******************************************************/ +/* IOC register bit settings ************************************************/ /* Common bitfield for all DIO configuration registers */ #define IOC_IOCFG_PORTID_SHIFT (0) /* Bits 0-5: Selects DIO usage */ #define IOC_IOCFG_PORTID_MASK (0x3f << IOC_IOCFG_PORTID_SHIFT) # define IOC_IOCFG_PORTID(n) ((uint32_t)(n) << IOC_IOCFG_PORTID_SHIFT) /* See PORT ID definitions */ + #define IOC_IOCFG_IOSTR_SHIFT (8) /* Bits 8-9: I/O drive strength */ #define IOC_IOCFG_IOSTR_MASK (3 << IOC_IOCFG_IOSTR_SHIFT) # define IOC_IOCFG_IOSTR_AUTO (0 << IOC_IOCFG_IOSTR_SHIFT) /* Automatic drive strength */ # define IOC_IOCFG_IOSTR_MIN (1 << IOC_IOCFG_IOSTR_SHIFT) /* Minimum drive strength */ # define IOC_IOCFG_IOSTR_MED (2 << IOC_IOCFG_IOSTR_SHIFT) /* Medium drive strength */ # define IOC_IOCFG_IOSTR_MAX (3 << IOC_IOCFG_IOSTR_SHIFT) /* Maximum drive strength */ + #define IOC_IOCFG_IOCURR_SHIFT (10) /* Bits 10-11: I/O current mode */ #define IOC_IOCFG_IOCURR_MASK (3 << IOC_IOCFG_IOCURR_SHIFT) # define IOC_IOCFG_IOCURR_2MA (0 << IOC_IOCFG_IOCURR_SHIFT) /* Extended-Current (EC) mode */ # define IOC_IOCFG_IOCURR_4MA (1 << IOC_IOCFG_IOCURR_SHIFT) /* High-Current (HC) mode */ # define IOC_IOCFG_IOCURR_8MA (2 << IOC_IOCFG_IOCURR_SHIFT) /* Low-Current (LC) mode */ + #define IOC_IOCFG_SLEW_RED (1 << 12) /* Bit 12: Reduces output slew rate */ #define IOC_IOCFG_PULLCTL_SHIFT (13) /* Bits 13-14: Pull Control */ #define IOC_IOCFG_PULLCTL_MASK (3 << IOC_IOCFG_PULLCTL_SHIFT) # define IOC_IOCFG_PULLCTL_DIS (3 << IOC_IOCFG_PULLCTL_SHIFT) /* No pull */ # define IOC_IOCFG_PULLCTL_DWN (1 << IOC_IOCFG_PULLCTL_SHIFT) /* Pull down */ # define IOC_IOCFG_PULLCTL_UP (2 << IOC_IOCFG_PULLCTL_SHIFT) /* Pull up */ + #define IOC_IOCFG_EDGEDET_SHIFT (16) /* Bits 16-17: Enable edge events generation */ #define IOC_IOCFG_EDGEDET_MASK (3 << IOC_IOCFG_EDGEDET_SHIFT) # define IOC_IOCFG_EDGEDET_NONE (0 << IOC_IOCFG_EDGEDET_SHIFT) /* No edge detection */ # define IOC_IOCFG_EDGEDET_NEG (1 << IOC_IOCFG_EDGEDET_SHIFT) /* Negative edge detection */ # define IOC_IOCFG_EDGEDET_POS (2 << IOC_IOCFG_EDGEDET_SHIFT) /* Positive edge detection */ # define IOC_IOCFG_EDGEDET_BOTH (3 << IOC_IOCFG_EDGEDET_SHIFT) /* Both edge detection */ + #define IOC_IOCFG_EDGE_IRQEN (1 << 18) /* Bit 18: Enable interrupt generation */ #define IOC_IOCFG_IOMODE_SHIFT (24) /* Bits 24-26: I/O Mode */ #define IOC_IOCFG_IOMODE_MASK (7 << IOC_IOCFG_IOMODE_SHIFT) @@ -165,12 +171,14 @@ # define IOC_IOCFG_IOMODE_OPENDRINV (5 << IOC_IOCFG_IOMODE_SHIFT) /* Open drain, inverted I/O */ # define IOC_IOCFG_IOMODE_OPENSRC (6 << IOC_IOCFG_IOMODE_SHIFT) /* Open source */ # define IOC_IOCFG_IOMODE_OPENSRCINV (7 << IOC_IOCFG_IOMODE_SHIFT) /* Open source, inverted I/O */ + #define IOC_IOCFG_WUCFG_SHIFT (27) /* Bits 27-28: Wakeup Configuration */ #define IOC_IOCFG_WUCFG_MASK (3 << IOC_IOCFG_WUCFG_SHIFT) # define IOC_IOCFG_WUCFG_NONE (0 << IOC_IOCFG_WUCFG_SHIFT) /* 0, 1: Wakeup disabled */ # define IOC_IOCFG_WUCFG_ENABLE (2 << IOC_IOCFG_WUCFG_SHIFT) /* 2, 3: Wakeup enabled */ # define IOC_IOCFG_WUCFG_WAKEUPL (2 << IOC_IOCFG_WUCFG_SHIFT) /* 2: Wakeup on transition low */ # define IOC_IOCFG_WUCFG_WEKUPH (3 << IOC_IOCFG_WUCFG_SHIFT) /* 3: Wakeup on transition high */ + #define IOC_IOCFG_IE (1 << 29) /* Bit 29: Input enable */ #define IOC_IOCFG_HYSTEN (1 << 30) /* Bit 30: Input hysteresis enable */ @@ -219,16 +227,16 @@ #define IOC_IOCFG_PORTID_RFC_SMI_CLOUT 0x37 #define IOC_IOCFG_PORTID_RFC_SMI_CLIN 0x38 -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2IOC_H */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_prcm.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_prcm.h index 12f5a4a871f..cade8f7a0e5 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_prcm.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_prcm.h @@ -1,10 +1,11 @@ -/**************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_prcm.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_PRCM_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_PRCM_H -/**************************************************************************************************** +/**************************************************************************** * Included Files - ****************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/**************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ****************************************************************************************************/ + ****************************************************************************/ -/* PRCM Register Offsets ****************************************************************************/ +/* PRCM Register Offsets ****************************************************/ #define TIVA_PRCM_INFRCLKDIVR_OFFSET 0x0000 /* Infrastructure Clock Division Factor For Run Mode */ #define TIVA_PRCM_INFRCLKDIVS_OFFSET 0x0004 /* Infrastructure Clock Division Factor For Sleep Mode */ @@ -114,7 +115,7 @@ #define TIVA_PRCM_PWRPROFSTAT_OFFSET 0x01e0 /* Power Profiler Register */ #define TIVA_PRCM_RAMRETEN_OFFSET 0x0224 /* Memory Retention Control */ -/* PRCM Register Addresses *************************************************************************/ +/* PRCM Register Addresses **************************************************/ #define TIVA_PRCM_INFRCLKDIVR (TIVA_PRCM_BASE + TIVA_PRCM_INFRCLKDIVR_OFFSET) #define TIVA_PRCM_INFRCLKDIVS (TIVA_PRCM_BASE + TIVA_PRCM_INFRCLKDIVS_OFFSET) @@ -176,7 +177,7 @@ #define TIVA_PRCM_PWRPROFSTAT (TIVA_PRCM_BASE + TIVA_PRCM_PWRPROFSTAT_OFFSET) #define TIVA_PRCM_RAMRETEN (TIVA_PRCM_BASE + TIVA_PRCM_RAMRETEN_OFFSET) -/* PRCM Register Bitfield Definitions **************************************************************/ +/* PRCM Register Bitfield Definitions ***************************************/ /* Infrastructure Clock Division Factor For Run Mode */ @@ -322,6 +323,7 @@ # define PRCM_I2SCLKCTL_WCLKPHASE_SINGLE (0 << PRCM_I2SCLKCTL_WCLKPHASE_SHIFT) /* Single phase */ # define PRCM_I2SCLKCTL_WCLKPHASE_DUAL (1 << PRCM_I2SCLKCTL_WCLKPHASE_SHIFT) /* Dual phase */ # define PRCM_I2SCLKCTL_WCLKPHASE_USER (2 << PRCM_I2SCLKCTL_WCLKPHASE_SHIFT) /* User Defined */ + #define PRCM_I2SCLKCTL_POSEDGE (1 << 3) /* Bit 3: Sample/clock on positive edge */ # define PRCM_I2SCLKCTL_NEGEDGE (0) /* Sample/clock on negative edge */ @@ -475,16 +477,16 @@ # define PRCM_RAMRETEN_VIMS_CRAM (2 << PRCM_RAMRETEN_VIMS_SHIFT) #define PRCM_RAMRETEN_RFC (1 << 2) /* Bit 2: RFC SRAM retention enabled */ -/**************************************************************************************************** +/**************************************************************************** * Public Types - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** +/**************************************************************************** * Public Data - ****************************************************************************************************/ + ****************************************************************************/ -/**************************************************************************************************** +/**************************************************************************** * Public Function Prototypes - ****************************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_PRCM_H */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_timer.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_timer.h index da427e5d354..7c255d5a113 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_timer.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_timer.h @@ -1,10 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_timer.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a compatible + * BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,37 +37,37 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_TIMER_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_TIMER_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* TIMER Register Offsets ***********************************************************/ +/* TIMER Register Offsets ***************************************************/ -/* TIMER Register Addresses *********************************************************/ +/* TIMER Register Addresses *************************************************/ -/* TIMER Register Bitfield Definitions **********************************************/ +/* TIMER Register Bitfield Definitions **************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_TIMER_H */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_uart.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_uart.h index 8eece398ed4..9cc681b4d46 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_uart.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_uart.h @@ -1,10 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_uart.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a compatible + * BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_UART_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_UART_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* UART register offsets ************************************************************/ +/* UART register offsets ****************************************************/ #define TIVA_UART_DR_OFFSET 0x0000 /* UART Data */ #define TIVA_UART_RSR_OFFSET 0x0004 /* UART Receive Status */ @@ -82,7 +83,7 @@ #define TIVA_UART_PCELLID2_OFFSET 0x0ff8 /* UART PrimeCell Identification 2 */ #define TIVA_UART_PCELLID3_OFFSET 0x0ffc /* UART PrimeCell Identification 3 */ -/* UART register addresses **********************************************************/ +/* UART register addresses **************************************************/ #define TIVA_UART_BASE(n) (TIVA_UART0_BASE + (n)*0x01000) @@ -118,7 +119,7 @@ # define TIVA_UART0_DMACTL (TIVA_UART0_BASE + TIVA_UART_DMACTL_OFFSET) #endif -/* UART register bit settings *******************************************************/ +/* UART register bit settings ***********************************************/ /* UART Data (DR) */ @@ -255,12 +256,12 @@ #define UART_DMACTL_TXDMAE (1 << 1) /* Bit 1: Transmit DMA Enable */ #define UART_DMACTL_DMAERR (1 << 2) /* Bit 2: DMA on Error */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_UART_H */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_vims.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_vims.h index 518809a7f60..bcedd87948a 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_vims.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_vims.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x0/cc13x0_vims.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,33 +37,33 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_VIMS_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_VIMS_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* VIMS Register Offsets ********************************************************************************************/ +/* VIMS Register Offsets ****************************************************/ #define TIVA_VIMS_STAT_OFFSET 0x0000 /* Status */ #define TIVA_VIMS_CTL_OFFSET 0x0004 /* Control */ -/* VIMS Register Addresses ******************************************************************************************/ +/* VIMS Register Addresses **************************************************/ #define TIVA_VIMS_STAT (TIVA_VIMS_BASE + TIVA_VIMS_STAT_OFFSET) #define TIVA_VIMS_CTL (TIVA_VIMS_BASE + TIVA_VIMS_CTL_OFFSET) -/* VIMS Bitfield Definitions ****************************************************************************************/ +/* VIMS Bitfield Definitions ************************************************/ /* VIMS_STAT */ @@ -71,6 +72,7 @@ # define VIMS_STAT_MODE_GPRAM (0 << VIMS_STAT_MODE_SHIFT) /* VIMS GPRAM mode */ # define VIMS_STAT_MODE_CACHE (1 << VIMS_STAT_MODE_SHIFT) /* VIMS Cache mode */ # define VIMS_STAT_MODE_OFF (3 << VIMS_STAT_MODE_SHIFT) /* VIMS Off mode */ + #define VIMS_STAT_INV (1 << 2) /* Bit 2: Invalidation of caching memory in-progress */ #define VIMS_STAT_MODE_CHANGING (1 << 3) /* Bit 3: VIMS mode change status */ #define VIMS_STAT_SYSBUS_LB_DIS (1 << 4) /* Bit 4: Sysbus flash line buffer control */ @@ -83,6 +85,7 @@ # define VIMS_CTL_MODE_GPRAM (0 << VIMS_CTL_MODE_SHIFT) /* VIMS GPRAM mode */ # define VIMS_CTL_MODE_CACHE (1 << VIMS_CTL_MODE_SHIFT) /* VIMS Cache mode */ # define VIMS_CTL_MODE_OFF (3 << VIMS_CTL_MODE_SHIFT) /* VIMS Off mode */ + #define VIMS_CTL_PREF_EN (1 << 2) /* Bit 2: Tag prefetch control */ #define VIMS_CTL_ARB_CFG (1 << 3) /* Bit 3: Icode/Dcode and sysbus arbitation scheme */ # define VIMS_CTL_ARB_STATIC (0) diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h index aa1bad93004..2cceba71c59 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_adi2_refsys.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,24 +37,24 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_ADI2_REFSYS_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_ADI2_REFSYS_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" #include "hardware/tiva_ddi.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* ADI2 REFSYS Register Offsets *************************************************************************************/ +/* ADI2 REFSYS Register Offsets *********************************************/ #define TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET 0x0000 #define TIVA_ADI2_REFSYS_SOCLDOCTL0_OFFSET 0x0002 @@ -66,7 +67,7 @@ #define TIVA_ADI2_REFSYS_HPOSCCTL1_OFFSET 0x000b #define TIVA_ADI2_REFSYS_HPOSCCTL2_OFFSET 0x000c -/* ADI2 REFSYS Register Addresses ***********************************************************************************/ +/* ADI2 REFSYS Register Addresses *******************************************/ #define TIVA_ADI2_REFSYS_REFSYSCTL0 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_REFSYSCTL0_OFFSET) #define TIVA_ADI2_REFSYS_SOCLDOCTL0 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_SOCLDOCTL0_OFFSET) @@ -79,7 +80,9 @@ #define TIVA_ADI2_REFSYS_HPOSCCTL1 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL1_OFFSET) #define TIVA_ADI2_REFSYS_HPOSCCTL2 (TIVA_ADI2_BASE + TIVA_ADI2_REFSYS_HPOSCCTL2_OFFSET) -/* Offsets may also be used in conjunction with access as described in cc13x2_cc26x2_ddi.h */ +/* Offsets may also be used in conjunction with access as described in + * cc13x2_cc26x2_ddi.h + */ #define TIVA_ADI2_REFSYS_DIR (TIVA_ADI2_BASE + TIVA_DDI_DIR_OFFSET) #define TIVA_ADI2_REFSYS_SET (TIVA_ADI2_BASE + TIVA_DDI_SET_OFFSET) @@ -88,7 +91,7 @@ #define TIVA_ADI2_REFSYS_MASK8B (TIVA_ADI2_BASE + TIVA_DDI_MASK8B_OFFSET) #define TIVA_ADI2_REFSYS_MASK16B (TIVA_ADI2_BASE + TIVA_DDI_MASK16B_OFFSET) -/* ADI2 REFSYS Bitfield Definitions *********************************************************************************/ +/* ADI2 REFSYS Bitfield Definitions *****************************************/ /* TIVA_ADI2_REFSYS_REFSYSCTL0 */ diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_batmon.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_batmon.h index 256395abd01..6ca9ce42982 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_batmon.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_batmon.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_batmon.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AON_BATMON_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AON_BATMON_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* AON BATMON Register Offsets **************************************************************************************/ +/* AON BATMON Register Offsets **********************************************/ #define TIVA_AON_BATMON_CTL_OFFSET 0x0000 #define TIVA_AON_BATMON_MEASCFG_OFFSET 0x0004 @@ -74,7 +75,7 @@ #define TIVA_AON_BATMON_TEMPUL_OFFSET 0x0058 /* Temperature Upper Limit */ #define TIVA_AON_BATMON_TEMPLL_OFFSET 0x005c /* Temperature Lower Limit */ -/* AON BATMON Register Addresses ************************************************************************************/ +/* AON BATMON Register Addresses ********************************************/ #define TIVA_AON_BATMON_CTL (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_CTL_OFFSET) #define TIVA_AON_BATMON_MEASCFG (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_MEASCFG_OFFSET) @@ -96,7 +97,7 @@ #define TIVA_AON_BATMON_TEMPUL (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPUL_OFFSET) #define TIVA_AON_BATMON_TEMPLL (TIVA_AON_BATMON_BASE + TIVA_AON_BATMON_TEMPLL_OFFSET) -/* AON BATMON Register Bitfield Definitions *************************************************************************/ +/* AON BATMON Register Bitfield Definitions *********************************/ /* AON_BATMON_CTL */ diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_ioc.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_ioc.h index c6fa6d8492e..35999b34397 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_ioc.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_ioc.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_ioc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a compatible + * BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AON_IOC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AON_IOC_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* AON IOC Register Offsets *****************************************************************************************/ +/* AON IOC Register Offsets *************************************************/ #define TIVA_AON_IOC_IOSTRMIN_OFFSET 0x0000 #define TIVA_AON_IOC_IOSTRMED_OFFSET 0x0004 @@ -61,7 +62,7 @@ #define TIVA_AON_IOC_CLK32KCTL_OFFSET 0x0010 /* SCLK_LF External Output Control */ #define TIVA_AON_IOC_TCKCTL_OFFSET 0x0014 /* TCK IO Pin Control */ -/* AON IOC Register Addresses ***************************************************************************************/ +/* AON IOC Register Addresses ***********************************************/ #define TIVA_AON_IOC_IOSTRMIN (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMIN_OFFSET) #define TIVA_AON_IOC_IOSTRMED (TIVA_AON_IOC_BASE + TIVA_AON_IOC_IOSTRMED_OFFSET) @@ -70,7 +71,7 @@ #define TIVA_AON_IOC_CLK32KCTL (TIVA_AON_IOC_BASE + TIVA_AON_IOC_CLK32KCTL_OFFSET) #define TIVA_AON_IOC_TCKCTL (TIVA_AON_IOC_BASE + TIVA_AON_IOC_TCKCTL_OFFSET) -/* AON IOC Bitfield Definitions *************************************************************************************/ +/* AON IOC Bitfield Definitions *********************************************/ /* TIVA_AON_IOC_IOSTRMIN */ diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_sysif.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_sysif.h index 534db31377a..c8baa3caa56 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_sysif.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_sysif.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_sysif.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AUX_SYSIF_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_AUX_SYSIF_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* AUX SYSIF Register Offsets ***************************************************************************************/ +/* AUX SYSIF Register Offsets ***********************************************/ #define TIVA_AUX_SYSIF_OPMODEREQ_OFFSET 0x0000 /* Operational Mode Request */ #define TIVA_AUX_SYSIF_OPMODEACK_OFFSET 0x0004 /* Operational Mode Acknowledgement */ @@ -96,7 +97,7 @@ #define TIVA_AUX_SYSIF_TIMER2BRIDGE_OFFSET 0x00b0 /* AUX_TIMER2 Bridge */ #define TIVA_AUX_SYSIF_SWPWRPROF_OFFSET 0x00b4 /* Software Power Profiler */ -/* AUX SYSIF Register Addresses *************************************************************************************/ +/* AUX SYSIF Register Addresses *********************************************/ #define TIVA_AUX_SYSIF_OPMODEREQ (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_OPMODEREQ_OFFSET) #define TIVA_AUX_SYSIF_OPMODEACK (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_OPMODEACK_OFFSET) @@ -140,7 +141,7 @@ #define TIVA_AUX_SYSIF_TIMER2BRIDGE (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_TIMER2BRIDGE_OFFSET) #define TIVA_AUX_SYSIF_SWPWRPROF (TIVA_AUX_SYSIF_BASE + TIVA_AUX_SYSIF_SWPWRPROF_OFFSET) -/* AUX SYSIF Register Bifield Definitions ***************************************************************************/ +/* AUX SYSIF Register Bifield Definitions ***********************************/ /* AUX_SYSIF_OPMODEREQ */ diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h index b4d78bfb08e..bfd137440f9 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h @@ -1,10 +1,11 @@ -/******************************************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a + * compatible BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,24 +37,24 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_DDI0_OSC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_DDI0_OSC_H -/******************************************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" #include "hardware/tiva_ddi.h" -/******************************************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************************************/ + ****************************************************************************/ -/* DDI0 OSC Register Offsets ****************************************************************************************/ +/* DDI0 OSC Register Offsets ************************************************/ #define TIVA_DDI0_OSC_CTL0_OFFSET 0x0000 /* Control 0 */ #define TIVA_DDI0_OSC_CTL1_OFFSET 0x0004 /* Control 1 */ @@ -73,7 +74,8 @@ #define TIVA_DDI0_OSC_STAT1_OFFSET 0x0040 /* Status 1 */ #define TIVA_DDI0_OSC_STAT2_OFFSET 0x0044 /* Status 2 */ -/* DDI0 OSC Register Addresses **************************************************************************************/ +/* DDI0 OSC Register Addresses **********************************************/ + /* Direct access */ #define TIVA_DDI0_OSC_CTL0 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_CTL0_OFFSET) @@ -94,7 +96,9 @@ #define TIVA_DDI0_OSC_STAT1 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_STAT1_OFFSET) #define TIVA_DDI0_OSC_STAT2 (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI0_OSC_STAT2_OFFSET) -/* Offsets may also be used in conjunction with access as described in cc13x2_cc26x2_ddi.h */ +/* Offsets may also be used in conjunction with access as described in + * cc13x2_cc26x2_ddi.h + */ #define TIVA_DDI0_OSC_DIR (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_DIR_OFFSET) #define TIVA_DDI0_OSC_SET (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_SET_OFFSET) @@ -103,13 +107,15 @@ #define TIVA_DDI0_OSC_MASK8B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK8B_OFFSET) #define TIVA_DDI0_OSC_MASK16B (TIVA_AUX_DDI0_OSC_BASE + TIVA_DDI_MASK16B_OFFSET) -/* DDI0 OSC Bitfield Definitions ************************************************************************************/ +/* DDI0 OSC Bitfield Definitions ********************************************/ /* DDI0_OSC_CTL0 */ #define DDI0_OSC_CTL0_SCLK_HF_SRC_SEL (1 << 0) /* Bit 0: Source select for sclk_hf */ # define DDI0_OSC_CTL0_SCLK_HF_SRC_RCOSC (0) /* High frequency RCOSC clock */ + # define DDI0_OSC_CTL0_SCLK_HF_SRC_XOSC DDI0_OSC_CTL0_SCLK_HF_SRC_SEL /* High frequency XOSC clock */ + #define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT (2) /* Bits 2-3: Source select for sclk_lf */ #define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_MASK (3 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) # define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF (1 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency clock derived @@ -118,6 +124,7 @@ * from High Frequency RCOSC */ # define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF (2 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency RCOSC */ # define DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF (3 << DDI0_OSC_CTL0_SCLK_LF_SRC_SEL_SHIFT) /* Low frequency XOSC */ + #define DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT (4) /* Bits 4-6: Source select for aclk_ref */ #define DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_MASK (7 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) # define DDI0_OSC_CTL0_ACLK_REF_SRC_RCOSCHF (0 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* RCOSC_HF derived (31.25kHz) */ @@ -125,20 +132,25 @@ # define DDI0_OSC_CTL0_ACLK_REF_SRC_RCOSCLF (2 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* RCOSC_LF (32kHz) */ # define DDI0_OSC_CTL0_ACLK_REF_SRC_XOSCLF (3 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* XOSC_LF (32.768kHz) */ # define DDI0_OSC_CTL0_ACLK_REF_SRC_RCOSCMF (4 << DDI0_OSC_CTL0_ACLK_REF_SRC_SEL_SHIFT) /* RCOSC_MF (2MHz) */ + #define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT (7) /* Bits 7-8: ource select for aclk_tdc */ #define DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_MASK (3 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) # define DDI0_OSC_CTL0_ACLK_TDC_SRC_RCOSCHF48 (0 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* RCOSC_HF (48MHz) */ # define DDI0_OSC_CTL0_ACLK_TDC_SRC_RCOSCHF24 (1 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* RCOSC_HF (24MHz) */ # define DDI0_OSC_CTL0_ACLK_TDC_SRC_XOSCHF24 (2 << DDI0_OSC_CTL0_ACLK_TDC_SRC_SEL_SHIFT) /* XOSC_HF (24MHz) */ + #define DDI0_OSC_CTL0_CLK_LOSS_EN (1 << 9) /* Bit 9: Enable SCLK_HF, SCLK_MF and SCLK_LF clock * loss detection and indicators to the system * controller */ + #define DDI0_OSC_CTL0_XOSC_LF_DIG_BYPASS (1 << 10) /* Bit 10: Bypass XOSC_LF and use the digital * input clock from AON for the xosc_lf */ + # define DDI0_OSC_CTL0_XOSC_LF_DIG_32KHZ (0) /* Use 32kHz XOSC as xosc_lf * clock source */ # define DDI0_OSC_CTL0_XOSC_LF_DIG_DIGINPUT DDI0_OSC_CTL0_XOSC_LF_DIG_BYPASS /* Use digital input (from AON) * as xosc_lf clock source */ + #define DDI0_OSC_CTL0_XOSC_HF_POWER_MODE (1 << 11) /* Bit 11 */ #define DDI0_OSC_CTL0_RCOSC_LF_TRIMMED (1 << 12) /* Bit 12 */ #define DDI0_OSC_CTL0_HPOSC_MODE_EN (1 << 14) /* Bit 14 */ @@ -264,6 +276,7 @@ # define DDI0_OSC_ATESTCTL_ATEST_RCOSCMF_BIAS (3 << DDI0_OSC_ATESTCTL_ATEST_RCOSCMF_SHIFT) /* ATEST enabled, bias current connected, * ATEST internal to RCOSC_MF enabled * to send out 2MHz clock. */ + #define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT (14) /* Bits 14-15: Test mode control for RCOSC_MF */ #define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_MASK (3 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT) # define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_DISABLE (0 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT) /* Test modes disabled */ @@ -273,6 +286,7 @@ # define DDI0_OSC_ATESTCTL_TEST_RCOSCMF_BOOSTDIS (3 << DDI0_OSC_ATESTCTL_TEST_RCOSCMF_SHIFT) /* Boosted bias current into self * biased inverter + clock qualification * disabled */ + #define DDI0_OSC_ATESTCTL_SCLK_LF_AUX_EN (1 << 31) /* Bit 31: Enable 32 kHz clock to AUX_COMPB */ /* DDI0_OSC_ADCDOUBLERNANOAMPCTL */ @@ -332,6 +346,7 @@ # define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_MIN (8 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_SHIFT) /* minimum current */ # define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_DEFAULT (0 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_SHIFT) /* default current */ # define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_MAX (7 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_SHIFT) /* maximum current */ + #define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_SHIFT (4) /* Bits 4-5: Select fine resistor for frequency adjustment */ #define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_MASK (3 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_SHIFT) # define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_11K (0 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_SHIFT) /* 11kohms, minimum resistance, @@ -340,6 +355,7 @@ # define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_16K (2 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_SHIFT) /* 16kohms */ # define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_20K (3 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_SHIFT) /* 20kohms, max resistance, * min freq */ + #define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_SHIFT (6) /* Bits 6-7: Select coarse resistor for frequency adjustment */ #define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_MASK (3 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_SHIFT) # define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_DEFAULT (0 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_SHIFT) /* 400kohms, default */ @@ -349,6 +365,7 @@ # define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_400KOHM (0 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_SHIFT) /* 400kohms */ # define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_500KOHM (3 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_SHIFT) /* 500kohms */ # define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_600KOHM (2 << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_SHIFT) /* 600kohms */ + #define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL (1 << 8) /* Bit 8: Select alternate regulator type */ #define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_SHIFT (9) /* Bits 9-15: Adjust RCOSC_MF capacitor array */ #define DDI0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_MASK (0x7f << DDI0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_SHIFT) @@ -382,8 +399,11 @@ #define DDI0_OSC_STAT0_RCOSC_LF_EN (1 << 21) /* Bit 21: RCOSC_LF enable */ #define DDI0_OSC_STAT0_RCOSC_HF_EN (1 << 22) /* Bit 22: RSOSC_HF enable */ #define DDI0_OSC_STAT0_SCLK_HF_SRC (1 << 28) /* Bit 28: Indicates source for sclk_hf */ + # define DDI0_OSC_STAT0_SCLK_HF_SRC_RCOSC (0) /* High frequency RCOSC clock */ + # define DDI0_OSC_STAT0_SCLK_HF_SRC_XOSC DDI0_OSC_STAT0_SCLK_HF_SRC /* High frequency XOSC */ + #define DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT (29) /* Bits 29-30: Indicates source for the sclk_lf */ #define DDI0_OSC_STAT0_SCLK_LF_SRC_MASK (3 << DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT) # define DDI0_OSC_STAT0_SCLK_LF_SRC(n) ((uint32_t)(n) << DDI0_OSC_STAT0_SCLK_LF_SRC_SHIFT) diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_gpio.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_gpio.h index f1f19a99d35..8e9fee51c71 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_gpio.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_gpio.h @@ -1,10 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_gpio.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a compatible + * BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_GPIO_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* GPIO Register Offsets ************************************************************/ +/* GPIO Register Offsets ****************************************************/ #define TIVA_GPIO_DOUT_PIN_OFFSET(n) ((n) & ~3) # define TIVA_GPIO_DOUT_PIN3_0_OFFSET 0x0000 /* Data Out 0 to 3 */ @@ -71,7 +72,7 @@ #define TIVA_GPIO_DOE_OFFSET 0x00d0 /* Data Output Enable for DIO 0 to 31 */ #define TIVA_GPIO_EVFLAGS_OFFSET 0x00e0 /* Event Register for DIO 0 to 31 */ -/* GPIO Register Addresses **********************************************************/ +/* GPIO Register Addresses **************************************************/ #define TIVA_GPIO_DOUT_PIN_BASE(n) (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN_OFFSET(n)) # define TIVA_GPIO_DOUT_PIN3_0 (TIVA_GPIO_BASE + TIVA_GPIO_DOUT_PIN3_0_OFFSET) @@ -90,7 +91,7 @@ #define TIVA_GPIO_DOE (TIVA_GPIO_BASE + TIVA_GPIO_DOE_OFFSET) #define TIVA_GPIO_EVFLAGS (TIVA_GPIO_BASE + TIVA_GPIO_EVFLAGS_OFFSET) -/* GPIO Register Bitfield Definitions ***********************************************/ +/* GPIO Register Bitfield Definitions ***************************************/ /* Data Out n to n + 3 */ @@ -125,16 +126,16 @@ #define GPIO_EVFLAGS(n) (1 << (n)) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_GPIO_H */ diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_i2c.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_i2c.h index f6c40ba9715..0119abb74e3 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_i2c.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_i2c.h @@ -1,10 +1,11 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_i2c.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a compatible + * BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,16 +37,16 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_I2C_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_I2C_H -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* I2C register offsets *********************************************************************/ +/* I2C register offsets *****************************************************/ #define TIVA_I2C_SOAR_OFFSET 0x0000 /* Slave Own Address */ #define TIVA_I2C_SSTAT_OFFSET 0x0004 /* Slave Status */ @@ -67,7 +68,7 @@ #define TIVA_I2C_MICR_OFFSET 0x081c /* Master Interrupt Clear */ #define TIVA_I2C_MCR_OFFSET 0x0820 /* Master Configuration */ -/* I2C register addresses *******************************************************************/ +/* I2C register addresses ***************************************************/ #define TIVA_I2C0_SOAR (TIVA_I2C0_BASE + TIVA_I2C_SOAR_OFFSET) #define TIVA_I2C0_SSTAT (TIVA_I2C0_BASE + TIVA_I2C_SSTAT_OFFSET) @@ -89,7 +90,7 @@ #define TIVA_I2C0_MICR (TIVA_I2C0_BASE + TIVA_I2C_MICR_OFFSET) #define TIVA_I2C0_MCR (TIVA_I2C0_BASE + TIVA_I2C_MCR_OFFSET) -/* I2C bitfield definitions *****************************************************************/ +/* I2C bitfield definitions *************************************************/ /* Slave Own Address */ diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ioc.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ioc.h index 3e54c7109dc..ca9cba3b66d 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ioc.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ioc.h @@ -1,10 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ioc.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a compatible + * BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,25 +37,25 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2IOC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2IOC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define TIVA_NDIO 32 /* DIO0-31 */ -/* IOC register offsets ************************************************************/ +/* IOC register offsets *****************************************************/ #define TIVA_IOC_IOCFG_OFFSET(n) ((n) << 2) # define TIVA_IOC_IOCFG0_OFFSET 0x0000 /* Configuration of DIO0 */ @@ -90,7 +91,7 @@ # define TIVA_IOC_IOCFG30_OFFSET 0x0078 /* Configuration of DIO30 */ # define TIVA_IOC_IOCFG31_OFFSET 0x007c /* Configuration of DIO31 */ -/* IOC register addresses **********************************************************/ +/* IOC register addresses ***************************************************/ #define TIVA_IOC_IOCFG(n) (TIVA_IOC_BASE + TIVA_IOC_IOCFG_OFFSET(n)) # define TIVA_IOC_IOCFG0 (TIVA_IOC_BASE + TIVA_IOC_IOCFG0_OFFSET) @@ -126,11 +127,12 @@ # define TIVA_IOC_IOCFG30 (TIVA_IOC_BASE + TIVA_IOC_IOCFG30_OFFSET) # define TIVA_IOC_IOCFG31 (TIVA_IOC_BASE + TIVA_IOC_IOCFG31_OFFSET) -/* IOC register bit settings *******************************************************/ +/* IOC register bit settings ************************************************/ #define IOC_IOCFG_PORTID_SHIFT (0) /* Bits 0-5: Selects DIO usage */ #define IOC_IOCFG_PORTID_MASK (0x3f << IOC_IOCFG_PORTID_SHIFT) # define IOC_IOCFG_PORTID(n) ((uint32_t)(n) << IOC_IOCFG_PORTID_SHIFT) /* See PORT ID definitions */ + #define IOC_IOCFG_IOEV_MCU_WUEN (1 << 6) /* Bit 6: Input edge asserts MCU_WU event */ #define IOC_IOCFG_IOEV_RTCEN (1 << 7) /* Bit 7: Input edge asserts RTC event */ #define IOC_IOCFG_IOSTR_SHIFT (8) /* Bits 8-9: I/O drive strength */ @@ -139,23 +141,27 @@ # define IOC_IOCFG_IOSTR_MIN (1 << IOC_IOCFG_IOSTR_SHIFT) /* Minimum drive strength */ # define IOC_IOCFG_IOSTR_MED (2 << IOC_IOCFG_IOSTR_SHIFT) /* Medium drive strength */ # define IOC_IOCFG_IOSTR_MAX (3 << IOC_IOCFG_IOSTR_SHIFT) /* Maximum drive strength */ + #define IOC_IOCFG_IOCURR_SHIFT (10) /* Bits 10-11: I/O current mode */ #define IOC_IOCFG_IOCURR_MASK (3 << IOC_IOCFG_IOCURR_SHIFT) # define IOC_IOCFG_IOCURR_2MA (0 << IOC_IOCFG_IOCURR_SHIFT) /* Extended-Current (EC) mode */ # define IOC_IOCFG_IOCURR_4MA (1 << IOC_IOCFG_IOCURR_SHIFT) /* High-Current (HC) mode */ # define IOC_IOCFG_IOCURR_8MA (2 << IOC_IOCFG_IOCURR_SHIFT) /* Low-Current (LC) mode */ + #define IOC_IOCFG_SLEW_RED (1 << 12) /* Bit 12: Reduces output slew rate */ #define IOC_IOCFG_PULLCTL_SHIFT (13) /* Bits 13-14: Pull Control */ #define IOC_IOCFG_PULLCTL_MASK (3 << IOC_IOCFG_PULLCTL_SHIFT) # define IOC_IOCFG_PULLCTL_DIS (3 << IOC_IOCFG_PULLCTL_SHIFT) /* No pull */ # define IOC_IOCFG_PULLCTL_DWN (1 << IOC_IOCFG_PULLCTL_SHIFT) /* Pull down */ # define IOC_IOCFG_PULLCTL_UP (2 << IOC_IOCFG_PULLCTL_SHIFT) /* Pull up */ + #define IOC_IOCFG_EDGEDET_SHIFT (16) /* Bits 16-17: Enable edge events generation */ #define IOC_IOCFG_EDGEDET_MASK (3 << IOC_IOCFG_EDGEDET_SHIFT) # define IOC_IOCFG_EDGEDET_NONE (0 << IOC_IOCFG_EDGEDET_SHIFT) /* No edge detection */ # define IOC_IOCFG_EDGEDET_NEG (1 << IOC_IOCFG_EDGEDET_SHIFT) /* Negative edge detection */ # define IOC_IOCFG_EDGEDET_POS (2 << IOC_IOCFG_EDGEDET_SHIFT) /* Positive edge detection */ # define IOC_IOCFG_EDGEDET_BOTH (3 << IOC_IOCFG_EDGEDET_SHIFT) /* Both edge detection */ + #define IOC_IOCFG_EDGE_IRQEN (1 << 18) /* Bit 18: Enable interrupt generation */ #define IOC_IOCFG_IOEV_AON_PROG0 (1 << 21) /* Bit 21: Input edge asserts AON_PROG0 */ #define IOC_IOCFG_IOEV_AON_PROG1 (1 << 22) /* Bit 22: Input edge asserts AON_PROG1 */ @@ -168,12 +174,14 @@ # define IOC_IOCFG_IOMODE_OPENDRINV (5 << IOC_IOCFG_IOMODE_SHIFT) /* Open drain, inverted I/O */ # define IOC_IOCFG_IOMODE_OPENSRC (6 << IOC_IOCFG_IOMODE_SHIFT) /* Open source */ # define IOC_IOCFG_IOMODE_OPENSRCINV (7 << IOC_IOCFG_IOMODE_SHIFT) /* Open source, inverted I/O */ + #define IOC_IOCFG_WUCFG_SHIFT (27) /* Bits 27-28: Wakeup Configuration */ #define IOC_IOCFG_WUCFG_MASK (3 << IOC_IOCFG_WUCFG_SHIFT) # define IOC_IOCFG_WUCFG_NONE (0 << IOC_IOCFG_WUCFG_SHIFT) /* 0, 1: Wakeup disabled */ # define IOC_IOCFG_WUCFG_ENABLE (2 << IOC_IOCFG_WUCFG_SHIFT) /* 2, 3: Wakeup enabled */ # define IOC_IOCFG_WUCFG_WAKEUPL (2 << IOC_IOCFG_WUCFG_SHIFT) /* 2: Wakeup on transition low */ # define IOC_IOCFG_WUCFG_WEKUPH (3 << IOC_IOCFG_WUCFG_SHIFT) /* 3: Wakeup on transition high */ + #define IOC_IOCFG_IE (1 << 29) /* Bit 29: Input enable */ #define IOC_IOCFG_HYSTEN (1 << 30) /* Bit 30: Input hysteresis enable */ @@ -226,16 +234,16 @@ #define IOC_IOCFG_PORTID_RFC_SMI_CLOUT 0x37 #define IOC_IOCFG_PORTID_RFC_SMI_CLIN 0x38 -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2IOC_H */ diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_timer.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_timer.h index 7507a74e376..27d7e9f5250 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_timer.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_timer.h @@ -1,10 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_timer.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a compatible + * BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,38 +37,38 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_TIMER_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_TIMER_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* TIMER Register Offsets ***********************************************************/ +/* TIMER Register Offsets ***************************************************/ -/* TIMER Register Addresses *********************************************************/ +/* TIMER Register Addresses *************************************************/ -/* TIMER Register Bitfield Definitions **********************************************/ +/* TIMER Register Bitfield Definitions **************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X2_CC26X2_CC13X2_CC26X2_TIMER_H */ diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_uart.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_uart.h index b934c3a17bc..2a74511651a 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_uart.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_uart.h @@ -1,10 +1,11 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_uart.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * - * Technical content derives from a TI header file that has a compatible BSD license: + * Technical content derives from a TI header file that has a compatible + * BSD license: * * Copyright (c) 2015-2017, Texas Instruments Incorporated * All rights reserved. @@ -36,23 +37,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_UART_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_UART_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* UART register offsets ************************************************************/ +/* UART register offsets ****************************************************/ #define TIVA_UART_DR_OFFSET 0x0000 /* UART Data */ #define TIVA_UART_RSR_OFFSET 0x0004 /* UART Receive Status */ @@ -69,7 +70,7 @@ #define TIVA_UART_ICR_OFFSET 0x0044 /* UART Interrupt Clear */ #define TIVA_UART_DMACTL_OFFSET 0x0048 /* UART DMA Control */ -/* UART register addresses **********************************************************/ +/* UART register addresses **************************************************/ #define TIVA_UART_BASE(n) (TIVA_UART0_BASE + (n)*0x01000) @@ -122,7 +123,7 @@ # define TIVA_UART1_DMACTL (TIVA_UART1_BASE + TIVA_UART_DMACTL_OFFSET) #endif -/* UART register bit settings *******************************************************/ +/* UART register bit settings ***********************************************/ /* UART Data (DR) */ @@ -264,12 +265,12 @@ #define UART_DMACTL_TXDMAE (1 << 1) /* Bit 1: Transmit DMA Enable */ #define UART_DMACTL_DMAERR (1 << 2) /* Bit 2: DMA on Error */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_UART_H */ diff --git a/arch/arm/src/tiva/hardware/lm/lm3s_ethernet.h b/arch/arm/src/tiva/hardware/lm/lm3s_ethernet.h index 173264064e4..83538a4e683 100644 --- a/arch/arm/src/tiva/hardware/lm/lm3s_ethernet.h +++ b/arch/arm/src/tiva/hardware/lm/lm3s_ethernet.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/lm/lm3s_ethernet.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_ETHERNET_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_ETHERNET_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Ethernet Controller Register Offsets *********************************************/ +/* Ethernet Controller Register Offsets *************************************/ /* Ethernet MAC Register Offsets */ @@ -59,7 +59,7 @@ /* MII Management Register Offsets (see include/nuttx/net/mii.h) */ -/* Ethernet Controller Register Addresses *******************************************/ +/* Ethernet Controller Register Addresses ***********************************/ #define TIVA_MAC_RIS (TIVA_ETHCON_BASE + TIVA_MAC_RIS_OFFSET) #define TIVA_MAC_IACK (TIVA_ETHCON_BASE + TIVA_MAC_IACK_OFFSET) @@ -96,9 +96,11 @@ #define MAC_MII_LEDCONFIG (TIVA_ETHCON_BASE + MII_TIVA_LEDCONFIG) #define MAC_MII_MDICONTROL (TIVA_ETHCON_BASE + MII_TIVA_MDICONTROL) -/* Ethernet Controller Register Bit Definitions *************************************/ +/* Ethernet Controller Register Bit Definitions *****************************/ -/* Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 */ +/* Ethernet MAC Raw Interrupt Status/Acknowledge + * (MACRIS/MACIACK), offset 0x000 + */ #define MAC_RIS_RXINT (1 << 0) /* Bit 0: Packet Received */ #define MAC_RIS_TXER (1 << 1) /* Bit 1: Transmit Error */ @@ -173,16 +175,16 @@ #define MAC_TR_NEWTX (1 << 0) /* Bit 0: New Transmission */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_ETHERNET_H */ diff --git a/arch/arm/src/tiva/hardware/lm/lm3s_flash.h b/arch/arm/src/tiva/hardware/lm/lm3s_flash.h index fdb38b6f9eb..23d0c7248ea 100644 --- a/arch/arm/src/tiva/hardware/lm/lm3s_flash.h +++ b/arch/arm/src/tiva/hardware/lm/lm3s_flash.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/lm/lm3s_flash.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_FLASH_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_FLASH_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* FLASH dimensions ****************************************************************/ +/* FLASH dimensions *********************************************************/ #if defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM4F120) || \ defined(CONFIG_ARCH_CHIP_LM3S8962) || defined(CONFIG_ARCH_CHIP_LM3S9B96) || \ @@ -39,8 +39,8 @@ defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || defined(CONFIG_ARCH_CHIP_TM4C123GH6PM) || \ defined(CONFIG_ARCH_CHIP_TM4C123AH6PM) -/* These parts all support a 1KiB erase page size and a total FLASH memory size - * of 256Kib or 256 pages. +/* These parts all support a 1KiB erase page size and a total FLASH memory + * size of 256Kib or 256 pages. */ # define TIVA_FLASH_NPAGES 256 @@ -49,10 +49,10 @@ #define TIVA_FLASH_SIZE (TIVA_FLASH_NPAGES * TIVA_FLASH_PAGESIZE) -/* FLASH register offsets ***********************************************************/ +/* FLASH register offsets ***************************************************/ -/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash - * control base address of TIVA_FLASHCON_BASE. +/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the + * Flash control base address of TIVA_FLASHCON_BASE. */ #define TIVA_FLASH_FMA_OFFSET 0x000 /* Flash memory address */ @@ -62,8 +62,8 @@ #define TIVA_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */ #define TIVA_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */ -/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the - * System Control base address of TIVA_SYSCON_BASE +/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative + * to the System Control base address of TIVA_SYSCON_BASE */ #define TIVA_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */ @@ -81,10 +81,10 @@ #define TIVA_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */ #define TIVA_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */ -/* FLASH register addresses *********************************************************/ +/* FLASH register addresses *************************************************/ -/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash - * control base address of TIVA_FLASHCON_BASE. +/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the + * Flash control base address of TIVA_FLASHCON_BASE. */ #define TIVA_FLASH_FMA (TIVA_FLASHCON_BASE + TIVA_FLASH_FMA_OFFSET) @@ -94,8 +94,8 @@ #define TIVA_FLASH_FCIM (TIVA_FLASHCON_BASE + TIVA_FLASH_FCIM_OFFSET) #define TIVA_FLASH_FCMISC (TIVA_FLASHCON_BASE + TIVA_FLASH_FCMISC_OFFSET) -/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the - * System Control base address of TIVA_SYSCON_BASE +/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative + * to the System Control base address of TIVA_SYSCON_BASE */ #define TIVA_FLASH_FMPRE (TIVA_SYSCON_BASE + TIVA_FLASH_FMPRE_OFFSET) @@ -113,7 +113,7 @@ #define TIVA_FLASH_FMPPE2 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE2_OFFSET) #define TIVA_FLASH_FMPPE3 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE3_OFFSET) -/* FLASH register bit definitions ***************************************************/ +/* FLASH register bit definitions *******************************************/ #define FLASH_FMA_OFFSET_SHIFT 0 /* Bits 17-0: Address Offset */ #define FLASH_FMA_OFFSET_MASK (0x0003ffff << FLASH_FMA_OFFSET_SHIFT) @@ -132,16 +132,16 @@ #define FLASH_FMC_WRKEY_MASK (0xffff << FLASH_FMC_WRKEY_SHIFT) #define FLASH_FMC_WRKEY (0xa442 << FLASH_FMC_WRKEY_SHIFT) /* Magic write key */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_FLASH_H */ diff --git a/arch/arm/src/tiva/hardware/lm/lm3s_gpio.h b/arch/arm/src/tiva/hardware/lm/lm3s_gpio.h index 3af2fb8010c..a616371e9d7 100644 --- a/arch/arm/src/tiva/hardware/lm/lm3s_gpio.h +++ b/arch/arm/src/tiva/hardware/lm/lm3s_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/lm/lm3s_gpio.h * * Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved. @@ -32,20 +32,21 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_GPIO_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* REVISIT: Why do we not use the AHB aperture for all GPIO accesses? */ #define TIVA_GPIOK_BASE TIVA_GPIOKAHB_BASE @@ -58,7 +59,7 @@ #define TIVA_GPIOS_BASE TIVA_GPIOSAHB_BASE #define TIVA_GPIOT_BASE TIVA_GPIOTAHB_BASE -/* GPIO Register Offsets ************************************************************/ +/* GPIO Register Offsets ****************************************************/ #define TIVA_GPIO_DATA_OFFSET 0x0000 /* GPIO Data */ #define TIVA_GPIO_DIR_OFFSET 0x0400 /* GPIO Direction */ @@ -98,7 +99,7 @@ #define TIVA_GPIO_PCELLID2_OFFSET 0x0ff8 /* GPIO PrimeCell Identification 2 */ #define TIVA_GPIO_PCELLID3_OFFSET 0x0ffc /* GPIO PrimeCell Identification 3*/ -/* GPIO Register Addresses **********************************************************/ +/* GPIO Register Addresses **************************************************/ #if TIVA_NPORTS > 0 @@ -457,7 +458,7 @@ # define TIVA_GPIOJ_PCELLID3 (TIVA_GPIOJ_BASE + TIVA_GPIO_PCELLID3_OFFSET) #endif -/* GPIO Register Bitfield Definitions ***********************************************/ +/* GPIO Register Bitfield Definitions ***************************************/ /* GPIO Lock */ @@ -488,16 +489,16 @@ # define GPIO_PCTL_PMC7_MASK (15 << GPIO_PCTL_PMC7_SHIFT) #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_GPIO_H */ diff --git a/arch/arm/src/tiva/hardware/lm/lm3s_memorymap.h b/arch/arm/src/tiva/hardware/lm/lm3s_memorymap.h index beb397dbb92..51b064bce76 100644 --- a/arch/arm/src/tiva/hardware/lm/lm3s_memorymap.h +++ b/arch/arm/src/tiva/hardware/lm/lm3s_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/lm/lm3s_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_MEMORYMAP_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Memory map ***********************************************************************/ +/* Memory map ***************************************************************/ #if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \ defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962) @@ -68,7 +68,7 @@ # define TIVA_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */ # define TIVA_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */ # define TIVA_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */ - /* -0xe000dfff: Reserved */ + /* -0xe000dfff: Reserved */ # define TIVA_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */ /* -0xe003ffff: Reserved */ # define TIVA_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */ @@ -77,11 +77,13 @@ # error "Memory map not specified for this LM3S chip" #endif -/* Peripheral base addresses ********************************************************/ -/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few different - * peripheral modules. They could probably be combined into one peripheral memory - * map. However, keeping them separate does also provide so early, compile-time - * error detection that makes the duplication worthwhile. +/* Peripheral base addresses ************************************************/ + +/* The LM3S6918 and LM3S6965 differ by only the presence or absence of a few + * different peripheral modules. They could probably be combined into one + * peripheral memory map. However, keeping them separate does also provide + * so early, compile-time error detection that makes the duplication + * worthwhile. */ #if defined(CONFIG_ARCH_CHIP_LM3S6918) @@ -99,6 +101,7 @@ # define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ # define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ /* -0x1ffff: Reserved */ + /* Peripheral Base Addresses */ # define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x20fff: I2C0 */ @@ -138,6 +141,7 @@ # define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ # define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ /* -0x1ffff: Reserved */ + /* Peripheral Base Addresses */ # define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x20fff: I2C0 */ @@ -178,6 +182,7 @@ # define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ # define TIVA_UART2_BASE (TIVA_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ /* -0x1ffff: Reserved */ + /* Peripheral Base Addresses */ # define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x20fff: I2C0 */ @@ -221,6 +226,7 @@ # define TIVA_UART0_BASE (TIVA_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */ # define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ /* -0x1ffff: Reserved */ + /* Peripheral Base Addresses */ # define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x20fff: I2C0 */ @@ -267,6 +273,7 @@ # define TIVA_UART1_BASE (TIVA_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */ # define TIVA_UART2_BASE (TIVA_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */ /* -0x1ffff: Reserved */ + /* Peripheral Base Addresses */ # define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x207ff: I2C0 */ @@ -322,16 +329,16 @@ # error "Peripheral base addresses not specified for this Stellaris chip" #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_MEMORYMAP_H */ diff --git a/arch/arm/src/tiva/hardware/lm/lm3s_pinmap.h b/arch/arm/src/tiva/hardware/lm/lm3s_pinmap.h index 57ca601c6ff..d0562794c0a 100644 --- a/arch/arm/src/tiva/hardware/lm/lm3s_pinmap.h +++ b/arch/arm/src/tiva/hardware/lm/lm3s_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/lm/lm3s_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_PINMAP_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* The following lists the input value to tiva_configgpio to setup the alternate, - * hardware function for each pin. +/* The following lists the input value to tiva_configgpio to setup the + * alternate, hardware function for each pin. */ #if defined(CONFIG_ARCH_CHIP_LM3S6918) @@ -261,18 +261,18 @@ # define GPIO_QEI1_IDX (GPIO_FUNC_PFINPUT | GPIO_PORTE | 1) /* PF1: QEI module 1 index. ) */ # define GPIO_ETHPHY_LED1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 2) /* PF2: LED1 */ # define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */ -# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PG1:PWM Generator 0, PWM1 */ +# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PG1:PWM Generator 0, PWM1 */ #else # error "Unknown Stellaris chip" #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/tiva/hardware/lm/lm3s_sysctrl.h b/arch/arm/src/tiva/hardware/lm/lm3s_sysctrl.h index 8eff26459d3..07871f434a0 100644 --- a/arch/arm/src/tiva/hardware/lm/lm3s_sysctrl.h +++ b/arch/arm/src/tiva/hardware/lm/lm3s_sysctrl.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/lm/lm3s_sysctrl.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_SYSCONTROL_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_SYSCONTROL_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* System Control Register Offsets **************************************************/ +/* System Control Register Offsets ******************************************/ #define TIVA_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */ #define TIVA_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */ @@ -63,7 +63,7 @@ #define TIVA_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */ #define TIVA_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/ -/* System Control Register Addresses ************************************************/ +/* System Control Register Addresses ****************************************/ #define TIVA_SYSCON_DID0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DID0_OFFSET) #define TIVA_SYSCON_DID1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DID1_OFFSET) @@ -95,7 +95,7 @@ #define TIVA_SYSCON_DCGC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGC2_OFFSET) #define TIVA_SYSCON_DSLPCLKCFG (TIVA_SYSCON_BASE + TIVA_SYSCON_DSLPCLKCFG_OFFSET) -/* System Control Register Bit Definitions ******************************************/ +/* System Control Register Bit Definitions **********************************/ /* Device Identification 0 (DID0), offset 0x000 */ @@ -113,7 +113,7 @@ #define SYSCON_DID1_QUAL_SHIFT 0 /* Bits 1-0: Qualification Status */ #define SYSCON_DID1_QUAL_MASK (0x03 << SYSCON_DID1_QUAL_SHIFT) #define SYSCON_DID1_ROHS (1 << 2) /* Bit 2: RoHS-Compliance */ -#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 4-3: Package Type */ +#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 4-3: Package Type */ #define SYSCON_DID1_PKG_MASK (0x03 << SYSCON_DID1_PKG_SHIFT) #define SYSCON_DID1_TEMP_SHIFT 5 /* Bits 7-5: Temperature Range */ #define SYSCON_DID1_TEMP_MASK (0x07 << SYSCON_DID1_TEMP_SHIFT) @@ -289,6 +289,7 @@ # define SYSCON_RCC_OSCSRC_PIOSC (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator (reset) */ # define SYSCON_RCC_OSCSRC_PIOSC4 (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Internal oscillator / 4 */ # define SYSCON_RCC_OSCSRC_LFIOSC (3 << SYSCON_RCC_OSCSRC_SHIFT) /* 30KHz internal oscillator */ + #define SYSCON_RCC_XTAL_SHIFT 6 /* Bits 10-6: Crystal Value */ #define SYSCON_RCC_XTAL_MASK (0x1f << SYSCON_RCC_XTAL_SHIFT) # define SYSCON_RCC_XTAL1000KHZ ( 0 << SYSCON_RCC_XTAL_SHIFT) /* 1.0000MHz (NO PLL) */ @@ -349,6 +350,7 @@ # define SYSCON_RCC2_OSCSRC2_PIOSC4 (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Internal oscillator / 4 */ # define SYSCON_RCC2_OSCSRC2_LFIOSC (3 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 30KHz internal oscillator */ # define SYSCON_RCC2_OSCSRC2_32768HZ (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */ + #define SYSCON_RCC2_BYPASS2 (1 << 11) /* Bit 11: Bypass PLL */ #define SYSCON_RCC2_PWRDN2 (1 << 13) /* Bit 13: Power-Down PLL */ #define SYSCON_RCC2_SYSDIV2_SHIFT 23 /* Bits 28-23: System Clock Divisor */ @@ -474,22 +476,22 @@ #define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT 4 /* Bits 6-4: Clock Source */ #define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK (0x07 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) -/* UART Run Mode Clock Gating Control*/ +/* UART Run Mode Clock Gating Control */ #ifdef CONFIG_ARCH_CHIP_LM3S9B92 # define SYSCON_RCGCUART(n) (1 << (n)) /* Bit n: UART Module n Run Mode Clock Gating Control */ #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ - * Public Functions - ************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_SYSCONTROL_H */ diff --git a/arch/arm/src/tiva/hardware/lm/lm3s_timer.h b/arch/arm/src/tiva/hardware/lm/lm3s_timer.h index 243042302c9..2c5a5b047a3 100644 --- a/arch/arm/src/tiva/hardware/lm/lm3s_timer.h +++ b/arch/arm/src/tiva/hardware/lm/lm3s_timer.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/lm/lm3s_timer.h * * Originally: @@ -44,23 +44,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_TIMER_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_TIMER_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* GPTM register offsets ************************************************************/ +/* GPTM register offsets ****************************************************/ #define TIVA_TIMER_CFG_OFFSET 0x0000 /* GPTM Configuration */ #define TIVA_TIMER_TAMR_OFFSET 0x0004 /* GPTM Timer A Mode */ @@ -81,7 +81,7 @@ #define TIVA_TIMER_TAR_OFFSET 0x0048 /* GPTM Timer A */ #define TIVA_TIMER_TBR_OFFSET 0x004c /* GPTM Timer B */ -/* GPTM register addresses **********************************************************/ +/* GPTM register addresses **************************************************/ #if TIVA_NTIMERS > 0 #define TIVA_TIMER0_CFG (TIVA_TIMER0_BASE + TIVA_TIMER_CFG_OFFSET) @@ -251,7 +251,8 @@ #define TIVA_TIMER7_TBR (TIVA_TIMER7_BASE + TIVA_TIMER_TBR_OFFSET) #endif /* TIVA_NTIMERS > 7 */ -/* GPTM register bit definitions ****************************************************/ +/* GPTM register bit definitions ********************************************/ + /* GPTM Configuration (CFG) */ #define TIMER_CFG_CFG_SHIFT 0 /* Bits 2-0: Configuration */ @@ -263,15 +264,20 @@ /* GPTM Timer A/B Mode (TAMR and TBMR) */ #define TIMER_TnMR_TnMR_SHIFT (0) /* Bits 1-0: Timer A/B Mode */ + #define TIMER_TnMR_TnMR_MASK (3 << TIMER_TnMR_TnMR_SHIFT) /* Bits 1-0: Timer A/B Mode */ # define TIMER_TnMR_TnMR_ONESHOT (1 << TIMER_TnMR_TnMR_SHIFT) /* One-Shot Timer mode */ # define TIMER_TnMR_TnMR_PERIODIC (2 << TIMER_TnMR_TnMR_SHIFT) /* Periodic Timer mode */ # define TIMER_TnMR_TnMR_CAPTURE (3 << TIMER_TnMR_TnMR_SHIFT) /* Capture mode */ + #define TIMER_TnMR_TnCMR_SHIFT (2) /* Bit 2: Timer A/B Capture Mode */ + #define TIMER_TnMR_TnCMR (1 << TIMER_TnMR_TnCMR_SHIFT) /* Bit 2: Timer A/B Capture Mode */ # define TIMER_TnMR_TnCMR_EDGECOUNT (0 << TIMER_TnMR_TnCMR_SHIFT) /* Edge-Count mode */ # define TIMER_TnMR_TnCMR_EDGETIME (1 << TIMER_TnMR_TnCMR_SHIFT) /* Edge-Time mode */ + #define TIMER_TnMR_TnAMS_SHIFT (3) /* Bit 3: Timer A/B Alternate Mode Select */ + #define TIMER_TnMR_TnAMS (1 << TIMER_TnMR_TnAMS_SHIFT) /* Bit 3: Timer A/B Alternate Mode Select */ # define TIMER_TnMR_TnAMS_CAPTURE (0 << TIMER_TnMR_TnAMS_SHIFT) /* Capture mode is enabled */ # define TIMER_TnMR_TnAMS_PWM (1 << TIMER_TnMR_TnAMS_SHIFT) /* PWM mode is enabled */ @@ -285,6 +291,7 @@ # define TIMER_CTL_TAEVENT_POS (0 << TIMER_CTL_TAEVENT_SHIFT) /* Positive edge */ # define TIMER_CTL_TAEVENT_NEG (1 << TIMER_CTL_TAEVENT_SHIFT) /* Negative edge */ # define TIMER_CTL_TAEVENT_BOTH (3 << TIMER_CTL_TAEVENT_SHIFT) /* Both edges */ + #define TIMER_CTL_RTCEN (1 << 4) /* Bit 4: GPTM RTC Stall Enable */ #define TIMER_CTL_TAOTE (1 << 5) /* Bit 5: GPTM Timer A Output Trigger Enable */ #define TIMER_CTL_TAPWML (1 << 6) /* Bit 6: GPTM Timer A PWM Output Level */ @@ -295,6 +302,7 @@ # define TIMER_CTL_TBEVENT_POS (0 << TIMER_CTL_TBEVENT_SHFIT) /* Positive edge */ # define TIMER_CTL_TBEVENT_NEG (1 << TIMER_CTL_TBEVENT_SHFIT) /* Negative edge */ # define TIMER_CTL_TBEVENT_BOTH (3 << TIMER_CTL_TBEVENT_SHFIT) /* Both edges */ + #define TIMER_CTL_TBOTE (1 << 13) /* Bit 13: GPTM Timer B Output Trigger Enable */ #define TIMER_CTL_TBPWML (1 << 14) /* Bit 14: GPTM Timer B PWM Output Level */ @@ -313,8 +321,11 @@ #define TIMER_ALLINTS 0x00000101 /* GPTM Timer A Interval Load (TAILR) (32-bit value) */ + /* GPTM Timer B Interval Load (TBILR) (32-bit value) */ + /* GPTM Timer A Match (TAMATCHR) (32-bit value) */ + /* GPTM Timer B Match (TBMATCHR) (32-bit value) */ /* GPTM Timer A/B Prescale (TnPR) */ @@ -330,6 +341,7 @@ # define TIMER_TnPMR_TnPSMR(n) ((uint32_t)(n) << TIMER_TnPMR_TnPSMR_SHIFT) /* GPTM Timer A (TAR) (16/32-bit value) */ + /* GPTM Timer B (TBR) (16/32-bit value) */ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM3S_TIMER_H */ diff --git a/arch/arm/src/tiva/hardware/lm/lm4f_gpio.h b/arch/arm/src/tiva/hardware/lm/lm4f_gpio.h index aeeba2a435a..4e7e47635a8 100644 --- a/arch/arm/src/tiva/hardware/lm/lm4f_gpio.h +++ b/arch/arm/src/tiva/hardware/lm/lm4f_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/lm/lm4f_gpio.h * * Copyright (C) 2009-2010, 2013, 2018 Gregory Nutt. All rights reserved. @@ -32,20 +32,21 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM4F_GPIO_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM4F_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* REVISIT: Why do we not use the AHB aperture for all GPIO accesses? */ #define TIVA_GPIOK_BASE TIVA_GPIOKAHB_BASE @@ -58,7 +59,7 @@ #define TIVA_GPIOS_BASE TIVA_GPIOSAHB_BASE #define TIVA_GPIOT_BASE TIVA_GPIOTAHB_BASE -/* GPIO Register Offsets ************************************************************/ +/* GPIO Register Offsets ****************************************************/ #define TIVA_GPIO_DATA_OFFSET 0x0000 /* GPIO Data */ #define TIVA_GPIO_DIR_OFFSET 0x0400 /* GPIO Direction */ @@ -96,9 +97,9 @@ #define TIVA_GPIO_PCELLID0_OFFSET 0x0ff0 /* GPIO PrimeCell Identification 0 */ #define TIVA_GPIO_PCELLID1_OFFSET 0x0ff4 /* GPIO PrimeCell Identification 1 */ #define TIVA_GPIO_PCELLID2_OFFSET 0x0ff8 /* GPIO PrimeCell Identification 2 */ -#define TIVA_GPIO_PCELLID3_OFFSET 0x0ffc /* GPIO PrimeCell Identification 3*/ +#define TIVA_GPIO_PCELLID3_OFFSET 0x0ffc /* GPIO PrimeCell Identification 3 */ -/* GPIO Register Addresses **********************************************************/ +/* GPIO Register Addresses **************************************************/ #if TIVA_NPORTS > 0 @@ -346,7 +347,7 @@ # define TIVA_GPIOF_PCELLID3 (TIVA_GPIOF_BASE + TIVA_GPIO_PCELLID3_OFFSET) #endif -/* GPIO Register Bitfield Definitions ***********************************************/ +/* GPIO Register Bitfield Definitions ***************************************/ /* GPIO Lock */ @@ -375,16 +376,16 @@ #define GPIO_PCTL_PMC7_SHIFT (28) /* Bits 28-31: Port Mux Control 7 */ #define GPIO_PCTL_PMC7_MASK (15 << GPIO_PCTL_PMC7_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM4F_GPIO_H */ diff --git a/arch/arm/src/tiva/hardware/lm/lm4f_memorymap.h b/arch/arm/src/tiva/hardware/lm/lm4f_memorymap.h index 8ecefc3cbe2..7bde11d0412 100644 --- a/arch/arm/src/tiva/hardware/lm/lm4f_memorymap.h +++ b/arch/arm/src/tiva/hardware/lm/lm4f_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/lm/lm4f_memorymap.h * * Copyright (C) 2013 Gregory Nutt. All rights reserved. @@ -32,22 +32,22 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM4F_MEMORYMAP_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM4F_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Memory map ***********************************************************************/ +/* Memory map ***************************************************************/ #if defined(CONFIG_ARCH_CHIP_LM4F120) # define TIVA_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */ @@ -74,7 +74,7 @@ # error "Memory map not specified for this LM4F chip" #endif -/* Peripheral base addresses ********************************************************/ +/* Peripheral base addresses ************************************************/ #if defined(CONFIG_ARCH_CHIP_LM4F120) /* FiRM Peripheral Base Addresses */ @@ -99,6 +99,7 @@ # define TIVA_UART6_BASE (TIVA_PERIPH_BASE + 0x12000) /* -0x12fff: UART6 */ # define TIVA_UART7_BASE (TIVA_PERIPH_BASE + 0x13000) /* -0x13fff: UART7 */ /* -0x1ffff: Reserved */ + /* Peripheral Base Addresses */ # define TIVA_I2C0_BASE (TIVA_PERIPH_BASE + 0x20000) /* -0x20fff: I2C0 */ @@ -148,16 +149,16 @@ # error "Peripheral base addresses not specified for this Stellaris chip" #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM4F_MEMORYMAP_H */ diff --git a/arch/arm/src/tiva/hardware/lm/lm4f_pinmap.h b/arch/arm/src/tiva/hardware/lm/lm4f_pinmap.h index 3922c9ea999..adc63ed2570 100644 --- a/arch/arm/src/tiva/hardware/lm/lm4f_pinmap.h +++ b/arch/arm/src/tiva/hardware/lm/lm4f_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/lm/lm4f_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,38 +16,40 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM4F_PINMAP_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM4F_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Alternate Pin Functions. All members of the LM4F family share the same pin - * multiplexing (although they may differ in the pins physically available). + ****************************************************************************/ + +/* Alternate Pin Functions. + * All members of the LM4F family share the same pin multiplexing + * (although they may differ in the pins physically available). * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if - * CAN1_RX connects vis PA11 on some board, then the following definitions should - * appear in the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. For + * example, if CAN1_RX connects vis PA11 on some board, then the following + * definitions should appear in the board.h header file for that board: * * #define GPIO_CAN1_RX GPIO_CAN1_RX_1 * * The driver will then automatically configure PA11 as the CAN1 RX pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. */ #if defined(CONFIG_ARCH_CHIP_LM4F120) @@ -185,13 +187,13 @@ # error "Unknown Stellaris chip" #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/tiva/hardware/lm/lm4f_sysctrl.h b/arch/arm/src/tiva/hardware/lm/lm4f_sysctrl.h index abb871cc8cf..e49ea7d46b9 100644 --- a/arch/arm/src/tiva/hardware/lm/lm4f_sysctrl.h +++ b/arch/arm/src/tiva/hardware/lm/lm4f_sysctrl.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/lm/lm4f_sysctrl.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM4F_SYSCONTROL_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM4F_SYSCONTROL_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* System Control Register Offsets **********************************************************/ +/* System Control Register Offsets ******************************************/ #define TIVA_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */ #define TIVA_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */ @@ -146,7 +146,7 @@ #define TIVA_SYSCON_PREEPROM_OFFSET 0xa58 /* EEPROM Peripheral Ready */ #define TIVA_SYSCON_PRWTIMER_OFFSET 0xa5c /* 2/64-BitWide Timer Peripheral Ready */ -/* System Control Legacy Register Offsets ***************************************************/ +/* System Control Legacy Register Offsets ***********************************/ #define TIVA_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */ #define TIVA_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */ @@ -177,7 +177,7 @@ #define TIVA_SYSCON_DC9_OFFSET 0x190 /* Device Capabilities */ #define TIVA_SYSCON_NVMSTAT_OFFSET 0x1a0 /* Non-Volatile Memory Information */ -/* System Control Register Addresses ********************************************************/ +/* System Control Register Addresses ****************************************/ #define TIVA_SYSCON_DID0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DID0_OFFSET) #define TIVA_SYSCON_DID1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DID1_OFFSET) @@ -292,7 +292,7 @@ #define TIVA_SYSCON_PREEPROM (TIVA_SYSCON_BASE + TIVA_SYSCON_PREEPROM_OFFSET) #define TIVA_SYSCON_PRWTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_PRWTIMER_OFFSET) -/* System Control Legacy Register Addresses *************************************************/ +/* System Control Legacy Register Addresses *********************************/ #define TIVA_SYSCON_DC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC0_OFFSET) #define TIVA_SYSCON_DC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC1_OFFSET) @@ -323,7 +323,7 @@ #define TIVA_SYSCON_DC9 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC9_OFFSET) #define TIVA_SYSCON_NVMSTAT (TIVA_SYSCON_BASE + TIVA_SYSCON_NVMSTAT_OFFSET) -/* System Control Register Bit Definitions **************************************************/ +/* System Control Register Bit Definitions **********************************/ /* Device Identification 0 */ @@ -341,7 +341,7 @@ #define SYSCON_DID1_QUAL_SHIFT 0 /* Bits 1-0: Qualification Status */ #define SYSCON_DID1_QUAL_MASK (0x03 << SYSCON_DID1_QUAL_SHIFT) #define SYSCON_DID1_ROHS (1 << 2) /* Bit 2: RoHS-Compliance */ -#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 4-3: Package Type */ +#define SYSCON_DID1_PKG_SHIFT 3 /* Bits 4-3: Package Type */ #define SYSCON_DID1_PKG_MASK (0x03 << SYSCON_DID1_PKG_SHIFT) #define SYSCON_DID1_TEMP_SHIFT 5 /* Bits 7-5: Temperature Range */ #define SYSCON_DID1_TEMP_MASK (0x07 << SYSCON_DID1_TEMP_SHIFT) @@ -408,6 +408,7 @@ # define SYSCON_RCC_OSCSRC_PIOSC (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Precision internal oscillator (reset) */ # define SYSCON_RCC_OSCSRC_PIOSC4 (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Precision internal oscillator / 4 */ # define SYSCON_RCC_OSCSRC_LFIOSC (3 << SYSCON_RCC_OSCSRC_SHIFT) /* Low-frequency internal oscillator */ + #define SYSCON_RCC_XTAL_SHIFT 6 /* Bits 10-6: Crystal Value */ #define SYSCON_RCC_XTAL_MASK (31 << SYSCON_RCC_XTAL_SHIFT) # define SYSCON_RCC_XTAL4000KHZ (6 << SYSCON_RCC_XTAL_SHIFT) /* 4 MHz (NO PLL) */ @@ -431,6 +432,7 @@ # define SYSCON_RCC_XTAL20000KHZ (24 << SYSCON_RCC_XTAL_SHIFT) /* 20.0 MHz (USB) */ # define SYSCON_RCC_XTAL24000KHZ (25 << SYSCON_RCC_XTAL_SHIFT) /* 24.0 MHz (USB) */ # define SYSCON_RCC_XTAL25000KHZ (26 << SYSCON_RCC_XTAL_SHIFT) /* 25.0 MHz (USB) */ + #define SYSCON_RCC_BYPASS (1 << 11) /* Bit 11: PLL Bypass */ #define SYSCON_RCC_PWRDN (1 << 13) /* Bit 13: PLL Power Down */ #define SYSCON_RCC_USESYSDIV (1 << 22) /* Bit 22: Enable System Clock Divider */ @@ -457,6 +459,7 @@ # define SYSCON_RCC2_OSCSRC2_PIOSC4 (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Precision internal oscillator / 4 */ # define SYSCON_RCC2_OSCSRC2_LFIOSC (4 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Low-frequency internal oscillator */ # define SYSCON_RCC2_OSCSRC2_32768HZ (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */ + #define SYSCON_RCC2_BYPASS2 (1 << 11) /* Bit 11: Bypass PLL */ #define SYSCON_RCC2_PWRDN2 (1 << 13) /* Bit 13: Power-Down PLL */ #define SYSCON_RCC2_USBPWRDN (1 << 14) /* Bit 14: Power-Down USB PLL */ @@ -483,6 +486,7 @@ # define SYSCON_DSLPCLKCFG_DSOSCSRC_PIOSC4 (2 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) /* Precision internal oscillator / 4 */ # define SYSCON_DSLPCLKCFG_DSOSCSRC_LFIOSC (4 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) /* Low-frequency internal oscillator */ # define SYSCON_DSLPCLKCFG_DSOSCSRC_32768KHZ (7 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) /* 32.768KHz external oscillator */ + #define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */ #define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT) # define SYSCON_DSLPCLKCFG_DSDIVORIDE(b) (((n)-1) << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT) @@ -679,7 +683,7 @@ #define SYSCON_SRHIB_R0 (1 << 0) /* Bit 0: Hibernation Module Software Reset */ -/* UART Software Reset*/ +/* UART Software Reset */ #define SYSCON_SRUARTR(n) (1 << (n)) /* Bit n: UART Module n Software Reset */ # define SYSCON_SRUARTR_R0 (1 << 0) /* Bit 0: UART Module 0 Software Reset */ @@ -756,7 +760,7 @@ # define SYSCON_RCGCTIMER_R4 (1 << 4) /* Bit 4: 16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control */ # define SYSCON_RCGCTIMER_R5 (1 << 5) /* Bit 5: 16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control */ -/* GPIO Run Mode Clock Gating Control*/ +/* GPIO Run Mode Clock Gating Control */ #define SYSCON_RCGCGPIO(n) (1 << (n)) /* Bit n: 16/32-Bit GPIO Port n Run Mode Clock Gating Control */ # define SYSCON_RCGCGPIO_R0 (1 << 0) /* Bit 0: 16/32-Bit GPIO Port A Run Mode Clock Gating Control */ @@ -766,7 +770,7 @@ # define SYSCON_RCGCGPIO_R4 (1 << 4) /* Bit 4: 16/32-Bit GPIO Port E Run Mode Clock Gating Control */ # define SYSCON_RCGCGPIO_R5 (1 << 5) /* Bit 5: 16/32-Bit GPIO Port F Run Mode Clock Gating Control */ -/* uDMA Run Mode Clock Gating Control*/ +/* uDMA Run Mode Clock Gating Control */ #define SYSCON_RCGCDMA_R0 (1 << 0) /* Bit 0: μDMA Module Run Mode Clock Gating Control */ @@ -774,7 +778,7 @@ #define SYSCON_RCGCHIB_R0 (1 << 0) /* Bit 0: Hibernation Module Run Mode Clock Gating Control */ -/* UART Run Mode Clock Gating Control*/ +/* UART Run Mode Clock Gating Control */ #define SYSCON_RCGCUART(n) (1 << (n)) /* Bit n: UART Module n Run Mode Clock Gating Control */ # define SYSCON_RCGCUART_R0 (1 << 0) /* Bit 0: UART Module 0 Run Mode Clock Gating Control */ @@ -786,7 +790,7 @@ # define SYSCON_RCGCUART_R6 (1 << 6) /* Bit 6: UART Module 6 Run Mode Clock Gating Control */ # define SYSCON_RCGCUART_R7 (1 << 7) /* Bit 7: UART Module 7 Run Mode Clock Gating Control */ -/* SSI Run Mode Clock Gating Control*/ +/* SSI Run Mode Clock Gating Control */ #define SYSCON_RCGCSSI(n) (1 << (n)) /* Bit n: SSI Module n Run Mode Clock Gating Control */ # define SYSCON_RCGCSSI_R0 (1 << 0) /* Bit 0: SSI Module 0 Run Mode Clock Gating Control */ @@ -1012,7 +1016,6 @@ #define SYSCON_DCGCEEPROM_D0 (1 << 0) /* Bit 0: EEPROM Module Deep-Sleep Mode Clock Gating Control */ - /* 32/64-BitWide Timer Deep-Sleep Mode Clock Gating Control */ #define SYSCON_DCGCWTIMER(n) (1 << (n)) /* Bit n: UART Module n Deep-Sleep Mode Clock Gating Control */ @@ -1117,7 +1120,8 @@ # define SYSCON_PRWTIMER_R4 (1 << 4) /* Bit 4: 32/64-Bit Wide General-Purpose Timer 4 Peripheral Ready */ # define SYSCON_PRWTIMER_R5 (1 << 5) /* Bit 5: 32/64-Bit Wide General-Purpose Timer 5 Peripheral Ready */ -/* System Control Legacy Register Bit Definitions *******************************************/ +/* System Control Legacy Register Bit Definitions ***************************/ + /* Device Capabilities 0 */ #define SYSCON_DC0_FLASHSZ_SHIFT 0 /* Bits 15-0: FLASH Size */ @@ -1506,16 +1510,16 @@ #define TIVA_SYSCON_NVMSTAT_FWB (1 << 0) /* Bit 0: 32 Word Flash Write Buffer Available */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM4F_SYSCONTROL_H */ diff --git a/arch/arm/src/tiva/hardware/lm/lm4f_timer.h b/arch/arm/src/tiva/hardware/lm/lm4f_timer.h index 04001009155..1136f72284b 100644 --- a/arch/arm/src/tiva/hardware/lm/lm4f_timer.h +++ b/arch/arm/src/tiva/hardware/lm/lm4f_timer.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/lm/lm4f_timer.h * * Originally: @@ -44,23 +44,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM4F_TIMER_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM4F_TIMER_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* GPTM register offsets ************************************************************/ +/* GPTM register offsets ****************************************************/ #define TIVA_TIMER_CFG_OFFSET 0x0000 /* GPTM Configuration */ #define TIVA_TIMER_TAMR_OFFSET 0x0004 /* GPTM Timer A Mode */ @@ -90,7 +90,7 @@ #define TIVA_TIMER_TBPV_OFFSET 0x0068 /* GPTM Timer B Prescale Value */ #define TIVA_TIMER_PP_OFFSET 0x0fc0 /* GPTM Peripheral Properties */ -/* GPTM register addresses **********************************************************/ +/* GPTM register addresses **************************************************/ #if TIVA_NTIMERS > 0 #define TIVA_TIMER0_CFG (TIVA_TIMER0_BASE + TIVA_TIMER_CFG_OFFSET) @@ -325,7 +325,8 @@ #define TIVA_TIMER7_PP (TIVA_TIMER7_BASE + TIVA_TIMER_PP_OFFSET) #endif /* TIVA_NTIMERS > 7 */ -/* GPTM register bit definitions ****************************************************/ +/* GPTM register bit definitions ********************************************/ + /* GPTM Configuration (CFG) */ #define TIMER_CFG_CFG_SHIFT 0 /* Bits 2-0: Configuration */ @@ -341,18 +342,25 @@ # define TIMER_TnMR_TnMR_ONESHOT (1 << TIMER_TnMR_TnMR_SHIFT) /* One-Shot Timer mode */ # define TIMER_TnMR_TnMR_PERIODIC (2 << TIMER_TnMR_TnMR_SHIFT) /* Periodic Timer mode */ # define TIMER_TnMR_TnMR_CAPTURE (3 << TIMER_TnMR_TnMR_SHIFT) /* Capture mode */ + #define TIMER_TnMR_TnCMR_SHIFT (2) /* Bit 2: Timer A/B Capture Mode */ + #define TIMER_TnMR_TnCMR (1 << TIMER_TnMR_TnCMR_SHIFT) /* Bit 2: Timer A/B Capture Mode */ # define TIMER_TnMR_TnCMR_EDGECOUNT (0 << TIMER_TnMR_TnCMR_SHIFT) /* Edge-Count mode */ # define TIMER_TnMR_TnCMR_EDGETIME (1 << TIMER_TnMR_TnCMR_SHIFT) /* Edge-Time mode */ + #define TIMER_TnMR_TnAMS_SHIFT (3) /* Bit 3: Timer A/B Alternate Mode Select */ + #define TIMER_TnMR_TnAMS (1 << TIMER_TnMR_TnAMS_SHIFT) /* Bit 3: Timer A/B Alternate Mode Select */ # define TIMER_TnMR_TnAMS_CAPTURE (0 << TIMER_TnMR_TnAMS_SHIFT) /* Capture mode is enabled */ # define TIMER_TnMR_TnAMS_PWM (1 << TIMER_TnMR_TnAMS_SHIFT) /* PWM mode is enabled */ + #define TIMER_TnMR_TnCDIR_SHIFT (4) /* Bit 4: Timer A/B Count Direction */ + #define TIMER_TnMR_TnCDIR (1 << TIMER_TnMR_TnCDIR_SHIFT) /* Bit 4: Timer A/B Count Direction */ # define TIMER_TnMR_TnCDIR_DOWN (0 << TIMER_TnMR_TnCDIR_SHIFT) /* Timer counts down */ # define TIMER_TnMR_TnCDIR_UP (1 << TIMER_TnMR_TnCDIR_SHIFT) /* Timer counts up (one-shot/periodic modes) */ + #define TIMER_TnMR_TnMIE (1 << 5) /* Bit 5: Timer A/B Match Interrupt Enable */ #define TIMER_TnMR_TnWOT (1 << 6) /* Bit 6: GPTM Timer A/B Wait-on-Trigger */ #define TIMER_TnMR_TnSNAPS (1 << 7) /* Bit 7: GPTM Timer A/B Snap-Shot Mode */ @@ -370,6 +378,7 @@ # define TIMER_CTL_TAEVENT_POS (0 << TIMER_CTL_TAEVENT_SHIFT) /* Positive edge */ # define TIMER_CTL_TAEVENT_NEG (1 << TIMER_CTL_TAEVENT_SHIFT) /* Negative edge */ # define TIMER_CTL_TAEVENT_BOTH (3 << TIMER_CTL_TAEVENT_SHIFT) /* Both edges */ + #define TIMER_CTL_RTCEN (1 << 4) /* Bit 4: GPTM RTC Stall Enable */ #define TIMER_CTL_TAOTE (1 << 5) /* Bit 5: GPTM Timer A Output Trigger Enable */ #define TIMER_CTL_TAPWML (1 << 6) /* Bit 6: GPTM Timer A PWM Output Level */ @@ -380,6 +389,7 @@ # define TIMER_CTL_TBEVENT_POS (0 << TIMER_CTL_TBEVENT_SHFIT) /* Positive edge */ # define TIMER_CTL_TBEVENT_NEG (1 << TIMER_CTL_TBEVENT_SHFIT) /* Negative edge */ # define TIMER_CTL_TBEVENT_BOTH (3 << TIMER_CTL_TBEVENT_SHFIT) /* Both edges */ + #define TIMER_CTL_TBOTE (1 << 13) /* Bit 13: GPTM Timer B Output Trigger Enable */ #define TIMER_CTL_TBPWML (1 << 14) /* Bit 14: GPTM Timer B PWM Output Level */ @@ -528,8 +538,11 @@ #define TIMER_ALLINTS 0x00010f1f /* GPTM Timer A Interval Load (TAILR) (32-bit value) */ + /* GPTM Timer B Interval Load (TBILR) (32-bit value) */ + /* GPTM Timer A Match (TAMATCHR) (32-bit value) */ + /* GPTM Timer B Match (TBMATCHR) (32-bit value) */ /* GPTM Timer A/B Prescale (TnPR) */ @@ -545,8 +558,11 @@ # define TIMER_TnPMR_TnPSMR(n) ((uint32_t)(n) << TIMER_TnPMR_TnPSMR_SHIFT) /* GPTM Timer A (TAR) (16/32-bit value) */ + /* GPTM Timer B (TBR) (16/32-bit value) */ + /* GPTM Timer A Value (TAV) (16/32-bit value) */ + /* GPTM Timer B Value (TBV) (16/32-bit value) */ /* GPTM RTC Predivide (RTCPD) */ diff --git a/arch/arm/src/tiva/hardware/lm/lm_i2c.h b/arch/arm/src/tiva/hardware/lm/lm_i2c.h index 6da397531da..0bfdeb2418d 100644 --- a/arch/arm/src/tiva/hardware/lm/lm_i2c.h +++ b/arch/arm/src/tiva/hardware/lm/lm_i2c.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/lm/lm_i2c.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM_I2C_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM_I2C_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* I2C Register Offsets *************************************************************/ +/* I2C Register Offsets *****************************************************/ /* I2C Master */ @@ -56,7 +56,7 @@ #define TIVA_I2CS_MIS_OFFSET 0x0814 /* I2C Slave Masked Interrupt Status */ #define TIVA_I2CS_ICR_OFFSET 0x0818 /* I2C Slave Interrupt Clear */ -/* I2C Register Addresses ***********************************************************/ +/* I2C Register Addresses ***************************************************/ #if TIVA_NI2C > 0 @@ -318,7 +318,7 @@ #endif /* TIVA_NI2C > 9 */ -/* I2C_Register Bit Definitions *****************************************************/ +/* I2C_Register Bit Definitions *********************************************/ /* I2C Master Slave Address (I2CM_SA) */ @@ -406,13 +406,13 @@ #define I2CS_ICR_DATAIC (1 << 0) /* Bit 0: Data Interrupt Clear */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/tiva/hardware/lm/lm_uart.h b/arch/arm/src/tiva/hardware/lm/lm_uart.h index 9e5f6ef42d8..2b60e03fe48 100644 --- a/arch/arm/src/tiva/hardware/lm/lm_uart.h +++ b/arch/arm/src/tiva/hardware/lm/lm_uart.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/lm/lm_uart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM_UART_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM_UART_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* UART register offsets ************************************************************/ +/* UART register offsets ****************************************************/ #define TIVA_UART_DR_OFFSET 0x0000 /* UART Data */ #define TIVA_UART_RSR_OFFSET 0x0004 /* UART Receive Status */ @@ -62,7 +62,7 @@ #define TIVA_UART_PCELLID2_OFFSET 0x0ff8 /* UART PrimeCell Identification 2 */ #define TIVA_UART_PCELLID3_OFFSET 0x0ffc /* UART PrimeCell Identification 3 */ -/* UART register addresses **********************************************************/ +/* UART register addresses **************************************************/ #define TIVA_UART_BASE(n) (TIVA_UART0_BASE + (n)*0x01000) @@ -334,7 +334,7 @@ # define TIVA_UART7_PCELLID3 (TIVA_UART7_BASE + TIVA_UART_PCELLID3_OFFSET) #endif -/* UART register bit settings *******************************************************/ +/* UART register bit settings ***********************************************/ /* UART Data (DR) */ @@ -511,12 +511,12 @@ #define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM_UART_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_adc.h b/arch/arm/src/tiva/hardware/tiva_adc.h index 1e92ce70e2a..78836b77a90 100644 --- a/arch/arm/src/tiva/hardware/tiva_adc.h +++ b/arch/arm/src/tiva/hardware/tiva_adc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_adc.h * * Copyright (C) 2015 Calvin Maguranis. All rights reserved. @@ -31,22 +31,22 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* ADC register offsets *************************************************************/ +/* ADC register offsets *****************************************************/ #define TIVA_ADC_ACTSS_OFFSET 0x000 /* ADC Active Sample Sequencer */ #define TIVA_ADC_RIS_OFFSET 0x004 /* ADC Raw Interrupt Status */ @@ -96,7 +96,7 @@ #define TIVA_ADC_PC_OFFSET 0xfc4 /* ADC Peripheral Configuration */ #define TIVA_ADC_CC_OFFSET 0xfc8 /* ADC Clock Configuration */ -/* ADC register addresses ***********************************************************/ +/* ADC register addresses ***************************************************/ #define TIVA_ADC_BASE(n) (TIVA_ADC0_BASE + (n)*0x01000) #define TIVA_ADC_SS(n) (TIVA_ADC_SS_BASE + ((n)*TIVA_ADC_SSMUX_OFFSET)) @@ -144,7 +144,7 @@ #define TIVA_ADC_DCCMP6(n) (TIVA_ADC_BASE(n)+TIVA_ADC_DCCMP6_OFFSET) /* ADC Digital Comparator Range 6 */ #define TIVA_ADC_DCCMP7(n) (TIVA_ADC_BASE(n)+TIVA_ADC_DCCMP7_OFFSET) /* ADC Digital Comparator Range 7 */ -/* ADC register address expansion ***************************************************/ +/* ADC register address expansion *******************************************/ #define TIVA_ADC0_ACTSS (TIVA_ADC_BASE(0) + TIVA_ADC_ACTSS_OFFSET) /* ADC Active Sample Sequencer */ #define TIVA_ADC0_RIS (TIVA_ADC_BASE(0) + TIVA_ADC_RIS_OFFSET) /* ADC Raw Interrupt Status */ @@ -286,7 +286,7 @@ #define TIVA_ADC1_DCCMP6 (TIVA_ADC_BASE(1) + TIVA_ADC_DCCMP6_OFFSET) /* ADC Digital Comparator Range 6 */ #define TIVA_ADC1_DCCMP7 (TIVA_ADC_BASE(1) + TIVA_ADC_DCCMP7_OFFSET) /* ADC Digital Comparator Range 7 */ -/* ADC register bit settings ********************************************************/ +/* ADC register bit settings ************************************************/ /* Bit fields in the TIVA_ADC_ACTSS register. */ diff --git a/arch/arm/src/tiva/hardware/tiva_adi2_refsys.h b/arch/arm/src/tiva/hardware/tiva_adi2_refsys.h index 127b8b21a63..01c0b822ff8 100644 --- a/arch/arm/src/tiva/hardware/tiva_adi2_refsys.h +++ b/arch/arm/src/tiva/hardware/tiva_adi2_refsys.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_adi2_refsys.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,18 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI2_REFSYS_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI2_REFSYS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) /* These architectures do not support the ADI2 REFSYS block */ @@ -39,20 +41,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink ADI2 REFSYS" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI2_REFSYS_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_adi3_refsys.h b/arch/arm/src/tiva/hardware/tiva_adi3_refsys.h index 597033b7013..aec15b06317 100644 --- a/arch/arm/src/tiva/hardware/tiva_adi3_refsys.h +++ b/arch/arm/src/tiva/hardware/tiva_adi3_refsys.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_adi3_refsys.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI3_REFSYS_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI3_REFSYS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) + /* These architectures do not support the ADI3 REFSYS block */ #elif defined(CONFIG_ARCH_CHIP_CC13X0) # include "hardware/cc13x0/cc13x0_adi3_refsys.h" @@ -39,20 +42,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink ADI3 REFSYS" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI3_REFSYS_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_adi4_aux.h b/arch/arm/src/tiva/hardware/tiva_adi4_aux.h index 7b4c0ca4a5e..73ec3167cdd 100644 --- a/arch/arm/src/tiva/hardware/tiva_adi4_aux.h +++ b/arch/arm/src/tiva/hardware/tiva_adi4_aux.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_adi4_aux.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI4_AUX_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI4_AUX_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) + /* These architectures do not support the ADI4 AUX block */ #elif defined(CONFIG_ARCH_CHIP_CC13X0) # include "hardware/cc13x0/cc13x0_adi4_aux.h" @@ -39,20 +42,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink ADI4 AUX" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADI4_AUX_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_aon_batmon.h b/arch/arm/src/tiva/hardware/tiva_aon_batmon.h index d30c148b420..e26dec935a0 100644 --- a/arch/arm/src/tiva/hardware/tiva_aon_batmon.h +++ b/arch/arm/src/tiva/hardware/tiva_aon_batmon.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_aon_batmon.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_BATMON_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_BATMON_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) + /* These architectures do not support the AON BATMON block */ #elif defined(CONFIG_ARCH_CHIP_CC13X0) # include "hardware/cc13x0/cc13x0_aon_batmon.h" @@ -39,20 +42,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink AON BATMON" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_BATMON_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_aon_ioc.h b/arch/arm/src/tiva/hardware/tiva_aon_ioc.h index e61c84cdadb..46ab7e147d5 100644 --- a/arch/arm/src/tiva/hardware/tiva_aon_ioc.h +++ b/arch/arm/src/tiva/hardware/tiva_aon_ioc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_aon_ioc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_IOC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_IOC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) + /* These architectures do not support the AON IOC block */ #elif defined(CONFIG_ARCH_CHIP_CC13X0) # include "hardware/cc13x0/cc13x0_aon_ioc.h" @@ -39,20 +42,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink AON IOC" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_IOC_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_aon_pmctl.h b/arch/arm/src/tiva/hardware/tiva_aon_pmctl.h index dd3507b5ee6..1efc776791b 100644 --- a/arch/arm/src/tiva/hardware/tiva_aon_pmctl.h +++ b/arch/arm/src/tiva/hardware/tiva_aon_pmctl.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_aon_pmctl.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,42 +16,45 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_PMCTL_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_PMCTL_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) || \ defined(CONFIG_ARCH_CHIP_CC13X0) - /* These architectures do not support the AON PMCTL block */ + +/* These architectures do not support the AON PMCTL block */ #elif defined(CONFIG_ARCH_CHIP_CC13X2) # include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_aon_pmctl.h" #else # error "Unsupported Tiva/Stellaris/SimpleLink AON PMCTL" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_PMCTL_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_aon_rtc.h b/arch/arm/src/tiva/hardware/tiva_aon_rtc.h index 3f80a8ecb06..b25342d5a0a 100644 --- a/arch/arm/src/tiva/hardware/tiva_aon_rtc.h +++ b/arch/arm/src/tiva/hardware/tiva_aon_rtc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_aon_rtc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_RTC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_RTC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) + /* These architectures do not support the AON RTC block */ #elif defined(CONFIG_ARCH_CHIP_CC13X0) # include "hardware/cc13x0/cc13x0_aon_rtc.h" @@ -39,20 +42,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink AON RTC" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_RTC_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_aon_sysctl.h b/arch/arm/src/tiva/hardware/tiva_aon_sysctl.h index 0fcd725a6fa..2be377529b4 100644 --- a/arch/arm/src/tiva/hardware/tiva_aon_sysctl.h +++ b/arch/arm/src/tiva/hardware/tiva_aon_sysctl.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_aon_sysctl.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_SYSCTL_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_SYSCTL_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) || \ defined(CONFIG_ARCH_CHIP_CC13X2) + /* These architectures do not support the AON SYSCTL block */ #elif defined(CONFIG_ARCH_CHIP_CC13X0) # include "hardware/cc13x0/cc13x0_aon_sysctl.h" @@ -38,20 +41,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink AON SYSCTL" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_SYSCTL_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_aon_wuc.h b/arch/arm/src/tiva/hardware/tiva_aon_wuc.h index a9c89883ee3..df1af7b725b 100644 --- a/arch/arm/src/tiva/hardware/tiva_aon_wuc.h +++ b/arch/arm/src/tiva/hardware/tiva_aon_wuc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_aon_wuc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,18 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_WUC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_WUC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) || \ defined(CONFIG_ARCH_CHIP_CC13X2) @@ -38,20 +40,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink AON WUC" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AON_WUC_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_aux_smph.h b/arch/arm/src/tiva/hardware/tiva_aux_smph.h index 8ac578814c7..1651fd86647 100644 --- a/arch/arm/src/tiva/hardware/tiva_aux_smph.h +++ b/arch/arm/src/tiva/hardware/tiva_aux_smph.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_aux_smph.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_SMPH_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_SMPH_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) + /* These architectures do not support the AUX SMPH block */ #elif defined(CONFIG_ARCH_CHIP_CC13X0) # include "hardware/cc13x0/cc13x0_aux_smph.h" @@ -39,20 +42,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink AUX SMPH" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_SMPH_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_aux_sysif.h b/arch/arm/src/tiva/hardware/tiva_aux_sysif.h index aa3e7677e3e..7baf964e5ee 100644 --- a/arch/arm/src/tiva/hardware/tiva_aux_sysif.h +++ b/arch/arm/src/tiva/hardware/tiva_aux_sysif.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_aux_sysif.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_SYSIF_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_SYSIF_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) || \ defined(CONFIG_ARCH_CHIP_CC13X0) + /* These architectures do not support the AUX SYSIF block */ #elif defined(CONFIG_ARCH_CHIP_CC13X2) # include "hardware/cc13x2_cc26x2/cc13x2_cc26x2_aux_sysif.h" @@ -38,20 +41,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink AUX SYSIF" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_SYSIF_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_aux_wuc.h b/arch/arm/src/tiva/hardware/tiva_aux_wuc.h index 5a81cabb8ef..6cdc5eb8f0c 100644 --- a/arch/arm/src/tiva/hardware/tiva_aux_wuc.h +++ b/arch/arm/src/tiva/hardware/tiva_aux_wuc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_aux_wuc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,18 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_WUC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_WUC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) || \ defined(CONFIG_ARCH_CHIP_CC13X2) @@ -38,20 +40,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink AUX WUC" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_AUX_WUC_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_ccfg.h b/arch/arm/src/tiva/hardware/tiva_ccfg.h index 27ccd94f43e..41ec7899904 100644 --- a/arch/arm/src/tiva/hardware/tiva_ccfg.h +++ b/arch/arm/src/tiva/hardware/tiva_ccfg.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_ccfg.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_CCFG_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_CCFG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) - /* These architectures do not support the CCFG block */ + +/* These architectures do not support the CCFG block */ #elif defined(CONFIG_ARCH_CHIP_CC13X0) # include "hardware/cc13x0/cc13x0_ccfg.h" #elif defined(CONFIG_ARCH_CHIP_CC13X2) @@ -39,20 +42,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink CCFG" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_CCFG_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_ddi.h b/arch/arm/src/tiva/hardware/tiva_ddi.h index e2efb94f06c..e715ae9cece 100644 --- a/arch/arm/src/tiva/hardware/tiva_ddi.h +++ b/arch/arm/src/tiva/hardware/tiva_ddi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_ddi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_DDI_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_DDI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) + /* These architectures do not support the DDI block */ #elif defined(CONFIG_ARCH_CHIP_CC13X0) # include "hardware/cc13x0/cc13x0_ddi.h" @@ -39,20 +42,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink DDI" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_DDI_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_ddi0_osc.h b/arch/arm/src/tiva/hardware/tiva_ddi0_osc.h index 9ae278e24be..c607adf3a3a 100644 --- a/arch/arm/src/tiva/hardware/tiva_ddi0_osc.h +++ b/arch/arm/src/tiva/hardware/tiva_ddi0_osc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_ddi0_osc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_DDI0_OSC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_DDI0_OSC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) + /* These architectures do not support the DDI0_OSC block */ #elif defined(CONFIG_ARCH_CHIP_CC13X0) # include "hardware/cc13x0/cc13x0_ddi0_osc.h" @@ -39,20 +42,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink DDI0_OSC" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_DDI0_OSC_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_eeprom.h b/arch/arm/src/tiva/hardware/tiva_eeprom.h index 333fb604d3d..4c6a1e0692d 100644 --- a/arch/arm/src/tiva/hardware/tiva_eeprom.h +++ b/arch/arm/src/tiva/hardware/tiva_eeprom.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_eeprom.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -32,16 +32,16 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_EEPROM_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_EEPROM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/* Register Offsets *****************************************************************/ +/* Register Offsets *********************************************************/ #define TIVA_EEPROM_EESIZE_OFFSET 0x0000 /* EEPROM Size Information */ #define TIVA_EEPROM_EEBLOCK_OFFSET 0x0004 /* EEPROM Current Block */ @@ -63,7 +63,7 @@ #define TIVA_EEPROM_EEDBGME_OFFSET 0x0080 /* EEPROM Debug Mass Erase */ #define TIVA_EEPROM_PP_OFFSET 0x0fc0 /* EEPROM Peripheral Properties */ -/* Register Addresses ***************************************************************/ +/* Register Addresses *******************************************************/ #define TIVA_EEPROM_EESIZE (TIVA_EEPROM_BASE + TIVA_EEPROM_EESIZE_OFFSET) #define TIVA_EEPROM_EEBLOCK (TIVA_EEPROM_BASE + TIVA_EEPROM_EEBLOCK_OFFSET) @@ -85,36 +85,48 @@ #define TIVA_EEPROM_EEDBGME (TIVA_EEPROM_BASE + TIVA_EEPROM_EEDBGME_OFFSET) #define TIVA_EEPROM_PP (TIVA_EEPROM_BASE + TIVA_EEPROM_PP_OFFSET) -/* Register Bit-Field Definitions ***************************************************/ +/* Register Bit-Field Definitions *******************************************/ -/* The following are defines for the bit fields in the EEPROM_EESIZE register. */ +/* The following are defines for the bit fields in the EEPROM_EESIZE + * register. + */ #define EEPROM_EESIZE_WORDCNT_M 0x0000ffff /* Number of 32-Bit Words */ #define EEPROM_EESIZE_BLKCNT_M 0x07ff0000 /* Number of 16-Word Blocks */ #define EEPROM_EESIZE_WORDCNT_S 0 #define EEPROM_EESIZE_BLKCNT_S 16 -/* The following are defines for the bit fields in the EEPROM_EEBLOCK register. */ +/* The following are defines for the bit fields in the EEPROM_EEBLOCK + * register. + */ #define EEPROM_EEBLOCK_BLOCK_M 0x0000ffff /* Current Block */ #define EEPROM_EEBLOCK_BLOCK_S 0 -/* The following are defines for the bit fields in the EEPROM_EEOFFSET register. */ +/* The following are defines for the bit fields in the EEPROM_EEOFFSET + * register. + */ #define EEPROM_EEOFFSET_OFFSET_M 0x0000000f /* Current Address Offset */ #define EEPROM_EEOFFSET_OFFSET_S 0 -/* The following are defines for the bit fields in the EEPROM_EERDWR register. */ +/* The following are defines for the bit fields in the EEPROM_EERDWR + * register. + */ #define EEPROM_EERDWR_VALUE_M 0xffffffff /* EEPROM Read or Write Data */ #define EEPROM_EERDWR_VALUE_S 0 -/* The following are defines for the bit fields in the EEPROM_EERDWRINC register. */ +/* The following are defines for the bit fields in the EEPROM_EERDWRINC + * register. + */ #define EEPROM_EERDWRINC_VALUE_M 0xffffffff /* EEPROM Read or Write Data with Increment */ #define EEPROM_EERDWRINC_VALUE_S 0 -/* The following are defines for the bit fields in the EEPROM_EEDONE register. */ +/* The following are defines for the bit fields in the EEPROM_EEDONE + * register. + */ #define EEPROM_EEDONE_WORKING 0x00000001 /* EEPROM Working */ #define EEPROM_EEDONE_WKERASE 0x00000004 /* Working on an Erase */ @@ -122,16 +134,22 @@ #define EEPROM_EEDONE_NOPERM 0x00000010 /* Write Without Permission */ #define EEPROM_EEDONE_WRBUSY 0x00000020 /* Write Busy */ -/* The following are defines for the bit fields in the EEPROM_EESUPP register. */ +/* The following are defines for the bit fields in the EEPROM_EESUPP + * register. + */ #define EEPROM_EESUPP_ERETRY 0x00000004 /* Erase Must Be Retried */ #define EEPROM_EESUPP_PRETRY 0x00000008 /* Programming Must Be Retried */ -/* The following are defines for the bit fields in the EEPROM_EEUNLOCK register. */ +/* The following are defines for the bit fields in the EEPROM_EEUNLOCK + * register. + */ #define EEPROM_EEUNLOCK_UNLOCK_M 0xffffffff /* EEPROM Unlock */ -/* The following are defines for the bit fields in the EEPROM_EEPROT register. */ +/* The following are defines for the bit fields in the EEPROM_EEPROT + * register. + */ #define EEPROM_EEPROT_PROT_M 0x00000007 /* Protection Control */ #define EEPROM_EEPROT_PROT_RWNPW 0x00000000 /* This setting is the default. If @@ -145,48 +163,68 @@ * block is readable, not writable */ #define EEPROM_EEPROT_ACC 0x00000008 /* Access Control */ -/* The following are defines for the bit fields in the EEPROM_EEPASS0 register. */ +/* The following are defines for the bit fields in the + * EEPROM_EEPASS0 register. + */ #define EEPROM_EEPASS0_PASS_M 0xffffffff /* Password */ #define EEPROM_EEPASS0_PASS_S 0 -/* The following are defines for the bit fields in the EEPROM_EEPASS1 register. */ +/* The following are defines for the bit fields in the + * EEPROM_EEPASS1 register. + */ #define EEPROM_EEPASS1_PASS_M 0xffffffff /* Password */ #define EEPROM_EEPASS1_PASS_S 0 -/* The following are defines for the bit fields in the EEPROM_EEPASS2 register. */ +/* The following are defines for the bit fields in the + * EEPROM_EEPASS2 register. + */ #define EEPROM_EEPASS2_PASS_M 0xffffffff /* Password */ #define EEPROM_EEPASS2_PASS_S 0 -/* The following are defines for the bit fields in the EEPROM_EEINT register. */ +/* The following are defines for the bit fields in the + * EEPROM_EEINT register. + */ #define EEPROM_EEINT_INT 0x00000001 /* Interrupt Enable */ -/* The following are defines for the bit fields in the EEPROM_EEHIDE0 register. */ +/* The following are defines for the bit fields in the + * EEPROM_EEHIDE0 register. + */ #define EEPROM_EEHIDE0_HN_M 0xfffffffe /* Hide Block */ -/* The following are defines for the bit fields in the EEPROM_EEHIDE register. */ +/* The following are defines for the bit fields in the + * EEPROM_EEHIDE register. + */ #define EEPROM_EEHIDE_HN_M 0xfffffffe /* Hide Block */ -/* The following are defines for the bit fields in the EEPROM_EEHIDE1 register. */ +/* The following are defines for the bit fields in the + * EEPROM_EEHIDE1 register. + */ #define EEPROM_EEHIDE1_HN_M 0xffffffff /* Hide Block */ -/* The following are defines for the bit fields in the EEPROM_EEHIDE2 register. */ +/* The following are defines for the bit fields in the + * EEPROM_EEHIDE2 register. + */ #define EEPROM_EEHIDE2_HN_M 0xffffffff /* Hide Block */ -/* The following are defines for the bit fields in the EEPROM_EEDBGME register. */ +/* The following are defines for the bit fields in the + * EEPROM_EEDBGME register. + */ #define EEPROM_EEDBGME_ME 0x00000001 /* Mass Erase */ #define EEPROM_EEDBGME_KEY_M 0xffff0000 /* Erase Key */ #define EEPROM_EEDBGME_KEY_S 16 -/* The following are defines for the bit fields in the EEPROM_PP register. */ +/* The following are defines for the bit fields in the + * EEPROM_PP register. + */ #define EEPROM_PP_SIZE_M 0x0000ffff /* EEPROM Size */ #define EEPROM_PP_SIZE_64 0x00000000 /* 64 bytes of EEPROM */ diff --git a/arch/arm/src/tiva/hardware/tiva_epi.h b/arch/arm/src/tiva/hardware/tiva_epi.h index 958bce9fb7d..0c842639173 100644 --- a/arch/arm/src/tiva/hardware/tiva_epi.h +++ b/arch/arm/src/tiva/hardware/tiva_epi.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_epi.h * * Copyright (C) 2009-2013 Max Neklyudov. All rights reserved. @@ -31,20 +31,20 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_EPI_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_EPI_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* External Peripheral Interface Register Offsets ***********************************/ +/* External Peripheral Interface Register Offsets ***************************/ #define TIVA_EPI_CFG_OFFSET 0x000 #define TIVA_EPI_SDRAMCFG_OFFSET 0x010 @@ -52,7 +52,7 @@ #define TIVA_EPI_STAT_OFFSET 0x060 #define TIVA_EPI_BAUD_OFFSET 0x004 -/* External Peripheral Interface Register Addresses *********************************/ +/* External Peripheral Interface Register Addresses *************************/ #define TIVA_EPI0_CFG (TIVA_EPI0_BASE + TIVA_EPI_CFG_OFFSET) #define TIVA_EPI0_SDRAMCFG (TIVA_EPI0_BASE + TIVA_EPI_SDRAMCFG_OFFSET) @@ -60,7 +60,7 @@ #define TIVA_EPI0_STAT (TIVA_EPI0_BASE + TIVA_EPI_STAT_OFFSET) #define TIVA_EPI0_BAUD (TIVA_EPI0_BASE + TIVA_EPI_BAUD_OFFSET) -/* External Peripheral Interface Register Bit Definitions ***************************/ +/* External Peripheral Interface Register Bit Definitions *******************/ /* EPI Configuration (EPICFG), offset 0x000 */ diff --git a/arch/arm/src/tiva/hardware/tiva_ethernet.h b/arch/arm/src/tiva/hardware/tiva_ethernet.h index 649bd9f25ca..65a4d4cdab6 100644 --- a/arch/arm/src/tiva/hardware/tiva_ethernet.h +++ b/arch/arm/src/tiva/hardware/tiva_ethernet.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_ethernet.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ETHERNET_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ETHERNET_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include diff --git a/arch/arm/src/tiva/hardware/tiva_fcfg1.h b/arch/arm/src/tiva/hardware/tiva_fcfg1.h index 51baaeef27b..582dbdabe02 100644 --- a/arch/arm/src/tiva/hardware/tiva_fcfg1.h +++ b/arch/arm/src/tiva/hardware/tiva_fcfg1.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_fcfg1.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,18 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_FCFG1_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_FCFG1_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) /* These architectures do not support the FCFG1 block */ @@ -39,20 +41,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink FCFG1" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_FCFG1_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_flash.h b/arch/arm/src/tiva/hardware/tiva_flash.h index be182491999..97c5ec8a674 100644 --- a/arch/arm/src/tiva/hardware/tiva_flash.h +++ b/arch/arm/src/tiva/hardware/tiva_flash.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_flash.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,21 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_FLASH_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_FLASH_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) -/* The TM4C129 family has a different FLASH register layout. Others (including LM4F - * and TM4C123) are similar to the LM3S family +/* The TM4C129 family has a different FLASH register layout. + * Others (including LM4F and TM4C123) are similar to the LM3S family */ # if defined(CONFIG_ARCH_CHIP_TM4C129) diff --git a/arch/arm/src/tiva/hardware/tiva_gpio.h b/arch/arm/src/tiva/hardware/tiva_gpio.h index 016c5e8aa4f..629c358f557 100644 --- a/arch/arm/src/tiva/hardware/tiva_gpio.h +++ b/arch/arm/src/tiva/hardware/tiva_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_gpio.h * * Copyright (C) 2009-2010, 2013, 2018 Gregory Nutt. All rights reserved. @@ -32,18 +32,20 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_GPIO_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the GPIO header file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the GPIO header file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM3S) # include "hardware/lm/lm3s_gpio.h" @@ -61,20 +63,20 @@ # error "Unsupported Tiva/Stellaris system GPIO" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_GPIO_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_i2c.h b/arch/arm/src/tiva/hardware/tiva_i2c.h index 3d613e8af13..ea1a906be4f 100644 --- a/arch/arm/src/tiva/hardware/tiva_i2c.h +++ b/arch/arm/src/tiva/hardware/tiva_i2c.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_i2c.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,18 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_I2C_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_I2C_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the I2C header file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the I2C header file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) # include "hardware/lm/lm_i2c.h" @@ -43,20 +45,20 @@ # error "Unsupported Tiva/Stellaris system I2C" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_I2C_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_ioc.h b/arch/arm/src/tiva/hardware/tiva_ioc.h index 919d50832d8..16853272780 100644 --- a/arch/arm/src/tiva/hardware/tiva_ioc.h +++ b/arch/arm/src/tiva/hardware/tiva_ioc.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_ioc.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_IOC_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_IOC_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) + /* These architectures do not support the IOC block */ #elif defined(CONFIG_ARCH_CHIP_CC13X0) # include "hardware/cc13x0/cc13x0_ioc.h" @@ -39,20 +42,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink IOC" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_IOC_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_memorymap.h b/arch/arm/src/tiva/hardware/tiva_memorymap.h index 5c6876c3202..63178038a5a 100644 --- a/arch/arm/src/tiva/hardware/tiva_memorymap.h +++ b/arch/arm/src/tiva/hardware/tiva_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,18 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_MEMORYMAP_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the memory map file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the memory map file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM3S) # include "hardware/lm/lm3s_memorymap.h" @@ -43,20 +45,20 @@ # error "Unsupported Tiva/Stellaris memory map" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_MEMORYMAP_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_pinmap.h b/arch/arm/src/tiva/hardware/tiva_pinmap.h index dad210f6e13..54a332869fd 100644 --- a/arch/arm/src/tiva/hardware/tiva_pinmap.h +++ b/arch/arm/src/tiva/hardware/tiva_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,18 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_PINMAP_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM3S) # include "hardware/lm/lm3s_pinmap.h" @@ -36,25 +38,26 @@ #elif defined(CONFIG_ARCH_CHIP_TM4C) # include "hardware/tm4c/tm4c_pinmap.h" #elif defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2) + /* There are no pin multiplex header files for these architectures */ #else # error "Unsupported Tiva/Stellaris/SimpleLink PIN mapping" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_PINMAP_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_prcm.h b/arch/arm/src/tiva/hardware/tiva_prcm.h index 48085c34625..0ca46c9b08d 100644 --- a/arch/arm/src/tiva/hardware/tiva_prcm.h +++ b/arch/arm/src/tiva/hardware/tiva_prcm.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_prcm.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,18 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_PRCM_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_PRCM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) /* These architectures do not support the PRCM block */ @@ -39,20 +41,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink PRCM" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_PRCM_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_pwm.h b/arch/arm/src/tiva/hardware/tiva_pwm.h index 4faee6ebad4..9540c5d8ecb 100644 --- a/arch/arm/src/tiva/hardware/tiva_pwm.h +++ b/arch/arm/src/tiva/hardware/tiva_pwm.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_pwm.h * * Copyright (C) 2016 Young Mu. All rights reserved. @@ -31,18 +31,18 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_PWM_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_PWM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define TIVA_PWM_CTL_OFFSET (0x0) /* PWM Master Control */ #define TIVA_PWM_SYNC_OFFSET (0x4) /* PWM Time Base Sync */ diff --git a/arch/arm/src/tiva/hardware/tiva_qencoder.h b/arch/arm/src/tiva/hardware/tiva_qencoder.h index 672b8a5cba7..7d5b4b23d2b 100644 --- a/arch/arm/src/tiva/hardware/tiva_qencoder.h +++ b/arch/arm/src/tiva/hardware/tiva_qencoder.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_qencoder.h * * Copyright (C) 2016 Young Mu. All rights reserved. @@ -31,18 +31,18 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_QENCODER_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_QENCODER_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ #define TIVA_QEI_CTL_OFFSET (0x0) /* QEI Control */ #define TIVA_QEI_STAT_OFFSET (0x4) /* QEI Status */ diff --git a/arch/arm/src/tiva/hardware/tiva_smph.h b/arch/arm/src/tiva/hardware/tiva_smph.h index 4bb23a07a55..731ef3eca00 100644 --- a/arch/arm/src/tiva/hardware/tiva_smph.h +++ b/arch/arm/src/tiva/hardware/tiva_smph.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_smph.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,20 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SMPH_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SMPH_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) + /* These architectures do not support the SMPH block */ #elif defined(CONFIG_ARCH_CHIP_CC13X0) # include "hardware/cc13x0/cc13x0_smph.h" @@ -39,20 +42,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink SMPH" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SMPH_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_ssi.h b/arch/arm/src/tiva/hardware/tiva_ssi.h index 9a2c2f87faf..78de3f1e123 100644 --- a/arch/arm/src/tiva/hardware/tiva_ssi.h +++ b/arch/arm/src/tiva/hardware/tiva_ssi.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_ssi.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SSI_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SSI_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include #if TIVA_NSSI > 0 -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* SSI register offsets *********************************************************************/ +/* SSI register offsets *****************************************************/ #define TIVA_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */ #define TIVA_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */ @@ -47,6 +47,7 @@ #define TIVA_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */ #if defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2) # define TIVA_SSI_DMACR_OFFSET 0x024 /* SSI DMA Control */ + #else /* if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TIVA) */ # define TIVA_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */ # define TIVA_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */ @@ -62,7 +63,7 @@ # define TIVA_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */ #endif -/* SSI register addresses *******************************************************************/ +/* SSI register addresses ***************************************************/ #define TIVA_SSI0_CR0 (TIVA_SSI0_BASE + TIVA_SSI_CR0_OFFSET) #define TIVA_SSI0_CR1 (TIVA_SSI0_BASE + TIVA_SSI_CR1_OFFSET) @@ -146,7 +147,7 @@ #endif #endif /* TIVA_NSSI > 1 */ -/* SSI register bit defitiions **************************************************************/ +/* SSI register bit defitiions **********************************************/ /* SSI Control 0 (SSICR0), offset 0x000 */ @@ -229,17 +230,17 @@ # define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */ #endif -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Function Prototypes - ********************************************************************************************/ + ****************************************************************************/ #endif /* TIVA_NSSI > 0 */ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SSI_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_sysctrl.h b/arch/arm/src/tiva/hardware/tiva_sysctrl.h index f5cc340ae4d..534ff13ac16 100644 --- a/arch/arm/src/tiva/hardware/tiva_sysctrl.h +++ b/arch/arm/src/tiva/hardware/tiva_sysctrl.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_sysctrl.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,18 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SYSCONTROL_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SYSCONTROL_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the system control header file for the specific Tiva/Stellaris chip */ +/* Include the system control header file for the specific Tiva/Stellaris + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM3S) # include "hardware/lm/lm3s_sysctrl.h" @@ -38,25 +40,26 @@ #elif defined(CONFIG_ARCH_CHIP_TM4C129) # include "hardware/tm4c/tm4c129_sysctrl.h" #elif defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2) + /* These MCUs have no SYSCTL block */ #else # error "Unsupported Tiva/Stellaris system control module" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SYSCONTROL_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_timer.h b/arch/arm/src/tiva/hardware/tiva_timer.h index 76c887a01eb..33d511b1186 100644 --- a/arch/arm/src/tiva/hardware/tiva_timer.h +++ b/arch/arm/src/tiva/hardware/tiva_timer.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_timer.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,18 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_TIMER_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_TIMER_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the timer header file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the timer header file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM3S) # include "hardware/lm/lm3s_timer.h" diff --git a/arch/arm/src/tiva/hardware/tiva_uart.h b/arch/arm/src/tiva/hardware/tiva_uart.h index e90bc293bc5..4cf03aae1dd 100644 --- a/arch/arm/src/tiva/hardware/tiva_uart.h +++ b/arch/arm/src/tiva/hardware/tiva_uart.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_uart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,18 +16,20 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_UART_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_UART_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the UART header file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the UART header file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) # include "hardware/lm/lm_uart.h" @@ -41,20 +43,20 @@ # error "Unsupported Tiva/Stellaris memory map" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_UART_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_vims.h b/arch/arm/src/tiva/hardware/tiva_vims.h index 7e47ac9db86..8e9a4d8f59b 100644 --- a/arch/arm/src/tiva/hardware/tiva_vims.h +++ b/arch/arm/src/tiva/hardware/tiva_vims.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_vims.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,21 +16,24 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_VIMS_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_VIMS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink chip */ +/* Include the pin mapping file for the specific Tiva/Stellaris/SimpleLink + * chip + */ #if defined(CONFIG_ARCH_CHIP_LM) || defined(CONFIG_ARCH_CHIP_TM4C) - /* These architectures do not support the VIMS block */ + +/* These architectures do not support the VIMS block */ #elif defined(CONFIG_ARCH_CHIP_CC13X0) # include "hardware/cc13x0/cc13x0_vims.h" #elif defined(CONFIG_ARCH_CHIP_CC13X2) @@ -39,20 +42,20 @@ # error "Unsupported Tiva/Stellaris/SimpleLink VIMS" #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_VIMS_H */ diff --git a/arch/arm/src/tiva/hardware/tiva_wdt.h b/arch/arm/src/tiva/hardware/tiva_wdt.h index 4f47fc4edc6..2e35540f115 100644 --- a/arch/arm/src/tiva/hardware/tiva_wdt.h +++ b/arch/arm/src/tiva/hardware/tiva_wdt.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/tiva_wdt.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_WDT_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_SSI_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include #include -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* WDT register offsets *********************************************************************/ +/* WDT register offsets *****************************************************/ #define TIVA_WDT_LOAD_OFFSET 0x0000 /* Configuration */ #define TIVA_WDT_VALUE_OFFSET 0x0004 /* Current Count Value */ @@ -61,7 +61,7 @@ # define TIVA_WDT_CELLID3_OFFSET 0x0ffc /* Watchdog PrimeCell Identification 3 */ #endif -/* WDT register addresses *******************************************************************/ +/* WDT register addresses ***************************************************/ #define TIVA_WDT_LOAD (TIVA_WDT_BASE + TIVA_WDT_LOAD_OFFSET) #define TIVA_WDT_VALUE (TIVA_WDT_BASE + TIVA_WDT_VALUE_OFFSET) @@ -89,7 +89,7 @@ # define TIVA_WDT_CELLID3 (TIVA_WDT_BASE + TIVA_WDT_CELLID3_OFFSET) #endif -/* WDT register bitfield definitions ********************************************************/ +/* WDT register bitfield definitions ****************************************/ /* Configuration (32-bit interval value) */ @@ -113,8 +113,8 @@ /* Interrupt Clear. * - * A write of any value to this register clears the WDT interrupt and reloads the 32-bit - * counter from the LOAD register. + * A write of any value to this register clears the WDT interrupt and reloads + * the 32-bit counter from the LOAD register. */ /* Raw Interrupt Status */ diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c123_gpio.h b/arch/arm/src/tiva/hardware/tm4c/tm4c123_gpio.h index bde8b4769a7..61bce291c24 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c123_gpio.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c123_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tm4c/tm4c123_gpio.h * * Copyright (C) 2009-2010, 2013, 2018 Gregory Nutt. All rights reserved. @@ -32,20 +32,21 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C123_GPIO_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C123_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* REVISIT: Why do we not use the AHB aperture for all GPIO accesses? */ #define TIVA_GPIOK_BASE TIVA_GPIOKAHB_BASE @@ -58,7 +59,7 @@ #define TIVA_GPIOS_BASE TIVA_GPIOSAHB_BASE #define TIVA_GPIOT_BASE TIVA_GPIOTAHB_BASE -/* GPIO Register Offsets ************************************************************/ +/* GPIO Register Offsets ****************************************************/ #define TIVA_GPIO_DATA_OFFSET 0x0000 /* GPIO Data */ #define TIVA_GPIO_DIR_OFFSET 0x0400 /* GPIO Direction */ @@ -98,7 +99,7 @@ #define TIVA_GPIO_PCELLID2_OFFSET 0x0ff8 /* GPIO PrimeCell Identification 2 */ #define TIVA_GPIO_PCELLID3_OFFSET 0x0ffc /* GPIO PrimeCell Identification 3*/ -/* GPIO Register Addresses **********************************************************/ +/* GPIO Register Addresses **************************************************/ #if TIVA_NPORTS > 0 @@ -469,7 +470,7 @@ # define TIVA_GPIOJ_PCELLID3 (TIVA_GPIOJ_BASE + TIVA_GPIO_PCELLID3_OFFSET) #endif -/* GPIO Register Bitfield Definitions ***********************************************/ +/* GPIO Register Bitfield Definitions ***************************************/ /* GPIO Lock */ @@ -498,16 +499,16 @@ #define GPIO_PCTL_PMC7_SHIFT (28) /* Bits 28-31: Port Mux Control 7 */ #define GPIO_PCTL_PMC7_MASK (15 << GPIO_PCTL_PMC7_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C123_GPIO_H */ diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c123_i2c.h b/arch/arm/src/tiva/hardware/tm4c/tm4c123_i2c.h index 4a00cada625..210210e4dec 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c123_i2c.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c123_i2c.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tm4c/tm4c123_i2c.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C123_I2C_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C123_I2C_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* I2C Register Offsets *************************************************************/ +/* I2C Register Offsets *****************************************************/ /* I2C Master */ @@ -68,7 +68,7 @@ #define TIVA_I2CSC_PP_OFFSET 0x0fc0 /* I2C Peripheral Properties */ #define TIVA_I2CSC_PC_OFFSET 0x0fc4 /* I2C Peripheral Configuration */ -/* I2C Register Addresses ***********************************************************/ +/* I2C Register Addresses ***************************************************/ #if TIVA_NI2C > 0 @@ -460,7 +460,7 @@ #endif /* TIVA_NI2C > 9 */ -/* I2C_Register Bit Definitions *****************************************************/ +/* I2C_Register Bit Definitions *********************************************/ /* I2C Master Slave Address (I2CM_SA) */ @@ -612,13 +612,13 @@ #define I2CSC_PC_HS (1 << 0) /* Bit 0: High-Speed Capable */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c123_sysctrl.h b/arch/arm/src/tiva/hardware/tm4c/tm4c123_sysctrl.h index 81dab86274e..fd78bfa6c42 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c123_sysctrl.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c123_sysctrl.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/tm4c/tm4c123_sysctrl.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C123_SYSCONTROL_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C123_SYSCONTROL_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ -/* System Control Register Offsets **********************************************************/ +/* System Control Register Offsets ******************************************/ #define TIVA_SYSCON_DID0_OFFSET 0x0000 /* Device Identification 0 */ #define TIVA_SYSCON_DID1_OFFSET 0x0004 /* Device Identification 1 */ @@ -163,7 +163,7 @@ #define TIVA_SYSCON_PREEPROM_OFFSET 0x0a58 /* EEPROM Peripheral Ready */ #define TIVA_SYSCON_PRWTIMER_OFFSET 0x0a5c /* 2/64-BitWide Timer Peripheral Ready */ -/* System Control Legacy Register Offsets ***************************************************/ +/* System Control Legacy Register Offsets ***********************************/ #define TIVA_SYSCON_DC0_OFFSET 0x0008 /* Device Capabilities 0 */ #define TIVA_SYSCON_DC1_OFFSET 0x0010 /* Device Capabilities 1 */ @@ -194,7 +194,7 @@ #define TIVA_SYSCON_DC9_OFFSET 0x0190 /* Device Capabilities */ #define TIVA_SYSCON_NVMSTAT_OFFSET 0x01a0 /* Non-Volatile Memory Information */ -/* System Control Register Addresses ********************************************************/ +/* System Control Register Addresses ****************************************/ #define TIVA_SYSCON_DID0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DID0_OFFSET) #define TIVA_SYSCON_DID1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DID1_OFFSET) @@ -326,7 +326,7 @@ #define TIVA_SYSCON_PREEPROM (TIVA_SYSCON_BASE + TIVA_SYSCON_PREEPROM_OFFSET) #define TIVA_SYSCON_PRWTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_PRWTIMER_OFFSET) -/* System Control Legacy Register Addresses *************************************************/ +/* System Control Legacy Register Addresses *********************************/ #define TIVA_SYSCON_DC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC0_OFFSET) #define TIVA_SYSCON_DC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC1_OFFSET) @@ -357,7 +357,7 @@ #define TIVA_SYSCON_DC9 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC9_OFFSET) #define TIVA_SYSCON_NVMSTAT (TIVA_SYSCON_BASE + TIVA_SYSCON_NVMSTAT_OFFSET) -/* System Control Register Bit Definitions **************************************************/ +/* System Control Register Bit Definitions **********************************/ /* Device Identification 0 */ @@ -442,6 +442,7 @@ # define SYSCON_RCC_OSCSRC_PIOSC (1 << SYSCON_RCC_OSCSRC_SHIFT) /* Precision internal oscillator (reset) */ # define SYSCON_RCC_OSCSRC_PIOSC4 (2 << SYSCON_RCC_OSCSRC_SHIFT) /* Precision internal oscillator / 4 */ # define SYSCON_RCC_OSCSRC_LFIOSC (3 << SYSCON_RCC_OSCSRC_SHIFT) /* Low-frequency internal oscillator */ + #define SYSCON_RCC_XTAL_SHIFT 6 /* Bits 10-6: Crystal Value */ #define SYSCON_RCC_XTAL_MASK (31 << SYSCON_RCC_XTAL_SHIFT) # define SYSCON_RCC_XTAL4000KHZ (6 << SYSCON_RCC_XTAL_SHIFT) /* 4 MHz (NO PLL) */ @@ -465,9 +466,10 @@ # define SYSCON_RCC_XTAL20000KHZ (24 << SYSCON_RCC_XTAL_SHIFT) /* 20.0 MHz (USB) */ # define SYSCON_RCC_XTAL24000KHZ (25 << SYSCON_RCC_XTAL_SHIFT) /* 24.0 MHz (USB) */ # define SYSCON_RCC_XTAL25000KHZ (26 << SYSCON_RCC_XTAL_SHIFT) /* 25.0 MHz (USB) */ + #define SYSCON_RCC_BYPASS (1 << 11) /* Bit 11: PLL Bypass */ #define SYSCON_RCC_PWRDN (1 << 13) /* Bit 13: PLL Power Down */ -#define SYSCON_RCC_PWMDIV_SHIFT 17 /* Bits 19-17: PWM Unit Clock Divisor */ +#define SYSCON_RCC_PWMDIV_SHIFT 17 /* Bits 19-17: PWM Unit Clock Divisor */ #define SYSCON_RCC_PWMDIV_MASK (7 << SYSCON_RCC_PWMDIV_SHIFT) # define SYSCON_RCC_PWMDIV_2 (0 << SYSCON_RCC_PWMDIV_SHIFT) /* /2 */ # define SYSCON_RCC_PWMDIV_4 (1 << SYSCON_RCC_PWMDIV_SHIFT) /* /4 */ @@ -475,6 +477,7 @@ # define SYSCON_RCC_PWMDIV_16 (3 << SYSCON_RCC_PWMDIV_SHIFT) /* /16 */ # define SYSCON_RCC_PWMDIV_32 (4 << SYSCON_RCC_PWMDIV_SHIFT) /* /32 */ # define SYSCON_RCC_PWMDIV_64 (7 << SYSCON_RCC_PWMDIV_SHIFT) /* /64 (default) */ + #define SYSCON_RCC_USEPWMDIV (1 << 20) /* Bit 20: Enable PWM Clock Divisor */ #define SYSCON_RCC_USESYSDIV (1 << 22) /* Bit 22: Enable System Clock Divider */ #define SYSCON_RCC_SYSDIV_SHIFT 23 /* Bits 26-23: System Clock Divisor */ @@ -510,6 +513,7 @@ # define SYSCON_RCC2_OSCSRC2_PIOSC4 (2 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Precision internal oscillator / 4 */ # define SYSCON_RCC2_OSCSRC2_LFIOSC (4 << SYSCON_RCC2_OSCSRC2_SHIFT) /* Low-frequency internal oscillator */ # define SYSCON_RCC2_OSCSRC2_32768HZ (7 << SYSCON_RCC2_OSCSRC2_SHIFT) /* 32.768KHz external oscillator */ + #define SYSCON_RCC2_BYPASS2 (1 << 11) /* Bit 11: Bypass PLL */ #define SYSCON_RCC2_PWRDN2 (1 << 13) /* Bit 13: Power-Down PLL */ #define SYSCON_RCC2_USBPWRDN (1 << 14) /* Bit 14: Power-Down USB PLL */ @@ -530,13 +534,14 @@ /* Deep Sleep Clock Configuration */ #define SYSCON_DSLPCLKCFG_PIOSCPD (1 << 1) /* Bit 1: PIOSC Power Down Request */ -#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT 4 /* Bits 6-4: Clock Source */ +#define SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT 4 /* Bits 6-4: Clock Source */ #define SYSCON_DSLPCLKCFG_DSOSCSRC_MASK (7 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) # define SYSCON_DSLPCLKCFG_DSOSCSRC_MOSC (0 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) /* Main oscillator */ # define SYSCON_DSLPCLKCFG_DSOSCSRC_PIOSC (1 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) /* Precision internal oscillator (reset) */ # define SYSCON_DSLPCLKCFG_DSOSCSRC_PIOSC4 (2 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) /* Precision internal oscillator / 4 */ # define SYSCON_DSLPCLKCFG_DSOSCSRC_LFIOSC (4 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) /* Low-frequency internal oscillator */ # define SYSCON_DSLPCLKCFG_DSOSCSRC_32768KHZ (7 << SYSCON_DSLPCLKCFG_DSOSCSRC_SHIFT) /* 32.768KHz external oscillator */ + #define SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT 23 /* Bits 28-23: Divider Field Override */ #define SYSCON_DSLPCLKCFG_DSDIVORIDE_MASK (0x3f << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT) # define SYSCON_DSLPCLKCFG_DSDIVORIDE(b) (((n)-1) << SYSCON_DSLPCLKCFG_DSDIVORIDE_SHIFT) @@ -599,6 +604,7 @@ # define SYSCON_SLPPWRCFG_SRAMPM_ACTIVE (0 << SYSCON_SLPPWRCFG_SRAMPM_SHIFT) /* Active Mode */ # define SYSCON_SLPPWRCFG_SRAMPM_STANDBY (1 << SYSCON_SLPPWRCFG_SRAMPM_SHIFT) /* Standby Mode */ # define SYSCON_SLPPWRCFG_SRAMPM_LOWPWR (3 << SYSCON_SLPPWRCFG_SRAMPM_SHIFT) /* Low Power Mode */ + #define SYSCON_SLPPWRCFG_FLASHPM_SHIFT (4) /* Bits 5-4: Flash Power Modes */ #define SYSCON_SLPPWRCFG_FLASHPM_MASK (3 << SYSCON_SLPPWRCFG_FLASHPM_SHIFT) # define SYSCON_SLPPWRCFG_FLASHPM_ACTIVE (0 << SYSCON_SLPPWRCFG_FLASHPM_SHIFT) /* Active Mode */ @@ -611,6 +617,7 @@ # define SYSCON_DSLPPWRCFG_SRAMPM_ACTIVE (0 << SYSCON_DSLPPWRCFG_SRAMPM_SHIFT) /* Active Mode */ # define SYSCON_DSLPPWRCFG_SRAMPM_STANDBY (1 << SYSCON_DSLPPWRCFG_SRAMPM_SHIFT) /* Standby Mode */ # define SYSCON_DSLPPWRCFG_SRAMPM_LOWPWR (3 << SYSCON_DSLPPWRCFG_SRAMPM_SHIFT) /* Low Power Mode */ + #define SYSCON_DSLPPWRCFG_FLASHPM_SHIFT (4) /* Bits 5-4: Flash Power Modes */ #define SYSCON_DSLPPWRCFG_FLASHPM_MASK (3 << SYSCON_DSLPPWRCFG_FLASHPM_SHIFT) # define SYSCON_DSLPPWRCFG_FLASHPM_ACTIVE (0 << SYSCON_DSLPPWRCFG_FLASHPM_SHIFT) /* Active Mode */ @@ -627,6 +634,7 @@ # define SYSCON_LDOSPCTL_VLDO_1p10V (0x16 << SYSCON_LDOSPCTL_VLDO_SHIFT) /* 1.10 V */ # define SYSCON_LDOSPCTL_VLDO_1p15V (0x17 << SYSCON_LDOSPCTL_VLDO_SHIFT) /* 1.15 V */ # define SYSCON_LDOSPCTL_VLDO_1p20V (0x18 << SYSCON_LDOSPCTL_VLDO_SHIFT) /* 1.20 V */ + #define SYSCON_LDOSPCTL_VADJEN (1 << 31) /* Bit 31: Voltage Adjust Enable */ /* LDO Sleep Power Calibration */ @@ -640,6 +648,7 @@ # define SYSCON_LDOSPCAL_NOPLL_1p10V (0x16 << SYSCON_LDOSPCAL_NOPLL_SHIFT) /* 1.10 V */ # define SYSCON_LDOSPCAL_NOPLL_1p15V (0x17 << SYSCON_LDOSPCAL_NOPLL_SHIFT) /* 1.15 V */ # define SYSCON_LDOSPCAL_NOPLL_1p20V (0x18 << SYSCON_LDOSPCAL_NOPLL_SHIFT) /* 1.20 V */ + #define SYSCON_LDOSPCAL_WITHPLL_SHIFT (8) /* Bits 15-8: Sleep with PLL */ #define SYSCON_LDOSPCAL_WITHPLL_MASK (0xff << SYSCON_LDOSPCAL_WITHPLL_SHIFT) # define SYSCON_LDOSPCAL_WITHPLL_0p90V (0x12 << SYSCON_LDOSPCAL_WITHPLL_SHIFT) /* 0.90 V */ @@ -661,6 +670,7 @@ # define SYSCON_LDODPCTL_VLDO_1p10V (0x16 << SYSCON_LDODPCTL_VLDO_SHIFT) /* 1.10 V */ # define SYSCON_LDODPCTL_VLDO_1p15V (0x17 << SYSCON_LDODPCTL_VLDO_SHIFT) /* 1.15 V */ # define SYSCON_LDODPCTL_VLDO_1p20V (0x18 << SYSCON_LDODPCTL_VLDO_SHIFT) /* 1.20 V */ + #define SYSCON_LDODPCTL_VADJEN (1 << 31) /* Bit 31: Voltage Adjust Enable */ /* LDO Deep-Sleep Power Calibration */ @@ -674,6 +684,7 @@ # define SYSCON_LDODPCAL_NOPLL_1p10V (0x16 << SYSCON_LDODPCAL_NOPLL_SHIFT) /* 1.10 V */ # define SYSCON_LDODPCAL_NOPLL_1p15V (0x17 << SYSCON_LDODPCAL_NOPLL_SHIFT) /* 1.15 V */ # define SYSCON_LDODPCAL_NOPLL_1p20V (0x18 << SYSCON_LDODPCAL_NOPLL_SHIFT) /* 1.20 V */ + #define SYSCON_LDODPCAL_30KHZ_SHIFT (8) /* Bits 15-8: Deep-Sleep with IOSC */ #define SYSCON_LDODPCAL_30KHZ_MASK (0xff << SYSCON_LDODPCAL_30KHZ_SHIFT) # define SYSCON_LDODPCAL_30KHZ_0p90V (0x12 << SYSCON_LDODPCAL_30KHZ_SHIFT) /* 0.90 V */ @@ -860,7 +871,7 @@ #define SYSCON_SRHIB_R0 (1 << 0) /* Bit 0: Hibernation Module Software Reset */ -/* UART Software Reset*/ +/* UART Software Reset */ #define SYSCON_SRUARTR(n) (1 << (n)) /* Bit n: UART Module n Software Reset */ # define SYSCON_SRUARTR_R0 (1 << 0) /* Bit 0: UART Module 0 Software Reset */ @@ -952,7 +963,7 @@ # define SYSCON_RCGCTIMER_R4 (1 << 4) /* Bit 4: 16/32-Bit General-Purpose Timer 4 Run Mode Clock Gating Control */ # define SYSCON_RCGCTIMER_R5 (1 << 5) /* Bit 5: 16/32-Bit General-Purpose Timer 5 Run Mode Clock Gating Control */ -/* GPIO Run Mode Clock Gating Control*/ +/* GPIO Run Mode Clock Gating Control */ #define SYSCON_RCGCGPIO(n) (1 << (n)) /* Bit n: 16/32-Bit GPIO Port n Run Mode Clock Gating Control */ # define SYSCON_RCGCGPIO_R0 (1 << 0) /* Bit 0: 16/32-Bit GPIO Port A Run Mode Clock Gating Control */ @@ -971,7 +982,7 @@ # define SYSCON_RCGCGPIO_R13 (1 << 13) /* Bit 13: 16/32-Bit GPIO Port P Run Mode Clock Gating Control */ # define SYSCON_RCGCGPIO_R14 (1 << 14) /* Bit 14: 16/32-Bit GPIO Port Q Run Mode Clock Gating Control */ -/* uDMA Run Mode Clock Gating Control*/ +/* uDMA Run Mode Clock Gating Control */ #define SYSCON_RCGCDMA_R0 (1 << 0) /* Bit 0: μDMA Module Run Mode Clock Gating Control */ @@ -979,7 +990,7 @@ #define SYSCON_RCGCHIB_R0 (1 << 0) /* Bit 0: Hibernation Module Run Mode Clock Gating Control */ -/* UART Run Mode Clock Gating Control*/ +/* UART Run Mode Clock Gating Control */ #define SYSCON_RCGCUART(n) (1 << (n)) /* Bit n: UART Module n Run Mode Clock Gating Control */ # define SYSCON_RCGCUART_R0 (1 << 0) /* Bit 0: UART Module 0 Run Mode Clock Gating Control */ @@ -991,7 +1002,7 @@ # define SYSCON_RCGCUART_R6 (1 << 6) /* Bit 6: UART Module 6 Run Mode Clock Gating Control */ # define SYSCON_RCGCUART_R7 (1 << 7) /* Bit 7: UART Module 7 Run Mode Clock Gating Control */ -/* SSI Run Mode Clock Gating Control*/ +/* SSI Run Mode Clock Gating Control */ #define SYSCON_RCGCSSI(n) (1 << (n)) /* Bit n: SSI Module n Run Mode Clock Gating Control */ # define SYSCON_RCGCSSI_R0 (1 << 0) /* Bit 0: SSI Module 0 Run Mode Clock Gating Control */ @@ -1412,7 +1423,8 @@ # define SYSCON_PRWTIMER_R4 (1 << 4) /* Bit 4: 32/64-Bit Wide General-Purpose Timer 4 Peripheral Ready */ # define SYSCON_PRWTIMER_R5 (1 << 5) /* Bit 5: 32/64-Bit Wide General-Purpose Timer 5 Peripheral Ready */ -/* System Control Legacy Register Bit Definitions *******************************************/ +/* System Control Legacy Register Bit Definitions ***************************/ + /* Device Capabilities 0 */ #define SYSCON_DC0_FLASHSZ_SHIFT 0 /* Bits 15-0: FLASH Size */ @@ -1673,12 +1685,14 @@ # define SYSCON_RCGC0_MAXADC0_250KSPS (1 << SYSCON_RCGC0_MAXADC0SPD_SHIFT) # define SYSCON_RCGC0_MAXADC0_500KSPS (2 << SYSCON_RCGC0_MAXADC0SPD_SHIFT) # define SYSCON_RCGC0_MAXADC0_1MSPS (3 << SYSCON_RCGC0_MAXADC0SPD_SHIFT) + #define SYSCON_RCGC0_MAXADC1SPD_SHIFT (8) /* Bits 10-11: ADC1 Sample Speed */ #define SYSCON_RCGC0_MAXADC1SPD_MASK (3 << SYSCON_RCGC0_MAXADC1SPD_SHIFT) # define SYSCON_RCGC0_MAXADC1_125KSPS (0 << SYSCON_RCGC0_MAXADC1SPD_SHIFT) # define SYSCON_RCGC0_MAXADC1_250KSPS (1 << SYSCON_RCGC0_MAXADC1SPD_SHIFT) # define SYSCON_RCGC0_MAXADC1_500KSPS (2 << SYSCON_RCGC0_MAXADC1SPD_SHIFT) # define SYSCON_RCGC0_MAXADC1_1MSPS (3 << SYSCON_RCGC0_MAXADC1SPD_SHIFT) + #define SYSCON_RCGC0_ADC0 (1 << 16) /* Bit 16: ADC0 Clock Gating Control */ #define SYSCON_RCGC0_ADC1 (1 << 17) /* Bit 17: ADC1 Clock Gating Control */ #define SYSCON_RCGC0_PWM0 (1 << 20) /* Bit 20: PWM0 Clock Gating Control */ @@ -1833,16 +1847,16 @@ #define TIVA_SYSCON_NVMSTAT_FWB (1 << 0) /* Bit 0: 32 Word Flash Write Buffer Available */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C123_SYSCONTROL_H */ diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c123_timer.h b/arch/arm/src/tiva/hardware/tm4c/tm4c123_timer.h index ed34fa81dde..4038c0818aa 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c123_timer.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c123_timer.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tm4c/tm4c123_timer.h * * Originally: @@ -44,23 +44,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_TM4C123_TIMER_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_TM4C123_TIMER_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* GPTM register offsets ************************************************************/ +/* GPTM register offsets ****************************************************/ #define TIVA_TIMER_CFG_OFFSET 0x0000 /* GPTM Configuration */ #define TIVA_TIMER_TAMR_OFFSET 0x0004 /* GPTM Timer A Mode */ @@ -90,7 +90,7 @@ #define TIVA_TIMER_TBPV_OFFSET 0x0068 /* GPTM Timer B Prescale Value */ #define TIVA_TIMER_PP_OFFSET 0x0fc0 /* GPTM Peripheral Properties */ -/* GPTM register addresses **********************************************************/ +/* GPTM register addresses **************************************************/ #if TIVA_NTIMERS > 0 #define TIVA_TIMER0_CFG (TIVA_TIMER0_BASE + TIVA_TIMER_CFG_OFFSET) @@ -325,7 +325,8 @@ #define TIVA_TIMER7_PP (TIVA_TIMER7_BASE + TIVA_TIMER_PP_OFFSET) #endif /* TIVA_NTIMERS > 7 */ -/* GPTM register bit definitions ****************************************************/ +/* GPTM register bit definitions ********************************************/ + /* GPTM Configuration (CFG) */ #define TIMER_CFG_CFG_SHIFT 0 /* Bits 2-0: Configuration */ @@ -341,18 +342,25 @@ # define TIMER_TnMR_TnMR_ONESHOT (1 << TIMER_TnMR_TnMR_SHIFT) /* One-Shot Timer mode */ # define TIMER_TnMR_TnMR_PERIODIC (2 << TIMER_TnMR_TnMR_SHIFT) /* Periodic Timer mode */ # define TIMER_TnMR_TnMR_CAPTURE (3 << TIMER_TnMR_TnMR_SHIFT) /* Capture mode */ + #define TIMER_TnMR_TnCMR_SHIFT (2) /* Bit 2: Timer A/B Capture Mode */ + #define TIMER_TnMR_TnCMR (1 << TIMER_TnMR_TnCMR_SHIFT) /* Bit 2: Timer A/B Capture Mode */ # define TIMER_TnMR_TnCMR_EDGECOUNT (0 << TIMER_TnMR_TnCMR_SHIFT) /* Edge-Count mode */ # define TIMER_TnMR_TnCMR_EDGETIME (1 << TIMER_TnMR_TnCMR_SHIFT) /* Edge-Time mode */ + #define TIMER_TnMR_TnAMS_SHIFT (3) /* Bit 3: Timer A/B Alternate Mode Select */ + #define TIMER_TnMR_TnAMS (1 << TIMER_TnMR_TnAMS_SHIFT) /* Bit 3: Timer A/B Alternate Mode Select */ # define TIMER_TnMR_TnAMS_CAPTURE (0 << TIMER_TnMR_TnAMS_SHIFT) /* Capture mode is enabled */ # define TIMER_TnMR_TnAMS_PWM (1 << TIMER_TnMR_TnAMS_SHIFT) /* PWM mode is enabled */ + #define TIMER_TnMR_TnCDIR_SHIFT (4) /* Bit 4: Timer A/B Count Direction */ + #define TIMER_TnMR_TnCDIR (1 << TIMER_TnMR_TnCDIR_SHIFT) /* Bit 4: Timer A/B Count Direction */ # define TIMER_TnMR_TnCDIR_DOWN (0 << TIMER_TnMR_TnCDIR_SHIFT) /* Timer counts down */ # define TIMER_TnMR_TnCDIR_UP (1 << TIMER_TnMR_TnCDIR_SHIFT) /* Timer counts up (one-shot/periodic modes) */ + #define TIMER_TnMR_TnMIE (1 << 5) /* Bit 5: Timer A/B Match Interrupt Enable */ #define TIMER_TnMR_TnWOT (1 << 6) /* Bit 6: GPTM Timer A/B Wait-on-Trigger */ #define TIMER_TnMR_TnSNAPS (1 << 7) /* Bit 7: GPTM Timer A/B Snap-Shot Mode */ @@ -370,6 +378,7 @@ # define TIMER_CTL_TAEVENT_POS (0 << TIMER_CTL_TAEVENT_SHIFT) /* Positive edge */ # define TIMER_CTL_TAEVENT_NEG (1 << TIMER_CTL_TAEVENT_SHIFT) /* Negative edge */ # define TIMER_CTL_TAEVENT_BOTH (3 << TIMER_CTL_TAEVENT_SHIFT) /* Both edges */ + #define TIMER_CTL_RTCEN (1 << 4) /* Bit 4: GPTM RTC Stall Enable */ #define TIMER_CTL_TAOTE (1 << 5) /* Bit 5: GPTM Timer A Output Trigger Enable */ #define TIMER_CTL_TAPWML (1 << 6) /* Bit 6: GPTM Timer A PWM Output Level */ @@ -380,6 +389,7 @@ # define TIMER_CTL_TBEVENT_POS (0 << TIMER_CTL_TBEVENT_SHFIT) /* Positive edge */ # define TIMER_CTL_TBEVENT_NEG (1 << TIMER_CTL_TBEVENT_SHFIT) /* Negative edge */ # define TIMER_CTL_TBEVENT_BOTH (3 << TIMER_CTL_TBEVENT_SHFIT) /* Both edges */ + #define TIMER_CTL_TBOTE (1 << 13) /* Bit 13: GPTM Timer B Output Trigger Enable */ #define TIMER_CTL_TBPWML (1 << 14) /* Bit 14: GPTM Timer B PWM Output Level */ @@ -528,8 +538,11 @@ #define TIMER_ALLINTS 0x00010f1f /* GPTM Timer A Interval Load (TAILR) (32-bit value) */ + /* GPTM Timer B Interval Load (TBILR) (32-bit value) */ + /* GPTM Timer A Match (TAMATCHR) (32-bit value) */ + /* GPTM Timer B Match (TBMATCHR) (32-bit value) */ /* GPTM Timer A/B Prescale (TnPR) */ @@ -545,8 +558,11 @@ # define TIMER_TnPMR_TnPSMR(n) ((uint32_t)(n) << TIMER_TnPMR_TnPSMR_SHIFT) /* GPTM Timer A (TAR) (16/32-bit value) */ + /* GPTM Timer B (TBR) (16/32-bit value) */ + /* GPTM Timer A Value (TAV) (16/32-bit value) */ + /* GPTM Timer B Value (TBV) (16/32-bit value) */ /* GPTM RTC Predivide (RTCPD) */ diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c129_gpio.h b/arch/arm/src/tiva/hardware/tm4c/tm4c129_gpio.h index c704eb4fe14..6e5c83bcaca 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c129_gpio.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c129_gpio.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tm4c/tm4c129_gpio.h * * Copyright (C) 2009-2010, 2013, 2018 Gregory Nutt. All rights reserved. @@ -32,20 +32,21 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C129_GPIO_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C129_GPIO_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ + /* REVISIT: Why do we not use the AHB aperture for all GPIO accesses? */ #define TIVA_GPIOK_BASE TIVA_GPIOKAHB_BASE @@ -58,7 +59,7 @@ #define TIVA_GPIOS_BASE TIVA_GPIOSAHB_BASE #define TIVA_GPIOT_BASE TIVA_GPIOTAHB_BASE -/* GPIO Register Offsets ************************************************************/ +/* GPIO Register Offsets ****************************************************/ #define TIVA_GPIO_DATA_OFFSET 0x0000 /* GPIO Data */ #define TIVA_GPIO_DIR_OFFSET 0x0400 /* GPIO Direction */ @@ -84,13 +85,13 @@ #define TIVA_GPIO_PCTL_OFFSET 0x052c /* GPIO Port Control */ #define TIVA_GPIO_ADCCTL_OFFSET 0x0530 /* GPIO ADC Control */ #define TIVA_GPIO_DMACTL_OFFSET 0x0534 /* GPIO DMA Control */ -#define TIVA_GPIO_SI_OFFSET 0x0538 /* GPIO Select Interrupt */ -#define TIVA_GPIO_DR12R_OFFSET 0x053c /* GPIO 12-mA Drive Select */ -#define TIVA_GPIO_WAKEPEN_OFFSET 0x0540 /* GPIO Wake Pin Enable */ -#define TIVA_GPIO_WAKELVL_OFFSET 0x0544 /* GPIO Wake Level */ -#define TIVA_GPIO_WAKESTAT_OFFSET 0x0548 /* GPIO Wake Status */ -#define TIVA_GPIO_PP_OFFSET 0x0fc0 /* GPIO Peripheral Property */ -#define TIVA_GPIO_PC_OFFSET 0x0fc4 /* GPIO Peripheral Configuration */ +#define TIVA_GPIO_SI_OFFSET 0x0538 /* GPIO Select Interrupt */ +#define TIVA_GPIO_DR12R_OFFSET 0x053c /* GPIO 12-mA Drive Select */ +#define TIVA_GPIO_WAKEPEN_OFFSET 0x0540 /* GPIO Wake Pin Enable */ +#define TIVA_GPIO_WAKELVL_OFFSET 0x0544 /* GPIO Wake Level */ +#define TIVA_GPIO_WAKESTAT_OFFSET 0x0548 /* GPIO Wake Status */ +#define TIVA_GPIO_PP_OFFSET 0x0fc0 /* GPIO Peripheral Property */ +#define TIVA_GPIO_PC_OFFSET 0x0fc4 /* GPIO Peripheral Configuration */ #define TIVA_GPIO_PERIPHID4_OFFSET 0x0fd0 /* GPIO Peripheral Identification 4 */ #define TIVA_GPIO_PERIPHID5_OFFSET 0x0fd4 /* GPIO Peripheral Identification 5 */ @@ -105,7 +106,7 @@ #define TIVA_GPIO_PCELLID2_OFFSET 0x0ff8 /* GPIO PrimeCell Identification 2 */ #define TIVA_GPIO_PCELLID3_OFFSET 0x0ffc /* GPIO PrimeCell Identification 3*/ -/* GPIO Register Addresses **********************************************************/ +/* GPIO Register Addresses **************************************************/ #if TIVA_NPORTS > 0 @@ -539,7 +540,7 @@ # define TIVA_GPIOJ_PCELLID3 (TIVA_GPIOJ_BASE + TIVA_GPIO_PCELLID3_OFFSET) #endif -/* GPIO Register Bitfield Definitions ***********************************************/ +/* GPIO Register Bitfield Definitions ***************************************/ /* GPIO Interrupt Mask */ @@ -614,16 +615,16 @@ #define GPIO_PC_EDM7_SHIFT (14) /* Bits 14-15: Extended Drive Mode Bit 7 */ #define GPIO_PC_EDM7_MASK (3 << GPIO_PC_EDM7_SHIFT) -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C129_GPIO_H */ diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c129_i2c.h b/arch/arm/src/tiva/hardware/tm4c/tm4c129_i2c.h index e10af760cf2..6e41bfa4b86 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c129_i2c.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c129_i2c.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tm4c/tm4c129_i2c.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C129_I2C_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C129_I2C_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* I2C Register Offsets *************************************************************/ +/* I2C Register Offsets *****************************************************/ /* I2C Master */ @@ -69,7 +69,7 @@ #define TIVA_I2CSC_PP_OFFSET 0x0fc0 /* I2C Peripheral Properties */ #define TIVA_I2CSC_PC_OFFSET 0x0fc4 /* I2C Peripheral Configuration */ -/* I2C Register Addresses ***********************************************************/ +/* I2C Register Addresses ***************************************************/ #if TIVA_NI2C > 0 @@ -471,7 +471,7 @@ #endif /* TIVA_NI2C > 9 */ -/* I2C_Register Bit Definitions *****************************************************/ +/* I2C_Register Bit Definitions *********************************************/ /* I2C Master Slave Address (I2CM_SA) */ @@ -728,13 +728,13 @@ #define I2CSC_PC_HS (1 << 0) /* Bit 0: High-Speed Capable */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c129_sysctrl.h b/arch/arm/src/tiva/hardware/tm4c/tm4c129_sysctrl.h index ac4030a83cc..0fe0a1366f3 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c129_sysctrl.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c129_sysctrl.h @@ -1,4 +1,4 @@ -/******************************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/hardware/tm4c/tm4c129_sysctrl.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ********************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C129_SYSCONTROL_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C129_SYSCONTROL_H -/******************************************************************************************** +/**************************************************************************** * Included Files - ********************************************************************************************/ + ****************************************************************************/ #include -/******************************************************************************************** +/**************************************************************************** * Pre-processor Definitions - ********************************************************************************************/ + ****************************************************************************/ + +/* System Control Register Offsets ******************************************/ -/* System Control Register Offsets **********************************************************/ /* System Control Registers (System Control Offset) */ #define TIVA_SYSCON_DID0_OFFSET 0x0000 /* Device Identification 0 */ @@ -247,7 +248,7 @@ #define TIVA_SYSCON_CCMCGREQ_OFFSET 0x0204 /* Cryptographic Modules Clock Gating Request */ -/* System Control Legacy Register Offsets ***************************************************/ +/* System Control Legacy Register Offsets ***********************************/ #define TIVA_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */ #define TIVA_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */ @@ -277,7 +278,7 @@ #define TIVA_SYSCON_DC9_OFFSET 0x190 /* Device Capabilities */ -/* System Control Register Addresses ********************************************************/ +/* System Control Register Addresses ****************************************/ /* System Control Registers (System Control Offset) */ @@ -494,7 +495,7 @@ #define TIVA_SYSCON_CCMCGREQ (TIVA_CCM_BASE+TIVA_SYSCON_CCMCGREQ_OFFSET) -/* System Control Legacy Register Addresses *************************************************/ +/* System Control Legacy Register Addresses *********************************/ #define TIVA_SYSCON_DC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC0_OFFSET) #define TIVA_SYSCON_DC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC1_OFFSET) @@ -524,7 +525,8 @@ #define TIVA_SYSCON_DC9 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC9_OFFSET) -/* System Control Register Bit Definitions **************************************************/ +/* System Control Register Bit Definitions **********************************/ + /* System Control Registers (System Control Offset) */ /* Device Identification 0 */ @@ -534,15 +536,18 @@ # define SYSCON_DID0_MIN_0 (0 << SYSCON_DID0_MINOR_SHIFT) /* Initial device or revision */ # define SYSCON_DID0_MIN_1 (1 << SYSCON_DID0_MINOR_SHIFT) /* First metal layer change */ # define SYSCON_DID0_MIN_2 (2 << SYSCON_DID0_MINOR_SHIFT) /* Second metal layer change */ + #define SYSCON_DID0_MAJOR_SHIFT 8 /* Bits 8-15: Major Revision of the device */ #define SYSCON_DID0_MAJOR_MASK (0xff << SYSCON_DID0_MAJOR_SHIFT) # define SYSCON_DID0_MAJ_REVA (0 << SYSCON_DID0_MAJOR_SHIFT) /* Revision A */ # define SYSCON_DID0_MAJ_REVB (1 << SYSCON_DID0_MAJOR_SHIFT) /* Revision B */ # define SYSCON_DID0_MAJ_REVC (2 << SYSCON_DID0_MAJOR_SHIFT) /* Revision C */ + #define SYSCON_DID0_CLASS_SHIFT 16 /* Bits 16-23: Device Class */ #define SYSCON_DID0_CLASS_MASK (0xff << SYSCON_DID0_CLASS_SHIFT) -# define SYSCON_DID0_CLASS_TM4C123 (5 << SYSCON_DID0_CLASS_SHIFT) /* Tiva TM4C123x and TM4E123x */ +# define SYSCON_DID0_CLASS_TM4C123 (5 << SYSCON_DID0_CLASS_SHIFT) /* Tiva TM4C123x and TM4E123x */ # define SYSCON_DID0_CLASS_TM4C129 (10 << SYSCON_DID0_CLASS_SHIFT) /* Tiva TM4C129-class */ + #define SYSCON_DID0_VER_SHIFT 28 /* Bits 28-30: DID0 Version */ #define SYSCON_DID0_VER_MASK (7 << SYSCON_DID0_VER_SHIFT) # define SYSCON_DID0_VER_1 (1 << SYSCON_DID0_VER_SHIFT) /* Second version of DID0 format */ @@ -554,17 +559,20 @@ # define SYSCON_DID1_QUAL_ES (0 << SYSCON_DID1_QUAL_SHIFT) /* Engineering Sample */ # define SYSCON_DID1_QUAL_PP (1 << SYSCON_DID1_QUAL_SHIFT) /* Pilot Production */ # define SYSCON_DID1_QUAL_FQ (2 << SYSCON_DID1_QUAL_SHIFT) /* Fully Qualified */ + #define SYSCON_DID1_ROHS (1 << 2) /* Bit 2: RoHS-Compliance */ #define SYSCON_DID1_PKG_SHIFT 3 /* Bits 3-4: Package Type */ #define SYSCON_DID1_PKG_MASK (3 << SYSCON_DID1_PKG_SHIFT) # define SYSCON_DID1_PKG_QFP (1 << SYSCON_DID1_PKG_SHIFT) /* QFP package */ # define SYSCON_DID1_PKG_BGA (2 << SYSCON_DID1_PKG_SHIFT) /* BGA package */ + #define SYSCON_DID1_TEMP_SHIFT 5 /* Bits 5-7: Temperature Range */ #define SYSCON_DID1_TEMP_MASK (7 << SYSCON_DID1_TEMP_SHIFT) # define SYSCON_DID1_TEMP_C (0 << SYSCON_DID1_TEMP_SHIFT) /* Commercial temperature */ # define SYSCON_DID1_TEMP_I (1 << SYSCON_DID1_TEMP_SHIFT) /* Industrial temperature */ # define SYSCON_DID1_TEMP_E (2 << SYSCON_DID1_TEMP_SHIFT) /* Extended temperature */ # define SYSCON_DID1_TEMP_IE (3 << SYSCON_DID1_TEMP_SHIFT) /* Industrial and extended */ + #define SYSCON_DID1_PINCOUNT_SHIFT 13 /* Bits 13-15: Package Pin Count */ #define SYSCON_DID1_PINCOUNT_MASK (7 << SYSCON_DID1_PINCOUNT_SHIFT) # define SYSCON_DID1_PINCNT_100 (2 << SYSCON_DID1_PINCOUNT_SHIFT) /* 100-pin LQFP */ @@ -573,16 +581,19 @@ # define SYSCON_DID1_PINCNT_157 (5 << SYSCON_DID1_PINCOUNT_SHIFT) /* 157-pin BGA */ # define SYSCON_DID1_PINCNT_128 (6 << SYSCON_DID1_PINCOUNT_SHIFT) /* 128-pin TQFP */ # define SYSCON_DID1_PINCNT_1212 (7 << SYSCON_DID1_PINCOUNT_SHIFT) /* 212-pin BGA */ + #define SYSCON_DID1_PARTNO_SHIFT 16 /* Bits 16-23: Part Number */ #define SYSCON_DID1_PARTNO_MASK (0xff << SYSCON_DID1_PARTNO_SHIFT) # define SYSCON_DID1_TM4C1294NCPDT (31 << SYSCON_DID1_PARTNO_SHIFT) /* TM4C1294NCPDT */ # define SYSCON_DID1_TM4C129XNCZAD (50 << SYSCON_DID1_PARTNO_SHIFT) /* TM4C129XNCZAD */ + #define SYSCON_DID1_FAM_SHIFT 24 /* Bits 24-27: Family */ #define SYSCON_DID1_FAM_MASK (15 << SYSCON_DID1_FAM_SHIFT) # define SYSCON_DID1_FAM_TIVA (0 << SYSCON_DID1_FAM_SHIFT) /* Tiva C family */ + #define SYSCON_DID1_VER_SHIFT 28 /* Bits 28-31: DID1 Version */ #define SYSCON_DID1_VER_MASK (15 << SYSCON_DID1_VER_SHIFT) - #define SYSCON_DID1_VER_1 (1 << SYSCON_DID1_VER_SHIFT) /* Second version of DID1 format */ +# define SYSCON_DID1_VER_1 (1 << SYSCON_DID1_VER_SHIFT) /* Second version of DID1 format */ /* Power-Temp Brown Out Control */ @@ -592,6 +603,7 @@ # define SYSCON_PTBOCTL_VDD_UBOR_SYSINT (1 << SYSCON_PTBOCTL_VDD_UBOR_SHIFT) /* System control interrupt */ # define SYSCON_PTBOCTL_VDD_UBOR_NMI (2 << SYSCON_PTBOCTL_VDD_UBOR_SHIFT) /* NMI */ # define SYSCON_PTBOCTL_VDD_UBOR_RST (3 << SYSCON_PTBOCTL_VDD_UBOR_SHIFT) /* Reset */ + #define SYSCON_PTBOCTL_VDDA_UBOR_SHIFT (8) /* Bits 8-9: VDDA under BOR Event Action */ #define SYSCON_PTBOCTL_VDDA_UBOR_MASK (3 << SYSCON_PTBOCTL_VDDA_UBOR_SHIFT) # define SYSCON_PTBOCTL_VDDA_UBOR_NONE (0 << SYSCON_PTBOCTL_VDDA_UBOR_SHIFT) /* No Action */ @@ -671,19 +683,23 @@ #define SYSCON_RSCLKCFG_PSYSDIV_SHIFT (0) /* Bits 0-9:PLL System Clock Divisor */ #define SYSCON_RSCLKCFG_PSYSDIV_MASK (0x3ff << SYSCON_RSCLKCFG_PSYSDIV_SHIFT) # define SYSCON_RSCLKCFG_PSYSDIV(n) ((uint32_t)(n) << SYSCON_RSCLKCFG_PSYSDIV_SHIFT) + #define SYSCON_RSCLKCFG_OSYSDIV_SHIFT (10) /* Bits 10-19: Oscillator System Clock Divisor */ #define SYSCON_RSCLKCFG_OSYSDIV_MASK (0x3ff << SYSCON_RSCLKCFG_OSYSDIV_SHIFT) # define SYSCON_RSCLKCFG_OSYSDIV(n) ((uint32_t)(n) << SYSCON_RSCLKCFG_OSYSDIV_SHIFT) + #define SYSCON_RSCLKCFG_OSCSRC_SHIFT (20) /* Bits 20-23: Oscillator Source */ #define SYSCON_RSCLKCFG_OSCSRC_MASK (15 << SYSCON_RSCLKCFG_OSCSRC_SHIFT) # define SYSCON_RSCLKCFG_OSCSRC_PIOSC (0 << SYSCON_RSCLKCFG_OSCSRC_SHIFT) /* PIOSC is source */ # define SYSCON_RSCLKCFG_OSCSRC_LFIOSC (1 << SYSCON_RSCLKCFG_OSCSRC_SHIFT) /* LFIOSC is source */ # define SYSCON_RSCLKCFG_OSCSRC_MOSC (3 << SYSCON_RSCLKCFG_OSCSRC_SHIFT) /* MOSC is source */ # define SYSCON_RSCLKCFG_OSCSRC_RTC (4 << SYSCON_RSCLKCFG_OSCSRC_SHIFT) /* RTCOSC is source */ + #define SYSCON_RSCLKCFG_PLLSRC_SHIFT (24) /* Bits 24-27: PLL Source */ #define SYSCON_RSCLKCFG_PLLSRC_MASK (15 << SYSCON_RSCLKCFG_PLLSRC_SHIFT) # define SYSCON_RSCLKCFG_PLLSRC_PIOSC (0 << SYSCON_RSCLKCFG_PLLSRC_SHIFT) /* PIOSC is clock source */ # define SYSCON_RSCLKCFG_PLLSRC_MOSC (3 << SYSCON_RSCLKCFG_PLLSRC_SHIFT) /* MOSC is the clock source */ + #define SYSCON_RSCLKCFG_USEPLL (1 << 28) /* Bit 28: Use PLL */ #define SYSCON_RSCLKCFG_ACG (1 << 29) /* Bit 29: Auto Clock Gating */ #define SYSCON_RSCLKCFG_NEWFREQ (1 << 30) /* Bit 30: New PLLFREQ Accept */ @@ -694,6 +710,7 @@ #define SYSCON_MEMTIM0_FWS_SHIFT (0) /* Bits 0-3: Flash Wait State */ #define SYSCON_MEMTIM0_FWS_MASK (15 << SYSCON_MEMTIM0_FWS_SHIFT) # define SYSCON_MEMTIM0_FWS(n) ((uint32_t)(n) << SYSCON_MEMTIM0_FWS_SHIFT) + #define SYSCON_MEMTIM0_FBCE (1 << 5) /* Bit 5: Flash Bank Clock Edge */ #define SYSCON_MEMTIM0_FBCHT_SHIFT (6) /* Bits 6-9: Flash Bank Clock High Time */ #define SYSCON_MEMTIM0_FBCHT_MASK (15 << SYSCON_MEMTIM0_FBCHT_SHIFT) @@ -706,9 +723,11 @@ # define SYSCON_MEMTIM0_FBCHT_3p5 (6 << SYSCON_MEMTIM0_FBCHT_SHIFT) /* 3.5 system clock periods */ # define SYSCON_MEMTIM0_FBCHT_4 (7 << SYSCON_MEMTIM0_FBCHT_SHIFT) /* 4 system clock periods */ # define SYSCON_MEMTIM0_FBCHT_4p5 (8 << SYSCON_MEMTIM0_FBCHT_SHIFT) /* 4.5 system clock periods */ + #define SYSCON_MEMTIM0_EWS_SHIFT (16) /* Bits 16-19: EEPROM Wait States */ #define SYSCON_MEMTIM0_EWS_MASK (15 << SYSCON_MEMTIM0_EWS_SHIFT) # define SYSCON_MEMTIM0_EWS(n) ((uint32_t)(n) << SYSCON_MEMTIM0_EWS_SHIFT) + #define SYSCON_MEMTIM0_EBCE (1 << 21) /* Bit 21: EEPROM Bank Clock Edge */ #define SYSCON_MEMTIM0_EBCHT_SHIFT (22) /* Bits 22-25: EEPROM Clock High Time */ #define SYSCON_MEMTIM0_EBCHT_MASK (15 << SYSCON_MEMTIM0_EBCHT_SHIFT) @@ -737,12 +756,14 @@ #define SYSCON_DSCLKCFG_DSSYSDIV_SHIFT (0) /* Bits 0-9: Deep Sleep Clock Divisor */ #define SYSCON_DSCLKCFG_DSSYSDIV_MASK (0x3ff << SYSCON_DSCLKCFG_DSSYSDIV_SHIFT) # define SYSCON_DSCLKCFG_DSSYSDIV(n) ((uint32_t)(n) << SYSCON_DSCLKCFG_DSSYSDIV_SHIFT) + #define SYSCON_DSCLKCFG_DSOSCSRC_SHIFT (20) /* Bits 20-23: Deep Sleep Oscillator Source */ #define SYSCON_DSCLKCFG_DSOSCSRC_MASK (15 << SYSCON_DSCLKCFG_DSOSCSRC_SHIFT) # define SYSCON_DSCLKCFG_DSOSCSRC_PIOSC (0 << SYSCON_DSCLKCFG_DSOSCSRC_SHIFT) /* PIOSC */ # define SYSCON_DSCLKCFG_DSOSCSRC_LFIOSC (2 << SYSCON_DSCLKCFG_DSOSCSRC_SHIFT) /* LFIOSC */ # define SYSCON_DSCLKCFG_DSOSCSRC_MOSC (3 << SYSCON_DSCLKCFG_DSOSCSRC_SHIFT) /* MOSC */ # define SYSCON_DSCLKCFG_DSOSCSRC_RTC (4 << SYSCON_DSCLKCFG_DSOSCSRC_SHIFT) /* RTCOSC */ + #define SYSCON_DSCLKCFG_MOSCDPD (1 << 30) /* Bit 30: MOSC Disable Power Down */ #define SYSCON_DSCLKCFG_PIOSCPD (1 << 31) /* Bit 31: PIOSC Power Down */ @@ -751,11 +772,13 @@ #define SYSCON_DIVSCLK_DIV_SHIFT (0) /* Bits 0-7: Divisor Value */ #define SYSCON_DIVSCLK_DIV_MASK (0xff << SYSCON_DIVSCLK_DIV_SHIFT) # define SYSCON_DIVSCLK_DIV(n) ((uint32_t)(n) << SYSCON_DIVSCLK_DIV_SHIFT) + #define SYSCON_DIVSCLK_SRC_SHIFT (16) /* Bits 16-17: Clock Source */ #define SYSCON_DIVSCLK_SRC_MASK (3 << SYSCON_DIVSCLK_SRC_SHIFT) # define SYSCON_DIVSCLK_SRC_SYSCLK (0 << SYSCON_DIVSCLK_SRC_SHIFT) /* System Clock */ # define SYSCON_DIVSCLK_SRC_PIOSC (1 << SYSCON_DIVSCLK_SRC_SHIFT) /* PIOSC */ # define SYSCON_DIVSCLK_SRC_MOSC (2 << SYSCON_DIVSCLK_SRC_SHIFT) /* MOSC */ + #define SYSCON_DIVSCLK_EN (1 << 31) /* Bit31: DIVSCLK Enable */ /* System Properties */ @@ -774,6 +797,7 @@ #define SYSCON_PIOSCCAL_UT_SHIFT (0) /* Bits 0-6: User Trim Value */ #define SYSCON_PIOSCCAL_UT_MASK (0x7f << SYSCON_PIOSCCAL_UT_SHIFT) # define SYSCON_PIOSCCAL_UT(n) ((uint32_t)(n) << SYSCON_PIOSCCAL_UT_SHIFT) + #define SYSCON_PIOSCCAL_UPDATE (1 << 8) /* Bit 8: Update Trim */ #define SYSCON_PIOSCCAL_CAL (1 << 9) /* Bit 9: Start Calibration */ #define SYSCON_PIOSCCAL_UTEN (1 << 31) /* Bit 31: Use User Trim Value */ @@ -783,12 +807,14 @@ #define SYSCON_PIOSCSTAT_CT_SHIFT (0) /* Bits 0-6: Calibration Trim Value */ #define SYSCON_PIOSCSTAT_CT_MASK (0x7f << SYSCON_PIOSCSTAT_CT_SHIFT) # define SYSCON_PIOSCSTAT_CT(n) ((uint32_t)(n) << SYSCON_PIOSCSTAT_CT_SHIFT) + #define SYSCON_PIOSCSTAT_RESULT_SHIFT (8) /* Bits 8-9: Calibration Result */ #define SYSCON_PIOSCSTAT_RESULT_MASK (3 << SYSCON_PIOSCSTAT_RESULT_SHIFT) # define SYSCON_PIOSCSTAT_RESULT(n) ((uint32_t)(n) << SYSCON_PIOSCSTAT_RESULT_SHIFT) # define SYSCON_PIOSCSTAT_CRNONE (0 << SYSCON_PIOSCSTAT_RESULT_SHIFT) # define SYSCON_PIOSCSTAT_CRPASS (1 << SYSCON_PIOSCSTAT_RESULT_SHIFT) # define SYSCON_PIOSCSTAT_CRFAIL (2 << SYSCON_PIOSCSTAT_RESULT_SHIFT) + #define SYSCON_PIOSCSTAT_DT_SHIFT (16) /* Bits 16-22: Default Trim Value */ #define SYSCON_PIOSCSTAT_DT_MASK (0x7f << SYSCON_PIOSCSTAT_DT_SHIFT) # define SYSCON_PIOSCSTAT_DT(n) ((uint32_t)(n) << SYSCON_PIOSCSTAT_DT_SHIFT) @@ -798,9 +824,11 @@ #define SYSCON_PLLFREQ0_MINT_SHIFT (0) /* Bits 0-9: PLL M Integer Value */ #define SYSCON_PLLFREQ0_MINT_MASK (0x3ff << SYSCON_PLLFREQ0_MINT_SHIFT) # define SYSCON_PLLFREQ0_MINT(n) ((uint32_t)(n) << SYSCON_PLLFREQ0_MINT_SHIFT) + #define SYSCON_PLLFREQ0_MFRAC_SHIFT (10) /* Bits 10-19: PLL M Fractional Value */ #define SYSCON_PLLFREQ0_MFRAC_MASK (0x3ff << SYSCON_PLLFREQ0_MFRAC_SHIFT) # define SYSCON_PLLFREQ0_MFRAC(n) ((uint32_t)(n) << SYSCON_PLLFREQ0_MFRAC_SHIFT) + #define SYSCON_PLLFREQ0_PLLPWR (1 << 23) /* Bit 23: PLL Power */ /* PLL Frequency 1 */ @@ -808,6 +836,7 @@ #define SYSCON_PLLFREQ1_N_SHIFT (0) /* Bits 0-4: PLL N Value */ #define SYSCON_PLLFREQ1_N_MASK (31 << SYSCON_PLLFREQ1_N_SHIFT) # define SYSCON_PLLFREQ1_N(n) ((uint32_t)(n) << SYSCON_PLLFREQ1_N_SHIFT) + #define SYSCON_PLLFREQ1_Q_SHIFT (8) /* Bits 8-12: PLL Q Value */ #define SYSCON_PLLFREQ1_Q_MASK (31 << SYSCON_PLLFREQ1_Q_SHIFT) # define SYSCON_PLLFREQ1_Q(n) ((uint32_t)(n) << SYSCON_PLLFREQ1_Q_SHIFT) @@ -823,6 +852,7 @@ # define SYSCON_SLPPWRCFG_SRAMPM_ACTIVE (0 << SYSCON_SLPPWRCFG_SRAMPM_SHIFT) /* Active Mode */ # define SYSCON_SLPPWRCFG_SRAMPM_STANDBY (1 << SYSCON_SLPPWRCFG_SRAMPM_SHIFT) /* Standby Mode */ # define SYSCON_SLPPWRCFG_SRAMPM_LOWPWR (3 << SYSCON_SLPPWRCFG_SRAMPM_SHIFT) /* Low Power Mode */ + #define SYSCON_SLPPWRCFG_FLASHPM_SHIFT (4) /* Bits 5-4: Flash Power Modes */ #define SYSCON_SLPPWRCFG_FLASHPM_MASK (3 << SYSCON_SLPPWRCFG_FLASHPM_SHIFT) # define SYSCON_SLPPWRCFG_FLASHPM_ACTIVE (0 << SYSCON_SLPPWRCFG_FLASHPM_SHIFT) /* Active Mode */ @@ -835,14 +865,15 @@ # define SYSCON_DSLPPWRCFG_SRAMPM_ACTIVE (0 << SYSCON_DSLPPWRCFG_SRAMPM_SHIFT) /* Active Mode */ # define SYSCON_DSLPPWRCFG_SRAMPM_STANDBY (1 << SYSCON_DSLPPWRCFG_SRAMPM_SHIFT) /* Standby Mode */ # define SYSCON_DSLPPWRCFG_SRAMPM_LOWPWR (3 << SYSCON_DSLPPWRCFG_SRAMPM_SHIFT) /* Low Power Mode */ + #define SYSCON_DSLPPWRCFG_FLASHPM_SHIFT (4) /* Bits 5-4: Flash Power Modes */ #define SYSCON_DSLPPWRCFG_FLASHPM_MASK (3 << SYSCON_DSLPPWRCFG_FLASHPM_SHIFT) # define SYSCON_DSLPPWRCFG_FLASHPM_ACTIVE (0 << SYSCON_DSLPPWRCFG_FLASHPM_SHIFT) /* Active Mode */ # define SYSCON_DSLPPWRCFG_FLASHPM_LOWPWR (2 << SYSCON_DSLPPWRCFG_FLASHPM_SHIFT) /* Low Power Mode */ + #define SYSCON_DSLPPWRCFG_TSPD (1 << 8) /* Bit 8: Temperature Sense Power Down */ #define SYSCON_DSLPPWRCFG_LDOSM (1 << 9) /* Bit 9: LDO Sleep Mode */ - /* Non-Volatile Memory Information */ #define TIVA_SYSCON_NVMSTAT_FWB (1 << 0) /* Bit 0: 32 Word Flash Write Buffer Available */ @@ -858,6 +889,7 @@ # define SYSCON_LDOSPCTL_VLDO_1p10V (0x16 << SYSCON_LDOSPCTL_VLDO_SHIFT) /* 1.10 V */ # define SYSCON_LDOSPCTL_VLDO_1p15V (0x17 << SYSCON_LDOSPCTL_VLDO_SHIFT) /* 1.15 V */ # define SYSCON_LDOSPCTL_VLDO_1p20V (0x18 << SYSCON_LDOSPCTL_VLDO_SHIFT) /* 1.20 V */ + #define SYSCON_LDOSPCTL_VADJEN (1 << 31) /* Bit 31: Voltage Adjust Enable */ /* LDO Sleep Power Calibration */ @@ -871,6 +903,7 @@ # define SYSCON_LDOSPCAL_NOPLL_1p10V (0x16 << SYSCON_LDOSPCAL_NOPLL_SHIFT) /* 1.10 V */ # define SYSCON_LDOSPCAL_NOPLL_1p15V (0x17 << SYSCON_LDOSPCAL_NOPLL_SHIFT) /* 1.15 V */ # define SYSCON_LDOSPCAL_NOPLL_1p20V (0x18 << SYSCON_LDOSPCAL_NOPLL_SHIFT) /* 1.20 V */ + #define SYSCON_LDOSPCAL_WITHPLL_SHIFT (8) /* Bits 15-8: Sleep with PLL */ #define SYSCON_LDOSPCAL_WITHPLL_MASK (0xff << SYSCON_LDOSPCAL_WITHPLL_SHIFT) # define SYSCON_LDOSPCAL_WITHPLL_0p90V (0x12 << SYSCON_LDOSPCAL_WITHPLL_SHIFT) /* 0.90 V */ @@ -892,6 +925,7 @@ # define SYSCON_LDODPCTL_VLDO_1p10V (0x16 << SYSCON_LDODPCTL_VLDO_SHIFT) /* 1.10 V */ # define SYSCON_LDODPCTL_VLDO_1p15V (0x17 << SYSCON_LDODPCTL_VLDO_SHIFT) /* 1.15 V */ # define SYSCON_LDODPCTL_VLDO_1p20V (0x18 << SYSCON_LDODPCTL_VLDO_SHIFT) /* 1.20 V */ + #define SYSCON_LDODPCTL_VADJEN (1 << 31) /* Bit 31: Voltage Adjust Enable */ /* LDO Deep-Sleep Power Calibration */ @@ -905,6 +939,7 @@ # define SYSCON_LDODPCAL_NOPLL_1p10V (0x16 << SYSCON_LDODPCAL_NOPLL_SHIFT) /* 1.10 V */ # define SYSCON_LDODPCAL_NOPLL_1p15V (0x17 << SYSCON_LDODPCAL_NOPLL_SHIFT) /* 1.15 V */ # define SYSCON_LDODPCAL_NOPLL_1p20V (0x18 << SYSCON_LDODPCAL_NOPLL_SHIFT) /* 1.20 V */ + #define SYSCON_LDODPCAL_30KHZ_SHIFT (8) /* Bits 15-8: Deep-Sleep with IOSC */ #define SYSCON_LDODPCAL_30KHZ_MASK (0xff << SYSCON_LDODPCAL_30KHZ_SHIFT) # define SYSCON_LDODPCAL_30KHZ_0p90V (0x12 << SYSCON_LDODPCAL_30KHZ_SHIFT) /* 0.90 V */ @@ -935,14 +970,17 @@ #define SYSCON_RESBEHAVCTL_EXTRES_MASK (3 << SYSCON_RESBEHAVCTL_EXTRES_SHIFT) # define SYSCON_RESBEHAVCTL_EXTRES_SYSRST (2 << SYSCON_RESBEHAVCTL_EXTRES_SHIFT) /* System reset */ # define SYSCON_RESBEHAVCTL_EXTRES_POR (3 << SYSCON_RESBEHAVCTL_EXTRES_SHIFT) /* POR */ + #define SYSCON_RESBEHAVCTL_BOR_SHIFT (2) /* Bits 2-3: BOR Reset operation */ #define SYSCON_RESBEHAVCTL_BOR_MASK (3 << SYSCON_RESBEHAVCTL_BOR_SHIFT) # define SYSCON_RESBEHAVCTL_BOR_SYSRST (2 << SYSCON_RESBEHAVCTL_BOR_SHIFT) /* System reset */ # define SYSCON_RESBEHAVCTL_BOR_POR (3 << SYSCON_RESBEHAVCTL_BOR_SHIFT) /* POR */ + #define SYSCON_RESBEHAVCTL_WDOG0_SHIFT (4) /* Bits 4-5: Watchdog 0 Reset Operation */ #define SYSCON_RESBEHAVCTL_WDOG0_MASK (3 << SYSCON_RESBEHAVCTL_WDOG0_SHIFT) # define SYSCON_RESBEHAVCTL_WDOG0_SYSRST (2 << SYSCON_RESBEHAVCTL_WDOG0_SHIFT) /* System reset */ # define SYSCON_RESBEHAVCTL_WDOG0_POR (3 << SYSCON_RESBEHAVCTL_WDOG0_SHIFT) /* POR */ + #define SYSCON_RESBEHAVCTL_WDOG1_SHIFT (6) /* Bits 6-7: Watchdog 1 Reset Operation */ #define SYSCON_RESBEHAVCTL_WDOG1_MASK (3 << SYSCON_RESBEHAVCTL_WDOG1_SHIFT) # define SYSCON_RESBEHAVCTL_WDOG1_SYSRST (2 << SYSCON_RESBEHAVCTL_WDOG1_SHIFT) /* System reset */ @@ -953,8 +991,9 @@ #define SYSCON_HSSR_CDOFF_SHIFT (0) /* Bits 0-23: Command Descriptor Pointer */ #define SYSCON_HSSR_CDOFF_MASK (0xffffff << SYSCON_HSSR_CDOFF_SHIFT) # define SYSCON_HSSR_CDOFF(n) ((uint32_t)(n) << SYSCON_HSSR_CDOFF_SHIFT) -# define SYSCON_HSSR_CDOFF_NOREQ (0 << SYSCON_HSSR_CDOFF_SHIFT) /* No request pending */ +# define SYSCON_HSSR_CDOFF_NOREQ (0 << SYSCON_HSSR_CDOFF_SHIFT) /* No request pending */ # define SYSCON_HSSR_CDOFF_ERROR (0xffffff << SYSCON_HSSR_CDOFF_SHIFT) /* An error occurred */ + #define SYSCON_HSSR_KEY_SHIFT (24) /* Bit 24-31: Write Key */ #define SYSCON_HSSR_KEY_MASK (0xff << SYSCON_HSSR_KEY_SHIFT) # define SYSCON_HSSR_KEY (0xca << SYSCON_HSSR_KEY_SHIFT) /* Key value */ @@ -965,6 +1004,7 @@ #define SYSCON_USBPDS_PWRSTAT_MASK (3 << SYSCON_USBPDS_PWRSTAT_SHIFT) # define SYSCON_USBPDS_PWRSTAT_OFF (0 << SYSCON_USBPDS_PWRSTAT_SHIFT) /* OFF */ # define SYSCON_USBPDS_PWRSTAT_ON (3 << SYSCON_USBPDS_PWRSTAT_SHIFT) /* ON */ + #define SYSCON_USBPDS_MEMSTAT_SHIFT (2) /* Bits 2-3: Memory Array Power Status */ #define SYSCON_USBPDS_MEMSTAT_MASK (3 << SYSCON_USBPDS_PWRSTAT_SHIFT) # define SYSCON_USBPDS_MEMSTAT_OFF (0 << SYSCON_USBPDS_PWRSTAT_SHIFT) /* Array OFF */ @@ -985,6 +1025,7 @@ #define SYSCON_EMACPDS_PWRSTAT_MASK (3 << SYSCON_EMACPDS_PWRSTAT_SHIFT) # define SYSCON_EMACPDS_PWRSTAT_OFF (0 << SYSCON_EMACPDS_PWRSTAT_SHIFT) /* OFF */ # define SYSCON_EMACPDS_PWRSTAT_ON (3 << SYSCON_EMACPDS_PWRSTAT_SHIFT) /* ON */ + #define SYSCON_EMACPDS_MEMSTAT_SHIFT (2) /* Bits 2-3: Memory Array Power Status */ #define SYSCON_EMACPDS_MEMSTAT_MASK (3 << SYSCON_EMACPDS_MEMSTAT_SHIFT) # define SYSCON_EMACPDS_MEMSTAT_OFF (0 << SYSCON_EMACPDS_MEMSTAT_SHIFT) /* Array OFF */ @@ -1003,6 +1044,7 @@ #define SYSCON_LCDPDS_PWRSTAT_MASK (3 << SYSCON_LCDPDS_PWRSTAT_SHIFT) # define SYSCON_LCDPDS_PWRSTAT_OFF (0 << SYSCON_LCDPDS_PWRSTAT_SHIFT) /* OFF */ # define SYSCON_LCDPDS_PWRSTAT_ON (3 << SYSCON_LCDPDS_PWRSTAT_SHIFT) /* ON */ + #define SYSCON_LCDPDS_MEMSTAT_SHIFT (2) /* Bits 2-3: Memory Array Power Status */ #define SYSCON_LCDPDS_MEMSTAT_MASK (3 << SYSCON_LCDPDS_MEMSTAT_SHIFT) # define SYSCON_LCDPDS_MEMSTAT_OFF (0 << SYSCON_LCDPDS_MEMSTAT_SHIFT) /* Array OFF */ @@ -1021,6 +1063,7 @@ #define SYSCON_CAN0PDS_PWRSTAT_MASK (3 << SYSCON_CAN0PDS_PWRSTAT_SHIFT) # define SYSCON_CAN0PDS_PWRSTAT_OFF (0 << SYSCON_CAN0PDS_PWRSTAT_SHIFT) /* OFF */ # define SYSCON_CAN0PDS_PWRSTAT_ON (3 << SYSCON_CAN0PDS_PWRSTAT_SHIFT) /* ON */ + #define SYSCON_CAN0PDS_MEMSTAT_SHIFT (2) /* Bits 2-3: Memory Array Power Status */ #define SYSCON_CAN0PDS_MEMSTAT_MASK (3 << SYSCON_CAN0PDS_MEMSTAT_SHIFT) # define SYSCON_CAN0PDS_MEMSTAT_OFF (0 << SYSCON_CAN0PDS_MEMSTAT_SHIFT) /* Array OFF */ @@ -1039,6 +1082,7 @@ #define SYSCON_CAN1PDS_PWRSTAT_MASK (3 << SYSCON_CAN1PDS_PWRSTAT_SHIFT) # define SYSCON_CAN1PDS_PWRSTAT_OFF (0 << SYSCON_CAN1PDS_PWRSTAT_SHIFT) /* OFF */ # define SYSCON_CAN1PDS_PWRSTAT_ON (3 << SYSCON_CAN1PDS_PWRSTAT_SHIFT) /* ON */ + #define SYSCON_CAN1PDS_MEMSTAT_SHIFT (2) /* Bits 2-3: Memory Array Power Status */ #define SYSCON_CAN1PDS_MEMSTAT_MASK (3 << SYSCON_CAN1PDS_MEMSTAT_SHIFT) # define SYSCON_CAN1PDS_MEMSTAT_OFF (0 << SYSCON_CAN1PDS_MEMSTAT_SHIFT) /* Array OFF */ @@ -2139,16 +2183,16 @@ #define SYSCON_CCMCGREQ_AESCFG (1 << 1) /* Bit 1: AES Clock Gating Request */ #define SYSCON_CCMCGREQ_DESCFG (1 << 2) /* Bit 2: DES Clock Gating Request */ -/******************************************************************************************** +/**************************************************************************** * Public Types - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** +/**************************************************************************** * Public Data - ********************************************************************************************/ + ****************************************************************************/ -/******************************************************************************************** - * Public Functions - ********************************************************************************************/ +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C129_SYSCONTROL_H */ diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c129_timer.h b/arch/arm/src/tiva/hardware/tm4c/tm4c129_timer.h index 8793219651d..c858ce64e7e 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c129_timer.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c129_timer.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tm4c/tm4c129_timer.h * * Originally: @@ -44,23 +44,23 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_TM4C129_TIMER_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_TM4C129_TIMER_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "hardware/tiva_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* GPTM register offsets ************************************************************/ +/* GPTM register offsets ****************************************************/ #define TIVA_TIMER_CFG_OFFSET 0x0000 /* GPTM Configuration */ #define TIVA_TIMER_TAMR_OFFSET 0x0004 /* GPTM Timer A Mode */ @@ -93,7 +93,7 @@ #define TIVA_TIMER_PP_OFFSET 0x0fc0 /* GPTM Peripheral Properties */ #define TIVA_TIMER_CC_OFFSET 0x0fc8 /* GPTM Clock Configuration */ -/* GPTM register addresses **********************************************************/ +/* GPTM register addresses **************************************************/ #if TIVA_NTIMERS > 0 #define TIVA_TIMER0_CFG (TIVA_TIMER0_BASE + TIVA_TIMER_CFG_OFFSET) @@ -352,7 +352,8 @@ #define TIVA_TIMER7_CC (TIVA_TIMER7_BASE + TIVA_TIMER_CC_OFFSET) #endif /* TIVA_NTIMERS > 7 */ -/* GPTM register bit definitions ****************************************************/ +/* GPTM register bit definitions ********************************************/ + /* GPTM Configuration (CFG) */ #define TIMER_CFG_CFG_SHIFT 0 /* Bits 2-0: Configuration */ @@ -368,18 +369,25 @@ # define TIMER_TnMR_TnMR_ONESHOT (1 << TIMER_TnMR_TnMR_SHIFT) /* One-Shot Timer mode */ # define TIMER_TnMR_TnMR_PERIODIC (2 << TIMER_TnMR_TnMR_SHIFT) /* Periodic Timer mode */ # define TIMER_TnMR_TnMR_CAPTURE (3 << TIMER_TnMR_TnMR_SHIFT) /* Capture mode */ + #define TIMER_TnMR_TnCMR_SHIFT (2) /* Bit 2: Timer A/B Capture Mode */ + #define TIMER_TnMR_TnCMR (1 << TIMER_TnMR_TnCMR_SHIFT) /* Bit 2: Timer A/B Capture Mode */ # define TIMER_TnMR_TnCMR_EDGECOUNT (0 << TIMER_TnMR_TnCMR_SHIFT) /* Edge-Count mode */ # define TIMER_TnMR_TnCMR_EDGETIME (1 << TIMER_TnMR_TnCMR_SHIFT) /* Edge-Time mode */ + #define TIMER_TnMR_TnAMS_SHIFT (3) /* Bit 3: Timer A/B Alternate Mode Select */ + #define TIMER_TnMR_TnAMS (1 << TIMER_TnMR_TnAMS_SHIFT) /* Bit 3: Timer A/B Alternate Mode Select */ # define TIMER_TnMR_TnAMS_CAPTURE (0 << TIMER_TnMR_TnAMS_SHIFT) /* Capture mode is enabled */ # define TIMER_TnMR_TnAMS_PWM (1 << TIMER_TnMR_TnAMS_SHIFT) /* PWM mode is enabled */ + #define TIMER_TnMR_TnCDIR_SHIFT (4) /* Bit 4: Timer A/B Count Direction */ + #define TIMER_TnMR_TnCDIR (1 << TIMER_TnMR_TnCDIR_SHIFT) /* Bit 4: Timer A/B Count Direction */ # define TIMER_TnMR_TnCDIR_DOWN (0 << TIMER_TnMR_TnCDIR_SHIFT) /* Timer counts down */ # define TIMER_TnMR_TnCDIR_UP (1 << TIMER_TnMR_TnCDIR_SHIFT) /* Timer counts up (one-shot/periodic modes) */ + #define TIMER_TnMR_TnMIE (1 << 5) /* Bit 5: Timer A/B Match Interrupt Enable */ #define TIMER_TnMR_TnWOT (1 << 6) /* Bit 6: GPTM Timer A/B Wait-on-Trigger */ #define TIMER_TnMR_TnSNAPS (1 << 7) /* Bit 7: GPTM Timer A/B Snap-Shot Mode */ @@ -408,6 +416,7 @@ # define TIMER_CTL_TAEVENT_POS (0 << TIMER_CTL_TAEVENT_SHIFT) /* Positive edge */ # define TIMER_CTL_TAEVENT_NEG (1 << TIMER_CTL_TAEVENT_SHIFT) /* Negative edge */ # define TIMER_CTL_TAEVENT_BOTH (3 << TIMER_CTL_TAEVENT_SHIFT) /* Both edges */ + #define TIMER_CTL_RTCEN (1 << 4) /* Bit 4: GPTM RTC Stall Enable */ #define TIMER_CTL_TAOTE (1 << 5) /* Bit 5: GPTM Timer A Output Trigger Enable */ #define TIMER_CTL_TAPWML (1 << 6) /* Bit 6: GPTM Timer A PWM Output Level Inverted */ @@ -418,6 +427,7 @@ # define TIMER_CTL_TBEVENT_POS (0 << TIMER_CTL_TBEVENT_SHFIT) /* Positive edge */ # define TIMER_CTL_TBEVENT_NEG (1 << TIMER_CTL_TBEVENT_SHFIT) /* Negative edge */ # define TIMER_CTL_TBEVENT_BOTH (3 << TIMER_CTL_TBEVENT_SHFIT) /* Both edges */ + #define TIMER_CTL_TBOTE (1 << 13) /* Bit 13: GPTM Timer B Output Trigger Enable */ #define TIMER_CTL_TBPWML (1 << 14) /* Bit 14: GPTM Timer B PWM Output Level Inverted */ @@ -567,8 +577,11 @@ #define TIMER_ALLINTS 0x00002f3f /* GPTM Timer A Interval Load (TAILR) (32-bit value) */ + /* GPTM Timer B Interval Load (TBILR) (32-bit value) */ + /* GPTM Timer A Match (TAMATCHR) (32-bit value) */ + /* GPTM Timer B Match (TBMATCHR) (32-bit value) */ /* GPTM Timer A/B Prescale (TnPR) */ @@ -584,8 +597,11 @@ # define TIMER_TnPMR_TnPSMR(n) ((uint32_t)(n) << TIMER_TnPMR_TnPSMR_SHIFT) /* GPTM Timer A (TAR) (16/32-bit value) */ + /* GPTM Timer B (TBR) (16/32-bit value) */ + /* GPTM Timer A Value (TAV) (16/32-bit value) */ + /* GPTM Timer B Value (TBV) (16/32-bit value) */ /* GPTM RTC Predivide (RTCPD) */ @@ -636,6 +652,7 @@ #define TIMER_PP_SIZE_MASK (15 << TIMER_PP_SIZE_SHIFT) # define TIMER_PP_SIZE_16 (0 << TIMER_PP_SIZE_SHIFT) /* Timer A/B 16 bits with 8-bit prescale */ # define TIMER_PP_SIZE_32 (1 << TIMER_PP_SIZE_SHIFT) /* Timer A/B 32 bits with 16-bit prescale */ + #define TIMER_PP_CHAIN (1 << 4) /* Bit 4: Chain with Other Timers */ #define TIMER_PP_SYNCCNT (1 << 5) /* Bit 5: Synchronize Start */ #define TIMER_PP_ALTCLK (1 << 6) /* Bit 6: Alternate Clock Source */ diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c_ethernet.h b/arch/arm/src/tiva/hardware/tm4c/tm4c_ethernet.h index a7e65160214..ab3f521930c 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c_ethernet.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c_ethernet.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tm4c/tm4c_ethernet.h * * Copyright (C) 2014 Gregory Nutt. All rights reserved. @@ -36,24 +36,24 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_ETHERNET_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_ETHERNET_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Ethernet Controller Register Offsets *********************************************/ +/* Ethernet Controller Register Offsets *************************************/ /* Ethernet MAC Register Offsets */ @@ -134,7 +134,7 @@ #define TIVA_EPHY_IM_OFFSET 0x0fd4 /* Ethernet PHY Interrupt Mask */ #define TIVA_EPHY_MISC_OFFSET 0x0fd8 /* RW1C Ethernet PHY Masked Interrupt Status and Clear */ -/* Ethernet Controller Register Addresses *******************************************/ +/* Ethernet Controller Register Addresses ***********************************/ #define TIVA_EMAC_CFG (TIVA_ETHCON_BASE + TIVA_EMAC_CFG_OFFSET) #define TIVA_EMAC_FRAMEFLTR (TIVA_ETHCON_BASE + TIVA_EMAC_FRAMEFLTR_OFFSET) @@ -240,7 +240,7 @@ #define TIVA_EPHY_RCR 0x1f /* Ethernet PHY Reset Control */ #define TIVA_EPHY_LEDCFG 0x25 /* Ethernet PHY LED Configuration */ -/* Ethernet Controller Register Bit Definitions *************************************/ +/* Ethernet Controller Register Bit Definitions *****************************/ /* Ethernet MAC Configuration */ @@ -249,6 +249,7 @@ # define EMAC_CFG_PRELEN_7 (0 << EMAC_CFG_PRELEN_SHIFT) /* 7 bytes of preamble */ # define EMAC_CFG_PRELEN_5 (1 << EMAC_CFG_PRELEN_SHIFT) /* 5 bytes of preamble */ # define EMAC_CFG_PRELEN_3 (2 << EMAC_CFG_PRELEN_SHIFT) /* 3 bytes of preamble */ + #define EMAC_CFG_RE (1 << 2) /* Bit 2: Receiver Enable */ #define EMAC_CFG_TE (1 << 3) /* Bit 3: Transmitter Enable */ #define EMAC_CFG_DC (1 << 4) /* Bit 4: Deferral Check */ @@ -258,6 +259,7 @@ # define EMAC_CFG_BL_8 (1 << EMAC_CFG_BL_SHIFT) /* k = min (n,8) */ # define EMAC_CFG_BL_4 (2 << EMAC_CFG_BL_SHIFT) /* k = min (n,4) */ # define EMAC_CFG_BL_1 (3 << EMAC_CFG_BL_SHIFT) /* k = min (n,1) */ + #define EMAC_CFG_ACS (1 << 7) /* Bit 7: Automatic Pad or CRC Stripping */ #define EMAC_CFG_DR (1 << 9) /* Bit 8: Disable Retry */ #define EMAC_CFG_IPC (1 << 10) /* Bit 10: Checksum Offload */ @@ -267,9 +269,10 @@ #define EMAC_CFG_FES (1 << 14) /* Bit 14: Speed */ #define EMAC_CFG_PS (1 << 15) /* Bit 15: Port Select */ #define EMAC_CFG_DISCRS (1 << 16) /* Bit 16: Disable Carrier Sense During Transmission */ -#define EMAC_CFG_IFG_SHIFT (17) /* Bits 17-19: Inter-Frame Gap (IFG) */ +#define EMAC_CFG_IFG_SHIFT (17) /* Bits 17-19: Inter-Frame Gap (IFG) */ #define EMAC_CFG_IFG_MASK (7 << EMAC_CFG_IFG_SHIFT) # define EMAC_CFG_IFG(n) ((12-((n) >> 3)) << EMAC_CFG_IFG_SHIFT) /* n bit times, n=40,48,..96 */ + # define EMAC_CFG_IFG_96 (0 << EMAC_CFG_IFG_SHIFT) /* 96 bit times */ # define EMAC_CFG_IFG_88 (1 << EMAC_CFG_IFG_SHIFT) /* 88 bit times */ # define EMAC_CFG_IFG_80 (2 << EMAC_CFG_IFG_SHIFT) /* 80 bit times */ @@ -278,6 +281,7 @@ # define EMAC_CFG_IFG_56 (5 << EMAC_CFG_IFG_SHIFT) /* 56 bit times */ # define EMAC_CFG_IFG_48 (6 << EMAC_CFG_IFG_SHIFT) /* 48 bit times */ # define EMAC_CFG_IFG_40 (7 << EMAC_CFG_IFG_SHIFT) /* 40 bit times */ + #define EMAC_CFG_JFEN (1 << 20) /* Bit 20: Jumbo Frame Enable */ #define EMAC_CFG_JD (1 << 22) /* Bit 21: Jabber Disable */ #define EMAC_CFG_WDDIS (1 << 23) /* Bit 23: Watchdog Disable */ @@ -304,6 +308,7 @@ # define EMAC_FRAMEFLTR_PCF_PAUSE (1 << EMAC_FRAMEFLTR_PCF_SHIFT) /* Prevents all except PAUSE */ # define EMAC_FRAMEFLTR_PCF_ALL (2 << EMAC_FRAMEFLTR_PCF_SHIFT) /* Forward all control frames */ # define EMAC_FRAMEFLTR_PCF_FILTER (3 << EMAC_FRAMEFLTR_PCF_SHIFT) /* Forwards all that pass address filter */ + #define EMAC_FRAMEFLTR_SAIF (1 << 8) /* Bit 8: Source Address (SA) Inverse Filtering */ #define EMAC_FRAMEFLTR_SAF (1 << 9) /* Bit 9: Source Address Filter Enable */ #define EMAC_FRAMEFLTR_HPF (1 << 10) /* Bit 10: Hash or Perfect Filter */ @@ -311,6 +316,7 @@ #define EMAC_FRAMEFLTR_RA (1 << 31) /* Bit 31: Receive All */ /* Ethernet MAC Hash Table High (32-bit data) */ + /* Ethernet MAC Hash Table Low (32-bit data) */ /* Ethernet MAC MII Address */ @@ -324,6 +330,7 @@ # define EMAC_MIIADDR_CR_20_35 (2 << EMAC_MIIADDR_CR_SHIFT) /* System Clock=20-35 MHz; MDIO clock=SYSCLK/16 */ # define EMAC_MIIADDR_CR_35_60 (3 << EMAC_MIIADDR_CR_SHIFT) /* System Clock=35-60 MHz; MDIO clock=SYSCLK/26 */ # define EMAC_MIIADDR_CR_150_168 (4 << EMAC_MIIADDR_CR_SHIFT) /* System Clock=150-168 MHz; MDIO clock=SYSCLK/102 */ + #define EMAC_MIIADDR_MII_SHIFT (6) /* Bits 6-10: MII Register */ #define EMAC_MIIADDR_MII_MASK (31 << EMAC_MIIADDR_MII_SHIFT) # define EMAC_MIIADDR_MII(n) ((uint32_t)(n) << EMAC_MIIADDR_MII_SHIFT) @@ -348,6 +355,7 @@ # define EMAC_FLOWCTL_PLT_M28 (1 << EMAC_FLOWCTL_PLT_SHIFT) /* Pause time minus 28 slot times */ # define EMAC_FLOWCTL_PLT_M144 (2 << EMAC_FLOWCTL_PLT_SHIFT) /* Pause time minus 144 slot times */ # define EMAC_FLOWCTL_PLT_M256 (3 << EMAC_FLOWCTL_PLT_SHIFT) /* Pause time minus 256 slot times */ + #define EMAC_FLOWCTL_DZQP (1 << 7) /* Bit 7: Disable Zero-Quanta Pause */ #define EMAC_FLOWCTL_PT_SHIFT (16) /* Bits 16-31: Pause Time */ #define EMAC_FLOWCTL_PT_MASK (0xffff << EMAC_FLOWCTL_PT_SHIFT) @@ -374,12 +382,14 @@ # define EMAC_STATUS_RRC_STATUS (1 << EMAC_STATUS_RRC_SHIFT) /* Reading frame data */ # define EMAC_STATUS_RRC_DATA (2 << EMAC_STATUS_RRC_SHIFT) /* Reading frame status (or timestamp) */ # define EMAC_STATUS_RRC_FLUSH (3 << EMAC_STATUS_RRC_SHIFT) /* Flushing the frame data and status */ + #define EMAC_STATUS_RXF_SHIFT (8) /* Bits 8-9: TX/RX Controller RX FIFO Fill-level Status */ #define EMAC_STATUS_RXF_MASK (3 << EMAC_STATUS_RXF_SHIFT) # define EMAC_STATUS_RXF_EMPTY (0 << EMAC_STATUS_RXF_SHIFT) /* RX FIFO Empty */ # define EMAC_STATUS_RXF_BELOW (1 << EMAC_STATUS_RXF_SHIFT) /* Below the flow-control deactivate threshold */ # define EMAC_STATUS_RXF_ABOVE (2 << EMAC_STATUS_RXF_SHIFT) /* Above the flow-control activate threshold */ # define EMAC_STATUS_RXF_FULL (3 << EMAC_STATUS_RXF_SHIFT) /* RX FIFO Full */ + #define EMAC_STATUS_TPE (1 << 16) /* Bit 16: MAC MII Transmit Protocol Engine Status */ #define EMAC_STATUS_TFC_SHIFT (17) /* Bits 17-18: MAC Transmit Frame Controller Status */ #define EMAC_STATUS_TFC_MASK (3 << EMAC_STATUS_TFC_SHIFT) @@ -387,6 +397,7 @@ # define EMAC_STATUS_TFC_STATUS (1 << EMAC_STATUS_TFC_SHIFT) /* Waiting for status */ # define EMAC_STATUS_TFC_PAUSE (2 << EMAC_STATUS_TFC_SHIFT) /* Generating and transmitting a PAUSE control frame */ # define EMAC_STATUS_TFC_INPUT (3 << EMAC_STATUS_TFC_SHIFT) /* Transferring input frame for transmission */ + #define EMAC_STATUS_TXPAUSED (1 << 19) /* Bit 19: MAC Transmitter PAUSE */ #define EMAC_STATUS_TRC_SHIFT (20) /* Bits 20-21: TX/RX Controller's TX FIFO Read Controller Status */ #define EMAC_STATUS_TRC_MASK (3 << EMAC_STATUS_TRC_SHIFT) @@ -394,6 +405,7 @@ # define EMAC_STATUS_TRC_READ (1 << EMAC_STATUS_TRC_SHIFT) /* READ state */ # define EMAC_STATUS_TRC_WAIT (2 << EMAC_STATUS_TRC_SHIFT) /* Waiting for TX Status from MAC transmitter */ # define EMAC_STATUS_TRC_WRFLUSH (3 << EMAC_STATUS_TRC_SHIFT) /* Writing received TX Status or flushing TX FIFO */ + #define EMAC_STATUS_TWC (1 << 22) /* Bit 22: TX/RX Controller TX FIFO Write Controller Active Status */ #define EMAC_STATUS_TXFE (1 << 24) /* Bit 24: TX/RX Controller TX FIFO Not Empty Status */ #define EMAC_STATUS_TXFF (1 << 25) /* Bit 25: TX/RX Controller TX FIFO Full Status */ @@ -428,6 +440,7 @@ #define EMAC_IM_ALLINTS (EMAC_IM_PMT|EMAC_IM_TSI) /* Ethernet MAC Address 0 High */ + /* Ethernet MAC Address 0 Low Register (32-bit MAC Address0 [31:0]) */ #define EMAC_ADDR0H_ADDRHI_SHIFT (0) /* Bits 0-15: MAC Address0 [47:32] */ @@ -436,6 +449,7 @@ #define EMAC_ADDR0H_AE (1 << 31) /* Bit 31: Address Enable */ /* Ethernet MAC Address 1 High */ + /* Ethernet MAC Address 1 Low (32-bit MAC Address0 [31:0]) */ #define EMAC_ADDR1H_ADDRHI_SHIFT (0) /* Bits 0-15: MAC Address0 [47:32] */ @@ -454,6 +468,7 @@ #define EMAC_ADDR1H_AE (1 << 31) /* Bit 31: Address Enable */ /* Ethernet MAC Address 2 High */ + /* Ethernet MAC Address 2 Low (32-bit MAC Address0 [31:0]) */ #define EMAC_ADDR2H_ADDRHI_SHIFT (0) /* Bits 0-15: MAC Address0 [47:32] */ @@ -472,6 +487,7 @@ #define EMAC_ADDR2H_AE (1 << 31) /* Bit 31: Address Enable */ /* Ethernet MAC Address 3 High */ + /* Ethernet MAC Address 3 Low (32-bit MAC Address0 [31:0]) */ #define EMAC_ADDR3H_ADDRHI_SHIFT (0) /* Bits 0-15: MAC Address0 [47:32] */ @@ -489,7 +505,6 @@ #define EMAC_ADDR3H_SA (1 << 30) /* Bit 30: Source Address */ #define EMAC_ADDR3H_AE (1 << 31) /* Bit 31: Address Enable */ - /* Ethernet MAC Watchdog Timeout */ #define EMAC_WDOGTO_WTO_SHIFT (0) /* Bits 0-13: Watchdog Timeout */ @@ -536,12 +551,25 @@ #define EMAC_MMCTXIM_OCTCNT (1 << 20) /* Bit 20: MMC Transmit Good Octet Counter Interrupt Mask */ /* Ethernet MAC Transmit Frame Count for Good and Bad Frames (32-bit data) */ -/* Ethernet MAC Transmit Frame Count for Frames Transmitted after Single Collision (32-bit data) */ -/* Ethernet MAC Transmit Frame Count for Frames Transmitted after Multiple Collisions (32-bit data) */ + +/* Ethernet MAC Transmit Frame Count for Frames Transmitted after + * Single Collision (32-bit data) + */ + +/* Ethernet MAC Transmit Frame Count for Frames Transmitted after + * Multiple Collisions (32-bit data) + */ + /* Ethernet MAC Transmit Octet Count Good (32-bit data) */ + /* Ethernet MAC Receive Frame Count for Good and Bad Frames (32-bit data) */ + /* Ethernet MAC Receive Frame Count for CRC Error Frames (32-bit data) */ -/* Ethernet MAC Receive Frame Count for Alignment Error Frames (32-bit data) */ + +/* Ethernet MAC Receive Frame Count for Alignment Error Frames + * (32-bit data) + */ + /* Ethernet MAC Receive Frame Count for Good Unicast Frames (32-bit data) */ /* Ethernet MAC VLAN Tag Inclusion or Replacement */ @@ -555,6 +583,7 @@ # define EMAC_VLNINCREP_VLC_TAGDEL (1 << EMAC_VLNINCREP_VLC_SHIFT) /* VLAN tag deletion */ # define EMAC_VLNINCREP_VLC_TAGINS (2 << EMAC_VLNINCREP_VLC_SHIFT) /* VLAN tag insertion */ # define EMAC_VLNINCREP_VLC_TAGREP (3 << EMAC_VLNINCREP_VLC_SHIFT) /* VLAN tag replacement */ + #define EMAC_VLNINCREP_VLP (1 << 18) /* Bit 18: VLAN Priority Control */ #define EMAC_VLNINCREP_CSVL (1 << 19) /* Bit 19: C-VLAN or S-VLAN */ @@ -590,12 +619,14 @@ #define EMAC_SUBSECINC_SSINC_MASK (0xff << EMAC_SUBSECINC_SSINC_SHIFT) /* Ethernet MAC System Time - Seconds (32-bit value) */ + /* Ethernet MAC System Time - Nanoseconds */ #define EMAC_TIMNANO_TSSS_SHIFT (0) /* Bits 0-30: Timestamp Sub-Seconds */ #define EMAC_TIMNANO_TSSS_MASK (0x7fffffff << EMAC_TIMNANO_TSSS_SHIFT) /* Ethernet MAC System Time - Seconds Update (32-bit value) */ + /* Ethernet MAC System Time - Nanoseconds Update */ #define EMAC_TIMNANOU_TSSS_SHIFT (0) /* Bits 0-30: Timestamp Sub-Second */ @@ -603,7 +634,9 @@ #define EMAC_TIMNANOU_ADDSUB (1 << 31) /* Bit 31: Add or subtract time */ /* Ethernet MAC Timestamp Addend (32-bit value) */ + /* Ethernet MAC Target Time Seconds (32-bit value) */ + /* Ethernet MAC Target Time Nanoseconds */ #define EMAC_TARGNANO_TTSLO_SHIFT (0) /* Bits 0-30: Target Timestamp Low Register */ @@ -640,6 +673,7 @@ # define EMAC_PPSCTRL_PPSCTRL_8192HZ (13 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* Binary rollover=8.192 kHz; digital rollover=4.096 kHz */ # define EMAC_PPSCTRL_PPSCTRL_16384HZ (14 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* Binary rollover=16.384 kHz; digital rollover=8.092 kHz */ # define EMAC_PPSCTRL_PPSCTRL_32768HZ (15 << EMAC_PPSCTRL_PPSCTRL_SHIFT) /* Binary rollover=32.768 KHz; digital rollover=16.384 KHz */ + #define EMAC_PPSCTRL_PPSEN0 (1 << 4) /* Bit 4: Flexible PPS Output Mode Enable */ #define EMAC_PPSCTRL_TRGMODS0_SHIFT (5) /* Bits 5-6: Target Time Register Mode for PPS0 Output */ #define EMAC_PPSCTRL_TRGMODS0_MASK (3 << EMAC_PPSCTRL_TRGMODS0_SHIFT) @@ -648,6 +682,7 @@ # define EMAC_PPSCTRL_TRGMODS0_PPS0ONLY (3 << EMAC_PPSCTRL_TRGMODS0_SHIFT) /* Control ENOPPS output */ /* Ethernet MAC PPS0 Interval (32-bit value) */ + /* Ethernet MAC PPS0 Width (32-bit value) */ /* Ethernet MAC DMA Bus Mode */ @@ -667,6 +702,7 @@ # define EMAC_DMABUSMOD_PR_2TO1 (1 << EMAC_DMABUSMOD_PR_SHIFT) /* Priority Ratio is 2:1 */ # define EMAC_DMABUSMOD_PR_3TO1 (2 << EMAC_DMABUSMOD_PR_SHIFT) /* Priority Ratio is 3:1 */ # define EMAC_DMABUSMOD_PR_4TO1 (3 << EMAC_DMABUSMOD_PR_SHIFT) /* Priority Ratio is 4:1 */ + #define EMAC_DMABUSMOD_FB (1 << 16) /* Bit 16: Fixed Burst */ #define EMAC_DMABUSMOD_RPBL_SHIFT (17) /* Bits 17:22: RX DMA Programmable Burst Length (PBL) */ #define EMAC_DMABUSMOD_RPBL_MASK (0x3f << EMAC_DMABUSMOD_RPBL_SHIFT) @@ -679,6 +715,7 @@ #define EMAC_DMABUSMOD_RIB (1 << 31) /* Bit 31: Rebuild Burst */ /* Ethernet MAC Transmit Poll Demand (32-bit value) */ + /* Ethernet MAC Receive Poll Demand (32-bit value) */ /* Ethernet MAC Receive Descriptor List Address */ @@ -689,7 +726,10 @@ #define EMAC_TXDLADDR_MASK (0xfffffffc) -/* Ethernet MAC DMA Interrupt Status and Ethernet MAC DMA Interrupt Mask Register (common bit definitions) */ +/* Ethernet MAC DMA Interrupt Status and + * Ethernet MAC DMA Interrupt Mask Register + * (common bit definitions) + */ #define EMAC_DMAINT_TI (1 << 0) /* Bit 0: Transmit interrupt */ #define EMAC_DMAINT_TPSI (1 << 1) /* Bit 1: Transmit process stopped interrupt */ @@ -718,6 +758,7 @@ # define EMAC_DMARIS_RS_RUNCRD (5 << EMAC_DMARIS_RS_SHIFT) /* Running: Closing receive descriptor */ # define EMAC_DMARIS_RS_TSWS (6 << EMAC_DMARIS_RS_SHIFT) /* Writing Timestamp */ # define EMAC_DMARIS_RS_RUNTXD (7 << EMAC_DMARIS_RS_SHIFT) /* Running: Transferring receive packet data from buffer */ + #define EMAC_DMARIS_TS_SHIFT (20) /* Bits 20-22: Transmit Process State */ #define EMAC_DMARIS_TS_MASK (7 << EMAC_DMARIS_TS_SHIFT) # define EMAC_DMARIS_TS_STOP (0 << EMAC_DMARIS_TS_SHIFT) /* Stopped; Reset or Stop transmit command processed */ @@ -726,7 +767,8 @@ # define EMAC_DMARIS_TS_RUNTX (3 << EMAC_DMARIS_TS_SHIFT) /* Running; Reading data from host buffer and queuing to TX FIFO */ # define EMAC_DMARIS_TS_TSTAMP (4 << EMAC_DMARIS_TS_SHIFT) /* Writing Timestamp */ # define EMAC_DMARIS_TS_SUSPEND (6 << EMAC_DMARIS_TS_SHIFT) /* Suspended; Transmit descriptor unavailable or transmit underflow */ -# define EMAC_DMARIS_TS_RUNCTD (7 << EMAC_DMARIS_TS_SHIFT) /* Running; Closing transmit descriptor */ +# define EMAC_DMARIS_TS_RUNCTD (7 << EMAC_DMARIS_TS_SHIFT) /* Running; Closing transmit descriptor */ + #define EMAC_DMARIS_AE_SHIFT (23) /* Bits 23-25: Access Error */ #define EMAC_DMARIS_AE_MASK (7 << EMAC_DMARIS_AE_SHIFT) # define EMAC_DMARIS_AE_RXDMAWD (0 << EMAC_DMARIS_AE_SHIFT) /* Error during RX DMA Write Data Transfer */ @@ -735,6 +777,7 @@ # define EMAC_DMARIS_AE_TXDMADW (5 << EMAC_DMARIS_AE_SHIFT) /* Error during TX DMA Descriptor Write Access */ # define EMAC_DMARIS_AE_RXDMADR (6 << EMAC_DMARIS_AE_SHIFT) /* Error during RX DMA Descriptor Read Access */ # define EMAC_DMARIS_AE_TXDMADR (7 << EMAC_DMARIS_AE_SHIFT) /* Error during TX DMA Descriptor Read Access */ + #define EMAC_DMARIS_MMC (1 << 27) /* Bit 27: MAC MMC Interrupt */ #define EMAC_DMARIS_PMT (1 << 28) /* Bit 28: MAC PMT Interrupt Status */ #define EMAC_DMARIS_TT (1 << 29) /* Bit 29: Timestamp Trigger Interrupt Status */ @@ -749,6 +792,7 @@ # define EMAC_DMAOPMODE_RTC_32 (1 << EMAC_DMAOPMODE_RTC_SHIFT) /* 32 bytes */ # define EMAC_DMAOPMODE_RTC_96 (2 << EMAC_DMAOPMODE_RTC_SHIFT) /* 96 bytes */ # define EMAC_DMAOPMODE_RTC_128 (3 << EMAC_DMAOPMODE_RTC_SHIFT) /* 128 bytes */ + #define EMAC_DMAOPMODE_DGF (1 << 5) /* Bit 5: Drop Giant Frame Enable */ #define EMAC_DMAOPMODE_FUF (1 << 6) /* Bit 6: Forward Undersized Good Frames */ #define EMAC_DMAOPMODE_FEF (1 << 7) /* Bit 7: Forward Error Frames */ @@ -763,6 +807,7 @@ # define EMAC_DMAOPMODE_TTC_32 (5 << EMAC_DMAOPMODE_TTC_SHIFT) /* 32 bytes */ # define EMAC_DMAOPMODE_TTC_24 (6 << EMAC_DMAOPMODE_TTC_SHIFT) /* 24 bytes */ # define EMAC_DMAOPMODE_TTC_16 (7 << EMAC_DMAOPMODE_TTC_SHIFT) /* 16 bytes */ + #define EMAC_DMAOPMODE_FTF (1 << 20) /* Bit 20: Flush Transmit FIFO */ #define EMAC_DMAOPMODE_TSF (1 << 21) /* Bit 21: Transmit Store and Forward */ #define EMAC_DMAOPMODE_DFF (1 << 24) /* Bit 24: Disable Flushing of Received Frames */ @@ -784,8 +829,11 @@ #define EMAC_RXINTWDT_RIWT_MASK (0xff << EMAC_RXINTWDT_RIWT_SHIFT) /* Ethernet MAC Current Host Transmit Descriptor (32-bit value) */ + /* Ethernet MAC Current Host Receive Descriptor (32-bit value) */ + /* Ethernet MAC Current Host Transmit Buffer Address (32-bit value) */ + /* Ethernet MAC Current Host Receive Buffer Address (32-bit value) */ /* Ethernet MAC Peripheral Property Register */ @@ -796,6 +844,7 @@ # define EMAC_PP_PHYTYPE_FURY (1 << EMAC_PP_PHYTYPE_SHIFT) /* Fury class PHY */ # define EMAC_PP_PHYTYPE_TPFS (2 << EMAC_PP_PHYTYPE_SHIFT) /* Tempest/Firestorm class PHY */ # define EMAC_PP_PHYTYPE_SNOWFLAKE (3 << EMAC_PP_PHYTYPE_SHIFT) /* Snowflake class PHY */ + #define EMAC_PP_MACTYPE_SHIFT (8) /* Bits 8-11: Ethernet MAC Type */ #define EMAC_PP_MACTYPE_MASK (7 << EMAC_PP_MACTYPE_SHIFT) # define EMAC_PP_MACTYPE_LM3S (0 << EMAC_PP_MACTYPE_SHIFT) /* Stellaris® LM3S-class MAC */ @@ -810,6 +859,7 @@ # define EMAC_PC_ANMODE_10FD (1 << EMAC_PC_ANMODE_SHIFT) /* When ANEN = 0x0, mode is 10Base-T, Full-Duplex */ # define EMAC_PC_ANMODE_100HD (2 << EMAC_PC_ANMODE_SHIFT) /* When ANEN = 0x0, mode is 100Base-TX, Half-Duplex */ # define EMAC_PC_ANMODE_100FD (3 << EMAC_PC_ANMODE_SHIFT) /* When ANEN = 0x0, mode is 100Base-TX, Full-Duplex */ + #define EMAC_PC_ANEN (1 << 3) /* Bit 3: Auto Negotiation Enable */ #define EMAC_PC_FASTANSEL_SHIFT (4) /* Bits 4-5: Fast Auto Negotiation Select */ #define EMAC_PC_FASTANSEL_MASK (3 << EMAC_PC_FASTANSEL_SHIFT) @@ -836,6 +886,7 @@ #define EMAC_PC_PINTFS_MASK (7 << EMAC_PC_PINTFS_SHIFT) # define EMAC_PC_PINTFS_MII (0 << EMAC_PC_PINTFS_SHIFT) /* MII: Internal PHY or external PHY connected via MII */ # define EMAC_PC_PINTFS_RMII (4 << EMAC_PC_PINTFS_SHIFT) /* RMII: External PHY connected via RMII */ + #define EMAC_PC_PHYEXT (1 << 31) /* Bit 31: PHY Select */ /* Ethernet MAC Clock Configuration Register */ @@ -884,7 +935,10 @@ #define EPHY_BMSR_100BTXHD (1 << 13) /* Bit 13: 100Base-TX Half Duplex Capable */ #define EPHY_BMSR_100BTXFD (1 << 14) /* Bit 14: 100Base-TX Full Duplex Capable */ -/* Ethernet PHY Identifier Register 1 (Most significant 16 bits of the OUI) */ +/* Ethernet PHY Identifier Register 1 + * (Most significant 16 bits of the OUI) + */ + /* Ethernet PHY Identifier Register 2 */ #define EPHY_ID2_MDLREV_SHIFT (0) /* Bits 0-3: Model Revision Number */ @@ -963,6 +1017,7 @@ # define EPHY_CFG1_FANSEL_BLT80 (0 << EPHY_CFG1_FANSEL_SHIFT) /* Break Link Timer: 80 ms */ # define EPHY_CFG1_FANSEL_BLT120 (1 << EPHY_CFG1_FANSEL_SHIFT) /* Break Link Timer: 120 ms */ # define EPHY_CFG1_FANSEL_BLT240 (2 << EPHY_CFG1_FANSEL_SHIFT) /* Break Link Timer: 240 ms */ + #define EPHY_CFG1_FASTANEN (1 << 4) /* Bit 4: Fast Auto Negotiation Enable */ #define EPHY_CFG1_RAMDIX (1 << 5) /* Bit 5: Robust Auto MDI/MDIX */ #define EPHY_CFG1_FAMDIX (1 << 6) /* Bit 6: Fast Auto MDI/MDIX */ @@ -1030,6 +1085,7 @@ # define EPHY_SCR_LBFIFO_5 (1 << EPHY_SCR_LBFIFO_SHIFT) /* Five nibble FIFO */ # define EPHY_SCR_LBFIFO_6 (2 << EPHY_SCR_LBFIFO_SHIFT) /* Six nibble FIFO */ # define EPHY_SCR_LBFIFO_8 (3 << EPHY_SCR_LBFIFO_SHIFT) /* Eight nibble FIFO */ + #define EPHY_SCR_SBPYASS (1 << 11) /* Bit 11: Scrambler Bypass */ #define EPHY_SCR_PSMODE_SHIFT (12) /* Bits 12-13: Power Saving Modes */ #define EPHY_SCR_PSMODE_MASK (3 << EPHY_SCR_PSMODE_SHIFT) @@ -1037,6 +1093,7 @@ # define EPHY_SCR_PSMODE_LOWPWR (1 << EPHY_SCR_PSMODE_SHIFT) /* IEEE Power Down */ # define EPHY_SCR_PSMODE_ACTWOL (2 << EPHY_SCR_PSMODE_SHIFT) /* Active Sleep */ # define EPHY_SCR_PSMODE_PASWOL (3 << EPHY_SCR_PSMODE_SHIFT) /* Passive Sleep */ + #define EPHY_SCR_PSEN (1 << 14) /* Bit 14: Power Saving Modes Enable */ #define EPHY_SCR_DISCLK (1 << 15) /* Bit 15: Disable CLK */ @@ -1148,6 +1205,7 @@ # define EPHY_CDCR_LINKQUAL_GOOD (1 << EPHY_CDCR_LINKQUAL_SHIFT) /* Good Quality Link Indication */ # define EPHY_CDCR_LINKQUAL_MILD (2 << EPHY_CDCR_LINKQUAL_SHIFT) /* Mid- Quality Link Indication */ # define EPHY_CDCR_LINKQUAL_POOR (3 << EPHY_CDCR_LINKQUAL_SHIFT) /* Poor Quality Link Indication */ + #define EPHY_CDCR_START (1 << 15) /* Bit 15: Cable Diagnostic Process Start */ /* Ethernet PHY Reset Control */ @@ -1168,6 +1226,7 @@ # define EPHY_LEDCFG_LED0_10BT (6 << EPHY_LEDCFG_LED0_SHIFT) /* 10-Base TX */ # define EPHY_LEDCFG_LED0_FD (7 << EPHY_LEDCFG_LED0_SHIFT) /* Full Duplex */ # define EPHY_LEDCFG_LED0_LINKTXRX (8 << EPHY_LEDCFG_LED0_SHIFT) /* Link OK/Blink on TX/RX Activity */ + #define EPHY_LEDCFG_LED1_SHIFT (4) /* Bits 4-7: LED1 Configuration */ #define EPHY_LEDCFG_LED1_MASK (15 << EPHY_LEDCFG_LED1_SHIFT) # define EPHY_LEDCFG_LED1_LINK (0 << EPHY_LEDCFG_LED1_SHIFT) /* Link OK */ @@ -1179,6 +1238,7 @@ # define EPHY_LEDCFG_LED1_10BT (6 << EPHY_LEDCFG_LED1_SHIFT) /* 10-Base TX */ # define EPHY_LEDCFG_LED1_FD (7 << EPHY_LEDCFG_LED1_SHIFT) /* Full Duplex */ # define EPHY_LEDCFG_LED1_LINKTXRX (8 << EPHY_LEDCFG_LED1_SHIFT) /* Link OK/Blink on TX/RX Activity */ + #define EPHY_LEDCFG_LED2_SHIFT (8) /* Bits 8-11: LED2 Configuration */ #define EPHY_LEDCFG_LED2_MASK (15 << EPHY_LEDCFG_LED2_SHIFT) # define EPHY_LEDCFG_LED2_LINK (0 << EPHY_LEDCFG_LED2_SHIFT) /* Link OK */ @@ -1191,7 +1251,8 @@ # define EPHY_LEDCFG_LED2_FD (7 << EPHY_LEDCFG_LED2_SHIFT) /* Full Duplex */ # define EPHY_LEDCFG_LED2_LINKTXRX (8 << EPHY_LEDCFG_LED2_SHIFT) /* Link OK/Blink on TX/RX Activity */ -/* DMA Descriptors **********************************************************************************/ +/* DMA Descriptors **********************************************************/ + /* TDES0: Transmit descriptor Word0 */ #define EMAC_TDES0_DB (1 << 0) /* Bit 0: Deferred bit */ @@ -1216,6 +1277,7 @@ # define EMAC_TDES0_VLIC_REMOVE (1 << EMAC_TDES0_VLIC_SHIFT) /* Remove the VLAN tag before sending */ # define EMAC_TDES0_VLIC_INSERT (2 << EMAC_TDES0_VLIC_SHIFT) /* Insert a VLAN tag (EMACVLNINCREP) */ # define EMAC_TDES0_VLIC_REPLACE (3 << EMAC_TDES0_VLIC_SHIFT) /* Replace the VLAN tag i(EMACVLNINCREP) */ + #define EMAC_TDES0_TCH (1 << 20) /* Bit 20: Second address chained */ #define EMAC_TDES0_TER (1 << 21) /* Bit 21: Transmit end of ring */ #define EMAC_TDES0_CIC_SHIFT (22) /* Bits 22-23: Checksum insertion control */ @@ -1224,6 +1286,7 @@ # define EMAC_TDES0_CIC_IH (1 << EMAC_TDES0_CIC_SHIFT) /* Insert IPv4 header checksum */ # define EMAC_TDES0_CIC_IHPL (2 << EMAC_TDES0_CIC_SHIFT) /* Insert TCP/UDP/ICMP checksum */ # define EMAC_TDES0_CIC_ALL (3 << EMAC_TDES0_CIC_SHIFT) /* TCP/UDP/ICMP checksum fully calculated */ + #define EMAC_TDES0_CRCR (1 << 24) /* Bit 24: CRC Replacement Control */ #define EMAC_TDES0_TTSE (1 << 25) /* Bit 25: Transmit time stamp enable */ #define EMAC_TDES0_DP (1 << 26) /* Bit 26: Disable pad */ @@ -1248,8 +1311,11 @@ # define EMAC_TDES1_CTRL_REPLACE (2 << EMAC_TDES1_CTRL_SHIFT) /* Replace the source address */ /* TDES2: Transmit descriptor Word2 (32-bit address) */ + /* TDES3: Transmit descriptor Word3 (32-bit address) */ + /* TDES6: Transmit descriptor Word6 (32-bit time stamp) */ + /* TDES7: Transmit descriptor Word7 (32-bit time stamp) */ /* RDES0: Receive descriptor Word0 */ @@ -1288,6 +1354,7 @@ #define EMAC_RDES1_DIC (1 << 31) /* Bit 31: Disable interrupt on completion */ /* RDES2: Receive descriptor Word2 (32-bit address) */ + /* RDES3: Receive descriptor Word3 (32-bit address) */ /* RDES4: Receive descriptor Word4 */ @@ -1298,6 +1365,7 @@ # define EMAC_RDES4_IPPT_UDP (1 << EMAC_RDES4_IPPT_SHIFT) /* UDP payload in IP datagram */ # define EMAC_RDES4_IPPT_TCP (2 << EMAC_RDES4_IPPT_SHIFT) /* TCP payload in IP datagram */ # define EMAC_RDES4_IPPT_ICMP (3 << EMAC_RDES4_IPPT_SHIFT) /* ICMP payload in IP datagram */ + #define EMAC_RDES4_IPHE (1 << 3) /* Bit 3: IP header error */ #define EMAC_RDES4_IPPE (1 << 4) /* Bit 4: IP payload error */ #define EMAC_RDES4_IPCB (1 << 5) /* Bit 5: IP checksum bypassed */ @@ -1324,17 +1392,20 @@ # define EMAC_RDES4_PMT_MANAGEMENT (9 << EMAC_RDES4_PMT_SHIFT) /* Management */ # define EMAC_RDES4_PMT_SIGNALING (10 << EMAC_RDES4_PMT_SHIFT) /* Signaling */ # define EMAC_RDES4_PMT_PTP (15 << EMAC_RDES4_PMT_SHIFT) /* PTP packet w/ Reserved message type */ + #define EMAC_RDES4_PFT (1 << 12) /* Bit 12: PTP frame type */ #define EMAC_RDES4_PV (1 << 13) /* Bit 13: PTP version */ #define EMAC_RDES4_TSD (1 << 14) /* Bit 14: Time stampe dropped */ /* RDES5: Receive descriptor Word5 - Reserved */ + /* RDES6: Receive descriptor Word6 (32-bit time stamp) */ + /* RDES7: Receive descriptor Word7 (32-bit time stamp) */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ @@ -1378,13 +1449,13 @@ struct emac_rxdesc_s #endif }; -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_ETHERNET_H */ diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c_flash.h b/arch/arm/src/tiva/hardware/tm4c/tm4c_flash.h index f1538297535..ead5615d208 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c_flash.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c_flash.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tm4c/tm4c_flash.h * * Copyright (C) 2015 Gregory Nutt. All rights reserved. @@ -36,30 +36,31 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_FLASH_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_FLASH_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* FLASH dimensions ****************************************************************/ + ****************************************************************************/ + +/* FLASH dimensions *********************************************************/ #if defined(CONFIG_ARCH_CHIP_TM4C129XNCZAD) || defined(CONFIG_ARCH_CHIP_TM4C1294NCPDT) || \ defined(CONFIG_ARCH_CHIP_TM4C129ENCPDT) -/* For the TM4C129X family, the Flash memory is configured in groups of four banks - * four banks of 16K x 128 bits (4 * 256 KB total) which are two-way interleaved. - * Because the memory is two-way interleaved and each bank individually is an 8-KB - * sector, when the user erases a sector, using the ERASE bits in the Flash Memory - * Control (FMC) register, it is a 16 KB erase. +/* For the TM4C129X family, the Flash memory is configured in groups of four + * banks of 16K x 128 bits (4 * 256 KB total) which are two-way interleaved. + * Because the memory is two-way interleaved and each bank individually is an + * 8-KB sector, when the user erases a sector, using the ERASE bits in the + * Flash Memory Control (FMC) register, it is a 16 KB erase. */ # define TIVA_FLASH_NPAGES 64 @@ -69,7 +70,7 @@ #define TIVA_FLASH_SIZE (TIVA_FLASH_NPAGES * TIVA_FLASH_PAGESIZE) -/* Flash register offsets ************************************************************/ +/* Flash register offsets ***************************************************/ /* Internal Memory Registers (Relative to Internal Memory Control Offset) */ @@ -133,7 +134,8 @@ #define TIVA_FLASH_FMPPE14_OFFSET 0x0438 /* Flash Memory Protection Program Enable 14 */ #define TIVA_FLASH_FMPPE15_OFFSET 0x043c /* Flash Memory Protection Program Enable 15 */ -/* Flash register addresses **********************************************************/ +/* Flash register addresses *************************************************/ + /* Internal Memory Registers (Internal Memory Control Offset) */ #define TIVA_FLASH_FMA (TIVA_FLASHCON_BASE + TIVA_FLASH_FMA_OFFSET) @@ -196,7 +198,7 @@ #define TIVA_FLASH_FMPPE14 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE14_OFFSET) #define TIVA_FLASH_FMPPE15 (TIVA_SYSCON_BASE + TIVA_FLASH_FMPPE15_OFFSET) -/* Flash register bit definitions ****************************************************/ +/* Flash register bit definitions *******************************************/ /* Internal Memory Registers (Relative to Internal Memory Control Offset) */ @@ -269,6 +271,7 @@ #define FLASH_PP_SIZE_MASK (0xffff << FLASH_PP_SIZE_SHIFT) # define FLASH_PP_SIZE_512KB (255 << FLASH_PP_SIZE_SHIFT)/* 512 KB of Flash */ # define FLASH_PP_SIZE_1MB (511 << FLASH_PP_SIZE_SHIFT)/* 1024 KB of Flash */ + #define FLASH_PP_MAINSS_SHIFT (16) /* Bit1 16-18: Flash Sector Size of the physical bank */ #define FLASH_PP_MAINSS_MASK (7 << FLASH_PP_MAINSS_SHIFT) # define FLASH_PP_MAINSS_1KB (0 << FLASH_PP_MAINSS_SHIFT) /* 1 KB */ @@ -276,12 +279,14 @@ # define FLASH_PP_MAINSS_4KB (2 << FLASH_PP_MAINSS_SHIFT) /* 4 KB */ # define FLASH_PP_MAINSS_8KB (3 << FLASH_PP_MAINSS_SHIFT) /* 8 KB */ # define FLASH_PP_MAINSS_16KB (4 << FLASH_PP_MAINSS_SHIFT) /* 16 KB */ + #define FLASH_PP_EESS_SHIFT (19) /* Bits 19-22: EEPROM Sector Size of the physical bank */ #define FLASH_PP_EESS_MASK (15 << FLASH_PP_EESS_SHIFT) # define FLASH_PP_EESS_1KB (0 << FLASH_PP_EESS_SHIFT) /* 1 KB */ # define FLASH_PP_EESS_2KB (1 << FLASH_PP_EESS_SHIFT) /* 2 KB */ # define FLASH_PP_EESS_4KB (2 << FLASH_PP_EESS_SHIFT) /* 4 KB */ # define FLASH_PP_EESS_8KB (3 << FLASH_PP_EESS_SHIFT) /* 8 KB */ + #define FLASH_PP_DFA (1 << 28) /* Bit 28: DMA Flash Access */ #define FLASH_PP_FMM (1 << 29) /* Bit 29: Flash Mirror Mode */ #define FLASH_PP_PFC (1 << 30) /* Bit 30: Prefetch Buffer Mode */ @@ -319,30 +324,37 @@ # define FLASH_ROMSWMAP_SW0EN_NOTVIS (0 << FLASH_ROMSWMAP_SW0EN_SHIFT) /* Software region not available to the core */ # define FLASH_ROMSWMAP_SAFERTOS (1 << FLASH_ROMSWMAP_SW0EN_SHIFT) /* SafeRTOS Present */ # define FLASH_ROMSWMAP_SW0EN_CORE (1 << FLASH_ROMSWMAP_SW0EN_SHIFT) /* Region available to core */ + #define FLASH_ROMSWMAP_SW1EN_SHIFT (2) /* Bits 2-3: ROM SW Region 1 Availability */ #define FLASH_ROMSWMAP_SW1EN_MASK (3 << FLASH_ROMSWMAP_SW1EN_SHIFT) # define FLASH_ROMSWMAP_SW1EN_NOTVIS (0 << FLASH_ROMSWMAP_SW1EN_SHIFT) /* Software region not available to the core */ # define FLASH_ROMSWMAP_SW1EN_CORE (1 << FLASH_ROMSWMAP_SW1EN_SHIFT) /* Region available to core */ + #define FLASH_ROMSWMAP_SW2EN_SHIFT (4) /* Bits 4-5: ROM SW Region 2 Availability */ #define FLASH_ROMSWMAP_SW2EN_MASK (3 << FLASH_ROMSWMAP_SW2EN_SHIFT) # define FLASH_ROMSWMAP_SW2EN_NOTVIS (0 << FLASH_ROMSWMAP_SW2EN_SHIFT) /* Software region not available to the core */ # define FLASH_ROMSWMAP_SW2EN_CORE (1 << FLASH_ROMSWMAP_SW2EN_SHIFT) /* Region available to core */ + #define FLASH_ROMSWMAP_SW3EN_SHIFT (6) /* Bits 6-7: ROM SW Region 3 Availability */ #define FLASH_ROMSWMAP_SW3EN_MASK (3 << FLASH_ROMSWMAP_SW3EN_SHIFT) # define FLASH_ROMSWMAP_SW3EN_NOTVIS (0 << FLASH_ROMSWMAP_SW3EN_SHIFT) /* Software region not available to the core */ # define FLASH_ROMSWMAP_SW3EN_CORE (1 << FLASH_ROMSWMAP_SW3EN_SHIFT) /* Region available to core */ + #define FLASH_ROMSWMAP_SW4EN_SHIFT (8) /* Bits 8-9: ROM SW Region 4 Availability */ #define FLASH_ROMSWMAP_SW4EN_MASK (3 << FLASH_ROMSWMAP_SW4EN_SHIFT) # define FLASH_ROMSWMAP_SW4EN_NOTVIS (0 << FLASH_ROMSWMAP_SW4EN_SHIFT) /* Software region not available to the core */ # define FLASH_ROMSWMAP_SW4EN_CORE (1 << FLASH_ROMSWMAP_SW4EN_SHIFT) /* Region available to core */ + #define FLASH_ROMSWMAP_SW5EN_SHIFT (10) /* Bits 10-11: ROM SW Region 5 Availability */ #define FLASH_ROMSWMAP_SW5EN_MASK (3 << FLASH_ROMSWMAP_SW5EN_SHIFT) # define FLASH_ROMSWMAP_SW5EN_NOTVIS (0 << FLASH_ROMSWMAP_SW5EN_SHIFT) /* Software region not available to the core */ -# define FLASH_ROMSWMAP_SW5EN_CORE (1 << FLASH_ROMSWMAP_SW5EN_SHIFT) /* Region available to core */ +# define FLASH_ROMSWMAP_SW5EN_CORE (1 << FLASH_ROMSWMAP_SW5EN_SHIFT) /* Region available to core */ + #define FLASH_ROMSWMAP_SW6EN_SHIFT (12) /* Bits 12-13: ROM SW Region 6 Availability */ #define FLASH_ROMSWMAP_SW6EN_MASK (3 << FLASH_ROMSWMAP_SW6EN_SHIFT) # define FLASH_ROMSWMAP_SW6EN_NOTVIS (0 << FLASH_ROMSWMAP_SW6EN_SHIFT) /* Software region not available to the core */ # define FLASH_ROMSWMAP_SW6EN_CORE (1 << FLASH_ROMSWMAP_SW6EN_SHIFT) /* Region available to core */ + #define FLASH_ROMSWMAP_SW7EN_SHIFT (14) /* Bits 14-15: ROM SW Region 7 Availability */ #define FLASH_ROMSWMAP_SW7EN_MASK (3 << FLASH_ROMSWMAP_SW7EN_SHIFT) # define FLASH_ROMSWMAP_SW7EN_NOTVIS (0 << FLASH_ROMSWMAP_SW7EN_SHIFT) /* Software region not available to the core */ @@ -383,6 +395,7 @@ # define FLASH_BOOTCFG_PIN_5 (5 << FLASH_BOOTCFG_PIN_SHIFT) /* Pin 5 */ # define FLASH_BOOTCFG_PIN_6 (6 << FLASH_BOOTCFG_PIN_SHIFT) /* Pin 6 */ # define FLASH_BOOTCFG_PIN_7 (7 << FLASH_BOOTCFG_PIN_SHIFT) /* Pin 7 */ + #define FLASH_BOOTCFG_PORT_SHIFT (13) /* Bits 13-15: Boot GPIO Port */ #define FLASH_BOOTCFG_PORT_MASK (7 << FLASH_BOOTCFG_PORT_SHIFT) # define FLASH_BOOTCFG_PORT_A (0 << FLASH_BOOTCFG_PORT_SHIFT) /* Port A */ @@ -393,10 +406,13 @@ # define FLASH_BOOTCFG_PORT_F (5 << FLASH_BOOTCFG_PORT_SHIFT) /* Port F */ # define FLASH_BOOTCFG_PORT_G (6 << FLASH_BOOTCFG_PORT_SHIFT) /* Port G */ # define FLASH_BOOTCFG_PORT_H (7 << FLASH_BOOTCFG_PORT_SHIFT) /* Port H */ + #define FLASH_BOOTCFG_NW (1 << 31) /* Bit 31: Not Written */ /* User Register 0-3 (32-bit value) */ + /* Flash Memory Protection Read Enable 0-15 (32-bit, bit-encoded) */ + /* Flash Memory Protection Program Enable 0-15 (32-bit, bit-encoded) */ #endif // __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_FLASH_H diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c_memorymap.h b/arch/arm/src/tiva/hardware/tm4c/tm4c_memorymap.h index 15c8253d10c..2ca2119dde8 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c_memorymap.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tm4c/tm4c_memorymap.h * * Copyright (C) 2014 Gregory Nutt. All rights reserved. @@ -31,22 +31,22 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_MEMORYMAP_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Memory map ***********************************************************************/ +/* Memory map ***************************************************************/ #if defined (CONFIG_ARCH_CHIP_TM4C123AH6PM) || defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \ defined(CONFIG_ARCH_CHIP_TM4C123GH6PM) || defined(CONFIG_ARCH_CHIP_TM4C123GH6PZ) || \ @@ -101,7 +101,7 @@ # error "Memory map not specified for this TM4C chip" #endif -/* Peripheral base addresses ********************************************************/ +/* Peripheral base addresses ************************************************/ #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) @@ -615,7 +615,10 @@ /* Peripheral region 2 */ - /* -0x2ffff: Reserved */ +/* -0x2ffff: + * Reserved + */ + # define TIVA_CCM_BASE (TIVA_PERIPH2_BASE + 0x30000) /* -0x30fff: CRC/Cryptographic Control */ /* -0x33fff: Reserved */ # define TIVA_SHAMD5_BASE (TIVA_PERIPH2_BASE + 0x34000) /* -0x35fff: SHA/MD5 */ @@ -722,7 +725,9 @@ /* Peripheral region 2 */ - /* -0x2ffff: Reserved */ +/* -0x2ffff: + * Reserved + */ # define TIVA_CCM_BASE (TIVA_PERIPH2_BASE + 0x30000) /* -0x30fff: CRC/Cryptographic Control */ /* -0x53fff: Reserved */ # define TIVA_EPHY_BASE (TIVA_PERIPH2_BASE + 0x54000) /* -0x54fff: EPHY 0 */ @@ -823,7 +828,10 @@ /* Peripheral region 2 */ - /* -0x2ffff: Reserved */ +/* -0x2ffff: + * Reserved + */ + # define TIVA_CCM_BASE (TIVA_PERIPH2_BASE + 0x30000) /* -0x30fff: CRC/Cryptographic Control */ /* -0x53fff: Reserved */ # define TIVA_EPHY_BASE (TIVA_PERIPH2_BASE + 0x54000) /* -0x54fff: EPHY 0 */ @@ -929,7 +937,9 @@ /* Peripheral region 2 */ - /* -0x2ffff: Reserved */ +/* -0x2ffff: + * Reserved + */ # define TIVA_CCM_BASE (TIVA_PERIPH2_BASE + 0x30000) /* -0x30fff: CRC/Cryptographic Control */ /* -0x33fff: Reserved */ # define TIVA_SHAMD5_BASE (TIVA_PERIPH2_BASE + 0x34000) /* -0x35fff: SHA/MD5 */ @@ -944,16 +954,16 @@ # error "Peripheral base addresses not specified for this Tiva chip" #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_MEMORYMAP_H */ diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c_pinmap.h b/arch/arm/src/tiva/hardware/tm4c/tm4c_pinmap.h index d3e19a8b802..a176127b559 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c_pinmap.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c_pinmap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tm4c/tm4c_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,39 +16,40 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_PINMAP_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_PINMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Alternate Pin Functions. All members of the TM4C family share the same pin - * multiplexing (although they may differ in the pins physically available). +/* Alternate Pin Functions. + * All members of the TM4C family share the same pin multiplexing + * (although they may differ in the pins physically available). * - * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. - * Drivers, however, will use the pin selection without the numeric suffix. - * Additional definitions are required in the board.h file. For example, if - * CAN1_RX connects via PN0 on some board, then the following definitions should - * appear in the board.h header file for that board: + * Alternative pin selections are provided with a numeric suffix like _1, _2, + * etc. Drivers, however, will use the pin selection without the numeric + * suffix. Additional definitions are required in the board.h file. + * For example, if CAN1_RX connects via PN0 on some board, then the following + * definitions should appear in the board.h header file for that board: * * #define GPIO_CAN1_RX GPIO_CAN1_RX_1 * * The driver will then automatically configure PA11 as the CAN1 RX pin. */ -/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! - * Additional effort is required to select specific GPIO options such as frequency, - * open-drain/push-pull, and pull-up/down! Just the basics are defined for most - * pins in this file. +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as + * frequency, open-drain/push-pull, and pull-up/down! Just the basics are + * defined for most pins in this file. */ #if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) @@ -3019,16 +3020,16 @@ # error "Unknown TIVA chip" #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_PINMAP_H */ diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c_uart.h b/arch/arm/src/tiva/hardware/tm4c/tm4c_uart.h index 4058fd0d4be..b6a3b1f7e18 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c_uart.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c_uart.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/hardware/tm4c/tm4c_uart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_UART_H #define __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_UART_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* UART register offsets ************************************************************/ +/* UART register offsets ****************************************************/ #define TIVA_UART_DR_OFFSET 0x0000 /* UART Data */ #define TIVA_UART_RSR_OFFSET 0x0004 /* UART Receive Status */ @@ -70,7 +70,7 @@ #define TIVA_UART_PCELLID2_OFFSET 0x0ff8 /* UART PrimeCell Identification 2 */ #define TIVA_UART_PCELLID3_OFFSET 0x0ffc /* UART PrimeCell Identification 3 */ -/* UART register addresses **********************************************************/ +/* UART register addresses **************************************************/ #define TIVA_UART_BASE(n) (TIVA_UART0_BASE + (n)*0x01000) @@ -414,7 +414,7 @@ # define TIVA_UART7_PCELLID3 (TIVA_UART7_BASE + TIVA_UART_PCELLID3_OFFSET) #endif -/* UART register bit settings *******************************************************/ +/* UART register bit settings ***********************************************/ /* UART Data (DR) */ @@ -711,12 +711,12 @@ #define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_UART_H */ diff --git a/arch/arm/src/tiva/tiva_chipinfo.h b/arch/arm/src/tiva/tiva_chipinfo.h index de34b3dd7c7..a43177fac38 100644 --- a/arch/arm/src/tiva/tiva_chipinfo.h +++ b/arch/arm/src/tiva/tiva_chipinfo.h @@ -1,4 +1,4 @@ -/***************************************************************************** +/**************************************************************************** * arch/arm/src/tiva/tiva_chipinfo.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -37,14 +37,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - *****************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_TIVA_CHIPINFO_H #define __ARCH_ARM_SRC_TIVA_TIVA_CHIPINFO_H -/***************************************************************************** +/**************************************************************************** * Included Files - *****************************************************************************/ + ****************************************************************************/ #include #include @@ -56,9 +56,9 @@ #if defined(CONFIG_ARCH_CHIP_CC13X0) || defined(CONFIG_ARCH_CHIP_CC13X2) -/***************************************************************************** +/**************************************************************************** * Public Types - *****************************************************************************/ + ****************************************************************************/ enum cc13xx_protocol_e { @@ -121,11 +121,11 @@ enum cc13xx_revision_e HWREV_2_4 = 24 /* 24 The chip's HW revision is 2.4 */ }; -/***************************************************************************** +/**************************************************************************** * Public Function Prototypes - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Name: chipinfo_protocols * * Description: @@ -134,11 +134,11 @@ enum cc13xx_revision_e * Returned Value: * Returns a bit set indicating supported protocols. * - *****************************************************************************/ + ****************************************************************************/ enum cc13xx_protocol_e chipinfo_protocols(void); -/***************************************************************************** +/**************************************************************************** * Name: chipinfo_packagetype * * Description: @@ -147,11 +147,11 @@ enum cc13xx_protocol_e chipinfo_protocols(void); * Returned Value: * Returns an enumeration value indicating the package type. * - *****************************************************************************/ + ****************************************************************************/ enum cc13xx_package_e chipinfo_packagetype(void); -/***************************************************************************** +/**************************************************************************** * Name: chipinfo_hwrevcode * * Description: @@ -160,7 +160,7 @@ enum cc13xx_package_e chipinfo_packagetype(void); * Returned Value: * Returns the internal chip HW revision code (in range 0-15) * - *****************************************************************************/ + ****************************************************************************/ static inline uint32_t chipinfo_hwrevcode(void) { @@ -172,7 +172,7 @@ static inline uint32_t chipinfo_hwrevcode(void) FCFG1_ICEPICK_DEVICE_ID_PG_REV_SHIFT; } -/***************************************************************************** +/**************************************************************************** * Name: chipinfo_hwminorrev * * Description: @@ -184,7 +184,7 @@ static inline uint32_t chipinfo_hwrevcode(void) * Returned Value: * Returns the minor hardware revision number (in range 0-127) * - *****************************************************************************/ + ****************************************************************************/ static inline uint32_t chipinfo_hwminorrev(void) { @@ -192,15 +192,15 @@ static inline uint32_t chipinfo_hwminorrev(void) uint32_t minorrev = (regval & FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_MASK) >> FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_SHIFT; - if (minorrev >= 0x80) - { + if (minorrev >= 0x80) + { minorrev = 0; - } + } - return minorrev; + return minorrev; } -/***************************************************************************** +/**************************************************************************** * Name: chipinfo_userid * * Description: @@ -212,14 +212,14 @@ static inline uint32_t chipinfo_hwminorrev(void) * Returned Value: * Returns the 32 bits USER_ID field * - *****************************************************************************/ + ****************************************************************************/ static inline uint32_t chipinfo_userid(void) { return getreg32(TIVA_FCFG1_USER_ID); } -/***************************************************************************** +/**************************************************************************** * Name: chipinfo_chiptype * * Description: @@ -228,11 +228,11 @@ static inline uint32_t chipinfo_userid(void) * Returned Value: * Returns an enumeration value indicating the chip type * - *****************************************************************************/ + ****************************************************************************/ enum cc13xx_chiptype_e chipinfo_chiptype(void); -/***************************************************************************** +/**************************************************************************** * Name: chipinfo_chipfamily * * Description: @@ -241,34 +241,37 @@ enum cc13xx_chiptype_e chipinfo_chiptype(void); * Returned Value: * Returns an enumeration value indicating the chip family * - *****************************************************************************/ + ****************************************************************************/ enum cc13xx_chipfamily_e chipinfo_chipfamily(void); -/***************************************************************************** +/**************************************************************************** * Name: chipinfo_hwrevision * * Description: - * Returns an enumeration value indicating the hardware revision of the chip + * Returns an enumeration value indicating the hardware revision of the + * chip * * Returned Value: - * Returns an enumeration value indicating the hardware revision of the chip + * Returns an enumeration value indicating the hardware revision of the + * chip * - *****************************************************************************/ + ****************************************************************************/ enum cc13xx_revision_e chipinfo_hwrevision(void); -/***************************************************************************** +/**************************************************************************** * Name: chipinfo_verify * * Description: - * Verifies that system is correctly configured for the current chip. This - * function will assert if that the system is NOT correctly configured. + * Verifies that system is correctly configured for the current chip. + * This function will assert if that the system is NOT correctly + * configured. * * Returned Value: * None * - *****************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_ASSERTIONS void chipinfo_verify(void); diff --git a/arch/arm/src/tiva/tiva_enableclks.h b/arch/arm/src/tiva/tiva_enableclks.h index e3f7bf81062..5a925148380 100644 --- a/arch/arm/src/tiva/tiva_enableclks.h +++ b/arch/arm/src/tiva/tiva_enableclks.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/tiva_enableclks.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_TIVA_ENABLECLKS_H #define __ARCH_ARM_SRC_TIVA_TIVA_ENABLECLKS_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include diff --git a/arch/arm/src/tiva/tiva_enablepwr.h b/arch/arm/src/tiva/tiva_enablepwr.h index 999bbc49f41..12e342ea3d2 100644 --- a/arch/arm/src/tiva/tiva_enablepwr.h +++ b/arch/arm/src/tiva/tiva_enablepwr.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/tiva_enablepwr.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_TIVA_ENABLEPWR_H #define __ARCH_ARM_SRC_TIVA_TIVA_ENABLEPWR_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include diff --git a/arch/arm/src/tiva/tiva_periphrdy.h b/arch/arm/src/tiva/tiva_periphrdy.h index b4f36a42a4f..02d2d1685c5 100644 --- a/arch/arm/src/tiva/tiva_periphrdy.h +++ b/arch/arm/src/tiva/tiva_periphrdy.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/tiva/tiva_periphrdy.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_TIVA_TIVAPERIPHRDY_H #define __ARCH_ARM_SRC_TIVA_TIVAPERIPHRDY_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -31,12 +31,12 @@ #include "chip.h" #include "hardware/tiva_sysctrl.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* We determine if a peripheral is ready by testing a bit (b) in system control - * register (a). +/* We determine if a peripheral is ready by testing a bit (b) in system + * control register (a). */ #define tiva_periphrdy(a,b) ((getreg32(a) & (b)) != 0)