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arch: arm: sam: fix nxstyle errors

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Fix nxstyle errors to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea
2021-03-24 09:35:15 +01:00
committed by Brennan Ashton
parent 56471c77b3
commit 60424bc762
422 changed files with 15478 additions and 9980 deletions
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arch/arm/src/sam34/chip.h
+12 -11
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,19 +16,20 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_H
#define __ARCH_ARM_SRC_SAM34_CHIP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/* Include the memory map and the chip definitions file. Other chip hardware files
* should then include this file for the proper setup.
/* Include the memory map and the chip definitions file.
* Other chip hardware files should then include this file for the proper
* setup.
*/
#include <arch/sam34/chip.h>
@@ -38,13 +39,13 @@
#include <arch/sam34/irq.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Provide the required number of peripheral interrupt vector definitions as well.
* The definition SAM_IRQ_NEXTINT simply comes from the chip-specific IRQ header
* file included by arch/sam34/irq.h.
/* Provide the required number of peripheral interrupt vector definitions as
* well. The definition SAM_IRQ_NEXTINT simply comes from the chip-specific
* IRQ header file included by arch/sam34/irq.h.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS SAM_IRQ_NEXTINT
arch/arm/src/sam34/hardware/sam3u_memorymap.h
+14 -14
View File
@@ -1,4 +1,4 @@
/************************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam3u_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_MEMORYMAP_H
/************************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************************/
****************************************************************************/
#define SAM_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */
# define SAM_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x0007ffff: Boot Memory */
@@ -113,18 +113,18 @@
#define SAM_WDT_BASE 0x400e1250 /* 0x400e1250-0x400e125f: Watchdog Timer */
#define SAM_RTC_BASE 0x400e1260 /* 0x400e1260-0x400e128f: Real Time Clock */
#define SAM_GPBR_BASE 0x400e1290 /* 0x400e1290-0x400e13ff: GPBR */
/* 0x490e1400-0x4007ffff: Reserved */
/* 0x490e1400-0x4007ffff: Reserved */
/************************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************************/
****************************************************************************/
/************************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************************/
****************************************************************************/
/************************************************************************************************
* Public Functions
************************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_MEMORYMAP_H */
arch/arm/src/sam34/hardware/sam3u_pinmap.h
+15 -15
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam3u_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam_gpio.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* GPIO pin definitions *************************************************************/
/* GPIO pin definitions *****************************************************/
#define GPIO_ADC0_AD0 (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN21)
#define GPIO_ADC0_AD1 (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN30)
@@ -172,19 +172,19 @@
#define GPIO_USB_VBUS (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN0)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -195,9 +195,9 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
arch/arm/src/sam34/hardware/sam3u_pio.h
+16 -16
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam3u_pio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PIO_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PIO_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* PIO register offsets *****************************************************************/
/* PIO register offsets *****************************************************/
#define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */
#define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */
@@ -93,7 +93,7 @@
/* 0x00ec-0x00f8: Reserved */
/* 0x0100-0x0144: Reserved */
/* PIO register addresses ***************************************************************/
/* PIO register addresses ***************************************************/
#define PIOA (0)
#define PIOB (1)
@@ -417,7 +417,7 @@
# define SAM_PIOF_WPSR (SAM_PIOF_BASE+SAM_PIO_WPSR_OFFSET)
#endif
/* PIO register bit definitions *********************************************************/
/* PIO register bit definitions *********************************************/
/* Common bit definitions for ALMOST all IO registers (exceptions follow) */
@@ -436,16 +436,16 @@
#define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define PIO_WPSR_WPVSRC_MASK (0xffff << PIO_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PIO_H */
arch/arm/src/sam34/hardware/sam3x_memorymap.h
+17 -13
View File
@@ -1,4 +1,4 @@
/************************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam3x_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_MEMORYMAP_H
/************************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************************/
****************************************************************************/
/* Address regions */
@@ -47,6 +47,7 @@
#define SAM_INTFLASH1_BASE (0x00080000 + SAM34_FLASH_SIZE/2)
#define SAM_INTROM_BASE 0x00100000 /* 0x00100000-0x001fffff: Internal ROM */
/* 0x00200000-0x1fffffff: Reserved */
/* Internal SRAM memory region */
#define SAM_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: Internal SRAM 0 */
@@ -56,6 +57,7 @@
/* 0x20200000-0x201fffff: Undefined */
#define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32Mb bit-band alias */
/* 0x24000000-0x3fffffff: Undefined */
/* Peripherals address region */
#define SAM_HSMCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */
@@ -101,6 +103,7 @@
/* 0x41000000-0x41ffffff: Undefined */
#define SAM_BBPERIPH_BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */
/* 0x44000000-0x5fffffff: Undefined */
/* System Controller Register Blocks: 0x400e0000-0x4007ffff */
#define SAM_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */
@@ -127,6 +130,7 @@
#define SAM_RTC_BASE 0x400e1a60 /* 0x400e1a60-0x400e1a8f: Real Time Clock */
#define SAM_GPBR_BASE 0x400e1a90 /* 0x400e1a90-0x400e1aaf: GPBR */
/* 0x400e1ab0-0x4007ffff: Reserved */
/* External RAM memory region */
#define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */
@@ -144,16 +148,16 @@
#define SAM_SDRAMCS_BASE 0x70000000 /* 0x70000000-0x7fffffff: SDRAM chip select */
/* 0x80000000-0x9fffffff: Reserved */
/************************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************************/
****************************************************************************/
/************************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************************/
****************************************************************************/
/************************************************************************************************
* Public Functions
************************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_MEMORYMAP_H */
arch/arm/src/sam34/hardware/sam3x_pinmap.h
+25 -24
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam3x_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,42 +16,43 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_PINMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_PINMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam_gpio.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* GPIO pin definitions *****************************************************/
/* GPIO pin definitions *************************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file. For example, if we
* wanted the PWM0 Output high on PE15, then the following definition should appear
* in the board.h header file for that board:
* Alternative pin selections are provided with a numeric suffix like _1, _2,
* etc. Drivers, however, will use the pin selection without the numeric
* suffix. Additional definitions are required in the board.h file. For
* example, if we wanted the PWM0 Output high on PE15, then the following
* definition should appear in the board.h header file for that board:
*
* #define GPIO_PWM0_H GPIO_PWM0_H_1
*
* The driver will then automatically configure RE15 as the PWM0 H pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file.
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as
* frequency, open-drain/push-pull, and pull-up/down! Just the basics are
* defined for most pins in this file.
*/
/* 12-bit Analog-to-Digital Conververt (ADC) */
@@ -408,19 +409,19 @@
#define GPIO_SWI_SWDIO (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN31)
#define GPIO_SWI_TRACESWO (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN30)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -431,9 +432,9 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
arch/arm/src/sam34/hardware/sam4cm_aes.h
+9 -9
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4cm_aes.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_AES_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_AES_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* AES register offsets *********************************************************************/
/* AES register offsets *****************************************************/
#define SAM_AES_CR_OFFSET 0x0000 /* Control Register */
#define SAM_AES_MR_OFFSET 0x0004 /* Control Register */
@@ -53,7 +53,7 @@
#define SAM_AES_CTRR_OFFSET 0x0098 /* GCM Encryption Counter Value Register */
#define SAM_AES_GCMHR_OFFSET 0x009C /* GCM H World Register */
/* AES register addresses *******************************************************************/
/* AES register addresses ***************************************************/
#define SAM_AES_CR (SAM_AES_BASE + SAM_AES_CR_OFFSET)
#define SAM_AES_MR (SAM_AES_BASE + SAM_AES_MR_OFFSET)
@@ -72,7 +72,7 @@
#define SAM_AES_CTRR (SAM_AES_BASE + SAM_AES_CTRR_OFFSET)
#define SAM_AES_GCMHR (SAM_AES_BASE + SAM_AES_GCMHR_OFFSET)
/* AES register bit definitions *************************************************************/
/* AES register bit definitions *********************************************/
/* AES Control Register */
arch/arm/src/sam34/hardware/sam4cm_ipc.h
+8 -8
View File
@@ -1,4 +1,4 @@
/***********************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4cm_ipc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
***********************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_IPC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_IPC_H
/***********************************************************************************
/****************************************************************************
* Included Files
***********************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/***********************************************************************************
/****************************************************************************
* Pre-processor Definitions
***********************************************************************************/
****************************************************************************/
/* IPC register offsets ************************************************************/
/* IPC register offsets *****************************************************/
#define SAM_SLCDC_CR_OFFSET 0x0000 /* Control Register */
@@ -44,7 +44,7 @@
#define SAM_IPC_IMR_OFFSET 0x0014 /* Interrupt Mask Register */
#define SAM_IPC_ISR_OFFSET 0x0018 /* Interrupt Status Register */
/* IPC register addresses **********************************************************/
/* IPC register addresses ***************************************************/
#define SAM_IPC0_ISCR (SAM_IPC0_BASE + SAM_IPC_ISCR_OFFSET)
#define SAM_IPC0_ICCR (SAM_IPC0_BASE + SAM_IPC_ICCR_OFFSET)
arch/arm/src/sam34/hardware/sam4cm_memorymap.h
+17 -14
View File
@@ -1,4 +1,4 @@
/************************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4cm_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_MEMORYMAP_H
/************************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************************/
****************************************************************************/
/* Address regions */
@@ -53,6 +53,7 @@
#define SAM_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: Internal SRAM 1 */
#define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32MB bit-band region */
/* 0x24000000-0x3fffffff: Undefined */
/* Peripherals address region */
#define SAM_AES_BASE 0x40000000
@@ -113,20 +114,21 @@
# define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */
# define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */
/* 0x64000000-0x9fffffff: Reserved */
/* System memory region */
#define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */
#define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */
/************************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -139,7 +141,8 @@ extern "C"
static inline unsigned long SAM_PION_BASE(int n)
{
switch(n) {
switch (n)
{
case 0:
return SAM_PIOA_BASE;
case 1:
@@ -148,12 +151,12 @@ static inline unsigned long SAM_PION_BASE(int n)
return SAM_PIOC_BASE;
default:
return 0;
}
}
}
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
arch/arm/src/sam34/hardware/sam4cm_pinmap.h
+28 -26
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4cm_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,42 +16,44 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_PINMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_PINMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam_gpio.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* GPIO pin definitions *****************************************************/
/* GPIO pin definitions *************************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file. For example, if we
* wanted the programmable clock output PCK0 on PA6, then the following definition
* should appear in the board.h header file for that board:
* Alternative pin selections are provided with a numeric suffix like _1, _2,
* etc. Drivers, however, will use the pin selection without the numeric
* suffix. Additional definitions are required in the board.h file. For
* example, if we wanted the programmable clock output PCK0 on PA6, then the
* following definition should appear in the board.h header file for that
* board:
*
* #define GPIO_PCK0 GPIO_PCK0_1
*
* The driver will then automatically configure PA6 as the PCK0 pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file.
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as
* frequency, open-drain/push-pull, and pull-up/down! Just the basics are
* defined for most pins in this file.
*/
/* 12-bit Analog-to-Digital Converter (ADC) */
@@ -237,7 +239,8 @@
#define GPIO_USART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22)
/* Segment LCD Controller (SLCDC) */
//TODO: add rest of segment pins
/* TODO: add rest of segment pins */
#define GPIO_SLCDC_COM0 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN0)
#define GPIO_SLCDC_COM1 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN1)
@@ -270,20 +273,19 @@
#define GPIO_SLCDC_SEG21 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN27)
#define GPIO_SLCDC_SEG22 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN28)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -294,9 +296,9 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
arch/arm/src/sam34/hardware/sam4cm_slcdc.h
+9 -9
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4cm_slcdc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SLCDC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SLCDC_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* SLCDC register offsets ************************************************************/
/* SLCDC register offsets ***************************************************/
#define SAM_SLCDC_CR_OFFSET 0x0000 /* Control Register */
#define SAM_SLCDC_MR_OFFSET 0x0004 /* Mode Register */
@@ -54,7 +54,7 @@
#define SAM_SLCDC_LMEMR_OFFSET(com) (0x200 + (com)*8 + 0x0)
#define SAM_SLCDC_MMEMR_OFFSET(com) (0x200 + (com)*8 + 0x4)
/* SLCDC register addresses **********************************************************/
/* SLCDC register addresses *************************************************/
#define SAM_SLCDC_CR (SAM_SLCDC_BASE + SAM_SLCDC_CR_OFFSET)
#define SAM_SLCDC_MR (SAM_SLCDC_BASE + SAM_SLCDC_MR_OFFSET)
@@ -74,7 +74,7 @@
#define SAM_SLCDC_LMEMR(com) (SAM_SLCDC_BASE + SAM_SLCDC_LMEMR_OFFSET(com))
#define SAM_SLCDC_MMEMR(com) (SAM_SLCDC_BASE + SAM_SLCDC_MMEMR_OFFSET(com))
/* SLCDC register bit definitions ****************************************************/
/* SLCDC register bit definitions *******************************************/
/* Control Register */
arch/arm/src/sam34/hardware/sam4cm_supc.h
+19 -16
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4cm_supc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SUPC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SUPC_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* SUPC register offsets ****************************************************************/
/* SUPC register offsets ****************************************************/
#define SAM_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */
#define SAM_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */
@@ -43,7 +43,7 @@
#define SAM_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */
#define SAM_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */
/* SUPC register addresses **************************************************************/
/* SUPC register addresses **************************************************/
#define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET)
#define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET)
@@ -52,7 +52,8 @@
#define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET)
#define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET)
/* SUPC register bit definitions ********************************************************/
/* SUPC register bit definitions ********************************************/
/* Supply Controller Control Register */
#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */
@@ -89,6 +90,7 @@
# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */
# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */
# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */
#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */
#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */
@@ -116,6 +118,7 @@
# define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */
# define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */
# define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */
#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */
#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT)
# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */
@@ -146,16 +149,16 @@
#define SUPC_SR_WKUPIS_SHIFT (16) /* Bits 16-31: WKUP Input Status 0 to 15 */
#define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT)
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SUPC_H */
arch/arm/src/sam34/hardware/sam4e_memorymap.h
+16 -14
View File
@@ -1,4 +1,4 @@
/************************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4e_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_MEMORYMAP_H
/************************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************************/
****************************************************************************/
/* Address regions */
@@ -47,6 +47,7 @@
#define SAM_INTFLASH_BASE 0x00400000 /* 0x00400000-0x007fffff: Internal FLASH */
#define SAM_INTROM_BASE 0x00800000 /* 0x00180000-0x00bfffff: Internal ROM */
/* 0x00c00000-0x1fffffff: Reserved */
/* Internal SRAM memory region */
#define SAM_INTSRAM0_BASE 0x20000000 /* For SAM3U compatibility */
@@ -111,7 +112,7 @@
/* System Controller Register Blocks: 0x400e0000-0x4007ffff */
/* 0x400e0000-0x400e01ff: Reserved */
/* 0x400e0000-0x400e01ff: Reserved */
#define SAM_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */
#define SAM_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */
#define SAM_UART0_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART 0 */
@@ -144,21 +145,22 @@
# define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */
# define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */
/* 0x64000000-0x9fffffff: Reserved */
/* System memory region */
#define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */
#define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */
/************************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************************/
****************************************************************************/
/************************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************************/
****************************************************************************/
/************************************************************************************************
* Public Functions
************************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_MEMORYMAP_H */
arch/arm/src/sam34/hardware/sam4e_pinmap.h
+26 -24
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4e_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,42 +16,44 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PINMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PINMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam_gpio.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* GPIO pin definitions *****************************************************/
/* GPIO pin definitions *************************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file. For example, if we
* wanted the programmable clock output PCK0 on PA6, then the following definition
* should appear in the board.h header file for that board:
* Alternative pin selections are provided with a numeric suffix like _1, _2,
* etc. Drivers, however, will use the pin selection without the numeric
* suffix. Additional definitions are required in the board.h file. For
* example, if we wanted the programmable clock output PCK0 on PA6, then the
* following definition should appear in the board.h header file for that
* board:
*
* #define GPIO_PCK0 GPIO_PCK0_1
*
* The driver will then automatically configure PA6 as the PCK0 pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file.
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as
* frequency, open-drain/push-pull, and pull-up/down! Just the basics are
* defined for most pins in this file.
*/
/* Analog Front End (AFE) */
@@ -286,19 +288,19 @@
#define GPIO_USART1_SCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23)
#define GPIO_USART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -309,9 +311,9 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
arch/arm/src/sam34/hardware/sam4e_pio.h
+20 -17
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4e_pio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PIO_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PIO_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* PIO register offsets *****************************************************************/
/* PIO register offsets *****************************************************/
#define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */
#define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */
@@ -107,7 +107,7 @@
#define SAM_PIO_PCRHR_OFFSET 0x0164 /* Parallel Capture Reception Holding Register */
/* 0x0168-0x018c: Reserved for PDC registers */
/* PIO register addresses ***************************************************************/
/* PIO register addresses ***************************************************/
#define PIOA (0)
#define PIOB (1)
@@ -450,7 +450,7 @@
#define SAM_PIOE_PCISR (SAM_PIOE_BASE+SAM_PIO_PCISR_OFFSET)
#define SAM_PIOE_PCRHR (SAM_PIOE_BASE+SAM_PIO_PCRHR_OFFSET
/* PIO register bit definitions *********************************************************/
/* PIO register bit definitions *********************************************/
/* Common bit definitions for ALMOST all IO registers (exceptions follow) */
@@ -512,27 +512,30 @@
# define PIO_PCMR_DSIZE_BYTE (0 << PIO_PCMR_DSIZE_SHIFT) /* 8-bit data in PIO_PCRHR */
# define PIO_PCMR_DSIZE_HWORD (1 << PIO_PCMR_DSIZE_SHIFT) /* 16-bit data in PIO_PCRHR */
# define PIO_PCMR_DSIZE_WORD (2 << PIO_PCMR_DSIZE_SHIFT) /* 32-bit data in PIO_PCRHR */
#define PIO_PCMR_ALWYS (1 << 9) /* Bit 9: Parallel Capture Mode Always Sampling */
#define PIO_PCMR_HALFS (1 << 10) /* Bit 10: Parallel Capture Mode Half Sampling */
#define PIO_PCMR_FRSTS (1 << 11) /* Bit 11: Parallel Capture Mode First Sample */
/* PIO Parallel Capture Interrupt Enable, Disable, Mask, and Status Registers */
/* PIO Parallel Capture Interrupt Enable, Disable, Mask,
* and Status Registers
*/
#define PIOC_PCINT_DRDY (1 << 0) /* Bit 0: Parallel Capture Mode Data Ready Interrupt Enable */
#define PIOC_PCINT_OVRE (1 << 1) /* Bit 1: Parallel Capture Mode Overrun Error Interrupt Enable */
#define PIOC_PCINT_ENDRX (1 << 2) /* Bit 2: End of Reception Transfer Interrupt Enable */
#define PIOC_PCINT_RXBUFF (1 << 3) /* Bit 3: Reception Buffer Full Interrupt Enable */
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PIO_H */
arch/arm/src/sam34/hardware/sam4l_bpm.h
+22 -16
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_bpm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BPM_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BPM_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* BPM register offsets ****************************************************************/
/* BPM register offsets *****************************************************/
#define SAM_BPM_IER_OFFSET 0x0000 /* Interrupt Enable Register */
#define SAM_BPM_IDR_OFFSET 0x0004 /* Interrupt Disable Register */
@@ -50,7 +50,7 @@
#define SAM_BPM_IORET_OFFSET 0x0034 /* Input Output Retention Register */
#define SAM_BPM_VERSION_OFFSET 0x00fc /* Version Register */
/* BPM register addresses **************************************************************/
/* BPM register addresses ***************************************************/
#define SAM_BPM_IER (SAM_BPM_BASE+SAM_BPM_IER_OFFSET)
#define SAM_BPM_IDR (SAM_BPM_BASE+SAM_BPM_IDR_OFFSET)
@@ -66,13 +66,18 @@
#define SAM_BPM_IORET (SAM_BPM_BASE+SAM_BPM_IORET_OFFSET)
#define SAM_BPM_VERSION (SAM_BPM_BASE+SAM_BPM_VERSION_OFFSET)
/* BPM register bit definitions ********************************************************/
/* BPM register bit definitions *********************************************/
/* Interrupt Enable Register */
/* Interrupt Disable Register */
/* Interrupt Mask Register */
/* Interrupt Status Register */
/* Interrupt Clear Register */
/* Status Register */
#define BPM_INT_PSOK (1 << 0) /* Bit 0: Power Scaling OK */
@@ -104,6 +109,7 @@
# define BPM_PMCON_SLEEP_SLEEP1 (1 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB clocks stopped */
# define BPM_PMCON_SLEEP_SLEEP2 (2 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK clocks stopped */
# define BPM_PMCON_SLEEP_SLEEP3 (3 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK+sources stopped */
#define BPM_PMCON_CK32S (1 << 16) /* Bit 16: 32kHz-1kHz Clock Source Selection */
#define BPM_PMCON_FASTWKUP (1 << 24) /* Bit 24: Fast Wakeup */
@@ -148,16 +154,16 @@
#define BPM_VERSION_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
#define BPM_VERSION_VARIANT_MASK (15 << BPM_VERSION_VARIANT_SHIFT)
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BPM_H */
arch/arm/src/sam34/hardware/sam4l_bscif.h
+34 -16
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_bscif.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BSCIF_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BSCIF_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* BSCIF register offsets ***************************************************************/
/* BSCIF register offsets ***************************************************/
#define SAM_BSCIF_IER_OFFSET 0x0000 /* Interrupt Enable Register */
#define SAM_BSCIF_IDR_OFFSET 0x0004 /* Interrupt Disable Register */
@@ -70,7 +70,7 @@
#define SAM_BSCIF_OSC32IFAVERSION_OFFSET 0x03f8 /* 32 kHz Oscillator Version Register */
#define SAM_BSCIF_VERSION_OFFSET 0x03fc /* BSCIF Version Register */
/* BSCIF register addresses *************************************************************/
/* BSCIF register addresses *************************************************/
#define SAM_BSCIF_IER (SAM_BSCIF_BASE+SAM_BSCIF_IER_OFFSET)
#define SAM_BSCIF_IDR (SAM_BSCIF_BASE+SAM_BSCIF_IDR_OFFSET)
@@ -106,12 +106,16 @@
#define SAM_BSCIF_OSC32IFAVERSION (SAM_BSCIF_BASE+SAM_BSCIF_OSC32IFAVERSION_OFFSET)
#define SAM_BSCIF_VERSION (SAM_BSCIF_BASE+SAM_BSCIF_VERSION_OFFSET)
/* BSCIF register bit definitions *******************************************************/
/* BSCIF register bit definitions *******************************************/
/* Interrupt Enable Register */
/* Interrupt Disable Register */
/* Interrupt Mask Register */
/* Interrupt Status Register */
/* Interrupt Clear Register */
#define BSCIF_INT_OSC32RDY (1 << 0) /* Bit 0 */
@@ -167,6 +171,7 @@
# define BSCIF_OSCCTRL32_MODE_XTALAC (3 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + amplitude controlled mode */
# define BSCIF_OSCCTRL32_MODE_XTALHC (4 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + high current mode */
# define BSCIF_OSCCTRL32_MODE_XTALHCAC (5 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + high current + amplitude controlled mode */
#define BSCIF_OSCCTRL32_SELCURR_SHIFT (12) /* Bits 12-15: Current Selection */
#define BSCIF_OSCCTRL32_SELCURR_MASK (15 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
# define BSCIF_OSCCTRL32_SELCURR_50 (0 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
@@ -185,6 +190,7 @@
# define BSCIF_OSCCTRL32_SELCURR_375 (13 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
# define BSCIF_OSCCTRL32_SELCURR_400 (14 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
# define BSCIF_OSCCTRL32_SELCURR_425 (15 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
#define BSCIF_OSCCTRL32_STARTUP_SHIFT (16) /* Bits 16-18: Oscillator Start-up Time */
#define BSCIF_OSCCTRL32_STARTUP_MASK (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT)
# define BSCIF_OSCCTRL32_STARTUP_0 (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT)
@@ -195,6 +201,7 @@
# define BSCIF_OSCCTRL32_STARTUP_128K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 131072 1.1 s */
# define BSCIF_OSCCTRL32_STARTUP_256K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 262144 2.3 s */
# define BSCIF_OSCCTRL32_STARTUP_512K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 524288 4.6 s */
#define BSCIF_OSCCTRL32_RESERVED (1 << 31) /* Bit 31: Reserved, must always be written as zero */
/* 32kHz RC Oscillator Control Register */
@@ -215,18 +222,22 @@
#define BSCIF_RC32KTUNE_COARSE_MASK (0x7f << BSCIF_RC32KTUNE_COARSE_SHIFT)
/* BOD33 Control Register */
/* BOD18 Control Register */
#define BSCIF_BODCTRL_EN (1 << 0) /* Bit 0: Enable */
#define BSCIF_BODCTRL_HYST (1 << 1) /* Bit 1: BOD Hysteresis */
#define BSCIF_BODCTRL_ACTION_SHIFT (8) /* Bits 8-9: Action */
# define BSCIF_BODCTRL_ACTION_RESET (1 << BSCIF_BODCTRL_ACTION_SHIFT) /* The BOD generates a reset */
# define BSCIF_BODCTRL_ACTION_INTR (2 << BSCIF_BODCTRL_ACTION_SHIFT) /* The BOD generates an interrupt */
#define BSCIF_BODCTRL_MODE (1 << 0) /* Bit 0: Operation modes */
#define BSCIF_BODCTRL_FCD (1 << 0) /* Bit 0: BOD Fuse Calibration Done */
#define BSCIF_BODCTRL_SFV (1 << 0) /* Bit 0: BOD Control Register Store Final Value */
/* BOD33 Level Register */
/* BOD18 Level Register */
#define BSCIF_BODLEVEL_CEN (1 << 0) /* Bit 0: Clock Enable */
@@ -235,6 +246,7 @@
#define BSCIF_BODLEVEL_PSEL_MASK (15 << BSCIF_BODLEVEL_PSEL_SHIFT)
/* BOD33 Sampling Control Register */
/* BOD18 Sampling Control Register */
#define BSCIF_BODSAMPLING_VAL_SHIFT (0) /* Bits 0-5: BOD Value */
@@ -274,11 +286,17 @@
/* 0x0078-0x0084 Backup register n=0..3 (32-bit data) */
/* Backup Register Interface Version Register */
/* BGREFIF Version Register */
/* Voltage Regulator Version Register */
/* BOD Version Register */
/* 32kHz RC Oscillator Version Register */
/* 32 kHz Oscillator Version Register */
/* BSCIF Version Register */
#define BSCIF_VERSION_SHIFT (0) /* Bits 0-11: Version Number */
@@ -286,16 +304,16 @@
#define BSCIF_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
#define BSCIF_VARIANT_MASK (15 << BSCIF_VARIANT_SHIFT)
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BSCIF_H */
arch/arm/src/sam34/hardware/sam4l_flashcalw.h
+20 -17
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_flashcalw.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,26 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_FLASHCALW_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_FLASHCALW_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register offsets *********************************************************/
/* Register offsets *****************************************************************/
/* Relative to SAM_FLASHCALW_BASE */
#define SAM_FLASHCALW_FCR_OFFSET 0x0000 /* Flash Control Register */
@@ -57,7 +58,7 @@
#define SAM_PICOCACHE_MSR_OFFSET 0x0034 /* PicoCache Monitor Status Register */
#define SAM_PICOCACHE_PVR_OFFSET 0x00fc /* Version Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define SAM_FLASHCALW_FCR (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FCR_OFFSET)
#define SAM_FLASHCALW_FCMD (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FCMD_OFFSET)
@@ -77,7 +78,7 @@
#define SAM_PICOCACHE_MSR (SAM_PICOCACHE_BASE+SAM_PICOCACHE_MSR_OFFSET)
#define SAM_PICOCACHE_PVR (SAM_PICOCACHE_BASE+SAM_PICOCACHE_PVR_OFFSET)
/* Register Bit-field Definitions ***************************************************/
/* Register Bit-field Definitions *******************************************/
/* Flash Control Register */
@@ -110,6 +111,7 @@
# define FLASHCALW_FCMD_CMD_QPRUP (15 << FLASHCALW_FCMD_CMD_SHIFT) /* Quick Page Read User Page */
# define FLASHCALW_FCMD_CMD_HSEN (16 << FLASHCALW_FCMD_CMD_SHIFT) /* High Speed Mode Enable */
# define FLASHCALW_FCMD_CMD_HSDIS (17 << FLASHCALW_FCMD_CMD_SHIFT) /* High Speed Mode Disable */
#define FLASHCALW_FCMD_PAGEN_SHIFT (8) /* Bits 8-23: Page number */
#define FLASHCALW_FCMD_PAGEN_MASK (0xffff << FLASHCALW_FCMD_PAGEN_SHIFT)
#define FLASHCALW_FCMD_KEY_SHIFT (14) /* Bits 24-31: Write protection key */
@@ -163,6 +165,7 @@
# define FLASHCALW_FPR_FSZ_768KB (12 << FLASHCALW_FPR_FSZ_SHIFT) /* 768 Kbytes */
# define FLASHCALW_FPR_FSZ_1MB (13 << FLASHCALW_FPR_FSZ_SHIFT) /* 1024 Kbytes */
# define FLASHCALW_FPR_FSZ_2MB (14 << FLASHCALW_FPR_FSZ_SHIFT) /* 2048 Kbytes */
#define FLASHCALW_FPR_PSZ_SHIFT (8) /* Bits 8-9: Page Size */
#define FLASHCALW_FPR_PSZ_MASK (7 << FLASHCALW_FPR_PSZ_SHIFT)
# define FLASHCALW_FPR_PSZ_32KB (0 << FLASHCALW_FPR_PSZ_SHIFT) /* 32 Kbytes */
@@ -295,7 +298,7 @@
#define PICOCACHE_PVR_MFN_SHIFT (16) /* Bits 16-19: MFN */
#define PICOCACHE_PVR_MFN_MASK (15 << PICOCACHE_PVR_FVR_MFN_SHIFT)
/* Flash Command Set ****************************************************************/
/* Flash Command Set ********************************************************/
#define FLASH_CMD_NOP 0 /* No operation */
#define FLASH_CMD_WP 1 /* Write Page */
@@ -346,16 +349,16 @@
#define FLASH_MAXFREQ_PS2_HSEN_FWS0 (24000000ul)
#define FLASH_MAXFREQ_PS2_HSEN_FWS1 (48000000ul)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_FLASHCALW_H */
arch/arm/src/sam34/hardware/sam4l_gpio.h
+25 -24
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_GPIO_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_GPIO_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* PIO register offsets *****************************************************************/
/* PIO register offsets *****************************************************/
#define SAM_GPIO_GPER_OFFSET 0x0000 /* GPIO Enable Register Read/Write */
#define SAM_GPIO_GPERS_OFFSET 0x0004 /* GPIO Enable Register Set */
@@ -48,10 +48,11 @@
* 010 C 110 G
* 011 D 111 H
*
* NOTE: Labeling in the data sheet is inconsistent. In the pin multiplexing table,
* It shows GPIO functions A-G with 000 apparently corresponding to the GPIO. In the
* register description, it should A-H with presumably A corresponding to 000. Here
* we adopt the above convention.
* NOTE:
* Labeling in the data sheet is inconsistent. In the pin multiplexing table,
* It shows GPIO functions A-G with 000 apparently corresponding to the GPIO.
* In the register description, it should A-H with presumably A
* corresponding to 000. Here we adopt the above convention.
*/
#define SAM_GPIO_PMR0_OFFSET 0x0010 /* Peripheral Mux Register 0 Read/Write */
@@ -166,7 +167,7 @@
#define SAM_GPIO_PARAMETER_OFFSET 0x01f8 /* Parameter Register Read */
#define SAM_GPIO_VERSION_OFFSET 0x01fc /* Version Register Read */
/* GPIO port offsets and addresses ******************************************************/
/* GPIO port offsets and addresses ******************************************/
#define SAM_GPIOA 0
#define SAM_GPIOB 1
@@ -179,7 +180,7 @@
#define SAM_GPIOB_BASE SAM_GPION_BASE(SAM_GPIOB)
#define SAM_GPIOC_BASE SAM_GPION_BASE(SAM_GPIOC)
/* GPIO register addresses **************************************************************/
/* GPIO register addresses **************************************************/
#define SAM_GPIO_GPER(n) (SAM_GPION_BASE(n)+SAM_GPIO_GPER_OFFSET)
#define SAM_GPIO_GPERS(n) (SAM_GPION_BASE(n)+SAM_GPIO_GPERS_OFFSET)
@@ -274,7 +275,7 @@
#define SAM_GPIO_PARAMETER(n) (SAM_GPION_BASE(n)+SAM_GPIO_PARAMETER_OFFSET)
#define SAM_GPIO_VERSION (n) (SAM_GPION_BASE(n)+SAM_GPIO_VERSION_OFFSET)
/* GPIO PORTA register addresses ********************************************************/
/* GPIO PORTA register addresses ********************************************/
#define SAM_GPIOA_GPER (SAM_GPIOA_BASE+SAM_GPIO_GPER_OFFSET)
#define SAM_GPIOA_GPERS (SAM_GPIOA_BASE+SAM_GPIO_GPERS_OFFSET)
@@ -369,7 +370,7 @@
#define SAM_GPIOA_PARAMETER (SAM_GPIOA_BASE+SAM_GPIO_PARAMETER_OFFSET)
#define SAM_GPIOA_VERSION (SAM_GPIOA_BASE+SAM_GPIO_VERSION_OFFSET)
/* GPIO PORTB register addresses ********************************************************/
/* GPIO PORTB register addresses ********************************************/
#define SAM_GPIOB_GPER (SAM_GPIOB_BASE+SAM_GPIO_GPER_OFFSET)
#define SAM_GPIOB_GPERS (SAM_GPIOB_BASE+SAM_GPIO_GPERS_OFFSET)
@@ -464,7 +465,7 @@
#define SAM_GPIOB_PARAMETER (SAM_GPIOB_BASE+SAM_GPIO_PARAMETER_OFFSET)
#define SAM_GPIOB_VERSION (SAM_GPIOB_BASE+SAM_GPIO_VERSION_OFFSET)
/* GPIO PORTC register addresses ********************************************************/
/* GPIO PORTC register addresses ********************************************/
#define SAM_GPIOC_GPER (SAM_GPIOC_BASE+SAM_GPIO_GPER_OFFSET)
#define SAM_GPIOC_GPERS (SAM_GPIOC_BASE+SAM_GPIO_GPERS_OFFSET)
@@ -559,22 +560,22 @@
#define SAM_GPIOC_PARAMETER (SAM_GPIOC_BASE+SAM_GPIO_PARAMETER_OFFSET)
#define SAM_GPIOC_VERSION (SAM_GPIOC_BASE+SAM_GPIO_VERSION_OFFSET)
/* GPIO register bit definitions ********************************************************/
/* GPIO register bit definitions ********************************************/
/* Common bit definitions for all GPIO registers */
#define PIN(n) (1 << (n)) /* Bit n: PIO n */
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_GPIO_H */
arch/arm/src/sam34/hardware/sam4l_lcdca.h
+37 -20
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_lcdca.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_LCDCA_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_LCDCA_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* LCDCA register offsets ************************************************************/
/* LCDCA register offsets ***************************************************/
#define SAM_LCDCA_CR_OFFSET 0x0000 /* Control Register */
#define SAM_LCDCA_CFG_OFFSET 0x0004 /* Configuration Register */
@@ -67,7 +67,7 @@
#define SAM_LCDCA_IMR_OFFSET 0x0060 /* Interrupt Mask Register */
#define SAM_LCDCA_VERSION_OFFSET 0x0064 /* Version Register */
/* LCDCA register addresses **********************************************************/
/* LCDCA register addresses *************************************************/
#define SAM_LCDCA_CR (SAM_LCDCA_BASE+SAM_LCDCA_CR_OFFSET)
#define SAM_LCDCA_CFG (SAM_LCDCA_BASE+SAM_LCDCA_CFG_OFFSET)
@@ -100,7 +100,7 @@
#define SAM_LCDCA_IMR (SAM_LCDCA_BASE+SAM_LCDCA_IMR_OFFSET)
#define SAM_LCDCA_VERSION (SAM_LCDCA_BASE+SAM_LCDCA_VERSION_OFFSET)
/* LCDCA register bit definitions ****************************************************/
/* LCDCA register bit definitions *******************************************/
/* Control Register */
@@ -132,9 +132,11 @@
# define LCDCA_CFG_DUTY_STATIC (1 << LCDCA_CFG_DUTY_SHIFT) /* Static, Static, COM0 */
# define LCDCA_CFG_DUTY_1TO2 (2 << LCDCA_CFG_DUTY_SHIFT) /* 1/2, 1/3, COM[0:1] */
# define LCDCA_CFG_DUTY_1TO3 (3 << LCDCA_CFG_DUTY_SHIFT) /* 1/3, 1/3, COM[0:2] */
#define LCDCA_CFG_FCST_SHIFT (16) /* Bits 16-21: Fine Contrast */
#define LCDCA_CFG_FCST_MASK (63 << LCDCA_CFG_FCST_SHIFT)
# define LCDCA_CFG_FCST(n) (((uint32_t)(n) & 63) << LCDCA_CFG_FCST_SHIFT) /* n = -32..31 */
#define LCDCA_CFG_NSU_SHIFT (24) /* Bits 24-29: Number of Segment Terminals in Use */
#define LCDCA_CFG_NSU_MASK (63 << LCDCA_CFG_NSU_SHIFT)
# define LCDCA_CFG_NSU(n) ((n) << LCDCA_CFG_NSU_SHIFT) /* n=0-40 */
@@ -145,13 +147,16 @@
#define LCDCA_TIM_CLKDIV_SHIFT (1) /* Bits 1-3: LCD Clock Division */
#define LCDCA_TIM_CLKDIV_MASK (7 << LCDCA_TIM_CLKDIV_SHIFT)
# define LCDCA_TIM_CLKDIV(n) (((n)-1) << LCDCA_TIM_CLKDIV_SHIFT) /* n=1..8 */
#define LCDCA_TIM_FC0_SHIFT (8) /* Bits 8-12: Frame Counter 0 */
#define LCDCA_TIM_FC0_MASK (31 << LCDCA_TIM_FC0_SHIFT)
# define LCDCA_TIM_FC0(n) ((n) << LCDCA_TIM_FC0_SHIFT) /* n=0-31 */
#define LCDCA_TIM_FC0PB (1 << 13) /* Bit 13: Frame Counter 0 Prescaler Bypass */
#define LCDCA_TIM_FC1_SHIFT (16) /* Bits 16-20: Frame Counter 1 */
#define LCDCA_TIM_FC1_MASK (31 << LCDCA_TIM_FC1_SHIFT)
# define LCDCA_TIM_FC1(n) ((n) << LCDCA_TIM_FC1_SHIFT) /* n=0-31 */
#define LCDCA_TIM_FC2_SHIFT (24) /* Bits 24-28: Frame Counter 2 */
#define LCDCA_TIM_FC2_MASK (31 << LCDCA_TIM_FC2_SHIFT)
# define LCDCA_TIM_FC2(n) ((n) << LCDCA_TIM_FC2_SHIFT) /* n=0-31 */
@@ -172,14 +177,14 @@
#define LCDCA_SCR_FC0R (1 << 0) /* Bit 0: Frame Counter 0 Rollover */
/* Data Register Low 0-3 (32-bit data, each bit defines a segment value in display
* memory for segments 0-31).
/* Data Register Low 0-3 (32-bit data, each bit defines a segment value in
* display memory for segments 0-31).
*/
#define LCDCA_DRL_MASK 0xffffffff
/* Data Register High 0-3 (8 bits data, each bit defines a segment value in display
* memory for segments 32-39)
/* Data Register High 0-3 (8 bits data, each bit defines a segment value in
* display memory for segments 32-39)
*/
#define LCDCA_DRH_MASK 0xff
@@ -221,6 +226,7 @@
# define LCDCA_BCFG_FCS0 (0 << LCDCA_BCFG_FCS_SHIFT)
# define LCDCA_BCFG_FCS1 (1 << LCDCA_BCFG_FCS_SHIFT)
# define LCDCA_BCFG_FCS2 (2 << LCDCA_BCFG_FCS_SHIFT)
#define LCDCA_BCFG_BSS0_SHIFT (8) /* Bits 8-11: Blink Segment Selection 0 */
#define LCDCA_BCFG_BSS0_MASK (15 << LCDCA_BCFG_BSS0_SHIFT)
# define LCDCA_BCFG_BSS0(n) ((n) << LCDCA_BCFG_BSS0_SHIFT) /* n=bitset */
@@ -228,6 +234,7 @@
# define LCDCA_BCFG_BSS01 (0 << LCDCA_BCFG_BSS0_SHIFT) /* Segment SEG0/COM1 selected */
# define LCDCA_BCFG_BSS02 (0 << LCDCA_BCFG_BSS0_SHIFT) /* Segment SEG0/COM2 selected */
# define LCDCA_BCFG_BSS03 (0 << LCDCA_BCFG_BSS0_SHIFT) /* Segment SEG0/COM3 selected */
#define LCDCA_BCFG_BSS1_SHIFT (12) /* Bits 12-15: Blink Segment Selection 1 */
#define LCDCA_BCFG_BSS1_MASK (15 << LCDCA_BCFG_BSS1_SHIFT)
# define LCDCA_BCFG_BSS1(n) ((n) << LCDCA_BCFG_BSS1_SHIFT) /* n=bitset */
@@ -245,9 +252,11 @@
# define LCDCA_CSRCFG_FCS0 (0 << LCDCA_CSRCFG_FCS_SHIFT)
# define LCDCA_CSRCFG_FCS1 (1 << LCDCA_CSRCFG_FCS_SHIFT)
# define LCDCA_CSRCFG_FCS2 (2 << LCDCA_CSRCFG_FCS_SHIFT)
#define LCDCA_CSRCFG_SIZE_SHIFT (3) /* Bits 3-5: Size */
#define LCDCA_CSRCFG_SIZE_MASK (7 << LCDCA_CSRCFG_SIZE_SHIFT)
# define LCDCA_CSRCFG_SIZE(n) (((n)-1) << LCDCA_CSRCFG_SIZE_SHIFT) /* n=1..8 */
#define LCDCA_CSRCFG_DATA_SHIFT (8) /* Bits 8-15: Circular Shift Register Value */
#define LCDCA_CSRCFG_DATA_MASK (0xff << LCDCA_CSRCFG_DATA_SHIFT)
# define LCDCA_CSRCFG_DATA(n) ((n) << LCDCA_CSRCFG_DATA_SHIFT)
@@ -261,6 +270,7 @@
# define LCDCA_CMCFG_TDG_7S4C (1 << LCDCA_CMCFG_TDG_SHIFT) /* 7-segment with 4 common terminals */
# define LCDCA_CMCFG_TDG_14S4C (2 << LCDCA_CMCFG_TDG_SHIFT) /* 14-segment with 4 common terminals */
# define LCDCA_CMCFG_TDG_14S3C (3 << LCDCA_CMCFG_TDG_SHIFT) /* 16-segment with 3 common terminals */
#define LCDCA_CMCFG_STSEG_SHIFT (8) /* Bits 8-13: Start Segment */
#define LCDCA_CMCFG_STSEG_MASK (63 << LCDCA_CMCFG_STSEG_SHIFT)
# define LCDCA_CMCFG_STSEG(n) ((n) << LCDCA_CMCFG_STSEG_SHIFT)
@@ -278,6 +288,7 @@
# define LCDCA_ACMCFG_FCS0 (0 << LCDCA_ACMCFG_FCS_SHIFT)
# define LCDCA_ACMCFG_FCS1 (1 << LCDCA_ACMCFG_FCS_SHIFT)
# define LCDCA_ACMCFG_FCS2 (2 << LCDCA_ACMCFG_FCS_SHIFT)
#define LCDCA_ACMCFG_MODE (1 << 3) /* Bit 3: Mode */
#define LCDCA_ACMCFG_DREV (1 << 4) /* Bit 4: Digit Reverse */
#define LCDCA_ACMCFG_TDG_SHIFT (5) /* Bits 5-6: Type of Digit */
@@ -286,12 +297,15 @@
# define LCDCA_ACMCFG_TDG_7S4C (1 << LCDCA_ACMCFG_TDG_SHIFT) /* 7-segment with 4 common terminals */
# define LCDCA_ACMCFG_TDG_14S4C (2 << LCDCA_ACMCFG_TDG_SHIFT) /* 14-segment with 4 common terminals */
# define LCDCA_ACMCFG_TDG_14S3C (3 << LCDCA_ACMCFG_TDG_SHIFT) /* 16-segment with 3 common terminals */
#define LCDCA_ACMCFG_STSEG_SHIFT (8) /* Bits 8-13: Start Segment */
#define LCDCA_ACMCFG_STSEG_MASK (63 << LCDCA_ACMCFG_STSEG_SHIFT)
# define LCDCA_ACMCFG_STSEG(n) ((n) << LCDCA_ACMCFG_STSEG_SHIFT)
#define LCDCA_ACMCFG_STEPS_SHIFT (16) /* Bits 16-23: Scrolling Steps */
#define LCDCA_ACMCFG_STEPS_MASK (0xff << LCDCA_ACMCFG_STEPS_SHIFT)
# define LCDCA_ACMCFG_STEPS(n) ((n) << LCDCA_ACMCFG_STEPS_SHIFT) /* n = string length - DIGN + 1 */
#define LCDCA_ACMCFG_DIGN_SHIFT (24) /* Bits 24-27: Digit Number */
#define LCDCA_ACMCFG_DIGN_MASK (15 << LCDCA_ACMCFG_DIGN_SHIFT)
# define LCDCA_ACMCFG_DIGN(n) ((n) << LCDCA_ACMCFG_DIGN_SHIFT) /* n=1..15 */
@@ -309,6 +323,7 @@
# define LCDCA_ABMCFG_FCS0 (0 << LCDCA_ABMCFG_FCS_SHIFT)
# define LCDCA_ABMCFG_FCS1 (1 << LCDCA_ABMCFG_FCS_SHIFT)
# define LCDCA_ABMCFG_FCS2 (2 << LCDCA_ABMCFG_FCS_SHIFT)
#define LCDCA_ABMCFG_SIZE_SHIFT (8) /* Bits 8-12: Size */
#define LCDCA_ABMCFG_SIZE_MASK (31 << LCDCA_ABMCFG_SIZE_SHIFT)
# define LCDCA_ABMCFG_SIZE(n) (((n)-1) << LCDCA_ABMCFG_SIZE_SHIFT) /* n=1..31 */
@@ -342,7 +357,9 @@
# define LCDCA_ABMDR_OFF(n) (31 << LCDCA_ABMDR_OFF_SHIFT)
/* Interrupt Enable Register */
/* Interrupt Disable Register */
/* Interrupt Mask Register */
#define LCDCA_INT_FC0R (1 << 0) /* Bit 0: Frame Counter 0 Rollover */
@@ -354,16 +371,16 @@
#define LCDCA_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
#define LCDCA_VARIANT_MASK (15 << LCDCA_VARIANT_SHIFT)
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_LCDCA_H */
arch/arm/src/sam34/hardware/sam4l_memorymap.h
+21 -13
View File
@@ -1,4 +1,4 @@
/************************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_MEMORYMAP_H
/************************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************************/
****************************************************************************/
/* Global Memory Space */
@@ -45,12 +45,14 @@
#define SAM_INTFLASH_BASE 0x00000000 /* 0x00000000-0x003fffff: Internal FLASH */
/* 0x00400000-0x1fffffff: Reserved */
/* Internal SRAM Space */
#define SAM_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: HRAMC0 (see chip.h) */
/* 0x20008000-0x20ffffff: Reserved */
#define SAM_INTSRAM1_BASE 0x21000000 /* 0x21000000-0x210007ff: HRAMC1 (see chip.h) */
/* 0x21000800-0x21ffffff: Reserved */
/* Peripherals Space */
#define SAM_PERIPHA_BASE 0x40000000 /* 0x40000000-0x4009ffff: Peripheral Bridge A */
@@ -60,7 +62,9 @@
#define SAM_PERIPHC_BASE 0x400e0000 /* 0x400e0000-0x400effff: Peripheral Bridge C */
#define SAM_PERIPHD_BASE 0x400e0000 /* 0x400f0000-0x400fffff: Peripheral Bridge D */
/* 0x40100000-0x5fffffff: Reserved */
/* Peripheral Bridge A */
/* 0x40000000-0x40003fff: Reserved */
#define SAM_I2SC_BASE 0x40004000 /* 0x40004000-0x40007fff: I2S Controller */
#define SAM_SPI0_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */
@@ -93,6 +97,7 @@
#define SAM_TWIM3_BASE 0x4007c000 /* 0x4007c000-0x4007ffff: Two-wire Master Interface 3 */
#define SAM_LCDCA_BASE 0x40080000 /* 0x40080000-0x40083fff: LCD Controller A */
/* 0x40084000-0x4009ffff: Reserved */
/* Peripheral Bridge B */
#define SAM_FLASHCALW_BASE 0x400a0000 /* 0x400a0000-0x400a03ff: FLASHCALW */
@@ -104,6 +109,7 @@
#define SAM_USBC_BASE 0x400a5000 /* 0x400a5000-0x400a5fff: USB 2.0 Interface */
#define SAM_PEVC_BASE 0x400a6000 /* 0x400a6000-0x400a63ff: Peripheral Event Controller */
/* 0x400a6400-0x400affff: Reserved */
/* Peripheral Bridge C */
#define SAM_PM_BASE 0x400e0000 /* 0x400e0000-0x400e073f: Power Manager */
@@ -112,6 +118,7 @@
#define SAM_FREQM_BASE 0x400e0c00 /* 0x400e0c00-0x400e0fff: Frequency Meter */
#define SAM_GPIO_BASE 0x400e1000 /* 0x400e1000-0x400e17ff: GPIO */
/* 0x400e1800-0x400effff: Reserved */
/* Peripheral Bridge D */
#define SAM_BPM_BASE 0x400f0000 /* 0x400f0000-0x400f03ff: Backup Power Manager */
@@ -121,6 +128,7 @@
#define SAM_EIC_BASE 0x400f1000 /* 0x400f1000-0x400f13ff: External Interrupt Controller */
#define SAM_PICOUART_BASE 0x400f1400 /* 0x400f1400-0x400f17ff: PICOUART */
/* 0x400f1800-0x400fffff: Reserved */
/* System Space */
#define SAM_ITM_BASE 0xe0000000 /* 0xe0000000-0xe0000fff: ITM */
@@ -135,16 +143,16 @@
#define SAM_ROMTAB_BASE 0xe00ff000 /* 0xe00ff000-0xe00fffff: ROM Table */
/* 0xe0100000-0xffffffff: Reserved */
/************************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************************/
****************************************************************************/
/************************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************************/
****************************************************************************/
/************************************************************************************************
* Public Functions
************************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_MEMORYMAP_H */
arch/arm/src/sam34/hardware/sam4l_pdca.h
+24 -19
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_pdca.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PDCA_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PDCA_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* PDCA channel offsets *****************************************************************/
/* PDCA channel offsets *****************************************************/
#define SAM_PDCA_CHAN_OFFSET(n) ((n) << 6)
#define SAM_PDCA_CHAN0_OFFSET 0x0000
@@ -54,7 +54,8 @@
#define SAM_PDCA_CHAN14_OFFSET 0x0380
#define SAM_PDCA_CHAN15_OFFSET 0x03c0
/* PDCA register offsets ****************************************************************/
/* PDCA register offsets ****************************************************/
/* Channel register offsets */
#define SAM_PDCA_MAR_OFFSET 0x0000 /* Memory Address Register */
@@ -74,7 +75,8 @@
#define SAM_PDCA_VERSION_OFFSET 0x834 /* Version Register */
/* PDCA channel addresses ***************************************************************/
/* PDCA channel addresses ***************************************************/
/* Channel register base addresses */
#define SAM_PDCA_CHAN(n) (SAM_PDCA_BASE+SAM_PDCA_CHAN_OFFSET(n))
@@ -95,7 +97,8 @@
#define SAM_PDCA_CHAN14 (SAM_PDCA_BASE+SAM_PDCA_CHAN14_OFFSET)
#define SAM_PDCA_CHAN15 (SAM_PDCA_BASE+SAM_PDCA_CHAN15_OFFSET)
/* PDCA register addresses **************************************************************/
/* PDCA register addresses **************************************************/
/* Channel register addresses */
#define SAM_PDCA_MAR(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_MAR_OFFSET)
@@ -115,7 +118,7 @@
#define SAM_PDCA_VERSION (SAM_PDCA_BASE+SAM_PDCA_VERSION_OFFSET)
/* PDCA register bit definitions ********************************************************/
/* PDCA register bit definitions ********************************************/
/* Memory Address Register (32-bit address) */
@@ -125,7 +128,7 @@
/* Transfer Counter Register */
#define PDCA_TCR_MASK 0xffff /* Bits 0-15: Transfer Counter Value
#define PDCA_TCR_MASK 0xffff /* Bits 0-15: Transfer Counter Value */
/* Memory Address Reload Register (32-bit address) */
@@ -158,7 +161,9 @@
#define PDCA_IER_
/* Interrupt Disable Register */
/* Interrupt Mask Register */
/* Interrupt Status Register */
#define PDCA_INT_RCZ (1 << 2) /* Bit 0: Reload Counter Zero */
@@ -174,16 +179,16 @@
#define PDCA_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
#define PDCA_VARIANT_MASK (15 << PDCA_VARIANT_SHIFT)
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PDCA_H */
arch/arm/src/sam34/hardware/sam4l_picouart.h
+17 -16
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_picouart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PICOUART_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PICOUART_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* PICOUART register offsets ************************************************************/
/* PICOUART register offsets ************************************************/
#define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */
#define SAM_PICOUART_CFG_OFFSET 0x0004 /* Configuration Register */
@@ -42,7 +42,7 @@
#define SAM_PICOUART_RHR_OFFSET 0x000c /* Receive Holding Register */
#define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */
/* PICOUART register addresses **********************************************************/
/* PICOUART register addresses **********************************************/
#define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */
#define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */
@@ -55,7 +55,7 @@
#define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */
#define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */
/* PICOUART register bit definitions ****************************************************/
/* PICOUART register bit definitions ****************************************/
/* Control Register */
@@ -70,6 +70,7 @@
# define PICOUART_CFG_SOURCE_WESB (1 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on start bit detection */
# define PICOUART_CFG_SOURCE_WEFF (2 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on full frame reception */
# define PICOUART_CFG_SOURCE_WECH (3 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on character recognition */
#define PICOUART_CFG_ACTION (1 << 0) /* Bit 0: Action to perform */
#define PICOUART_CFG_MATCH_SHIFT (8) /* Bit 8-15: Data Match */
#define PICOUART_CFG_MATCH_SHIFT (8) /* Bit 8-15: Data Match */
@@ -91,16 +92,16 @@
#define PICOUART_VARIANT_SHIFT (16) /* Bits 16-18: Reserved */
#define PICOUART_VARIANT_MASK (7 << PICOUART_VARIANT_SHIFT)
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PICOUART_H */
arch/arm/src/sam34/hardware/sam4l_pinmap.h
+24 -23
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,40 +16,41 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam_gpio.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file. For example, if
* SPI MSIO connects vis PA21 on some board, then the following definition should
* appear in the board.h header file for that board:
* Alternative pin selections are provided with a numeric suffix like _1, _2,
* etc. Drivers, however, will use the pin selection without the numeric
* suffix. Additional definitions are required in the board.h file. For
* example, if SPI MSIO connects vis PA21 on some board, then the following
* definition should appear in the board.h header file for that board:
*
* #define GPIO_SPI_MISO GPIO_SPI_MISO_1
*
* The driver will then automatically configure PA21 as the SPI MISO pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file.
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as
* frequency, open-drain/push-pull, and pull-up/down! Just the basics are
* defined for most pins in this file.
*/
/* Audio Bitstream DAC */
@@ -528,19 +529,19 @@
#define GPIO_USBC_DM (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN25)
#define GPIO_USBC_DP (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN26)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -551,9 +552,9 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
arch/arm/src/sam34/hardware/sam4l_pm.h
+21 -16
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_pm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PM_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PM_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register offsets *****************************************************************/
/* Register offsets *********************************************************/
#define SAM_PM_MCCTRL_OFFSET 0x0000 /* Main Clock Control Register */
#define SAM_PM_CPUSEL_OFFSET 0x0004 /* CPU Clock Select Register */
@@ -66,7 +66,7 @@
#define SAM_PM_CONFIG_OFFSET 0x03f8 /* Configuration Register */
#define SAM_PM_VERSION_OFFSET 0x03fc /* Version Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define SAM_PM_MCCTRL (SAM_PM_BASE+SAM_PM_MCCTRL_OFFSET)
#define SAM_PM_CPUSEL (SAM_PM_BASE+SAM_PM_CPUSEL_OFFSET)
@@ -98,7 +98,7 @@
#define SAM_PM_CONFIG (SAM_PM_BASE+SAM_PM_CONFIG_OFFSET)
#define SAM_PM_VERSION (SAM_PM_BASE+SAM_PM_VERSION_OFFSET)
/* Register Bit-field Definitions ***************************************************/
/* Register Bit-field Definitions *******************************************/
/* Main Clock Control Register Bit-field Definitions */
@@ -231,10 +231,15 @@
# define PM_UNLOCK_KEY(n) ((n) << PM_UNLOCK_KEY_SHIFT)
/* Interrupt Enable Register Bit-field Definitions */
/* Interrupt Disable Register Bit-field Definitions */
/* Interrupt Mask Register Bit-field Definitions */
/* Interrupt Status Register Bit-field Definitions */
/* Interrupt Clear Register Bit-field Definitions */
/* Status Register Register */
#define PM_INT_CFD (1 << 0) /* Bit 0: CFD */
@@ -318,16 +323,16 @@
#define PM_VERSION_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
#define PM_VERSION_VARIANT_MASK (15 << PM_VERSION_VARIANT_SHIFT)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PM_H */
arch/arm/src/sam34/hardware/sam4l_scif.h
+37 -17
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_scif.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_SCIF_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_SCIF_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* SCIF register offsets ****************************************************************/
/* SCIF register offsets ****************************************************/
#define SAM_SCIF_IER_OFFSET 0x0000 /* Interrupt Enable Register */
#define SAM_SCIF_IDR_OFFSET 0x0004 /* Interrupt Disable Register */
@@ -83,7 +83,7 @@
#define SAM_SCIF_GCLKVERSION_OFFSET 0x03f8 /* Generic Clock Version Register */
#define SAM_SCIF_VERSION_OFFSET 0x03fc /* SCIF Version Register */
/* SCIF register addresses **************************************************************/
/* SCIF register addresses **************************************************/
#define SAM_SCIF_IER (SAM_SCIF_BASE+SAM_SCIF_IER_OFFSET)
#define SAM_SCIF_IDR (SAM_SCIF_BASE+SAM_SCIF_IDR_OFFSET)
@@ -132,13 +132,18 @@
#define SAM_SCIF_GCLKVERSION (SAM_SCIF_BASE+SAM_SCIF_GCLKVERSION_OFFSET)
#define SAM_SCIF_VERSION (SAM_SCIF_BASE+SAM_SCIF_VERSION_OFFSET)
/* SCIF register bit definitions ********************************************************/
/* SCIF register bit definitions ********************************************/
/* Interrupt Enable Register */
/* Interrupt Disable Register */
/* Interrupt Mask Register */
/* Interrupt Status Register */
/* Interrupt Clear Register */
/* Power and Clocks Status Register */
#define SCIF_INT_OSC0RDY (1 << 0) /* Bit 0: OSC0 Ready */
@@ -187,6 +192,7 @@
# define SCIF_OSCCTRL0_STARTUP_512 (13 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 512 4.5 ms */
# define SCIF_OSCCTRL0_STARTUP_1K (14 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 1024 8.9 ms */
# define SCIF_OSCCTRL0_STARTUP_32K2 (15 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 2768 285 ms */
#define SCIF_OSCCTRL0_OSCEN (1 << 16) /* Bit 16: Oscillator Enable */
/* PLL0 Control Register */
@@ -196,11 +202,13 @@
#define SCIF_PLL0_PLLOSC_MASK (3 << SCIF_PLL0_PLLOSC_SHIFT)
# define SCIF_PLL0_PLLOSC_OSC0 (0 << SCIF_PLL0_PLLOSC_SHIFT) /* Output clock from Oscillator0 */
# define SCIF_PLL0_PLLOSC_GCLK9 (1 << SCIF_PLL0_PLLOSC_SHIFT) /* Generic clock 9 */
#define SCIF_PLL0_PLLOPT_SHIFT (3) /* Bits 3-5: PLL Option */
#define SCIF_PLL0_PLLOPT_MASK (7 << SCIF_PLL0_PLLOPT_SHIFT)
# define SCIF_PLL0_PLLOPT_FVO (1 << SCIF_PLL0_PLLOPT_SHIFT) /* Selects the VCO frequency range (fvco) */
# define SCIF_PLL0_PLLOPT_DIV2 (2 << SCIF_PLL0_PLLOPT_SHIFT) /* Divides the output frequency by 2 */
# define SCIF_PLL0_PLLOPT_WBM (4 << SCIF_PLL0_PLLOPT_SHIFT) /* Wide-Bandwidth mode */
#define SCIF_PLL0_PLLDIV_SHIFT (8) /* Bits 8-11: PLL Division Factor */
#define SCIF_PLL0_PLLDIV_MASK (15 << SCIF_PLL0_PLLDIV_SHIFT)
#define SCIF_PLL0_PLLMUL_SHIFT (16) /* Bits 16-19: PLL Multiply Factor */
@@ -209,7 +217,8 @@
#define SCIF_PLL0_PLLCOUNT_MASK (63 << SCIF_PLL0_PLLCOUNT_SHIFT)
# define SCIF_PLL0_PLLCOUNT_MAX (63 << SCIF_PLL0_PLLCOUNT_SHIFT)
/* PLL0 operates in two frequency ranges as determined by SCIF_PLL0_PLLOPT_FVO:
/* PLL0 operates in two frequency ranges as determined by
* SCIF_PLL0_PLLOPT_FVO:
*
* 0: 80MHz < fvco < 180MHz
* 1: 160MHz < fvco < 240MHz
@@ -240,6 +249,7 @@
# define SCIF_DFLL0CONF_RANGE1 (1 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 50-110MHz */
# define SCIF_DFLL0CONF_RANGE2 (2 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 25-55MHz */
# define SCIF_DFLL0CONF_RANGE3 (3 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 20-30MHz */
#define SCIF_DFLL0CONF_FCD (1 << 23) /* Bit 23: Fuse Calibration Done */
#define SCIF_DFLL0CONF_CALIB_SHIFT (24) /* Bits 24-27: Calibration Value */
#define SCIF_DFLL0CONF_CALIB_MASK (15 << SCIF_DFLL0CONF_CALIB_SHIFT)
@@ -311,6 +321,7 @@
# define SCIF_RCFASTCFG_FRANGE_4MHZ (0 << SCIF_RCFASTCFG_FRANGE_SHIFT) /* 4MHz range selected */
# define SCIF_RCFASTCFG_FRANGE_8MHZ (1 << SCIF_RCFASTCFG_FRANGE_SHIFT) /* 8MHz range selected */
# define SCIF_RCFASTCFG_FRANGE_12MHZ (2 << SCIF_RCFASTCFG_FRANGE_SHIFT) /* 12MHz range selected */
#define SCIF_RCFASTCFG_LOCKMARGIN_SHIFT (12) /* Bits 12-15: Accepted Count Error for Lock */
#define SCIF_RCFASTCFG_LOCKMARGIN_MASK (15 << SCIF_RCFASTCFG_LOCKMARGIN_SHIFT)
#define SCIF_RCFASTCFG_CALIB_SHIFT (16) /* Bits 16-22: Oscillator Calibration Value */
@@ -383,18 +394,27 @@
# define SCIF_GCCTRL_OSCSEL_GCLKIN0 (19 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLKIN0 */
# define SCIF_GCCTRL_OSCSEL_GCLKIN1 (20 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLKIN1 */
# define SCIF_GCCTRL_OSCSEL_GCLK11 (21 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLK11 */
#define SCIF_GCCTRL_DIV_SHIFT (16) /* Bits 16-31: Division Factor */
#define SCIF_GCCTRL_DIV_MASK (0xffff << SCIF_GCCTRL_DIV_SHIFT)
# define SCIF_GCCTRL_DIV(n) ((n) << SCIF_GCCTRL_DIV_SHIFT)
/* 4/8/12MHz RC Oscillator Version Register */
/* Generic Clock Prescaler Version Register */
/* PLL Version Register */
/* Oscillator0 Version Register */
/* DFLL Version Register */
/* System RC Oscillator Version Register */
/* 80MHz RC Oscillator Version Register */
/* Generic Clock Version Register */
/* SCIF Version Register */
#define SCIF_VERSION_SHIFT (0) /* Bits 0-11: Version Number */
@@ -402,16 +422,16 @@
#define SCIF_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
#define SCIF_VARIANT_MASK (15 << SCIF_VARIANT_SHIFT)
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_SCIF_H */
arch/arm/src/sam34/hardware/sam4l_usart.h
+27 -17
View File
@@ -1,4 +1,4 @@
/************************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_usart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_UART_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_UART_H
/************************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************************/
****************************************************************************/
/* USART register offsets ***********************************************************************/
/* USART register offsets ***************************************************/
#define SAM_UART_CR_OFFSET 0x0000 /* Control Register */
#define SAM_UART_MR_OFFSET 0x0004 /* Mode Register */
@@ -63,7 +63,7 @@
#define SAM_UART_VERSION_OFFSET 0x00fc /* Version Register */
/* 0x0100-0x0124: PDC Area */
/* USART register addresses *********************************************************************/
/* USART register addresses *************************************************/
#define SAM_USART_CR(n) (SAM_USARTN_BASE(n)+SAM_UART_CR_OFFSET)
#define SAM_USART_MR(n) (SAM_USARTN_BASE(n)+SAM_UART_MR_OFFSET)
@@ -175,7 +175,7 @@
#define SAM_USART3_WPSR (SAM_USART3_BASE+SAM_UART_WPSR_OFFSET)
#define SAM_USART3_VERSION (SAM_USART3_BASE+SAM_UART_VERSION_OFFSET)
/* USART register bit definitions ***************************************************************/
/* USART register bit definitions *******************************************/
/* USART Control Register */
@@ -214,17 +214,20 @@
# define UART_MR_MODE_IRDA (8 << UART_MR_MODE_SHIFT) /* IrDA */
# define UART_MR_MODE_SPIMSTR (14 << UART_MR_MODE_SHIFT) /* SPI Master */
# define UART_MR_MODE_SPISLV (15 << UART_MR_MODE_SHIFT) /* SPI Slave */
#define UART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection */
#define UART_MR_USCLKS_MASK (3 << UART_MR_USCLKS_SHIFT)
# define UART_MR_USCLKS_USART (0 << UART_MR_USCLKS_SHIFT) /* CLK_USART */
# define UART_MR_USCLKS_USARTDIV (0 << UART_MR_USCLKS_SHIFT) /* CLK_USART/DIV(1) */
# define UART_MR_USCLKS_CLK (0 << UART_MR_USCLKS_SHIFT) /* CLK */
#define UART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length */
#define UART_MR_CHRL_MASK (3 << UART_MR_CHRL_SHIFT)
# define UART_MR_CHRL_5BITS (0 << UART_MR_CHRL_SHIFT) /* 5 bits */
# define UART_MR_CHRL_6BITS (1 << UART_MR_CHRL_SHIFT) /* 6 bits */
# define UART_MR_CHRL_7BITS (2 << UART_MR_CHRL_SHIFT) /* 7 bits */
# define UART_MR_CHRL_8BITS (3 << UART_MR_CHRL_SHIFT) /* 8 bits */
#define UART_MR_SYNC (1 << 8) /* Bit 8: Synchronous Mode Select */
#define UART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase */
#define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type */
@@ -235,17 +238,20 @@
# define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 */
# define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity */
# define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode */
#define UART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits */
#define UART_MR_NBSTOP_MASK (3 << UART_MR_NBSTOP_SHIFT)
# define UART_MR_NBSTOP_1 (0 << UART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */
# define UART_MR_NBSTOP_1p5 (1 << UART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */
# define UART_MR_NBSTOP_2 (2 << UART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */
#define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode */
#define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT)
# define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */
# define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */
# define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */
# define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */
#define UART_MR_MSBF (1 << 16) /* Bit 16: Most Significant Bit first */
#define UART_MR_CPOL (1 << 16) /* Bit 16: SPI Clock Polarity */
#define UART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length */
@@ -262,7 +268,8 @@
#define UART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode */
#define UART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector */
/* USART Interrupt Enable Register, USART Interrupt Disable Register, USART Interrupt Mask
/* USART Interrupt Enable Register
* USART Interrupt Disable Register, USART Interrupt Mask
* Register, and USART Status Register common bit field definitions.
*
* - Bits that provide interrupts with UART_INT_
@@ -357,6 +364,7 @@
# define UART_MAN_TXPP_ALLZERO (1 << UART_MAN_TXPP_SHIFT) /* ALL_ZERO */
# define UART_MAN_TXPP_ZEROONE (2 << UART_MAN_TXPP_SHIFT) /* ZERO_ONE */
# define UART_MAN_TXPP_ONEZERO (3 << UART_MAN_TXPP_SHIFT) /* ONE_ZERO */
#define UART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity */
#define UART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length */
#define UART_MAN_RXPL_MASK (15 << UART_MAN_RXPL_SHIFT)
@@ -366,6 +374,7 @@
# define UART_MAN_RXPP_ALLZERO (1 << UART_MAN_RXPP_SHIFT) /* ALL_ZERO */
# define UART_MAN_RXPP_ZEROONE (2 << UART_MAN_RXPP_SHIFT) /* ZERO_ONE */
# define UART_MAN_RXPP_ONEZERO (3 << UART_MAN_RXPP_SHIFT) /* ONE_ZERO */
#define UART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity */
#define UART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation */
@@ -376,6 +385,7 @@
# define UART_LINMR_NACT_PUBLISH (0 << UART_LINMR_NACT_SHIFT) /* USART transmits response */
# define UART_LINMR_NACT_SUBSCRIBE (1 << UART_LINMR_NACT_SHIFT) /* USART receives response */
# define UART_LINMR_NACT_IGNORE (2 << UART_LINMR_NACT_SHIFT) /* USART does neither */
#define UART_LINMR_PARDIS (1 << 2) /* Bit 0: Parity Disable */
#define UART_LINMR_CHKDIS (1 << 3) /* Bit 0: Checksum Disable */
#define UART_LINMR_CHKTYP (1 << 4) /* Bit 0: Checksum Type */
@@ -417,16 +427,16 @@
#define UART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved */
#define UART_VERSION_MFN_MASK (7 << UART_VERSION_MFN_SHIFT)
/************************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************************/
****************************************************************************/
/************************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************************/
****************************************************************************/
/************************************************************************************************
* Public Functions
************************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_UART_H */
arch/arm/src/sam34/hardware/sam4l_wdt.h
+20 -16
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_wdt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_WDT_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_WDT_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* WDT register offsets ****************************************************************/
/* WDT register offsets *****************************************************/
#define SAM_WDT_CTRL_OFFSET 0x0000 /* Control Register */
#define SAM_WDT_CLR_OFFSET 0x0004 /* Clear Register */
@@ -46,7 +46,7 @@
#define SAM_WDT_ICR_OFFSET 0x001c /* Interrupt Clear Register */
#define SAM_WDT_VERSION_OFFSET 0x03fc /* Version Register */
/* WDT register addresses **************************************************************/
/* WDT register addresses ***************************************************/
#define SAM_WDT_CTRL (SAM_WDT_BASE+SAM_WDT_CTRL_OFFSET)
#define SAM_WDT_CLR (SAM_WDT_BASE+SAM_WDT_CLR_OFFSET)
@@ -58,7 +58,7 @@
#define SAM_WDT_ICR (SAM_WDT_BASE+SAM_WDT_ICR_OFFSET)
#define SAM_WDT_VERSION (SAM_WDT_BASE+SAM_WDT_VERSION_OFFSET)
/* WDT register bit definitions ********************************************************/
/* WDT register bit definitions *********************************************/
/* Control Register */
@@ -93,9 +93,13 @@
#define WDT_SR_CLEARED (1 << 1) /* Bit 1: WDT Counter Cleared */
/* Interrupt Enable Register */
/* Interrupt Disable Register */
/* Interrupt Mask Register */
/* Interrupt Status Register */
/* Interrupt Clear Register */
#define WDT_WINT (1 << 2) /* Bit 2: WINT */
@@ -107,16 +111,16 @@
#define WDT_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
#define WDT_VARIANT_MASK (15 << WDT_VARIANT_SHIFT)
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_WDT_H */
arch/arm/src/sam34/hardware/sam4s_memorymap.h
+18 -13
View File
@@ -1,4 +1,4 @@
/************************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4s_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_MEMORYMAP_H
/************************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************************/
****************************************************************************/
/* Address regions */
@@ -47,11 +47,13 @@
#define SAM_INTFLASH_BASE 0x00400000 /* 0x00400000-0x007fffff: Internal FLASH */
#define SAM_INTROM_BASE 0x00800000 /* 0x00180000-0x00bfffff: Internal ROM */
/* 0x00c00000-0x1fffffff: Reserved */
/* Internal SRAM memory region */
#define SAM_INTSRAM0_BASE 0x20000000 /* For SAM3U compatibility */
#define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32MB bit-band region */
/* 0x24000000-0x3fffffff: Undefined */
/* Peripherals address region */
#define SAM_HSMCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */
@@ -89,6 +91,7 @@
/* 0x40100000-0x4002ffff: Reserved */
#define SAM_BBPERIPH_BASE 0x42000000 /* 0x42000000-0x43ffffff: 32MB bit-band region */
/* 0x44000000-0x5fffffff: Reserved */
/* System Controller Register Blocks: 0x400e0000-0x4007ffff */
#define SAM_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */
@@ -112,6 +115,7 @@
#define SAM_RTC_BASE 0x400e1460 /* 0x400e1460-0x400e148f: Real Time Clock */
#define SAM_GPBR_BASE 0x400e1490 /* 0x400e1490-0x400e15ff: GPBR */
/* 0x400e1600-0x4007ffff: Reserved */
/* External RAM memory region */
#define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */
@@ -121,21 +125,22 @@
# define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */
# define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */
/* 0x64000000-0x9fffffff: Reserved */
/* System memory region */
#define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */
#define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */
/************************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************************/
****************************************************************************/
/************************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************************/
****************************************************************************/
/************************************************************************************************
* Public Functions
************************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_MEMORYMAP_H */
arch/arm/src/sam34/hardware/sam4s_pinmap.h
+26 -24
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4s_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,42 +16,44 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PINMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PINMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam_gpio.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* GPIO pin definitions *****************************************************/
/* GPIO pin definitions *************************************************************/
/* Alternate Pin Functions.
*
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file. For example, if we
* wanted the programmable clock output PCK0 on PA6, then the following definition
* should appear in the board.h header file for that board:
* Alternative pin selections are provided with a numeric suffix like _1, _2,
* etc. Drivers, however, will use the pin selection without the numeric
* suffix. Additional definitions are required in the board.h file. For
* example, if we wanted the programmable clock output PCK0 on PA6, then the
* following definition should appear in the board.h header file for that
* board:
*
* #define GPIO_PCK0 GPIO_PCK0_1
*
* The driver will then automatically configure PA6 as the PCK0 pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file.
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as
* frequency, open-drain/push-pull, and pull-up/down! Just the basics are
* defined for most pins in this file.
*/
/* 12-bit Analog-to-Digital Converter (ADC) */
@@ -263,19 +265,19 @@
#define GPIO_USART1_SCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23)
#define GPIO_USART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22)
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -286,9 +288,9 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
arch/arm/src/sam34/hardware/sam4s_pio.h
+20 -17
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam4s_pio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PIO_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PIO_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* PIO register offsets *****************************************************************/
/* PIO register offsets *****************************************************/
#define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */
#define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */
@@ -105,7 +105,7 @@
#define SAM_PIO_PCRHR_OFFSET 0x0164 /* Parallel Capture Reception Holding Register */
/* 0x0168-0x018c: Reserved for PDC registers */
/* PIO register addresses ***************************************************************/
/* PIO register addresses ***************************************************/
#define PIOA (0)
#define PIOB (1)
@@ -332,7 +332,7 @@
#define SAM_PIOC_PCISR (SAM_PIOC_BASE+SAM_PIO_PCISR_OFFSET)
#define SAM_PIOC_PCRHR (SAM_PIOC_BASE+SAM_PIO_PCRHR_OFFSET
/* PIO register bit definitions *********************************************************/
/* PIO register bit definitions *********************************************/
/* Common bit definitions for ALMOST all IO registers (exceptions follow) */
@@ -359,27 +359,30 @@
# define PIO_PCMR_DSIZE_BYTE (0 << PIO_PCMR_DSIZE_SHIFT) /* 8-bit data in PIO_PCRHR */
# define PIO_PCMR_DSIZE_HWORD (1 << PIO_PCMR_DSIZE_SHIFT) /* 16-bit data in PIO_PCRHR */
# define PIO_PCMR_DSIZE_WORD (2 << PIO_PCMR_DSIZE_SHIFT) /* 32-bit data in PIO_PCRHR */
#define PIO_PCMR_ALWYS (1 << 9) /* Bit 9: Parallel Capture Mode Always Sampling */
#define PIO_PCMR_HALFS (1 << 10) /* Bit 10: Parallel Capture Mode Half Sampling */
#define PIO_PCMR_FRSTS (1 << 11) /* Bit 11: Parallel Capture Mode First Sample */
/* PIO Parallel Capture Interrupt Enable, Disable, Mask, and Status Registers */
/* PIO Parallel Capture Interrupt Enable, Disable, Mask,
* and Status Registers
*/
#define PIOC_PCINT_DRDY (1 << 0) /* Bit 0: Parallel Capture Mode Data Ready Interrupt Enable */
#define PIOC_PCINT_OVRE (1 << 1) /* Bit 1: Parallel Capture Mode Overrun Error Interrupt Enable */
#define PIOC_PCINT_ENDRX (1 << 2) /* Bit 2: End of Reception Transfer Interrupt Enable */
#define PIOC_PCINT_RXBUFF (1 << 3) /* Bit 3: Reception Buffer Full Interrupt Enable */
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PIO_H */
arch/arm/src/sam34/hardware/sam_acc.h
+23 -17
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_acc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ACC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ACC_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* ACC register offsets *****************************************************************/
/* ACC register offsets *****************************************************/
#define SAM_ACC_CR_OFFSET 0x0000 /* Control Register */
#define SAM_ACC_MR_OFFSET 0x0004 /* Mode Register */
@@ -46,7 +46,7 @@
#define SAM_ACC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
#define SAM_ACC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
/* ACC register addresses **************************************************************/
/* ACC register addresses ***************************************************/
#define SAM_ACC_CR (SAM_ACC_BASE+SAM_ACC_CR_OFFSET)
#define SAM_ACC_MR (SAM_ACC_BASE+SAM_ACC_MR_OFFSET)
@@ -58,7 +58,7 @@
#define SAM_ACC_WPMR (SAM_ACC_BASE+SAM_ACC_WPMR_OFFSET)
#define SAM_ACC_WPSR (SAM_ACC_BASE+SAM_ACC_WPSR_OFFSET
/* ACC register bit definitions ********************************************************/
/* ACC register bit definitions *********************************************/
/* Control Register */
@@ -76,9 +76,11 @@
# define ACC_MR_SELMINUS_AD1 (5 << ACC_MR_SELMINUS_SHIFT) /* Select AD1 */
# define ACC_MR_SELMINUS_AD2 (6 << ACC_MR_SELMINUS_SHIFT) /* Select AD2 */
# define ACC_MR_SELMINUS_AD3 (7 << ACC_MR_SELMINUS_SHIFT) /* Select AD3 */
#define ACC_MR_SELPLUS_SHIFT (4) /* Bits 4-6: Selection for plus comparator input */
#define ACC_MR_SELPLUS_MASK (7 << ACC_MR_SELPLUS_SHIFT)
# define ACC_MR_SELPLUS_AD(n) ((uint32_t)(n) << ACC_MR_SELPLUS_SHIFT) /* Select and, n=0-7 */
# define ACC_MR_SELPLUS_AD0 (0 << ACC_MR_SELPLUS_SHIFT) /* Select AD0 */
# define ACC_MR_SELPLUS_AD1 (1 << ACC_MR_SELPLUS_SHIFT) /* Select AD1 */
# define ACC_MR_SELPLUS_AD2 (2 << ACC_MR_SELPLUS_SHIFT) /* Select AD2 */
@@ -87,17 +89,21 @@
# define ACC_MR_SELPLUS_AD5 (5 << ACC_MR_SELPLUS_SHIFT) /* Select AD5 */
# define ACC_MR_SELPLUS_AD6 (6 << ACC_MR_SELPLUS_SHIFT) /* Select AD6 */
# define ACC_MR_SELPLUS_AD7 (7 << ACC_MR_SELPLUS_SHIFT) /* Select AD7 */
#define ACC_MR_ACEN (1 << 8) /* Bit 8: Analog comparator enable */
#define ACC_MR_EDGETYP_SHIFT (9) /* Bits 9-10: Edge type */
#define ACC_MR_EDGETYP_MASK (3 << ACC_MR_EDGETYP_SHIFT)
# define ACC_MR_EDGETYP_RISING (0 << ACC_MR_EDGETYP_SHIFT) /* Only rising edge of comparator output */
# define ACC_MR_EDGETYP_FALLING (1 << ACC_MR_EDGETYP_SHIFT) /* Falling edge of comparator output */
# define ACC_MR_EDGETYP_ANY (2 << ACC_MR_EDGETYP_SHIFT) /* Any edge of comparator output */
#define ACC_MR_INV (1 << 12) /* Bit 12: Invert comparator output */
#define ACC_MR_SELFS (1 << 13) /* Bit 13: Selection of fault source */
#define ACC_MR_FE (1 << 14) /* Bit 14: Fault enable */
/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status */
/* Interrupt Enable, Interrupt Disable, Interrupt Mask,
* and Interrupt Status
*/
#define ACC_INT_CE (1 << 0) /* Bit 0: Comparison edge interrupt */
@@ -123,16 +129,16 @@
#define ACC_WPSR_WPROTERR (1 << 0) /* Bit 0: Write protection error */
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ACC_H */
arch/arm/src/sam34/hardware/sam_adc.h
+31 -24
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_adc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ADC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ADC_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* General definitions ******************************************************************/
****************************************************************************/
/* General definitions ******************************************************/
#define SAM_ADC_NCHANNELS 8 /* 8 ADC Channels */
/* ADC register offsets *****************************************************************/
/* ADC register offsets *****************************************************/
#define SAM_ADC_CR_OFFSET 0x00 /* Control Register (Both) */
#define SAM_ADC_MR_OFFSET 0x04 /* Mode Register (Both) */
@@ -63,7 +64,7 @@
#define SAM_ADC12B_ACR_OFFSET 0x64 /* Analog Control Register (ADC12B only) */
#define SAM_ADC12B_EMR_OFFSET 0x68 /* Extended Mode Register (ADC12B only) */
/* ADC register addresses ***************************************************************/
/* ADC register addresses ***************************************************/
#define SAM_ADC12B_CR (SAM_ADC12B_BASE+SAM_ADC_CR_OFFSET)
#define SAM_ADC12B_MR (SAM_ADC12B_BASE+SAM_ADC_MR_OFFSET)
@@ -107,14 +108,18 @@
# define SAM_ADC_CDR6 (SAM_ADC_BASE+SAM_ADC_CDR6_OFFSET)
# define SAM_ADC_CDR7 (SAM_ADC_BASE+SAM_ADC_CDR7_OFFSET)
/* ADC register bit definitions *********************************************************/
/* ADC register bit definitions *********************************************/
/* ADC12B Control Register and ADC(10B) Control Register common bit-field definitions */
/* ADC12B Control Register and ADC(10B) Control Register common bit-field
* definitions
*/
#define ADC_CR_SWRST (1 << 0) /* Bit 0: Software Reset */
#define ADC_CR_START (1 << 1) /* Bit 1: Start Conversion */
/* ADC12B Mode Register and ADC(10B) Mode Register common bit-field definitions */
/* ADC12B Mode Register and ADC(10B) Mode Register common bit-field
* definitions
*/
#define ADC_MR_TRGEN (1 << 0) /* Bit 0: Trigger Enable */
#define ADC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */
@@ -135,8 +140,9 @@
#define ADC_MR_SHTIM_MASK (15 << ADC_MR_SHTIM_SHIFT)
# define ADC_MR_SHTIM(n) ((uint32_t)(n) << ADC_MR_SHTIM_SHIFT)
/* ADC12B Channel Enable Register, ADC12B Channel Disable Register, ADC12B Channel
* Status Register, ADC(10B) Channel Enable Register, ADC(10B) Channel Disable Register,
/* ADC12B Channel Enable Register, ADC12B Channel Disable Register,
* ADC12B Channel Status Register, ADC(10B) Channel Enable Register,
* ADC(10B) Channel Disable Register,
* and ADC(10B) Channel Status Register common bit-field definitions
*/
@@ -168,9 +174,10 @@
#define ADC12B_EMR_OFFMSTIME_MASK (0xff << ADC12B_EMR_OFFMSTIME_SHIFT)
# define ADC12B_EMR_OFFMSTIME(n) ((uint32_t)(n) << ADC12B_EMR_OFFMSTIME_SHIFT)
/* ADC12B Status Register , ADC12B Interrupt Enable Register, ADC12B Interrupt
* Disable Register, ADC12B Interrupt Mask Register, ADC(10B) Status Register,
* ADC(10B) Interrupt Enable Register, ADC(10B) Interrupt Disable Register, and
/* ADC12B Status Register , ADC12B Interrupt Enable Register,
* ADC12B Interrupt Disable Register, ADC12B Interrupt Mask Register,
* ADC(10B) Status Register, ADC(10B) Interrupt Enable Register,
* ADC(10B) Interrupt Disable Register, and
* ADC(10B) Interrupt Mask Register common bit-field definitions
*/
@@ -217,16 +224,16 @@
#define ADC10B_CDR_DATA_SHIFT (0) /* Bits 0-9: Converted Data */
#define ADC10B_CDR_DATA_MASK (0x1ff << ADC10B_CDR_DATA_SHIFT)
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ADC_H */
arch/arm/src/sam34/hardware/sam_aes.h
+25 -17
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_aes.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AES_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AES_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* AES register offsets *****************************************************************/
/* AES register offsets *****************************************************/
#define SAM_AES_CR_OFFSET 0x0000 /* Control Register */
#define SAM_AES_MR_OFFSET 0x0004 /* Mode Register */
@@ -65,7 +65,7 @@
#define SAM_AES_IVR3_OFFSET 0x006c /* Initialization Vector Register 3 */
/* 0x0070-0x00fc: Reserved */
/* AES register addresses ***************************************************************/
/* AES register addresses ***************************************************/
#define SAM_AES_CR (SAM_AES_BASE+SAM_AES_CR_OFFSET)
#define SAM_AES_MR (SAM_AES_BASE+SAM_AES_MR_OFFSET)
@@ -94,7 +94,7 @@
#define SAM_AES_IVR2 (SAM_AES_BASE+SAM_AES_IVR2_OFFSET)
#define SAM_AES_IVR3 (SAM_AES_BASE+SAM_AES_IVR3_OFFSET)
/* AES register bit definitions ********************************************************/
/* AES register bit definitions *********************************************/
/* Control Register */
@@ -113,11 +113,13 @@
# define AES_MR_SMOD_MANUAL (0 << AES_MR_SMOD_SHIFT) /* Manual Mode */
# define AES_MR_SMOD_AUTO (1 << AES_MR_SMOD_SHIFT) /* Auto Mode */
# define AES_MR_SMOD_IDATR0 (2 << AES_MR_SMOD_SHIFT) /* AES_IDATAR0 access only Auto Mode */
#define AES_MR_KEYSIZE_SHIFT (10) /* Bits 10-11: Key Size */
#define AES_MR_KEYSIZE_MASK (2 << AES_MR_KEYSIZE_SHIFT)
# define AES_MR_KEYSIZE_AES128 (0 << AES_MR_KEYSIZE_SHIFT) /* AES Key Size is 128 bits */
# define AES_MR_KEYSIZE_AES192 (1 << AES_MR_KEYSIZE_SHIFT) /* AES Key Size is 192 bits */
# define AES_MR_KEYSIZE_AES256 (2 << AES_MR_KEYSIZE_SHIFT) /* AES Key Size is 256 bits */
#define AES_MR_OPMOD_SHIFT (12) /* Bits 12-14: Operation Mode */
#define AES_MR_OPMOD_MASK (7 << AES_MR_OPMOD_SHIFT)
# define AES_MR_OPMOD_ECB (0 << AES_MR_OPMOD_SHIFT) /* ECB: Electronic Code Book mode */
@@ -125,6 +127,7 @@
# define AES_MR_OPMOD_OFB (2 << AES_MR_OPMOD_SHIFT) /* OFB: Output Feedback mode */
# define AES_MR_OPMOD_CFB (3 << AES_MR_OPMOD_SHIFT) /* CFB: Cipher Feedback mode */
# define AES_MR_OPMOD_CTR (4 << AES_MR_OPMOD_SHIFT) /* CTR: Counter mode (16-bit counter) */
#define AES_MR_LOD (1 << 15) /* Bit 15: Last Output Data Mode */
#define AES_MR_CFBS_SHIFT (16) /* Bits 16-18: Cipher Feedback Data Size */
#define AES_MR_CFBS_MASK (7 << AES_MR_CFBS_SHIFT)
@@ -133,11 +136,14 @@
# define AES_MR_CFBS_32BIT (2 << AES_MR_CFBS_SHIFT) /* 32-bit */
# define AES_MR_CFBS_16BIT (3 << AES_MR_CFBS_SHIFT) /* 16-bit */
# define AES_MR_CFBS_8BIT (4 << AES_MR_CFBS_SHIFT) /* 8-bit */
#define AES_MR_CKEY_SHIFT (20) /* Bits 20-23: Key */
#define AES_MR_CKEY_MASK (15 << AES_MR_CKEY_SHIFT)
# define AES_MR_CKEY (14 << AES_MR_CKEY_SHIFT)
/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status Register */
/* Interrupt Enable, Interrupt Disable, Interrupt Mask,
* and Interrupt Status Register
*/
#define AES_INT_DATRDY (1 << 0) /* Bit 0: Data Ready Interrupt */
#define AES_INT_URAD (1 << 8) /* Bit 8: Unspecified Register Access Detection Interrupt */
@@ -154,19 +160,21 @@
# define AES_ISR_URAT_WORRDACC (5 << AES_ISR_URAT_SHIFT) /* WRONLY register read access */
/* Key Word Register 0-7 (32-bit value) */
/* Input Data Register 0-7 (32-bit value) */
/* Initialization Vector Register 0-7 (32-bit value) */
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AES_H */
arch/arm/src/sam34/hardware/sam_afec.h
+29 -19
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_afec.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AFEC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AFEC_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* General definitions ******************************************************************/
****************************************************************************/
/* General definitions ******************************************************/
#define SAM_ADC_NCHANNELS 16 /* 16 ADC Channels */
/* AFEC register offsets ****************************************************************/
/* AFEC register offsets ****************************************************/
#define SAM_AFEC_CR_OFFSET 0x0000 /* Control Register */
#define SAM_AFEC_MR_OFFSET 0x0004 /* Mode Register */
@@ -73,7 +74,7 @@
/* 0x0fc Reserved */
/* 0x0100-0x0124 Reserved for PDC */
/* AFEC register addresses **************************************************************/
/* AFEC register addresses **************************************************/
#define SAM_AFEC0_CR (SAM_AFEC0_BASE+SAM_AFEC_CR_OFFSET)
#define SAM_AFEC0_MR (SAM_AFEC0_BASE+SAM_AFEC_MR_OFFSET)
@@ -129,7 +130,7 @@
#define SAM_AFEC1_WPMR (SAM_AFEC1_BASE+SAM_AFEC_WPMR_OFFSET)
#define SAM_AFEC1_WPSR (SAM_AFEC1_BASE+SAM_AFEC_WPSR_OFFSET)
/* AFEC register bit definitions *******************************************************/
/* AFEC register bit definitions ********************************************/
/* Control Register */
@@ -148,6 +149,7 @@
# define AFEC_MR_TRGSEL_TIOA2 (3 << AFEC_MR_TRGSEL_SHIFT) /* TIOA2 */
# define AFEC_MR_TRGSEL_PWM0 (4 << AFEC_MR_TRGSEL_SHIFT) /* PWM Event Line 0 */
# define AFEC_MR_TRGSEL_PWM1 (5 << AFEC_MR_TRGSEL_SHIFT) /* PWM Event Line 1 */
#define AFEC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */
#define AFEC_MR_FWUP (1 << 6) /* Bit 6: Fast Wake Up */
#define AFEC_MR_FREERUN (1 << 7) /* Bit 7: Free Run Mode */
@@ -172,12 +174,14 @@
# define AFEC_MR_STARTUP_832 (13 << AFEC_MR_STARTUP_SHIFT) /* 832 periods of ADCClock */
# define AFEC_MR_STARTUP_896 (14 << AFEC_MR_STARTUP_SHIFT) /* 896 periods of ADCClock */
# define AFEC_MR_STARTUP_960 (15 << AFEC_MR_STARTUP_SHIFT) /* 960 periods of ADCClock */
#define AFEC_MR_SETTLING_SHIFT (20) /* Bits 20-21: Analog Settling Time */
#define AFEC_MR_SETTLING_MASK (15 << AFEC_MR_SETTLING_SHIFT)
# define AFEC_MR_SETTLING_3 (0 << AFEC_MR_SETTLING_SHIFT) /* 3 periods of ADCClock */
# define AFEC_MR_SETTLING_5 (1 << AFEC_MR_SETTLING_SHIFT) /* 5 periods of ADCClock */
# define AFEC_MR_SETTLING_9 (2 << AFEC_MR_SETTLING_SHIFT) /* 9 periods of ADCClock */
# define AFEC_MR_SETTLING_17 (3 << AFEC_MR_SETTLING_SHIFT) /* 17 periods of ADCClock */
#define AFEC_MR_ANACH (1 << 23) /* Bit 23: Analog Change */
#define AFEC_MR_TRACKTIM_SHIFT (24) /* Bits 24-27: Tracking Time */
#define AFEC_MR_TRACKTIM_MASK (15 << AFEC_MR_TRACKTIM_SHIFT)
@@ -195,6 +199,7 @@
# define AFEC_EMR_CMPMODE_HIGH (1 << AFEC_EMR_CMPMODE_SHIFT) /* Event when higher than high window threshold */
# define AFEC_EMR_CMPMODE_IN (2 << AFEC_EMR_CMPMODE_SHIFT) /* Event when in comparison window */
# define AFEC_EMR_CMPMODE_OUT (3 << AFEC_EMR_CMPMODE_SHIFT) /* Event when out of comparison window */
#define AFEC_EMR_CMPSEL_SHIFT (3) /* Bit 3-7: Comparison Selected Channel */
#define AFEC_EMR_CMPSEL_MASK (31 << AFEC_EMR_CMPSEL_SHIFT)
# define AFEC_EMR_CMPSEL(n) ((uint32_t)(n) << AFEC_EMR_CMPSEL_SHIFT)
@@ -210,6 +215,7 @@
# define AFEC_EMR_RES_OSR16 (3 << AFEC_EMR_RES_SHIFT) /* 14-bit resolution, AFEC sample rate divided by 16 (averaging) */
# define AFEC_EMR_RES_OSR64 (4 << AFEC_EMR_RES_SHIFT) /* 15-bit resolution, AFEC sample rate divided by 64 (averaging) */
# define AFEC_EMR_RES_OSR256 (5 << AFEC_EMR_RES_SHIFT) /* 16-bit resolution, AFEC sample rate divided by 256 (averaging) */
#define AFEC_EMR_TAG (1 << 24) /* Bit 24: TAG of the AFEC_LDCR register */
#define AFEC_EMR_STM (1 << 25) /* Bit 25: Single Trigger Mode */
@@ -301,7 +307,9 @@
#define AFEC_LCDR_CHANB_SHIFT (24) /* Bits 24-27: Channel number */
#define AFEC_LCDR_CHANB_MASK (15 << AFEC_LCDR_CHANB_SHIFT)
/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status Registers */
/* Interrupt Enable, Interrupt Disable, Interrupt Mask,
* and Interrupt Status Registers
*/
#define AFEC_INT_EOC(n) (1 << (n))
# define AFEC_INT_EOC0 (1 << 0) /* Bit 0: End of Conversion 0 */
@@ -415,7 +423,9 @@
#define AFEC_CGR_GAIN15_MASK (3 << AFEC_CGR_GAIN15_SHIFT)
# define AFEC_CGR_GAIN15(v) ((uint32_t)(v) << AFEC_CGR_GAIN15_SHIFT)
/* Channel Calibration DC Offset Register (Used in Automatic Calibration Procedure) */
/* Channel Calibration DC Offset Register
* (Used in Automatic Calibration Procedure)
*/
#define AFEC_CDOR_OFF(n) (1 << (n))
# define AFEC_CDOR_OFF0 (1 << 0) /* Bit 0: Offset for channel 0 */
@@ -507,16 +517,16 @@
#define AFEC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define AFEC_WPSR_WPVSRC_MASK (0x0000ffff << AFEC_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AFEC_H */
arch/arm/src/sam34/hardware/sam_can.h
+22 -17
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_can.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CAN_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CAN_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
#define SAM_CAN_NMBOXES 8 /* 8 Mailboxes */
#define SAM_CAN_MBOX(n) (n)
@@ -45,7 +45,7 @@
#define SAM_CAN_MBOX6 6
#define SAM_CAN_MBOX7 7
/* CAN register offsets *****************************************************************/
/* CAN register offsets *****************************************************/
#define SAM_CAN_MR_OFFSET 0x0000 /* Mode Register */
#define SAM_CAN_IER_OFFSET 0x0004 /* Interrupt Enable Register */
@@ -58,10 +58,13 @@
#define SAM_CAN_ECR_OFFSET 0x0020 /* Error Counter Register */
#define SAM_CAN_TCR_OFFSET 0x0024 /* Transfer Command Register */
#define SAM_CAN_ACR_OFFSET 0x0028 /* Abort Command Register */
/* 0x002c-0x00e0: Reserved */
#define SAM_CAN_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
#define SAM_CAN_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
/* 0x00eC-0x01fc: Reserved */
/* Mailbox Registers */
#define SAM_CAN_MBOX_OFFSET(n) (0x0200+((n) << 5))
@@ -74,7 +77,7 @@
#define SAM_CAN_MDH_OFFSET 0x0018 /* Mailbox Data High Register */
#define SAM_CAN_MCR_OFFSET 0x001c /* Mailbox Control Register */
/* CAN register addresses ***************************************************************/
/* CAN register addresses ***************************************************/
#define SAM_CAN0_MR (SAM_CAN0_BASE+SAM_CAN_MR_OFFSET)
#define SAM_CAN0_IER (SAM_CAN0_BASE+SAM_CAN_IER_OFFSET)
@@ -128,7 +131,7 @@
#define SAM_CAN1_MDH(n) (SAM_CAN1_MBOX_BASE(n)+SAM_CAN_MDH_OFFSET)
#define SAM_CAN1_MCR(n) (SAM_CAN1_MBOX_BASE(n)+SAM_CAN_MCR_OFFSET)
/* CAN register bit definitions *********************************************************/
/* CAN register bit definitions *********************************************/
/* Mode Register */
@@ -144,6 +147,7 @@
/* Interrupt Enable, Interrupt Disable, Interrupt Mask and Status Register */
#define CAN_INT_MB(n) (1 << (n)) /* Bit n: Mailbox n Interrupt */
#define CAN_INT_ERRA (1 << 16) /* Bit 16: Error Active Mode Interrupt */
#define CAN_INT_WARN (1 << 17) /* Bit 17: Warning Limit Interrupt */
#define CAN_INT_ERRP (1 << 18) /* Bit 18: Error Passive Mode Interrupt */
@@ -179,7 +183,7 @@
#define CAN_BR_BRP_SHIFT (16) /* Bits 16-22: Baudrate Prescaler */
#define CAN_BR_BRP_MASK (127 << CAN_BR_BRP_SHIFT)
# define CAN_BR_BRP(n) ((uint32_t)(n) << CAN_BR_BRP_SHIFT)
#define CAN_BR_SMP (1 << 24) /* Bit 24: Sampling Mode
#define CAN_BR_SMP (1 << 24) /* Bit 24: Sampling Mode */
/* Timer Register */
@@ -277,6 +281,7 @@
#define CAN_MSR_MMI (1 << 24) /* Bit 24: Mailbox Message Ignored */
/* Mailbox Data Low Register (32-bit value) */
/* Mailbox Data High Register (32-bit value) */
/* Mailbox Control Register */
@@ -288,16 +293,16 @@
#define CAN_MCR_MACR (1 << 22) /* Bit 22: Abort Request for Mailbox n */
#define CAN_MCR_MTCR (1 << 23) /* Bit 23: Mailbox Transfer Command */
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CAN_H */
arch/arm/src/sam34/hardware/sam_chipid.h
+22 -16
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_chipid.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,35 +16,35 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CHIPID_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CHIPID_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* CHIPID register offsets **************************************************************/
/* CHIPID register offsets **************************************************/
#define SAM_CHIPID_CIDR 0x00 /* Chip ID Register */
#define SAM_CHIPID_EXID 0x04 /* Chip ID Extension Register */
/* CHIPID register addresses ************************************************************/
/* CHIPID register addresses ************************************************/
#define SAM_CHIPID_CIDR (SAM_CHIPID_BASE+SAM_CHIPID_CIDR)
#define SAM_CHIPID_EXID (SAM_CHIPID_BASE+SAM_CHIPID_EXID)
/* CHIPID register bit definitions ******************************************************/
/* CHIPID register bit definitions ******************************************/
#define CHIPID_CIDR_VERSION_SHIFT (0) /* Bits 0-4: Version of the Device */
#define CHIPID_CIDR_VERSION_MASK (0x1f << CHIPID_CIDR_VERSION_SHIFT)
@@ -57,6 +57,7 @@
# define CHIPID_CIDR_EPROC_ARM926EJS (5 << CHIPID_CIDR_EPROC_SHIFT) /* ARM926EJ-S */
# define CHIPID_CIDR_EPROC_CORTEXA5 (6 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-A5 */
# define CHIPID_CIDR_EPROC_CORTEXM4 (7 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-M4 */
#define CHIPID_CIDR_NVPSIZ_SHIFT (8) /* Bits 8-11: Nonvolatile Program Memory Size */
#define CHIPID_CIDR_NVPSIZ_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT)
# define CHIPID_CIDR_NVPSIZ_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */
@@ -69,6 +70,7 @@
# define CHIPID_CIDR_NVPSIZ_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */
# define CHIPID_CIDR_NVPSIZ_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */
# define CHIPID_CIDR_NVPSIZ_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */
#define CHIPID_CIDR_NVPSIZ2_SHIFT (12) /* Bits 12-15: Nonvolatile Program Memory Size */
#define CHIPID_CIDR_NVPSIZ2_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT)
# define CHIPID_CIDR_NVPSIZ2_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */
@@ -81,6 +83,7 @@
# define CHIPID_CIDR_NVPSIZ2_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */
# define CHIPID_CIDR_NVPSIZ2_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */
# define CHIPID_CIDR_NVPSIZ2_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */
#define CHIPID_CIDR_SRAMSIZ_SHIFT (16) /* Bits 16-19: Internal SRAM Size */
#define CHIPID_CIDR_SRAMSIZ_MASK (15 << CHIPID_CIDR_SRAMSIZ_SHIFT)
# define CHIPID_CIDR_SRAMSIZ_48KB (0 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 48K bytes */
@@ -101,6 +104,7 @@
# define CHIPID_CIDR_SRAMSIZ_256KB (13 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 256K bytes */
# define CHIPID_CIDR_SRAMSIZ_96KB (14 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 96K bytes */
# define CHIPID_CIDR_SRAMSIZ_512KB (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 512K bytes */
#define CHIPID_CIDR_ARCH_SHIFT (20) /* Bits 20-27: Architecture Identifier */
#define CHIPID_CIDR_ARCH_MASK (0xff << CHIPID_CIDR_ARCH_SHIFT)
# define CHIPID_CIDR_ARCH_AT91SAM9XX (0x19 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM9xx Series */
@@ -144,6 +148,7 @@
# define CHIPID_CIDR_ARCH_SAM4LB (0xb1 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxB Series */
# define CHIPID_CIDR_ARCH_SAM4LC (0xb2 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxC Series */
# define CHIPID_CIDR_ARCH_AT75CXX (0xf0 << CHIPID_CIDR_ARCH_SHIFT) /* AT75Cxx Series */
#define CHIPID_CIDR_NVPTYP_SHIFT (28) /* Bits 28-30: Nonvolatile Program Memory Type */
#define CHIPID_CIDR_NVPTYP_MASK (7 << CHIPID_CIDR_NVPTYP_SHIFT)
# define CHIPID_CIDR_NVPTYP_ROM (0 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM */
@@ -151,6 +156,7 @@
# define CHIPID_CIDR_NVPTYP_SRAM (4 << CHIPID_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */
# define CHIPID_CIDR_NVPTYP_EFLASH (2 << CHIPID_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */
# define CHIPID_CIDR_NVPTYP_REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */
#define CHIPID_CIDR_EXT (1 << 31) /* Bit 31: Extension Flag */
/* Chip ID Extension Register (32-bit value for SAM3U and SAM4S) */
@@ -170,16 +176,16 @@
# define CHIPID_EXID_PACKAGE_144PIN (5 << CHIPID_EXID_PACKAGE_SHIFT) /* 144-pin package */
#endif
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CHIPID_H */
arch/arm/src/sam34/hardware/sam_cmcc.h
+22 -18
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_cmcc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,27 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CMCC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CMCC_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* This information is available in the Cache Type Register. How every, it is more
* efficient if we do not to do the decoding on each cache access.
****************************************************************************/
/* This information is available in the Cache Type Register.
* How ever, it is more efficient if we do not to do the decoding on each
* cache access.
*
* CacheSize = CacheLineSize * NCacheLines * NWays
* CacheAddressRange = CacheLineSize * NCacheLines = CacheSize / NWays
@@ -46,7 +48,7 @@
# define CMCC_NWAYS 4
#endif
/* CMCC register offsets ****************************************************************/
/* CMCC register offsets ****************************************************/
#define SAM_CMCC_TYPE_OFFSET 0x0000 /* Cache Type Register */
#define SAM_CMCC_CFG_OFFSET 0x0004 /* Cache Configuration Register */
@@ -61,7 +63,7 @@
#define SAM_CMCC_MSR_OFFSET 0x0034 /* Cache Monitor Status Register */
/* 0x0038-0x00fc Reserved */
/* CMCC register addresses **************************************************************/
/* CMCC register addresses **************************************************/
#define SAM_CMCC_TYPE (SAM_CMCC_BASE+SAM_CMCC_TYPE_OFFSET)
#define SAM_CMCC_CFG (SAM_CMCC_BASE+SAM_CMCC_CFG_OFFSET)
@@ -74,7 +76,7 @@
#define SAM_CMCC_MCTRL (SAM_CMCC_BASE+SAM_CMCC_MCTRL_OFFSET)
#define SAM_CMCC_MSR (SAM_CMCC_BASE+SAM_CMCC_MSR_OFFSET)
/* CMCC register bit definitions ********************************************************/
/* CMCC register bit definitions ********************************************/
/* Cache Type Register */
@@ -89,6 +91,7 @@
# define CMCC_TYPE_WAYNUM_ARCH2WAY (1 << CMCC_TYPE_WAYNUM_SHIFT) /* 2-WAY set associative */
# define CMCC_TYPE_WAYNUM_ARCH4WAY (2 << CMCC_TYPE_WAYNUM_SHIFT) /* 4-WAY set associative */
# define CMCC_TYPE_WAYNUM_ARCH8WAY (3 << CMCC_TYPE_WAYNUM_SHIFT) /* 8-WAY set associative */
#define CMCC_TYPE_LCKDOWN (1 << 7) /* Bit 7: Lock Down Supported */
#define CMCC_TYPE_CSIZE_SHIFT (8) /* Bits 8-10: Cache Size */
#define CMCC_TYPE_CSIZE_MASK (7 << CMCC_TYPE_CSIZE_SHIFT)
@@ -96,6 +99,7 @@
# define CMCC_TYPE_CSIZE_2KB (1 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 2 Kbytes */
# define CMCC_TYPE_CSIZE_4KB (2 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 4 Kbytes */
# define CMCC_TYPE_CSIZE_8KB (3 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 8 Kbytes */
#define CMCC_TYPE_CLSIZE_SHIFT (11) /* Bits 11-13: Cache Line Size */
#define CMCC_TYPE_CLSIZE_MASK (7 << CMCC_TYPE_CLSIZE_SHIFT)
# define CMCC_TYPE_CLSIZE_4B (0 << CMCC_TYPE_CLSIZE_SHIFT) /* 4 Bytes */
@@ -150,16 +154,16 @@
/* Cache Monitor Status Register -- 32-bit event count */
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CMCC_H */
arch/arm/src/sam34/hardware/sam_dacc.h
+24 -17
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_dacc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DACC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DACC_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* DACC register offsets *****************************************************************/
/* DACC register offsets ****************************************************/
#define SAM_DACC_CR_OFFSET 0x0000 /* Control Register */
#define SAM_DACC_MR_OFFSET 0x0004 /* Mode Register */
@@ -50,7 +50,7 @@
#define SAM_DACC_WPMR_OFFSET 0x00e4 /* Write Protect Mode register */
#define SAM_DACC_WPSR_OFFSET 0x00e8 /* Write Protect Status register */
/* DACC register addresses **************************************************************/
/* DACC register addresses **************************************************/
#define SAM_DACC_CR (SAM_DACC_BASE+SAM_DACC_CR_OFFSET)
#define SAM_DACC_MR (SAM_DACC_BASE+SAM_DACC_MR_OFFSET)
@@ -66,7 +66,7 @@
#define SAM_DACC_WPMR (SAM_DACC_BASE+SAM_DACC_WPMR_OFFSET)
#define SAM_DACC_WPSR (SAM_DACC_BASE+SAM_DACC_WPSR_OFFSET)
/* DACC register bit definitions ********************************************************/
/* DACC register bit definitions ********************************************/
/* Control Register */
@@ -83,6 +83,7 @@
# define DACC_MR_TRGSEL_TIO2 (3 << DACC_MR_TRGSEL_SHIFT) /* TIO Output of the TC Channel 2 */
# define DACC_MR_TRGSEL_PWM0 (4 << DACC_MR_TRGSEL_SHIFT) /* PWM Event Line 0 */
# define DACC_MR_TRGSEL_PWM1 (5 << DACC_MR_TRGSEL_SHIFT) /* PWM Event Line 1 */
#define DACC_MR_WORD (1 << 4) /* Bit 4: Word Transfer */
#define DACC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */
#define DACC_MR_FASTWKUP (1 << 6) /* Bit 6: Fast Wake up Mode */
@@ -92,13 +93,17 @@
#define DACC_MR_USERSEL_MASK (3 << DACC_MR_USERSEL_SHIFT)
# define DACC_MR_USERSEL_CHAN0 (0 << DACC_MR_USERSEL_SHIFT) /* Channel 0 */
# define DACC_MR_USERSEL_CHAN1 (1 << DACC_MR_USERSEL_SHIFT) /* Channel 1 */
#define DACC_MR_TAG (1 << 20) /* Bit 20: Tag Selection Mode */
#define DACC_MR_MAXS (1 << 21) /* Bit 21: Max Speed Mode */
#define DACC_MR_CLKDIV (1 << 22) /* Bit 22: Clock Divider */
# define DACC_MR_CLKDIV_2 (0) /* DAC clock is MCK divided by 2 */
# define DACC_MR_CLKDIV_4 DACC_MR_CLKDIV /* DAC clock is MCK divided by 4 */
#define DACC_MR_STARTUP_SHIFT (24) /* Bits 24-29: Startup Time Select */
#define DACC_MR_STARTUP_MASK (63 << DACC_MR_STARTUP_SHIFT)
# define DACC_MR_STARTUP_0 (0 << DACC_MR_STARTUP_SHIFT) /* 0 periods of DACClock */
# define DACC_MR_STARTUP_8 (1 << DACC_MR_STARTUP_SHIFT) /* 8 periods of DACClock */
# define DACC_MR_STARTUP_16 (2 << DACC_MR_STARTUP_SHIFT) /* 16 periods of DACClock */
@@ -171,7 +176,9 @@
/* Conversion Data Register -- 32-bit data */
/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status Register */
/* Interrupt Enable, Interrupt Disable, Interrupt Mask,
* and Interrupt Status Register
*/
#define DACC_INT_TXRDY (1 << 0) /* Bit 0: Transmit Ready Interrupt */
#define DACC_INT_EOC (1 << 1) /* Bit 1: End of Conversion Interrupt Flag */
@@ -201,16 +208,16 @@
#define DACC_WPSR_WPROTADDR_SHIFT (8) /* Bits 8-15: Write protection error address */
#define DACC_WPSR_WPROTADDR_MASK (0xff << DACC_WPSR_WPROTADDR_SHIFT)
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DACC_H */
arch/arm/src/sam34/hardware/sam_dmac.h
+46 -26
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_dmac.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DMAC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DMAC_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* DMAC register offsets ****************************************************************/
/* DMAC register offsets ****************************************************/
/* Global Registers */
@@ -52,6 +52,7 @@
#define SAM_DMAC_CHDR_OFFSET 0x002c /* DMAC Channel Handler Disable Register */
#define SAM_DMAC_CHSR_OFFSET 0x0030 /* DMAC Channel Handler Status Register */
/* 0x034-0x38: Reserved */
/* DMA channel registers */
#define SAM_DMACHAN_OFFSET(n) (0x003c+((n)*0x28))
@@ -68,7 +69,7 @@
#define SAM_DMACHAN_CTRLA_OFFSET 0x000c /* DMAC Channel Control A Register */
#define SAM_DMACHAN_CTRLB_OFFSET 0x0010 /* DMAC Channel Control B Register */
#define SAM_DMACHAN_CFG_OFFSET 0x0014 /* DMAC Channel Configuration Register */
/* 0x18-0x24: Reserved */
/* 0x18-0x24: Reserved */
/* More Global Registers */
@@ -77,7 +78,7 @@
# define SAM_DMAC_WPSR_OFFSET 0x01e8 /* DMAC Write Protect Status Register DMAC_WPSR */
#endif
/* DMAC register addresses **************************************************************/
/* DMAC register addresses **************************************************/
/* Global Registers */
@@ -146,7 +147,7 @@
# define SAM_DMAC_WPSR (SAM_DMAC_BASE+SAM_DMAC_WPSR_OFFSET)
#endif
/* DMAC register bit definitions ********************************************************/
/* DMAC register bit definitions ********************************************/
/* Global Registers */
@@ -236,10 +237,14 @@
# define DMAC_LAST_DLAST2 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST2_SHIFT)
# define DMAC_LAST_DLAST3 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST3_SHIFT)
/* DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register,
* DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register,
* DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register, and
* DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register common
/* DMAC Error, Buffer Transfer and Chained Buffer
* Transfer Interrupt Enable Register,
* DMAC Error, Buffer Transfer and Chained Buffer
* Transfer Interrupt Disable Register,
* DMAC Error, Buffer Transfer and Chained Buffer
* Transfer Interrupt Mask Register, and
* DMAC Error, Buffer Transfer and Chained Buffer
* Transfer Status Register common
* bit field definitions
*/
@@ -344,10 +349,22 @@
# define DMAC_CHSR_STAL3 (1 << (DMAC_CHSR_STAL_SHIFT+3))
/* DMA channel registers */
/* DMAC Channel n [n = 0..3] Source Address Register -- 32-bit address*/
/* DMAC Channel n [n = 0..3] Destination Address Register -- 32-bit address*/
/* DMAC Channel n [n = 0..3] Descriptor Address Register -- 32-bit address*/
/* DMAC Channel n [n = 0..3] Control A Register */
/* DMAC Channel n [n = 0..3]
* Source Address Register -- 32-bit address
*/
/* DMAC Channel n [n = 0..3]
* Destination Address Register -- 32-bit address
*/
/* DMAC Channel n [n = 0..3]
* Descriptor Address Register -- 32-bit address
*/
/* DMAC Channel n [n = 0..3]
* Control A Register
*/
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
@@ -395,6 +412,7 @@
# define DMACHAN_CTRLB_FC_M2P (1 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Peripheral */
# define DMACHAN_CTRLB_FC_P2M (2 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Memory */
# define DMACHAN_CTRLB_FC_P2P (3 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Peripheral */
#define DMACHAN_CTRLB_SRCINCR_SHIFT (24) /* Bits 24-25 */
#define DMACHAN_CTRLB_SRCINCR_MASK (3 << DMACHAN_CTRLB_SRCINCR_SHIFT)
# define DMACHAN_CTRLB_SRCINCR_INCR (0 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Incrementing address */
@@ -402,6 +420,7 @@
# define DMACHAN_CTRLB_SRCINCR_DECR (1 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Decrementing address */
# endif
# define DMACHAN_CTRLB_SRCINCR_FIXED (2 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Fixed address */
#define DMACHAN_CTRLB_DSTINCR_SHIFT (28) /* Bits 28-29 */
#define DMACHAN_CTRLB_DSTINCR_MASK (3 << DMACHAN_CTRLB_DSTINCR_SHIFT)
# define DMACHAN_CTRLB_DSTINCR_INCR (0 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Incrementing address */
@@ -409,6 +428,7 @@
# define DMACHAN_CTRLB_DSTINCR_DECR (1 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Decrementing address */
# endif
# define DMACHAN_CTRLB_DSTINCR_FIXED (2 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Fixed address */
#define DMACHAN_CTRLB_IEN (1 << 30) /* Bit 30: Clear sets BTC[n] flag in EBCISR */
/* DMAC Channel n [n = 0..3] Configuration Register */
@@ -453,7 +473,7 @@
# define DMAC_WPSR_WPVSRC_MASK (0xffff << DMAC_WPSR_WPVSRC_SHIFT)
#endif
/* DMA Hardware interface numbers *******************************************************/
/* DMA Hardware interface numbers *******************************************/
#if defined(CONFIG_ARCH_CHIP_SAM3U)
@@ -496,9 +516,9 @@
#endif
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/* DMA multi buffer transfer link list entry structure */
@@ -511,12 +531,12 @@ struct dma_linklist_s
uint32_t next; /* Next descriptor address */
};
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DMAC_H */
arch/arm/src/sam34/hardware/sam_eefc.h
+17 -16
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_eefc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,32 +16,32 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EEFC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EEFC_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* EEFC register offsets ****************************************************************/
/* EEFC register offsets ****************************************************/
#define SAM_EEFC_FMR_OFFSET 0x00 /* EEFC Flash Mode Register */
#define SAM_EEFC_FCR_OFFSET 0x04 /* EEFC Flash Command Register */
#define SAM_EEFC_FSR_OFFSET 0x08 /* EEFC Flash Status Register */
#define SAM_EEFC_FRR_OFFSET 0x0c /* EEFC Flash Result Register */
/* EEFC register addresses **************************************************************/
/* EEFC register addresses **************************************************/
#define SAM_EEFC_FMR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FMR_OFFSET)
#define SAM_EEFC_FCR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FCR_OFFSET)
@@ -60,7 +60,8 @@
# define SAM_EEFC1_FRR (SAM_EEFC1_BASE+SAM_EEFC_FRR_OFFSET)
#endif
/* EEFC register bit definitions ********************************************************/
/* EEFC register bit definitions ********************************************/
/* EEFC Flash Mode Register */
#define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */
@@ -135,16 +136,16 @@
/* EEFC Flash Result Register -- 32-bit value */
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EEFC_H */
arch/arm/src/sam34/hardware/sam_emac.h
+45 -20
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_emac.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,22 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EMAC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EMAC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/sam_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* EMAC Register Offsets ************************************************************/
****************************************************************************/
/* EMAC Register Offsets ****************************************************/
#define SAM_EMAC_NCR_OFFSET 0x0000 /* Network Control Register */
#define SAM_EMAC_NCFGR_OFFSET 0x0004 /* Network Configuration Register */
@@ -71,6 +72,7 @@
#define SAM_EMAC_SAMB1_OFFSET 0x00c8 /* Specific Address 1 Mask Bottom [31:0] Register */
#define SAM_EMAC_SAMT1_OFFSET 0x00cc /* Specific Address 1 Mask Top [47:32] Register */
/* 0x00fc: Reserved */
/* Statistics registers */
#define SAM_EMAC_OTLO_OFFSET 0x0100 /* Octets Transmitted [31:0] Register */
@@ -137,7 +139,7 @@
#define SAM_EMAC_PEFRN_OFFSET 0x01fc /* PTP Peer Event Frame Received Nanoseconds */
/* 0x0280-0x0298: Reserved */
/* EMAC Register Addresses **********************************************************/
/* EMAC Register Addresses **************************************************/
#define SAM_EMAC_NCR (SAM_EMAC_BASE+SAM_EMAC_NCR_OFFSET)
#define SAM_EMAC_NCFGR (SAM_EMAC_BASE+SAM_EMAC_NCFGR_OFFSET)
@@ -240,7 +242,7 @@
#define SAM_EMAC_PEFRS (SAM_EMAC_BASE+SAM_EMAC_PEFRS_OFFSET)
#define SAM_EMAC_PEFRN (SAM_EMAC_BASE+SAM_EMAC_PEFRN_OFFSET)
/* EMAC Register Bit Definitions ****************************************************/
/* EMAC Register Bit Definitions ********************************************/
/* Network Control Register */
@@ -282,6 +284,7 @@
# define EMAC_NCFGR_RXBUFO_1 (1 << EMAC_NCFGR_RXBUFO_SHIFT) /* One-byte offset from RX buffer start */
# define EMAC_NCFGR_RXBUFO_2 (2 << EMAC_NCFGR_RXBUFO_SHIFT) /* Two-byte offset from RX buffer start */
# define EMAC_NCFGR_RXBUFO_3 (3 << EMAC_NCFGR_RXBUFO_SHIFT) /* Three-byte offset fromRX buffer start */
#define EMAC_NCFGR_LFERD (1 << 16) /* Bit 16: Length Field Error Frame Discard */
#define EMAC_NCFGR_RFCS (1 << 17) /* Bit 17: Remove FCS */
#define EMAC_NCFGR_CLK_SHIFT (18) /* Bits 18-20: MDC clock divider */
@@ -292,9 +295,11 @@
# define EMAC_NCFGR_CLK_DIV48 (3 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 48 (MCK up to 120 MHz) */
# define EMAC_NCFGR_CLK_DIV64 (4 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 64 (MCK up to 160 MHz) */
# define EMAC_NCFGR_CLK_DIV96 (5 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 96 (MCK up to 240 MHz) */
#define EMAC_NCFGR_DBW_SHIFT (21) /* Bit 21-22: Data Bus Width */
#define EMAC_NCFGR_DBW_MASK (3 << EMAC_NCFGR_DBW_SHIFT)
# define EMAC_NCFGR_DBW_ZERO (0 << EMAC_NCFGR_DBW_SHIFT) /* Must be zero */
#define EMAC_NCFGR_DCPF (1 << 23) /* Bit 23: Disable Copy of Pause Frames */
#define EMAC_NCFGR_RXCOEN (1 << 24) /* Bit 24: Receive Checksum Offload Enable */
#define EMAC_NCFGR_EFRHD (1 << 25) /* Bit 25: Enable Frames Received in Half Duplex */
@@ -316,10 +321,11 @@
#define EMAC_DCFGR_FBLDO_SHIFT (0) /* Bits 0-4: Fixed Burst Length for DMA Data Operations */
#define EMAC_DCFGR_FBLDO_MASK (31 << EMAC_DCFGR_FBLDO_SHIFT)
# define EMAC_DCFGR_FBLDO_SINGLE (1 << EMAC_DCFGR_FBLDO_SHIFT) /* Always use SINGLE AHB bursts */
# define EMAC_DCFGR_FBLDO_INCR4 (4 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR4 AHB bursts */
# define EMAC_DCFGR_FBLDO_INCR8 (8 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR8 AHB bursts */
# define EMAC_DCFGR_FBLDO_SINGLE (1 << EMAC_DCFGR_FBLDO_SHIFT) /* Always use SINGLE AHB bursts */
# define EMAC_DCFGR_FBLDO_INCR4 (4 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR4 AHB bursts */
# define EMAC_DCFGR_FBLDO_INCR8 (8 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR8 AHB bursts */
# define EMAC_DCFGR_FBLDO_INCR16 (16 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR16 AHB bursts */
#define EMAC_DCFGR_ESMA (1 << 6) /* Bit 6: Endian Swap Mode Enable for Management Descriptor Accesses */
#define EMAC_DCFGR_ESPA (1 << 7) /* Bit 7: Endian Swap Mode Enable for Packet Data Accesses */
#define EMAC_DCFGR_TXCOEN (1 << 11) /* Bit 11: Transmitter Checksum Generation Offload Enable */
@@ -352,7 +358,9 @@
#define EMAC_RSR_RXOVR (1 << 2) /* Bit 2: Receive Overrun */
#define EMAC_RSR_HNO (1 << 3) /* Bit 3: HRESP Not OK */
/* Interrupt Status Register (ISR), Interrupt Enable Register (IER), Interrupt Disable Register (IDR) and Interrupt Mask Register (IMR) */
/* Interrupt Status Register (ISR), Interrupt Enable Register (IER),
* Interrupt Disable Register (IDR) and Interrupt Mask Register (IMR)
*/
#define EMAC_INT_MFS (1 << 0) /* Bit 0: Management Frame Sent */
#define EMAC_INT_RCOMP (1 << 1) /* Bit 1: Receive Complete */
@@ -412,24 +420,29 @@
#define EMAC_TPQ_MASK (0x0000ffff) /* Bits 0-15: Transmit Pause Quantum */
/* Hash Register Bottom [31:0] Register (LS 32-bit hash address) */
/* Hash Register Top [63:32] Register (MS 32-bit hash address) */
/* Specific Address 1 Bottom [31:0] Register (LS 32-bit address) */
/* Specific Address 1 Top [47:32] Register */
#define EMAC_SAT1_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
/* Specific Address 2 Bottom [31:0] Register (LS 32-bit address) */
/* Specific Address 2 Top [47:32] Register */
#define EMAC_SAT2_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
/* Specific Address 3 Bottom [31:0] Register (LS 32-bit address) */
/* Specific Address 3 Top [47:32] Register */
#define EMAC_SAT3_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
/* Specific Address 4 Bottom [31:0] Register (LS 32-bit address) */
/* Specific Address 4 Top [47:32] Register */
#define EMAC_SAT4_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
@@ -461,6 +474,7 @@
#define EMAC_TPFCP_PQ_MASK (0xff << EMAC_TPFCP_PQ_SHIFT)
/* Specific Address 1 Mask Bottom [31:0] Register (LS 32-bit address) */
/* Specific Address 1 Mask Top [47:32] Register (MS 16-bit address) */
#define EMAC_SAMT1_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of Specific Address 1 Mask */
@@ -517,11 +531,13 @@
/* PTP/1588 Timer Registers */
/* 1588 Timer Sync Strobe Seconds Register (32-bit timer value) */
/* 1588 Timer Sync Strobe Nanoseconds Register (30-bit timer value) */
#define EMAC_TSSN_MASK (0x3fffffff) /* Bit 0-29: Value Timer Nanoseconds Register Capture */
/* 1588 Timer Seconds Register (32-bit timer value) */
/* 1588 Timer Nanoseconds Register (30-bit timer value) */
#define EMAC_TN_MASK (0x3fffffff) /* Bit 0-29: Timer Count in Nanoseconds */
@@ -546,31 +562,35 @@
# define EMAC_TI_NIT(n) ((uint32_t)(n) << EMAC_TI_NIT_SHIFT)
/* PTP Event Frame Transmitted Seconds (32-bit timer value) */
/* PTP Event Frame Transmitted Nanoseconds (30-bit timer value) */
#define EMAC_EFTN_MASK (0x3fffffff) /* Bit 0-29: Register Update */
/* PTP Event Frame Received Seconds (32-bit timer value) */
/* PTP Event Frame Received Nanoseconds (30-bit timer value) */
#define EMAC_EFRN_MASK (0x3fffffff) /* Bit 0-29: Register Update */
/* PTP Peer Event Frame Transmitted Seconds (32-bit timer value) */
/* PTP Peer Event Frame Transmitted Nanoseconds (30-bit timer value) */
#define EMAC_PEFTN_MASK (0x3fffffff) /* Bit 0-29: Register Update */
/* PTP Peer Event Frame Received Seconds (32-bit timer value) */
/* PTP Peer Event Frame Received Nanoseconds (30-bit timer value) */
#define EMAC_PEFRN_MASK (0x3fffffff) /* Bit 0-29: Register Update */
/* Descriptors **********************************************************************/
/* Descriptors **************************************************************/
/* Receive buffer descriptor: Address word */
#define EMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=EMAC owns */
#define EMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */
#define EMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=EMAC owns */
#define EMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */
#define EMACRXD_ADDR_MASK (0xfffffffc) /* Bits 2-31: Aligned buffer address */
/* Receive buffer descriptor: Control word */
@@ -587,20 +607,22 @@
#define EMACRXD_STA_VLPRIO_MASK (7 << EMACRXD_STA_VLANPRIO_SHIFT)
#define EMACRXD_STA_PRIODET (1 << 20) /* Bit 20: Priority tag detected */
#define EMACRXD_STA_VLANTAG (1 << 21) /* Bit 21: VLAN tag detected */
#define EMACRXD_STA_TYPEID_SHIFT (22) /* Bit 22-23: Specific address register */
#define EMACRXD_STA_TYPEID_SHIFT (22) /* Bit 22-23: Specific address register */
#define EMACRXD_STA_TYPEID_MASK (3 << EMACRXD_STA_TYPEID_SHIFT)
# define EMACRXD_STA_TYPEID1 (0 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 1 match */
# define EMACRXD_STA_TYPEID2 (1 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 2 match */
# define EMACRXD_STA_TYPEID3 (2 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 3 match */
# define EMACRXD_STA_TYPEID4 (3 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 4 match */
#define EMACRXD_STA_TYPEIDMATCH (1 << 24) /* Bit 24: Type ID register match found */
#define EMACRXD_STA_SNAP (1 << 24) /* Bit 24: Frame was SNAP encoded */
#define EMACRXD_STA_ADDR_SHIFT (25) /* Bit 25-26: Specific address register */
#define EMACRXD_STA_ADDR_SHIFT (25) /* Bit 25-26: Specific address register */
#define EMACRXD_STA_ADDR_MASK (3 << EMACRXD_STA_ADDR_SHIFT)
# define EMACRXD_STA_ADDR1 (0 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 1 match */
# define EMACRXD_STA_ADDR2 (1 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 2 match */
# define EMACRXD_STA_ADDR3 (2 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 3 match */
# define EMACRXD_STA_ADDR4 (3 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 4 match */
#define EMACRXD_STA_ADDRMATCH (1 << 27) /* Bit 27: Specific address match found */
/* Bit 28: Reserved */
#define EMACRXD_STA_UCAST (1 << 29) /* Bit 29: Unicast hash match */
@@ -608,6 +630,7 @@
#define EMACRXD_STA_BCAST (1 << 31) /* Bit 31: Global all ones broadcast address detected */
/* Transmit buffer descriptor: Address word (un-aligned, 32-bit address */
/* Transmit buffer descriptor: Control word */
#define EMACTXD_STA_BUFLEN_SHIFT (0) /* Bits 0-13: Length of buffer */
@@ -626,6 +649,7 @@
# define EMACTXD_STA_CHKERR_BADFRAG (5 << EMACTXD_STA_CHKERR_SHIFT) /* Unsupported fragmentation */
# define EMACTXD_STA_CHKERR_PKTTYPE (6 << EMACTXD_STA_CHKERR_SHIFT) /* Not TCP or UDP */
# define EMACTXD_STA_CHKERR_EPKT (7 << EMACTXD_STA_CHKERR_SHIFT) /* Premature end of packet */
/* Bits 23-25: Reserved */
#define EMACTXD_STA_LCOL (1 << 26) /* Bit 26: Late collision, transmit error detected */
#define EMACTXD_STA_TFC (1 << 27) /* Bit 27: Transmit frame corruption due to AHB error */
@@ -634,9 +658,10 @@
#define EMACTXD_STA_WRAP (1 << 30) /* Bit 30: Last descriptor in descriptor list */
#define EMACTXD_STA_USED (1 << 31) /* Bit 31: Zero for the EMAC to read from buffer */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/* Receive buffer descriptor */
struct emac_rxdesc_s
arch/arm/src/sam34/hardware/sam_gpbr.h
+16 -16
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_gpbr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_GPBR_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_GPBR_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* GPBR register offsets ****************************************************************/
/* GPBR register offsets ****************************************************/
#define SAM_GPBR_OFFSET(n) ((n)<<2) /* General purpose back-up registers */
#define SAM_GPBR0_OFFSET 0x00
@@ -61,7 +61,7 @@
# define SAM_GPBR19_OFFSET 0x4c
#endif
/* GPBR register addresses **************************************************************/
/* GPBR register addresses **************************************************/
#define SAM_GPBR(n)) (SAM_GPBR_BASE+SAM_GPBR_OFFSET(n))
#define SAM_GPBR0 (SAM_GPBR_BASE+SAM_GPBR0_OFFSET)
@@ -88,20 +88,20 @@
# define SAM_GPBR19 (SAM_GPBR_BASE+SAM_GPBR19_OFFSET)
#endif
/* GPBR register bit definitions ********************************************************/
/* GPBR register bit definitions ********************************************/
/* All 32-bit values */
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_GPBR_H */
arch/arm/src/sam34/hardware/sam_hsmci.h
+26 -18
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_hsmci.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_HSMCI_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_HSMCI_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@@ -31,11 +31,11 @@
#include "hardware/sam_pdc.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* HSMCI register offsets ***************************************************************/
/* HSMCI register offsets ***************************************************/
#define SAM_HSMCI_CR_OFFSET 0x0000 /* Control Register */
#define SAM_HSMCI_MR_OFFSET 0x0004 /* Mode Register */
@@ -69,7 +69,7 @@
/* 0x0100-0x0124: Reserved for PCD registers */
#define SAM_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x3ffc FIFO Memory Aperture */
/* HSMCI register addresses *************************************************************/
/* HSMCI register addresses *************************************************/
#define SAM_HSMCI_CR (SAM_HSMCI_BASE+SAM_HSMCI_CR_OFFSET)
#define SAM_HSMCI_MR (SAM_HSMCI_BASE+SAM_HSMCI_MR_OFFSET)
@@ -112,7 +112,7 @@
# define SAM_HSMCI_PDC_PTSR (SAM_HSMCI_BASE+SAM_PDC_PTSR_OFFSET)
#endif
/* HSMCI register bit definitions *******************************************************/
/* HSMCI register bit definitions *******************************************/
/* HSMCI Control Register */
@@ -191,6 +191,7 @@
# define HSMCI_CMDR_RSPTYP_48BIT (1 << HSMCI_CMDR_RSPTYP_SHIFT) /* 48-bit response */
# define HSMCI_CMDR_RSPTYP_136BIT (2 << HSMCI_CMDR_RSPTYP_SHIFT) /* 136-bit response */
# define HSMCI_CMDR_RSPTYP_R1B (3 << HSMCI_CMDR_RSPTYP_SHIFT) /* R1b response type */
#define HSMCI_CMDR_SPCMD_SHIFT (8) /* Bits 8-10: Special Command */
#define HSMCI_CMDR_SPCMD_MASK (7 << HSMCI_CMDR_SPCMD_SHIFT)
# define HSMCI_CMDR_SPCMD_NORMAL (0 << HSMCI_CMDR_SPCMD_SHIFT) /* Not a special CMD */
@@ -201,6 +202,7 @@
# define HSMCI_CMDR_SPCMD_INTRESP (5 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt response */
# define HSMCI_CMDR_SPCMD_BOOTOP (6 << HSMCI_CMDR_SPCMD_SHIFT) /* Boot Operation Request */
# define HSMCI_CMDR_SPCMD_BOOTEND (7 << HSMCI_CMDR_SPCMD_SHIFT) /* End Boot Operation */
#define HSMCI_CMDR_OPDCMD (1 << 11) /* Bit 11: Open Drain Command */
#define HSMCI_CMDR_MAXLAT (1 << 12) /* Bit 12: Max Latency for Command to Response */
#define HSMCI_CMDR_TRCMD_SHIFT (16) /* Bits 16-17: Transfer Command */
@@ -208,6 +210,7 @@
# define HSMCI_CMDR_TRCMD_NONE (0 << HSMCI_CMDR_TRCMD_SHIFT) /* No data transfer */
# define HSMCI_CMDR_TRCMD_START (1 << HSMCI_CMDR_TRCMD_SHIFT) /* Start data transfer */
# define HSMCI_CMDR_TRCMD_STOP (2 << HSMCI_CMDR_TRCMD_SHIFT) /* Stop data transfer */
#define HSMCI_CMDR_TRDIR (1 << 18) /* Bit 18: Transfer Direction */
# define HSMCI_CMDR_TRDIR_WRITE (0 << 18)
# define HSMCI_CMDR_TRDIR_READ (1 << 18)
@@ -218,11 +221,13 @@
# define HSMCI_CMDR_TRTYP_STREAM (2 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC Stream */
# define HSMCI_CMDR_TRTYP_SDIOBYTE (4 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Byte */
# define HSMCI_CMDR_TRTYP_SDIOBLK (5 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Block */
#define HSMCI_CMDR_IOSPCMD_SHIFT (24) /* Bits 24-25: SDIO Special Command */
#define HSMCI_CMDR_IOSPCMD_MASK (3 << HSMCI_CMDR_IOSPCMD_SHIFT)
# define HSMCI_CMDR_IOSPCMD_NORMAL (0 << HSMCI_CMDR_IOSPCMD_SHIFT) /* Not an SDIO Special Command */
# define HSMCI_CMDR_IOSPCMD_SUSP (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */
# define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */
#define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */
#define HSMCI_CMDR_BOOTACK (1 << 27) /* Bit 27: Boot Operation Acknowledge */
@@ -252,11 +257,14 @@
# define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT)
/* HSMCI Response Registers (32-bit data) */
/* HSMCI Receive Data Registers (32-bit data) */
/* HSMCI Transmit Data Registers (32-bit data) */
/* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable
* Register, and HSMCI Interrupt Mask Register common bit-field definitions
/* HSMCI Status Register, HSMCI Interrupt Enable Register,
* HSMCI Interrupt Disable Register, and HSMCI Interrupt Mask Register
* common bit-field definitions
*/
#define HSMCI_INT_CMDRDY (1 << 0) /* Bit 0: Command Ready */
@@ -336,16 +344,16 @@
#define HSMCI_WPSR_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
#define HSMCI_WPSR_VSRC_MASK (0xffff << HSMCI_WPSR_VSRC_SHIFT)
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_HSMCI_H */
arch/arm/src/sam34/hardware/sam_matrix.h
+13 -13
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_matrix.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MATRIX_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MATRIX_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* MATRIX register offsets **************************************************************/
/* MATRIX register offsets **************************************************/
#define SAM_MATRIX_MCFG_OFFSET(n) ((n)<<2)
#define SAM_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */
@@ -110,7 +110,7 @@
#define SAM_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */
/* 0x0110 - 0x01fc: Reserved */
/* MATRIX register addresses ************************************************************/
/* MATRIX register addresses ************************************************/
#define SAM_MATRIX_MCFG(n) (SAM_MATRIX_BASE+SAM_MATRIX_MCFG_OFFSET(n))
#define SAM_MATRIX_MCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG0_OFFSET)
@@ -183,7 +183,7 @@
#define SAM_MATRIX_WPMR (SAM_MATRIX_BASE+SAM_MATRIX_WPMR_OFFSET)
#define SAM_MATRIX_WPSR (SAM_MATRIX_BASE+SAM_MATRIX_WPSR_OFFSET)
/* MATRIX register bit definitions ******************************************************/
/* MATRIX register bit definitions ******************************************/
/* Master Configuration Registers */
@@ -342,12 +342,12 @@
#define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define MATRIX_WPSR_WPVSRC_MASK (0xffff << MATRIX_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MATRIX_H */
arch/arm/src/sam34/hardware/sam_memorymap.h
+4 -4
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <arch/sam34/chip.h>
arch/arm/src/sam34/hardware/sam_pdc.h
+23 -17
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_pdc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PDC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PDC_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* PDC register offsets *****************************************************************/
/* PDC register offsets *****************************************************/
#define SAM_PDC_RPR_OFFSET 0x100 /* Receive Pointer Register */
#define SAM_PDC_RCR_OFFSET 0x104 /* Receive Counter Register */
@@ -47,31 +47,37 @@
#define SAM_PDC_PTCR_OFFSET 0x120 /* Transfer Control Register */
#define SAM_PDC_PTSR_OFFSET 0x124 /* Transfer Status Register */
/* PDC register addresses ***************************************************************/
/* PDC register addresses ***************************************************/
/* These 10 registers are mapped in the peripheral memory space at the same offset. */
/* These 10 registers are mapped in the peripheral memory space at the same
* offset.
*/
/* PDC register bit definitions *********************************************************/
/* PDC register bit definitions *********************************************/
/* Receive Pointer Register -- 32-bit address value */
/* Receive Counter Register -- 16-bit counter value */
#define PDC_RCR_RXCTR_SHIFT (0) /* Bits 0-15: Receive Counter Register */
#define PDC_RCR_RXCTR_MASK (0xffff << PDC_RCR_RXCTR_SHIFT)
/* Transmit Pointer Register -- 32-bit address value */
/* Transmit Counter Register -- 16-bit counter value */
#define PDC_TCR_TXCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Register */
#define PDC_TCR_TXCTR_MASK (0xffff << PDC_TCR_TXCTR_SHIFT)
/* Receive Next Pointer Register -- 32-bit address value */
/* Receive Next Counter Register -- 16-bit counter value */
#define PDC_RNCR_RXNCTR_SHIFT (0) /* Bits 0-15: Receive Next Counter */
#define PDC_RNCR_RXNCTR_MASK (0xffff << PDC_RNCR_RXNCTR_SHIFT)
/* Transmit Next Pointer Register -- 32-bit address value */
/* Transmit Next Counter Register -- 16-bit counter value */
#define PDC_TNCR_TXNCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Next */
@@ -89,16 +95,16 @@
#define PDC_PTSR_RXTEN (1 << 0) /* Bit 0: Receiver Transfer Enable */
#define PDC_PTSR_TXTEN (1 << 8) /* Bit 8: Transmitter Transfer Enable */
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PDC_H */
arch/arm/src/sam34/hardware/sam_pinmap.h
+4 -4
View File
@@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PINMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PINMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
arch/arm/src/sam34/hardware/sam_pmc.h
+33 -26
View File
@@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_pmc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PMC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PMC_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* PMC register offsets *********************************************************************/
/* PMC register offsets *****************************************************/
#define SAM_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */
#define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */
@@ -56,7 +56,7 @@
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_PMC_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */
#endif
/* 0x001c: Reserved (SAM4S)*/
/* 0x001c: Reserved (SAM4S) */
#define SAM_PMC_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */
#define SAM_PMC_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */
#define SAM_PMC_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */
@@ -64,7 +64,7 @@
#if defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_PMC_CKGR_PLLBR_OFFSET 0x002c /* PLLB Register */
#endif
/* 0x002c: Reserved (SAM3U)*/
/* 0x002c: Reserved (SAM3U) */
#define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
@@ -111,7 +111,7 @@
# define SAM_PMC_PMMR_OFFSET 0x0130 /* PLL Maximum Multiplier Value Register */
#endif
/* PMC register addresses *******************************************************************/
/* PMC register addresses ***************************************************/
#define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET)
#define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET)
@@ -182,10 +182,10 @@
# define SAM_PMC_PMMR (SAM_PMC_BASE+SAM_PMC_PMMR_OFFSET)
#endif
/* PMC register bit definitions *************************************************************/
/* PMC register bit definitions *********************************************/
/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System
* Clock Status Register common bit-field definitions
/* PMC System Clock Enable Register, PMC System Clock Disable Register,
* and PMC System Clock Status Register common bit-field definitions
*/
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM4S)
@@ -207,8 +207,9 @@
# define PMC_CPKEY (0xa << 20)
#endif
/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC
* Peripheral Clock Status Register common bit-field definitions.
/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable
* Register, and PMC Peripheral Clock Status Register common bit-field
* definitions.
*/
#define PMC_PIDL(n) (1 << (n))
@@ -267,6 +268,7 @@
# define PMC_CKGR_MOR_MOSCRCF_4MHz (0 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 4MHz (default) */
# define PMC_CKGR_MOR_MOSCRCF_8MHz (1 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 8MHz */
# define PMC_CKGR_MOR_MOSCRCF_12MHz (2 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 12MHz */
#define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-15: Main Crystal Oscillator Start-up Time */
#define PMC_CKGR_MOR_MOSCXTST_MASK (0xff << PMC_CKGR_MOR_MOSCXTST_SHIFT)
# define PMC_CKGR_MOR_MOSCXTST(n) ((uint32_t)(n) << PMC_CKGR_MOR_MOSCXTST_SHIFT)
@@ -317,6 +319,7 @@
# define PMC_CKGR_PLLBR_DIV_ZERO (0 << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider output is 0 */
# define PMC_CKGR_PLLBR_DIV_BYPASS (1 << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider is bypassed (DIV=1) */
# define PMC_CKGR_PLLBR_DIV(n) ((n) << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */
# define PMC_CKGR_PLLBR_COUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */
# define PMC_CKGR_PLLBR_COUNT_MASK (63 << PMC_CKGR_PLLBR_COUNT_SHIFT)
# define PMC_CKGR_PLLBR_MUL_SHIFT (16) /* Bits 16-26: PLLA Multiplier */
@@ -421,8 +424,8 @@
# define PMC_PCK_PRES_DIV32 (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */
# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */
/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register,
* and PMC Interrupt Mask Register common bit-field definitions
/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status
* Register, and PMC Interrupt Mask Register common bit-field definitions
*/
#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */
@@ -450,8 +453,8 @@
#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */
#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */
/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field
* definitions
/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register
* common bit-field definitions
*/
#define PMC_FSTI(n) (1 << (n))
@@ -491,6 +494,7 @@
/* Fast Startup Polarity Register */
#define PMC_FSTP(n) (1 << (n)) /* Fast Startup Input Polarity n, n=0..15 */
# define PMC_FSTP0 (1 << 0) /* Bit 0: Fast Startup Input Polarity 0 */
# define PMC_FSTP1 (1 << 1) /* Bit 1: Fast Startup Input Polarity 1 */
# define PMC_FSTP2 (1 << 2) /* Bit 2: Fast Startup Input Polarity 2 */
@@ -526,7 +530,9 @@
#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT)
/* Peripheral Clock Enable Register 1 */
/* Peripheral Clock Disable Register 1 */
/* Peripheral Clock Status Register 1 */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
@@ -567,6 +573,7 @@
# define PMC_PCR_DIV1 (0 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK */
# define PMC_PCR_DIV2 (1 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/2 */
# define PMC_PCR_DIV4 (2 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/4 */
# define PMC_PCR_EN (1 << 28) /* Bit 28: Enable */
#endif
@@ -593,16 +600,16 @@
# define PMC_PMMR_MASK (0x7ff) /* Bits 0-10: PLLA Maximum Allowed Multiplier */
#endif
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PMC_H */
arch/arm/src/sam34/hardware/sam_pwm.h
+55 -32
View File
@@ -1,4 +1,4 @@
/****************************************************************************************
/****************************************************************************
* arch/arm/src/sam34/hardware/sam_pwm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PWM_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PWM_H
/****************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
/****************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************/
****************************************************************************/
/* PWM register offsets *****************************************************************/
/* PWM register offsets *****************************************************/
#define SAM_PWM_CLK_OFFSET 0x000 /* PWM Clock Register */
#define SAM_PWM_ENA_OFFSET 0x004 /* PWM Enable Register */
@@ -91,6 +91,7 @@
#define SAM_PWM_WPSR_OFFSET 0x0e8 /* PWM Write Protect Status Register */
/* 0x100-0x128: Reserved for PDC registers */
/* 0x12c: Reserved */
/* PWM Comparison Registers */
#define SAM_PWMCMP_OFFSET(n) (0x130+((n)<<4))
@@ -138,7 +139,8 @@
#define SAM_PWMCMP7_VUPD_OFFSET 0x1a4 /* PWM Comparison 7 Value Update Register */
#define SAM_PWMCMP7_M_OFFSET 0x1a8 /* PWM Comparison 7 Mode Register */
#define SAM_PWMCMP7_MUPD_OFFSET 0x1ac /* PWM Comparison 7 Mode Update Register */
/* 0x1b0-0x1fc: Reserved */
/* 0x1b0-0x1fc: Reserved */
/* PWM Channel Registers */
#define SAM_PWMCH_OFFSET(n) (0x200+((n)<< 5))
@@ -210,7 +212,7 @@
# define SAM_PWMCH3_CAEUPD_OFFSET 0x0468 /* PWM Channel 3 Additional Edge Update Register */
#endif
/* PWM register addresses ***************************************************************/
/* PWM register addresses ***************************************************/
#define SAM_PWM_CLK (SAM_PWM_BASE+SAM_PWM_CLK_OFFSET)
#define SAM_PWM_ENA (SAM_PWM_BASE+SAM_PWM_ENA_OFFSET)
@@ -388,7 +390,7 @@
# define SAM_PWMCH3_CAEUPD (SAM_PWMCH3_BASE2+SAM_PWMCH0_CAEUPD_OFFSET)
#endif
/* PWM register bit definitions *********************************************************/
/* PWM register bit definitions *********************************************/
/* PWM Clock Register */
@@ -410,6 +412,7 @@
# define PWM_CLK_PREA_MCKDIV256 (8 << PWM_CLK_PREA_SHIFT) /* MCK/256 */
# define PWM_CLK_PREA_MCKDIV512 (9 << PWM_CLK_PREA_SHIFT) /* MCK/512 */
# define PWM_CLK_PREA_MCKDIV1024 (10 << PWM_CLK_PREA_SHIFT) /* MCK/1024 */
#define PWM_CLK_DIVB_SHIFT (16) /* Bits 16-23: CLKB Divide Factor */
#define PWM_CLK_DIVB_MASK (0xff << PWM_CLK_DIVB_SHIFT)
# define PWM_CLK_DIVB_OFF (0 << PWM_CLK_DIVB_SHIFT)
@@ -429,7 +432,9 @@
# define PWM_CLK_PREB_MCKDIV512 (9 << PWM_CLK_PREB_SHIFT) /* MCK/512 */
# define PWM_CLK_PREB_MCKDIV1024 (10 << PWM_CLK_PREB_SHIFT) /* MCK/1024 */
/* PWM Enable Register, PWM Disable Register, and PWM Status Register common bit-field definitions */
/* PWM Enable Register, PWM Disable Register, and
* PWM Status Register common bit-field definitions
*/
#define SAM_ENAB_CHID(n) (1 << ((n))
# define SAM_ENAB_CHID0 (1 << 0) /* Bit 0: Counter Event Channel 0 Interrupt */
@@ -437,8 +442,9 @@
# define SAM_ENAB_CHID2 (1 << 2) /* Bit 2: Counter Event Channel 2 Interrupt */
# define SAM_ENAB_CHID3 (1 << 3) /* Bit 3: Counter Event Channel 3 Interrupt */
/* PWM Interrupt Enable Register 1, PWM Interrupt Disable Register 1, PWM Interrupt
* Mask Register 1, and PWM Interrupt Status Register 1 common bit definitions
/* PWM Interrupt Enable Register 1, PWM Interrupt Disable Register 1,
* PWM Interrupt Mask Register 1, and PWM Interrupt Status Register 1
* common bit definitions
*/
#define SAM_INT_CHID(n) (1 << (n))
@@ -464,6 +470,7 @@
# define PWM_SCM_UPDM_MANMAN (0 << PWM_SCM_UPDM_SHIFT) /* Manual write/manual update */
# define PWM_SCM_UPDM_MANAUTO (1 << PWM_SCM_UPDM_SHIFT) /* Manual write/automatic update */
# define PWM_SCM_UPDM_AUTOAUTO (2 << PWM_SCM_UPDM_SHIFT) /* Auto write/automatic update */
#define PWM_SCM_PTRM (1 << 20) /* Bit 20: PDC Transfer Request Mode */
#define PWM_SCM_PTRCS_SHIFT (21) /* Bits 21-23: PDC Transfer Request Comparison Selection */
#define PWM_SCM_PTRCS_MASK (7 << PWM_SCM_PTRCS_SHIFT)
@@ -488,7 +495,10 @@
#define PWM_SCUPUPD_MASK (15 << PWM_SCUPUPD_SHIFT)
# define PWM_SCUPUPD(n) ((uint32_t)(n) << PWM_SCUPUPD_SHIFT)
/* PWM Interrupt Enable Register 2, PWM Interrupt Disable Register 2, PWM Interrupt Mask Register 2, and PWM Interrupt Status Register 2 common bit-field definitions */
/* PWM Interrupt Enable Register 2, PWM Interrupt Disable Register 2,
* PWM Interrupt Mask Register 2, and PWM Interrupt Status Register 2
* common bit-field definitions
*/
#define SAM_INT_WRDY (1 << 0) /* Bit 0: Write Ready Update Interrupt */
#define SAM_INT_ENDTX (1 << 1) /* Bit 1: PDC End of TX Buffer Interrupt */
@@ -513,10 +523,10 @@
# define SAM_INT_CMPU6 (1 << 22) /* Bit 22: Comparison 6 Update Interrupt */
# define SAM_INT_CMPU7 (1 << 23) /* Bit 23: Comparison 7 Update Interrupt */
/* PWM Output Override Value Register, PWM Output Selection Register, PWM Output
* Selection Set Register, PWM Output Selection Clear Register, PWM Output Selection
* Set Update Register, and PWM Output Selection Clear Update Register common bit-field
* definitions
/* PWM Output Override Value Register, PWM Output Selection Register,
* PWM Output Selection Set Register, PWM Output Selection Clear Register,
* PWM Output Selection Set Update Register, and PWM Output Selection Clear
* Update Register common bit-field definitions
*/
#define PWM_OUT_OH(n) (1 << (n))
@@ -720,13 +730,17 @@
#define PWM_WPSR_WPVSRC_SHIFT (16) /* Bits 16-31: Write Protect Violation Source */
#define PWM_WPSR_WPVSRC_MASK (0xffff << PWM_WPSR_WPVSRC_SHIFT)
/* PWM Comparison x Value Register and PWM Comparison x Value Update Register */
/* PWM Comparison x Value Register and
* PWM Comparison x Value Update Register
*/
#define PWMCMP_CV_SHIFT (0) /* Bits 0-23: Comparison x Value */
#define PWMCMP_CV_MASK (0x00ffffff << PWMCMP_CV_SHIFT)
#define PWMCMP_CVM (1 << 24) /* Bit 24: Comparison x Value Mode */
/* PWM Comparison x Mode Register and PWM Comparison x Mode Update Register */
/* PWM Comparison x Mode Register and
* PWM Comparison x Mode Update Register
*/
#define PWMCMP_CEN (1 << 0) /* Bit 0: Comparison x Enable */
#define PWMCMP_CTR_SHIFT (4) /* Bits 4-7: Comparison x Trigger */
@@ -760,8 +774,9 @@
# define PWMCH_MR_CPRE_MCKDIV256 (8 << PWMCH_MR_CPRE_SHIFT) /* MCK/256 */
# define PWMCH_MR_CPRE_MCKDIV512 (9 << PWMCH_MR_CPRE_SHIFT) /* MCK/512 */
# define PWMCH_MR_CPRE_MCKDIV1024 (10 << PWMCH_MR_CPRE_SHIFT) /* MCK/1024 */
# define PWMCH_MR_CPRE_CLKA (11 << PWMCH_MR_CPRE_SHIFT) /*CLKA */
# define PWMCH_MR_CPRE_CLKA (11 << PWMCH_MR_CPRE_SHIFT) /* CLKA */
# define PWMCH_MR_CPRE_CLKB (12 << PWMCH_MR_CPRE_SHIFT) /* CLKB */
#define PWMCH_MR_CALG (1 << 8) /* Bit 8: Channel Alignment */
#define PWMCH_MR_CPOL (1 << 9) /* Bit 9: Channel Polarity */
#define PWMCH_MR_CES (1 << 10) /* Bit 10: Counter Event Selection */
@@ -774,12 +789,16 @@
#define PWMCH_MR_DTHI (1 << 17) /* Bit 17: Dead-Time PWMHx Output Inverted */
#define PWMCH_MR_DTLI (1 << 18) /* Bit 18: Dead-Time PWMLx Output Inverted */
/* PWM Channel Duty Cycle Register and PWM Channel Duty Cycle Update Register common bit-field definitions */
/* PWM Channel Duty Cycle Register and
* PWM Channel Duty Cycle Update Register common bit-field definitions
*/
#define PWMCH_DTY_SHIFT (0) /* Bits 0-23: Channel Duty-Cycle */
#define PWMCH_DTY_MASK (0x00ffffff << PWMCH_DTY_SHIFT)
/* PWM Channel Period Register and PWM Channel Period Update Register common bit-field definitions */
/* PWM Channel Period Register and
* PWM Channel Period Update Register common bit-field definitions
*/
#define PWMCH_PRD_SHIFT (0) /* Bits 0-23: Channel Period */
#define PWMCH_PRD_MASK (0x00ffffff << PWMCH_PRD_SHIFT)
@@ -789,7 +808,9 @@
#define PWMCH_CCNT_SHIFT (0) /* Bits 0-23: Channel Counter Register */
#define PWMCH_CCNT_MASK (0x00ffffff << PWMCH_CCNT_SHIFT)
/* PWM Channel Dead Time Register and PWM Channel Dead Time Update Register common bit-field definitions */
/* PWM Channel Dead Time Register and
* PWM Channel Dead Time Update Register common bit-field definitions
*/
#define PWMCH_DTH_SHIFT (0) /* Bits 0-15: Dead-Time Value for PWMHx Output */
#define PWMCH_DTH_MASK (0xffff << PWMCH_DTH_SHIFT)
@@ -805,7 +826,9 @@
# define PWMCH_CMUPD_CPOLINVUP (1 << 13) /* Bit 13: Channel Polarity Inversion Update */
#endif
/* PWM Channel Additional Edge Register and PWM Channel Additional Edge Update Register */
/* PWM Channel Additional Edge Register and
* PWM Channel Additional Edge Update Register
*/
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define PWMCH_CAE_ADEDGV_SHIFT (0) /* Bits 0-23: Channel Additional Edge Value */
@@ -818,16 +841,16 @@
# define PWMCH_CAE_ADEDGM_BOTH (2 << PWMCH_CAE_ADEDGM_SHIFT)
#endif
/****************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************/
****************************************************************************/
/****************************************************************************************
* Public Functions
****************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PWM_H */

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